1115 files changed, 44903 insertions, 39177 deletions
diff --git a/arch/alpha/kernel/osf_sys.c b/arch/alpha/kernel/osf_sys.c
index f9c732e18284..e51f578636a5 100644
--- a/arch/alpha/kernel/osf_sys.c
+++ b/arch/alpha/kernel/osf_sys.c
@@ -104,11 +104,12 @@ struct osf_dirent_callback {
 };
 static int
-osf_filldir(void *__buf, const char *name, int namlen, loff_t offset,
+osf_filldir(struct dir_context *ctx, const char *name, int namlen,
-            u64 ino, unsigned int d_type)
+            loff_t offset, u64 ino, unsigned int d_type)
 {
        struct osf_dirent __user *dirent;
-        struct osf_dirent_callback *buf = (struct osf_dirent_callback *) __buf;
+        struct osf_dirent_callback *buf =
+                container_of(ctx, struct osf_dirent_callback, ctx);
        unsigned int reclen = ALIGN(NAME_OFFSET + namlen + 1, sizeof(u32));
        unsigned int d_ino;
diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h
index 334ce7017a18..cabd518cb253 100644
--- a/arch/arc/include/asm/io.h
+++ b/arch/arc/include/asm/io.h
@@ -13,8 +13,6 @@
 #include <asm/byteorder.h>
 #include <asm/page.h>
-#define PCI_IOBASE ((void __iomem *)0)
 extern void __iomem *ioremap(unsigned long physaddr, unsigned long size);
 extern void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
                                  unsigned long flags);
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 89c4b5ccc68d..c8424a85bc04 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -320,24 +320,6 @@ config ARCH_MULTIPLATFORM
        select SPARSE_IRQ
        select USE_OF
-config ARCH_INTEGRATOR
-        bool "ARM Ltd. Integrator family"
-        select ARM_AMBA
-        select ARM_PATCH_PHYS_VIRT if MMU
-        select AUTO_ZRELADDR
-        select COMMON_CLK
-        select COMMON_CLK_VERSATILE
-        select GENERIC_CLOCKEVENTS
-        select HAVE_TCM
-        select ICST
-        select MULTI_IRQ_HANDLER
-        select PLAT_VERSATILE
-        select SPARSE_IRQ
-        select USE_OF
-        select VERSATILE_FPGA_IRQ
-        help
-          Support for ARM's Integrator platform.
 config ARCH_REALVIEW
        bool "ARM Ltd. RealView family"
        select ARCH_WANT_OPTIONAL_GPIOLIB
@@ -350,6 +332,7 @@ config ARCH_REALVIEW
        select ICST
        select NEED_MACH_MEMORY_H
        select PLAT_VERSATILE
+        select PLAT_VERSATILE_SCHED_CLOCK
        help
          This enables support for ARM Ltd RealView boards.
@@ -365,6 +348,7 @@ config ARCH_VERSATILE
        select ICST
        select PLAT_VERSATILE
        select PLAT_VERSATILE_CLOCK
+        select PLAT_VERSATILE_SCHED_CLOCK
        select VERSATILE_FPGA_IRQ
        help
          This enables support for ARM Ltd Versatile board.
@@ -376,10 +360,11 @@ config ARCH_AT91
        select IRQ_DOMAIN
        select NEED_MACH_IO_H if PCCARD
        select PINCTRL
-        select PINCTRL_AT91 if USE_OF
+        select PINCTRL_AT91
+        select USE_OF
        help
          This enables support for systems based on Atmel
-          AT91RM9200 and AT91SAM9* processors.
+          AT91RM9200, AT91SAM9 and SAMA5 processors.
 config ARCH_CLPS711X
        bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
@@ -854,6 +839,8 @@ config ARCH_VIRT
 #
 source "arch/arm/mach-mvebu/Kconfig"
+source "arch/arm/mach-asm9260/Kconfig"
 source "arch/arm/mach-at91/Kconfig"
 source "arch/arm/mach-axxia/Kconfig"
@@ -1259,9 +1246,6 @@ source "arch/arm/common/Kconfig"
 menu "Bus support"
-config ARM_AMBA
-        bool
 config ISA
        bool
        help
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index d8f6a2ec3d4e..f9295a4e1036 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -93,6 +93,27 @@ choice
        prompt "Kernel low-level debugging port"
        depends on DEBUG_LL
+        config DEBUG_ASM9260_UART
+                bool "Kernel low-level debugging via asm9260 UART"
+                depends on MACH_ASM9260
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to an UART or USART port on asm9260 based
+                  machines.
+                    DEBUG_UART_PHYS | DEBUG_UART_VIRT
+                    0x80000000      | 0xf0000000     | UART0
+                    0x80004000      | 0xf0004000     | UART1
+                    0x80008000      | 0xf0008000     | UART2
+                    0x8000c000      | 0xf000c000     | UART3
+                    0x80010000      | 0xf0010000     | UART4
+                    0x80014000      | 0xf0014000     | UART5
+                    0x80018000      | 0xf0018000     | UART6
+                    0x8001c000      | 0xf001c000     | UART7
+                    0x80020000      | 0xf0020000     | UART8
+                    0x80024000      | 0xf0024000     | UART9
        config AT91_DEBUG_LL_DBGU0
                bool "Kernel low-level debugging on rm9200, 9260/9g20, 9261/9g10 and 9rl"
                depends on HAVE_AT91_DBGU0
@@ -113,7 +134,7 @@ choice
        config DEBUG_BCM_5301X
                bool "Kernel low-level debugging on BCM5301X UART1"
                depends on ARCH_BCM_5301X
-                select DEBUG_UART_PL01X
+                select DEBUG_UART_8250
        config DEBUG_BCM_KONA_UART
                bool "Kernel low-level debugging messages via BCM KONA UART"
@@ -139,6 +160,17 @@ choice
                  Say Y here if you want kernel low-level debugging support
                  on Marvell Berlin SoC based platforms.
+        config DEBUG_BRCMSTB_UART
+                bool "Use BRCMSTB UART for low-level debug"
+                depends on ARCH_BRCMSTB
+                select DEBUG_UART_8250
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the first serial port on these devices.
+                  If you have a Broadcom STB chip and would like early print
+                  messages to appear over the UART, select this option.
        config DEBUG_CLPS711X_UART1
                bool "Kernel low-level debugging messages via UART1"
                depends on ARCH_CLPS711X
@@ -653,6 +685,64 @@ choice
                  Say Y here if you want kernel low-level debugging support
                  on Rockchip RK32xx based platforms.
+        config DEBUG_R7S72100_SCIF2
+                bool "Kernel low-level debugging messages via SCIF2 on R7S72100"
+                depends on ARCH_R7S72100
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  via SCIF2 on Renesas RZ/A1H (R7S72100).
+        config DEBUG_RCAR_GEN1_SCIF0
+                bool "Kernel low-level debugging messages via SCIF0 on R8A7778"
+                depends on ARCH_R8A7778
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  via SCIF0 on Renesas R-Car M1A (R8A7778).
+        config DEBUG_RCAR_GEN1_SCIF2
+                bool "Kernel low-level debugging messages via SCIF2 on R8A7779"
+                depends on ARCH_R8A7779
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  via SCIF2 on Renesas R-Car H1 (R8A7779).
+        config DEBUG_RCAR_GEN2_SCIF0
+                bool "Kernel low-level debugging messages via SCIF0 on R8A7790/R8A7791/R8A7793)"
+                depends on ARCH_R8A7790 || ARCH_R8A7791 || ARCH_R8A7793
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  via SCIF0 on Renesas R-Car H2 (R8A7790), M2-W (R8A7791), or
+                  M2-N (R8A7793).
+        config DEBUG_RCAR_GEN2_SCIF2
+                bool "Kernel low-level debugging messages via SCIF2 on R8A7794"
+                depends on ARCH_R8A7794
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  via SCIF2 on Renesas R-Car E2 (R8A7794).
+        config DEBUG_RMOBILE_SCIFA0
+                bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4/SH7372"
+                depends on ARCH_R8A73A4 || ARCH_SH7372
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  via SCIFA0 on Renesas R-Mobile APE6 (R8A73A4) or SH-Mobile
+                  AP4 (SH7372).
+        config DEBUG_RMOBILE_SCIFA1
+                bool "Kernel low-level debugging messages via SCIFA1 on R8A7740"
+                depends on ARCH_R8A7740
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  via SCIFA1 on Renesas R-Mobile A1 (R8A7740).
+        config DEBUG_RMOBILE_SCIFA4
+                bool "Kernel low-level debugging messages via SCIFA4 on SH73A0"
+                depends on ARCH_SH73A0
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  via SCIFA4 on Renesas SH-Mobile AG5 (SH73A0).
        config DEBUG_S3C_UART0
                depends on PLAT_SAMSUNG
                select DEBUG_EXYNOS_UART if ARCH_EXYNOS
@@ -723,6 +813,14 @@ choice
                  their output to UART 2. The port must have been initialised
                  by the boot-loader before use.
+        config DEBUG_SA1100
+                depends on ARCH_SA1100
+                bool "Use SA1100 UARTs for low-level debug"
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on SA-11x0 UART ports. The kernel will check for the first
+                  enabled UART in a sequence 3-1-2.
        config DEBUG_SOCFPGA_UART
                depends on ARCH_SOCFPGA
                bool "Use SOCFPGA UART for low-level debug"
@@ -731,6 +829,14 @@ choice
                  Say Y here if you want kernel low-level debugging support
                  on SOCFPGA based platforms.
+        config DEBUG_SUN9I_UART0
+                bool "Kernel low-level debugging messages via sun9i UART0"
+                depends on MACH_SUN9I
+                select DEBUG_UART_8250
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on Allwinner A80 based platforms on the UART0.
        config DEBUG_SUNXI_UART0
                bool "Kernel low-level debugging messages via sunXi UART0"
                depends on ARCH_SUNXI
@@ -866,6 +972,22 @@ choice
                  Say Y here if you want kernel low-level debugging support
                  for Mediatek mt6589 based platforms on UART0.
+        config DEBUG_MT8127_UART0
+                bool "Mediatek mt8127 UART0"
+                depends on ARCH_MEDIATEK
+                select DEBUG_UART_8250
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  for Mediatek mt8127 based platforms on UART0.
+        config DEBUG_MT8135_UART3
+                bool "Mediatek mt8135 UART3"
+                depends on ARCH_MEDIATEK
+                select DEBUG_UART_8250
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  for Mediatek mt8135 based platforms on UART3.
        config DEBUG_VEXPRESS_UART0_DETECT
                bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
                depends on ARCH_VEXPRESS && CPU_CP15_MMU
@@ -1041,7 +1163,9 @@ config DEBUG_STI_UART
 config DEBUG_LL_INCLUDE
        string
+        default "debug/sa1100.S" if DEBUG_SA1100
        default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250
+        default "debug/asm9260.S" if DEBUG_ASM9260_UART
        default "debug/clps711x.S" if DEBUG_CLPS711X_UART1 || DEBUG_CLPS711X_UART2
        default "debug/meson.S" if DEBUG_MESON_UARTAO
        default "debug/pl01x.S" if DEBUG_LL_UART_PL01X || DEBUG_UART_PL01X
@@ -1061,6 +1185,14 @@ config DEBUG_LL_INCLUDE
                                 DEBUG_IMX6SX_UART
        default "debug/msm.S" if DEBUG_MSM_UART || DEBUG_QCOM_UARTDM
        default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
+        default "debug/renesas-scif.S" if DEBUG_R7S72100_SCIF2
+        default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF0
+        default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF2
+        default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF0
+        default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF2
+        default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA0
+        default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA1
+        default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4
        default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART
        default "debug/s5pv210.S" if DEBUG_S5PV210_UART
        default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
@@ -1106,6 +1238,7 @@ config DEBUG_UART_PHYS
        default 0x02530c00 if DEBUG_KEYSTONE_UART0
        default 0x02531000 if DEBUG_KEYSTONE_UART1
        default 0x03010fe0 if ARCH_RPC
+        default 0x07000000 if DEBUG_SUN9I_UART0
        default 0x10009000 if DEBUG_REALVIEW_STD_PORT || \
                                DEBUG_VEXPRESS_UART0_CA9
        default 0x1010c000 if DEBUG_REALVIEW_PB1176_PORT
@@ -1113,7 +1246,9 @@ config DEBUG_UART_PHYS
        default 0x10126000 if DEBUG_RK3X_UART1
        default 0x101f1000 if ARCH_VERSATILE
        default 0x101fb000 if DEBUG_NOMADIK_UART
+        default 0x11002000 if DEBUG_MT8127_UART0
        default 0x11006000 if DEBUG_MT6589_UART0
+        default 0x11009000 if DEBUG_MT8135_UART3
        default 0x16000000 if ARCH_INTEGRATOR
        default 0x18000300 if DEBUG_BCM_5301X
        default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1
@@ -1135,6 +1270,7 @@ config DEBUG_UART_PHYS
        default 0x78000000 if DEBUG_CNS3XXX
        default 0x7c0003f8 if FOOTBRIDGE
        default 0x78000000 if DEBUG_CNS3XXX
+        default 0x80010000 if DEBUG_ASM9260_UART
        default 0x80070000 if DEBUG_IMX23_UART
        default 0x80074000 if DEBUG_IMX28_UART
        default 0x80230000 if DEBUG_PICOXCELL_UART
@@ -1152,7 +1288,14 @@ config DEBUG_UART_PHYS
        default 0xd4018000 if DEBUG_MMP_UART3
        default 0xe0000000 if ARCH_SPEAR13XX
        default 0xe4007000 if DEBUG_HIP04_UART
+        default 0xe6c40000 if DEBUG_RMOBILE_SCIFA0
+        default 0xe6c50000 if DEBUG_RMOBILE_SCIFA1
+        default 0xe6c80000 if DEBUG_RMOBILE_SCIFA4
+        default 0xe6e58000 if DEBUG_RCAR_GEN2_SCIF2
+        default 0xe6e60000 if DEBUG_RCAR_GEN2_SCIF0
+        default 0xe8008000 if DEBUG_R7S72100_SCIF2
        default 0xf0000be0 if ARCH_EBSA110
+        default 0xf040ab00 if DEBUG_BRCMSTB_UART
        default 0xf1012000 if DEBUG_MVEBU_UART_ALTERNATE
        default 0xf1012000 if ARCH_DOVE || ARCH_MV78XX0 || \
                                ARCH_ORION5X
@@ -1164,24 +1307,33 @@ config DEBUG_UART_PHYS
        default 0xff690000 if DEBUG_RK32_UART2
        default 0xffc02000 if DEBUG_SOCFPGA_UART
        default 0xffd82340 if ARCH_IOP13XX
+        default 0xffe40000 if DEBUG_RCAR_GEN1_SCIF0
+        default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2
        default 0xfff36000 if DEBUG_HIGHBANK_UART
        default 0xfffe8600 if DEBUG_UART_BCM63XX
        default 0xfffff700 if ARCH_IOP33X
        depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
                DEBUG_LL_UART_EFM32 || \
                DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
-                DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
+                DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \
-                DEBUG_UART_BCM63XX
+                DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \
+                DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF2 || \
+                DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \
+                DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \
+                DEBUG_UART_BCM63XX || DEBUG_ASM9260_UART
 config DEBUG_UART_VIRT
        hex "Virtual base address of debug UART"
        default 0xe0010fe0 if ARCH_RPC
        default 0xe1000000 if DEBUG_MSM_UART
        default 0xf0000be0 if ARCH_EBSA110
+        default 0xf0010000 if DEBUG_ASM9260_UART
        default 0xf01fb000 if DEBUG_NOMADIK_UART
        default 0xf0201000 if DEBUG_BCM2835
        default 0xf1000300 if DEBUG_BCM_5301X
+        default 0xf1002000 if DEBUG_MT8127_UART0
        default 0xf1006000 if DEBUG_MT6589_UART0
+        default 0xf1009000 if DEBUG_MT8135_UART3
        default 0xf11f1000 if ARCH_VERSATILE
        default 0xf1600000 if ARCH_INTEGRATOR
        default 0xf1c28000 if DEBUG_SUNXI_UART0
@@ -1190,6 +1342,7 @@ config DEBUG_UART_VIRT
        default 0xf6200000 if DEBUG_PXA_UART1
        default 0xf4090000 if ARCH_LPC32XX
        default 0xf4200000 if ARCH_GEMINI
+        default 0xf7000000 if DEBUG_SUN9I_UART0
        default 0xf7000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \
                                DEBUG_S3C2410_UART0)
        default 0xf7004000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART1 || \
@@ -1204,6 +1357,7 @@ config DEBUG_UART_VIRT
        default 0xfb002000 if DEBUG_CNS3XXX
        default 0xfb009000 if DEBUG_REALVIEW_STD_PORT
        default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT
+        default 0xfc40ab00 if DEBUG_BRCMSTB_UART
        default 0xfcfe8600 if DEBUG_UART_BCM63XX
        default 0xfd000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX
        default 0xfd000000 if ARCH_SPEAR13XX
@@ -1244,12 +1398,12 @@ config DEBUG_UART_VIRT
        depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
                DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
                DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
-                DEBUG_UART_BCM63XX
+                DEBUG_UART_BCM63XX || DEBUG_ASM9260_UART
 config DEBUG_UART_8250_SHIFT
        int "Register offset shift for the 8250 debug UART"
        depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
-        default 0 if FOOTBRIDGE || ARCH_IOP32X
+        default 0 if FOOTBRIDGE || ARCH_IOP32X || DEBUG_BCM_5301X
        default 2
 config DEBUG_UART_8250_WORD
@@ -1260,7 +1414,8 @@ config DEBUG_UART_8250_WORD
                ARCH_KEYSTONE || \
                DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
                DEBUG_DAVINCI_DA8XX_UART2 || \
-                DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2
+                DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2 || \
+                DEBUG_BRCMSTB_UART
 config DEBUG_UART_8250_FLOW_CONTROL
        bool "Enable flow control for 8250 UART"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 034a94904d69..c1785eec2cf7 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -312,8 +312,12 @@ $(INSTALL_TARGETS):
        $(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@
 PHONY += dtbs dtbs_install
-dtbs dtbs_install: prepare scripts
-        $(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $@
+dtbs: prepare scripts
+        $(Q)$(MAKE) $(build)=$(boot)/dts
+dtbs_install:
+        $(Q)$(MAKE) $(dtbinst)=$(boot)/dts
 # We use MRPROPER_FILES and CLEAN_FILES now
 archclean:
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 38c89cafa1ab..6a3d9a6c4497 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -54,8 +54,17 @@ dtb-$(CONFIG_ARCH_AT91)	+= at91-sama5d4ek.dtb
 dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
 dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
-dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
+dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b-plus.dtb
+dtb-$(CONFIG_ARCH_BCM_5301X) += \
+        bcm4708-buffalo-wzr-1750dhp.dtb \
+        bcm4708-netgear-r6250.dtb \
+        bcm4708-netgear-r6300-v2.dtb \
+        bcm47081-asus-rt-n18u.dtb \
+        bcm47081-buffalo-wzr-600dhp2.dtb
 dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb
+dtb-$(CONFIG_ARCH_BCM_CYGNUS) += bcm911360_entphn.dtb \
+        bcm911360k.dtb \
+        bcm958300k.dtb
 dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
        bcm21664-garnet.dtb
 dtb-$(CONFIG_ARCH_BERLIN) += \
@@ -67,7 +76,9 @@ dtb-$(CONFIG_ARCH_BRCMSTB) += \
 dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
        da850-evm.dtb
 dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb
-dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
+dtb-$(CONFIG_ARCH_EXYNOS) += exynos3250-monk.dtb \
+        exynos3250-rinato.dtb \
+        exynos4210-origen.dtb \
        exynos4210-smdkv310.dtb \
        exynos4210-trats.dtb \
        exynos4210-universal_c210.dtb \
@@ -81,6 +92,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
        exynos5250-arndale.dtb \
        exynos5250-smdk5250.dtb \
        exynos5250-snow.dtb \
+        exynos5250-spring.dtb \
        exynos5260-xyref5260.dtb \
        exynos5410-smdk5410.dtb \
        exynos5420-arndale-octa.dtb \
@@ -104,6 +116,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
        kirkwood-d2net.dtb \
        kirkwood-db-88f6281.dtb \
        kirkwood-db-88f6282.dtb \
+        kirkwood-dir665.dtb \
        kirkwood-dns320.dtb \
        kirkwood-dns325.dtb \
        kirkwood-dockstar.dtb \
@@ -240,6 +253,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
        imx6q-sabrelite.dtb \
        imx6q-sabresd.dtb \
        imx6q-sbc6x.dtb \
+        imx6q-tbs2910.dtb \
        imx6q-udoo.dtb \
        imx6q-wandboard.dtb \
        imx6q-wandboard-revb1.dtb \
@@ -250,6 +264,9 @@ dtb-$(CONFIG_ARCH_MXC) += \
        imx6q-tx6q-1110.dtb \
        imx6sl-evk.dtb \
        imx6sx-sdb.dtb \
+        ls1021a-qds.dtb \
+        ls1021a-twr.dtb \
+        vf500-colibri-eval-v3.dtb \
        vf610-colibri-eval-v3.dtb \
        vf610-cosmic.dtb \
        vf610-twr.dtb
@@ -274,7 +291,8 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
        imx28-m28evk.dtb \
        imx28-sps1.dtb \
        imx28-tx28.dtb
-dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb
+dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb \
+        ste-nomadik-nhk15.dtb
 dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \
        nspire-tp.dtb \
        nspire-clp.dtb
@@ -302,7 +320,9 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \
        omap3-ha.dtb \
        omap3-ha-lcd.dtb \
        omap3-igep0020.dtb \
+        omap3-igep0020-rev-f.dtb \
        omap3-igep0030.dtb \
+        omap3-igep0030-rev-g.dtb \
        omap3-ldp.dtb \
        omap3-lilly-dbb056.dtb \
        omap3-n900.dtb \
@@ -331,7 +351,8 @@ dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \
        am335x-evm.dtb \
        am335x-evmsk.dtb \
        am335x-nano.dtb \
-        am335x-pepper.dtb
+        am335x-pepper.dtb \
+        am335x-lxm.dtb
 dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \
        omap4-panda.dtb \
        omap4-panda-a4.dtb \
@@ -347,6 +368,7 @@ dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \
        omap5-sbc-t54.dtb \
        omap5-uevm.dtb
 dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb \
+        am57xx-beagle-x15.dtb \
        dra72-evm.dtb
 dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \
        orion5x-lacie-ethernet-disk-mini-v2.dtb \
@@ -363,8 +385,10 @@ dtb-$(CONFIG_ARCH_QCOM) += \
        qcom-msm8660-surf.dtb \
        qcom-msm8960-cdp.dtb \
        qcom-msm8974-sony-xperia-honami.dtb
+dtb-$(CONFIG_ARCH_REALVIEW) += arm-realview-pb1176.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
        rk3066a-bqcurie2.dtb \
+        rk3066a-marsboard.dtb \
        rk3188-radxarock.dtb \
        rk3288-evb-act8846.dtb \
        rk3288-evb-rk808.dtb
@@ -376,27 +400,27 @@ dtb-$(CONFIG_ARCH_S5PV210) += s5pv210-aquila.dtb \
        s5pv210-smdkc110.dtb \
        s5pv210-smdkv210.dtb \
        s5pv210-torbreck.dtb
-dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
+dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \
+        r8a73a4-ape6evm.dtb \
+        r8a73a4-ape6evm-reference.dtb \
        r8a7740-armadillo800eva.dtb \
        r8a7778-bockw.dtb \
        r8a7778-bockw-reference.dtb \
        r8a7779-marzen.dtb \
-        r8a7791-koelsch.dtb \
        r8a7790-lager.dtb \
+        sh7372-mackerel.dtb \
        sh73a0-kzm9g.dtb \
-        sh73a0-kzm9g-reference.dtb \
+        sh73a0-kzm9g-reference.dtb
-        r8a73a4-ape6evm.dtb \
-        r8a73a4-ape6evm-reference.dtb \
-        sh7372-mackerel.dtb
 dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
        r7s72100-genmai.dtb \
        r8a7740-armadillo800eva.dtb \
+        r8a7779-marzen.dtb \
+        r8a7790-lager.dtb \
        r8a7791-henninger.dtb \
        r8a7791-koelsch.dtb \
-        r8a7790-lager.dtb \
-        r8a7779-marzen.dtb \
        r8a7794-alt.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
+        socfpga_arria10_socdk.dtb \
        socfpga_cyclone5_socdk.dtb \
        socfpga_cyclone5_sockit.dtb \
        socfpga_cyclone5_socrates.dtb \
@@ -409,6 +433,7 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
        spear320-hmi.dtb
 dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
 dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \
+        stih410-b2120.dtb \
        stih415-b2000.dtb \
        stih415-b2020.dtb \
        stih416-b2000.dtb \
@@ -435,15 +460,20 @@ dtb-$(CONFIG_MACH_SUN6I) += \
        sun6i-a31-hummingbird.dtb \
        sun6i-a31-m9.dtb
 dtb-$(CONFIG_MACH_SUN7I) += \
+        sun7i-a20-bananapi.dtb \
        sun7i-a20-cubieboard2.dtb \
        sun7i-a20-cubietruck.dtb \
        sun7i-a20-hummingbird.dtb \
        sun7i-a20-i12-tvbox.dtb \
+        sun7i-a20-m3.dtb \
        sun7i-a20-olinuxino-lime.dtb \
+        sun7i-a20-olinuxino-lime2.dtb \
        sun7i-a20-olinuxino-micro.dtb \
        sun7i-a20-pcduino3.dtb
 dtb-$(CONFIG_MACH_SUN8I) += \
        sun8i-a23-ippo-q8h-v5.dtb
+dtb-$(CONFIG_MACH_SUN9I) += \
+        sun9i-a80-optimus.dtb
 dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
        tegra20-iris-512.dtb \
        tegra20-medcom-wide.dtb \
@@ -489,13 +519,15 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
        zynq-parallella.dtb \
        zynq-zc702.dtb \
        zynq-zc706.dtb \
-        zynq-zed.dtb
+        zynq-zed.dtb \
+        zynq-zybo.dtb
 dtb-$(CONFIG_MACH_ARMADA_370) += \
        armada-370-db.dtb \
        armada-370-mirabox.dtb \
        armada-370-netgear-rn102.dtb \
        armada-370-netgear-rn104.dtb \
-        armada-370-rd.dtb
+        armada-370-rd.dtb \
+        armada-370-synology-ds213j.dtb
 dtb-$(CONFIG_MACH_ARMADA_375) += \
        armada-375-db.dtb
 dtb-$(CONFIG_MACH_ARMADA_38X) += \
@@ -508,24 +540,20 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \
        armada-xp-lenovo-ix4-300d.dtb \
        armada-xp-matrix.dtb \
        armada-xp-netgear-rn2120.dtb \
-        armada-xp-openblocks-ax3-4.dtb
+        armada-xp-openblocks-ax3-4.dtb \
+        armada-xp-synology-ds414.dtb
 dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \
        dove-cubox.dtb \
        dove-cubox-es.dtb \
        dove-d2plug.dtb \
        dove-d3plug.dtb \
        dove-dove-db.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt6589-aquaris5.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt6589-aquaris5.dtb \
+        mt6592-evb.dtb \
+        mt8127-moose.dtb \
+        mt8135-evbp1.dtb
-targets += dtbs dtbs_install
-targets += $(dtb-y)
 endif
-# *.dtb used to be generated in the directory above. Clean out the
+always          := $(dtb-y)
-# old build results so people don't accidentally use them.
+clean-files     := *.dtb
-dtbs: $(addprefix $(obj)/, $(dtb-y))
-        $(Q)rm -f $(obj)/../*.dtb
-clean-files := *.dtb
-dtbs_install: $(addsuffix _dtbinst_, $(dtb-y))
diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts
index 901739fcb85a..5c42d259fa68 100644
--- a/arch/arm/boot/dts/am335x-boneblack.dts
+++ b/arch/arm/boot/dts/am335x-boneblack.dts
@@ -80,3 +80,7 @@
                status = "okay";
        };
 };
+&rtc {
+        system-power-controller;
+};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index c4b968f0feb5..54f118c08db8 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -307,6 +307,13 @@
                        0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
                >;
        };
+        dcan1_pins_default: dcan1_pins_default {
+                pinctrl-single,pins = <
+                        0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
+                        0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
+                >;
+        };
 };
 &uart0 {
@@ -437,9 +444,9 @@
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&nandflash_pins_s0>;
-        ranges = <0 0 0x08000000 0x10000000>;   /* CS0: NAND */
+        ranges = <0 0 0x08000000 0x1000000>;    /* CS0: 16MB for NAND */
        nand@0,0 {
-                reg = <0 0 0>; /* CS0, offset 0 */
+                reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
                ti,nand-ecc-opt = "bch8";
                ti,elm-id = <&elm>;
                nand-bus-width = <8>;
@@ -664,3 +671,9 @@
 &aes {
        status = "okay";
 };
+&dcan1 {
+        status = "disabled";    /* Enable only if Profile 1 is selected */
+        pinctrl-names = "default";
+        pinctrl-0 = <&dcan1_pins_default>;
+};
diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi
index a1a0cc5eb35c..c0e1135256cc 100644
--- a/arch/arm/boot/dts/am335x-igep0033.dtsi
+++ b/arch/arm/boot/dts/am335x-igep0033.dtsi
@@ -126,10 +126,10 @@
        pinctrl-names = "default";
        pinctrl-0 = <&nandflash_pins>;
-        ranges = <0 0 0x08000000 0x10000000>;   /* CS0: NAND */
+        ranges = <0 0 0x08000000 0x1000000>;    /* CS0: 16MB for NAND */
        nand@0,0 {
-                reg = <0 0 0>; /* CS0, offset 0 */
+                reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
                nand-bus-width = <8>;
                ti,nand-ecc-opt = "bch8";
                gpmc,device-width = <1>;
diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/am335x-lxm.dts
new file mode 100644
index 000000000000..7266a00aab2e
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-lxm.dts
@@ -0,0 +1,362 @@
+/*
+ * Copyright (C) 2014 NovaTech LLC - http://www.novatechweb.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "am33xx.dtsi"
+/ {
+        model = "NovaTech OrionLXm";
+        compatible = "novatech,am335x-lxm", "ti,am33xx";
+        cpus {
+                cpu@0 {
+                        cpu0-supply = <&vdd1_reg>;
+                };
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x20000000>; /* 512 MB */
+        };
+        /* Power supply provides a fixed 5V @2A */
+        vbat: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vbat";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
+        };
+        /* Power supply provides a fixed 3.3V @3A */
+        vmmcsd_fixed: fixedregulator@1 {
+                compatible = "regulator-fixed";
+                regulator-name = "vmmcsd_fixed";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+        };
+};
+&am33xx_pinmux {
+        mmc1_pins: pinmux_mmc1_pins {
+                pinctrl-single,pins = <
+                        0xf0 (PIN_INPUT_PULLUP | MUX_MODE0)     /* mmc0_dat3 */
+                        0xf4 (PIN_INPUT_PULLUP | MUX_MODE0)     /* mmc0_dat2 */
+                        0xf8 (PIN_INPUT_PULLUP | MUX_MODE0)     /* mmc0_dat1 */
+                        0xfc (PIN_INPUT_PULLUP | MUX_MODE0)     /* mmc0_dat0 */
+                        0x100 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_clk */
+                        0x104 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_cmd */
+                >;
+        };
+        i2c0_pins: pinmux_i2c0_pins {
+                pinctrl-single,pins = <
+                        0x188 (PIN_INPUT | MUX_MODE0)   /* i2c0_sda.i2c0_sda */
+                        0x18c (PIN_INPUT | MUX_MODE0)   /* i2c0_scl.i2c0_scl */
+                >;
+        };
+        cpsw_default: cpsw_default {
+                pinctrl-single,pins = <
+                        /* Slave 1 */
+                        0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii1_int */
+                        0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* rmii1_crs_dv */
+                        0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* rmii1_rxer */
+                        0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_txen */
+                        0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td1 */
+                        0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td0 */
+                        0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* rmii1_rd1 */
+                        0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* rmii1_rd0 */
+                        0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* rmii1_refclk */
+                        /* Slave 2 */
+                        0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)  /* rmii2_txen */
+                        0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)  /* rmii2_td1 */
+                        0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)  /* rmii2_td0 */
+                        0x68 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* rmii2_rd1 */
+                        0x6c (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* rmii2_rd0 */
+                        0x70 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* rmii2_crs_dv */
+                        0x74 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* rmii2_rxer */
+                        0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_int */
+                        0x108 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* rmii2_refclk */
+                >;
+        };
+        cpsw_sleep: cpsw_sleep {
+                pinctrl-single,pins = <
+                        /* Slave 1 reset value */
+                        0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii1_int */
+                        0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_crs_dv */
+                        0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_rxer */
+                        0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_txen */
+                        0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_td1 */
+                        0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_td0 */
+                        0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_rd1 */
+                        0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_rd0 */
+                        0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_refclk */
+                        /* Slave 2 reset value*/
+                        0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_txen */
+                        0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_td1 */
+                        0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_td0 */
+                        0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_rd1 */
+                        0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_rd0 */
+                        0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_crs_dv */
+                        0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_rxer */
+                        0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_int */
+                        0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii2_refclk */
+                >;
+        };
+        davinci_mdio_default: davinci_mdio_default {
+                pinctrl-single,pins = <
+                        /* MDIO */
+                        0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
+                        0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
+                >;
+        };
+        davinci_mdio_sleep: davinci_mdio_sleep {
+                pinctrl-single,pins = <
+                        /* MDIO reset value */
+                        0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                >;
+        };
+        emmc_pins: pinmux_emmc_pins {
+                pinctrl-single,pins = <
+                        0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
+                        0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
+                        0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
+                        0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
+                        0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
+                        0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
+                        0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
+                        0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
+                        0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
+                        0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
+                >;
+        };
+        uart0_pins: pinmux_uart0_pins {
+                pinctrl-single,pins = <
+                        0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
+                        0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+                >;
+        };
+};
+&i2c0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c0_pins>;
+        status = "okay";
+        clock-frequency = <400000>;
+        serial_config1: serial_config1@20 {
+                compatible = "nxp,pca9539";
+                reg = <0x20>;
+        };
+        serial_config2: serial_config2@21 {
+                compatible = "nxp,pca9539";
+                reg = <0x21>;
+        };
+        tps: tps@2d {
+                compatible = "ti,tps65910";
+                reg = <0x2d>;
+        };
+};
+/include/ "tps65910.dtsi"
+&tps {
+        vcc1-supply = <&vbat>;
+        vcc2-supply = <&vbat>;
+        vcc3-supply = <&vbat>;
+        vcc4-supply = <&vbat>;
+        vcc5-supply = <&vbat>;
+        vcc6-supply = <&vbat>;
+        vcc7-supply = <&vbat>;
+        vccio-supply = <&vbat>;
+        regulators {
+                /* vrtc - unused */
+                vio_reg: regulator@1 {
+                        regulator-name = "vio_1v5,ddr";
+                        regulator-min-microvolt = <1500000>;
+                        regulator-max-microvolt = <1500000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+                vdd1_reg: regulator@2 {
+                        regulator-name = "vdd1,mpu";
+                        regulator-min-microvolt = <600000>;
+                        regulator-max-microvolt = <1500000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+                vdd2_reg: regulator@3 {
+                        regulator-name = "vdd2_1v1,core";
+                        regulator-min-microvolt = <1100000>;
+                        regulator-max-microvolt = <1100000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+                /* vdd3 - unused */
+                /* vdig1 - unused */
+                vdig2_reg: regulator@6 {
+                        regulator-name = "vdig2_1v8,vdds_pll";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+                /* vpll - unused */
+                vdac_reg: regulator@8 {
+                        regulator-name = "vdac_1v8,vdds";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+                vaux1_reg: regulator@9 {
+                        regulator-name = "vaux1_1v8,usb";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+                vaux2_reg: regulator@10 {
+                        regulator-name = "vaux2_3v3,io";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+                vaux33_reg: regulator@11 {
+                        regulator-name = "vaux33_3v3,usb";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+                vmmc_reg: regulator@12 {
+                        regulator-name = "vmmc_3v3,io";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+        };
+};
+&sham {
+        status = "okay";
+};
+&aes {
+        status = "okay";
+};
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins>;
+        status = "okay";
+};
+&usb {
+        status = "okay";
+};
+&usb_ctrl_mod {
+        status = "okay";
+};
+&usb0_phy {
+        status = "okay";
+};
+&usb1_phy {
+        status = "okay";
+};
+&usb0 {
+        status = "okay";
+        dr_mode = "host";
+};
+&usb1 {
+        status = "okay";
+        dr_mode = "host";
+};
+&cppi41dma  {
+        status = "okay";
+};
+&cpsw_emac0 {
+        phy_id = <&davinci_mdio>, <5>;
+        phy-mode = "rmii";
+        dual_emac_res_vlan = <2>;
+};
+&cpsw_emac1 {
+        phy_id = <&davinci_mdio>, <4>;
+        phy-mode = "rmii";
+        dual_emac_res_vlan = <3>;
+};
+&mac {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&cpsw_default>;
+        pinctrl-1 = <&cpsw_sleep>;
+        dual_emac = <1>;
+        status = "okay";
+};
+&davinci_mdio {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&davinci_mdio_default>;
+        pinctrl-1 = <&davinci_mdio_sleep>;
+        status = "okay";
+};
+&mmc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+        vmmc-supply = <&vmmcsd_fixed>;
+        bus-width = <4>;
+        status = "okay";
+};
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&emmc_pins>;
+        vmmc-supply = <&vmmcsd_fixed>;
+        bus-width = <8>;
+        ti,non-removable;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 831810583823..acd37057bca9 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -83,6 +83,11 @@
                };
        };
+        am33xx_control_module: control_module@4a002000 {
+                compatible = "syscon";
+                reg = <0x44e10000 0x7fc>;
+        };
        am33xx_pinmux: pinmux@44e10800 {
                compatible = "pinctrl-single";
                reg = <0x44e10800 0x0238>;
@@ -204,6 +209,8 @@
                        reg = <0x44e09000 0x2000>;
                        interrupts = <72>;
                        status = "disabled";
+                        dmas = <&edma 26>, <&edma 27>;
+                        dma-names = "tx", "rx";
                };
                uart1: serial@48022000 {
@@ -213,6 +220,8 @@
                        reg = <0x48022000 0x2000>;
                        interrupts = <73>;
                        status = "disabled";
+                        dmas = <&edma 28>, <&edma 29>;
+                        dma-names = "tx", "rx";
                };
                uart2: serial@48024000 {
@@ -222,6 +231,8 @@
                        reg = <0x48024000 0x2000>;
                        interrupts = <74>;
                        status = "disabled";
+                        dmas = <&edma 30>, <&edma 31>;
+                        dma-names = "tx", "rx";
                };
                uart3: serial@481a6000 {
@@ -333,20 +344,24 @@
                        interrupts = <91>;
                };
-                dcan0: d_can@481cc000 {
+                dcan0: can@481cc000 {
-                        compatible = "bosch,d_can";
+                        compatible = "ti,am3352-d_can";
                        ti,hwmods = "d_can0";
-                        reg = <0x481cc000 0x2000
+                        reg = <0x481cc000 0x2000>;
-                                0x44e10644 0x4>;
+                        clocks = <&dcan0_fck>;
+                        clock-names = "fck";
+                        syscon-raminit = <&am33xx_control_module 0x644 0>;
                        interrupts = <52>;
                        status = "disabled";
                };
-                dcan1: d_can@481d0000 {
+                dcan1: can@481d0000 {
-                        compatible = "bosch,d_can";
+                        compatible = "ti,am3352-d_can";
                        ti,hwmods = "d_can1";
-                        reg = <0x481d0000 0x2000
+                        reg = <0x481d0000 0x2000>;
-                                0x44e10644 0x4>;
+                        clocks = <&dcan1_fck>;
+                        clock-names = "fck";
+                        syscon-raminit = <&am33xx_control_module 0x644 1>;
                        interrupts = <55>;
                        status = "disabled";
                };
@@ -356,6 +371,7 @@
                        reg = <0x480C8000 0x200>;
                        interrupts = <77>;
                        ti,hwmods = "mailbox";
+                        #mbox-cells = <1>;
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <8>;
                        mbox_wkupm3: wkup_m3 {
@@ -419,7 +435,7 @@
                };
                rtc: rtc@44e3e000 {
-                        compatible = "ti,da830-rtc";
+                        compatible = "ti,am3352-rtc", "ti,da830-rtc";
                        reg = <0x44e3e000 0x1000>;
                        interrupts = <75
                                      76>;
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 46660ffd2b65..d42d7865dd53 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -57,6 +57,11 @@
                cache-level = <2>;
        };
+        am43xx_control_module: control_module@4a002000 {
+                compatible = "syscon";
+                reg = <0x44e10000 0x7f4>;
+        };
        am43xx_pinmux: pinmux@44e10800 {
                compatible = "ti,am437-padconf", "pinctrl-single";
                reg = <0x44e10800 0x31c>;
@@ -168,6 +173,7 @@
                        reg = <0x480C8000 0x200>;
                        interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mailbox";
+                        #mbox-cells = <1>;
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <8>;
                        mbox_wkupm3: wkup_m3 {
@@ -667,6 +673,26 @@
                        };
                };
+                tscadc: tscadc@44e0d000 {
+                        compatible = "ti,am3359-tscadc";
+                        reg = <0x44e0d000 0x1000>;
+                        ti,hwmods = "adc_tsc";
+                        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&adc_tsc_fck>;
+                        clock-names = "fck";
+                        status = "disabled";
+                        tsc {
+                                compatible = "ti,am3359-tsc";
+                        };
+                        adc {
+                                #io-channel-cells = <1>;
+                                compatible = "ti,am3359-adc";
+                        };
+                };
                sham: sham@53100000 {
                        compatible = "ti,omap5-sham";
                        ti,hwmods = "sham";
@@ -896,6 +922,28 @@
                        compatible = "mmio-sram";
                        reg = <0x40300000 0x40000>; /* 256k */
                };
+                dcan0: can@481cc000 {
+                        compatible = "ti,am4372-d_can", "ti,am3352-d_can";
+                        ti,hwmods = "d_can0";
+                        clocks = <&dcan0_fck>;
+                        clock-names = "fck";
+                        reg = <0x481cc000 0x2000>;
+                        syscon-raminit = <&am43xx_control_module 0x644 0>;
+                        interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+                dcan1: can@481d0000 {
+                        compatible = "ti,am4372-d_can", "ti,am3352-d_can";
+                        ti,hwmods = "d_can1";
+                        clocks = <&dcan1_fck>;
+                        clock-names = "fck";
+                        reg = <0x481d0000 0x2000>;
+                        syscon-raminit = <&am43xx_control_module 0x644 1>;
+                        interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index a521ac0a7d5a..7eaae4cf9f89 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -254,6 +254,20 @@
                        0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
                >;
        };
+        dcan0_default: dcan0_default_pins {
+                pinctrl-single,pins = <
+                        0x178 (PIN_OUTPUT | MUX_MODE2)          /* uart1_ctsn.d_can0_tx */
+                        0x17c (PIN_INPUT_PULLUP | MUX_MODE2)    /* uart1_rtsn.d_can0_rx */
+                >;
+        };
+        dcan1_default: dcan1_default_pins {
+                pinctrl-single,pins = <
+                        0x180 (PIN_OUTPUT | MUX_MODE2)          /* uart1_rxd.d_can1_tx */
+                        0x184 (PIN_INPUT_PULLUP | MUX_MODE2)    /* uart1_txd.d_can1_rx */
+                >;
+        };
 };
 &i2c0 {
@@ -343,6 +357,14 @@
        status = "okay";
 };
+&tscadc {
+        status = "okay";
+        adc {
+                ti,adc-channels = <0 1 2 3 4 5 6 7>;
+        };
+};
 &ecap0 {
        status = "okay";
        pinctrl-names = "default";
@@ -511,3 +533,15 @@
                };
        };
 };
+&dcan0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&dcan0_default>;
+        status = "okay";
+};
+&dcan1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&dcan1_default>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index f7e9bba10bd6..662261d6b2ca 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -438,9 +438,9 @@
        status = "okay";        /* Disable QSPI when enabling GPMC (NAND) */
        pinctrl-names = "default";
        pinctrl-0 = <&nand_flash_x8>;
-        ranges = <0 0 0x08000000 0x10000000>;   /* CS0: NAND */
+        ranges = <0 0 0x08000000 0x1000000>;    /* CS0: 16MB for NAND */
        nand@0,0 {
-                reg = <0 0 0>; /* CS0, offset 0 */
+                reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
                ti,nand-ecc-opt = "bch16";
                ti,elm-id = <&elm>;
                nand-bus-width = <8>;
@@ -519,6 +519,14 @@
        status = "okay";
 };
+&tscadc {
+        status = "okay";
+        adc {
+                ti,adc-channels = <0 1 2 3 4 5 6 7>;
+        };
+};
 &ecap0 {
                status = "okay";
                pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
new file mode 100644
index 000000000000..49edbda68cd5
--- /dev/null
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -0,0 +1,405 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "dra74x.dtsi"
+#include <dt-bindings/clk/ti-dra7-atl.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+/ {
+        model = "TI AM5728 BeagleBoard-X15";
+        compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
+        aliases {
+                rtc0 = &mcp_rtc;
+                rtc1 = &tps659038_rtc;
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x80000000>;
+        };
+        vdd_3v3: fixedregulator-vdd_3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "vdd_3v3";
+                vin-supply = <&regen1>;
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+        vtt_fixed: fixedregulator-vtt {
+                /* TPS51200 */
+                compatible = "regulator-fixed";
+                regulator-name = "vtt_fixed";
+                vin-supply = <&smps3_reg>;
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                regulator-boot-on;
+                enable-active-high;
+                gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&leds_pins_default>;
+                led@0 {
+                        label = "beagle-x15:usr0";
+                        gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                        default-state = "off";
+                };
+                led@1 {
+                        label = "beagle-x15:usr1";
+                        gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "cpu0";
+                        default-state = "off";
+                };
+                led@2 {
+                        label = "beagle-x15:usr2";
+                        gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "mmc0";
+                        default-state = "off";
+                };
+                led@3 {
+                        label = "beagle-x15:usr3";
+                        gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "ide-disk";
+                        default-state = "off";
+                };
+        };
+};
+&dra7_pmx_core {
+        leds_pins_default: leds_pins_default {
+                pinctrl-single,pins = <
+                        0x3a8 (PIN_OUTPUT | MUX_MODE14) /* spi1_d1.gpio7_8 */
+                        0x3ac (PIN_OUTPUT | MUX_MODE14) /* spi1_d0.gpio7_9 */
+                        0x3c0 (PIN_OUTPUT | MUX_MODE14) /* spi2_sclk.gpio7_14 */
+                        0x3c4 (PIN_OUTPUT | MUX_MODE14) /* spi2_d1.gpio7_15 */
+                >;
+        };
+        i2c1_pins_default: i2c1_pins_default {
+                pinctrl-single,pins = <
+                        0x400 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c1_sda.sda */
+                        0x404 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c1_scl.scl */
+                >;
+        };
+        i2c3_pins_default: i2c3_pins_default {
+                pinctrl-single,pins = <
+                        0x2a4 (PIN_INPUT| MUX_MODE10)   /* mcasp1_aclkx.i2c3_sda */
+                        0x2a8 (PIN_INPUT| MUX_MODE10)   /* mcasp1_fsx.i2c3_scl */
+                >;
+        };
+        uart3_pins_default: uart3_pins_default {
+                pinctrl-single,pins = <
+                        0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd.rxd */
+                        0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd.txd */
+                >;
+        };
+        mmc1_pins_default: mmc1_pins_default {
+                pinctrl-single,pins = <
+                        0x36c (PIN_INPUT | MUX_MODE14)  /* mmc1sdcd.gpio219 */
+                        0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+                        0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+                        0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+                        0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+                        0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+                        0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+                >;
+        };
+        mmc2_pins_default: mmc2_pins_default {
+                pinctrl-single,pins = <
+                        0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+                        0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+                        0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+                        0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+                        0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+                        0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+                        0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+                        0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+                        0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+                        0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+                >;
+        };
+        tps659038_pins_default: tps659038_pins_default {
+                pinctrl-single,pins = <
+                        0x418 (PIN_INPUT_PULLUP | MUX_MODE14)   /* wakeup0.gpio1_0 */
+                >;
+        };
+        tmp102_pins_default: tmp102_pins_default {
+                pinctrl-single,pins = <
+                        0x3C8 (PIN_INPUT_PULLUP | MUX_MODE14)   /* spi2_d0.gpio7_16 */
+                >;
+        };
+        mcp79410_pins_default: mcp79410_pins_default {
+                pinctrl-single,pins = <
+                        0x424 (PIN_INPUT_PULLUP | MUX_MODE1)    /* wakeup3.sys_nirq1 */
+                >;
+        };
+        usb1_pins: pinmux_usb1_pins {
+                pinctrl-single,pins = <
+                        0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
+                >;
+        };
+};
+&i2c1 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins_default>;
+        clock-frequency = <400000>;
+        tps659038: tps659038@58 {
+                compatible = "ti,tps659038";
+                reg = <0x58>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&tps659038_pins_default>;
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                ti,system-power-controller;
+                tps659038_pmic {
+                        compatible = "ti,tps659038-pmic";
+                        regulators {
+                                smps12_reg: smps12 {
+                                        /* VDD_MPU */
+                                        regulator-name = "smps12";
+                                        regulator-min-microvolt = < 850000>;
+                                        regulator-max-microvolt = <1250000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                smps3_reg: smps3 {
+                                        /* VDD_DDR */
+                                        regulator-name = "smps3";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                smps45_reg: smps45 {
+                                        /* VDD_DSPEVE, VDD_IVA, VDD_GPU */
+                                        regulator-name = "smps45";
+                                        regulator-min-microvolt = < 850000>;
+                                        regulator-max-microvolt = <1150000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                smps6_reg: smps6 {
+                                        /* VDD_CORE */
+                                        regulator-name = "smps6";
+                                        regulator-min-microvolt = <850000>;
+                                        regulator-max-microvolt = <1030000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                /* SMPS7 unused */
+                                smps8_reg: smps8 {
+                                        /* VDD_1V8 */
+                                        regulator-name = "smps8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                /* SMPS9 unused */
+                                ldo1_reg: ldo1 {
+                                        /* VDD_SD  */
+                                        regulator-name = "ldo1";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-boot-on;
+                                };
+                                ldo2_reg: ldo2 {
+                                        /* VDD_SHV5 */
+                                        regulator-name = "ldo2";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ldo3_reg: ldo3 {
+                                        /* VDDA_1V8_PHY */
+                                        regulator-name = "ldo3";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ldo9_reg: ldo9 {
+                                        /* VDD_RTC */
+                                        regulator-name = "ldo9";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ldoln_reg: ldoln {
+                                        /* VDDA_1V8_PLL */
+                                        regulator-name = "ldoln";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ldousb_reg: ldousb {
+                                        /* VDDA_3V_USB: VDDA_USBHS33 */
+                                        regulator-name = "ldousb";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-boot-on;
+                                };
+                                regen1: regen1 {
+                                        /* VDD_3V3_ON */
+                                        regulator-name = "regen1";
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+                tps659038_rtc: tps659038_rtc {
+                        compatible = "ti,palmas-rtc";
+                        interrupt-parent = <&tps659038>;
+                        interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
+                        wakeup-source;
+                };
+                tps659038_pwr_button: tps659038_pwr_button {
+                        compatible = "ti,palmas-pwrbutton";
+                        interrupt-parent = <&tps659038>;
+                        interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+                        wakeup-source;
+                        ti,palmas-long-press-seconds = <12>;
+                };
+        };
+        tmp102: tmp102@48 {
+                compatible = "ti,tmp102";
+                reg = <0x48>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&tmp102_pins_default>;
+                interrupt-parent = <&gpio7>;
+                interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+        };
+};
+&i2c3 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c3_pins_default>;
+        clock-frequency = <400000>;
+        mcp_rtc: rtc@6f {
+                compatible = "microchip,mcp7941x";
+                reg = <0x6f>;
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_LOW>;  /* IRQ_SYS_1N */
+                pinctrl-names = "default";
+                pinctrl-0 = <&mcp79410_pins_default>;
+                vcc-supply = <&vdd_3v3>;
+                wakeup-source;
+        };
+};
+&gpio7 {
+        ti,no-reset-on-init;
+        ti,no-idle-on-init;
+};
+&cpu0 {
+        cpu0-supply = <&smps12_reg>;
+        voltage-tolerance = <1>;
+};
+&uart3 {
+        status = "okay";
+        interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+                              <&dra7_pmx_core 0x248>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins_default>;
+};
+&mmc1 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins_default>;
+        vmmc-supply = <&ldo1_reg>;
+        vmmc_aux-supply = <&vdd_3v3>;
+        pbias-supply = <&pbias_mmc_reg>;
+        bus-width = <4>;
+        cd-gpios = <&gpio6 27 0>; /* gpio 219 */
+};
+&mmc2 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins_default>;
+        vmmc-supply = <&vdd_3v3>;
+        bus-width = <8>;
+        ti,non-removable;
+        cap-mmc-dual-data-rate;
+};
+&sata {
+        status = "okay";
+};
+&usb2_phy1 {
+        phy-supply = <&ldousb_reg>;
+};
+&usb1 {
+        dr_mode = "host";
+        pinctrl-names = "default";
+        pinctrl-0 = <&usb1_pins>;
+};
diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts
new file mode 100644
index 000000000000..ff26c7ed8c41
--- /dev/null
+++ b/arch/arm/boot/dts/arm-realview-pb1176.dts
@@ -0,0 +1,412 @@
+/*
+ * Copyright 2014 Linaro Ltd
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "skeleton.dtsi"
+/ {
+        model = "ARM RealView PB1176";
+        compatible = "arm,realview-pb1176";
+        chosen { };
+        aliases {
+                serial0 = &pb1176_serial0;
+                serial1 = &pb1176_serial1;
+                serial2 = &pb1176_serial2;
+                serial3 = &pb1176_serial3;
+                serial4 = &fpga_serial;
+        };
+        memory {
+                /* 128 MiB memory @ 0x0 */
+                reg = <0x00000000 0x08000000>;
+        };
+        /* The voltage to the MMC card is hardwired at 3.3V */
+        vmmc: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vmmc";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+        };
+        xtal24mhz: xtal24mhz@24M {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <24000000>;
+        };
+        timclk: timclk@1M {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clock-div = <24>;
+                clock-mult = <1>;
+                clocks = <&xtal24mhz>;
+        };
+        mclk: mclk@24M {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clock-div = <1>;
+                clock-mult = <1>;
+                clocks = <&xtal24mhz>;
+        };
+        kmiclk: kmiclk@24M {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clock-div = <1>;
+                clock-mult = <1>;
+                clocks = <&xtal24mhz>;
+        };
+        sspclk: sspclk@24M {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clock-div = <1>;
+                clock-mult = <1>;
+                clocks = <&xtal24mhz>;
+        };
+        uartclk: uartclk@24M {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clock-div = <1>;
+                clock-mult = <1>;
+                clocks = <&xtal24mhz>;
+        };
+        /* FIXME: this actually hangs off the PLL clocks */
+        pclk: pclk@0 {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "arm,realview-pb1176-soc", "simple-bus";
+                regmap = <&syscon>;
+                ranges;
+                syscon: syscon@10000000 {
+                        compatible = "arm,realview-pb1176-syscon", "syscon";
+                        reg = <0x10000000 0x1000>;
+                        led@08.0 {
+                                compatible = "register-bit-led";
+                                offset = <0x08>;
+                                mask = <0x01>;
+                                label = "versatile:0";
+                                linux,default-trigger = "heartbeat";
+                                default-state = "on";
+                        };
+                        led@08.1 {
+                                compatible = "register-bit-led";
+                                offset = <0x08>;
+                                mask = <0x02>;
+                                label = "versatile:1";
+                                linux,default-trigger = "mmc0";
+                                default-state = "off";
+                        };
+                        led@08.2 {
+                                compatible = "register-bit-led";
+                                offset = <0x08>;
+                                mask = <0x04>;
+                                label = "versatile:2";
+                                linux,default-trigger = "cpu0";
+                                default-state = "off";
+                        };
+                        led@08.3 {
+                                compatible = "register-bit-led";
+                                offset = <0x08>;
+                                mask = <0x08>;
+                                label = "versatile:3";
+                                default-state = "off";
+                        };
+                        led@08.4 {
+                                compatible = "register-bit-led";
+                                offset = <0x08>;
+                                mask = <0x10>;
+                                label = "versatile:4";
+                                default-state = "off";
+                        };
+                        led@08.5 {
+                                compatible = "register-bit-led";
+                                offset = <0x08>;
+                                mask = <0x20>;
+                                label = "versatile:5";
+                                default-state = "off";
+                        };
+                        led@08.6 {
+                                compatible = "register-bit-led";
+                                offset = <0x08>;
+                                mask = <0x40>;
+                                label = "versatile:6";
+                                default-state = "off";
+                        };
+                        led@08.7 {
+                                compatible = "register-bit-led";
+                                offset = <0x08>;
+                                mask = <0x80>;
+                                label = "versatile:7";
+                                default-state = "off";
+                        };
+                };
+                /* Primary DevChip GIC synthesized with the CPU */
+                intc_dc1176: interrupt-controller@10120000 {
+                        compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
+                        #interrupt-cells = <3>;
+                        #address-cells = <1>;
+                        interrupt-controller;
+                        reg = <0x10121000 0x1000>,
+                              <0x10120000 0x100>;
+                };
+                L2: l2-cache {
+                        compatible = "arm,l220-cache";
+                        reg = <0x10110000 0x1000>;
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
+                        cache-unified;
+                        cache-level = <2>;
+                        /*
+                         * Override default cache size, sets and
+                         * associativity as these may be erroneously set
+                         * up by boot loader(s).
+                         */
+                        arm,override-auxreg;
+                        cache-size = <131072>; // 128kB
+                        cache-sets = <512>;
+                        cache-line-size = <32>;
+                };
+                pmu {
+                        compatible = "arm,arm1176-pmu";
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
+                };
+                timer01: timer@10104000 {
+                        compatible = "arm,sp804", "arm,primecell";
+                        reg = <0x10104000 0x1000>;
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&timclk>, <&timclk>, <&pclk>;
+                        clock-names = "timer1", "timer2", "apb_pclk";
+                };
+                timer23: timer@10105000 {
+                        compatible = "arm,sp804", "arm,primecell";
+                        reg = <0x10105000 0x1000>;
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
+                        arm,sp804-has-irq = <1>;
+                        clocks = <&timclk>, <&timclk>, <&pclk>;
+                        clock-names = "timer1", "timer2", "apb_pclk";
+                };
+                pb1176_rtc: rtc@10108000 {
+                        compatible = "arm,pl031", "arm,primecell";
+                        reg = <0x10108000 0x1000>;
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                };
+                pb1176_gpio0: gpio@1010a000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x1010a000 0x1000>;
+                        gpio-controller;
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                };
+                pb1176_ssp: ssp@1010b000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0x1010b000 0x1000>;
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&sspclk>, <&pclk>;
+                        clock-names = "SSPCLK", "apb_pclk";
+                };
+                pb1176_serial0: serial@1010c000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x1010c000 0x1000>;
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&uartclk>, <&pclk>;
+                        clock-names = "uartclk", "apb_pclk";
+                };
+                pb1176_serial1: serial@1010d000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x1010d000 0x1000>;
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&uartclk>, <&pclk>;
+                        clock-names = "uartclk", "apb_pclk";
+                };
+                pb1176_serial2: serial@1010e000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x1010e000 0x1000>;
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&uartclk>, <&pclk>;
+                        clock-names = "uartclk", "apb_pclk";
+                };
+                pb1176_serial3: serial@1010f000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x1010f000 0x1000>;
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&uartclk>, <&pclk>;
+                        clock-names = "uartclk", "apb_pclk";
+                };
+        };
+        /* These peripherals are inside the FPGA rather than the DevChip */
+        fpga {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+                fpga_mci: mmcsd@10005000 {
+                        compatible = "arm,pl18x", "arm,primecell";
+                        reg = <0x10005000 0x1000>;
+                        interrupt-parent = <&intc_fpga1176>;
+                        interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>,
+                                        <0 2 IRQ_TYPE_LEVEL_HIGH>;
+                        /* Due to frequent FIFO overruns, use just 500 kHz */
+                        max-frequency = <500000>;
+                        bus-width = <4>;
+                        cap-sd-highspeed;
+                        cap-mmc-highspeed;
+                        clocks = <&mclk>, <&pclk>;
+                        clock-names = "mclk", "apb_pclk";
+                        vmmc-supply = <&vmmc>;
+                        cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>;
+                        wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>;
+                };
+                fpga_kmi0: kmi@10006000 {
+                        compatible = "arm,pl050", "arm,primecell";
+                        reg = <0x10006000 0x1000>;
+                        interrupt-parent = <&intc_fpga1176>;
+                        interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&kmiclk>, <&pclk>;
+                        clock-names = "KMIREFCLK", "apb_pclk";
+                };
+                fpga_kmi1: kmi@10007000 {
+                        compatible = "arm,pl050", "arm,primecell";
+                        reg = <0x10007000 0x1000>;
+                        interrupt-parent = <&intc_fpga1176>;
+                        interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&kmiclk>, <&pclk>;
+                        clock-names = "KMIREFCLK", "apb_pclk";
+                };
+                fpga_charlcd: charlcd@10008000 {
+                        compatible = "arm,versatile-lcd";
+                        reg = <0x10008000 0x1000>;
+                        interrupt-parent = <&intc_fpga1176>;
+                        interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                };
+                fpga_serial: serial@10009000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x10009000 0x1000>;
+                        interrupt-parent = <&intc_fpga1176>;
+                        interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&uartclk>, <&pclk>;
+                        clock-names = "uartclk", "apb_pclk";
+                };
+                /* This GIC on the board is cascaded off the DevChip GIC */
+                intc_fpga1176: interrupt-controller@10040000 {
+                        compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
+                        #interrupt-cells = <3>;
+                        #address-cells = <1>;
+                        interrupt-controller;
+                        reg = <0x10041000 0x1000>,
+                              <0x10040000 0x100>;
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
+                };
+                fpga_gpio0: gpio@10014000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x10014000 0x1000>;
+                        gpio-controller;
+                        interrupt-parent = <&intc_fpga1176>;
+                        interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                };
+                fpga_gpio1: gpio@10015000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x10015000 0x1000>;
+                        gpio-controller;
+                        interrupt-parent = <&intc_fpga1176>;
+                        interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                };
+                fpga_rtc: rtc@10017000 {
+                        compatible = "arm,pl031", "arm,primecell";
+                        reg = <0x10017000 0x1000>;
+                        interrupt-parent = <&intc_fpga1176>;
+                        interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index a495e5821ab8..1466580be295 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -75,6 +75,7 @@
                                clock-frequency = <100000>;
                                status = "okay";
                                audio_codec: audio-codec@4a {
+                                        #sound-dai-cells = <0>;
                                        compatible = "cirrus,cs42l51";
                                        reg = <0x4a>;
                                };
@@ -102,30 +103,6 @@
                                broken-cd;
                        };
-                        pinctrl {
-                                /*
-                                 * These pins might be muxed as I2S by
-                                 * the bootloader, but it conflicts
-                                 * with the real I2S pins that are
-                                 * muxed using i2s_pins. We must mux
-                                 * those pins to a function other than
-                                 * I2S.
-                                 */
-                                pinctrl-0 = <&hog_pins1 &hog_pins2>;
-                                pinctrl-names = "default";
-                                hog_pins1: hog-pins1 {
-                                        marvell,pins = "mpp6",  "mpp8", "mpp10",
-                                                       "mpp12", "mpp13";
-                                        marvell,function = "gpio";
-                                };
-                                hog_pins2: hog-pins2 {
-                                        marvell,pins = "mpp5", "mpp7", "mpp9";
-                                        marvell,function = "gpo";
-                                };
-                        };
                        usb@50000 {
                                status = "okay";
                        };
@@ -135,6 +112,8 @@
                        };
                        spi0: spi@10600 {
+                                pinctrl-0 = <&spi0_pins2>;
+                                pinctrl-names = "default";
                                status = "okay";
                                spi-flash@0 {
@@ -167,17 +146,84 @@
        };
        sound {
-              compatible = "marvell,a370db-audio";
+                compatible = "simple-audio-card";
-              marvell,audio-controller = <&audio_controller>;
+                simple-audio-card,name = "Armada 370 DB Audio";
-              marvell,audio-codec = <&audio_codec &spdif_out &spdif_in>;
+                simple-audio-card,mclk-fs = <256>;
-              status = "okay";
+                simple-audio-card,widgets =
+                        "Headphone", "Out Jack",
+                        "Line", "In Jack";
+                simple-audio-card,routing =
+                        "Out Jack", "HPL",
+                        "Out Jack", "HPR",
+                        "AIN1L", "In Jack",
+                        "AIN1L", "In Jack";
+                status = "okay";
+                simple-audio-card,dai-link@0 {
+                        format = "i2s";
+                        cpu {
+                                sound-dai = <&audio_controller 0>;
+                        };
+                        codec {
+                                sound-dai = <&audio_codec>;
+                        };
+                };
+                simple-audio-card,dai-link@1 {
+                        format = "i2s";
+                        cpu {
+                                sound-dai = <&audio_controller 1>;
+                        };
+                        codec {
+                                sound-dai = <&spdif_out>;
+                        };
+                };
+                simple-audio-card,dai-link@2 {
+                        format = "i2s";
+                        cpu {
+                                sound-dai = <&audio_controller 1>;
+                        };
+                        codec {
+                                sound-dai = <&spdif_in>;
+                        };
+                };
        };
        spdif_out: spdif-out {
-              compatible = "linux,spdif-dit";
+                #sound-dai-cells = <0>;
+                compatible = "linux,spdif-dit";
        };
        spdif_in: spdif-in {
-              compatible = "linux,spdif-dir";
+                #sound-dai-cells = <0>;
+                compatible = "linux,spdif-dir";
+        };
+};
+&pinctrl {
+        /*
+         * These pins might be muxed as I2S by
+         * the bootloader, but it conflicts
+         * with the real I2S pins that are
+         * muxed using i2s_pins. We must mux
+         * those pins to a function other than
+         * I2S.
+         */
+        pinctrl-0 = <&hog_pins1 &hog_pins2>;
+        pinctrl-names = "default";
+        hog_pins1: hog-pins1 {
+                marvell,pins = "mpp6",  "mpp8", "mpp10",
+                               "mpp12", "mpp13";
+                marvell,function = "gpio";
+        };
+        hog_pins2: hog-pins2 {
+                marvell,pins = "mpp5", "mpp7", "mpp9";
+                marvell,function = "gpo";
        };
 };
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 2b6d24e0d1e8..e1b0eb6b091f 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -54,18 +54,6 @@
                                status = "okay";
                        };
-                        pinctrl {
-                                pwr_led_pin: pwr-led-pin {
-                                        marvell,pins = "mpp63";
-                                        marvell,function = "gpo";
-                                };
-                                stat_led_pins: stat-led-pins {
-                                        marvell,pins = "mpp64", "mpp65";
-                                        marvell,function = "gpio";
-                                };
-                        };
                        gpio_leds {
                                compatible = "gpio-leds";
                                pinctrl-names = "default";
@@ -169,3 +157,16 @@
                };
        };
 };
+&pinctrl {
+        pwr_led_pin: pwr-led-pin {
+                marvell,pins = "mpp63";
+                marvell,function = "gpo";
+        };
+        stat_led_pins: stat-led-pins {
+                marvell,pins = "mpp64", "mpp65";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index 3aebd93cc33c..4e24932c6e30 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -35,7 +35,7 @@
                pcie-controller {
                        status = "okay";
-                        /* Connected to Marvell SATA controller */
+                        /* Connected to Marvell 88SE9170 SATA controller */
                        pcie@1,0 {
                                /* Port 0, Lane 0 */
                                status = "okay";
@@ -53,53 +53,12 @@
                                status = "okay";
                        };
+                        /* eSATA interface */
                        sata@a0000 {
-                                nr-ports = <2>;
+                                nr-ports = <1>;
                                status = "okay";
                        };
-                        pinctrl {
-                                power_led_pin: power-led-pin {
-                                        marvell,pins = "mpp57";
-                                        marvell,function = "gpio";
-                                };
-                                sata1_led_pin: sata1-led-pin {
-                                        marvell,pins = "mpp15";
-                                        marvell,function = "gpio";
-                                };
-                                sata2_led_pin: sata2-led-pin {
-                                        marvell,pins = "mpp14";
-                                        marvell,function = "gpio";
-                                };
-                                backup_led_pin: backup-led-pin {
-                                        marvell,pins = "mpp56";
-                                        marvell,function = "gpio";
-                                };
-                                backup_button_pin: backup-button-pin {
-                                        marvell,pins = "mpp58";
-                                        marvell,function = "gpio";
-                                };
-                                power_button_pin: power-button-pin {
-                                        marvell,pins = "mpp62";
-                                        marvell,function = "gpio";
-                                };
-                                reset_button_pin: reset-button-pin {
-                                        marvell,pins = "mpp6";
-                                        marvell,function = "gpio";
-                                };
-                                poweroff: poweroff {
-                                        marvell,pins = "mpp8";
-                                        marvell,function = "gpio";
-                                };
-                        };
                        mdio {
                                pinctrl-0 = <&mdio_pins>;
                                pinctrl-names = "default";
@@ -204,20 +163,20 @@
                        default-state = "keep";
                };
-                green-sata1-led {
+                blue-sata1-led {
-                        label = "rn102:green:sata1";
+                        label = "rn102:blue:sata1";
                        gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
                        default-state = "on";
                };
-                green-sata2-led {
+                blue-sata2-led {
-                        label = "rn102:green:sata2";
+                        label = "rn102:blue:sata2";
                        gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
                        default-state = "on";
                };
-                green-backup-led {
+                blue-backup-led {
-                        label = "rn102:green:backup";
+                        label = "rn102:blue:backup";
                        gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
                        default-state = "on";
                };
@@ -256,3 +215,45 @@
                gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
        };
 };
+&pinctrl {
+        power_led_pin: power-led-pin {
+                marvell,pins = "mpp57";
+                marvell,function = "gpio";
+        };
+        sata1_led_pin: sata1-led-pin {
+                marvell,pins = "mpp15";
+                marvell,function = "gpio";
+        };
+        sata2_led_pin: sata2-led-pin {
+                marvell,pins = "mpp14";
+                marvell,function = "gpio";
+        };
+        backup_led_pin: backup-led-pin {
+                marvell,pins = "mpp56";
+                marvell,function = "gpio";
+        };
+        backup_button_pin: backup-button-pin {
+                marvell,pins = "mpp58";
+                marvell,function = "gpio";
+        };
+        power_button_pin: power-button-pin {
+                marvell,pins = "mpp62";
+                marvell,function = "gpio";
+        };
+        reset_button_pin: reset-button-pin {
+                marvell,pins = "mpp6";
+                marvell,function = "gpio";
+        };
+        poweroff: poweroff {
+                marvell,pins = "mpp8";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
index c2f414bb9aba..30586e47986a 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
@@ -53,38 +53,6 @@
                                status = "okay";
                        };
-                        pinctrl {
-                                poweroff: poweroff {
-                                        marvell,pins = "mpp60";
-                                        marvell,function = "gpio";
-                                };
-                                backup_button_pin: backup-button-pin {
-                                        marvell,pins = "mpp52";
-                                        marvell,function = "gpio";
-                                };
-                                power_button_pin: power-button-pin {
-                                        marvell,pins = "mpp62";
-                                        marvell,function = "gpio";
-                                };
-                                backup_led_pin: backup-led-pin {
-                                        marvell,pins = "mpp63";
-                                        marvell,function = "gpo";
-                                };
-                                power_led_pin: power-led-pin {
-                                        marvell,pins = "mpp64";
-                                        marvell,function = "gpio";
-                                };
-                                reset_button_pin: reset-button-pin {
-                                        marvell,pins = "mpp65";
-                                        marvell,function = "gpio";
-                                };
-                        };
                        mdio {
                                pinctrl-0 = <&mdio_pins>;
                                pinctrl-names = "default";
@@ -269,3 +237,35 @@
                gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
        };
 };
+&pinctrl {
+        poweroff: poweroff {
+                marvell,pins = "mpp60";
+                marvell,function = "gpio";
+        };
+        backup_button_pin: backup-button-pin {
+                marvell,pins = "mpp52";
+                marvell,function = "gpio";
+        };
+        power_button_pin: power-button-pin {
+                marvell,pins = "mpp62";
+                marvell,function = "gpio";
+        };
+        backup_led_pin: backup-led-pin {
+                marvell,pins = "mpp63";
+                marvell,function = "gpo";
+        };
+        power_led_pin: power-led-pin {
+                marvell,pins = "mpp64";
+                marvell,function = "gpio";
+        };
+        reset_button_pin: reset-button-pin {
+                marvell,pins = "mpp65";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index f57a8f841498..394308951ed9 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -59,18 +59,6 @@
                };
                internal-regs {
-                        pinctrl {
-                                fan_pins: fan-pins {
-                                        marvell,pins = "mpp8";
-                                        marvell,function = "gpio";
-                                };
-                                led_pins: led-pins {
-                                        marvell,pins = "mpp32";
-                                        marvell,function = "gpio";
-                                };
-                        };
                        serial@12000 {
                                status = "okay";
                        };
@@ -85,10 +73,6 @@
                                phy0: ethernet-phy@0 {
                                        reg = <0>;
                                };
-                                phy1: ethernet-phy@1 {
-                                        reg = <1>;
-                                };
                        };
                        ethernet@70000 {
@@ -100,8 +84,11 @@
                                pinctrl-0 = <&ge1_rgmii_pins>;
                                pinctrl-names = "default";
                                status = "okay";
-                                phy = <&phy1>;
                                phy-mode = "rgmii-id";
+                                fixed-link {
+                                           speed = <1000>;
+                                           full-duplex;
+                                };
                        };
                        mvsdio@d4000 {
@@ -173,4 +160,56 @@
                        };
                };
        };
+        dsa@0 {
+                compatible = "marvell,dsa";
+                #address-cells = <2>;
+                #size-cells = <0>;
+                dsa,ethernet = <&eth1>;
+                dsa,mii-bus = <&mdio>;
+                switch@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x10 0>; /* MDIO address 16, switch 0 in tree */
+                        port@0 {
+                                reg = <0>;
+                                label = "lan0";
+                        };
+                        port@1 {
+                               reg = <1>;
+                               label = "lan1";
+                        };
+                        port@2 {
+                               reg = <2>;
+                               label = "lan2";
+                        };
+                        port@3 {
+                               reg = <3>;
+                               label = "lan3";
+                        };
+                        port@5 {
+                              reg = <5>;
+                              label = "cpu";
+                        };
+                };
+         };
 };
+&pinctrl {
+        fan_pins: fan-pins {
+                marvell,pins = "mpp8";
+                marvell,function = "gpio";
+        };
+        led_pins: led-pins {
+                marvell,pins = "mpp32";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
new file mode 100644
index 000000000000..70fecde76ccb
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
@@ -0,0 +1,316 @@
+/*
+ * Device Tree file for Synology DS213j
+ *
+ * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the old 0xd0000000).
+ * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
+ * bootloaders provided by Marvell. It is used in recent versions of
+ * DSM software provided by Synology. Nonetheless, some earlier boards
+ * were delivered with an older version of u-boot that left internal
+ * registers mapped at 0xd0000000. If you have such a device you will
+ * not be able to directly boot a kernel based on this Device Tree. In
+ * that case, the preferred solution is to update your bootloader (e.g.
+ * by upgrading to latest version of DSM, or building a new one and
+ * installing it from u-boot prompt) or adjust the Devive Tree
+ * (s/0xf1000000/0xd0000000/ in 'ranges' below).
+ */
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-370.dtsi"
+/ {
+        model = "Synology DS213j";
+        compatible = "synology,ds213j", "marvell,armada370",
+                     "marvell,armada-370-xp";
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = &uart0;
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>; /* 512 MB */
+        };
+        soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+                          MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
+                internal-regs {
+                        /* RTC provided by Seiko S-35390A I2C RTC chip below */
+                        rtc@10300 {
+                                status = "disabled";
+                        };
+                        spi0: spi@10600 {
+                                status = "okay";
+                                spi-flash@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        compatible = "micron,n25q064";
+                                        reg = <0>; /* Chip select 0 */
+                                        spi-max-frequency = <20000000>;
+                                        /*
+                                         * Warning!
+                                         *
+                                         * Synology u-boot uses its compiled-in environment
+                                         * and it seems Synology did not care to change u-boot
+                                         * default configuration in order to allow saving a
+                                         * modified environment at a sensible location. So,
+                                         * if you do a 'saveenv' under u-boot, your modified
+                                         * environment will be saved at 1MB after the start
+                                         * of the flash, i.e. in the middle of the uImage.
+                                         * For that reason, it is strongly advised not to
+                                         * change the default environment, unless you know
+                                         * what you are doing.
+                                         */
+                                        partition@00000000 { /* u-boot */
+                                                label = "RedBoot";
+                                                reg = <0x00000000 0x000c0000>; /* 768KB */
+                                        };
+                                        partition@000c0000 { /* uImage */
+                                                label = "zImage";
+                                                reg = <0x000c0000 0x002d0000>; /* 2880KB */
+                                        };
+                                        partition@00390000 { /* uInitramfs */
+                                                label = "rd.gz";
+                                                reg = <0x00390000 0x00440000>; /* 4250KB */
+                                        };
+                                        partition@007d0000 { /* MAC address and serial number */
+                                                label = "vendor";
+                                                reg = <0x007d0000 0x00010000>; /* 64KB */
+                                        };
+                                        partition@007e0000 {
+                                                label = "RedBoot config";
+                                                reg = <0x007e0000 0x00010000>; /* 64KB */
+                                        };
+                                        partition@007f0000 {
+                                                label = "FIS directory";
+                                                reg = <0x007f0000 0x00010000>; /* 64KB */
+                                        };
+                                };
+                        };
+                        i2c@11000 {
+                                compatible = "marvell,mv64xxx-i2c";
+                                pinctrl-0 = <&i2c0_pins>;
+                                pinctrl-names = "default";
+                                clock-frequency = <400000>;
+                                status = "okay";
+                                /* Main device RTC chip */
+                                s35390a: s35390a@30 {
+                                         compatible = "sii,s35390a";
+                                         reg = <0x30>;
+                                };
+                        };
+                        /* Connected to a header on device's PCB */
+                        serial@12000 {
+                                status = "okay";
+                        };
+                        /* Connected to a TI MSP430F2111 for power control */
+                        serial@12100 {
+                                status = "okay";
+                        };
+                        poweroff@12100 {
+                                compatible = "synology,power-off";
+                                reg = <0x12100 0x100>;
+                                clocks = <&coreclk 0>;
+                        };
+                        /* rear USB port, near reset button */
+                        usb@50000 {
+                                status = "okay";
+                        };
+                        /* rear USB port, near RJ45 port */
+                        usb@51000 {
+                                status = "okay";
+                        };
+                        mdio {
+                                phy1: ethernet-phy@1 { /* Marvell 88E1512 */
+                                        reg = <1>;
+                                };
+                        };
+                        ethernet@70000 {
+                               status = "okay";
+                               phy = <&phy1>;
+                               phy-mode = "sgmii";
+                        };
+                        sata@a0000 {
+                                nr-ports = <2>;
+                                status = "okay";
+                        };
+                };
+        };
+        gpio-fan-32-38 {
+                status = "okay";
+                compatible = "gpio-fan";
+                pinctrl-0 = <&fan_ctrl_low_pin &fan_ctrl_mid_pin
+                             &fan_ctrl_high_pin &fan_alarm_pin>;
+                pinctrl-names = "default";
+                gpios = <&gpio1 31 GPIO_ACTIVE_HIGH
+                         &gpio2  0 GPIO_ACTIVE_HIGH
+                         &gpio2  1 GPIO_ACTIVE_HIGH>;
+                alarm-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+                gpio-fan,speed-map = <    0 0
+                                       1000 1
+                                       1150 2
+                                       1350 4
+                                       1500 3
+                                       1650 5
+                                       1750 6
+                                       1900 7 >;
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+                pinctrl-0 = <&disk1_led_pin
+                             &disk2_led_pin>;
+                pinctrl-names = "default";
+                disk1-led-amber {
+                        label = "synology:amber:disk1";
+                        gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
+                };
+                disk2-led-amber {
+                        label = "synology:amber:disk2";
+                        gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin>;
+                pinctrl-names = "default";
+                sata1_regulator: sata1-regulator {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "SATA1 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        startup-delay-us = <2000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+                };
+                sata2_regulator: sata2-regulator {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "SATA2 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        startup-delay-us = <4000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
+&pinctrl {
+        disk1_led_pin: disk1-led-pin {
+                marvell,pins = "mpp31";
+                marvell,function = "gpio";
+        };
+        disk2_led_pin: disk2-led-pin {
+                marvell,pins = "mpp32";
+                marvell,function = "gpio";
+        };
+        sata1_pwr_pin: sata1-pwr-pin {
+                marvell,pins = "mpp37";
+                marvell,function = "gpio";
+        };
+        sata2_pwr_pin: sata2-pwr-pin {
+                marvell,pins = "mpp62";
+                marvell,function = "gpio";
+        };
+        sata1_pres_pin: sata1-pres-pin {
+                marvell,pins = "mpp60";
+                marvell,function = "gpio";
+        };
+        sata2_pres_pin: sata2-pres-pin {
+                marvell,pins = "mpp48";
+                marvell,function = "gpio";
+        };
+        syno_id_bit0_pin: syno-id-bit0-pin {
+                marvell,pins = "mpp55";
+                marvell,function = "gpio";
+        };
+        syno_id_bit1_pin: syno-id-bit1-pin {
+                marvell,pins = "mpp56";
+                marvell,function = "gpio";
+        };
+        syno_id_bit2_pin: syno-id-bit2-pin {
+                marvell,pins = "mpp57";
+                marvell,function = "gpio";
+        };
+        syno_id_bit3_pin: syno-id-bit3-pin {
+                marvell,pins = "mpp58";
+                marvell,function = "gpio";
+        };
+        fan_ctrl_low_pin: fan-ctrl-low-pin {
+                marvell,pins = "mpp65";
+                marvell,function = "gpio";
+        };
+        fan_ctrl_mid_pin: fan-ctrl-mid-pin {
+                marvell,pins = "mpp64";
+                marvell,function = "gpio";
+        };
+        fan_ctrl_high_pin: fan-ctrl-high-pin {
+                marvell,pins = "mpp63";
+                marvell,function = "gpo";
+        };
+        fan_alarm_pin: fan-alarm-pin {
+                marvell,pins = "mpp38";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 83286ec9702c..1af428602748 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -151,7 +151,7 @@
                                status = "disabled";
                        };
-                        serial@12000 {
+                        uart0: serial@12000 {
                                compatible = "snps,dw-apb-uart";
                                reg = <0x12000 0x100>;
                                reg-shift = <2>;
@@ -160,7 +160,8 @@
                                clocks = <&coreclk 0>;
                                status = "disabled";
                        };
-                        serial@12100 {
+                        uart1: serial@12100 {
                                compatible = "snps,dw-apb-uart";
                                reg = <0x12100 0x100>;
                                reg-shift = <2>;
@@ -170,6 +171,10 @@
                                status = "disabled";
                        };
+                        pinctrl: pin-ctrl@18000 {
+                                reg = <0x18000 0x38>;
+                        };
                        coredivclk: corediv-clock@18740 {
                                compatible = "marvell,armada-370-corediv-clock";
                                reg = <0x18740 0xc>;
@@ -180,7 +185,8 @@
                        mbusc: mbus-controller@20000 {
                                compatible = "marvell,mbus-controller";
-                                reg = <0x20000 0x100>, <0x20180 0x20>;
+                                reg = <0x20000 0x100>, <0x20180 0x20>,
+                                      <0x20250 0x8>;
                        };
                        mpic: interrupt-controller@20000 {
@@ -232,7 +238,7 @@
                                status = "disabled";
                        };
-                        mdio {
+                        mdio: mdio {
                                #address-cells = <1>;
                                #size-cells = <0>;
                                compatible = "marvell,orion-mdio";
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 6b3c23b1e138..fdb3c12a6139 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -95,81 +95,30 @@
                                compatible = "marvell,aurora-outer-cache";
                                reg = <0x08000 0x1000>;
                                cache-id-part = <0x100>;
+                                cache-unified;
                                wt-override;
                        };
-                        i2c0: i2c@11000 {
+                        /*
-                                reg = <0x11000 0x20>;
+                         * Default SPI pinctrl setting, can be overwritten on
+                         * board level if a different configuration is used.
+                         */
+                        spi0: spi@10600 {
+                                pinctrl-0 = <&spi0_pins1>;
+                                pinctrl-names = "default";
                        };
-                        i2c1: i2c@11100 {
+                        spi1: spi@10680 {
-                                reg = <0x11100 0x20>;
+                                pinctrl-0 = <&spi1_pins>;
+                                pinctrl-names = "default";
                        };
-                        system-controller@18200 {
+                        i2c0: i2c@11000 {
-                                compatible = "marvell,armada-370-xp-system-controller";
+                                reg = <0x11000 0x20>;
-                                reg = <0x18200 0x100>;
                        };
-                        pinctrl {
+                        i2c1: i2c@11100 {
-                                compatible = "marvell,mv88f6710-pinctrl";
+                                reg = <0x11100 0x20>;
-                                reg = <0x18000 0x38>;
-                                sdio_pins1: sdio-pins1 {
-                                        marvell,pins = "mpp9",  "mpp11", "mpp12",
-                                                        "mpp13", "mpp14", "mpp15";
-                                        marvell,function = "sd0";
-                                };
-                                sdio_pins2: sdio-pins2 {
-                                        marvell,pins = "mpp47", "mpp48", "mpp49",
-                                                        "mpp50", "mpp51", "mpp52";
-                                        marvell,function = "sd0";
-                                };
-                                sdio_pins3: sdio-pins3 {
-                                        marvell,pins = "mpp48", "mpp49", "mpp50",
-                                                        "mpp51", "mpp52", "mpp53";
-                                        marvell,function = "sd0";
-                                };
-                                i2c0_pins: i2c0-pins {
-                                        marvell,pins = "mpp2", "mpp3";
-                                        marvell,function = "i2c0";
-                                };
-                                i2s_pins1: i2s-pins1 {
-                                        marvell,pins = "mpp5", "mpp6", "mpp7",
-                                                       "mpp8", "mpp9", "mpp10",
-                                                       "mpp12", "mpp13";
-                                        marvell,function = "audio";
-                                };
-                                i2s_pins2: i2s-pins2 {
-                                        marvell,pins = "mpp49", "mpp47", "mpp50",
-                                                       "mpp59", "mpp57", "mpp61",
-                                                       "mpp62", "mpp60", "mpp58";
-                                        marvell,function = "audio";
-                                };
-                                mdio_pins: mdio-pins {
-                                        marvell,pins = "mpp17", "mpp18";
-                                        marvell,function = "ge";
-                                };
-                                ge0_rgmii_pins: ge0-rgmii-pins {
-                                        marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
-                                                       "mpp9", "mpp10", "mpp11", "mpp12",
-                                                       "mpp13", "mpp14", "mpp15", "mpp16";
-                                        marvell,function = "ge0";
-                                };
-                                ge1_rgmii_pins: ge1-rgmii-pins {
-                                        marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
-                                                       "mpp23", "mpp24", "mpp25", "mpp26",
-                                                       "mpp27", "mpp28", "mpp29", "mpp30";
-                                        marvell,function = "ge1";
-                                };
                        };
                        gpio0: gpio@18100 {
@@ -205,6 +154,26 @@
                                interrupts = <91>;
                        };
+                        /*
+                         * Default UART pinctrl setting without RTS/CTS, can
+                         * be overwritten on board level if a different
+                         * configuration is used.
+                         */
+                        uart0: serial@12000 {
+                                pinctrl-0 = <&uart0_pins>;
+                                pinctrl-names = "default";
+                        };
+                        uart1: serial@12100 {
+                                pinctrl-0 = <&uart1_pins>;
+                                pinctrl-names = "default";
+                        };
+                        system-controller@18200 {
+                                compatible = "marvell,armada-370-xp-system-controller";
+                                reg = <0x18200 0x100>;
+                        };
                        gateclk: clock-gating-control@18220 {
                                compatible = "marvell,armada-370-gating-clock";
                                reg = <0x18220 0x4>;
@@ -249,6 +218,7 @@
                        };
                        audio_controller: audio-controller@30000 {
+                                #sound-dai-cells = <1>;
                                compatible = "marvell,armada370-audio";
                                reg = <0x30000 0x4000>;
                                interrupts = <93>;
@@ -305,3 +275,91 @@
                };
        };
 };
+&pinctrl {
+        compatible = "marvell,mv88f6710-pinctrl";
+        spi0_pins1: spi0-pins1 {
+                marvell,pins = "mpp33", "mpp34",
+                               "mpp35", "mpp36";
+                marvell,function = "spi0";
+        };
+        spi0_pins2: spi0_pins2 {
+                marvell,pins = "mpp32", "mpp63",
+                               "mpp64", "mpp65";
+                marvell,function = "spi0";
+        };
+        spi1_pins: spi1-pins {
+                marvell,pins = "mpp49", "mpp50",
+                               "mpp51", "mpp52";
+                marvell,function = "spi1";
+        };
+        uart0_pins: uart0-pins {
+                marvell,pins = "mpp0", "mpp1";
+                marvell,function = "uart0";
+        };
+        uart1_pins: uart1-pins {
+                marvell,pins = "mpp41", "mpp42";
+                marvell,function = "uart1";
+        };
+        sdio_pins1: sdio-pins1 {
+                marvell,pins = "mpp9",  "mpp11", "mpp12",
+                                "mpp13", "mpp14", "mpp15";
+                marvell,function = "sd0";
+        };
+        sdio_pins2: sdio-pins2 {
+                marvell,pins = "mpp47", "mpp48", "mpp49",
+                                "mpp50", "mpp51", "mpp52";
+                marvell,function = "sd0";
+        };
+        sdio_pins3: sdio-pins3 {
+                marvell,pins = "mpp48", "mpp49", "mpp50",
+                                "mpp51", "mpp52", "mpp53";
+                marvell,function = "sd0";
+        };
+        i2c0_pins: i2c0-pins {
+                marvell,pins = "mpp2", "mpp3";
+                marvell,function = "i2c0";
+        };
+        i2s_pins1: i2s-pins1 {
+                marvell,pins = "mpp5", "mpp6", "mpp7",
+                               "mpp8", "mpp9", "mpp10",
+                               "mpp12", "mpp13";
+                marvell,function = "audio";
+        };
+        i2s_pins2: i2s-pins2 {
+                marvell,pins = "mpp49", "mpp47", "mpp50",
+                               "mpp59", "mpp57", "mpp61",
+                               "mpp62", "mpp60", "mpp58";
+                marvell,function = "audio";
+        };
+        mdio_pins: mdio-pins {
+                marvell,pins = "mpp17", "mpp18";
+                marvell,function = "ge";
+        };
+        ge0_rgmii_pins: ge0-rgmii-pins {
+                marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
+                               "mpp9", "mpp10", "mpp11", "mpp12",
+                               "mpp13", "mpp14", "mpp15", "mpp16";
+                marvell,function = "ge0";
+        };
+        ge1_rgmii_pins: ge1-rgmii-pins {
+                marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
+                               "mpp23", "mpp24", "mpp25", "mpp26",
+                               "mpp27", "mpp28", "mpp29", "mpp30";
+                marvell,function = "ge1";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index de6571445cef..9721e55384ce 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -36,6 +36,12 @@
                        #clock-cells = <0>;
                        clock-frequency = <2000000000>;
                };
+                /* 25 MHz reference crystal */
+                refclk: oscillator {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <25000000>;
+                };
        };
        cpus {
@@ -366,13 +372,15 @@
                                                      <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
                                                      <&mpic 5>,
                                                      <&mpic 6>;
-                                clocks = <&coreclk 0>;
+                                clocks = <&coreclk 0>, <&refclk>;
+                                clock-names = "nbclk", "fixed";
                        };
                        watchdog@20300 {
                                compatible = "marvell,armada-375-wdt";
                                reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
-                                clocks = <&coreclk 0>;
+                                clocks = <&coreclk 0>, <&refclk>;
+                                clock-names = "nbclk", "fixed";
                        };
                        cpurst@20800 {
diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts
index 1af886f1e486..2aaa9d2ac284 100644
--- a/arch/arm/boot/dts/armada-385-db.dts
+++ b/arch/arm/boot/dts/armada-385-db.dts
@@ -116,11 +116,11 @@
                        };
                        sdhci@d8000 {
-                                clock-frequency = <200000000>;
                                broken-cd;
                                wp-inverted;
                                bus-width = <8>;
                                status = "okay";
+                                no-1-8-v;
                        };
                        usb3@f0000 {
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 242d0ecc99f3..74391dace9e7 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -25,9 +25,9 @@
        aliases {
                gpio0 = &gpio0;
                gpio1 = &gpio1;
-                eth0 = &eth0;
+                ethernet0 = &eth0;
-                eth1 = &eth1;
+                ethernet1 = &eth1;
-                eth2 = &eth2;
+                ethernet2 = &eth2;
        };
        soc {
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
index a55a97a70505..ca0200e20751 100644
--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts
+++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
@@ -60,40 +60,6 @@
                };
                internal-regs {
-                        pinctrl {
-                                pinctrl-0 = <&pmx_phy_int>;
-                                pinctrl-names = "default";
-                                pmx_ge0: pmx-ge0 {
-                                        marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
-                                                       "mpp4", "mpp5", "mpp6", "mpp7",
-                                                       "mpp8", "mpp9", "mpp10", "mpp11";
-                                        marvell,function = "ge0";
-                                };
-                                pmx_ge1: pmx-ge1 {
-                                        marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15",
-                                                       "mpp16", "mpp17", "mpp18", "mpp19",
-                                                       "mpp20", "mpp21", "mpp22", "mpp23";
-                                        marvell,function = "ge1";
-                                };
-                                pmx_keys: pmx-keys {
-                                        marvell,pins = "mpp33";
-                                        marvell,function = "gpio";
-                                };
-                                pmx_spi: pmx-spi {
-                                        marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39";
-                                        marvell,function = "spi";
-                                };
-                                pmx_phy_int: pmx-phy-int {
-                                        marvell,pins = "mpp32";
-                                        marvell,function = "gpio";
-                                };
-                        };
                        serial@12000 {
                                status = "okay";
                        };
@@ -118,14 +84,14 @@
                        };
                        ethernet@70000 {
-                                pinctrl-0 = <&pmx_ge0>;
+                                pinctrl-0 = <&ge0_rgmii_pins>;
                                pinctrl-names = "default";
                                status = "okay";
                                phy = <&phy0>;
                                phy-mode = "rgmii-id";
                        };
                        ethernet@74000 {
-                                pinctrl-0 = <&pmx_ge1>;
+                                pinctrl-0 = <&ge1_rgmii_pins>;
                                pinctrl-names = "default";
                                status = "okay";
                                phy = <&phy1>;
@@ -134,8 +100,6 @@
                        spi0: spi@10600 {
                                status = "okay";
-                                pinctrl-0 = <&pmx_spi>;
-                                pinctrl-names = "default";
                                spi-flash@0 {
                                        #address-cells = <1>;
@@ -152,7 +116,7 @@
                compatible = "gpio-keys";
                #address-cells = <1>;
                #size-cells = <0>;
-                pinctrl-0 = <&pmx_keys>;
+                pinctrl-0 = <&keys_pin>;
                pinctrl-names = "default";
                button@1 {
@@ -162,3 +126,18 @@
                };
        };
 };
+&pinctrl {
+        pinctrl-0 = <&phy_int_pin>;
+        pinctrl-names = "default";
+        keys_pin: keys-pin {
+                marvell,pins = "mpp33";
+                marvell,function = "gpio";
+        };
+        phy_int_pin: phy-int-pin {
+                marvell,pins = "mpp32";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 0478c55ca656..ea8673647494 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -23,6 +23,7 @@
 */
 /dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
 #include "armada-xp-mv78460.dtsi"
 / {
@@ -48,6 +49,14 @@
                      <0x00000001 0x00000000 0x00000001 0x00000000>;
        };
+        cpus {
+                pm_pic {
+                        ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
+                                     <&gpio0 17 GPIO_ACTIVE_LOW>,
+                                     <&gpio0 18 GPIO_ACTIVE_LOW>;
+                };
+        };
        soc {
                ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
                          MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
@@ -115,7 +124,15 @@
                        serial@12300 {
                                status = "okay";
                        };
+                        pinctrl {
+                                pinctrl-0 = <&pic_pins>;
+                                pinctrl-names = "default";
+                                pic_pins: pic-pins-0 {
+                                        marvell,pins = "mpp16", "mpp17",
+                                                       "mpp18";
+                                        marvell,function = "gpio";
+                                };
+                        };
                        sata@a0000 {
                                nr-ports = <2>;
                                status = "okay";
diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
index 469cf7137595..a2ef93c1eb10 100644
--- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
+++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
@@ -22,7 +22,7 @@
        chosen {
                bootargs = "console=ttyS0,115200 earlyprintk";
-                stdout-path = "/soc/internal-regs/serial@12000";
+                stdout-path = &uart0;
        };
        memory {
@@ -51,37 +51,6 @@
                };
                internal-regs {
-                        pinctrl {
-                                poweroff_pin: poweroff-pin {
-                                        marvell,pins = "mpp24";
-                                        marvell,function = "gpio";
-                                };
-                                power_button_pin: power-button-pin {
-                                        marvell,pins = "mpp44";
-                                        marvell,function = "gpio";
-                                };
-                                reset_button_pin: reset-button-pin {
-                                        marvell,pins = "mpp45";
-                                        marvell,function = "gpio";
-                                };
-                                select_button_pin: select-button-pin {
-                                        marvell,pins = "mpp41";
-                                        marvell,function = "gpio";
-                                };
-                                scroll_button_pin: scroll-button-pin {
-                                        marvell,pins = "mpp42";
-                                        marvell,function = "gpio";
-                                };
-                                hdd_led_pin: hdd-led-pin {
-                                        marvell,pins = "mpp26";
-                                        marvell,function = "gpio";
-                                };
-                        };
                        serial@12000 {
                                status = "okay";
                        };
@@ -97,12 +66,16 @@
                        };
                        ethernet@70000 {
+                                pinctrl-0 = <&ge0_rgmii_pins>;
+                                pinctrl-names = "default";
                                status = "okay";
                                phy = <&phy0>;
                                phy-mode = "rgmii-id";
                        };
                        ethernet@74000 {
+                                pinctrl-0 = <&ge1_rgmii_pins>;
+                                pinctrl-names = "default";
                                status = "okay";
                                phy = <&phy1>;
                                phy-mode = "rgmii-id";
@@ -125,6 +98,11 @@
                                        reg = <0x2e>;
                                };
+                                eeprom@50 {
+                                        compatible = "atmel,24c64";
+                                        reg = <0x50>;
+                                };
                                pcf8563@51 {
                                        compatible = "nxp,pcf8563";
                                        reg = <0x51>;
@@ -226,7 +204,7 @@
                        gpio-controller;
                        #gpio-cells = <2>;
                        reg = <0>;
-                        registers-number = <2>;
+                        registers-number = <1>;
                        spi-max-frequency = <100000>;
                };
        };
@@ -282,3 +260,34 @@
                gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
        };
 };
+&pinctrl {
+        poweroff_pin: poweroff-pin {
+                marvell,pins = "mpp24";
+                marvell,function = "gpio";
+        };
+        power_button_pin: power-button-pin {
+                marvell,pins = "mpp44";
+                marvell,function = "gpio";
+        };
+        reset_button_pin: reset-button-pin {
+                marvell,pins = "mpp45";
+                marvell,function = "gpio";
+        };
+        select_button_pin: select-button-pin {
+                marvell,pins = "mpp41";
+                marvell,function = "gpio";
+        };
+        scroll_button_pin: scroll-button-pin {
+                marvell,pins = "mpp42";
+                marvell,function = "gpio";
+        };
+        hdd_led_pin: hdd-led-pin {
+                marvell,pins = "mpp26";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index 2592e1c13560..281ccd24295c 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -167,17 +167,6 @@
                };
                internal-regs {
-                        pinctrl {
-                                compatible = "marvell,mv78230-pinctrl";
-                                reg = <0x18000 0x38>;
-                                sdio_pins: sdio-pins {
-                                        marvell,pins = "mpp30", "mpp31", "mpp32",
-                                                       "mpp33", "mpp34", "mpp35";
-                                        marvell,function = "sd0";
-                                };
-                        };
                        gpio0: gpio@18100 {
                                compatible = "marvell,orion-gpio";
                                reg = <0x18100 0x40>;
@@ -202,3 +191,7 @@
                };
        };
 };
+&pinctrl {
+        compatible = "marvell,mv78230-pinctrl";
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 480e237a870f..d7a8d0b0f385 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -251,17 +251,6 @@
                };
                internal-regs {
-                        pinctrl {
-                                compatible = "marvell,mv78260-pinctrl";
-                                reg = <0x18000 0x38>;
-                                sdio_pins: sdio-pins {
-                                        marvell,pins = "mpp30", "mpp31", "mpp32",
-                                                       "mpp33", "mpp34", "mpp35";
-                                        marvell,function = "sd0";
-                                };
-                        };
                        gpio0: gpio@18100 {
                                compatible = "marvell,orion-gpio";
                                reg = <0x18100 0x40>;
@@ -305,3 +294,7 @@
                };
        };
 };
+&pinctrl {
+        compatible = "marvell,mv78260-pinctrl";
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 2c7b1fef4703..9c40c130d11a 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -289,17 +289,6 @@
                };
                internal-regs {
-                        pinctrl {
-                                compatible = "marvell,mv78460-pinctrl";
-                                reg = <0x18000 0x38>;
-                                sdio_pins: sdio-pins {
-                                        marvell,pins = "mpp30", "mpp31", "mpp32",
-                                                       "mpp33", "mpp34", "mpp35";
-                                        marvell,function = "sd0";
-                                };
-                        };
                        gpio0: gpio@18100 {
                                compatible = "marvell,orion-gpio";
                                reg = <0x18100 0x40>;
@@ -343,3 +332,7 @@
                };
        };
 };
+&pinctrl {
+        compatible = "marvell,mv78460-pinctrl";
+};
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
index 7d8f32873e82..d81430aa4ab3 100644
--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -55,86 +55,10 @@
                };
                internal-regs {
-                        pinctrl {
+                        /* Two rear eSATA ports */
-                                poweroff: poweroff {
+                        sata@a0000 {
-                                        marvell,pins = "mpp42";
+                                nr-ports = <2>;
-                                        marvell,function = "gpio";
+                                status = "okay";
-                                };
-                                power_button_pin: power-button-pin {
-                                        marvell,pins = "mpp27";
-                                        marvell,function = "gpio";
-                                };
-                                reset_button_pin: reset-button-pin {
-                                        marvell,pins = "mpp41";
-                                        marvell,function = "gpio";
-                                };
-                                sata1_led_pin: sata1-led-pin {
-                                        marvell,pins = "mpp31";
-                                        marvell,function = "gpio";
-                                };
-                                sata2_led_pin: sata2-led-pin {
-                                        marvell,pins = "mpp40";
-                                        marvell,function = "gpio";
-                                };
-                                sata3_led_pin: sata3-led-pin {
-                                        marvell,pins = "mpp44";
-                                        marvell,function = "gpio";
-                                };
-                                sata4_led_pin: sata4-led-pin {
-                                        marvell,pins = "mpp47";
-                                        marvell,function = "gpio";
-                                };
-                                sata1_power_pin: sata1-power-pin {
-                                        marvell,pins = "mpp24";
-                                        marvell,function = "gpio";
-                                };
-                                sata2_power_pin: sata2-power-pin {
-                                        marvell,pins = "mpp25";
-                                        marvell,function = "gpio";
-                                };
-                                sata3_power_pin: sata3-power-pin {
-                                        marvell,pins = "mpp26";
-                                        marvell,function = "gpio";
-                                };
-                                sata4_power_pin: sata4-power-pin {
-                                        marvell,pins = "mpp28";
-                                        marvell,function = "gpio";
-                                };
-                                sata1_pres_pin: sata1-pres-pin {
-                                        marvell,pins = "mpp32";
-                                        marvell,function = "gpio";
-                                };
-                                sata2_pres_pin: sata2-pres-pin {
-                                        marvell,pins = "mpp33";
-                                        marvell,function = "gpio";
-                                };
-                                sata3_pres_pin: sata3-pres-pin {
-                                        marvell,pins = "mpp34";
-                                        marvell,function = "gpio";
-                                };
-                                sata4_pres_pin: sata4-pres-pin {
-                                        marvell,pins = "mpp35";
-                                        marvell,function = "gpio";
-                                };
-                                err_led_pin: err-led-pin {
-                                        marvell,pins = "mpp45";
-                                        marvell,function = "gpio";
-                                };
                        };
                        serial@12000 {
@@ -328,3 +252,85 @@
                gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
        };
 };
+&pinctrl {
+        poweroff: poweroff {
+                marvell,pins = "mpp42";
+                marvell,function = "gpio";
+        };
+        power_button_pin: power-button-pin {
+                marvell,pins = "mpp27";
+                marvell,function = "gpio";
+        };
+        reset_button_pin: reset-button-pin {
+                marvell,pins = "mpp41";
+                marvell,function = "gpio";
+        };
+        sata1_led_pin: sata1-led-pin {
+                marvell,pins = "mpp31";
+                marvell,function = "gpio";
+        };
+        sata2_led_pin: sata2-led-pin {
+                marvell,pins = "mpp40";
+                marvell,function = "gpio";
+        };
+        sata3_led_pin: sata3-led-pin {
+                marvell,pins = "mpp44";
+                marvell,function = "gpio";
+        };
+        sata4_led_pin: sata4-led-pin {
+                marvell,pins = "mpp47";
+                marvell,function = "gpio";
+        };
+        sata1_power_pin: sata1-power-pin {
+                marvell,pins = "mpp24";
+                marvell,function = "gpio";
+        };
+        sata2_power_pin: sata2-power-pin {
+                marvell,pins = "mpp25";
+                marvell,function = "gpio";
+        };
+        sata3_power_pin: sata3-power-pin {
+                marvell,pins = "mpp26";
+                marvell,function = "gpio";
+        };
+        sata4_power_pin: sata4-power-pin {
+                marvell,pins = "mpp28";
+                marvell,function = "gpio";
+        };
+        sata1_pres_pin: sata1-pres-pin {
+                marvell,pins = "mpp32";
+                marvell,function = "gpio";
+        };
+        sata2_pres_pin: sata2-pres-pin {
+                marvell,pins = "mpp33";
+                marvell,function = "gpio";
+        };
+        sata3_pres_pin: sata3-pres-pin {
+                marvell,pins = "mpp34";
+                marvell,function = "gpio";
+        };
+        sata4_pres_pin: sata4-pres-pin {
+                marvell,pins = "mpp35";
+                marvell,function = "gpio";
+        };
+        err_led_pin: err-led-pin {
+                marvell,pins = "mpp45";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 4e5a59ee1501..6f6b0916df48 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -77,12 +77,7 @@
                        serial@12100 {
                                status = "okay";
                        };
-                        pinctrl {
-                                led_pins: led-pins-0 {
-                                        marvell,pins = "mpp49", "mpp51", "mpp53";
-                                        marvell,function = "gpio";
-                                };
-                        };
                        leds {
                                compatible = "gpio-leds";
                                pinctrl-names = "default";
@@ -187,3 +182,10 @@
                };
        };
 };
+&pinctrl {
+        led_pins: led-pins-0 {
+                marvell,pins = "mpp49", "mpp51", "mpp53";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
new file mode 100644
index 000000000000..749fdba5a642
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
@@ -0,0 +1,330 @@
+/*
+ * Device Tree file for Synology DS414
+ *
+ * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the old 0xd0000000).
+ * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
+ * bootloaders provided by Marvell. It is used in recent versions of
+ * DSM software provided by Synology. Nonetheless, some earlier boards
+ * were delivered with an older version of u-boot that left internal
+ * registers mapped at 0xd0000000. If you have such a device you will
+ * not be able to directly boot a kernel based on this Device Tree. In
+ * that case, the preferred solution is to update your bootloader (e.g.
+ * by upgrading to latest version of DSM, or building a new one and
+ * installing it from u-boot prompt) or adjust the Devive Tree
+ * (s/0xf1000000/0xd0000000/ in 'ranges' below).
+ */
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-xp-mv78230.dtsi"
+/ {
+        model = "Synology DS414";
+        compatible = "synology,ds414", "marvell,armadaxp-mv78230",
+                     "marvell,armadaxp", "marvell,armada-370-xp";
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = &uart0;
+        };
+        memory {
+                device_type = "memory";
+                reg = <0 0x00000000 0 0x40000000>; /* 1GB */
+        };
+        soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
+                pcie-controller {
+                        status = "okay";
+                        /*
+                         * Connected to Marvell 88SX7042 SATA-II controller
+                         * handling the four disks.
+                         */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                        /*
+                         * Connected to EtronTech EJ168A XHCI controller
+                         * providing the two rear USB 3.0 ports.
+                         */
+                        pcie@5,0 {
+                                /* Port 1, Lane 0 */
+                                status = "okay";
+                        };
+                };
+                internal-regs {
+                        /* RTC is provided by Seiko S-35390A below */
+                        rtc@10300 {
+                                status = "disabled";
+                        };
+                        spi0: spi@10600 {
+                                status = "okay";
+                                spi-flash@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        compatible = "micron,n25q064";
+                                        reg = <0>; /* Chip select 0 */
+                                        spi-max-frequency = <20000000>;
+                                        /*
+                                         * Warning!
+                                         *
+                                         * Synology u-boot uses its compiled-in environment
+                                         * and it seems Synology did not care to change u-boot
+                                         * default configuration in order to allow saving a
+                                         * modified environment at a sensible location. So,
+                                         * if you do a 'saveenv' under u-boot, your modified
+                                         * environment will be saved at 1MB after the start
+                                         * of the flash, i.e. in the middle of the uImage.
+                                         * For that reason, it is strongly advised not to
+                                         * change the default environment, unless you know
+                                         * what you are doing.
+                                         */
+                                        partition@00000000 { /* u-boot */
+                                                label = "RedBoot";
+                                                reg = <0x00000000 0x000d0000>; /* 832KB */
+                                        };
+                                        partition@000c0000 { /* uImage */
+                                                label = "zImage";
+                                                reg = <0x000d0000 0x002d0000>; /* 2880KB */
+                                        };
+                                        partition@003a0000 { /* uInitramfs */
+                                                label = "rd.gz";
+                                                reg = <0x003a0000 0x00430000>; /* 4250KB */
+                                        };
+                                        partition@007d0000 { /* MAC address and serial number */
+                                                label = "vendor";
+                                                reg = <0x007d0000 0x00010000>; /* 64KB */
+                                        };
+                                        partition@007e0000 {
+                                                label = "RedBoot config";
+                                                reg = <0x007e0000 0x00010000>; /* 64KB */
+                                        };
+                                        partition@007f0000 {
+                                                label = "FIS directory";
+                                                reg = <0x007f0000 0x00010000>; /* 64KB */
+                                        };
+                                };
+                        };
+                        i2c@11000 {
+                                clock-frequency = <400000>;
+                                status = "okay";
+                                s35390a: s35390a@30 {
+                                         compatible = "sii,s35390a";
+                                         reg = <0x30>;
+                                };
+                        };
+                        /* Connected to a header on device's PCB. This
+                         * provides the main console for the device.
+                         *
+                         * Warning: the device may not boot with a 3.3V
+                         * USB-serial converter connected when the power
+                         * button is pressed. The converter needs to be
+                         * connected a few seconds after pressing the
+                         * power button. This is possibly due to UART0_TXD
+                         * pin being sampled at reset (bit 0 of SAR).
+                         */
+                        serial@12000 {
+                                status = "okay";
+                        };
+                        /* Connected to a Microchip PIC16F883 for power control */
+                        serial@12100 {
+                                status = "okay";
+                        };
+                        poweroff@12100 {
+                                compatible = "synology,power-off";
+                                reg = <0x12100 0x100>;
+                                clocks = <&coreclk 0>;
+                        };
+                        /* Front USB 2.0 port */
+                        usb@50000 {
+                                status = "okay";
+                        };
+                        mdio {
+                                phy0: ethernet-phy@0 { /* Marvell 88E1512 */
+                                        reg = <0>;
+                                };
+                                phy1: ethernet-phy@1 { /* Marvell 88E1512 */
+                                        reg = <1>;
+                                };
+                        };
+                        ethernet@70000 {
+                                status = "okay";
+                                pinctrl-0 = <&ge0_rgmii_pins>;
+                                pinctrl-names = "default";
+                                phy = <&phy1>;
+                                phy-mode = "rgmii-id";
+                        };
+                        ethernet@74000 {
+                                pinctrl-0 = <&ge1_rgmii_pins>;
+                                pinctrl-names = "default";
+                                status = "okay";
+                                phy = <&phy0>;
+                                phy-mode = "rgmii-id";
+                        };
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin
+                             &sata3_pwr_pin &sata4_pwr_pin>;
+                pinctrl-names = "default";
+                sata1_regulator: sata1-regulator {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "SATA1 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        startup-delay-us = <2000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+                };
+                sata2_regulator: sata2-regulator {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "SATA2 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        startup-delay-us = <4000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+                };
+                sata3_regulator: sata3-regulator {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "SATA3 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        startup-delay-us = <6000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+                };
+                sata4_regulator: sata4-regulator {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "SATA4 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        startup-delay-us = <8000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
+&pinctrl {
+        sata1_pwr_pin: sata1-pwr-pin {
+                marvell,pins = "mpp42";
+                marvell,function = "gpio";
+        };
+        sata2_pwr_pin: sata2-pwr-pin {
+                marvell,pins = "mpp44";
+                marvell,function = "gpio";
+        };
+        sata3_pwr_pin: sata3-pwr-pin {
+                marvell,pins = "mpp45";
+                marvell,function = "gpio";
+        };
+        sata4_pwr_pin: sata4-pwr-pin {
+                marvell,pins = "mpp46";
+                marvell,function = "gpio";
+        };
+        sata1_pres_pin: sata1-pres-pin {
+                marvell,pins = "mpp34";
+                marvell,function = "gpio";
+        };
+        sata2_pres_pin: sata2-pres-pin {
+                marvell,pins = "mpp35";
+                marvell,function = "gpio";
+        };
+        sata3_pres_pin: sata3-pres-pin {
+                marvell,pins = "mpp40";
+                marvell,function = "gpio";
+        };
+        sata4_pres_pin: sata4-pres-pin {
+                marvell,pins = "mpp41";
+                marvell,function = "gpio";
+        };
+        syno_id_bit0_pin: syno-id-bit0-pin {
+                marvell,pins = "mpp26";
+                marvell,function = "gpio";
+        };
+        syno_id_bit1_pin: syno-id-bit1-pin {
+                marvell,pins = "mpp28";
+                marvell,function = "gpio";
+        };
+        syno_id_bit2_pin: syno-id-bit2-pin {
+                marvell,pins = "mpp29";
+                marvell,function = "gpio";
+        };
+        fan1_alarm_pin: fan1-alarm-pin {
+                marvell,pins = "mpp33";
+                marvell,function = "gpio";
+        };
+        fan2_alarm_pin: fan2-alarm-pin {
+                marvell,pins = "mpp32";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index bff9f6c18db1..62c3ba958b39 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -35,13 +35,24 @@
                };
                internal-regs {
+                        sdramc@1400 {
+                                compatible = "marvell,armada-xp-sdram-controller";
+                                reg = <0x1400 0x500>;
+                        };
                        L2: l2-cache {
                                compatible = "marvell,aurora-system-cache";
                                reg = <0x08000 0x1000>;
                                cache-id-part = <0x100>;
+                                cache-unified;
                                wt-override;
                        };
+                        spi0: spi@10600 {
+                                pinctrl-0 = <&spi0_pins>;
+                                pinctrl-names = "default";
+                        };
                        i2c0: i2c@11000 {
                                compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
                                reg = <0x11000 0x100>;
@@ -52,8 +63,10 @@
                                reg = <0x11100 0x100>;
                        };
-                        serial@12200 {
+                        uart2: serial@12200 {
                                compatible = "snps,dw-apb-uart";
+                                pinctrl-0 = <&uart2_pins>;
+                                pinctrl-names = "default";
                                reg = <0x12200 0x100>;
                                reg-shift = <2>;
                                interrupts = <43>;
@@ -61,8 +74,11 @@
                                clocks = <&coreclk 0>;
                                status = "disabled";
                        };
-                        serial@12300 {
+                        uart3: serial@12300 {
                                compatible = "snps,dw-apb-uart";
+                                pinctrl-0 = <&uart3_pins>;
+                                pinctrl-names = "default";
                                reg = <0x12300 0x100>;
                                reg-shift = <2>;
                                interrupts = <44>;
@@ -199,3 +215,54 @@
                };
        };
 };
+&pinctrl {
+        ge0_gmii_pins: ge0-gmii-pins {
+                marvell,pins =
+                     "mpp0",  "mpp1",  "mpp2",  "mpp3",
+                     "mpp4",  "mpp5",  "mpp6",  "mpp7",
+                     "mpp8",  "mpp9",  "mpp10", "mpp11",
+                     "mpp12", "mpp13", "mpp14", "mpp15",
+                     "mpp16", "mpp17", "mpp18", "mpp19",
+                     "mpp20", "mpp21", "mpp22", "mpp23";
+                marvell,function = "ge0";
+        };
+        ge0_rgmii_pins: ge0-rgmii-pins {
+                marvell,pins =
+                     "mpp0", "mpp1", "mpp2", "mpp3",
+                     "mpp4", "mpp5", "mpp6", "mpp7",
+                     "mpp8", "mpp9", "mpp10", "mpp11";
+                marvell,function = "ge0";
+        };
+        ge1_rgmii_pins: ge1-rgmii-pins {
+                marvell,pins =
+                     "mpp12", "mpp13", "mpp14", "mpp15",
+                     "mpp16", "mpp17", "mpp18", "mpp19",
+                     "mpp20", "mpp21", "mpp22", "mpp23";
+                marvell,function = "ge1";
+        };
+        sdio_pins: sdio-pins {
+                marvell,pins = "mpp30", "mpp31", "mpp32",
+                               "mpp33", "mpp34", "mpp35";
+                marvell,function = "sd0";
+        };
+        spi0_pins: spi0-pins {
+                marvell,pins = "mpp36", "mpp37",
+                               "mpp38", "mpp39";
+                marvell,function = "spi";
+        };
+        uart2_pins: uart2-pins {
+                marvell,pins = "mpp42", "mpp43";
+                marvell,function = "uart2";
+        };
+        uart3_pins: uart3-pins {
+                marvell,pins = "mpp44", "mpp45";
+                marvell,function = "uart3";
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 51416c7d0625..653e4395b7cb 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -677,6 +677,14 @@
                                        };
                                };
+                                can {
+                                        pinctrl_can_rx_tx: can_rx_tx {
+                                                atmel,pins =
+                                                        <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* CANRX, conflicts with IRQ0 */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* CANTX, conflicts with PCK0 */
+                                        };
+                                };
                                pioA: gpio@fffff200 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffff200 0x200>;
@@ -905,6 +913,17 @@
                                clock-names = "pwm_clk";
                                status = "disabled";
                        };
+                        can: can@fffac000 {
+                                compatible = "atmel,at91sam9263-can";
+                                reg = <0xfffac000 0x300>;
+                                interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_can_rx_tx>;
+                                clocks = <&can_clk>;
+                                clock-names = "can_clk";
+                                status = "disabled";
+                        };
                };
                fb0: fb@0x00700000 {
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
index c2554219f7a4..3c5fa3388997 100644
--- a/arch/arm/boot/dts/at91sam9x25.dtsi
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -10,6 +10,7 @@
 #include "at91sam9x5_usart3.dtsi"
 #include "at91sam9x5_macb0.dtsi"
 #include "at91sam9x5_macb1.dtsi"
+#include "at91sam9x5_can.dtsi"
 / {
        model = "Atmel AT91SAM9X25 SoC";
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
index 8eac66ce0ab7..499cdc81f4c0 100644
--- a/arch/arm/boot/dts/at91sam9x35.dtsi
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -8,6 +8,7 @@
 #include "at91sam9x5.dtsi"
 #include "at91sam9x5_macb0.dtsi"
+#include "at91sam9x5_can.dtsi"
 / {
        model = "Atmel AT91SAM9X35 SoC";
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 726274f7959b..bbb3ba65165f 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -860,6 +860,9 @@
                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_dbgu>;
+                                dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>,
+                                       <&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
+                                dma-names = "tx", "rx";
                                clocks = <&mck>;
                                clock-names = "usart";
                                status = "disabled";
@@ -871,6 +874,9 @@
                                interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart0>;
+                                dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>,
+                                       <&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
+                                dma-names = "tx", "rx";
                                clocks = <&usart0_clk>;
                                clock-names = "usart";
                                status = "disabled";
@@ -882,6 +888,9 @@
                                interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart1>;
+                                dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>,
+                                       <&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
+                                dma-names = "tx", "rx";
                                clocks = <&usart1_clk>;
                                clock-names = "usart";
                                status = "disabled";
@@ -893,6 +902,9 @@
                                interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart2>;
+                                dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>,
+                                       <&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
+                                dma-names = "tx", "rx";
                                clocks = <&usart2_clk>;
                                clock-names = "usart";
                                status = "disabled";
diff --git a/arch/arm/boot/dts/at91sam9x5_can.dtsi b/arch/arm/boot/dts/at91sam9x5_can.dtsi
index f44ab7702a12..8eb2f9c1b978 100644
--- a/arch/arm/boot/dts/at91sam9x5_can.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_can.dtsi
@@ -1,5 +1,5 @@
 /*
- * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
+ * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
 * Ethernet interface.
 *
 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
@@ -20,10 +20,50 @@
                                                reg = <29>;
                                        };
-                                        can1_clk: can1_clk {
+                                        can1_clk: can1_clk {
-                                                #clock-cells = <0>;
+                                                #clock-cells = <0>;
-                                                reg = <30>;
+                                                reg = <30>;
-                                        };
+                                        };
+                                };
+                        };
+                        can0: can@f8000000 {
+                                compatible = "atmel,at91sam9x5-can";
+                                reg = <0xf8000000 0x300>;
+                                interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_can0_rx_tx>;
+                                clocks = <&can0_clk>;
+                                clock-names = "can_clk";
+                                status = "disabled";
+                        };
+                        can1: can@f8004000 {
+                                compatible = "atmel,at91sam9x5-can";
+                                reg = <0xf8004000 0x300>;
+                                interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_can1_rx_tx>;
+                                clocks = <&can1_clk>;
+                                clock-names = "can_clk";
+                                status = "disabled";
+                        };
+                        pinctrl@fffff400 {
+                                can0 {
+                                        pinctrl_can0_rx_tx: can0_rx_tx {
+                                                atmel,pins =
+                                                        <AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE    /* CANRX0, conflicts with DRXD */
+                                                        AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* CANTX0, conflicts with DTXD */
+                                        };
+                                };
+                                can1 {
+                                        pinctrl_can1_rx_tx: can1_rx_tx {
+                                                atmel,pins =
+                                                        <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE    /* CANRX1, conflicts with RXD1 */
+                                                        AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;   /* CANTX1, conflicts with TXD1 */
+                                        };
                                };
                        };
                };
diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
index 140217a54384..43bb5b51caa6 100644
--- a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
@@ -57,6 +57,9 @@
                                interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart3>;
+                                dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>,
+                                       <&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
+                                dma-names = "tx", "rx";
                                clocks = <&usart3_clk>;
                                clock-names = "usart";
                                status = "disabled";
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
index bb22842a0826..29598667420b 100644
--- a/arch/arm/boot/dts/atlas6.dtsi
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -131,6 +131,7 @@
                                reg = <0x90020000 0x10000>;
                                interrupts = <31>;
                                clocks = <&clks 35>;
+                                resets = <&rstc 6>;
                        };
                };
@@ -312,6 +313,7 @@
                                #address-cells = <1>;
                                #size-cells = <0>;
                                clocks = <&clks 19>;
+                                resets = <&rstc 26>;
                                status = "disabled";
                        };
@@ -327,6 +329,7 @@
                                #address-cells = <1>;
                                #size-cells = <0>;
                                clocks = <&clks 20>;
+                                resets = <&rstc 27>;
                                status = "disabled";
                        };
@@ -522,6 +525,18 @@
                                                sirf,function = "sdmmc5";
                                        };
                                };
+                                i2s_mclk_pins_a: i2s_mclk@0 {
+                                        i2s_mclk {
+                                                sirf,pins = "i2smclkgrp";
+                                                sirf,function = "i2s_mclk";
+                                        };
+                                };
+                                i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 {
+                                        i2s_ext_clk_input {
+                                                sirf,pins = "i2s_ext_clk_inputgrp";
+                                                sirf,function = "i2s_ext_clk_input";
+                                        };
+                                };
                                i2s_pins_a: i2s@0 {
                                        i2s {
                                                sirf,pins = "i2sgrp";
diff --git a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
new file mode 100644
index 000000000000..60d8389fdb6c
--- /dev/null
+++ b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
@@ -0,0 +1,91 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+clocks {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+        osc: oscillator {
+                compatible = "fixed-clock";
+                #clock-cells = <1>;
+                clock-frequency = <25000000>;
+        };
+        apb_clk: apb_clk {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <1000000000>;
+        };
+        periph_clk: periph_clk {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <500000000>;
+        };
+        sdio_clk: lcpll_ch2 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <200000000>;
+        };
+        axi81_clk: axi81_clk {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <100000000>;
+        };
+        keypad_clk: keypad_clk {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <31806>;
+        };
+        adc_clk: adc_clk {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <1562500>;
+        };
+        pwm_clk: pwm_clk {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <1000000>;
+        };
+        lcd_clk: mipipll_ch1 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <100000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
new file mode 100644
index 000000000000..5126f9e77a98
--- /dev/null
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -0,0 +1,140 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "skeleton.dtsi"
+/ {
+        compatible = "brcm,cygnus";
+        model = "Broadcom Cygnus SoC";
+        interrupt-parent = <&gic>;
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
+                        reg = <0x0>;
+                };
+        };
+        /include/ "bcm-cygnus-clock.dtsi"
+        amba {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "arm,amba-bus", "simple-bus";
+                interrupt-parent = <&gic>;
+                ranges;
+                wdt@18009000 {
+                         compatible = "arm,sp805" , "arm,primecell";
+                         reg = <0x18009000 0x1000>;
+                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+                         clocks = <&axi81_clk>;
+                         clock-names = "apb_pclk";
+                };
+        };
+        uart0: serial@18020000 {
+                compatible = "snps,dw-apb-uart";
+                reg = <0x18020000 0x100>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+                interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&axi81_clk>;
+                clock-frequency = <100000000>;
+                status = "disabled";
+        };
+        uart1: serial@18021000 {
+                compatible = "snps,dw-apb-uart";
+                reg = <0x18021000 0x100>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+                interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&axi81_clk>;
+                clock-frequency = <100000000>;
+                status = "disabled";
+        };
+        uart2: serial@18022000 {
+                compatible = "snps,dw-apb-uart";
+                reg = <0x18020000 0x100>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+                interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&axi81_clk>;
+                clock-frequency = <100000000>;
+                status = "disabled";
+        };
+        uart3: serial@18023000 {
+                compatible = "snps,dw-apb-uart";
+                reg = <0x18023000 0x100>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+                interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&axi81_clk>;
+                clock-frequency = <100000000>;
+                status = "disabled";
+        };
+        gic: interrupt-controller@19021000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0x19021000 0x1000>,
+                      <0x19020100 0x100>;
+        };
+        L2: l2-cache {
+                compatible = "arm,pl310-cache";
+                reg = <0x19022000 0x1000>;
+                cache-unified;
+                cache-level = <2>;
+        };
+        timer@19020200 {
+                compatible = "arm,cortex-a9-global-timer";
+                reg = <0x19020200 0x100>;
+                interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&periph_clk>;
+        };
+};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
new file mode 100644
index 000000000000..e479515099c3
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
@@ -0,0 +1,30 @@
+/dts-v1/;
+/include/ "bcm2835-rpi.dtsi"
+/ {
+        compatible = "raspberrypi,model-b-plus", "brcm,bcm2835";
+        model = "Raspberry Pi Model B+";
+        leds {
+                act {
+                        gpios = <&gpio 47 0>;
+                };
+                pwr {
+                        label = "PWR";
+                        gpios = <&gpio 35 0>;
+                        default-state = "keep";
+                        linux,default-trigger = "default-on";
+                };
+        };
+};
+&gpio {
+        pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
+        /* I2S interface */
+        i2s_alt0: i2s_alt0 {
+                brcm,pins = <18 19 20 21>;
+                brcm,function = <4>; /* alt0 */
+        };
+};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index 58a0d60b95f1..bafa46fc226a 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -1,63 +1,23 @@
 /dts-v1/;
-/include/ "bcm2835.dtsi"
+/include/ "bcm2835-rpi.dtsi"
 / {
        compatible = "raspberrypi,model-b", "brcm,bcm2835";
        model = "Raspberry Pi Model B";
-        memory {
-                reg = <0 0x10000000>;
-        };
        leds {
-                compatible = "gpio-leds";
                act {
-                        label = "ACT";
                        gpios = <&gpio 16 1>;
-                        default-state = "keep";
-                        linux,default-trigger = "heartbeat";
                };
        };
 };
 &gpio {
-        pinctrl-names = "default";
+        pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
-        pinctrl-0 = <&gpioout &alt0 &alt2 &alt3>;
-        gpioout: gpioout {
-                brcm,pins = <6>;
-                brcm,function = <1>; /* GPIO out */
-        };
-        alt0: alt0 {
-                brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>;
-                brcm,function = <4>; /* alt0 */
-        };
-        alt3: alt3 {
-                brcm,pins = <48 49 50 51 52 53>;
-                brcm,function = <7>; /* alt3 */
-        };
        /* I2S interface */
-        alt2: alt2 {
+        i2s_alt2: i2s_alt2 {
                brcm,pins = <28 29 30 31>;
                brcm,function = <6>; /* alt2 */
        };
 };
-&i2c0 {
-        status = "okay";
-        clock-frequency = <100000>;
-};
-&i2c1 {
-        status = "okay";
-        clock-frequency = <100000>;
-};
-&sdhci {
-        status = "okay";
-        bus-width = <4>;
-};
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
new file mode 100644
index 000000000000..c7064487017d
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -0,0 +1,51 @@
+/include/ "bcm2835.dtsi"
+/ {
+        memory {
+                reg = <0 0x10000000>;
+        };
+        leds {
+                compatible = "gpio-leds";
+                act {
+                        label = "ACT";
+                        default-state = "keep";
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
+&gpio {
+        pinctrl-names = "default";
+        gpioout: gpioout {
+                brcm,pins = <6>;
+                brcm,function = <1>; /* GPIO out */
+        };
+        alt0: alt0 {
+                brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>;
+                brcm,function = <4>; /* alt0 */
+        };
+        alt3: alt3 {
+                brcm,pins = <48 49 50 51 52 53>;
+                brcm,function = <7>; /* alt3 */
+        };
+};
+&i2c0 {
+        status = "okay";
+        clock-frequency = <100000>;
+};
+&i2c1 {
+        status = "okay";
+        clock-frequency = <100000>;
+};
+&sdhci {
+        status = "okay";
+        bus-width = <4>;
+};
diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
new file mode 100644
index 000000000000..5fc0fae03092
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
@@ -0,0 +1,64 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ * DTS for Buffalo WZR-1750DHP
+ *
+ * Copyright (C) 2014 Rafał Miłecki <zajec5@gmail.com>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+/dts-v1/;
+#include "bcm4708.dtsi"
+/ {
+        compatible = "buffalo,wzr-1750dhp", "brcm,bcm4708";
+        model = "Buffalo WZR-1750DHP (BCM4708)";
+        chosen {
+                bootargs = "console=ttyS0,115200";
+        };
+        memory {
+                reg = <0x00000000 0x08000000>;
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                poll-interval = <200>;
+                restart {
+                        label = "Reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+                };
+                aoss {
+                        label = "AOSS";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>;
+                };
+                /* Commit mode set by switch? */
+                mode {
+                        label = "Mode";
+                        linux,code = <KEY_SETUP>;
+                        gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
+                };
+                /* Switch: AP mode */
+                sw_ap {
+                        label = "AP";
+                        linux,code = <BTN_0>;
+                        gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
+                };
+                eject {
+                        label = "USB eject";
+                        linux,code = <KEY_EJECTCD>;
+                        gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
index 3b5259de5a38..4ed7de1058b7 100644
--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
@@ -32,4 +32,63 @@
                        status = "okay";
                };
        };
+        leds {
+                compatible = "gpio-leds";
+                logo {
+                        label = "bcm53xx:white:logo";
+                        gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "default-on";
+                };
+                power0 {
+                        label = "bcm53xx:green:power";
+                        gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-off";
+                };
+                power1 {
+                        label = "bcm53xx:amber:power";
+                        gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-on";
+                };
+                usb {
+                        label = "bcm53xx:blue:usb";
+                        gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-off";
+                };
+                wireless {
+                        label = "bcm53xx:blue:wireless";
+                        gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-off";
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                poll-interval = <200>;
+                wps {
+                        label = "WPS";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
+                };
+                rfkill {
+                        label = "WiFi";
+                        linux,code = <KEY_RFKILL>;
+                        gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
+                };
+                restart {
+                        label = "Reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
new file mode 100644
index 000000000000..12fc2a01e6ab
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
@@ -0,0 +1,84 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ * DTS for Netgear R6300 V2
+ *
+ * Copyright (C) 2014 Rafał Miłecki <zajec5@gmail.com>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+/dts-v1/;
+#include "bcm4708.dtsi"
+/ {
+        compatible = "netgear,r6300v2", "brcm,bcm4708";
+        model = "Netgear R6300 V2 (BCM4708)";
+        chosen {
+                bootargs = "console=ttyS0,115200";
+        };
+        memory {
+                reg = <0x00000000 0x08000000>;
+        };
+        leds {
+                compatible = "gpio-leds";
+                logo {
+                        label = "bcm53xx:white:logo";
+                        gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "default-on";
+                };
+                power0 {
+                        label = "bcm53xx:green:power";
+                        gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-off";
+                };
+                power1 {
+                        label = "bcm53xx:amber:power";
+                        gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-on";
+                };
+                usb {
+                        label = "bcm53xx:blue:usb";
+                        gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-off";
+                };
+                wireless {
+                        label = "bcm53xx:blue:wireless";
+                        gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-off";
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                poll-interval = <200>;
+                wps {
+                        label = "WPS";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
+                };
+                rfkill {
+                        label = "WiFi";
+                        linux,code = <KEY_RFKILL>;
+                        gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
+                };
+                restart {
+                        label = "Reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
new file mode 100644
index 000000000000..fb76378bd511
--- /dev/null
+++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
@@ -0,0 +1,78 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ * DTS for Asus RT-N18U
+ *
+ * Copyright (C) 2014 Rafał Miłecki <zajec5@gmail.com>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+/dts-v1/;
+#include "bcm47081.dtsi"
+/ {
+        compatible = "asus,rt-n18u", "brcm,bcm47081", "brcm,bcm4708";
+        model = "Asus RT-N18U (BCM47081)";
+        chosen {
+                bootargs = "console=ttyS0,115200";
+        };
+        memory {
+                reg = <0x00000000 0x08000000>;
+        };
+        leds {
+                compatible = "gpio-leds";
+                power {
+                        label = "bcm53xx:blue:power";
+                        gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-on";
+                };
+                usb2 {
+                        label = "bcm53xx:blue:usb2";
+                        gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-off";
+                };
+                wan {
+                        label = "bcm53xx:blue:wan";
+                        gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-on";
+                };
+                lan {
+                        label = "bcm53xx:blue:lan";
+                        gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-on";
+                };
+                usb3 {
+                        label = "bcm53xx:blue:usb3";
+                        gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-off";
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                poll-interval = <200>;
+                restart {
+                        label = "Reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
+                };
+                wps {
+                        label = "WPS";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
new file mode 100644
index 000000000000..bbb414fbad65
--- /dev/null
+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
@@ -0,0 +1,57 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ * DTS for Buffalo WZR-600DHP2
+ *
+ * Copyright (C) 2014 Rafał Miłecki <zajec5@gmail.com>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+/dts-v1/;
+#include "bcm47081.dtsi"
+/ {
+        compatible = "buffalo,wzr-600dhp2", "brcm,bcm47081", "brcm,bcm4708";
+        model = "Buffalo WZR-600DHP2 (BCM47081)";
+        chosen {
+                bootargs = "console=ttyS0,115200";
+        };
+        memory {
+                reg = <0x00000000 0x08000000>;
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                poll-interval = <200>;
+                aoss {
+                        label = "AOSS";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
+                };
+                restart {
+                        label = "Reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+                };
+                /* Switch device mode? */
+                mode {
+                        label = "Mode";
+                        linux,code = <KEY_SETUP>;
+                        gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
+                };
+                eject {
+                        label = "USB eject";
+                        linux,code = <KEY_EJECTCD>;
+                        gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm47081.dtsi b/arch/arm/boot/dts/bcm47081.dtsi
new file mode 100644
index 000000000000..f720012ee5ed
--- /dev/null
+++ b/arch/arm/boot/dts/bcm47081.dtsi
@@ -0,0 +1,26 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ * DTS for BCM47081 SoC.
+ *
+ * Copyright © 2014 Rafał Miłecki <zajec5@gmail.com>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+#include "bcm5301x.dtsi"
+/ {
+        compatible = "brcm,bcm47081";
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
+                        reg = <0x0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 53c624f766b4..78aec6270c2f 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -8,6 +8,8 @@
 * Licensed under the GNU/GPL. See COPYING for details.
 */
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include "skeleton.dtsi"
@@ -92,4 +94,53 @@
                        clock-frequency = <400000000>;
                };
        };
+        axi@18000000 {
+                compatible = "brcm,bus-axi";
+                reg = <0x18000000 0x1000>;
+                ranges = <0x00000000 0x18000000 0x00100000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0x000fffff 0xffff>;
+                interrupt-map = 
+                        /* ChipCommon */
+                        <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+                        /* USB 2.0 Controller */
+                        <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+                        /* USB 3.0 Controller */
+                        <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+                        /* Ethernet Controller 0 */
+                        <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+                        /* Ethernet Controller 1 */
+                        <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+                        /* Ethernet Controller 2 */
+                        <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+                        /* Ethernet Controller 3 */
+                        <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+                        /* NAND Controller */
+                        <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                chipcommon: chipcommon@0 {
+                        reg = <0x00000000 0x1000>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts
new file mode 100644
index 000000000000..d2ee95280548
--- /dev/null
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -0,0 +1,53 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+#include "bcm-cygnus.dtsi"
+/ {
+        model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)";
+        compatible = "brcm,bcm11360", "brcm,cygnus";
+        aliases {
+                serial0 = &uart3;
+        };
+        chosen {
+                stdout-path = &uart3;
+                bootargs = "console=ttyS0,115200";
+        };
+        uart3: serial@18023000 {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/bcm911360k.dts b/arch/arm/boot/dts/bcm911360k.dts
new file mode 100644
index 000000000000..9658d4f62d59
--- /dev/null
+++ b/arch/arm/boot/dts/bcm911360k.dts
@@ -0,0 +1,53 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+#include "bcm-cygnus.dtsi"
+/ {
+        model = "Cygnus SVK (BCM911360K)";
+        compatible = "brcm,bcm11360", "brcm,cygnus";
+        aliases {
+                serial0 = &uart3;
+        };
+        chosen {
+                stdout-path = &uart3;
+                bootargs = "console=ttyS0,115200";
+        };
+        uart3: serial@18023000 {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
new file mode 100644
index 000000000000..f1bb36f3975c
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958300k.dts
@@ -0,0 +1,53 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+#include "bcm-cygnus.dtsi"
+/ {
+        model = "Cygnus SVK (BCM958300K)";
+        compatible = "brcm,bcm58300", "brcm,cygnus";
+        aliases {
+                serial0 = &uart3;
+        };
+        chosen {
+                stdout-path = &uart3;
+                bootargs = "console=ttyS0,115200";
+        };
+        uart3: serial@18023000 {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
index c72bfd468d10..86d85d8896a3 100644
--- a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
+++ b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
@@ -26,4 +26,20 @@
        };
 };
+&ahci { status = "okay"; };
+&eth1 { status = "okay"; };
+/* Unpopulated SATA plug on solder side */
+&sata0 { status = "okay"; };
+&sata_phy { status = "okay"; };
+/* Samsung M8G2FA 8GB eMMC */
+&sdhci2 {
+        non-removable;
+        bus-width = <8>;
+        status = "okay";
+};
 &uart0 { status = "okay"; };
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index 9d7c810ebd0b..015a06c67c91 100644
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -53,6 +53,35 @@
                ranges = <0 0xf7000000 0x1000000>;
+                sdhci0: sdhci@ab0000 {
+                        compatible = "mrvl,pxav3-mmc";
+                        reg = <0xab0000 0x200>;
+                        clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>;
+                        clock-names = "io", "core";
+                        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+                sdhci1: sdhci@ab0800 {
+                        compatible = "mrvl,pxav3-mmc";
+                        reg = <0xab0800 0x200>;
+                        clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>;
+                        clock-names = "io", "core";
+                        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+                sdhci2: sdhci@ab1000 {
+                        compatible = "mrvl,pxav3-mmc";
+                        reg = <0xab1000 0x200>;
+                        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
+                        clock-names = "io", "core";
+                        pinctrl-0 = <&emmc_pmux>;
+                        pinctrl-names = "default";
+                        status = "disabled";
+                };
                l2: l2-cache-controller@ac0000 {
                        compatible = "marvell,tauros3-cache", "arm,pl310-cache";
                        reg = <0xac0000 0x1000>;
@@ -79,11 +108,47 @@
                        clocks = <&chip CLKID_TWD>;
                };
+                eth1: ethernet@b90000 {
+                        compatible = "marvell,pxa168-eth";
+                        reg = <0xb90000 0x10000>;
+                        clocks = <&chip CLKID_GETH1>;
+                        interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+                        /* set by bootloader */
+                        local-mac-address = [00 00 00 00 00 00];
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        phy-connection-type = "mii";
+                        phy-handle = <&ethphy1>;
+                        status = "disabled";
+                        ethphy1: ethernet-phy@0 {
+                                reg = <0>;
+                        };
+                };
                cpu-ctrl@dd0000 {
                        compatible = "marvell,berlin-cpu-ctrl";
                        reg = <0xdd0000 0x10000>;
                };
+                eth0: ethernet@e50000 {
+                        compatible = "marvell,pxa168-eth";
+                        reg = <0xe50000 0x10000>;
+                        clocks = <&chip CLKID_GETH0>;
+                        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                        /* set by bootloader */
+                        local-mac-address = [00 00 00 00 00 00];
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        phy-connection-type = "mii";
+                        phy-handle = <&ethphy0>;
+                        status = "disabled";
+                        ethphy0: ethernet-phy@0 {
+                                reg = <0>;
+                        };
+                };
                apb@e80000 {
                        compatible = "simple-bus";
                        #address-cells = <1>;
@@ -246,12 +311,57 @@
                        };
                };
+                ahci: sata@e90000 {
+                        compatible = "marvell,berlin2-ahci", "generic-ahci";
+                        reg = <0xe90000 0x1000>;
+                        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&chip CLKID_SATA>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        sata0: sata-port@0 {
+                                reg = <0>;
+                                phys = <&sata_phy 0>;
+                                status = "disabled";
+                        };
+                        sata1: sata-port@1 {
+                                reg = <1>;
+                                phys = <&sata_phy 1>;
+                                status = "disabled";
+                        };
+                };
+                sata_phy: phy@e900a0 {
+                        compatible = "marvell,berlin2-sata-phy";
+                        reg = <0xe900a0 0x200>;
+                        clocks = <&chip CLKID_SATA>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        #phy-cells = <1>;
+                        status = "disabled";
+                        sata-phy@0 {
+                                reg = <0>;
+                        };
+                        sata-phy@1 {
+                                reg = <1>;
+                        };
+                };
                chip: chip-control@ea0000 {
                        compatible = "marvell,berlin2-chip-ctrl";
                        #clock-cells = <1>;
+                        #reset-cells = <2>;
                        reg = <0xea0000 0x400>;
                        clocks = <&refclk>;
                        clock-names = "refclk";
+                        emmc_pmux: emmc-pmux {
+                                groups = "G26";
+                                function = "emmc";
+                        };
                };
                apb@fc0000 {
diff --git a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
index bcd81ffc495d..30270be4d0c9 100644
--- a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
+++ b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
@@ -11,6 +11,7 @@
 /dts-v1/;
 #include "berlin2cd.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 / {
        model = "Google Chromecast";
@@ -24,6 +25,35 @@
                device_type = "memory";
                reg = <0x00000000 0x20000000>; /* 512 MB */
        };
+        leds {
+                compatible = "gpio-leds";
+                white {
+                        label = "white";
+                        gpios = <&portc 1 GPIO_ACTIVE_HIGH>;
+                        default-state = "keep";
+                };
+                red {
+                        label = "red";
+                        gpios = <&portc 2 GPIO_ACTIVE_HIGH>;
+                        default-state = "keep";
+                };
+        };
+};
+/*
+ * AzureWave AW-NH387 (Marvell 88W8787)
+ * 802.11b/g/n + Bluetooth 2.1
+ */
+&sdhci0 {
+        non-removable;
+        status = "okay";
 };
 &uart0 { status = "okay"; };
+&usb_phy1 { status = "okay"; };
+&usb1 { status = "okay"; };
diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index cc1df65da504..230df3b1770e 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -45,6 +45,15 @@
                ranges = <0 0xf7000000 0x1000000>;
+                sdhci0: sdhci@ab0000 {
+                        compatible = "mrvl,pxav3-mmc";
+                        reg = <0xab0000 0x200>;
+                        clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>;
+                        clock-names = "io", "core";
+                        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
                l2: l2-cache-controller@ac0000 {
                        compatible = "arm,pl310-cache";
                        reg = <0xac0000 0x1000>;
@@ -66,6 +75,58 @@
                        clocks = <&chip CLKID_TWD>;
                };
+                usb_phy0: usb-phy@b74000 {
+                        compatible = "marvell,berlin2cd-usb-phy";
+                        reg = <0xb74000 0x128>;
+                        #phy-cells = <0>;
+                        resets = <&chip 0x178 23>;
+                        status = "disabled";
+                };
+                usb_phy1: usb-phy@b78000 {
+                        compatible = "marvell,berlin2cd-usb-phy";
+                        reg = <0xb78000 0x128>;
+                        #phy-cells = <0>;
+                        resets = <&chip 0x178 24>;
+                        status = "disabled";
+                };
+                eth1: ethernet@b90000 {
+                        compatible = "marvell,pxa168-eth";
+                        reg = <0xb90000 0x10000>;
+                        clocks = <&chip CLKID_GETH1>;
+                        interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+                        /* set by bootloader */
+                        local-mac-address = [00 00 00 00 00 00];
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        phy-connection-type = "mii";
+                        phy-handle = <&ethphy1>;
+                        status = "disabled";
+                        ethphy1: ethernet-phy@0 {
+                                reg = <0>;
+                        };
+                };
+                eth0: ethernet@e50000 {
+                        compatible = "marvell,pxa168-eth";
+                        reg = <0xe50000 0x10000>;
+                        clocks = <&chip CLKID_GETH0>;
+                        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                        /* set by bootloader */
+                        local-mac-address = [00 00 00 00 00 00];
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        phy-connection-type = "mii";
+                        phy-handle = <&ethphy0>;
+                        status = "disabled";
+                        ethphy0: ethernet-phy@0 {
+                                reg = <0>;
+                        };
+                };
                apb@e80000 {
                        compatible = "simple-bus";
                        #address-cells = <1>;
@@ -231,6 +292,7 @@
                chip: chip-control@ea0000 {
                        compatible = "marvell,berlin2cd-chip-ctrl";
                        #clock-cells = <1>;
+                        #reset-cells = <2>;
                        reg = <0xea0000 0x400>;
                        clocks = <&refclk>;
                        clock-names = "refclk";
@@ -241,6 +303,26 @@
                        };
                };
+                usb0: usb@ed0000 {
+                        compatible = "chipidea,usb2";
+                        reg = <0xed0000 0x200>;
+                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&chip CLKID_USB0>;
+                        phys = <&usb_phy0>;
+                        phy-names = "usb-phy";
+                        status = "disabled";
+                };
+                usb1: usb@ee0000 {
+                        compatible = "chipidea,usb2";
+                        reg = <0xee0000 0x200>;
+                        interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&chip CLKID_USB1>;
+                        phys = <&usb_phy1>;
+                        phy-names = "usb-phy";
+                        status = "disabled";
+                };
                apb@fc0000 {
                        compatible = "simple-bus";
                        #address-cells = <1>;
diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
index ea1f99b8eed6..28e7e2060c33 100644
--- a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
+++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
@@ -7,6 +7,8 @@
 */
 /dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
 #include "berlin2q.dtsi"
 / {
@@ -21,6 +23,39 @@
        choosen {
                bootargs = "console=ttyS0,115200 earlyprintk";
        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_usb0_vbus: regulator@0 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb0_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&portb 8 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+                reg_usb1_vbus: regulator@1 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&portb 10 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+                reg_usb2_vbus: regulator@2 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb2_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&portb 12 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+        };
 };
 &sdhci1 {
@@ -46,6 +81,32 @@
        status = "okay";
 };
+&usb_phy0 {
+        status = "okay";
+};
+&usb_phy2 {
+        status = "okay";
+};
+&usb0 {
+        vbus-supply = <&reg_usb0_vbus>;
+        status = "okay";
+};
+&usb2 {
+        vbus-supply = <&reg_usb2_vbus>;
+        status = "okay";
+};
 &eth0 {
        status = "okay";
 };
+&sata0 {
+        status = "okay";
+};
+&sata_phy {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 891d56b03922..35253c947a7c 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -114,6 +114,40 @@
                        #interrupt-cells = <3>;
                };
+                usb_phy2: phy@a2f400 {
+                        compatible = "marvell,berlin2-usb-phy";
+                        reg = <0xa2f400 0x128>;
+                        #phy-cells = <0>;
+                        resets = <&chip 0x104 14>;
+                        status = "disabled";
+                };
+                usb2: usb@a30000 {
+                        compatible = "chipidea,usb2";
+                        reg = <0xa30000 0x10000>;
+                        interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&chip CLKID_USB2>;
+                        phys = <&usb_phy2>;
+                        phy-names = "usb-phy";
+                        status = "disabled";
+                };
+                usb_phy0: phy@b74000 {
+                        compatible = "marvell,berlin2-usb-phy";
+                        reg = <0xb74000 0x128>;
+                        #phy-cells = <0>;
+                        resets = <&chip 0x104 12>;
+                        status = "disabled";
+                };
+                usb_phy1: phy@b78000 {
+                        compatible = "marvell,berlin2-usb-phy";
+                        reg = <0xb78000 0x128>;
+                        #phy-cells = <0>;
+                        resets = <&chip 0x104 13>;
+                        status = "disabled";
+                };
                eth0: ethernet@b90000 {
                        compatible = "marvell,pxa168-eth";
                        reg = <0xb90000 0x10000>;
@@ -123,6 +157,7 @@
                        local-mac-address = [00 00 00 00 00 00];
                        #address-cells = <1>;
                        #size-cells = <0>;
+                        phy-connection-type = "mii";
                        phy-handle = <&ethphy0>;
                        status = "disabled";
@@ -255,7 +290,6 @@
                                reg = <0x2c14 0x14>;
                                clocks = <&chip CLKID_CFG>;
                                clock-names = "timer";
-                                status = "disabled";
                        };
                        timer2: timer@2c28 {
@@ -349,6 +383,7 @@
                chip: chip-control@ea0000 {
                        compatible = "marvell,berlin2q-chip-ctrl";
                        #clock-cells = <1>;
+                        #reset-cells = <2>;
                        reg = <0xea0000 0x400>, <0xdd0170 0x10>;
                        clocks = <&refclk>;
                        clock-names = "refclk";
@@ -364,6 +399,65 @@
                        };
                };
+                ahci: sata@e90000 {
+                        compatible = "marvell,berlin2q-ahci", "generic-ahci";
+                        reg = <0xe90000 0x1000>;
+                        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&chip CLKID_SATA>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        sata0: sata-port@0 {
+                                reg = <0>;
+                                phys = <&sata_phy 0>;
+                                status = "disabled";
+                        };
+                        sata1: sata-port@1 {
+                                reg = <1>;
+                                phys = <&sata_phy 1>;
+                                status = "disabled";
+                        };
+                };
+                sata_phy: phy@e900a0 {
+                        compatible = "marvell,berlin2q-sata-phy";
+                        reg = <0xe900a0 0x200>;
+                        clocks = <&chip CLKID_SATA>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        #phy-cells = <1>;
+                        status = "disabled";
+                        sata-phy@0 {
+                                reg = <0>;
+                        };
+                        sata-phy@1 {
+                                reg = <1>;
+                        };
+                };
+                usb0: usb@ed0000 {
+                        compatible = "chipidea,usb2";
+                        reg = <0xed0000 0x10000>;
+                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&chip CLKID_USB0>;
+                        phys = <&usb_phy0>;
+                        phy-names = "usb-phy";
+                        status = "disabled";
+                };
+                usb1: usb@ee0000 {
+                        compatible = "chipidea,usb2";
+                        reg = <0xee0000 0x10000>;
+                        interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&chip CLKID_USB1>;
+                        phys = <&usb_phy1>;
+                        phy-names = "usb-phy";
+                        status = "disabled";
+                };
                apb@fc0000 {
                        compatible = "simple-bus";
                        #address-cells = <1>;
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index c6ce6258434f..736092b1a535 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -171,6 +171,101 @@
                        0xd0    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_be0n_cle */
                >;
        };
+        cpsw_default: cpsw_default {
+                pinctrl-single,pins = <
+                        /* Slave 1 */
+                        0x250 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txc.rgmii0_txc */
+                        0x254 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txctl.rgmii0_txctl */
+                        0x258 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_td3.rgmii0_txd3 */
+                        0x25c (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txd2.rgmii0_txd2 */
+                        0x260 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txd1.rgmii0_txd1 */
+                        0x264 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txd0.rgmii0_txd0 */
+                        0x268 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxc.rgmii0_rxc */
+                        0x26c (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxctl.rgmii0_rxctl */
+                        0x270 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd3.rgmii0_rxd3 */
+                        0x274 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd2.rgmii0_rxd2 */
+                        0x278 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd1.rgmii0_rxd1 */
+                        0x27c (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd0.rgmii0_rxd0 */
+                        /* Slave 2 */
+                        0x198 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d12.rgmii1_txc */
+                        0x19c (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d13.rgmii1_tctl */
+                        0x1a0 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d14.rgmii1_td3 */
+                        0x1a4 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d15.rgmii1_td2 */
+                        0x1a8 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d16.rgmii1_td1 */
+                        0x1ac (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d17.rgmii1_td0 */
+                        0x1b0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d18.rgmii1_rclk */
+                        0x1b4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d19.rgmii1_rctl */
+                        0x1b8 (PIN_INPUT | MUX_MODE3)   /* vin2a_d20.rgmii1_rd3 */
+                        0x1bc (PIN_INPUT | MUX_MODE3)   /* vin2a_d21.rgmii1_rd2 */
+                        0x1c0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d22.rgmii1_rd1 */
+                        0x1c4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d23.rgmii1_rd0 */
+                >;
+        };
+        cpsw_sleep: cpsw_sleep {
+                pinctrl-single,pins = <
+                        /* Slave 1 */
+                        0x250 (MUX_MODE15)
+                        0x254 (MUX_MODE15)
+                        0x258 (MUX_MODE15)
+                        0x25c (MUX_MODE15)
+                        0x260 (MUX_MODE15)
+                        0x264 (MUX_MODE15)
+                        0x268 (MUX_MODE15)
+                        0x26c (MUX_MODE15)
+                        0x270 (MUX_MODE15)
+                        0x274 (MUX_MODE15)
+                        0x278 (MUX_MODE15)
+                        0x27c (MUX_MODE15)
+                        /* Slave 2 */
+                        0x198 (MUX_MODE15)
+                        0x19c (MUX_MODE15)
+                        0x1a0 (MUX_MODE15)
+                        0x1a4 (MUX_MODE15)
+                        0x1a8 (MUX_MODE15)
+                        0x1ac (MUX_MODE15)
+                        0x1b0 (MUX_MODE15)
+                        0x1b4 (MUX_MODE15)
+                        0x1b8 (MUX_MODE15)
+                        0x1bc (MUX_MODE15)
+                        0x1c0 (MUX_MODE15)
+                        0x1c4 (MUX_MODE15)
+                >;
+        };
+        davinci_mdio_default: davinci_mdio_default {
+                pinctrl-single,pins = <
+                        0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* mdio_d.mdio_d */
+                        0x240 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mdio_clk.mdio_clk */
+                >;
+        };
+        davinci_mdio_sleep: davinci_mdio_sleep {
+                pinctrl-single,pins = <
+                        0x23c (MUX_MODE15)
+                        0x240 (MUX_MODE15)
+                >;
+        };
+        dcan1_pins_default: dcan1_pins_default {
+                pinctrl-single,pins = <
+                        0x3d0   (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */
+                        0x3d4   (MUX_MODE15)            /* dcan1_rx.off */
+                        0x418   (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */
+                >;
+        };
+        dcan1_pins_sleep: dcan1_pins_sleep {
+                pinctrl-single,pins = <
+                        0x3d0   (MUX_MODE15)    /* dcan1_tx.off */
+                        0x3d4   (MUX_MODE15)    /* dcan1_rx.off */
+                        0x418   (MUX_MODE15)    /* wakeup0.off */
+                >;
+        };
 };
 &i2c1 {
@@ -201,6 +296,7 @@
                                        regulator-name = "smps45";
                                        regulator-min-microvolt = < 850000>;
                                        regulator-max-microvolt = <1150000>;
+                                        regulator-always-on;
                                        regulator-boot-on;
                                };
@@ -209,6 +305,7 @@
                                        regulator-name = "smps6";
                                        regulator-min-microvolt = <850000>;
                                        regulator-max-microvolt = <12500000>;
+                                        regulator-always-on;
                                        regulator-boot-on;
                                };
@@ -226,6 +323,7 @@
                                        regulator-name = "smps8";
                                        regulator-min-microvolt = < 850000>;
                                        regulator-max-microvolt = <1250000>;
+                                        regulator-always-on;
                                        regulator-boot-on;
                                };
@@ -252,6 +350,7 @@
                                        regulator-name = "ldo2";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
                                        regulator-boot-on;
                                };
@@ -269,6 +368,7 @@
                                        regulator-name = "ldo9";
                                        regulator-min-microvolt = <1050000>;
                                        regulator-max-microvolt = <1050000>;
+                                        regulator-always-on;
                                        regulator-boot-on;
                                };
@@ -528,3 +628,36 @@
        ti,no-reset-on-init;
        ti,no-idle-on-init;
 };
+&mac {
+        status = "okay";
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&cpsw_default>;
+        pinctrl-1 = <&cpsw_sleep>;
+        dual_emac;
+};
+&cpsw_emac0 {
+        phy_id = <&davinci_mdio>, <2>;
+        phy-mode = "rgmii";
+        dual_emac_res_vlan = <1>;
+};
+&cpsw_emac1 {
+        phy_id = <&davinci_mdio>, <3>;
+        phy-mode = "rgmii";
+        dual_emac_res_vlan = <2>;
+};
+&davinci_mdio {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&davinci_mdio_default>;
+        pinctrl-1 = <&davinci_mdio_sleep>;
+};
+&dcan1 {
+        status = "ok";
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&dcan1_pins_default>;
+        pinctrl-1 = <&dcan1_pins_sleep>;
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 9cc98436a982..63bf99be1762 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -34,6 +34,14 @@
                serial3 = &uart4;
                serial4 = &uart5;
                serial5 = &uart6;
+                serial6 = &uart7;
+                serial7 = &uart8;
+                serial8 = &uart9;
+                serial9 = &uart10;
+                ethernet0 = &cpsw_emac0;
+                ethernet1 = &cpsw_emac1;
+                d_can0 = &dcan1;
+                d_can1 = &dcan2;
        };
        timer {
@@ -201,6 +209,11 @@
                        ti,hwmods = "counter_32k";
                };
+                dra7_ctrl_core: ctrl_core@4a002000 {
+                        compatible = "syscon";
+                        reg = <0x4a002000 0x6d0>;
+                };
                dra7_ctrl_general: tisyscon@4a002e00 {
                        compatible = "syscon";
                        reg = <0x4a002e00 0x7c>;
@@ -335,6 +348,8 @@
                        ti,hwmods = "uart1";
                        clock-frequency = <48000000>;
                        status = "disabled";
+                        dmas = <&sdma 49>, <&sdma 50>;
+                        dma-names = "tx", "rx";
                };
                uart2: serial@4806c000 {
@@ -344,6 +359,8 @@
                        ti,hwmods = "uart2";
                        clock-frequency = <48000000>;
                        status = "disabled";
+                        dmas = <&sdma 51>, <&sdma 52>;
+                        dma-names = "tx", "rx";
                };
                uart3: serial@48020000 {
@@ -353,6 +370,8 @@
                        ti,hwmods = "uart3";
                        clock-frequency = <48000000>;
                        status = "disabled";
+                        dmas = <&sdma 53>, <&sdma 54>;
+                        dma-names = "tx", "rx";
                };
                uart4: serial@4806e000 {
@@ -362,6 +381,8 @@
                        ti,hwmods = "uart4";
                        clock-frequency = <48000000>;
                        status = "disabled";
+                        dmas = <&sdma 55>, <&sdma 56>;
+                        dma-names = "tx", "rx";
                };
                uart5: serial@48066000 {
@@ -371,6 +392,8 @@
                        ti,hwmods = "uart5";
                        clock-frequency = <48000000>;
                        status = "disabled";
+                        dmas = <&sdma 63>, <&sdma 64>;
+                        dma-names = "tx", "rx";
                };
                uart6: serial@48068000 {
@@ -380,6 +403,8 @@
                        ti,hwmods = "uart6";
                        clock-frequency = <48000000>;
                        status = "disabled";
+                        dmas = <&sdma 79>, <&sdma 80>;
+                        dma-names = "tx", "rx";
                };
                uart7: serial@48420000 {
@@ -421,7 +446,11 @@
                mailbox1: mailbox@4a0f4000 {
                        compatible = "ti,omap4-mailbox";
                        reg = <0x4a0f4000 0x200>;
+                        interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mailbox1";
+                        #mbox-cells = <1>;
                        ti,mbox-num-users = <3>;
                        ti,mbox-num-fifos = <8>;
                        status = "disabled";
@@ -430,7 +459,12 @@
                mailbox2: mailbox@4883a000 {
                        compatible = "ti,omap4-mailbox";
                        reg = <0x4883a000 0x200>;
+                        interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mailbox2";
+                        #mbox-cells = <1>;
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <12>;
                        status = "disabled";
@@ -439,7 +473,12 @@
                mailbox3: mailbox@4883c000 {
                        compatible = "ti,omap4-mailbox";
                        reg = <0x4883c000 0x200>;
+                        interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mailbox3";
+                        #mbox-cells = <1>;
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <12>;
                        status = "disabled";
@@ -448,7 +487,12 @@
                mailbox4: mailbox@4883e000 {
                        compatible = "ti,omap4-mailbox";
                        reg = <0x4883e000 0x200>;
+                        interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mailbox4";
+                        #mbox-cells = <1>;
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <12>;
                        status = "disabled";
@@ -457,7 +501,12 @@
                mailbox5: mailbox@48840000 {
                        compatible = "ti,omap4-mailbox";
                        reg = <0x48840000 0x200>;
+                        interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mailbox5";
+                        #mbox-cells = <1>;
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <12>;
                        status = "disabled";
@@ -466,7 +515,12 @@
                mailbox6: mailbox@48842000 {
                        compatible = "ti,omap4-mailbox";
                        reg = <0x48842000 0x200>;
+                        interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mailbox6";
+                        #mbox-cells = <1>;
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <12>;
                        status = "disabled";
@@ -475,7 +529,12 @@
                mailbox7: mailbox@48844000 {
                        compatible = "ti,omap4-mailbox";
                        reg = <0x48844000 0x200>;
+                        interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mailbox7";
+                        #mbox-cells = <1>;
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <12>;
                        status = "disabled";
@@ -484,7 +543,12 @@
                mailbox8: mailbox@48846000 {
                        compatible = "ti,omap4-mailbox";
                        reg = <0x48846000 0x200>;
+                        interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mailbox8";
+                        #mbox-cells = <1>;
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <12>;
                        status = "disabled";
@@ -493,7 +557,12 @@
                mailbox9: mailbox@4885e000 {
                        compatible = "ti,omap4-mailbox";
                        reg = <0x4885e000 0x200>;
+                        interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mailbox9";
+                        #mbox-cells = <1>;
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <12>;
                        status = "disabled";
@@ -502,7 +571,12 @@
                mailbox10: mailbox@48860000 {
                        compatible = "ti,omap4-mailbox";
                        reg = <0x48860000 0x200>;
+                        interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mailbox10";
+                        #mbox-cells = <1>;
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <12>;
                        status = "disabled";
@@ -511,7 +585,12 @@
                mailbox11: mailbox@48862000 {
                        compatible = "ti,omap4-mailbox";
                        reg = <0x48862000 0x200>;
+                        interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mailbox11";
+                        #mbox-cells = <1>;
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <12>;
                        status = "disabled";
@@ -520,7 +599,12 @@
                mailbox12: mailbox@48864000 {
                        compatible = "ti,omap4-mailbox";
                        reg = <0x48864000 0x200>;
+                        interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mailbox12";
+                        #mbox-cells = <1>;
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <12>;
                        status = "disabled";
@@ -529,7 +613,12 @@
                mailbox13: mailbox@48802000 {
                        compatible = "ti,omap4-mailbox";
                        reg = <0x48802000 0x200>;
+                        interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mailbox13";
+                        #mbox-cells = <1>;
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <12>;
                        status = "disabled";
@@ -1075,6 +1164,15 @@
                        status = "disabled";
                };
+                rtc@48838000 {
+                        compatible = "ti,am3352-rtc";
+                        reg = <0x48838000 0x100>;
+                        interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
+                        ti,hwmods = "rtcss";
+                        clocks = <&sys_32k_ck>;
+                };
                omap_control_usb2phy1: control-phy@4a002300 {
                        compatible = "ti,control-phy-usb2";
                        reg = <0x4a002300 0x4>;
@@ -1141,7 +1239,7 @@
                        };
                };
-                omap_dwc3_1@48880000 {
+                omap_dwc3_1: omap_dwc3_1@48880000 {
                        compatible = "ti,dwc3";
                        ti,hwmods = "usb_otg_ss1";
                        reg = <0x48880000 0x10000>;
@@ -1162,7 +1260,7 @@
                        };
                };
-                omap_dwc3_2@488c0000 {
+                omap_dwc3_2: omap_dwc3_2@488c0000 {
                        compatible = "ti,dwc3";
                        ti,hwmods = "usb_otg_ss2";
                        reg = <0x488c0000 0x10000>;
@@ -1184,7 +1282,7 @@
                };
                /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
-                omap_dwc3_3@48900000 {
+                omap_dwc3_3: omap_dwc3_3@48900000 {
                        compatible = "ti,dwc3";
                        ti,hwmods = "usb_otg_ss3";
                        reg = <0x48900000 0x10000>;
@@ -1204,26 +1302,6 @@
                        };
                };
-                omap_dwc3_4@48940000 {
-                        compatible = "ti,dwc3";
-                        ti,hwmods = "usb_otg_ss4";
-                        reg = <0x48940000 0x10000>;
-                        interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        utmi-mode = <2>;
-                        ranges;
-                        status = "disabled";
-                        usb4: usb@48950000 {
-                                compatible = "snps,dwc3";
-                                reg = <0x48950000 0x17000>;
-                                interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
-                                tx-fifo-resize;
-                                maximum-speed = "high-speed";
-                                dr_mode = "otg";
-                        };
-                };
                elm: elm@48078000 {
                        compatible = "ti,am3352-elm";
                        reg = <0x48078000 0xfc0>;      /* device IO registers */
@@ -1265,6 +1343,84 @@
                        ti,irqs-skip = <10 133 139 140>;
                        ti,irqs-safe-map = <0>;
                };
+                mac: ethernet@4a100000 {
+                        compatible = "ti,cpsw";
+                        ti,hwmods = "gmac";
+                        clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
+                        clock-names = "fck", "cpts";
+                        cpdma_channels = <8>;
+                        ale_entries = <1024>;
+                        bd_ram_size = <0x2000>;
+                        no_bd_ram = <0>;
+                        rx_descs = <64>;
+                        mac_control = <0x20>;
+                        slaves = <2>;
+                        active_slave = <0>;
+                        cpts_clock_mult = <0x80000000>;
+                        cpts_clock_shift = <29>;
+                        reg = <0x48484000 0x1000
+                               0x48485200 0x2E00>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        /*
+                         * rx_thresh_pend
+                         * rx_pend
+                         * tx_pend
+                         * misc_pend
+                         */
+                        interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
+                        ranges;
+                        status = "disabled";
+                        davinci_mdio: mdio@48485000 {
+                                compatible = "ti,davinci_mdio";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                ti,hwmods = "davinci_mdio";
+                                bus_freq = <1000000>;
+                                reg = <0x48485000 0x100>;
+                        };
+                        cpsw_emac0: slave@48480200 {
+                                /* Filled in by U-Boot */
+                                mac-address = [ 00 00 00 00 00 00 ];
+                        };
+                        cpsw_emac1: slave@48480300 {
+                                /* Filled in by U-Boot */
+                                mac-address = [ 00 00 00 00 00 00 ];
+                        };
+                        phy_sel: cpsw-phy-sel@4a002554 {
+                                compatible = "ti,dra7xx-cpsw-phy-sel";
+                                reg= <0x4a002554 0x4>;
+                                reg-names = "gmii-sel";
+                        };
+                };
+                dcan1: can@481cc000 {
+                        compatible = "ti,dra7-d_can";
+                        ti,hwmods = "dcan1";
+                        reg = <0x4ae3c000 0x2000>;
+                        syscon-raminit = <&dra7_ctrl_core 0x558 0>;
+                        interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&dcan1_sys_clk_mux>;
+                        status = "disabled";
+                };
+                dcan2: can@481d0000 {
+                        compatible = "ti,dra7-d_can";
+                        ti,hwmods = "dcan2";
+                        reg = <0x48480000 0x2000>;
+                        syscon-raminit = <&dra7_ctrl_core 0x558 1>;
+                        interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&sys_clkin1>;
+                        status = "disabled";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 41074288adfa..afc74fd4bb5e 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -17,6 +17,13 @@
                device_type = "memory";
                reg = <0x80000000 0x40000000>; /* 1024 MB */
        };
+        evm_3v3: fixedregulator-evm_3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "evm_3v3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
 };
 &dra7_pmx_core {
@@ -26,6 +33,94 @@
                        0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
                >;
        };
+        nand_default: nand_default {
+                pinctrl-single,pins = <
+                        0x0     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad0 */
+                        0x4     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad1 */
+                        0x8     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad2 */
+                        0xc     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad3 */
+                        0x10    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad4 */
+                        0x14    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad5 */
+                        0x18    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad6 */
+                        0x1c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad7 */
+                        0x20    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad8 */
+                        0x24    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad9 */
+                        0x28    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad10 */
+                        0x2c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad11 */
+                        0x30    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad12 */
+                        0x34    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad13 */
+                        0x38    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad14 */
+                        0x3c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad15 */
+                        0xb4    (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
+                        0xc4    (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
+                        0xcc    (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
+                        0xc8    (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
+                        0xd0    (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
+                        0xd8    (PIN_INPUT  | MUX_MODE0) /* gpmc_wait0 */
+                >;
+        };
+        usb1_pins: pinmux_usb1_pins {
+                pinctrl-single,pins = <
+                        0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
+                >;
+        };
+        usb2_pins: pinmux_usb2_pins {
+                pinctrl-single,pins = <
+                        0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
+                >;
+        };
+        tps65917_pins_default: tps65917_pins_default {
+                pinctrl-single,pins = <
+                        0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
+                >;
+        };
+        mmc1_pins_default: mmc1_pins_default {
+                pinctrl-single,pins = <
+                        0x36c (PIN_INPUT | MUX_MODE14)  /* mmc1sdcd.gpio219 */
+                        0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+                        0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+                        0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+                        0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+                        0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+                        0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+                >;
+        };
+        mmc2_pins_default: mmc2_pins_default {
+                pinctrl-single,pins = <
+                        0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+                        0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+                        0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+                        0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+                        0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+                        0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+                        0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+                        0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+                        0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+                        0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+                >;
+        };
+        dcan1_pins_default: dcan1_pins_default {
+                pinctrl-single,pins = <
+                        0x3d0   (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */
+                        0x3d4   (MUX_MODE15)            /* dcan1_rx.off */
+                        0x418   (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */
+                >;
+        };
+        dcan1_pins_sleep: dcan1_pins_sleep {
+                pinctrl-single,pins = <
+                        0x3d0   (MUX_MODE15)    /* dcan1_tx.off */
+                        0x3d4   (MUX_MODE15)    /* dcan1_rx.off */
+                        0x418   (MUX_MODE15)    /* wakeup0.off */
+                >;
+        };
 };
 &i2c1 {
@@ -38,6 +133,9 @@
                compatible = "ti,tps65917";
                reg = <0x58>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&tps65917_pins_default>;
                interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
                interrupt-parent = <&gic>;
                interrupt-controller;
@@ -136,9 +234,230 @@
                                };
                        };
                };
+                tps65917_power_button {
+                        compatible = "ti,palmas-pwrbutton";
+                        interrupt-parent = <&tps65917>;
+                        interrupts = <1 IRQ_TYPE_NONE>;
+                        wakeup-source;
+                        ti,palmas-long-press-seconds = <6>;
+                };
        };
 };
 &uart1 {
        status = "okay";
 };
+&elm {
+        status = "okay";
+};
+&gpmc {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&nand_default>;
+        ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
+        nand@0,0 {
+                /* To use NAND, DIP switch SW5 must be set like so:
+                 * SW5.1 (NAND_SELn) = ON (LOW)
+                 * SW5.9 (GPMC_WPN) = OFF (HIGH)
+                 */
+                reg = <0 0 4>;          /* device IO registers */
+                ti,nand-ecc-opt = "bch8";
+                ti,elm-id = <&elm>;
+                nand-bus-width = <16>;
+                gpmc,device-width = <2>;
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <80>;
+                gpmc,cs-wr-off-ns = <80>;
+                gpmc,adv-on-ns = <0>;
+                gpmc,adv-rd-off-ns = <60>;
+                gpmc,adv-wr-off-ns = <60>;
+                gpmc,we-on-ns = <10>;
+                gpmc,we-off-ns = <50>;
+                gpmc,oe-on-ns = <4>;
+                gpmc,oe-off-ns = <40>;
+                gpmc,access-ns = <40>;
+                gpmc,wr-access-ns = <80>;
+                gpmc,rd-cycle-ns = <80>;
+                gpmc,wr-cycle-ns = <80>;
+                gpmc,bus-turnaround-ns = <0>;
+                gpmc,cycle2cycle-delay-ns = <0>;
+                gpmc,clk-activation-ns = <0>;
+                gpmc,wait-monitoring-ns = <0>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+                /* MTD partition table */
+                /* All SPL-* partitions are sized to minimal length
+                 * which can be independently programmable. For
+                 * NAND flash this is equal to size of erase-block */
+                #address-cells = <1>;
+                #size-cells = <1>;
+                partition@0 {
+                        label = "NAND.SPL";
+                        reg = <0x00000000 0x000020000>;
+                };
+                partition@1 {
+                        label = "NAND.SPL.backup1";
+                        reg = <0x00020000 0x00020000>;
+                };
+                partition@2 {
+                        label = "NAND.SPL.backup2";
+                        reg = <0x00040000 0x00020000>;
+                };
+                partition@3 {
+                        label = "NAND.SPL.backup3";
+                        reg = <0x00060000 0x00020000>;
+                };
+                partition@4 {
+                        label = "NAND.u-boot-spl-os";
+                        reg = <0x00080000 0x00040000>;
+                };
+                partition@5 {
+                        label = "NAND.u-boot";
+                        reg = <0x000c0000 0x00100000>;
+                };
+                partition@6 {
+                        label = "NAND.u-boot-env";
+                        reg = <0x001c0000 0x00020000>;
+                };
+                partition@7 {
+                        label = "NAND.u-boot-env.backup1";
+                        reg = <0x001e0000 0x00020000>;
+                };
+                partition@8 {
+                        label = "NAND.kernel";
+                        reg = <0x00200000 0x00800000>;
+                };
+                partition@9 {
+                        label = "NAND.file-system";
+                        reg = <0x00a00000 0x0f600000>;
+                };
+        };
+};
+&usb2_phy1 {
+        phy-supply = <&ldo4_reg>;
+};
+&usb2_phy2 {
+        phy-supply = <&ldo4_reg>;
+};
+&usb1 {
+        dr_mode = "peripheral";
+        pinctrl-names = "default";
+        pinctrl-0 = <&usb1_pins>;
+};
+&usb2 {
+        dr_mode = "host";
+        pinctrl-names = "default";
+        pinctrl-0 = <&usb2_pins>;
+};
+&mmc1 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins_default>;
+        vmmc-supply = <&ldo1_reg>;
+        bus-width = <4>;
+        /*
+         * SDCD signal is not being used here - using the fact that GPIO mode
+         * is a viable alternative
+         */
+        cd-gpios = <&gpio6 27 0>;
+};
+&mmc2 {
+        /* SW5-3 in ON position */
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins_default>;
+        vmmc-supply = <&evm_3v3>;
+        bus-width = <8>;
+        ti,non-removable;
+};
+&dra7_pmx_core {
+        cpsw_default: cpsw_default {
+                pinctrl-single,pins = <
+                        /* Slave 2 */
+                        0x198 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d12.rgmii1_txc */
+                        0x19c (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d13.rgmii1_tctl */
+                        0x1a0 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d14.rgmii1_td3 */
+                        0x1a4 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d15.rgmii1_td2 */
+                        0x1a8 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d16.rgmii1_td1 */
+                        0x1ac (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d17.rgmii1_td0 */
+                        0x1b0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d18.rgmii1_rclk */
+                        0x1b4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d19.rgmii1_rctl */
+                        0x1b8 (PIN_INPUT | MUX_MODE3)   /* vin2a_d20.rgmii1_rd3 */
+                        0x1bc (PIN_INPUT | MUX_MODE3)   /* vin2a_d21.rgmii1_rd2 */
+                        0x1c0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d22.rgmii1_rd1 */
+                        0x1c4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d23.rgmii1_rd0 */
+                >;
+        };
+        cpsw_sleep: cpsw_sleep {
+                pinctrl-single,pins = <
+                        /* Slave 2 */
+                        0x198 (MUX_MODE15)
+                        0x19c (MUX_MODE15)
+                        0x1a0 (MUX_MODE15)
+                        0x1a4 (MUX_MODE15)
+                        0x1a8 (MUX_MODE15)
+                        0x1ac (MUX_MODE15)
+                        0x1b0 (MUX_MODE15)
+                        0x1b4 (MUX_MODE15)
+                        0x1b8 (MUX_MODE15)
+                        0x1bc (MUX_MODE15)
+                        0x1c0 (MUX_MODE15)
+                        0x1c4 (MUX_MODE15)
+                >;
+        };
+        davinci_mdio_default: davinci_mdio_default {
+                pinctrl-single,pins = <
+                        /* MDIO */
+                        0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* mdio_d.mdio_d */
+                        0x240 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mdio_clk.mdio_clk */
+                >;
+        };
+        davinci_mdio_sleep: davinci_mdio_sleep {
+                pinctrl-single,pins = <
+                        0x23c (MUX_MODE15)
+                        0x240 (MUX_MODE15)
+                >;
+        };
+};
+&mac {
+        status = "okay";
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&cpsw_default>;
+        pinctrl-1 = <&cpsw_sleep>;
+};
+&cpsw_emac1 {
+        phy_id = <&davinci_mdio>, <3>;
+        phy-mode = "rgmii";
+};
+&davinci_mdio {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&davinci_mdio_default>;
+        pinctrl-1 = <&davinci_mdio_sleep>;
+        active_slave = <1>;
+};
+&dcan1 {
+        status = "ok";
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&dcan1_pins_default>;
+        pinctrl-1 = <&dcan1_pins_sleep>;
+};
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 3be544c4891f..10173fab1a15 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -44,4 +44,26 @@
                interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>;
        };
+        ocp {
+                omap_dwc3_4: omap_dwc3_4@48940000 {
+                        compatible = "ti,dwc3";
+                        ti,hwmods = "usb_otg_ss4";
+                        reg = <0x48940000 0x10000>;
+                        interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        utmi-mode = <2>;
+                        ranges;
+                        status = "disabled";
+                        usb4: usb@48950000 {
+                                compatible = "snps,dwc3";
+                                reg = <0x48950000 0x17000>;
+                                interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+                                tx-fifo-resize;
+                                maximum-speed = "high-speed";
+                                dr_mode = "otg";
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
index 50ccd151091e..667d323e80a3 100644
--- a/arch/arm/boot/dts/emev2-kzm9d.dts
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -25,37 +25,7 @@
        chosen {
                bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp";
-        };
+                stdout-path = &uart1;
-        reg_1p8v: regulator@0 {
-                compatible = "regulator-fixed";
-                regulator-name = "fixed-1.8V";
-                regulator-min-microvolt = <1800000>;
-                regulator-max-microvolt = <1800000>;
-                regulator-always-on;
-                regulator-boot-on;
-        };
-        reg_3p3v: regulator@1 {
-                compatible = "regulator-fixed";
-                regulator-name = "fixed-3.3V";
-                regulator-min-microvolt = <3300000>;
-                regulator-max-microvolt = <3300000>;
-                regulator-always-on;
-                regulator-boot-on;
-        };
-        lan9220@20000000 {
-                compatible = "smsc,lan9220", "smsc,lan9115";
-                reg = <0x20000000 0x10000>;
-                phy-mode = "mii";
-                interrupt-parent = <&gpio0>;
-                interrupts = <1 IRQ_TYPE_EDGE_RISING>;
-                reg-io-width = <4>;
-                smsc,irq-active-high;
-                smsc,irq-push-pull;
-                vddvario-supply = <&reg_1p8v>;
-                vdd33a-supply = <&reg_3p3v>;
        };
        gpio_keys {
@@ -92,4 +62,35 @@
                        gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
                };
        };
+        reg_1p8v: regulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-1.8V";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+        reg_3p3v: regulator@1 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+        lan9220@20000000 {
+                compatible = "smsc,lan9220", "smsc,lan9115";
+                reg = <0x20000000 0x10000>;
+                phy-mode = "mii";
+                interrupt-parent = <&gpio0>;
+                interrupts = <1 IRQ_TYPE_EDGE_RISING>;
+                reg-io-width = <4>;
+                smsc,irq-active-high;
+                smsc,irq-push-pull;
+                vddvario-supply = <&reg_1p8v>;
+                vdd33a-supply = <&reg_3p3v>;
+        };
 };
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
index 00eeed3721b6..cc7bfe0ba40a 100644
--- a/arch/arm/boot/dts/emev2.dtsi
+++ b/arch/arm/boot/dts/emev2.dtsi
@@ -55,7 +55,7 @@
                             <0 121 IRQ_TYPE_LEVEL_HIGH>;
        };
-        smu@e0110000 {
+        clocks@e0110000 {
                compatible = "renesas,emev2-smu";
                reg = <0xe0110000 0x10000>;
                #address-cells = <2>;
@@ -129,7 +129,7 @@
                };
        };
-        sti@e0180000 {
+        timer@e0180000 {
                compatible = "renesas,em-sti";
                reg = <0xe0180000 0x54>;
                interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
@@ -137,7 +137,7 @@
                clock-names = "sclk";
        };
-        uart@e1020000 {
+        uart0: serial@e1020000 {
                compatible = "renesas,em-uart";
                reg = <0xe1020000 0x38>;
                interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
@@ -145,7 +145,7 @@
                clock-names = "sclk";
        };
-        uart@e1030000 {
+        uart1: serial@e1030000 {
                compatible = "renesas,em-uart";
                reg = <0xe1030000 0x38>;
                interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
@@ -153,7 +153,7 @@
                clock-names = "sclk";
        };
-        uart@e1040000 {
+        uart2: serial@e1040000 {
                compatible = "renesas,em-uart";
                reg = <0xe1040000 0x38>;
                interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
@@ -161,7 +161,7 @@
                clock-names = "sclk";
        };
-        uart@e1050000 {
+        uart3: serial@e1050000 {
                compatible = "renesas,em-uart";
                reg = <0xe1050000 0x38>;
                interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts
new file mode 100644
index 000000000000..24822aa98057
--- /dev/null
+++ b/arch/arm/boot/dts/exynos3250-monk.dts
@@ -0,0 +1,579 @@
+/*
+ * Samsung's Exynos3250 based Monk board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Device tree source file for Samsung's Monk board which is based on
+ * Samsung Exynos3250 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "exynos3250.dtsi"
+#include <dt-bindings/input/input.h>
+/ {
+        model = "Samsung Monk board";
+        compatible = "samsung,monk", "samsung,exynos3250", "samsung,exynos3";
+        aliases {
+                i2c7 = &i2c_max77836;
+        };
+        memory {
+                reg =  <0x40000000 0x1ff00000>;
+        };
+        firmware@0205F000 {
+                compatible = "samsung,secure-firmware";
+                reg = <0x0205F000 0x1000>;
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                power_key {
+                        interrupt-parent = <&gpx2>;
+                        interrupts = <7 0>;
+                        gpios = <&gpx2 7 1>;
+                        linux,code = <KEY_POWER>;
+                        label = "power key";
+                        debounce-interval = <10>;
+                        gpio-key,wakeup;
+                };
+        };
+        vemmc_reg: voltage-regulator-0 {
+                compatible = "regulator-fixed";
+                regulator-name = "V_EMMC_2.8V-fixed";
+                regulator-min-microvolt = <2800000>;
+                regulator-max-microvolt = <2800000>;
+                gpio = <&gpk0 2 0>;
+                enable-active-high;
+        };
+        i2c_max77836: i2c-gpio-0 {
+                compatible = "i2c-gpio";
+                gpios = <&gpd0 2 0>, <&gpd0 3 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                max77836: subpmic@25 {
+                        compatible = "maxim,max77836";
+                        interrupt-parent = <&gpx1>;
+                        interrupts = <5 0>;
+                        reg = <0x25>;
+                        wakeup;
+                        muic: max77836-muic {
+                                compatible = "maxim,max77836-muic";
+                        };
+                        regulators {
+                                compatible = "maxim,max77836-regulator";
+                                safeout_reg: SAFEOUT {
+                                        regulator-name = "SAFEOUT";
+                                };
+                                charger_reg: CHARGER {
+                                        regulator-name = "CHARGER";
+                                        regulator-min-microamp = <45000>;
+                                        regulator-max-microamp = <475000>;
+                                        regulator-boot-on;
+                                };
+                                motor_reg: LDO1 {
+                                        regulator-name = "MOT_2.7V";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <2700000>;
+                                };
+                                LDO2 {
+                                        regulator-name = "UNUSED_LDO2";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <3950000>;
+                                };
+                        };
+                        charger {
+                                compatible = "maxim,max77836-charger";
+                                maxim,constant-uvolt = <4350000>;
+                                maxim,fast-charge-uamp = <225000>;
+                                maxim,eoc-uamp = <7500>;
+                                maxim,ovp-uvolt = <6500000>;
+                        };
+                };
+        };
+};
+&adc {
+        vdd-supply = <&ldo3_reg>;
+        status = "okay";
+        assigned-clocks = <&cmu CLK_SCLK_TSADC>;
+        assigned-clock-rates = <6000000>;
+        thermistor-ap {
+                compatible = "ntc,ncp15wb473";
+                pullup-uv = <1800000>;
+                pullup-ohm = <100000>;
+                pulldown-ohm = <100000>;
+                io-channels = <&adc 0>;
+        };
+        thermistor-battery {
+                compatible = "ntc,ncp15wb473";
+                pullup-uv = <1800000>;
+                pullup-ohm = <100000>;
+                pulldown-ohm = <100000>;
+                io-channels = <&adc 1>;
+        };
+};
+&i2c_0 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-slave-addr = <0x10>;
+        samsung,i2c-max-bus-freq = <100000>;
+        status = "okay";
+        s2mps14_pmic@66 {
+                compatible = "samsung,s2mps14-pmic";
+                interrupt-parent = <&gpx0>;
+                interrupts = <7 0>;
+                reg = <0x66>;
+                wakeup;
+                s2mps14_osc: clocks {
+                        compatible = "samsung,s2mps14-clk";
+                        #clock-cells = <1>;
+                        clock-output-names = "s2mps14_ap", "unused",
+                                "s2mps14_bt";
+                };
+                regulators {
+                        ldo1_reg: LDO1 {
+                                regulator-name = "VAP_ALIVE_1.0V";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                        };
+                        ldo2_reg: LDO2 {
+                                regulator-name = "VAP_M1_1.2V";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                        };
+                        ldo3_reg: LDO3 {
+                                regulator-name = "VCC_AP_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+                        ldo4_reg: LDO4 {
+                                regulator-name = "VAP_AVDD_PLL1";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+                        ldo5_reg: LDO5 {
+                                regulator-name = "VAP_PLL_ISO_1.0V";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                        };
+                        ldo6_reg: LDO6 {
+                                regulator-name = "VAP_MIPI_1.0V";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                        };
+                        ldo7_reg: LDO7 {
+                                regulator-name = "VAP_AVDD_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+                        ldo8_reg: LDO8 {
+                                regulator-name = "VAP_USB_3.0V";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                        };
+                        ldo9_reg: LDO9 {
+                                regulator-name = "V_LPDDR_1.2V";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                        };
+                        ldo10_reg: LDO10 {
+                                regulator-name = "UNUSED_LDO10";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                        };
+                        ldo11_reg: LDO11 {
+                                regulator-name = "V_EMMC_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                samsung,ext-control-gpios = <&gpk0 2 0>;
+                        };
+                        ldo12_reg: LDO12 {
+                                regulator-name = "V_EMMC_2.8V";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                samsung,ext-control-gpios = <&gpk0 2 0>;
+                        };
+                        ldo13_reg: LDO13 {
+                                regulator-name = "VSENSOR_2.85V";
+                                regulator-min-microvolt = <2850000>;
+                                regulator-max-microvolt = <2850000>;
+                                regulator-always-on;
+                        };
+                        ldo14_reg: LDO14 {
+                                regulator-name = "UNUSED_LDO14";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+                        ldo15_reg: LDO15 {
+                                regulator-name = "TSP_AVDD_3.3V";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+                        ldo16_reg: LDO16 {
+                                regulator-name = "LCD_VDD_3.3V";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+                        ldo17_reg: LDO17 {
+                                regulator-name = "UNUSED_LDO17";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+                        ldo18_reg: LDO18 {
+                                regulator-name = "UNUSED_LDO18";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+                        ldo19_reg: LDO19 {
+                                regulator-name = "TSP_VDD_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+                        ldo20_reg: LDO20 {
+                                regulator-name = "LCD_VDD_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+                        ldo21_reg: LDO21 {
+                                regulator-name = "UNUSED_LDO21";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                        };
+                        ldo22_reg: LDO22 {
+                                regulator-name = "UNUSED_LDO22";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                        };
+                        ldo23_reg: LDO23 {
+                                regulator-name = "UNUSED_LDO23";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                        };
+                        ldo24_reg: LDO24 {
+                                regulator-name = "UNUSED_LDO24";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+                        ldo25_reg: LDO25 {
+                                regulator-name = "UNUSED_LDO25";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+                        buck1_reg: BUCK1 {
+                                regulator-name = "VAP_MIF_1.0V";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <900000>;
+                                regulator-always-on;
+                        };
+                        buck2_reg: BUCK2 {
+                                regulator-name = "VAP_ARM_1.0V";
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1150000>;
+                                regulator-always-on;
+                        };
+                        buck3_reg: BUCK3 {
+                                regulator-name = "VAP_INT3D_1.0V";
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                        };
+                        buck4_reg: BUCK4 {
+                                regulator-name = "VCC_SUB_1.95V";
+                                regulator-min-microvolt = <1950000>;
+                                regulator-max-microvolt = <1950000>;
+                                regulator-always-on;
+                        };
+                        buck5_reg: BUCK5 {
+                                regulator-name = "VCC_SUB_1.35V";
+                                regulator-min-microvolt = <1350000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                        };
+                };
+        };
+};
+&i2c_1 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-slave-addr = <0x10>;
+        samsung,i2c-max-bus-freq = <400000>;
+        status = "okay";
+        fuelgauge@36 {
+                compatible = "maxim,max77836-battery";
+                interrupt-parent = <&gpx1>;
+                interrupts = <2 8>;
+                reg = <0x36>;
+        };
+};
+&i2s2 {
+        status = "okay";
+};
+&mshc_0 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        num-slots = <1>;
+        broken-cd;
+        non-removable;
+        cap-mmc-highspeed;
+        desc-num = <4>;
+        mmc-hs200-1_8v;
+        card-detect-delay = <200>;
+        vmmc-supply = <&vemmc_reg>;
+        clock-frequency = <100000000>;
+        clock-freq-min-max = <400000 100000000>;
+        samsung,dw-mshc-ciu-div = <1>;
+        samsung,dw-mshc-sdr-timing = <0 1>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
+        bus-width = <8>;
+        status = "okay";
+};
+&serial_0 {
+        assigned-clocks = <&cmu CLK_SCLK_UART0>;
+        assigned-clock-rates = <100000000>;
+        status = "okay";
+};
+&serial_1 {
+        status = "okay";
+};
+&tmu {
+        vtmu-supply = <&ldo7_reg>;
+        status = "okay";
+};
+&rtc {
+        clocks = <&cmu CLK_RTC>, <&s2mps14_osc 0>;
+        clock-names = "rtc", "rtc_src";
+        status = "okay";
+};
+&xusbxti {
+        clock-frequency = <24000000>;
+};
+&pinctrl_0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sleep0>;
+        sleep0: sleep-state {
+                PIN_SLP(gpa0-0, INPUT, DOWN);
+                PIN_SLP(gpa0-1, INPUT, DOWN);
+                PIN_SLP(gpa0-2, INPUT, DOWN);
+                PIN_SLP(gpa0-3, INPUT, DOWN);
+                PIN_SLP(gpa0-4, INPUT, DOWN);
+                PIN_SLP(gpa0-5, INPUT, DOWN);
+                PIN_SLP(gpa0-6, INPUT, DOWN);
+                PIN_SLP(gpa0-7, INPUT, DOWN);
+                PIN_SLP(gpa1-0, INPUT, DOWN);
+                PIN_SLP(gpa1-1, INPUT, DOWN);
+                PIN_SLP(gpa1-2, INPUT, DOWN);
+                PIN_SLP(gpa1-3, INPUT, DOWN);
+                PIN_SLP(gpa1-4, INPUT, DOWN);
+                PIN_SLP(gpa1-5, INPUT, DOWN);
+                PIN_SLP(gpb-0, PREV, NONE);
+                PIN_SLP(gpb-1, PREV, NONE);
+                PIN_SLP(gpb-2, PREV, NONE);
+                PIN_SLP(gpb-3, PREV, NONE);
+                PIN_SLP(gpb-4, INPUT, DOWN);
+                PIN_SLP(gpb-5, INPUT, DOWN);
+                PIN_SLP(gpb-6, INPUT, DOWN);
+                PIN_SLP(gpb-7, INPUT, DOWN);
+                PIN_SLP(gpc0-0, INPUT, DOWN);
+                PIN_SLP(gpc0-1, INPUT, DOWN);
+                PIN_SLP(gpc0-2, INPUT, DOWN);
+                PIN_SLP(gpc0-3, INPUT, DOWN);
+                PIN_SLP(gpc0-4, INPUT, DOWN);
+                PIN_SLP(gpc1-0, INPUT, DOWN);
+                PIN_SLP(gpc1-1, INPUT, DOWN);
+                PIN_SLP(gpc1-2, INPUT, DOWN);
+                PIN_SLP(gpc1-3, INPUT, DOWN);
+                PIN_SLP(gpc1-4, INPUT, DOWN);
+                PIN_SLP(gpd0-0, INPUT, DOWN);
+                PIN_SLP(gpd0-1, INPUT, DOWN);
+                PIN_SLP(gpd0-2, INPUT, NONE);
+                PIN_SLP(gpd0-3, INPUT, NONE);
+                PIN_SLP(gpd1-0, INPUT, NONE);
+                PIN_SLP(gpd1-1, INPUT, NONE);
+                PIN_SLP(gpd1-2, INPUT, NONE);
+                PIN_SLP(gpd1-3, INPUT, NONE);
+        };
+};
+&pinctrl_1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sleep1>;
+        sleep1: sleep-state {
+                PIN_SLP(gpe0-0, PREV, NONE);
+                PIN_SLP(gpe0-1, PREV, NONE);
+                PIN_SLP(gpe0-2, INPUT, DOWN);
+                PIN_SLP(gpe0-3, INPUT, DOWN);
+                PIN_SLP(gpe0-4, PREV, NONE);
+                PIN_SLP(gpe0-5, INPUT, DOWN);
+                PIN_SLP(gpe0-6, INPUT, DOWN);
+                PIN_SLP(gpe0-7, INPUT, DOWN);
+                PIN_SLP(gpe1-0, INPUT, DOWN);
+                PIN_SLP(gpe1-1, PREV, NONE);
+                PIN_SLP(gpe1-2, INPUT, DOWN);
+                PIN_SLP(gpe1-3, INPUT, DOWN);
+                PIN_SLP(gpe1-4, INPUT, DOWN);
+                PIN_SLP(gpe1-5, INPUT, DOWN);
+                PIN_SLP(gpe1-6, INPUT, DOWN);
+                PIN_SLP(gpe1-7, INPUT, NONE);
+                PIN_SLP(gpe2-0, INPUT, NONE);
+                PIN_SLP(gpe2-1, INPUT, NONE);
+                PIN_SLP(gpe2-2, INPUT, NONE);
+                PIN_SLP(gpk0-0, INPUT, DOWN);
+                PIN_SLP(gpk0-1, INPUT, DOWN);
+                PIN_SLP(gpk0-2, OUT0, NONE);
+                PIN_SLP(gpk0-3, INPUT, DOWN);
+                PIN_SLP(gpk0-4, INPUT, DOWN);
+                PIN_SLP(gpk0-5, INPUT, DOWN);
+                PIN_SLP(gpk0-6, INPUT, DOWN);
+                PIN_SLP(gpk0-7, INPUT, DOWN);
+                PIN_SLP(gpk1-0, PREV, NONE);
+                PIN_SLP(gpk1-1, PREV, NONE);
+                PIN_SLP(gpk1-2, INPUT, DOWN);
+                PIN_SLP(gpk1-3, PREV, NONE);
+                PIN_SLP(gpk1-4, PREV, NONE);
+                PIN_SLP(gpk1-5, PREV, NONE);
+                PIN_SLP(gpk1-6, PREV, NONE);
+                PIN_SLP(gpk2-0, INPUT, DOWN);
+                PIN_SLP(gpk2-1, INPUT, DOWN);
+                PIN_SLP(gpk2-2, INPUT, DOWN);
+                PIN_SLP(gpk2-3, INPUT, DOWN);
+                PIN_SLP(gpk2-4, INPUT, DOWN);
+                PIN_SLP(gpk2-5, INPUT, DOWN);
+                PIN_SLP(gpk2-6, INPUT, DOWN);
+                PIN_SLP(gpl0-0, INPUT, DOWN);
+                PIN_SLP(gpl0-1, INPUT, DOWN);
+                PIN_SLP(gpl0-2, INPUT, DOWN);
+                PIN_SLP(gpl0-3, INPUT, DOWN);
+                PIN_SLP(gpm0-0, INPUT, DOWN);
+                PIN_SLP(gpm0-1, INPUT, DOWN);
+                PIN_SLP(gpm0-2, INPUT, DOWN);
+                PIN_SLP(gpm0-3, INPUT, DOWN);
+                PIN_SLP(gpm0-4, INPUT, DOWN);
+                PIN_SLP(gpm0-5, INPUT, DOWN);
+                PIN_SLP(gpm0-6, INPUT, DOWN);
+                PIN_SLP(gpm0-7, INPUT, DOWN);
+                PIN_SLP(gpm1-0, INPUT, DOWN);
+                PIN_SLP(gpm1-1, INPUT, DOWN);
+                PIN_SLP(gpm1-2, INPUT, DOWN);
+                PIN_SLP(gpm1-3, INPUT, DOWN);
+                PIN_SLP(gpm1-4, INPUT, DOWN);
+                PIN_SLP(gpm1-5, INPUT, DOWN);
+                PIN_SLP(gpm1-6, INPUT, DOWN);
+                PIN_SLP(gpm2-0, INPUT, DOWN);
+                PIN_SLP(gpm2-1, INPUT, DOWN);
+                PIN_SLP(gpm2-2, INPUT, DOWN);
+                PIN_SLP(gpm2-3, INPUT, DOWN);
+                PIN_SLP(gpm2-4, INPUT, DOWN);
+                PIN_SLP(gpm3-0, INPUT, DOWN);
+                PIN_SLP(gpm3-1, INPUT, DOWN);
+                PIN_SLP(gpm3-2, INPUT, DOWN);
+                PIN_SLP(gpm3-3, INPUT, DOWN);
+                PIN_SLP(gpm3-4, INPUT, DOWN);
+                PIN_SLP(gpm3-5, INPUT, DOWN);
+                PIN_SLP(gpm3-6, INPUT, DOWN);
+                PIN_SLP(gpm3-7, INPUT, DOWN);
+                PIN_SLP(gpm4-0, INPUT, DOWN);
+                PIN_SLP(gpm4-1, INPUT, DOWN);
+                PIN_SLP(gpm4-2, INPUT, DOWN);
+                PIN_SLP(gpm4-3, INPUT, DOWN);
+                PIN_SLP(gpm4-4, INPUT, DOWN);
+                PIN_SLP(gpm4-5, INPUT, DOWN);
+                PIN_SLP(gpm4-6, INPUT, DOWN);
+                PIN_SLP(gpm4-7, INPUT, DOWN);
+        };
+};
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index 47b92c150f4e..5ab81c39e2c9 100644
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -12,6 +12,22 @@
 * published by the Free Software Foundation.
 */
+#define PIN_PULL_NONE           0
+#define PIN_PULL_DOWN           1
+#define PIN_PULL_UP             3
+#define PIN_PDN_OUT0            0
+#define PIN_PDN_OUT1            1
+#define PIN_PDN_INPUT           2
+#define PIN_PDN_PREV            3
+#define PIN_SLP(_pin, _mode, _pull)                             \
+        _pin {                                                  \
+                samsung,pins = #_pin;                           \
+                samsung,pin-con-pdn = <PIN_PDN_ ##_mode>;       \
+                samsung,pin-pud-pdn = <PIN_PULL_ ##_pull>;      \
+        }
 &pinctrl_0 {
        gpa0: gpa0 {
                gpio-controller;
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts
new file mode 100644
index 000000000000..80aa8b4c4a3d
--- /dev/null
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -0,0 +1,682 @@
+/*
+ * Samsung's Exynos3250 based Rinato board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Device tree source file for Samsung's Rinato board which is based on
+ * Samsung Exynos3250 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "exynos3250.dtsi"
+#include <dt-bindings/input/input.h>
+/ {
+        model = "Samsung Rinato board";
+        compatible = "samsung,rinato", "samsung,exynos3250", "samsung,exynos3";
+        aliases {
+                i2c7 = &i2c_max77836;
+        };
+        memory {
+                reg =  <0x40000000 0x1ff00000>;
+        };
+        firmware@0205F000 {
+                compatible = "samsung,secure-firmware";
+                reg = <0x0205F000 0x1000>;
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                power_key {
+                        interrupt-parent = <&gpx2>;
+                        interrupts = <7 0>;
+                        gpios = <&gpx2 7 1>;
+                        linux,code = <KEY_POWER>;
+                        label = "power key";
+                        debounce-interval = <10>;
+                        gpio-key,wakeup;
+                };
+        };
+        i2c_max77836: i2c-gpio-0 {
+                compatible = "i2c-gpio";
+                gpios = <&gpd0 2 0>, <&gpd0 3 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                max77836: subpmic@25 {
+                        compatible = "maxim,max77836";
+                        interrupt-parent = <&gpx1>;
+                        interrupts = <5 0>;
+                        reg = <0x25>;
+                        wakeup;
+                        muic: max77836-muic {
+                                compatible = "maxim,max77836-muic";
+                        };
+                        regulators {
+                                compatible = "maxim,max77836-regulator";
+                                safeout_reg: SAFEOUT {
+                                        regulator-name = "SAFEOUT";
+                                };
+                                charger_reg: CHARGER {
+                                        regulator-name = "CHARGER";
+                                        regulator-min-microamp = <45000>;
+                                        regulator-max-microamp = <475000>;
+                                        regulator-boot-on;
+                                };
+                                motor_reg: LDO1 {
+                                        regulator-name = "MOT_2.7V";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <2700000>;
+                                };
+                                LDO2 {
+                                        regulator-name = "UNUSED_LDO2";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <3950000>;
+                                };
+                        };
+                        charger {
+                                compatible = "maxim,max77836-charger";
+                                maxim,constant-uvolt = <4350000>;
+                                maxim,fast-charge-uamp = <225000>;
+                                maxim,eoc-uamp = <7500>;
+                                maxim,ovp-uvolt = <6500000>;
+                        };
+                };
+        };
+};
+&adc {
+        vdd-supply = <&ldo3_reg>;
+        status = "okay";
+        assigned-clocks = <&cmu CLK_SCLK_TSADC>;
+        assigned-clock-rates = <6000000>;
+        thermistor-ap {
+                compatible = "ntc,ncp15wb473";
+                pullup-uv = <1800000>;
+                pullup-ohm = <100000>;
+                pulldown-ohm = <100000>;
+                io-channels = <&adc 0>;
+        };
+        thermistor-battery {
+                compatible = "ntc,ncp15wb473";
+                pullup-uv = <1800000>;
+                pullup-ohm = <100000>;
+                pulldown-ohm = <100000>;
+                io-channels = <&adc 1>;
+        };
+};
+&i2c_0 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-slave-addr = <0x10>;
+        samsung,i2c-max-bus-freq = <100000>;
+        status = "okay";
+        s2mps14_pmic@66 {
+                compatible = "samsung,s2mps14-pmic";
+                interrupt-parent = <&gpx0>;
+                interrupts = <7 0>;
+                reg = <0x66>;
+                wakeup;
+                s2mps14_osc: clocks {
+                        compatible = "samsung,s2mps14-clk";
+                        #clock-cells = <1>;
+                        clock-output-names = "s2mps14_ap", "unused",
+                                "s2mps14_bt";
+                };
+                regulators {
+                        ldo1_reg: LDO1 {
+                                regulator-name = "VAP_ALIVE_1.0V";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+                        ldo2_reg: LDO2 {
+                                regulator-name = "VAP_M1_1.2V";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        ldo3_reg: LDO3 {
+                                regulator-name = "VCC_AP_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        ldo4_reg: LDO4 {
+                                regulator-name = "VAP_AVDD_PLL1";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        ldo5_reg: LDO5 {
+                                regulator-name = "VAP_PLL_ISO_1.0V";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        ldo6_reg: LDO6 {
+                                regulator-name = "VAP_VMIPI_1.0V";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        ldo7_reg: LDO7 {
+                                regulator-name = "VAP_AVDD_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        ldo8_reg: LDO8 {
+                                regulator-name = "VAP_USB_3.0V";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        ldo9_reg: LDO9 {
+                                regulator-name = "V_LPDDR_1.2V";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+                        ldo10_reg: LDO10 {
+                                regulator-name = "UNUSED_LDO10";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        ldo11_reg: LDO11 {
+                                regulator-name = "V_EMMC_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                samsung,ext-control-gpios = <&gpk0 2 0>;
+                        };
+                        ldo12_reg: LDO12 {
+                                regulator-name = "V_EMMC_2.8V";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                samsung,ext-control-gpios = <&gpk0 2 0>;
+                        };
+                        ldo13_reg: LDO13 {
+                                regulator-name = "CAM_AVDD_2.8V";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        ldo14_reg: LDO14 {
+                                regulator-name = "UNUSED_LDO14";
+                                regulator-min-microvolt = <2700000>;
+                                regulator-max-microvolt = <2700000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        ldo15_reg: LDO15 {
+                                regulator-name = "TSP_AVDD_3.3V";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        ldo16_reg: LDO16 {
+                                regulator-name = "LCD_VDD_3.3V";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        ldo17_reg: LDO17 {
+                                regulator-name = "V_IRLED_3.3V";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        ldo18_reg: LDO18 {
+                                regulator-name = "CAM_AF_2.8V";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        ldo19_reg: LDO19 {
+                                regulator-name = "TSP_VDD_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        ldo20_reg: LDO20 {
+                                regulator-name = "LCD_VDD_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        ldo21_reg: LDO21 {
+                                regulator-name = "CAM_IO_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        ldo22_reg: LDO22 {
+                                regulator-name = "CAM_DVDD_1.2V";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        ldo23_reg: LDO23 {
+                                regulator-name = "HRM_VCC_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+                        ldo24_reg: LDO24 {
+                                regulator-name = "HRM_VCC_3.3V";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        ldo25_reg: LDO25 {
+                                regulator-name = "UNUSED_LDO25";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        buck1_reg: BUCK1 {
+                                regulator-name = "VAP_MIF_1.0V";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <900000>;
+                                regulator-always-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        buck2_reg: BUCK2 {
+                                regulator-name = "VAP_ARM_1.0V";
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1150000>;
+                                regulator-always-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        buck3_reg: BUCK3 {
+                                regulator-name = "VAP_INT3D_1.0V";
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                        buck4_reg: BUCK4 {
+                                regulator-name = "VCC_SUB_1.95V";
+                                regulator-min-microvolt = <1950000>;
+                                regulator-max-microvolt = <1950000>;
+                                regulator-always-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+                        buck5_reg: BUCK5 {
+                                regulator-name = "VCC_SUB_1.35V";
+                                regulator-min-microvolt = <1350000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+                };
+        };
+};
+&i2c_1 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-slave-addr = <0x10>;
+        samsung,i2c-max-bus-freq = <400000>;
+        status = "okay";
+        fuelgauge@36 {
+                compatible = "maxim,max77836-battery";
+                interrupt-parent = <&gpx1>;
+                interrupts = <2 8>;
+                reg = <0x36>;
+        };
+};
+&i2s2 {
+        status = "okay";
+};
+&mfc {
+        status = "okay";
+};
+&mshc_0 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        num-slots = <1>;
+        broken-cd;
+        non-removable;
+        cap-mmc-highspeed;
+        desc-num = <4>;
+        mmc-hs200-1_8v;
+        card-detect-delay = <200>;
+        vmmc-supply = <&ldo12_reg>;
+        clock-frequency = <100000000>;
+        clock-freq-min-max = <400000 100000000>;
+        samsung,dw-mshc-ciu-div = <1>;
+        samsung,dw-mshc-sdr-timing = <0 1>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
+        bus-width = <8>;
+        status = "okay";
+};
+&serial_0 {
+        assigned-clocks = <&cmu CLK_SCLK_UART0>;
+        assigned-clock-rates = <100000000>;
+        status = "okay";
+};
+&serial_1 {
+        status = "okay";
+};
+&tmu {
+        vtmu-supply = <&ldo7_reg>;
+        status = "okay";
+};
+&rtc {
+        clocks = <&cmu CLK_RTC>, <&s2mps14_osc 0>;
+        clock-names = "rtc", "rtc_src";
+        status = "okay";
+};
+&xusbxti {
+        clock-frequency = <24000000>;
+};
+&pinctrl_0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sleep0>;
+        sleep0: sleep-state {
+                PIN_SLP(gpa0-0, INPUT, DOWN);
+                PIN_SLP(gpa0-1, INPUT, DOWN);
+                PIN_SLP(gpa0-2, INPUT, DOWN);
+                PIN_SLP(gpa0-3, INPUT, DOWN);
+                PIN_SLP(gpa0-4, INPUT, DOWN);
+                PIN_SLP(gpa0-5, INPUT, DOWN);
+                PIN_SLP(gpa0-6, INPUT, DOWN);
+                PIN_SLP(gpa0-7, INPUT, DOWN);
+                PIN_SLP(gpa1-0, INPUT, DOWN);
+                PIN_SLP(gpa1-1, INPUT, DOWN);
+                PIN_SLP(gpa1-2, INPUT, DOWN);
+                PIN_SLP(gpa1-3, INPUT, DOWN);
+                PIN_SLP(gpa1-4, INPUT, DOWN);
+                PIN_SLP(gpa1-5, INPUT, DOWN);
+                PIN_SLP(gpb-0, PREV, NONE);
+                PIN_SLP(gpb-1, PREV, NONE);
+                PIN_SLP(gpb-2, PREV, NONE);
+                PIN_SLP(gpb-3, PREV, NONE);
+                PIN_SLP(gpb-4, INPUT, DOWN);
+                PIN_SLP(gpb-5, INPUT, DOWN);
+                PIN_SLP(gpb-6, INPUT, DOWN);
+                PIN_SLP(gpb-7, INPUT, DOWN);
+                PIN_SLP(gpc0-0, INPUT, DOWN);
+                PIN_SLP(gpc0-1, INPUT, DOWN);
+                PIN_SLP(gpc0-2, INPUT, DOWN);
+                PIN_SLP(gpc0-3, INPUT, DOWN);
+                PIN_SLP(gpc0-4, INPUT, DOWN);
+                PIN_SLP(gpc1-0, INPUT, DOWN);
+                PIN_SLP(gpc1-1, INPUT, DOWN);
+                PIN_SLP(gpc1-2, INPUT, DOWN);
+                PIN_SLP(gpc1-3, INPUT, DOWN);
+                PIN_SLP(gpc1-4, INPUT, DOWN);
+                PIN_SLP(gpd0-0, INPUT, DOWN);
+                PIN_SLP(gpd0-1, INPUT, DOWN);
+                PIN_SLP(gpd0-2, INPUT, NONE);
+                PIN_SLP(gpd0-3, INPUT, NONE);
+                PIN_SLP(gpd1-0, INPUT, NONE);
+                PIN_SLP(gpd1-1, INPUT, NONE);
+                PIN_SLP(gpd1-2, INPUT, NONE);
+                PIN_SLP(gpd1-3, INPUT, NONE);
+        };
+};
+&pinctrl_1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sleep1>;
+        sleep1: sleep-state {
+                PIN_SLP(gpe0-0, PREV, NONE);
+                PIN_SLP(gpe0-1, PREV, NONE);
+                PIN_SLP(gpe0-2, INPUT, DOWN);
+                PIN_SLP(gpe0-3, INPUT, UP);
+                PIN_SLP(gpe0-4, INPUT, DOWN);
+                PIN_SLP(gpe0-5, INPUT, DOWN);
+                PIN_SLP(gpe0-6, INPUT, DOWN);
+                PIN_SLP(gpe0-7, INPUT, DOWN);
+                PIN_SLP(gpe1-0, INPUT, DOWN);
+                PIN_SLP(gpe1-1, PREV, NONE);
+                PIN_SLP(gpe1-2, INPUT, DOWN);
+                PIN_SLP(gpe1-3, INPUT, DOWN);
+                PIN_SLP(gpe1-4, INPUT, DOWN);
+                PIN_SLP(gpe1-5, INPUT, DOWN);
+                PIN_SLP(gpe1-6, INPUT, DOWN);
+                PIN_SLP(gpe1-7, INPUT, NONE);
+                PIN_SLP(gpe2-0, INPUT, NONE);
+                PIN_SLP(gpe2-1, INPUT, NONE);
+                PIN_SLP(gpe2-2, INPUT, NONE);
+                PIN_SLP(gpk0-0, INPUT, DOWN);
+                PIN_SLP(gpk0-1, INPUT, DOWN);
+                PIN_SLP(gpk0-2, OUT0, NONE);
+                PIN_SLP(gpk0-3, INPUT, DOWN);
+                PIN_SLP(gpk0-4, INPUT, DOWN);
+                PIN_SLP(gpk0-5, INPUT, DOWN);
+                PIN_SLP(gpk0-6, INPUT, DOWN);
+                PIN_SLP(gpk0-7, INPUT, DOWN);
+                PIN_SLP(gpk1-0, INPUT, DOWN);
+                PIN_SLP(gpk1-1, INPUT, DOWN);
+                PIN_SLP(gpk1-2, INPUT, DOWN);
+                PIN_SLP(gpk1-3, INPUT, DOWN);
+                PIN_SLP(gpk1-4, INPUT, DOWN);
+                PIN_SLP(gpk1-5, INPUT, DOWN);
+                PIN_SLP(gpk1-6, INPUT, DOWN);
+                PIN_SLP(gpk2-0, INPUT, DOWN);
+                PIN_SLP(gpk2-1, INPUT, DOWN);
+                PIN_SLP(gpk2-2, INPUT, DOWN);
+                PIN_SLP(gpk2-3, INPUT, DOWN);
+                PIN_SLP(gpk2-4, INPUT, DOWN);
+                PIN_SLP(gpk2-5, INPUT, DOWN);
+                PIN_SLP(gpk2-6, INPUT, DOWN);
+                PIN_SLP(gpl0-0, INPUT, DOWN);
+                PIN_SLP(gpl0-1, INPUT, DOWN);
+                PIN_SLP(gpl0-2, INPUT, DOWN);
+                PIN_SLP(gpl0-3, INPUT, DOWN);
+                PIN_SLP(gpm0-0, INPUT, DOWN);
+                PIN_SLP(gpm0-1, INPUT, DOWN);
+                PIN_SLP(gpm0-2, INPUT, DOWN);
+                PIN_SLP(gpm0-3, INPUT, DOWN);
+                PIN_SLP(gpm0-4, INPUT, DOWN);
+                PIN_SLP(gpm0-5, INPUT, DOWN);
+                PIN_SLP(gpm0-6, INPUT, DOWN);
+                PIN_SLP(gpm0-7, INPUT, DOWN);
+                PIN_SLP(gpm1-0, INPUT, DOWN);
+                PIN_SLP(gpm1-1, INPUT, DOWN);
+                PIN_SLP(gpm1-2, INPUT, DOWN);
+                PIN_SLP(gpm1-3, INPUT, DOWN);
+                PIN_SLP(gpm1-4, INPUT, DOWN);
+                PIN_SLP(gpm1-5, INPUT, DOWN);
+                PIN_SLP(gpm1-6, INPUT, DOWN);
+                PIN_SLP(gpm2-0, INPUT, DOWN);
+                PIN_SLP(gpm2-1, INPUT, DOWN);
+                PIN_SLP(gpm2-2, INPUT, DOWN);
+                PIN_SLP(gpm2-3, INPUT, DOWN);
+                PIN_SLP(gpm2-4, INPUT, DOWN);
+                PIN_SLP(gpm3-0, INPUT, DOWN);
+                PIN_SLP(gpm3-1, INPUT, DOWN);
+                PIN_SLP(gpm3-2, INPUT, DOWN);
+                PIN_SLP(gpm3-3, INPUT, DOWN);
+                PIN_SLP(gpm3-4, INPUT, DOWN);
+                PIN_SLP(gpm3-5, INPUT, DOWN);
+                PIN_SLP(gpm3-6, INPUT, DOWN);
+                PIN_SLP(gpm3-7, INPUT, DOWN);
+                PIN_SLP(gpm4-0, INPUT, DOWN);
+                PIN_SLP(gpm4-1, INPUT, DOWN);
+                PIN_SLP(gpm4-2, INPUT, DOWN);
+                PIN_SLP(gpm4-3, INPUT, DOWN);
+                PIN_SLP(gpm4-4, INPUT, DOWN);
+                PIN_SLP(gpm4-5, INPUT, DOWN);
+                PIN_SLP(gpm4-6, INPUT, DOWN);
+                PIN_SLP(gpm4-7, INPUT, DOWN);
+        };
+};
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 693a3275606f..242ddda0a8cd 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -320,6 +320,16 @@
                        status = "disabled";
                };
+                mfc: codec@13400000 {
+                        compatible = "samsung,mfc-v7";
+                        reg = <0x13400000 0x10000>;
+                        interrupts = <0 102 0>;
+                        clock-names = "mfc", "sclk_mfc";
+                        clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
+                        samsung,power-domain = <&pd_mfc>;
+                        status = "disabled";
+                };
                serial_0: serial@13800000 {
                        compatible = "samsung,exynos4210-uart";
                        reg = <0x13800000 0x100>;
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index e0278ecbc816..b8168f1f8139 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -392,8 +392,8 @@
                reg = <0x13400000 0x10000>;
                interrupts = <0 94 0>;
                samsung,power-domain = <&pd_mfc>;
-                clocks = <&clock CLK_MFC>;
+                clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
-                clock-names = "mfc";
+                clock-names = "mfc", "sclk_mfc";
                status = "disabled";
        };
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index f516da9e8b3a..720836205546 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -431,18 +431,34 @@
                fimc_0: fimc@11800000 {
                        status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC0>,
+                                        <&clock CLK_SCLK_FIMC0>;
+                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+                        assigned-clock-rates = <0>, <160000000>;
                };
                fimc_1: fimc@11810000 {
                        status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC1>,
+                                        <&clock CLK_SCLK_FIMC1>;
+                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+                        assigned-clock-rates = <0>, <160000000>;
                };
                fimc_2: fimc@11820000 {
                        status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC2>,
+                                        <&clock CLK_SCLK_FIMC2>;
+                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+                        assigned-clock-rates = <0>, <160000000>;
                };
                fimc_3: fimc@11830000 {
                        status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC3>,
+                                        <&clock CLK_SCLK_FIMC3>;
+                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+                        assigned-clock-rates = <0>, <160000000>;
                };
        };
 };
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index d50eb3aa708e..aaf0cae4f5e8 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -473,18 +473,34 @@
                fimc_0: fimc@11800000 {
                        status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC0>,
+                                        <&clock CLK_SCLK_FIMC0>;
+                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+                        assigned-clock-rates = <0>, <160000000>;
                };
                fimc_1: fimc@11810000 {
                        status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC1>,
+                                        <&clock CLK_SCLK_FIMC1>;
+                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+                        assigned-clock-rates = <0>, <160000000>;
                };
                fimc_2: fimc@11820000 {
                        status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC2>,
+                                        <&clock CLK_SCLK_FIMC2>;
+                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+                        assigned-clock-rates = <0>, <160000000>;
                };
                fimc_3: fimc@11830000 {
                        status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC3>,
+                                        <&clock CLK_SCLK_FIMC3>;
+                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+                        assigned-clock-rates = <0>, <160000000>;
                };
        };
 };
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 807bb5bf91fc..bcc9e63c8070 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -31,6 +31,23 @@
                pinctrl2 = &pinctrl_2;
        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@900 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0x900>;
+                };
+                cpu@901 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0x901>;
+                };
+        };
        pmu_system_controller: system-controller@10020000 {
                clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
                                "clkout4", "clkout8", "clkout9";
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index 3c00e6ec9302..dd0a43ec56da 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -22,6 +22,23 @@
 / {
        compatible = "samsung,exynos4212", "samsung,exynos4";
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@A00 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0xA00>;
+                };
+                cpu@A01 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0xA01>;
+                };
+        };
        combiner: interrupt-controller@10440000 {
                samsung,combiner-nr = <18>;
        };
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index c697ff01ae8d..3fbf588682b9 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -45,6 +45,16 @@
                compatible = "samsung,odroidx2-audio";
                samsung,i2s-controller = <&i2s0>;
                samsung,audio-codec = <&max98090>;
+                assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
+                                <&clock_audss EXYNOS_MOUT_I2S>,
+                                <&clock_audss EXYNOS_DOUT_SRP>,
+                                <&clock_audss EXYNOS_DOUT_AUD_BUS>;
+                assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
+                                <&clock_audss EXYNOS_MOUT_AUDSS>;
+                assigned-clock-rates = <0>,
+                                <0>,
+                                <192000000>,
+                                <19200000>;
        };
        mmc@12550000 {
@@ -82,18 +92,34 @@
                fimc_0: fimc@11800000 {
                        status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC0>,
+                                        <&clock CLK_SCLK_FIMC0>;
+                        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+                        assigned-clock-rates = <0>, <176000000>;
                };
                fimc_1: fimc@11810000 {
                        status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC1>,
+                                        <&clock CLK_SCLK_FIMC1>;
+                        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+                        assigned-clock-rates = <0>, <176000000>;
                };
                fimc_2: fimc@11820000 {
                        status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC2>,
+                                        <&clock CLK_SCLK_FIMC2>;
+                        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+                        assigned-clock-rates = <0>, <176000000>;
                };
                fimc_3: fimc@11830000 {
                        status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC3>,
+                                        <&clock CLK_SCLK_FIMC3>;
+                        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+                        assigned-clock-rates = <0>, <176000000>;
                };
        };
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 5e066cd87f66..29231b452643 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -14,6 +14,7 @@
 /dts-v1/;
 #include "exynos4412.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 / {
        model = "Samsung Trats 2 based on Exynos4412";
@@ -22,6 +23,7 @@
        aliases {
                i2c9 = &i2c_ak8975;
                i2c10 = &i2c_cm36651;
+                i2c11 = &i2c_max77693;
        };
        memory {
@@ -399,8 +401,6 @@
                                        regulator-name = "VMEM_VDD_2.8V";
                                        regulator-min-microvolt = <2800000>;
                                        regulator-max-microvolt = <2800000>;
-                                        regulator-always-on;
-                                        regulator-mem-off;
                                };
                                ldo23_reg: ldo23 {
@@ -503,8 +503,6 @@
                                        regulator-name = "VMEM_VDDF_3.0V";
                                        regulator-min-microvolt = <2850000>;
                                        regulator-max-microvolt = <2850000>;
-                                        regulator-always-on;
-                                        regulator-mem-off;
                                };
                                buck9_reg: buck9 {
@@ -518,6 +516,42 @@
                };
        };
+        i2c_max77693: i2c-gpio-1 {
+                compatible = "i2c-gpio";
+                gpios = <&gpm2 0 GPIO_ACTIVE_HIGH>, <&gpm2 1 GPIO_ACTIVE_HIGH>;
+                i2c-gpio,delay-us = <2>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "okay";
+                max77693@66 {
+                        compatible = "maxim,max77693";
+                        interrupt-parent = <&gpx1>;
+                        interrupts = <5 2>;
+                        reg = <0x66>;
+                        regulators {
+                                esafeout1_reg: ESAFEOUT1@1 {
+                                        regulator-name = "ESAFEOUT1";
+                                };
+                                esafeout2_reg: ESAFEOUT2@2 {
+                                        regulator-name = "ESAFEOUT2";
+                                };
+                                charger_reg: CHARGER@0 {
+                                        regulator-name = "CHARGER";
+                                        regulator-min-microamp = <60000>;
+                                        regulator-max-microamp = <2580000>;
+                                };
+                        };
+                        max77693_haptic {
+                                compatible = "maxim,max77693-haptic";
+                                haptic-supply = <&ldo26_reg>;
+                                pwms = <&pwm 0 38022 0>;
+                        };
+                };
+        };
        mmc@12550000 {
                num-slots = <1>;
                broken-cd;
@@ -535,6 +569,16 @@
                cap-mmc-highspeed;
        };
+        sdhci@12530000 {
+                bus-width = <4>;
+                cd-gpios = <&gpx3 4 0>;
+                cd-inverted;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>;
+                pinctrl-names = "default";
+                vmmc-supply = <&ldo21_reg>;
+                status = "okay";
+        };
        serial@13800000 {
                status = "okay";
        };
@@ -551,6 +595,11 @@
                status = "okay";
        };
+        tmu@100C0000 {
+                vtmu-supply = <&ldo10_reg>;
+                status = "okay";
+        };
        i2c_ak8975: i2c-gpio-0 {
                compatible = "i2c-gpio";
                gpios = <&gpy2 4 0>, <&gpy2 5 0>;
@@ -598,6 +647,13 @@
                };
        };
+        pwm: pwm@139D0000 {
+                pinctrl-0 = <&pwm0_out>;
+                pinctrl-names = "default";
+                samsung,pwm-outputs = <0>;
+                status = "okay";
+        };
        dsi_0: dsi@11C80000 {
                vddcore-supply = <&ldo8_reg>;
                vddio-supply = <&ldo10_reg>;
@@ -663,28 +719,51 @@
                pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>;
                pinctrl-names = "default";
                status = "okay";
+                assigned-clocks = <&clock CLK_MOUT_CAM0>,
+                                  <&clock CLK_MOUT_CAM1>;
+                assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>,
+                                         <&clock CLK_MOUT_MPLL_USER_T>;
                fimc_0: fimc@11800000 {
                        status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC0>,
+                                        <&clock CLK_SCLK_FIMC0>;
+                        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+                        assigned-clock-rates = <0>, <176000000>;
                };
                fimc_1: fimc@11810000 {
                        status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC1>,
+                                        <&clock CLK_SCLK_FIMC1>;
+                        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+                        assigned-clock-rates = <0>, <176000000>;
                };
                fimc_2: fimc@11820000 {
                        status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC2>,
+                                        <&clock CLK_SCLK_FIMC2>;
+                        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+                        assigned-clock-rates = <0>, <176000000>;
                };
                fimc_3: fimc@11830000 {
                        status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC3>,
+                                        <&clock CLK_SCLK_FIMC3>;
+                        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+                        assigned-clock-rates = <0>, <176000000>;
                };
                csis_0: csis@11880000 {
                        status = "okay";
                        vddcore-supply = <&ldo8_reg>;
                        vddio-supply = <&ldo10_reg>;
-                        clock-frequency = <176000000>;
+                        assigned-clocks = <&clock CLK_MOUT_CSIS0>,
+                                        <&clock CLK_SCLK_CSIS0>;
+                        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+                        assigned-clock-rates = <0>, <176000000>;
                        /* Camera C (3) MIPI CSI-2 (CSIS0) */
                        port@3 {
@@ -698,10 +777,13 @@
                };
                csis_1: csis@11890000 {
+                        status = "okay";
                        vddcore-supply = <&ldo8_reg>;
                        vddio-supply = <&ldo10_reg>;
-                        clock-frequency = <160000000>;
+                        assigned-clocks = <&clock CLK_MOUT_CSIS1>,
-                        status = "okay";
+                                        <&clock CLK_SCLK_CSIS1>;
+                        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+                        assigned-clock-rates = <0>, <176000000>;
                        /* Camera D (4) MIPI CSI-2 (CSIS1) */
                        port@4 {
@@ -782,3 +864,319 @@
                io-channels = <&adc 2>;  /* Battery temperature */
        };
 };
+&pinctrl_0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sleep0>;
+        sleep0: sleep-states {
+                PIN_SLP(gpa0-0, INPUT, NONE);
+                PIN_SLP(gpa0-1, OUT0, NONE);
+                PIN_SLP(gpa0-2, INPUT, NONE);
+                PIN_SLP(gpa0-3, INPUT, UP);
+                PIN_SLP(gpa0-4, INPUT, NONE);
+                PIN_SLP(gpa0-5, INPUT, DOWN);
+                PIN_SLP(gpa0-6, INPUT, DOWN);
+                PIN_SLP(gpa0-7, INPUT, UP);
+                PIN_SLP(gpa1-0, INPUT, DOWN);
+                PIN_SLP(gpa1-1, INPUT, DOWN);
+                PIN_SLP(gpa1-2, INPUT, DOWN);
+                PIN_SLP(gpa1-3, INPUT, DOWN);
+                PIN_SLP(gpa1-4, INPUT, DOWN);
+                PIN_SLP(gpa1-5, INPUT, DOWN);
+                PIN_SLP(gpb-0, INPUT, NONE);
+                PIN_SLP(gpb-1, INPUT, NONE);
+                PIN_SLP(gpb-2, INPUT, NONE);
+                PIN_SLP(gpb-3, INPUT, NONE);
+                PIN_SLP(gpb-4, INPUT, DOWN);
+                PIN_SLP(gpb-5, INPUT, UP);
+                PIN_SLP(gpb-6, INPUT, DOWN);
+                PIN_SLP(gpb-7, INPUT, DOWN);
+                PIN_SLP(gpc0-0, INPUT, DOWN);
+                PIN_SLP(gpc0-1, INPUT, DOWN);
+                PIN_SLP(gpc0-2, INPUT, DOWN);
+                PIN_SLP(gpc0-3, INPUT, DOWN);
+                PIN_SLP(gpc0-4, INPUT, DOWN);
+                PIN_SLP(gpc1-0, INPUT, NONE);
+                PIN_SLP(gpc1-1, PREV, NONE);
+                PIN_SLP(gpc1-2, INPUT, NONE);
+                PIN_SLP(gpc1-3, INPUT, NONE);
+                PIN_SLP(gpc1-4, INPUT, NONE);
+                PIN_SLP(gpd0-0, INPUT, DOWN);
+                PIN_SLP(gpd0-1, INPUT, DOWN);
+                PIN_SLP(gpd0-2, INPUT, NONE);
+                PIN_SLP(gpd0-3, INPUT, NONE);
+                PIN_SLP(gpd1-0, INPUT, DOWN);
+                PIN_SLP(gpd1-1, INPUT, DOWN);
+                PIN_SLP(gpd1-2, INPUT, NONE);
+                PIN_SLP(gpd1-3, INPUT, NONE);
+                PIN_SLP(gpf0-0, INPUT, NONE);
+                PIN_SLP(gpf0-1, INPUT, NONE);
+                PIN_SLP(gpf0-2, INPUT, DOWN);
+                PIN_SLP(gpf0-3, INPUT, DOWN);
+                PIN_SLP(gpf0-4, INPUT, NONE);
+                PIN_SLP(gpf0-5, INPUT, DOWN);
+                PIN_SLP(gpf0-6, INPUT, NONE);
+                PIN_SLP(gpf0-7, INPUT, DOWN);
+                PIN_SLP(gpf1-0, INPUT, DOWN);
+                PIN_SLP(gpf1-1, INPUT, DOWN);
+                PIN_SLP(gpf1-2, INPUT, DOWN);
+                PIN_SLP(gpf1-3, INPUT, DOWN);
+                PIN_SLP(gpf1-4, INPUT, NONE);
+                PIN_SLP(gpf1-5, INPUT, NONE);
+                PIN_SLP(gpf1-6, INPUT, DOWN);
+                PIN_SLP(gpf1-7, PREV, NONE);
+                PIN_SLP(gpf2-0, PREV, NONE);
+                PIN_SLP(gpf2-1, INPUT, DOWN);
+                PIN_SLP(gpf2-2, INPUT, DOWN);
+                PIN_SLP(gpf2-3, INPUT, DOWN);
+                PIN_SLP(gpf2-4, INPUT, DOWN);
+                PIN_SLP(gpf2-5, INPUT, DOWN);
+                PIN_SLP(gpf2-6, INPUT, NONE);
+                PIN_SLP(gpf2-7, INPUT, NONE);
+                PIN_SLP(gpf3-0, INPUT, NONE);
+                PIN_SLP(gpf3-1, PREV, NONE);
+                PIN_SLP(gpf3-2, PREV, NONE);
+                PIN_SLP(gpf3-3, PREV, NONE);
+                PIN_SLP(gpf3-4, OUT1, NONE);
+                PIN_SLP(gpf3-5, INPUT, DOWN);
+                PIN_SLP(gpj0-0, PREV, NONE);
+                PIN_SLP(gpj0-1, PREV, NONE);
+                PIN_SLP(gpj0-2, PREV, NONE);
+                PIN_SLP(gpj0-3, INPUT, DOWN);
+                PIN_SLP(gpj0-4, PREV, NONE);
+                PIN_SLP(gpj0-5, PREV, NONE);
+                PIN_SLP(gpj0-6, INPUT, DOWN);
+                PIN_SLP(gpj0-7, INPUT, DOWN);
+                PIN_SLP(gpj1-0, INPUT, DOWN);
+                PIN_SLP(gpj1-1, PREV, NONE);
+                PIN_SLP(gpj1-2, PREV, NONE);
+                PIN_SLP(gpj1-3, INPUT, DOWN);
+                PIN_SLP(gpj1-4, INPUT, DOWN);
+        };
+};
+&pinctrl_1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sleep1>;
+        sleep1: sleep-states {
+                PIN_SLP(gpk0-0, PREV, NONE);
+                PIN_SLP(gpk0-1, PREV, NONE);
+                PIN_SLP(gpk0-2, OUT0, NONE);
+                PIN_SLP(gpk0-3, PREV, NONE);
+                PIN_SLP(gpk0-4, PREV, NONE);
+                PIN_SLP(gpk0-5, PREV, NONE);
+                PIN_SLP(gpk0-6, PREV, NONE);
+                PIN_SLP(gpk1-0, INPUT, DOWN);
+                PIN_SLP(gpk1-1, INPUT, DOWN);
+                PIN_SLP(gpk1-2, INPUT, DOWN);
+                PIN_SLP(gpk1-3, PREV, NONE);
+                PIN_SLP(gpk1-4, PREV, NONE);
+                PIN_SLP(gpk1-5, PREV, NONE);
+                PIN_SLP(gpk1-6, PREV, NONE);
+                PIN_SLP(gpk2-0, INPUT, DOWN);
+                PIN_SLP(gpk2-1, INPUT, DOWN);
+                PIN_SLP(gpk2-2, INPUT, DOWN);
+                PIN_SLP(gpk2-3, INPUT, DOWN);
+                PIN_SLP(gpk2-4, INPUT, DOWN);
+                PIN_SLP(gpk2-5, INPUT, DOWN);
+                PIN_SLP(gpk2-6, INPUT, DOWN);
+                PIN_SLP(gpk3-0, OUT0, NONE);
+                PIN_SLP(gpk3-1, INPUT, NONE);
+                PIN_SLP(gpk3-2, INPUT, DOWN);
+                PIN_SLP(gpk3-3, INPUT, NONE);
+                PIN_SLP(gpk3-4, INPUT, NONE);
+                PIN_SLP(gpk3-5, INPUT, NONE);
+                PIN_SLP(gpk3-6, INPUT, NONE);
+                PIN_SLP(gpl0-0, INPUT, DOWN);
+                PIN_SLP(gpl0-1, INPUT, DOWN);
+                PIN_SLP(gpl0-2, INPUT, DOWN);
+                PIN_SLP(gpl0-3, INPUT, DOWN);
+                PIN_SLP(gpl0-4, PREV, NONE);
+                PIN_SLP(gpl0-6, PREV, NONE);
+                PIN_SLP(gpl1-0, INPUT, DOWN);
+                PIN_SLP(gpl1-1, INPUT, DOWN);
+                PIN_SLP(gpl2-0, INPUT, DOWN);
+                PIN_SLP(gpl2-1, INPUT, DOWN);
+                PIN_SLP(gpl2-2, INPUT, DOWN);
+                PIN_SLP(gpl2-3, INPUT, DOWN);
+                PIN_SLP(gpl2-4, INPUT, DOWN);
+                PIN_SLP(gpl2-5, INPUT, DOWN);
+                PIN_SLP(gpl2-6, PREV, NONE);
+                PIN_SLP(gpl2-7, INPUT, DOWN);
+                PIN_SLP(gpm0-0, INPUT, DOWN);
+                PIN_SLP(gpm0-1, INPUT, DOWN);
+                PIN_SLP(gpm0-2, INPUT, DOWN);
+                PIN_SLP(gpm0-3, INPUT, DOWN);
+                PIN_SLP(gpm0-4, INPUT, DOWN);
+                PIN_SLP(gpm0-5, INPUT, DOWN);
+                PIN_SLP(gpm0-6, INPUT, DOWN);
+                PIN_SLP(gpm0-7, INPUT, DOWN);
+                PIN_SLP(gpm1-0, INPUT, DOWN);
+                PIN_SLP(gpm1-1, INPUT, DOWN);
+                PIN_SLP(gpm1-2, INPUT, NONE);
+                PIN_SLP(gpm1-3, INPUT, NONE);
+                PIN_SLP(gpm1-4, INPUT, NONE);
+                PIN_SLP(gpm1-5, INPUT, NONE);
+                PIN_SLP(gpm1-6, INPUT, DOWN);
+                PIN_SLP(gpm2-0, INPUT, NONE);
+                PIN_SLP(gpm2-1, INPUT, NONE);
+                PIN_SLP(gpm2-2, INPUT, DOWN);
+                PIN_SLP(gpm2-3, INPUT, DOWN);
+                PIN_SLP(gpm2-4, INPUT, DOWN);
+                PIN_SLP(gpm3-0, PREV, NONE);
+                PIN_SLP(gpm3-1, PREV, NONE);
+                PIN_SLP(gpm3-2, PREV, NONE);
+                PIN_SLP(gpm3-3, OUT1, NONE);
+                PIN_SLP(gpm3-4, INPUT, DOWN);
+                PIN_SLP(gpm3-5, INPUT, DOWN);
+                PIN_SLP(gpm3-6, INPUT, DOWN);
+                PIN_SLP(gpm3-7, INPUT, DOWN);
+                PIN_SLP(gpm4-0, INPUT, DOWN);
+                PIN_SLP(gpm4-1, INPUT, DOWN);
+                PIN_SLP(gpm4-2, INPUT, DOWN);
+                PIN_SLP(gpm4-3, INPUT, DOWN);
+                PIN_SLP(gpm4-4, INPUT, DOWN);
+                PIN_SLP(gpm4-5, INPUT, DOWN);
+                PIN_SLP(gpm4-6, INPUT, DOWN);
+                PIN_SLP(gpm4-7, INPUT, DOWN);
+                PIN_SLP(gpy0-0, INPUT, DOWN);
+                PIN_SLP(gpy0-1, INPUT, DOWN);
+                PIN_SLP(gpy0-2, INPUT, DOWN);
+                PIN_SLP(gpy0-3, INPUT, DOWN);
+                PIN_SLP(gpy0-4, INPUT, DOWN);
+                PIN_SLP(gpy0-5, INPUT, DOWN);
+                PIN_SLP(gpy1-0, INPUT, DOWN);
+                PIN_SLP(gpy1-1, INPUT, DOWN);
+                PIN_SLP(gpy1-2, INPUT, DOWN);
+                PIN_SLP(gpy1-3, INPUT, DOWN);
+                PIN_SLP(gpy2-0, PREV, NONE);
+                PIN_SLP(gpy2-1, INPUT, DOWN);
+                PIN_SLP(gpy2-2, INPUT, NONE);
+                PIN_SLP(gpy2-3, INPUT, NONE);
+                PIN_SLP(gpy2-4, INPUT, NONE);
+                PIN_SLP(gpy2-5, INPUT, NONE);
+                PIN_SLP(gpy3-0, INPUT, DOWN);
+                PIN_SLP(gpy3-1, INPUT, DOWN);
+                PIN_SLP(gpy3-2, INPUT, DOWN);
+                PIN_SLP(gpy3-3, INPUT, DOWN);
+                PIN_SLP(gpy3-4, INPUT, DOWN);
+                PIN_SLP(gpy3-5, INPUT, DOWN);
+                PIN_SLP(gpy3-6, INPUT, DOWN);
+                PIN_SLP(gpy3-7, INPUT, DOWN);
+                PIN_SLP(gpy4-0, INPUT, DOWN);
+                PIN_SLP(gpy4-1, INPUT, DOWN);
+                PIN_SLP(gpy4-2, INPUT, DOWN);
+                PIN_SLP(gpy4-3, INPUT, DOWN);
+                PIN_SLP(gpy4-4, INPUT, DOWN);
+                PIN_SLP(gpy4-5, INPUT, DOWN);
+                PIN_SLP(gpy4-6, INPUT, DOWN);
+                PIN_SLP(gpy4-7, INPUT, DOWN);
+                PIN_SLP(gpy5-0, INPUT, DOWN);
+                PIN_SLP(gpy5-1, INPUT, DOWN);
+                PIN_SLP(gpy5-2, INPUT, DOWN);
+                PIN_SLP(gpy5-3, INPUT, DOWN);
+                PIN_SLP(gpy5-4, INPUT, DOWN);
+                PIN_SLP(gpy5-5, INPUT, DOWN);
+                PIN_SLP(gpy5-6, INPUT, DOWN);
+                PIN_SLP(gpy5-7, INPUT, DOWN);
+                PIN_SLP(gpy6-0, INPUT, DOWN);
+                PIN_SLP(gpy6-1, INPUT, DOWN);
+                PIN_SLP(gpy6-2, INPUT, DOWN);
+                PIN_SLP(gpy6-3, INPUT, DOWN);
+                PIN_SLP(gpy6-4, INPUT, DOWN);
+                PIN_SLP(gpy6-5, INPUT, DOWN);
+                PIN_SLP(gpy6-6, INPUT, DOWN);
+                PIN_SLP(gpy6-7, INPUT, DOWN);
+        };
+};
+&pinctrl_2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sleep2>;
+        sleep2: sleep-states {
+                PIN_SLP(gpz-0, INPUT, DOWN);
+                PIN_SLP(gpz-1, INPUT, DOWN);
+                PIN_SLP(gpz-2, INPUT, DOWN);
+                PIN_SLP(gpz-3, INPUT, DOWN);
+                PIN_SLP(gpz-4, INPUT, DOWN);
+                PIN_SLP(gpz-5, INPUT, DOWN);
+                PIN_SLP(gpz-6, INPUT, DOWN);
+        };
+};
+&pinctrl_3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sleep3>;
+        sleep3: sleep-states {
+                PIN_SLP(gpv0-0, INPUT, DOWN);
+                PIN_SLP(gpv0-1, INPUT, DOWN);
+                PIN_SLP(gpv0-2, INPUT, DOWN);
+                PIN_SLP(gpv0-3, INPUT, DOWN);
+                PIN_SLP(gpv0-4, INPUT, DOWN);
+                PIN_SLP(gpv0-5, INPUT, DOWN);
+                PIN_SLP(gpv0-6, INPUT, DOWN);
+                PIN_SLP(gpv0-7, INPUT, DOWN);
+                PIN_SLP(gpv1-0, INPUT, DOWN);
+                PIN_SLP(gpv1-1, INPUT, DOWN);
+                PIN_SLP(gpv1-2, INPUT, DOWN);
+                PIN_SLP(gpv1-3, INPUT, DOWN);
+                PIN_SLP(gpv1-4, INPUT, DOWN);
+                PIN_SLP(gpv1-5, INPUT, DOWN);
+                PIN_SLP(gpv1-6, INPUT, DOWN);
+                PIN_SLP(gpv1-7, INPUT, DOWN);
+                PIN_SLP(gpv2-0, INPUT, DOWN);
+                PIN_SLP(gpv2-1, INPUT, DOWN);
+                PIN_SLP(gpv2-2, INPUT, DOWN);
+                PIN_SLP(gpv2-3, INPUT, DOWN);
+                PIN_SLP(gpv2-4, INPUT, DOWN);
+                PIN_SLP(gpv2-5, INPUT, DOWN);
+                PIN_SLP(gpv2-6, INPUT, DOWN);
+                PIN_SLP(gpv2-7, INPUT, DOWN);
+                PIN_SLP(gpv3-0, INPUT, DOWN);
+                PIN_SLP(gpv3-1, INPUT, DOWN);
+                PIN_SLP(gpv3-2, INPUT, DOWN);
+                PIN_SLP(gpv3-3, INPUT, DOWN);
+                PIN_SLP(gpv3-4, INPUT, DOWN);
+                PIN_SLP(gpv3-5, INPUT, DOWN);
+                PIN_SLP(gpv3-6, INPUT, DOWN);
+                PIN_SLP(gpv3-7, INPUT, DOWN);
+                PIN_SLP(gpv4-0, INPUT, DOWN);
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index d8bc059e172f..0f6ec93bb1d8 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -22,6 +22,35 @@
 / {
        compatible = "samsung,exynos4412", "samsung,exynos4";
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@A00 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0xA00>;
+                };
+                cpu@A01 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0xA01>;
+                };
+                cpu@A02 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0xA02>;
+                };
+                cpu@A03 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0xA03>;
+                };
+        };
        combiner: interrupt-controller@10440000 {
                samsung,combiner-nr = <20>;
        };
diff --git a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi
new file mode 100644
index 000000000000..75af9c56123e
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi
@@ -0,0 +1,573 @@
+/*
+ * Samsung's Exynos4415 SoCs pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *
+ * Samsung's Exynos4415 SoCs pin-mux and pin-config optiosn are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+&pinctrl_0 {
+        gpa0: gpa0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpa1: gpa1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpb: gpb {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpc0: gpc0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpc1: gpc1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpd0: gpd0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpd1: gpd1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpf0: gpf0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpf1: gpf1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpf2: gpf2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        uart0_data: uart0-data {
+                samsung,pins = "gpa0-0", "gpa0-1";
+                samsung,pin-function = <0x2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        uart0_fctl: uart0-fctl {
+                samsung,pins = "gpa0-2", "gpa0-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        uart1_data: uart1-data {
+                samsung,pins = "gpa0-4", "gpa0-5";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        uart1_fctl: uart1-fctl {
+                samsung,pins = "gpa0-6", "gpa0-7";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        uart2_data: uart2-data {
+                samsung,pins = "gpa1-0", "gpa1-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        uart2_fctl: uart2-fctl {
+                samsung,pins = "gpa1-2", "gpa1-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        uart3_data: uart3-data {
+                samsung,pins = "gpa1-4", "gpa1-5";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        i2c2_bus: i2c2-bus {
+                samsung,pins = "gpa0-6", "gpa0-7";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        i2c3_bus: i2c3-bus {
+                samsung,pins = "gpa1-2", "gpa1-3";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        spi0_bus: spi0-bus {
+                samsung,pins = "gpb-0", "gpb-2", "gpb-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        i2c4_bus: i2c4-bus {
+                samsung,pins = "gpb-0", "gpb-1";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        spi1_bus: spi1-bus {
+                samsung,pins = "gpb-4", "gpb-6", "gpb-7";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        i2c5_bus: i2c5-bus {
+                samsung,pins = "gpb-2", "gpb-3";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        i2s1_bus: i2s1-bus {
+                samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+                                "gpc0-4";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        i2s2_bus: i2s2-bus {
+                samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+                                "gpc1-4";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        pcm2_bus: pcm2-bus {
+                samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+                                "gpc1-4";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        i2c6_bus: i2c6-bus {
+                samsung,pins = "gpc1-3", "gpc1-4";
+                samsung,pin-function = <4>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        spi2_bus: spi2-bus {
+                samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4";
+                samsung,pin-function = <5>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        pwm0_out: pwm0-out {
+                samsung,pins = "gpd0-0";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        pwm1_out: pwm1-out {
+                samsung,pins = "gpd0-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        pwm2_out: pwm2-out {
+                samsung,pins = "gpd0-2";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        pwm3_out: pwm3-out {
+                samsung,pins = "gpd0-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        i2c7_bus: i2c7-bus {
+                samsung,pins = "gpd0-2", "gpd0-3";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        i2c0_bus: i2c0-bus {
+                samsung,pins = "gpd1-0", "gpd1-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        i2c1_bus: i2c1-bus {
+                samsung,pins = "gpd1-2", "gpd1-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+};
+&pinctrl_1 {
+        gpk0: gpk0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpk1: gpk1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpk2: gpk2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpk3: gpk3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpl0: gpl0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpm0: gpm0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpm1: gpm1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpm2: gpm2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpm3: gpm3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpm4: gpm4 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpx0: gpx0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                interrupt-parent = <&gic>;
+                interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>,
+                                <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>;
+                #interrupt-cells = <2>;
+        };
+        gpx1: gpx1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                interrupt-parent = <&gic>;
+                interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>,
+                                <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>;
+                #interrupt-cells = <2>;
+        };
+        gpx2: gpx2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpx3: gpx3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        sd0_clk: sd0-clk {
+                samsung,pins = "gpk0-0";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+        sd0_cmd: sd0-cmd {
+                samsung,pins = "gpk0-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+        sd0_cd: sd0-cd {
+                samsung,pins = "gpk0-2";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+        sd0_rdqs: sd0-rdqs {
+                samsung,pins = "gpk0-7";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+        sd0_bus1: sd0-bus-width1 {
+                samsung,pins = "gpk0-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+        sd0_bus4: sd0-bus-width4 {
+                samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+        sd0_bus8: sd0-bus-width8 {
+                samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+        sd1_clk: sd1-clk {
+                samsung,pins = "gpk1-0";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+        sd1_cmd: sd1-cmd {
+                samsung,pins = "gpk1-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+        sd1_cd: sd1-cd {
+                samsung,pins = "gpk1-2";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+        sd1_bus1: sd1-bus-width1 {
+                samsung,pins = "gpk1-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+        sd1_bus4: sd1-bus-width4 {
+                samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+        sd2_clk: sd2-clk {
+                samsung,pins = "gpk2-0";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <4>;
+        };
+        sd2_cmd: sd2-cmd {
+                samsung,pins = "gpk2-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <4>;
+        };
+        sd2_cd: sd2-cd {
+                samsung,pins = "gpk2-2";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+        sd2_bus1: sd2-bus-width1 {
+                samsung,pins = "gpk2-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <4>;
+        };
+        sd2_bus4: sd2-bus-width4 {
+                samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <4>;
+        };
+        cam_port_b_io: cam-port-b-io {
+                samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
+                                "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
+                                "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        cam_port_b_clk_active: cam-port-b-clk-active {
+                samsung,pins = "gpm2-2";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+        cam_port_b_clk_idle: cam-port-b-clk-idle {
+                samsung,pins = "gpm2-2";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        fimc_is_i2c0: fimc-is-i2c0 {
+                samsung,pins = "gpm4-0", "gpm4-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        fimc_is_i2c1: fimc-is-i2c1 {
+                samsung,pins = "gpm4-2", "gpm4-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        fimc_is_uart: fimc-is-uart {
+                samsung,pins = "gpm3-5", "gpm3-7";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+};
+&pinctrl_2 {
+        gpz: gpz {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        i2s0_bus: i2s0-bus {
+                samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+                                "gpz-4", "gpz-5", "gpz-6";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4415.dtsi b/arch/arm/boot/dts/exynos4415.dtsi
new file mode 100644
index 000000000000..c1c9b37340d9
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4415.dtsi
@@ -0,0 +1,604 @@
+/*
+ * Samsung's Exynos4415 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *
+ * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415
+ * based board files can include this file and provide values for board
+ * specific bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/exynos4415.h>
+#include <dt-bindings/clock/exynos-audss-clk.h>
+/ {
+        compatible = "samsung,exynos4415";
+        interrupt-parent = <&gic>;
+        aliases {
+                pinctrl0 = &pinctrl_0;
+                pinctrl1 = &pinctrl_1;
+                pinctrl2 = &pinctrl_2;
+                mshc0 = &mshc_0;
+                mshc1 = &mshc_1;
+                mshc2 = &mshc_2;
+                spi0 = &spi_0;
+                spi1 = &spi_1;
+                spi2 = &spi_2;
+                i2c0 = &i2c_0;
+                i2c1 = &i2c_1;
+                i2c2 = &i2c_2;
+                i2c3 = &i2c_3;
+                i2c4 = &i2c_4;
+                i2c5 = &i2c_5;
+                i2c6 = &i2c_6;
+                i2c7 = &i2c_7;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu0: cpu@a00 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0xa00>;
+                        clock-frequency = <1600000000>;
+                };
+                cpu1: cpu@a01 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0xa01>;
+                        clock-frequency = <1600000000>;
+                };
+                cpu2: cpu@a02 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0xa02>;
+                        clock-frequency = <1600000000>;
+                };
+                cpu3: cpu@a03 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0xa03>;
+                        clock-frequency = <1600000000>;
+                };
+        };
+        soc: soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                sysram@02020000 {
+                        compatible = "mmio-sram";
+                        reg = <0x02020000 0x50000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x02020000 0x50000>;
+                        smp-sysram@0 {
+                                compatible = "samsung,exynos4210-sysram";
+                                reg = <0x0 0x1000>;
+                        };
+                        smp-sysram@4f000 {
+                                compatible = "samsung,exynos4210-sysram-ns";
+                                reg = <0x4f000 0x1000>;
+                        };
+                };
+                pinctrl_2: pinctrl@03860000 {
+                        compatible = "samsung,exynos4415-pinctrl";
+                        reg = <0x03860000 0x1000>;
+                        interrupts = <0 242 0>;
+                };
+                chipid@10000000 {
+                        compatible = "samsung,exynos4210-chipid";
+                        reg = <0x10000000 0x100>;
+                };
+                sysreg_system_controller: syscon@10010000 {
+                        compatible = "samsung,exynos4-sysreg", "syscon";
+                        reg = <0x10010000 0x400>;
+                };
+                pmu_system_controller: system-controller@10020000 {
+                        compatible = "samsung,exynos4415-pmu", "syscon";
+                        reg = <0x10020000 0x4000>;
+                };
+                mipi_phy: video-phy@10020710 {
+                        compatible = "samsung,s5pv210-mipi-video-phy";
+                        reg = <0x10020710 8>;
+                        #phy-cells = <1>;
+                };
+                pd_cam: cam-power-domain@10024000 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10024000 0x20>;
+                };
+                pd_tv: tv-power-domain@10024020 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10024020 0x20>;
+                };
+                pd_mfc: mfc-power-domain@10024040 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10024040 0x20>;
+                };
+                pd_g3d: g3d-power-domain@10024060 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10024060 0x20>;
+                };
+                pd_lcd0: lcd0-power-domain@10024080 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10024080 0x20>;
+                };
+                pd_isp0: isp0-power-domain@100240A0 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x100240A0 0x20>;
+                };
+                pd_isp1: isp1-power-domain@100240E0 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x100240E0 0x20>;
+                };
+                cmu: clock-controller@10030000 {
+                        compatible = "samsung,exynos4415-cmu";
+                        reg = <0x10030000 0x18000>;
+                        #clock-cells = <1>;
+                };
+                rtc: rtc@10070000 {
+                        compatible = "samsung,exynos3250-rtc";
+                        reg = <0x10070000 0x100>;
+                        interrupts = <0 73 0>, <0 74 0>;
+                        status = "disabled";
+                };
+                mct@10050000 {
+                        compatible = "samsung,exynos4210-mct";
+                        reg = <0x10050000 0x800>;
+                        interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
+                                     <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
+                        clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
+                        clock-names = "fin_pll", "mct";
+                };
+                gic: interrupt-controller@10481000 {
+                        compatible = "arm,cortex-a9-gic";
+                        #interrupt-cells = <3>;
+                        interrupt-controller;
+                        reg = <0x10481000 0x1000>,
+                              <0x10482000 0x1000>,
+                              <0x10484000 0x2000>,
+                              <0x10486000 0x2000>;
+                        interrupts = <1 9 0xf04>;
+                };
+                l2c: l2-cache-controller@10502000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0x10502000 0x1000>;
+                        cache-unified;
+                        cache-level = <2>;
+                        arm,tag-latency = <2 2 1>;
+                        arm,data-latency = <3 2 1>;
+                        arm,double-linefill = <1>;
+                        arm,double-linefill-incr = <0>;
+                        arm,double-linefill-wrap = <1>;
+                        arm,prefetch-drop = <1>;
+                        arm,prefetch-offset = <7>;
+                };
+                cmu_dmc: clock-controller@105C0000 {
+                        compatible = "samsung,exynos4415-cmu-dmc";
+                        reg = <0x105C0000 0x3000>;
+                        #clock-cells = <1>;
+                };
+                pinctrl_1: pinctrl@11000000 {
+                        compatible = "samsung,exynos4415-pinctrl";
+                        reg = <0x11000000 0x1000>;
+                        interrupts = <0 225 0>;
+                        wakeup-interrupt-controller {
+                                compatible = "samsung,exynos4210-wakeup-eint";
+                                interrupt-parent = <&gic>;
+                                interrupts = <0 48 0>;
+                        };
+                };
+                pinctrl_0: pinctrl@11400000 {
+                        compatible = "samsung,exynos4415-pinctrl";
+                        reg = <0x11400000 0x1000>;
+                        interrupts = <0 240 0>;
+                };
+                hsotg: hsotg@12480000 {
+                        compatible = "samsung,s3c6400-hsotg";
+                        reg = <0x12480000 0x20000>;
+                        interrupts = <0 141 0>;
+                        clocks = <&cmu CLK_USBDEVICE>;
+                        clock-names = "otg";
+                        phys = <&exynos_usbphy 0>;
+                        phy-names = "usb2-phy";
+                        status = "disabled";
+                };
+                mshc_0: mshc@12510000 {
+                        compatible = "samsung,exynos5250-dw-mshc";
+                        reg = <0x12510000 0x1000>;
+                        interrupts = <0 142 0>;
+                        clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
+                        clock-names = "biu", "ciu";
+                        fifo-depth = <0x80>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+                mshc_1: mshc@12520000 {
+                        compatible = "samsung,exynos5250-dw-mshc";
+                        reg = <0x12520000 0x1000>;
+                        interrupts = <0 143 0>;
+                        clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
+                        clock-names = "biu", "ciu";
+                        fifo-depth = <0x80>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+                mshc_2: mshc@12530000 {
+                        compatible = "samsung,exynos5250-dw-mshc";
+                        reg = <0x12530000 0x1000>;
+                        interrupts = <0 144 0>;
+                        clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
+                        clock-names = "biu", "ciu";
+                        fifo-depth = <0x80>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+                ehci: ehci@12580000 {
+                        compatible = "samsung,exynos4210-ehci";
+                        reg = <0x12580000 0x100>;
+                        interrupts = <0 140 0>;
+                        clocks = <&cmu CLK_USBHOST>;
+                        clock-names = "usbhost";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                phys = <&exynos_usbphy 1>;
+                                status = "disabled";
+                        };
+                        port@1 {
+                                reg = <1>;
+                                phys = <&exynos_usbphy 2>;
+                                status = "disabled";
+                        };
+                        port@2 {
+                                reg = <2>;
+                                phys = <&exynos_usbphy 3>;
+                                status = "disabled";
+                        };
+                };
+                ohci: ohci@12590000 {
+                        compatible = "samsung,exynos4210-ohci";
+                        reg = <0x12590000 0x100>;
+                        interrupts = <0 140 0>;
+                        clocks = <&cmu CLK_USBHOST>;
+                        clock-names = "usbhost";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                phys = <&exynos_usbphy 1>;
+                                status = "disabled";
+                        };
+                };
+                exynos_usbphy: exynos-usbphy@125B0000 {
+                        compatible = "samsung,exynos4x12-usb2-phy";
+                        reg = <0x125B0000 0x100>;
+                        samsung,pmureg-phandle = <&pmu_system_controller>;
+                        samsung,sysreg-phandle = <&sysreg_system_controller>;
+                        clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>;
+                        clock-names = "phy", "ref";
+                        #phy-cells = <1>;
+                        status = "disabled";
+                };
+                amba {
+                        compatible = "arm,amba-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        interrupt-parent = <&gic>;
+                        ranges;
+                        pdma0: pdma@12680000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0x12680000 0x1000>;
+                                interrupts = <0 138 0>;
+                                clocks = <&cmu CLK_PDMA0>;
+                                clock-names = "apb_pclk";
+                                #dma-cells = <1>;
+                                #dma-channels = <8>;
+                                #dma-requests = <32>;
+                        };
+                        pdma1: pdma@12690000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0x12690000 0x1000>;
+                                interrupts = <0 139 0>;
+                                clocks = <&cmu CLK_PDMA1>;
+                                clock-names = "apb_pclk";
+                                #dma-cells = <1>;
+                                #dma-channels = <8>;
+                                #dma-requests = <32>;
+                        };
+                };
+                adc: adc@126C0000 {
+                        compatible = "samsung,exynos3250-adc",
+                                     "samsung,exynos-adc-v2";
+                        reg = <0x126C0000 0x100>, <0x10020718 0x4>;
+                        interrupts = <0 137 0>;
+                        clock-names = "adc", "sclk";
+                        clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
+                        #io-channel-cells = <1>;
+                        io-channel-ranges;
+                        status = "disabled";
+                };
+                serial_0: serial@13800000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x13800000 0x100>;
+                        interrupts = <0 109 0>;
+                        clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
+                        clock-names = "uart", "clk_uart_baud0";
+                        status = "disabled";
+                };
+                serial_1: serial@13810000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x13810000 0x100>;
+                        interrupts = <0 110 0>;
+                        clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
+                        clock-names = "uart", "clk_uart_baud0";
+                        status = "disabled";
+                };
+                serial_2: serial@13820000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x13820000 0x100>;
+                        interrupts = <0 111 0>;
+                        clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
+                        clock-names = "uart", "clk_uart_baud0";
+                        status = "disabled";
+                };
+                serial_3: serial@13830000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x13830000 0x100>;
+                        interrupts = <0 112 0>;
+                        clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>;
+                        clock-names = "uart", "clk_uart_baud0";
+                        status = "disabled";
+                };
+                i2c_0: i2c@13860000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x13860000 0x100>;
+                        interrupts = <0 113 0>;
+                        clocks = <&cmu CLK_I2C0>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_bus>;
+                        status = "disabled";
+                };
+                i2c_1: i2c@13870000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x13870000 0x100>;
+                        interrupts = <0 114 0>;
+                        clocks = <&cmu CLK_I2C1>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_bus>;
+                        status = "disabled";
+                };
+                i2c_2: i2c@13880000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x13880000 0x100>;
+                        interrupts = <0 115 0>;
+                        clocks = <&cmu CLK_I2C2>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c2_bus>;
+                        status = "disabled";
+                };
+                i2c_3: i2c@13890000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x13890000 0x100>;
+                        interrupts = <0 116 0>;
+                        clocks = <&cmu CLK_I2C3>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c3_bus>;
+                        status = "disabled";
+                };
+                i2c_4: i2c@138A0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x138A0000 0x100>;
+                        interrupts = <0 117 0>;
+                        clocks = <&cmu CLK_I2C4>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c4_bus>;
+                        status = "disabled";
+                };
+                i2c_5: i2c@138B0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x138B0000 0x100>;
+                        interrupts = <0 118 0>;
+                        clocks = <&cmu CLK_I2C5>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c5_bus>;
+                        status = "disabled";
+                };
+                i2c_6: i2c@138C0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x138C0000 0x100>;
+                        interrupts = <0 119 0>;
+                        clocks = <&cmu CLK_I2C6>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c6_bus>;
+                        status = "disabled";
+                };
+                i2c_7: i2c@138D0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x138D0000 0x100>;
+                        interrupts = <0 120 0>;
+                        clocks = <&cmu CLK_I2C7>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c7_bus>;
+                        status = "disabled";
+                };
+                spi_0: spi@13920000 {
+                        compatible = "samsung,exynos4210-spi";
+                        reg = <0x13920000 0x100>;
+                        interrupts = <0 121 0>;
+                        dmas = <&pdma0 7>, <&pdma0 6>;
+                        dma-names = "tx", "rx";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
+                        clock-names = "spi", "spi_busclk0";
+                        samsung,spi-src-clk = <0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi0_bus>;
+                        status = "disabled";
+                };
+                spi_1: spi@13930000 {
+                        compatible = "samsung,exynos4210-spi";
+                        reg = <0x13930000 0x100>;
+                        interrupts = <0 122 0>;
+                        dmas = <&pdma1 7>, <&pdma1 6>;
+                        dma-names = "tx", "rx";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
+                        clock-names = "spi", "spi_busclk0";
+                        samsung,spi-src-clk = <0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi1_bus>;
+                        status = "disabled";
+                };
+                spi_2: spi@13940000 {
+                        compatible = "samsung,exynos4210-spi";
+                        reg = <0x13940000 0x100>;
+                        interrupts = <0 123 0>;
+                        dmas = <&pdma0 9>, <&pdma0 8>;
+                        dma-names = "tx", "rx";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&cmu CLK_SPI2>, <&cmu CLK_SCLK_SPI2>;
+                        clock-names = "spi", "spi_busclk0";
+                        samsung,spi-src-clk = <0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi2_bus>;
+                        status = "disabled";
+                };
+                clock_audss: clock-controller@03810000 {
+                        compatible = "samsung,exynos4210-audss-clock";
+                        reg = <0x03810000 0x0C>;
+                        #clock-cells = <1>;
+                };
+                i2s0: i2s@3830000 {
+                        compatible = "samsung,s5pv210-i2s";
+                        reg = <0x03830000 0x100>;
+                        interrupts = <0 124 0>;
+                        clocks = <&clock_audss EXYNOS_I2S_BUS>,
+                                <&clock_audss EXYNOS_SCLK_I2S>;
+                        clock-names = "iis", "i2s_opclk0";
+                        dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 8>;
+                        dma-names = "tx", "rx", "tx-sec";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2s0_bus>;
+                        samsung,idma-addr = <0x03000000>;
+                        status = "disabled";
+                };
+                pwm: pwm@139D0000 {
+                        compatible = "samsung,exynos4210-pwm";
+                        reg = <0x139D0000 0x1000>;
+                        interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
+                                     <0 107 0>, <0 108 0>;
+                        #pwm-cells = <3>;
+                        status = "disabled";
+                };
+                pmu {
+                        compatible = "arm,cortex-a9-pmu";
+                        interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>;
+                };
+        };
+};
+#include "exynos4415-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
index 0865a2e33f97..c141931378e7 100644
--- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
@@ -12,6 +12,22 @@
 * published by the Free Software Foundation.
 */
+#define PIN_PULL_NONE           0
+#define PIN_PULL_DOWN           1
+#define PIN_PULL_UP             3
+#define PIN_PDN_OUT0            0
+#define PIN_PDN_OUT1            1
+#define PIN_PDN_INPUT           2
+#define PIN_PDN_PREV            3
+#define PIN_SLP(_pin, _mode, _pull)                             \
+        _pin {                                                  \
+                samsung,pins = #_pin;                           \
+                samsung,pin-con-pdn = <PIN_PDN_ ##_mode>;       \
+                samsung,pin-pud-pdn = <PIN_PULL_ ##_pull>;      \
+        }
 / {
        pinctrl@11400000 {
                gpa0: gpa0 {
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 861bb919f6d3..2e9f1f7be77b 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -271,4 +271,14 @@
                compatible = "samsung,exynos4x12-usb2-phy";
                samsung,sysreg-phandle = <&sys_reg>;
        };
+        tmu@100C0000 {
+                compatible = "samsung,exynos4412-tmu";
+                interrupt-parent = <&combiner>;
+                interrupts = <2 4>;
+                reg = <0x100C0000 0x100>;
+                clocks = <&clock 383>;
+                clock-names = "tmu_apbif";
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 3acd97eb6630..7e728a1b5559 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -7,12 +7,13 @@
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
-*/
+ */
 /dts-v1/;
-#include "exynos5250.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/input/input.h>
+#include "exynos5250.dtsi"
 / {
        model = "Insignal Arndale evaluation board based on EXYNOS5250";
@@ -26,465 +27,52 @@
                bootargs = "console=ttySAC2,115200";
        };
-        rtc@101E0000 {
-                status = "okay";
-        };
-        codec@11000000 {
-                samsung,mfc-r = <0x43000000 0x800000>;
-                samsung,mfc-l = <0x51000000 0x800000>;
-        };
-        i2c@12C60000 {
-                samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <20000>;
-                samsung,i2c-slave-addr = <0x66>;
-                status = "okay";
-                s5m8767_pmic@66 {
-                        compatible = "samsung,s5m8767-pmic";
-                        reg = <0x66>;
-                        interrupt-parent = <&gpx3>;
-                        interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
-                        vinb1-supply = <&main_dc_reg>;
-                        vinb2-supply = <&main_dc_reg>;
-                        vinb3-supply = <&main_dc_reg>;
-                        vinb4-supply = <&main_dc_reg>;
-                        vinb5-supply = <&main_dc_reg>;
-                        vinb6-supply = <&main_dc_reg>;
-                        vinb7-supply = <&main_dc_reg>;
-                        vinb8-supply = <&main_dc_reg>;
-                        vinb9-supply = <&main_dc_reg>;
-                        vinl1-supply = <&buck7_reg>;
-                        vinl2-supply = <&buck7_reg>;
-                        vinl3-supply = <&buck7_reg>;
-                        vinl4-supply = <&main_dc_reg>;
-                        vinl5-supply = <&main_dc_reg>;
-                        vinl6-supply = <&main_dc_reg>;
-                        vinl7-supply = <&main_dc_reg>;
-                        vinl8-supply = <&buck8_reg>;
-                        vinl9-supply = <&buck8_reg>;
-                        s5m8767,pmic-buck2-dvs-voltage = <1300000>;
-                        s5m8767,pmic-buck3-dvs-voltage = <1100000>;
-                        s5m8767,pmic-buck4-dvs-voltage = <1200000>;
-                        s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 0>,
-                                                        <&gpd1 1 0>,
-                                                        <&gpd1 2 0>;
-                        s5m8767,pmic-buck-ds-gpios = <&gpx2 3 0>,
-                                                        <&gpx2 4 0>,
-                                                        <&gpx2 5 0>;
-                        regulators {
-                                ldo1_reg: LDO1 {
-                                        regulator-name = "VDD_ALIVE_1.0V";
-                                        regulator-min-microvolt = <1100000>;
-                                        regulator-max-microvolt = <1100000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-                                ldo2_reg: LDO2 {
-                                        regulator-name = "VDD_28IO_DP_1.35V";
-                                        regulator-min-microvolt = <1200000>;
-                                        regulator-max-microvolt = <1200000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-                                ldo3_reg: LDO3 {
-                                        regulator-name = "VDD_COMMON1_1.8V";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-                                ldo4_reg: LDO4 {
-                                        regulator-name = "VDD_IOPERI_1.8V";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        regulator-always-on;
-                                        op_mode = <1>;
-                                };
-                                ldo5_reg: LDO5 {
-                                        regulator-name = "VDD_EXT_1.8V";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-                                ldo6_reg: LDO6 {
-                                        regulator-name = "VDD_MPLL_1.1V";
-                                        regulator-min-microvolt = <1100000>;
-                                        regulator-max-microvolt = <1100000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-                                ldo7_reg: LDO7 {
-                                        regulator-name = "VDD_XPLL_1.1V";
-                                        regulator-min-microvolt = <1100000>;
-                                        regulator-max-microvolt = <1100000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-                                ldo8_reg: LDO8 {
-                                        regulator-name = "VDD_COMMON2_1.0V";
-                                        regulator-min-microvolt = <1000000>;
-                                        regulator-max-microvolt = <1000000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-                                ldo9_reg: LDO9 {
-                                        regulator-name = "VDD_33ON_3.0V";
-                                        regulator-min-microvolt = <3000000>;
-                                        regulator-max-microvolt = <3000000>;
-                                        op_mode = <1>;
-                                };
-                                ldo10_reg: LDO10 {
-                                        regulator-name = "VDD_COMMON3_1.8V";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-                                ldo11_reg: LDO11 {
-                                        regulator-name = "VDD_ABB2_1.8V";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-                                ldo12_reg: LDO12 {
-                                        regulator-name = "VDD_USB_3.0V";
-                                        regulator-min-microvolt = <3000000>;
-                                        regulator-max-microvolt = <3000000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-                                ldo13_reg: LDO13 {
-                                        regulator-name = "VDDQ_C2C_W_1.8V";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-                                ldo14_reg: LDO14 {
-                                        regulator-name = "VDD18_ABB0_3_1.8V";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-                                ldo15_reg: LDO15 {
-                                        regulator-name = "VDD10_COMMON4_1.0V";
-                                        regulator-min-microvolt = <1000000>;
-                                        regulator-max-microvolt = <1000000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-                                ldo16_reg: LDO16 {
-                                        regulator-name = "VDD18_HSIC_1.8V";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-                                ldo17_reg: LDO17 {
-                                        regulator-name = "VDDQ_MMC2_3_2.8V";
-                                        regulator-min-microvolt = <2800000>;
-                                        regulator-max-microvolt = <2800000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-                                ldo18_reg: LDO18 {
-                                        regulator-name = "VDD_33ON_2.8V";
-                                        regulator-min-microvolt = <2800000>;
-                                        regulator-max-microvolt = <2800000>;
-                                        op_mode = <1>;
-                                };
-                                ldo22_reg: LDO22 {
-                                        regulator-name = "EXT_33_OFF";
-                                        regulator-min-microvolt = <3300000>;
-                                        regulator-max-microvolt = <3300000>;
-                                        op_mode = <1>;
-                                };
-                                ldo23_reg: LDO23 {
-                                        regulator-name = "EXT_28_OFF";
-                                        regulator-min-microvolt = <2800000>;
-                                        regulator-max-microvolt = <2800000>;
-                                        op_mode = <1>;
-                                };
-                                ldo25_reg: LDO25 {
-                                        regulator-name = "PVDD_LDO25";
-                                        regulator-min-microvolt = <1200000>;
-                                        regulator-max-microvolt = <1200000>;
-                                        op_mode = <1>;
-                                };
-                                ldo26_reg: LDO26 {
-                                        regulator-name = "EXT_18_OFF";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        op_mode = <1>;
-                                };
-                                buck1_reg: BUCK1 {
-                                        regulator-name = "vdd_mif";
-                                        regulator-min-microvolt = <950000>;
-                                        regulator-max-microvolt = <1200000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-                                buck2_reg: BUCK2 {
-                                        regulator-name = "vdd_arm";
-                                        regulator-min-microvolt = <912500>;
-                                        regulator-max-microvolt = <1300000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-                                buck3_reg: BUCK3 {
-                                        regulator-name = "vdd_int";
-                                        regulator-min-microvolt = <900000>;
-                                        regulator-max-microvolt = <1200000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-                                buck4_reg: BUCK4 {
-                                        regulator-name = "vdd_g3d";
-                                        regulator-min-microvolt = <1000000>;
-                                        regulator-max-microvolt = <1000000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-                                buck5_reg: BUCK5 {
-                                        regulator-name = "VDD_MEM_1.35V";
-                                        regulator-min-microvolt = <750000>;
-                                        regulator-max-microvolt = <1355000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-                                buck7_reg: BUCK7 {
-                                        regulator-name = "PVDD_BUCK7";
-                                        regulator-always-on;
-                                        op_mode = <1>;
-                                };
-                                buck8_reg: BUCK8 {
-                                        regulator-name = "PVDD_BUCK8";
-                                        regulator-always-on;
-                                        op_mode = <1>;
-                                };
-                                buck9_reg: BUCK9 {
-                                        regulator-name = "VDD_33_OFF_EXT1";
-                                        regulator-min-microvolt = <750000>;
-                                        regulator-max-microvolt = <3000000>;
-                                        op_mode = <1>;
-                                };
-                        };
-                };
-        };
-        i2c@12C80000 {
-                status = "okay";
-                samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <66000>;
-                samsung,i2c-slave-addr = <0x50>;
-                hdmiddc@50 {
-                        compatible = "samsung,exynos4210-hdmiddc";
-                        reg = <0x50>;
-                };
-        };
-        i2c@12C90000 {
-                status = "okay";
-                wm1811a@1a {
-                        compatible = "wlf,wm1811";
-                        reg = <0x1a>;
-                        AVDD2-supply = <&main_dc_reg>;
-                        CPVDD-supply = <&main_dc_reg>;
-                        DBVDD1-supply = <&main_dc_reg>;
-                        DBVDD2-supply = <&main_dc_reg>;
-                        DBVDD3-supply = <&main_dc_reg>;
-                        LDO1VDD-supply = <&main_dc_reg>;
-                        SPKVDD1-supply = <&main_dc_reg>;
-                        SPKVDD2-supply = <&main_dc_reg>;
-                        wlf,ldo1ena = <&gpb0 0 0>;
-                        wlf,ldo2ena = <&gpb0 1 0>;
-                };
-        };
-        i2c@12CE0000 {
-                status = "okay";
-                samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <66000>;
-                samsung,i2c-slave-addr = <0x38>;
-                hdmiphy@38 {
-                        compatible = "samsung,exynos4212-hdmiphy";
-                        reg = <0x38>;
-                };
-        };
-        i2c@121D0000 {
-                status = "okay";
-                samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <40000>;
-                samsung,i2c-slave-addr = <0x38>;
-                sata_phy_i2c:sata-phy@38 {
-                        compatible = "samsung,exynos-sataphy-i2c";
-                        reg = <0x38>;
-                };
-        };
-        sata@122F0000 {
-                status = "okay";
-        };
-        sata-phy@12170000 {
-                status = "okay";
-                samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
-        };
-        mmc_0: mmc@12200000 {
-                status = "okay";
-                num-slots = <1>;
-                broken-cd;
-                card-detect-delay = <200>;
-                samsung,dw-mshc-ciu-div = <3>;
-                samsung,dw-mshc-sdr-timing = <2 3>;
-                samsung,dw-mshc-ddr-timing = <1 2>;
-                vmmc-supply = <&mmc_reg>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
-                bus-width = <8>;
-                cap-mmc-highspeed;
-        };
-        mmc_2: mmc@12220000 {
-                status = "okay";
-                num-slots = <1>;
-                card-detect-delay = <200>;
-                samsung,dw-mshc-ciu-div = <3>;
-                samsung,dw-mshc-sdr-timing = <2 3>;
-                samsung,dw-mshc-ddr-timing = <1 2>;
-                vmmc-supply = <&mmc_reg>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
-                bus-width = <4>;
-                disable-wp;
-                cap-sd-highspeed;
-        };
-        i2s0: i2s@03830000 {
-                status = "okay";
-        };
        gpio_keys {
                compatible = "gpio-keys";
                menu {
                        label = "SW-TACT2";
-                        gpios = <&gpx1 4 1>;
+                        gpios = <&gpx1 4 GPIO_ACTIVE_LOW>;
                        linux,code = <KEY_MENU>;
                        gpio-key,wakeup;
                };
                home {
                        label = "SW-TACT3";
-                        gpios = <&gpx1 5 1>;
+                        gpios = <&gpx1 5 GPIO_ACTIVE_LOW>;
                        linux,code = <KEY_HOME>;
                        gpio-key,wakeup;
                };
                up {
                        label = "SW-TACT4";
-                        gpios = <&gpx1 6 1>;
+                        gpios = <&gpx1 6 GPIO_ACTIVE_LOW>;
                        linux,code = <KEY_UP>;
                        gpio-key,wakeup;
                };
                down {
                        label = "SW-TACT5";
-                        gpios = <&gpx1 7 1>;
+                        gpios = <&gpx1 7 GPIO_ACTIVE_LOW>;
                        linux,code = <KEY_DOWN>;
                        gpio-key,wakeup;
                };
                back {
                        label = "SW-TACT6";
-                        gpios = <&gpx2 0 1>;
+                        gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
                        linux,code = <KEY_BACK>;
                        gpio-key,wakeup;
                };
                wakeup {
                        label = "SW-TACT7";
-                        gpios = <&gpx2 1 1>;
+                        gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
                        linux,code = <KEY_WAKEUP>;
                        gpio-key,wakeup;
                };
        };
-        hdmi {
-                hpd-gpio = <&gpx3 7 2>;
-                vdd_osc-supply = <&ldo10_reg>;
-                vdd_pll-supply = <&ldo8_reg>;
-                vdd-supply = <&ldo8_reg>;
-        };
        regulators {
                compatible = "simple-bus";
                #address-cells = <1>;
@@ -502,7 +90,7 @@
                        regulator-name = "VDD_33ON_2.8V";
                        regulator-min-microvolt = <2800000>;
                        regulator-max-microvolt = <2800000>;
-                        gpio = <&gpx1 1 1>;
+                        gpio = <&gpx1 1 GPIO_ACTIVE_LOW>;
                        enable-active-high;
                };
@@ -520,46 +108,455 @@
                };
        };
-        dp-controller@145B0000 {
+        // SMSC USB3503 connected in hardware only mode as a PHY
-                samsung,color-space = <0>;
+        usb_hub: usb-hub {
-                samsung,dynamic-range = <0>;
+                compatible = "smsc,usb3503a";
-                samsung,ycbcr-coeff = <0>;
-                samsung,color-depth = <1>;
+                reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
-                samsung,link-rate = <0x0a>;
+                connect-gpios = <&gpd1 7 GPIO_ACTIVE_LOW>;
-                samsung,lane-count = <4>;
-                status = "okay";
        };
+};
-        fimd: fimd@14400000 {
+&dp {
-                status = "okay";
+        status = "okay";
-                display-timings {
+        samsung,color-space = <0>;
-                        native-mode = <&timing0>;
+        samsung,dynamic-range = <0>;
-                        timing0: timing@0 {
+        samsung,ycbcr-coeff = <0>;
-                                /* 2560x1600 DP panel */
+        samsung,color-depth = <1>;
-                                clock-frequency = <50000>;
+        samsung,link-rate = <0x0a>;
-                                hactive = <2560>;
+        samsung,lane-count = <4>;
-                                vactive = <1600>;
+};
-                                hfront-porch = <48>;
-                                hback-porch = <80>;
+&fimd {
-                                hsync-len = <32>;
+        status = "okay";
-                                vback-porch = <16>;
-                                vfront-porch = <8>;
+        display-timings {
-                                vsync-len = <6>;
+                native-mode = <&timing0>;
-                        };
+                timing0: timing@0 {
+                        /* 2560x1600 DP panel */
+                        clock-frequency = <50000>;
+                        hactive = <2560>;
+                        vactive = <1600>;
+                        hfront-porch = <48>;
+                        hback-porch = <80>;
+                        hsync-len = <32>;
+                        vback-porch = <16>;
+                        vfront-porch = <8>;
+                        vsync-len = <6>;
                };
        };
+};
-        usb_hub_bus {
+&hdmi {
-                compatible = "simple-bus";
+        hpd-gpio = <&gpx3 7 GPIO_ACTIVE_LOW>;
-                #address-cells = <1>;
+        vdd_osc-supply = <&ldo10_reg>;
-                #size-cells = <0>;
+        vdd_pll-supply = <&ldo8_reg>;
+        vdd-supply = <&ldo8_reg>;
+};
+&i2c_0 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <20000>;
+        samsung,i2c-slave-addr = <0x66>;
+        s5m8767_pmic@66 {
+                compatible = "samsung,s5m8767-pmic";
+                reg = <0x66>;
+                interrupt-parent = <&gpx3>;
+                interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+                vinb1-supply = <&main_dc_reg>;
+                vinb2-supply = <&main_dc_reg>;
+                vinb3-supply = <&main_dc_reg>;
+                vinb4-supply = <&main_dc_reg>;
+                vinb5-supply = <&main_dc_reg>;
+                vinb6-supply = <&main_dc_reg>;
+                vinb7-supply = <&main_dc_reg>;
+                vinb8-supply = <&main_dc_reg>;
+                vinb9-supply = <&main_dc_reg>;
+                vinl1-supply = <&buck7_reg>;
+                vinl2-supply = <&buck7_reg>;
+                vinl3-supply = <&buck7_reg>;
+                vinl4-supply = <&main_dc_reg>;
+                vinl5-supply = <&main_dc_reg>;
+                vinl6-supply = <&main_dc_reg>;
+                vinl7-supply = <&main_dc_reg>;
+                vinl8-supply = <&buck8_reg>;
+                vinl9-supply = <&buck8_reg>;
+                s5m8767,pmic-buck2-dvs-voltage = <1300000>;
+                s5m8767,pmic-buck3-dvs-voltage = <1100000>;
+                s5m8767,pmic-buck4-dvs-voltage = <1200000>;
+                s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_HIGH>,
+                                              <&gpd1 1 GPIO_ACTIVE_HIGH>,
+                                              <&gpd1 2 GPIO_ACTIVE_HIGH>;
+                s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>,
+                                             <&gpx2 4 GPIO_ACTIVE_HIGH>,
+                                             <&gpx2 5 GPIO_ACTIVE_HIGH>;
+                regulators {
+                        ldo1_reg: LDO1 {
+                                regulator-name = "VDD_ALIVE_1.0V";
+                                regulator-min-microvolt = <1100000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
-                // SMSC USB3503 connected in hardware only mode as a PHY
+                        ldo2_reg: LDO2 {
-                usb_hub: usb_hub {
+                                regulator-name = "VDD_28IO_DP_1.35V";
-                        compatible = "smsc,usb3503a";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+                        ldo3_reg: LDO3 {
+                                regulator-name = "VDD_COMMON1_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+                        ldo4_reg: LDO4 {
+                                regulator-name = "VDD_IOPERI_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                op_mode = <1>;
+                        };
+                        ldo5_reg: LDO5 {
+                                regulator-name = "VDD_EXT_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+                        ldo6_reg: LDO6 {
+                                regulator-name = "VDD_MPLL_1.1V";
+                                regulator-min-microvolt = <1100000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
-                        reset-gpios = <&gpx3 5 1>;
+                        ldo7_reg: LDO7 {
-                        connect-gpios = <&gpd1 7 1>;
+                                regulator-name = "VDD_XPLL_1.1V";
+                                regulator-min-microvolt = <1100000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+                        ldo8_reg: LDO8 {
+                                regulator-name = "VDD_COMMON2_1.0V";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+                        ldo9_reg: LDO9 {
+                                regulator-name = "VDD_33ON_3.0V";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                op_mode = <1>;
+                        };
+                        ldo10_reg: LDO10 {
+                                regulator-name = "VDD_COMMON3_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+                        ldo11_reg: LDO11 {
+                                regulator-name = "VDD_ABB2_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+                        ldo12_reg: LDO12 {
+                                regulator-name = "VDD_USB_3.0V";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+                        ldo13_reg: LDO13 {
+                                regulator-name = "VDDQ_C2C_W_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+                        ldo14_reg: LDO14 {
+                                regulator-name = "VDD18_ABB0_3_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+                        ldo15_reg: LDO15 {
+                                regulator-name = "VDD10_COMMON4_1.0V";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+                        ldo16_reg: LDO16 {
+                                regulator-name = "VDD18_HSIC_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+                        ldo17_reg: LDO17 {
+                                regulator-name = "VDDQ_MMC2_3_2.8V";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+                        ldo18_reg: LDO18 {
+                                regulator-name = "VDD_33ON_2.8V";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                op_mode = <1>;
+                        };
+                        ldo22_reg: LDO22 {
+                                regulator-name = "EXT_33_OFF";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                op_mode = <1>;
+                        };
+                        ldo23_reg: LDO23 {
+                                regulator-name = "EXT_28_OFF";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                op_mode = <1>;
+                        };
+                        ldo25_reg: LDO25 {
+                                regulator-name = "PVDD_LDO25";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                op_mode = <1>;
+                        };
+                        ldo26_reg: LDO26 {
+                                regulator-name = "EXT_18_OFF";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                op_mode = <1>;
+                        };
+                        buck1_reg: BUCK1 {
+                                regulator-name = "vdd_mif";
+                                regulator-min-microvolt = <950000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+                        buck2_reg: BUCK2 {
+                                regulator-name = "vdd_arm";
+                                regulator-min-microvolt = <912500>;
+                                regulator-max-microvolt = <1300000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+                        buck3_reg: BUCK3 {
+                                regulator-name = "vdd_int";
+                                regulator-min-microvolt = <900000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+                        buck4_reg: BUCK4 {
+                                regulator-name = "vdd_g3d";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+                        buck5_reg: BUCK5 {
+                                regulator-name = "VDD_MEM_1.35V";
+                                regulator-min-microvolt = <750000>;
+                                regulator-max-microvolt = <1355000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+                        buck7_reg: BUCK7 {
+                                regulator-name = "PVDD_BUCK7";
+                                regulator-always-on;
+                                op_mode = <1>;
+                        };
+                        buck8_reg: BUCK8 {
+                                regulator-name = "PVDD_BUCK8";
+                                regulator-always-on;
+                                op_mode = <1>;
+                        };
+                        buck9_reg: BUCK9 {
+                                regulator-name = "VDD_33_OFF_EXT1";
+                                regulator-min-microvolt = <750000>;
+                                regulator-max-microvolt = <3000000>;
+                                op_mode = <1>;
+                        };
                };
        };
 };
+&i2c_2 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
+        samsung,i2c-slave-addr = <0x50>;
+        hdmiddc@50 {
+                compatible = "samsung,exynos4210-hdmiddc";
+                reg = <0x50>;
+        };
+};
+&i2c_3 {
+        status = "okay";
+        wm1811a@1a {
+                compatible = "wlf,wm1811";
+                reg = <0x1a>;
+                AVDD2-supply = <&main_dc_reg>;
+                CPVDD-supply = <&main_dc_reg>;
+                DBVDD1-supply = <&main_dc_reg>;
+                DBVDD2-supply = <&main_dc_reg>;
+                DBVDD3-supply = <&main_dc_reg>;
+                LDO1VDD-supply = <&main_dc_reg>;
+                SPKVDD1-supply = <&main_dc_reg>;
+                SPKVDD2-supply = <&main_dc_reg>;
+                wlf,ldo1ena = <&gpb0 0 GPIO_ACTIVE_HIGH>;
+                wlf,ldo2ena = <&gpb0 1 GPIO_ACTIVE_HIGH>;
+        };
+};
+&i2c_8 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
+        samsung,i2c-slave-addr = <0x38>;
+        hdmiphy@38 {
+                compatible = "samsung,exynos4212-hdmiphy";
+                reg = <0x38>;
+        };
+};
+&i2c_9 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <40000>;
+        samsung,i2c-slave-addr = <0x38>;
+        sata_phy_i2c:sata-phy@38 {
+                compatible = "samsung,exynos-sataphy-i2c";
+                reg = <0x38>;
+        };
+};
+&i2s0 {
+        status = "okay";
+};
+&mfc {
+        samsung,mfc-r = <0x43000000 0x800000>;
+        samsung,mfc-l = <0x51000000 0x800000>;
+};
+&mmc_0 {
+        status = "okay";
+        num-slots = <1>;
+        broken-cd;
+        card-detect-delay = <200>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <2 3>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        vmmc-supply = <&mmc_reg>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+        bus-width = <8>;
+        cap-mmc-highspeed;
+};
+&mmc_2 {
+        status = "okay";
+        num-slots = <1>;
+        card-detect-delay = <200>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <2 3>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        vmmc-supply = <&mmc_reg>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+        bus-width = <4>;
+        disable-wp;
+        cap-sd-highspeed;
+};
+&rtc {
+        status = "okay";
+};
+&sata {
+        status = "okay";
+};
+&sata_phy {
+        status = "okay";
+        samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
+};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 6a0f4c0ff763..bc27cc2558fe 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -7,9 +7,11 @@
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
-*/
+ */
 /dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include "exynos5250.dtsi"
 / {
@@ -27,165 +29,6 @@
                bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
        };
-        rtc@101E0000 {
-                status = "okay";
-        };
-        i2c@12C60000 {
-                samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <20000>;
-                status = "okay";
-                eeprom@50 {
-                        compatible = "samsung,s524ad0xd1";
-                        reg = <0x50>;
-                };
-                max77686@09 {
-                        compatible = "maxim,max77686";
-                        reg = <0x09>;
-                        interrupt-parent = <&gpx3>;
-                        interrupts = <2 0>;
-                        voltage-regulators {
-                                ldo1_reg: LDO1 {
-                                        regulator-name = "P1.0V_LDO_OUT1";
-                                        regulator-min-microvolt = <1000000>;
-                                        regulator-max-microvolt = <1000000>;
-                                        regulator-always-on;
-                                };
-                                ldo2_reg: LDO2 {
-                                        regulator-name = "P1.2V_LDO_OUT2";
-                                        regulator-min-microvolt = <1200000>;
-                                        regulator-max-microvolt = <1200000>;
-                                        regulator-always-on;
-                                };
-                                ldo3_reg: LDO3 {
-                                        regulator-name = "P1.8V_LDO_OUT3";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        regulator-always-on;
-                                };
-                                ldo4_reg: LDO4 {
-                                        regulator-name = "P2.8V_LDO_OUT4";
-                                        regulator-min-microvolt = <2800000>;
-                                        regulator-max-microvolt = <2800000>;
-                                };
-                                ldo5_reg: LDO5 {
-                                        regulator-name = "P1.8V_LDO_OUT5";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                };
-                                ldo6_reg: LDO6 {
-                                        regulator-name = "P1.1V_LDO_OUT6";
-                                        regulator-min-microvolt = <1100000>;
-                                        regulator-max-microvolt = <1100000>;
-                                        regulator-always-on;
-                                };
-                                ldo7_reg: LDO7 {
-                                        regulator-name = "P1.1V_LDO_OUT7";
-                                        regulator-min-microvolt = <1100000>;
-                                        regulator-max-microvolt = <1100000>;
-                                        regulator-always-on;
-                                };
-                                ldo8_reg: LDO8 {
-                                        regulator-name = "P1.0V_LDO_OUT8";
-                                        regulator-min-microvolt = <1000000>;
-                                        regulator-max-microvolt = <1000000>;
-                                };
-                                ldo10_reg: LDO10 {
-                                        regulator-name = "P1.8V_LDO_OUT10";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                };
-                                ldo11_reg: LDO11 {
-                                        regulator-name = "P1.8V_LDO_OUT11";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                };
-                                ldo12_reg: LDO12 {
-                                        regulator-name = "P3.0V_LDO_OUT12";
-                                        regulator-min-microvolt = <3000000>;
-                                        regulator-max-microvolt = <3000000>;
-                                };
-                                ldo13_reg: LDO13 {
-                                        regulator-name = "P1.8V_LDO_OUT13";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                };
-                                ldo14_reg: LDO14 {
-                                        regulator-name = "P1.8V_LDO_OUT14";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                };
-                                ldo15_reg: LDO15 {
-                                        regulator-name = "P1.0V_LDO_OUT15";
-                                        regulator-min-microvolt = <1000000>;
-                                        regulator-max-microvolt = <1000000>;
-                                };
-                                ldo16_reg: LDO16 {
-                                        regulator-name = "P1.8V_LDO_OUT16";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                };
-                                buck1_reg: BUCK1 {
-                                        regulator-name = "vdd_mif";
-                                        regulator-min-microvolt = <950000>;
-                                        regulator-max-microvolt = <1300000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                };
-                                buck2_reg: BUCK2 {
-                                        regulator-name = "vdd_arm";
-                                        regulator-min-microvolt = <850000>;
-                                        regulator-max-microvolt = <1350000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                };
-                                buck3_reg: BUCK3 {
-                                        regulator-name = "vdd_int";
-                                        regulator-min-microvolt = <900000>;
-                                        regulator-max-microvolt = <1200000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                };
-                                buck4_reg: BUCK4 {
-                                        regulator-name = "vdd_g3d";
-                                        regulator-min-microvolt = <850000>;
-                                        regulator-max-microvolt = <1300000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                };
-                                buck5_reg: BUCK5 {
-                                        regulator-name = "P1.8V_BUCK_OUT5";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                };
-                        };
-                };
-        };
        vdd: fixed-regulator@0 {
                compatible = "regulator-fixed";
                regulator-name = "vdd-supply";
@@ -210,199 +53,360 @@
                regulator-always-on;
        };
-        i2c@12C70000 {
+        sound {
-                samsung,i2c-sda-delay = <100>;
+                compatible = "samsung,smdk-wm8994";
-                samsung,i2c-max-bus-freq = <20000>;
-                status = "okay";
-                eeprom@51 {
+                samsung,i2s-controller = <&i2s0>;
-                        compatible = "samsung,s524ad0xd1";
+                samsung,audio-codec = <&wm8994>;
-                        reg = <0x51>;
+        };
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <24000000>;
                };
-                wm8994: wm8994@1a {
+                codec_mclk: codec-mclk {
-                        compatible = "wlf,wm8994";
+                        compatible = "fixed-clock";
-                        reg = <0x1a>;
+                        #clock-cells = <0>;
+                        clock-frequency = <16934000>;
+                };
+        };
+};
-                        gpio-controller;
+&dp {
-                        #gpio-cells = <2>;
+        samsung,color-space = <0>;
+        samsung,dynamic-range = <0>;
+        samsung,ycbcr-coeff = <0>;
+        samsung,color-depth = <1>;
+        samsung,link-rate = <0x0a>;
+        samsung,lane-count = <4>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&dp_hpd>;
+        status = "okay";
+};
-                        clocks = <&codec_mclk>;
+&ehci {
-                        clock-names = "MCLK1";
+        samsung,vbus-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
+};
-                        AVDD2-supply = <&vdd>;
+&fimd {
-                        CPVDD-supply = <&vdd>;
+        status = "okay";
-                        DBVDD-supply = <&dbvdd>;
-                        SPKVDD1-supply = <&spkvdd>;
+        display-timings {
-                        SPKVDD2-supply = <&spkvdd>;
+                native-mode = <&timing0>;
+                timing0: timing@0 {
+                        /* 1280x800 */
+                        clock-frequency = <50000>;
+                        hactive = <1280>;
+                        vactive = <800>;
+                        hfront-porch = <4>;
+                        hback-porch = <4>;
+                        hsync-len = <4>;
+                        vback-porch = <4>;
+                        vfront-porch = <4>;
+                        vsync-len = <4>;
                };
        };
+};
-        i2c@121D0000 {
+&hdmi {
-                samsung,i2c-sda-delay = <100>;
+        hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
-                samsung,i2c-max-bus-freq = <40000>;
+};
-                samsung,i2c-slave-addr = <0x38>;
-                status = "okay";
-                sata_phy_i2c:sata-phy@38 {
+&i2c_0 {
-                        compatible = "samsung,exynos-sataphy-i2c";
+        status = "okay";
-                        reg = <0x38>;
+        samsung,i2c-sda-delay = <100>;
-                };
+        samsung,i2c-max-bus-freq = <20000>;
+        eeprom@50 {
+                compatible = "samsung,s524ad0xd1";
+                reg = <0x50>;
        };
-        i2c@12C80000 {
+        max77686@09 {
-                samsung,i2c-sda-delay = <100>;
+                compatible = "maxim,max77686";
-                samsung,i2c-max-bus-freq = <66000>;
+                reg = <0x09>;
-                status = "okay";
+                interrupt-parent = <&gpx3>;
+                interrupts = <2 IRQ_TYPE_NONE>;
+                voltage-regulators {
+                        ldo1_reg: LDO1 {
+                                regulator-name = "P1.0V_LDO_OUT1";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                        };
-                hdmiddc@50 {
+                        ldo2_reg: LDO2 {
-                        compatible = "samsung,exynos4210-hdmiddc";
+                                regulator-name = "P1.2V_LDO_OUT2";
-                        reg = <0x50>;
+                                regulator-min-microvolt = <1200000>;
-                };
+                                regulator-max-microvolt = <1200000>;
-        };
+                                regulator-always-on;
+                        };
-        i2c@12CE0000 {
+                        ldo3_reg: LDO3 {
-                samsung,i2c-sda-delay = <100>;
+                                regulator-name = "P1.8V_LDO_OUT3";
-                samsung,i2c-max-bus-freq = <66000>;
+                                regulator-min-microvolt = <1800000>;
-                status = "okay";
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
-                hdmiphy@38 {
+                        ldo4_reg: LDO4 {
-                        compatible = "samsung,exynos4212-hdmiphy";
+                                regulator-name = "P2.8V_LDO_OUT4";
-                        reg = <0x38>;
+                                regulator-min-microvolt = <2800000>;
-                };
+                                regulator-max-microvolt = <2800000>;
-        };
+                        };
-        sata@122F0000 {
+                        ldo5_reg: LDO5 {
-                status = "okay";
+                                regulator-name = "P1.8V_LDO_OUT5";
-        };
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
-        sata-phy@12170000 {
+                        ldo6_reg: LDO6 {
-                status = "okay";
+                                regulator-name = "P1.1V_LDO_OUT6";
-                samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
+                                regulator-min-microvolt = <1100000>;
-        };
+                                regulator-max-microvolt = <1100000>;
+                                regulator-always-on;
+                        };
-        mmc@12200000 {
+                        ldo7_reg: LDO7 {
-                status = "okay";
+                                regulator-name = "P1.1V_LDO_OUT7";
-                num-slots = <1>;
+                                regulator-min-microvolt = <1100000>;
-                broken-cd;
+                                regulator-max-microvolt = <1100000>;
-                card-detect-delay = <200>;
+                                regulator-always-on;
-                samsung,dw-mshc-ciu-div = <3>;
+                        };
-                samsung,dw-mshc-sdr-timing = <2 3>;
-                samsung,dw-mshc-ddr-timing = <1 2>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
-                bus-width = <8>;
-                cap-mmc-highspeed;
-        };
-        mmc@12220000 {
+                        ldo8_reg: LDO8 {
-                status = "okay";
+                                regulator-name = "P1.0V_LDO_OUT8";
-                num-slots = <1>;
+                                regulator-min-microvolt = <1000000>;
-                card-detect-delay = <200>;
+                                regulator-max-microvolt = <1000000>;
-                samsung,dw-mshc-ciu-div = <3>;
+                        };
-                samsung,dw-mshc-sdr-timing = <2 3>;
-                samsung,dw-mshc-ddr-timing = <1 2>;
+                        ldo10_reg: LDO10 {
-                pinctrl-names = "default";
+                                regulator-name = "P1.8V_LDO_OUT10";
-                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+                                regulator-min-microvolt = <1800000>;
-                bus-width = <4>;
+                                regulator-max-microvolt = <1800000>;
-                disable-wp;
+                        };
-                cap-sd-highspeed;
-        };
-        spi_1: spi@12d30000 {
+                        ldo11_reg: LDO11 {
-                cs-gpios = <&gpa2 5 0>;
+                                regulator-name = "P1.8V_LDO_OUT11";
-                status = "okay";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
-                w25q80bw@0 {
+                        ldo12_reg: LDO12 {
-                        #address-cells = <1>;
+                                regulator-name = "P3.0V_LDO_OUT12";
-                        #size-cells = <1>;
+                                regulator-min-microvolt = <3000000>;
-                        compatible = "w25x80";
+                                regulator-max-microvolt = <3000000>;
-                        reg = <0>;
+                        };
-                        spi-max-frequency = <1000000>;
-                        controller-data {
+                        ldo13_reg: LDO13 {
-                                samsung,spi-feedback-delay = <0>;
+                                regulator-name = "P1.8V_LDO_OUT13";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
                        };
-                        partition@0 {
+                        ldo14_reg: LDO14 {
-                                label = "U-Boot";
+                                regulator-name = "P1.8V_LDO_OUT14";
-                                reg = <0x0 0x40000>;
+                                regulator-min-microvolt = <1800000>;
-                                read-only;
+                                regulator-max-microvolt = <1800000>;
                        };
-                        partition@40000 {
+                        ldo15_reg: LDO15 {
-                                label = "Kernel";
+                                regulator-name = "P1.0V_LDO_OUT15";
-                                reg = <0x40000 0xc0000>;
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                        };
+                        ldo16_reg: LDO16 {
+                                regulator-name = "P1.8V_LDO_OUT16";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+                        buck1_reg: BUCK1 {
+                                regulator-name = "vdd_mif";
+                                regulator-min-microvolt = <950000>;
+                                regulator-max-microvolt = <1300000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        buck2_reg: BUCK2 {
+                                regulator-name = "vdd_arm";
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        buck3_reg: BUCK3 {
+                                regulator-name = "vdd_int";
+                                regulator-min-microvolt = <900000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        buck4_reg: BUCK4 {
+                                regulator-name = "vdd_g3d";
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1300000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        buck5_reg: BUCK5 {
+                                regulator-name = "P1.8V_BUCK_OUT5";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
                        };
                };
        };
+};
-        hdmi {
+&i2c_1 {
-                hpd-gpio = <&gpx3 7 0>;
+        status = "okay";
-        };
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <20000>;
-        codec@11000000 {
+        eeprom@51 {
-                samsung,mfc-r = <0x43000000 0x800000>;
+                compatible = "samsung,s524ad0xd1";
-                samsung,mfc-l = <0x51000000 0x800000>;
+                reg = <0x51>;
        };
-        i2s0: i2s@03830000 {
+        wm8994: wm8994@1a {
-                status = "okay";
+                compatible = "wlf,wm8994";
+                reg = <0x1a>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                clocks = <&codec_mclk>;
+                clock-names = "MCLK1";
+                AVDD2-supply = <&vdd>;
+                CPVDD-supply = <&vdd>;
+                DBVDD-supply = <&dbvdd>;
+                SPKVDD1-supply = <&spkvdd>;
+                SPKVDD2-supply = <&spkvdd>;
        };
+};
-        sound {
+&i2c_2 {
-                compatible = "samsung,smdk-wm8994";
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
-                samsung,i2s-controller = <&i2s0>;
+        hdmiddc@50 {
-                samsung,audio-codec = <&wm8994>;
+                compatible = "samsung,exynos4210-hdmiddc";
+                reg = <0x50>;
        };
+};
+&i2c_8 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
-        usb@12110000 {
+        hdmiphy@38 {
-                samsung,vbus-gpio = <&gpx2 6 0>;
+                compatible = "samsung,exynos4212-hdmiphy";
+                reg = <0x38>;
        };
+};
+&i2c_9 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <40000>;
+        samsung,i2c-slave-addr = <0x38>;
-        dp-controller@145B0000 {
+        sata_phy_i2c: sata-phy@38 {
-                samsung,color-space = <0>;
+                compatible = "samsung,exynos-sataphy-i2c";
-                samsung,dynamic-range = <0>;
+                reg = <0x38>;
-                samsung,ycbcr-coeff = <0>;
-                samsung,color-depth = <1>;
-                samsung,link-rate = <0x0a>;
-                samsung,lane-count = <4>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&dp_hpd>;
-                status = "okay";
        };
+};
-        fimd@14400000 {
+&i2s0 {
-                status = "okay";
+        status = "okay";
-                display-timings {
+};
-                        native-mode = <&timing0>;
-                        timing0: timing@0 {
+&mfc {
-                                /* 1280x800 */
+        samsung,mfc-r = <0x43000000 0x800000>;
-                                clock-frequency = <50000>;
+        samsung,mfc-l = <0x51000000 0x800000>;
-                                hactive = <1280>;
+};
-                                vactive = <800>;
-                                hfront-porch = <4>;
+&mmc_0 {
-                                hback-porch = <4>;
+        status = "okay";
-                                hsync-len = <4>;
+        num-slots = <1>;
-                                vback-porch = <4>;
+        broken-cd;
-                                vfront-porch = <4>;
+        card-detect-delay = <200>;
-                                vsync-len = <4>;
+        samsung,dw-mshc-ciu-div = <3>;
-                        };
+        samsung,dw-mshc-sdr-timing = <2 3>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+        bus-width = <8>;
+        cap-mmc-highspeed;
+};
+&mmc_2 {
+        status = "okay";
+        num-slots = <1>;
+        card-detect-delay = <200>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <2 3>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+        bus-width = <4>;
+        disable-wp;
+        cap-sd-highspeed;
+};
+&rtc {
+        status = "okay";
+};
+&sata {
+        status = "okay";
+};
+&sata_phy {
+        status = "okay";
+        samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
+};
+&spi_1 {
+        status = "okay";
+        cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>;
+        w25q80bw@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "w25x80";
+                reg = <0>;
+                spi-max-frequency = <1000000>;
+                controller-data {
+                        samsung,spi-feedback-delay = <0>;
                };
-        };
-        fixed-rate-clocks {
+                partition@0 {
-                xxti {
+                        label = "U-Boot";
-                        compatible = "samsung,clock-xxti";
+                        reg = <0x0 0x40000>;
-                        clock-frequency = <24000000>;
+                        read-only;
                };
-                codec_mclk: codec-mclk {
+                partition@40000 {
-                        compatible = "fixed-clock";
+                        label = "Kernel";
-                        #clock-cells = <0>;
+                        reg = <0x40000 0xc0000>;
-                        clock-frequency = <16934000>;
                };
        };
 };
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 60429ad1c5d8..effaf2af41bc 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -6,10 +6,13 @@
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
-*/
+ */
 /dts-v1/;
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/maxim,max77686.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/input/input.h>
 #include "exynos5250.dtsi"
 / {
@@ -25,76 +28,7 @@
        };
        chosen {
-        };
+                bootargs = "console=tty1";
-        rtc@101E0000 {
-                status = "okay";
-        };
-        pinctrl@11400000 {
-                ec_irq: ec-irq {
-                        samsung,pins = "gpx1-6";
-                        samsung,pin-function = <0>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-                sd3_clk: sd3-clk {
-                        samsung,pin-drv = <0>;
-                };
-                sd3_cmd: sd3-cmd {
-                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
-                };
-                sd3_bus4: sd3-bus-width4 {
-                        samsung,pin-drv = <0>;
-                };
-                max98095_en: max98095-en {
-                        samsung,pins = "gpx1-7";
-                        samsung,pin-function = <0>;
-                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
-                };
-                tps65090_irq: tps65090-irq {
-                        samsung,pins = "gpx2-6";
-                        samsung,pin-function = <0>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-                usb3_vbus_en: usb3-vbus-en {
-                        samsung,pins = "gpx2-7";
-                        samsung,pin-function = <1>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-                hdmi_hpd_irq: hdmi-hpd-irq {
-                        samsung,pins = "gpx3-7";
-                        samsung,pin-function = <0>;
-                        samsung,pin-pud = <1>;
-                        samsung,pin-drv = <0>;
-                };
-        };
-        pinctrl@13400000 {
-                arb_their_claim: arb-their-claim {
-                        samsung,pins = "gpe0-4";
-                        samsung,pin-function = <0>;
-                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
-                };
-                arb_our_claim: arb-our-claim {
-                        samsung,pins = "gpf0-3";
-                        samsung,pin-function = <1>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
        };
        gpio-keys {
@@ -102,14 +36,14 @@
                power {
                        label = "Power";
-                        gpios = <&gpx1 3 1>;
+                        gpios = <&gpx1 3 GPIO_ACTIVE_LOW>;
-                        linux,code = <116>; /* KEY_POWER */
+                        linux,code = <KEY_POWER>;
                        gpio-key,wakeup;
                };
                lid-switch {
                        label = "Lid";
-                        gpios = <&gpx3 5 1>;
+                        gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
                        linux,input-type = <5>; /* EV_SW */
                        linux,code = <0>; /* SW_LID */
                        debounce-interval = <1>;
@@ -130,8 +64,8 @@
                i2c-parent = <&{/i2c@12CA0000}>;
-                our-claim-gpio = <&gpf0 3 1>;
+                our-claim-gpio = <&gpf0 3 GPIO_ACTIVE_LOW>;
-                their-claim-gpios = <&gpe0 4 1>;
+                their-claim-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>;
                slew-delay-us = <10>;
                wait-retry-us = <3000>;
                wait-free-us = <50000>;
@@ -154,7 +88,7 @@
                        cros_ec: embedded-controller {
                                compatible = "google,cros-ec-i2c";
                                reg = <0x1e>;
-                                interrupts = <6 0>;
+                                interrupts = <6 IRQ_TYPE_NONE>;
                                interrupt-parent = <&gpx1>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&ec_irq>;
@@ -241,13 +175,6 @@
        };
        i2c@12CD0000 {
-                max98095: codec@11 {
-                        compatible = "maxim,max98095";
-                        reg = <0x11>;
-                        pinctrl-0 = <&max98095_en>;
-                        pinctrl-names = "default";
-                };
                ptn3460: lvds-bridge@20 {
                        compatible = "nxp,ptn3460";
                        reg = <0x20>;
@@ -258,10 +185,6 @@
                };
        };
-        i2s0: i2s@03830000 {
-                status = "okay";
-        };
        sound {
                compatible = "google,snow-audio-max98095";
@@ -275,20 +198,12 @@
                regulator-name = "P5.0V_USB3CON";
                regulator-min-microvolt = <5000000>;
                regulator-max-microvolt = <5000000>;
-                gpio = <&gpx2 7 0>;
+                gpio = <&gpx2 7 GPIO_ACTIVE_HIGH>;
                pinctrl-names = "default";
                pinctrl-0 = <&usb3_vbus_en>;
                enable-active-high;
        };
-        phy@12100000 {
-                vbus-supply = <&usb3_vbus_reg>;
-        };
-        usb@12110000 {
-                samsung,vbus-gpio = <&gpx1 1 0>;
-        };
        fixed-rate-clocks {
                xxti {
                        compatible = "samsung,clock-xxti";
@@ -296,18 +211,6 @@
                };
        };
-        hdmi {
-                hpd-gpio = <&gpx3 7 0>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&hdmi_hpd_irq>;
-                phy = <&hdmiphy>;
-                ddc = <&i2c_2>;
-                hdmi-en-supply = <&tps65090_fet7>;
-                vdd-supply = <&ldo8_reg>;
-                vdd_osc-supply = <&ldo10_reg>;
-                vdd_pll-supply = <&ldo8_reg>;
-        };
        backlight: backlight {
                compatible = "pwm-backlight";
                pwms = <&pwm 0 1000000 0>;
@@ -319,30 +222,46 @@
                pinctrl-names = "default";
        };
-        fimd@14400000 {
-                status = "okay";
-                samsung,invert-vclk;
-        };
        panel: panel {
                compatible = "auo,b116xw03";
                power-supply = <&fet6>;
                backlight = <&backlight>;
        };
+};
-        dp-controller@145B0000 {
+&dp {
-                status = "okay";
+        status = "okay";
-                pinctrl-names = "default";
+        pinctrl-names = "default";
-                pinctrl-0 = <&dp_hpd>;
+        pinctrl-0 = <&dp_hpd>;
-                samsung,color-space = <0>;
+        samsung,color-space = <0>;
-                samsung,dynamic-range = <0>;
+        samsung,dynamic-range = <0>;
-                samsung,ycbcr-coeff = <0>;
+        samsung,ycbcr-coeff = <0>;
-                samsung,color-depth = <1>;
+        samsung,color-depth = <1>;
-                samsung,link-rate = <0x0a>;
+        samsung,link-rate = <0x0a>;
-                samsung,lane-count = <2>;
+        samsung,lane-count = <2>;
-                samsung,hpd-gpio = <&gpx0 7 0>;
+        samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
-                bridge = <&ptn3460>;
+        bridge = <&ptn3460>;
-        };
+};
+&ehci {
+        samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>;
+};
+&fimd {
+        status = "okay";
+        samsung,invert-vclk;
+};
+&hdmi {
+        hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&hdmi_hpd_irq>;
+        phy = <&hdmiphy>;
+        ddc = <&i2c_2>;
+        hdmi-en-supply = <&tps65090_fet7>;
+        vdd-supply = <&ldo8_reg>;
+        vdd_osc-supply = <&ldo10_reg>;
+        vdd_pll-supply = <&ldo8_reg>;
 };
 &i2c_0 {
@@ -350,10 +269,10 @@
        samsung,i2c-sda-delay = <100>;
        samsung,i2c-max-bus-freq = <378000>;
-        max77686@09 {
+        max77686: max77686@09 {
                compatible = "maxim,max77686";
                interrupt-parent = <&gpx3>;
-                interrupts = <2 0>;
+                interrupts = <2 IRQ_TYPE_NONE>;
                pinctrl-names = "default";
                pinctrl-0 = <&max77686_irq>;
                wakeup-source;
@@ -503,7 +422,7 @@
        trackpad {
                reg = <0x67>;
                compatible = "cypress,cyapa";
-                interrupts = <2 0>;
+                interrupts = <2 IRQ_TYPE_NONE>;
                interrupt-parent = <&gpx1>;
                wakeup-source;
        };
@@ -550,6 +469,13 @@
        status = "okay";
        samsung,i2c-sda-delay = <100>;
        samsung,i2c-max-bus-freq = <66000>;
+        max98095: codec@11 {
+                compatible = "maxim,max98095";
+                reg = <0x11>;
+                pinctrl-0 = <&max98095_en>;
+                pinctrl-names = "default";
+        };
 };
 &i2c_8 {
@@ -563,6 +489,10 @@
        };
 };
+&i2s0 {
+        status = "okay";
+};
 &mmc_0 {
        status = "okay";
        num-slots = <1>;
@@ -587,7 +517,7 @@
        pinctrl-names = "default";
        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
        bus-width = <4>;
-        wp-gpios = <&gpc2 1 0>;
+        wp-gpios = <&gpc2 1 GPIO_ACTIVE_HIGH>;
        cap-sd-highspeed;
 };
@@ -610,12 +540,82 @@
 };
 &pinctrl_0 {
+        ec_irq: ec-irq {
+                samsung,pins = "gpx1-6";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        max98095_en: max98095-en {
+                samsung,pins = "gpx1-7";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        tps65090_irq: tps65090-irq {
+                samsung,pins = "gpx2-6";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        usb3_vbus_en: usb3-vbus-en {
+                samsung,pins = "gpx2-7";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
        max77686_irq: max77686-irq {
                samsung,pins = "gpx3-2";
                samsung,pin-function = <0>;
                samsung,pin-pud = <0>;
                samsung,pin-drv = <0>;
        };
+        hdmi_hpd_irq: hdmi-hpd-irq {
+                samsung,pins = "gpx3-7";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <1>;
+                samsung,pin-drv = <0>;
+        };
+};
+&pinctrl_1 {
+        arb_their_claim: arb-their-claim {
+                samsung,pins = "gpe0-4";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        arb_our_claim: arb-our-claim {
+                samsung,pins = "gpf0-3";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+};
+&rtc {
+        status = "okay";
+        clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>;
+        clock-names = "rtc", "rtc_src";
+};
+&sd3_bus4 {
+        samsung,pin-drv = <0>;
+};
+&sd3_clk {
+        samsung,pin-drv = <0>;
+};
+&sd3_cmd {
+        samsung,pin-pud = <3>;
+        samsung,pin-drv = <0>;
 };
 &spi_1 {
@@ -628,4 +628,8 @@
        dr_mode = "host";
 };
+&usbdrd_phy {
+        vbus-supply = <&usb3_vbus_reg>;
+};
 #include "cros-ec-keyboard.dtsi"
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
new file mode 100644
index 000000000000..f02775487cd4
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -0,0 +1,566 @@
+/*
+ * Google Spring board device tree source
+ *
+ * Copyright (c) 2013 Google, Inc
+ * Copyright (c) 2014 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/input/input.h>
+#include "exynos5250.dtsi"
+/ {
+        model = "Google Spring";
+        compatible = "google,spring", "samsung,exynos5250", "samsung,exynos5";
+        memory {
+                reg = <0x40000000 0x80000000>;
+        };
+        chosen {
+                bootargs = "console=tty1";
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&power_key_irq>, <&lid_irq>;
+                power {
+                        label = "Power";
+                        gpios = <&gpx1 3 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_POWER>;
+                        gpio-key,wakeup;
+                };
+                lid-switch {
+                        label = "Lid";
+                        gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
+                        linux,input-type = <5>; /* EV_SW */
+                        linux,code = <0>; /* SW_LID */
+                        debounce-interval = <1>;
+                        gpio-key,wakeup;
+                };
+        };
+        usb-hub {
+                compatible = "smsc,usb3503a";
+                reset-gpios = <&gpe1 0 GPIO_ACTIVE_LOW>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&hsic_reset>;
+        };
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <24000000>;
+                };
+        };
+};
+&dp {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&dp_hpd_gpio>;
+        samsung,color-space = <0>;
+        samsung,dynamic-range = <0>;
+        samsung,ycbcr-coeff = <0>;
+        samsung,color-depth = <1>;
+        samsung,link-rate = <0x0a>;
+        samsung,lane-count = <1>;
+        samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>;
+};
+&ehci {
+        samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>;
+};
+&fimd {
+        status = "okay";
+        samsung,invert-vclk;
+};
+&hdmi {
+        hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&hdmi_hpd_irq>;
+        phy = <&hdmiphy>;
+        ddc = <&i2c_2>;
+        hdmi-en-supply = <&ldo8_reg>;
+        vdd-supply = <&ldo8_reg>;
+        vdd_osc-supply = <&ldo10_reg>;
+        vdd_pll-supply = <&ldo8_reg>;
+};
+&i2c_0 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <378000>;
+        s5m8767-pmic@66 {
+                compatible = "samsung,s5m8767-pmic";
+                reg = <0x66>;
+                interrupt-parent = <&gpx3>;
+                interrupts = <2 IRQ_TYPE_NONE>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&s5m8767_irq &s5m8767_dvs &s5m8767_ds>;
+                wakeup-source;
+                s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>, /* DVS1 */
+                                              <&gpd1 1 GPIO_ACTIVE_LOW>, /* DVS2 */
+                                              <&gpd1 2 GPIO_ACTIVE_LOW>; /* DVS3 */
+                s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_LOW>, /* SET1 */
+                                             <&gpx2 4 GPIO_ACTIVE_LOW>, /* SET2 */
+                                             <&gpx2 5 GPIO_ACTIVE_LOW>; /* SET3 */
+                /*
+                 * The following arrays of DVS voltages are not used, since we are
+                 * not using GPIOs to control PMIC bucks, but they must be defined
+                 * to please the driver.
+                 */
+                s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>,
+                                                 <1250000>, <1200000>,
+                                                 <1150000>, <1100000>,
+                                                 <1000000>, <950000>;
+                s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>,
+                                                 <1100000>, <1100000>,
+                                                 <1000000>, <1000000>,
+                                                 <1000000>, <1000000>;
+                s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>,
+                                                 <1200000>, <1200000>,
+                                                 <1200000>, <1200000>,
+                                                 <1200000>, <1200000>;
+                clocks {
+                        compatible = "samsung,s5m8767-clk";
+                        #clock-cells = <1>;
+                        clock-output-names = "en32khz_ap",
+                                             "en32khz_cp",
+                                             "en32khz_bt";
+                };
+                regulators {
+                        ldo4_reg: LDO4 {
+                                regulator-name = "P1.0V_LDO_OUT4";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                op_mode = <0>;
+                        };
+                        ldo5_reg: LDO5 {
+                                regulator-name = "P1.0V_LDO_OUT5";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                op_mode = <0>;
+                        };
+                        ldo6_reg: LDO6 {
+                                regulator-name = "vdd_mydp";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                op_mode = <3>;
+                        };
+                        ldo7_reg: LDO7 {
+                                regulator-name = "P1.1V_LDO_OUT7";
+                                regulator-min-microvolt = <1100000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-always-on;
+                                op_mode = <3>;
+                        };
+                        ldo8_reg: LDO8 {
+                                regulator-name = "P1.0V_LDO_OUT8";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                op_mode = <3>;
+                        };
+                        ldo10_reg: LDO10 {
+                                regulator-name = "P1.8V_LDO_OUT10";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                op_mode = <3>;
+                        };
+                        ldo11_reg: LDO11 {
+                                regulator-name = "P1.8V_LDO_OUT11";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                op_mode = <0>;
+                        };
+                        ldo12_reg: LDO12 {
+                                regulator-name = "P3.0V_LDO_OUT12";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                                op_mode = <3>;
+                        };
+                        ldo13_reg: LDO13 {
+                                regulator-name = "P1.8V_LDO_OUT13";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                op_mode = <0>;
+                        };
+                        ldo14_reg: LDO14 {
+                                regulator-name = "P1.8V_LDO_OUT14";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                op_mode = <3>;
+                        };
+                        ldo15_reg: LDO15 {
+                                regulator-name = "P1.0V_LDO_OUT15";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                op_mode = <3>;
+                        };
+                        ldo16_reg: LDO16 {
+                                regulator-name = "P1.8V_LDO_OUT16";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                op_mode = <3>;
+                        };
+                        ldo17_reg: LDO17 {
+                                regulator-name = "P2.8V_LDO_OUT17";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-always-on;
+                                op_mode = <0>;
+                        };
+                        ldo25_reg: LDO25 {
+                                regulator-name = "vdd_bridge";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                op_mode = <1>;
+                        };
+                        buck1_reg: BUCK1 {
+                                regulator-name = "vdd_mif";
+                                regulator-min-microvolt = <950000>;
+                                regulator-max-microvolt = <1300000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <3>;
+                        };
+                        buck2_reg: BUCK2 {
+                                regulator-name = "vdd_arm";
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <3>;
+                        };
+                        buck3_reg: BUCK3 {
+                                regulator-name = "vdd_int";
+                                regulator-min-microvolt = <900000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <3>;
+                        };
+                        buck4_reg: BUCK4 {
+                                regulator-name = "vdd_g3d";
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1300000>;
+                                regulator-boot-on;
+                                op_mode = <3>;
+                        };
+                        buck5_reg: BUCK5 {
+                                regulator-name = "P1.8V_BUCK_OUT5";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+                        buck6_reg: BUCK6 {
+                                regulator-name = "P1.2V_BUCK_OUT6";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <0>;
+                        };
+                        buck9_reg: BUCK9 {
+                                regulator-name = "vdd_ummc";
+                                regulator-min-microvolt = <950000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <3>;
+                        };
+                };
+        };
+};
+&i2c_1 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <378000>;
+        trackpad@4b {
+                compatible = "atmel,maxtouch";
+                reg = <0x4b>;
+                interrupt-parent = <&gpx1>;
+                interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&trackpad_irq>;
+                linux,gpio-keymap = <KEY_RESERVED
+                                     KEY_RESERVED
+                                     KEY_RESERVED
+                                     KEY_RESERVED
+                                     KEY_RESERVED
+                                     BTN_LEFT>;
+                wakeup-source;
+        };
+};
+/*
+ * Disabled pullups since external part has its own pullups and
+ * double-pulling gets us out of spec in some cases.
+ */
+&i2c2_bus {
+        samsung,pin-pud = <0>;
+};
+&i2c_2 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
+        hdmiddc@50 {
+                compatible = "samsung,exynos4210-hdmiddc";
+                reg = <0x50>;
+        };
+};
+&i2c_3 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
+};
+&i2c_4 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
+        cros_ec: embedded-controller {
+                compatible = "google,cros-ec-i2c";
+                reg = <0x1e>;
+                interrupts = <6 IRQ_TYPE_NONE>;
+                interrupt-parent = <&gpx1>;
+                wakeup-source;
+                pinctrl-names = "default";
+                pinctrl-0 = <&ec_irq>;
+        };
+};
+&i2c_5 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
+};
+&i2c_7 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
+        temperature-sensor@4c {
+                compatible = "gmt,g781";
+                reg = <0x4c>;
+        };
+};
+&i2c_8 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <378000>;
+        hdmiphy: hdmiphy@38 {
+                compatible = "samsung,exynos4212-hdmiphy";
+                reg = <0x38>;
+        };
+};
+&i2s0 {
+        status = "okay";
+};
+&mfc {
+        samsung,mfc-r = <0x43000000 0x800000>;
+        samsung,mfc-l = <0x51000000 0x800000>;
+};
+&mmc_0 {
+        status = "okay";
+        num-slots = <1>;
+        supports-highspeed;
+        broken-cd;
+        card-detect-delay = <200>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <2 3>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
+        slot@0 {
+                reg = <0>;
+                bus-width = <8>;
+        };
+};
+/*
+ * On Spring we've got SIP WiFi and so can keep drive strengths low to
+ * reduce EMI.
+ */
+&mmc_1 {
+        status = "okay";
+        num-slots = <1>;
+        supports-highspeed;
+        broken-cd;
+        card-detect-delay = <200>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <2 3>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
+        slot@0 {
+                reg = <0>;
+                bus-width = <4>;
+        };
+};
+&pinctrl_0 {
+        s5m8767_dvs: s5m8767-dvs {
+                samsung,pins = "gpd1-0", "gpd1-1", "gpd1-2";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <1>;
+                samsung,pin-drv = <0>;
+        };
+        dp_hpd_gpio: dp-hpd-gpio {
+                samsung,pins = "gpc3-0";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        trackpad_irq: trackpad-irq {
+                samsung,pins = "gpx1-2";
+                samsung,pin-function = <0xf>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        power_key_irq: power-key-irq {
+                samsung,pins = "gpx1-3";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        ec_irq: ec-irq {
+                samsung,pins = "gpx1-6";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        s5m8767_ds: s5m8767-ds {
+                samsung,pins = "gpx2-3", "gpx2-4", "gpx2-5";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <1>;
+                samsung,pin-drv = <0>;
+        };
+        s5m8767_irq: s5m8767-irq {
+                samsung,pins = "gpx3-2";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        lid_irq: lid-irq {
+                samsung,pins = "gpx3-5";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        hdmi_hpd_irq: hdmi-hpd-irq {
+                samsung,pins = "gpx3-7";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <1>;
+                samsung,pin-drv = <0>;
+        };
+};
+&pinctrl_1 {
+        hsic_reset: hsic-reset {
+                samsung,pins = "gpe1-0";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+};
+&sd1_bus4 {
+        samsung,pin-drv = <0>;
+};
+&sd1_cd {
+        samsung,pin-drv = <0>;
+};
+&sd1_clk {
+        samsung,pin-drv = <0>;
+};
+&sd1_cmd {
+        samsung,pin-pud = <3>;
+        samsung,pin-drv = <0>;
+};
+&spi_1 {
+        status = "okay";
+        samsung,spi-src-clk = <0>;
+        num-cs = <1>;
+};
+#include "cros-ec-keyboard.dtsi"
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index d55c1a2eb798..d45a07ea3402 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -218,7 +218,7 @@
                clock-names = "fimg2d";
        };
-        codec@11000000 {
+        mfc: codec@11000000 {
                compatible = "samsung,mfc-v6";
                reg = <0x11000000 0x10000>;
                interrupts = <0 96 0>;
@@ -227,7 +227,7 @@
                clock-names = "mfc";
        };
-        rtc@101E0000 {
+        rtc: rtc@101E0000 {
                clocks = <&clock CLK_RTC>;
                clock-names = "rtc";
                status = "disabled";
@@ -261,7 +261,7 @@
                clock-names = "uart", "clk_uart_baud0";
        };
-        sata@122F0000 {
+        sata: sata@122F0000 {
                compatible = "snps,dwc-ahci";
                samsung,sata-freq = <66>;
                reg = <0x122F0000 0x1ff>;
@@ -293,6 +293,7 @@
                clock-names = "i2c";
                pinctrl-names = "default";
                pinctrl-0 = <&i2c0_bus>;
+                samsung,sysreg-phandle = <&sysreg_system_controller>;
                status = "disabled";
        };
@@ -306,6 +307,7 @@
                clock-names = "i2c";
                pinctrl-names = "default";
                pinctrl-0 = <&i2c1_bus>;
+                samsung,sysreg-phandle = <&sysreg_system_controller>;
                status = "disabled";
        };
@@ -319,6 +321,7 @@
                clock-names = "i2c";
                pinctrl-names = "default";
                pinctrl-0 = <&i2c2_bus>;
+                samsung,sysreg-phandle = <&sysreg_system_controller>;
                status = "disabled";
        };
@@ -332,6 +335,7 @@
                clock-names = "i2c";
                pinctrl-names = "default";
                pinctrl-0 = <&i2c3_bus>;
+                samsung,sysreg-phandle = <&sysreg_system_controller>;
                status = "disabled";
        };
@@ -573,7 +577,7 @@
                #phy-cells = <1>;
        };
-        usb@12110000 {
+        ehci: usb@12110000 {
                compatible = "samsung,exynos4210-ehci";
                reg = <0x12110000 0x100>;
                interrupts = <0 71 0>;
@@ -588,7 +592,7 @@
                };
        };
-        usb@12120000 {
+        ohci: usb@12120000 {
                compatible = "samsung,exynos4210-ohci";
                reg = <0x12120000 0x100>;
                interrupts = <0 71 0>;
@@ -710,7 +714,7 @@
                clock-names = "gscl";
        };
-        hdmi {
+        hdmi: hdmi {
                compatible = "samsung,exynos4212-hdmi";
                reg = <0x14530000 0x70000>;
                interrupts = <0 95 0>;
@@ -736,14 +740,14 @@
                #phy-cells = <0>;
        };
-        dp-controller@145B0000 {
+        dp: dp-controller@145B0000 {
                clocks = <&clock CLK_DP>;
                clock-names = "dp";
                phys = <&dp_phy>;
                phy-names = "dp";
        };
-        fimd@14400000 {
+        fimd: fimd@14400000 {
                clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
                clock-names = "sclk_fimd", "fimd";
        };
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 82cdb74484cc..9a050e19a4dc 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -12,6 +12,7 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/maxim,max77802.h>
 #include "exynos5420.dtsi"
 / {
@@ -151,7 +152,7 @@
        status = "okay";
        clock-frequency = <400000>;
-        max77802-pmic@9 {
+        max77802: max77802-pmic@9 {
                compatible = "maxim,max77802";
                interrupt-parent = <&gpx3>;
                interrupts = <1 IRQ_TYPE_NONE>;
@@ -560,7 +561,7 @@
        status = "okay";
        num-slots = <1>;
        broken-cd;
-        caps2-mmc-hs200-1_8v;
+        mmc-hs200-1_8v;
        cap-mmc-highspeed;
        non-removable;
        card-detect-delay = <200>;
@@ -727,6 +728,8 @@
 &rtc {
        status = "okay";
+        clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>;
+        clock-names = "rtc", "rtc_src";
 };
 &spi_2 {
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 8617a031cbc0..90bf4011e319 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -560,6 +560,7 @@
                clock-names = "i2c";
                pinctrl-names = "default";
                pinctrl-0 = <&i2c0_bus>;
+                samsung,sysreg-phandle = <&sysreg_system_controller>;
                status = "disabled";
        };
@@ -573,6 +574,7 @@
                clock-names = "i2c";
                pinctrl-names = "default";
                pinctrl-0 = <&i2c1_bus>;
+                samsung,sysreg-phandle = <&sysreg_system_controller>;
                status = "disabled";
        };
@@ -586,6 +588,7 @@
                clock-names = "i2c";
                pinctrl-names = "default";
                pinctrl-0 = <&i2c2_bus>;
+                samsung,sysreg-phandle = <&sysreg_system_controller>;
                status = "disabled";
        };
@@ -599,6 +602,7 @@
                clock-names = "i2c";
                pinctrl-names = "default";
                pinctrl-0 = <&i2c3_bus>;
+                samsung,sysreg-phandle = <&sysreg_system_controller>;
                status = "disabled";
        };
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 7bb1c8dd42dd..e8fdda827fc9 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -12,6 +12,7 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/maxim,max77802.h>
 #include "exynos5800.dtsi"
 / {
@@ -150,7 +151,7 @@
        status = "okay";
        clock-frequency = <400000>;
-        max77802-pmic@9 {
+        max77802: max77802-pmic@9 {
                compatible = "maxim,max77802";
                interrupt-parent = <&gpx3>;
                interrupts = <1 IRQ_TYPE_NONE>;
@@ -548,7 +549,7 @@
        status = "okay";
        num-slots = <1>;
        broken-cd;
-        caps2-mmc-hs200-1_8v;
+        mmc-hs200-1_8v;
        cap-mmc-highspeed;
        non-removable;
        card-detect-delay = <200>;
@@ -715,6 +716,8 @@
 &rtc {
        status = "okay";
+        clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>;
+        clock-names = "rtc", "rtc_src";
 };
 &spi_2 {
diff --git a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
index 05b44c272c9a..721b09238f58 100644
--- a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
+++ b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
@@ -51,3 +51,36 @@
 &uart0 {
        status = "okay";
 };
+&gmac0 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        phy-handle = <&phy2>;
+        phy-mode = "mii";
+        /* Placeholder, overwritten by bootloader */
+        mac-address = [00 00 00 00 00 00];
+        status = "okay";
+        phy2: ethernet-phy@2 {
+                reg = <2>;
+        };
+};
+&gmac1 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        phy-handle = <&phy1>;
+        phy-mode = "rgmii";
+        /* Placeholder, overwritten by bootloader */
+        mac-address = [00 00 00 00 00 00];
+        status = "okay";
+        phy1: ethernet-phy@1 {
+                reg = <1>;
+        };
+};
+&ahci {
+        phys = <&sata_phy>;
+        phy-names = "sata-phy";
+};
diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index f85ba2924ff7..c52722b14e4a 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -131,6 +131,249 @@
                                clock-names = "apb_pclk";
                                status = "disabled";
                        };
+                        gpio0: gpio@b20000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb20000 0x1000>;
+                                interrupts = <0 108 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+                        gpio1: gpio@b21000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb21000 0x1000>;
+                                interrupts = <0 109 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+                        gpio2: gpio@b22000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb22000 0x1000>;
+                                interrupts = <0 110 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+                        gpio3: gpio@b23000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb23000 0x1000>;
+                                interrupts = <0 111 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+                        gpio4: gpio@b24000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb24000 0x1000>;
+                                interrupts = <0 112 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+                        gpio5: gpio@004000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0x004000 0x1000>;
+                                interrupts = <0 113 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+                        gpio6: gpio@b26000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb26000 0x1000>;
+                                interrupts = <0 114 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+                        gpio7: gpio@b27000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb27000 0x1000>;
+                                interrupts = <0 115 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+                        gpio8: gpio@b28000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb28000 0x1000>;
+                                interrupts = <0 116 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+                        gpio9: gpio@b29000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb29000 0x1000>;
+                                interrupts = <0 117 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+                        gpio10: gpio@b2a000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb2a000 0x1000>;
+                                interrupts = <0 118 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+                        gpio11: gpio@b2b000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb2b000 0x1000>;
+                                interrupts = <0 119 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+                        gpio12: gpio@b2c000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb2c000 0x1000>;
+                                interrupts = <0 120 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+                        gpio13: gpio@b2d000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb2d000 0x1000>;
+                                interrupts = <0 121 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+                        gpio14: gpio@b2e000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb2e000 0x1000>;
+                                interrupts = <0 122 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+                        gpio15: gpio@b2f000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb2f000 0x1000>;
+                                interrupts = <0 123 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+                        gpio16: gpio@b30000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb30000 0x1000>;
+                                interrupts = <0 124 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+                        gpio17: gpio@b31000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb31000 0x1000>;
+                                interrupts = <0 125 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+                        wdt0: watchdog@a2c000 {
+                                compatible = "arm,sp805", "arm,primecell";
+                                arm,primecell-periphid = <0x00141805>;
+                                reg = <0xa2c000 0x1000>;
+                                interrupts = <0 29 4>;
+                                clocks = <&clock HIX5HD2_WDG0_RST>;
+                                clock-names = "apb_pclk";
+                        };
                };
                local_timer@00a00600 {
@@ -148,9 +391,15 @@
                };
                sysctrl: system-controller@00000000 {
-                        compatible = "hisilicon,sysctrl";
+                        compatible = "hisilicon,sysctrl", "syscon";
                        reg = <0x00000000 0x1000>;
-                        reboot-offset = <0x4>;
+                };
+                reboot {
+                        compatible = "syscon-reboot";
+                        regmap = <&sysctrl>;
+                        offset = <0x4>;
+                        mask = <0xdeadbeef>;
                };
                cpuctrl@00a22000 {
@@ -166,5 +415,142 @@
                                #clock-cells = <1>;
                        };
                };
+                /* unremovable emmc as mmcblk0 */
+                mmc: mmc@1830000 {
+                        compatible = "snps,dw-mshc";
+                        reg = <0x1830000 0x1000>;
+                        interrupts = <0 35 4>;
+                        clocks = <&clock HIX5HD2_MMC_CIU_RST>,
+                                 <&clock HIX5HD2_MMC_BIU_CLK>;
+                        clock-names = "ciu", "biu";
+                };
+                sd: mmc@1820000 {
+                        compatible = "snps,dw-mshc";
+                        reg = <0x1820000 0x1000>;
+                        interrupts = <0 34 4>;
+                        clocks = <&clock HIX5HD2_SD_CIU_RST>,
+                                 <&clock HIX5HD2_SD_BIU_CLK>;
+                        clock-names = "ciu","biu";
+                };
+                gmac0: ethernet@1840000 {
+                        compatible = "hisilicon,hix5hd2-gmac";
+                        reg = <0x1840000 0x1000>,<0x184300c 0x4>;
+                        interrupts = <0 71 4>;
+                        clocks = <&clock HIX5HD2_MAC0_CLK>;
+                        status = "disabled";
+                };
+                gmac1: ethernet@1841000 {
+                        compatible = "hisilicon,hix5hd2-gmac";
+                        reg = <0x1841000 0x1000>,<0x1843010 0x4>;
+                        interrupts = <0 72 4>;
+                        clocks = <&clock HIX5HD2_MAC1_CLK>;
+                        status = "disabled";
+                };
+                usb0: ehci@1890000 {
+                        compatible = "generic-ehci";
+                        reg = <0x1890000 0x1000>;
+                        interrupts = <0 66 4>;
+                        clocks = <&clock HIX5HD2_USB_CLK>;
+                };
+                usb1: ohci@1880000 {
+                        compatible = "generic-ohci";
+                        reg = <0x1880000 0x1000>;
+                        interrupts = <0 67 4>;
+                        clocks = <&clock HIX5HD2_USB_CLK>;
+                };
+                peripheral_ctrl: syscon@a20000 {
+                        compatible = "syscon";
+                        reg = <0xa20000 0x1000>;
+                };
+                sata_phy: phy@1900000 {
+                        compatible = "hisilicon,hix5hd2-sata-phy";
+                        reg = <0x1900000 0x10000>;
+                        #phy-cells = <0>;
+                        hisilicon,peripheral-syscon = <&peripheral_ctrl>;
+                        hisilicon,power-reg = <0x8 10>;
+                };
+                ahci: sata@1900000 {
+                        compatible = "hisilicon,hisi-ahci";
+                        reg = <0x1900000 0x10000>;
+                        interrupts = <0 70 4>;
+                        clocks = <&clock HIX5HD2_SATA_CLK>;
+                };
+                ir: ir@001000 {
+                        compatible = "hisilicon,hix5hd2-ir";
+                        reg = <0x001000 0x1000>;
+                        interrupts = <0 47 4>;
+                        clocks = <&clock HIX5HD2_FIXED_24M>;
+                        hisilicon,power-syscon = <&sysctrl>;
+                };
+                i2c0: i2c@b10000 {
+                        compatible = "hisilicon,hix5hd2-i2c";
+                        reg = <0xb10000 0x1000>;
+                        interrupts = <0 38 4>;
+                        clocks = <&clock HIX5HD2_I2C0_RST>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+                i2c1: i2c@b11000 {
+                        compatible = "hisilicon,hix5hd2-i2c";
+                        reg = <0xb11000 0x1000>;
+                        interrupts = <0 39 4>;
+                        clocks = <&clock HIX5HD2_I2C1_RST>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+                i2c2: i2c@b12000 {
+                        compatible = "hisilicon,hix5hd2-i2c";
+                        reg = <0xb12000 0x1000>;
+                        interrupts = <0 40 4>;
+                        clocks = <&clock HIX5HD2_I2C2_RST>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+                i2c3: i2c@b13000 {
+                        compatible = "hisilicon,hix5hd2-i2c";
+                        reg = <0xb13000 0x1000>;
+                        interrupts = <0 41 4>;
+                        clocks = <&clock HIX5HD2_I2C3_RST>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+                i2c4: i2c@b16000 {
+                        compatible = "hisilicon,hix5hd2-i2c";
+                        reg = <0xb16000 0x1000>;
+                        interrupts = <0 43 4>;
+                        clocks = <&clock HIX5HD2_I2C4_RST>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+                i2c5: i2c@b17000 {
+                        compatible = "hisilicon,hix5hd2-i2c";
+                        reg = <0xb17000 0x1000>;
+                        interrupts = <0 44 4>;
+                        clocks = <&clock HIX5HD2_I2C5_RST>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 92660e1fe1fc..c0116cffc513 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -214,7 +214,9 @@
                                        compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
                                        reg = <0x70014000 0x4000>;
                                        interrupts = <30>;
-                                        clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
+                                        clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
+                                                 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
+                                        clock-names = "ipg", "baud";
                                        dmas = <&sdma 24 1 0>,
                                               <&sdma 25 1 0>;
                                        dma-names = "rx", "tx";
@@ -504,7 +506,9 @@
                                compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
                                reg = <0x83fcc000 0x4000>;
                                interrupts = <29>;
-                                clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
+                                clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
+                                         <&clks IMX5_CLK_SSI1_ROOT_GATE>;
+                                clock-names = "ipg", "baud";
                                dmas = <&sdma 28 0 0>,
                                       <&sdma 29 0 0>;
                                dma-names = "rx", "tx";
@@ -560,7 +564,9 @@
                                compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
                                reg = <0x83fe8000 0x4000>;
                                interrupts = <96>;
-                                clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
+                                clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
+                                         <&clks IMX5_CLK_SSI3_ROOT_GATE>;
+                                clock-names = "ipg", "baud";
                                dmas = <&sdma 46 0 0>,
                                       <&sdma 47 0 0>;
                                dma-names = "rx", "tx";
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index f91725b2e8ab..a30bddfdbdb6 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -46,10 +46,21 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
-                cpu@0 {
+                cpu0: cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a8";
                        reg = <0x0>;
+                        clocks = <&clks IMX5_CLK_ARM>;
+                        clock-latency = <61036>;
+                        voltage-tolerance = <5>;
+                        operating-points = <
+                                /* kHz */
+                                 166666  850000
+                                 400000  900000
+                                 800000 1050000
+                                1000000 1200000
+                                1200000 1300000
+                        >;
                };
        };
@@ -227,7 +238,9 @@
                                                        "fsl,imx21-ssi";
                                        reg = <0x50014000 0x4000>;
                                        interrupts = <30>;
-                                        clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
+                                        clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
+                                                 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
+                                        clock-names = "ipg", "baud";
                                        dmas = <&sdma 24 1 0>,
                                               <&sdma 25 1 0>;
                                        dma-names = "rx", "tx";
@@ -675,7 +688,9 @@
                                                "fsl,imx21-ssi";
                                reg = <0x63fcc000 0x4000>;
                                interrupts = <29>;
-                                clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
+                                clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
+                                         <&clks IMX5_CLK_SSI1_ROOT_GATE>;
+                                clock-names = "ipg", "baud";
                                dmas = <&sdma 28 0 0>,
                                       <&sdma 29 0 0>;
                                dma-names = "rx", "tx";
@@ -703,7 +718,9 @@
                                                "fsl,imx21-ssi";
                                reg = <0x63fe8000 0x4000>;
                                interrupts = <96>;
-                                clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
+                                clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
+                                         <&clks IMX5_CLK_SSI3_ROOT_GATE>;
+                                clock-names = "ipg", "baud";
                                dmas = <&sdma 46 0 0>,
                                       <&sdma 47 0 0>;
                                dma-names = "rx", "tx";
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index b453e0e28aee..1ac2fe732867 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -13,6 +13,10 @@
 #include "imx6qdl.dtsi"
 / {
+        aliases {
+                i2c3 = &i2c4;
+        };
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -114,3 +118,7 @@
                      "di0_sel", "di1_sel",
                      "di0", "di1";
 };
+&vpu {
+        compatible = "fsl,imx6dl-vpu", "cnm,coda960";
+};
diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts
new file mode 100644
index 000000000000..a43abfa21e33
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-tbs2910.dts
@@ -0,0 +1,432 @@
+/*
+ * Copyright 2014 Soeren Moch <smoch@web.de>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include "imx6q.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+/ {
+        model = "TBS2910 Matrix ARM mini PC";
+        compatible = "tbs,imx6q-tbs2910", "fsl,imx6q";
+        chosen {
+                stdout-path = &uart1;
+        };
+        memory {
+                reg = <0x10000000 0x80000000>;
+        };
+        fan {
+                compatible = "gpio-fan";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_fan>;
+                gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
+                gpio-fan,speed-map = <0    0
+                                      3000 1>;
+        };
+        ir_recv {
+                compatible = "gpio-ir-receiver";
+                gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_ir>;
+        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_leds>;
+                blue {
+                        label = "blue_status_led";
+                        gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+                        default-state = "keep";
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_2p5v: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "2P5V";
+                        regulator-min-microvolt = <2500000>;
+                        regulator-max-microvolt = <2500000>;
+                };
+                reg_3p3v: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                };
+                reg_5p0v: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "5P0V";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                };
+        };
+        sound-sgtl5000 {
+                audio-codec = <&sgtl5000>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "Headphone Jack", "HP_OUT";
+                compatible = "fsl,imx-audio-sgtl5000";
+                model = "On-board Codec";
+                mux-ext-port = <3>;
+                mux-int-port = <1>;
+                ssi-controller = <&ssi1>;
+        };
+        sound-spdif {
+                compatible = "fsl,imx-audio-spdif";
+                model = "On-board SPDIF";
+                spdif-controller = <&spdif>;
+                spdif-out;
+        };
+};
+&audmux {
+        status = "okay";
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-mode = "rgmii";
+        phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
+&hdmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hdmi>;
+        ddc-i2c-bus = <&i2c2>;
+        status = "okay";
+};
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+        sgtl5000: sgtl5000@0a {
+                clocks = <&clks 201>;
+                compatible = "fsl,sgtl5000";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_sgtl5000>;
+                reg = <0x0a>;
+                VDDA-supply = <&reg_2p5v>;
+                VDDIO-supply = <&reg_3p3v>;
+        };
+};
+&i2c2 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+};
+&i2c3 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        status = "okay";
+        rtc: ds1307@68 {
+                compatible = "dallas,ds1307";
+                reg = <0x68>;
+        };
+};
+&pcie {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pcie>;
+        reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
+&sata {
+        status = "okay";
+};
+&snvs_poweroff {
+        status = "okay";
+};
+&spdif {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_spdif>;
+        status = "okay";
+};
+&ssi1 {
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+&usbh1 {
+        vbus-supply = <&reg_5p0v>;
+        status = "okay";
+};
+&usbotg {
+        vbus-supply = <&reg_5p0v>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        disable-over-current;
+        status = "okay";
+};
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2>;
+        bus-width = <4>;
+        cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        bus-width = <4>;
+        cd-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
+        wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
+&usdhc4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc4>;
+        bus-width = <8>;
+        non-removable;
+        no-1-8-v;
+        status = "okay";
+};
+&iomuxc {
+        imx6q-tbs2910 {
+                pinctrl_enet: enetgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+                                MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+                                MX6QDL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
+                                MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25    0x1b059
+                        >;
+                };
+                pinctrl_hdmi: hdmigrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_CSI0_DAT9__I2C1_SCL        0x4001b8b1
+                                MX6QDL_PAD_CSI0_DAT8__I2C1_SDA        0x4001b8b1
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL3__I2C2_SCL         0x4001b8b1
+                                MX6QDL_PAD_KEY_ROW3__I2C2_SDA         0x4001b8b1
+                        >;
+                };
+                pinctrl_i2c3: i2c3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_3__I2C3_SCL           0x4001b8b1
+                                MX6QDL_PAD_GPIO_6__I2C3_SDA           0x4001b8b1
+                        >;
+                };
+                pinctrl_ir: irgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D18__GPIO3_IO18        0x17059
+                        >;
+                };
+                pinctrl_pcie: pciegrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_17__GPIO7_IO12        0x17059
+                        >;
+                };
+                pinctrl_sgtl5000: sgtl5000grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_CSI0_DAT7__AUD3_RXD        0x130b0
+                                MX6QDL_PAD_CSI0_DAT4__AUD3_TXC        0x130b0
+                                MX6QDL_PAD_CSI0_DAT5__AUD3_TXD        0x110b0
+                                MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS       0x130b0
+                                MX6QDL_PAD_GPIO_0__CCM_CLKO1          0x130b0
+                        >;
+                };
+                pinctrl_spdif: spdifgrp {
+                        fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT     0x13091
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA  0x1b0b1
+                                MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA  0x1b0b1
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D26__UART2_TX_DATA     0x1b0b1
+                                MX6QDL_PAD_EIM_D27__UART2_RX_DATA     0x1b0b1
+                        >;
+                };
+                pinctrl_usbotg: usbotggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID     0x17059
+                        >;
+                };
+                pinctrl_usdhc2: usdhc2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD2_CMD__SD2_CMD           0x17059
+                                MX6QDL_PAD_SD2_CLK__SD2_CLK           0x10059
+                                MX6QDL_PAD_SD2_DAT0__SD2_DATA0        0x17059
+                                MX6QDL_PAD_SD2_DAT1__SD2_DATA1        0x17059
+                                MX6QDL_PAD_SD2_DAT2__SD2_DATA2        0x17059
+                                MX6QDL_PAD_SD2_DAT3__SD2_DATA3        0x17059
+                                MX6QDL_PAD_NANDF_D2__GPIO2_IO02       0x17059
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CMD__SD3_CMD           0x17059
+                                MX6QDL_PAD_SD3_CLK__SD3_CLK           0x10059
+                                MX6QDL_PAD_SD3_DAT0__SD3_DATA0        0x17059
+                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1        0x17059
+                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2        0x17059
+                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3        0x17059
+                                MX6QDL_PAD_NANDF_D0__GPIO2_IO00       0x17059
+                                MX6QDL_PAD_NANDF_D1__GPIO2_IO01       0x17059
+                        >;
+                };
+                pinctrl_usdhc4: usdhc4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD4_CMD__SD4_CMD           0x17059
+                                MX6QDL_PAD_SD4_CLK__SD4_CLK           0x10059
+                                MX6QDL_PAD_SD4_DAT0__SD4_DATA0        0x17059
+                                MX6QDL_PAD_SD4_DAT1__SD4_DATA1        0x17059
+                                MX6QDL_PAD_SD4_DAT2__SD4_DATA2        0x17059
+                                MX6QDL_PAD_SD4_DAT3__SD4_DATA3        0x17059
+                                MX6QDL_PAD_SD4_DAT4__SD4_DATA4        0x17059
+                                MX6QDL_PAD_SD4_DAT5__SD4_DATA5        0x17059
+                                MX6QDL_PAD_SD4_DAT6__SD4_DATA6        0x17059
+                                MX6QDL_PAD_SD4_DAT7__SD4_DATA7        0x17059
+                        >;
+                };
+        };
+        gpio_fan {
+                pinctrl_gpio_fan: gpiofangrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D28__GPIO3_IO28        0x130b1
+                        >;
+                };
+        };
+        gpio_leds {
+                pinctrl_gpio_leds: gpioledsgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_2__GPIO1_IO02         0x130b1
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index e9f3646d1760..85f72e6b5bad 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -308,3 +308,7 @@
                };
        };
 };
+&vpu {
+        compatible = "fsl,imx6q-vpu", "cnm,coda960";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index d3c0bf5c84e3..b5756c21ea1d 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -282,7 +282,6 @@
 };
 &ssi1 {
-        fsl,mode = "i2s-slave";
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index cade1bdc97e9..86f03c1b147c 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -287,7 +287,6 @@
 };
 &ssi1 {
-        fsl,mode = "i2s-slave";
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index cf13239a1619..4a8d97f47759 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -376,12 +376,10 @@
 };
 &ssi1 {
-        fsl,mode = "i2s-slave";
        status = "okay";
 };
 &ssi2 {
-        fsl,mode = "i2s-slave";
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
index 584721264121..585b4f6986c1 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
@@ -9,17 +9,103 @@
 * http://www.gnu.org/copyleft/gpl.html
 */
+#include <dt-bindings/sound/fsl-imx-audmux.h>
 / {
        chosen {
                linux,stdout-path = &uart4;
        };
+        regulators {
+                sound_1v8: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "i2s-audio-1v8";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                };
+                sound_3v3: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "i2s-audio-3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                };
+        };
+        tlv320_mclk: oscillator {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <19200000>;
+                clock-output-names = "tlv320-mclk";
+        };
+        sound {
+                compatible = "simple-audio-card";
+                simple-audio-card,name = "OnboardTLV320AIC3007";
+                simple-audio-card,format = "i2s";
+                simple-audio-card,bitclock-master = <&dailink_master>;
+                simple-audio-card,frame-master = <&dailink_master>;
+                simple-audio-card,widgets =
+                        "Microphone", "Mic Jack",
+                        "Line", "Line In",
+                        "Line", "Line Out",
+                        "Speaker", "Speaker",
+                        "Headphone", "Headphone Jack";
+                simple-audio-card,routing =
+                        "Line Out", "LLOUT",
+                        "Line Out", "RLOUT",
+                        "Speaker", "SPOP",
+                        "Speaker", "SPOM",
+                        "Headphone Jack", "HPLOUT",
+                        "Headphone Jack", "HPROUT",
+                        "MIC3L", "Mic Jack",
+                        "MIC3R", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "LINE1L", "Line In",
+                        "LINE1R", "Line In";
+                simple-audio-card,cpu {
+                        sound-dai = <&ssi2>;
+                };
+                dailink_master: simple-audio-card,codec {
+                        sound-dai = <&codec>;
+                        clocks = <&tlv320_mclk>;
+                };
+        };
 };
-&fec {
+&audmux {
        status = "okay";
+        ssi2 {
+                fsl,audmux-port = <1>;
+                fsl,port-config = <
+                        (IMX_AUDMUX_V2_PTCR_TFSDIR |
+                        IMX_AUDMUX_V2_PTCR_TFSEL(4) |
+                        IMX_AUDMUX_V2_PTCR_TCLKDIR |
+                        IMX_AUDMUX_V2_PTCR_TCSEL(4))
+                        IMX_AUDMUX_V2_PDCR_RXDSEL(4)
+                >;
+        };
+        pins5 {
+                fsl,audmux-port = <4>;
+                fsl,port-config = <
+                        0x00000000
+                        IMX_AUDMUX_V2_PDCR_RXDSEL(1)
+                >;
+        };
 };
-&gpmi {
+&can1 {
+        status = "okay";
+};
+&fec {
        status = "okay";
 };
@@ -28,14 +114,18 @@
 };
 &i2c2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c2>;
-        clock-frequency = <100000>;
        status = "okay";
-        tlv320@18 {
+        codec: tlv320@18 {
-                compatible = "ti,tlv320aic3x";
+                compatible = "ti,tlv320aic3007";
+                #sound-dai-cells = <0>;
                reg = <0x18>;
+                ai3x-micbias-vg = <2>;
+                AVDD-supply = <&sound_3v3>;
+                IOVDD-supply = <&sound_3v3>;
+                DRVDD-supply = <&sound_3v3>;
+                DVDD-supply = <&sound_1v8>;
        };
        stmpe@41 {
@@ -55,9 +145,14 @@
 };
 &i2c3 {
-        pinctrl-names = "default";
+        status = "okay";
-        pinctrl-0 = <&pinctrl_i2c3>;
+};
-        clock-frequency = <100000>;
+&pcie {
+        status = "okay";
+};
+&ssi2 {
        status = "okay";
 };
@@ -84,19 +179,3 @@
 &usdhc3 {
        status = "okay";
 };
-&iomuxc {
-        pinctrl_i2c2: i2c2grp {
-                fsl,pins = <
-                        MX6QDL_PAD_EIM_EB2__I2C2_SCL            0x4001b8b1
-                        MX6QDL_PAD_EIM_D16__I2C2_SDA            0x4001b8b1
-                >;
-        };
-        pinctrl_i2c3: i2c3grp {
-                fsl,pins = <
-                        MX6QDL_PAD_EIM_D17__I2C3_SCL            0x4001b8b1
-                        MX6QDL_PAD_EIM_D18__I2C3_SDA            0x4001b8b1
-                >;
-        };
-};
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index 0e50bb0a6b94..19cc269a08d4 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -58,6 +58,18 @@
        };
 };
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux>;
+        status = "disabled";
+};
+&can1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_flexcan1>;
+        status = "disabled";
+};
 &ecspi3 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_ecspi3>;
@@ -72,6 +84,22 @@
        };
 };
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-mode = "rgmii";
+        phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+        phy-supply = <&vdd_eth_io_reg>;
+        status = "disabled";
+};
+&gpmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpmi_nand>;
+        nand-on-flash-bbt;
+        status = "okay";
+};
 &i2c1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_i2c1>;
@@ -85,8 +113,8 @@
        pmic@58 {
                compatible = "dlg,da9063";
                reg = <0x58>;
-                interrupt-parent = <&gpio4>;
+                interrupt-parent = <&gpio2>;
-                interrupts = <17 0x8>; /* active-low GPIO4_17 */
+                interrupts = <9 0x8>; /* active-low GPIO2_9 */
                regulators {
                        vddcore_reg: bcore1 {
@@ -162,6 +190,18 @@
        };
 };
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        clock-frequency = <100000>;
+};
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        clock-frequency = <100000>;
+};
 &iomuxc {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hog>;
@@ -171,7 +211,7 @@
                        fsl,pins = <
                                MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
                                MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
-                                MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000 /* PMIC interrupt */
+                                MX6QDL_PAD_SD4_DAT1__GPIO2_IO09  0x80000000 /* PMIC interrupt */
                                MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */
                                MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */
                        >;
@@ -206,6 +246,13 @@
                        >;
                };
+                pinctrl_flexcan1: flexcan1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b0
+                                MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b0
+                        >;
+                };
                pinctrl_gpmi_nand: gpminandgrp {
                        fsl,pins = <
                                MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
@@ -235,6 +282,24 @@
                        >;
                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_EB2__I2C2_SCL            0x4001b8b1
+                                MX6QDL_PAD_EIM_D16__I2C2_SDA            0x4001b8b1
+                        >;
+                };
+                pinctrl_i2c3: i2c3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D17__I2C3_SCL            0x4001b8b1
+                                MX6QDL_PAD_EIM_D18__I2C3_SDA            0x4001b8b1
+                        >;
+                };
+                pinctrl_pcie: pciegrp {
+                        fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000>;
+                };
                pinctrl_uart3: uart3grp {
                        fsl,pins = <
                                MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
@@ -293,22 +358,22 @@
                                MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
                        >;
                };
-        };
-};
-&fec {
+                pinctrl_audmux: audmuxgrp {
-        pinctrl-names = "default";
+                        fsl,pins = <
-        pinctrl-0 = <&pinctrl_enet>;
+                                MX6QDL_PAD_DISP0_DAT16__AUD5_TXC        0x130b0
-        phy-mode = "rgmii";
+                                MX6QDL_PAD_DISP0_DAT17__AUD5_TXD        0x110b0
-        phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+                                MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS       0x130b0
-        phy-supply = <&vdd_eth_io_reg>;
+                                MX6QDL_PAD_DISP0_DAT19__AUD5_RXD        0x130b0
-        status = "disabled";
+                        >;
+                };
+        };
 };
-&gpmi {
+&pcie {
-        pinctrl-names = "default";
+        pinctrl-name = "default";
-        pinctrl-0 = <&pinctrl_gpmi_nand>;
+        pinctrl-0 = <&pinctrl_pcie>;
-        nand-on-flash-bbt;
+        reset-gpio = <&gpio4 17 0>;
        status = "disabled";
 };
diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/imx6qdl-rex.dtsi
index df7bcf86c156..488a640796ac 100644
--- a/arch/arm/boot/dts/imx6qdl-rex.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-rex.dtsi
@@ -308,7 +308,6 @@
 };
 &ssi1 {
-        fsl,mode = "i2s-slave";
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index baf2f00d519a..f1cd2147421d 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -107,10 +107,8 @@
                        "Headphone Jack", "HPOUTR",
                        "Ext Spk", "SPKOUTL",
                        "Ext Spk", "SPKOUTR",
-                        "MICBIAS", "AMIC",
+                        "AMIC", "MICBIAS",
-                        "IN3R", "MICBIAS",
+                        "IN3R", "AMIC";
-                        "DMIC", "MICBIAS",
-                        "DMICDAT", "DMIC";
                mux-int-port = <2>;
                mux-ext-port = <3>;
        };
@@ -179,7 +177,7 @@
        codec: wm8962@1a {
                compatible = "wlf,wm8962";
                reg = <0x1a>;
-                clocks = <&clks 201>;
+                clocks = <&clks IMX6QDL_CLK_CKO>;
                DCVDD-supply = <&reg_audio>;
                DBVDD-supply = <&reg_audio>;
                AVDD-supply = <&reg_audio>;
@@ -531,6 +529,10 @@
        status = "okay";
 };
+&snvs_poweroff {
+        status = "okay";
+};
 &ssi2 {
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 9596ed5867e6..4fc03b7f1cee 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -333,9 +333,17 @@
                        };
                        vpu: vpu@02040000 {
+                                compatible = "cnm,coda960";
                                reg = <0x02040000 0x3c000>;
                                interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
                                             <0 12 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "bit", "jpeg";
+                                clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
+                                         <&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
+                                         <&clks IMX6QDL_CLK_OCRAM>;
+                                clock-names = "per", "ahb", "ocram";
+                                resets = <&src 1>;
+                                iram = <&ocram>;
                        };
                        aipstz@0207c000 { /* AIPSTZ1 */
@@ -657,6 +665,12 @@
                                        interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
                                                     <0 20 IRQ_TYPE_LEVEL_HIGH>;
                                };
+                                snvs_poweroff: snvs-poweroff@38 {
+                                        compatible = "fsl,sec-v4.0-poweroff";
+                                        reg = <0x38 0x4>;
+                                        status = "disabled";
+                                };
                        };
                        epit1: epit@020d0000 { /* EPIT1 */
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index 898d14fd765f..fda4932faefd 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -580,6 +580,10 @@
        status = "okay";
 };
+&snvs_poweroff {
+        status = "okay";
+};
 &ssi2 {
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index dfd83e6d8087..36ab8e054cee 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -574,6 +574,12 @@
                                        interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
                                                     <0 20 IRQ_TYPE_LEVEL_HIGH>;
                                };
+                                snvs_poweroff: snvs-poweroff@38 {
+                                        compatible = "fsl,sec-v4.0-poweroff";
+                                        reg = <0x38 0x4>;
+                                        status = "disabled";
+                                };
                        };
                        epit1: epit@020d0000 {
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index 82d6b34527b7..1e6e5cc1c14c 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -105,6 +105,30 @@
                        gpio = <&gpio3 27 0>;
                        enable-active-high;
                };
+                reg_peri_3v3: regulator@5 {
+                        compatible = "regulator-fixed";
+                        reg = <5>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_peri_3v3>;
+                        regulator-name = "peri_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        regulator-always-on;
+                };
+                reg_enet_3v3: regulator@6 {
+                        compatible = "regulator-fixed";
+                        reg = <6>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_enet_3v3>;
+                        regulator-name = "enet_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
+                };
        };
        sound {
@@ -133,6 +157,14 @@
 &fec1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet1>;
+        phy-supply = <&reg_enet_3v3>;
+        phy-mode = "rgmii";
+        status = "okay";
+};
+&fec2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet2>;
        phy-mode = "rgmii";
        status = "okay";
 };
@@ -304,6 +336,10 @@
        status = "okay";
 };
+&snvs_poweroff {
+        status = "okay";
+};
 &ssi2 {
        status = "okay";
 };
@@ -394,6 +430,30 @@
                                MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2   0x3081
                                MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3   0x3081
                                MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x3081
+                                MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M       0x91
+                        >;
+                };
+                pinctrl_enet_3v3: enet3v3grp {
+                        fsl,pins = <
+                                MX6SX_PAD_ENET2_COL__GPIO2_IO_6         0x80000000
+                        >;
+                };
+                pinctrl_enet2: enet2grp {
+                        fsl,pins = <
+                                MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0xa0b9
+                                MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0xa0b1
+                                MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0xa0b1
+                                MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2   0xa0b1
+                                MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3   0xa0b1
+                                MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0xa0b1
+                                MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK      0x3081
+                                MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
+                                MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
+                                MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2   0x3081
+                                MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3   0x3081
+                                MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
                        >;
                };
@@ -452,6 +512,12 @@
                        >;
                };
+                pinctrl_peri_3v3: peri3v3grp {
+                        fsl,pins = <
+                                MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16     0x80000000
+                        >;
+                };
                pinctrl_pwm3: pwm3grp-1 {
                        fsl,pins = <
                                MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index f3e88c03b1e4..7a24fee1e7ae 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -671,6 +671,12 @@
                                        reg = <0x34 0x58>;
                                        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
                                };
+                                snvs_poweroff: snvs-poweroff@38 {
+                                        compatible = "fsl,sec-v4.0-poweroff";
+                                        reg = <0x38 0x4>;
+                                        status = "disabled";
+                                };
                        };
                        epit1: epit@020d0000 {
@@ -877,7 +883,7 @@
                        };
                        fec2: ethernet@021b4000 {
-                                compatible = "fsl,imx6sx-fec";
+                                compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
                                reg = <0x021b4000 0x4000>;
                                interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
                                             <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi
index 88e3d477bf16..28e38f8c6b0f 100644
--- a/arch/arm/boot/dts/integrator.dtsi
+++ b/arch/arm/boot/dts/integrator.dtsi
@@ -6,8 +6,18 @@
 / {
        core-module@10000000 {
-                compatible = "arm,core-module-integrator";
+                compatible = "arm,core-module-integrator", "syscon";
                reg = <0x10000000 0x200>;
+                /* Use core module LED to indicate CPU load */
+                led@0c.0 {
+                        compatible = "register-bit-led";
+                        offset = <0x0c>;
+                        mask = <0x01>;
+                        label = "integrator:core_module";
+                        linux,default-trigger = "cpu0";
+                        default-state = "on";
+                };
        };
        ebi@12000000 {
@@ -82,5 +92,41 @@
                        reg = <0x19000000 0x1000>;
                        interrupts = <4>;
                };
+                syscon {
+                        /* Debug registers mapped as syscon */
+                        compatible = "syscon";
+                        reg = <0x1a000000 0x10>;
+                        led@04.0 {
+                                compatible = "register-bit-led";
+                                offset = <0x04>;
+                                mask = <0x01>;
+                                label = "integrator:green0";
+                                linux,default-trigger = "heartbeat";
+                                default-state = "on";
+                        };
+                        led@04.1 {
+                                compatible = "register-bit-led";
+                                offset = <0x04>;
+                                mask = <0x02>;
+                                label = "integrator:yellow";
+                                default-state = "off";
+                        };
+                        led@04.2 {
+                                compatible = "register-bit-led";
+                                offset = <0x04>;
+                                mask = <0x04>;
+                                label = "integrator:red";
+                                default-state = "off";
+                        };
+                        led@04.3 {
+                                compatible = "register-bit-led";
+                                offset = <0x04>;
+                                mask = <0x08>;
+                                label = "integrator:green1";
+                                default-state = "off";
+                        };
+                };
        };
 };
diff --git a/arch/arm/boot/dts/k2e-evm.dts b/arch/arm/boot/dts/k2e-evm.dts
index c568f067604d..560d62150ade 100644
--- a/arch/arm/boot/dts/k2e-evm.dts
+++ b/arch/arm/boot/dts/k2e-evm.dts
@@ -139,3 +139,15 @@
                };
        };
 };
+&mdio {
+        ethphy0: ethernet-phy@0 {
+                compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
+                reg = <0>;
+        };
+        ethphy1: ethernet-phy@1 {
+                compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
+                reg = <1>;
+        };
+};
diff --git a/arch/arm/boot/dts/k2e.dtsi b/arch/arm/boot/dts/k2e.dtsi
index c358b4b9a073..5fc14683d6df 100644
--- a/arch/arm/boot/dts/k2e.dtsi
+++ b/arch/arm/boot/dts/k2e.dtsi
@@ -85,6 +85,51 @@
                        #gpio-cells = <2>;
                        gpio,syscon-dev = <&devctrl 0x240>;
                };
+                pcie@21020000 {
+                        compatible = "ti,keystone-pcie","snps,dw-pcie";
+                        clocks = <&clkpcie1>;
+                        clock-names = "pcie";
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        reg =  <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
+                        ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000
+                                0x82000000 0 0x60000000 0x60000000 0 0x10000000>;
+                        device_type = "pci";
+                        num-lanes = <2>;
+                        #interrupt-cells = <1>;
+                        interrupt-map-mask = <0 0 0 7>;
+                        interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */
+                                        <0 0 0 2 &pcie_intc1 1>, /* INT B */
+                                        <0 0 0 3 &pcie_intc1 2>, /* INT C */
+                                        <0 0 0 4 &pcie_intc1 3>; /* INT D */
+                        pcie_msi_intc1: msi-interrupt-controller {
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 379 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 380 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 381 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 382 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 383 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 384 IRQ_TYPE_EDGE_RISING>;
+                        };
+                        pcie_intc1: legacy-interrupt-controller {
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>;
+                        };
+                };
        };
 };
diff --git a/arch/arm/boot/dts/k2l-evm.dts b/arch/arm/boot/dts/k2l-evm.dts
index fec43128a2e0..85cc7f2872d7 100644
--- a/arch/arm/boot/dts/k2l-evm.dts
+++ b/arch/arm/boot/dts/k2l-evm.dts
@@ -116,3 +116,15 @@
                };
        };
 };
+&mdio {
+        ethphy0: ethernet-phy@0 {
+                compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
+                reg = <0>;
+        };
+        ethphy1: ethernet-phy@1 {
+                compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
+                reg = <1>;
+        };
+};
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index 5d3e83fa2242..c06542b2c954 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -285,5 +285,50 @@
                        #interrupt-cells = <1>;
                        ti,syscon-dev = <&devctrl 0x2a0>;
                };
+                pcie@21800000 {
+                        compatible = "ti,keystone-pcie", "snps,dw-pcie";
+                        clocks = <&clkpcie>;
+                        clock-names = "pcie";
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        reg =  <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
+                        ranges = <0x81000000 0 0 0x23250000 0 0x4000
+                                0x82000000 0 0x50000000 0x50000000 0 0x10000000>;
+                        device_type = "pci";
+                        num-lanes = <2>;
+                        #interrupt-cells = <1>;
+                        interrupt-map-mask = <0 0 0 7>;
+                        interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
+                                        <0 0 0 2 &pcie_intc0 1>, /* INT B */
+                                        <0 0 0 3 &pcie_intc0 2>, /* INT C */
+                                        <0 0 0 4 &pcie_intc0 3>; /* INT D */
+                        pcie_msi_intc0: msi-interrupt-controller {
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
+                        };
+                        pcie_intc0: legacy-interrupt-controller {
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
+                        };
+                };
        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-dir665.dts b/arch/arm/boot/dts/kirkwood-dir665.dts
new file mode 100644
index 000000000000..786959ee9cbe
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dir665.dts
@@ -0,0 +1,278 @@
+/*
+ * Copyright (C) 2014 Claudio Leite <leitec@staticky.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+/ {
+        model = "D-Link DIR-665";
+        compatible = "dlink,dir-665", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>; /* 128 MB */
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                stdout-path = &uart0;
+        };
+        mbus {
+                pcie-controller {
+                        status = "okay";
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+        ocp@f1000000 {
+                pinctrl: pin-controller@10000 {
+                        pinctrl-0 =< &pmx_led_usb
+                                     &pmx_led_internet_blue
+                                     &pmx_led_internet_amber
+                                     &pmx_led_5g &pmx_led_status_blue
+                                     &pmx_led_wps &pmx_led_status_amber
+                                     &pmx_led_24g
+                                     &pmx_btn_restart &pmx_btn_wps>;
+                        pinctrl-names = "default";
+                        pmx_led_usb: pmx-led-usb {
+                                marvell,pins = "mpp12";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_internet_blue: pmx-led-internet-blue {
+                                marvell,pins = "mpp42";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_internet_amber: pmx-led-internet-amber {
+                                marvell,pins = "mpp43";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_5g: pmx-led-5g {
+                                marvell,pins = "mpp44";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_status_blue: pmx-led-status-blue {
+                                marvell,pins = "mpp45";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_wps: pmx-led-wps {
+                                marvell,pins = "mpp47";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_status_amber: pmx-led-status-amber {
+                                marvell,pins = "mpp48";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_24g: pmx-led-24g {
+                                marvell,pins = "mpp49";
+                                marvell,function = "gpio";
+                        };
+                        pmx_btn_restart: pmx-btn-restart {
+                                marvell,pins = "mpp28";
+                                marvell,function = "gpio";
+                        };
+                        pmx_btn_wps: pmx-btn-wps {
+                                marvell,pins = "mpp46";
+                                marvell,function = "gpio";
+                        };
+                };
+                spi@10600 {
+                        status = "okay";
+                        m25p80@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "mxicy,mx25l12805d";
+                                spi-max-frequency = <50000000>;
+                                reg = <0>;
+                                partition@0 {
+                                        label = "uboot";
+                                        reg = <0x0 0x30000>;
+                                        read-only;
+                                };
+                                partition@30000 {
+                                        label = "nvram";
+                                        reg = <0x30000 0x10000>;
+                                        read-only;
+                                };
+                                partition@40000 {
+                                        label = "kernel";
+                                        reg = <0x40000 0x180000>;
+                                };
+                                partition@1c0000 {
+                                        label = "rootfs";
+                                        reg = <0x1c0000 0xe00000>;
+                                };
+                                cal_data: partition@fc0000 {
+                                        label = "cal_data";
+                                        reg = <0xfc0000 0x10000>;
+                                        read-only;
+                                };
+                                partition@fd0000 {
+                                        label = "lang_pack";
+                                        reg = <0xfd0000 0x30000>;
+                                        read-only;
+                                };
+                        };
+                };
+                serial@12000 {
+                        status = "okay";
+                };
+                i2c@11000 {
+                        status = "okay";
+                };
+                ehci@50000 {
+                        status = "okay";
+                };
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+                blue-usb {
+                        label = "dir665:blue:usb";
+                        gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+                };
+                blue-internet {
+                        /* Can only be turned on if the Internet
+                         * Ethernet port has Link
+                         */
+                        label = "dir665:blue:internet";
+                        gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+                };
+                amber-internet {
+                        label = "dir665:amber:internet";
+                        gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+                };
+                blue-wifi5g {
+                        label = "dir665:blue:5g";
+                        gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+                };
+                blue-status {
+                        label = "dir665:blue:status";
+                        gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+                };
+                blue-wps {
+                        label = "dir665:blue:wps";
+                        gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+                };
+                amber-status {
+                        label = "dir665:amber:status";
+                        gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
+                };
+                blue-24g {
+                        label = "dir665:blue:24g";
+                        gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reset {
+                        label = "reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
+                };
+                wps {
+                        label = "wps";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+                };
+        };
+        dsa@0 {
+                compatible = "marvell,dsa";
+                #address-cells = <2>;
+                #size-cells = <0>;
+                dsa,ethernet = <&eth0port>;
+                dsa,mii-bus = <&mdio>;
+                switch@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0 0>;    /* MDIO address 0, switch 0 in tree */
+                        port@0 {
+                                reg = <0>;
+                                label = "lan4";
+                        };
+                        port@1 {
+                               reg = <1>;
+                               label = "lan3";
+                        };
+                        port@2 {
+                               reg = <2>;
+                               label = "lan2";
+                        };
+                        port@3 {
+                               reg = <3>;
+                               label = "lan1";
+                        };
+                        port@4 {
+                                reg = <4>;
+                                label = "wan";
+                        };
+                        port@6 {
+                               reg = <6>;
+                               label = "cpu";
+                        };
+                };
+        };
+};
+&mdio {
+        status = "okay";
+};
+/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set
+ * fixed speed and duplex. */
+&eth0 {
+        status = "okay";
+        ethernet0-port@0 {
+                speed = <1000>;
+                duplex = <1>;
+        };
+};
+/* eth1 is connected to the switch as well. However DSA only supports a
+ * single CPU port. So leave this port disabled to avoid confusion. */
+&eth1 {
+        status = "disabled";
+};
+/* There is no battery on the boards, so the RTC does not keep time
+ * when there is no power, making it useless. */
+&rtc {
+        status = "disabled";
+};
diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi
index 811e0971fc58..8be5b2e4626e 100644
--- a/arch/arm/boot/dts/kirkwood-synology.dtsi
+++ b/arch/arm/boot/dts/kirkwood-synology.dtsi
@@ -266,7 +266,7 @@
                        s35390a: s35390a@30 {
                                status = "disabled";
-                                compatible = "ssi,s35390a";
+                                compatible = "sii,s35390a";
                                reg = <0x30>;
                        };
                };
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
new file mode 100644
index 000000000000..9c5e16ba8c95
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -0,0 +1,240 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include "ls1021a.dtsi"
+/ {
+        model = "LS1021A QDS Board";
+        aliases {
+                enet0_rgmii_phy = &rgmii_phy1;
+                enet1_rgmii_phy = &rgmii_phy2;
+                enet2_rgmii_phy = &rgmii_phy3;
+                enet0_sgmii_phy = &sgmii_phy1c;
+                enet1_sgmii_phy = &sgmii_phy1d;
+        };
+};
+&dspi0 {
+        bus-num = <0>;
+        status = "okay";
+        dspiflash: at45db021d@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
+                spi-max-frequency = <16000000>;
+                spi-cpol;
+                spi-cpha;
+                reg = <0>;
+        };
+};
+&i2c0 {
+        status = "okay";
+        pca9547: mux@77 {
+                reg = <0x77>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                i2c@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x0>;
+                        ds3232: rtc@68 {
+                                compatible = "dallas,ds3232";
+                                reg = <0x68>;
+                                interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                };
+                i2c@2 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x2>;
+                        ina220@40 {
+                                compatible = "ti,ina220";
+                                reg = <0x40>;
+                                shunt-resistor = <1000>;
+                        };
+                        ina220@41 {
+                                compatible = "ti,ina220";
+                                reg = <0x41>;
+                                shunt-resistor = <1000>;
+                        };
+                };
+                i2c@3 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x3>;
+                        eeprom@56 {
+                                compatible = "atmel,24c512";
+                                reg = <0x56>;
+                        };
+                        eeprom@57 {
+                                compatible = "atmel,24c512";
+                                reg = <0x57>;
+                        };
+                        adt7461a@4c {
+                                compatible = "adi,adt7461a";
+                                reg = <0x4c>;
+                        };
+                };
+        };
+};
+&ifc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        /* NOR, NAND Flashes and FPGA on board */
+        ranges = <0x0 0x0 0x0 0x60000000 0x08000000
+                  0x2 0x0 0x0 0x7e800000 0x00010000
+                  0x3 0x0 0x0 0x7fb00000 0x00000100>;
+        status = "okay";
+        nor@0,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "cfi-flash";
+                reg = <0x0 0x0 0x8000000>;
+                bank-width = <2>;
+                device-width = <1>;
+        };
+        fpga: board-control@3,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                reg = <0x3 0x0 0x0000100>;
+                bank-width = <1>;
+                device-width = <1>;
+                ranges = <0 3 0 0x100>;
+                mdio-mux-emi1 {
+                        compatible = "mdio-mux-mmioreg";
+                        mdio-parent-bus = <&mdio0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x54 1>; /* BRDCFG4 */
+                        mux-mask = <0xe0>; /* EMI1[2:0] */
+                        /* Onboard PHYs */
+                        ls1021amdio0: mdio@0 {
+                                reg = <0>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                rgmii_phy1: ethernet-phy@1 {
+                                        reg = <0x1>;
+                                };
+                        };
+                        ls1021amdio1: mdio@20 {
+                                reg = <0x20>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                rgmii_phy2: ethernet-phy@2 {
+                                        reg = <0x2>;
+                                };
+                        };
+                        ls1021amdio2: mdio@40 {
+                                reg = <0x40>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                rgmii_phy3: ethernet-phy@3 {
+                                        reg = <0x3>;
+                                };
+                        };
+                        ls1021amdio3: mdio@60 {
+                                reg = <0x60>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                sgmii_phy1c: ethernet-phy@1c {
+                                        reg = <0x1c>;
+                                };
+                        };
+                        ls1021amdio4: mdio@80 {
+                                reg = <0x80>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                sgmii_phy1d: ethernet-phy@1d {
+                                        reg = <0x1d>;
+                                };
+                        };
+                };
+        };
+};
+&lpuart0 {
+        status = "okay";
+};
+&mdio0 {
+        tbi0: tbi-phy@8 {
+                reg = <0x8>;
+                device_type = "tbi-phy";
+        };
+};
+&uart0 {
+        status = "okay";
+};
+&uart1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
new file mode 100644
index 000000000000..a2c591e2d918
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include "ls1021a.dtsi"
+/ {
+        model = "LS1021A TWR Board";
+        aliases {
+                enet2_rgmii_phy = &rgmii_phy1;
+                enet0_sgmii_phy = &sgmii_phy2;
+                enet1_sgmii_phy = &sgmii_phy0;
+        };
+};
+&dspi1 {
+        bus-num = <0>;
+        status = "okay";
+        dspiflash: s25fl064k@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "spansion,s25fl064k";
+                spi-max-frequency = <16000000>;
+                spi-cpol;
+                spi-cpha;
+                reg = <0>;
+        };
+};
+&i2c0 {
+        status = "okay";
+};
+&i2c1 {
+        status = "okay";
+};
+&ifc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        /* NOR Flash on board */
+        ranges = <0x0 0x0 0x0 0x60000000 0x08000000>;
+        status = "okay";
+        nor@0,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "cfi-flash";
+                reg = <0x0 0x0 0x8000000>;
+                bank-width = <2>;
+                device-width = <1>;
+        };
+};
+&lpuart0 {
+        status = "okay";
+};
+&mdio0 {
+        sgmii_phy0: ethernet-phy@0 {
+                reg = <0x0>;
+        };
+        rgmii_phy1: ethernet-phy@1 {
+                reg = <0x1>;
+        };
+        sgmii_phy2: ethernet-phy@2 {
+                reg = <0x2>;
+        };
+        tbi1: tbi-phy@1f {
+                reg = <0x1f>;
+                device_type = "tbi-phy";
+        };
+};
+&uart0 {
+        status = "okay";
+};
+&uart1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
new file mode 100644
index 000000000000..657da14cb4b5
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -0,0 +1,408 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "skeleton64.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+/ {
+        compatible = "fsl,ls1021a";
+        interrupt-parent = <&gic>;
+        aliases {
+                serial0 = &lpuart0;
+                serial1 = &lpuart1;
+                serial2 = &lpuart2;
+                serial3 = &lpuart3;
+                serial4 = &lpuart4;
+                serial5 = &lpuart5;
+                sysclk = &sysclk;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@f00 {
+                        compatible = "arm,cortex-a7";
+                        device_type = "cpu";
+                        reg = <0xf00>;
+                        clocks = <&cluster1_clk>;
+                };
+                cpu@f01 {
+                        compatible = "arm,cortex-a7";
+                        device_type = "cpu";
+                        reg = <0xf01>;
+                        clocks = <&cluster1_clk>;
+                };
+        };
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+        };
+        pmu {
+                compatible = "arm,cortex-a7-pmu";
+                interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+        };
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                device_type = "soc";
+                interrupt-parent = <&gic>;
+                ranges;
+                gic: interrupt-controller@1400000 {
+                        compatible = "arm,cortex-a7-gic";
+                        #interrupt-cells = <3>;
+                        interrupt-controller;
+                        reg = <0x0 0x1401000 0x0 0x1000>,
+                              <0x0 0x1402000 0x0 0x1000>,
+                              <0x0 0x1404000 0x0 0x2000>,
+                              <0x0 0x1406000 0x0 0x2000>;
+                        interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+                };
+                ifc: ifc@1530000 {
+                        compatible = "fsl,ifc", "simple-bus";
+                        reg = <0x0 0x1530000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+                };
+                dcfg: dcfg@1ee0000 {
+                        compatible = "fsl,ls1021a-dcfg", "syscon";
+                        reg = <0x0 0x1ee0000 0x0 0x10000>;
+                        big-endian;
+                };
+                esdhc: esdhc@1560000 {
+                        compatible = "fsl,esdhc";
+                        reg = <0x0 0x1560000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-frequency = <0>;
+                        voltage-ranges = <1800 1800 3300 3300>;
+                        sdhci,auto-cmd12;
+                        big-endian;
+                        bus-width = <4>;
+                        status = "disabled";
+                };
+                scfg: scfg@1570000 {
+                        compatible = "fsl,ls1021a-scfg", "syscon";
+                        reg = <0x0 0x1570000 0x0 0x10000>;
+                };
+                clockgen: clocking@1ee1000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x0 0x0 0x1ee1000 0x10000>;
+                        sysclk: sysclk {
+                                compatible = "fixed-clock";
+                                #clock-cells = <0>;
+                                clock-output-names = "sysclk";
+                        };
+                        cga_pll1: pll@800 {
+                                compatible = "fsl,qoriq-core-pll-2.0";
+                                #clock-cells = <1>;
+                                reg = <0x800 0x10>;
+                                clocks = <&sysclk>;
+                                clock-output-names = "cga-pll1", "cga-pll1-div2",
+                                                     "cga-pll1-div4";
+                        };
+                        platform_clk: pll@c00 {
+                                compatible = "fsl,qoriq-core-pll-2.0";
+                                #clock-cells = <1>;
+                                reg = <0xc00 0x10>;
+                                clocks = <&sysclk>;
+                                clock-output-names = "platform-clk", "platform-clk-div2";
+                        };
+                        cluster1_clk: clk0c0@0 {
+                                compatible = "fsl,qoriq-core-mux-2.0";
+                                #clock-cells = <0>;
+                                reg = <0x0 0x10>;
+                                clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
+                                clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
+                                clock-output-names = "cluster1-clk";
+                        };
+                };
+                dspi0: dspi@2100000 {
+                        compatible = "fsl,vf610-dspi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x0 0x2100000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-names = "dspi";
+                        clocks = <&platform_clk 1>;
+                        spi-num-chipselects = <5>;
+                        big-endian;
+                        status = "disabled";
+                };
+                dspi1: dspi@2110000 {
+                        compatible = "fsl,vf610-dspi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x0 0x2110000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-names = "dspi";
+                        clocks = <&platform_clk 1>;
+                        spi-num-chipselects = <5>;
+                        big-endian;
+                        status = "disabled";
+                };
+                i2c0: i2c@2180000 {
+                        compatible = "fsl,vf610-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x0 0x2180000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-names = "i2c";
+                        clocks = <&platform_clk 1>;
+                        status = "disabled";
+                };
+                i2c1: i2c@2190000 {
+                        compatible = "fsl,vf610-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x0 0x2190000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-names = "i2c";
+                        clocks = <&platform_clk 1>;
+                        status = "disabled";
+                };
+                i2c2: i2c@21a0000 {
+                        compatible = "fsl,vf610-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x0 0x21a0000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-names = "i2c";
+                        clocks = <&platform_clk 1>;
+                        status = "disabled";
+                };
+                uart0: serial@21c0500 {
+                        compatible = "fsl,16550-FIFO64", "ns16550a";
+                        reg = <0x0 0x21c0500 0x0 0x100>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-frequency = <0>;
+                        fifo-size = <15>;
+                        status = "disabled";
+                };
+                uart1: serial@21c0600 {
+                        compatible = "fsl,16550-FIFO64", "ns16550a";
+                        reg = <0x0 0x21c0600 0x0 0x100>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-frequency = <0>;
+                        fifo-size = <15>;
+                        status = "disabled";
+                };
+                uart2: serial@21d0500 {
+                        compatible = "fsl,16550-FIFO64", "ns16550a";
+                        reg = <0x0 0x21d0500 0x0 0x100>;
+                        interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-frequency = <0>;
+                        fifo-size = <15>;
+                        status = "disabled";
+                };
+                uart3: serial@21d0600 {
+                        compatible = "fsl,16550-FIFO64", "ns16550a";
+                        reg = <0x0 0x21d0600 0x0 0x100>;
+                        interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-frequency = <0>;
+                        fifo-size = <15>;
+                        status = "disabled";
+                };
+                lpuart0: serial@2950000 {
+                        compatible = "fsl,ls1021a-lpuart";
+                        reg = <0x0 0x2950000 0x0 0x1000>;
+                        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&sysclk>;
+                        clock-names = "ipg";
+                        status = "disabled";
+                };
+                lpuart1: serial@2960000 {
+                        compatible = "fsl,ls1021a-lpuart";
+                        reg = <0x0 0x2960000 0x0 0x1000>;
+                        interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&platform_clk 1>;
+                        clock-names = "ipg";
+                        status = "disabled";
+                };
+                lpuart2: serial@2970000 {
+                        compatible = "fsl,ls1021a-lpuart";
+                        reg = <0x0 0x2970000 0x0 0x1000>;
+                        interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&platform_clk 1>;
+                        clock-names = "ipg";
+                        status = "disabled";
+                };
+                lpuart3: serial@2980000 {
+                        compatible = "fsl,ls1021a-lpuart";
+                        reg = <0x0 0x2980000 0x0 0x1000>;
+                        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&platform_clk 1>;
+                        clock-names = "ipg";
+                        status = "disabled";
+                };
+                lpuart4: serial@2990000 {
+                        compatible = "fsl,ls1021a-lpuart";
+                        reg = <0x0 0x2990000 0x0 0x1000>;
+                        interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&platform_clk 1>;
+                        clock-names = "ipg";
+                        status = "disabled";
+                };
+                lpuart5: serial@29a0000 {
+                        compatible = "fsl,ls1021a-lpuart";
+                        reg = <0x0 0x29a0000 0x0 0x1000>;
+                        interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&platform_clk 1>;
+                        clock-names = "ipg";
+                        status = "disabled";
+                };
+                wdog0: watchdog@2ad0000 {
+                        compatible = "fsl,imx21-wdt";
+                        reg = <0x0 0x2ad0000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&platform_clk 1>;
+                        clock-names = "wdog-en";
+                        big-endian;
+                };
+                sai1: sai@2b50000 {
+                        compatible = "fsl,vf610-sai";
+                        reg = <0x0 0x2b50000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&platform_clk 1>;
+                        clock-names = "sai";
+                        dma-names = "tx", "rx";
+                        dmas = <&edma0 1 47>,
+                               <&edma0 1 46>;
+                        big-endian;
+                        status = "disabled";
+                };
+                sai2: sai@2b60000 {
+                        compatible = "fsl,vf610-sai";
+                        reg = <0x0 0x2b60000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&platform_clk 1>;
+                        clock-names = "sai";
+                        dma-names = "tx", "rx";
+                        dmas = <&edma0 1 45>,
+                               <&edma0 1 44>;
+                        big-endian;
+                        status = "disabled";
+                };
+                edma0: edma@2c00000 {
+                        #dma-cells = <2>;
+                        compatible = "fsl,vf610-edma";
+                        reg = <0x0 0x2c00000 0x0 0x10000>,
+                              <0x0 0x2c10000 0x0 0x10000>,
+                              <0x0 0x2c20000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "edma-tx", "edma-err";
+                        dma-channels = <32>;
+                        big-endian;
+                        clock-names = "dmamux0", "dmamux1";
+                        clocks = <&platform_clk 1>,
+                                 <&platform_clk 1>;
+                };
+                mdio0: mdio@2d24000 {
+                        compatible = "gianfar";
+                        device_type = "mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x0 0x2d24000 0x0 0x4000>;
+                };
+                usb@8600000 {
+                        compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
+                        reg = <0x0 0x8600000 0x0 0x1000>;
+                        interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+                        dr_mode = "host";
+                        phy_type = "ulpi";
+                };
+                usb3@3100000 {
+                        compatible = "snps,dwc3";
+                        reg = <0x0 0x3100000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+                        dr_mode = "host";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index e6539ea5a711..b67ede515bcd 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -50,6 +50,13 @@
 / {
        interrupt-parent = <&gic>;
+        L2: l2-cache-controller@c4200000 {
+                compatible = "arm,pl310-cache";
+                reg = <0xc4200000 0x1000>;
+                cache-unified;
+                cache-level = <2>;
+        };
        gic: interrupt-controller@c4301000 {
                compatible = "arm,cortex-a9-gic";
                reg = <0xc4301000 0x1000>,
@@ -106,5 +113,42 @@
                        clocks = <&clk81>;
                        status = "disabled";
                };
+                i2c_AO: i2c@c8100500 {
+                        compatible = "amlogic,meson6-i2c";
+                        reg = <0xc8100500 0x20>;
+                        interrupts = <0 92 1>;
+                        clocks = <&clk81>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+                i2c_A: i2c@c1108500 {
+                        compatible = "amlogic,meson6-i2c";
+                        reg = <0xc1108500 0x20>;
+                        interrupts = <0 21 1>;
+                        clocks = <&clk81>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+                i2c_B: i2c@c11087c0 {
+                        compatible = "amlogic,meson6-i2c";
+                        reg = <0xc11087c0 0x20>;
+                        interrupts = <0 128 1>;
+                        clocks = <&clk81>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+                ir_receiver: ir-receiver@c8100480 {
+                        compatible= "amlogic,meson6-ir";
+                        reg = <0xc8100480 0x20>;
+                        interrupts = <0 15 1>;
+                        status = "disabled";
+                };
        };
 }; /* end of / */
diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts
index dc2541faf1ec..d7d351a68944 100644
--- a/arch/arm/boot/dts/meson6-atv1200.dts
+++ b/arch/arm/boot/dts/meson6-atv1200.dts
@@ -50,7 +50,7 @@
 / {
        model = "Geniatech ATV1200";
-        compatible = "geniatech,atv1200";
+        compatible = "geniatech,atv1200", "amlogic,meson6";
        aliases {
                serial0 = &uart_AO;
diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
index 4ba49127779f..8b33be15af94 100644
--- a/arch/arm/boot/dts/meson6.dtsi
+++ b/arch/arm/boot/dts/meson6.dtsi
@@ -60,12 +60,14 @@
                cpu@200 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
                        reg = <0x200>;
                };
                cpu@201 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
                        reg = <0x201>;
                };
        };
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
new file mode 100644
index 000000000000..1f442a7fe03b
--- /dev/null
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2014 Carlo Caione <carlo@caione.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public License
+ *     along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+/include/ "meson.dtsi"
+/ {
+        model = "Amlogic Meson8 SoC";
+        compatible = "amlogic,meson8";
+        interrupt-parent = <&gic>;
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@200 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
+                        reg = <0x200>;
+                };
+                cpu@201 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
+                        reg = <0x201>;
+                };
+                cpu@202 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
+                        reg = <0x202>;
+                };
+                cpu@203 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
+                        reg = <0x203>;
+                };
+        };
+        clk81: clk@0 {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <141666666>;
+        };
+}; /* end of / */
diff --git a/arch/arm/boot/dts/mt6592-evb.dts b/arch/arm/boot/dts/mt6592-evb.dts
new file mode 100644
index 000000000000..b57237e6394a
--- /dev/null
+++ b/arch/arm/boot/dts/mt6592-evb.dts
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Howard Chen <ibanezchen@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+#include "mt6592.dtsi"
+/ {
+        model = "mt6592 evb";
+        compatible = "mediatek,mt6592-evb", "mediatek,mt6592";
+        memory {
+                reg = <0x80000000 0x40000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/mt6592.dtsi b/arch/arm/boot/dts/mt6592.dtsi
new file mode 100644
index 000000000000..31e5a0979d78
--- /dev/null
+++ b/arch/arm/boot/dts/mt6592.dtsi
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Howard Chen <ibanezchen@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
+/ {
+        compatible = "mediatek,mt6592";
+        interrupt-parent = <&gic>;
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x1>;
+                };
+                cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x2>;
+                };
+                cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x3>;
+                };
+                cpu@4 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x4>;
+                };
+                cpu@5 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x5>;
+                };
+                cpu@6 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x6>;
+                };
+                cpu@7 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x7>;
+                };
+        };
+        system_clk: dummy13m {
+                compatible = "fixed-clock";
+                clock-frequency = <13000000>;
+                #clock-cells = <0>;
+        };
+        rtc_clk: dummy32k {
+                compatible = "fixed-clock";
+                clock-frequency = <32000>;
+                #clock-cells = <0>;
+        };
+        timer: timer@10008000 {
+                compatible = "mediatek,mt6577-timer";
+                reg = <0x10008000 0x80>;
+                interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&system_clk>, <&rtc_clk>;
+                clock-names = "system-clk", "rtc-clk";
+        };
+        gic: interrupt-controller@10211000 {
+                compatible = "arm,cortex-a7-gic";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = <0x10211000 0x1000>,
+                      <0x10212000 0x1000>;
+        };
+};
diff --git a/arch/arm/boot/dts/mt8127-moose.dts b/arch/arm/boot/dts/mt8127-moose.dts
new file mode 100644
index 000000000000..13cba0e77e08
--- /dev/null
+++ b/arch/arm/boot/dts/mt8127-moose.dts
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Joe.C <yingjoe.chen@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+#include "mt8127.dtsi"
+/ {
+        model = "MediaTek MT8127 Moose Board";
+        compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
+        memory {
+                reg = <0 0x80000000 0 0x40000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
new file mode 100644
index 000000000000..b24c0a2f3c44
--- /dev/null
+++ b/arch/arm/boot/dts/mt8127.dtsi
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Joe.C <yingjoe.chen@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton64.dtsi"
+/ {
+        compatible = "mediatek,mt8127";
+        interrupt-parent = <&gic>;
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x1>;
+                };
+                cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x2>;
+                };
+                cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x3>;
+                };
+        };
+        clocks {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                compatible = "simple-bus";
+                ranges;
+                system_clk: dummy13m {
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                        #clock-cells = <0>;
+                };
+                rtc_clk: dummy32k {
+                        compatible = "fixed-clock";
+                        clock-frequency = <32000>;
+                        #clock-cells = <0>;
+                };
+        };
+        soc {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                compatible = "simple-bus";
+                ranges;
+                timer: timer@10008000 {
+                        compatible = "mediatek,mt8127-timer",
+                                        "mediatek,mt6577-timer";
+                        reg = <0 0x10008000 0 0x80>;
+                        interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&system_clk>, <&rtc_clk>;
+                        clock-names = "system-clk", "rtc-clk";
+                };
+                gic: interrupt-controller@10211000 {
+                        compatible = "arm,cortex-a7-gic";
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        reg = <0 0x10211000 0 0x1000>,
+                              <0 0x10212000 0 0x1000>,
+                              <0 0x10214000 0 0x2000>,
+                              <0 0x10216000 0 0x2000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/mt8135-evbp1.dts b/arch/arm/boot/dts/mt8135-evbp1.dts
new file mode 100644
index 000000000000..a5adf9742308
--- /dev/null
+++ b/arch/arm/boot/dts/mt8135-evbp1.dts
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Joe.C <yingjoe.chen@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+#include "mt8135.dtsi"
+/ {
+        model = "MediaTek MT8135 evaluation board";
+        compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135";
+        memory {
+                reg = <0 0x80000000 0 0x40000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
new file mode 100644
index 000000000000..7d56a986358e
--- /dev/null
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Joe.C <yingjoe.chen@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton64.dtsi"
+/ {
+        compatible = "mediatek,mt8135";
+        interrupt-parent = <&gic>;
+        cpu-map {
+                cluster0 {
+                        core0 {
+                                cpu = <&cpu0>;
+                        };
+                        core1 {
+                                cpu = <&cpu1>;
+                        };
+                };
+                cluster1 {
+                        core0 {
+                                cpu = <&cpu2>;
+                        };
+                        core1 {
+                                cpu = <&cpu3>;
+                        };
+                };
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x000>;
+                };
+                cpu1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x001>;
+                };
+                cpu2: cpu@100 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x100>;
+                };
+                cpu3: cpu@101 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x101>;
+                };
+        };
+        clocks {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                compatible = "simple-bus";
+                ranges;
+                system_clk: dummy13m {
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                        #clock-cells = <0>;
+                };
+                rtc_clk: dummy32k {
+                        compatible = "fixed-clock";
+                        clock-frequency = <32000>;
+                        #clock-cells = <0>;
+                };
+        };
+        soc {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                compatible = "simple-bus";
+                ranges;
+                timer: timer@10008000 {
+                        compatible = "mediatek,mt8135-timer",
+                                        "mediatek,mt6577-timer";
+                        reg = <0 0x10008000 0 0x80>;
+                        interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&system_clk>, <&rtc_clk>;
+                        clock-names = "system-clk", "rtc-clk";
+                };
+                gic: interrupt-controller@10211000 {
+                        compatible = "arm,cortex-a15-gic";
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        reg = <0 0x10211000 0 0x1000>,
+                              <0 0x10212000 0 0x1000>,
+                              <0 0x10214000 0 0x2000>,
+                              <0 0x10216000 0 0x2000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
index 521c587acaee..445fafc73254 100644
--- a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
+++ b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
@@ -23,24 +23,29 @@
        ethernet@gpmc {
                compatible = "smsc,lan9221", "smsc,lan9115";
                bank-width = <2>;
-                gpmc,mux-add-data;
+                gpmc,device-width = <1>;
-                gpmc,cs-on-ns = <1>;
+                gpmc,cycle2cycle-samecsen = <1>;
-                gpmc,cs-rd-off-ns = <180>;
+                gpmc,cycle2cycle-diffcsen = <1>;
-                gpmc,cs-wr-off-ns = <180>;
+                gpmc,cs-on-ns = <5>;
-                gpmc,adv-rd-off-ns = <18>;
+                gpmc,cs-rd-off-ns = <150>;
-                gpmc,adv-wr-off-ns = <48>;
+                gpmc,cs-wr-off-ns = <150>;
-                gpmc,oe-on-ns = <54>;
+                gpmc,adv-on-ns = <0>;
-                gpmc,oe-off-ns = <168>;
+                gpmc,adv-rd-off-ns = <15>;
-                gpmc,we-on-ns = <54>;
+                gpmc,adv-wr-off-ns = <40>;
-                gpmc,we-off-ns = <168>;
+                gpmc,oe-on-ns = <45>;
-                gpmc,rd-cycle-ns = <186>;
+                gpmc,oe-off-ns = <140>;
-                gpmc,wr-cycle-ns = <186>;
+                gpmc,we-on-ns = <45>;
-                gpmc,access-ns = <144>;
+                gpmc,we-off-ns = <140>;
-                gpmc,page-burst-access-ns = <24>;
+                gpmc,rd-cycle-ns = <155>;
-                gpmc,bus-turnaround-ns = <90>;
+                gpmc,wr-cycle-ns = <155>;
-                gpmc,cycle2cycle-delay-ns = <90>;
+                gpmc,access-ns = <120>;
-                gpmc,cycle2cycle-samecsen;
+                gpmc,page-burst-access-ns = <20>;
-                gpmc,cycle2cycle-diffcsen;
+                gpmc,bus-turnaround-ns = <75>;
+                gpmc,cycle2cycle-delay-ns = <75>;
+                gpmc,wait-monitoring-ns = <0>;
+                gpmc,clk-activation-ns = <0>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+                gpmc,wr-access-ns = <0>;
                vddvario-supply = <&vddvario>;
                vdd33a-supply = <&vdd33a>;
                reg-io-width = <4>;
diff --git a/arch/arm/boot/dts/omap-zoom-common.dtsi b/arch/arm/boot/dts/omap-zoom-common.dtsi
index 68221fab978d..46ef3e443861 100644
--- a/arch/arm/boot/dts/omap-zoom-common.dtsi
+++ b/arch/arm/boot/dts/omap-zoom-common.dtsi
@@ -5,7 +5,7 @@
 #include "omap-gpmc-smsc911x.dtsi"
 &gpmc {
-        ranges = <3 0 0x10000000 0x00000400>,
+        ranges = <3 0 0x10000000 0x1000000>,    /* CS3: 16MB for UART */
                 <7 0 0x2c000000 0x01000000>;
        /*
@@ -15,7 +15,65 @@
         */
        uart@3,0 {
                compatible = "ns16550a";
-                reg = <3 0 0x100>;
+                reg = <3 0 8>;  /* CS3, offset 0, IO size 8 */
+                bank-width = <2>;
+                reg-shift = <1>;
+                reg-io-width = <1>;
+                interrupt-parent = <&gpio4>;
+                interrupts = <6 IRQ_TYPE_EDGE_RISING>;  /* gpio102 */
+                clock-frequency = <1843200>;
+                current-speed = <115200>;
+                gpmc,mux-add-data = <0>;
+                gpmc,device-width = <1>;
+                gpmc,wait-pin = <1>;
+                gpmc,cycle2cycle-samecsen = <1>;
+                gpmc,cycle2cycle-diffcsen = <1>;
+                gpmc,cs-on-ns = <5>;
+                gpmc,cs-rd-off-ns = <155>;
+                gpmc,cs-wr-off-ns = <155>;
+                gpmc,adv-on-ns = <15>;
+                gpmc,adv-rd-off-ns = <40>;
+                gpmc,adv-wr-off-ns = <40>;
+                gpmc,oe-on-ns = <45>;
+                gpmc,oe-off-ns = <145>;
+                gpmc,we-on-ns = <45>;
+                gpmc,we-off-ns = <145>;
+                gpmc,rd-cycle-ns = <155>;
+                gpmc,wr-cycle-ns = <155>;
+                gpmc,access-ns = <145>;
+                gpmc,page-burst-access-ns = <20>;
+                gpmc,bus-turnaround-ns = <20>;
+                gpmc,cycle2cycle-delay-ns = <20>;
+                gpmc,wait-monitoring-ns = <0>;
+                gpmc,clk-activation-ns = <0>;
+                gpmc,wr-data-mux-bus-ns = <45>;
+                gpmc,wr-access-ns = <145>;
+        };
+        uart@3,1 {
+                compatible = "ns16550a";
+                reg = <3 0x100 8>;      /* CS3, offset 0x100, IO size 8 */
+                bank-width = <2>;
+                reg-shift = <1>;
+                reg-io-width = <1>;
+                interrupt-parent = <&gpio4>;
+                interrupts = <6 IRQ_TYPE_EDGE_RISING>;  /* gpio102 */
+                clock-frequency = <1843200>;
+                current-speed = <115200>;
+        };
+        uart@3,2 {
+                compatible = "ns16550a";
+                reg = <3 0x200 8>;      /* CS3, offset 0x200, IO size 8 */
+                bank-width = <2>;
+                reg-shift = <1>;
+                reg-io-width = <1>;
+                interrupt-parent = <&gpio4>;
+                interrupts = <6 IRQ_TYPE_EDGE_RISING>;  /* gpio102 */
+                clock-frequency = <1843200>;
+                current-speed = <115200>;
+        };
+        uart@3,3 {
+                compatible = "ns16550a";
+                reg = <3 0x300 8>;      /* CS3, offset 0x300, IO size 8 */
                bank-width = <2>;
                reg-shift = <1>;
                reg-io-width = <1>;
diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
index 24c50db2a478..c9f1e93a95ae 100644
--- a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
+++ b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
@@ -40,14 +40,14 @@
 };
 &gpmc {
-        ranges = <0 0 0x04000000 0x10000000>;
+        ranges = <0 0 0x04000000 0x1000000>;    /* CS0: 16MB for OneNAND */
        /* gpio-irq for dma: 26 */
        onenand@0,0 {
                #address-cells = <1>;
                #size-cells = <1>;
-                reg = <0 0 0x10000000>;
+                reg = <0 0 0x20000>;    /* CS0, offset 0, IO size 128K */
                gpmc,sync-read;
                gpmc,burst-length = <16>;
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index ae89aad01595..e2b2e93d7b61 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -157,6 +157,7 @@
                        interrupts = <26>, <34>;
                        interrupt-names = "dsp", "iva";
                        ti,hwmods = "mailbox";
+                        #mbox-cells = <1>;
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <6>;
                        mbox_dsp: dsp {
diff --git a/arch/arm/boot/dts/omap2430-sdp.dts b/arch/arm/boot/dts/omap2430-sdp.dts
index 2c90d29b4cad..05eca2e4430f 100644
--- a/arch/arm/boot/dts/omap2430-sdp.dts
+++ b/arch/arm/boot/dts/omap2430-sdp.dts
@@ -43,7 +43,31 @@
                interrupts = <21 IRQ_TYPE_LEVEL_LOW>;   /* gpio149 */
                reg = <5 0x300 0xf>;
                bank-width = <2>;
-                gpmc,mux-add-data;
+                gpmc,sync-clk-ps = <0>;
-        };
+                gpmc,mux-add-data = <2>;
+                gpmc,device-width = <1>;
+                gpmc,cycle2cycle-samecsen = <1>;
+                gpmc,cycle2cycle-diffcsen = <1>;
+                gpmc,cs-on-ns = <7>;
+                gpmc,cs-rd-off-ns = <233>;
+                gpmc,cs-wr-off-ns = <233>;
+                gpmc,adv-on-ns = <22>;
+                gpmc,adv-rd-off-ns = <60>;
+                gpmc,adv-wr-off-ns = <60>;
+                gpmc,oe-on-ns = <67>;
+                gpmc,oe-off-ns = <210>;
+                gpmc,we-on-ns = <67>;
+                gpmc,we-off-ns = <210>;
+                gpmc,rd-cycle-ns = <233>;
+                gpmc,wr-cycle-ns = <233>;
+                gpmc,access-ns = <233>;
+                gpmc,page-burst-access-ns = <30>;
+                gpmc,bus-turnaround-ns = <30>;
+                gpmc,cycle2cycle-delay-ns = <30>;
+                gpmc,wait-monitoring-ns = <0>;
+                gpmc,clk-activation-ns = <0>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+                gpmc,wr-access-ns = <0>;
+        };
 };
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index b56d71611026..0dc8de2782b1 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -247,6 +247,7 @@
                        reg = <0x48094000 0x200>;
                        interrupts = <26>;
                        ti,hwmods = "mailbox";
+                        #mbox-cells = <1>;
                        ti,mbox-num-users = <4>;
                        ti,mbox-num-fifos = <6>;
                        mbox_dsp: dsp {
diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts
index d00502f4fd9b..0ab748cf7749 100644
--- a/arch/arm/boot/dts/omap3-cm-t3517.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3517.dts
@@ -134,3 +134,14 @@
        bus-width = <4>;
        cap-power-off-card;
 };
+&dss {
+        status = "ok";
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &dss_dpi_pins_common
+                &dss_dpi_pins_cm_t35x
+        >;
+};
diff --git a/arch/arm/boot/dts/omap3-cm-t3530.dts b/arch/arm/boot/dts/omap3-cm-t3530.dts
index d1458496520e..8dd14fcf6825 100644
--- a/arch/arm/boot/dts/omap3-cm-t3530.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3530.dts
@@ -46,3 +46,14 @@
        bus-width = <4>;
        cap-power-off-card;
 };
+&dss {
+        status = "ok";
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &dss_dpi_pins_common
+                &dss_dpi_pins_cm_t35x
+        >;
+};
diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts
index b3f9a50b3bc8..46eadb21b5ef 100644
--- a/arch/arm/boot/dts/omap3-cm-t3730.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3730.dts
@@ -31,6 +31,19 @@
        };
 };
+&omap3_pmx_wkup {
+        dss_dpi_pins_cm_t3730: pinmux_dss_dpi_pins_cm_t3730 {
+                pinctrl-single,pins = <
+                        OMAP3_WKUP_IOPAD(0x2a08, PIN_OUTPUT | MUX_MODE3)   /* sys_boot0.dss_data18 */
+                        OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3)   /* sys_boot1.dss_data19 */
+                        OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3)   /* sys_boot3.dss_data20 */
+                        OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3)   /* sys_boot4.dss_data21 */
+                        OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3)   /* sys_boot5.dss_data22 */
+                        OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3)   /* sys_boot6.dss_data23 */
+                >;
+        };
+};
 &omap3_pmx_core {
        mmc2_pins: pinmux_mmc2_pins {
@@ -61,3 +74,14 @@
        bus-width = <4>;
        cap-power-off-card;
 };
+&dss {
+        status = "ok";
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &dss_dpi_pins_common
+                &dss_dpi_pins_cm_t3730
+        >;
+};
diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
index c671a2299ea8..6ea6d460db30 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
@@ -49,6 +49,24 @@
                compatible = "usb-nop-xceiv";
                vcc-supply = <&hsusb2_power>;
        };
+        ads7846reg: ads7846-reg {
+                compatible = "regulator-fixed";
+                regulator-name = "ads7846-reg";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+        tv0: connector@1 {
+                compatible = "svideo-connector";
+                label = "tv";
+                port {
+                        tv_connector_in: endpoint {
+                                remote-endpoint = <&venc_out>;
+                        };
+                };
+        };
 };
 &omap3_pmx_core {
@@ -76,6 +94,76 @@
                        OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4)       /* sys_clkout2.gpio_186 */
                >;
        };
+        dss_dpi_pins_common: pinmux_dss_dpi_pins_common {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0)       /* dss_pclk.dss_pclk */
+                        OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0)       /* dss_hsync.dss_hsync */
+                        OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0)       /* dss_vsync.dss_vsync */
+                        OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0)       /* dss_acbias.dss_acbias */
+                        OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0)       /* dss_data6.dss_data6 */
+                        OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0)       /* dss_data7.dss_data7 */
+                        OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0)       /* dss_data8.dss_data8 */
+                        OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0)       /* dss_data9.dss_data9 */
+                        OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0)       /* dss_data10.dss_data10 */
+                        OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0)       /* dss_data11.dss_data11 */
+                        OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0)       /* dss_data12.dss_data12 */
+                        OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0)       /* dss_data13.dss_data13 */
+                        OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0)       /* dss_data14.dss_data14 */
+                        OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0)       /* dss_data15.dss_data15 */
+                        OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0)       /* dss_data16.dss_data16 */
+                        OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0)       /* dss_data17.dss_data17 */
+                        OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0)       /* dss_data18.dss_data18 */
+                        OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0)       /* dss_data19.dss_data19 */
+                        OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0)       /* dss_data20.dss_data20 */
+                        OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0)       /* dss_data21.dss_data21 */
+                        OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0)       /* dss_data22.dss_data22 */
+                        OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0)       /* dss_data23.dss_data23 */
+                >;
+        };
+        dss_dpi_pins_cm_t35x: pinmux_dss_dpi_pins_cm_t35x {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0)       /* dss_data0.dss_data0 */
+                        OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0)       /* dss_data1.dss_data1 */
+                        OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0)       /* dss_data2.dss_data2 */
+                        OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0)       /* dss_data3.dss_data3 */
+                        OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0)       /* dss_data4.dss_data4 */
+                        OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0)       /* dss_data5.dss_data5 */
+                >;
+        };
+        ads7846_pins: pinmux_ads7846_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20ba, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs6.gpio_57 */
+                >;
+        };
+        mcspi1_pins: pinmux_mcspi1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0)        /* mcspi1_clk */
+                        OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0)        /* mcspi1_simo */
+                        OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0)        /* mcspi1_somi */
+                        OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0 */
+                >;
+        };
+        i2c1_pins: pinmux_i2c1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
+                        OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
+                >;
+        };
+        mcbsp2_pins: pinmux_mcbsp2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0)        /* mcbsp2_fsx */
+                        OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0)        /* mcbsp2_clkx */
+                        OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0)        /* mcbsp2_dr */
+                        OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0)       /* mcbsp2_dx */
+                >;
+        };
 };
 &uart3 {
@@ -94,12 +182,22 @@
 };
 &i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins>;
        clock-frequency = <400000>;
+        at24@50 {
+                compatible = "at24,24c02";
+                pagesize = <16>;
+                reg = <0x50>;
+        };
 };
 &i2c3 {
        clock-frequency = <400000>;
 };
 &usbhshost {
        port1-mode = "ehci-phy";
        port2-mode = "ehci-phy";
@@ -108,3 +206,56 @@
 &usbhsehci {
        phys = <&hsusb1_phy &hsusb2_phy>;
 };
+&mcspi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcspi1_pins>;
+        /* touch controller */
+        ads7846@0 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&ads7846_pins>;
+                compatible = "ti,ads7846";
+                vcc-supply = <&ads7846reg>;
+                reg = <0>;                      /* CS0 */
+                spi-max-frequency = <1500000>;
+                interrupt-parent = <&gpio2>;
+                interrupts = <25 0>;            /* gpio_57 */
+                pendown-gpio = <&gpio2 25 0>;
+                ti,x-min = /bits/ 16 <0x0>;
+                ti,x-max = /bits/ 16 <0x0fff>;
+                ti,y-min = /bits/ 16 <0x0>;
+                ti,y-max = /bits/ 16 <0x0fff>;
+                ti,x-plate-ohms = /bits/ 16 <180>;
+                ti,pressure-max = /bits/ 16 <255>;
+                ti,debounce-max = /bits/ 16 <30>;
+                ti,debounce-tol = /bits/ 16 <10>;
+                ti,debounce-rep = /bits/ 16 <1>;
+                linux,wakeup;
+        };
+};
+&venc {
+        status = "ok";
+        port {
+                venc_out: endpoint {
+                        remote-endpoint = <&tv_connector_in>;
+                        ti,channels = <2>;
+                };
+        };
+};
+&mcbsp2 {
+        status = "ok";
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcbsp2_pins>;
+};
diff --git a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
index 25ba08331d88..9a4a3ab9af78 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
@@ -10,6 +10,14 @@
                        cpu0-supply = <&vcc>;
                };
        };
+        sound {
+                compatible = "ti,omap-twl4030";
+                ti,model = "cm-t35";
+                ti,mcbsp = <&mcbsp2>;
+                ti,codec = <&twl_audio>;
+        };
 };
 &omap3_pmx_core {
@@ -59,11 +67,22 @@
                reg = <0x48>;
                interrupts = <7>; /* SYS_NIRQ cascaded to intc */
                interrupt-parent = <&intc>;
+                twl_audio: audio {
+                        compatible = "ti,twl4030-audio";
+                        codec {
+                        };
+                };
        };
 };
 #include "twl4030.dtsi"
 #include "twl4030_omap3.dtsi"
+#include <dt-bindings/input/input.h>
+&venc {
+        vdda-supply = <&vdac>;
+};
 &mmc1 {
        vmmc-supply = <&vmmc1>;
@@ -75,6 +94,22 @@
        ti,pullups = <0x000001>;
 };
+&twl_keypad {
+        linux,keymap = <
+                                MATRIX_KEY(0x00, 0x01, KEY_A)
+                                MATRIX_KEY(0x00, 0x02, KEY_B)
+                                MATRIX_KEY(0x00, 0x03, KEY_LEFT)
+                                MATRIX_KEY(0x01, 0x01, KEY_UP)
+                                MATRIX_KEY(0x01, 0x02, KEY_ENTER)
+                                MATRIX_KEY(0x01, 0x03, KEY_DOWN)
+                                MATRIX_KEY(0x02, 0x01, KEY_RIGHT)
+                                MATRIX_KEY(0x02, 0x02, KEY_C)
+                                MATRIX_KEY(0x02, 0x03, KEY_D)
+                        >;
+};
 &hsusb1_phy {
        reset-gpios = <&twl_gpio 6 GPIO_ACTIVE_LOW>;
 };
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index da402f0fdab4..169037e5ff53 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -106,10 +106,10 @@
 };
 &gpmc {
-        ranges = <0 0 0x30000000 0x04>;       /* CS0: NAND */
+        ranges = <0 0 0x30000000 0x1000000>;       /* CS0: 16MB for NAND */
        nand@0,0 {
-                reg = <0 0 0>; /* CS0, offset 0 */
+                reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
                nand-bus-width = <16>;
                gpmc,sync-clk-ps = <0>;
diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts
index a8bd4349c7d2..16e8ce350dda 100644
--- a/arch/arm/boot/dts/omap3-evm-37xx.dts
+++ b/arch/arm/boot/dts/omap3-evm-37xx.dts
@@ -154,13 +154,14 @@
 };
 &gpmc {
-        ranges = <0 0 0x00000000 0x20000000>,
+        ranges = <0 0 0x00000000 0x1000000>,    /* CS0: 16MB for NAND */
                 <5 0 0x2c000000 0x01000000>;
        nand@0,0 {
                linux,mtd-name= "hynix,h8kds0un0mer-4em";
-                reg = <0 0 0>;
+                reg = <0 0 4>;  /* CS0, offset 0, IO size 4 */
                nand-bus-width = <16>;
+                gpmc,device-width = <2>;
                ti,nand-ecc-opt = "bch8";
                gpmc,sync-clk-ps = <0>;
diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi
index c8747c7f1cc8..127f3e7c10c4 100644
--- a/arch/arm/boot/dts/omap3-evm-common.dtsi
+++ b/arch/arm/boot/dts/omap3-evm-common.dtsi
@@ -2,6 +2,7 @@
 * Common support for omap3 EVM boards
 */
+#include <dt-bindings/input/input.h>
 #include "omap-gpmc-smsc911x.dtsi"
 / {
@@ -111,6 +112,26 @@
        ti,use-leds;
 };
+&twl_keypad {
+        linux,keymap = <
+                        MATRIX_KEY(2, 2, KEY_1)
+                        MATRIX_KEY(1, 1, KEY_2)
+                        MATRIX_KEY(0, 0, KEY_3)
+                        MATRIX_KEY(3, 2, KEY_4)
+                        MATRIX_KEY(2, 1, KEY_5)
+                        MATRIX_KEY(1, 0, KEY_6)
+                        MATRIX_KEY(1, 3, KEY_7)
+                        MATRIX_KEY(3, 1, KEY_8)
+                        MATRIX_KEY(2, 0, KEY_9)
+                        MATRIX_KEY(2, 3, KEY_KPASTERISK)
+                        MATRIX_KEY(0, 2, KEY_0)
+                        MATRIX_KEY(3, 0, KEY_KPDOT)
+                        /* s4 not wired */
+                        MATRIX_KEY(1, 2, KEY_BACKSPACE)
+                        MATRIX_KEY(0, 1, KEY_ENTER)
+                        >;
+};
 &usb_otg_hs {
        interface-type = <0>;
        usb-phy = <&usb2_phy>;
diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi
index fd34f913ace3..655d6e920a86 100644
--- a/arch/arm/boot/dts/omap3-gta04.dtsi
+++ b/arch/arm/boot/dts/omap3-gta04.dtsi
@@ -104,67 +104,67 @@
        uart1_pins: pinmux_uart1_pins {
                pinctrl-single,pins = <
-                        0x152 (PIN_INPUT | MUX_MODE0)           /* uart1_rx.uart1_rx */
+                        OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0)                /* uart1_rx.uart1_rx */
-                        0x14c (PIN_OUTPUT |MUX_MODE0)           /* uart1_tx.uart1_tx */
+                        OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0)               /* uart1_tx.uart1_tx */
                >;
        };
        uart2_pins: pinmux_uart2_pins {
                pinctrl-single,pins = <
-                        0x14a (PIN_INPUT | MUX_MODE0)           /* uart2_rx.uart2_rx */
+                        OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0)                /* uart2_rx.uart2_rx */
-                        0x148 (PIN_OUTPUT | MUX_MODE0)          /* uart2_tx.uart2_tx */
+                        OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0)               /* uart2_tx.uart2_tx */
                >;
        };
        uart3_pins: pinmux_uart3_pins {
                pinctrl-single,pins = <
-                        0x16e (PIN_INPUT | MUX_MODE0)           /* uart3_rx.uart3_rx */
+                        OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0)                /* uart3_rx.uart3_rx */
-                        0x170 (PIN_OUTPUT | MUX_MODE0)          /* uart3_tx.uart3_tx */
+                        OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)               /* uart3_tx.uart3_tx */
                >;
        };
        mmc1_pins: pinmux_mmc1_pins {
                pinctrl-single,pins = <
-                        0x114 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_clk.sdmmc1_clk */
+                        OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_clk.sdmmc1_clk */
-                        0x116 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_cmd.sdmmc1_cmd */
+                        OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_cmd.sdmmc1_cmd */
-                        0x118 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat0.sdmmc1_dat0 */
+                        OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat0.sdmmc1_dat0 */
-                        0x11a (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat1.sdmmc1_dat1 */
+                        OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat1.sdmmc1_dat1 */
-                        0x11c (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat2.sdmmc1_dat2 */
+                        OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat2.sdmmc1_dat2 */
-                        0x11e (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat3.sdmmc1_dat3 */
+                        OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat3.sdmmc1_dat3 */
                >;
        };
        dss_dpi_pins: pinmux_dss_dpi_pins {
               pinctrl-single,pins = <
-                       0x0a4 (PIN_OUTPUT | MUX_MODE0)   /* dss_pclk.dss_pclk */
+                        OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0)   /* dss_pclk.dss_pclk */
-                       0x0a6 (PIN_OUTPUT | MUX_MODE0)   /* dss_hsync.dss_hsync */
+                        OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0)   /* dss_hsync.dss_hsync */
-                       0x0a8 (PIN_OUTPUT | MUX_MODE0)   /* dss_vsync.dss_vsync */
+                        OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0)   /* dss_vsync.dss_vsync */
-                       0x0aa (PIN_OUTPUT | MUX_MODE0)   /* dss_acbias.dss_acbias */
+                        OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0)   /* dss_acbias.dss_acbias */
-                       0x0ac (PIN_OUTPUT | MUX_MODE0)   /* dss_data0.dss_data0 */
+                        OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0)   /* dss_data0.dss_data0 */
-                       0x0ae (PIN_OUTPUT | MUX_MODE0)   /* dss_data1.dss_data1 */
+                        OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0)   /* dss_data1.dss_data1 */
-                       0x0b0 (PIN_OUTPUT | MUX_MODE0)   /* dss_data2.dss_data2 */
+                        OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0)   /* dss_data2.dss_data2 */
-                       0x0b2 (PIN_OUTPUT | MUX_MODE0)   /* dss_data3.dss_data3 */
+                        OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0)   /* dss_data3.dss_data3 */
-                       0x0b4 (PIN_OUTPUT | MUX_MODE0)   /* dss_data4.dss_data4 */
+                        OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0)   /* dss_data4.dss_data4 */
-                       0x0b6 (PIN_OUTPUT | MUX_MODE0)   /* dss_data5.dss_data5 */
+                        OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0)   /* dss_data5.dss_data5 */
-                       0x0b8 (PIN_OUTPUT | MUX_MODE0)   /* dss_data6.dss_data6 */
+                        OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0)   /* dss_data6.dss_data6 */
-                       0x0ba (PIN_OUTPUT | MUX_MODE0)   /* dss_data7.dss_data7 */
+                        OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0)   /* dss_data7.dss_data7 */
-                       0x0bc (PIN_OUTPUT | MUX_MODE0)   /* dss_data8.dss_data8 */
+                        OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0)   /* dss_data8.dss_data8 */
-                       0x0be (PIN_OUTPUT | MUX_MODE0)   /* dss_data9.dss_data9 */
+                        OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0)   /* dss_data9.dss_data9 */
-                       0x0c0 (PIN_OUTPUT | MUX_MODE0)   /* dss_data10.dss_data10 */
+                        OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0)   /* dss_data10.dss_data10 */
-                       0x0c2 (PIN_OUTPUT | MUX_MODE0)   /* dss_data11.dss_data11 */
+                        OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0)   /* dss_data11.dss_data11 */
-                       0x0c4 (PIN_OUTPUT | MUX_MODE0)   /* dss_data12.dss_data12 */
+                        OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0)   /* dss_data12.dss_data12 */
-                       0x0c6 (PIN_OUTPUT | MUX_MODE0)   /* dss_data13.dss_data13 */
+                        OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0)   /* dss_data13.dss_data13 */
-                       0x0c8 (PIN_OUTPUT | MUX_MODE0)   /* dss_data14.dss_data14 */
+                        OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0)   /* dss_data14.dss_data14 */
-                       0x0ca (PIN_OUTPUT | MUX_MODE0)   /* dss_data15.dss_data15 */
+                        OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0)   /* dss_data15.dss_data15 */
-                       0x0cc (PIN_OUTPUT | MUX_MODE0)   /* dss_data16.dss_data16 */
+                        OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0)   /* dss_data16.dss_data16 */
-                       0x0ce (PIN_OUTPUT | MUX_MODE0)   /* dss_data17.dss_data17 */
+                        OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0)   /* dss_data17.dss_data17 */
-                       0x0d0 (PIN_OUTPUT | MUX_MODE0)   /* dss_data18.dss_data18 */
+                        OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0)   /* dss_data18.dss_data18 */
-                       0x0d2 (PIN_OUTPUT | MUX_MODE0)   /* dss_data19.dss_data19 */
+                        OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0)   /* dss_data19.dss_data19 */
-                       0x0d4 (PIN_OUTPUT | MUX_MODE0)   /* dss_data20.dss_data20 */
+                        OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0)   /* dss_data20.dss_data20 */
-                       0x0d6 (PIN_OUTPUT | MUX_MODE0)   /* dss_data21.dss_data21 */
+                        OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0)   /* dss_data21.dss_data21 */
-                       0x0d8 (PIN_OUTPUT | MUX_MODE0)   /* dss_data22.dss_data22 */
+                        OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0)   /* dss_data22.dss_data22 */
-                       0x0da (PIN_OUTPUT | MUX_MODE0)   /* dss_data23.dss_data23 */
+                        OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0)   /* dss_data23.dss_data23 */
-               >;
+                >;
       };
 };
@@ -397,10 +397,10 @@
 };
 &gpmc {
-        ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */
+        ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
        nand@0,0 {
-                reg = <0 0 0>; /* CS0, offset 0 */
+                reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
                nand-bus-width = <16>;
                ti,nand-ecc-opt = "bch8";
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index e2d163bf0619..8a63ad2286aa 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -31,18 +31,6 @@
                regulator-always-on;
        };
-        lbee1usjyc_vmmc: lbee1usjyc_vmmc {
-                pinctrl-names = "default";
-                pinctrl-0 = <&lbee1usjyc_pins>;
-                compatible = "regulator-fixed";
-                regulator-name = "regulator-lbee1usjyc";
-                regulator-min-microvolt = <3300000>;
-                regulator-max-microvolt = <3300000>;
-                gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;    /* gpio_138 WIFI_PDN */
-                startup-delay-us = <10000>;
-                enable-active-high;
-                vin-supply = <&vdd33>;
-        };
 };
 &omap3_pmx_core {
@@ -53,13 +41,6 @@
                >;
        };
-        uart2_pins: pinmux_uart2_pins {
-                pinctrl-single,pins = <
-                        0x14a (PIN_INPUT | MUX_MODE0)           /* uart2_rx.uart2_rx */
-                        0x148 (PIN_OUTPUT | MUX_MODE0)          /* uart2_tx.uart2_tx */
-                >;
-        };
        uart3_pins: pinmux_uart3_pins {
                pinctrl-single,pins = <
                        0x16e (PIN_INPUT | MUX_MODE0)           /* uart3_rx.uart3_rx */
@@ -67,15 +48,6 @@
                >;
        };
-        /* WiFi/BT combo */
-        lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
-                pinctrl-single,pins = <
-                        0x136 (PIN_OUTPUT | MUX_MODE4)  /* sdmmc2_dat5.gpio_137 */
-                        0x138 (PIN_OUTPUT | MUX_MODE4)  /* sdmmc2_dat6.gpio_138 */
-                        0x13a (PIN_OUTPUT | MUX_MODE4)  /* sdmmc2_dat7.gpio_139 */
-                >;
-        };
        mcbsp2_pins: pinmux_mcbsp2_pins {
                pinctrl-single,pins = <
                        0x10c (PIN_INPUT | MUX_MODE0)           /* mcbsp2_fsx.mcbsp2_fsx */
@@ -120,13 +92,6 @@
                >;
        };
-        i2c2_pins: pinmux_i2c2_pins {
-                pinctrl-single,pins = <
-                        0x18e (PIN_INPUT | MUX_MODE0)   /* i2c2_scl.i2c2_scl */
-                        0x190 (PIN_INPUT | MUX_MODE0)   /* i2c2_sda.i2c2_sda */
-                >;
-        };
        i2c3_pins: pinmux_i2c3_pins {
                pinctrl-single,pins = <
                        0x192 (PIN_INPUT | MUX_MODE0)   /* i2c3_scl.i2c3_scl */
@@ -135,6 +100,55 @@
        };
 };
+&gpmc {
+        nand@0,0 {
+                linux,mtd-name= "micron,mt29c4g96maz";
+                reg = <0 0 4>;  /* CS0, offset 0, IO size 4 */
+                nand-bus-width = <16>;
+                gpmc,device-width = <2>;
+                ti,nand-ecc-opt = "bch8";
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <44>;
+                gpmc,cs-wr-off-ns = <44>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <34>;
+                gpmc,adv-wr-off-ns = <44>;
+                gpmc,we-off-ns = <40>;
+                gpmc,oe-off-ns = <54>;
+                gpmc,access-ns = <64>;
+                gpmc,rd-cycle-ns = <82>;
+                gpmc,wr-cycle-ns = <82>;
+                gpmc,wr-access-ns = <40>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                partition@0 {
+                        label = "SPL";
+                        reg = <0 0x100000>;
+                };
+                partition@80000 {
+                        label = "U-Boot";
+                        reg = <0x100000 0x180000>;
+                };
+                partition@1c0000 {
+                        label = "Environment";
+                        reg = <0x280000 0x100000>;
+                };
+                partition@280000 {
+                        label = "Kernel";
+                        reg = <0x380000 0x300000>;
+                };
+                partition@780000 {
+                        label = "Filesystem";
+                        reg = <0x680000 0x1f980000>;
+                };
+        };
+};
 &i2c1 {
        pinctrl-names = "default";
        pinctrl-0 = <&i2c1_pins>;
@@ -156,12 +170,6 @@
 #include "twl4030.dtsi"
 #include "twl4030_omap3.dtsi"
-&i2c2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c2_pins>;
-        clock-frequency = <400000>;
-};
 &i2c3 {
        pinctrl-names = "default";
        pinctrl-0 = <&i2c3_pins>;
@@ -181,14 +189,6 @@
      bus-width = <4>;
 };
-&mmc2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc2_pins>;
-        vmmc-supply = <&lbee1usjyc_vmmc>;
-        bus-width = <4>;
-        non-removable;
-};
 &mmc3 {
        status = "disabled";
 };
@@ -198,11 +198,6 @@
       pinctrl-0 = <&uart1_pins>;
 };
-&uart2 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&uart2_pins>;
-};
 &uart3 {
       pinctrl-names = "default";
       pinctrl-0 = <&uart3_pins>;
diff --git a/arch/arm/boot/dts/omap3-igep0020-common.dtsi b/arch/arm/boot/dts/omap3-igep0020-common.dtsi
new file mode 100644
index 000000000000..e458c2185e3c
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-igep0020-common.dtsi
@@ -0,0 +1,246 @@
+/*
+ * Common Device Tree Source for IGEPv2
+ *
+ * Copyright (C) 2014 Javier Martinez Canillas <javier@collabora.co.uk>
+ * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "omap3-igep.dtsi"
+#include "omap-gpmc-smsc9221.dtsi"
+/ {
+        leds {
+                pinctrl-names = "default";
+                pinctrl-0 = <&leds_pins>;
+                compatible = "gpio-leds";
+                boot {
+                         label = "omap3:green:boot";
+                         gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+                         default-state = "on";
+                };
+                user0 {
+                         label = "omap3:red:user0";
+                         gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
+                         default-state = "off";
+                };
+                user1 {
+                         label = "omap3:red:user1";
+                         gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+                         default-state = "off";
+                };
+                user2 {
+                        label = "omap3:green:user1";
+                        gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
+                };
+        };
+        /* HS USB Port 1 Power */
+        hsusb1_power: hsusb1_power_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb1_vbus";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>;  /* GPIO LEDA */
+                startup-delay-us = <70000>;
+        };
+        /* HS USB Host PHY on PORT 1 */
+        hsusb1_phy: hsusb1_phy {
+                compatible = "usb-nop-xceiv";
+                reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
+                vcc-supply = <&hsusb1_power>;
+        };
+        tfp410: encoder@0 {
+                compatible = "ti,tfp410";
+                powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                tfp410_in: endpoint@0 {
+                                        remote-endpoint = <&dpi_out>;
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                tfp410_out: endpoint@0 {
+                                        remote-endpoint = <&dvi_connector_in>;
+                                };
+                        };
+                };
+        };
+        dvi0: connector@0 {
+                compatible = "dvi-connector";
+                label = "dvi";
+                digital;
+                ddc-i2c-bus = <&i2c3>;
+                port {
+                        dvi_connector_in: endpoint {
+                                remote-endpoint = <&tfp410_out>;
+                        };
+                };
+        };
+};
+&omap3_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &tfp410_pins
+                &dss_dpi_pins
+        >;
+        tfp410_pins: pinmux_tfp410_pins {
+                pinctrl-single,pins = <
+                        0x196 (PIN_OUTPUT | MUX_MODE4)   /* hdq_sio.gpio_170 */
+                >;
+        };
+        dss_dpi_pins: pinmux_dss_dpi_pins {
+                pinctrl-single,pins = <
+                        0x0a4 (PIN_OUTPUT | MUX_MODE0)   /* dss_pclk.dss_pclk */
+                        0x0a6 (PIN_OUTPUT | MUX_MODE0)   /* dss_hsync.dss_hsync */
+                        0x0a8 (PIN_OUTPUT | MUX_MODE0)   /* dss_vsync.dss_vsync */
+                        0x0aa (PIN_OUTPUT | MUX_MODE0)   /* dss_acbias.dss_acbias */
+                        0x0ac (PIN_OUTPUT | MUX_MODE0)   /* dss_data0.dss_data0 */
+                        0x0ae (PIN_OUTPUT | MUX_MODE0)   /* dss_data1.dss_data1 */
+                        0x0b0 (PIN_OUTPUT | MUX_MODE0)   /* dss_data2.dss_data2 */
+                        0x0b2 (PIN_OUTPUT | MUX_MODE0)   /* dss_data3.dss_data3 */
+                        0x0b4 (PIN_OUTPUT | MUX_MODE0)   /* dss_data4.dss_data4 */
+                        0x0b6 (PIN_OUTPUT | MUX_MODE0)   /* dss_data5.dss_data5 */
+                        0x0b8 (PIN_OUTPUT | MUX_MODE0)   /* dss_data6.dss_data6 */
+                        0x0ba (PIN_OUTPUT | MUX_MODE0)   /* dss_data7.dss_data7 */
+                        0x0bc (PIN_OUTPUT | MUX_MODE0)   /* dss_data8.dss_data8 */
+                        0x0be (PIN_OUTPUT | MUX_MODE0)   /* dss_data9.dss_data9 */
+                        0x0c0 (PIN_OUTPUT | MUX_MODE0)   /* dss_data10.dss_data10 */
+                        0x0c2 (PIN_OUTPUT | MUX_MODE0)   /* dss_data11.dss_data11 */
+                        0x0c4 (PIN_OUTPUT | MUX_MODE0)   /* dss_data12.dss_data12 */
+                        0x0c6 (PIN_OUTPUT | MUX_MODE0)   /* dss_data13.dss_data13 */
+                        0x0c8 (PIN_OUTPUT | MUX_MODE0)   /* dss_data14.dss_data14 */
+                        0x0ca (PIN_OUTPUT | MUX_MODE0)   /* dss_data15.dss_data15 */
+                        0x0cc (PIN_OUTPUT | MUX_MODE0)   /* dss_data16.dss_data16 */
+                        0x0ce (PIN_OUTPUT | MUX_MODE0)   /* dss_data17.dss_data17 */
+                        0x0d0 (PIN_OUTPUT | MUX_MODE0)   /* dss_data18.dss_data18 */
+                        0x0d2 (PIN_OUTPUT | MUX_MODE0)   /* dss_data19.dss_data19 */
+                        0x0d4 (PIN_OUTPUT | MUX_MODE0)   /* dss_data20.dss_data20 */
+                        0x0d6 (PIN_OUTPUT | MUX_MODE0)   /* dss_data21.dss_data21 */
+                        0x0d8 (PIN_OUTPUT | MUX_MODE0)   /* dss_data22.dss_data22 */
+                        0x0da (PIN_OUTPUT | MUX_MODE0)   /* dss_data23.dss_data23 */
+                >;
+        };
+        uart2_pins: pinmux_uart2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0)        /* uart2_cts.uart2_cts */
+                        OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0)       /* uart2_rts .uart2_rts*/
+                        OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0)       /* uart2_tx.uart2_tx */
+                        OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0)        /* uart2_rx.uart2_rx */
+                >;
+        };
+};
+&omap3_pmx_core2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &hsusbb1_pins
+        >;
+        hsusbb1_pins: pinmux_hsusbb1_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3)            /* etk_ctl.hsusb1_clk */
+                        OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3)            /* etk_clk.hsusb1_stp */
+                        OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d8.hsusb1_dir */
+                        OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d9.hsusb1_nxt */
+                        OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d0.hsusb1_data0 */
+                        OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d1.hsusb1_data1 */
+                        OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d2.hsusb1_data2 */
+                        OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d3.hsusb1_data7 */
+                        OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d4.hsusb1_data4 */
+                        OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d5.hsusb1_data5 */
+                        OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d6.hsusb1_data6 */
+                        OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d7.hsusb1_data3 */
+                >;
+        };
+        leds_pins: pinmux_leds_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
+                        OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
+                        OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
+                >;
+        };
+};
+&i2c3 {
+        clock-frequency = <100000>;
+        /*
+         * Display monitor features are burnt in the EEPROM
+         * as EDID data.
+         */
+        eeprom@50 {
+                compatible = "ti,eeprom";
+                reg = <0x50>;
+        };
+};
+&gpmc {
+        ranges = <0 0 0x00000000 0x20000000>,
+                 <5 0 0x2c000000 0x01000000>;
+        ethernet@gpmc {
+                pinctrl-names = "default";
+                pinctrl-0 = <&smsc9221_pins>;
+                reg = <5 0 0xff>;
+                interrupt-parent = <&gpio6>;
+                interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+        };
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart2_pins>;
+};
+&usbhshost {
+        port1-mode = "ehci-phy";
+};
+&usbhsehci {
+        phys = <&hsusb1_phy>;
+};
+&vpll2 {
+        /* Needed for DSS */
+        regulator-name = "vdds_dsi";
+};
+&dss {
+        status = "ok";
+        port {
+                dpi_out: endpoint {
+                        remote-endpoint = <&tfp410_in>;
+                        data-lines = <24>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
new file mode 100644
index 000000000000..cc8bd0cd8cf8
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
@@ -0,0 +1,45 @@
+/*
+ * Device Tree Source for IGEPv2 Rev. F (TI OMAP AM/DM37x)
+ *
+ * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
+ * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "omap3-igep0020-common.dtsi"
+/ {
+        model = "IGEPv2 Rev. F (TI OMAP AM/DM37x)";
+        compatible = "isee,omap3-igep0020-rev-f", "ti,omap36xx", "ti,omap3";
+        /* Regulator to trigger the WL_EN signal of the Wifi module */
+        lbep5clwmc_wlen: regulator-lbep5clwmc-wlen {
+                compatible = "regulator-fixed";
+                regulator-name = "regulator-lbep5clwmc-wlen";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>;            /* gpio_139 - WL_EN */
+                enable-active-high;
+        };
+};
+&omap3_pmx_core {
+        lbep5clwmc_pins: pinmux_lbep5clwmc_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT | MUX_MODE4)        /* mcspi1_cs3.gpio_177 - W_IRQ */
+                        OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat5.gpio_137 - BT_EN */
+                        OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat7.gpio_139 - WL_EN */
+                >;
+        };
+};
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>;
+        vmmc-supply = <&lbep5clwmc_wlen>;
+        bus-width = <4>;
+        non-removable;
+};
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index b22caaaf774b..fea7f7edb45d 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -1,5 +1,5 @@
 /*
- * Device Tree Source for IGEPv2 Rev. (TI OMAP AM/DM37x)
+ * Device Tree Source for IGEPv2 Rev. C (TI OMAP AM/DM37x)
 *
 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
@@ -9,272 +9,59 @@
 * published by the Free Software Foundation.
 */
-#include "omap3-igep.dtsi"
+#include "omap3-igep0020-common.dtsi"
-#include "omap-gpmc-smsc9221.dtsi"
 / {
-        model = "IGEPv2 (TI OMAP AM/DM37x)";
+        model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)";
        compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3";
-        leds {
+        /* Regulator to trigger the WIFI_PDN signal of the Wifi module */
-                pinctrl-names = "default";
+        lbee1usjyc_pdn: lbee1usjyc_pdn {
-                pinctrl-0 = <&leds_pins>;
+                compatible = "regulator-fixed";
-                compatible = "gpio-leds";
+                regulator-name = "regulator-lbee1usjyc-pdn";
+                regulator-min-microvolt = <3300000>;
-                boot {
+                regulator-max-microvolt = <3300000>;
-                         label = "omap3:green:boot";
+                gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;    /* gpio_138 - WIFI_PDN */
-                         gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+                startup-delay-us = <10000>;
-                         default-state = "on";
+                enable-active-high;
-                };
-                user0 {
-                         label = "omap3:red:user0";
-                         gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
-                         default-state = "off";
-                };
-                user1 {
-                         label = "omap3:red:user1";
-                         gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
-                         default-state = "off";
-                };
-                user2 {
-                        label = "omap3:green:user1";
-                        gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
-                };
        };
-       /* HS USB Port 1 Power */
+        /* Regulator to trigger the RESET_N_W signal of the Wifi module */
-       hsusb1_power: hsusb1_power_reg {
+        lbee1usjyc_reset_n_w: lbee1usjyc_reset_n_w {
-               compatible = "regulator-fixed";
+                compatible = "regulator-fixed";
-               regulator-name = "hsusb1_vbus";
+                regulator-name = "regulator-lbee1usjyc-reset-n-w";
-               regulator-min-microvolt = <3300000>;
+                regulator-min-microvolt = <3300000>;
-               regulator-max-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
-               gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>;   /* GPIO LEDA */
+                gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>;    /* gpio_139 - RESET_N_W */
-               startup-delay-us = <70000>;
+                enable-active-high;
-       };
-        /* HS USB Host PHY on PORT 1 */
-        hsusb1_phy: hsusb1_phy {
-                compatible = "usb-nop-xceiv";
-                reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
-                vcc-supply = <&hsusb1_power>;
-        };
-        tfp410: encoder@0 {
-                compatible = "ti,tfp410";
-                powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        port@0 {
-                                reg = <0>;
-                                tfp410_in: endpoint@0 {
-                                        remote-endpoint = <&dpi_out>;
-                                };
-                        };
-                        port@1 {
-                                reg = <1>;
-                                tfp410_out: endpoint@0 {
-                                        remote-endpoint = <&dvi_connector_in>;
-                                };
-                        };
-                };
-        };
-        dvi0: connector@0 {
-                compatible = "dvi-connector";
-                label = "dvi";
-                digital;
-                ddc-i2c-bus = <&i2c3>;
-                port {
-                        dvi_connector_in: endpoint {
-                                remote-endpoint = <&tfp410_out>;
-                        };
-                };
        };
 };
 &omap3_pmx_core {
-        pinctrl-names = "default";
+        lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
-        pinctrl-0 = <
-                &tfp410_pins
-                &dss_dpi_pins
-        >;
-        tfp410_pins: pinmux_tfp410_pins {
                pinctrl-single,pins = <
-                        0x196 (PIN_OUTPUT | MUX_MODE4)   /* hdq_sio.gpio_170 */
+                        OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat5.gpio_137 - RESET_N_W */
+                        OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat6.gpio_138 - WIFI_PDN */
+                        OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat7.gpio_139 - RST_N_B */
                >;
        };
-        dss_dpi_pins: pinmux_dss_dpi_pins {
+        uart2_pins: pinmux_uart2_pins {
                pinctrl-single,pins = <
-                        0x0a4 (PIN_OUTPUT | MUX_MODE0)   /* dss_pclk.dss_pclk */
+                        OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0)        /* uart2_cts.uart2_cts */
-                        0x0a6 (PIN_OUTPUT | MUX_MODE0)   /* dss_hsync.dss_hsync */
+                        OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0)       /* uart2_rts .uart2_rts*/
-                        0x0a8 (PIN_OUTPUT | MUX_MODE0)   /* dss_vsync.dss_vsync */
+                        OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0)       /* uart2_tx.uart2_tx */
-                        0x0aa (PIN_OUTPUT | MUX_MODE0)   /* dss_acbias.dss_acbias */
+                        OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0)        /* uart2_rx.uart2_rx */
-                        0x0ac (PIN_OUTPUT | MUX_MODE0)   /* dss_data0.dss_data0 */
-                        0x0ae (PIN_OUTPUT | MUX_MODE0)   /* dss_data1.dss_data1 */
-                        0x0b0 (PIN_OUTPUT | MUX_MODE0)   /* dss_data2.dss_data2 */
-                        0x0b2 (PIN_OUTPUT | MUX_MODE0)   /* dss_data3.dss_data3 */
-                        0x0b4 (PIN_OUTPUT | MUX_MODE0)   /* dss_data4.dss_data4 */
-                        0x0b6 (PIN_OUTPUT | MUX_MODE0)   /* dss_data5.dss_data5 */
-                        0x0b8 (PIN_OUTPUT | MUX_MODE0)   /* dss_data6.dss_data6 */
-                        0x0ba (PIN_OUTPUT | MUX_MODE0)   /* dss_data7.dss_data7 */
-                        0x0bc (PIN_OUTPUT | MUX_MODE0)   /* dss_data8.dss_data8 */
-                        0x0be (PIN_OUTPUT | MUX_MODE0)   /* dss_data9.dss_data9 */
-                        0x0c0 (PIN_OUTPUT | MUX_MODE0)   /* dss_data10.dss_data10 */
-                        0x0c2 (PIN_OUTPUT | MUX_MODE0)   /* dss_data11.dss_data11 */
-                        0x0c4 (PIN_OUTPUT | MUX_MODE0)   /* dss_data12.dss_data12 */
-                        0x0c6 (PIN_OUTPUT | MUX_MODE0)   /* dss_data13.dss_data13 */
-                        0x0c8 (PIN_OUTPUT | MUX_MODE0)   /* dss_data14.dss_data14 */
-                        0x0ca (PIN_OUTPUT | MUX_MODE0)   /* dss_data15.dss_data15 */
-                        0x0cc (PIN_OUTPUT | MUX_MODE0)   /* dss_data16.dss_data16 */
-                        0x0ce (PIN_OUTPUT | MUX_MODE0)   /* dss_data17.dss_data17 */
-                        0x0d0 (PIN_OUTPUT | MUX_MODE0)   /* dss_data18.dss_data18 */
-                        0x0d2 (PIN_OUTPUT | MUX_MODE0)   /* dss_data19.dss_data19 */
-                        0x0d4 (PIN_OUTPUT | MUX_MODE0)   /* dss_data20.dss_data20 */
-                        0x0d6 (PIN_OUTPUT | MUX_MODE0)   /* dss_data21.dss_data21 */
-                        0x0d8 (PIN_OUTPUT | MUX_MODE0)   /* dss_data22.dss_data22 */
-                        0x0da (PIN_OUTPUT | MUX_MODE0)   /* dss_data23.dss_data23 */
                >;
        };
 };
-&omap3_pmx_core2 {
+/* On board Wifi module */
+&mmc2 {
        pinctrl-names = "default";
-        pinctrl-0 = <
+        pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>;
-                &hsusbb1_pins
+        vmmc-supply = <&lbee1usjyc_pdn>;
-        >;
+        vmmc_aux-supply = <&lbee1usjyc_reset_n_w>;
+        bus-width = <4>;
-        hsusbb1_pins: pinmux_hsusbb1_pins {
+        non-removable;
-                pinctrl-single,pins = <
-                        OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3)            /* etk_ctl.hsusb1_clk */
-                        OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3)            /* etk_clk.hsusb1_stp */
-                        OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d8.hsusb1_dir */
-                        OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d9.hsusb1_nxt */
-                        OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d0.hsusb1_data0 */
-                        OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d1.hsusb1_data1 */
-                        OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d2.hsusb1_data2 */
-                        OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d3.hsusb1_data7 */
-                        OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d4.hsusb1_data4 */
-                        OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d5.hsusb1_data5 */
-                        OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d6.hsusb1_data6 */
-                        OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d7.hsusb1_data3 */
-                >;
-        };
-        leds_pins: pinmux_leds_pins {
-                pinctrl-single,pins = <
-                        OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
-                        OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
-                        OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
-                >;
-        };
-};
-&i2c3 {
-        clock-frequency = <100000>;
-        /*
-         * Display monitor features are burnt in the EEPROM
-         * as EDID data.
-         */
-        eeprom@50 {
-                compatible = "ti,eeprom";
-                reg = <0x50>;
-        };
-};
-&gpmc {
-        ranges = <0 0 0x00000000 0x20000000>,
-                 <5 0 0x2c000000 0x01000000>;
-        nand@0,0 {
-                linux,mtd-name= "micron,mt29c4g96maz";
-                reg = <0 0 0>;
-                nand-bus-width = <16>;
-                ti,nand-ecc-opt = "bch8";
-                gpmc,sync-clk-ps = <0>;
-                gpmc,cs-on-ns = <0>;
-                gpmc,cs-rd-off-ns = <44>;
-                gpmc,cs-wr-off-ns = <44>;
-                gpmc,adv-on-ns = <6>;
-                gpmc,adv-rd-off-ns = <34>;
-                gpmc,adv-wr-off-ns = <44>;
-                gpmc,we-off-ns = <40>;
-                gpmc,oe-off-ns = <54>;
-                gpmc,access-ns = <64>;
-                gpmc,rd-cycle-ns = <82>;
-                gpmc,wr-cycle-ns = <82>;
-                gpmc,wr-access-ns = <40>;
-                gpmc,wr-data-mux-bus-ns = <0>;
-                #address-cells = <1>;
-                #size-cells = <1>;
-                partition@0 {
-                        label = "SPL";
-                        reg = <0 0x100000>;
-                };
-                partition@80000 {
-                        label = "U-Boot";
-                        reg = <0x100000 0x180000>;
-                };
-                partition@1c0000 {
-                        label = "Environment";
-                        reg = <0x280000 0x100000>;
-                };
-                partition@280000 {
-                        label = "Kernel";
-                        reg = <0x380000 0x300000>;
-                };
-                partition@780000 {
-                        label = "Filesystem";
-                        reg = <0x680000 0x1f980000>;
-                };
-        };
-        ethernet@gpmc {
-                pinctrl-names = "default";
-                pinctrl-0 = <&smsc9221_pins>;
-                reg = <5 0 0xff>;
-                interrupt-parent = <&gpio6>;
-                interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
-        };
-};
-&usbhshost {
-        port1-mode = "ehci-phy";
-};
-&usbhsehci {
-        phys = <&hsusb1_phy>;
-};
-&vpll2 {
-        /* Needed for DSS */
-        regulator-name = "vdds_dsi";
-};
-&dss {
-        status = "ok";
-        port {
-                dpi_out: endpoint {
-                        remote-endpoint = <&tfp410_in>;
-                        data-lines = <24>;
-                };
-        };
 };
diff --git a/arch/arm/boot/dts/omap3-igep0030-common.dtsi b/arch/arm/boot/dts/omap3-igep0030-common.dtsi
new file mode 100644
index 000000000000..0cb1527c39d4
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-igep0030-common.dtsi
@@ -0,0 +1,60 @@
+/*
+ * Common Device Tree Source for IGEP COM MODULE
+ *
+ * Copyright (C) 2014 Javier Martinez Canillas <javier@collabora.co.uk>
+ * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "omap3-igep.dtsi"
+/ {
+        leds: gpio_leds {
+                compatible = "gpio-leds";
+                user0 {
+                         label = "omap3:red:user0";
+                         gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>;        /* LEDA */
+                         default-state = "off";
+                };
+                user1 {
+                         label = "omap3:green:user1";
+                         gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;        /* LEDB */
+                         default-state = "off";
+                };
+                user2 {
+                         label = "omap3:red:user1";
+                         gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;           /* gpio_16 */
+                         default-state = "off";
+                };
+        };
+};
+&omap3_pmx_core {
+        uart2_pins: pinmux_uart2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1)        /* mcbsp3_dx.uart2_cts */
+                        OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1)       /* mcbsp3_dr.uart2_rts */
+                        OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1)       /* mcbsp3_clk.uart2_tx */
+                        OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1)        /* mcbsp3_fsx.uart2_rx */
+                >;
+        };
+};
+&omap3_pmx_core2 {
+        leds_core2_pins: pinmux_leds_core2_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4)    /* etk_d2.gpio_16 */
+                >;
+        };
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart2_pins>;
+};
diff --git a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
new file mode 100644
index 000000000000..9326b282c94a
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
@@ -0,0 +1,67 @@
+/*
+ * Device Tree Source for IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)
+ *
+ * Copyright (C) 2014 Javier Martinez Canillas <javier@collabora.co.uk>
+ * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "omap3-igep0030-common.dtsi"
+/ {
+        model = "IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)";
+        compatible = "isee,omap3-igep0030-rev-g", "ti,omap36xx", "ti,omap3";
+        /* Regulator to trigger the WL_EN signal of the Wifi module */
+        lbep5clwmc_wlen: regulator-lbep5clwmc-wlen {
+                compatible = "regulator-fixed";
+                regulator-name = "regulator-lbep5clwmc-wlen";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>;            /* gpio_139 - WL_EN */
+                enable-active-high;
+        };
+};
+&omap3_pmx_core {
+        lbep5clwmc_pins: pinmux_lbep5clwmc_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4)        /* sdmmc2_dat4.gpio_136 - W_IRQ */
+                        OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat5.gpio_137 - BT_EN */
+                        OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat7.gpio_139 - WL_EN */
+                >;
+        };
+        leds_pins: pinmux_leds_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4)       /* i2c2_scl.gpio_168 */
+                >;
+        };
+};
+&i2c2 {
+        status = "disabled";
+};
+&leds {
+        pinctrl-names = "default";
+        pinctrl-0 = <&leds_pins &leds_core2_pins>;
+        boot {
+                label = "omap3:green:boot";
+                gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
+                default-state = "on";
+        };
+};
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>;
+        vmmc-supply = <&lbep5clwmc_wlen>;
+        bus-width = <4>;
+        non-removable;
+};
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index 2793749eb1ba..8150f47ccdf5 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -1,5 +1,5 @@
 /*
- * Device Tree Source for IGEP COM MODULE (TI OMAP AM/DM37x)
+ * Device Tree Source for IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)
 *
 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
@@ -9,97 +9,62 @@
 * published by the Free Software Foundation.
 */
-#include "omap3-igep.dtsi"
+#include "omap3-igep0030-common.dtsi"
 / {
-        model = "IGEP COM MODULE (TI OMAP AM/DM37x)";
+        model = "IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)";
        compatible = "isee,omap3-igep0030", "ti,omap36xx", "ti,omap3";
-        leds {
+        /* Regulator to trigger the WIFI_PDN signal of the Wifi module */
-                pinctrl-names = "default";
+        lbee1usjyc_pdn: lbee1usjyc_pdn {
-                pinctrl-0 = <&leds_pins>;
+                compatible = "regulator-fixed";
-                compatible = "gpio-leds";
+                regulator-name = "regulator-lbee1usjyc-pdn";
+                regulator-min-microvolt = <3300000>;
-                boot {
+                regulator-max-microvolt = <3300000>;
-                         label = "omap3:green:boot";
+                gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;    /* gpio_138 - WIFI_PDN */
-                         gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>;
+                startup-delay-us = <10000>;
-                         default-state = "on";
+                enable-active-high;
-                };
+        };
-                user0 {
-                         label = "omap3:red:user0";
-                         gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
-                         default-state = "off";
-                };
-                user1 {
-                         label = "omap3:green:user1";
-                         gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */
-                         default-state = "off";
-                };
-                user2 {
+        /* Regulator to trigger the RESET_N_W signal of the Wifi module */
-                         label = "omap3:red:user1";
+        lbee1usjyc_reset_n_w: lbee1usjyc_reset_n_w {
-                         gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
+                compatible = "regulator-fixed";
-                         default-state = "off";
+                regulator-name = "regulator-lbee1usjyc-reset-n-w";
-                };
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>;    /* gpio_139 - RESET_N_W */
+                enable-active-high;
        };
 };
-&omap3_pmx_core2 {
+&omap3_pmx_core {
-        leds_pins: pinmux_leds_pins {
+        lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
                pinctrl-single,pins = <
-                        OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
+                        OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat5.gpio_137 - RESET_N_W */
+                        OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat6.gpio_138 - WIFI_PDN */
+                        OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat7.gpio_139 - RST_N_B */
                >;
        };
 };
-&gpmc {
+&leds {
-        ranges = <0 0 0x00000000 0x20000000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&leds_core2_pins>;
-        nand@0,0 {
-                linux,mtd-name= "micron,mt29c4g96maz";
-                reg = <0 0 0>;
-                nand-bus-width = <16>;
-                ti,nand-ecc-opt = "bch8";
-                gpmc,sync-clk-ps = <0>;
+        boot {
-                gpmc,cs-on-ns = <0>;
+                label = "omap3:green:boot";
-                gpmc,cs-rd-off-ns = <44>;
+                gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; /* LEDSYNC */
-                gpmc,cs-wr-off-ns = <44>;
+                default-state = "on";
-                gpmc,adv-on-ns = <6>;
-                gpmc,adv-rd-off-ns = <34>;
-                gpmc,adv-wr-off-ns = <44>;
-                gpmc,we-off-ns = <40>;
-                gpmc,oe-off-ns = <54>;
-                gpmc,access-ns = <64>;
-                gpmc,rd-cycle-ns = <82>;
-                gpmc,wr-cycle-ns = <82>;
-                gpmc,wr-access-ns = <40>;
-                gpmc,wr-data-mux-bus-ns = <0>;
-                #address-cells = <1>;
-                #size-cells = <1>;
-                partition@0 {
-                        label = "SPL";
-                        reg = <0 0x100000>;
-                };
-                partition@80000 {
-                        label = "U-Boot";
-                        reg = <0x100000 0x180000>;
-                };
-                partition@1c0000 {
-                        label = "Environment";
-                        reg = <0x280000 0x100000>;
-                };
-                partition@280000 {
-                        label = "Kernel";
-                        reg = <0x380000 0x300000>;
-                };
-                partition@780000 {
-                        label = "Filesystem";
-                        reg = <0x680000 0x1f980000>;
-                };
        };
 };
+/* On board Wifi module */
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>;
+        vmmc-supply = <&lbee1usjyc_pdn>;
+        vmmc_aux-supply = <&lbee1usjyc_reset_n_w>;
+        bus-width = <4>;
+        non-removable;
+};
diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts
index 72dca0b7904d..b699bc48f242 100644
--- a/arch/arm/boot/dts/omap3-ldp.dts
+++ b/arch/arm/boot/dts/omap3-ldp.dts
@@ -7,6 +7,7 @@
 */
 /dts-v1/;
+#include <dt-bindings/input/input.h>
 #include "omap34xx.dtsi"
 #include "omap-gpmc-smsc911x.dtsi"
@@ -101,8 +102,9 @@
        nand@0,0 {
                linux,mtd-name= "micron,nand";
-                reg = <0 0 0>;
+                reg = <0 0 4>;  /* CS0, offset 0, IO size 4 */
                nand-bus-width = <16>;
+                gpmc,device-width = <2>;
                ti,nand-ecc-opt = "bch8";
                gpmc,sync-clk-ps = <0>;
@@ -141,7 +143,7 @@
                };
                partition@2000000 {
                        label = "Filesystem";
-                        reg = <0x2000000 0xe000000>;
+                        reg = <0x2000000 0x6000000>;
                };
        };
@@ -263,6 +265,26 @@
        };
 };
+&twl_keypad {
+        linux,keymap = <MATRIX_KEY(0, 0, KEY_1)
+                        MATRIX_KEY(0, 1, KEY_2)
+                        MATRIX_KEY(0, 2, KEY_3)
+                        MATRIX_KEY(1, 0, KEY_4)
+                        MATRIX_KEY(1, 1, KEY_5)
+                        MATRIX_KEY(1, 2, KEY_6)
+                        MATRIX_KEY(1, 3, KEY_F5)
+                        MATRIX_KEY(2, 0, KEY_7)
+                        MATRIX_KEY(2, 1, KEY_8)
+                        MATRIX_KEY(2, 2, KEY_9)
+                        MATRIX_KEY(2, 3, KEY_F6)
+                        MATRIX_KEY(3, 0, KEY_F7)
+                        MATRIX_KEY(3, 1, KEY_0)
+                        MATRIX_KEY(3, 2, KEY_F8)
+                        MATRIX_KEY(5, 4, KEY_RESERVED)
+                        MATRIX_KEY(4, 4, KEY_VOLUMEUP)
+                        MATRIX_KEY(5, 5, KEY_VOLUMEDOWN)>;
+};
 &uart3 {
        interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
 };
diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
index d97308896f0c..e81fb651d5d0 100644
--- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
+++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
@@ -363,7 +363,7 @@
                <7 0 0x15000000 0x01000000>;
        nand@0,0 {
-                reg = <0 0 0x1000000>;
+                reg = <0 0 4>;  /* CS0, offset 0, IO size 4 */
                nand-bus-width = <16>;
                ti,nand-ecc-opt = "bch8";
                /* no elm on omap3 */
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index bc82a12d4c2c..53f3ca064140 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -115,6 +115,12 @@
                eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */
                speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>;
        };
+        battery: n900-battery {
+                compatible = "nokia,n900-battery";
+                io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>;
+                io-channel-names = "temp", "bsi", "vbat";
+        };
 };
 &omap3_pmx_core {
@@ -142,6 +148,33 @@
                >;
        };
+        gpmc_pins: pinmux_gpmc_pins {
+                pinctrl-single,pins = <
+                        /* address lines */
+                        OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0)       /* gpmc_a1.gpmc_a1 */
+                        OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0)       /* gpmc_a2.gpmc_a2 */
+                        OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0)       /* gpmc_a3.gpmc_a3 */
+                        /* data lines, gpmc_d0..d7 not muxable according to TRM */
+                        OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0)        /* gpmc_d8.gpmc_d8 */
+                        OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0)        /* gpmc_d9.gpmc_d9 */
+                        OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0)        /* gpmc_d10.gpmc_d10 */
+                        OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0)        /* gpmc_d11.gpmc_d11 */
+                        OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0)        /* gpmc_d12.gpmc_d12 */
+                        OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0)        /* gpmc_d13.gpmc_d13 */
+                        OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0)        /* gpmc_d14.gpmc_d14 */
+                        OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0)        /* gpmc_d15.gpmc_d15 */
+                        /*
+                         * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable
+                         * according to TRM. OneNAND seems to require PIN_INPUT on clock.
+                         */
+                        OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0)       /* gpmc_ncs1.gpmc_ncs1 */
+                        OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0)        /* gpmc_clk.gpmc_clk */
+                >;
+        };
        i2c1_pins: pinmux_i2c1_pins {
                pinctrl-single,pins = <
                        0x18a (PIN_INPUT | MUX_MODE0)           /* i2c1_scl */
@@ -540,6 +573,16 @@
                power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */
        };
+        si4713: si4713@63 {
+                compatible = "silabs,si4713";
+                reg = <0x63>;
+                interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */
+                reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */
+                vio-supply = <&vio>;
+                vdd-supply = <&vaux1>;
+        };
        bq24150a: bq24150a@6b {
                compatible = "ti,bq24150a";
                reg = <0x6b>;
@@ -585,16 +628,16 @@
 };
 &gpmc {
-        ranges = <0 0 0x04000000 0x10000000>; /* 256MB */
        ranges = <0 0 0x01000000 0x01000000>,   /* 16 MB for OneNAND */
                 <1 0 0x02000000 0x01000000>;   /* 16 MB for smc91c96 */
+        pinctrl-names = "default";
+        pinctrl-0 = <&gpmc_pins>;
-        /* gpio-irq for dma: 65 */
+        /* sys_ndmareq1 could be used by the driver, not as gpio65 though */
        onenand@0,0 {
                #address-cells = <1>;
                #size-cells = <1>;
-                reg = <0 0 0x10000000>;
+                reg = <0 0 0x20000>;    /* CS0, offset 0, IO size 128K */
                gpmc,sync-read;
                gpmc,sync-write;
diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi
index 70addcba37c5..1e49dfe7e212 100644
--- a/arch/arm/boot/dts/omap3-n950-n9.dtsi
+++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi
@@ -115,12 +115,12 @@
 };
 &gpmc {
-        ranges = <0 0 0x04000000 0x20000000>;
+        ranges = <0 0 0x04000000 0x1000000>;    /* CS0: 16MB for OneNAND */
        onenand@0,0 {
                #address-cells = <1>;
                #size-cells = <1>;
-                reg = <0 0 0x20000000>;
+                reg = <0 0 0x20000>;    /* CS0, offset 0, IO size 128K */
                gpmc,sync-read;
                gpmc,sync-write;
diff --git a/arch/arm/boot/dts/omap3-sb-t35.dtsi b/arch/arm/boot/dts/omap3-sb-t35.dtsi
index d59e3de1441e..827f614261f6 100644
--- a/arch/arm/boot/dts/omap3-sb-t35.dtsi
+++ b/arch/arm/boot/dts/omap3-sb-t35.dtsi
@@ -2,6 +2,59 @@
 * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730
 */
+/ {
+        tfp410: encoder@0 {
+                compatible = "ti,tfp410";
+                powerdown-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;  /* gpio_54 */
+                pinctrl-names = "default";
+                pinctrl-0 = <&tfp410_pins>;
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                tfp410_in: endpoint@0 {
+                                        remote-endpoint = <&dpi_out>;
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                tfp410_out: endpoint@0 {
+                                        remote-endpoint = <&dvi_connector_in>;
+                                };
+                        };
+                };
+        };
+        dvi0: connector@0 {
+                compatible = "dvi-connector";
+                label = "dvi";
+                port {
+                        dvi_connector_in: endpoint {
+                                remote-endpoint = <&tfp410_out>;
+                        };
+                };
+        };
+        audio_amp: audio_amp {
+                compatible = "regulator-fixed";
+                regulator-name = "audio_amp";
+                pinctrl-names = "default";
+                pinctrl-0 = <&sb_t35_audio_amp>;
+                gpio = <&gpio2 29 GPIO_ACTIVE_LOW>;   /* gpio_61 */
+                enable-active-low;
+                regulator-always-on;
+        };
+};
 &omap3_pmx_core {
        smsc2_pins: pinmux_smsc2_pins {
                pinctrl-single,pins = <
@@ -9,6 +62,38 @@
                        OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */
                >;
        };
+        tfp410_pins: pinmux_tfp410_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4)       /* gpmc_ncs3.gpio_54 */
+                >;
+        };
+        i2c3_pins: pinmux_i2c3_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */
+                        OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */
+                >;
+        };
+        sb_t35_audio_amp: pinmux_sb_t35_audio_amp {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) /* gpmc_nbe1.gpio_61 */
+                >;
+        };
+};
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c3_pins>;
+        clock-frequency = <400000>;
+        at24@50 {
+                compatible = "at24,24c02";
+                pagesize = <16>;
+                reg = <0x50>;
+        };
 };
 &gpmc {
@@ -22,24 +107,29 @@
                interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
                reg = <4 0 0xff>;
                bank-width = <2>;
-                gpmc,mux-add-data;
+                gpmc,device-width = <1>;
-                gpmc,cs-on-ns = <1>;
+                gpmc,cycle2cycle-samecsen = <1>;
-                gpmc,cs-rd-off-ns = <180>;
+                gpmc,cycle2cycle-diffcsen = <1>;
-                gpmc,cs-wr-off-ns = <180>;
+                gpmc,cs-on-ns = <5>;
-                gpmc,adv-rd-off-ns = <18>;
+                gpmc,cs-rd-off-ns = <150>;
-                gpmc,adv-wr-off-ns = <48>;
+                gpmc,cs-wr-off-ns = <150>;
-                gpmc,oe-on-ns = <54>;
+                gpmc,adv-on-ns = <0>;
-                gpmc,oe-off-ns = <168>;
+                gpmc,adv-rd-off-ns = <15>;
-                gpmc,we-on-ns = <54>;
+                gpmc,adv-wr-off-ns = <40>;
-                gpmc,we-off-ns = <168>;
+                gpmc,oe-on-ns = <45>;
-                gpmc,rd-cycle-ns = <186>;
+                gpmc,oe-off-ns = <140>;
-                gpmc,wr-cycle-ns = <186>;
+                gpmc,we-on-ns = <45>;
-                gpmc,access-ns = <144>;
+                gpmc,we-off-ns = <140>;
-                gpmc,page-burst-access-ns = <24>;
+                gpmc,rd-cycle-ns = <155>;
-                gpmc,bus-turnaround-ns = <90>;
+                gpmc,wr-cycle-ns = <155>;
-                gpmc,cycle2cycle-delay-ns = <90>;
+                gpmc,access-ns = <120>;
-                gpmc,cycle2cycle-samecsen;
+                gpmc,page-burst-access-ns = <20>;
-                gpmc,cycle2cycle-diffcsen;
+                gpmc,bus-turnaround-ns = <75>;
+                gpmc,cycle2cycle-delay-ns = <75>;
+                gpmc,wait-monitoring-ns = <0>;
+                gpmc,clk-activation-ns = <0>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+                gpmc,wr-access-ns = <0>;
                vddvario-supply = <&vddvario>;
                vdd33a-supply = <&vdd33a>;
                reg-io-width = <4>;
diff --git a/arch/arm/boot/dts/omap3-sbc-t3517.dts b/arch/arm/boot/dts/omap3-sbc-t3517.dts
index 42189b65d393..17986536c61f 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3517.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3517.dts
@@ -9,6 +9,11 @@
        model = "CompuLab SBC-T3517 with CM-T3517";
        compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3";
+        aliases {
+                display0 = &dvi0;
+                display1 = &tv0;
+        };
        /* Only one GPMC smsc9220 on SBC-T3517, CM-T3517 uses am35x Ethernet */
        vddvario: regulator-vddvario-sb-t35 {
                compatible = "regulator-fixed";
@@ -54,3 +59,13 @@
        wp-gpios =  <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio_59  */
        cd-gpios =  <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */
 };
+&dss {
+        port {
+                dpi_out: endpoint {
+                        remote-endpoint = <&tfp410_in>;
+                        data-lines = <24>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-sbc-t3530.dts b/arch/arm/boot/dts/omap3-sbc-t3530.dts
index bbbeea6b1988..c994f0f7e38a 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3530.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3530.dts
@@ -8,6 +8,11 @@
 / {
        model = "CompuLab SBC-T3530 with CM-T3530";
        compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3";
+        aliases {
+                display0 = &dvi0;
+                display1 = &tv0;
+        };
 };
 &omap3_pmx_core {
@@ -34,3 +39,13 @@
 &mmc1 {
        cd-gpios =  <&twl_gpio 0 GPIO_ACTIVE_HIGH>;
 };
+&dss {
+        port {
+                dpi_out: endpoint {
+                        remote-endpoint = <&tfp410_in>;
+                        data-lines = <24>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-sbc-t3730.dts b/arch/arm/boot/dts/omap3-sbc-t3730.dts
index 08e4a7086f22..5bdddf29341d 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3730.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3730.dts
@@ -8,6 +8,11 @@
 / {
        model = "CompuLab SBC-T3730 with CM-T3730";
        compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3";
+        aliases {
+                display0 = &dvi0;
+                display1 = &tv0;
+        };
 };
 &omap3_pmx_core {
@@ -25,3 +30,13 @@
        ranges = <5 0 0x2c000000 0x01000000>,
                 <4 0 0x2d000000 0x01000000>;
 };
+&dss {
+        port {
+                dpi_out: endpoint {
+                        remote-endpoint = <&tfp410_in>;
+                        data-lines = <24>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi
index b30f387d3a83..e89820a6776e 100644
--- a/arch/arm/boot/dts/omap3-tao3530.dtsi
+++ b/arch/arm/boot/dts/omap3-tao3530.dtsi
@@ -270,7 +270,7 @@
        ranges = <0 0 0x00000000 0x01000000>;
        nand@0,0 {
-                reg = <0 0 0>; /* CS0, offset 0 */
+                reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
                nand-bus-width = <16>;
                gpmc,device-width = <2>;        /* GPMC_DEVWIDTH_16BIT */
                ti,nand-ecc-opt = "sw";
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index d0e884d3a737..01b71111bd55 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -79,7 +79,7 @@
         * hierarchy.
         */
        ocp {
-                compatible = "simple-bus";
+                compatible = "ti,omap3-l3-smx", "simple-bus";
                reg = <0x68000000 0x10000>;
                interrupts = <9 10>;
                #address-cells = <1>;
@@ -332,6 +332,7 @@
                        ti,hwmods = "mailbox";
                        reg = <0x48094000 0x200>;
                        interrupts = <26>;
+                        #mbox-cells = <1>;
                        ti,mbox-num-users = <2>;
                        ti,mbox-num-fifos = <2>;
                        mbox_dsp: dsp {
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index 9bad94efe1c8..16b0cdfbee9c 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -51,8 +51,8 @@
 &gpmc {
        ranges = <0 0 0x10000000 0x08000000>,
-                 <1 0 0x28000000 0x08000000>,
+                 <1 0 0x28000000 0x1000000>,    /* CS1: 16MB for NAND */
-                 <2 0 0x20000000 0x10000000>;
+                 <2 0 0x20000000 0x1000000>;    /* CS2: 16MB for OneNAND */
        nor@0,0 {
                compatible = "cfi-flash";
@@ -106,7 +106,7 @@
                linux,mtd-name= "micron,mt29f1g08abb";
                #address-cells = <1>;
                #size-cells = <1>;
-                reg = <1 0 0x08000000>;
+                reg = <1 0 4>;  /* CS1, offset 0, IO size 4 */
                ti,nand-ecc-opt = "sw";
                nand-bus-width = <8>;
                gpmc,cs-on-ns = <0>;
@@ -150,7 +150,7 @@
                linux,mtd-name= "samsung,kfm2g16q2m-deb8";
                #address-cells = <1>;
                #size-cells = <1>;
-                reg = <2 0 0x10000000>;
+                reg = <2 0 0x20000>;    /* CS2, offset 0, IO size 4 */
                gpmc,device-width = <2>;
                gpmc,mux-add-data = <2>;
diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/omap4-duovero-parlor.dts
index 6dc84d9f9b4c..1a78f013f37a 100644
--- a/arch/arm/boot/dts/omap4-duovero-parlor.dts
+++ b/arch/arm/boot/dts/omap4-duovero-parlor.dts
@@ -177,6 +177,7 @@
 &hdmi {
        status = "ok";
+        vdda-supply = <&vdac>;
        pinctrl-names = "default";
        pinctrl-0 = <&dss_hdmi_pins>;
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 878c979203d0..074147cebae4 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -661,6 +661,7 @@
                        reg = <0x4a0f4000 0x200>;
                        interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mailbox";
+                        #mbox-cells = <1>;
                        ti,mbox-num-users = <3>;
                        ti,mbox-num-fifos = <8>;
                        mbox_ipu: mbox_ipu {
@@ -895,7 +896,7 @@
                                reg = <0x58002000 0x1000>;
                                status = "disabled";
                                ti,hwmods = "dss_rfbi";
-                                clocks = <&dss_dss_clk>, <&dss_fck>;
+                                clocks = <&dss_dss_clk>, <&l3_div_ck>;
                                clock-names = "fck", "ick";
                        };
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
index c821ff5e9b8d..f2c48f09824e 100644
--- a/arch/arm/boot/dts/omap44xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -1018,14 +1018,6 @@
                reg = <0x1120>;
        };
-        dss_fck: dss_fck {
-                #clock-cells = <0>;
-                compatible = "ti,gate-clock";
-                clocks = <&l3_div_ck>;
-                ti,bit-shift = <1>;
-                reg = <0x1120>;
-        };
        fdif_fck: fdif_fck {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 256b7f69e45b..b321fdf42c9f 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -651,6 +651,7 @@
                        reg = <0x4a0f4000 0x200>;
                        interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "mailbox";
+                        #mbox-cells = <1>;
                        ti,mbox-num-users = <3>;
                        ti,mbox-num-fifos = <8>;
                        mbox_ipu: mbox_ipu {
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 963b7e54ab15..1ca1a9aa953f 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -41,6 +41,11 @@
                };
        };
+        arm-pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupts = <29>;
+        };
        axi {
                compatible = "simple-bus";
                #address-cells = <1>;
@@ -132,6 +137,7 @@
                                reg = <0x90020000 0x10000>;
                                interrupts = <31>;
                                clocks = <&clks 35>;
+                                resets = <&rstc 6>;
                        };
                };
@@ -173,6 +179,7 @@
                                compatible = "sirf,prima2-dspif";
                                reg = <0xa8000000 0x10000>;
                                interrupts = <9>;
+                                resets = <&rstc 1>;
                        };
                        gps@a8010000 {
@@ -180,6 +187,7 @@
                                reg = <0xa8010000 0x10000>;
                                interrupts = <7>;
                                clocks = <&clks 9>;
+                                resets = <&rstc 2>;
                        };
                        dsp@a9000000 {
@@ -187,6 +195,7 @@
                                reg = <0xa9000000 0x1000000>;
                                interrupts = <8>;
                                clocks = <&clks 8>;
+                                resets = <&rstc 0>;
                        };
                };
@@ -524,12 +533,36 @@
                                                sirf,function = "sdmmc5";
                                        };
                                };
+                                i2s_mclk_pins_a: i2s_mclk@0 {
+                                        i2s_mclk {
+                                                sirf,pins = "i2smclkgrp";
+                                                sirf,function = "i2s_mclk";
+                                        };
+                                };
+                                i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 {
+                                        i2s_ext_clk_input {
+                                                sirf,pins = "i2s_ext_clk_inputgrp";
+                                                sirf,function = "i2s_ext_clk_input";
+                                        };
+                                };
                                i2s_pins_a: i2s@0 {
                                        i2s {
                                                sirf,pins = "i2sgrp";
                                                sirf,function = "i2s";
                                        };
                                };
+                                i2s_no_din_pins_a: i2s_no_din@0 {
+                                        i2s_no_din {
+                                                sirf,pins = "i2s_no_dingrp";
+                                                sirf,function = "i2s_no_din";
+                                        };
+                                };
+                                i2s_6chn_pins_a: i2s_6chn@0 {
+                                        i2s_6chn {
+                                                sirf,pins = "i2s_6chngrp";
+                                                sirf,function = "i2s_6chn";
+                                        };
+                                };
                                ac97_pins_a: ac97@0 {
                                        ac97 {
                                                sirf,pins = "ac97grp";
diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index a3ed23c0a8f5..1518c5bcca33 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -21,7 +21,8 @@
        };
        chosen {
-                bootargs = "console=ttySC2,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
+                bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+                stdout-path = &scif2;
        };
        memory {
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 801a556e264b..277e73c110e5 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -52,16 +52,6 @@
                        clock-output-names = "usb_x1";
                };
-                /* Special CPG clocks */
-                cpg_clocks: cpg_clocks@fcfe0000 {
-                        #clock-cells = <1>;
-                        compatible = "renesas,r7s72100-cpg-clocks",
-                                     "renesas,rz-cpg-clocks";
-                        reg = <0xfcfe0000 0x18>;
-                        clocks = <&extal_clk>, <&usb_x1_clk>;
-                        clock-output-names = "pll", "i", "g";
-                };
                /* Fixed factor clocks */
                b_clk: b_clk {
                        #clock-cells = <0>;
@@ -88,6 +78,16 @@
                        clock-output-names = "p0";
                };
+                /* Special CPG clocks */
+                cpg_clocks: cpg_clocks@fcfe0000 {
+                        #clock-cells = <1>;
+                        compatible = "renesas,r7s72100-cpg-clocks",
+                                     "renesas,rz-cpg-clocks";
+                        reg = <0xfcfe0000 0x18>;
+                        clocks = <&extal_clk>, <&usb_x1_clk>;
+                        clock-output-names = "pll", "i", "g";
+                };
                /* MSTP clocks */
                mstp3_clks: mstp3_clks@fcfe0420 {
                        #clock-cells = <1>;
@@ -148,97 +148,6 @@
                };
        };
-        gic: interrupt-controller@e8201000 {
-                compatible = "arm,cortex-a9-gic";
-                #interrupt-cells = <3>;
-                #address-cells = <0>;
-                interrupt-controller;
-                reg = <0xe8201000 0x1000>,
-                        <0xe8202000 0x1000>;
-        };
-        i2c0: i2c@fcfee000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
-                reg = <0xfcfee000 0x44>;
-                interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>,
-                             <0 158 IRQ_TYPE_EDGE_RISING>,
-                             <0 159 IRQ_TYPE_EDGE_RISING>,
-                             <0 160 IRQ_TYPE_LEVEL_HIGH>,
-                             <0 161 IRQ_TYPE_LEVEL_HIGH>,
-                             <0 162 IRQ_TYPE_LEVEL_HIGH>,
-                             <0 163 IRQ_TYPE_LEVEL_HIGH>,
-                             <0 164 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
-                clock-frequency = <100000>;
-                status = "disabled";
-        };
-        i2c1: i2c@fcfee400 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
-                reg = <0xfcfee400 0x44>;
-                interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>,
-                             <0 166 IRQ_TYPE_EDGE_RISING>,
-                             <0 167 IRQ_TYPE_EDGE_RISING>,
-                             <0 168 IRQ_TYPE_LEVEL_HIGH>,
-                             <0 169 IRQ_TYPE_LEVEL_HIGH>,
-                             <0 170 IRQ_TYPE_LEVEL_HIGH>,
-                             <0 171 IRQ_TYPE_LEVEL_HIGH>,
-                             <0 172 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
-                clock-frequency = <100000>;
-                status = "disabled";
-        };
-        i2c2: i2c@fcfee800 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
-                reg = <0xfcfee800 0x44>;
-                interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>,
-                             <0 174 IRQ_TYPE_EDGE_RISING>,
-                             <0 175 IRQ_TYPE_EDGE_RISING>,
-                             <0 176 IRQ_TYPE_LEVEL_HIGH>,
-                             <0 177 IRQ_TYPE_LEVEL_HIGH>,
-                             <0 178 IRQ_TYPE_LEVEL_HIGH>,
-                             <0 179 IRQ_TYPE_LEVEL_HIGH>,
-                             <0 180 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
-                clock-frequency = <100000>;
-                status = "disabled";
-        };
-        i2c3: i2c@fcfeec00 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
-                reg = <0xfcfeec00 0x44>;
-                interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>,
-                             <0 182 IRQ_TYPE_EDGE_RISING>,
-                             <0 183 IRQ_TYPE_EDGE_RISING>,
-                             <0 184 IRQ_TYPE_LEVEL_HIGH>,
-                             <0 185 IRQ_TYPE_LEVEL_HIGH>,
-                             <0 186 IRQ_TYPE_LEVEL_HIGH>,
-                             <0 187 IRQ_TYPE_LEVEL_HIGH>,
-                             <0 188 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
-                clock-frequency = <100000>;
-                status = "disabled";
-        };
-        mtu2: timer@fcff0000 {
-                compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
-                reg = <0xfcff0000 0x400>;
-                interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "tgi0a";
-                clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
-                clock-names = "fck";
-                status = "disabled";
-        };
        scif0: serial@e8007000 {
                compatible = "renesas,scif-r7s72100", "renesas,scif";
                reg = <0xe8007000 64>;
@@ -404,4 +313,95 @@
                #size-cells = <0>;
                status = "disabled";
        };
+        gic: interrupt-controller@e8201000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0xe8201000 0x1000>,
+                        <0xe8202000 0x1000>;
+        };
+        i2c0: i2c@fcfee000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
+                reg = <0xfcfee000 0x44>;
+                interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 158 IRQ_TYPE_EDGE_RISING>,
+                             <0 159 IRQ_TYPE_EDGE_RISING>,
+                             <0 160 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 161 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 162 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 163 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 164 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
+                clock-frequency = <100000>;
+                status = "disabled";
+        };
+        i2c1: i2c@fcfee400 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
+                reg = <0xfcfee400 0x44>;
+                interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 166 IRQ_TYPE_EDGE_RISING>,
+                             <0 167 IRQ_TYPE_EDGE_RISING>,
+                             <0 168 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 169 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 170 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 171 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 172 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
+                clock-frequency = <100000>;
+                status = "disabled";
+        };
+        i2c2: i2c@fcfee800 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
+                reg = <0xfcfee800 0x44>;
+                interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 174 IRQ_TYPE_EDGE_RISING>,
+                             <0 175 IRQ_TYPE_EDGE_RISING>,
+                             <0 176 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 177 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 178 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 179 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 180 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
+                clock-frequency = <100000>;
+                status = "disabled";
+        };
+        i2c3: i2c@fcfeec00 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
+                reg = <0xfcfeec00 0x44>;
+                interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 182 IRQ_TYPE_EDGE_RISING>,
+                             <0 183 IRQ_TYPE_EDGE_RISING>,
+                             <0 184 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 185 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 186 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 187 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 188 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
+                clock-frequency = <100000>;
+                status = "disabled";
+        };
+        mtu2: timer@fcff0000 {
+                compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
+                reg = <0xfcff0000 0x400>;
+                interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "tgi0a";
+                clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
+                clock-names = "fck";
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
index a860f32bca27..84e05f713c54 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
@@ -21,7 +21,8 @@
        };
        chosen {
-                bootargs = "console=ttySC0,115200 ignore_loglevel rw";
+                bootargs = "ignore_loglevel rw";
+                stdout-path = &scifa0;
        };
        memory@40000000 {
@@ -93,6 +94,10 @@
        voltage-tolerance = <1>; /* 1% */
 };
+&cmt1 {
+        status = "okay";
+};
 &pfc {
        scifa0_pins: serial0 {
                renesas,groups = "scifa0_data";
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index ef152e384822..5ac57babc3b9 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -30,18 +30,6 @@
                };
        };
-        gic: interrupt-controller@f1001000 {
-                compatible = "arm,cortex-a15-gic";
-                #interrupt-cells = <3>;
-                #address-cells = <0>;
-                interrupt-controller;
-                reg = <0 0xf1001000 0 0x1000>,
-                        <0 0xf1002000 0 0x1000>,
-                        <0 0xf1004000 0 0x2000>,
-                        <0 0xf1006000 0 0x2000>;
-                interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-        };
        timer {
                compatible = "arm,armv7-timer";
                interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -50,6 +38,91 @@
                             <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
        };
+        dmac: dma-multiplexer {
+                compatible = "renesas,shdma-mux";
+                #dma-cells = <1>;
+                dma-channels = <20>;
+                dma-requests = <256>;
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+                dma0: dma-controller@e6700020 {
+                        compatible = "renesas,shdma-r8a73a4";
+                        reg = <0 0xe6700020 0 0x89e0>;
+                        interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
+                                        0 200 IRQ_TYPE_LEVEL_HIGH
+                                        0 201 IRQ_TYPE_LEVEL_HIGH
+                                        0 202 IRQ_TYPE_LEVEL_HIGH
+                                        0 203 IRQ_TYPE_LEVEL_HIGH
+                                        0 204 IRQ_TYPE_LEVEL_HIGH
+                                        0 205 IRQ_TYPE_LEVEL_HIGH
+                                        0 206 IRQ_TYPE_LEVEL_HIGH
+                                        0 207 IRQ_TYPE_LEVEL_HIGH
+                                        0 208 IRQ_TYPE_LEVEL_HIGH
+                                        0 209 IRQ_TYPE_LEVEL_HIGH
+                                        0 210 IRQ_TYPE_LEVEL_HIGH
+                                        0 211 IRQ_TYPE_LEVEL_HIGH
+                                        0 212 IRQ_TYPE_LEVEL_HIGH
+                                        0 213 IRQ_TYPE_LEVEL_HIGH
+                                        0 214 IRQ_TYPE_LEVEL_HIGH
+                                        0 215 IRQ_TYPE_LEVEL_HIGH
+                                        0 216 IRQ_TYPE_LEVEL_HIGH
+                                        0 217 IRQ_TYPE_LEVEL_HIGH
+                                        0 218 IRQ_TYPE_LEVEL_HIGH
+                                        0 219 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                        "ch0", "ch1", "ch2", "ch3",
+                                        "ch4", "ch5", "ch6", "ch7",
+                                        "ch8", "ch9", "ch10", "ch11",
+                                        "ch12", "ch13", "ch14", "ch15",
+                                        "ch16", "ch17", "ch18", "ch19";
+                };
+        };
+        pfc: pfc@e6050000 {
+                compatible = "renesas,pfc-r8a73a4";
+                reg = <0 0xe6050000 0 0x9000>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupts-extended =
+                        <&irqc0  0 0>, <&irqc0  1 0>, <&irqc0  2 0>, <&irqc0  3 0>,
+                        <&irqc0  4 0>, <&irqc0  5 0>, <&irqc0  6 0>, <&irqc0  7 0>,
+                        <&irqc0  8 0>, <&irqc0  9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
+                        <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
+                        <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
+                        <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
+                        <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
+                        <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
+                        <&irqc1  0 0>, <&irqc1  1 0>, <&irqc1  2 0>, <&irqc1  3 0>,
+                        <&irqc1  4 0>, <&irqc1  5 0>, <&irqc1  6 0>, <&irqc1  7 0>,
+                        <&irqc1  8 0>, <&irqc1  9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
+                        <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
+                        <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
+                        <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
+                        <&irqc1 24 0>, <&irqc1 25 0>;
+        };
+        i2c5: i2c@e60b0000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
+                reg = <0 0xe60b0000 0 0x428>;
+                interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+        cmt1: timer@e6130000 {
+                compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2";
+                reg = <0 0xe6130000 0 0x1004>;
+                interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
+                renesas,channels-mask = <0xff>;
+                status = "disabled";
+        };
        irqc0: interrupt-controller@e61c0000 {
                compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
                #interrupt-cells = <2>;
@@ -122,48 +195,6 @@
                             <0 57 IRQ_TYPE_LEVEL_HIGH>;
        };
-        dmac: dma-multiplexer@0 {
-                compatible = "renesas,shdma-mux";
-                #dma-cells = <1>;
-                dma-channels = <20>;
-                dma-requests = <256>;
-                #address-cells = <2>;
-                #size-cells = <2>;
-                ranges;
-                dma0: dma-controller@e6700020 {
-                        compatible = "renesas,shdma-r8a73a4";
-                        reg = <0 0xe6700020 0 0x89e0>;
-                        interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
-                                        0 200 IRQ_TYPE_LEVEL_HIGH
-                                        0 201 IRQ_TYPE_LEVEL_HIGH
-                                        0 202 IRQ_TYPE_LEVEL_HIGH
-                                        0 203 IRQ_TYPE_LEVEL_HIGH
-                                        0 204 IRQ_TYPE_LEVEL_HIGH
-                                        0 205 IRQ_TYPE_LEVEL_HIGH
-                                        0 206 IRQ_TYPE_LEVEL_HIGH
-                                        0 207 IRQ_TYPE_LEVEL_HIGH
-                                        0 208 IRQ_TYPE_LEVEL_HIGH
-                                        0 209 IRQ_TYPE_LEVEL_HIGH
-                                        0 210 IRQ_TYPE_LEVEL_HIGH
-                                        0 211 IRQ_TYPE_LEVEL_HIGH
-                                        0 212 IRQ_TYPE_LEVEL_HIGH
-                                        0 213 IRQ_TYPE_LEVEL_HIGH
-                                        0 214 IRQ_TYPE_LEVEL_HIGH
-                                        0 215 IRQ_TYPE_LEVEL_HIGH
-                                        0 216 IRQ_TYPE_LEVEL_HIGH
-                                        0 217 IRQ_TYPE_LEVEL_HIGH
-                                        0 218 IRQ_TYPE_LEVEL_HIGH
-                                        0 219 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupt-names = "error",
-                                        "ch0", "ch1", "ch2", "ch3",
-                                        "ch4", "ch5", "ch6", "ch7",
-                                        "ch8", "ch9", "ch10", "ch11",
-                                        "ch12", "ch13", "ch14", "ch15",
-                                        "ch16", "ch17", "ch18", "ch19";
-                };
-        };
        thermal@e61f0000 {
                compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
                reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
@@ -174,7 +205,7 @@
        i2c0: i2c@e6500000 {
                #address-cells = <1>;
                #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                reg = <0 0xe6500000 0 0x428>;
                interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
@@ -183,7 +214,7 @@
        i2c1: i2c@e6510000 {
                #address-cells = <1>;
                #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                reg = <0 0xe6510000 0 0x428>;
                interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
@@ -192,7 +223,7 @@
        i2c2: i2c@e6520000 {
                #address-cells = <1>;
                #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                reg = <0 0xe6520000 0 0x428>;
                interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
@@ -201,7 +232,7 @@
        i2c3: i2c@e6530000 {
                #address-cells = <1>;
                #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                reg = <0 0xe6530000 0 0x428>;
                interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
@@ -210,25 +241,16 @@
        i2c4: i2c@e6540000 {
                #address-cells = <1>;
                #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                reg = <0 0xe6540000 0 0x428>;
                interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
-        i2c5: i2c@e60b0000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
-                reg = <0 0xe60b0000 0 0x428>;
-                interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>;
-                status = "disabled";
-        };
        i2c6: i2c@e6550000 {
                #address-cells = <1>;
                #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                reg = <0 0xe6550000 0 0x428>;
                interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
@@ -237,7 +259,7 @@
        i2c7: i2c@e6560000 {
                #address-cells = <1>;
                #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                reg = <0 0xe6560000 0 0x428>;
                interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
@@ -246,12 +268,26 @@
        i2c8: i2c@e6570000 {
                #address-cells = <1>;
                #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                reg = <0 0xe6570000 0 0x428>;
                interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
+        scifb0: serial@e6c20000 {
+                compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
+                reg = <0 0xe6c20000 0 0x100>;
+                interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+        scifb1: serial@e6c30000 {
+                compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
+                reg = <0 0xe6c30000 0 0x100>;
+                interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
        scifa0: serial@e6c40000 {
                compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
                reg = <0 0xe6c40000 0 0x100>;
@@ -266,73 +302,20 @@
                status = "disabled";
        };
-        scifb2: serial@e6c20000 {
+        scifb2: serial@e6ce0000 {
-                compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
-                reg = <0 0xe6c20000 0 0x100>;
-                interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
-                status = "disabled";
-        };
-        scifb3: serial@e6c30000 {
-                compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
-                reg = <0 0xe6c30000 0 0x100>;
-                interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
-                status = "disabled";
-        };
-        scifb4: serial@e6ce0000 {
                compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
                reg = <0 0xe6ce0000 0 0x100>;
                interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
-        scifb5: serial@e6cf0000 {
+        scifb3: serial@e6cf0000 {
                compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
                reg = <0 0xe6cf0000 0 0x100>;
                interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
-        mmcif0: mmc@ee200000 {
-                compatible = "renesas,sh-mmcif";
-                reg = <0 0xee200000 0 0x80>;
-                interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
-                reg-io-width = <4>;
-                status = "disabled";
-        };
-        mmcif1: mmc@ee220000 {
-                compatible = "renesas,sh-mmcif";
-                reg = <0 0xee220000 0 0x80>;
-                interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
-                reg-io-width = <4>;
-                status = "disabled";
-        };
-        pfc: pfc@e6050000 {
-                compatible = "renesas,pfc-r8a73a4";
-                reg = <0 0xe6050000 0 0x9000>;
-                gpio-controller;
-                #gpio-cells = <2>;
-                interrupts-extended =
-                        <&irqc0  0 0>, <&irqc0  1 0>, <&irqc0  2 0>, <&irqc0  3 0>,
-                        <&irqc0  4 0>, <&irqc0  5 0>, <&irqc0  6 0>, <&irqc0  7 0>,
-                        <&irqc0  8 0>, <&irqc0  9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
-                        <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
-                        <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
-                        <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
-                        <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
-                        <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
-                        <&irqc1  0 0>, <&irqc1  1 0>, <&irqc1  2 0>, <&irqc1  3 0>,
-                        <&irqc1  4 0>, <&irqc1  5 0>, <&irqc1  6 0>, <&irqc1  7 0>,
-                        <&irqc1  8 0>, <&irqc1  9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
-                        <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
-                        <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
-                        <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
-                        <&irqc1 24 0>, <&irqc1 25 0>;
-        };
        sdhi0: sd@ee100000 {
                compatible = "renesas,sdhi-r8a73a4";
                reg = <0 0xee100000 0 0x100>;
@@ -356,4 +339,32 @@
                cap-sd-highspeed;
                status = "disabled";
        };
+        mmcif0: mmc@ee200000 {
+                compatible = "renesas,sh-mmcif";
+                reg = <0 0xee200000 0 0x80>;
+                interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
+                reg-io-width = <4>;
+                status = "disabled";
+        };
+        mmcif1: mmc@ee220000 {
+                compatible = "renesas,sh-mmcif";
+                reg = <0 0xee220000 0 0x80>;
+                interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
+                reg-io-width = <4>;
+                status = "disabled";
+        };
+        gic: interrupt-controller@f1001000 {
+                compatible = "arm,cortex-a15-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0 0xf1001000 0 0x1000>,
+                        <0 0xf1002000 0 0x1000>,
+                        <0 0xf1004000 0 0x2000>,
+                        <0 0xf1006000 0 0x2000>;
+                interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+        };
 };
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
index effb7b46f131..d4af4d86c6b0 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
@@ -25,6 +25,7 @@
        chosen {
                bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
+                stdout-path = &scifa1;
        };
        memory {
@@ -77,7 +78,7 @@
                regulator-boot-on;
        };
-        gpio-keys {
+        keyboard {
                compatible = "gpio-keys";
                power-key {
@@ -298,3 +299,7 @@
        status = "okay";
 };
+&tmu0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index eed697a6bd6b..a8a674bafa67 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -71,6 +71,7 @@
                              0 149 IRQ_TYPE_LEVEL_HIGH
                              0 149 IRQ_TYPE_LEVEL_HIGH
                              0 149 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
        };
        /* irqpin1: IRQ8 - IRQ15 */
@@ -91,6 +92,7 @@
                              0 149 IRQ_TYPE_LEVEL_HIGH
                              0 149 IRQ_TYPE_LEVEL_HIGH
                              0 149 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
        };
        /* irqpin2: IRQ16 - IRQ23 */
@@ -111,6 +113,7 @@
                              0 149 IRQ_TYPE_LEVEL_HIGH
                              0 149 IRQ_TYPE_LEVEL_HIGH
                              0 149 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
        };
        /* irqpin3: IRQ24 - IRQ31 */
@@ -131,6 +134,7 @@
                              0 149 IRQ_TYPE_LEVEL_HIGH
                              0 149 IRQ_TYPE_LEVEL_HIGH
                              0 149 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
        };
        ether: ethernet@e9a00000 {
@@ -193,7 +197,7 @@
                compatible = "renesas,scifa-r8a7740", "renesas,scifa";
                reg = <0xe6c60000 0x100>;
                interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
+                clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
                clock-names = "sci_ick";
                status = "disabled";
        };
@@ -331,6 +335,34 @@
                status = "disabled";
        };
+        tmu0: timer@fff80000 {
+                compatible = "renesas,tmu-r8a7740", "renesas,tmu";
+                reg = <0xfff80000 0x2c>;
+                interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 199 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 200 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
+                clock-names = "fck";
+                #renesas,channels = <3>;
+                status = "disabled";
+        };
+        tmu1: timer@fff90000 {
+                compatible = "renesas,tmu-r8a7740", "renesas,tmu";
+                reg = <0xfff90000 0x2c>;
+                interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 171 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 172 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
+                clock-names = "fck";
+                #renesas,channels = <3>;
+                status = "disabled";
+        };
        clocks {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -448,8 +480,8 @@
                mstp2_clks: mstp2_clks@e6150138 {
                        compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0xe6150138 4>, <0xe6150040 4>;
-                        clocks = <&sub_clk>, <&sub_clk>,
+                        clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
-                                 <&cpg_clocks R8A7740_CLK_HP>,
+                                 <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
                                 <&cpg_clocks R8A7740_CLK_HP>,
                                 <&cpg_clocks R8A7740_CLK_HP>,
                                 <&cpg_clocks R8A7740_CLK_HP>,
@@ -458,7 +490,8 @@
                                 <&sub_clk>;
                        #clock-cells = <1>;
                        renesas,clock-indices = <
-                                R8A7740_CLK_SCIFA6 R8A7740_CLK_SCIFA7
+                                R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA
+                                R8A7740_CLK_SCIFA7
                                R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
                                R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
                                R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
@@ -467,7 +500,8 @@
                                R8A7740_CLK_SCIFA4
                        >;
                        clock-output-names =
-                                "scifa6", "scifa7", "dmac1", "dmac2", "dmac3",
+                                "scifa6", "intca",
+                                "scifa7", "dmac1", "dmac2", "dmac3",
                                "usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
                                "scifa2", "scifa3", "scifa4";
                };
diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
index 3342c74c5de8..04c0c37bb784 100644
--- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
@@ -28,7 +28,8 @@
        };
        chosen {
-                bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
+                bootargs = "ignore_loglevel root=/dev/nfs ip=dhcp rw";
+                stdout-path = &scif0;
        };
        memory {
@@ -73,6 +74,10 @@
        status = "okay";
 };
+&tmu0 {
+        status = "okay";
+};
 &pfc {
        scif0_pins: serial0 {
                renesas,groups = "scif0_data_a", "scif0_ctrl";
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 315ec62cb96b..ef8533910029 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -162,6 +162,42 @@
                status = "disabled";
        };
+        tmu0: timer@ffd80000 {
+                compatible = "renesas,tmu-r8a7778", "renesas,tmu";
+                reg = <0xffd80000 0x30>;
+                interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 33 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 34 IRQ_TYPE_LEVEL_HIGH>;
+                #renesas,channels = <3>;
+                status = "disabled";
+        };
+        tmu1: timer@ffd81000 {
+                compatible = "renesas,tmu-r8a7778", "renesas,tmu";
+                reg = <0xffd81000 0x30>;
+                interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 37 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 38 IRQ_TYPE_LEVEL_HIGH>;
+                #renesas,channels = <3>;
+                status = "disabled";
+        };
+        tmu2: timer@ffd82000 {
+                compatible = "renesas,tmu-r8a7778", "renesas,tmu";
+                reg = <0xffd82000 0x30>;
+                interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 41 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 42 IRQ_TYPE_LEVEL_HIGH>;
+                #renesas,channels = <3>;
+                status = "disabled";
+        };
        scif0: serial@ffe40000 {
                compatible = "renesas,scif-r8a7778", "renesas,scif";
                reg = <0xffe40000 0x100>;
@@ -215,8 +251,6 @@
                compatible = "renesas,sdhi-r8a7778";
                reg = <0xffe4c000 0x100>;
                interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
-                cap-sd-highspeed;
-                cap-sdio-irq;
                status = "disabled";
        };
@@ -224,8 +258,6 @@
                compatible = "renesas,sdhi-r8a7778";
                reg = <0xffe4d000 0x100>;
                interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
-                cap-sd-highspeed;
-                cap-sdio-irq;
                status = "disabled";
        };
@@ -233,8 +265,6 @@
                compatible = "renesas,sdhi-r8a7778";
                reg = <0xffe4f000 0x100>;
                interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
-                cap-sd-highspeed;
-                cap-sdio-irq;
                status = "disabled";
        };
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index c160404e4d40..e83d40e24bcd 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -25,6 +25,7 @@
        chosen {
                bootargs = "console=ttySC2,115200 ignore_loglevel root=/dev/nfs ip=on";
+                stdout-path = &scif2;
        };
        memory {
@@ -68,6 +69,78 @@
                        gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
                };
        };
+        vga-encoder {
+                compatible = "adi,adv7123";
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                vga_enc_in: endpoint {
+                                        remote-endpoint = <&du_out_rgb0>;
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                vga_enc_out: endpoint {
+                                        remote-endpoint = <&vga_in>;
+                                };
+                        };
+                };
+        };
+        vga {
+                compatible = "vga-connector";
+                port {
+                        vga_in: endpoint {
+                                remote-endpoint = <&vga_enc_out>;
+                        };
+                };
+        };
+        lvds-encoder {
+                compatible = "thine,thc63lvdm83d";
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                lvds_enc_in: endpoint {
+                                        remote-endpoint = <&du_out_rgb1>;
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                lvds_connector: endpoint {
+                                };
+                        };
+                };
+        };
+};
+&du {
+        pinctrl-0 = <&du_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+        ports {
+                port@0 {
+                        endpoint {
+                                remote-endpoint = <&vga_enc_in>;
+                        };
+                };
+                port@1 {
+                        endpoint {
+                                remote-endpoint = <&lvds_enc_in>;
+                        };
+                };
+        };
 };
 &irqpin0 {
@@ -83,6 +156,17 @@
 };
 &pfc {
+        du_pins: du {
+                du0 {
+                        renesas,groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0";
+                        renesas,function = "du0";
+                };
+                du1 {
+                        renesas,groups = "du1_rgb666", "du1_sync_1", "du1_clk_out";
+                        renesas,function = "du1";
+                };
+        };
        lan0_pins: lan0 {
                intc {
                        renesas,groups = "intc_irq1_b";
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 7cfba9aa1b41..ede9a29e4bc6 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -303,7 +303,7 @@
        };
        sata: sata@fc600000 {
-                compatible = "renesas,rcar-sata";
+                compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
                reg = <0xfc600000 0x2000>;
                interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp1_clks R8A7779_CLK_SATA>;
@@ -314,8 +314,6 @@
                reg = <0xffe4c000 0x100>;
                interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
-                cap-sd-highspeed;
-                cap-sdio-irq;
                status = "disabled";
        };
@@ -324,8 +322,6 @@
                reg = <0xffe4d000 0x100>;
                interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
-                cap-sd-highspeed;
-                cap-sdio-irq;
                status = "disabled";
        };
@@ -334,8 +330,6 @@
                reg = <0xffe4e000 0x100>;
                interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
-                cap-sd-highspeed;
-                cap-sdio-irq;
                status = "disabled";
        };
@@ -344,8 +338,6 @@
                reg = <0xffe4f000 0x100>;
                interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
-                cap-sd-highspeed;
-                cap-sdio-irq;
                status = "disabled";
        };
@@ -379,6 +371,30 @@
                status = "disabled";
        };
+        du: display@fff80000 {
+                compatible = "renesas,du-r8a7779";
+                reg = <0 0xfff80000 0 0x40000>;
+                interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp1_clks R8A7779_CLK_DU>;
+                status = "disabled";
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                du_out_rgb0: endpoint {
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                du_out_rgb1: endpoint {
+                                };
+                        };
+                };
+        };
        clocks {
                #address-cells = <1>;
                #size-cells = <1>;
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 69098b906b39..636d53bb87a2 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -9,6 +9,34 @@
 * kind, whether express or implied.
 */
+/*
+ * SSI-AK4643
+ *
+ * SW1: 1: AK4643
+ *      2: CN22
+ *      3: ADV7511
+ *
+ * This command is required when Playback/Capture
+ *
+ *      amixer set "LINEOUT Mixer DACL" on
+ *      amixer set "DVC Out" 100%
+ *      amixer set "DVC In" 100%
+ *
+ * You can use Mute
+ *
+ *      amixer set "DVC Out Mute" on
+ *      amixer set "DVC In Mute" on
+ *
+ * You can use Volume Ramp
+ *
+ *      amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"
+ *      amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
+ *      amixer set "DVC Out Ramp" on
+ *      aplay xxx.wav &
+ *      amixer set "DVC Out"  80%  // Volume Down
+ *      amixer set "DVC Out" 100%  // Volume Up
+ */
 /dts-v1/;
 #include "r8a7790.dtsi"
 #include <dt-bindings/gpio/gpio.h>
@@ -19,12 +47,13 @@
        compatible = "renesas,lager", "renesas,r8a7790";
        aliases {
-                serial6 = &scif0;
+                serial6 = &scifa0;
-                serial7 = &scif1;
+                serial7 = &scifa1;
        };
        chosen {
                bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
+                stdout-path = &scifa0;
        };
        memory@40000000 {
@@ -42,7 +71,7 @@
                #size-cells = <1>;
        };
-        gpio_keys {
+        keyboard {
                compatible = "gpio-keys";
                button@1 {
@@ -144,6 +173,73 @@
                states = <3300000 1
                          1800000 0>;
        };
+        sound {
+                compatible = "simple-audio-card";
+                simple-audio-card,format = "left_j";
+                simple-audio-card,bitclock-master = <&sndcodec>;
+                simple-audio-card,frame-master = <&sndcodec>;
+                sndcpu: simple-audio-card,cpu {
+                        sound-dai = <&rcar_sound>;
+                };
+                sndcodec: simple-audio-card,codec {
+                        sound-dai = <&ak4643>;
+                        system-clock-frequency = <11289600>;
+                };
+        };
+        vga-encoder {
+                compatible = "adi,adv7123";
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                adv7123_in: endpoint {
+                                        remote-endpoint = <&du_out_rgb>;
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                adv7123_out: endpoint {
+                                        remote-endpoint = <&vga_in>;
+                                };
+                        };
+                };
+        };
+        vga {
+                compatible = "vga-connector";
+                port {
+                        vga_in: endpoint {
+                                remote-endpoint = <&adv7123_out>;
+                        };
+                };
+        };
+};
+&du {
+        pinctrl-0 = <&du_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+        ports {
+                port@0 {
+                        endpoint {
+                                remote-endpoint = <&adv7123_in>;
+                        };
+                };
+                port@2 {
+                        lvds_connector: endpoint {
+                        };
+                };
+        };
 };
 &extal_clk {
@@ -151,17 +247,14 @@
 };
 &pfc {
-        pinctrl-0 = <&du_pins>;
-        pinctrl-names = "default";
        du_pins: du {
                renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
                renesas,function = "du";
        };
-        scif0_pins: serial0 {
+        scifa0_pins: serial0 {
-                renesas,groups = "scif0_data";
+                renesas,groups = "scifa0_data";
-                renesas,function = "scif0";
+                renesas,function = "scifa0";
        };
        ether_pins: ether {
@@ -174,9 +267,9 @@
                renesas,function = "intc";
        };
-        scif1_pins: serial1 {
+        scifa1_pins: serial1 {
-                renesas,groups = "scif1_data";
+                renesas,groups = "scifa1_data";
-                renesas,function = "scif1";
+                renesas,function = "scifa1";
        };
        sdhi0_pins: sd0 {
@@ -220,6 +313,11 @@
                renesas,function = "iic3";
        };
+        hsusb_pins: hsusb {
+                renesas,groups = "usb0_ovc_vbus";
+                renesas,function = "usb0";
+        };
        usb0_pins: usb0 {
                renesas,groups = "usb0";
                renesas,function = "usb0";
@@ -239,6 +337,16 @@
                renesas,groups = "vin1_data8", "vin1_clk";
                renesas,function = "vin1";
        };
+        sound_pins: sound {
+                renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
+                renesas,function = "ssi";
+        };
+        sound_clk_pins: sound_clk {
+                renesas,groups = "audio_clk_a";
+                renesas,function = "audio_clk";
+        };
 };
 &ether {
@@ -308,15 +416,15 @@
        };
 };
-&scif0 {
+&scifa0 {
-        pinctrl-0 = <&scif0_pins>;
+        pinctrl-0 = <&scifa0_pins>;
        pinctrl-names = "default";
        status = "okay";
 };
-&scif1 {
+&scifa1 {
-        pinctrl-0 = <&scif1_pins>;
+        pinctrl-0 = <&scifa1_pins>;
        pinctrl-names = "default";
        status = "okay";
@@ -376,6 +484,14 @@
        pinctrl-0 = <&iic2_pins>;
        pinctrl-names = "default";
+        clock-frequency = <100000>;
+        ak4643: sound-codec@12 {
+                compatible = "asahi-kasei,ak4643";
+                #sound-dai-cells = <0>;
+                reg = <0x12>;
+        };
        composite-in@20 {
                compatible = "adi,adv7180";
                reg = <0x20>;
@@ -418,12 +534,29 @@
        pinctrl-names = "default";
 };
+&xhci {
+        status = "okay";
+        pinctrl-0 = <&usb2_pins>;
+        pinctrl-names = "default";
+};
 &pci2 {
        status = "okay";
        pinctrl-0 = <&usb2_pins>;
        pinctrl-names = "default";
 };
+&hsusb {
+        status = "okay";
+        pinctrl-0 = <&hsusb_pins>;
+        pinctrl-names = "default";
+        renesas,enable-gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+};
+&usbphy {
+        status = "okay";
+};
 /* composite video input */
 &vin1 {
        pinctrl-0 = <&vin1_pins>;
@@ -441,3 +574,23 @@
                };
        };
 };
+&rcar_sound {
+        pinctrl-0 = <&sound_pins &sound_clk_pins>;
+        pinctrl-names = "default";
+        #sound-dai-cells = <0>;
+        status = "okay";
+        rcar_sound,dai {
+                dai0 {
+                        playback = <&ssi0 &src2 &dvc0>;
+                        capture  = <&ssi1 &src3 &dvc1>;
+                };
+        };
+};
+&ssi1 {
+        shared-pin;
+};
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index e20affe156c1..af7e255f629e 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -312,6 +312,70 @@
                #dma-cells = <1>;
                dma-channels = <15>;
        };
+        audma0: dma-controller@ec700000 {
+                compatible = "renesas,rcar-dmac";
+                reg = <0 0xec700000 0 0x10000>;
+                interrupts =    <0 346 IRQ_TYPE_LEVEL_HIGH
+                                 0 320 IRQ_TYPE_LEVEL_HIGH
+                                 0 321 IRQ_TYPE_LEVEL_HIGH
+                                 0 322 IRQ_TYPE_LEVEL_HIGH
+                                 0 323 IRQ_TYPE_LEVEL_HIGH
+                                 0 324 IRQ_TYPE_LEVEL_HIGH
+                                 0 325 IRQ_TYPE_LEVEL_HIGH
+                                 0 326 IRQ_TYPE_LEVEL_HIGH
+                                 0 327 IRQ_TYPE_LEVEL_HIGH
+                                 0 328 IRQ_TYPE_LEVEL_HIGH
+                                 0 329 IRQ_TYPE_LEVEL_HIGH
+                                 0 330 IRQ_TYPE_LEVEL_HIGH
+                                 0 331 IRQ_TYPE_LEVEL_HIGH
+                                 0 332 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error",
+                                "ch0", "ch1", "ch2", "ch3",
+                                "ch4", "ch5", "ch6", "ch7",
+                                "ch8", "ch9", "ch10", "ch11",
+                                "ch12";
+                clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
+                clock-names = "fck";
+                #dma-cells = <1>;
+                dma-channels = <13>;
+        };
+        audma1: dma-controller@ec720000 {
+                compatible = "renesas,rcar-dmac";
+                reg = <0 0xec720000 0 0x10000>;
+                interrupts =    <0 347 IRQ_TYPE_LEVEL_HIGH
+                                 0 333 IRQ_TYPE_LEVEL_HIGH
+                                 0 334 IRQ_TYPE_LEVEL_HIGH
+                                 0 335 IRQ_TYPE_LEVEL_HIGH
+                                 0 336 IRQ_TYPE_LEVEL_HIGH
+                                 0 337 IRQ_TYPE_LEVEL_HIGH
+                                 0 338 IRQ_TYPE_LEVEL_HIGH
+                                 0 339 IRQ_TYPE_LEVEL_HIGH
+                                 0 340 IRQ_TYPE_LEVEL_HIGH
+                                 0 341 IRQ_TYPE_LEVEL_HIGH
+                                 0 342 IRQ_TYPE_LEVEL_HIGH
+                                 0 343 IRQ_TYPE_LEVEL_HIGH
+                                 0 344 IRQ_TYPE_LEVEL_HIGH
+                                 0 345 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error",
+                                "ch0", "ch1", "ch2", "ch3",
+                                "ch4", "ch5", "ch6", "ch7",
+                                "ch8", "ch9", "ch10", "ch11",
+                                "ch12";
+                clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
+                clock-names = "fck";
+                #dma-cells = <1>;
+                dma-channels = <13>;
+        };
+        audmapp: dma-controller@ec740000 {
+                compatible = "renesas,rcar-audmapp";
+                #dma-cells = <1>;
+                reg = <0 0xec740000 0 0x200>;
+        };
        i2c0: i2c@e6508000 {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -359,6 +423,8 @@
                reg = <0 0xe6500000 0 0x425>;
                interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
+                dmas = <&dmac0 0x61>, <&dmac0 0x62>;
+                dma-names = "tx", "rx";
                status = "disabled";
        };
@@ -369,6 +435,8 @@
                reg = <0 0xe6510000 0 0x425>;
                interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
+                dmas = <&dmac0 0x65>, <&dmac0 0x66>;
+                dma-names = "tx", "rx";
                status = "disabled";
        };
@@ -379,6 +447,8 @@
                reg = <0 0xe6520000 0 0x425>;
                interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
+                dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
+                dma-names = "tx", "rx";
                status = "disabled";
        };
@@ -389,14 +459,18 @@
                reg = <0 0xe60b0000 0 0x425>;
                interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
+                dmas = <&dmac0 0x77>, <&dmac0 0x78>;
+                dma-names = "tx", "rx";
                status = "disabled";
        };
-        mmcif0: mmcif@ee200000 {
+        mmcif0: mmc@ee200000 {
                compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
                reg = <0 0xee200000 0 0x80>;
                interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
+                dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
+                dma-names = "tx", "rx";
                reg-io-width = <4>;
                status = "disabled";
        };
@@ -406,6 +480,8 @@
                reg = <0 0xee220000 0 0x80>;
                interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
+                dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
+                dma-names = "tx", "rx";
                reg-io-width = <4>;
                status = "disabled";
        };
@@ -420,7 +496,6 @@
                reg = <0 0xee100000 0 0x200>;
                interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
-                cap-sd-highspeed;
                status = "disabled";
        };
@@ -429,7 +504,6 @@
                reg = <0 0xee120000 0 0x200>;
                interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
-                cap-sd-highspeed;
                status = "disabled";
        };
@@ -438,7 +512,6 @@
                reg = <0 0xee140000 0 0x100>;
                interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
-                cap-sd-highspeed;
                status = "disabled";
        };
@@ -447,7 +520,6 @@
                reg = <0 0xee160000 0 0x100>;
                interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
-                cap-sd-highspeed;
                status = "disabled";
        };
@@ -568,6 +640,36 @@
                status = "disabled";
        };
+        hsusb: usb@e6590000 {
+                compatible = "renesas,usbhs-r8a7790";
+                reg = <0 0xe6590000 0 0x100>;
+                interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
+                renesas,buswait = <4>;
+                phys = <&usb0 1>;
+                phy-names = "usb";
+                status = "disabled";
+        };
+        usbphy: usb-phy@e6590100 {
+                compatible = "renesas,usb-phy-r8a7790";
+                reg = <0 0xe6590100 0 0x100>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
+                clock-names = "usbhs";
+                status = "disabled";
+                usb0: usb-channel@0 {
+                        reg = <0>;
+                        #phy-cells = <1>;
+                };
+                usb2: usb-channel@2 {
+                        reg = <2>;
+                        #phy-cells = <1>;
+                };
+        };
        vin0: video@e6ef0000 {
                compatible = "renesas,vin-r8a7790";
                clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
@@ -600,6 +702,96 @@
                status = "disabled";
        };
+        vsp1@fe920000 {
+                compatible = "renesas,vsp1";
+                reg = <0 0xfe920000 0 0x8000>;
+                interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
+                renesas,has-sru;
+                renesas,#rpf = <5>;
+                renesas,#uds = <1>;
+                renesas,#wpf = <4>;
+        };
+        vsp1@fe928000 {
+                compatible = "renesas,vsp1";
+                reg = <0 0xfe928000 0 0x8000>;
+                interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
+                renesas,has-lut;
+                renesas,has-sru;
+                renesas,#rpf = <5>;
+                renesas,#uds = <3>;
+                renesas,#wpf = <4>;
+        };
+        vsp1@fe930000 {
+                compatible = "renesas,vsp1";
+                reg = <0 0xfe930000 0 0x8000>;
+                interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
+                renesas,has-lif;
+                renesas,has-lut;
+                renesas,#rpf = <4>;
+                renesas,#uds = <1>;
+                renesas,#wpf = <4>;
+        };
+        vsp1@fe938000 {
+                compatible = "renesas,vsp1";
+                reg = <0 0xfe938000 0 0x8000>;
+                interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
+                renesas,has-lif;
+                renesas,has-lut;
+                renesas,#rpf = <4>;
+                renesas,#uds = <1>;
+                renesas,#wpf = <4>;
+        };
+        du: display@feb00000 {
+                compatible = "renesas,du-r8a7790";
+                reg = <0 0xfeb00000 0 0x70000>,
+                      <0 0xfeb90000 0 0x1c>,
+                      <0 0xfeb94000 0 0x1c>;
+                reg-names = "du", "lvds.0", "lvds.1";
+                interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 268 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 269 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7790_CLK_DU0>,
+                         <&mstp7_clks R8A7790_CLK_DU1>,
+                         <&mstp7_clks R8A7790_CLK_DU2>,
+                         <&mstp7_clks R8A7790_CLK_LVDS0>,
+                         <&mstp7_clks R8A7790_CLK_LVDS1>;
+                clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
+                status = "disabled";
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                du_out_rgb: endpoint {
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                du_out_lvds0: endpoint {
+                                };
+                        };
+                        port@2 {
+                                reg = <2>;
+                                du_out_lvds1: endpoint {
+                                };
+                        };
+                };
+        };
        clocks {
                #address-cells = <2>;
                #size-cells = <2>;
@@ -868,18 +1060,25 @@
                mstp1_clks: mstp1_clks@e6150134 {
                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
-                        clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
+                        clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
-                                 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
+                                 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
-                                 <&zs_clk>;
+                                 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
+                                 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
                        #clock-cells = <1>;
                        renesas,clock-indices = <
-                                R8A7790_CLK_JPU R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
+                                R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
-                                R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
+                                R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
-                                R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
+                                R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
+                                R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
+                                R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
+                                R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
+                                R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
                        >;
                        clock-output-names =
-                                "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
+                                "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
-                                "vsp1-du0", "vsp1-rt", "vsp1-sy";
+                                "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
+                                "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
+                                "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
                };
                mstp2_clks: mstp2_clks@e6150138 {
                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -904,25 +1103,29 @@
                        reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
                        clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
                                 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
-                                 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
+                                 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
+                                 <&hp_clk>, <&hp_clk>;
                        #clock-cells = <1>;
                        renesas,clock-indices = <
                                R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
                                R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
                                R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
+                                R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
                        >;
                        clock-output-names =
                                "iic2", "tpu0", "mmcif1", "sdhi3",
                                "sdhi2", "sdhi1", "sdhi0", "mmcif0",
-                                "iic0", "pciec", "iic1", "ssusb", "cmt1";
+                                "iic0", "pciec", "iic1", "ssusb", "cmt1",
+                                "usbdmac0", "usbdmac1";
                };
                mstp5_clks: mstp5_clks@e6150144 {
                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
-                        clocks = <&extal_clk>, <&p_clk>;
+                        clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
                        #clock-cells = <1>;
-                        renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
+                        renesas,clock-indices = <R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
-                        clock-output-names = "thermal", "pwm";
+                                                 R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
+                        clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
                };
                mstp7_clks: mstp7_clks@e615014c {
                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1070,6 +1273,16 @@
                status = "disabled";
        };
+        xhci: usb@ee000000 {
+                compatible = "renesas,xhci-r8a7790";
+                reg = <0 0xee000000 0 0xc00>;
+                interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
+                phys = <&usb2 1>;
+                phy-names = "usb";
+                status = "disabled";
+        };
        pci0: pci@ee090000 {
                compatible = "renesas,pci-r8a7790";
                device_type = "pci";
@@ -1088,6 +1301,20 @@
                interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
                                 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
                                 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
+                usb@0,1 {
+                        reg = <0x800 0 0 0 0>;
+                        device_type = "pci";
+                        phys = <&usb0 0>;
+                        phy-names = "usb";
+                };
+                usb@0,2 {
+                        reg = <0x1000 0 0 0 0>;
+                        device_type = "pci";
+                        phys = <&usb0 0>;
+                        phy-names = "usb";
+                };
        };
        pci1: pci@ee0b0000 {
@@ -1128,6 +1355,20 @@
                interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
                                 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
                                 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
+                usb@0,1 {
+                        reg = <0x800 0 0 0 0>;
+                        device_type = "pci";
+                        phys = <&usb2 0>;
+                        phy-names = "usb";
+                };
+                usb@0,2 {
+                        reg = <0x1000 0 0 0 0>;
+                        device_type = "pci";
+                        phys = <&usb2 0>;
+                        phy-names = "usb";
+                };
        };
        pciec: pcie@fe000000 {
@@ -1155,7 +1396,7 @@
                status = "disabled";
        };
-        rcar_sound: rcar_sound@0xec500000 {
+        rcar_sound: rcar_sound@ec500000 {
                #sound-dai-cells = <1>;
                compatible =  "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
                reg =   <0 0xec500000 0 0x1000>, /* SCU */
diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts
index f1b56de10205..740e38678032 100644
--- a/arch/arm/boot/dts/r8a7791-henninger.dts
+++ b/arch/arm/boot/dts/r8a7791-henninger.dts
@@ -23,6 +23,7 @@
        chosen {
                bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp";
+                stdout-path = &scif0;
        };
        memory@40000000 {
@@ -271,6 +272,17 @@
        pinctrl-names = "default";
 };
+&hsusb {
+        status = "okay";
+        pinctrl-0 = <&usb0_pins>;
+        pinctrl-names = "default";
+        renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>;
+};
+&usbphy {
+        status = "okay";
+};
 &pcie_bus_clk {
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 07550e775e80..990af167c551 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -10,6 +10,34 @@
 * kind, whether express or implied.
 */
+/*
+ * SSI-AK4643
+ *
+ * SW1: 1: AK4643
+ *      2: CN22
+ *      3: ADV7511
+ *
+ * This command is required when Playback/Capture
+ *
+ *      amixer set "LINEOUT Mixer DACL" on
+ *      amixer set "DVC Out" 100%
+ *      amixer set "DVC In" 100%
+ *
+ * You can use Mute
+ *
+ *      amixer set "DVC Out Mute" on
+ *      amixer set "DVC In Mute" on
+ *
+ * You can use Volume Ramp
+ *
+ *      amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"
+ *      amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
+ *      amixer set "DVC Out Ramp" on
+ *      aplay xxx.wav &
+ *      amixer set "DVC Out"  80%  // Volume Down
+ *      amixer set "DVC Out" 100%  // Volume Up
+ */
 /dts-v1/;
 #include "r8a7791.dtsi"
 #include <dt-bindings/gpio/gpio.h>
@@ -25,7 +53,8 @@
        };
        chosen {
-                bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
+                bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+                stdout-path = &scif0;
        };
        memory@40000000 {
@@ -43,7 +72,7 @@
                #size-cells = <1>;
        };
-        gpio-keys {
+        keyboard {
                compatible = "gpio-keys";
                key-1 {
@@ -129,12 +158,15 @@
                compatible = "gpio-leds";
                led6 {
                        gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+                        label = "LED6";
                };
                led7 {
                        gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+                        label = "LED7";
                };
                led8 {
                        gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+                        label = "LED8";
                };
        };
@@ -209,6 +241,36 @@
                states = <3300000 1
                          1800000 0>;
        };
+        sound {
+                compatible = "simple-audio-card";
+                simple-audio-card,format = "left_j";
+                simple-audio-card,bitclock-master = <&sndcodec>;
+                simple-audio-card,frame-master = <&sndcodec>;
+                sndcpu: simple-audio-card,cpu {
+                        sound-dai = <&rcar_sound>;
+                };
+                sndcodec: simple-audio-card,codec {
+                        sound-dai = <&ak4643>;
+                        system-clock-frequency = <11289600>;
+                };
+        };
+};
+&du {
+        pinctrl-0 = <&du_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+        ports {
+                port@1 {
+                        lvds_connector: endpoint {
+                        };
+                };
+        };
 };
 &extal_clk {
@@ -216,9 +278,6 @@
 };
 &pfc {
-        pinctrl-0 = <&du_pins>;
-        pinctrl-names = "default";
        i2c2_pins: i2c2 {
                renesas,groups = "i2c2";
                renesas,function = "i2c2";
@@ -289,6 +348,16 @@
                renesas,groups = "vin1_data8", "vin1_clk";
                renesas,function = "vin1";
        };
+        sound_pins: sound {
+                renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
+                renesas,function = "ssi";
+        };
+        sound_clk_pins: sound_clk {
+                renesas,groups = "audio_clk_a";
+                renesas,function = "audio_clk";
+        };
 };
 &ether {
@@ -414,7 +483,13 @@
        pinctrl-names = "default";
        status = "okay";
-        clock-frequency = <400000>;
+        clock-frequency = <100000>;
+        ak4643: sound-codec@12 {
+                compatible = "asahi-kasei,ak4643";
+                #sound-dai-cells = <0>;
+                reg = <0x12>;
+        };
        composite-in@20 {
                compatible = "adi,adv7180";
@@ -463,6 +538,17 @@
        pinctrl-names = "default";
 };
+&hsusb {
+        status = "okay";
+        pinctrl-0 = <&usb0_pins>;
+        pinctrl-names = "default";
+        renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>;
+};
+&usbphy {
+        status = "okay";
+};
 &pcie_bus_clk {
        status = "okay";
 };
@@ -491,3 +577,23 @@
                };
        };
 };
+&rcar_sound {
+        pinctrl-0 = <&sound_pins &sound_clk_pins>;
+        pinctrl-names = "default";
+        #sound-dai-cells = <0>;
+        status = "okay";
+        rcar_sound,dai {
+                dai0 {
+                        playback = <&ssi0 &src2 &dvc0>;
+                        capture  = <&ssi1 &src3 &dvc1>;
+                };
+        };
+};
+&ssi1 {
+        shared-pin;
+};
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index e06c11fa8698..77c0beeb8d7c 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1,7 +1,7 @@
 /*
 * Device Tree Source for the r8a7791 SoC
 *
- * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013-2014 Renesas Electronics Corporation
 * Copyright (C) 2013-2014 Renesas Solutions Corp.
 * Copyright (C) 2014 Cogent Embedded Inc.
 *
@@ -301,6 +301,69 @@
                dma-channels = <15>;
        };
+        audma0: dma-controller@ec700000 {
+                compatible = "renesas,rcar-dmac";
+                reg = <0 0xec700000 0 0x10000>;
+                interrupts =    <0 346 IRQ_TYPE_LEVEL_HIGH
+                                 0 320 IRQ_TYPE_LEVEL_HIGH
+                                 0 321 IRQ_TYPE_LEVEL_HIGH
+                                 0 322 IRQ_TYPE_LEVEL_HIGH
+                                 0 323 IRQ_TYPE_LEVEL_HIGH
+                                 0 324 IRQ_TYPE_LEVEL_HIGH
+                                 0 325 IRQ_TYPE_LEVEL_HIGH
+                                 0 326 IRQ_TYPE_LEVEL_HIGH
+                                 0 327 IRQ_TYPE_LEVEL_HIGH
+                                 0 328 IRQ_TYPE_LEVEL_HIGH
+                                 0 329 IRQ_TYPE_LEVEL_HIGH
+                                 0 330 IRQ_TYPE_LEVEL_HIGH
+                                 0 331 IRQ_TYPE_LEVEL_HIGH
+                                 0 332 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error",
+                                "ch0", "ch1", "ch2", "ch3",
+                                "ch4", "ch5", "ch6", "ch7",
+                                "ch8", "ch9", "ch10", "ch11",
+                                "ch12";
+                clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
+                clock-names = "fck";
+                #dma-cells = <1>;
+                dma-channels = <13>;
+        };
+        audma1: dma-controller@ec720000 {
+                compatible = "renesas,rcar-dmac";
+                reg = <0 0xec720000 0 0x10000>;
+                interrupts =    <0 347 IRQ_TYPE_LEVEL_HIGH
+                                 0 333 IRQ_TYPE_LEVEL_HIGH
+                                 0 334 IRQ_TYPE_LEVEL_HIGH
+                                 0 335 IRQ_TYPE_LEVEL_HIGH
+                                 0 336 IRQ_TYPE_LEVEL_HIGH
+                                 0 337 IRQ_TYPE_LEVEL_HIGH
+                                 0 338 IRQ_TYPE_LEVEL_HIGH
+                                 0 339 IRQ_TYPE_LEVEL_HIGH
+                                 0 340 IRQ_TYPE_LEVEL_HIGH
+                                 0 341 IRQ_TYPE_LEVEL_HIGH
+                                 0 342 IRQ_TYPE_LEVEL_HIGH
+                                 0 343 IRQ_TYPE_LEVEL_HIGH
+                                 0 344 IRQ_TYPE_LEVEL_HIGH
+                                 0 345 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error",
+                                "ch0", "ch1", "ch2", "ch3",
+                                "ch4", "ch5", "ch6", "ch7",
+                                "ch8", "ch9", "ch10", "ch11",
+                                "ch12";
+                clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
+                clock-names = "fck";
+                #dma-cells = <1>;
+                dma-channels = <13>;
+        };
+        audmapp: dma-controller@ec740000 {
+                compatible = "renesas,rcar-audmapp";
+                #dma-cells = <1>;
+                reg = <0 0xec740000 0 0x200>;
+        };
        /* The memory map in the User's Manual maps the cores to bus numbers */
        i2c0: i2c@e6508000 {
                #address-cells = <1>;
@@ -371,6 +434,8 @@
                reg = <0 0xe60b0000 0 0x425>;
                interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
+                dmas = <&dmac0 0x77>, <&dmac0 0x78>;
+                dma-names = "tx", "rx";
                status = "disabled";
        };
@@ -381,6 +446,8 @@
                reg = <0 0xe6500000 0 0x425>;
                interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
+                dmas = <&dmac0 0x61>, <&dmac0 0x62>;
+                dma-names = "tx", "rx";
                status = "disabled";
        };
@@ -391,6 +458,8 @@
                reg = <0 0xe6510000 0 0x425>;
                interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
+                dmas = <&dmac0 0x65>, <&dmac0 0x66>;
+                dma-names = "tx", "rx";
                status = "disabled";
        };
@@ -400,6 +469,17 @@
                #gpio-range-cells = <3>;
        };
+        mmcif0: mmc@ee200000 {
+                compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
+                reg = <0 0xee200000 0 0x80>;
+                interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
+                dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
+                dma-names = "tx", "rx";
+                reg-io-width = <4>;
+                status = "disabled";
+        };
        sdhi0: sd@ee100000 {
                compatible = "renesas,sdhi-r8a7791";
                reg = <0 0xee100000 0 0x200>;
@@ -613,6 +693,36 @@
                status = "disabled";
        };
+        hsusb: usb@e6590000 {
+                compatible = "renesas,usbhs-r8a7791";
+                reg = <0 0xe6590000 0 0x100>;
+                interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
+                renesas,buswait = <4>;
+                phys = <&usb0 1>;
+                phy-names = "usb";
+                status = "disabled";
+        };
+        usbphy: usb-phy@e6590100 {
+                compatible = "renesas,usb-phy-r8a7791";
+                reg = <0 0xe6590100 0 0x100>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
+                clock-names = "usbhs";
+                status = "disabled";
+                usb0: usb-channel@0 {
+                        reg = <0>;
+                        #phy-cells = <1>;
+                };
+                usb2: usb-channel@2 {
+                        reg = <2>;
+                        #phy-cells = <1>;
+                };
+        };
        vin0: video@e6ef0000 {
                compatible = "renesas,vin-r8a7791";
                clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
@@ -637,6 +747,75 @@
                status = "disabled";
        };
+        vsp1@fe928000 {
+                compatible = "renesas,vsp1";
+                reg = <0 0xfe928000 0 0x8000>;
+                interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
+                renesas,has-lut;
+                renesas,has-sru;
+                renesas,#rpf = <5>;
+                renesas,#uds = <3>;
+                renesas,#wpf = <4>;
+        };
+        vsp1@fe930000 {
+                compatible = "renesas,vsp1";
+                reg = <0 0xfe930000 0 0x8000>;
+                interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
+                renesas,has-lif;
+                renesas,has-lut;
+                renesas,#rpf = <4>;
+                renesas,#uds = <1>;
+                renesas,#wpf = <4>;
+        };
+        vsp1@fe938000 {
+                compatible = "renesas,vsp1";
+                reg = <0 0xfe938000 0 0x8000>;
+                interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
+                renesas,has-lif;
+                renesas,has-lut;
+                renesas,#rpf = <4>;
+                renesas,#uds = <1>;
+                renesas,#wpf = <4>;
+        };
+        du: display@feb00000 {
+                compatible = "renesas,du-r8a7791";
+                reg = <0 0xfeb00000 0 0x40000>,
+                      <0 0xfeb90000 0 0x1c>;
+                reg-names = "du", "lvds.0";
+                interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 268 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7791_CLK_DU0>,
+                         <&mstp7_clks R8A7791_CLK_DU1>,
+                         <&mstp7_clks R8A7791_CLK_LVDS0>;
+                clock-names = "du.0", "du.1", "lvds.0";
+                status = "disabled";
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                du_out_rgb: endpoint {
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                du_out_lvds0: endpoint {
+                                };
+                        };
+                };
+        };
        clocks {
                #address-cells = <2>;
                #size-cells = <2>;
@@ -889,17 +1068,23 @@
                mstp1_clks: mstp1_clks@e6150134 {
                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
-                        clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
+                        clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
-                                 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
+                                 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
+                                 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
+                                 <&zs_clk>;
                        #clock-cells = <1>;
                        renesas,clock-indices = <
-                                R8A7791_CLK_JPU R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
+                                R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
-                                R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
+                                R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
-                                R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
+                                R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
+                                R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
+                                R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
+                                R8A7791_CLK_VSP1_S
                        >;
                        clock-output-names =
-                                "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
+                                "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
-                                "vsp1-du0", "vsp1-sy";
+                                "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
+                                "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
                };
                mstp2_clks: mstp2_clks@e6150138 {
                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -923,24 +1108,28 @@
                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
                        clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
-                                 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
+                                 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
+                                 <&hp_clk>, <&hp_clk>;
                        #clock-cells = <1>;
                        renesas,clock-indices = <
                                R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
                                R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
                                R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
+                                R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1
                        >;
                        clock-output-names =
                                "tpu0", "sdhi2", "sdhi1", "sdhi0",
-                                "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1";
+                                "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
+                                "usbdmac0", "usbdmac1";
                };
                mstp5_clks: mstp5_clks@e6150144 {
                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
-                        clocks = <&extal_clk>, <&p_clk>;
+                        clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
                        #clock-cells = <1>;
-                        renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
+                        renesas,clock-indices = <R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
-                        clock-output-names = "thermal", "pwm";
+                                                 R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
+                        clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
                };
                mstp7_clks: mstp7_clks@e615014c {
                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1088,6 +1277,16 @@
                status = "disabled";
        };
+        xhci: usb@ee000000 {
+                compatible = "renesas,xhci-r8a7791";
+                reg = <0 0xee000000 0 0xc00>;
+                interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
+                phys = <&usb2 1>;
+                phy-names = "usb";
+                status = "disabled";
+        };
        pci0: pci@ee090000 {
                compatible = "renesas,pci-r8a7791";
                device_type = "pci";
@@ -1106,6 +1305,20 @@
                interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
                                 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
                                 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
+                usb@0,1 {
+                        reg = <0x800 0 0 0 0>;
+                        device_type = "pci";
+                        phys = <&usb0 0>;
+                        phy-names = "usb";
+                };
+                usb@0,2 {
+                        reg = <0x1000 0 0 0 0>;
+                        device_type = "pci";
+                        phys = <&usb0 0>;
+                        phy-names = "usb";
+                };
        };
        pci1: pci@ee0d0000 {
@@ -1126,6 +1339,20 @@
                interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
                                 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
                                 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
+                usb@0,1 {
+                        reg = <0x800 0 0 0 0>;
+                        device_type = "pci";
+                        phys = <&usb2 0>;
+                        phy-names = "usb";
+                };
+                usb@0,2 {
+                        reg = <0x1000 0 0 0 0>;
+                        device_type = "pci";
+                        phys = <&usb2 0>;
+                        phy-names = "usb";
+                };
        };
        pciec: pcie@fe000000 {
@@ -1153,7 +1380,7 @@
                status = "disabled";
        };
-        rcar_sound: rcar_sound@0xec500000 {
+        rcar_sound: rcar_sound@ec500000 {
                #sound-dai-cells = <1>;
                compatible =  "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
                reg =   <0 0xec500000 0 0x1000>, /* SCU */
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 79d06ef017a0..f2cf7576bf3f 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -20,7 +20,8 @@
        };
        chosen {
-                bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp";
+                bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+                stdout-path = &scif2;
        };
        memory@40000000 {
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index d4e8bce1e0b7..19c9de3f2a5a 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -82,6 +82,14 @@
                status = "disabled";
        };
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+        };
        irqc0: interrupt-controller@e61c0000 {
                compatible = "renesas,irqc-r8a7794", "renesas,irqc";
                #interrupt-cells = <2>;
@@ -453,16 +461,19 @@
                mstp1_clks: mstp1_clks@e6150134 {
                        compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
-                        clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
+                        clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
-                                 <&cp_clk>,
+                                 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
-                                 <&zs_clk>, <&zs_clk>, <&zs_clk>;
+                                 <&zs_clk>, <&zs_clk>;
                        #clock-cells = <1>;
                        renesas,clock-indices = <
-                                R8A7794_CLK_TMU1 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2
+                                R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
-                                R8A7794_CLK_CMT0 R8A7794_CLK_TMU0
+                                R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
+                                R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
+                                R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
                        >;
                        clock-output-names =
-                                "tmu1", "tmu3", "tmu2", "cmt0", "tmu0";
+                                "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
+                                "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
                };
                mstp2_clks: mstp2_clks@e6150138 {
                        compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -509,13 +520,13 @@
                mstp8_clks: mstp8_clks@e6150990 {
                        compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
-                        clocks = <&p_clk>;
+                        clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
                        #clock-cells = <1>;
                        renesas,clock-indices = <
-                                R8A7794_CLK_ETHER
+                                R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
                        >;
                        clock-output-names =
-                                "ether";
+                                "vin1", "vin0", "ether";
                };
                mstp11_clks: mstp11_clks@e615099c {
                        compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
diff --git a/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi b/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi
new file mode 100644
index 000000000000..65cb50f0c29f
--- /dev/null
+++ b/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Common file for the AA104XD12 panel connected to Renesas R-Car boards
+ *
+ * Copyright (C) 2014 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+/ {
+        panel {
+                compatible = "mitsubishi,aa104xd12", "panel-dpi";
+                width-mm = <210>;
+                height-mm = <158>;
+                panel-timing {
+                        /* 1024x768 @65Hz */
+                        clock-frequency = <65000000>;
+                        hactive = <1024>;
+                        vactive = <768>;
+                        hsync-len = <136>;
+                        hfront-porch = <20>;
+                        hback-porch = <160>;
+                        vfront-porch = <3>;
+                        vback-porch = <29>;
+                        vsync-len = <6>;
+                };
+                port {
+                        panel_in: endpoint {
+                                remote-endpoint = <&lvds_connector>;
+                        };
+                };
+        };
+};
+&lvds_connector {
+        remote-endpoint = <&panel_in>;
+};
diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index d5344510c676..baf21ac6ce7f 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -60,6 +60,10 @@
        };
 };
+&cpu0 {
+        cpu0-supply = <&vdd_arm>;
+};
 &i2c1 {
        status = "okay";
        clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts
new file mode 100644
index 000000000000..0a7304beb417
--- /dev/null
+++ b/arch/arm/boot/dts/rk3066a-marsboard.dts
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2014 Romain Perier <romain.perier@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include "rk3066a.dtsi"
+/ {
+        model = "MarsBoard RK3066";
+        compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a";
+        memory {
+                reg = <0x60000000 0x40000000>;
+        };
+        vcc_sd0: sdmmc-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "sdmmc-supply";
+                regulator-min-microvolt = <3000000>;
+                regulator-max-microvolt = <3000000>;
+                gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
+                startup-delay-us = <100000>;
+                vin-supply = <&vcc_io>;
+        };
+        vsys: vsys-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "vsys";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
+        };
+};
+&i2c1 {
+        status = "okay";
+        clock-frequency = <400000>;
+        tps: tps@2d {
+                reg = <0x2d>;
+                interrupt-parent = <&gpio6>;
+                interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+                vcc1-supply = <&vsys>;
+                vcc2-supply = <&vsys>;
+                vcc3-supply = <&vsys>;
+                vcc4-supply = <&vsys>;
+                vcc5-supply = <&vcc_io>;
+                vcc6-supply = <&vcc_io>;
+                vcc7-supply = <&vsys>;
+                vccio-supply = <&vsys>;
+                regulators {
+                        vcc_rtc: regulator@0 {
+                                regulator-name = "vcc_rtc";
+                                regulator-always-on;
+                        };
+                        vcc_io: regulator@1 {
+                                regulator-name = "vcc_io";
+                                regulator-always-on;
+                        };
+                        vdd_arm: regulator@2 {
+                                regulator-name = "vdd_arm";
+                                regulator-min-microvolt = <600000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vcc_ddr: regulator@3 {
+                                regulator-name = "vcc_ddr";
+                                regulator-min-microvolt = <600000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vcc18_cif: regulator@5 {
+                                regulator-name = "vcc18_cif";
+                                regulator-always-on;
+                        };
+                        vdd_11: regulator@6 {
+                                regulator-name = "vdd_11";
+                                regulator-always-on;
+                        };
+                        vcc_25: regulator@7 {
+                                regulator-name = "vcc_25";
+                                regulator-always-on;
+                        };
+                        vcc_18: regulator@8 {
+                                regulator-name = "vcc_18";
+                                regulator-always-on;
+                        };
+                        vcc25_hdmi: regulator@9 {
+                                regulator-name = "vcc25_hdmi";
+                                regulator-always-on;
+                        };
+                        vcca_33: regulator@10 {
+                                regulator-name = "vcca_33";
+                                regulator-always-on;
+                        };
+                        vcc_rmii: regulator@11 {
+                                regulator-name = "vcc_rmii";
+                        };
+                        vcc28_cif: regulator@12 {
+                                regulator-name = "vcc28_cif";
+                                regulator-always-on;
+                        };
+                };
+        };
+};
+/* must be included after &tps gets defined */
+#include "tps65910.dtsi"
+&emac {
+        status = "okay";
+        phy = <&phy0>;
+        phy-supply = <&vcc_rmii>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
+        phy0: ethernet-phy@0 {
+                reg = <0>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+        };
+};
+&pinctrl {
+        lan8720a {
+                phy_int: phy-int {
+                        rockchip,pins = <RK_GPIO1 26 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+};
+&uart0 {
+        status = "okay";
+};
+&uart1 {
+        status = "okay";
+};
+&uart2 {
+        status = "okay";
+};
+&uart3 {
+        status = "okay";
+};
+&wdt {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index ad9c2db59670..41ffd4951ef3 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -26,11 +26,21 @@
                #size-cells = <0>;
                enable-method = "rockchip,rk3066-smp";
-                cpu@0 {
+                cpu0: cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        next-level-cache = <&L2>;
                        reg = <0x0>;
+                        operating-points = <
+                                /* kHz    uV */
+                                1008000 1075000
+                                 816000 1025000
+                                 600000 1025000
+                                 504000 1000000
+                                 312000  975000
+                        >;
+                        clock-latency = <40000>;
+                        clocks = <&cru ARMCLK>;
                };
                cpu@1 {
                        device_type = "cpu";
@@ -53,6 +63,51 @@
                };
        };
+        i2s0: i2s@10118000 {
+                compatible = "rockchip,rk3066-i2s";
+                reg = <0x10118000 0x2000>;
+                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2s0_bus>;
+                dmas = <&dmac1_s 4>, <&dmac1_s 5>;
+                dma-names = "tx", "rx";
+                clock-names = "i2s_hclk", "i2s_clk";
+                clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
+                status = "disabled";
+        };
+        i2s1: i2s@1011a000 {
+                compatible = "rockchip,rk3066-i2s";
+                reg = <0x1011a000 0x2000>;
+                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2s1_bus>;
+                dmas = <&dmac1_s 6>, <&dmac1_s 7>;
+                dma-names = "tx", "rx";
+                clock-names = "i2s_hclk", "i2s_clk";
+                clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
+                status = "disabled";
+        };
+        i2s2: i2s@1011c000 {
+                compatible = "rockchip,rk3066-i2s";
+                reg = <0x1011c000 0x2000>;
+                interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2s2_bus>;
+                dmas = <&dmac1_s 9>, <&dmac1_s 10>;
+                dma-names = "tx", "rx";
+                clock-names = "i2s_hclk", "i2s_clk";
+                clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
+                status = "disabled";
+        };
        cru: clock-controller@20000000 {
                compatible = "rockchip,rk3066a-cru";
                reg = <0x20000000 0x1000>;
@@ -179,6 +234,24 @@
                        bias-disable;
                };
+                emac {
+                        emac_xfer: emac-xfer {
+                                rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
+                                                <RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
+                                                <RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
+                                                <RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
+                                                <RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
+                                                <RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
+                                                <RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
+                                                <RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
+                        };
+                        emac_mdio: emac-mdio {
+                                rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
+                                                <RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
+                        };
+                };
                emmc {
                        emmc_clk: emmc-clk {
                                rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
@@ -405,6 +478,42 @@
                                                <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
                        };
                };
+                i2s0 {
+                        i2s0_bus: i2s0-bus {
+                                rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
+                        };
+                };
+                i2s1 {
+                        i2s1_bus: i2s1-bus {
+                                rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
+                        };
+                };
+                i2s2 {
+                        i2s2_bus: i2s2-bus {
+                                rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
+                        };
+                };
        };
 };
@@ -496,3 +605,7 @@
 &wdt {
        compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
 };
+&emac {
+        compatible = "rockchip,rk3066-emac";
+};
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index 15910c9ddbc7..9a09579b8309 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -43,16 +43,19 @@
                compatible = "gpio-leds";
                green {
+                        label = "rock:green:user1";
                        gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
                        default-state = "off";
                };
-                yellow {
+                blue {
+                        label = "rock:blue:user2";
                        gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
                        default-state = "off";
                };
                sleep {
+                        label = "rock:red:power";
                        gpios = <&gpio0 15 0>;
                        default-state = "off";
                };
@@ -118,6 +121,10 @@
        };
 };
+&cpu0 {
+        cpu0-supply = <&vdd_arm>;
+};
 &i2c1 {
        status = "okay";
        clock-frequency = <400000>;
@@ -159,7 +166,7 @@
                        vdd_arm: REG3 {
                                regulator-name = "VDD_ARM";
                                regulator-min-microvolt = <875000>;
-                                regulator-max-microvolt = <1300000>;
+                                regulator-max-microvolt = <1350000>;
                                regulator-always-on;
                        };
@@ -239,6 +246,18 @@
        disable-wp;
 };
+&pwm1 {
+        status = "okay";
+};
+&pwm2 {
+        status = "okay";
+};
+&pwm3 {
+        status = "okay";
+};
 &pinctrl {
        pcfg_output_low: pcfg-output-low {
                output-low;
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index ddaada788b45..1d4d79c6688d 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -26,11 +26,24 @@
                #size-cells = <0>;
                enable-method = "rockchip,rk3066-smp";
-                cpu@0 {
+                cpu0: cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        next-level-cache = <&L2>;
                        reg = <0x0>;
+                        operating-points = <
+                                /* kHz    uV */
+                                1608000 1350000
+                                1416000 1250000
+                                1200000 1150000
+                                1008000 1075000
+                                 816000  975000
+                                 600000  950000
+                                 504000  925000
+                                 312000  875000
+                        >;
+                        clock-latency = <40000>;
+                        clocks = <&cru ARMCLK>;
                };
                cpu@1 {
                        device_type = "cpu";
@@ -65,6 +78,21 @@
                };
        };
+        i2s0: i2s@1011a000 {
+                compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
+                reg = <0x1011a000 0x2000>;
+                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2s0_bus>;
+                dmas = <&dmac1_s 6>, <&dmac1_s 7>;
+                dma-names = "tx", "rx";
+                clock-names = "i2s_hclk", "i2s_clk";
+                clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
+                status = "disabled";
+        };
        cru: clock-controller@20000000 {
                compatible = "rockchip,rk3188-cru";
                reg = <0x20000000 0x1000>;
@@ -83,7 +111,7 @@
                #size-cells = <1>;
                ranges;
-                gpio0: gpio0@0x2000a000 {
+                gpio0: gpio0@2000a000 {
                        compatible = "rockchip,rk3188-gpio-bank0";
                        reg = <0x2000a000 0x100>;
                        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
@@ -96,7 +124,7 @@
                        #interrupt-cells = <2>;
                };
-                gpio1: gpio1@0x2003c000 {
+                gpio1: gpio1@2003c000 {
                        compatible = "rockchip,gpio-bank";
                        reg = <0x2003c000 0x100>;
                        interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
@@ -395,6 +423,17 @@
                                                <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
                        };
                };
+                i2s0 {
+                        i2s0_bus: i2s0-bus {
+                                rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
+                                                <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
+                                                <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
+                                                <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
+                                                <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
+                                                <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
+                        };
+                };
        };
 };
diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts
index ff522f8e3df4..d8c775e6d5fe 100644
--- a/arch/arm/boot/dts/rk3288-evb-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -17,6 +17,10 @@
        compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";
 };
+&cpu0 {
+        cpu0-supply = <&vdd_cpu>;
+};
 &i2c0 {
        clock-frequency = <400000>;
        status = "okay";
@@ -44,7 +48,7 @@
                                regulator-always-on;
                                regulator-boot-on;
                                regulator-min-microvolt = <750000>;
-                                regulator-max-microvolt = <1300000>;
+                                regulator-max-microvolt = <1350000>;
                                regulator-name = "vdd_arm";
                        };
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index cb83cea52fa1..3e067dd65d0c 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -148,6 +148,12 @@
        status = "okay";
 };
+&tsadc {
+        rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
+        rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
+        status = "okay";
+};
 &pinctrl {
        backlight {
                bl_en: bl-en {
diff --git a/arch/arm/boot/dts/rk3288-thermal.dtsi b/arch/arm/boot/dts/rk3288-thermal.dtsi
new file mode 100644
index 000000000000..2695200c0af7
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-thermal.dtsi
@@ -0,0 +1,74 @@
+/*
+ * Device Tree Source for RK3288 SoC thermal
+ *
+ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#include <dt-bindings/thermal/thermal.h>
+reserve_thermal: reserve_thermal {
+        polling-delay-passive = <1000>; /* milliseconds */
+        polling-delay = <5000>; /* milliseconds */
+        thermal-sensors = <&tsadc 0>;
+};
+cpu_thermal: cpu_thermal {
+        polling-delay-passive = <1000>; /* milliseconds */
+        polling-delay = <5000>; /* milliseconds */
+        thermal-sensors = <&tsadc 1>;
+        trips {
+                cpu_alert0: cpu_alert0 {
+                        temperature = <70000>; /* millicelsius */
+                        hysteresis = <2000>; /* millicelsius */
+                        type = "passive";
+                };
+                cpu_crit: cpu_crit {
+                        temperature = <90000>; /* millicelsius */
+                        hysteresis = <2000>; /* millicelsius */
+                        type = "critical";
+                };
+        };
+        cooling-maps {
+                map0 {
+                        trip = <&cpu_alert0>;
+                        cooling-device =
+                                <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                };
+        };
+};
+gpu_thermal: gpu_thermal {
+        polling-delay-passive = <1000>; /* milliseconds */
+        polling-delay = <5000>; /* milliseconds */
+        thermal-sensors = <&tsadc 2>;
+        trips {
+                gpu_alert0: gpu_alert0 {
+                        temperature = <70000>; /* millicelsius */
+                        hysteresis = <2000>; /* millicelsius */
+                        type = "passive";
+                };
+                gpu_crit: gpu_crit {
+                        temperature = <90000>; /* millicelsius */
+                        hysteresis = <2000>; /* millicelsius */
+                        type = "critical";
+                };
+        };
+        cooling-maps {
+                map0 {
+                        trip = <&gpu_alert0>;
+                        cooling-device =
+                                <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 874e66dbb93b..fd19f00784bd 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -15,6 +15,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/clock/rk3288-cru.h>
+#include <dt-bindings/thermal/thermal.h>
 #include "skeleton.dtsi"
 / {
@@ -46,26 +47,50 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
+                enable-method = "rockchip,rk3066-smp";
+                rockchip,pmu = <&pmu>;
-                cpu@500 {
+                cpu0: cpu@500 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a12";
                        reg = <0x500>;
+                        resets = <&cru SRST_CORE0>;
+                        operating-points = <
+                                /* KHz    uV */
+                                1608000 1350000
+                                1512000 1300000
+                                1416000 1200000
+                                1200000 1100000
+                                1008000 1050000
+                                 816000 1000000
+                                 696000  950000
+                                 600000  900000
+                                 408000  900000
+                                 312000  900000
+                                 216000  900000
+                                 126000  900000
+                        >;
+                        #cooling-cells = <2>; /* min followed by max */
+                        clock-latency = <40000>;
+                        clocks = <&cru ARMCLK>;
                };
                cpu@501 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a12";
                        reg = <0x501>;
+                        resets = <&cru SRST_CORE1>;
                };
                cpu@502 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a12";
                        reg = <0x502>;
+                        resets = <&cru SRST_CORE2>;
                };
                cpu@503 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a12";
                        reg = <0x503>;
+                        resets = <&cru SRST_CORE3>;
                };
        };
@@ -116,6 +141,7 @@
        timer {
                compatible = "arm,armv7-timer";
+                arm,cpu-registers-not-fw-configured;
                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
                             <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
                             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
@@ -177,6 +203,8 @@
                compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
                clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
                clock-names = "spiclk", "apb_pclk";
+                dmas = <&dmac_peri 11>, <&dmac_peri 12>;
+                dma-names = "tx", "rx";
                interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
                pinctrl-names = "default";
                pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
@@ -190,6 +218,8 @@
                compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
                clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
                clock-names = "spiclk", "apb_pclk";
+                dmas = <&dmac_peri 13>, <&dmac_peri 14>;
+                dma-names = "tx", "rx";
                interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
                pinctrl-names = "default";
                pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
@@ -203,6 +233,8 @@
                compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
                clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
                clock-names = "spiclk", "apb_pclk";
+                dmas = <&dmac_peri 15>, <&dmac_peri 16>;
+                dma-names = "tx", "rx";
                interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                pinctrl-names = "default";
                pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
@@ -329,6 +361,25 @@
                status = "disabled";
        };
+        thermal-zones {
+                #include "rk3288-thermal.dtsi"
+        };
+        tsadc: tsadc@ff280000 {
+                compatible = "rockchip,rk3288-tsadc";
+                reg = <0xff280000 0x100>;
+                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
+                clock-names = "tsadc", "apb_pclk";
+                resets = <&cru SRST_TSADC>;
+                reset-names = "tsadc-apb";
+                pinctrl-names = "default";
+                pinctrl-0 = <&otp_out>;
+                #thermal-sensor-cells = <1>;
+                rockchip,hw-tshut-temp = <95000>;
+                status = "disabled";
+        };
        usb_host0_ehci: usb@ff500000 {
                compatible = "generic-ehci";
                reg = <0xff500000 0x100>;
@@ -439,6 +490,18 @@
                status = "disabled";
        };
+        bus_intmem@ff700000 {
+                compatible = "mmio-sram";
+                reg = <0xff700000 0x18000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0xff700000 0x18000>;
+                smp-sram@0 {
+                        compatible = "rockchip,rk3066-smp-sram";
+                        reg = <0x00 0x10>;
+                };
+        };
        pmu: power-management@ff730000 {
                compatible = "rockchip,rk3288-pmu", "syscon";
                reg = <0xff730000 0x100>;
@@ -455,6 +518,16 @@
                rockchip,grf = <&grf>;
                #clock-cells = <1>;
                #reset-cells = <1>;
+                assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
+                                  <&cru PLL_NPLL>, <&cru ACLK_CPU>,
+                                  <&cru HCLK_CPU>, <&cru PCLK_CPU>,
+                                  <&cru ACLK_PERI>, <&cru HCLK_PERI>,
+                                  <&cru PCLK_PERI>;
+                assigned-clock-rates = <594000000>, <400000000>,
+                                       <500000000>, <300000000>,
+                                       <150000000>, <75000000>,
+                                       <300000000>, <150000000>,
+                                       <75000000>;
        };
        grf: syscon@ff770000 {
@@ -484,6 +557,24 @@
                status = "disabled";
        };
+        vopb_mmu: iommu@ff930300 {
+                compatible = "rockchip,iommu";
+                reg = <0xff930300 0x100>;
+                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "vopb_mmu";
+                #iommu-cells = <0>;
+                status = "disabled";
+        };
+        vopl_mmu: iommu@ff940300 {
+                compatible = "rockchip,iommu";
+                reg = <0xff940300 0x100>;
+                interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "vopl_mmu";
+                #iommu-cells = <0>;
+                status = "disabled";
+        };
        gic: interrupt-controller@ffc01000 {
                compatible = "arm,gic-400";
                interrupt-controller;
@@ -948,6 +1039,12 @@
                        };
                };
+                tsadc {
+                        otp_out: otp-out {
+                                rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
+                        };
+                };
                pwm0 {
                        pwm0_pin: pwm0-pin {
                                rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 499468d42ada..c54a9715dcfa 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -29,6 +29,10 @@
                mshc0 = &emmc;
                mshc1 = &mmc0;
                mshc2 = &mmc1;
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
                spi0 = &spi0;
                spi1 = &spi1;
        };
@@ -173,10 +177,9 @@
                compatible = "rockchip,rk2928-dw-mshc";
                reg = <0x10214000 0x1000>;
                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
                clock-names = "biu", "ciu";
+                fifo-depth = <256>;
                status = "disabled";
        };
@@ -184,10 +187,9 @@
                compatible = "rockchip,rk2928-dw-mshc";
                reg = <0x10218000 0x1000>;
                interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
                clock-names = "biu", "ciu";
+                fifo-depth = <256>;
                status = "disabled";
        };
@@ -195,10 +197,9 @@
                compatible = "rockchip,rk2928-dw-mshc";
                reg = <0x1021c000 0x1000>;
                interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
                clock-names = "biu", "ciu";
+                fifo-depth = <256>;
                status = "disabled";
        };
@@ -367,6 +368,8 @@
                reg = <0x20070000 0x1000>;
                #address-cells = <1>;
                #size-cells = <0>;
+                dmas = <&dmac2 10>, <&dmac2 11>;
+                dma-names = "tx", "rx";
                status = "disabled";
        };
@@ -378,6 +381,8 @@
                reg = <0x20074000 0x1000>;
                #address-cells = <1>;
                #size-cells = <0>;
+                dmas = <&dmac2 12>, <&dmac2 13>;
+                dma-names = "tx", "rx";
                status = "disabled";
        };
 };
diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts
index 57e00f9bce99..a25debb50401 100644
--- a/arch/arm/boot/dts/s3c6410-mini6410.dts
+++ b/arch/arm/boot/dts/s3c6410-mini6410.dts
@@ -198,10 +198,6 @@
        status = "okay";
 };
-&pwm {
-        status = "okay";
-};
 &pinctrl0 {
        gpio_leds: gpio-leds {
                samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7";
diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi
index ff5bdaac987a..0ccb414cd268 100644
--- a/arch/arm/boot/dts/s3c64xx.dtsi
+++ b/arch/arm/boot/dts/s3c64xx.dtsi
@@ -172,7 +172,6 @@
                        clocks = <&clocks PCLK_PWM>;
                        samsung,pwm-outputs = <0>, <1>;
                        #pwm-cells = <3>;
-                        status = "disabled";
                };
                pinctrl0: pinctrl@7f008000 {
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index 30ef97e99dc5..939be1299ca6 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -40,6 +40,7 @@
        chosen {
                bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel rw";
+                stdout-path = &scifa4;
        };
        memory {
@@ -100,19 +101,23 @@
                compatible = "gpio-leds";
                led1 {
                        gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
+                        label = "LED1";
                };
                led2 {
                        gpios = <&pfc 21 GPIO_ACTIVE_LOW>;
+                        label = "LED2";
                };
                led3 {
                        gpios = <&pfc 22 GPIO_ACTIVE_LOW>;
+                        label = "LED3";
                };
                led4 {
                        gpios = <&pfc 23 GPIO_ACTIVE_LOW>;
+                        label = "LED4";
                };
        };
-        gpio-keys {
+        keyboard {
                compatible = "gpio-keys";
                back-key {
@@ -250,7 +255,7 @@
                };
        };
-        ak4648: ak4648@0x12 {
+        ak4648: ak4648@12 {
                #sound-dai-cells = <0>;
                compatible = "asahi-kasei,ak4648";
                reg = <0x12>;
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 030a5920312f..d8def5a529da 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -138,7 +138,7 @@
        i2c0: i2c@e6820000 {
                #address-cells = <1>;
                #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
                reg = <0xe6820000 0x425>;
                interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH
                              0 168 IRQ_TYPE_LEVEL_HIGH
@@ -150,7 +150,7 @@
        i2c1: i2c@e6822000 {
                #address-cells = <1>;
                #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
                reg = <0xe6822000 0x425>;
                interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH
                              0 52 IRQ_TYPE_LEVEL_HIGH
@@ -162,7 +162,7 @@
        i2c2: i2c@e6824000 {
                #address-cells = <1>;
                #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
                reg = <0xe6824000 0x425>;
                interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH
                              0 172 IRQ_TYPE_LEVEL_HIGH
@@ -174,7 +174,7 @@
        i2c3: i2c@e6826000 {
                #address-cells = <1>;
                #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
                reg = <0xe6826000 0x425>;
                interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH
                              0 184 IRQ_TYPE_LEVEL_HIGH
@@ -186,7 +186,7 @@
        i2c4: i2c@e6828000 {
                #address-cells = <1>;
                #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
                reg = <0xe6828000 0x425>;
                interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH
                              0 188 IRQ_TYPE_LEVEL_HIGH
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 4472fd92685c..252c3d1bda50 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -639,6 +639,33 @@
                        clock-names = "biu", "ciu";
                };
+                ocram: sram@ffff0000 {
+                        compatible = "mmio-sram";
+                        reg = <0xffff0000 0x10000>;
+                };
+                spi0: spi@fff00000 {
+                        compatible = "snps,dw-apb-ssi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0xfff00000 0x1000>;
+                        interrupts = <0 154 4>;
+                        num-cs = <4>;
+                        clocks = <&spi_m_clk>;
+                        status = "disabled";
+                };
+                spi1: spi@fff01000 {
+                        compatible = "snps,dw-apb-ssi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0xfff01000 0x1000>;
+                        interrupts = <0 156 4>;
+                        num-cs = <4>;
+                        clocks = <&spi_m_clk>;
+                        status = "disabled";
+                };
                /* Local timer */
                timer@fffec600 {
                        compatible = "arm,cortex-a9-twd-timer";
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
new file mode 100644
index 000000000000..8a05c47fd57f
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -0,0 +1,374 @@
+/*
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        aliases {
+                ethernet0 = &gmac0;
+                ethernet1 = &gmac1;
+                ethernet2 = &gmac2;
+                serial0 = &uart0;
+                serial1 = &uart1;
+                timer0 = &timer0;
+                timer1 = &timer1;
+                timer2 = &timer2;
+                timer3 = &timer3;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                };
+                cpu@1 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+        intc: intc@ffffd000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0xffffd000 0x1000>,
+                      <0xffffc100 0x100>;
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                device_type = "soc";
+                interrupt-parent = <&intc>;
+                ranges;
+                amba {
+                        compatible = "arm,amba-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        pdma: pdma@ffda1000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0xffda1000 0x1000>;
+                                interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 84 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 85 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 86 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 87 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 88 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 89 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 90 IRQ_TYPE_LEVEL_HIGH>;
+                                #dma-cells = <1>;
+                                #dma-channels = <8>;
+                                #dma-requests = <32>;
+                        };
+                };
+                clkmgr@ffd04000 {
+                                compatible = "altr,clk-mgr";
+                                reg = <0xffd04000 0x1000>;
+                                clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        osc1: osc1 {
+                                                #clock-cells = <0>;
+                                                compatible = "fixed-clock";
+                                        };
+                                        main_pll: main_pll {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-pll-clock";
+                                                clocks = <&osc1>;
+                                        };
+                                        periph_pll: periph_pll {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-pll-clock";
+                                                clocks = <&osc1>;
+                                        };
+                                };
+                };
+                gmac0: ethernet@ff800000 {
+                        compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
+                        reg = <0xff800000 0x2000>;
+                        interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "macirq";
+                        /* Filled in by bootloader */
+                        mac-address = [00 00 00 00 00 00];
+                        status = "disabled";
+                };
+                gmac1: ethernet@ff802000 {
+                        compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
+                        reg = <0xff802000 0x2000>;
+                        interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "macirq";
+                        /* Filled in by bootloader */
+                        mac-address = [00 00 00 00 00 00];
+                        status = "disabled";
+                };
+                gmac2: ethernet@ff804000 {
+                        compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
+                        reg = <0xff804000 0x2000>;
+                        interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "macirq";
+                        /* Filled in by bootloader */
+                        mac-address = [00 00 00 00 00 00];
+                        status = "disabled";
+                };
+                gpio0: gpio@ffc02900 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "snps,dw-apb-gpio";
+                        reg = <0xffc02900 0x100>;
+                        status = "disabled";
+                        porta: gpio-controller@0 {
+                                compatible = "snps,dw-apb-gpio-port";
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                snps,nr-gpios = <29>;
+                                reg = <0>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                };
+                gpio1: gpio@ffc02a00 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "snps,dw-apb-gpio";
+                        reg = <0xffc02a00 0x100>;
+                        status = "disabled";
+                        portb: gpio-controller@0 {
+                                compatible = "snps,dw-apb-gpio-port";
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                snps,nr-gpios = <29>;
+                                reg = <0>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                };
+                gpio2: gpio@ffc02b00 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "snps,dw-apb-gpio";
+                        reg = <0xffc02b00 0x100>;
+                        status = "disabled";
+                        portc: gpio-controller@0 {
+                                compatible = "snps,dw-apb-gpio-port";
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                snps,nr-gpios = <27>;
+                                reg = <0>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                };
+                i2c0: i2c@ffc02200 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "snps,designware-i2c";
+                        reg = <0xffc02200 0x100>;
+                        interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+                i2c1: i2c@ffc02300 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "snps,designware-i2c";
+                        reg = <0xffc02300 0x100>;
+                        interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+                i2c2: i2c@ffc02400 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "snps,designware-i2c";
+                        reg = <0xffc02400 0x100>;
+                        interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+                i2c3: i2c@ffc02500 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "snps,designware-i2c";
+                        reg = <0xffc02500 0x100>;
+                        interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+                i2c4: i2c@ffc02600 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "snps,designware-i2c";
+                        reg = <0xffc02600 0x100>;
+                        interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+                L2: l2-cache@fffff000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0xfffff000 0x1000>;
+                        interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+                mmc: dwmmc0@ff808000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "altr,socfpga-dw-mshc";
+                        reg = <0xff808000 0x1000>;
+                        interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
+                        fifo-depth = <0x400>;
+                };
+                ocram: sram@ffe00000 {
+                        compatible = "mmio-sram";
+                        reg = <0xffe00000 0x40000>;
+                };
+                rst: rstmgr@ffd05000 {
+                        #reset-cells = <1>;
+                        compatible = "altr,rst-mgr";
+                        reg = <0xffd05000 0x100>;
+                };
+                sysmgr: sysmgr@ffd06000 {
+                        compatible = "altr,sys-mgr", "syscon";
+                        reg = <0xffd06000 0x300>;
+                };
+                /* Local timer */
+                timer@ffffc600 {
+                        compatible = "arm,cortex-a9-twd-timer";
+                        reg = <0xffffc600 0x100>;
+                        interrupts = <1 13 0xf04>;
+                };
+                timer0: timer0@ffc02700 {
+                        compatible = "snps,dw-apb-timer";
+                        interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
+                        reg = <0xffc02700 0x100>;
+                };
+                timer1: timer1@ffc02800 {
+                        compatible = "snps,dw-apb-timer";
+                        interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
+                        reg = <0xffc02800 0x100>;
+                };
+                timer2: timer2@ffd00000 {
+                        compatible = "snps,dw-apb-timer";
+                        interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
+                        reg = <0xffd00000 0x100>;
+                };
+                timer3: timer3@ffd00100 {
+                        compatible = "snps,dw-apb-timer";
+                        interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
+                        reg = <0xffd01000 0x100>;
+                };
+                uart0: serial0@ffc02000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0xffc02000 0x100>;
+                        interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                };
+                uart1: serial1@ffc02100 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0xffc02100 0x100>;
+                        interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                };
+                usbphy0: usbphy@0 {
+                        #phy-cells = <0>;
+                        compatible = "usb-nop-xceiv";
+                        status = "okay";
+                };
+                usb0: usb@ffb00000 {
+                        compatible = "snps,dwc2";
+                        reg = <0xffb00000 0xffff>;
+                        interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
+                        phys = <&usbphy0>;
+                        phy-names = "usb2-phy";
+                        status = "disabled";
+                };
+                usb1: usb@ffb40000 {
+                        compatible = "snps,dwc2";
+                        reg = <0xffb40000 0xffff>;
+                        interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
+                        phys = <&usbphy0>;
+                        phy-names = "usb2-phy";
+                        status = "disabled";
+                };
+                watchdog0: watchdog@ffd00200 {
+                        compatible = "snps,dw-wdt";
+                        reg = <0xffd00200 0x100>;
+                        interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+                watchdog1: watchdog@ffd00300 {
+                        compatible = "snps,dw-wdt";
+                        reg = <0xffd00300 0x100>;
+                        interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dts b/arch/arm/boot/dts/socfpga_arria10_socdk.dts
new file mode 100755
index 000000000000..3015ce8d3057
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dts
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/dts-v1/;
+#include "socfpga_arria10.dtsi"
+/ {
+        model = "Altera SOCFPGA Arria 10";
+        compatible = "altr,socfpga-arria10", "altr,socfpga";
+        chosen {
+                bootargs = "console=ttyS0,115200 rootwait";
+        };
+        memory {
+                name = "memory";
+                device_type = "memory";
+                reg = <0x0 0x40000000>; /* 1GB */
+        };
+        soc {
+                clkmgr@ffd04000 {
+                        clocks {
+                                osc1 {
+                                        clock-frequency = <25000000>;
+                                };
+                        };
+                };
+                serial0@ffc02000 {
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index 28c05e7a31c9..06db951e06f8 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -49,3 +49,7 @@
                };
        };
 };
+&watchdog0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi b/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi
index e0799966bc25..52dba2e39c71 100644
--- a/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi
+++ b/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi
@@ -16,31 +16,31 @@
                        uart0 {
                                uart0_default_mux: uart0_mux {
                                        default_mux {
-                                                ste,function = "u0";
+                                                function = "u0";
-                                                ste,pins = "u0_a_1";
+                                                groups = "u0_a_1";
                                        };
                                };
                                uart0_default_mode: uart0_default {
                                        default_cfg1 {
-                                                ste,pins = "GPIO0", "GPIO2";
+                                                pins = "GPIO0", "GPIO2";
                                                ste,config = <&in_pu>;
                                        };
                                        default_cfg2 {
-                                                ste,pins = "GPIO1", "GPIO3";
+                                                pins = "GPIO1", "GPIO3";
                                                ste,config = <&out_hi>;
                                        };
                                };
                                uart0_sleep_mode: uart0_sleep {
                                        sleep_cfg1 {
-                                                ste,pins = "GPIO0", "GPIO2";
+                                                pins = "GPIO0", "GPIO2";
                                                ste,config = <&slpm_in_pu>;
                                        };
                                        sleep_cfg2 {
-                                                ste,pins = "GPIO1", "GPIO3";
+                                                pins = "GPIO1", "GPIO3";
                                                ste,config = <&slpm_out_hi>;
                                        };
                                };
@@ -49,29 +49,29 @@
                        uart2 {
                                uart2_default_mode: uart2_default {
                                        default_mux {
-                                                ste,function = "u2";
+                                                function = "u2";
-                                                ste,pins = "u2txrx_a_1";
+                                                groups = "u2txrx_a_1";
                                        };
                                        default_cfg1 {
-                                                ste,pins = "GPIO120";
+                                                pins = "GPIO120";
                                                ste,config = <&in_pu>;
                                        };
                                        default_cfg2 {
-                                                ste,pins = "GPIO121";
+                                                pins = "GPIO121";
                                                ste,config = <&out_hi>;
                                        };
                                };
                                uart2_sleep_mode: uart2_sleep {
                                        sleep_cfg1 {
-                                                ste,pins = "GPIO120";
+                                                pins = "GPIO120";
                                                ste,config = <&slpm_in_pu>;
                                        };
                                        sleep_cfg2 {
-                                                ste,pins = "GPIO121";
+                                                pins = "GPIO121";
                                                ste,config = <&slpm_out_hi>;
                                        };
                                };
@@ -80,21 +80,21 @@
                        i2c0 {
                                i2c0_default_mux: i2c_mux {
                                        default_mux {
-                                                ste,function = "i2c0";
+                                                function = "i2c0";
-                                                ste,pins = "i2c0_a_1";
+                                                groups = "i2c0_a_1";
                                        };
                                };
                                i2c0_default_mode: i2c_default {
                                        default_cfg1 {
-                                                ste,pins = "GPIO147", "GPIO148";
+                                                pins = "GPIO147", "GPIO148";
                                                ste,config = <&in_pu>;
                                        };
                                };
                                i2c0_sleep_mode: i2c_sleep {
                                        sleep_cfg1 {
-                                                ste,pins = "GPIO147", "GPIO148";
+                                                pins = "GPIO147", "GPIO148";
                                                ste,config = <&slpm_in_pu>;
                                        };
                                };
@@ -103,21 +103,21 @@
                        i2c1 {
                                i2c1_default_mux: i2c_mux {
                                        default_mux {
-                                                ste,function = "i2c1";
+                                                function = "i2c1";
-                                                ste,pins = "i2c1_b_2";
+                                                groups = "i2c1_b_2";
                                        };
                                };
                                i2c1_default_mode: i2c_default {
                                        default_cfg1 {
-                                                ste,pins = "GPIO16", "GPIO17";
+                                                pins = "GPIO16", "GPIO17";
                                                ste,config = <&in_pu>;
                                        };
                                };
                                i2c1_sleep_mode: i2c_sleep {
                                        sleep_cfg1 {
-                                                ste,pins = "GPIO16", "GPIO17";
+                                                pins = "GPIO16", "GPIO17";
                                                ste,config = <&slpm_in_pu>;
                                        };
                                };
@@ -126,21 +126,21 @@
                        i2c2 {
                                i2c2_default_mux: i2c_mux {
                                        default_mux {
-                                                ste,function = "i2c2";
+                                                function = "i2c2";
-                                                ste,pins = "i2c2_b_2";
+                                                groups = "i2c2_b_2";
                                        };
                                };
                                i2c2_default_mode: i2c_default {
                                        default_cfg1 {
-                                                ste,pins = "GPIO10", "GPIO11";
+                                                pins = "GPIO10", "GPIO11";
                                                ste,config = <&in_pu>;
                                        };
                                };
                                i2c2_sleep_mode: i2c_sleep {
                                        sleep_cfg1 {
-                                                ste,pins = "GPIO11", "GPIO11";
+                                                pins = "GPIO11", "GPIO11";
                                                ste,config = <&slpm_in_pu>;
                                        };
                                };
@@ -149,21 +149,21 @@
                        i2c4 {
                                i2c4_default_mux: i2c_mux {
                                        default_mux {
-                                                ste,function = "i2c4";
+                                                function = "i2c4";
-                                                ste,pins = "i2c4_b_2";
+                                                groups = "i2c4_b_2";
                                        };
                                };
                                i2c4_default_mode: i2c_default {
                                        default_cfg1 {
-                                                ste,pins = "GPIO122", "GPIO123";
+                                                pins = "GPIO122", "GPIO123";
                                                ste,config = <&in_pu>;
                                        };
                                };
                                i2c4_sleep_mode: i2c_sleep {
                                        sleep_cfg1 {
-                                                ste,pins = "GPIO122", "GPIO123";
+                                                pins = "GPIO122", "GPIO123";
                                                ste,config = <&slpm_in_pu>;
                                        };
                                };
@@ -172,21 +172,21 @@
                        i2c5 {
                                i2c5_default_mux: i2c_mux {
                                        default_mux {
-                                                ste,function = "i2c5";
+                                                function = "i2c5";
-                                                ste,pins = "i2c5_c_2";
+                                                groups = "i2c5_c_2";
                                        };
                                };
                                i2c5_default_mode: i2c_default {
                                        default_cfg1 {
-                                                ste,pins = "GPIO118", "GPIO119";
+                                                pins = "GPIO118", "GPIO119";
                                                ste,config = <&in_pu>;
                                        };
                                };
                                i2c5_sleep_mode: i2c_sleep {
                                        sleep_cfg1 {
-                                                ste,pins = "GPIO118", "GPIO119";
+                                                pins = "GPIO118", "GPIO119";
                                                ste,config = <&slpm_in_pu>;
                                        };
                                };
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index 9d2323020d34..bfd3f1c734b8 100644
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/mfd/dbx500-prcmu.h>
+#include <dt-bindings/arm/ux500_pm_domains.h>
 #include "skeleton.dtsi"
 / {
@@ -43,6 +44,10 @@
                        interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
                };
+                pm_domains: pm_domains0 {
+                        compatible = "stericsson,ux500-pm-domains";
+                        #power-domain-cells = <1>;
+                };
                clocks {
                        compatible = "stericsson,u8500-clks";
@@ -636,6 +641,7 @@
                        clock-frequency = <400000>;
                        clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
                        clock-names = "i2cclk", "apb_pclk";
+                        power-domains = <&pm_domains DOMAIN_VAPE>;
                };
                i2c@80122000 {
@@ -651,6 +657,7 @@
                        clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
                        clock-names = "i2cclk", "apb_pclk";
+                        power-domains = <&pm_domains DOMAIN_VAPE>;
                };
                i2c@80128000 {
@@ -666,6 +673,7 @@
                        clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
                        clock-names = "i2cclk", "apb_pclk";
+                        power-domains = <&pm_domains DOMAIN_VAPE>;
                };
                i2c@80110000 {
@@ -681,6 +689,7 @@
                        clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
                        clock-names = "i2cclk", "apb_pclk";
+                        power-domains = <&pm_domains DOMAIN_VAPE>;
                };
                i2c@8012a000 {
@@ -696,6 +705,7 @@
                        clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
                        clock-names = "i2cclk", "apb_pclk";
+                        power-domains = <&pm_domains DOMAIN_VAPE>;
                };
                ssp@80002000 {
@@ -709,6 +719,7 @@
                        dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
                               <&dma 8 0 0x0>; /* Logical - MemToDev */
                        dma-names = "rx", "tx";
+                        power-domains = <&pm_domains DOMAIN_VAPE>;
                };
                ssp@80003000 {
@@ -722,6 +733,7 @@
                        dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
                               <&dma 9 0 0x0>; /* Logical - MemToDev */
                        dma-names = "rx", "tx";
+                        power-domains = <&pm_domains DOMAIN_VAPE>;
                };
                spi@8011a000 {
@@ -736,6 +748,7 @@
                        dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
                               <&dma 0 0 0x0>; /* Logical - MemToDev */
                        dma-names = "rx", "tx";
+                        power-domains = <&pm_domains DOMAIN_VAPE>;
                };
                spi@80112000 {
@@ -750,6 +763,7 @@
                        dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
                               <&dma 35 0 0x0>; /* Logical - MemToDev */
                        dma-names = "rx", "tx";
+                        power-domains = <&pm_domains DOMAIN_VAPE>;
                };
                spi@80111000 {
@@ -764,6 +778,7 @@
                        dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
                               <&dma 33 0 0x0>; /* Logical - MemToDev */
                        dma-names = "rx", "tx";
+                        power-domains = <&pm_domains DOMAIN_VAPE>;
                };
                spi@80129000 {
@@ -778,6 +793,7 @@
                        dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
                               <&dma 40 0 0x0>; /* Logical - MemToDev */
                        dma-names = "rx", "tx";
+                        power-domains = <&pm_domains DOMAIN_VAPE>;
                };
                uart@80120000 {
@@ -836,6 +852,7 @@
                        clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
                        clock-names = "sdi", "apb_pclk";
+                        power-domains = <&pm_domains DOMAIN_VAPE>;
                        status = "disabled";
                };
@@ -851,6 +868,7 @@
                        clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
                        clock-names = "sdi", "apb_pclk";
+                        power-domains = <&pm_domains DOMAIN_VAPE>;
                        status = "disabled";
                };
@@ -866,6 +884,7 @@
                        clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
                        clock-names = "sdi", "apb_pclk";
+                        power-domains = <&pm_domains DOMAIN_VAPE>;
                        status = "disabled";
                };
@@ -881,6 +900,7 @@
                        clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
                        clock-names = "sdi", "apb_pclk";
+                        power-domains = <&pm_domains DOMAIN_VAPE>;
                        status = "disabled";
                };
@@ -896,6 +916,7 @@
                        clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
                        clock-names = "sdi", "apb_pclk";
+                        power-domains = <&pm_domains DOMAIN_VAPE>;
                        status = "disabled";
                };
@@ -911,6 +932,7 @@
                        clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
                        clock-names = "sdi", "apb_pclk";
+                        power-domains = <&pm_domains DOMAIN_VAPE>;
                        status = "disabled";
                };
diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi
index 30f8601da323..9b69bce9297d 100644
--- a/arch/arm/boot/dts/ste-href-ab8500.dtsi
+++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi
@@ -47,11 +47,11 @@
                                        gpio2 {
                                                gpio2_default_mode: gpio2_default {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio2_a_1";
+                                                                groups = "gpio2_a_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO2_T9";
+                                                                pins = "GPIO2_T9";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -60,11 +60,11 @@
                                        gpio4 {
                                                gpio4_default_mode: gpio4_default {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio4_a_1";
+                                                                groups = "gpio4_a_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO4_W2";
+                                                                pins = "GPIO4_W2";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -73,11 +73,11 @@
                                        gpio10 {
                                                gpio10_default_mode: gpio10_default {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio10_d_1";
+                                                                groups = "gpio10_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO10_U17";
+                                                                pins = "GPIO10_U17";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -86,11 +86,11 @@
                                        gpio11 {
                                                gpio11_default_mode: gpio11_default {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio11_d_1";
+                                                                groups = "gpio11_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO11_AA18";
+                                                                pins = "GPIO11_AA18";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -99,11 +99,11 @@
                                        gpio12 {
                                                gpio12_default_mode: gpio12_default {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio12_d_1";
+                                                                groups = "gpio12_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO12_U16";
+                                                                pins = "GPIO12_U16";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -112,11 +112,11 @@
                                        gpio13 {
                                                gpio13_default_mode: gpio13_default {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio13_d_1";
+                                                                groups = "gpio13_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO13_W17";
+                                                                pins = "GPIO13_W17";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -125,11 +125,11 @@
                                        gpio16 {
                                                gpio16_default_mode: gpio16_default {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio16_a_1";
+                                                                groups = "gpio16_a_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO16_F15";
+                                                                pins = "GPIO16_F15";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -138,11 +138,11 @@
                                        gpio24 {
                                                gpio24_default_mode: gpio24_default {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio24_a_1";
+                                                                groups = "gpio24_a_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO24_T14";
+                                                                pins = "GPIO24_T14";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -151,11 +151,11 @@
                                        gpio25 {
                                                gpio25_default_mode: gpio25_default {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio25_a_1";
+                                                                groups = "gpio25_a_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO25_R16";
+                                                                pins = "GPIO25_R16";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -164,11 +164,11 @@
                                        gpio36 {
                                                gpio36_default_mode: gpio36_default {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio36_a_1";
+                                                                groups = "gpio36_a_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO36_A17";
+                                                                pins = "GPIO36_A17";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -177,11 +177,11 @@
                                        gpio37 {
                                                gpio37_default_mode: gpio37_default {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio37_a_1";
+                                                                groups = "gpio37_a_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO37_E15";
+                                                                pins = "GPIO37_E15";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -190,11 +190,11 @@
                                        gpio38 {
                                                gpio38_default_mode: gpio38_default {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio38_a_1";
+                                                                groups = "gpio38_a_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO38_C17";
+                                                                pins = "GPIO38_C17";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -203,11 +203,11 @@
                                        gpio39 {
                                                gpio39_default_mode: gpio39_default {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio39_a_1";
+                                                                groups = "gpio39_a_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO39_E16";
+                                                                pins = "GPIO39_E16";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -216,11 +216,11 @@
                                        gpio42 {
                                                gpio42_default_mode: gpio42_default {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio42_a_1";
+                                                                groups = "gpio42_a_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO42_U2";
+                                                                pins = "GPIO42_U2";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -232,11 +232,11 @@
                                        gpio26 {
                                                gpio26_default_mode: gpio26_default {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio26_d_1";
+                                                                groups = "gpio26_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO26_M16";
+                                                                pins = "GPIO26_M16";
                                                                output-low;
                                                        };
                                                };
@@ -244,11 +244,11 @@
                                        gpio35 {
                                                gpio35_default_mode: gpio35_default {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio35_d_1";
+                                                                groups = "gpio35_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO35_W15";
+                                                                pins = "GPIO35_W15";
                                                                output-low;
                                                        };
                                                };
@@ -260,11 +260,11 @@
                                        ycbcr {
                                                ycbcr_default_mode: ycbcr_default {
                                                        default_mux {
-                                                                ste,function = "ycbcr";
+                                                                function = "ycbcr";
-                                                                ste,pins = "ycbcr0123_d_1";
+                                                                groups = "ycbcr0123_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO6_Y18",
+                                                                pins = "GPIO6_Y18",
                                                                         "GPIO7_AA20",
                                                                         "GPIO8_W18",
                                                                         "GPIO9_AA19";
@@ -277,11 +277,11 @@
                                        pwm {
                                                pwm_default_mode: pwm_default {
                                                        default_mux {
-                                                                ste,function = "pwmout";
+                                                                function = "pwmout";
-                                                                ste,pins = "pwmout1_d_1", "pwmout2_d_1";
+                                                                groups = "pwmout1_d_1", "pwmout2_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO14_F14",
+                                                                pins = "GPIO14_F14",
                                                                         "GPIO15_B17";
                                                                input-enable;
                                                                bias-pull-down;
@@ -292,11 +292,11 @@
                                        adi1 {
                                                adi1_default_mode: adi1_default {
                                                        default_mux {
-                                                                ste,function = "adi1";
+                                                                function = "adi1";
-                                                                ste,pins = "adi1_d_1";
+                                                                groups = "adi1_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO17_P5",
+                                                                pins = "GPIO17_P5",
                                                                         "GPIO18_R5",
                                                                         "GPIO19_U5",
                                                                         "GPIO20_T5";
@@ -309,11 +309,11 @@
                                        usbuicc {
                                                usbuicc_default_mode: usbuicc_default {
                                                        default_mux {
-                                                                ste,function = "usbuicc";
+                                                                function = "usbuicc";
-                                                                ste,pins = "usbuicc_d_1";
+                                                                groups = "usbuicc_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO21_H19",
+                                                                pins = "GPIO21_H19",
                                                                         "GPIO22_G20",
                                                                         "GPIO23_G19";
                                                                input-enable;
@@ -325,13 +325,13 @@
                                        dmic {
                                                dmic_default_mode: dmic_default {
                                                        default_mux {
-                                                                ste,function = "dmic";
+                                                                function = "dmic";
-                                                                ste,pins = "dmic12_d_1",
+                                                                groups = "dmic12_d_1",
                                                                         "dmic34_d_1",
                                                                         "dmic56_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO27_J6",
+                                                                pins = "GPIO27_J6",
                                                                         "GPIO28_K6",
                                                                         "GPIO29_G6",
                                                                         "GPIO30_H6",
@@ -345,11 +345,11 @@
                                        extcpena {
                                                extcpena_default_mode: extcpena_default {
                                                        default_mux {
-                                                                ste,function = "extcpena";
+                                                                function = "extcpena";
-                                                                ste,pins = "extcpena_d_1";
+                                                                groups = "extcpena_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO34_R17";
+                                                                pins = "GPIO34_R17";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -359,11 +359,11 @@
                                        modsclsda {
                                                modsclsda_default_mode: modsclsda_default {
                                                        default_mux {
-                                                                ste,function = "modsclsda";
+                                                                function = "modsclsda";
-                                                                ste,pins = "modsclsda_d_1";
+                                                                groups = "modsclsda_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO40_T19",
+                                                                pins = "GPIO40_T19",
                                                                        "GPIO41_U19";
                                                                input-enable;
                                                                bias-pull-down;
@@ -376,22 +376,22 @@
                                        sysclkreq2 {
                                                sysclkreq2_default_mode: sysclkreq2_default {
                                                        default_mux {
-                                                                ste,function = "sysclkreq";
+                                                                function = "sysclkreq";
-                                                                ste,pins = "sysclkreq2_d_1";
+                                                                groups = "sysclkreq2_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO1_T10";
+                                                                pins = "GPIO1_T10";
                                                                input-enable;
                                                                bias-disable;
                                                        };
                                                };
                                                sysclkreq2_sleep_mode: sysclkreq2_sleep {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio1_a_1";
+                                                                groups = "gpio1_a_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO1_T10";
+                                                                pins = "GPIO1_T10";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -400,22 +400,22 @@
                                        sysclkreq4 {
                                                sysclkreq4_default_mode: sysclkreq4_default {
                                                        default_mux {
-                                                                ste,function = "sysclkreq";
+                                                                function = "sysclkreq";
-                                                                ste,pins = "sysclkreq4_d_1";
+                                                                groups = "sysclkreq4_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO3_U9";
+                                                                pins = "GPIO3_U9";
                                                                input-enable;
                                                                bias-disable;
                                                        };
                                                };
                                                sysclkreq4_sleep_mode: sysclkreq4_sleep {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio3_a_1";
+                                                                groups = "gpio3_a_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO3_U9";
+                                                                pins = "GPIO3_U9";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
diff --git a/arch/arm/boot/dts/ste-href-ab8505.dtsi b/arch/arm/boot/dts/ste-href-ab8505.dtsi
index 6006d62086a2..ccf37a9df050 100644
--- a/arch/arm/boot/dts/ste-href-ab8505.dtsi
+++ b/arch/arm/boot/dts/ste-href-ab8505.dtsi
@@ -35,11 +35,11 @@
                                        gpio2 {
                                                gpio2_default_mode: gpio2_default {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio2_a_1";
+                                                                groups = "gpio2_a_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO2_R5";
+                                                                pins = "GPIO2_R5";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -48,11 +48,11 @@
                                        gpio10 {
                                                gpio10_default_mode: gpio10_default {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio10_d_1";
+                                                                groups = "gpio10_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO10_B16";
+                                                                pins = "GPIO10_B16";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -61,11 +61,11 @@
                                        gpio11 {
                                                gpio11_default_mode: gpio11_default {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio11_d_1";
+                                                                groups = "gpio11_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO11_B17";
+                                                                pins = "GPIO11_B17";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -74,11 +74,11 @@
                                        gpio13 {
                                                gpio13_default_mode: gpio13_default {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio13_d_1";
+                                                                groups = "gpio13_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO13_D17";
+                                                                pins = "GPIO13_D17";
                                                                input-enable;
                                                                bias-disable;
                                                        };
@@ -87,11 +87,11 @@
                                        gpio34 {
                                                gpio34_default_mode: gpio34_default {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio34_a_1";
+                                                                groups = "gpio34_a_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO34_H14";
+                                                                pins = "GPIO34_H14";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -100,11 +100,11 @@
                                        gpio50 {
                                                gpio50_default_mode: gpio50_default {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio50_d_1";
+                                                                groups = "gpio50_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO50_L4";
+                                                                pins = "GPIO50_L4";
                                                                input-enable;
                                                                bias-disable;
                                                        };
@@ -114,11 +114,11 @@
                                        pwm {
                                                pwm_default_mode: pwm_default {
                                                        default_mux {
-                                                                ste,function = "pwmout";
+                                                                function = "pwmout";
-                                                                ste,pins = "pwmout1_d_1";
+                                                                groups = "pwmout1_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO14_C16";
+                                                                pins = "GPIO14_C16";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -128,11 +128,11 @@
                                        adi2 {
                                                adi2_default_mode: adi2_default {
                                                        default_mux {
-                                                                ste,function = "adi2";
+                                                                function = "adi2";
-                                                                ste,pins = "adi2_d_1";
+                                                                groups = "adi2_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO17_P2",
+                                                                pins = "GPIO17_P2",
                                                                         "GPIO18_N3",
                                                                         "GPIO19_T1",
                                                                         "GPIO20_P3";
@@ -145,11 +145,11 @@
                                        modsclsda {
                                                modsclsda_default_mode: modsclsda_default {
                                                        default_mux {
-                                                                ste,function = "modsclsda";
+                                                                function = "modsclsda";
-                                                                ste,pins = "modsclsda_d_1";
+                                                                groups = "modsclsda_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO40_J15",
+                                                                pins = "GPIO40_J15",
                                                                        "GPIO41_J14";
                                                                input-enable;
                                                                bias-pull-down;
@@ -159,11 +159,11 @@
                                        resethw {
                                                resethw_default_mode: resethw_default {
                                                        default_mux {
-                                                                ste,function = "resethw";
+                                                                function = "resethw";
-                                                                ste,pins = "resethw_d_1";
+                                                                groups = "resethw_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO52_D16";
+                                                                pins = "GPIO52_D16";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -172,11 +172,11 @@
                                        service {
                                                service_default_mode: service_default {
                                                        default_mux {
-                                                                ste,function = "service";
+                                                                function = "service";
-                                                                ste,pins = "service_d_1";
+                                                                groups = "service_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO53_D15";
+                                                                pins = "GPIO53_D15";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -188,22 +188,22 @@
                                        sysclkreq2 {
                                                sysclkreq2_default_mode: sysclkreq2_default {
                                                        default_mux {
-                                                                ste,function = "sysclkreq";
+                                                                function = "sysclkreq";
-                                                                ste,pins = "sysclkreq2_d_1";
+                                                                groups = "sysclkreq2_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO1_N4";
+                                                                pins = "GPIO1_N4";
                                                                input-enable;
                                                                bias-disable;
                                                        };
                                                };
                                                sysclkreq2_sleep_mode: sysclkreq2_sleep {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio1_a_1";
+                                                                groups = "gpio1_a_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO1_N4";
+                                                                pins = "GPIO1_N4";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
@@ -212,22 +212,22 @@
                                        sysclkreq4 {
                                                sysclkreq4_default_mode: sysclkreq4_default {
                                                        default_mux {
-                                                                ste,function = "sysclkreq";
+                                                                function = "sysclkreq";
-                                                                ste,pins = "sysclkreq4_d_1";
+                                                                groups = "sysclkreq4_d_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO3_P5";
+                                                                pins = "GPIO3_P5";
                                                                input-enable;
                                                                bias-disable;
                                                        };
                                                };
                                                sysclkreq4_sleep_mode: sysclkreq4_sleep {
                                                        default_mux {
-                                                                ste,function = "gpio";
+                                                                function = "gpio";
-                                                                ste,pins = "gpio3_a_1";
+                                                                groups = "gpio3_a_1";
                                                        };
                                                        default_cfg {
-                                                                ste,pins = "GPIO3_P5";
+                                                                pins = "GPIO3_P5";
                                                                input-enable;
                                                                bias-pull-down;
                                                        };
diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
index addfcc7c2750..5c5cea232743 100644
--- a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
+++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
@@ -18,33 +18,33 @@
                        uart0 {
                                uart0_default_mode: uart0_default {
                                        default_mux {
-                                                ste,function = "u0";
+                                                function = "u0";
-                                                ste,pins = "u0_a_1";
+                                                groups = "u0_a_1";
                                        };
                                        default_cfg1 {
-                                                ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
+                                                pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
                                                ste,config = <&in_pu>;
                                        };
                                        default_cfg2 {
-                                                ste,pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
+                                                pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
                                                ste,config = <&out_hi>;
                                        };
                                };
                                uart0_sleep_mode: uart0_sleep {
                                        sleep_cfg1 {
-                                                ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
+                                                pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
                                                ste,config = <&slpm_in_wkup_pdis>;
                                        };
                                        sleep_cfg2 {
-                                                ste,pins = "GPIO1_AJ3"; /* RTS */
+                                                pins = "GPIO1_AJ3"; /* RTS */
                                                ste,config = <&slpm_out_hi_wkup_pdis>;
                                        };
                                        sleep_cfg3 {
-                                                ste,pins = "GPIO3_AH3"; /* TXD */
+                                                pins = "GPIO3_AH3"; /* TXD */
                                                ste,config = <&slpm_out_wkup_pdis>;
                                        };
                                };
@@ -53,28 +53,28 @@
                        uart1 {
                                uart1_default_mode: uart1_default {
                                        default_mux {
-                                                ste,function = "u1";
+                                                function = "u1";
-                                                ste,pins = "u1rxtx_a_1";
+                                                groups = "u1rxtx_a_1";
                                        };
                                        default_cfg1 {
-                                                ste,pins = "GPIO4_AH6"; /* RXD */
+                                                pins = "GPIO4_AH6"; /* RXD */
                                                ste,config = <&in_pu>;
                                        };
                                        default_cfg2 {
-                                                ste,pins = "GPIO5_AG6"; /* TXD */
+                                                pins = "GPIO5_AG6"; /* TXD */
                                                ste,config = <&out_hi>;
                                        };
                                };
                                uart1_sleep_mode: uart1_sleep {
                                        sleep_cfg1 {
-                                                ste,pins = "GPIO4_AH6"; /* RXD */
+                                                pins = "GPIO4_AH6"; /* RXD */
                                                ste,config = <&slpm_in_wkup_pdis>;
                                        };
                                        sleep_cfg2 {
-                                                ste,pins = "GPIO5_AG6"; /* TXD */
+                                                pins = "GPIO5_AG6"; /* TXD */
                                                ste,config = <&slpm_out_wkup_pdis>;
                                        };
                                };
@@ -83,28 +83,28 @@
                        uart2 {
                                uart2_default_mode: uart2_default {
                                        default_mux {
-                                                ste,function = "u2";
+                                                function = "u2";
-                                                ste,pins = "u2rxtx_c_1";
+                                                groups = "u2rxtx_c_1";
                                        };
                                        default_cfg1 {
-                                                ste,pins = "GPIO29_W2"; /* RXD */
+                                                pins = "GPIO29_W2"; /* RXD */
                                                ste,config = <&in_pu>;
                                        };
                                        default_cfg2 {
-                                                ste,pins = "GPIO30_W3"; /* TXD */
+                                                pins = "GPIO30_W3"; /* TXD */
                                                ste,config = <&out_hi>;
                                        };
                                };
                                uart2_sleep_mode: uart2_sleep {
                                        sleep_cfg1 {
-                                                ste,pins = "GPIO29_W2"; /* RXD */
+                                                pins = "GPIO29_W2"; /* RXD */
                                                ste,config = <&in_wkup_pdis>;
                                        };
                                        sleep_cfg2 {
-                                                ste,pins = "GPIO30_W3"; /* TXD */
+                                                pins = "GPIO30_W3"; /* TXD */
                                                ste,config = <&out_wkup_pdis>;
                                        };
                                };
@@ -114,18 +114,18 @@
                        i2c0 {
                                i2c0_default_mode: i2c_default {
                                        default_mux {
-                                                ste,function = "i2c0";
+                                                function = "i2c0";
-                                                ste,pins = "i2c0_a_1";
+                                                groups = "i2c0_a_1";
                                        };
                                        default_cfg1 {
-                                                ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
+                                                pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
                                                ste,config = <&in_pu>;
                                        };
                                };
                                i2c0_sleep_mode: i2c_sleep {
                                        sleep_cfg1 {
-                                                ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
+                                                pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
                                                ste,config = <&slpm_in_wkup_pdis>;
                                        };
                                };
@@ -134,18 +134,18 @@
                        i2c1 {
                                i2c1_default_mode: i2c_default {
                                        default_mux {
-                                                ste,function = "i2c1";
+                                                function = "i2c1";
-                                                ste,pins = "i2c1_b_2";
+                                                groups = "i2c1_b_2";
                                        };
                                        default_cfg1 {
-                                                ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
+                                                pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
                                                ste,config = <&in_pu>;
                                        };
                                };
                                i2c1_sleep_mode: i2c_sleep {
                                        sleep_cfg1 {
-                                                ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
+                                                pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
                                                ste,config = <&slpm_in_wkup_pdis>;
                                        };
                                };
@@ -154,18 +154,18 @@
                        i2c2 {
                                i2c2_default_mode: i2c_default {
                                        default_mux {
-                                                ste,function = "i2c2";
+                                                function = "i2c2";
-                                                ste,pins = "i2c2_b_2";
+                                                groups = "i2c2_b_2";
                                        };
                                        default_cfg1 {
-                                                ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
+                                                pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
                                                ste,config = <&in_pu>;
                                        };
                                };
                                i2c2_sleep_mode: i2c_sleep {
                                        sleep_cfg1 {
-                                                ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
+                                                pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
                                                ste,config = <&slpm_in_wkup_pdis>;
                                        };
                                };
@@ -174,18 +174,18 @@
                        i2c3 {
                                i2c3_default_mode: i2c_default {
                                        default_mux {
-                                                ste,function = "i2c3";
+                                                function = "i2c3";
-                                                ste,pins = "i2c3_c_2";
+                                                groups = "i2c3_c_2";
                                        };
                                        default_cfg1 {
-                                                ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
+                                                pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
                                                ste,config = <&in_pu>;
                                        };
                                };
                                i2c3_sleep_mode: i2c_sleep {
                                        sleep_cfg1 {
-                                                ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
+                                                pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
                                                ste,config = <&slpm_in_wkup_pdis>;
                                        };
                                };
@@ -198,18 +198,18 @@
                        i2c4 {
                                i2c4_default_mode: i2c_default {
                                        default_mux {
-                                                ste,function = "i2c4";
+                                                function = "i2c4";
-                                                ste,pins = "i2c4_b_1";
+                                                groups = "i2c4_b_1";
                                        };
                                        default_cfg1 {
-                                                ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
+                                                pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
                                                ste,config = <&in_pu>;
                                        };
                                };
                                i2c4_sleep_mode: i2c_sleep {
                                        sleep_cfg1 {
-                                                ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
+                                                pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
                                                ste,config = <&slpm_in_wkup_pdis>;
                                        };
                                };
@@ -219,19 +219,19 @@
                        spi2 {
                                spi2_default_mode: spi_default {
                                        default_mux {
-                                                ste,function = "spi2";
+                                                function = "spi2";
-                                                ste,pins = "spi2_oc1_2";
+                                                groups = "spi2_oc1_2";
                                        };
                                        default_cfg1 {
-                                                ste,pins = "GPIO216_AG12"; /* FRM */
+                                                pins = "GPIO216_AG12"; /* FRM */
                                                ste,config = <&gpio_out_hi>;
                                        };
                                        default_cfg2 {
-                                                ste,pins = "GPIO218_AH11"; /* RXD */
+                                                pins = "GPIO218_AH11"; /* RXD */
                                                ste,config = <&in_pd>;
                                        };
                                        default_cfg3 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO215_AH13", /* TXD */
                                                "GPIO217_AH12"; /* CLK */
                                                ste,config = <&out_lo>;
@@ -245,32 +245,32 @@
                                         * as we do not state any muxing.
                                         */
                                        idle_cfg1 {
-                                                ste,pins = "GPIO218_AH11"; /* RXD */
+                                                pins = "GPIO218_AH11"; /* RXD */
                                                ste,config = <&slpm_in_pdis>;
                                        };
                                        idle_cfg2 {
-                                                ste,pins = "GPIO215_AH13"; /* TXD */
+                                                pins = "GPIO215_AH13"; /* TXD */
                                                ste,config = <&slpm_out_lo_pdis>;
                                        };
                                        idle_cfg3 {
-                                                ste,pins = "GPIO217_AH12"; /* CLK */
+                                                pins = "GPIO217_AH12"; /* CLK */
                                                ste,config = <&slpm_pdis>;
                                        };
                                };
                                spi2_sleep_mode: spi_sleep {
                                        sleep_cfg1 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO216_AG12", /* FRM */
                                                "GPIO218_AH11"; /* RXD */
                                                ste,config = <&slpm_in_wkup_pdis>;
                                        };
                                        sleep_cfg2 {
-                                                ste,pins = "GPIO215_AH13"; /* TXD */
+                                                pins = "GPIO215_AH13"; /* TXD */
                                                ste,config = <&slpm_out_lo_wkup_pdis>;
                                        };
                                        sleep_cfg3 {
-                                                ste,pins = "GPIO217_AH12"; /* CLK */
+                                                pins = "GPIO217_AH12"; /* CLK */
                                                ste,config = <&slpm_wkup_pdis>;
                                        };
                                };
@@ -281,26 +281,26 @@
                                /* This is the external SD card slot, 4 bits wide */
                                sdi0_default_mode: sdi0_default {
                                        default_mux {
-                                                ste,function = "mc0";
+                                                function = "mc0";
-                                                ste,pins = "mc0_a_1";
+                                                groups = "mc0_a_1";
                                        };
                                        default_cfg1 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO18_AC2", /* CMDDIR */
                                                "GPIO19_AC1", /* DAT0DIR */
                                                "GPIO20_AB4"; /* DAT2DIR */
                                                ste,config = <&out_hi>;
                                        };
                                        default_cfg2 {
-                                                ste,pins = "GPIO22_AA3"; /* FBCLK */
+                                                pins = "GPIO22_AA3"; /* FBCLK */
                                                ste,config = <&in_nopull>;
                                        };
                                        default_cfg3 {
-                                                ste,pins = "GPIO23_AA4"; /* CLK */
+                                                pins = "GPIO23_AA4"; /* CLK */
                                                ste,config = <&out_lo>;
                                        };
                                        default_cfg4 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO24_AB2", /* CMD */
                                                "GPIO25_Y4", /* DAT0 */
                                                "GPIO26_Y2", /* DAT1 */
@@ -312,14 +312,14 @@
                                sdi0_sleep_mode: sdi0_sleep {
                                        sleep_cfg1 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO18_AC2", /* CMDDIR */
                                                "GPIO19_AC1", /* DAT0DIR */
                                                "GPIO20_AB4"; /* DAT2DIR */
                                                ste,config = <&slpm_out_hi_wkup_pdis>;
                                        };
                                        sleep_cfg2 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO22_AA3", /* FBCLK */
                                                "GPIO24_AB2", /* CMD */
                                                "GPIO25_Y4", /* DAT0 */
@@ -329,7 +329,7 @@
                                                ste,config = <&slpm_in_wkup_pdis>;
                                        };
                                        sleep_cfg3 {
-                                                ste,pins = "GPIO23_AA4"; /* CLK */
+                                                pins = "GPIO23_AA4"; /* CLK */
                                                ste,config = <&slpm_out_lo_wkup_pdis>;
                                        };
                                };
@@ -339,19 +339,19 @@
                                /* This is the WLAN SDIO 4 bits wide */
                                sdi1_default_mode: sdi1_default {
                                        default_mux {
-                                                ste,function = "mc1";
+                                                function = "mc1";
-                                                ste,pins = "mc1_a_1";
+                                                groups = "mc1_a_1";
                                        };
                                        default_cfg1 {
-                                                ste,pins = "GPIO208_AH16"; /* CLK */
+                                                pins = "GPIO208_AH16"; /* CLK */
                                                ste,config = <&out_lo>;
                                        };
                                        default_cfg2 {
-                                                ste,pins = "GPIO209_AG15"; /* FBCLK */
+                                                pins = "GPIO209_AG15"; /* FBCLK */
                                                ste,config = <&in_nopull>;
                                        };
                                        default_cfg3 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO210_AJ15", /* CMD */
                                                "GPIO211_AG14", /* DAT0 */
                                                "GPIO212_AF13", /* DAT1 */
@@ -363,11 +363,11 @@
                                sdi1_sleep_mode: sdi1_sleep {
                                        sleep_cfg1 {
-                                                ste,pins = "GPIO208_AH16"; /* CLK */
+                                                pins = "GPIO208_AH16"; /* CLK */
                                                ste,config = <&slpm_out_lo_wkup_pdis>;
                                        };
                                        sleep_cfg2 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO209_AG15", /* FBCLK */
                                                "GPIO210_AJ15", /* CMD */
                                                "GPIO211_AG14", /* DAT0 */
@@ -383,19 +383,19 @@
                                /* This is the eMMC 8 bits wide, usually PoP eMMC */
                                sdi2_default_mode: sdi2_default {
                                        default_mux {
-                                                ste,function = "mc2";
+                                                function = "mc2";
-                                                ste,pins = "mc2_a_1";
+                                                groups = "mc2_a_1";
                                        };
                                        default_cfg1 {
-                                                ste,pins = "GPIO128_A5"; /* CLK */
+                                                pins = "GPIO128_A5"; /* CLK */
                                                ste,config = <&out_lo>;
                                        };
                                        default_cfg2 {
-                                                ste,pins = "GPIO130_C8"; /* FBCLK */
+                                                pins = "GPIO130_C8"; /* FBCLK */
                                                ste,config = <&in_nopull>;
                                        };
                                        default_cfg3 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO129_B4", /* CMD */
                                                "GPIO131_A12", /* DAT0 */
                                                "GPIO132_C10", /* DAT1 */
@@ -411,17 +411,17 @@
                                sdi2_sleep_mode: sdi2_sleep {
                                        sleep_cfg1 {
-                                                ste,pins = "GPIO128_A5"; /* CLK */
+                                                pins = "GPIO128_A5"; /* CLK */
                                                ste,config = <&out_lo_wkup_pdis>;
                                        };
                                        sleep_cfg2 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO130_C8", /* FBCLK */
                                                "GPIO129_B4"; /* CMD */
                                                ste,config = <&in_wkup_pdis_en>;
                                        };
                                        sleep_cfg3 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO131_A12", /* DAT0 */
                                                "GPIO132_C10", /* DAT1 */
                                                "GPIO133_B10", /* DAT2 */
@@ -439,19 +439,19 @@
                                /* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */
                                sdi4_default_mode: sdi4_default {
                                        default_mux {
-                                                ste,function = "mc4";
+                                                function = "mc4";
-                                                ste,pins = "mc4_a_1";
+                                                groups = "mc4_a_1";
                                        };
                                        default_cfg1 {
-                                                ste,pins = "GPIO203_AE23"; /* CLK */
+                                                pins = "GPIO203_AE23"; /* CLK */
                                                ste,config = <&out_lo>;
                                        };
                                        default_cfg2 {
-                                                ste,pins = "GPIO202_AF25"; /* FBCLK */
+                                                pins = "GPIO202_AF25"; /* FBCLK */
                                                ste,config = <&in_nopull>;
                                        };
                                        default_cfg3 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO201_AF24", /* CMD */
                                                "GPIO200_AH26", /* DAT0 */
                                                "GPIO199_AH23", /* DAT1 */
@@ -467,11 +467,11 @@
                                sdi4_sleep_mode: sdi4_sleep {
                                        sleep_cfg1 {
-                                                ste,pins = "GPIO203_AE23"; /* CLK */
+                                                pins = "GPIO203_AE23"; /* CLK */
                                                ste,config = <&out_lo_wkup_pdis>;
                                        };
                                        sleep_cfg2 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO202_AF25", /* FBCLK */
                                                "GPIO201_AF24", /* CMD */
                                                "GPIO200_AH26", /* DAT0 */
@@ -494,11 +494,11 @@
                        msp0 {
                                msp0_default_mode: msp0_default {
                                        default_msp0_mux {
-                                                ste,function = "msp0";
+                                                function = "msp0";
-                                                ste,pins = "msp0txrx_a_1", "msp0tfstck_a_1";
+                                                groups = "msp0txrx_a_1", "msp0tfstck_a_1";
                                        };
                                        default_msp0_cfg {
-                                                ste,pins =
+                                                pins =
                                                "GPIO12_AC4", /* TXD */
                                                "GPIO15_AC3", /* RXD */
                                                "GPIO13_AF3", /* TFS */
@@ -511,15 +511,15 @@
                        msp1 {
                                msp1_default_mode: msp1_default {
                                        default_mux {
-                                                ste,function = "msp1";
+                                                function = "msp1";
-                                                ste,pins = "msp1txrx_a_1", "msp1_a_1";
+                                                groups = "msp1txrx_a_1", "msp1_a_1";
                                        };
                                        default_cfg1 {
-                                                ste,pins = "GPIO33_AF2";
+                                                pins = "GPIO33_AF2";
                                                ste,config = <&out_lo>;
                                        };
                                        default_cfg2 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO34_AE1",
                                                "GPIO35_AE2",
                                                "GPIO36_AG2";
@@ -533,18 +533,18 @@
                                msp2_default_mode: msp2_default {
                                        /* MSP2 usually used for HDMI audio */
                                        default_mux {
-                                                ste,function = "msp2";
+                                                function = "msp2";
-                                                ste,pins = "msp2_a_1";
+                                                groups = "msp2_a_1";
                                        };
                                        default_cfg1 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO193_AH27", /* TXD */
                                                "GPIO194_AF27", /* TCK */
                                                "GPIO195_AG28"; /* TFS */
                                                ste,config = <&in_pd>;
                                        };
                                        default_cfg2 {
-                                                ste,pins = "GPIO196_AG26"; /* RXD */
+                                                pins = "GPIO196_AG26"; /* RXD */
                                                ste,config = <&out_lo>;
                                        };
                                };
@@ -554,11 +554,11 @@
                        musb {
                                musb_default_mode: musb_default {
                                        default_mux {
-                                                ste,function = "usb";
+                                                function = "usb";
-                                                ste,pins = "usb_a_1";
+                                                groups = "usb_a_1";
                                        };
                                        default_cfg1 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO256_AF28", /* NXT */
                                                "GPIO258_AD29", /* XCLK */
                                                "GPIO259_AC29", /* DIR */
@@ -573,25 +573,25 @@
                                                ste,config = <&in_nopull>;
                                        };
                                        default_cfg2 {
-                                                ste,pins = "GPIO257_AE29"; /* STP */
+                                                pins = "GPIO257_AE29"; /* STP */
                                                ste,config = <&out_hi>;
                                        };
                                };
                                musb_sleep_mode: musb_sleep {
                                        sleep_cfg1 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO256_AF28", /* NXT */
                                                "GPIO258_AD29", /* XCLK */
                                                "GPIO259_AC29"; /* DIR */
                                                ste,config = <&slpm_wkup_pdis_en>;
                                        };
                                        sleep_cfg2 {
-                                                ste,pins = "GPIO257_AE29"; /* STP */
+                                                pins = "GPIO257_AE29"; /* STP */
                                                ste,config = <&slpm_out_hi_wkup_pdis>;
                                        };
                                        sleep_cfg3 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO260_AD28", /* DAT7 */
                                                "GPIO261_AD26", /* DAT6 */
                                                "GPIO262_AE26", /* DAT5 */
@@ -609,8 +609,8 @@
                                lcd_default_mode: lcd_default {
                                        default_mux {
                                                /* Mux in VSI0 and all the data lines */
-                                                ste,function = "lcd";
+                                                function = "lcd";
-                                                ste,pins =
+                                                groups =
                                                "lcdvsi0_a_1", /* VSI0 for LCD */
                                                "lcd_d0_d7_a_1", /* Data lines */
                                                "lcd_d8_d11_a_1", /* TV-out */
@@ -618,7 +618,7 @@
                                                "lcdvsi1_a_1"; /* VSI1 for HDMI */
                                        };
                                        default_cfg1 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO68_E1", /* VSI0 */
                                                "GPIO69_E2"; /* VSI1 */
                                                ste,config = <&in_pu>;
@@ -626,7 +626,7 @@
                                };
                                lcd_sleep_mode: lcd_sleep {
                                        sleep_cfg1 {
-                                                ste,pins = "GPIO69_E2"; /* VSI1 */
+                                                pins = "GPIO69_E2"; /* VSI1 */
                                                ste,config = <&slpm_in_wkup_pdis>;
                                        };
                                };
@@ -636,11 +636,11 @@
                                /* SKE keys on position 2 in an 8x8 matrix */
                                ske_kpa2_default_mode: ske_kpa2_default {
                                        default_mux {
-                                                ste,function = "kp";
+                                                function = "kp";
-                                                ste,pins = "kp_a_2";
+                                                groups = "kp_a_2";
                                        };
                                        default_cfg1 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO153_B17", /* I7 */
                                                "GPIO154_C16", /* I6 */
                                                "GPIO155_C19", /* I5 */
@@ -652,7 +652,7 @@
                                                ste,config = <&in_pd>;
                                        };
                                        default_cfg2 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO157_A18", /* O7 */
                                                "GPIO158_C18", /* O6 */
                                                "GPIO159_B19", /* O5 */
@@ -666,7 +666,7 @@
                                };
                                ske_kpa2_sleep_mode: ske_kpa2_sleep {
                                        sleep_cfg1 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO153_B17", /* I7 */
                                                "GPIO154_C16", /* I6 */
                                                "GPIO155_C19", /* I5 */
@@ -678,7 +678,7 @@
                                                ste,config = <&slpm_in_pu_wkup_pdis_en>;
                                        };
                                        sleep_cfg2 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO157_A18", /* O7 */
                                                "GPIO158_C18", /* O6 */
                                                "GPIO159_B19", /* O5 */
@@ -696,11 +696,11 @@
                                 */
                                ske_kpaoc1_default_mode: ske_kpaoc1_default {
                                        default_mux {
-                                                ste,function = "kp";
+                                                function = "kp";
-                                                ste,pins = "kp_a_1", "kp_oc1_1";
+                                                groups = "kp_a_1", "kp_oc1_1";
                                        };
                                        default_cfg1 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO91_B6", /* KP_O0 */
                                                "GPIO90_A3", /* KP_O1 */
                                                "GPIO87_B3", /* KP_O2 */
@@ -710,7 +710,7 @@
                                                ste,config = <&out_lo>;
                                        };
                                        default_cfg2 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO93_B7", /* KP_I0 */
                                                "GPIO92_D6", /* KP_I1 */
                                                "GPIO89_E6", /* KP_I2 */
@@ -729,13 +729,13 @@
                                         * These are plain GPIO pins used by WLAN
                                         */
                                        default_cfg1 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO226_AF8", /* WLAN_PMU_EN */
                                                "GPIO85_D5"; /* WLAN_ENA */
                                                ste,config = <&gpio_out_lo>;
                                        };
                                        default_cfg2 {
-                                                ste,pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */
+                                                pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */
                                                ste,config = <&gpio_in_pu>;
                                        };
                                };
diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi
index 84d7c5d883f2..7d4f8184c522 100644
--- a/arch/arm/boot/dts/ste-href-stuib.dtsi
+++ b/arch/arm/boot/dts/ste-href-stuib.dtsi
@@ -103,7 +103,7 @@
                        prox {
                                prox_stuib_mode: prox_stuib {
                                        stuib_cfg {
-                                                ste,pins = "GPIO217_AH12";
+                                                pins = "GPIO217_AH12";
                                                ste,config = <&gpio_in_pu>;
                                        };
                                };
@@ -111,7 +111,7 @@
                        hall {
                                hall_stuib_mode: stuib_tvk {
                                        stuib_cfg {
-                                                ste,pins = "GPIO145_C13";
+                                                pins = "GPIO145_C13";
                                                ste,config = <&gpio_in_pu>;
                                        };
                                };
diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
index 18b65d1b14f2..062c6aae3afa 100644
--- a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
+++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
@@ -130,7 +130,7 @@
                        tc35893 {
                                tc35893_tvk_mode: tc35893_tvk {
                                        tvk_cfg {
-                                                ste,pins = "GPIO218_AH11";
+                                                pins = "GPIO218_AH11";
                                                ste,config = <&gpio_in_pu>;
                                        };
                                };
@@ -138,7 +138,7 @@
                        prox {
                                prox_tvk_mode: prox_tvk {
                                        tvk_cfg {
-                                                ste,pins = "GPIO217_AH12";
+                                                pins = "GPIO217_AH12";
                                                ste,config = <&gpio_in_pu>;
                                        };
                                };
@@ -146,7 +146,7 @@
                        hall {
                                hall_tvk_mode: hall_tvk {
                                        tvk_cfg {
-                                                ste,pins = "GPIO145_C13";
+                                                pins = "GPIO145_C13";
                                                ste,config = <&gpio_in_pu>;
                                        };
                                };
@@ -155,7 +155,7 @@
                                accel_tvk_mode: accel_tvk {
                                        /* Accelerometer interrupt lines 1 & 2 */
                                        tvk_cfg {
-                                                ste,pins = "GPIO82_C1", "GPIO83_D3";
+                                                pins = "GPIO82_C1", "GPIO83_D3";
                                                ste,config = <&gpio_in_pu>;
                                        };
                                };
@@ -164,11 +164,11 @@
                                magneto_tvk_mode: magneto_tvk {
                                        /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
                                        tvk_cfg1 {
-                                                ste,pins = "GPIO31_V3";
+                                                pins = "GPIO31_V3";
                                                ste,config = <&gpio_in_pu>;
                                        };
                                        tvk_cfg2 {
-                                                ste,pins = "GPIO32_V2";
+                                                pins = "GPIO32_V2";
                                                ste,config = <&gpio_in_pd>;
                                        };
                                };
diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi
index abc762e24fcb..7f3975b58d16 100644
--- a/arch/arm/boot/dts/ste-hrefprev60.dtsi
+++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi
@@ -79,11 +79,11 @@
                        ssp0 {
                                ssp0_hrefprev60_mode: ssp0_hrefprev60_default {
                                        hrefprev60_mux {
-                                                ste,function = "ssp0";
+                                                function = "ssp0";
-                                                ste,pins = "ssp0_a_1";
+                                                groups = "ssp0_a_1";
                                        };
                                        hrefprev60_cfg1 {
-                                                ste,pins = "GPIO145_C13"; /* RXD */
+                                                pins = "GPIO145_C13"; /* RXD */
                                                ste,config = <&in_pd>;
                                        };
@@ -93,11 +93,11 @@
                                /* This additional pin needed on early MOP500 and HREFs previous to v60 */
                                sdi0_default_mode: sdi0_default {
                                        hrefprev60_mux {
-                                                ste,function = "mc0";
+                                                function = "mc0";
-                                                ste,pins = "mc0dat31dir_a_1";
+                                                groups = "mc0dat31dir_a_1";
                                        };
                                        hrefprev60_cfg1 {
-                                                ste,pins = "GPIO21_AB3"; /* DAT31DIR */
+                                                pins = "GPIO21_AB3"; /* DAT31DIR */
                                                ste,config = <&out_hi>;
                                        };
@@ -106,7 +106,7 @@
                        tc35892 {
                                tc35892_hrefprev60_mode: tc35892_hrefprev60 {
                                        hrefprev60_cfg {
-                                                ste,pins = "GPIO217_AH12";
+                                                pins = "GPIO217_AH12";
                                                ste,config = <&gpio_in_pu>;
                                        };
                                };
@@ -114,11 +114,11 @@
                        ipgpio {
                                 ipgpio_hrefprev60_mode: ipgpio_hrefprev60 {
                                        hrefprev60_mux {
-                                                ste,function = "ipgpio";
+                                                function = "ipgpio";
-                                                ste,pins = "ipgpio0_c_1", "ipgpio1_c_1";
+                                                groups = "ipgpio0_c_1", "ipgpio1_c_1";
                                        };
                                        hrefprev60_cfg1 {
-                                                ste,pins = "GPIO6_AF6", "GPIO7_AG5";
+                                                pins = "GPIO6_AF6", "GPIO7_AG5";
                                                ste,config = <&in_pu>;
                                        };
                                 };
diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
index bcc1f0c37f49..a4bc9e77d640 100644
--- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi
+++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
@@ -49,7 +49,7 @@
                                /* SD card detect GPIO pin, extend default state */
                                sdi0_default_mode: sdi0_default {
                                        default_hrefv60_cfg1 {
-                                                ste,pins = "GPIO95_E8";
+                                                pins = "GPIO95_E8";
                                                ste,config = <&gpio_in_pu>;
                                        };
                                };
@@ -64,19 +64,19 @@
                                 */
                                ipgpio_hrefv60_mode: ipgpio_hrefv60 {
                                        hrefv60_mux {
-                                                ste,function = "ipgpio";
+                                                function = "ipgpio";
-                                                ste,pins = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1";
+                                                groups = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1";
                                        };
                                        hrefv60_cfg1 {
-                                                ste,pins = "GPIO6_AF6", "GPIO7_AG5";
+                                                pins = "GPIO6_AF6", "GPIO7_AG5";
                                                ste,config = <&in_pu>;
                                        };
                                        hrefv60_cfg2 {
-                                                ste,pins = "GPIO21_AB3";
+                                                pins = "GPIO21_AB3";
                                                ste,config = <&gpio_out_lo>;
                                        };
                                        hrefv60_cfg3 {
-                                                ste,pins = "GPIO64_F3";
+                                                pins = "GPIO64_F3";
                                                ste,config = <&out_lo>;
                                        };
                                };
@@ -89,7 +89,7 @@
                                 */
                                etm_hrefv60_mode: etm_hrefv60 {
                                        hrefv60_cfg1 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO70_G5",
                                                "GPIO71_G4",
                                                "GPIO72_H4",
@@ -103,11 +103,11 @@
                                nahj_hrefv60_mode: nahj_hrefv60 {
                                        /* NAHJ CTRL on GPIO76 to low, CTRL_INV on GPIO216 to high */
                                        hrefv60_cfg1 {
-                                                ste,pins = "GPIO76_J2";
+                                                pins = "GPIO76_J2";
                                                ste,config = <&gpio_out_lo>;
                                        };
                                        hrefv60_cfg2 {
-                                                ste,pins = "GPIO216_AG12";
+                                                pins = "GPIO216_AG12";
                                                ste,config = <&gpio_out_hi>;
                                        };
                                 };
@@ -116,13 +116,13 @@
                                nfc_hrefv60_mode: nfc_hrefv60 {
                                        /* NFC ENA and RESET to low, pulldown IRQ line */
                                        hrefv60_cfg1 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO77_H1", /* NFC_ENA */
                                                "GPIO142_C11"; /* NFC_RESET */
                                                ste,config = <&gpio_out_lo>;
                                        };
                                        hrefv60_cfg2 {
-                                                ste,pins = "GPIO144_B13"; /* NFC_IRQ */
+                                                pins = "GPIO144_B13"; /* NFC_IRQ */
                                                ste,config = <&gpio_in_pd>;
                                        };
                                 };
@@ -130,11 +130,11 @@
                        force {
                                force_hrefv60_mode: force_hrefv60 {
                                        hrefv60_cfg1 {
-                                                ste,pins = "GPIO91_B6"; /* FORCE_SENSING_INT */
+                                                pins = "GPIO91_B6"; /* FORCE_SENSING_INT */
                                                ste,config = <&gpio_in_pu>;
                                        };
                                        hrefv60_cfg2 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO92_D6", /* FORCE_SENSING_RST */
                                                "GPIO97_D9"; /* FORCE_SENSING_WU */
                                                ste,config = <&gpio_out_lo>;
@@ -144,7 +144,7 @@
                        dipro {
                                dipro_hrefv60_mode: dipro_hrefv60 {
                                        hrefv60_cfg1 {
-                                                ste,pins = "GPIO139_C9"; /* DIPRO_INT */
+                                                pins = "GPIO139_C9"; /* DIPRO_INT */
                                                ste,config = <&gpio_in_pu>;
                                        };
                                 };
@@ -153,7 +153,7 @@
                                vaudio_hf_hrefv60_mode: vaudio_hf_hrefv60 {
                                        /* Audio Amplifier HF enable GPIO */
                                        hrefv60_cfg1 {
-                                                ste,pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */
+                                                pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */
                                                ste,config = <&gpio_out_hi>;
                                        };
                                 };
@@ -165,7 +165,7 @@
                                         * pull low to reset state
                                         */
                                        hrefv60_cfg1 {
-                                                ste,pins = "GPIO171_D23"; /* GBF_ENA_RESET */
+                                                pins = "GPIO171_D23"; /* GBF_ENA_RESET */
                                                ste,config = <&gpio_out_lo>;
                                        };
                                 };
@@ -174,7 +174,7 @@
                                hdtv_hrefv60_mode: hdtv_hrefv60 {
                                        /* MSP : HDTV INTERFACE GPIO line */
                                        hrefv60_cfg1 {
-                                                ste,pins = "GPIO192_AJ27";
+                                                pins = "GPIO192_AJ27";
                                                ste,config = <&gpio_in_pd>;
                                        };
                                 };
@@ -187,11 +187,11 @@
                                         * reset signals low.
                                         */
                                        hrefv60_cfg1 {
-                                                ste,pins = "GPIO143_D12", "GPIO146_D13";
+                                                pins = "GPIO143_D12", "GPIO146_D13";
                                                ste,config = <&gpio_out_lo>;
                                        };
                                        hrefv60_cfg2 {
-                                                ste,pins = "GPIO67_G2";
+                                                pins = "GPIO67_G2";
                                                ste,config = <&gpio_in_pu>;
                                        };
                                };
@@ -204,11 +204,11 @@
                                         * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
                                         */
                                        hrefv60_cfg1 {
-                                                ste,pins ="GPIO65_F1";
+                                                pins ="GPIO65_F1";
                                                ste,config = <&gpio_out_hi>;
                                        };
                                        hrefv60_cfg2 {
-                                                ste,pins ="GPIO66_G3";
+                                                pins ="GPIO66_G3";
                                                ste,config = <&gpio_out_lo>;
                                        };
                                };
diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts
new file mode 100644
index 000000000000..a8c00ee7522a
--- /dev/null
+++ b/arch/arm/boot/dts/ste-nomadik-nhk15.dts
@@ -0,0 +1,151 @@
+/*
+ * Device Tree for the ST-Ericsson Nomadik S8815 board
+ * Produced by Calao Systems
+ */
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "ste-nomadik-stn8815.dtsi"
+/ {
+        model = "Nomadik STN8815NHK";
+        compatible = "st,nomadik-nhk-15";
+        chosen {
+                bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk";
+        };
+        aliases {
+                stmpe-i2c0 = &stmpe0;
+                stmpe-i2c1 = &stmpe1;
+        };
+        pinctrl {
+                stmpe2401_1 {
+                        stmpe2401_1_nhk_mode: stmpe2401_1_nhk {
+                                nhk_cfg1 {
+                                        ste,pins = "GPIO76_B20"; // IRQ line
+                                        ste,input = <0>;
+                                };
+                                nhk_cfg2 {
+                                        ste,pins = "GPIO77_B8"; // reset line
+                                        ste,output = <1>;
+                                };
+                        };
+                };
+                stmpe2401_2 {
+                        stmpe2401_2_nhk_mode: stmpe2401_2_nhk {
+                                nhk_cfg1 {
+                                        ste,pins = "GPIO78_A8"; // IRQ line
+                                        ste,input = <0>;
+                                };
+                                nhk_cfg2 {
+                                        ste,pins = "GPIO79_C9"; // reset line
+                                        ste,output = <1>;
+                                };
+                        };
+                };
+        };
+        src@101e0000 {
+                /* These chrystal outputs are not used on this board */
+                disable-sxtalo;
+                disable-mxtalo;
+        };
+        /* This is where the interrupt is routed on the NHK-15 debug board */
+        external-bus@34000000 {
+                compatible = "simple-bus";
+                reg = <0x34000000 0x1000000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0x34000000 0x1000000>;
+                ethernet@300 {
+                        compatible = "smsc,lan91c111";
+                        reg = <0x300 0x0fd00>;
+                        reg-io-width = <2>;
+                        reset-gpios = <&stmpe_gpio44 10 GPIO_ACTIVE_HIGH>;
+                        interrupt-parent = <&stmpe_gpio44>;
+                        interrupts = <11 IRQ_TYPE_EDGE_RISING>;
+                };
+        };
+        i2c0 {
+                stmpe0: stmpe2401@43 {
+                        compatible = "st,stmpe2401";
+                        reg = <0x43>;
+                        reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>; // GPIO77
+                        interrupts = <12 IRQ_TYPE_EDGE_FALLING>; // GPIO76
+                        interrupt-parent = <&gpio2>;
+                        interrupt-controller;
+                        wakeup-source;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&stmpe2401_1_nhk_mode>;
+                        stmpe_gpio43: stmpe_gpio {
+                                compatible = "st,stmpe-gpio";
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                /* Some pins in alternate functions */
+                                st,norequest-mask = <0xf0f002>;
+                        };
+                        stmpe_keypad {
+                                compatible = "st,stmpe-keypad";
+                                debounce-interval = <64>;
+                                st,scan-count = <8>;
+                                st,no-autorepeat;
+                                keypad,num-rows = <8>;
+                                keypad,num-columns = <8>;
+                                linux,keymap = <0x00020072 // Vol down
+                                                0x00030073 // Vol up
+                                                0x0100009e // Back
+                                                0x010100e3 // TV out
+                                                0x01020098 // Lock
+                                                0x0103013b // Start
+                                                0x020000a3 // Next
+                                                0x020100a4 // Play
+                                                0x020200a5 // Prev
+                                                0x02030160 // OK
+                                                0x03000069 // Left
+                                                0x0301006a // Right
+                                                0x03020067 // Up
+                                                0x0303006c>; // Down
+                        };
+                };
+                stmpe1: stmpe2401@44 {
+                        compatible = "st,stmpe2401";
+                        reg = <0x44>;
+                        reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; // GPIO79
+                        interrupts = <14 IRQ_TYPE_EDGE_FALLING>; // GPIO78
+                        interrupt-parent = <&gpio2>;
+                        interrupt-controller;
+                        wakeup-source;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&stmpe2401_2_nhk_mode>;
+                        stmpe_gpio44: stmpe_gpio {
+                                compatible = "st,stmpe-gpio";
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                };
+        };
+        amba {
+                mmcsd: sdi@101f6000 {
+                        cd-gpios = <&stmpe_gpio44 7 GPIO_ACTIVE_LOW>;
+                        wp-gpios = <&stmpe_gpio44 18 GPIO_ACTIVE_HIGH>;
+                };
+        };
+        /* Custom board node with GPIO pins to active etc */
+        usb-s8815 {
+                /* This will turn off SATA so that MMC/SD can thrive */
+                mmcsd-gpio {
+                        gpios = <&stmpe_gpio44 2 0x1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts
index 90d8b6c7a205..85d3b95dfdba 100644
--- a/arch/arm/boot/dts/ste-nomadik-s8815.dts
+++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts
@@ -4,6 +4,7 @@
 */
 /dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
 #include "ste-nomadik-stn8815.dtsi"
 / {
@@ -14,14 +15,6 @@
                bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk";
        };
-        /* This is where the interrupt is routed on the S8815 board */
-        external-bus@34000000 {
-                ethernet@300 {
-                        interrupt-parent = <&gpio3>;
-                        interrupts = <8 0x1>;
-                };
-        };
        src@101e0000 {
                /* These chrystal drivers are not used on this board */
                disable-sxtalo;
@@ -37,20 +30,28 @@
                        cd_default_mode: cd_default {
                                cd_default_cfg1 {
                                        /* CD input GPIO */
-                                        ste,pins = "GPIO111_H21";
+                                        pins = "GPIO111_H21";
                                        ste,input = <0>;
                                };
                                cd_default_cfg2 {
                                        /* CD GPIO biasing */
-                                        ste,pins = "GPIO112_J21";
+                                        pins = "GPIO112_J21";
                                        ste,output = <0>;
                                };
                        };
                };
+                gpioi2c {
+                        gpioi2c_default_mode: gpioi2c_default {
+                                gpioi2c_default_cfg {
+                                        pins = "GPIO73_C21", "GPIO74_C20";
+                                        ste,input = <0>;
+                                };
+                        };
+                };
                user-led {
                        user_led_default_mode: user_led_default {
                                user_led_default_cfg {
-                                        ste,pins = "GPIO2_C5";
+                                        pins = "GPIO2_C5";
                                        ste,output = <1>;
                                };
                        };
@@ -58,13 +59,52 @@
                user-button {
                        user_button_default_mode: user_button_default {
                                user_button_default_cfg {
-                                        ste,pins = "GPIO3_A4";
+                                        pins = "GPIO3_A4";
                                        ste,input = <0>;
                                };
                        };
                };
        };
+        /* Ethernet */
+        external-bus@34000000 {
+                compatible = "simple-bus";
+                reg = <0x34000000 0x1000000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0x34000000 0x1000000>;
+                ethernet@300 {
+                        compatible = "smsc,lan91c111";
+                        reg = <0x300 0x0fd00>;
+                        interrupt-parent = <&gpio3>;
+                        interrupts = <8 IRQ_TYPE_EDGE_RISING>;
+                };
+        };
+        /* GPIO I2C connected to the USB portions of the STw4811 only */
+        gpio-i2c {
+                compatible = "i2c-gpio";
+                gpios = <&gpio2 10 0>, /* sda */
+                        <&gpio2 9 0>; /* scl */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&gpioi2c_default_mode>;
+                stw4811@2d {
+                           compatible = "st,stw4811-usb";
+                           reg = <0x2d>;
+                };
+        };
+        /* Configure card detect for the uSD slot */
+        amba {
+                mmcsd: sdi@101f6000 {
+                        cd-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
+                };
+        };
        /* Custom board node with GPIO pins to active etc */
        usb-s8815 {
                /* This will bias the MMC/SD card detect line */
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
index dbcf521b017f..f182f6538e90 100644
--- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -100,41 +100,41 @@
                uart0 {
                        uart0_default_mux: uart0_mux {
                                u0_default_mux {
-                                        ste,function = "u0";
+                                        function = "u0";
-                                        ste,pins = "u0_a_1";
+                                        groups = "u0_a_1";
                                };
                        };
                };
                uart1 {
                        uart1_default_mux: uart1_mux {
                                u1_default_mux {
-                                        ste,function = "u1";
+                                        function = "u1";
-                                        ste,pins = "u1_a_1";
+                                        groups = "u1_a_1";
                                };
                        };
                };
                mmcsd {
                        mmcsd_default_mux: mmcsd_mux {
                                mmcsd_default_mux {
-                                        ste,function = "mmcsd";
+                                        function = "mmcsd";
-                                        ste,pins = "mmcsd_a_1";
+                                        groups = "mmcsd_a_1", "mmcsd_b_1";
                                };
                        };
                        mmcsd_default_mode: mmcsd_default {
                                mmcsd_default_cfg1 {
                                        /* MCCLK */
-                                        ste,pins = "GPIO8_B10";
+                                        pins = "GPIO8_B10";
                                        ste,output = <0>;
                                };
                                mmcsd_default_cfg2 {
-                                        /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR */
+                                        /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR, MCDATDIR2 */
-                                        ste,pins = "GPIO10_C11", "GPIO15_A12",
+                                        pins = "GPIO10_C11", "GPIO15_A12",
-                                        "GPIO16_C13";
+                                        "GPIO16_C13", "GPIO23_D15";
                                        ste,output = <1>;
                                };
                                mmcsd_default_cfg3 {
                                        /* MCCMD, MCDAT3-0, MCMSFBCLK */
-                                        ste,pins = "GPIO9_A10", "GPIO11_B11",
+                                        pins = "GPIO9_A10", "GPIO11_B11",
                                        "GPIO12_A11", "GPIO13_C12",
                                        "GPIO14_B12", "GPIO24_C15";
                                        ste,input = <1>;
@@ -144,13 +144,13 @@
                i2c0 {
                        i2c0_default_mux: i2c0_mux {
                                i2c0_default_mux {
-                                        ste,function = "i2c0";
+                                        function = "i2c0";
-                                        ste,pins = "i2c0_a_1";
+                                        groups = "i2c0_a_1";
                                };
                        };
                        i2c0_default_mode: i2c0_default {
                                i2c0_default_cfg {
-                                        ste,pins = "GPIO62_D3", "GPIO63_D2";
+                                        pins = "GPIO62_D3", "GPIO63_D2";
                                        ste,input = <0>;
                                };
                        };
@@ -158,21 +158,13 @@
                i2c1 {
                        i2c1_default_mux: i2c1_mux {
                                i2c1_default_mux {
-                                        ste,function = "i2c1";
+                                        function = "i2c1";
-                                        ste,pins = "i2c1_a_1";
+                                        groups = "i2c1_a_1";
                                };
                        };
                        i2c1_default_mode: i2c1_default {
                                i2c1_default_cfg {
-                                        ste,pins = "GPIO53_L4", "GPIO54_L3";
+                                        pins = "GPIO53_L4", "GPIO54_L3";
-                                        ste,input = <0>;
-                                };
-                        };
-                };
-                i2c2 {
-                        i2c2_default_mode: i2c2_default {
-                                i2c2_default_cfg {
-                                        ste,pins = "GPIO73_C21", "GPIO74_C20";
                                        ste,input = <0>;
                                };
                        };
@@ -182,8 +174,6 @@
        src: src@101e0000 {
                compatible = "stericsson,nomadik-src";
                reg = <0x101e0000 0x1000>;
-                disable-sxtalo;
-                disable-mxtalo;
                /*
                 * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz
@@ -683,18 +673,6 @@
                };
        };
-        external-bus@34000000 {
-                compatible = "simple-bus";
-                reg = <0x34000000 0x1000000>;
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges = <0 0x34000000 0x1000000>;
-                ethernet@300 {
-                        compatible = "smsc,lan91c111";
-                        reg = <0x300 0x0fd00>;
-                };
-        };
        /* I2C0 connected to the STw4811 power management chip */
        i2c0 {
                compatible = "st,nomadik-i2c", "arm,primecell";
@@ -749,22 +727,6 @@
                };
        };
-        /* I2C2 connected to the USB portions of the STw4811 only */
-        i2c2 {
-                compatible = "i2c-gpio";
-                gpios = <&gpio2 10 0>, /* sda */
-                        <&gpio2 9 0>; /* scl */
-                #address-cells = <1>;
-                #size-cells = <0>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c2_default_mode>;
-                stw4811@2d {
-                           compatible = "st,stw4811-usb";
-                           reg = <0x2d>;
-                };
-        };
        amba {
                compatible = "arm,amba-bus";
                #address-cells = <1>;
@@ -844,7 +806,6 @@
                        bus-width = <4>;
                        cap-mmc-highspeed;
                        cap-sd-highspeed;
-                        cd-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>;
                        vmmc-supply = <&vmmc_regulator>;
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index 3e97a669f15e..206826a855c0 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -404,17 +404,17 @@
                                 */
                                eth_snowball_mode: eth_snowball {
                                        snowball_mux {
-                                                ste,function = "sm";
+                                                function = "sm";
-                                                ste,pins = "sm_b_1";
+                                                groups = "sm_b_1";
                                        };
                                        /* LAN IRQ pin */
                                        snowball_cfg1 {
-                                                ste,pins = "GPIO140_B11";
+                                                pins = "GPIO140_B11";
                                                ste,config = <&in_nopull>;
                                        };
                                        /* LAN reset pin */
                                        snowball_cfg2 {
-                                                ste,pins = "GPIO141_C12";
+                                                pins = "GPIO141_C12";
                                                ste,config = <&gpio_out_hi>;
                                        };
@@ -423,11 +423,11 @@
                        sdi0 {
                                sdi0_default_mode: sdi0_default {
                                        snowball_mux {
-                                                ste,function = "mc0";
+                                                function = "mc0";
-                                                ste,pins = "mc0dat31dir_a_1";
+                                                groups = "mc0dat31dir_a_1";
                                        };
                                        snowball_cfg1 {
-                                                ste,pins = "GPIO21_AB3"; /* DAT31DIR */
+                                                pins = "GPIO21_AB3"; /* DAT31DIR */
                                                ste,config = <&out_hi>;
                                        };
@@ -436,19 +436,19 @@
                        ssp0 {
                                ssp0_snowball_mode: ssp0_snowball_default {
                                        snowball_mux {
-                                                ste,function = "ssp0";
+                                                function = "ssp0";
-                                                ste,pins = "ssp0_a_1";
+                                                groups = "ssp0_a_1";
                                        };
                                        snowball_cfg1 {
-                                                ste,pins = "GPIO144_B13"; /* FRM */
+                                                pins = "GPIO144_B13"; /* FRM */
                                                ste,config = <&gpio_out_hi>;
                                        };
                                        snowball_cfg2 {
-                                                ste,pins = "GPIO145_C13"; /* RXD */
+                                                pins = "GPIO145_C13"; /* RXD */
                                                ste,config = <&in_pd>;
                                        };
                                        snowball_cfg3 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO146_D13", /* TXD */
                                                "GPIO143_D12"; /* CLK */
                                                ste,config = <&out_lo>;
@@ -459,7 +459,7 @@
                        gpio_led {
                                gpioled_snowball_mode: gpioled_default {
                                        snowball_cfg1 {
-                                                ste,pins = "GPIO142_C11";
+                                                pins = "GPIO142_C11";
                                                ste,config = <&gpio_out_hi>;
                                        };
@@ -469,7 +469,7 @@
                                accel_snowball_mode: accel_snowball {
                                        /* Accelerometer lines */
                                        snowball_cfg1 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO163_C20", /* ACCEL_IRQ1 */
                                                "GPIO164_B21"; /* ACCEL_IRQ2 */
                                                ste,config = <&gpio_in_pu>;
@@ -479,7 +479,7 @@
                        magnetometer {
                                magneto_snowball_mode: magneto_snowball {
                                        snowball_cfg1 {
-                                                ste,pins = "GPIO165_C21"; /* MAG_DRDY */
+                                                pins = "GPIO165_C21"; /* MAG_DRDY */
                                                ste,config = <&gpio_in_pu>;
                                        };
                                };
@@ -491,7 +491,7 @@
                                         * pull low to reset state
                                         */
                                        snowball_cfg1 {
-                                                ste,pins = "GPIO171_D23"; /* GBF_ENA_RESET */
+                                                pins = "GPIO171_D23"; /* GBF_ENA_RESET */
                                                ste,config = <&gpio_out_lo>;
                                        };
                                 };
@@ -503,13 +503,13 @@
                                         * These are plain GPIO pins used by WLAN
                                         */
                                        snowball_cfg1 {
-                                                ste,pins =
+                                                pins =
                                                "GPIO161_D21", /* WLAN_PMU_EN */
                                                "GPIO215_AH13"; /* WLAN_ENA */
                                                ste,config = <&gpio_out_lo>;
                                        };
                                        snowball_cfg2 {
-                                                ste,pins = "GPIO216_AG12"; /* WLAN_IRQ */
+                                                pins = "GPIO216_AG12"; /* WLAN_IRQ */
                                                ste,config = <&gpio_in_pu>;
                                        };
                                };
diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts
index fe69f92e5f82..261d5e2c48d2 100644
--- a/arch/arm/boot/dts/stih407-b2120.dts
+++ b/arch/arm/boot/dts/stih407-b2120.dts
@@ -7,13 +7,15 @@
 * published by the Free Software Foundation.
 */
 /dts-v1/;
-#include "stih407.dtsi"
+#include "stih407-clock.dtsi"
+#include "stih407-family.dtsi"
+#include "stihxxx-b2120.dtsi"
 / {
        model = "STiH407 B2120";
        compatible = "st,stih407-b2120", "st,stih407";
        chosen {
-                bootargs = "console=ttyAS0,115200";
+                bootargs = "console=ttyAS0,115200 clk_ignore_unused";
                linux,stdout-path = &sbc_serial0;
        };
@@ -26,53 +28,4 @@
                ttyAS0 = &sbc_serial0;
        };
-        soc {
-                sbc_serial0: serial@9530000 {
-                        status = "okay";
-                };
-                leds {
-                        compatible = "gpio-leds";
-                        red {
-                                #gpio-cells = <2>;
-                                label = "Front Panel LED";
-                                gpios = <&pio4 1 0>;
-                                linux,default-trigger = "heartbeat";
-                        };
-                        green {
-                                #gpio-cells = <2>;
-                                gpios = <&pio1 3 0>;
-                                default-state = "off";
-                        };
-                };
-                i2c@9842000 {
-                        status = "okay";
-                };
-                i2c@9843000 {
-                        status = "okay";
-                };
-                i2c@9844000 {
-                        status = "okay";
-                };
-                i2c@9845000 {
-                        status = "okay";
-                };
-                i2c@9540000 {
-                        status = "okay";
-                };
-                /* SSC11 to HDMI */
-                i2c@9541000 {
-                        status = "okay";
-                        /* HDMI V1.3a supports Standard mode only */
-                        clock-frequency = <100000>;
-                        st,i2c-min-scl-pulse-width-us = <0>;
-                        st,i2c-min-sda-pulse-width-us = <5>;
-                };
-        };
 };
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi
index 800f46f009f3..e65744fc12ab 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -5,8 +5,13 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
+#include <dt-bindings/clock/stih407-clks.h>
 / {
        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
                /*
                 * Fixed 30MHz oscillator inputs to SoC
                 */
@@ -19,10 +24,59 @@
                /*
                 * ARM Peripheral clock for timers
                 */
-                arm_periph_clk: arm-periph-clk {
+                arm_periph_clk: clk-m-a9-periphs {
                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
+                        compatible = "fixed-factor-clock";
-                        clock-frequency = <600000000>;
+                        clocks = <&clk_m_a9>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                };
+                /*
+                 * A9 PLL.
+                 */
+                clockgen-a9@92b0000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x92b0000 0xffff>;
+                        clockgen_a9_pll: clockgen-a9-pll {
+                                #clock-cells = <1>;
+                                compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clockgen-a9-pll-odf";
+                        };
+                };
+                /*
+                 * ARM CPU related clocks.
+                 */
+                clk_m_a9: clk-m-a9@92b0000 {
+                        #clock-cells = <0>;
+                        compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
+                        reg = <0x92b0000 0x10000>;
+                        clocks = <&clockgen_a9_pll 0>,
+                                 <&clockgen_a9_pll 0>,
+                                 <&clk_s_c0_flexgen 13>,
+                                 <&clk_m_a9_ext2f_div2>;
+                };
+                /*
+                 * ARM Peripheral clock for timers
+                 */
+                clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clocks = <&clk_s_c0_flexgen 13>;
+                        clock-output-names = "clk-m-a9-ext2f-div2";
+                        clock-div = <2>;
+                        clock-mult = <1>;
                };
                /*
@@ -35,5 +89,238 @@
                        clock-frequency = <200000000>;
                        clock-output-names = "clk-s-icn-reg-0";
                };
+                clockgen-a@090ff000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x90ff000 0x1000>;
+                        clk_s_a0_pll: clk-s-a0-pll {
+                                #clock-cells = <1>;
+                                compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-s-a0-pll-ofd-0";
+                        };
+                        clk_s_a0_flexgen: clk-s-a0-flexgen {
+                                compatible = "st,flexgen";
+                                #clock-cells = <1>;
+                                clocks = <&clk_s_a0_pll 0>,
+                                         <&clk_sysin>;
+                                clock-output-names = "clk-ic-lmi0";
+                        };
+                };
+                clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
+                        #clock-cells = <1>;
+                        compatible = "st,stih407-quadfs660-C", "st,quadfs";
+                        reg = <0x9103000 0x1000>;
+                        clocks = <&clk_sysin>;
+                        clock-output-names = "clk-s-c0-fs0-ch0",
+                                             "clk-s-c0-fs0-ch1",
+                                             "clk-s-c0-fs0-ch2",
+                                             "clk-s-c0-fs0-ch3";
+                };
+                clk_s_c0: clockgen-c@09103000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x9103000 0x1000>;
+                        clk_s_c0_pll0: clk-s-c0-pll0 {
+                                #clock-cells = <1>;
+                                compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-s-c0-pll0-odf-0";
+                        };
+                        clk_s_c0_pll1: clk-s-c0-pll1 {
+                                #clock-cells = <1>;
+                                compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-s-c0-pll1-odf-0";
+                        };
+                        clk_s_c0_flexgen: clk-s-c0-flexgen {
+                                #clock-cells = <1>;
+                                compatible = "st,flexgen";
+                                clocks = <&clk_s_c0_pll0 0>,
+                                         <&clk_s_c0_pll1 0>,
+                                         <&clk_s_c0_quadfs 0>,
+                                         <&clk_s_c0_quadfs 1>,
+                                         <&clk_s_c0_quadfs 2>,
+                                         <&clk_s_c0_quadfs 3>,
+                                         <&clk_sysin>;
+                                clock-output-names = "clk-icn-gpu",
+                                                     "clk-fdma",
+                                                     "clk-nand",
+                                                     "clk-hva",
+                                                     "clk-proc-stfe",
+                                                     "clk-proc-tp",
+                                                     "clk-rx-icn-dmu",
+                                                     "clk-rx-icn-hva",
+                                                     "clk-icn-cpu",
+                                                     "clk-tx-icn-dmu",
+                                                     "clk-mmc-0",
+                                                     "clk-mmc-1",
+                                                     "clk-jpegdec",
+                                                     "clk-ext2fa9",
+                                                     "clk-ic-bdisp-0",
+                                                     "clk-ic-bdisp-1",
+                                                     "clk-pp-dmu",
+                                                     "clk-vid-dmu",
+                                                     "clk-dss-lpc",
+                                                     "clk-st231-aud-0",
+                                                     "clk-st231-gp-1",
+                                                     "clk-st231-dmu",
+                                                     "clk-icn-lmi",
+                                                     "clk-tx-icn-disp-1",
+                                                     "clk-icn-sbc",
+                                                     "clk-stfe-frc2",
+                                                     "clk-eth-phy",
+                                                     "clk-eth-ref-phyclk",
+                                                     "clk-flash-promip",
+                                                     "clk-main-disp",
+                                                     "clk-aux-disp",
+                                                     "clk-compo-dvp";
+                        };
+                };
+                clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
+                        #clock-cells = <1>;
+                        compatible = "st,stih407-quadfs660-D", "st,quadfs";
+                        reg = <0x9104000 0x1000>;
+                        clocks = <&clk_sysin>;
+                        clock-output-names = "clk-s-d0-fs0-ch0",
+                                             "clk-s-d0-fs0-ch1",
+                                             "clk-s-d0-fs0-ch2",
+                                             "clk-s-d0-fs0-ch3";
+                };
+                clockgen-d0@09104000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x9104000 0x1000>;
+                        clk_s_d0_flexgen: clk-s-d0-flexgen {
+                                #clock-cells = <1>;
+                                compatible = "st,flexgen";
+                                clocks = <&clk_s_d0_quadfs 0>,
+                                         <&clk_s_d0_quadfs 1>,
+                                         <&clk_s_d0_quadfs 2>,
+                                         <&clk_s_d0_quadfs 3>,
+                                         <&clk_sysin>;
+                                clock-output-names = "clk-pcm-0",
+                                                     "clk-pcm-1",
+                                                     "clk-pcm-2",
+                                                     "clk-spdiff";
+                        };
+                };
+                clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
+                        #clock-cells = <1>;
+                        compatible = "st,stih407-quadfs660-D", "st,quadfs";
+                        reg = <0x9106000 0x1000>;
+                        clocks = <&clk_sysin>;
+                        clock-output-names = "clk-s-d2-fs0-ch0",
+                                             "clk-s-d2-fs0-ch1",
+                                             "clk-s-d2-fs0-ch2",
+                                             "clk-s-d2-fs0-ch3";
+                };
+                clk_tmdsout_hdmi: clk-tmdsout-hdmi {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <0>;
+                };
+                clockgen-d2@x9106000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x9106000 0x1000>;
+                        clk_s_d2_flexgen: clk-s-d2-flexgen {
+                                #clock-cells = <1>;
+                                compatible = "st,flexgen";
+                                clocks = <&clk_s_d2_quadfs 0>,
+                                         <&clk_s_d2_quadfs 1>,
+                                         <&clk_s_d2_quadfs 2>,
+                                         <&clk_s_d2_quadfs 3>,
+                                         <&clk_sysin>,
+                                         <&clk_sysin>,
+                                         <&clk_tmdsout_hdmi>;
+                                clock-output-names = "clk-pix-main-disp",
+                                                     "clk-pix-pip",
+                                                     "clk-pix-gdp1",
+                                                     "clk-pix-gdp2",
+                                                     "clk-pix-gdp3",
+                                                     "clk-pix-gdp4",
+                                                     "clk-pix-aux-disp",
+                                                     "clk-denc",
+                                                     "clk-pix-hddac",
+                                                     "clk-hddac",
+                                                     "clk-sddac",
+                                                     "clk-pix-dvo",
+                                                     "clk-dvo",
+                                                     "clk-pix-hdmi",
+                                                     "clk-tmds-hdmi",
+                                                     "clk-ref-hdmiphy";
+                                                     };
+                };
+                clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
+                        #clock-cells = <1>;
+                        compatible = "st,stih407-quadfs660-D", "st,quadfs";
+                        reg = <0x9107000 0x1000>;
+                        clocks = <&clk_sysin>;
+                        clock-output-names = "clk-s-d3-fs0-ch0",
+                                             "clk-s-d3-fs0-ch1",
+                                             "clk-s-d3-fs0-ch2",
+                                             "clk-s-d3-fs0-ch3";
+                };
+                clockgen-d3@9107000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x9107000 0x1000>;
+                        clk_s_d3_flexgen: clk-s-d3-flexgen {
+                                #clock-cells = <1>;
+                                compatible = "st,flexgen";
+                                clocks = <&clk_s_d3_quadfs 0>,
+                                         <&clk_s_d3_quadfs 1>,
+                                         <&clk_s_d3_quadfs 2>,
+                                         <&clk_s_d3_quadfs 3>,
+                                         <&clk_sysin>;
+                                clock-output-names = "clk-stfe-frc1",
+                                                     "clk-tsout-0",
+                                                     "clk-tsout-1",
+                                                     "clk-mchi",
+                                                     "clk-vsens-compo",
+                                                     "clk-frc1-remote",
+                                                     "clk-lpc-0",
+                                                     "clk-lpc-1";
+                        };
+                };
        };
 };
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 4f9024f19866..3e31d32133b8 100644
--- a/arch/arm/boot/dts/stih407.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -6,8 +6,8 @@
 * it under the terms of the GNU General Public License version 2 as
 * publishhed by the Free Software Foundation.
 */
-#include "stih407-clock.dtsi"
 #include "stih407-pinctrl.dtsi"
+#include <dt-bindings/reset-controller/stih407-resets.h>
 / {
        #address-cells = <1>;
        #size-cells = <1>;
@@ -63,6 +63,21 @@
                ranges;
                compatible = "simple-bus";
+                powerdown: powerdown-controller {
+                        compatible = "st,stih407-powerdown";
+                        #reset-cells = <1>;
+                };
+                softreset: softreset-controller {
+                        compatible = "st,stih407-softreset";
+                        #reset-cells = <1>;
+                };
+                picophyreset: picophyreset-controller {
+                        compatible = "st,stih407-picophyreset";
+                        #reset-cells = <1>;
+                };
                syscfg_sbc: sbc-syscfg@9620000 {
                        compatible = "st,stih407-sbc-syscfg", "syscon";
                        reg = <0x9620000 0x1000>;
@@ -104,7 +119,7 @@
                        interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_serial0>;
-                        clocks = <&clk_ext2f_a9>;
+                        clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                        status = "disabled";
                };
@@ -115,7 +130,7 @@
                        interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_serial1>;
-                        clocks = <&clk_ext2f_a9>;
+                        clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                        status = "disabled";
                };
@@ -126,7 +141,7 @@
                        interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_serial2>;
-                        clocks = <&clk_ext2f_a9>;
+                        clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                        status = "disabled";
                };
@@ -158,7 +173,7 @@
                        compatible = "st,comms-ssc4-i2c";
                        interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
                        reg = <0x9840000 0x110>;
-                        clocks = <&clk_ext2f_a9>;
+                        clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                        clock-names = "ssc";
                        clock-frequency = <400000>;
                        pinctrl-names = "default";
@@ -171,7 +186,7 @@
                        compatible = "st,comms-ssc4-i2c";
                        reg = <0x9841000 0x110>;
                        interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&clk_ext2f_a9>;
+                        clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                        clock-names = "ssc";
                        clock-frequency = <400000>;
                        pinctrl-names = "default";
@@ -184,7 +199,7 @@
                        compatible = "st,comms-ssc4-i2c";
                        reg = <0x9842000 0x110>;
                        interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&clk_ext2f_a9>;
+                        clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                        clock-names = "ssc";
                        clock-frequency = <400000>;
                        pinctrl-names = "default";
@@ -197,7 +212,7 @@
                        compatible = "st,comms-ssc4-i2c";
                        reg = <0x9843000 0x110>;
                        interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&clk_ext2f_a9>;
+                        clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                        clock-names = "ssc";
                        clock-frequency = <400000>;
                        pinctrl-names = "default";
@@ -210,7 +225,7 @@
                        compatible = "st,comms-ssc4-i2c";
                        reg = <0x9844000 0x110>;
                        interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&clk_ext2f_a9>;
+                        clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                        clock-names = "ssc";
                        clock-frequency = <400000>;
                        pinctrl-names = "default";
@@ -223,7 +238,7 @@
                        compatible = "st,comms-ssc4-i2c";
                        reg = <0x9845000 0x110>;
                        interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&clk_ext2f_a9>;
+                        clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                        clock-names = "ssc";
                        clock-frequency = <400000>;
                        pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts
new file mode 100644
index 000000000000..2f61a9960dee
--- /dev/null
+++ b/arch/arm/boot/dts/stih410-b2120.dts
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics (R&D) Limited.
+ * Author: Peter Griffin <peter.griffin@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "stih410.dtsi"
+#include "stihxxx-b2120.dtsi"
+/ {
+        model = "STiH410 B2120";
+        compatible = "st,stih410-b2120", "st,stih410";
+        chosen {
+                bootargs = "console=ttyAS0,115200 clk_ignore_unused";
+                linux,stdout-path = &sbc_serial0;
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x40000000 0x80000000>;
+        };
+        aliases {
+                ttyAS0 = &sbc_serial0;
+        };
+};
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi
new file mode 100644
index 000000000000..6b5803a30096
--- /dev/null
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -0,0 +1,338 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics R&D Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <dt-bindings/clock/stih410-clks.h>
+/ {
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                compatible = "st,stih410-clk", "simple-bus";
+                /*
+                 * Fixed 30MHz oscillator inputs to SoC
+                 */
+                clk_sysin: clk-sysin {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <30000000>;
+                        clock-output-names = "CLK_SYSIN";
+                };
+                /*
+                 * ARM Peripheral clock for timers
+                 */
+                arm_periph_clk: clk-m-a9-periphs {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clocks = <&clk_m_a9>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                };
+                /*
+                 * A9 PLL.
+                 */
+                clockgen-a9@92b0000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x92b0000 0xffff>;
+                        clockgen_a9_pll: clockgen-a9-pll {
+                                #clock-cells = <1>;
+                                compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clockgen-a9-pll-odf";
+                        };
+                };
+                /*
+                 * ARM CPU related clocks.
+                 */
+                clk_m_a9: clk-m-a9@92b0000 {
+                        #clock-cells = <0>;
+                        compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
+                        reg = <0x92b0000 0x10000>;
+                        clocks = <&clockgen_a9_pll 0>,
+                                 <&clockgen_a9_pll 0>,
+                                 <&clk_s_c0_flexgen 13>,
+                                 <&clk_m_a9_ext2f_div2>;
+                };
+                /*
+                 * ARM Peripheral clock for timers
+                 */
+                clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clocks = <&clk_s_c0_flexgen 13>;
+                        clock-output-names = "clk-m-a9-ext2f-div2";
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                };
+                /*
+                 * Bootloader initialized system infrastructure clock for
+                 * serial devices.
+                 */
+                clk_ext2f_a9: clockgen-c0@13 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <200000000>;
+                        clock-output-names = "clk-s-icn-reg-0";
+                };
+                clockgen-a@090ff000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x90ff000 0x1000>;
+                        clk_s_a0_pll: clk-s-a0-pll {
+                                #clock-cells = <1>;
+                                compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-s-a0-pll-ofd-0";
+                        };
+                        clk_s_a0_flexgen: clk-s-a0-flexgen {
+                                compatible = "st,flexgen";
+                                #clock-cells = <1>;
+                                clocks = <&clk_s_a0_pll 0>,
+                                         <&clk_sysin>;
+                                clock-output-names = "clk-ic-lmi0",
+                                                     "clk-ic-lmi1";
+                        };
+                };
+                clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
+                        #clock-cells = <1>;
+                        compatible = "st,stih407-quadfs660-C", "st,quadfs";
+                        reg = <0x9103000 0x1000>;
+                        clocks = <&clk_sysin>;
+                        clock-output-names = "clk-s-c0-fs0-ch0",
+                                             "clk-s-c0-fs0-ch1",
+                                             "clk-s-c0-fs0-ch2",
+                                             "clk-s-c0-fs0-ch3";
+                };
+                clk_s_c0: clockgen-c@09103000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x9103000 0x1000>;
+                        clk_s_c0_pll0: clk-s-c0-pll0 {
+                                #clock-cells = <1>;
+                                compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-s-c0-pll0-odf-0";
+                        };
+                        clk_s_c0_pll1: clk-s-c0-pll1 {
+                                #clock-cells = <1>;
+                                compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-s-c0-pll1-odf-0";
+                        };
+                        clk_s_c0_flexgen: clk-s-c0-flexgen {
+                                #clock-cells = <1>;
+                                compatible = "st,flexgen";
+                                clocks = <&clk_s_c0_pll0 0>,
+                                         <&clk_s_c0_pll1 0>,
+                                         <&clk_s_c0_quadfs 0>,
+                                         <&clk_s_c0_quadfs 1>,
+                                         <&clk_s_c0_quadfs 2>,
+                                         <&clk_s_c0_quadfs 3>,
+                                         <&clk_sysin>;
+                                clock-output-names = "clk-icn-gpu",
+                                                     "clk-fdma",
+                                                     "clk-nand",
+                                                     "clk-hva",
+                                                     "clk-proc-stfe",
+                                                     "clk-proc-tp",
+                                                     "clk-rx-icn-dmu",
+                                                     "clk-rx-icn-hva",
+                                                     "clk-icn-cpu",
+                                                     "clk-tx-icn-dmu",
+                                                     "clk-mmc-0",
+                                                     "clk-mmc-1",
+                                                     "clk-jpegdec",
+                                                     "clk-ext2fa9",
+                                                     "clk-ic-bdisp-0",
+                                                     "clk-ic-bdisp-1",
+                                                     "clk-pp-dmu",
+                                                     "clk-vid-dmu",
+                                                     "clk-dss-lpc",
+                                                     "clk-st231-aud-0",
+                                                     "clk-st231-gp-1",
+                                                     "clk-st231-dmu",
+                                                     "clk-icn-lmi",
+                                                     "clk-tx-icn-disp-1",
+                                                     "clk-icn-sbc",
+                                                     "clk-stfe-frc2",
+                                                     "clk-eth-phy",
+                                                     "clk-eth-ref-phyclk",
+                                                     "clk-flash-promip",
+                                                     "clk-main-disp",
+                                                     "clk-aux-disp",
+                                                     "clk-compo-dvp",
+                                                     "clk-tx-icn-hades",
+                                                     "clk-rx-icn-hades",
+                                                     "clk-icn-reg-16",
+                                                     "clk-pp-hades",
+                                                     "clk-clust-hades",
+                                                     "clk-hwpe-hades",
+                                                     "clk-fc-hades";
+                        };
+                };
+                clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
+                        #clock-cells = <1>;
+                        compatible = "st,stih407-quadfs660-D", "st,quadfs";
+                        reg = <0x9104000 0x1000>;
+                        clocks = <&clk_sysin>;
+                        clock-output-names = "clk-s-d0-fs0-ch0",
+                                             "clk-s-d0-fs0-ch1",
+                                             "clk-s-d0-fs0-ch2",
+                                             "clk-s-d0-fs0-ch3";
+                };
+                clockgen-d0@09104000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x9104000 0x1000>;
+                        clk_s_d0_flexgen: clk-s-d0-flexgen {
+                                #clock-cells = <1>;
+                                compatible = "st,flexgen";
+                                clocks = <&clk_s_d0_quadfs 0>,
+                                         <&clk_s_d0_quadfs 1>,
+                                         <&clk_s_d0_quadfs 2>,
+                                         <&clk_s_d0_quadfs 3>,
+                                         <&clk_sysin>;
+                                clock-output-names = "clk-pcm-0",
+                                                     "clk-pcm-1",
+                                                     "clk-pcm-2",
+                                                     "clk-spdiff",
+                                                     "clk-pcmr10-master",
+                                                     "clk-usb2-phy";
+                        };
+                };
+                clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
+                        #clock-cells = <1>;
+                        compatible = "st,stih407-quadfs660-D", "st,quadfs";
+                        reg = <0x9106000 0x1000>;
+                        clocks = <&clk_sysin>;
+                        clock-output-names = "clk-s-d2-fs0-ch0",
+                                             "clk-s-d2-fs0-ch1",
+                                             "clk-s-d2-fs0-ch2",
+                                             "clk-s-d2-fs0-ch3";
+                };
+                clk_tmdsout_hdmi: clk-tmdsout-hdmi {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <0>;
+                };
+                clockgen-d2@x9106000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x9106000 0x1000>;
+                        clk_s_d2_flexgen: clk-s-d2-flexgen {
+                                #clock-cells = <1>;
+                                compatible = "st,flexgen";
+                                clocks = <&clk_s_d2_quadfs 0>,
+                                         <&clk_s_d2_quadfs 1>,
+                                         <&clk_s_d2_quadfs 2>,
+                                         <&clk_s_d2_quadfs 3>,
+                                         <&clk_sysin>,
+                                         <&clk_sysin>,
+                                         <&clk_tmdsout_hdmi>;
+                                clock-output-names = "clk-pix-main-disp",
+                                                     "clk-pix-pip",
+                                                     "clk-pix-gdp1",
+                                                     "clk-pix-gdp2",
+                                                     "clk-pix-gdp3",
+                                                     "clk-pix-gdp4",
+                                                     "clk-pix-aux-disp",
+                                                     "clk-denc",
+                                                     "clk-pix-hddac",
+                                                     "clk-hddac",
+                                                     "clk-sddac",
+                                                     "clk-pix-dvo",
+                                                     "clk-dvo",
+                                                     "clk-pix-hdmi",
+                                                     "clk-tmds-hdmi",
+                                                     "clk-ref-hdmiphy";
+                                                     };
+                };
+                clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
+                        #clock-cells = <1>;
+                        compatible = "st,stih407-quadfs660-D", "st,quadfs";
+                        reg = <0x9107000 0x1000>;
+                        clocks = <&clk_sysin>;
+                        clock-output-names = "clk-s-d3-fs0-ch0",
+                                             "clk-s-d3-fs0-ch1",
+                                             "clk-s-d3-fs0-ch2",
+                                             "clk-s-d3-fs0-ch3";
+                };
+                clockgen-d3@9107000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x9107000 0x1000>;
+                        clk_s_d3_flexgen: clk-s-d3-flexgen {
+                                #clock-cells = <1>;
+                                compatible = "st,flexgen";
+                                clocks = <&clk_s_d3_quadfs 0>,
+                                         <&clk_s_d3_quadfs 1>,
+                                         <&clk_s_d3_quadfs 2>,
+                                         <&clk_s_d3_quadfs 3>,
+                                         <&clk_sysin>;
+                                clock-output-names = "clk-stfe-frc1",
+                                                     "clk-tsout-0",
+                                                     "clk-tsout-1",
+                                                     "clk-mchi",
+                                                     "clk-vsens-compo",
+                                                     "clk-frc1-remote",
+                                                     "clk-lpc-0",
+                                                     "clk-lpc-1";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih410-pinctrl.dtsi b/arch/arm/boot/dts/stih410-pinctrl.dtsi
new file mode 100644
index 000000000000..b3e9dfc81c07
--- /dev/null
+++ b/arch/arm/boot/dts/stih410-pinctrl.dtsi
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics Limited.
+ * Author: Peter Griffin <peter.griffin@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "st-pincfg.h"
+/ {
+        soc {
+                pin-controller-rear {
+                        usb0 {
+                                pinctrl_usb0: usb2-0 {
+                                        st,pins {
+                                                usb-oc-detect = <&pio35 0 ALT1 IN>;
+                                                usb-pwr-enable = <&pio35 1 ALT1 OUT>;
+                                        };
+                                };
+                        };
+                        usb1 {
+                                pinctrl_usb1: usb2-1 {
+                                        st,pins {
+                                                usb-oc-detect = <&pio35 2 ALT1 IN>;
+                                                usb-pwr-enable = <&pio35 3 ALT1 OUT>;
+                                        };
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
new file mode 100644
index 000000000000..c05627eb717d
--- /dev/null
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics Limited.
+ * Author: Peter Griffin <peter.griffin@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "stih410-clock.dtsi"
+#include "stih407-family.dtsi"
+#include "stih410-pinctrl.dtsi"
+/ {
+};
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
index 8509a037ae21..3791ad95dbaf 100644
--- a/arch/arm/boot/dts/stih415-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -11,33 +11,33 @@
 / {
        aliases {
-                gpio0   = &PIO0;
+                gpio0   = &pio0;
-                gpio1   = &PIO1;
+                gpio1   = &pio1;
-                gpio2   = &PIO2;
+                gpio2   = &pio2;
-                gpio3   = &PIO3;
+                gpio3   = &pio3;
-                gpio4   = &PIO4;
+                gpio4   = &pio4;
-                gpio5   = &PIO5;
+                gpio5   = &pio5;
-                gpio6   = &PIO6;
+                gpio6   = &pio6;
-                gpio7   = &PIO7;
+                gpio7   = &pio7;
-                gpio8   = &PIO8;
+                gpio8   = &pio8;
-                gpio9   = &PIO9;
+                gpio9   = &pio9;
-                gpio10  = &PIO10;
+                gpio10  = &pio10;
-                gpio11  = &PIO11;
+                gpio11  = &pio11;
-                gpio12  = &PIO12;
+                gpio12  = &pio12;
-                gpio13  = &PIO13;
+                gpio13  = &pio13;
-                gpio14  = &PIO14;
+                gpio14  = &pio14;
-                gpio15  = &PIO15;
+                gpio15  = &pio15;
-                gpio16  = &PIO16;
+                gpio16  = &pio16;
-                gpio17  = &PIO17;
+                gpio17  = &pio17;
-                gpio18  = &PIO18;
+                gpio18  = &pio18;
-                gpio19  = &PIO100;
+                gpio19  = &pio100;
-                gpio20  = &PIO101;
+                gpio20  = &pio101;
-                gpio21  = &PIO102;
+                gpio21  = &pio102;
-                gpio22  = &PIO103;
+                gpio22  = &pio103;
-                gpio23  = &PIO104;
+                gpio23  = &pio104;
-                gpio24  = &PIO105;
+                gpio24  = &pio105;
-                gpio25  = &PIO106;
+                gpio25  = &pio106;
-                gpio26  = &PIO107;
+                gpio26  = &pio107;
        };
        soc {
@@ -52,7 +52,7 @@
                        interrupt-names = "irqmux";
                        ranges          = <0 0xfe610000 0x5000>;
-                        PIO0: gpio@fe610000 {
+                        pio0: gpio@fe610000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -60,7 +60,7 @@
                                reg             = <0 0x100>;
                                st,bank-name    = "PIO0";
                        };
-                        PIO1: gpio@fe611000 {
+                        pio1: gpio@fe611000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -68,7 +68,7 @@
                                reg             = <0x1000 0x100>;
                                st,bank-name    = "PIO1";
                        };
-                        PIO2: gpio@fe612000 {
+                        pio2: gpio@fe612000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -76,7 +76,7 @@
                                reg             = <0x2000 0x100>;
                                st,bank-name    = "PIO2";
                        };
-                        PIO3: gpio@fe613000 {
+                        pio3: gpio@fe613000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -84,7 +84,7 @@
                                reg             = <0x3000 0x100>;
                                st,bank-name    = "PIO3";
                        };
-                        PIO4: gpio@fe614000 {
+                        pio4: gpio@fe614000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -96,8 +96,8 @@
                        sbc_serial1 {
                                pinctrl_sbc_serial1:sbc_serial1 {
                                        st,pins {
-                                                tx      = <&PIO2 6 ALT3 OUT>;
+                                                tx      = <&pio2 6 ALT3 OUT>;
-                                                rx      = <&PIO2 7 ALT3 IN>;
+                                                rx      = <&pio2 7 ALT3 IN>;
                                        };
                                };
                        };
@@ -105,15 +105,15 @@
                        keyscan {
                                pinctrl_keyscan: keyscan {
                                        st,pins {
-                                                keyin0 = <&PIO0 2 ALT2 IN>;
+                                                keyin0 = <&pio0 2 ALT2 IN>;
-                                                keyin1 = <&PIO0 3 ALT2 IN>;
+                                                keyin1 = <&pio0 3 ALT2 IN>;
-                                                keyin2 = <&PIO0 4 ALT2 IN>;
+                                                keyin2 = <&pio0 4 ALT2 IN>;
-                                                keyin3 = <&PIO2 6 ALT2 IN>;
+                                                keyin3 = <&pio2 6 ALT2 IN>;
-                                                keyout0 = <&PIO1 6 ALT2 OUT>;
+                                                keyout0 = <&pio1 6 ALT2 OUT>;
-                                                keyout1 = <&PIO1 7 ALT2 OUT>;
+                                                keyout1 = <&pio1 7 ALT2 OUT>;
-                                                keyout2 = <&PIO0 6 ALT2 OUT>;
+                                                keyout2 = <&pio0 6 ALT2 OUT>;
-                                                keyout3 = <&PIO2 7 ALT2 OUT>;
+                                                keyout3 = <&pio2 7 ALT2 OUT>;
                                        };
                                };
                        };
@@ -121,8 +121,8 @@
                        sbc_i2c0 {
                                pinctrl_sbc_i2c0_default: sbc_i2c0-default {
                                        st,pins {
-                                                sda = <&PIO4 6 ALT1 BIDIR>;
+                                                sda = <&pio4 6 ALT1 BIDIR>;
-                                                scl = <&PIO4 5 ALT1 BIDIR>;
+                                                scl = <&pio4 5 ALT1 BIDIR>;
                                        };
                                };
                        };
@@ -130,8 +130,8 @@
                        sbc_i2c1 {
                                pinctrl_sbc_i2c1_default: sbc_i2c1-default {
                                        st,pins {
-                                                sda = <&PIO3 2 ALT2 BIDIR>;
+                                                sda = <&pio3 2 ALT2 BIDIR>;
-                                                scl = <&PIO3 1 ALT2 BIDIR>;
+                                                scl = <&pio3 1 ALT2 BIDIR>;
                                        };
                                };
                        };
@@ -139,7 +139,7 @@
                        rc{
                                pinctrl_ir: ir0 {
                                        st,pins {
-                                                ir = <&PIO4 0 ALT2 IN>;
+                                                ir = <&pio4 0 ALT2 IN>;
                                        };
                                };
                        };
@@ -147,49 +147,49 @@
                        gmac1 {
                                pinctrl_mii1: mii1 {
                                                st,pins {
-                                                 txd0   = <&PIO0 0 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
+                                                 txd0   = <&pio0 0 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
-                                                 txd1   = <&PIO0 1 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
+                                                 txd1   = <&pio0 1 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
-                                                 txd2   = <&PIO0 2 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
+                                                 txd2   = <&pio0 2 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
-                                                 txd3   = <&PIO0 3 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
+                                                 txd3   = <&pio0 3 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
-                                                 txer   = <&PIO0 4 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
+                                                 txer   = <&pio0 4 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
-                                                 txen   = <&PIO0 5 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
+                                                 txen   = <&pio0 5 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
-                                                 txclk  = <&PIO0 6 ALT1 IN   NICLK      0       CLK_A>;
+                                                 txclk  = <&pio0 6 ALT1 IN   NICLK      0       CLK_A>;
-                                                 col    = <&PIO0 7 ALT1 IN   BYPASS     1000>;
+                                                 col    = <&pio0 7 ALT1 IN   BYPASS     1000>;
-                                                 mdio   = <&PIO1 0 ALT1 OUT  BYPASS     0>;
+                                                 mdio   = <&pio1 0 ALT1 OUT  BYPASS     0>;
-                                                 mdc    = <&PIO1 1 ALT1 OUT  NICLK      0       CLK_A>;
+                                                 mdc    = <&pio1 1 ALT1 OUT  NICLK      0       CLK_A>;
-                                                 crs    = <&PIO1 2 ALT1 IN   BYPASS     1000>;
+                                                 crs    = <&pio1 2 ALT1 IN   BYPASS     1000>;
-                                                 mdint  = <&PIO1 3 ALT1 IN   BYPASS     0>;
+                                                 mdint  = <&pio1 3 ALT1 IN   BYPASS     0>;
-                                                 rxd0   = <&PIO1 4 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
+                                                 rxd0   = <&pio1 4 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
-                                                 rxd1   = <&PIO1 5 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
+                                                 rxd1   = <&pio1 5 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
-                                                 rxd2   = <&PIO1 6 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
+                                                 rxd2   = <&pio1 6 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
-                                                 rxd3   = <&PIO1 7 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
+                                                 rxd3   = <&pio1 7 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
-                                                 rxdv   = <&PIO2 0 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
+                                                 rxdv   = <&pio2 0 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
-                                                 rx_er  = <&PIO2 1 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
+                                                 rx_er  = <&pio2 1 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
-                                                 rxclk  = <&PIO2 2 ALT1 IN   NICLK      0       CLK_A>;
+                                                 rxclk  = <&pio2 2 ALT1 IN   NICLK      0       CLK_A>;
-                                                 phyclk = <&PIO2 3 ALT1 IN   NICLK      1000    CLK_A>;
+                                                 phyclk = <&pio2 3 ALT1 IN   NICLK      1000    CLK_A>;
                                        };
                                };
                                pinctrl_rgmii1: rgmii1-0 {
                                        st,pins {
-                                                 txd0 =  <&PIO0 0 ALT1 OUT DE_IO        1000    CLK_A>;
+                                                 txd0 =  <&pio0 0 ALT1 OUT DE_IO        1000    CLK_A>;
-                                                 txd1 =  <&PIO0 1 ALT1 OUT DE_IO        1000    CLK_A>;
+                                                 txd1 =  <&pio0 1 ALT1 OUT DE_IO        1000    CLK_A>;
-                                                 txd2 =  <&PIO0 2 ALT1 OUT DE_IO        1000    CLK_A>;
+                                                 txd2 =  <&pio0 2 ALT1 OUT DE_IO        1000    CLK_A>;
-                                                 txd3 =  <&PIO0 3 ALT1 OUT DE_IO        1000    CLK_A>;
+                                                 txd3 =  <&pio0 3 ALT1 OUT DE_IO        1000    CLK_A>;
-                                                 txen =  <&PIO0 5 ALT1 OUT DE_IO        0       CLK_A>;
+                                                 txen =  <&pio0 5 ALT1 OUT DE_IO        0       CLK_A>;
-                                                 txclk = <&PIO0 6 ALT1 IN       NICLK   0       CLK_A>;
+                                                 txclk = <&pio0 6 ALT1 IN       NICLK   0       CLK_A>;
-                                                 mdio =  <&PIO1 0 ALT1 OUT      BYPASS  0>;
+                                                 mdio =  <&pio1 0 ALT1 OUT      BYPASS  0>;
-                                                 mdc =   <&PIO1 1 ALT1 OUT      NICLK   0       CLK_A>;
+                                                 mdc =   <&pio1 1 ALT1 OUT      NICLK   0       CLK_A>;
-                                                 rxd0 =  <&PIO1 4 ALT1 IN DE_IO 0       CLK_A>;
+                                                 rxd0 =  <&pio1 4 ALT1 IN DE_IO 0       CLK_A>;
-                                                 rxd1 =  <&PIO1 5 ALT1 IN DE_IO 0       CLK_A>;
+                                                 rxd1 =  <&pio1 5 ALT1 IN DE_IO 0       CLK_A>;
-                                                 rxd2 =  <&PIO1 6 ALT1 IN DE_IO 0       CLK_A>;
+                                                 rxd2 =  <&pio1 6 ALT1 IN DE_IO 0       CLK_A>;
-                                                 rxd3 =  <&PIO1 7 ALT1 IN DE_IO 0       CLK_A>;
+                                                 rxd3 =  <&pio1 7 ALT1 IN DE_IO 0       CLK_A>;
-                                                 rxdv =   <&PIO2 0 ALT1 IN DE_IO        500     CLK_A>;
+                                                 rxdv =   <&pio2 0 ALT1 IN DE_IO        500     CLK_A>;
-                                                 rxclk =  <&PIO2 2 ALT1 IN      NICLK   0       CLK_A>;
+                                                 rxclk =  <&pio2 2 ALT1 IN      NICLK   0       CLK_A>;
-                                                 phyclk = <&PIO2 3 ALT4 OUT     NICLK   0       CLK_B>;
+                                                 phyclk = <&pio2 3 ALT4 OUT     NICLK   0       CLK_B>;
-                                                 clk125= <&PIO3 7 ALT4 IN       NICLK   0       CLK_A>;
+                                                 clk125= <&pio3 7 ALT4 IN       NICLK   0       CLK_A>;
                                        };
                                };
                        };
@@ -206,7 +206,7 @@
                        interrupt-names = "irqmux";
                        ranges          = <0 0xfee00000 0x8000>;
-                        PIO5: gpio@fee00000 {
+                        pio5: gpio@fee00000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -214,7 +214,7 @@
                                reg             = <0 0x100>;
                                st,bank-name    = "PIO5";
                        };
-                        PIO6: gpio@fee01000 {
+                        pio6: gpio@fee01000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -222,7 +222,7 @@
                                reg             = <0x1000 0x100>;
                                st,bank-name    = "PIO6";
                        };
-                        PIO7: gpio@fee02000 {
+                        pio7: gpio@fee02000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -230,7 +230,7 @@
                                reg             = <0x2000 0x100>;
                                st,bank-name    = "PIO7";
                        };
-                        PIO8: gpio@fee03000 {
+                        pio8: gpio@fee03000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -238,7 +238,7 @@
                                reg             = <0x3000 0x100>;
                                st,bank-name    = "PIO8";
                        };
-                        PIO9: gpio@fee04000 {
+                        pio9: gpio@fee04000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -246,7 +246,7 @@
                                reg             = <0x4000 0x100>;
                                st,bank-name    = "PIO9";
                        };
-                        PIO10: gpio@fee05000 {
+                        pio10: gpio@fee05000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -254,7 +254,7 @@
                                reg             = <0x5000 0x100>;
                                st,bank-name    = "PIO10";
                        };
-                        PIO11: gpio@fee06000 {
+                        pio11: gpio@fee06000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -262,7 +262,7 @@
                                reg             = <0x6000 0x100>;
                                st,bank-name    = "PIO11";
                        };
-                        PIO12: gpio@fee07000 {
+                        pio12: gpio@fee07000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -274,8 +274,8 @@
                        i2c0 {
                                pinctrl_i2c0_default: i2c0-default {
                                        st,pins {
-                                                sda = <&PIO9 3 ALT1 BIDIR>;
+                                                sda = <&pio9 3 ALT1 BIDIR>;
-                                                scl = <&PIO9 2 ALT1 BIDIR>;
+                                                scl = <&pio9 2 ALT1 BIDIR>;
                                        };
                                };
                        };
@@ -283,8 +283,8 @@
                        i2c1 {
                                pinctrl_i2c1_default: i2c1-default {
                                        st,pins {
-                                                sda = <&PIO12 1 ALT1 BIDIR>;
+                                                sda = <&pio12 1 ALT1 BIDIR>;
-                                                scl = <&PIO12 0 ALT1 BIDIR>;
+                                                scl = <&pio12 0 ALT1 BIDIR>;
                                        };
                                };
                        };
@@ -301,7 +301,7 @@
                        interrupt-names = "irqmux";
                        ranges          = <0 0xfe820000 0x8000>;
-                        PIO13: gpio@fe820000 {
+                        pio13: gpio@fe820000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -309,7 +309,7 @@
                                reg             = <0 0x100>;
                                st,bank-name    = "PIO13";
                        };
-                        PIO14: gpio@fe821000 {
+                        pio14: gpio@fe821000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -317,7 +317,7 @@
                                reg             = <0x1000 0x100>;
                                st,bank-name    = "PIO14";
                        };
-                        PIO15: gpio@fe822000 {
+                        pio15: gpio@fe822000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -325,7 +325,7 @@
                                reg             = <0x2000 0x100>;
                                st,bank-name    = "PIO15";
                        };
-                        PIO16: gpio@fe823000 {
+                        pio16: gpio@fe823000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -333,7 +333,7 @@
                                reg             = <0x3000 0x100>;
                                st,bank-name    = "PIO16";
                        };
-                        PIO17: gpio@fe824000 {
+                        pio17: gpio@fe824000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -341,7 +341,7 @@
                                reg             = <0x4000 0x100>;
                                st,bank-name    = "PIO17";
                        };
-                        PIO18: gpio@fe825000 {
+                        pio18: gpio@fe825000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -353,8 +353,8 @@
                        serial2 {
                                pinctrl_serial2: serial2-0 {
                                        st,pins {
-                                                tx      = <&PIO17 4 ALT2 OUT>;
+                                                tx      = <&pio17 4 ALT2 OUT>;
-                                                rx      = <&PIO17 5 ALT2 IN>;
+                                                rx      = <&pio17 5 ALT2 IN>;
                                        };
                                };
                        };
@@ -362,73 +362,94 @@
                        gmac0{
                                pinctrl_mii0: mii0 {
                                        st,pins {
-                                         mdint =        <&PIO13 6 ALT2  IN      BYPASS          0>;
+                                         mdint =        <&pio13 6 ALT2  IN      BYPASS          0>;
-                                         txen =         <&PIO13 7 ALT2  OUT     SE_NICLK_IO     0       CLK_A>;
+                                         txen =         <&pio13 7 ALT2  OUT     SE_NICLK_IO     0       CLK_A>;
-                                         txd0 =         <&PIO14 0 ALT2  OUT     SE_NICLK_IO     0       CLK_A>;
+                                         txd0 =         <&pio14 0 ALT2  OUT     SE_NICLK_IO     0       CLK_A>;
-                                         txd1 =         <&PIO14 1 ALT2  OUT     SE_NICLK_IO     0       CLK_A>;
+                                         txd1 =         <&pio14 1 ALT2  OUT     SE_NICLK_IO     0       CLK_A>;
-                                         txd2 =         <&PIO14 2 ALT2  OUT     SE_NICLK_IO     0       CLK_B>;
+                                         txd2 =         <&pio14 2 ALT2  OUT     SE_NICLK_IO     0       CLK_B>;
-                                         txd3 =         <&PIO14 3 ALT2  OUT     SE_NICLK_IO     0       CLK_B>;
+                                         txd3 =         <&pio14 3 ALT2  OUT     SE_NICLK_IO     0       CLK_B>;
-                                         txclk =        <&PIO15 0 ALT2  IN      NICLK           0       CLK_A>;
+                                         txclk =        <&pio15 0 ALT2  IN      NICLK           0       CLK_A>;
-                                         txer =         <&PIO15 1 ALT2  OUT     SE_NICLK_IO     0       CLK_A>;
+                                         txer =         <&pio15 1 ALT2  OUT     SE_NICLK_IO     0       CLK_A>;
-                                         crs =          <&PIO15 2 ALT2  IN      BYPASS          1000>;
+                                         crs =          <&pio15 2 ALT2  IN      BYPASS          1000>;
-                                         col =          <&PIO15 3 ALT2  IN      BYPASS          1000>;
+                                         col =          <&pio15 3 ALT2  IN      BYPASS          1000>;
-                                         mdio  =        <&PIO15 4 ALT2  OUT     BYPASS  3000>;
+                                         mdio  =        <&pio15 4 ALT2  OUT     BYPASS  3000>;
-                                         mdc   =        <&PIO15 5 ALT2  OUT     NICLK   0       CLK_B>;
+                                         mdc   =        <&pio15 5 ALT2  OUT     NICLK   0       CLK_B>;
-                                         rxd0 =         <&PIO16 0 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
+                                         rxd0 =         <&pio16 0 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
-                                         rxd1 =         <&PIO16 1 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
+                                         rxd1 =         <&pio16 1 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
-                                         rxd2 =         <&PIO16 2 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
+                                         rxd2 =         <&pio16 2 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
-                                         rxd3 =         <&PIO16 3 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
+                                         rxd3 =         <&pio16 3 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
-                                         rxdv =         <&PIO15 6 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
+                                         rxdv =         <&pio15 6 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
-                                         rx_er =        <&PIO15 7 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
+                                         rx_er =        <&pio15 7 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
-                                         rxclk =        <&PIO17 0 ALT2  IN      NICLK           0       CLK_A>;
+                                         rxclk =        <&pio17 0 ALT2  IN      NICLK           0       CLK_A>;
-                                         phyclk =       <&PIO13 5 ALT2  OUT     NICLK   1000    CLK_A>;
+                                         phyclk =       <&pio13 5 ALT2  OUT     NICLK   1000    CLK_A>;
                                        };
                                };
                        pinctrl_gmii0: gmii0 {
                                st,pins {
-                                         mdint =        <&PIO13 6       ALT2 IN         BYPASS  0>;
+                                         mdint =        <&pio13 6       ALT2 IN         BYPASS  0>;
-                                         mdio  =        <&PIO15 4       ALT2 OUT        BYPASS  3000>;
+                                         mdio  =        <&pio15 4       ALT2 OUT        BYPASS  3000>;
-                                         mdc   =        <&PIO15 5       ALT2 OUT        NICLK   0       CLK_B>;
+                                         mdc   =        <&pio15 5       ALT2 OUT        NICLK   0       CLK_B>;
-                                         txen =         <&PIO13 7       ALT2 OUT        SE_NICLK_IO     3000    CLK_A>;
+                                         txen =         <&pio13 7       ALT2 OUT        SE_NICLK_IO     3000    CLK_A>;
-                                         txd0 =         <&PIO14 0       ALT2 OUT        SE_NICLK_IO     3000    CLK_A>;
+                                         txd0 =         <&pio14 0       ALT2 OUT        SE_NICLK_IO     3000    CLK_A>;
-                                         txd1 =         <&PIO14 1       ALT2 OUT        SE_NICLK_IO     3000    CLK_A>;
+                                         txd1 =         <&pio14 1       ALT2 OUT        SE_NICLK_IO     3000    CLK_A>;
-                                         txd2 =         <&PIO14 2       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
+                                         txd2 =         <&pio14 2       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
-                                         txd3 =         <&PIO14 3       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
+                                         txd3 =         <&pio14 3       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
-                                         txd4 =         <&PIO14 4       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
+                                         txd4 =         <&pio14 4       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
-                                         txd5 =         <&PIO14 5       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
+                                         txd5 =         <&pio14 5       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
-                                         txd6 =         <&PIO14 6       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
+                                         txd6 =         <&pio14 6       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
-                                         txd7 =         <&PIO14 7       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
+                                         txd7 =         <&pio14 7       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
-                                         txclk =        <&PIO15 0       ALT2 IN         NICLK   0       CLK_A>;
+                                         txclk =        <&pio15 0       ALT2 IN         NICLK   0       CLK_A>;
-                                         txer =         <&PIO15 1       ALT2 OUT        SE_NICLK_IO     3000    CLK_A>;
+                                         txer =         <&pio15 1       ALT2 OUT        SE_NICLK_IO     3000    CLK_A>;
-                                         crs =          <&PIO15 2       ALT2 IN         BYPASS  1000>;
+                                         crs =          <&pio15 2       ALT2 IN         BYPASS  1000>;
-                                         col =          <&PIO15 3       ALT2 IN         BYPASS  1000>;
+                                         col =          <&pio15 3       ALT2 IN         BYPASS  1000>;
-                                         rxdv =         <&PIO15 6       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxdv =         <&pio15 6       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
-                                         rx_er =        <&PIO15 7       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rx_er =        <&pio15 7       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
-                                         rxd0 =         <&PIO16 0       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxd0 =         <&pio16 0       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
-                                         rxd1 =         <&PIO16 1       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxd1 =         <&pio16 1       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
-                                         rxd2 =         <&PIO16 2       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxd2 =         <&pio16 2       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
-                                         rxd3 =         <&PIO16 3       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxd3 =         <&pio16 3       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
-                                         rxd4 =         <&PIO16 4       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxd4 =         <&pio16 4       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
-                                         rxd5 =         <&PIO16 5       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxd5 =         <&pio16 5       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
-                                         rxd6 =         <&PIO16 6       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxd6 =         <&pio16 6       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
-                                         rxd7 =         <&PIO16 7       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxd7 =         <&pio16 7       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
-                                         rxclk =        <&PIO17 0       ALT2 IN NICLK   0       CLK_A>;
+                                         rxclk =        <&pio17 0       ALT2 IN NICLK   0       CLK_A>;
-                                         clk125 =       <&PIO17 6       ALT1 IN NICLK   0       CLK_A>;
+                                         clk125 =       <&pio17 6       ALT1 IN NICLK   0       CLK_A>;
-                                         phyclk =       <&PIO13 5       ALT4 OUT NICLK   0       CLK_B>;
+                                         phyclk =       <&pio13 5       ALT4 OUT NICLK   0       CLK_B>;
                                        };
                                };
                        };
+                        mmc0 {
+                                pinctrl_mmc0: mmc0 {
+                                        st,pins {
+                                                mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;
+                                                data0  = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>;
+                                                data1  = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>;
+                                                data2  = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>;
+                                                data3  = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>;
+                                                cmd    = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>;
+                                                wp     = <&pio15 3 ALT4 IN>;
+                                                data4  = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>;
+                                                data5  = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>;
+                                                data6  = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>;
+                                                data7  = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>;
+                                                pwr    = <&pio17 1 ALT4 OUT>;
+                                                cd     = <&pio17 2 ALT4 IN>;
+                                                led    = <&pio17 3 ALT4 OUT>;
+                                        };
+                                };
+                        };
                };
                pin-controller-left {
@@ -442,7 +463,7 @@
                        interrupt-names = "irqmux";
                        ranges          = <0 0xfd6b0000 0x3000>;
-                        PIO100: gpio@fd6b0000 {
+                        pio100: gpio@fd6b0000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -450,7 +471,7 @@
                                reg             = <0 0x100>;
                                st,bank-name    = "PIO100";
                        };
-                        PIO101: gpio@fd6b1000 {
+                        pio101: gpio@fd6b1000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -458,7 +479,7 @@
                                reg             = <0x1000 0x100>;
                                st,bank-name    = "PIO101";
                        };
-                        PIO102: gpio@fd6b2000 {
+                        pio102: gpio@fd6b2000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -479,7 +500,7 @@
                        interrupt-names = "irqmux";
                        ranges          = <0 0xfd330000 0x5000>;
-                        PIO103: gpio@fd330000 {
+                        pio103: gpio@fd330000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -487,7 +508,7 @@
                                reg             = <0 0x100>;
                                st,bank-name    = "PIO103";
                        };
-                        PIO104: gpio@fd331000 {
+                        pio104: gpio@fd331000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -495,7 +516,7 @@
                                reg             = <0x1000 0x100>;
                                st,bank-name    = "PIO104";
                        };
-                        PIO105: gpio@fd332000 {
+                        pio105: gpio@fd332000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -503,7 +524,7 @@
                                reg             = <0x2000 0x100>;
                                st,bank-name    = "PIO105";
                        };
-                        PIO106: gpio@fd333000 {
+                        pio106: gpio@fd333000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -511,7 +532,7 @@
                                reg             = <0x3000 0x100>;
                                st,bank-name    = "PIO106";
                        };
-                        PIO107: gpio@fd334000 {
+                        pio107: gpio@fd334000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index a0f6f75fe3b5..9198c12765ea 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -218,5 +218,17 @@
                        resets  = <&powerdown STIH415_KEYSCAN_POWERDOWN>,
                                  <&softreset STIH415_KEYSCAN_SOFTRESET>;
                };
+                mmc0: sdhci@fe81e000 {
+                        compatible      = "st,sdhci";
+                        status          = "disabled";
+                        reg             = <0xfe81e000 0x1000>;
+                        interrupts      = <GIC_SPI 145 IRQ_TYPE_NONE>;
+                        interrupt-names = "mmcirq";
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_mmc0>;
+                        clock-names     = "mmc";
+                        clocks          = <&clk_s_a1_ls 1>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts
index 4e2df66b99ea..200a81844765 100644
--- a/arch/arm/boot/dts/stih416-b2020.dts
+++ b/arch/arm/boot/dts/stih416-b2020.dts
@@ -12,4 +12,26 @@
 / {
        model = "STiH416 B2020";
        compatible = "st,stih416-b2020", "st,stih416";
+        soc {
+                mmc1: sdhci@fe81f000 {
+                        status       = "okay";
+                        bus-width    = <8>;
+                        non-removable;
+                };
+                miphy365x_phy: phy@fe382000 {
+                        phy_port0: port@fe382000 {
+                                st,sata-gen = <3>;
+                        };
+                        phy_port1: port@fe38a000 {
+                                st,pcie-tx-pol-inv;
+                        };
+                };
+                sata0: sata@fe380000{
+                        status = "okay";
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/stih416-b2020e.dts b/arch/arm/boot/dts/stih416-b2020e.dts
index ba0fa2caaf18..961799e1dc51 100644
--- a/arch/arm/boot/dts/stih416-b2020e.dts
+++ b/arch/arm/boot/dts/stih416-b2020e.dts
@@ -19,17 +19,37 @@
                        red {
                                #gpio-cells             = <1>;
                                label                   = "Front Panel LED";
-                                gpios                   = <&PIO4 1>;
+                                gpios                   = <&pio4 1>;
                                linux,default-trigger   = "heartbeat";
                        };
                        green {
-                                gpios                   = <&PIO1 3>;
+                                gpios                   = <&pio1 3>;
                                default-state           = "off";
                        };
                };
                ethernet1: dwmac@fef08000 {
-                        snps,reset-gpio = <&PIO0 7>;
+                        snps,reset-gpio = <&pio0 7>;
+                };
+                mmc1: sdhci@fe81f000 {
+                        status       = "okay";
+                        bus-width    = <8>;
+                        non-removable;
+                };
+                miphy365x_phy: phy@fe382000 {
+                        phy_port0: port@fe382000 {
+                                st,sata-gen = <3>;
+                        };
+                        phy_port1: port@fe38a000 {
+                                st,pcie-tx-pol-inv;
+                        };
+                };
+                sata0: sata@fe380000{
+                        status = "okay";
                };
        };
 };
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
index ee6c119e261e..9cccf2d6aa26 100644
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -12,36 +12,36 @@
 / {
        aliases {
-                gpio0   = &PIO0;
+                gpio0   = &pio0;
-                gpio1   = &PIO1;
+                gpio1   = &pio1;
-                gpio2   = &PIO2;
+                gpio2   = &pio2;
-                gpio3   = &PIO3;
+                gpio3   = &pio3;
-                gpio4   = &PIO4;
+                gpio4   = &pio4;
-                gpio5   = &PIO40;
+                gpio5   = &pio40;
-                gpio6   = &PIO5;
+                gpio6   = &pio5;
-                gpio7   = &PIO6;
+                gpio7   = &pio6;
-                gpio8   = &PIO7;
+                gpio8   = &pio7;
-                gpio9   = &PIO8;
+                gpio9   = &pio8;
-                gpio10  = &PIO9;
+                gpio10  = &pio9;
-                gpio11  = &PIO10;
+                gpio11  = &pio10;
-                gpio12  = &PIO11;
+                gpio12  = &pio11;
-                gpio13  = &PIO12;
+                gpio13  = &pio12;
-                gpio14  = &PIO30;
+                gpio14  = &pio30;
-                gpio15  = &PIO31;
+                gpio15  = &pio31;
-                gpio16  = &PIO13;
+                gpio16  = &pio13;
-                gpio17  = &PIO14;
+                gpio17  = &pio14;
-                gpio18  = &PIO15;
+                gpio18  = &pio15;
-                gpio19  = &PIO16;
+                gpio19  = &pio16;
-                gpio20  = &PIO17;
+                gpio20  = &pio17;
-                gpio21  = &PIO18;
+                gpio21  = &pio18;
-                gpio22  = &PIO100;
+                gpio22  = &pio100;
-                gpio23  = &PIO101;
+                gpio23  = &pio101;
-                gpio24  = &PIO102;
+                gpio24  = &pio102;
-                gpio25  = &PIO103;
+                gpio25  = &pio103;
-                gpio26  = &PIO104;
+                gpio26  = &pio104;
-                gpio27  = &PIO105;
+                gpio27  = &pio105;
-                gpio28  = &PIO106;
+                gpio28  = &pio106;
-                gpio29  = &PIO107;
+                gpio29  = &pio107;
        };
        soc {
@@ -56,7 +56,7 @@
                        interrupt-names = "irqmux";
                        ranges          = <0 0xfe610000 0x6000>;
-                        PIO0: gpio@fe610000 {
+                        pio0: gpio@fe610000 {
                                gpio-controller;
                                #gpio-cells = <1>;
                                interrupt-controller;
@@ -64,7 +64,7 @@
                                reg             = <0 0x100>;
                                st,bank-name    = "PIO0";
                        };
-                        PIO1: gpio@fe611000 {
+                        pio1: gpio@fe611000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -72,7 +72,7 @@
                                reg             = <0x1000 0x100>;
                                st,bank-name    = "PIO1";
                        };
-                        PIO2: gpio@fe612000 {
+                        pio2: gpio@fe612000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -80,7 +80,7 @@
                                reg             = <0x2000 0x100>;
                                st,bank-name    = "PIO2";
                        };
-                        PIO3: gpio@fe613000 {
+                        pio3: gpio@fe613000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -88,7 +88,7 @@
                                reg             = <0x3000 0x100>;
                                st,bank-name    = "PIO3";
                        };
-                        PIO4: gpio@fe614000 {
+                        pio4: gpio@fe614000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -96,7 +96,7 @@
                                reg             = <0x4000 0x100>;
                                st,bank-name    = "PIO4";
                        };
-                        PIO40: gpio@fe615000 {
+                        pio40: gpio@fe615000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -109,15 +109,15 @@
                        rc{
                                pinctrl_ir: ir0 {
                                        st,pins {
-                                                ir = <&PIO4 0 ALT2 IN>;
+                                                ir = <&pio4 0 ALT2 IN>;
                                        };
                                };
                        };
                        sbc_serial1 {
                                pinctrl_sbc_serial1: sbc_serial1 {
                                        st,pins {
-                                                tx      = <&PIO2 6 ALT3 OUT>;
+                                                tx      = <&pio2 6 ALT3 OUT>;
-                                                rx      = <&PIO2 7 ALT3 IN>;
+                                                rx      = <&pio2 7 ALT3 IN>;
                                        };
                                };
                        };
@@ -125,15 +125,15 @@
                        keyscan {
                                pinctrl_keyscan: keyscan {
                                        st,pins {
-                                                keyin0 = <&PIO0 2 ALT2 IN>;
+                                                keyin0 = <&pio0 2 ALT2 IN>;
-                                                keyin1 = <&PIO0 3 ALT2 IN>;
+                                                keyin1 = <&pio0 3 ALT2 IN>;
-                                                keyin2 = <&PIO0 4 ALT2 IN>;
+                                                keyin2 = <&pio0 4 ALT2 IN>;
-                                                keyin3 = <&PIO2 6 ALT2 IN>;
+                                                keyin3 = <&pio2 6 ALT2 IN>;
-                                                keyout0 = <&PIO1 6 ALT2 OUT>;
+                                                keyout0 = <&pio1 6 ALT2 OUT>;
-                                                keyout1 = <&PIO1 7 ALT2 OUT>;
+                                                keyout1 = <&pio1 7 ALT2 OUT>;
-                                                keyout2 = <&PIO0 6 ALT2 OUT>;
+                                                keyout2 = <&pio0 6 ALT2 OUT>;
-                                                keyout3 = <&PIO2 7 ALT2 OUT>;
+                                                keyout3 = <&pio2 7 ALT2 OUT>;
                                        };
                                };
                        };
@@ -141,8 +141,17 @@
                        sbc_i2c0 {
                                pinctrl_sbc_i2c0_default: sbc_i2c0-default {
                                        st,pins {
-                                                sda = <&PIO4 6 ALT1 BIDIR>;
+                                                sda = <&pio4 6 ALT1 BIDIR>;
-                                                scl = <&PIO4 5 ALT1 BIDIR>;
+                                                scl = <&pio4 5 ALT1 BIDIR>;
+                                        };
+                                };
+                        };
+                        usb {
+                                pinctrl_usb3: usb3 {
+                                        st,pins {
+                                                oc-detect = <&pio40 0 ALT1 IN>;
+                                                pwr-enable = <&pio40 1 ALT1 OUT>;
                                        };
                                };
                        };
@@ -150,8 +159,8 @@
                        sbc_i2c1 {
                                pinctrl_sbc_i2c1_default: sbc_i2c1-default {
                                        st,pins {
-                                                sda = <&PIO3 2 ALT2 BIDIR>;
+                                                sda = <&pio3 2 ALT2 BIDIR>;
-                                                scl = <&PIO3 1 ALT2 BIDIR>;
+                                                scl = <&pio3 1 ALT2 BIDIR>;
                                        };
                                };
                        };
@@ -159,51 +168,51 @@
                        gmac1 {
                                pinctrl_mii1: mii1 {
                                        st,pins {
-                                                txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
-                                                txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
-                                                txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
-                                                txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
-                                                txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
-                                                txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
-                                                txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
+                                                txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
-                                                col =   <&PIO0 7 ALT1 IN BYPASS 1000>;
+                                                col =   <&pio0 7 ALT1 IN BYPASS 1000>;
-                                                mdio =  <&PIO1 0 ALT1 OUT BYPASS 1500>;
+                                                mdio =  <&pio1 0 ALT1 OUT BYPASS 1500>;
-                                                mdc =   <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
+                                                mdc =   <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
-                                                crs =   <&PIO1 2 ALT1 IN BYPASS 1000>;
+                                                crs =   <&pio1 2 ALT1 IN BYPASS 1000>;
-                                                mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
+                                                mdint = <&pio1 3 ALT1 IN BYPASS 0>;
-                                                rxd0 =  <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxd0 =  <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
-                                                rxd1 =  <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxd1 =  <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
-                                                rxd2 =  <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxd2 =  <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
-                                                rxd3 =  <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxd3 =  <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
-                                                rxdv =  <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxdv =  <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
-                                                rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                                rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
-                                                rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
+                                                rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
-                                                phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>;
+                                                phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
                                        };
                                };
                                pinctrl_rgmii1: rgmii1-0 {
                                        st,pins {
-                                                txd0 =  <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>;
+                                                txd0 =  <&pio0 0 ALT1 OUT DE_IO 500 CLK_A>;
-                                                txd1 =  <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>;
+                                                txd1 =  <&pio0 1 ALT1 OUT DE_IO 500 CLK_A>;
-                                                txd2 =  <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>;
+                                                txd2 =  <&pio0 2 ALT1 OUT DE_IO 500 CLK_A>;
-                                                txd3 =  <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>;
+                                                txd3 =  <&pio0 3 ALT1 OUT DE_IO 500 CLK_A>;
-                                                txen =  <&PIO0 5 ALT1 OUT DE_IO 0   CLK_A>;
+                                                txen =  <&pio0 5 ALT1 OUT DE_IO 0   CLK_A>;
-                                                txclk = <&PIO0 6 ALT1 IN  NICLK 0   CLK_A>;
+                                                txclk = <&pio0 6 ALT1 IN  NICLK 0   CLK_A>;
-                                                mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
+                                                mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
-                                                mdc  = <&PIO1 1 ALT1 OUT NICLK  0 CLK_A>;
+                                                mdc  = <&pio1 1 ALT1 OUT NICLK  0 CLK_A>;
-                                                rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>;
+                                                rxd0 = <&pio1 4 ALT1 IN DE_IO 500 CLK_A>;
-                                                rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>;
+                                                rxd1 = <&pio1 5 ALT1 IN DE_IO 500 CLK_A>;
-                                                rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>;
+                                                rxd2 = <&pio1 6 ALT1 IN DE_IO 500 CLK_A>;
-                                                rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>;
+                                                rxd3 = <&pio1 7 ALT1 IN DE_IO 500 CLK_A>;
-                                                rxdv   = <&PIO2 0 ALT1 IN  DE_IO 500 CLK_A>;
+                                                rxdv   = <&pio2 0 ALT1 IN  DE_IO 500 CLK_A>;
-                                                rxclk  = <&PIO2 2 ALT1 IN  NICLK 0   CLK_A>;
+                                                rxclk  = <&pio2 2 ALT1 IN  NICLK 0   CLK_A>;
-                                                phyclk = <&PIO2 3 ALT4 OUT NICLK 0   CLK_B>;
+                                                phyclk = <&pio2 3 ALT4 OUT NICLK 0   CLK_B>;
-                                                clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
+                                                clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
                                        };
                                };
                        };
@@ -220,7 +229,7 @@
                        interrupt-names = "irqmux";
                        ranges          = <0 0xfee00000 0x10000>;
-                        PIO5: gpio@fee00000 {
+                        pio5: gpio@fee00000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -228,7 +237,7 @@
                                reg             = <0 0x100>;
                                st,bank-name    = "PIO5";
                        };
-                        PIO6: gpio@fee01000 {
+                        pio6: gpio@fee01000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -236,7 +245,7 @@
                                reg             = <0x1000 0x100>;
                                st,bank-name    = "PIO6";
                        };
-                        PIO7: gpio@fee02000 {
+                        pio7: gpio@fee02000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -244,7 +253,7 @@
                                reg             = <0x2000 0x100>;
                                st,bank-name    = "PIO7";
                        };
-                        PIO8: gpio@fee03000 {
+                        pio8: gpio@fee03000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -252,7 +261,7 @@
                                reg             = <0x3000 0x100>;
                                st,bank-name    = "PIO8";
                        };
-                        PIO9: gpio@fee04000 {
+                        pio9: gpio@fee04000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -260,7 +269,7 @@
                                reg             = <0x4000 0x100>;
                                st,bank-name    = "PIO9";
                        };
-                        PIO10: gpio@fee05000 {
+                        pio10: gpio@fee05000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -268,7 +277,7 @@
                                reg             = <0x5000 0x100>;
                                st,bank-name    = "PIO10";
                        };
-                        PIO11: gpio@fee06000 {
+                        pio11: gpio@fee06000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -276,7 +285,7 @@
                                reg             = <0x6000 0x100>;
                                st,bank-name    = "PIO11";
                        };
-                        PIO12: gpio@fee07000 {
+                        pio12: gpio@fee07000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -284,7 +293,7 @@
                                reg             = <0x7000 0x100>;
                                st,bank-name    = "PIO12";
                        };
-                        PIO30: gpio@fee08000 {
+                        pio30: gpio@fee08000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -292,7 +301,7 @@
                                reg             = <0x8000 0x100>;
                                st,bank-name    = "PIO30";
                        };
-                        PIO31: gpio@fee09000 {
+                        pio31: gpio@fee09000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -304,7 +313,7 @@
                        serial2-oe {
                                pinctrl_serial2_oe: serial2-1 {
                                        st,pins {
-                                                output-enable   = <&PIO11 3 ALT2 OUT>;
+                                                output-enable   = <&pio11 3 ALT2 OUT>;
                                        };
                                };
                        };
@@ -312,17 +321,27 @@
                        i2c0 {
                                pinctrl_i2c0_default: i2c0-default {
                                        st,pins {
-                                                sda = <&PIO9 3 ALT1 BIDIR>;
+                                                sda = <&pio9 3 ALT1 BIDIR>;
-                                                scl = <&PIO9 2 ALT1 BIDIR>;
+                                                scl = <&pio9 2 ALT1 BIDIR>;
+                                        };
+                                };
+                        };
+                        usb {
+                                pinctrl_usb0: usb0 {
+                                        st,pins {
+                                                oc-detect = <&pio9 4 ALT1 IN>;
+                                                pwr-enable = <&pio9 5 ALT1 OUT>;
                                        };
                                };
                        };
                        i2c1 {
                                pinctrl_i2c1_default: i2c1-default {
                                        st,pins {
-                                                sda = <&PIO12 1 ALT1 BIDIR>;
+                                                sda = <&pio12 1 ALT1 BIDIR>;
-                                                scl = <&PIO12 0 ALT1 BIDIR>;
+                                                scl = <&pio12 0 ALT1 BIDIR>;
                                        };
                                };
                        };
@@ -330,12 +349,12 @@
                        fsm {
                                pinctrl_fsm: fsm {
                                        st,pins {
-                                                spi-fsm-clk  = <&PIO12 2 ALT1 OUT>;
+                                                spi-fsm-clk  = <&pio12 2 ALT1 OUT>;
-                                                spi-fsm-cs   = <&PIO12 3 ALT1 OUT>;
+                                                spi-fsm-cs   = <&pio12 3 ALT1 OUT>;
-                                                spi-fsm-mosi = <&PIO12 4 ALT1 OUT>;
+                                                spi-fsm-mosi = <&pio12 4 ALT1 OUT>;
-                                                spi-fsm-miso = <&PIO12 5 ALT1 IN>;
+                                                spi-fsm-miso = <&pio12 5 ALT1 IN>;
-                                                spi-fsm-hol  = <&PIO12 6 ALT1 OUT>;
+                                                spi-fsm-hol  = <&pio12 6 ALT1 OUT>;
-                                                spi-fsm-wp   = <&PIO12 7 ALT1 OUT>;
+                                                spi-fsm-wp   = <&pio12 7 ALT1 OUT>;
                                        };
                                };
                        };
@@ -352,7 +371,7 @@
                        interrupt-names = "irqmux";
                        ranges          = <0 0xfe820000 0x6000>;
-                        PIO13: gpio@fe820000 {
+                        pio13: gpio@fe820000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -360,7 +379,7 @@
                                reg             = <0 0x100>;
                                st,bank-name    = "PIO13";
                        };
-                        PIO14: gpio@fe821000 {
+                        pio14: gpio@fe821000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -368,7 +387,7 @@
                                reg             = <0x1000 0x100>;
                                st,bank-name    = "PIO14";
                        };
-                        PIO15: gpio@fe822000 {
+                        pio15: gpio@fe822000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -376,7 +395,7 @@
                                reg             = <0x2000 0x100>;
                                st,bank-name    = "PIO15";
                        };
-                        PIO16: gpio@fe823000 {
+                        pio16: gpio@fe823000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -384,7 +403,7 @@
                                reg             = <0x3000 0x100>;
                                st,bank-name    = "PIO16";
                        };
-                        PIO17: gpio@fe824000 {
+                        pio17: gpio@fe824000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -392,7 +411,7 @@
                                reg             = <0x4000 0x100>;
                                st,bank-name    = "PIO17";
                        };
-                        PIO18: gpio@fe825000 {
+                        pio18: gpio@fe825000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -405,8 +424,8 @@
                        serial2 {
                                pinctrl_serial2: serial2-0 {
                                        st,pins {
-                                                tx      = <&PIO17 4 ALT2 OUT>;
+                                                tx      = <&pio17 4 ALT2 OUT>;
-                                                rx      = <&PIO17 5 ALT2 IN>;
+                                                rx      = <&pio17 5 ALT2 IN>;
                                        };
                                };
                        };
@@ -414,28 +433,28 @@
                        gmac0 {
                                pinctrl_mii0: mii0 {
                                        st,pins {
-                                                mdint = <&PIO13 6 ALT2 IN  BYPASS      0>;
+                                                mdint = <&pio13 6 ALT2 IN  BYPASS      0>;
-                                                txen =  <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txen =  <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
-                                                txd0 =  <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txd0 =  <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
-                                                txd1 =  <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txd1 =  <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
-                                                txd2 =  <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+                                                txd2 =  <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
-                                                txd3 =  <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+                                                txd3 =  <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
-                                                txclk = <&PIO15 0 ALT2 IN  NICLK       0 CLK_A>;
+                                                txclk = <&pio15 0 ALT2 IN  NICLK       0 CLK_A>;
-                                                txer =  <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txer =  <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
-                                                crs = <&PIO15 2 ALT2 IN  BYPASS 1000>;
+                                                crs = <&pio15 2 ALT2 IN  BYPASS 1000>;
-                                                col = <&PIO15 3 ALT2 IN  BYPASS 1000>;
+                                                col = <&pio15 3 ALT2 IN  BYPASS 1000>;
-                                                mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>;
+                                                mdio= <&pio15 4 ALT2 OUT BYPASS 1500>;
-                                                mdc = <&PIO15 5 ALT2 OUT NICLK  0    CLK_B>;
+                                                mdc = <&pio15 5 ALT2 OUT NICLK  0    CLK_B>;
-                                                rxd0 =  <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxd0 =  <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
-                                                rxd1 =  <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxd1 =  <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
-                                                rxd2 =  <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxd2 =  <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
-                                                rxd3 =  <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxd3 =  <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
-                                                rxdv =  <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxdv =  <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
-                                                rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                                rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
-                                                rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
+                                                rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>;
-                                                phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>;
+                                                phyclk = <&pio13 5 ALT2 OUT NICLK 0 CLK_B>;
                                        };
                                };
@@ -445,25 +464,79 @@
                                };
                                pinctrl_rgmii0: rgmii0 {
                                        st,pins {
-                                                 phyclk = <&PIO13  5 ALT4 OUT NICLK 0 CLK_B>;
+                                                 phyclk = <&pio13  5 ALT4 OUT NICLK 0 CLK_B>;
-                                                 txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>;
+                                                 txen = <&pio13 7 ALT2 OUT DE_IO 0 CLK_A>;
-                                                 txd0  = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>;
+                                                 txd0  = <&pio14 0 ALT2 OUT DE_IO 500 CLK_A>;
-                                                 txd1  = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>;
+                                                 txd1  = <&pio14 1 ALT2 OUT DE_IO 500 CLK_A>;
-                                                 txd2  = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>;
+                                                 txd2  = <&pio14 2 ALT2 OUT DE_IO 500 CLK_B>;
-                                                 txd3  = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>;
+                                                 txd3  = <&pio14 3 ALT2 OUT DE_IO 500 CLK_B>;
-                                                 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
+                                                 txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
-                                                 mdio = <&PIO15 4 ALT2 OUT BYPASS 0>;
+                                                 mdio = <&pio15 4 ALT2 OUT BYPASS 0>;
-                                                 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
+                                                 mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
-                                                 rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>;
+                                                 rxdv = <&pio15 6 ALT2 IN DE_IO 500 CLK_A>;
-                                                 rxd0 =<&PIO16 0 ALT2 IN DE_IO  500 CLK_A>;
+                                                 rxd0 =<&pio16 0 ALT2 IN DE_IO  500 CLK_A>;
-                                                 rxd1 =<&PIO16 1 ALT2 IN DE_IO  500 CLK_A>;
+                                                 rxd1 =<&pio16 1 ALT2 IN DE_IO  500 CLK_A>;
-                                                 rxd2 =<&PIO16 2 ALT2 IN DE_IO  500 CLK_A>;
+                                                 rxd2 =<&pio16 2 ALT2 IN DE_IO  500 CLK_A>;
-                                                 rxd3  =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>;
+                                                 rxd3  =<&pio16 3 ALT2 IN DE_IO 500 CLK_A>;
-                                                 rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
+                                                 rxclk =<&pio17 0 ALT2 IN NICLK 0 CLK_A>;
-                                                 clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
+                                                 clk125=<&pio17 6 ALT1 IN NICLK 0 CLK_A>;
+                                        };
+                                };
+                        };
+                        mmc0 {
+                                pinctrl_mmc0: mmc0 {
+                                        st,pins {
+                                                mmcclk  = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;
+                                                data0   = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>;
+                                                data1   = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>;
+                                                data2   = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>;
+                                                data3   = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>;
+                                                cmd     = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>;
+                                                wp      = <&pio15 3 ALT4 IN>;
+                                                data4   = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>;
+                                                data5   = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>;
+                                                data6   = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>;
+                                                data7   = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>;
+                                                pwr     = <&pio17 1 ALT4 OUT>;
+                                                cd      = <&pio17 2 ALT4 IN>;
+                                                led     = <&pio17 3 ALT4 OUT>;
+                                        };
+                                };
+                        };
+                        mmc1 {
+                                pinctrl_mmc1: mmc1 {
+                                        st,pins {
+                                                mmcclk  = <&pio15 0 ALT3 BIDIR_PU NICLK 0 CLK_B>;
+                                                data0   = <&pio13 7 ALT3 BIDIR_PU BYPASS 0>;
+                                                data1   = <&pio14 1 ALT3 BIDIR_PU BYPASS 0>;
+                                                data2   = <&pio14 2 ALT3 BIDIR_PU BYPASS 0>;
+                                                data3   = <&pio14 3 ALT3 BIDIR_PU BYPASS 0>;
+                                                cmd     = <&pio15 4 ALT3 BIDIR_PU BYPASS 0>;
+                                                data4   = <&pio15 6 ALT3 BIDIR_PU BYPASS 0>;
+                                                data5   = <&pio15 7 ALT3 BIDIR_PU BYPASS 0>;
+                                                data6   = <&pio16 0 ALT3 BIDIR_PU BYPASS 0>;
+                                                data7   = <&pio16 1 ALT3 BIDIR_PU BYPASS 0>;
+                                                pwr     = <&pio16 2 ALT3 OUT>;
+                                                nreset  = <&pio13 6 ALT3 OUT>;
+                                        };
+                                };
+                        };
+                        usb {
+                                pinctrl_usb1: usb1 {
+                                        st,pins {
+                                                oc-detect = <&pio18 0 ALT1 IN>;
+                                                pwr-enable = <&pio18 1 ALT1 OUT>;
+                                        };
+                                };
+                                pinctrl_usb2: usb2 {
+                                        st,pins {
+                                                oc-detect = <&pio18 2 ALT1 IN>;
+                                                pwr-enable = <&pio18 3 ALT1 OUT>;
                                        };
                                };
                        };
@@ -480,7 +553,7 @@
                        interrupt-names = "irqmux";
                        ranges          = <0 0xfd6b0000 0x3000>;
-                        PIO100: gpio@fd6b0000 {
+                        pio100: gpio@fd6b0000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -488,7 +561,7 @@
                                reg             = <0 0x100>;
                                st,bank-name    = "PIO100";
                        };
-                        PIO101: gpio@fd6b1000 {
+                        pio101: gpio@fd6b1000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -496,7 +569,7 @@
                                reg             = <0x1000 0x100>;
                                st,bank-name    = "PIO101";
                        };
-                        PIO102: gpio@fd6b2000 {
+                        pio102: gpio@fd6b2000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -517,7 +590,7 @@
                        interrupt-names = "irqmux";
                        ranges                  = <0 0xfd330000 0x5000>;
-                        PIO103: gpio@fd330000 {
+                        pio103: gpio@fd330000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -525,7 +598,7 @@
                                reg             = <0 0x100>;
                                st,bank-name    = "PIO103";
                        };
-                        PIO104: gpio@fd331000 {
+                        pio104: gpio@fd331000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -533,7 +606,7 @@
                                reg             = <0x1000 0x100>;
                                st,bank-name    = "PIO104";
                        };
-                        PIO105: gpio@fd332000 {
+                        pio105: gpio@fd332000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -541,7 +614,7 @@
                                reg             = <0x2000 0x100>;
                                st,bank-name    = "PIO105";
                        };
-                        PIO106: gpio@fd333000 {
+                        pio106: gpio@fd333000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
@@ -550,7 +623,7 @@
                                st,bank-name    = "PIO106";
                        };
-                        PIO107: gpio@fd334000 {
+                        pio107: gpio@fd334000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
                                interrupt-controller;
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 84758d76d064..fad9073ddeed 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -9,6 +9,8 @@
 #include "stih41x.dtsi"
 #include "stih416-clock.dtsi"
 #include "stih416-pinctrl.dtsi"
+#include <dt-bindings/phy/phy-miphy365x.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset-controller/stih416-resets.h>
 / {
@@ -236,5 +238,212 @@
                        resets  = <&powerdown STIH416_KEYSCAN_POWERDOWN>,
                                  <&softreset STIH416_KEYSCAN_SOFTRESET>;
                };
+                temp0 {
+                        compatible = "st,stih416-sas-thermal";
+                        clock-names = "thermal";
+                        clocks = <&clockgen_c_vcc 14>;
+                        status = "okay";
+                };
+                temp1@fdfe8000 {
+                        compatible = "st,stih416-mpe-thermal";
+                        reg = <0xfdfe8000 0x10>;
+                        clocks = <&clockgen_e 3>;
+                        clock-names = "thermal";
+                        interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
+                        status = "okay";
+                };
+                mmc0: sdhci@fe81e000 {
+                        compatible      = "st,sdhci";
+                        status          = "disabled";
+                        reg             = <0xfe81e000 0x1000>;
+                        interrupts      = <GIC_SPI 127 IRQ_TYPE_NONE>;
+                        interrupt-names = "mmcirq";
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_mmc0>;
+                        clock-names     = "mmc";
+                        clocks          = <&clk_s_a1_ls 1>;
+                };
+                mmc1: sdhci@fe81f000 {
+                        compatible      = "st,sdhci";
+                        status          = "disabled";
+                        reg             = <0xfe81f000 0x1000>;
+                        interrupts      = <GIC_SPI 128 IRQ_TYPE_NONE>;
+                        interrupt-names = "mmcirq";
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_mmc1>;
+                        clock-names     = "mmc";
+                        clocks          = <&clk_s_a1_ls 8>;
+                };
+                miphy365x_phy: phy@fe382000 {
+                        compatible      = "st,miphy365x-phy";
+                        st,syscfg       = <&syscfg_rear>;
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        ranges;
+                        phy_port0: port@fe382000 {
+                                #phy-cells = <1>;
+                                reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
+                                reg-names = "sata", "pcie", "syscfg";
+                        };
+                        phy_port1: port@fe38a000 {
+                                #phy-cells = <1>;
+                                reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
+                                reg-names = "sata", "pcie", "syscfg";
+                        };
+                };
+                sata0: sata@fe380000 {
+                        compatible      = "st,sti-ahci";
+                        reg             = <0xfe380000 0x1000>;
+                        interrupts      = <GIC_SPI 157 IRQ_TYPE_NONE>;
+                        interrupt-names = "hostc";
+                        phys            = <&phy_port0 MIPHY_TYPE_SATA>;
+                        phy-names       = "sata-phy";
+                        resets          = <&powerdown STIH416_SATA0_POWERDOWN>,
+                                          <&softreset STIH416_SATA0_SOFTRESET>;
+                        reset-names     = "pwr-dwn", "sw-rst";
+                        clock-names     = "ahci_clk";
+                        clocks          = <&clk_s_a0_ls CLK_ICN_REG>;
+                        status          = "disabled";
+                };
+                usb2_phy: phy@0 {
+                        compatible = "st,stih416-usb-phy";
+                        #phy-cells = <0>;
+                        st,syscfg = <&syscfg_rear>;
+                        clocks = <&clk_sysin>;
+                        clock-names = "osc_phy";
+                };
+                ehci0: usb@fe1ffe00 {
+                        compatible = "st,st-ehci-300x";
+                        reg = <0xfe1ffe00 0x100>;
+                        interrupts = <GIC_SPI 148 IRQ_TYPE_NONE>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usb0>;
+                        clocks = <&clk_s_a1_ls 0>,
+                                 <&clockgen_b0 0>;
+                        clock-names = "ic", "clk48";
+                        phys = <&usb2_phy>;
+                        phy-names = "usb";
+                        resets = <&powerdown STIH416_USB0_POWERDOWN>,
+                                 <&softreset STIH416_USB0_SOFTRESET>;
+                        reset-names = "power", "softreset";
+                };
+                ohci0: usb@fe1ffc00 {
+                        compatible = "st,st-ohci-300x";
+                        reg = <0xfe1ffc00 0x100>;
+                        interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>;
+                        clocks = <&clk_s_a1_ls 0>,
+                                 <&clockgen_b0 0>;
+                        clock-names = "ic", "clk48";
+                        phys = <&usb2_phy>;
+                        phy-names = "usb";
+                        status = "okay";
+                        resets = <&powerdown STIH416_USB0_POWERDOWN>,
+                                 <&softreset STIH416_USB0_SOFTRESET>;
+                        reset-names = "power", "softreset";
+                };
+                ehci1: usb@fe203e00 {
+                        compatible = "st,st-ehci-300x";
+                        reg = <0xfe203e00 0x100>;
+                        interrupts = <GIC_SPI 150 IRQ_TYPE_NONE>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usb1>;
+                        clocks = <&clk_s_a1_ls 0>,
+                                 <&clockgen_b0 0>;
+                        clock-names = "ic", "clk48";
+                        phys = <&usb2_phy>;
+                        phy-names = "usb";
+                        resets = <&powerdown STIH416_USB1_POWERDOWN>,
+                                 <&softreset STIH416_USB1_SOFTRESET>;
+                        reset-names = "power", "softreset";
+                };
+                ohci1: usb@fe203c00 {
+                        compatible = "st,st-ohci-300x";
+                        reg = <0xfe203c00 0x100>;
+                        interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
+                        clocks = <&clk_s_a1_ls 0>,
+                                 <&clockgen_b0 0>;
+                        clock-names = "ic", "clk48";
+                        phys = <&usb2_phy>;
+                        phy-names = "usb";
+                        resets = <&powerdown STIH416_USB1_POWERDOWN>,
+                                 <&softreset STIH416_USB1_SOFTRESET>;
+                        reset-names = "power", "softreset";
+                };
+                ehci2: usb@fe303e00 {
+                        compatible = "st,st-ehci-300x";
+                        reg = <0xfe303e00 0x100>;
+                        interrupts = <GIC_SPI 152 IRQ_TYPE_NONE>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usb2>;
+                        clocks = <&clk_s_a1_ls 0>,
+                                 <&clockgen_b0 0>;
+                        clock-names = "ic", "clk48";
+                        phys = <&usb2_phy>;
+                        phy-names = "usb";
+                        resets = <&powerdown STIH416_USB2_POWERDOWN>,
+                                 <&softreset STIH416_USB2_SOFTRESET>;
+                        reset-names = "power", "softreset";
+                };
+                ohci2: usb@fe303c00 {
+                        compatible = "st,st-ohci-300x";
+                        reg = <0xfe303c00 0x100>;
+                        interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
+                        clocks = <&clk_s_a1_ls 0>,
+                                 <&clockgen_b0 0>;
+                        clock-names = "ic", "clk48";
+                        phys = <&usb2_phy>;
+                        phy-names = "usb";
+                        resets = <&powerdown STIH416_USB2_POWERDOWN>,
+                                 <&softreset STIH416_USB2_SOFTRESET>;
+                        reset-names = "power", "softreset";
+                };
+                ehci3: usb@fe343e00 {
+                        compatible = "st,st-ehci-300x";
+                        reg = <0xfe343e00 0x100>;
+                        interrupts = <GIC_SPI 154 IRQ_TYPE_NONE>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usb3>;
+                        clocks = <&clk_s_a1_ls 0>,
+                                 <&clockgen_b0 0>;
+                        clock-names = "ic", "clk48";
+                        phys = <&usb2_phy>;
+                        phy-names = "usb";
+                        resets = <&powerdown STIH416_USB3_POWERDOWN>,
+                                 <&softreset STIH416_USB3_SOFTRESET>;
+                        reset-names = "power", "softreset";
+                };
+                ohci3: usb@fe343c00 {
+                        compatible = "st,st-ohci-300x";
+                        reg = <0xfe343c00 0x100>;
+                        interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
+                        clocks = <&clk_s_a1_ls 0>,
+                                 <&clockgen_b0 0>;
+                        clock-names = "ic", "clk48";
+                        phys = <&usb2_phy>;
+                        phy-names = "usb";
+                        resets = <&powerdown STIH416_USB3_POWERDOWN>,
+                                 <&softreset STIH416_USB3_SOFTRESET>;
+                        reset-names = "power", "softreset";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
index b3dd6ca5c2ae..5f91f455f05b 100644
--- a/arch/arm/boot/dts/stih41x-b2000.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2000.dtsi
@@ -35,7 +35,7 @@
                        fp_led {
                                #gpio-cells = <1>;
                                label   = "Front Panel LED";
-                                gpios   = <&PIO105 7>;
+                                gpios   = <&pio105 7>;
                                linux,default-trigger   = "heartbeat";
                        };
                };
@@ -55,7 +55,7 @@
                        phy-mode                = "mii";
                        pinctrl-0               = <&pinctrl_mii0>;
-                        snps,reset-gpio         = <&PIO106 2>;
+                        snps,reset-gpio         = <&pio106 2>;
                        snps,reset-active-low;
                        snps,reset-delays-us    = <0 10000 10000>;
                };
@@ -65,7 +65,7 @@
                        phy-mode                = "mii";
                        st,tx-retime-src        = "txclk";
-                        snps,reset-gpio         = <&PIO4 7>;
+                        snps,reset-gpio         = <&pio4 7>;
                        snps,reset-active-low;
                        snps,reset-delays-us    = <0 10000 10000>;
                };
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
index d8a84295c328..487d7d87dbef 100644
--- a/arch/arm/boot/dts/stih41x-b2020.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -32,11 +32,11 @@
                        red {
                                #gpio-cells = <1>;
                                label   = "Front Panel LED";
-                                gpios   = <&PIO4 1>;
+                                gpios   = <&pio4 1>;
                                linux,default-trigger   = "heartbeat";
                        };
                        green {
-                                gpios   = <&PIO4 7>;
+                                gpios   = <&pio4 7>;
                                default-state = "off";
                        };
                };
@@ -68,11 +68,15 @@
                        phy-mode                = "rgmii-id";
                        max-speed               = <1000>;
                        st,tx-retime-src        = "clk_125";
-                        snps,reset-gpio         = <&PIO3 0>;
+                        snps,reset-gpio         = <&pio3 0>;
                        snps,reset-active-low;
                        snps,reset-delays-us    = <0 10000 10000>;
                        pinctrl-0       = <&pinctrl_rgmii1>;
                };
+                mmc0: sdhci@fe81e000 {
+                        bus-width = <8>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/stih41x-b2020x.dtsi b/arch/arm/boot/dts/stih41x-b2020x.dtsi
index df01c1211b32..f797a0607382 100644
--- a/arch/arm/boot/dts/stih41x-b2020x.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2020x.dtsi
@@ -8,6 +8,10 @@
 */
 / {
        soc {
+                mmc0: sdhci@fe81e000 {
+                        status = "okay";
+                };
                spifsm: spifsm@fe902000 {
                        #address-cells = <1>;
                        #size-cells    = <1>;
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
new file mode 100644
index 000000000000..0074bd49797c
--- /dev/null
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics (R&D) Limited.
+ * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/ {
+        soc {
+                sbc_serial0: serial@9530000 {
+                        status = "okay";
+                };
+                leds {
+                        compatible = "gpio-leds";
+                        red {
+                                #gpio-cells = <2>;
+                                label = "Front Panel LED";
+                                gpios = <&pio4 1 0>;
+                                linux,default-trigger = "heartbeat";
+                        };
+                        green {
+                                #gpio-cells = <2>;
+                                gpios = <&pio1 3 0>;
+                                default-state = "off";
+                        };
+                };
+                i2c@9842000 {
+                        status = "okay";
+                };
+                i2c@9843000 {
+                        status = "okay";
+                };
+                i2c@9844000 {
+                        status = "okay";
+                };
+                i2c@9845000 {
+                        status = "okay";
+                };
+                i2c@9540000 {
+                        status = "okay";
+                };
+                /* SSC11 to HDMI */
+                i2c@9541000 {
+                        status = "okay";
+                        /* HDMI V1.3a supports Standard mode only */
+                        clock-frequency = <100000>;
+                        st,i2c-min-scl-pulse-width-us = <0>;
+                        st,i2c-min-sda-pulse-width-us = <5>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index 9e99ade35e37..3bcfd81837f0 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -3,12 +3,48 @@
 *
 * Emilio López <emilio@elopez.com.ar>
 *
- * The code contained herein is licensed under the GNU General Public
+ * This file is dual-licensed: you can use it either under the terms
- * License. You may obtain a copy of the GNU General Public License
+ * of the GPL or the X11 license, at your option. Note that this dual
- * Version 2 or later at the following locations:
+ * licensing only applies to this file, and not this project as a
+ * whole.
 *
- * http://www.opensource.org/licenses/gpl-license.html
+ *  a) This file is free software; you can redistribute it and/or
- * http://www.gnu.org/copyleft/gpl.html
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
index 1763cc7ec023..f3f2974658e4 100644
--- a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
+++ b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
@@ -1,12 +1,48 @@
 /*
 * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
 *
- * The code contained herein is licensed under the GNU General Public
+ * This file is dual-licensed: you can use it either under the terms
- * License. You may obtain a copy of the GNU General Public License
+ * of the GPL or the X11 license, at your option. Note that this dual
- * Version 2 or later at the following locations:
+ * licensing only applies to this file, and not this project as a
+ * whole.
 *
- * http://www.opensource.org/licenses/gpl-license.html
+ *  a) This file is free software; you can redistribute it and/or
- * http://www.gnu.org/copyleft/gpl.html
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 3ce56bfbc0b5..6a310da53f18 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -2,12 +2,48 @@
 * Copyright 2012 Stefan Roese
 * Stefan Roese <sr@denx.de>
 *
- * The code contained herein is licensed under the GNU General Public
+ * This file is dual-licensed: you can use it either under the terms
- * License. You may obtain a copy of the GNU General Public License
+ * of the GPL or the X11 license, at your option. Note that this dual
- * Version 2 or later at the following locations:
+ * licensing only applies to this file, and not this project as a
+ * whole.
 *
- * http://www.opensource.org/licenses/gpl-license.html
+ *  a) This file is free software; you can redistribute it and/or
- * http://www.gnu.org/copyleft/gpl.html
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index 891ea446abae..efc116287e0f 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -3,12 +3,48 @@
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
- * The code contained herein is licensed under the GNU General Public
+ * This file is dual-licensed: you can use it either under the terms
- * License. You may obtain a copy of the GNU General Public License
+ * of the GPL or the X11 license, at your option. Note that this dual
- * Version 2 or later at the following locations:
+ * licensing only applies to this file, and not this project as a
+ * whole.
 *
- * http://www.opensource.org/licenses/gpl-license.html
+ *  a) This file is free software; you can redistribute it and/or
- * http://www.gnu.org/copyleft/gpl.html
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
index 6b0c37812ade..3e25ee4d3248 100644
--- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
+++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
@@ -3,12 +3,48 @@
 *
 * David Lanzend�rfer <david.lanzendoerfer@o2s.ch>
 *
- * The code contained herein is licensed under the GNU General Public
+ * This file is dual-licensed: you can use it either under the terms
- * License. You may obtain a copy of the GNU General Public License
+ * of the GPL or the X11 license, at your option. Note that this dual
- * Version 2 or later at the following locations:
+ * licensing only applies to this file, and not this project as a
+ * whole.
 *
- * http://www.opensource.org/licenses/gpl-license.html
+ *  a) This file is free software; you can redistribute it and/or
- * http://www.gnu.org/copyleft/gpl.html
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
index b9ecce60f2e7..8b3f97470249 100644
--- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -3,12 +3,48 @@
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
- * The code contained herein is licensed under the GNU General Public
+ * This file is dual-licensed: you can use it either under the terms
- * License. You may obtain a copy of the GNU General Public License
+ * of the GPL or the X11 license, at your option. Note that this dual
- * Version 2 or later at the following locations:
+ * licensing only applies to this file, and not this project as a
+ * whole.
 *
- * http://www.opensource.org/licenses/gpl-license.html
+ *  a) This file is free software; you can redistribute it and/or
- * http://www.gnu.org/copyleft/gpl.html
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
index d046d568f5a1..88cf1a531155 100644
--- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
@@ -1,12 +1,48 @@
 /*
 * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
 *
- * The code contained herein is licensed under the GNU General Public
+ * This file is dual-licensed: you can use it either under the terms
- * License. You may obtain a copy of the GNU General Public License
+ * of the GPL or the X11 license, at your option. Note that this dual
- * Version 2 or later at the following locations:
+ * licensing only applies to this file, and not this project as a
+ * whole.
 *
- * http://www.opensource.org/licenses/gpl-license.html
+ *  a) This file is free software; you can redistribute it and/or
- * http://www.gnu.org/copyleft/gpl.html
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
index 6675bcd7860e..ce5994597407 100644
--- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts
+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
@@ -2,12 +2,48 @@
 * Copyright 2014 Zoltan HERPAI
 * Zoltan HERPAI <wigyori@uid0.hu>
 *
- * The code contained herein is licensed under the GNU General Public
+ * This file is dual-licensed: you can use it either under the terms
- * License. You may obtain a copy of the GNU General Public License
+ * of the GPL or the X11 license, at your option. Note that this dual
- * Version 2 or later at the following locations:
+ * licensing only applies to this file, and not this project as a
+ * whole.
 *
- * http://www.opensource.org/licenses/gpl-license.html
+ *  a) This file is free software; you can redistribute it and/or
- * http://www.gnu.org/copyleft/gpl.html
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 380f914b226d..e3ab942fd148 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -27,6 +27,20 @@
                serial7 = &uart7;
        };
+        chosen {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                framebuffer@0 {
+                        compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
+                        allwinner,pipeline = "de_be0-lcd0-hdmi";
+                        clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
+                                 <&ahb_gates 44>;
+                        status = "disabled";
+                };
+        };
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index ea9519da5764..fe3c559ca6a8 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -3,12 +3,48 @@
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
- * The code contained herein is licensed under the GNU General Public
+ * This file is dual-licensed: you can use it either under the terms
- * License. You may obtain a copy of the GNU General Public License
+ * of the GPL or the X11 license, at your option. Note that this dual
- * Version 2 or later at the following locations:
+ * licensing only applies to this file, and not this project as a
+ * whole.
 *
- * http://www.opensource.org/licenses/gpl-license.html
+ *  a) This file is free software; you can redistribute it and/or
- * http://www.gnu.org/copyleft/gpl.html
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
index 43a93762d4f2..1fa2916eafc2 100644
--- a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
@@ -1,12 +1,48 @@
 /*
 * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
 *
- * The code contained herein is licensed under the GNU General Public
+ * This file is dual-licensed: you can use it either under the terms
- * License. You may obtain a copy of the GNU General Public License
+ * of the GPL or the X11 license, at your option. Note that this dual
- * Version 2 or later at the following locations:
+ * licensing only applies to this file, and not this project as a
+ * whole.
 *
- * http://www.opensource.org/licenses/gpl-license.html
+ *  a) This file is free software; you can redistribute it and/or
- * http://www.gnu.org/copyleft/gpl.html
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 531272c0e526..81ad4b94e812 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -24,6 +24,20 @@
                serial3 = &uart3;
        };
+        chosen {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                framebuffer@0 {
+                        compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
+                        allwinner,pipeline = "de_be0-lcd0-hdmi";
+                        clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
+                                 <&ahb_gates 44>;
+                        status = "disabled";
+                };
+        };
        cpus {
                cpu@0 {
                        compatible = "arm,cortex-a8";
diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
index 8b3cd0907b32..eeed1f236ee8 100644
--- a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
+++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
@@ -6,18 +6,18 @@
 * licensing only applies to this file, and not this project as a
 * whole.
 *
- *  a) This library is free software; you can redistribute it and/or
+ *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
- *     This library is distributed in the hope that it will be useful,
+ *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 *     You should have received a copy of the GNU General Public
- *     License along with this library; if not, write to the Free
+ *     License along with this file; if not, write to the Free
 *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
 *     MA 02110-1301 USA
 *
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
index fa44b026483b..916ee8bb826f 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
@@ -1,15 +1,49 @@
 /*
- * Copyright 2012 Maxime Ripard
+ * Copyright 2012 Maxime Ripard <maxime.ripard@free-electrons.com>
 * Copyright 2013 Hans de Goede <hdegoede@redhat.com>
 *
- * Maxime Ripard <maxime.ripard@free-electrons.com>
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
 *
- * The code contained herein is licensed under the GNU General Public
+ *  a) This file is free software; you can redistribute it and/or
- * License. You may obtain a copy of the GNU General Public License
+ *     modify it under the terms of the GNU General Public License as
- * Version 2 or later at the following locations:
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
 *
- * http://www.opensource.org/licenses/gpl-license.html
+ *     This file is distributed in the hope that it will be useful,
- * http://www.gnu.org/copyleft/gpl.html
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 429994e1943e..e31d291d14cb 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -3,12 +3,48 @@
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
- * The code contained herein is licensed under the GNU General Public
+ * This file is dual-licensed: you can use it either under the terms
- * License. You may obtain a copy of the GNU General Public License
+ * of the GPL or the X11 license, at your option. Note that this dual
- * Version 2 or later at the following locations:
+ * licensing only applies to this file, and not this project as a
+ * whole.
 *
- * http://www.opensource.org/licenses/gpl-license.html
+ *  a) This file is free software; you can redistribute it and/or
- * http://www.gnu.org/copyleft/gpl.html
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts
index 2bbf8867362b..c74a63a39531 100644
--- a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts
+++ b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts
@@ -3,12 +3,48 @@
 *
 * Boris Brezillon <boris.brezillon@free-electrons.com>
 *
- * The code contained herein is licensed under the GNU General Public
+ * This file is dual-licensed: you can use it either under the terms
- * License. You may obtain a copy of the GNU General Public License
+ * of the GPL or the X11 license, at your option. Note that this dual
- * Version 2 or later at the following locations:
+ * licensing only applies to this file, and not this project as a
+ * whole.
 *
- * http://www.opensource.org/licenses/gpl-license.html
+ *  a) This file is free software; you can redistribute it and/or
- * http://www.gnu.org/copyleft/gpl.html
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts
index 546cf6eff5c7..c36b4dc89c13 100644
--- a/arch/arm/boot/dts/sun6i-a31-colombus.dts
+++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts
@@ -3,12 +3,48 @@
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
- * The code contained herein is licensed under the GNU General Public
+ * This file is dual-licensed: you can use it either under the terms
- * License. You may obtain a copy of the GNU General Public License
+ * of the GPL or the X11 license, at your option. Note that this dual
- * Version 2 or later at the following locations:
+ * licensing only applies to this file, and not this project as a
+ * whole.
 *
- * http://www.opensource.org/licenses/gpl-license.html
+ *  a) This file is free software; you can redistribute it and/or
- * http://www.gnu.org/copyleft/gpl.html
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
index f142065b3c1f..6e924d9d2912 100644
--- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
+++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
@@ -3,12 +3,48 @@
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
- * The code contained herein is licensed under the GNU General Public
+ * This file is dual-licensed: you can use it either under the terms
- * License. You may obtain a copy of the GNU General Public License
+ * of the GPL or the X11 license, at your option. Note that this dual
- * Version 2 or later at the following locations:
+ * licensing only applies to this file, and not this project as a
+ * whole.
 *
- * http://www.opensource.org/licenses/gpl-license.html
+ *  a) This file is free software; you can redistribute it and/or
- * http://www.gnu.org/copyleft/gpl.html
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts
index bc6115da5ae1..3ab544f3af4a 100644
--- a/arch/arm/boot/dts/sun6i-a31-m9.dts
+++ b/arch/arm/boot/dts/sun6i-a31-m9.dts
@@ -1,12 +1,48 @@
 /*
 * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
 *
- * The code contained herein is licensed under the GNU General Public
+ * This file is dual-licensed: you can use it either under the terms
- * License. You may obtain a copy of the GNU General Public License
+ * of the GPL or the X11 license, at your option. Note that this dual
- * Version 2 or later at the following locations:
+ * licensing only applies to this file, and not this project as a
+ * whole.
 *
- * http://www.opensource.org/licenses/gpl-license.html
+ *  a) This file is free software; you can redistribute it and/or
- * http://www.gnu.org/copyleft/gpl.html
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
@@ -32,13 +68,40 @@
                        status = "okay";
                };
+                usbphy: phy@01c19400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        status = "okay";
+                };
+                ehci0: usb@01c1a000 {
+                        status = "okay";
+                };
+                ehci1: usb@01c1b000 {
+                        status = "okay";
+                };
                pio: pinctrl@01c20800 {
+                        led_pins_m9: led_pins@0 {
+                                allwinner,pins = "PH13";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                        mmc0_cd_pin_m9: mmc0_cd_pin@0 {
                                allwinner,pins = "PH22";
                                allwinner,function = "gpio_in";
                                allwinner,drive = <0>;
                                allwinner,pull = <1>;
                        };
+                        usb1_vbus_pin_m9: usb1_vbus_pin@0 {
+                                allwinner,pins = "PC27";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                };
                uart0: serial@01c28000 {
@@ -46,5 +109,35 @@
                        pinctrl-0 = <&uart0_pins_a>;
                        status = "okay";
                };
+                gmac: ethernet@01c30000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&gmac_pins_mii_a>;
+                        phy = <&phy1>;
+                        phy-mode = "mii";
+                        status = "okay";
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_m9>;
+                blue {
+                        label = "m9:blue:usr";
+                        gpios = <&pio 7 13 0>;
+                };
+        };
+        reg_usb1_vbus: usb1-vbus {
+                pinctrl-names = "default";
+                pinctrl-0 = <&usb1_vbus_pin_m9>;
+                gpio = <&pio 2 27 0>;
+                status = "okay";
        };
 };
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 2e652e2339e9..a400172a8a52 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -8,18 +8,18 @@
 * licensing only applies to this file, and not this project as a
 * whole.
 *
- *  a) This library is free software; you can redistribute it and/or
+ *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
- *     This library is distributed in the hope that it will be useful,
+ *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 *     You should have received a copy of the GNU General Public
- *     License along with this library; if not, write to the Free
+ *     License along with this file; if not, write to the Free
 *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
 *     MA 02110-1301 USA
 *
@@ -62,6 +62,18 @@
                ethernet0 = &gmac;
        };
+        chosen {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                framebuffer@0 {
+                        compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
+                        allwinner,pipeline = "de_be0-lcd0-hdmi";
+                        clocks = <&pll6 0>;
+                        status = "disabled";
+                };
+        };
        cpus {
                enable-method = "allwinner,sun6i-a31";
@@ -132,11 +144,11 @@
                };
                pll6: clk@01c20028 {
-                        #clock-cells = <0>;
+                        #clock-cells = <1>;
                        compatible = "allwinner,sun6i-a31-pll6-clk";
                        reg = <0x01c20028 0x4>;
                        clocks = <&osc24M>;
-                        clock-output-names = "pll6";
+                        clock-output-names = "pll6", "pll6x2";
                };
                cpu: cpu@01c20050 {
@@ -166,7 +178,7 @@
                        #clock-cells = <0>;
                        compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
                        reg = <0x01c20054 0x4>;
-                        clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
+                        clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
                        clock-output-names = "ahb1_mux";
                };
@@ -221,7 +233,7 @@
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
-                        clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
+                        clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
                        clock-output-names = "apb2_mux";
                };
@@ -248,7 +260,7 @@
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20088 0x4>;
-                        clocks = <&osc24M>, <&pll6>;
+                        clocks = <&osc24M>, <&pll6 0>;
                        clock-output-names = "mmc0";
                };
@@ -256,7 +268,7 @@
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2008c 0x4>;
-                        clocks = <&osc24M>, <&pll6>;
+                        clocks = <&osc24M>, <&pll6 0>;
                        clock-output-names = "mmc1";
                };
@@ -264,7 +276,7 @@
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20090 0x4>;
-                        clocks = <&osc24M>, <&pll6>;
+                        clocks = <&osc24M>, <&pll6 0>;
                        clock-output-names = "mmc2";
                };
@@ -272,7 +284,7 @@
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20094 0x4>;
-                        clocks = <&osc24M>, <&pll6>;
+                        clocks = <&osc24M>, <&pll6 0>;
                        clock-output-names = "mmc3";
                };
@@ -280,7 +292,7 @@
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a0 0x4>;
-                        clocks = <&osc24M>, <&pll6>;
+                        clocks = <&osc24M>, <&pll6 0>;
                        clock-output-names = "spi0";
                };
@@ -288,7 +300,7 @@
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a4 0x4>;
-                        clocks = <&osc24M>, <&pll6>;
+                        clocks = <&osc24M>, <&pll6 0>;
                        clock-output-names = "spi1";
                };
@@ -296,7 +308,7 @@
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a8 0x4>;
-                        clocks = <&osc24M>, <&pll6>;
+                        clocks = <&osc24M>, <&pll6 0>;
                        clock-output-names = "spi2";
                };
@@ -304,7 +316,7 @@
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200ac 0x4>;
-                        clocks = <&osc24M>, <&pll6>;
+                        clocks = <&osc24M>, <&pll6 0>;
                        clock-output-names = "spi3";
                };
@@ -364,7 +376,7 @@
                        /* DMA controller requires AHB1 clocked from PLL6 */
                        assigned-clocks = <&ahb1_mux>;
-                        assigned-clock-parents = <&pll6>;
+                        assigned-clock-parents = <&pll6 0>;
                };
                mmc0: mmc@01c0f000 {
@@ -844,7 +856,7 @@
                        ar100: ar100_clk {
                                compatible = "allwinner,sun6i-a31-ar100-clk";
                                #clock-cells = <0>;
-                                clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
+                                clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
                                clock-output-names = "ar100";
                        };
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
new file mode 100644
index 000000000000..1cf1214cc068
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
@@ -0,0 +1,214 @@
+/*
+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+/include/ "sun7i-a20.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
+/ {
+        model = "LeMaker Banana Pi";
+        compatible = "lemaker,bananapi", "allwinner,sun7i-a20";
+        soc@01c00000 {
+                spi0: spi@01c05000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi0_pins_a>;
+                        status = "okay";
+                };
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 7 10 0>; /* PH10 */
+                        cd-inverted;
+                        status = "okay";
+                };
+                usbphy: phy@01c13400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        usb2_vbus-supply = <&reg_usb2_vbus>;
+                        status = "okay";
+                };
+                ehci0: usb@01c14000 {
+                        status = "okay";
+                };
+                ohci0: usb@01c14400 {
+                        status = "okay";
+                };
+                ahci: sata@01c18000 {
+                        status = "okay";
+                };
+                ehci1: usb@01c1c000 {
+                        status = "okay";
+                };
+                ohci1: usb@01c1c400 {
+                        status = "okay";
+                };
+                pinctrl@01c20800 {
+                        mmc0_cd_pin_bananapi: mmc0_cd_pin@0 {
+                                allwinner,pins = "PH10";
+                                allwinner,function = "gpio_in";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <1>;
+                        };
+                        gmac_power_pin_bananapi: gmac_power_pin@0 {
+                                allwinner,pins = "PH23";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        led_pins_bananapi: led_pins@0 {
+                                allwinner,pins = "PH24";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+                ir0: ir@01c21800 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&ir0_pins_a>;
+                        status = "okay";
+                };
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+                uart3: serial@01c28c00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart3_pins_b>;
+                        status = "okay";
+                };
+                uart7: serial@01c29c00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart7_pins_a>;
+                        status = "okay";
+                };
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+                        axp209: pmic@34 {
+                                compatible = "x-powers,axp209";
+                                reg = <0x34>;
+                                interrupt-parent = <&nmi_intc>;
+                                interrupts = <0 8>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                };
+                i2c2: i2c@01c2b400 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c2_pins_a>;
+                        status = "okay";
+                };
+                gmac: ethernet@01c50000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&gmac_pins_rgmii_a>;
+                        phy = <&phy1>;
+                        phy-mode = "rgmii";
+                        phy-supply = <&reg_gmac_3v3>;
+                        status = "okay";
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_bananapi>;
+                green {
+                        label = "bananapi:green:usr";
+                        gpios = <&pio 7 24 0>;
+                };
+        };
+        reg_usb1_vbus: usb1-vbus {
+                status = "okay";
+        };
+        reg_usb2_vbus: usb2-vbus {
+                status = "okay";
+        };
+        reg_gmac_3v3: gmac-3v3 {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&gmac_power_pin_bananapi>;
+                regulator-name = "gmac-3v3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                startup-delay-us = <100000>;
+                enable-active-high;
+                gpio = <&pio 7 23 0>;
+        };
+};
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index a6c1a3c717bc..a281d259b9b8 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -40,6 +40,7 @@
                };
                usbphy: phy@01c13400 {
+                        usb0_vbus-supply = <&reg_usb0_vbus>;
                        usb1_vbus-supply = <&reg_usb1_vbus>;
                        usb2_vbus-supply = <&reg_usb2_vbus>;
                        status = "okay";
@@ -92,6 +93,13 @@
                                allwinner,drive = <0>;
                                allwinner,pull = <0>;
                        };
+                        usb0_vbus_pin_a: usb0_vbus_pin@0 {
+                                allwinner,pins = "PH17";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                };
                pwm: pwm@01c20e00 {
@@ -185,6 +193,12 @@
                status = "okay";
        };
+        reg_usb0_vbus: usb0-vbus {
+                pinctrl-0 = <&usb0_vbus_pin_a>;
+                gpio = <&pio 7 17 0>;
+                status = "okay";
+        };
        reg_usb1_vbus: usb1-vbus {
                status = "okay";
        };
diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
index 6a67712d417a..f38bb1a6656c 100644
--- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
+++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
@@ -1,12 +1,48 @@
 /*
 * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
 *
- * The code contained herein is licensed under the GNU General Public
+ * This file is dual-licensed: you can use it either under the terms
- * License. You may obtain a copy of the GNU General Public License
+ * of the GPL or the X11 license, at your option. Note that this dual
- * Version 2 or later at the following locations:
+ * licensing only applies to this file, and not this project as a
+ * whole.
 *
- * http://www.opensource.org/licenses/gpl-license.html
+ *  a) This file is free software; you can redistribute it and/or
- * http://www.gnu.org/copyleft/gpl.html
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun7i-a20-m3.dts b/arch/arm/boot/dts/sun7i-a20-m3.dts
new file mode 100644
index 000000000000..b8e568c55271
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-m3.dts
@@ -0,0 +1,168 @@
+/*
+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+/include/ "sun7i-a20.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
+/ {
+        model = "Mele M3";
+        compatible = "mele,m3", "allwinner,sun7i-a20";
+        soc@01c00000 {
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 7 1 0>; /* PH1 */
+                        cd-inverted;
+                        status = "okay";
+                };
+                mmc2: mmc@01c11000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc2_pins_a>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        non-removable;
+                        status = "okay";
+                };
+                usbphy: phy@01c13400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        usb2_vbus-supply = <&reg_usb2_vbus>;
+                        status = "okay";
+                };
+                ehci0: usb@01c14000 {
+                        status = "okay";
+                };
+                ohci0: usb@01c14400 {
+                        status = "okay";
+                };
+                ehci1: usb@01c1c000 {
+                        status = "okay";
+                };
+                ohci1: usb@01c1c400 {
+                        status = "okay";
+                };
+                pinctrl@01c20800 {
+                        led_pins_m3: led_pins@0 {
+                                allwinner,pins = "PH20";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+                ir0: ir@01c21800 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&ir0_pins_a>;
+                        status = "okay";
+                };
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+                        axp209: pmic@34 {
+                                compatible = "x-powers,axp209";
+                                reg = <0x34>;
+                                interrupt-parent = <&nmi_intc>;
+                                interrupts = <0 8>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                };
+                gmac: ethernet@01c50000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&gmac_pins_mii_a>;
+                        phy = <&phy1>;
+                        phy-mode = "mii";
+                        status = "okay";
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_m3>;
+                blue {
+                        label = "m3:blue:usr";
+                        gpios = <&pio 7 20 0>;
+                };
+        };
+        reg_usb1_vbus: usb1-vbus {
+                status = "okay";
+        };
+        reg_usb2_vbus: usb2-vbus {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
index 1eb8175959a6..3f3ff9693992 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
@@ -4,12 +4,48 @@
 * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
 * Copyright (c) 2014 FUKAUMI Naoki <naobsd@gmail.com>
 *
- * The code contained herein is licensed under the GNU General Public
+ * This file is dual-licensed: you can use it either under the terms
- * License. You may obtain a copy of the GNU General Public License
+ * of the GPL or the X11 license, at your option. Note that this dual
- * Version 2 or later at the following locations:
+ * licensing only applies to this file, and not this project as a
+ * whole.
 *
- * http://www.opensource.org/licenses/gpl-license.html
+ *  a) This file is free software; you can redistribute it and/or
- * http://www.gnu.org/copyleft/gpl.html
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
new file mode 100644
index 000000000000..ed364d5e755e
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
@@ -0,0 +1,228 @@
+/*
+ * Copyright 2014 - Iain Paton <ipaton0@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+/include/ "sun7i-a20.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
+/ {
+        model = "Olimex A20-OLinuXino-LIME2";
+        compatible = "olimex,a20-olinuxino-lime2", "allwinner,sun7i-a20";
+        soc@01c00000 {
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 7 1 0>; /* PH1 */
+                        cd-inverted;
+                        status = "okay";
+                };
+                usbphy: phy@01c13400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        usb2_vbus-supply = <&reg_usb2_vbus>;
+                        status = "okay";
+                };
+                ehci0: usb@01c14000 {
+                        status = "okay";
+                };
+                ohci0: usb@01c14400 {
+                        status = "okay";
+                };
+                ahci: sata@01c18000 {
+                        target-supply = <&reg_ahci_5v>;
+                        status = "okay";
+                };
+                ehci1: usb@01c1c000 {
+                        status = "okay";
+                };
+                ohci1: usb@01c1c400 {
+                        status = "okay";
+                };
+                pinctrl@01c20800 {
+                        ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
+                                allwinner,pins = "PC3";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        led_pins_olinuxinolime: led_pins@0 {
+                                allwinner,pins = "PH2";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <1>;
+                                allwinner,pull = <0>;
+                        };
+                };
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+                        axp209: pmic@34 {
+                                compatible = "x-powers,axp209";
+                                reg = <0x34>;
+                                interrupt-parent = <&nmi_intc>;
+                                interrupts = <0 8>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                acin-supply = <&reg_axp_ipsout>;
+                                vin2-supply = <&reg_axp_ipsout>;
+                                vin3-supply = <&reg_axp_ipsout>;
+                                ldo24in-supply = <&reg_axp_ipsout>;
+                                ldo3in-supply = <&reg_axp_ipsout>;
+                                regulators {
+                                        vdd_rtc: ldo1 {
+                                                regulator-min-microvolt = <1300000>;
+                                                regulator-max-microvolt = <1300000>;
+                                                regulator-always-on;
+                                        };
+                                        avcc: ldo2 {
+                                                regulator-min-microvolt = <1800000>;
+                                                regulator-max-microvolt = <3300000>;
+                                                regulator-always-on;
+                                        };
+                                        vcc_csi0: ldo3 {
+                                                regulator-min-microvolt = <700000>;
+                                                regulator-max-microvolt = <3500000>;
+                                                regulator-always-on;
+                                        };
+                                        vcc_csi1: ldo4 {
+                                                regulator-min-microvolt = <1250000>;
+                                                regulator-max-microvolt = <3300000>;
+                                                regulator-always-on;
+                                        };
+                                        vdd_cpu: dcdc2 {
+                                                regulator-min-microvolt = <700000>;
+                                                regulator-max-microvolt = <2275000>;
+                                                regulator-always-on;
+                                        };
+                                        vdd_int: dcdc3 {
+                                                regulator-min-microvolt = <700000>;
+                                                regulator-max-microvolt = <3500000>;
+                                                regulator-always-on;
+                                        };
+                                };
+                        };
+                };
+                i2c1: i2c@01c2b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_pins_a>;
+                        status = "okay";
+                };
+                gmac: ethernet@01c50000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&gmac_pins_rgmii_a>;
+                        phy = <&phy1>;
+                        phy-mode = "rgmii";
+                        status = "okay";
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_olinuxinolime>;
+                green {
+                        label = "a20-olinuxino-lime2:green:usr";
+                        gpios = <&pio 7 2 0>;
+                        default-state = "on";
+                };
+        };
+        reg_ahci_5v: ahci-5v {
+                pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>;
+                gpio = <&pio 2 3 0>;
+                status = "okay";
+        };
+        reg_usb1_vbus: usb1-vbus {
+                status = "okay";
+        };
+        reg_usb2_vbus: usb2-vbus {
+                status = "okay";
+        };
+        reg_axp_ipsout: axp_ipsout {
+                compatible = "regulator-fixed";
+                regulator-name = "axp-ipsout";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+        };
+};
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
index 046dfc0d45d8..8dca49b2477b 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
@@ -2,12 +2,48 @@
 * Copyright 2014 Zoltan HERPAI
 * Zoltan HERPAI <wigyori@uid0.hu>
 *
- * The code contained herein is licensed under the GNU General Public
+ * This file is dual-licensed: you can use it either under the terms
- * License. You may obtain a copy of the GNU General Public License
+ * of the GPL or the X11 license, at your option. Note that this dual
- * Version 2 or later at the following locations:
+ * licensing only applies to this file, and not this project as a
+ * whole.
 *
- * http://www.opensource.org/licenses/gpl-license.html
+ *  a) This file is free software; you can redistribute it and/or
- * http://www.gnu.org/copyleft/gpl.html
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 82097c905c48..82a524ce28ad 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -8,18 +8,18 @@
 * licensing only applies to this file, and not this project as a
 * whole.
 *
- *  a) This library is free software; you can redistribute it and/or
+ *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
- *     This library is distributed in the hope that it will be useful,
+ *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 *     You should have received a copy of the GNU General Public
- *     License along with this library; if not, write to the Free
+ *     License along with this file; if not, write to the Free
 *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
 *     MA 02110-1301 USA
 *
@@ -64,6 +64,20 @@
                serial7 = &uart7;
        };
+        chosen {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                framebuffer@0 {
+                        compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
+                        allwinner,pipeline = "de_be0-lcd0-hdmi";
+                        clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
+                                 <&ahb_gates 44>;
+                        status = "disabled";
+                };
+        };
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -552,8 +566,8 @@
                        reg-names = "phy_ctrl", "pmu1", "pmu2";
                        clocks = <&usb_clk 8>;
                        clock-names = "usb_phy";
-                        resets = <&usb_clk 1>, <&usb_clk 2>;
+                        resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
-                        reset-names = "usb1_reset", "usb2_reset";
+                        reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
                        status = "disabled";
                };
@@ -677,6 +691,13 @@
                                allwinner,pull = <0>;
                        };
+                        uart3_pins_b: uart3@1 {
+                                allwinner,pins = "PH0", "PH1";
+                                allwinner,function = "uart3";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                        uart4_pins_a: uart4@0 {
                                allwinner,pins = "PG10", "PG11";
                                allwinner,function = "uart4";
@@ -784,6 +805,13 @@
                                allwinner,pull = <0>;
                        };
+                        spi0_pins_a: spi0@0 {
+                                allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14";
+                                allwinner,function = "spi0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                        spi1_pins_a: spi1@0 {
                                allwinner,pins = "PI16", "PI17", "PI18", "PI19";
                                allwinner,function = "spi1";
@@ -819,6 +847,13 @@
                                allwinner,pull = <1>;
                        };
+                        mmc2_pins_a: mmc2@0 {
+                                allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11";
+                                allwinner,function = "mmc2";
+                                allwinner,drive = <2>;
+                                allwinner,pull = <1>;
+                        };
                        mmc3_pins_a: mmc3@0 {
                                allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
                                allwinner,function = "mmc3";
diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
index e9b8cca8dcc1..7f2117ce6985 100644
--- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
+++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
@@ -3,12 +3,48 @@
 *
 * Chen-Yu Tsai <wens@csie.org>
 *
- * The code contained herein is licensed under the GNU General Public
+ * This file is dual-licensed: you can use it either under the terms
- * License. You may obtain a copy of the GNU General Public License
+ * of the GPL or the X11 license, at your option. Note that this dual
- * Version 2 or later at the following locations:
+ * licensing only applies to this file, and not this project as a
+ * whole.
 *
- * http://www.opensource.org/licenses/gpl-license.html
+ *  a) This file is free software; you can redistribute it and/or
- * http://www.gnu.org/copyleft/gpl.html
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 6146ef15efbe..6086adbf9d74 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -8,18 +8,18 @@
 * licensing only applies to this file, and not this project as a
 * whole.
 *
- *  a) This library is free software; you can redistribute it and/or
+ *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
- *     This library is distributed in the hope that it will be useful,
+ *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 *     You should have received a copy of the GNU General Public
- *     License along with this library; if not, write to the Free
+ *     License along with this file; if not, write to the Free
 *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
 *     MA 02110-1301 USA
 *
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
new file mode 100644
index 000000000000..506948f582ee
--- /dev/null
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2014 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+/include/ "sun9i-a80.dtsi"
+/ {
+        model = "Merrii A80 Optimus Board";
+        compatible = "merrii,a80-optimus", "allwinner,sun9i-a80";
+        chosen {
+                bootargs = "earlyprintk console=ttyS0,115200";
+        };
+        soc {
+                pio: pinctrl@06000800 {
+                        i2c3_pins_a: i2c3@0 {
+                                /* Enable internal pull-up */
+                                allwinner,pull = <1>;
+                        };
+                        led_pins_optimus: led-pins@0 {
+                                allwinner,pins = "PH0", "PH1";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        uart4_pins_a: uart4@0 {
+                                /* Enable internal pull-up */
+                                allwinner,pull = <1>;
+                        };
+                };
+                uart0: serial@07000000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+                uart4: serial@07001000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart4_pins_a>;
+                        status = "okay";
+                };
+                i2c3: i2c@07003400 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c3_pins_a>;
+                        status = "okay";
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_optimus>;
+                /* The LED names match those found on the board */
+                led2 {
+                        label = "optimus:led2:usr";
+                        gpios = <&pio 7 1 0>;
+                };
+                /* led3 is on PM15, in R_PIO */
+                led4 {
+                        label = "optimus:led4:usr";
+                        gpios = <&pio 7 0 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
new file mode 100644
index 000000000000..494714f67b57
--- /dev/null
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -0,0 +1,514 @@
+/*
+ * Copyright 2014 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+/include/ "skeleton64.dtsi"
+/ {
+        interrupt-parent = <&gic>;
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+                serial5 = &uart5;
+                serial6 = &r_uart;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu0: cpu@0 {
+                        compatible = "arm,cortex-a7";
+                        device_type = "cpu";
+                        reg = <0x0>;
+                };
+                cpu1: cpu@1 {
+                        compatible = "arm,cortex-a7";
+                        device_type = "cpu";
+                        reg = <0x1>;
+                };
+                cpu2: cpu@2 {
+                        compatible = "arm,cortex-a7";
+                        device_type = "cpu";
+                        reg = <0x2>;
+                };
+                cpu3: cpu@3 {
+                        compatible = "arm,cortex-a7";
+                        device_type = "cpu";
+                        reg = <0x3>;
+                };
+                cpu4: cpu@100 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <0x100>;
+                };
+                cpu5: cpu@101 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <0x101>;
+                };
+                cpu6: cpu@102 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <0x102>;
+                };
+                cpu7: cpu@103 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <0x103>;
+                };
+        };
+        memory {
+                /* 8GB max. with LPAE */
+                reg = <0 0x20000000 0x02 0>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                /*
+                 * map 64 bit address range down to 32 bits,
+                 * as the peripherals are all under 512MB.
+                 */
+                ranges = <0 0 0 0x20000000>;
+                osc24M: osc24M_clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <24000000>;
+                        clock-output-names = "osc24M";
+                };
+                osc32k: osc32k_clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                        clock-output-names = "osc32k";
+                };
+                pll4: clk@0600000c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun9i-a80-pll4-clk";
+                        reg = <0x0600000c 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll4";
+                };
+                pll12: clk@0600002c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun9i-a80-pll4-clk";
+                        reg = <0x0600002c 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll12";
+                };
+                gt_clk: clk@0600005c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun9i-a80-gt-clk";
+                        reg = <0x0600005c 0x4>;
+                        clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
+                        clock-output-names = "gt";
+                };
+                ahb0: clk@06000060 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun9i-a80-ahb-clk";
+                        reg = <0x06000060 0x4>;
+                        clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
+                        clock-output-names = "ahb0";
+                };
+                ahb1: clk@06000064 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun9i-a80-ahb-clk";
+                        reg = <0x06000064 0x4>;
+                        clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
+                        clock-output-names = "ahb1";
+                };
+                ahb2: clk@06000068 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun9i-a80-ahb-clk";
+                        reg = <0x06000068 0x4>;
+                        clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
+                        clock-output-names = "ahb2";
+                };
+                apb0: clk@06000070 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun9i-a80-apb0-clk";
+                        reg = <0x06000070 0x4>;
+                        clocks = <&osc24M>, <&pll4>;
+                        clock-output-names = "apb0";
+                };
+                apb1: clk@06000074 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun9i-a80-apb1-clk";
+                        reg = <0x06000074 0x4>;
+                        clocks = <&osc24M>, <&pll4>;
+                        clock-output-names = "apb1";
+                };
+                cci400_clk: clk@06000078 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun9i-a80-gt-clk";
+                        reg = <0x06000078 0x4>;
+                        clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
+                        clock-output-names = "cci400";
+                };
+                ahb0_gates: clk@06000580 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
+                        reg = <0x06000580 0x4>;
+                        clocks = <&ahb0>;
+                        clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
+                                        "ahb0_ss", "ahb0_sd", "ahb0_nand1",
+                                        "ahb0_nand0", "ahb0_sdram",
+                                        "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
+                                        "ahb0_spi0","ahb0_spi1", "ahb0_spi2",
+                                        "ahb0_spi3";
+                };
+                ahb1_gates: clk@06000584 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
+                        reg = <0x06000584 0x4>;
+                        clocks = <&ahb1>;
+                        clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
+                                        "ahb1_gmac", "ahb1_msgbox",
+                                        "ahb1_spinlock", "ahb1_hstimer",
+                                        "ahb1_dma";
+                };
+                ahb2_gates: clk@06000588 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
+                        reg = <0x06000588 0x4>;
+                        clocks = <&ahb2>;
+                        clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
+                                        "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
+                                        "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
+                };
+                apb0_gates: clk@06000590 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun9i-a80-apb0-gates-clk";
+                        reg = <0x06000590 0x4>;
+                        clocks = <&apb0>;
+                        clock-output-names = "apb0_spdif", "apb0_pio",
+                                        "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
+                                        "apb0_lradc", "apb0_gpadc", "apb0_twd",
+                                        "apb0_cirtx";
+                };
+                apb1_gates: clk@06000594 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun9i-a80-apb1-gates-clk";
+                        reg = <0x06000594 0x4>;
+                        clocks = <&apb1>;
+                        clock-output-names = "apb1_i2c0", "apb1_i2c1",
+                                        "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
+                                        "apb1_uart0", "apb1_uart1",
+                                        "apb1_uart2", "apb1_uart3",
+                                        "apb1_uart4", "apb1_uart5";
+                };
+        };
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                /*
+                 * map 64 bit address range down to 32 bits,
+                 * as the peripherals are all under 512MB.
+                 */
+                ranges = <0 0 0 0x20000000>;
+                gic: interrupt-controller@01c41000 {
+                        compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+                        reg = <0x01c41000 0x1000>,
+                              <0x01c42000 0x1000>,
+                              <0x01c44000 0x2000>,
+                              <0x01c46000 0x2000>;
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        interrupts = <1 9 0xf04>;
+                };
+                ahb0_resets: reset@060005a0 {
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-clock-reset";
+                        reg = <0x060005a0 0x4>;
+                };
+                ahb1_resets: reset@060005a4 {
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-clock-reset";
+                        reg = <0x060005a4 0x4>;
+                };
+                ahb2_resets: reset@060005a8 {
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-clock-reset";
+                        reg = <0x060005a8 0x4>;
+                };
+                apb0_resets: reset@060005b0 {
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-clock-reset";
+                        reg = <0x060005b0 0x4>;
+                };
+                apb1_resets: reset@060005b4 {
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-clock-reset";
+                        reg = <0x060005b4 0x4>;
+                };
+                timer@06000c00 {
+                        compatible = "allwinner,sun4i-a10-timer";
+                        reg = <0x06000c00 0xa0>;
+                        interrupts = <0 18 4>,
+                                     <0 19 4>,
+                                     <0 20 4>,
+                                     <0 21 4>,
+                                     <0 22 4>,
+                                     <0 23 4>;
+                        clocks = <&osc24M>;
+                };
+                pio: pinctrl@06000800 {
+                        compatible = "allwinner,sun9i-a80-pinctrl";
+                        reg = <0x06000800 0x400>;
+                        interrupts = <0 11 4>,
+                                     <0 15 4>,
+                                     <0 16 4>,
+                                     <0 17 4>,
+                                     <0 120 4>;
+                        clocks = <&apb0_gates 5>;
+                        gpio-controller;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        #size-cells = <0>;
+                        #gpio-cells = <3>;
+                        i2c3_pins_a: i2c3@0 {
+                                allwinner,pins = "PG10", "PG11";
+                                allwinner,function = "i2c3";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        uart0_pins_a: uart0@0 {
+                                allwinner,pins = "PH12", "PH13";
+                                allwinner,function = "uart0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        uart4_pins_a: uart4@0 {
+                                allwinner,pins = "PG12", "PG13", "PG14", "PG15";
+                                allwinner,function = "uart4";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+                uart0: serial@07000000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x07000000 0x400>;
+                        interrupts = <0 0 4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 16>;
+                        resets = <&apb1_resets 16>;
+                        status = "disabled";
+                };
+                uart1: serial@07000400 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x07000400 0x400>;
+                        interrupts = <0 1 4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 17>;
+                        resets = <&apb1_resets 17>;
+                        status = "disabled";
+                };
+                uart2: serial@07000800 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x07000800 0x400>;
+                        interrupts = <0 2 4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 18>;
+                        resets = <&apb1_resets 18>;
+                        status = "disabled";
+                };
+                uart3: serial@07000c00 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x07000c00 0x400>;
+                        interrupts = <0 3 4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 19>;
+                        resets = <&apb1_resets 19>;
+                        status = "disabled";
+                };
+                uart4: serial@07001000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x07001000 0x400>;
+                        interrupts = <0 4 4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 20>;
+                        resets = <&apb1_resets 20>;
+                        status = "disabled";
+                };
+                uart5: serial@07001400 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x07001400 0x400>;
+                        interrupts = <0 5 4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 21>;
+                        resets = <&apb1_resets 21>;
+                        status = "disabled";
+                };
+                i2c0: i2c@07002800 {
+                        compatible = "allwinner,sun6i-a31-i2c";
+                        reg = <0x07002800 0x400>;
+                        interrupts = <0 6 4>;
+                        clocks = <&apb1_gates 0>;
+                        resets = <&apb1_resets 0>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+                i2c1: i2c@07002c00 {
+                        compatible = "allwinner,sun6i-a31-i2c";
+                        reg = <0x07002c00 0x400>;
+                        interrupts = <0 7 4>;
+                        clocks = <&apb1_gates 1>;
+                        resets = <&apb1_resets 1>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+                i2c2: i2c@07003000 {
+                        compatible = "allwinner,sun6i-a31-i2c";
+                        reg = <0x07003000 0x400>;
+                        interrupts = <0 8 4>;
+                        clocks = <&apb1_gates 2>;
+                        resets = <&apb1_resets 2>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+                i2c3: i2c@07003400 {
+                        compatible = "allwinner,sun6i-a31-i2c";
+                        reg = <0x07003400 0x400>;
+                        interrupts = <0 9 4>;
+                        clocks = <&apb1_gates 3>;
+                        resets = <&apb1_resets 3>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+                i2c4: i2c@07003800 {
+                        compatible = "allwinner,sun6i-a31-i2c";
+                        reg = <0x07003800 0x400>;
+                        interrupts = <0 10 4>;
+                        clocks = <&apb1_gates 4>;
+                        resets = <&apb1_resets 4>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+                r_wdt: watchdog@08001000 {
+                        compatible = "allwinner,sun6i-a31-wdt";
+                        reg = <0x08001000 0x20>;
+                        interrupts = <0 36 4>;
+                };
+                r_uart: serial@08002800 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x08002800 0x400>;
+                        interrupts = <0 38 4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&osc24M>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
index c9c5b10e03eb..d8876634f965 100644
--- a/arch/arm/boot/dts/sunxi-common-regulators.dtsi
+++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
@@ -3,12 +3,48 @@
 *
 * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
 *
- * The code contained herein is licensed under the GNU General Public
+ * This file is dual-licensed: you can use it either under the terms
- * License. You may obtain a copy of the GNU General Public License
+ * of the GPL or the X11 license, at your option. Note that this dual
- * Version 2 or later at the following locations:
+ * licensing only applies to this file, and not this project as a
+ * whole.
 *
- * http://www.opensource.org/licenses/gpl-license.html
+ *  a) This file is free software; you can redistribute it and/or
- * http://www.gnu.org/copyleft/gpl.html
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 / {
@@ -21,6 +57,13 @@
                                allwinner,pull = <0>;
                        };
+                        usb0_vbus_pin_a: usb0_vbus_pin@0 {
+                                allwinner,pins = "PB9";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                        usb1_vbus_pin_a: usb1_vbus_pin@0 {
                                allwinner,pins = "PH6";
                                allwinner,function = "gpio_out";
@@ -44,11 +87,24 @@
                regulator-name = "ahci-5v";
                regulator-min-microvolt = <5000000>;
                regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
                enable-active-high;
                gpio = <&pio 1 8 0>;
                status = "disabled";
        };
+        reg_usb0_vbus: usb0-vbus {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&usb0_vbus_pin_a>;
+                regulator-name = "usb0-vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                enable-active-high;
+                gpio = <&pio 1 9 0>;
+                status = "disabled";
+        };
        reg_usb1_vbus: usb1-vbus {
                compatible = "regulator-fixed";
                pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index a1b682ea01bd..cbf5a1ae0ca7 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -189,7 +189,7 @@
                /* ALS and Proximity sensor */
                isl29028@44 {
-                        compatible = "isil,isl29028";
+                        compatible = "isl,isl29028";
                        reg = <0x44>;
                        interrupt-parent = <&gpio>;
                        interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
new file mode 100644
index 000000000000..56a452bc326c
--- /dev/null
+++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2014 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+/ {
+        chosen {
+                bootargs = "console=ttyLP0,115200";
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                sys_5v0_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+                /* USBH_PEN */
+                usbh_vbus_reg: regulator@1 {
+                        compatible = "regulator-fixed";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usbh1_reg>;
+                        reg = <1>;
+                        regulator-name = "usbh_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
+                        vin-supply = <&sys_5v0_reg>;
+                };
+        };
+};
+&bl {
+        brightness-levels = <0 4 8 16 32 64 128 255>;
+        default-brightness-level = <6>;
+        status  = "okay";
+};
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1>;
+        bus-width = <4>;
+        status = "okay";
+};
+&fec1 {
+        phy-mode = "rmii";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec1>;
+        status = "okay";
+};
+&i2c0 {
+        status = "okay";
+        /* M41T0M6 real time clock on carrier board */
+        rtc: m41t0m6@68 {
+                compatible = "st,m41t00";
+                reg = <0x68>;
+        };
+};
+&pwm0 {
+        status = "okay";
+};
+&pwm1 {
+        status = "okay";
+};
+&uart0 {
+        status = "okay";
+};
+&uart1 {
+        status = "okay";
+};
+&uart2 {
+        status = "okay";
+};
+&usbh1 {
+        vbus-supply = <&usbh_vbus_reg>;
+};
diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi
new file mode 100644
index 000000000000..82f5728be5c9
--- /dev/null
+++ b/arch/arm/boot/dts/vf-colibri.dtsi
@@ -0,0 +1,186 @@
+/*
+ * Copyright 2014 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+/ {
+        bl: backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm0 0 5000000 0>;
+                status = "disabled";
+        };
+};
+&adc0 {
+        status = "okay";
+};
+&adc1 {
+        status = "okay";
+};
+&edma0 {
+        status = "okay";
+};
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1>;
+        bus-width = <4>;
+        cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+};
+&fec1 {
+        phy-mode = "rmii";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec1>;
+};
+&i2c0 {
+        clock-frequency = <400000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c0>;
+};
+&pwm0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm0>;
+};
+&pwm1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm1>;
+};
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart0>;
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+};
+&usbdev0 {
+        disable-over-current;
+        status = "okay";
+};
+&usbh1 {
+        disable-over-current;
+        status = "okay";
+};
+&usbmisc0 {
+        status = "okay";
+};
+&usbmisc1 {
+        status = "okay";
+};
+&usbphy0 {
+        status = "okay";
+};
+&usbphy1 {
+        status = "okay";
+};
+&iomuxc {
+        vf610-colibri {
+                pinctrl_gpio_ext: gpio_ext {
+                        fsl,pins = <
+                                VF610_PAD_PTD10__GPIO_89        0x22ed /* EXT_IO_0 */
+                                VF610_PAD_PTD9__GPIO_88         0x22ed /* EXT_IO_1 */
+                                VF610_PAD_PTD26__GPIO_68        0x22ed /* EXT_IO_2 */
+                        >;
+                };
+                pinctrl_esdhc1: esdhc1grp {
+                        fsl,pins = <
+                                VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
+                                VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
+                                VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
+                                VF610_PAD_PTA27__ESDHC1_DAT1    0x31ef
+                                VF610_PAD_PTA28__ESDHC1_DATA2   0x31ef
+                                VF610_PAD_PTA29__ESDHC1_DAT3    0x31ef
+                                VF610_PAD_PTB20__GPIO_42        0x219d
+                        >;
+                };
+                pinctrl_fec1: fec1grp {
+                        fsl,pins = <
+                                VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
+                                VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
+                                VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
+                                VF610_PAD_PTC12__ENET_RMII_RXD1         0x30d1
+                                VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
+                                VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
+                                VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
+                                VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
+                                VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
+                        >;
+                };
+                pinctrl_i2c0: i2c0grp {
+                        fsl,pins = <
+                                VF610_PAD_PTB14__I2C0_SCL               0x37ff
+                                VF610_PAD_PTB15__I2C0_SDA               0x37ff
+                        >;
+                };
+                pinctrl_pwm0: pwm0grp {
+                        fsl,pins = <
+                                VF610_PAD_PTB0__FTM0_CH0                0x1182
+                                VF610_PAD_PTB1__FTM0_CH1                0x1182
+                        >;
+                };
+                pinctrl_pwm1: pwm1grp {
+                        fsl,pins = <
+                                VF610_PAD_PTB8__FTM1_CH0                0x1182
+                                VF610_PAD_PTB9__FTM1_CH1                0x1182
+                        >;
+                };
+                pinctrl_uart0: uart0grp {
+                        fsl,pins = <
+                                VF610_PAD_PTB10__UART0_TX               0x21a2
+                                VF610_PAD_PTB11__UART0_RX               0x21a1
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                VF610_PAD_PTB4__UART1_TX                0x21a2
+                                VF610_PAD_PTB5__UART1_RX                0x21a1
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                VF610_PAD_PTD0__UART2_TX                0x21a2
+                                VF610_PAD_PTD1__UART2_RX                0x21a1
+                                VF610_PAD_PTD2__UART2_RTS               0x21a2
+                                VF610_PAD_PTD3__UART2_CTS               0x21a1
+                        >;
+                };
+                pinctrl_usbh1_reg: gpio_usb_vbus {
+                        fsl,pins = <
+                                VF610_PAD_PTD4__GPIO_83                 0x22ed
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/vf500-colibri-eval-v3.dts b/arch/arm/boot/dts/vf500-colibri-eval-v3.dts
new file mode 100644
index 000000000000..7fc782c4fc52
--- /dev/null
+++ b/arch/arm/boot/dts/vf500-colibri-eval-v3.dts
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2014 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+/dts-v1/;
+#include "vf500-colibri.dtsi"
+#include "vf-colibri-eval-v3.dtsi"
+/ {
+        model = "Toradex Colibri VF50 on Colibri Evaluation Board";
+        compatible = "toradex,vf500-colibri_vf50-on-eval", "toradex,vf500-colibri_vf50", "fsl,vf500";
+};
diff --git a/arch/arm/boot/dts/vf500-colibri.dtsi b/arch/arm/boot/dts/vf500-colibri.dtsi
new file mode 100644
index 000000000000..cee34a32f25b
--- /dev/null
+++ b/arch/arm/boot/dts/vf500-colibri.dtsi
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2014 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include "vf500.dtsi"
+#include "vf-colibri.dtsi"
+/ {
+        model = "Toradex Colibri VF50 COM";
+        compatible = "toradex,vf610-colibri_vf50", "fsl,vf500";
+        memory {
+                reg = <0x80000000 0x8000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
new file mode 100644
index 000000000000..de6700542714
--- /dev/null
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -0,0 +1,171 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include "skeleton.dtsi"
+#include "vfxxx.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+/ {
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                a5_cpu: cpu@0 {
+                        compatible = "arm,cortex-a5";
+                        device_type = "cpu";
+                        reg = <0x0>;
+                };
+        };
+        soc {
+                interrupt-parent = <&intc>;
+                aips-bus@40000000 {
+                        intc: interrupt-controller@40002000 {
+                                compatible = "arm,cortex-a9-gic";
+                                #interrupt-cells = <3>;
+                                interrupt-controller;
+                                reg = <0x40003000 0x1000>,
+                                      <0x40002100 0x100>;
+                        };
+                        global_timer: timer@40002200 {
+                                compatible = "arm,cortex-a9-global-timer";
+                                reg = <0x40002200 0x20>;
+                                interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks VF610_CLK_PLATFORM_BUS>;
+                        };
+                };
+        };
+};
+&adc0 {
+        interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+};
+&adc1 {
+        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+};
+&can0 {
+        interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+};
+&can1 {
+        interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+};
+&dspi0 {
+        interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+};
+&edma0 {
+        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+                        <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "edma-tx", "edma-err";
+};
+&edma1 {
+        interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+                        <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "edma-tx", "edma-err";
+};
+&esdhc1 {
+        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+};
+&fec0 {
+        interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+};
+&fec1 {
+        interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+};
+&ftm {
+        interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+};
+&gpio1 {
+        interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+};
+&gpio2 {
+        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+};
+&gpio3 {
+        interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+};
+&gpio4 {
+        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+};
+&gpio5 {
+        interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+};
+&i2c0 {
+        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+};
+&pit {
+        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+};
+&qspi0 {
+        interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+};
+&sai2 {
+        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+};
+&uart0 {
+        interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+};
+&uart1 {
+        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+};
+&uart2 {
+        interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+};
+&uart3 {
+        interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+};
+&uart4 {
+        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+};
+&uart5 {
+        interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+};
+&usbdev0 {
+        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+};
+&usbh1 {
+        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+};
+&usbphy0 {
+        interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+};
+&usbphy1 {
+        interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts
index 7fb306679341..10ebe99e2751 100644
--- a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts
@@ -9,38 +9,9 @@
 /dts-v1/;
 #include "vf610-colibri.dtsi"
+#include "vf-colibri-eval-v3.dtsi"
 / {
        model = "Toradex Colibri VF61 on Colibri Evaluation Board";
        compatible = "toradex,vf610-colibri_vf61-on-eval", "toradex,vf610-colibri_vf61", "fsl,vf610";
+};
+\ No newline at end of file
-        chosen {
-                bootargs = "console=ttyLP0,115200";
-        };
-};
-&esdhc1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc1>;
-        bus-width = <4>;
-        status = "okay";
-};
-&fec1 {
-        phy-mode = "rmii";
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_fec1>;
-        status = "okay";
-};
-&uart0 {
-        status = "okay";
-};
-&uart1 {
-        status = "okay";
-};
-&uart2 {
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/vf610-colibri.dtsi b/arch/arm/boot/dts/vf610-colibri.dtsi
index 0cd83434b073..19fe045b8334 100644
--- a/arch/arm/boot/dts/vf610-colibri.dtsi
+++ b/arch/arm/boot/dts/vf610-colibri.dtsi
@@ -8,6 +8,7 @@
 */
 #include "vf610.dtsi"
+#include "vf-colibri.dtsi"
 / {
        model = "Toradex Colibri VF61 COM";
@@ -16,108 +17,9 @@
        memory {
                reg = <0x80000000 0x10000000>;
        };
-        clocks {
-                enet_ext {
-                        compatible = "fixed-clock";
-                        #clock-cells = <0>;
-                        clock-frequency = <50000000>;
-                };
-        };
-};
-&esdhc1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc1>;
-        bus-width = <4>;
-};
-&fec1 {
-        phy-mode = "rmii";
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_fec1>;
 };
 &L2 {
        arm,data-latency = <2 1 2>;
        arm,tag-latency = <3 2 3>;
 };
-&uart0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart0>;
-};
-&uart1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1>;
-};
-&uart2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart2>;
-};
-&usbdev0 {
-        disable-over-current;
-        status = "okay";
-};
-&usbh1 {
-        disable-over-current;
-        status = "okay";
-};
-&iomuxc {
-        vf610-colibri {
-                pinctrl_esdhc1: esdhc1grp {
-                        fsl,pins = <
-                                VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
-                                VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
-                                VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
-                                VF610_PAD_PTA27__ESDHC1_DAT1    0x31ef
-                                VF610_PAD_PTA28__ESDHC1_DATA2   0x31ef
-                                VF610_PAD_PTA29__ESDHC1_DAT3    0x31ef
-                                VF610_PAD_PTB20__GPIO_42        0x219d
-                        >;
-                };
-                pinctrl_fec1: fec1grp {
-                        fsl,pins = <
-                                VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
-                                VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
-                                VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
-                                VF610_PAD_PTC12__ENET_RMII_RXD1         0x30d1
-                                VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
-                                VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
-                                VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
-                                VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
-                                VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
-                        >;
-                };
-                pinctrl_uart0: uart0grp {
-                        fsl,pins = <
-                                VF610_PAD_PTB10__UART0_TX               0x21a2
-                                VF610_PAD_PTB11__UART0_RX               0x21a1
-                        >;
-                };
-                pinctrl_uart1: uart1grp {
-                        fsl,pins = <
-                                VF610_PAD_PTB4__UART1_TX                0x21a2
-                                VF610_PAD_PTB5__UART1_RX                0x21a1
-                        >;
-                };
-                pinctrl_uart2: uart2grp {
-                        fsl,pins = <
-                                VF610_PAD_PTD0__UART2_TX                0x21a2
-                                VF610_PAD_PTD1__UART2_RX                0x21a1
-                                VF610_PAD_PTD2__UART2_RTS               0x21a2
-                                VF610_PAD_PTD3__UART2_CTS               0x21a1
-                        >;
-                };
-        };
-};
diff --git a/arch/arm/boot/dts/vf610-cosmic.dts b/arch/arm/boot/dts/vf610-cosmic.dts
index de1b453c2932..fd8758b639f5 100644
--- a/arch/arm/boot/dts/vf610-cosmic.dts
+++ b/arch/arm/boot/dts/vf610-cosmic.dts
@@ -23,14 +23,16 @@
                reg = <0x80000000 0x10000000>;
        };
-        clocks {
+        enet_ext: enet_ext {
-                enet_ext {
+                compatible = "fixed-clock";
-                        compatible = "fixed-clock";
+                #clock-cells = <0>;
-                        #clock-cells = <0>;
+                clock-frequency = <50000000>;
-                        clock-frequency = <50000000>;
-                };
        };
+};
+&clks {
+        clocks = <&sxosc>, <&fxosc>, <&enet_ext>;
+        clock-names = "sxosc", "fxosc", "enet_ext";
 };
 &esdhc1 {
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index 189b6975fe7d..a0f762159cb2 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -22,18 +22,16 @@
                reg = <0x80000000 0x8000000>;
        };
-        clocks {
+        audio_ext: mclk_osc {
-                audio_ext {
+                compatible = "fixed-clock";
-                        compatible = "fixed-clock";
+                #clock-cells = <0>;
-                        #clock-cells = <0>;
+                clock-frequency = <24576000>;
-                        clock-frequency = <24576000>;
+        };
-                };
-                enet_ext {
+        enet_ext: eth_osc {
-                        compatible = "fixed-clock";
+                compatible = "fixed-clock";
-                        #clock-cells = <0>;
+                #clock-cells = <0>;
-                        clock-frequency = <50000000>;
+                clock-frequency = <50000000>;
-                };
        };
        regulators {
@@ -95,6 +93,11 @@
        status = "okay";
 };
+&clks {
+        clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>;
+        clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext";
+};
 &dspi0 {
        bus-num = <0>;
        pinctrl-names = "default";
@@ -112,10 +115,15 @@
        };
 };
+&edma0 {
+        status = "okay";
+};
 &esdhc1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_esdhc1>;
        bus-width = <4>;
+        cd-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
        status = "okay";
 };
@@ -285,3 +293,19 @@
        disable-over-current;
        status = "okay";
 };
+&usbmisc0 {
+        status = "okay";
+};
+&usbmisc1 {
+        status = "okay";
+};
+&usbphy0 {
+        status = "okay";
+};
+&usbphy1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
index 4d2ec32de96f..5f8eb1bd782b 100644
--- a/arch/arm/boot/dts/vf610.dtsi
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -7,481 +7,19 @@
 * (at your option) any later version.
 */
-#include "skeleton.dtsi"
+#include "vf500.dtsi"
-#include "vf610-pinfunc.h"
-#include <dt-bindings/clock/vf610-clock.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-/ {
+&a5_cpu {
-        aliases {
+        next-level-cache = <&L2>;
-                can0 = &can0;
+};
-                can1 = &can1;
-                serial0 = &uart0;
-                serial1 = &uart1;
-                serial2 = &uart2;
-                serial3 = &uart3;
-                serial4 = &uart4;
-                serial5 = &uart5;
-                gpio0 = &gpio1;
-                gpio1 = &gpio2;
-                gpio2 = &gpio3;
-                gpio3 = &gpio4;
-                gpio4 = &gpio5;
-                usbphy0 = &usbphy0;
-                usbphy1 = &usbphy1;
-        };
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                cpu@0 {
-                        compatible = "arm,cortex-a5";
-                        device_type = "cpu";
-                        reg = <0x0>;
-                        next-level-cache = <&L2>;
-                };
-        };
-        clocks {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                sxosc {
-                        compatible = "fixed-clock";
-                        #clock-cells = <0>;
-                        clock-frequency = <32768>;
-                };
-                fxosc {
-                        compatible = "fixed-clock";
-                        #clock-cells = <0>;
-                        clock-frequency = <24000000>;
-                };
-        };
-        soc {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "simple-bus";
-                interrupt-parent = <&intc>;
-                ranges;
-                aips0: aips-bus@40000000 {
-                        compatible = "fsl,aips-bus", "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        interrupt-parent = <&intc>;
-                        reg = <0x40000000 0x70000>;
-                        ranges;
-                        intc: interrupt-controller@40002000 {
-                                compatible = "arm,cortex-a9-gic";
-                                #interrupt-cells = <3>;
-                                interrupt-controller;
-                                reg = <0x40003000 0x1000>,
-                                      <0x40002100 0x100>;
-                        };
-                        L2: l2-cache@40006000 {
-                                compatible = "arm,pl310-cache";
-                                reg = <0x40006000 0x1000>;
-                                cache-unified;
-                                cache-level = <2>;
-                                arm,data-latency = <1 1 1>;
-                                arm,tag-latency = <2 2 2>;
-                        };
-                        edma0: dma-controller@40018000 {
-                                #dma-cells = <2>;
-                                compatible = "fsl,vf610-edma";
-                                reg = <0x40018000 0x2000>,
-                                        <0x40024000 0x1000>,
-                                        <0x40025000 0x1000>;
-                                interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
-                                                <0 9 IRQ_TYPE_LEVEL_HIGH>;
-                                interrupt-names = "edma-tx", "edma-err";
-                                dma-channels = <32>;
-                                clock-names = "dmamux0", "dmamux1";
-                                clocks = <&clks VF610_CLK_DMAMUX0>,
-                                        <&clks VF610_CLK_DMAMUX1>;
-                        };
-                        can0: flexcan@40020000 {
-                                compatible = "fsl,vf610-flexcan";
-                                reg = <0x40020000 0x4000>;
-                                interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_FLEXCAN0>,
-                                         <&clks VF610_CLK_FLEXCAN0>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
-                        uart0: serial@40027000 {
-                                compatible = "fsl,vf610-lpuart";
-                                reg = <0x40027000 0x1000>;
-                                interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_UART0>;
-                                clock-names = "ipg";
-                                dmas = <&edma0 0 2>,
-                                        <&edma0 0 3>;
-                                dma-names = "rx","tx";
-                                status = "disabled";
-                        };
-                        uart1: serial@40028000 {
-                                compatible = "fsl,vf610-lpuart";
-                                reg = <0x40028000 0x1000>;
-                                interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_UART1>;
-                                clock-names = "ipg";
-                                dmas = <&edma0 0 4>,
-                                        <&edma0 0 5>;
-                                dma-names = "rx","tx";
-                                status = "disabled";
-                        };
-                        uart2: serial@40029000 {
-                                compatible = "fsl,vf610-lpuart";
-                                reg = <0x40029000 0x1000>;
-                                interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_UART2>;
-                                clock-names = "ipg";
-                                dmas = <&edma0 0 6>,
-                                        <&edma0 0 7>;
-                                dma-names = "rx","tx";
-                                status = "disabled";
-                        };
-                        uart3: serial@4002a000 {
-                                compatible = "fsl,vf610-lpuart";
-                                reg = <0x4002a000 0x1000>;
-                                interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_UART3>;
-                                clock-names = "ipg";
-                                dmas = <&edma0 0 8>,
-                                        <&edma0 0 9>;
-                                dma-names = "rx","tx";
-                                status = "disabled";
-                        };
-                        dspi0: dspi0@4002c000 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,vf610-dspi";
-                                reg = <0x4002c000 0x1000>;
-                                interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_DSPI0>;
-                                clock-names = "dspi";
-                                spi-num-chipselects = <5>;
-                                status = "disabled";
-                        };
-                        sai2: sai@40031000 {
-                                compatible = "fsl,vf610-sai";
-                                reg = <0x40031000 0x1000>;
-                                interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_SAI2>;
-                                clock-names = "sai";
-                                dma-names = "tx", "rx";
-                                dmas = <&edma0 0 21>,
-                                        <&edma0 0 20>;
-                                status = "disabled";
-                        };
-                        pit: pit@40037000 {
-                                compatible = "fsl,vf610-pit";
-                                reg = <0x40037000 0x1000>;
-                                interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_PIT>;
-                                clock-names = "pit";
-                        };
-                        pwm0: pwm@40038000 {
-                                compatible = "fsl,vf610-ftm-pwm";
-                                #pwm-cells = <3>;
-                                reg = <0x40038000 0x1000>;
-                                clock-names = "ftm_sys", "ftm_ext",
-                                              "ftm_fix", "ftm_cnt_clk_en";
-                                clocks = <&clks VF610_CLK_FTM0>,
-                                        <&clks VF610_CLK_FTM0_EXT_SEL>,
-                                        <&clks VF610_CLK_FTM0_FIX_SEL>,
-                                        <&clks VF610_CLK_FTM0_EXT_FIX_EN>;
-                                status = "disabled";
-                        };
-                        adc0: adc@4003b000 {
-                                compatible = "fsl,vf610-adc";
-                                reg = <0x4003b000 0x1000>;
-                                interrupts = <0 53 0x04>;
-                                clocks = <&clks VF610_CLK_ADC0>;
-                                clock-names = "adc";
-                                status = "disabled";
-                        };
-                        wdog@4003e000 {
-                                compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
-                                reg = <0x4003e000 0x1000>;
-                                clocks = <&clks VF610_CLK_WDT>;
-                                clock-names = "wdog";
-                        };
-                        qspi0: quadspi@40044000 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,vf610-qspi";
-                                reg = <0x40044000 0x1000>;
-                                interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_QSPI0_EN>,
-                                        <&clks VF610_CLK_QSPI0>;
-                                clock-names = "qspi_en", "qspi";
-                                status = "disabled";
-                        };
-                        iomuxc: iomuxc@40048000 {
-                                compatible = "fsl,vf610-iomuxc";
-                                reg = <0x40048000 0x1000>;
-                                #gpio-range-cells = <3>;
-                        };
-                        gpio1: gpio@40049000 {
-                                compatible = "fsl,vf610-gpio";
-                                reg = <0x40049000 0x1000 0x400ff000 0x40>;
-                                interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                gpio-ranges = <&iomuxc 0 0 32>;
-                        };
-                        gpio2: gpio@4004a000 {
-                                compatible = "fsl,vf610-gpio";
-                                reg = <0x4004a000 0x1000 0x400ff040 0x40>;
-                                interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                gpio-ranges = <&iomuxc 0 32 32>;
-                        };
-                        gpio3: gpio@4004b000 {
-                                compatible = "fsl,vf610-gpio";
-                                reg = <0x4004b000 0x1000 0x400ff080 0x40>;
-                                interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                gpio-ranges = <&iomuxc 0 64 32>;
-                        };
-                        gpio4: gpio@4004c000 {
-                                compatible = "fsl,vf610-gpio";
-                                reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
-                                interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                gpio-ranges = <&iomuxc 0 96 32>;
-                        };
-                        gpio5: gpio@4004d000 {
-                                compatible = "fsl,vf610-gpio";
-                                reg = <0x4004d000 0x1000 0x400ff100 0x40>;
-                                interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                gpio-ranges = <&iomuxc 0 128 7>;
-                        };
-                        anatop: anatop@40050000 {
-                                compatible = "fsl,vf610-anatop", "syscon";
-                                reg = <0x40050000 0x400>;
-                        };
-                        usbphy0: usbphy@40050800 {
-                                compatible = "fsl,vf610-usbphy";
-                                reg = <0x40050800 0x400>;
-                                interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_USBPHY0>;
-                                fsl,anatop = <&anatop>;
-                        };
-                        usbphy1: usbphy@40050c00 {
-                                compatible = "fsl,vf610-usbphy";
-                                reg = <0x40050c00 0x400>;
-                                interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_USBPHY1>;
-                                fsl,anatop = <&anatop>;
-                        };
-                        i2c0: i2c@40066000 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,vf610-i2c";
-                                reg = <0x40066000 0x1000>;
-                                interrupts =<0 71 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_I2C0>;
-                                clock-names = "ipg";
-                                dmas = <&edma0 0 50>,
-                                        <&edma0 0 51>;
-                                dma-names = "rx","tx";
-                                status = "disabled";
-                        };
-                        clks: ccm@4006b000 {
-                                compatible = "fsl,vf610-ccm";
-                                reg = <0x4006b000 0x1000>;
-                                #clock-cells = <1>;
-                        };
-                        usbdev0: usb@40034000 {
-                                compatible = "fsl,vf610-usb", "fsl,imx27-usb";
-                                reg = <0x40034000 0x800>;
-                                interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_USBC0>;
-                                fsl,usbphy = <&usbphy0>;
-                                fsl,usbmisc = <&usbmisc0 0>;
-                                dr_mode = "peripheral";
-                                status = "disabled";
-                        };
-                        usbmisc0: usb@40034800 {
-                                #index-cells = <1>;
-                                compatible = "fsl,vf610-usbmisc";
-                                reg = <0x40034800 0x200>;
-                                clocks = <&clks VF610_CLK_USBC0>;
-                        };
-                };
-                aips1: aips-bus@40080000 {
-                        compatible = "fsl,aips-bus", "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        reg = <0x40080000 0x80000>;
-                        ranges;
-                        edma1: dma-controller@40098000 {
-                                #dma-cells = <2>;
-                                compatible = "fsl,vf610-edma";
-                                reg = <0x40098000 0x2000>,
-                                        <0x400a1000 0x1000>,
-                                        <0x400a2000 0x1000>;
-                                interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>,
-                                                <0 11 IRQ_TYPE_LEVEL_HIGH>;
-                                interrupt-names = "edma-tx", "edma-err";
-                                dma-channels = <32>;
-                                clock-names = "dmamux0", "dmamux1";
-                                clocks = <&clks VF610_CLK_DMAMUX2>,
-                                        <&clks VF610_CLK_DMAMUX3>;
-                        };
-                        uart4: serial@400a9000 {
-                                compatible = "fsl,vf610-lpuart";
-                                reg = <0x400a9000 0x1000>;
-                                interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_UART4>;
-                                clock-names = "ipg";
-                                status = "disabled";
-                        };
-                        uart5: serial@400aa000 {
-                                compatible = "fsl,vf610-lpuart";
-                                reg = <0x400aa000 0x1000>;
-                                interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_UART5>;
-                                clock-names = "ipg";
-                                status = "disabled";
-                        };
-                        adc1: adc@400bb000 {
-                                compatible = "fsl,vf610-adc";
-                                reg = <0x400bb000 0x1000>;
-                                interrupts = <0 54 0x04>;
-                                clocks = <&clks VF610_CLK_ADC1>;
-                                clock-names = "adc";
-                                status = "disabled";
-                        };
-                        esdhc1: esdhc@400b2000 {
-                                compatible = "fsl,imx53-esdhc";
-                                reg = <0x400b2000 0x1000>;
-                                interrupts = <0 28 0x04>;
-                                clocks = <&clks VF610_CLK_IPG_BUS>,
-                                        <&clks VF610_CLK_PLATFORM_BUS>,
-                                        <&clks VF610_CLK_ESDHC1>;
-                                clock-names = "ipg", "ahb", "per";
-                                status = "disabled";
-                        };
-                        usbh1: usb@400b4000 {
-                                compatible = "fsl,vf610-usb", "fsl,imx27-usb";
-                                reg = <0x400b4000 0x800>;
-                                interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_USBC1>;
-                                fsl,usbphy = <&usbphy1>;
-                                fsl,usbmisc = <&usbmisc1 0>;
-                                dr_mode = "host";
-                                status = "disabled";
-                        };
-                        usbmisc1: usb@400b4800 {
-                                #index-cells = <1>;
-                                compatible = "fsl,vf610-usbmisc";
-                                reg = <0x400b4800 0x200>;
-                                clocks = <&clks VF610_CLK_USBC1>;
-                        };
-                        ftm: ftm@400b8000 {
-                                compatible = "fsl,ftm-timer";
-                                reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
-                                interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
-                                clock-names = "ftm-evt", "ftm-src",
-                                        "ftm-evt-counter-en", "ftm-src-counter-en";
-                                clocks = <&clks VF610_CLK_FTM2>,
-                                        <&clks VF610_CLK_FTM3>,
-                                        <&clks VF610_CLK_FTM2_EXT_FIX_EN>,
-                                        <&clks VF610_CLK_FTM3_EXT_FIX_EN>;
-                                status = "disabled";
-                        };
-                        fec0: ethernet@400d0000 {
-                                compatible = "fsl,mvf600-fec";
-                                reg = <0x400d0000 0x1000>;
-                                interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_ENET0>,
-                                        <&clks VF610_CLK_ENET0>,
-                                        <&clks VF610_CLK_ENET>;
-                                clock-names = "ipg", "ahb", "ptp";
-                                status = "disabled";
-                        };
-                        fec1: ethernet@400d1000 {
-                                compatible = "fsl,mvf600-fec";
-                                reg = <0x400d1000 0x1000>;
-                                interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_ENET1>,
-                                        <&clks VF610_CLK_ENET1>,
-                                        <&clks VF610_CLK_ENET>;
-                                clock-names = "ipg", "ahb", "ptp";
-                                status = "disabled";
-                        };
-                        can1: flexcan@400d4000 {
-                                compatible = "fsl,vf610-flexcan";
-                                reg = <0x400d4000 0x4000>;
-                                interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_FLEXCAN1>,
-                                         <&clks VF610_CLK_FLEXCAN1>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
-                };
+&aips0 {
+        L2: l2-cache@40006000 {
+                compatible = "arm,pl310-cache";
+                reg = <0x40006000 0x1000>;
+                cache-unified;
+                cache-level = <2>;
+                arm,data-latency = <1 1 1>;
+                arm,tag-latency = <2 2 2>;
        };
 };
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
new file mode 100644
index 000000000000..505969ae8093
--- /dev/null
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -0,0 +1,437 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include "vf610-pinfunc.h"
+#include <dt-bindings/clock/vf610-clock.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+/ {
+        aliases {
+                can0 = &can0;
+                can1 = &can1;
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+                serial5 = &uart5;
+                gpio0 = &gpio1;
+                gpio1 = &gpio2;
+                gpio2 = &gpio3;
+                gpio3 = &gpio4;
+                gpio4 = &gpio5;
+                usbphy0 = &usbphy0;
+                usbphy1 = &usbphy1;
+        };
+        fxosc: fxosc {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <24000000>;
+        };
+        sxosc: sxosc {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <32768>;
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+                aips0: aips-bus@40000000 {
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        edma0: dma-controller@40018000 {
+                                #dma-cells = <2>;
+                                compatible = "fsl,vf610-edma";
+                                reg = <0x40018000 0x2000>,
+                                        <0x40024000 0x1000>,
+                                        <0x40025000 0x1000>;
+                                dma-channels = <32>;
+                                clock-names = "dmamux0", "dmamux1";
+                                clocks = <&clks VF610_CLK_DMAMUX0>,
+                                        <&clks VF610_CLK_DMAMUX1>;
+                                status = "disabled";
+                        };
+                        can0: flexcan@40020000 {
+                                compatible = "fsl,vf610-flexcan";
+                                reg = <0x40020000 0x4000>;
+                                clocks = <&clks VF610_CLK_FLEXCAN0>,
+                                         <&clks VF610_CLK_FLEXCAN0>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+                        uart0: serial@40027000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x40027000 0x1000>;
+                                clocks = <&clks VF610_CLK_UART0>;
+                                clock-names = "ipg";
+                                dmas = <&edma0 0 2>,
+                                        <&edma0 0 3>;
+                                dma-names = "rx","tx";
+                                status = "disabled";
+                        };
+                        uart1: serial@40028000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x40028000 0x1000>;
+                                clocks = <&clks VF610_CLK_UART1>;
+                                clock-names = "ipg";
+                                dmas = <&edma0 0 4>,
+                                        <&edma0 0 5>;
+                                dma-names = "rx","tx";
+                                status = "disabled";
+                        };
+                        uart2: serial@40029000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x40029000 0x1000>;
+                                clocks = <&clks VF610_CLK_UART2>;
+                                clock-names = "ipg";
+                                dmas = <&edma0 0 6>,
+                                        <&edma0 0 7>;
+                                dma-names = "rx","tx";
+                                status = "disabled";
+                        };
+                        uart3: serial@4002a000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x4002a000 0x1000>;
+                                clocks = <&clks VF610_CLK_UART3>;
+                                clock-names = "ipg";
+                                dmas = <&edma0 0 8>,
+                                        <&edma0 0 9>;
+                                dma-names = "rx","tx";
+                                status = "disabled";
+                        };
+                        dspi0: dspi0@4002c000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,vf610-dspi";
+                                reg = <0x4002c000 0x1000>;
+                                clocks = <&clks VF610_CLK_DSPI0>;
+                                clock-names = "dspi";
+                                spi-num-chipselects = <5>;
+                                status = "disabled";
+                        };
+                        sai2: sai@40031000 {
+                                compatible = "fsl,vf610-sai";
+                                reg = <0x40031000 0x1000>;
+                                clocks = <&clks VF610_CLK_SAI2>;
+                                clock-names = "sai";
+                                dma-names = "tx", "rx";
+                                dmas = <&edma0 0 21>,
+                                        <&edma0 0 20>;
+                                status = "disabled";
+                        };
+                        pit: pit@40037000 {
+                                compatible = "fsl,vf610-pit";
+                                reg = <0x40037000 0x1000>;
+                                clocks = <&clks VF610_CLK_PIT>;
+                                clock-names = "pit";
+                        };
+                        pwm0: pwm@40038000 {
+                                compatible = "fsl,vf610-ftm-pwm";
+                                #pwm-cells = <3>;
+                                reg = <0x40038000 0x1000>;
+                                clock-names = "ftm_sys", "ftm_ext",
+                                              "ftm_fix", "ftm_cnt_clk_en";
+                                clocks = <&clks VF610_CLK_FTM0>,
+                                        <&clks VF610_CLK_FTM0_EXT_SEL>,
+                                        <&clks VF610_CLK_FTM0_FIX_SEL>,
+                                        <&clks VF610_CLK_FTM0_EXT_FIX_EN>;
+                                status = "disabled";
+                        };
+                        pwm1: pwm@40039000 {
+                                compatible = "fsl,vf610-ftm-pwm";
+                                #pwm-cells = <3>;
+                                reg = <0x40039000 0x1000>;
+                                clock-names = "ftm_sys", "ftm_ext",
+                                              "ftm_fix", "ftm_cnt_clk_en";
+                                clocks = <&clks VF610_CLK_FTM1>,
+                                        <&clks VF610_CLK_FTM1_EXT_SEL>,
+                                        <&clks VF610_CLK_FTM1_FIX_SEL>,
+                                        <&clks VF610_CLK_FTM1_EXT_FIX_EN>;
+                                status = "disabled";
+                        };
+                        adc0: adc@4003b000 {
+                                compatible = "fsl,vf610-adc";
+                                reg = <0x4003b000 0x1000>;
+                                clocks = <&clks VF610_CLK_ADC0>;
+                                clock-names = "adc";
+                                status = "disabled";
+                        };
+                        wdog@4003e000 {
+                                compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
+                                reg = <0x4003e000 0x1000>;
+                                clocks = <&clks VF610_CLK_WDT>;
+                                clock-names = "wdog";
+                                status = "disabled";
+                        };
+                        qspi0: quadspi@40044000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,vf610-qspi";
+                                reg = <0x40044000 0x1000>;
+                                clocks = <&clks VF610_CLK_QSPI0_EN>,
+                                        <&clks VF610_CLK_QSPI0>;
+                                clock-names = "qspi_en", "qspi";
+                                status = "disabled";
+                        };
+                        iomuxc: iomuxc@40048000 {
+                                compatible = "fsl,vf610-iomuxc";
+                                reg = <0x40048000 0x1000>;
+                                #gpio-range-cells = <3>;
+                        };
+                        gpio1: gpio@40049000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x40049000 0x1000 0x400ff000 0x40>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 0 32>;
+                        };
+                        gpio2: gpio@4004a000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x4004a000 0x1000 0x400ff040 0x40>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 32 32>;
+                        };
+                        gpio3: gpio@4004b000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x4004b000 0x1000 0x400ff080 0x40>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 64 32>;
+                        };
+                        gpio4: gpio@4004c000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 96 32>;
+                        };
+                        gpio5: gpio@4004d000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x4004d000 0x1000 0x400ff100 0x40>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 128 7>;
+                        };
+                        anatop: anatop@40050000 {
+                                compatible = "fsl,vf610-anatop", "syscon";
+                                reg = <0x40050000 0x400>;
+                        };
+                        usbphy0: usbphy@40050800 {
+                                compatible = "fsl,vf610-usbphy";
+                                reg = <0x40050800 0x400>;
+                                clocks = <&clks VF610_CLK_USBPHY0>;
+                                fsl,anatop = <&anatop>;
+                                status = "disabled";
+                        };
+                        usbphy1: usbphy@40050c00 {
+                                compatible = "fsl,vf610-usbphy";
+                                reg = <0x40050c00 0x400>;
+                                clocks = <&clks VF610_CLK_USBPHY1>;
+                                fsl,anatop = <&anatop>;
+                                status = "disabled";
+                        };
+                        i2c0: i2c@40066000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,vf610-i2c";
+                                reg = <0x40066000 0x1000>;
+                                clocks = <&clks VF610_CLK_I2C0>;
+                                clock-names = "ipg";
+                                dmas = <&edma0 0 50>,
+                                        <&edma0 0 51>;
+                                dma-names = "rx","tx";
+                                status = "disabled";
+                        };
+                        clks: ccm@4006b000 {
+                                compatible = "fsl,vf610-ccm";
+                                reg = <0x4006b000 0x1000>;
+                                clocks = <&sxosc>, <&fxosc>;
+                                clock-names = "sxosc", "fxosc";
+                                #clock-cells = <1>;
+                        };
+                        usbdev0: usb@40034000 {
+                                compatible = "fsl,vf610-usb", "fsl,imx27-usb";
+                                reg = <0x40034000 0x800>;
+                                clocks = <&clks VF610_CLK_USBC0>;
+                                fsl,usbphy = <&usbphy0>;
+                                fsl,usbmisc = <&usbmisc0 0>;
+                                dr_mode = "peripheral";
+                                status = "disabled";
+                        };
+                        usbmisc0: usb@40034800 {
+                                #index-cells = <1>;
+                                compatible = "fsl,vf610-usbmisc";
+                                reg = <0x40034800 0x200>;
+                                clocks = <&clks VF610_CLK_USBC0>;
+                                status = "disabled";
+                        };
+                };
+                aips1: aips-bus@40080000 {
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        edma1: dma-controller@40098000 {
+                                #dma-cells = <2>;
+                                compatible = "fsl,vf610-edma";
+                                reg = <0x40098000 0x2000>,
+                                        <0x400a1000 0x1000>,
+                                        <0x400a2000 0x1000>;
+                                dma-channels = <32>;
+                                clock-names = "dmamux0", "dmamux1";
+                                clocks = <&clks VF610_CLK_DMAMUX2>,
+                                        <&clks VF610_CLK_DMAMUX3>;
+                                status = "disabled";
+                        };
+                        uart4: serial@400a9000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x400a9000 0x1000>;
+                                clocks = <&clks VF610_CLK_UART4>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+                        uart5: serial@400aa000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x400aa000 0x1000>;
+                                clocks = <&clks VF610_CLK_UART5>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+                        adc1: adc@400bb000 {
+                                compatible = "fsl,vf610-adc";
+                                reg = <0x400bb000 0x1000>;
+                                clocks = <&clks VF610_CLK_ADC1>;
+                                clock-names = "adc";
+                                status = "disabled";
+                        };
+                        esdhc1: esdhc@400b2000 {
+                                compatible = "fsl,imx53-esdhc";
+                                reg = <0x400b2000 0x1000>;
+                                clocks = <&clks VF610_CLK_IPG_BUS>,
+                                        <&clks VF610_CLK_PLATFORM_BUS>,
+                                        <&clks VF610_CLK_ESDHC1>;
+                                clock-names = "ipg", "ahb", "per";
+                                status = "disabled";
+                        };
+                        usbh1: usb@400b4000 {
+                                compatible = "fsl,vf610-usb", "fsl,imx27-usb";
+                                reg = <0x400b4000 0x800>;
+                                clocks = <&clks VF610_CLK_USBC1>;
+                                fsl,usbphy = <&usbphy1>;
+                                fsl,usbmisc = <&usbmisc1 0>;
+                                dr_mode = "host";
+                                status = "disabled";
+                        };
+                        usbmisc1: usb@400b4800 {
+                                #index-cells = <1>;
+                                compatible = "fsl,vf610-usbmisc";
+                                reg = <0x400b4800 0x200>;
+                                clocks = <&clks VF610_CLK_USBC1>;
+                                status = "disabled";
+                        };
+                        ftm: ftm@400b8000 {
+                                compatible = "fsl,ftm-timer";
+                                reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
+                                clock-names = "ftm-evt", "ftm-src",
+                                        "ftm-evt-counter-en", "ftm-src-counter-en";
+                                clocks = <&clks VF610_CLK_FTM2>,
+                                        <&clks VF610_CLK_FTM3>,
+                                        <&clks VF610_CLK_FTM2_EXT_FIX_EN>,
+                                        <&clks VF610_CLK_FTM3_EXT_FIX_EN>;
+                                status = "disabled";
+                        };
+                        fec0: ethernet@400d0000 {
+                                compatible = "fsl,mvf600-fec";
+                                reg = <0x400d0000 0x1000>;
+                                clocks = <&clks VF610_CLK_ENET0>,
+                                        <&clks VF610_CLK_ENET0>,
+                                        <&clks VF610_CLK_ENET>;
+                                clock-names = "ipg", "ahb", "ptp";
+                                status = "disabled";
+                        };
+                        fec1: ethernet@400d1000 {
+                                compatible = "fsl,mvf600-fec";
+                                reg = <0x400d1000 0x1000>;
+                                clocks = <&clks VF610_CLK_ENET1>,
+                                        <&clks VF610_CLK_ENET1>,
+                                        <&clks VF610_CLK_ENET>;
+                                clock-names = "ipg", "ahb", "ptp";
+                                status = "disabled";
+                        };
+                        can1: flexcan@400d4000 {
+                                compatible = "fsl,vf610-flexcan";
+                                reg = <0x400d4000 0x4000>;
+                                clocks = <&clks VF610_CLK_FLEXCAN1>,
+                                         <&clks VF610_CLK_FLEXCAN1>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index ce2ef5bec4f2..ee3e5d675b05 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -243,7 +243,6 @@
                        clkc: clkc@100 {
                                #clock-cells = <1>;
                                compatible = "xlnx,ps7-clkc";
-                                ps-clk-frequency = <33333333>;
                                fclk-enable = <0>;
                                clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
                                                "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
index 0429bbd89fba..ab1dc0a56cdd 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -36,6 +36,7 @@
 &clkc {
        fclk-enable = <0xf>;
+        ps-clk-frequency = <33333333>;
 };
 &gem0 {
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 94e2cda6f9b6..280f02dd4ddc 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -42,6 +42,10 @@
        status = "okay";
 };
+&clkc {
+        ps-clk-frequency = <33333333>;
+};
 &gem0 {
        status = "okay";
        phy-mode = "rgmii-id";
diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts
index a8bbdfbc7093..34f7812d2ee8 100644
--- a/arch/arm/boot/dts/zynq-zc706.dts
+++ b/arch/arm/boot/dts/zynq-zc706.dts
@@ -29,6 +29,10 @@
 };
+&clkc {
+        ps-clk-frequency = <33333333>;
+};
 &gem0 {
        status = "okay";
        phy-mode = "rgmii-id";
diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts
index 697779a353ed..1c7cc990b47a 100644
--- a/arch/arm/boot/dts/zynq-zed.dts
+++ b/arch/arm/boot/dts/zynq-zed.dts
@@ -29,6 +29,10 @@
 };
+&clkc {
+        ps-clk-frequency = <33333333>;
+};
 &gem0 {
        status = "okay";
        phy-mode = "rgmii-id";
diff --git a/arch/arm/boot/dts/zynq-zybo.dts b/arch/arm/boot/dts/zynq-zybo.dts
new file mode 100644
index 000000000000..a9a12ce5023b
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zybo.dts
@@ -0,0 +1,52 @@
+/*
+ *  Copyright (C) 2011 - 2014 Xilinx
+ *  Copyright (C) 2012 National Instruments Corp.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+/ {
+        model = "Zynq ZYBO Development Board";
+        compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x20000000>;
+        };
+        chosen {
+                bootargs = "console=ttyPS0,115200 earlyprintk";
+        };
+};
+&clkc {
+        ps-clk-frequency = <50000000>;
+};
+&gem0 {
+        status = "okay";
+        phy-mode = "rgmii-id";
+        phy-handle = <&ethernet_phy>;
+        ethernet_phy: ethernet-phy@0 {
+                reg = <0>;
+        };
+};
+&sdhci0 {
+        status = "okay";
+};
+&uart1 {
+        status = "okay";
+};
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 72041f002b7e..5662a872689b 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -245,6 +245,8 @@ struct edma {
        /* list of channels with no even trigger; terminated by "-1" */
        const s8        *noevent;
+        struct edma_soc_info *info;
        /* The edma_inuse bit for each PaRAM slot is clear unless the
         * channel is in use ... by ARM or DSP, for QDMA, or whatever.
         */
@@ -296,7 +298,7 @@ static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
                        ~(0x7 << bit), queue_no << bit);
 }
-static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
+static void assign_priority_to_queue(unsigned ctlr, int queue_no,
                int priority)
 {
        int bit = queue_no * 4;
@@ -315,7 +317,7 @@ static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
 * included in that particular EDMA variant (Eg : dm646x)
 *
 */
-static void __init map_dmach_param(unsigned ctlr)
+static void map_dmach_param(unsigned ctlr)
 {
        int i;
        for (i = 0; i < EDMA_MAX_DMACH; i++)
@@ -1798,6 +1800,7 @@ static int edma_probe(struct platform_device *pdev)
                        edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
                        edma_write_array(j, EDMA_QRAE, i, 0x0);
                }
+                edma_cc[j]->info = info[j];
                arch_num_cc++;
                edma_dev_info.id = j;
@@ -1807,9 +1810,56 @@ static int edma_probe(struct platform_device *pdev)
        return 0;
 }
+#ifdef CONFIG_PM_SLEEP
+static int edma_pm_resume(struct device *dev)
+{
+        int i, j;
+        for (j = 0; j < arch_num_cc; j++) {
+                struct edma *cc = edma_cc[j];
+                s8 (*queue_priority_mapping)[2];
+                queue_priority_mapping = cc->info->queue_priority_mapping;
+                /* Event queue priority mapping */
+                for (i = 0; queue_priority_mapping[i][0] != -1; i++)
+                        assign_priority_to_queue(j,
+                                                 queue_priority_mapping[i][0],
+                                                 queue_priority_mapping[i][1]);
+                /*
+                 * Map the channel to param entry if channel mapping logic
+                 * exist
+                 */
+                if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
+                        map_dmach_param(j);
+                for (i = 0; i < cc->num_channels; i++) {
+                        if (test_bit(i, cc->edma_inuse)) {
+                                /* ensure access through shadow region 0 */
+                                edma_or_array2(j, EDMA_DRAE, 0, i >> 5,
+                                               BIT(i & 0x1f));
+                                setup_dma_interrupt(i,
+                                                    cc->intr_data[i].callback,
+                                                    cc->intr_data[i].data);
+                        }
+                }
+        }
+        return 0;
+}
+#endif
+static const struct dev_pm_ops edma_pm_ops = {
+        SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, edma_pm_resume)
+};
 static struct platform_driver edma_driver = {
        .driver = {
                .name   = "edma",
+                .pm     = &edma_pm_ops,
                .of_match_table = edma_of_ids,
        },
        .probe = edma_probe,
diff --git a/arch/arm/configs/ape6evm_defconfig b/arch/arm/configs/ape6evm_defconfig
index b54b28fc5a70..db81d8ce4c03 100644
--- a/arch/arm/configs/ape6evm_defconfig
+++ b/arch/arm/configs/ape6evm_defconfig
@@ -33,6 +33,7 @@ CONFIG_ARM_APPENDED_DTB=y
 CONFIG_VFP=y
 CONFIG_NEON=y
 CONFIG_BINFMT_MISC=y
+CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 3b515c179487..a67375f24b21 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -80,6 +80,7 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_NETDEVICES=y
 CONFIG_MACB=y
 # CONFIG_NET_VENDOR_BROADCOM is not set
+CONFIG_DM9000=y
 # CONFIG_NET_VENDOR_FARADAY is not set
 # CONFIG_NET_VENDOR_INTEL is not set
 # CONFIG_NET_VENDOR_MARVELL is not set
@@ -113,6 +114,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=272
 CONFIG_INPUT_JOYDEV=y
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_QT1070=y
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
@@ -186,6 +188,7 @@ CONFIG_IIO=y
 CONFIG_AT91_ADC=y
 CONFIG_PWM=y
 CONFIG_PWM_ATMEL=y
+CONFIG_PWM_ATMEL_TCB=y
 CONFIG_EXT4_FS=y
 CONFIG_FANOTIFY=y
 CONFIG_VFAT_FS=y
diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig
deleted file mode 100644
index bf057719dab0..000000000000
--- a/arch/arm/configs/at91rm9200_defconfig
+++ /dev/null
@@ -1,161 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_USER_NS=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91RM9200=y
-CONFIG_MACH_ONEARM=y
-CONFIG_MACH_AT91RM9200EK=y
-CONFIG_MACH_CSB337=y
-CONFIG_MACH_CSB637=y
-CONFIG_MACH_CARMEVA=y
-CONFIG_MACH_ATEB9200=y
-CONFIG_MACH_KB9200=y
-CONFIG_MACH_PICOTUX2XX=y
-CONFIG_MACH_KAFA=y
-CONFIG_MACH_ECBAT91=y
-CONFIG_MACH_YL9200=y
-CONFIG_MACH_CPUAT91=y
-CONFIG_MACH_ECO920=y
-CONFIG_MTD_AT91_DATAFLASH_CARD=y
-CONFIG_AT91_TIMER_HZ=100
-# CONFIG_ARM_THUMB is not set
-CONFIG_PCCARD=y
-CONFIG_AT91_CF=y
-CONFIG_AEABI=y
-# CONFIG_COMPACTION is not set
-CONFIG_ZBOOT_ROM_TEXT=0x10000000
-CONFIG_ZBOOT_ROM_BSS=0x20040000
-CONFIG_KEXEC=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_MISC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-CONFIG_IPV6=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_STANDALONE is not set
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PLATRAM=y
-CONFIG_MTD_DATAFLASH=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ATMEL=y
-CONFIG_MTD_NAND_PLATFORM=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_GLUEBI=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_NETDEVICES=y
-CONFIG_MII=y
-CONFIG_ARM_AT91_ETHER=y
-CONFIG_DAVICOM_PHY=y
-CONFIG_SMSC_PHY=y
-CONFIG_MICREL_PHY=y
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-CONFIG_SPI=y
-CONFIG_SPI_ATMEL=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_AT91RM9200_WATCHDOG=y
-CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_TILEBLITTING=y
-CONFIG_FB_S1D13XXX=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_LOGO=y
-CONFIG_USB=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_AT91=y
-CONFIG_USB_G_SERIAL=y
-CONFIG_MMC=y
-CONFIG_MMC_ATMELMCI=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91RM9200=y
-CONFIG_EXT4_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_UBIFS_FS=y
-CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CRYPTO_PCBC=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_XZ_DEC_ARMTHUMB=y
diff --git a/arch/arm/configs/at91sam9260_9g20_defconfig b/arch/arm/configs/at91sam9260_9g20_defconfig
deleted file mode 100644
index 3ada05d639ad..000000000000
--- a/arch/arm/configs/at91sam9260_9g20_defconfig
+++ /dev/null
@@ -1,145 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9260=y
-CONFIG_MACH_AT91SAM9260EK=y
-CONFIG_MACH_CAM60=y
-CONFIG_MACH_SAM9_L9260=y
-CONFIG_MACH_AFEB9260=y
-CONFIG_MACH_CPU9260=y
-CONFIG_MACH_FLEXIBITY=y
-CONFIG_MACH_AT91SAM9G20EK=y
-CONFIG_MACH_AT91SAM9G20EK_2MMC=y
-CONFIG_MACH_CPU9G20=y
-CONFIG_MACH_ACMENETUSFOXG20=y
-CONFIG_MACH_PORTUXG20=y
-CONFIG_MACH_STAMP9G20=y
-CONFIG_MACH_PCONTROL_G20=y
-CONFIG_MACH_GSIA18S=y
-CONFIG_MACH_SNAPPER_9260=y
-CONFIG_MACH_AT91SAM9_DT=y
-CONFIG_AT91_SLOW_CLOCK=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_DATAFLASH=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ATMEL=y
-CONFIG_MTD_UBI=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_EEPROM_AT25=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_MACB=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_FARADAY is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-CONFIG_SMSC_PHY=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-CONFIG_SPI=y
-CONFIG_SPI_ATMEL=y
-CONFIG_SPI_SPIDEV=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_POWER_RESET=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_AT91SAM9X_WATCHDOG=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_SEQUENCER=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_SEQUENCER_OSS=y
-# CONFIG_SND_VERBOSE_PROCFS is not set
-CONFIG_USB=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_AT91=y
-CONFIG_USB_G_SERIAL=y
-CONFIG_MMC=y
-CONFIG_MMC_ATMELMCI=y
-CONFIG_MMC_SPI=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_RV3029C2=y
-CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_IIO=y
-CONFIG_AT91_ADC=y
-CONFIG_EXT4_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_UBIFS_FS=y
-CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_UTF8=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_LL=y
-CONFIG_EARLY_PRINTK=y
diff --git a/arch/arm/configs/at91sam9261_9g10_defconfig b/arch/arm/configs/at91sam9261_9g10_defconfig
deleted file mode 100644
index 0c505d801e25..000000000000
--- a/arch/arm/configs/at91sam9261_9g10_defconfig
+++ /dev/null
@@ -1,147 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZMA=y
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_NAMESPACES=y
-CONFIG_EMBEDDED=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9261=y
-CONFIG_MACH_AT91SAM9261EK=y
-CONFIG_MACH_AT91SAM9G10EK=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_VFP=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ATMEL=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_GLUEBI=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_ATMEL_TCLIB=y
-CONFIG_ATMEL_SSC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_DM9000=y
-CONFIG_USB_ZD1201=m
-CONFIG_RTL8187=m
-CONFIG_LIBERTAS=m
-CONFIG_LIBERTAS_USB=m
-CONFIG_LIBERTAS_SDIO=m
-CONFIG_LIBERTAS_SPI=m
-CONFIG_RT2X00=m
-CONFIG_RT2500USB=m
-CONFIG_RT73USB=m
-CONFIG_ZD1211RW=m
-CONFIG_INPUT_POLLDEV=m
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-CONFIG_SPI=y
-CONFIG_SPI_ATMEL=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_POWER_RESET=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_AT91SAM9X_WATCHDOG=y
-CONFIG_FB=y
-CONFIG_FB_ATMEL=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_ATMEL_LCDC=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_LOGO=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_SEQUENCER=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_AT73C213=y
-CONFIG_SND_USB_AUDIO=m
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_AT91=y
-CONFIG_USB_G_SERIAL=y
-CONFIG_MMC=y
-CONFIG_MMC_ATMELMCI=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_UBIFS_FS=y
-CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_SQUASHFS=y
-CONFIG_SQUASHFS_LZO=y
-CONFIG_SQUASHFS_XZ=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_UTF8=y
-CONFIG_CRC_CCITT=m
diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig
deleted file mode 100644
index 8b671c977b81..000000000000
--- a/arch/arm/configs/at91sam9263_defconfig
+++ /dev/null
@@ -1,151 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_NAMESPACES=y
-CONFIG_EMBEDDED=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9263=y
-CONFIG_MACH_AT91SAM9263EK=y
-CONFIG_MTD_AT91_DATAFLASH_CARD=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_ROUTE_VERBOSE=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_NET_IPIP=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-CONFIG_IPV6=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_NFTL=y
-CONFIG_NFTL_RW=y
-CONFIG_MTD_DATAFLASH=y
-CONFIG_MTD_BLOCK2MTD=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ATMEL=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_GLUEBI=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_ATMEL_TCLIB=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_MACB=y
-CONFIG_SMSC_PHY=y
-# CONFIG_WLAN is not set
-CONFIG_INPUT_POLLDEV=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-CONFIG_SPI=y
-CONFIG_SPI_ATMEL=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_POWER_RESET=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_AT91SAM9X_WATCHDOG=y
-CONFIG_FB=y
-CONFIG_FB_ATMEL=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_LOGO=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_SEQUENCER=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_ATMEL_AC97C=y
-# CONFIG_SND_SPI is not set
-CONFIG_SND_USB_AUDIO=m
-CONFIG_USB=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ATMEL_USBA=y
-CONFIG_USB_G_SERIAL=y
-CONFIG_MMC=y
-CONFIG_SDIO_UART=m
-CONFIG_MMC_ATMELMCI=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_PWM=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_PWM=y
-CONFIG_PWM_ATMEL=y
-CONFIG_EXT4_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_UBIFS_FS=y
-CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=y
-CONFIG_DEBUG_USER=y
-CONFIG_XZ_DEC=y
-CONFIG_FONTS=y
diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig
deleted file mode 100644
index f66d1a1b64bf..000000000000
--- a/arch/arm/configs/at91sam9g45_defconfig
+++ /dev/null
@@ -1,175 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_EMBEDDED=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9G45=y
-CONFIG_MACH_AT91SAM9M10G45EK=y
-CONFIG_MACH_AT91SAM9_DT=y
-CONFIG_AT91_SLOW_CLOCK=y
-CONFIG_AEABI=y
-CONFIG_UACCESS_WITH_MEMCPY=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x71100000,25165824 root=/dev/ram0 rw"
-CONFIG_AUTO_ZRELADDR=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-CONFIG_IPV6=y
-# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET6_XFRM_MODE_BEET is not set
-CONFIG_IPV6_SIT_6RD=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_STANDALONE is not set
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_DATAFLASH=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ATMEL=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_GLUEBI=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=4
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_ATMEL_TCLIB=y
-CONFIG_ATMEL_SSC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_MACB=y
-CONFIG_DAVICOM_PHY=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_JOYDEV=y
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_QT1070=y
-CONFIG_KEYBOARD_QT2160=y
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ATMEL_MXT=m
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-CONFIG_SPI=y
-CONFIG_SPI_ATMEL=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_POWER_RESET=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_AT91SAM9X_WATCHDOG=y
-CONFIG_FB=y
-CONFIG_FB_ATMEL=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_ATMEL_LCDC=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_BACKLIGHT_PWM=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_LOGO=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_SEQUENCER=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_ATMEL_AC97C=y
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_ACM=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ATMEL_USBA=y
-CONFIG_USB_G_MULTI=y
-CONFIG_USB_G_MULTI_CDC=y
-CONFIG_MMC=y
-# CONFIG_MMC_BLOCK_BOUNCE is not set
-CONFIG_MMC_ATMELMCI=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_PWM=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91RM9200=y
-CONFIG_DMADEVICES=y
-CONFIG_AT_HDMAC=y
-CONFIG_DMATEST=m
-# CONFIG_IOMMU_SUPPORT is not set
-CONFIG_IIO=y
-CONFIG_AT91_ADC=y
-CONFIG_PWM=y
-CONFIG_PWM_ATMEL=y
-CONFIG_EXT4_FS=y
-CONFIG_FANOTIFY=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_UBIFS_FS=y
-CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_STRIP_ASM_SYMS=y
-CONFIG_DEBUG_MEMORY_INIT=y
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CRYPTO_ECB=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_USER_API_HASH=m
-CONFIG_CRYPTO_USER_API_SKCIPHER=m
-# CONFIG_CRYPTO_HW is not set
-CONFIG_FONTS=y
diff --git a/arch/arm/configs/at91sam9rl_defconfig b/arch/arm/configs/at91sam9rl_defconfig
deleted file mode 100644
index 4c26d344ae88..000000000000
--- a/arch/arm/configs/at91sam9rl_defconfig
+++ /dev/null
@@ -1,92 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9RL=y
-CONFIG_MACH_AT91SAM9RLEK=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,17105363 root=/dev/ram0 rw"
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_DATAFLASH=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ATMEL=y
-CONFIG_MTD_UBI=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=4
-CONFIG_BLK_DEV_RAM_SIZE=24576
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-CONFIG_SPI=y
-CONFIG_SPI_ATMEL=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_POWER_RESET=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_AT91SAM9X_WATCHDOG=y
-CONFIG_FB=y
-CONFIG_FB_ATMEL=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ATMEL_USBA=y
-CONFIG_MMC=y
-CONFIG_MMC_ATMELMCI=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_PWM=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_IIO=y
-CONFIG_AT91_ADC=y
-CONFIG_PWM=y
-CONFIG_PWM_ATMEL=y
-CONFIG_EXT4_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_UBIFS_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_UTF8=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/at91x40_defconfig b/arch/arm/configs/at91x40_defconfig
deleted file mode 100644
index c55e9212fcbb..000000000000
--- a/arch/arm/configs/at91x40_defconfig
+++ /dev/null
@@ -1,48 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_EMBEDDED=y
-# CONFIG_HOTPLUG is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_SLAB=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-# CONFIG_MMU is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91X40=y
-CONFIG_MACH_AT91EB01=y
-CONFIG_AT91_EARLY_USART0=y
-CONFIG_CPU_ARM7TDMI=y
-CONFIG_SET_MEM_PARAM=y
-CONFIG_DRAM_BASE=0x01000000
-CONFIG_DRAM_SIZE=0x00400000
-CONFIG_FLASH_MEM_BASE=0x01400000
-CONFIG_PROCESSOR_ID=0x14000040
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_BINFMT_FLAT=y
-# CONFIG_SUSPEND is not set
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=y
-CONFIG_BLK_DEV_RAM=y
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_ROMFS_FS=y
-# CONFIG_ENABLE_MUST_CHECK is not set
diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
index bc614f44b33d..83a87e48901c 100644
--- a/arch/arm/configs/bcm_defconfig
+++ b/arch/arm/configs/bcm_defconfig
@@ -25,7 +25,8 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_BCM=y
-CONFIG_ARCH_BCM_MOBILE=y
+CONFIG_ARCH_BCM_21664=y
+CONFIG_ARCH_BCM_281XX=y
 CONFIG_ARM_THUMBEE=y
 CONFIG_SMP=y
 CONFIG_PREEMPT=y
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index e21ef830a483..c41990729024 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -134,6 +134,7 @@ CONFIG_USB_STORAGE=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_HSIC_USB3503=y
 CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_S3C=y
 CONFIG_MMC_SDHCI_S3C_DMA=y
diff --git a/arch/arm/configs/hisi_defconfig b/arch/arm/configs/hisi_defconfig
index 1772505caeba..1fe3621faf65 100644
--- a/arch/arm/configs/hisi_defconfig
+++ b/arch/arm/configs/hisi_defconfig
@@ -5,6 +5,8 @@ CONFIG_BLK_DEV_INITRD=y
 CONFIG_RD_LZMA=y
 CONFIG_ARCH_HISI=y
 CONFIG_ARCH_HI3xxx=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_CMDLINE_PARTITION=y
 CONFIG_ARCH_HIX5HD2=y
 CONFIG_ARCH_HIP04=y
 CONFIG_SMP=y
@@ -14,8 +16,11 @@ CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_NEON=y
 CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
+CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_PNP=y
@@ -26,6 +31,7 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=y
 CONFIG_SATA_AHCI_PLATFORM=y
 CONFIG_NETDEVICES=y
+CONFIG_HIX5HD2_GMAC=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
 CONFIG_SERIAL_8250_CONSOLE=y
@@ -39,8 +45,13 @@ CONFIG_I2C_DESIGNWARE_PLATFORM=y
 CONFIG_SPI=y
 CONFIG_SPI_PL022=y
 CONFIG_PINCTRL_SINGLE=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIOLIB=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
 CONFIG_REGULATOR_GPIO=y
+CONFIG_MFD_SYSCON=y
+CONFIG_POWER_RESET_SYSCON=y
 CONFIG_DRM=y
 CONFIG_FB_SIMPLE=y
 CONFIG_USB=y
@@ -48,15 +59,21 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_MXC=y
 CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
 CONFIG_USB_STORAGE=y
 CONFIG_NOP_USB_XCEIV=y
 CONFIG_MMC=y
 CONFIG_RTC_CLASS=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_IDMAC=y
+CONFIG_MMC_DW_PLTFM=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_DMADEVICES=y
 CONFIG_DW_DMAC=y
 CONFIG_PL330_DMA=y
 CONFIG_PWM=y
+CONFIG_PHY_HIX5HD2_SATA=y
 CONFIG_EXT4_FS=y
 CONFIG_TMPFS=y
 CONFIG_NFS_FS=y
@@ -65,6 +82,8 @@ CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
 CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_FS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_LOCKUP_DETECTOR=y
 CONFIG_VFP=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 6790f1b3f3a1..f707cd2691cf 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -163,7 +163,13 @@ CONFIG_SPI_IMX=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_MC9S08DZ60=y
 CONFIG_GPIO_STMPE=y
-# CONFIG_HWMON is not set
+CONFIG_SENSORS_GPIO_FAN=y
+CONFIG_THERMAL=y
+CONFIG_CPU_THERMAL=y
+CONFIG_IMX_THERMAL=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_IMX=y
 CONFIG_WATCHDOG=y
 CONFIG_IMX2_WDT=y
 CONFIG_MFD_DA9052_I2C=y
@@ -211,6 +217,7 @@ CONFIG_SND_SOC_IMX_WM8962=y
 CONFIG_SND_SOC_IMX_SGTL5000=y
 CONFIG_SND_SOC_IMX_SPDIF=y
 CONFIG_SND_SOC_IMX_MC13783=y
+CONFIG_SND_SOC_TLV320AIC3X=y
 CONFIG_SND_SIMPLE_CARD=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
@@ -239,6 +246,7 @@ CONFIG_LEDS_TRIGGER_BACKLIGHT=y
 CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_DRV_DS1307=y
 CONFIG_RTC_DRV_ISL1208=y
 CONFIG_RTC_DRV_PCF8563=y
 CONFIG_RTC_DRV_MC13XXX=y
diff --git a/arch/arm/configs/integrator_defconfig b/arch/arm/configs/integrator_defconfig
index c1f5adc5493e..71f14675d009 100644
--- a/arch/arm/configs/integrator_defconfig
+++ b/arch/arm/configs/integrator_defconfig
@@ -8,6 +8,9 @@ CONFIG_BLK_DEV_INITRD=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_PARTITION_ADVANCED=y
+CONFIG_ARCH_MULTI_V4T=y
+CONFIG_ARCH_MULTI_V5=y
+# CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_ARCH_INTEGRATOR=y
 CONFIG_ARCH_INTEGRATOR_AP=y
 CONFIG_ARCH_INTEGRATOR_CP=y
diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig
index 932ae40fb128..20a3ff99fae2 100644
--- a/arch/arm/configs/keystone_defconfig
+++ b/arch/arm/configs/keystone_defconfig
@@ -20,6 +20,9 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_ARCH_KEYSTONE=y
 CONFIG_ARM_LPAE=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_KEYSTONE=y
 CONFIG_SMP=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
@@ -194,3 +197,7 @@ CONFIG_LEDS_TRIGGER_ONESHOT=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_BACKLIGHT=y
 CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_KEYSTONE_IRQ=y
+CONFIG_GPIO_SYSCON=y
+CONFIG_TI_DAVINCI_MDIO=y
+CONFIG_MARVELL_PHY=y
diff --git a/arch/arm/configs/koelsch_defconfig b/arch/arm/configs/koelsch_defconfig
deleted file mode 100644
index b33d19b7f134..000000000000
--- a/arch/arm/configs/koelsch_defconfig
+++ /dev/null
@@ -1,113 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_EMBEDDED=y
-CONFIG_PERF_EVENTS=y
-CONFIG_SLAB=y
-CONFIG_ARCH_SHMOBILE_LEGACY=y
-CONFIG_ARCH_R8A7791=y
-CONFIG_MACH_KOELSCH=y
-# CONFIG_SWP_EMULATE is not set
-CONFIG_CPU_BPREDICT_DISABLE=y
-CONFIG_PL310_ERRATA_588369=y
-CONFIG_ARM_ERRATA_754322=y
-CONFIG_PCI=y
-CONFIG_PCI_RCAR_GEN2=y
-CONFIG_PCI_RCAR_GEN2_PCIE=y
-CONFIG_SMP=y
-CONFIG_SCHED_MC=y
-CONFIG_NR_CPUS=8
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_KEXEC=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_BLK_DEV_SD=y
-CONFIG_ATA=y
-CONFIG_SATA_RCAR=y
-CONFIG_MTD=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_EEPROM_AT24=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_ARC is not set
-# CONFIG_NET_CADENCE is not set
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CIRRUS is not set
-# CONFIG_NET_VENDOR_FARADAY is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-CONFIG_SH_ETH=y
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_NET_VENDOR_VIA is not set
-# CONFIG_NET_VENDOR_WIZNET is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_SH_SCI=y
-CONFIG_SERIAL_SH_SCI_NR_UARTS=20
-CONFIG_SERIAL_SH_SCI_CONSOLE=y
-CONFIG_I2C=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_SH_MOBILE=y
-CONFIG_I2C_RCAR=y
-CONFIG_SPI=y
-CONFIG_SPI_RSPI=y
-CONFIG_SPI_SH_MSIOF=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_RCAR=y
-# CONFIG_HWMON is not set
-CONFIG_THERMAL=y
-CONFIG_RCAR_THERMAL=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_DA9210=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_PLATFORM=y
-CONFIG_VIDEO_RCAR_VIN=y
-# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
-CONFIG_VIDEO_ADV7180=y
-# CONFIG_HID is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_SDHI=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-# CONFIG_IOMMU_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_TMPFS=y
-CONFIG_CONFIGFS_FS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-# CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig
index 018bef9fa7e8..9d56781a8f80 100644
--- a/arch/arm/configs/multi_v5_defconfig
+++ b/arch/arm/configs/multi_v5_defconfig
@@ -67,9 +67,11 @@ CONFIG_SATA_AHCI=y
 CONFIG_SATA_MV=y
 CONFIG_NETDEVICES=y
 CONFIG_NET_DSA_MV88E6123_61_65=y
+CONFIG_NET_DSA_MV88E6171=y
 CONFIG_MV643XX_ETH=y
 CONFIG_R8169=y
 CONFIG_MARVELL_PHY=y
+CONFIG_MWL8K=m
 CONFIG_LIBERTAS=y
 CONFIG_LIBERTAS_SDIO=y
 CONFIG_INPUT_EVDEV=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 9d7a32f93fcf..d7896580f3bb 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -3,12 +3,14 @@ CONFIG_FHANDLE=y
 CONFIG_IRQ_DOMAIN_DEBUG=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_CGROUPS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EMBEDDED=y
 CONFIG_PERF_EVENTS=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_PARTITION_ADVANCED=y
+CONFIG_CMDLINE_PARTITION=y
 CONFIG_ARCH_VIRT=y
 CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_ARMADA_370=y
@@ -17,7 +19,9 @@ CONFIG_MACH_ARMADA_38X=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_MACH_DOVE=y
 CONFIG_ARCH_BCM=y
-CONFIG_ARCH_BCM_MOBILE=y
+CONFIG_ARCH_BCM_CYGNUS=y
+CONFIG_ARCH_BCM_21664=y
+CONFIG_ARCH_BCM_281XX=y
 CONFIG_ARCH_BCM_5301X=y
 CONFIG_ARCH_BRCMSTB=y
 CONFIG_ARCH_BERLIN=y
@@ -124,8 +128,12 @@ CONFIG_DMA_CMA=y
 CONFIG_CMA_SIZE_MBYTES=64
 CONFIG_OMAP_OCP2SCP=y
 CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
 CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
 CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_UBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_AD525X_DPOT=y
 CONFIG_AD525X_DPOT_I2C=y
@@ -146,6 +154,7 @@ CONFIG_AHCI_TEGRA=y
 CONFIG_SATA_HIGHBANK=y
 CONFIG_SATA_MV=y
 CONFIG_NETDEVICES=y
+CONFIG_HIX5HD2_GMAC=y
 CONFIG_SUN4I_EMAC=y
 CONFIG_MACB=y
 CONFIG_NET_CALXEDA_XGMAC=y
@@ -160,6 +169,7 @@ CONFIG_TI_CPSW=y
 CONFIG_XILINX_EMACLITE=y
 CONFIG_AT803X_PHY=y
 CONFIG_MARVELL_PHY=y
+CONFIG_BROADCOM_PHY=y
 CONFIG_ICPLUS_PHY=y
 CONFIG_USB_PEGASUS=y
 CONFIG_USB_USBNET=y
@@ -234,6 +244,7 @@ CONFIG_SPI_TEGRA114=y
 CONFIG_SPI_TEGRA20_SFLASH=y
 CONFIG_SPI_TEGRA20_SLINK=y
 CONFIG_SPI_XILINX=y
+CONFIG_SPI_SPIDEV=y
 CONFIG_PINCTRL_AS3722=y
 CONFIG_PINCTRL_PALMAS=y
 CONFIG_PINCTRL_APQ8084=y
@@ -261,6 +272,7 @@ CONFIG_ST_THERMAL_SYSCFG=y
 CONFIG_ST_THERMAL_MEMMAP=y
 CONFIG_WATCHDOG=y
 CONFIG_XILINX_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
 CONFIG_ORION_WATCHDOG=y
 CONFIG_SUNXI_WATCHDOG=y
 CONFIG_MESON_WATCHDOG=y
@@ -268,6 +280,7 @@ CONFIG_MFD_AS3722=y
 CONFIG_MFD_BCM590XX=y
 CONFIG_MFD_CROS_EC=y
 CONFIG_MFD_CROS_EC_SPI=y
+CONFIG_MFD_MAX77686=y
 CONFIG_MFD_MAX8907=y
 CONFIG_MFD_SEC_CORE=y
 CONFIG_MFD_STMPE=y
@@ -279,7 +292,10 @@ CONFIG_REGULATOR_AB8500=y
 CONFIG_REGULATOR_AS3722=y
 CONFIG_REGULATOR_BCM590XX=y
 CONFIG_REGULATOR_GPIO=y
+CONFIG_MFD_SYSCON=y
+CONFIG_POWER_RESET_SYSCON=y
 CONFIG_REGULATOR_MAX8907=y
+CONFIG_REGULATOR_MAX77686=y
 CONFIG_REGULATOR_PALMAS=y
 CONFIG_REGULATOR_S2MPS11=y
 CONFIG_REGULATOR_S5M8767=y
@@ -308,6 +324,8 @@ CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
 CONFIG_SOUND=y
 CONFIG_SND=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_USB_AUDIO=y
 CONFIG_SND_SOC=y
 CONFIG_SND_SOC_TEGRA=y
 CONFIG_SND_SOC_TEGRA_RT5640=y
@@ -321,9 +339,11 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_MVEBU=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_EHCI_HCD_STI=y
 CONFIG_USB_EHCI_HCD_PLATFORM=y
 CONFIG_USB_ISP1760_HCD=y
 CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_STI=y
 CONFIG_USB_OHCI_HCD_PLATFORM=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_CHIPIDEA=y
@@ -355,6 +375,8 @@ CONFIG_MMC_OMAP_HS=y
 CONFIG_MMC_MVSDIO=y
 CONFIG_MMC_SUNXI=y
 CONFIG_MMC_DW=y
+CONFIG_MMC_DW_IDMAC=y
+CONFIG_MMC_DW_PLTFM=y
 CONFIG_MMC_DW_EXYNOS=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_NEW_LEDS=y
@@ -379,6 +401,7 @@ CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_AS3722=y
 CONFIG_RTC_DRV_DS1307=y
 CONFIG_RTC_DRV_MAX8907=y
+CONFIG_RTC_DRV_MAX77686=y
 CONFIG_RTC_DRV_PALMAS=y
 CONFIG_RTC_DRV_TWL4030=y
 CONFIG_RTC_DRV_TPS6586X=y
@@ -413,6 +436,7 @@ CONFIG_NVEC_POWER=y
 CONFIG_NVEC_PAZ00=y
 CONFIG_QCOM_GSBI=y
 CONFIG_COMMON_CLK_QCOM=y
+CONFIG_COMMON_CLK_MAX77686=y
 CONFIG_APQ_MMCC_8084=y
 CONFIG_MSM_GCC_8660=y
 CONFIG_MSM_MMCC_8960=y
@@ -426,12 +450,19 @@ CONFIG_AK8975=y
 CONFIG_PWM=y
 CONFIG_PWM_TEGRA=y
 CONFIG_PWM_VT8500=y
+CONFIG_PHY_HIX5HD2_SATA=y
 CONFIG_OMAP_USB2=y
 CONFIG_TI_PIPE3=y
 CONFIG_PHY_MIPHY365X=y
+CONFIG_PHY_STIH41X_USB=y
 CONFIG_PHY_SUN4I_USB=y
 CONFIG_EXT4_FS=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_UBIFS_FS=y
 CONFIG_TMPFS=y
 CONFIG_SQUASHFS=y
 CONFIG_SQUASHFS_LZO=y
@@ -440,6 +471,9 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
 CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_FS=y
 CONFIG_MAGIC_SYSRQ=y
diff --git a/arch/arm/configs/mvebu_v5_defconfig b/arch/arm/configs/mvebu_v5_defconfig
index 22058e18dfaa..824de499237b 100644
--- a/arch/arm/configs/mvebu_v5_defconfig
+++ b/arch/arm/configs/mvebu_v5_defconfig
@@ -67,9 +67,11 @@ CONFIG_SATA_AHCI=y
 CONFIG_SATA_MV=y
 CONFIG_NETDEVICES=y
 CONFIG_NET_DSA_MV88E6123_61_65=y
+CONFIG_NET_DSA_MV88E6171=y
 CONFIG_MV643XX_ETH=y
 CONFIG_R8169=y
 CONFIG_MARVELL_PHY=y
+CONFIG_MWL8K=m
 CONFIG_LIBERTAS=y
 CONFIG_LIBERTAS_SDIO=y
 CONFIG_INPUT_EVDEV=y
diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig
index ed0a0d1be0f3..627accea72fb 100644
--- a/arch/arm/configs/mvebu_v7_defconfig
+++ b/arch/arm/configs/mvebu_v7_defconfig
@@ -45,6 +45,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
+CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
@@ -59,10 +60,12 @@ CONFIG_ATA=y
 CONFIG_AHCI_MVEBU=y
 CONFIG_SATA_MV=y
 CONFIG_NETDEVICES=y
+CONFIG_NET_DSA_MV88E6171=y
 CONFIG_MV643XX_ETH=y
 CONFIG_MVNETA=y
 CONFIG_MVPP2=y
 CONFIG_MARVELL_PHY=y
+CONFIG_FIXED_PHY=y
 CONFIG_MWIFIEX=y
 CONFIG_MWIFIEX_SDIO=y
 CONFIG_INPUT_EVDEV=y
@@ -72,6 +75,7 @@ CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_MV64XXX=y
 CONFIG_SPI=y
 CONFIG_SPI_ORION=y
@@ -85,7 +89,9 @@ CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_SOC=y
 CONFIG_SND_KIRKWOOD_SOC=y
-CONFIG_SND_KIRKWOOD_SOC_ARMADA370_DB=y
+CONFIG_SND_SOC_CS42L51_I2C=y
+CONFIG_SND_SOC_SPDIF=y
+CONFIG_SND_SIMPLE_CARD=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_MVEBU=y
@@ -96,6 +102,7 @@ CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_DOVE=y
+CONFIG_MMC_SDHCI_PXAV3=y
 CONFIG_MMC_MVSDIO=y
 CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_CLASS=y
diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
index 263ae3869e32..7d2ad30d9e70 100644
--- a/arch/arm/configs/nhk8815_defconfig
+++ b/arch/arm/configs/nhk8815_defconfig
@@ -20,7 +20,6 @@ CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_FPE_NWFPE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -57,14 +56,12 @@ CONFIG_MTD_NAND_FSMC=y
 CONFIG_MTD_ONENAND=y
 CONFIG_MTD_ONENAND_VERIFY_WRITE=y
 CONFIG_MTD_ONENAND_GENERIC=y
-CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_SG=y
-CONFIG_SCSI_MULTI_LUN=y
 CONFIG_SCSI_CONSTANTS=y
 CONFIG_SCSI_LOGGING=y
 CONFIG_SCSI_SCAN_ASYNC=y
@@ -83,21 +80,21 @@ CONFIG_PPP_SYNC_TTY=m
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
 CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_STMPE=y
 # CONFIG_MOUSE_PS2 is not set
 # CONFIG_SERIO is not set
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_NOMADIK=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
-CONFIG_I2C_NOMADIK=y
 CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_STMPE=y
 # CONFIG_HWMON is not set
+CONFIG_MFD_STMPE=y
 CONFIG_REGULATOR=y
 CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
 # CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ARMMMCI=y
 CONFIG_NEW_LEDS=y
@@ -125,12 +122,12 @@ CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=y
+CONFIG_DEBUG_INFO=y
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
 CONFIG_CRYPTO_MD5=y
 CONFIG_CRYPTO_SHA1=y
 CONFIG_CRYPTO_DES=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index b3f86670d2eb..3e09286f7ff1 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -129,11 +129,27 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_SCAN_ASYNC=y
 CONFIG_MD=y
 CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_HISILICON is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
 CONFIG_KS8851=y
 CONFIG_KS8851_MLL=y
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
 CONFIG_SMC91X=y
 CONFIG_SMSC911X=y
+# CONFIG_NET_VENDOR_STMICRO is not set
 CONFIG_TI_CPSW=y
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
 CONFIG_AT803X_PHY=y
 CONFIG_SMSC_PHY=y
 CONFIG_USB_USBNET=y
@@ -161,6 +177,7 @@ CONFIG_KEYBOARD_MATRIX=m
 CONFIG_KEYBOARD_TWL4030=y
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ADS7846=m
+CONFIG_TOUCHSCREEN_EDT_FT5X06=m
 CONFIG_TOUCHSCREEN_TSC2005=m
 CONFIG_TOUCHSCREEN_TSC2007=m
 CONFIG_INPUT_MISC=y
@@ -264,6 +281,8 @@ CONFIG_SND_VERBOSE_PRINTK=y
 CONFIG_SND_DEBUG=y
 CONFIG_SND_USB_AUDIO=m
 CONFIG_SND_SOC=m
+CONFIG_SND_EDMA_SOC=m
+CONFIG_SND_AM33XX_SOC_EVM=m
 CONFIG_SND_OMAP_SOC=m
 CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m
 CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m
@@ -271,6 +290,7 @@ CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m
 CONFIG_USB=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 CONFIG_USB_MON=y
+CONFIG_USB_XHCI_HCD=m
 CONFIG_USB_WDM=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_DWC3=m
@@ -306,6 +326,8 @@ CONFIG_DMA_OMAP=y
 CONFIG_EXTCON=y
 CONFIG_EXTCON_PALMAS=y
 CONFIG_PWM=y
+CONFIG_PWM_TIECAP=y
+CONFIG_PWM_TIEHRPWM=y
 CONFIG_PWM_TWL=y
 CONFIG_PWM_TWL_LED=y
 CONFIG_OMAP_USB2=y
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
index c9089c927daf..b58fb32770a0 100644
--- a/arch/arm/configs/sama5_defconfig
+++ b/arch/arm/configs/sama5_defconfig
@@ -12,7 +12,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_FORCE_LOAD=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_LBDAF is not set
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
@@ -20,7 +20,6 @@ CONFIG_ARCH_AT91=y
 CONFIG_SOC_SAM_V7=y
 CONFIG_SOC_SAMA5D3=y
 CONFIG_SOC_SAMA5D4=y
-CONFIG_MACH_SAMA5_DT=y
 CONFIG_AEABI=y
 CONFIG_UACCESS_WITH_MEMCPY=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -30,6 +29,8 @@ CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 r
 CONFIG_KEXEC=y
 CONFIG_AUTO_ZRELADDR=y
 CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_KERNEL_MODE_NEON=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_PM_RUNTIME=y
 CONFIG_PM_DEBUG=y
@@ -176,11 +177,13 @@ CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_AT91RM9200=y
 CONFIG_DMADEVICES=y
+CONFIG_AT_XDMAC=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_IIO=y
 CONFIG_AT91_ADC=y
 CONFIG_PWM=y
 CONFIG_PWM_ATMEL=y
+CONFIG_PWM_ATMEL_TCB=y
 CONFIG_EXT4_FS=y
 CONFIG_FANOTIFY=y
 CONFIG_VFAT_FS=y
diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index d7346ad51043..63fb5316ff02 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -17,7 +17,6 @@ CONFIG_ARCH_R8A7779=y
 CONFIG_ARCH_R8A7790=y
 CONFIG_ARCH_R8A7791=y
 CONFIG_ARCH_R8A7794=y
-CONFIG_MACH_KOELSCH=y
 CONFIG_MACH_LAGER=y
 CONFIG_MACH_MARZEN=y
 # CONFIG_SWP_EMULATE is not set
@@ -126,6 +125,7 @@ CONFIG_SND=y
 CONFIG_SND_SOC=y
 CONFIG_SND_SOC_SH4_FSI=y
 CONFIG_SND_SOC_RCAR=y
+CONFIG_SND_SOC_AK4642=y
 CONFIG_SND_SOC_WM8978=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
@@ -146,6 +146,8 @@ CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_S35390A=y
 CONFIG_DMADEVICES=y
 CONFIG_SH_DMAE=y
+CONFIG_RCAR_AUDMAC_PP=y
+CONFIG_RCAR_DMAC=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_PWM=y
 CONFIG_PWM_RENESAS_TPU=y
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 888fc1521322..40750f93aa83 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -97,10 +97,8 @@ CONFIG_ICS932S401=y
 CONFIG_APDS9802ALS=y
 CONFIG_ISL29003=y
 CONFIG_EEPROM_AT24=y
-CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=y
-CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_ATA=y
 CONFIG_SATA_AHCI=y
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 92793ba69c40..d4ebf5679f1f 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -78,6 +78,15 @@ static inline u32 arch_timer_get_cntfrq(void)
        return val;
 }
+static inline u64 arch_counter_get_cntpct(void)
+{
+        u64 cval;
+        isb();
+        asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
+        return cval;
+}
 static inline u64 arch_counter_get_cntvct(void)
 {
        u64 cval;
diff --git a/arch/arm/include/asm/cpuidle.h b/arch/arm/include/asm/cpuidle.h
index 2fca60ab513a..af319ac4960c 100644
--- a/arch/arm/include/asm/cpuidle.h
+++ b/arch/arm/include/asm/cpuidle.h
@@ -15,7 +15,6 @@ static inline int arm_cpuidle_simple_enter(struct cpuidle_device *dev,
        .exit_latency           = 1,\
        .target_residency       = 1,\
        .power_usage            = p,\
-        .flags                  = CPUIDLE_FLAG_TIME_VALID,\
        .name                   = "WFI",\
        .desc                   = "ARM WFI",\
 }
diff --git a/arch/arm/include/asm/firmware.h b/arch/arm/include/asm/firmware.h
index 2c9f10df7568..89aefe10d66b 100644
--- a/arch/arm/include/asm/firmware.h
+++ b/arch/arm/include/asm/firmware.h
@@ -28,7 +28,7 @@ struct firmware_ops {
        /*
         * Enters CPU idle mode
         */
-        int (*do_idle)(void);
+        int (*do_idle)(unsigned long mode);
        /*
         * Sets boot address of specified physical CPU
         */
@@ -41,6 +41,14 @@ struct firmware_ops {
         * Initializes L2 cache
         */
        int (*l2x0_init)(void);
+        /*
+         * Enter system-wide suspend.
+         */
+        int (*suspend)(void);
+        /*
+         * Restore state of privileged hardware after system-wide suspend.
+         */
+        int (*resume)(void);
 };
 /* Global pointer for current firmware_ops structure, can't be NULL. */
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 180567408ee8..db58deb00aa7 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -47,13 +47,13 @@ extern void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set);
 * Generic IO read/write.  These perform native-endian accesses.  Note
 * that some architectures will want to re-define __raw_{read,write}w.
 */
-extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
+void __raw_writesb(volatile void __iomem *addr, const void *data, int bytelen);
-extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
+void __raw_writesw(volatile void __iomem *addr, const void *data, int wordlen);
-extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
+void __raw_writesl(volatile void __iomem *addr, const void *data, int longlen);
-extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
+void __raw_readsb(const volatile void __iomem *addr, void *data, int bytelen);
-extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
+void __raw_readsw(const volatile void __iomem *addr, void *data, int wordlen);
-extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
+void __raw_readsl(const volatile void __iomem *addr, void *data, int longlen);
 #if __LINUX_ARM_ARCH__ < 6
 /*
@@ -69,6 +69,7 @@ extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
 * writeback addressing modes as these incur a significant performance
 * overhead (the address generation must be emulated in software).
 */
+#define __raw_writew __raw_writew
 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
 {
        asm volatile("strh %1, %0"
@@ -76,6 +77,7 @@ static inline void __raw_writew(u16 val, volatile void __iomem *addr)
                     : "r" (val));
 }
+#define __raw_readw __raw_readw
 static inline u16 __raw_readw(const volatile void __iomem *addr)
 {
        u16 val;
@@ -86,6 +88,7 @@ static inline u16 __raw_readw(const volatile void __iomem *addr)
 }
 #endif
+#define __raw_writeb __raw_writeb
 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
 {
        asm volatile("strb %1, %0"
@@ -93,6 +96,7 @@ static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
                     : "r" (val));
 }
+#define __raw_writel __raw_writel
 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
 {
        asm volatile("str %1, %0"
@@ -100,6 +104,7 @@ static inline void __raw_writel(u32 val, volatile void __iomem *addr)
                     : "r" (val));
 }
+#define __raw_readb __raw_readb
 static inline u8 __raw_readb(const volatile void __iomem *addr)
 {
        u8 val;
@@ -109,6 +114,7 @@ static inline u8 __raw_readb(const volatile void __iomem *addr)
        return val;
 }
+#define __raw_readl __raw_readl
 static inline u32 __raw_readl(const volatile void __iomem *addr)
 {
        u32 val;
@@ -267,20 +273,6 @@ extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
 #define insl(p,d,l)             __raw_readsl(__io(p),d,l)
 #endif
-#define outb_p(val,port)        outb((val),(port))
-#define outw_p(val,port)        outw((val),(port))
-#define outl_p(val,port)        outl((val),(port))
-#define inb_p(port)             inb((port))
-#define inw_p(port)             inw((port))
-#define inl_p(port)             inl((port))
-#define outsb_p(port,from,len)  outsb(port,from,len)
-#define outsw_p(port,from,len)  outsw(port,from,len)
-#define outsl_p(port,from,len)  outsl(port,from,len)
-#define insb_p(port,to,len)     insb(port,to,len)
-#define insw_p(port,to,len)     insw(port,to,len)
-#define insl_p(port,to,len)     insl(port,to,len)
 /*
 * String version of IO memory access ops:
 */
@@ -347,40 +339,42 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
 #define iounmap                         __arm_iounmap
 /*
- * io{read,write}{8,16,32} macros
+ * io{read,write}{16,32}be() macros
 */
-#ifndef ioread8
+#define ioread16be(p)           ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
-#define ioread8(p)      ({ unsigned int __v = __raw_readb(p); __iormb(); __v; })
+#define ioread32be(p)           ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
-#define ioread16(p)     ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __iormb(); __v; })
-#define ioread32(p)     ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __iormb(); __v; })
-#define ioread16be(p)   ({ unsigned int __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
-#define ioread32be(p)   ({ unsigned int __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
-#define iowrite8(v,p)   ({ __iowmb(); __raw_writeb(v, p); })
-#define iowrite16(v,p)  ({ __iowmb(); __raw_writew((__force __u16)cpu_to_le16(v), p); })
-#define iowrite32(v,p)  ({ __iowmb(); __raw_writel((__force __u32)cpu_to_le32(v), p); })
-#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
+#define iowrite16be(v,p)        ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
-#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
+#define iowrite32be(v,p)        ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
-#define ioread8_rep(p,d,c)      __raw_readsb(p,d,c)
-#define ioread16_rep(p,d,c)     __raw_readsw(p,d,c)
-#define ioread32_rep(p,d,c)     __raw_readsl(p,d,c)
-#define iowrite8_rep(p,s,c)     __raw_writesb(p,s,c)
-#define iowrite16_rep(p,s,c)    __raw_writesw(p,s,c)
-#define iowrite32_rep(p,s,c)    __raw_writesl(p,s,c)
+#ifndef ioport_map
+#define ioport_map ioport_map
 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
+#endif
+#ifndef ioport_unmap
+#define ioport_unmap ioport_unmap
 extern void ioport_unmap(void __iomem *addr);
 #endif
 struct pci_dev;
+#define pci_iounmap pci_iounmap
 extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
 /*
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem
+ * access
+ */
+#define xlate_dev_mem_ptr(p)    __va(p)
+/*
+ * Convert a virtual cached pointer to an uncached pointer
+ */
+#define xlate_dev_kmem_ptr(p)   p
+#include <asm-generic/io.h>
+/*
 * can the hardware map this into one segment or not, given no other
 * constraints.
 */
@@ -402,17 +396,6 @@ extern int devmem_is_allowed(unsigned long pfn);
 #endif
 /*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p)    __va(p)
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)   p
-/*
 * Register ISA memory and port locations for glibc iopl/inb/outb
 * emulation.
 */
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 7fc42784becb..8292b5f81e23 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -22,6 +22,9 @@ struct hw_pci {
 #ifdef CONFIG_PCI_DOMAINS
        int             domain;
 #endif
+#ifdef CONFIG_PCI_MSI
+        struct msi_controller *msi_ctrl;
+#endif
        struct pci_ops  *ops;
        int             nr_controllers;
        void            **private_data;
@@ -36,8 +39,6 @@ struct hw_pci {
                                          resource_size_t start,
                                          resource_size_t size,
                                          resource_size_t align);
-        void            (*add_bus)(struct pci_bus *bus);
-        void            (*remove_bus)(struct pci_bus *bus);
 };
 /*
@@ -47,6 +48,9 @@ struct pci_sys_data {
 #ifdef CONFIG_PCI_DOMAINS
        int             domain;
 #endif
+#ifdef CONFIG_PCI_MSI
+        struct msi_controller *msi_ctrl;
+#endif
        struct list_head node;
        int             busnr;          /* primary bus number                   */
        u64             mem_offset;     /* bus->cpu memory mapping offset       */
@@ -65,8 +69,6 @@ struct pci_sys_data {
                                          resource_size_t start,
                                          resource_size_t size,
                                          resource_size_t align);
-        void            (*add_bus)(struct pci_bus *bus);
-        void            (*remove_bus)(struct pci_bus *bus);
        void            *private_data;  /* platform controller private data     */
 };
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index e731018869a7..184def0e1652 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -274,11 +274,13 @@ static inline unsigned long __phys_to_virt(phys_addr_t x)
 * translation for translating DMA addresses.  Use the driver
 * DMA support - see dma-mapping.h.
 */
+#define virt_to_phys virt_to_phys
 static inline phys_addr_t virt_to_phys(const volatile void *x)
 {
        return __virt_to_phys((unsigned long)(x));
 }
+#define phys_to_virt phys_to_virt
 static inline void *phys_to_virt(phys_addr_t x)
 {
        return (void *)__phys_to_virt(x);
@@ -322,11 +324,13 @@ static inline phys_addr_t __virt_to_idmap(unsigned long x)
 #endif
 #ifdef CONFIG_VIRT_TO_BUS
+#define virt_to_bus virt_to_bus
 static inline __deprecated unsigned long virt_to_bus(void *x)
 {
        return __virt_to_bus((unsigned long)x);
 }
+#define bus_to_virt bus_to_virt
 static inline __deprecated void *bus_to_virt(unsigned long x)
 {
        return (void *)__bus_to_virt(x);
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index c3a83691af8e..d9cf138fd7d4 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -12,7 +12,7 @@
 #ifndef __ARM_PERF_EVENT_H__
 #define __ARM_PERF_EVENT_H__
-#ifdef CONFIG_HW_PERF_EVENTS
+#ifdef CONFIG_PERF_EVENTS
 struct pt_regs;
 extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
 extern unsigned long perf_misc_flags(struct pt_regs *regs);
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 0b648c541293..b1596bd59129 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -15,6 +15,8 @@
 #include <linux/interrupt.h>
 #include <linux/perf_event.h>
+#include <asm/cputype.h>
 /*
 * struct arm_pmu_platdata - ARM PMU platform data
 *
@@ -66,19 +68,25 @@ struct pmu_hw_events {
        /*
         * The events that are active on the PMU for the given index.
         */
-        struct perf_event       **events;
+        struct perf_event       *events[ARMPMU_MAX_HWEVENTS];
        /*
         * A 1 bit for an index indicates that the counter is being used for
         * an event. A 0 means that the counter can be used.
         */
-        unsigned long           *used_mask;
+        DECLARE_BITMAP(used_mask, ARMPMU_MAX_HWEVENTS);
        /*
         * Hardware lock to serialize accesses to PMU registers. Needed for the
         * read/modify/write sequences.
         */
        raw_spinlock_t          pmu_lock;
+        /*
+         * When using percpu IRQs, we need a percpu dev_id. Place it here as we
+         * already have to allocate this struct per cpu.
+         */
+        struct arm_pmu          *percpu_pmu;
 };
 struct arm_pmu {
@@ -107,7 +115,8 @@ struct arm_pmu {
        struct mutex    reserve_mutex;
        u64             max_period;
        struct platform_device  *plat_device;
-        struct pmu_hw_events    *(*get_hw_events)(void);
+        struct pmu_hw_events    __percpu *hw_events;
+        struct notifier_block   hotplug_nb;
 };
 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
@@ -127,6 +136,27 @@ int armpmu_map_event(struct perf_event *event,
                                                [PERF_COUNT_HW_CACHE_RESULT_MAX],
                     u32 raw_event_mask);
+struct pmu_probe_info {
+        unsigned int cpuid;
+        unsigned int mask;
+        int (*init)(struct arm_pmu *);
+};
+#define PMU_PROBE(_cpuid, _mask, _fn)   \
+{                                       \
+        .cpuid = (_cpuid),              \
+        .mask = (_mask),                \
+        .init = (_fn),                  \
+}
+#define ARM_PMU_PROBE(_cpuid, _fn) \
+        PMU_PROBE(_cpuid, ARM_CPU_PART_MASK, _fn)
+#define ARM_PMU_XSCALE_MASK     ((0xff << 24) | ARM_CPU_XSCALE_ARCH_MASK)
+#define XSCALE_PMU_PROBE(_version, _fn) \
+        PMU_PROBE(ARM_CPU_IMP_INTEL << 24 | _version, ARM_PMU_XSCALE_MASK, _fn)
 #endif /* CONFIG_HW_PERF_EVENTS */
 #endif /* __ARM_PMU_H__ */
diff --git a/arch/arm/include/debug/asm9260.S b/arch/arm/include/debug/asm9260.S
new file mode 100644
index 000000000000..292f85b49fca
--- /dev/null
+++ b/arch/arm/include/debug/asm9260.S
@@ -0,0 +1,29 @@
+/* Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *  Modified for ASM9260 by Oleksij Remepl <linux@rempel-privat.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+                .macro  addruart, rp, rv, tmp
+                ldr     \rp, = CONFIG_DEBUG_UART_PHYS
+                ldr     \rv, = CONFIG_DEBUG_UART_VIRT
+                .endm
+                .macro  waituart,rd,rx
+                .endm
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0x50]       @ TXDATA
+                .endm
+                .macro  busyuart,rd,rx
+1002:           ldr     \rd, [\rx, #0x60]       @ STAT
+                tst     \rd, #1 << 27           @ TXEMPTY
+                beq     1002b                   @ wait until transmit done
+                .endm
diff --git a/arch/arm/include/debug/renesas-scif.S b/arch/arm/include/debug/renesas-scif.S
new file mode 100644
index 000000000000..97820a8df51a
--- /dev/null
+++ b/arch/arm/include/debug/renesas-scif.S
@@ -0,0 +1,52 @@
+/*
+ * Renesas SCIF(A) debugging macro include header
+ *
+ * Based on r8a7790.S
+ *
+ * Copyright (C) 2012-2013 Renesas Electronics Corporation
+ * Copyright (C) 1994-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#define SCIF_PHYS       CONFIG_DEBUG_UART_PHYS
+#define SCIF_VIRT       ((SCIF_PHYS & 0x00ffffff) | 0xfd000000)
+#if CONFIG_DEBUG_UART_PHYS < 0xe6e00000
+/* SCIFA */
+#define FTDR            0x20
+#define FSR             0x14
+#else
+/* SCIF */
+#define FTDR            0x0c
+#define FSR             0x10
+#endif
+#define TDFE    (1 << 5)
+#define TEND    (1 << 6)
+        .macro  addruart, rp, rv, tmp
+        ldr     \rp, =SCIF_PHYS
+        ldr     \rv, =SCIF_VIRT
+        .endm
+        .macro  waituart, rd, rx
+1001:   ldrh    \rd, [\rx, #FSR]
+        tst     \rd, #TDFE
+        beq     1001b
+        .endm
+        .macro  senduart, rd, rx
+        strb    \rd, [\rx, #FTDR]
+        ldrh    \rd, [\rx, #FSR]
+        bic     \rd, \rd, #TEND
+        strh    \rd, [\rx, #FSR]
+        .endm
+        .macro  busyuart, rd, rx
+1001:   ldrh    \rd, [\rx, #FSR]
+        tst     \rd, #TEND
+        beq     1001b
+        .endm
diff --git a/arch/arm/mach-sa1100/include/mach/debug-macro.S b/arch/arm/include/debug/sa1100.S
index 530772d937ad..a0ae4f4cd924 100644
--- a/arch/arm/mach-sa1100/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/sa1100.S
@@ -1,4 +1,4 @@
-/* arch/arm/mach-sa1100/include/mach/debug-macro.S
+/* arch/arm/include/debug/sa1100.S
 *
 * Debugging macro include header
 *
@@ -10,7 +10,13 @@
 * published by the Free Software Foundation.
 *
 */
-#include <mach/hardware.h>
+#define UTCR3           0x0c
+#define UTDR            0x14
+#define UTSR1           0x20
+#define UTCR3_TXE       0x00000002      /* Transmit Enable                 */
+#define UTSR1_TBY       0x00000001      /* Transmitter BusY (read)         */
+#define UTSR1_TNF       0x00000004      /* Transmit FIFO Not Full (read)   */
                .macro  addruart, rp, rv, tmp
                mrc     p15, 0, \rp, c1, c0
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 38ddd9f83d0e..8dcbed5016ac 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -82,7 +82,7 @@ obj-$(CONFIG_CPU_MOHAWK)	+= xscale-cp0.o
 obj-$(CONFIG_CPU_PJ4)           += pj4-cp0.o
 obj-$(CONFIG_CPU_PJ4B)          += pj4-cp0.o
 obj-$(CONFIG_IWMMXT)            += iwmmxt.o
-obj-$(CONFIG_PERF_EVENTS)       += perf_regs.o
+obj-$(CONFIG_PERF_EVENTS)       += perf_regs.o perf_callchain.o
 obj-$(CONFIG_HW_PERF_EVENTS)    += perf_event.o perf_event_cpu.o
 AFLAGS_iwmmxt.o                 := -Wa,-mcpu=iwmmxt
 obj-$(CONFIG_ARM_CPU_TOPOLOGY)  += topology.o
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index 17a26c17f7f5..daaff73bc776 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -18,6 +18,15 @@
 static int debug_pci;
+#ifdef CONFIG_PCI_MSI
+struct msi_controller *pcibios_msi_controller(struct pci_dev *dev)
+{
+        struct pci_sys_data *sysdata = dev->bus->sysdata;
+        return sysdata->msi_ctrl;
+}
+#endif
 /*
 * We can't use pci_get_device() here since we are
 * called from interrupt context.
@@ -360,20 +369,6 @@ void pcibios_fixup_bus(struct pci_bus *bus)
 }
 EXPORT_SYMBOL(pcibios_fixup_bus);
-void pcibios_add_bus(struct pci_bus *bus)
-{
-        struct pci_sys_data *sys = bus->sysdata;
-        if (sys->add_bus)
-                sys->add_bus(bus);
-}
-void pcibios_remove_bus(struct pci_bus *bus)
-{
-        struct pci_sys_data *sys = bus->sysdata;
-        if (sys->remove_bus)
-                sys->remove_bus(bus);
-}
 /*
 * Swizzle the device pin each time we cross a bridge.  If a platform does
 * not provide a swizzle function, we perform the standard PCI swizzling.
@@ -471,12 +466,13 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
 #ifdef CONFIG_PCI_DOMAINS
                sys->domain  = hw->domain;
 #endif
+#ifdef CONFIG_PCI_MSI
+                sys->msi_ctrl = hw->msi_ctrl;
+#endif
                sys->busnr   = busnr;
                sys->swizzle = hw->swizzle;
                sys->map_irq = hw->map_irq;
                sys->align_resource = hw->align_resource;
-                sys->add_bus = hw->add_bus;
-                sys->remove_bus = hw->remove_bus;
                INIT_LIST_HEAD(&sys->resources);
                if (hw->private_data)
diff --git a/arch/arm/kernel/perf_callchain.c b/arch/arm/kernel/perf_callchain.c
new file mode 100644
index 000000000000..4e02ae5950ff
--- /dev/null
+++ b/arch/arm/kernel/perf_callchain.c
@@ -0,0 +1,136 @@
+/*
+ * ARM callchain support
+ *
+ * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
+ * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
+ *
+ * This code is based on the ARM OProfile backtrace code.
+ */
+#include <linux/perf_event.h>
+#include <linux/uaccess.h>
+#include <asm/stacktrace.h>
+/*
+ * The registers we're interested in are at the end of the variable
+ * length saved register structure. The fp points at the end of this
+ * structure so the address of this struct is:
+ * (struct frame_tail *)(xxx->fp)-1
+ *
+ * This code has been adapted from the ARM OProfile support.
+ */
+struct frame_tail {
+        struct frame_tail __user *fp;
+        unsigned long sp;
+        unsigned long lr;
+} __attribute__((packed));
+/*
+ * Get the return address for a single stackframe and return a pointer to the
+ * next frame tail.
+ */
+static struct frame_tail __user *
+user_backtrace(struct frame_tail __user *tail,
+               struct perf_callchain_entry *entry)
+{
+        struct frame_tail buftail;
+        unsigned long err;
+        if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
+                return NULL;
+        pagefault_disable();
+        err = __copy_from_user_inatomic(&buftail, tail, sizeof(buftail));
+        pagefault_enable();
+        if (err)
+                return NULL;
+        perf_callchain_store(entry, buftail.lr);
+        /*
+         * Frame pointers should strictly progress back up the stack
+         * (towards higher addresses).
+         */
+        if (tail + 1 >= buftail.fp)
+                return NULL;
+        return buftail.fp - 1;
+}
+void
+perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
+{
+        struct frame_tail __user *tail;
+        if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
+                /* We don't support guest os callchain now */
+                return;
+        }
+        perf_callchain_store(entry, regs->ARM_pc);
+        if (!current->mm)
+                return;
+        tail = (struct frame_tail __user *)regs->ARM_fp - 1;
+        while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
+               tail && !((unsigned long)tail & 0x3))
+                tail = user_backtrace(tail, entry);
+}
+/*
+ * Gets called by walk_stackframe() for every stackframe. This will be called
+ * whist unwinding the stackframe and is like a subroutine return so we use
+ * the PC.
+ */
+static int
+callchain_trace(struct stackframe *fr,
+                void *data)
+{
+        struct perf_callchain_entry *entry = data;
+        perf_callchain_store(entry, fr->pc);
+        return 0;
+}
+void
+perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
+{
+        struct stackframe fr;
+        if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
+                /* We don't support guest os callchain now */
+                return;
+        }
+        arm_get_current_stackframe(regs, &fr);
+        walk_stackframe(&fr, callchain_trace, entry);
+}
+unsigned long perf_instruction_pointer(struct pt_regs *regs)
+{
+        if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
+                return perf_guest_cbs->get_guest_ip();
+        return instruction_pointer(regs);
+}
+unsigned long perf_misc_flags(struct pt_regs *regs)
+{
+        int misc = 0;
+        if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
+                if (perf_guest_cbs->is_user_mode())
+                        misc |= PERF_RECORD_MISC_GUEST_USER;
+                else
+                        misc |= PERF_RECORD_MISC_GUEST_KERNEL;
+        } else {
+                if (user_mode(regs))
+                        misc |= PERF_RECORD_MISC_USER;
+                else
+                        misc |= PERF_RECORD_MISC_KERNEL;
+        }
+        return misc;
+}
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 266cba46db3e..e34934f63a49 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -7,21 +7,18 @@
 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
 *
 * This code is based on the sparc64 perf event code, which is in turn based
- * on the x86 code. Callchain code is based on the ARM OProfile backtrace
+ * on the x86 code.
- * code.
 */
 #define pr_fmt(fmt) "hw perfevents: " fmt
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
-#include <linux/uaccess.h>
 #include <linux/irq.h>
 #include <linux/irqdesc.h>
 #include <asm/irq_regs.h>
 #include <asm/pmu.h>
-#include <asm/stacktrace.h>
 static int
 armpmu_map_cache_event(const unsigned (*cache_map)
@@ -80,8 +77,12 @@ armpmu_map_event(struct perf_event *event,
                 u32 raw_event_mask)
 {
        u64 config = event->attr.config;
+        int type = event->attr.type;
-        switch (event->attr.type) {
+        if (type == event->pmu->type)
+                return armpmu_map_raw_event(raw_event_mask, config);
+        switch (type) {
        case PERF_TYPE_HARDWARE:
                return armpmu_map_hw_event(event_map, config);
        case PERF_TYPE_HW_CACHE:
@@ -200,7 +201,7 @@ static void
 armpmu_del(struct perf_event *event, int flags)
 {
        struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
-        struct pmu_hw_events *hw_events = armpmu->get_hw_events();
+        struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
        struct hw_perf_event *hwc = &event->hw;
        int idx = hwc->idx;
@@ -217,7 +218,7 @@ static int
 armpmu_add(struct perf_event *event, int flags)
 {
        struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
-        struct pmu_hw_events *hw_events = armpmu->get_hw_events();
+        struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
        struct hw_perf_event *hwc = &event->hw;
        int idx;
        int err = 0;
@@ -274,14 +275,12 @@ validate_group(struct perf_event *event)
 {
        struct perf_event *sibling, *leader = event->group_leader;
        struct pmu_hw_events fake_pmu;
-        DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
        /*
         * Initialise the fake PMU. We only need to populate the
         * used_mask for the purposes of validation.
         */
-        memset(fake_used_mask, 0, sizeof(fake_used_mask));
+        memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask));
-        fake_pmu.used_mask = fake_used_mask;
        if (!validate_event(&fake_pmu, leader))
                return -EINVAL;
@@ -305,17 +304,21 @@ static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
        int ret;
        u64 start_clock, finish_clock;
-        if (irq_is_percpu(irq))
+        /*
-                dev = *(void **)dev;
+         * we request the IRQ with a (possibly percpu) struct arm_pmu**, but
-        armpmu = dev;
+         * the handlers expect a struct arm_pmu*. The percpu_irq framework will
+         * do any necessary shifting, we just need to perform the first
+         * dereference.
+         */
+        armpmu = *(void **)dev;
        plat_device = armpmu->plat_device;
        plat = dev_get_platdata(&plat_device->dev);
        start_clock = sched_clock();
        if (plat && plat->handle_irq)
-                ret = plat->handle_irq(irq, dev, armpmu->handle_irq);
+                ret = plat->handle_irq(irq, armpmu, armpmu->handle_irq);
        else
-                ret = armpmu->handle_irq(irq, dev);
+                ret = armpmu->handle_irq(irq, armpmu);
        finish_clock = sched_clock();
        perf_sample_event_took(finish_clock - start_clock);
@@ -468,7 +471,7 @@ static int armpmu_event_init(struct perf_event *event)
 static void armpmu_enable(struct pmu *pmu)
 {
        struct arm_pmu *armpmu = to_arm_pmu(pmu);
-        struct pmu_hw_events *hw_events = armpmu->get_hw_events();
+        struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
        int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
        if (enabled)
@@ -533,130 +536,3 @@ int armpmu_register(struct arm_pmu *armpmu, int type)
        return perf_pmu_register(&armpmu->pmu, armpmu->name, type);
 }
-/*
- * Callchain handling code.
- */
-/*
- * The registers we're interested in are at the end of the variable
- * length saved register structure. The fp points at the end of this
- * structure so the address of this struct is:
- * (struct frame_tail *)(xxx->fp)-1
- *
- * This code has been adapted from the ARM OProfile support.
- */
-struct frame_tail {
-        struct frame_tail __user *fp;
-        unsigned long sp;
-        unsigned long lr;
-} __attribute__((packed));
-/*
- * Get the return address for a single stackframe and return a pointer to the
- * next frame tail.
- */
-static struct frame_tail __user *
-user_backtrace(struct frame_tail __user *tail,
-               struct perf_callchain_entry *entry)
-{
-        struct frame_tail buftail;
-        unsigned long err;
-        if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
-                return NULL;
-        pagefault_disable();
-        err = __copy_from_user_inatomic(&buftail, tail, sizeof(buftail));
-        pagefault_enable();
-        if (err)
-                return NULL;
-        perf_callchain_store(entry, buftail.lr);
-        /*
-         * Frame pointers should strictly progress back up the stack
-         * (towards higher addresses).
-         */
-        if (tail + 1 >= buftail.fp)
-                return NULL;
-        return buftail.fp - 1;
-}
-void
-perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
-{
-        struct frame_tail __user *tail;
-        if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
-                /* We don't support guest os callchain now */
-                return;
-        }
-        perf_callchain_store(entry, regs->ARM_pc);
-        if (!current->mm)
-                return;
-        tail = (struct frame_tail __user *)regs->ARM_fp - 1;
-        while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
-               tail && !((unsigned long)tail & 0x3))
-                tail = user_backtrace(tail, entry);
-}
-/*
- * Gets called by walk_stackframe() for every stackframe. This will be called
- * whist unwinding the stackframe and is like a subroutine return so we use
- * the PC.
- */
-static int
-callchain_trace(struct stackframe *fr,
-                void *data)
-{
-        struct perf_callchain_entry *entry = data;
-        perf_callchain_store(entry, fr->pc);
-        return 0;
-}
-void
-perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
-{
-        struct stackframe fr;
-        if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
-                /* We don't support guest os callchain now */
-                return;
-        }
-        arm_get_current_stackframe(regs, &fr);
-        walk_stackframe(&fr, callchain_trace, entry);
-}
-unsigned long perf_instruction_pointer(struct pt_regs *regs)
-{
-        if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
-                return perf_guest_cbs->get_guest_ip();
-        return instruction_pointer(regs);
-}
-unsigned long perf_misc_flags(struct pt_regs *regs)
-{
-        int misc = 0;
-        if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
-                if (perf_guest_cbs->is_user_mode())
-                        misc |= PERF_RECORD_MISC_GUEST_USER;
-                else
-                        misc |= PERF_RECORD_MISC_GUEST_KERNEL;
-        } else {
-                if (user_mode(regs))
-                        misc |= PERF_RECORD_MISC_USER;
-                else
-                        misc |= PERF_RECORD_MISC_KERNEL;
-        }
-        return misc;
-}
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
index eb2c4d55666b..dd9acc95ebc0 100644
--- a/arch/arm/kernel/perf_event_cpu.c
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -35,11 +35,6 @@
 /* Set at runtime when we know what CPU type we are. */
 static struct arm_pmu *cpu_pmu;
-static DEFINE_PER_CPU(struct arm_pmu *, percpu_pmu);
-static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
-static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
-static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
 /*
 * Despite the names, these two functions are CPU-specific and are used
 * by the OProfile/perf code.
@@ -69,11 +64,6 @@ EXPORT_SYMBOL_GPL(perf_num_counters);
 #include "perf_event_v6.c"
 #include "perf_event_v7.c"
-static struct pmu_hw_events *cpu_pmu_get_cpu_events(void)
-{
-        return this_cpu_ptr(&cpu_hw_events);
-}
 static void cpu_pmu_enable_percpu_irq(void *data)
 {
        int irq = *(int *)data;
@@ -92,20 +82,21 @@ static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu)
 {
        int i, irq, irqs;
        struct platform_device *pmu_device = cpu_pmu->plat_device;
+        struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events;
        irqs = min(pmu_device->num_resources, num_possible_cpus());
        irq = platform_get_irq(pmu_device, 0);
        if (irq >= 0 && irq_is_percpu(irq)) {
                on_each_cpu(cpu_pmu_disable_percpu_irq, &irq, 1);
-                free_percpu_irq(irq, &percpu_pmu);
+                free_percpu_irq(irq, &hw_events->percpu_pmu);
        } else {
                for (i = 0; i < irqs; ++i) {
                        if (!cpumask_test_and_clear_cpu(i, &cpu_pmu->active_irqs))
                                continue;
                        irq = platform_get_irq(pmu_device, i);
                        if (irq >= 0)
-                                free_irq(irq, cpu_pmu);
+                                free_irq(irq, per_cpu_ptr(&hw_events->percpu_pmu, i));
                }
        }
 }
@@ -114,19 +105,21 @@ static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
 {
        int i, err, irq, irqs;
        struct platform_device *pmu_device = cpu_pmu->plat_device;
+        struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events;
        if (!pmu_device)
                return -ENODEV;
        irqs = min(pmu_device->num_resources, num_possible_cpus());
        if (irqs < 1) {
-                printk_once("perf/ARM: No irqs for PMU defined, sampling events not supported\n");
+                pr_warn_once("perf/ARM: No irqs for PMU defined, sampling events not supported\n");
                return 0;
        }
        irq = platform_get_irq(pmu_device, 0);
        if (irq >= 0 && irq_is_percpu(irq)) {
-                err = request_percpu_irq(irq, handler, "arm-pmu", &percpu_pmu);
+                err = request_percpu_irq(irq, handler, "arm-pmu",
+                                         &hw_events->percpu_pmu);
                if (err) {
                        pr_err("unable to request IRQ%d for ARM PMU counters\n",
                                irq);
@@ -153,7 +146,7 @@ static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
                        err = request_irq(irq, handler,
                                          IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu",
-                                          cpu_pmu);
+                                          per_cpu_ptr(&hw_events->percpu_pmu, i));
                        if (err) {
                                pr_err("unable to request IRQ%d for ARM PMU counters\n",
                                        irq);
@@ -167,18 +160,50 @@ static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
        return 0;
 }
-static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
+/*
+ * PMU hardware loses all context when a CPU goes offline.
+ * When a CPU is hotplugged back in, since some hardware registers are
+ * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
+ * junk values out of them.
+ */
+static int cpu_pmu_notify(struct notifier_block *b, unsigned long action,
+                          void *hcpu)
+{
+        struct arm_pmu *pmu = container_of(b, struct arm_pmu, hotplug_nb);
+        if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
+                return NOTIFY_DONE;
+        if (pmu->reset)
+                pmu->reset(pmu);
+        else
+                return NOTIFY_DONE;
+        return NOTIFY_OK;
+}
+static int cpu_pmu_init(struct arm_pmu *cpu_pmu)
 {
+        int err;
        int cpu;
+        struct pmu_hw_events __percpu *cpu_hw_events;
+        cpu_hw_events = alloc_percpu(struct pmu_hw_events);
+        if (!cpu_hw_events)
+                return -ENOMEM;
+        cpu_pmu->hotplug_nb.notifier_call = cpu_pmu_notify;
+        err = register_cpu_notifier(&cpu_pmu->hotplug_nb);
+        if (err)
+                goto out_hw_events;
        for_each_possible_cpu(cpu) {
-                struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
+                struct pmu_hw_events *events = per_cpu_ptr(cpu_hw_events, cpu);
-                events->events = per_cpu(hw_events, cpu);
-                events->used_mask = per_cpu(used_mask, cpu);
                raw_spin_lock_init(&events->pmu_lock);
-                per_cpu(percpu_pmu, cpu) = cpu_pmu;
+                events->percpu_pmu = cpu_pmu;
        }
-        cpu_pmu->get_hw_events  = cpu_pmu_get_cpu_events;
+        cpu_pmu->hw_events      = cpu_hw_events;
        cpu_pmu->request_irq    = cpu_pmu_request_irq;
        cpu_pmu->free_irq       = cpu_pmu_free_irq;
@@ -189,31 +214,19 @@ static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
        /* If no interrupts available, set the corresponding capability flag */
        if (!platform_get_irq(cpu_pmu->plat_device, 0))
                cpu_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
-}
-/*
- * PMU hardware loses all context when a CPU goes offline.
- * When a CPU is hotplugged back in, since some hardware registers are
- * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
- * junk values out of them.
- */
-static int cpu_pmu_notify(struct notifier_block *b, unsigned long action,
-                          void *hcpu)
-{
-        if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
-                return NOTIFY_DONE;
-        if (cpu_pmu && cpu_pmu->reset)
+        return 0;
-                cpu_pmu->reset(cpu_pmu);
-        else
-                return NOTIFY_DONE;
-        return NOTIFY_OK;
+out_hw_events:
+        free_percpu(cpu_hw_events);
+        return err;
 }
-static struct notifier_block cpu_pmu_hotplug_notifier = {
+static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
-        .notifier_call = cpu_pmu_notify,
+{
-};
+        unregister_cpu_notifier(&cpu_pmu->hotplug_nb);
+        free_percpu(cpu_pmu->hw_events);
+}
 /*
 * PMU platform driver and devicetree bindings.
@@ -241,48 +254,34 @@ static struct platform_device_id cpu_pmu_plat_device_ids[] = {
        {},
 };
+static const struct pmu_probe_info pmu_probe_table[] = {
+        ARM_PMU_PROBE(ARM_CPU_PART_ARM1136, armv6_1136_pmu_init),
+        ARM_PMU_PROBE(ARM_CPU_PART_ARM1156, armv6_1156_pmu_init),
+        ARM_PMU_PROBE(ARM_CPU_PART_ARM1176, armv6_1176_pmu_init),
+        ARM_PMU_PROBE(ARM_CPU_PART_ARM11MPCORE, armv6mpcore_pmu_init),
+        ARM_PMU_PROBE(ARM_CPU_PART_CORTEX_A8, armv7_a8_pmu_init),
+        ARM_PMU_PROBE(ARM_CPU_PART_CORTEX_A9, armv7_a9_pmu_init),
+        XSCALE_PMU_PROBE(ARM_CPU_XSCALE_ARCH_V1, xscale1pmu_init),
+        XSCALE_PMU_PROBE(ARM_CPU_XSCALE_ARCH_V2, xscale2pmu_init),
+        { /* sentinel value */ }
+};
 /*
 * CPU PMU identification and probing.
 */
 static int probe_current_pmu(struct arm_pmu *pmu)
 {
        int cpu = get_cpu();
+        unsigned int cpuid = read_cpuid_id();
        int ret = -ENODEV;
+        const struct pmu_probe_info *info;
        pr_info("probing PMU on CPU %d\n", cpu);
-        switch (read_cpuid_part()) {
+        for (info = pmu_probe_table; info->init != NULL; info++) {
-        /* ARM Ltd CPUs. */
+                if ((cpuid & info->mask) != info->cpuid)
-        case ARM_CPU_PART_ARM1136:
+                        continue;
-                ret = armv6_1136_pmu_init(pmu);
+                ret = info->init(pmu);
-                break;
-        case ARM_CPU_PART_ARM1156:
-                ret = armv6_1156_pmu_init(pmu);
-                break;
-        case ARM_CPU_PART_ARM1176:
-                ret = armv6_1176_pmu_init(pmu);
-                break;
-        case ARM_CPU_PART_ARM11MPCORE:
-                ret = armv6mpcore_pmu_init(pmu);
-                break;
-        case ARM_CPU_PART_CORTEX_A8:
-                ret = armv7_a8_pmu_init(pmu);
-                break;
-        case ARM_CPU_PART_CORTEX_A9:
-                ret = armv7_a9_pmu_init(pmu);
-                break;
-        default:
-                if (read_cpuid_implementor() == ARM_CPU_IMP_INTEL) {
-                        switch (xscale_cpu_arch_version()) {
-                        case ARM_CPU_XSCALE_ARCH_V1:
-                                ret = xscale1pmu_init(pmu);
-                                break;
-                        case ARM_CPU_XSCALE_ARCH_V2:
-                                ret = xscale2pmu_init(pmu);
-                                break;
-                        }
-                }
                break;
        }
@@ -299,13 +298,13 @@ static int cpu_pmu_device_probe(struct platform_device *pdev)
        int ret = -ENODEV;
        if (cpu_pmu) {
-                pr_info("attempt to register multiple PMU devices!");
+                pr_info("attempt to register multiple PMU devices!\n");
                return -ENOSPC;
        }
        pmu = kzalloc(sizeof(struct arm_pmu), GFP_KERNEL);
        if (!pmu) {
-                pr_info("failed to allocate PMU device!");
+                pr_info("failed to allocate PMU device!\n");
                return -ENOMEM;
        }
@@ -320,18 +319,24 @@ static int cpu_pmu_device_probe(struct platform_device *pdev)
        }
        if (ret) {
-                pr_info("failed to probe PMU!");
+                pr_info("failed to probe PMU!\n");
                goto out_free;
        }
-        cpu_pmu_init(cpu_pmu);
+        ret = cpu_pmu_init(cpu_pmu);
-        ret = armpmu_register(cpu_pmu, PERF_TYPE_RAW);
+        if (ret)
+                goto out_free;
-        if (!ret)
+        ret = armpmu_register(cpu_pmu, -1);
-                return 0;
+        if (ret)
+                goto out_destroy;
+        return 0;
+out_destroy:
+        cpu_pmu_destroy(cpu_pmu);
 out_free:
-        pr_info("failed to register PMU devices!");
+        pr_info("failed to register PMU devices!\n");
        kfree(pmu);
        return ret;
 }
@@ -348,16 +353,6 @@ static struct platform_driver cpu_pmu_driver = {
 static int __init register_pmu_driver(void)
 {
-        int err;
+        return platform_driver_register(&cpu_pmu_driver);
-        err = register_cpu_notifier(&cpu_pmu_hotplug_notifier);
-        if (err)
-                return err;
-        err = platform_driver_register(&cpu_pmu_driver);
-        if (err)
-                unregister_cpu_notifier(&cpu_pmu_hotplug_notifier);
-        return err;
 }
 device_initcall(register_pmu_driver);
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index abfeb04f3213..f2ffd5c542ed 100644
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -262,7 +262,7 @@ static void armv6pmu_enable_event(struct perf_event *event)
        unsigned long val, mask, evt, flags;
        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
        struct hw_perf_event *hwc = &event->hw;
-        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
        int idx = hwc->idx;
        if (ARMV6_CYCLE_COUNTER == idx) {
@@ -300,7 +300,7 @@ armv6pmu_handle_irq(int irq_num,
        unsigned long pmcr = armv6_pmcr_read();
        struct perf_sample_data data;
        struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
-        struct pmu_hw_events *cpuc = cpu_pmu->get_hw_events();
+        struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
        struct pt_regs *regs;
        int idx;
@@ -356,7 +356,7 @@ armv6pmu_handle_irq(int irq_num,
 static void armv6pmu_start(struct arm_pmu *cpu_pmu)
 {
        unsigned long flags, val;
-        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
        raw_spin_lock_irqsave(&events->pmu_lock, flags);
        val = armv6_pmcr_read();
@@ -368,7 +368,7 @@ static void armv6pmu_start(struct arm_pmu *cpu_pmu)
 static void armv6pmu_stop(struct arm_pmu *cpu_pmu)
 {
        unsigned long flags, val;
-        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
        raw_spin_lock_irqsave(&events->pmu_lock, flags);
        val = armv6_pmcr_read();
@@ -409,7 +409,7 @@ static void armv6pmu_disable_event(struct perf_event *event)
        unsigned long val, mask, evt, flags;
        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
        struct hw_perf_event *hwc = &event->hw;
-        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
        int idx = hwc->idx;
        if (ARMV6_CYCLE_COUNTER == idx) {
@@ -444,7 +444,7 @@ static void armv6mpcore_pmu_disable_event(struct perf_event *event)
        unsigned long val, mask, flags, evt = 0;
        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
        struct hw_perf_event *hwc = &event->hw;
-        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
        int idx = hwc->idx;
        if (ARMV6_CYCLE_COUNTER == idx) {
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 116758b77f93..8993770c47de 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -564,13 +564,11 @@ static inline int armv7_pmnc_counter_has_overflowed(u32 pmnc, int idx)
        return pmnc & BIT(ARMV7_IDX_TO_COUNTER(idx));
 }
-static inline int armv7_pmnc_select_counter(int idx)
+static inline void armv7_pmnc_select_counter(int idx)
 {
        u32 counter = ARMV7_IDX_TO_COUNTER(idx);
        asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (counter));
        isb();
-        return idx;
 }
 static inline u32 armv7pmu_read_counter(struct perf_event *event)
@@ -580,13 +578,15 @@ static inline u32 armv7pmu_read_counter(struct perf_event *event)
        int idx = hwc->idx;
        u32 value = 0;
-        if (!armv7_pmnc_counter_valid(cpu_pmu, idx))
+        if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) {
                pr_err("CPU%u reading wrong counter %d\n",
                        smp_processor_id(), idx);
-        else if (idx == ARMV7_IDX_CYCLE_COUNTER)
+        } else if (idx == ARMV7_IDX_CYCLE_COUNTER) {
                asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value));
-        else if (armv7_pmnc_select_counter(idx) == idx)
+        } else {
+                armv7_pmnc_select_counter(idx);
                asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (value));
+        }
        return value;
 }
@@ -597,45 +597,43 @@ static inline void armv7pmu_write_counter(struct perf_event *event, u32 value)
        struct hw_perf_event *hwc = &event->hw;
        int idx = hwc->idx;
-        if (!armv7_pmnc_counter_valid(cpu_pmu, idx))
+        if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) {
                pr_err("CPU%u writing wrong counter %d\n",
                        smp_processor_id(), idx);
-        else if (idx == ARMV7_IDX_CYCLE_COUNTER)
+        } else if (idx == ARMV7_IDX_CYCLE_COUNTER) {
                asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value));
-        else if (armv7_pmnc_select_counter(idx) == idx)
+        } else {
+                armv7_pmnc_select_counter(idx);
                asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (value));
+        }
 }
 static inline void armv7_pmnc_write_evtsel(int idx, u32 val)
 {
-        if (armv7_pmnc_select_counter(idx) == idx) {
+        armv7_pmnc_select_counter(idx);
-                val &= ARMV7_EVTYPE_MASK;
+        val &= ARMV7_EVTYPE_MASK;
-                asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
+        asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
-        }
 }
-static inline int armv7_pmnc_enable_counter(int idx)
+static inline void armv7_pmnc_enable_counter(int idx)
 {
        u32 counter = ARMV7_IDX_TO_COUNTER(idx);
        asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(counter)));
-        return idx;
 }
-static inline int armv7_pmnc_disable_counter(int idx)
+static inline void armv7_pmnc_disable_counter(int idx)
 {
        u32 counter = ARMV7_IDX_TO_COUNTER(idx);
        asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(counter)));
-        return idx;
 }
-static inline int armv7_pmnc_enable_intens(int idx)
+static inline void armv7_pmnc_enable_intens(int idx)
 {
        u32 counter = ARMV7_IDX_TO_COUNTER(idx);
        asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(counter)));
-        return idx;
 }
-static inline int armv7_pmnc_disable_intens(int idx)
+static inline void armv7_pmnc_disable_intens(int idx)
 {
        u32 counter = ARMV7_IDX_TO_COUNTER(idx);
        asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter)));
@@ -643,8 +641,6 @@ static inline int armv7_pmnc_disable_intens(int idx)
        /* Clear the overflow flag in case an interrupt is pending. */
        asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(counter)));
        isb();
-        return idx;
 }
 static inline u32 armv7_pmnc_getreset_flags(void)
@@ -667,34 +663,34 @@ static void armv7_pmnc_dump_regs(struct arm_pmu *cpu_pmu)
        u32 val;
        unsigned int cnt;
-        printk(KERN_INFO "PMNC registers dump:\n");
+        pr_info("PMNC registers dump:\n");
        asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
-        printk(KERN_INFO "PMNC  =0x%08x\n", val);
+        pr_info("PMNC  =0x%08x\n", val);
        asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
-        printk(KERN_INFO "CNTENS=0x%08x\n", val);
+        pr_info("CNTENS=0x%08x\n", val);
        asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val));
-        printk(KERN_INFO "INTENS=0x%08x\n", val);
+        pr_info("INTENS=0x%08x\n", val);
        asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
-        printk(KERN_INFO "FLAGS =0x%08x\n", val);
+        pr_info("FLAGS =0x%08x\n", val);
        asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val));
-        printk(KERN_INFO "SELECT=0x%08x\n", val);
+        pr_info("SELECT=0x%08x\n", val);
        asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
-        printk(KERN_INFO "CCNT  =0x%08x\n", val);
+        pr_info("CCNT  =0x%08x\n", val);
        for (cnt = ARMV7_IDX_COUNTER0;
                        cnt <= ARMV7_IDX_COUNTER_LAST(cpu_pmu); cnt++) {
                armv7_pmnc_select_counter(cnt);
                asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
-                printk(KERN_INFO "CNT[%d] count =0x%08x\n",
+                pr_info("CNT[%d] count =0x%08x\n",
                        ARMV7_IDX_TO_COUNTER(cnt), val);
                asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));
-                printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n",
+                pr_info("CNT[%d] evtsel=0x%08x\n",
                        ARMV7_IDX_TO_COUNTER(cnt), val);
        }
 }
@@ -705,7 +701,7 @@ static void armv7pmu_enable_event(struct perf_event *event)
        unsigned long flags;
        struct hw_perf_event *hwc = &event->hw;
        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
-        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
        int idx = hwc->idx;
        if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) {
@@ -751,7 +747,7 @@ static void armv7pmu_disable_event(struct perf_event *event)
        unsigned long flags;
        struct hw_perf_event *hwc = &event->hw;
        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
-        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
        int idx = hwc->idx;
        if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) {
@@ -783,7 +779,7 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
        u32 pmnc;
        struct perf_sample_data data;
        struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
-        struct pmu_hw_events *cpuc = cpu_pmu->get_hw_events();
+        struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
        struct pt_regs *regs;
        int idx;
@@ -843,7 +839,7 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
 static void armv7pmu_start(struct arm_pmu *cpu_pmu)
 {
        unsigned long flags;
-        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
        raw_spin_lock_irqsave(&events->pmu_lock, flags);
        /* Enable all counters */
@@ -854,7 +850,7 @@ static void armv7pmu_start(struct arm_pmu *cpu_pmu)
 static void armv7pmu_stop(struct arm_pmu *cpu_pmu)
 {
        unsigned long flags;
-        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
        raw_spin_lock_irqsave(&events->pmu_lock, flags);
        /* Disable all counters */
@@ -1287,7 +1283,7 @@ static void krait_pmu_disable_event(struct perf_event *event)
        struct hw_perf_event *hwc = &event->hw;
        int idx = hwc->idx;
        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
-        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
        /* Disable counter and interrupt */
        raw_spin_lock_irqsave(&events->pmu_lock, flags);
@@ -1313,7 +1309,7 @@ static void krait_pmu_enable_event(struct perf_event *event)
        struct hw_perf_event *hwc = &event->hw;
        int idx = hwc->idx;
        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
-        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
        /*
         * Enable counter and interrupt, and set the counter to count
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
index 08da0af550b7..8af9f1f82c68 100644
--- a/arch/arm/kernel/perf_event_xscale.c
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -138,7 +138,7 @@ xscale1pmu_handle_irq(int irq_num, void *dev)
        unsigned long pmnc;
        struct perf_sample_data data;
        struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
-        struct pmu_hw_events *cpuc = cpu_pmu->get_hw_events();
+        struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
        struct pt_regs *regs;
        int idx;
@@ -198,7 +198,7 @@ static void xscale1pmu_enable_event(struct perf_event *event)
        unsigned long val, mask, evt, flags;
        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
        struct hw_perf_event *hwc = &event->hw;
-        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
        int idx = hwc->idx;
        switch (idx) {
@@ -234,7 +234,7 @@ static void xscale1pmu_disable_event(struct perf_event *event)
        unsigned long val, mask, evt, flags;
        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
        struct hw_perf_event *hwc = &event->hw;
-        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
        int idx = hwc->idx;
        switch (idx) {
@@ -287,7 +287,7 @@ xscale1pmu_get_event_idx(struct pmu_hw_events *cpuc,
 static void xscale1pmu_start(struct arm_pmu *cpu_pmu)
 {
        unsigned long flags, val;
-        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
        raw_spin_lock_irqsave(&events->pmu_lock, flags);
        val = xscale1pmu_read_pmnc();
@@ -299,7 +299,7 @@ static void xscale1pmu_start(struct arm_pmu *cpu_pmu)
 static void xscale1pmu_stop(struct arm_pmu *cpu_pmu)
 {
        unsigned long flags, val;
-        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
        raw_spin_lock_irqsave(&events->pmu_lock, flags);
        val = xscale1pmu_read_pmnc();
@@ -485,7 +485,7 @@ xscale2pmu_handle_irq(int irq_num, void *dev)
        unsigned long pmnc, of_flags;
        struct perf_sample_data data;
        struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
-        struct pmu_hw_events *cpuc = cpu_pmu->get_hw_events();
+        struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
        struct pt_regs *regs;
        int idx;
@@ -539,7 +539,7 @@ static void xscale2pmu_enable_event(struct perf_event *event)
        unsigned long flags, ien, evtsel;
        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
        struct hw_perf_event *hwc = &event->hw;
-        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
        int idx = hwc->idx;
        ien = xscale2pmu_read_int_enable();
@@ -585,7 +585,7 @@ static void xscale2pmu_disable_event(struct perf_event *event)
        unsigned long flags, ien, evtsel, of_flags;
        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
        struct hw_perf_event *hwc = &event->hw;
-        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
        int idx = hwc->idx;
        ien = xscale2pmu_read_int_enable();
@@ -651,7 +651,7 @@ out:
 static void xscale2pmu_start(struct arm_pmu *cpu_pmu)
 {
        unsigned long flags, val;
-        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
        raw_spin_lock_irqsave(&events->pmu_lock, flags);
        val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64;
@@ -663,7 +663,7 @@ static void xscale2pmu_start(struct arm_pmu *cpu_pmu)
 static void xscale2pmu_stop(struct arm_pmu *cpu_pmu)
 {
        unsigned long flags, val;
-        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
        raw_spin_lock_irqsave(&events->pmu_lock, flags);
        val = xscale2pmu_read_pmnc();
diff --git a/arch/arm/mach-asm9260/Kconfig b/arch/arm/mach-asm9260/Kconfig
new file mode 100644
index 000000000000..8423be76080e
--- /dev/null
+++ b/arch/arm/mach-asm9260/Kconfig
@@ -0,0 +1,6 @@
+config MACH_ASM9260
+        bool "Alphascale ASM9260"
+        depends on ARCH_MULTI_V5
+        select CPU_ARM926T
+        help
+          Support for Alphascale ASM9260 based platform.
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 0e6d548b70d9..2395c68b3e32 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -15,27 +15,10 @@ config HAVE_AT91_DBGU1
 config HAVE_AT91_DBGU2
        bool
-config AT91_USE_OLD_CLK
-        bool
-config AT91_PMC_UNIT
-        bool
-        default !ARCH_AT91X40
 config COMMON_CLK_AT91
        bool
-        default AT91_PMC_UNIT && USE_OF && !AT91_USE_OLD_CLK
        select COMMON_CLK
-config OLD_CLK_AT91
-        bool
-        default AT91_PMC_UNIT && AT91_USE_OLD_CLK
-config OLD_IRQ_AT91
-        bool
-        select MULTI_IRQ_HANDLER
-        select SPARSE_IRQ
 config HAVE_AT91_SMD
        bool
@@ -44,20 +27,22 @@ config HAVE_AT91_H32MX
 config SOC_AT91SAM9
        bool
-        select ATMEL_AIC_IRQ if !OLD_IRQ_AT91
+        select ATMEL_AIC_IRQ
+        select COMMON_CLK_AT91
        select CPU_ARM926T
        select GENERIC_CLOCKEVENTS
-        select MEMORY if USE_OF
+        select MEMORY
-        select ATMEL_SDRAMC if USE_OF
+        select ATMEL_SDRAMC
 config SOC_SAMA5
        bool
        select ATMEL_AIC5_IRQ
+        select COMMON_CLK_AT91
        select CPU_V7
        select GENERIC_CLOCKEVENTS
-        select USE_OF
        select MEMORY
        select ATMEL_SDRAMC
+        select PHYLIB if NETDEVICES
 menu "Atmel AT91 System-on-Chip"
@@ -65,16 +50,6 @@ choice
        prompt "Core type"
-config ARCH_AT91X40
-        bool "ARM7 AT91X40"
-        depends on !MMU
-        select CPU_ARM7TDMI
-        select ARCH_USES_GETTIMEOFFSET
-        select OLD_IRQ_AT91
-        help
-          Select this if you are using one of Atmel's AT91X40 SoC.
 config SOC_SAM_V4_V5
        bool "ARM9 AT91SAM9/AT91RM9200"
        help
@@ -122,7 +97,8 @@ endif
 if SOC_SAM_V4_V5
 config SOC_AT91RM9200
        bool "AT91RM9200"
-        select ATMEL_AIC_IRQ if !OLD_IRQ_AT91
+        select ATMEL_AIC_IRQ
+        select COMMON_CLK_AT91
        select CPU_ARM920T
        select GENERIC_CLOCKEVENTS
        select HAVE_AT91_DBGU0
@@ -198,37 +174,11 @@ config SOC_AT91SAM9N12
 # ----------------------------------------------------------
 endif # SOC_SAM_V4_V5
-if SOC_SAM_V4_V5 || ARCH_AT91X40
-source arch/arm/mach-at91/Kconfig.non_dt
-endif
-comment "Generic Board Type"
 config MACH_AT91RM9200_DT
-        bool "Atmel AT91RM9200 Evaluation Kits with device-tree support"
+        def_bool SOC_AT91RM9200
-        depends on SOC_AT91RM9200
-        select USE_OF
-        help
-          Select this if you want to experiment device-tree with
-          an Atmel RM9200 Evaluation Kit.
 config MACH_AT91SAM9_DT
-        bool "Atmel AT91SAM Evaluation Kits with device-tree support"
+        def_bool SOC_AT91SAM9
-        depends on SOC_AT91SAM9
-        select USE_OF
-        help
-          Select this if you want to experiment device-tree with
-          an Atmel Evaluation Kit.
-config MACH_SAMA5_DT
-        bool "Atmel SAMA5 Evaluation Kits with device-tree support"
-        depends on SOC_SAMA5
-        select USE_OF
-        select PHYLIB if NETDEVICES
-        help
-          Select this if you want to experiment device-tree with
-          an Atmel Evaluation Kit.
 # ----------------------------------------------------------
@@ -251,7 +201,7 @@ config AT91_TIMER_HZ
       int "Kernel HZ (jiffies per second)"
       range 32 1024
       depends on ARCH_AT91
-       default "128" if ARCH_AT91RM9200
+       default "128" if SOC_AT91RM9200
       default "100"
       help
          On AT91rm9200 chips where you're using a system clock derived
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
deleted file mode 100644
index d8e88219edb4..000000000000
--- a/arch/arm/mach-at91/Kconfig.non_dt
+++ /dev/null
@@ -1,344 +0,0 @@
-menu "Atmel Non-DT world"
-config HAVE_AT91_DATAFLASH_CARD
-        bool
-choice
-        prompt "Atmel AT91 Processor Devices for non DT boards"
-        depends on !ARCH_AT91X40
-config ARCH_AT91_NONE
-        bool "None"
-config ARCH_AT91RM9200
-        bool "AT91RM9200"
-        select SOC_AT91RM9200
-        select AT91_USE_OLD_CLK
-        select OLD_IRQ_AT91
-config ARCH_AT91SAM9260
-        bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20"
-        select SOC_AT91SAM9260
-        select AT91_USE_OLD_CLK
-        select OLD_IRQ_AT91
-config ARCH_AT91SAM9261
-        bool "AT91SAM9261 or AT91SAM9G10"
-        select SOC_AT91SAM9261
-        select AT91_USE_OLD_CLK
-        select OLD_IRQ_AT91
-config ARCH_AT91SAM9263
-        bool "AT91SAM9263"
-        select SOC_AT91SAM9263
-        select AT91_USE_OLD_CLK
-        select OLD_IRQ_AT91
-config ARCH_AT91SAM9RL
-        bool "AT91SAM9RL"
-        select SOC_AT91SAM9RL
-        select AT91_USE_OLD_CLK
-        select OLD_IRQ_AT91
-config ARCH_AT91SAM9G45
-        bool "AT91SAM9G45"
-        select SOC_AT91SAM9G45
-        select AT91_USE_OLD_CLK
-        select OLD_IRQ_AT91
-endchoice
-config ARCH_AT91SAM9G20
-        bool
-        select ARCH_AT91SAM9260
-config ARCH_AT91SAM9G10
-        bool
-        select ARCH_AT91SAM9261
-# ----------------------------------------------------------
-if ARCH_AT91RM9200
-comment "AT91RM9200 Board Type"
-config MACH_ONEARM
-        bool "Ajeco 1ARM Single Board Computer"
-        help
-          Select this if you are using Ajeco's 1ARM Single Board Computer.
-          <http://www.ajeco.fi/>
-config MACH_AT91RM9200EK
-        bool "Atmel AT91RM9200-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507>
-config MACH_CSB337
-        bool "Cogent CSB337"
-        help
-          Select this if you are using Cogent's CSB337 board.
-          <http://www.cogcomp.com/csb_csb337.htm>
-config MACH_CSB637
-        bool "Cogent CSB637"
-        help
-          Select this if you are using Cogent's CSB637 board.
-          <http://www.cogcomp.com/csb_csb637.htm>
-config MACH_CARMEVA
-        bool "Conitec ARM&EVA"
-        help
-          Select this if you are using Conitec's AT91RM9200-MCU-Module.
-          <http://www.conitec.net/english/linuxboard.php>
-config MACH_ATEB9200
-        bool "Embest ATEB9200"
-        help
-          Select this if you are using Embest's ATEB9200 board.
-          <http://www.embedinfo.com/english/product/ATEB9200.asp>
-config MACH_KB9200
-        bool "KwikByte KB920x"
-        help
-          Select this if you are using KwikByte's KB920x board.
-          <http://www.kwikbyte.com/KB9202.html>
-config MACH_PICOTUX2XX
-        bool "picotux 200"
-        help
-          Select this if you are using a picotux 200.
-          <http://www.picotux.com/>
-config MACH_KAFA
-        bool "Sperry-Sun KAFA board"
-        help
-          Select this if you are using Sperry-Sun's KAFA board.
-config MACH_ECBAT91
-        bool "emQbit ECB_AT91 SBC"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using emQbit's ECB_AT91 board.
-          <http://wiki.emqbit.com/free-ecb-at91>
-config MACH_YL9200
-        bool "ucDragon YL-9200"
-        help
-          Select this if you are using the ucDragon YL-9200 board.
-config MACH_CPUAT91
-        bool "Eukrea CPUAT91"
-        help
-          Select this if you are using the Eukrea Electromatique's
-          CPUAT91 board <http://www.eukrea.com/>.
-config MACH_ECO920
-        bool "eco920"
-        help
-          Select this if you are using the eco920 board
-endif
-# ----------------------------------------------------------
-if ARCH_AT91SAM9260
-comment "AT91SAM9260 Variants"
-comment "AT91SAM9260 / AT91SAM9XE Board Type"
-config MACH_AT91SAM9260EK
-        bool "Atmel AT91SAM9260-EK / AT91SAM9XE Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
-config MACH_CAM60
-        bool "KwikByte KB9260 (CAM60) board"
-        help
-          Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260.
-          <http://www.kwikbyte.com/KB9260.html>
-config MACH_SAM9_L9260
-        bool "Olimex SAM9-L9260 board"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260.
-          <http://www.olimex.com/dev/sam9-L9260.html>
-config MACH_AFEB9260
-        bool "Custom afeb9260 board v1"
-        help
-          Select this if you are using custom afeb9260 board based on
-          open hardware design. Select this for revision 1 of the board.
-          <svn://194.85.238.22/home/users/george/svn/arm9eb>
-          <http://groups.google.com/group/arm9fpga-evolution-board>
-config MACH_CPU9260
-        bool "Eukrea CPU9260 board"
-        help
-          Select this if you are using a Eukrea Electromatique's
-          CPU9260 Board <http://www.eukrea.com/>
-config MACH_FLEXIBITY
-        bool "Flexibity Connect board"
-        help
-          Select this if you are using Flexibity Connect board
-          <http://www.flexibity.com>
-comment "AT91SAM9G20 Board Type"
-config MACH_AT91SAM9G20EK
-        bool "Atmel AT91SAM9G20-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit
-          that embeds only one SD/MMC slot.
-config MACH_AT91SAM9G20EK_2MMC
-        depends on MACH_AT91SAM9G20EK
-        bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots"
-        help
-          Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit
-          with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and
-          onwards.
-          <http://www.atmel.com/tools/SAM9G20-EK.aspx>
-config MACH_CPU9G20
-        bool "Eukrea CPU9G20 board"
-        help
-          Select this if you are using a Eukrea Electromatique's
-          CPU9G20 Board <http://www.eukrea.com/>
-config MACH_PORTUXG20
-        bool "taskit PortuxG20"
-        help
-          Select this if you are using taskit's PortuxG20.
-          <http://www.taskit.de/en/>
-config MACH_STAMP9G20
-        bool "taskit Stamp9G20 CPU module"
-        help
-          Select this if you are using taskit's Stamp9G20 CPU module on its
-          evaluation board.
-          <http://www.taskit.de/en/>
-config MACH_PCONTROL_G20
-        bool "PControl G20 CPU module"
-        help
-          Select this if you are using taskit's Stamp9G20 CPU module on this
-          carrier board, being the decentralized unit of a building automation
-          system; featuring nvram, eth-switch, iso-rs485, display, io
-config MACH_GSIA18S
-        bool "GS_IA18_S board"
-        help
-          This enables support for the GS_IA18_S board
-          produced by GeoSIG Ltd company. This is an internet accelerograph.
-          <http://www.geosig.com>
-config MACH_SNAPPER_9260
-        bool "Bluewater Systems Snapper 9260/9G20 module"
-        help
-          Select this if you are using the Bluewater Systems Snapper 9260 or
-          Snapper 9G20 modules.
-          <http://www.bluewatersys.com/>
-endif
-# ----------------------------------------------------------
-if ARCH_AT91SAM9261
-comment "AT91SAM9261 Board Type"
-config MACH_AT91SAM9261EK
-        bool "Atmel AT91SAM9261-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
-comment "AT91SAM9G10 Board Type"
-config MACH_AT91SAM9G10EK
-        bool "Atmel AT91SAM9G10-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
-endif
-# ----------------------------------------------------------
-if ARCH_AT91SAM9263
-comment "AT91SAM9263 Board Type"
-config MACH_AT91SAM9263EK
-        bool "Atmel AT91SAM9263-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
-endif
-# ----------------------------------------------------------
-if ARCH_AT91SAM9RL
-comment "AT91SAM9RL Board Type"
-config MACH_AT91SAM9RLEK
-        bool "Atmel AT91SAM9RL-EK Evaluation Kit"
-        help
-          Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
-endif
-# ----------------------------------------------------------
-if ARCH_AT91SAM9G45
-comment "AT91SAM9G45 Board Type"
-config MACH_AT91SAM9M10G45EK
-        bool "Atmel AT91SAM9M10G45-EK Evaluation Kits"
-        help
-          Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit.
-          Those boards can be populated with any SoC of AT91SAM9G45 or AT91SAM9M10
-          families: AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
-          <http://www.atmel.com/tools/SAM9M10-G45-EK.aspx>
-endif
-# ----------------------------------------------------------
-if ARCH_AT91X40
-comment "AT91X40 Board Type"
-config MACH_AT91EB01
-        bool "Atmel AT91EB01 Evaluation Kit"
-        help
-          Select this if you are using Atmel's AT91EB01 Evaluation Kit.
-          It is also a popular target for simulators such as GDB's
-          ARM simulator (commonly known as the ARMulator) and the
-          Skyeye simulator.
-endif
-# ----------------------------------------------------------
-comment "AT91 Board Options"
-config MTD_AT91_DATAFLASH_CARD
-        bool "Enable DataFlash Card support"
-        depends on HAVE_AT91_DATAFLASH_CARD
-        help
-          Enable support for the DataFlash card.
-endmenu
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 1b9ae0257a6e..7b6424d40764 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -2,10 +2,8 @@
 # Makefile for the linux kernel.
 #
-obj-y           := gpio.o setup.o sysirq_mask.o
+obj-y           := setup.o sysirq_mask.o
-obj-$(CONFIG_OLD_IRQ_AT91)      += irq.o
-obj-$(CONFIG_OLD_CLK_AT91)      += clock.o
 obj-$(CONFIG_SOC_AT91SAM9)      += sam9_smc.o
 # CPU-specific support
@@ -20,73 +18,12 @@ obj-$(CONFIG_SOC_AT91SAM9RL)	+= at91sam9rl.o
 obj-$(CONFIG_SOC_SAMA5D3)       += sama5d3.o
 obj-$(CONFIG_SOC_SAMA5D4)       += sama5d4.o
-obj-$(CONFIG_ARCH_AT91RM9200)   += at91rm9200_devices.o
-obj-$(CONFIG_ARCH_AT91SAM9260)  += at91sam9260_devices.o
-obj-$(CONFIG_ARCH_AT91SAM9261)  += at91sam9261_devices.o
-obj-$(CONFIG_ARCH_AT91SAM9263)  += at91sam9263_devices.o
-obj-$(CONFIG_ARCH_AT91SAM9RL)   += at91sam9rl_devices.o
-obj-$(CONFIG_ARCH_AT91SAM9G45)  += at91sam9g45_devices.o
-obj-$(CONFIG_ARCH_AT91X40)      += at91x40.o at91x40_time.o
-# AT91RM9200 board-specific support
-obj-$(CONFIG_MACH_ONEARM)       += board-1arm.o
-obj-$(CONFIG_MACH_AT91RM9200EK) += board-rm9200ek.o
-obj-$(CONFIG_MACH_CSB337)       += board-csb337.o
-obj-$(CONFIG_MACH_CSB637)       += board-csb637.o
-obj-$(CONFIG_MACH_CARMEVA)      += board-carmeva.o
-obj-$(CONFIG_MACH_KB9200)       += board-kb9202.o
-obj-$(CONFIG_MACH_ATEB9200)     += board-eb9200.o
-obj-$(CONFIG_MACH_KAFA)         += board-kafa.o
-obj-$(CONFIG_MACH_PICOTUX2XX)   += board-picotux200.o
-obj-$(CONFIG_MACH_ECBAT91)      += board-ecbat91.o
-obj-$(CONFIG_MACH_YL9200)       += board-yl-9200.o
-obj-$(CONFIG_MACH_CPUAT91)      += board-cpuat91.o
-obj-$(CONFIG_MACH_ECO920)       += board-eco920.o
-# AT91SAM9260 board-specific support
-obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
-obj-$(CONFIG_MACH_CAM60)        += board-cam60.o
-obj-$(CONFIG_MACH_SAM9_L9260)   += board-sam9-l9260.o
-obj-$(CONFIG_MACH_AFEB9260)     += board-afeb-9260v1.o
-obj-$(CONFIG_MACH_CPU9260)      += board-cpu9krea.o
-obj-$(CONFIG_MACH_FLEXIBITY)    += board-flexibity.o
-# AT91SAM9261 board-specific support
-obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
-obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o
-# AT91SAM9263 board-specific support
-obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
-# AT91SAM9RL board-specific support
-obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o
-# AT91SAM9G20 board-specific support
-obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
-obj-$(CONFIG_MACH_CPU9G20)      += board-cpu9krea.o
-obj-$(CONFIG_MACH_STAMP9G20)    += board-stamp9g20.o
-obj-$(CONFIG_MACH_PORTUXG20)    += board-stamp9g20.o
-obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o
-obj-$(CONFIG_MACH_GSIA18S)      += board-gsia18s.o board-stamp9g20.o
-# AT91SAM9260/AT91SAM9G20 board-specific support
-obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
-# AT91SAM9G45 board-specific support
-obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
 # AT91SAM board with device-tree
 obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o
 obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o
 # SAMA5 board with device-tree
-obj-$(CONFIG_MACH_SAMA5_DT) += board-dt-sama5.o
+obj-$(CONFIG_SOC_SAMA5)         += board-dt-sama5.o
-# AT91X40 board-specific support
-obj-$(CONFIG_MACH_AT91EB01)     += board-eb01.o
-# Drivers
-obj-y                           += leds.o
 # Power Management
 obj-$(CONFIG_PM)                += pm.o
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index 5309f9b6aabc..29ed0fa374ca 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -3,12 +3,6 @@
 #   PARAMS_PHYS must be within 4MB of ZRELADDR
 #   INITRD_PHYS must be in RAM
-ifeq ($(CONFIG_ARCH_AT91SAM9G45),y)
-   zreladdr-y   += 0x70008000
-params_phys-y   := 0x70000100
-initrd_phys-y   := 0x70410000
-else
   zreladdr-y   += 0x20008000
 params_phys-y   := 0x20000100
 initrd_phys-y   := 0x20410000
-endif
diff --git a/arch/arm/mach-at91/at91_aic.h b/arch/arm/mach-at91/at91_aic.h
deleted file mode 100644
index eaea66197fa1..000000000000
--- a/arch/arm/mach-at91/at91_aic.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91_aic.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Advanced Interrupt Controller (AIC) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91_AIC_H
-#define AT91_AIC_H
-#ifndef __ASSEMBLY__
-extern void __iomem *at91_aic_base;
-#define at91_aic_read(field) \
-        __raw_readl(at91_aic_base + field)
-#define at91_aic_write(field, value) \
-        __raw_writel(value, at91_aic_base + field)
-#else
-.extern at91_aic_base
-#endif
-/* Number of irq lines managed by AIC */
-#define NR_AIC_IRQS     32
-#define NR_AIC5_IRQS    128
-#define AT91_AIC5_SSR           0x0                     /* Source Select Register [AIC5] */
-#define         AT91_AIC5_INTSEL_MSK    (0x7f << 0)             /* Interrupt Line Selection Mask */
-#define AT91_AIC_IRQ_MIN_PRIORITY       0
-#define AT91_AIC_IRQ_MAX_PRIORITY       7
-#define AT91_AIC_SMR(n)         ((n) * 4)               /* Source Mode Registers 0-31 */
-#define AT91_AIC5_SMR           0x4                     /* Source Mode Register [AIC5] */
-#define         AT91_AIC_PRIOR          (7 << 0)                /* Priority Level */
-#define         AT91_AIC_SRCTYPE        (3 << 5)                /* Interrupt Source Type */
-#define                 AT91_AIC_SRCTYPE_LOW            (0 << 5)
-#define                 AT91_AIC_SRCTYPE_FALLING        (1 << 5)
-#define                 AT91_AIC_SRCTYPE_HIGH           (2 << 5)
-#define                 AT91_AIC_SRCTYPE_RISING         (3 << 5)
-#define AT91_AIC_SVR(n)         (0x80 + ((n) * 4))      /* Source Vector Registers 0-31 */
-#define AT91_AIC5_SVR           0x8                     /* Source Vector Register [AIC5] */
-#define AT91_AIC_IVR            0x100                   /* Interrupt Vector Register */
-#define AT91_AIC5_IVR           0x10                    /* Interrupt Vector Register [AIC5] */
-#define AT91_AIC_FVR            0x104                   /* Fast Interrupt Vector Register */
-#define AT91_AIC5_FVR           0x14                    /* Fast Interrupt Vector Register [AIC5] */
-#define AT91_AIC_ISR            0x108                   /* Interrupt Status Register */
-#define AT91_AIC5_ISR           0x18                    /* Interrupt Status Register [AIC5] */
-#define         AT91_AIC_IRQID          (0x1f << 0)             /* Current Interrupt Identifier */
-#define AT91_AIC_IPR            0x10c                   /* Interrupt Pending Register */
-#define AT91_AIC5_IPR0          0x20                    /* Interrupt Pending Register 0 [AIC5] */
-#define AT91_AIC5_IPR1          0x24                    /* Interrupt Pending Register 1 [AIC5] */
-#define AT91_AIC5_IPR2          0x28                    /* Interrupt Pending Register 2 [AIC5] */
-#define AT91_AIC5_IPR3          0x2c                    /* Interrupt Pending Register 3 [AIC5] */
-#define AT91_AIC_IMR            0x110                   /* Interrupt Mask Register */
-#define AT91_AIC5_IMR           0x30                    /* Interrupt Mask Register [AIC5] */
-#define AT91_AIC_CISR           0x114                   /* Core Interrupt Status Register */
-#define AT91_AIC5_CISR          0x34                    /* Core Interrupt Status Register [AIC5] */
-#define         AT91_AIC_NFIQ           (1 << 0)                /* nFIQ Status */
-#define         AT91_AIC_NIRQ           (1 << 1)                /* nIRQ Status */
-#define AT91_AIC_IECR           0x120                   /* Interrupt Enable Command Register */
-#define AT91_AIC5_IECR          0x40                    /* Interrupt Enable Command Register [AIC5] */
-#define AT91_AIC_IDCR           0x124                   /* Interrupt Disable Command Register */
-#define AT91_AIC5_IDCR          0x44                    /* Interrupt Disable Command Register [AIC5] */
-#define AT91_AIC_ICCR           0x128                   /* Interrupt Clear Command Register */
-#define AT91_AIC5_ICCR          0x48                    /* Interrupt Clear Command Register [AIC5] */
-#define AT91_AIC_ISCR           0x12c                   /* Interrupt Set Command Register */
-#define AT91_AIC5_ISCR          0x4c                    /* Interrupt Set Command Register [AIC5] */
-#define AT91_AIC_EOICR          0x130                   /* End of Interrupt Command Register */
-#define AT91_AIC5_EOICR         0x38                    /* End of Interrupt Command Register [AIC5] */
-#define AT91_AIC_SPU            0x134                   /* Spurious Interrupt Vector Register */
-#define AT91_AIC5_SPU           0x3c                    /* Spurious Interrupt Vector Register [AIC5] */
-#define AT91_AIC_DCR            0x138                   /* Debug Control Register */
-#define AT91_AIC5_DCR           0x6c                    /* Debug Control Register [AIC5] */
-#define         AT91_AIC_DCR_PROT       (1 << 0)                /* Protection Mode */
-#define         AT91_AIC_DCR_GMSK       (1 << 1)                /* General Mask */
-#define AT91_AIC_FFER           0x140                   /* Fast Forcing Enable Register [SAM9 only] */
-#define AT91_AIC5_FFER          0x50                    /* Fast Forcing Enable Register [AIC5] */
-#define AT91_AIC_FFDR           0x144                   /* Fast Forcing Disable Register [SAM9 only] */
-#define AT91_AIC5_FFDR          0x54                    /* Fast Forcing Disable Register [AIC5] */
-#define AT91_AIC_FFSR           0x148                   /* Fast Forcing Status Register [SAM9 only] */
-#define AT91_AIC5_FFSR          0x58                    /* Fast Forcing Status Register [AIC5] */
-void at91_aic_handle_irq(struct pt_regs *regs);
-void at91_aic5_handle_irq(struct pt_regs *regs);
-#endif
diff --git a/arch/arm/mach-at91/at91_tc.h b/arch/arm/mach-at91/at91_tc.h
deleted file mode 100644
index 46a317fd7164..000000000000
--- a/arch/arm/mach-at91/at91_tc.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91_tc.h
- *
- * Copyright (C) SAN People
- *
- * Timer/Counter Unit (TC) registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91_TC_H
-#define AT91_TC_H
-#define AT91_TC_BCR             0xc0            /* TC Block Control Register */
-#define         AT91_TC_SYNC            (1 << 0)        /* Synchro Command */
-#define AT91_TC_BMR             0xc4            /* TC Block Mode Register */
-#define         AT91_TC_TC0XC0S         (3 << 0)        /* External Clock Signal 0 Selection */
-#define                 AT91_TC_TC0XC0S_TCLK0           (0 << 0)
-#define                 AT91_TC_TC0XC0S_NONE            (1 << 0)
-#define                 AT91_TC_TC0XC0S_TIOA1           (2 << 0)
-#define                 AT91_TC_TC0XC0S_TIOA2           (3 << 0)
-#define         AT91_TC_TC1XC1S         (3 << 2)        /* External Clock Signal 1 Selection */
-#define                 AT91_TC_TC1XC1S_TCLK1           (0 << 2)
-#define                 AT91_TC_TC1XC1S_NONE            (1 << 2)
-#define                 AT91_TC_TC1XC1S_TIOA0           (2 << 2)
-#define                 AT91_TC_TC1XC1S_TIOA2           (3 << 2)
-#define         AT91_TC_TC2XC2S         (3 << 4)        /* External Clock Signal 2 Selection */
-#define                 AT91_TC_TC2XC2S_TCLK2           (0 << 4)
-#define                 AT91_TC_TC2XC2S_NONE            (1 << 4)
-#define                 AT91_TC_TC2XC2S_TIOA0           (2 << 4)
-#define                 AT91_TC_TC2XC2S_TIOA1           (3 << 4)
-#define AT91_TC_CCR             0x00            /* Channel Control Register */
-#define         AT91_TC_CLKEN           (1 << 0)        /* Counter Clock Enable Command */
-#define         AT91_TC_CLKDIS          (1 << 1)        /* Counter CLock Disable Command */
-#define         AT91_TC_SWTRG           (1 << 2)        /* Software Trigger Command */
-#define AT91_TC_CMR             0x04            /* Channel Mode Register */
-#define         AT91_TC_TCCLKS          (7 << 0)        /* Capture/Waveform Mode: Clock Selection */
-#define                 AT91_TC_TIMER_CLOCK1            (0 << 0)
-#define                 AT91_TC_TIMER_CLOCK2            (1 << 0)
-#define                 AT91_TC_TIMER_CLOCK3            (2 << 0)
-#define                 AT91_TC_TIMER_CLOCK4            (3 << 0)
-#define                 AT91_TC_TIMER_CLOCK5            (4 << 0)
-#define                 AT91_TC_XC0                     (5 << 0)
-#define                 AT91_TC_XC1                     (6 << 0)
-#define                 AT91_TC_XC2                     (7 << 0)
-#define         AT91_TC_CLKI            (1 << 3)        /* Capture/Waveform Mode: Clock Invert */
-#define         AT91_TC_BURST           (3 << 4)        /* Capture/Waveform Mode: Burst Signal Selection */
-#define         AT91_TC_LDBSTOP         (1 << 6)        /* Capture Mode: Counter Clock Stopped with TB Loading */
-#define         AT91_TC_LDBDIS          (1 << 7)        /* Capture Mode: Counter Clock Disable with RB Loading */
-#define         AT91_TC_ETRGEDG         (3 << 8)        /* Capture Mode: External Trigger Edge Selection */
-#define         AT91_TC_ABETRG          (1 << 10)       /* Capture Mode: TIOA or TIOB External Trigger Selection */
-#define         AT91_TC_CPCTRG          (1 << 14)       /* Capture Mode: RC Compare Trigger Enable */
-#define         AT91_TC_WAVE            (1 << 15)       /* Capture/Waveform mode */
-#define         AT91_TC_LDRA            (3 << 16)       /* Capture Mode: RA Loading Selection */
-#define         AT91_TC_LDRB            (3 << 18)       /* Capture Mode: RB Loading Selection */
-#define         AT91_TC_CPCSTOP         (1 <<  6)       /* Waveform Mode: Counter Clock Stopped with RC Compare */
-#define         AT91_TC_CPCDIS          (1 <<  7)       /* Waveform Mode: Counter Clock Disable with RC Compare */
-#define         AT91_TC_EEVTEDG         (3 <<  8)       /* Waveform Mode: External Event Edge Selection */
-#define                 AT91_TC_EEVTEDG_NONE            (0 << 8)
-#define                 AT91_TC_EEVTEDG_RISING          (1 << 8)
-#define                 AT91_TC_EEVTEDG_FALLING         (2 << 8)
-#define                 AT91_TC_EEVTEDG_BOTH            (3 << 8)
-#define         AT91_TC_EEVT            (3 << 10)       /* Waveform Mode: External Event Selection */
-#define                 AT91_TC_EEVT_TIOB               (0 << 10)
-#define                 AT91_TC_EEVT_XC0                (1 << 10)
-#define                 AT91_TC_EEVT_XC1                (2 << 10)
-#define                 AT91_TC_EEVT_XC2                (3 << 10)
-#define         AT91_TC_ENETRG          (1 << 12)       /* Waveform Mode: External Event Trigger Enable */
-#define         AT91_TC_WAVESEL         (3 << 13)       /* Waveform Mode: Waveform Selection */
-#define                 AT91_TC_WAVESEL_UP              (0 << 13)
-#define                 AT91_TC_WAVESEL_UP_AUTO         (2 << 13)
-#define                 AT91_TC_WAVESEL_UPDOWN          (1 << 13)
-#define                 AT91_TC_WAVESEL_UPDOWN_AUTO     (3 << 13)
-#define         AT91_TC_ACPA            (3 << 16)       /* Waveform Mode: RA Compare Effect on TIOA */
-#define                 AT91_TC_ACPA_NONE               (0 << 16)
-#define                 AT91_TC_ACPA_SET                (1 << 16)
-#define                 AT91_TC_ACPA_CLEAR              (2 << 16)
-#define                 AT91_TC_ACPA_TOGGLE             (3 << 16)
-#define         AT91_TC_ACPC            (3 << 18)       /* Waveform Mode: RC Compre Effect on TIOA */
-#define                 AT91_TC_ACPC_NONE               (0 << 18)
-#define                 AT91_TC_ACPC_SET                (1 << 18)
-#define                 AT91_TC_ACPC_CLEAR              (2 << 18)
-#define                 AT91_TC_ACPC_TOGGLE             (3 << 18)
-#define         AT91_TC_AEEVT           (3 << 20)       /* Waveform Mode: External Event Effect on TIOA */
-#define                 AT91_TC_AEEVT_NONE              (0 << 20)
-#define                 AT91_TC_AEEVT_SET               (1 << 20)
-#define                 AT91_TC_AEEVT_CLEAR             (2 << 20)
-#define                 AT91_TC_AEEVT_TOGGLE            (3 << 20)
-#define         AT91_TC_ASWTRG          (3 << 22)       /* Waveform Mode: Software Trigger Effect on TIOA */
-#define                 AT91_TC_ASWTRG_NONE             (0 << 22)
-#define                 AT91_TC_ASWTRG_SET              (1 << 22)
-#define                 AT91_TC_ASWTRG_CLEAR            (2 << 22)
-#define                 AT91_TC_ASWTRG_TOGGLE           (3 << 22)
-#define         AT91_TC_BCPB            (3 << 24)       /* Waveform Mode: RB Compare Effect on TIOB */
-#define                 AT91_TC_BCPB_NONE               (0 << 24)
-#define                 AT91_TC_BCPB_SET                (1 << 24)
-#define                 AT91_TC_BCPB_CLEAR              (2 << 24)
-#define                 AT91_TC_BCPB_TOGGLE             (3 << 24)
-#define         AT91_TC_BCPC            (3 << 26)       /* Waveform Mode: RC Compare Effect on TIOB */
-#define                 AT91_TC_BCPC_NONE               (0 << 26)
-#define                 AT91_TC_BCPC_SET                (1 << 26)
-#define                 AT91_TC_BCPC_CLEAR              (2 << 26)
-#define                 AT91_TC_BCPC_TOGGLE             (3 << 26)
-#define         AT91_TC_BEEVT           (3 << 28)       /* Waveform Mode: External Event Effect on TIOB */
-#define                 AT91_TC_BEEVT_NONE              (0 << 28)
-#define                 AT91_TC_BEEVT_SET               (1 << 28)
-#define                 AT91_TC_BEEVT_CLEAR             (2 << 28)
-#define                 AT91_TC_BEEVT_TOGGLE            (3 << 28)
-#define         AT91_TC_BSWTRG          (3 << 30)       /* Waveform Mode: Software Trigger Effect on TIOB */
-#define                 AT91_TC_BSWTRG_NONE             (0 << 30)
-#define                 AT91_TC_BSWTRG_SET              (1 << 30)
-#define                 AT91_TC_BSWTRG_CLEAR            (2 << 30)
-#define                 AT91_TC_BSWTRG_TOGGLE           (3 << 30)
-#define AT91_TC_CV              0x10            /* Counter Value */
-#define AT91_TC_RA              0x14            /* Register A */
-#define AT91_TC_RB              0x18            /* Register B */
-#define AT91_TC_RC              0x1c            /* Register C */
-#define AT91_TC_SR              0x20            /* Status Register */
-#define         AT91_TC_COVFS           (1 <<  0)       /* Counter Overflow Status */
-#define         AT91_TC_LOVRS           (1 <<  1)       /* Load Overrun Status */
-#define         AT91_TC_CPAS            (1 <<  2)       /* RA Compare Status */
-#define         AT91_TC_CPBS            (1 <<  3)       /* RB Compare Status */
-#define         AT91_TC_CPCS            (1 <<  4)       /* RC Compare Status */
-#define         AT91_TC_LDRAS           (1 <<  5)       /* RA Loading Status */
-#define         AT91_TC_LDRBS           (1 <<  6)       /* RB Loading Status */
-#define         AT91_TC_ETRGS           (1 <<  7)       /* External Trigger Status */
-#define         AT91_TC_CLKSTA          (1 << 16)       /* Clock Enabling Status */
-#define         AT91_TC_MTIOA           (1 << 17)       /* TIOA Mirror */
-#define         AT91_TC_MTIOB           (1 << 18)       /* TIOB Mirror */
-#define AT91_TC_IER             0x24            /* Interrupt Enable Register */
-#define AT91_TC_IDR             0x28            /* Interrupt Disable Register */
-#define AT91_TC_IMR             0x2c            /* Interrupt Mask Register */
-#endif
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 038702ee8bc6..b52916947535 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -11,296 +11,15 @@
 */
 #include <linux/module.h>
-#include <linux/reboot.h>
 #include <linux/clk/at91_pmc.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
-#include <mach/at91rm9200.h>
 #include <mach/at91_st.h>
-#include <mach/cpu.h>
 #include <mach/hardware.h>
-#include "at91_aic.h"
 #include "soc.h"
 #include "generic.h"
-#include "sam9_smc.h"
-#include "pm.h"
-#if defined(CONFIG_OLD_CLK_AT91)
-#include "clock.h"
-/* --------------------------------------------------------------------
- *  Clocks
- * -------------------------------------------------------------------- */
-/*
- * The peripheral clocks.
- */
-static struct clk udc_clk = {
-        .name           = "udc_clk",
-        .pmc_mask       = 1 << AT91RM9200_ID_UDP,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ohci_clk = {
-        .name           = "ohci_clk",
-        .pmc_mask       = 1 << AT91RM9200_ID_UHP,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ether_clk = {
-        .name           = "ether_clk",
-        .pmc_mask       = 1 << AT91RM9200_ID_EMAC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc_clk = {
-        .name           = "mci_clk",
-        .pmc_mask       = 1 << AT91RM9200_ID_MCI,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi_clk = {
-        .name           = "twi_clk",
-        .pmc_mask       = 1 << AT91RM9200_ID_TWI,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
-        .name           = "usart0_clk",
-        .pmc_mask       = 1 << AT91RM9200_ID_US0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
-        .name           = "usart1_clk",
-        .pmc_mask       = 1 << AT91RM9200_ID_US1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
-        .name           = "usart2_clk",
-        .pmc_mask       = 1 << AT91RM9200_ID_US2,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart3_clk = {
-        .name           = "usart3_clk",
-        .pmc_mask       = 1 << AT91RM9200_ID_US3,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi_clk = {
-        .name           = "spi_clk",
-        .pmc_mask       = 1 << AT91RM9200_ID_SPI,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioA_clk = {
-        .name           = "pioA_clk",
-        .pmc_mask       = 1 << AT91RM9200_ID_PIOA,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
-        .name           = "pioB_clk",
-        .pmc_mask       = 1 << AT91RM9200_ID_PIOB,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
-        .name           = "pioC_clk",
-        .pmc_mask       = 1 << AT91RM9200_ID_PIOC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioD_clk = {
-        .name           = "pioD_clk",
-        .pmc_mask       = 1 << AT91RM9200_ID_PIOD,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
-        .name           = "ssc0_clk",
-        .pmc_mask       = 1 << AT91RM9200_ID_SSC0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
-        .name           = "ssc1_clk",
-        .pmc_mask       = 1 << AT91RM9200_ID_SSC1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc2_clk = {
-        .name           = "ssc2_clk",
-        .pmc_mask       = 1 << AT91RM9200_ID_SSC2,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc0_clk = {
-        .name           = "tc0_clk",
-        .pmc_mask       = 1 << AT91RM9200_ID_TC0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc1_clk = {
-        .name           = "tc1_clk",
-        .pmc_mask       = 1 << AT91RM9200_ID_TC1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc2_clk = {
-        .name           = "tc2_clk",
-        .pmc_mask       = 1 << AT91RM9200_ID_TC2,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc3_clk = {
-        .name           = "tc3_clk",
-        .pmc_mask       = 1 << AT91RM9200_ID_TC3,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc4_clk = {
-        .name           = "tc4_clk",
-        .pmc_mask       = 1 << AT91RM9200_ID_TC4,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc5_clk = {
-        .name           = "tc5_clk",
-        .pmc_mask       = 1 << AT91RM9200_ID_TC5,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk *periph_clocks[] __initdata = {
-        &pioA_clk,
-        &pioB_clk,
-        &pioC_clk,
-        &pioD_clk,
-        &usart0_clk,
-        &usart1_clk,
-        &usart2_clk,
-        &usart3_clk,
-        &mmc_clk,
-        &udc_clk,
-        &twi_clk,
-        &spi_clk,
-        &ssc0_clk,
-        &ssc1_clk,
-        &ssc2_clk,
-        &tc0_clk,
-        &tc1_clk,
-        &tc2_clk,
-        &tc3_clk,
-        &tc4_clk,
-        &tc5_clk,
-        &ohci_clk,
-        &ether_clk,
-        // irq0 .. irq6
-};
-static struct clk_lookup periph_clocks_lookups[] = {
-        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
-        CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
-        CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
-        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
-        CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
-        CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
-        CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
-        CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
-        CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
-        CLKDEV_CON_DEV_ID("pclk", "fffd0000.ssc", &ssc0_clk),
-        CLKDEV_CON_DEV_ID("pclk", "fffd4000.ssc", &ssc1_clk),
-        CLKDEV_CON_DEV_ID("pclk", "fffd8000.ssc", &ssc2_clk),
-        CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200.0", &twi_clk),
-        /* fake hclk clock */
-        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
-        CLKDEV_CON_ID("pioA", &pioA_clk),
-        CLKDEV_CON_ID("pioB", &pioB_clk),
-        CLKDEV_CON_ID("pioC", &pioC_clk),
-        CLKDEV_CON_ID("pioD", &pioD_clk),
-        /* usart lookup table for DT entries */
-        CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
-        CLKDEV_CON_DEV_ID("usart", "fffc0000.serial", &usart0_clk),
-        CLKDEV_CON_DEV_ID("usart", "fffc4000.serial", &usart1_clk),
-        CLKDEV_CON_DEV_ID("usart", "fffc8000.serial", &usart2_clk),
-        CLKDEV_CON_DEV_ID("usart", "fffcc000.serial", &usart3_clk),
-        /* tc lookup table for DT entries */
-        CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
-        CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
-        CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
-        CLKDEV_CON_DEV_ID("t0_clk", "fffa4000.timer", &tc3_clk),
-        CLKDEV_CON_DEV_ID("t1_clk", "fffa4000.timer", &tc4_clk),
-        CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "fffb4000.mmc", &mmc_clk),
-        CLKDEV_CON_DEV_ID("emac_clk", "fffbc000.ethernet", &ether_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffb8000.i2c", &twi_clk),
-        CLKDEV_CON_DEV_ID("hclk", "300000.ohci", &ohci_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
-};
-static struct clk_lookup usart_clocks_lookups[] = {
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
-};
-/*
- * The four programmable clocks.
- * You must configure pin multiplexing to bring these signals out.
- */
-static struct clk pck0 = {
-        .name           = "pck0",
-        .pmc_mask       = AT91_PMC_PCK0,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 0,
-};
-static struct clk pck1 = {
-        .name           = "pck1",
-        .pmc_mask       = AT91_PMC_PCK1,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 1,
-};
-static struct clk pck2 = {
-        .name           = "pck2",
-        .pmc_mask       = AT91_PMC_PCK2,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 2,
-};
-static struct clk pck3 = {
-        .name           = "pck3",
-        .pmc_mask       = AT91_PMC_PCK3,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 3,
-};
-static void __init at91rm9200_register_clocks(void)
-{
-        int i;
-        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
-                clk_register(periph_clocks[i]);
-        clkdev_add_table(periph_clocks_lookups,
-                         ARRAY_SIZE(periph_clocks_lookups));
-        clkdev_add_table(usart_clocks_lookups,
-                         ARRAY_SIZE(usart_clocks_lookups));
-        clk_register(&pck0);
-        clk_register(&pck1);
-        clk_register(&pck2);
-        clk_register(&pck3);
-}
-#else
-#define at91rm9200_register_clocks NULL
-#endif
-/* --------------------------------------------------------------------
- *  GPIO
- * -------------------------------------------------------------------- */
-static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
-        {
-                .id             = AT91RM9200_ID_PIOA,
-                .regbase        = AT91RM9200_BASE_PIOA,
-        }, {
-                .id             = AT91RM9200_ID_PIOB,
-                .regbase        = AT91RM9200_BASE_PIOB,
-        }, {
-                .id             = AT91RM9200_ID_PIOC,
-                .regbase        = AT91RM9200_BASE_PIOC,
-        }, {
-                .id             = AT91RM9200_ID_PIOD,
-                .regbase        = AT91RM9200_BASE_PIOD,
-        }
-};
 static void at91rm9200_idle(void)
 {
@@ -329,74 +48,14 @@ static void __init at91rm9200_map_io(void)
        at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE);
 }
-static void __init at91rm9200_ioremap_registers(void)
-{
-        at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
-        at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
-        at91_pm_set_standby(at91rm9200_standby);
-}
 static void __init at91rm9200_initialize(void)
 {
        arm_pm_idle = at91rm9200_idle;
        arm_pm_restart = at91rm9200_restart;
-        /* Initialize GPIO subsystem */
-        at91_gpio_init(at91rm9200_gpio,
-                cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP);
 }
-/* --------------------------------------------------------------------
- *  Interrupt initialization
- * -------------------------------------------------------------------- */
-/*
- * The default interrupt priority levels (0 = lowest, 7 = highest).
- */
-static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
-        7,      /* Advanced Interrupt Controller (FIQ) */
-        7,      /* System Peripherals */
-        1,      /* Parallel IO Controller A */
-        1,      /* Parallel IO Controller B */
-        1,      /* Parallel IO Controller C */
-        1,      /* Parallel IO Controller D */
-        5,      /* USART 0 */
-        5,      /* USART 1 */
-        5,      /* USART 2 */
-        5,      /* USART 3 */
-        0,      /* Multimedia Card Interface */
-        2,      /* USB Device Port */
-        6,      /* Two-Wire Interface */
-        5,      /* Serial Peripheral Interface */
-        4,      /* Serial Synchronous Controller 0 */
-        4,      /* Serial Synchronous Controller 1 */
-        4,      /* Serial Synchronous Controller 2 */
-        0,      /* Timer Counter 0 */
-        0,      /* Timer Counter 1 */
-        0,      /* Timer Counter 2 */
-        0,      /* Timer Counter 3 */
-        0,      /* Timer Counter 4 */
-        0,      /* Timer Counter 5 */
-        2,      /* USB Host port */
-        3,      /* Ethernet MAC */
-        0,      /* Advanced Interrupt Controller (IRQ0) */
-        0,      /* Advanced Interrupt Controller (IRQ1) */
-        0,      /* Advanced Interrupt Controller (IRQ2) */
-        0,      /* Advanced Interrupt Controller (IRQ3) */
-        0,      /* Advanced Interrupt Controller (IRQ4) */
-        0,      /* Advanced Interrupt Controller (IRQ5) */
-        0       /* Advanced Interrupt Controller (IRQ6) */
-};
 AT91_SOC_START(at91rm9200)
        .map_io = at91rm9200_map_io,
-        .default_irq_priority = at91rm9200_default_irq_priority,
-        .extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
-                    | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
-                    | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
-                    | (1 << AT91RM9200_ID_IRQ6),
-        .ioremap_registers = at91rm9200_ioremap_registers,
-        .register_clocks = at91rm9200_register_clocks,
        .init = at91rm9200_initialize,
 AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
deleted file mode 100644
index 74f1eaf97801..000000000000
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ /dev/null
@@ -1,1212 +0,0 @@
-/*
- * arch/arm/mach-at91/at91rm9200_devices.c
- *
- *  Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
- *  Copyright (C) 2005 David Brownell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/platform_device.h>
-#include <linux/i2c-gpio.h>
-#include <mach/at91rm9200.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
-#include <mach/hardware.h>
-#include "board.h"
-#include "generic.h"
-#include "gpio.h"
-/* --------------------------------------------------------------------
- *  USB Host
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static u64 ohci_dmamask = DMA_BIT_MASK(32);
-static struct at91_usbh_data usbh_data;
-static struct resource usbh_resources[] = {
-        [0] = {
-                .start  = AT91RM9200_UHP_BASE,
-                .end    = AT91RM9200_UHP_BASE + SZ_1M - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_UHP,
-                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_UHP,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91rm9200_usbh_device = {
-        .name           = "at91_ohci",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &ohci_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &usbh_data,
-        },
-        .resource       = usbh_resources,
-        .num_resources  = ARRAY_SIZE(usbh_resources),
-};
-void __init at91_add_device_usbh(struct at91_usbh_data *data)
-{
-        int i;
-        if (!data)
-                return;
-        /* Enable overcurrent notification */
-        for (i = 0; i < data->ports; i++) {
-                if (gpio_is_valid(data->overcurrent_pin[i]))
-                        at91_set_gpio_input(data->overcurrent_pin[i], 1);
-        }
-        usbh_data = *data;
-        platform_device_register(&at91rm9200_usbh_device);
-}
-#else
-void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  USB Device (Gadget)
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
-static struct at91_udc_data udc_data;
-static struct resource udc_resources[] = {
-        [0] = {
-                .start  = AT91RM9200_BASE_UDP,
-                .end    = AT91RM9200_BASE_UDP + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_UDP,
-                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_UDP,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91rm9200_udc_device = {
-        .name           = "at91_udc",
-        .id             = -1,
-        .dev            = {
-                                .platform_data          = &udc_data,
-        },
-        .resource       = udc_resources,
-        .num_resources  = ARRAY_SIZE(udc_resources),
-};
-void __init at91_add_device_udc(struct at91_udc_data *data)
-{
-        if (!data)
-                return;
-        if (gpio_is_valid(data->vbus_pin)) {
-                at91_set_gpio_input(data->vbus_pin, 0);
-                at91_set_deglitch(data->vbus_pin, 1);
-        }
-        if (gpio_is_valid(data->pullup_pin))
-                at91_set_gpio_output(data->pullup_pin, 0);
-        udc_data = *data;
-        platform_device_register(&at91rm9200_udc_device);
-}
-#else
-void __init at91_add_device_udc(struct at91_udc_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  Ethernet
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE)
-static u64 eth_dmamask = DMA_BIT_MASK(32);
-static struct macb_platform_data eth_data;
-static struct resource eth_resources[] = {
-        [0] = {
-                .start  = AT91RM9200_BASE_EMAC,
-                .end    = AT91RM9200_BASE_EMAC + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_EMAC,
-                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_EMAC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91rm9200_eth_device = {
-        .name           = "at91_ether",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &eth_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &eth_data,
-        },
-        .resource       = eth_resources,
-        .num_resources  = ARRAY_SIZE(eth_resources),
-};
-void __init at91_add_device_eth(struct macb_platform_data *data)
-{
-        if (!data)
-                return;
-        if (gpio_is_valid(data->phy_irq_pin)) {
-                at91_set_gpio_input(data->phy_irq_pin, 0);
-                at91_set_deglitch(data->phy_irq_pin, 1);
-        }
-        /* Pins used for MII and RMII */
-        at91_set_A_periph(AT91_PIN_PA16, 0);    /* EMDIO */
-        at91_set_A_periph(AT91_PIN_PA15, 0);    /* EMDC */
-        at91_set_A_periph(AT91_PIN_PA14, 0);    /* ERXER */
-        at91_set_A_periph(AT91_PIN_PA13, 0);    /* ERX1 */
-        at91_set_A_periph(AT91_PIN_PA12, 0);    /* ERX0 */
-        at91_set_A_periph(AT91_PIN_PA11, 0);    /* ECRS_ECRSDV */
-        at91_set_A_periph(AT91_PIN_PA10, 0);    /* ETX1 */
-        at91_set_A_periph(AT91_PIN_PA9, 0);     /* ETX0 */
-        at91_set_A_periph(AT91_PIN_PA8, 0);     /* ETXEN */
-        at91_set_A_periph(AT91_PIN_PA7, 0);     /* ETXCK_EREFCK */
-        if (!data->is_rmii) {
-                at91_set_B_periph(AT91_PIN_PB19, 0);    /* ERXCK */
-                at91_set_B_periph(AT91_PIN_PB18, 0);    /* ECOL */
-                at91_set_B_periph(AT91_PIN_PB17, 0);    /* ERXDV */
-                at91_set_B_periph(AT91_PIN_PB16, 0);    /* ERX3 */
-                at91_set_B_periph(AT91_PIN_PB15, 0);    /* ERX2 */
-                at91_set_B_periph(AT91_PIN_PB14, 0);    /* ETXER */
-                at91_set_B_periph(AT91_PIN_PB13, 0);    /* ETX3 */
-                at91_set_B_periph(AT91_PIN_PB12, 0);    /* ETX2 */
-        }
-        eth_data = *data;
-        platform_device_register(&at91rm9200_eth_device);
-}
-#else
-void __init at91_add_device_eth(struct macb_platform_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  Compact Flash / PCMCIA
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
-static struct at91_cf_data cf_data;
-#define CF_BASE         AT91_CHIPSELECT_4
-static struct resource cf_resources[] = {
-        [0] = {
-                .start  = CF_BASE,
-                /* ties up CS4, CS5 and CS6 */
-                .end    = CF_BASE + (0x30000000 - 1),
-                .flags  = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
-        },
-};
-static struct platform_device at91rm9200_cf_device = {
-        .name           = "at91_cf",
-        .id             = -1,
-        .dev            = {
-                                .platform_data          = &cf_data,
-        },
-        .resource       = cf_resources,
-        .num_resources  = ARRAY_SIZE(cf_resources),
-};
-void __init at91_add_device_cf(struct at91_cf_data *data)
-{
-        unsigned int csa;
-        if (!data)
-                return;
-        data->chipselect = 4;           /* can only use EBI ChipSelect 4 */
-        /* CF takes over CS4, CS5, CS6 */
-        csa = at91_ramc_read(0, AT91_EBI_CSA);
-        at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
-        /*
-         * Static memory controller timing adjustments.
-         * REVISIT:  these timings are in terms of MCK cycles, so
-         * when MCK changes (cpufreq etc) so must these values...
-         */
-        at91_ramc_write(0, AT91_SMC_CSR(4),
-                                  AT91_SMC_ACSS_STD
-                                | AT91_SMC_DBW_16
-                                | AT91_SMC_BAT
-                                | AT91_SMC_WSEN
-                                | AT91_SMC_NWS_(32)     /* wait states */
-                                | AT91_SMC_RWSETUP_(6)  /* setup time */
-                                | AT91_SMC_RWHOLD_(4)   /* hold time */
-        );
-        /* input/irq */
-        if (gpio_is_valid(data->irq_pin)) {
-                at91_set_gpio_input(data->irq_pin, 1);
-                at91_set_deglitch(data->irq_pin, 1);
-        }
-        at91_set_gpio_input(data->det_pin, 1);
-        at91_set_deglitch(data->det_pin, 1);
-        /* outputs, initially off */
-        if (gpio_is_valid(data->vcc_pin))
-                at91_set_gpio_output(data->vcc_pin, 0);
-        at91_set_gpio_output(data->rst_pin, 0);
-        /* force poweron defaults for these pins ... */
-        at91_set_A_periph(AT91_PIN_PC9, 0);     /* A25/CFRNW */
-        at91_set_A_periph(AT91_PIN_PC10, 0);    /* NCS4/CFCS */
-        at91_set_A_periph(AT91_PIN_PC11, 0);    /* NCS5/CFCE1 */
-        at91_set_A_periph(AT91_PIN_PC12, 0);    /* NCS6/CFCE2 */
-        /* nWAIT is _not_ a default setting */
-        at91_set_A_periph(AT91_PIN_PC6, 1);     /* nWAIT */
-        cf_data = *data;
-        platform_device_register(&at91rm9200_cf_device);
-}
-#else
-void __init at91_add_device_cf(struct at91_cf_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  MMC / SD
- * -------------------------------------------------------------------- */
-#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
-static u64 mmc_dmamask = DMA_BIT_MASK(32);
-static struct mci_platform_data mmc_data;
-static struct resource mmc_resources[] = {
-        [0] = {
-                .start  = AT91RM9200_BASE_MCI,
-                .end    = AT91RM9200_BASE_MCI + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_MCI,
-                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_MCI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91rm9200_mmc_device = {
-        .name           = "atmel_mci",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &mmc_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &mmc_data,
-        },
-        .resource       = mmc_resources,
-        .num_resources  = ARRAY_SIZE(mmc_resources),
-};
-void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
-{
-        unsigned int i;
-        unsigned int slot_count = 0;
-        if (!data)
-                return;
-        for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
-                if (!data->slot[i].bus_width)
-                        continue;
-                /* input/irq */
-                if (gpio_is_valid(data->slot[i].detect_pin)) {
-                        at91_set_gpio_input(data->slot[i].detect_pin, 1);
-                        at91_set_deglitch(data->slot[i].detect_pin, 1);
-                }
-                if (gpio_is_valid(data->slot[i].wp_pin))
-                        at91_set_gpio_input(data->slot[i].wp_pin, 1);
-                switch (i) {
-                case 0:                                 /* slot A */
-                        /* CMD */
-                        at91_set_A_periph(AT91_PIN_PA28, 1);
-                        /* DAT0, maybe DAT1..DAT3 */
-                        at91_set_A_periph(AT91_PIN_PA29, 1);
-                        if (data->slot[i].bus_width == 4) {
-                                at91_set_B_periph(AT91_PIN_PB3, 1);
-                                at91_set_B_periph(AT91_PIN_PB4, 1);
-                                at91_set_B_periph(AT91_PIN_PB5, 1);
-                        }
-                        slot_count++;
-                        break;
-                case 1:                                 /* slot B */
-                        /* CMD */
-                        at91_set_B_periph(AT91_PIN_PA8, 1);
-                        /* DAT0, maybe DAT1..DAT3 */
-                        at91_set_B_periph(AT91_PIN_PA9, 1);
-                        if (data->slot[i].bus_width == 4) {
-                                at91_set_B_periph(AT91_PIN_PA10, 1);
-                                at91_set_B_periph(AT91_PIN_PA11, 1);
-                                at91_set_B_periph(AT91_PIN_PA12, 1);
-                        }
-                        slot_count++;
-                        break;
-                default:
-                        printk(KERN_ERR
-                               "AT91: SD/MMC slot %d not available\n", i);
-                        break;
-                }
-                if (slot_count) {
-                        /* CLK */
-                        at91_set_A_periph(AT91_PIN_PA27, 0);
-                        mmc_data = *data;
-                        platform_device_register(&at91rm9200_mmc_device);
-                }
-        }
-}
-#else
-void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  NAND / SmartMedia
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
-static struct atmel_nand_data nand_data;
-#define NAND_BASE       AT91_CHIPSELECT_3
-static struct resource nand_resources[] = {
-        {
-                .start  = NAND_BASE,
-                .end    = NAND_BASE + SZ_256M - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct platform_device at91rm9200_nand_device = {
-        .name           = "atmel_nand",
-        .id             = -1,
-        .dev            = {
-                                .platform_data  = &nand_data,
-        },
-        .resource       = nand_resources,
-        .num_resources  = ARRAY_SIZE(nand_resources),
-};
-void __init at91_add_device_nand(struct atmel_nand_data *data)
-{
-        unsigned int csa;
-        if (!data)
-                return;
-        /* enable the address range of CS3 */
-        csa = at91_ramc_read(0, AT91_EBI_CSA);
-        at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
-        /* set the bus interface characteristics */
-        at91_ramc_write(0, AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
-                | AT91_SMC_NWS_(5)
-                | AT91_SMC_TDF_(1)
-                | AT91_SMC_RWSETUP_(0)  /* tDS Data Set up Time 30 - ns */
-                | AT91_SMC_RWHOLD_(1)   /* tDH Data Hold Time 20 - ns */
-        );
-        /* enable pin */
-        if (gpio_is_valid(data->enable_pin))
-                at91_set_gpio_output(data->enable_pin, 1);
-        /* ready/busy pin */
-        if (gpio_is_valid(data->rdy_pin))
-                at91_set_gpio_input(data->rdy_pin, 1);
-        /* card detect pin */
-        if (gpio_is_valid(data->det_pin))
-                at91_set_gpio_input(data->det_pin, 1);
-        at91_set_A_periph(AT91_PIN_PC1, 0);             /* SMOE */
-        at91_set_A_periph(AT91_PIN_PC3, 0);             /* SMWE */
-        nand_data = *data;
-        platform_device_register(&at91rm9200_nand_device);
-}
-#else
-void __init at91_add_device_nand(struct atmel_nand_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  TWI (i2c)
- * -------------------------------------------------------------------- */
-/*
- * Prefer the GPIO code since the TWI controller isn't robust
- * (gets overruns and underruns under load) and can only issue
- * repeated STARTs in one scenario (the driver doesn't yet handle them).
- */
-#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
-static struct i2c_gpio_platform_data pdata = {
-        .sda_pin                = AT91_PIN_PA25,
-        .sda_is_open_drain      = 1,
-        .scl_pin                = AT91_PIN_PA26,
-        .scl_is_open_drain      = 1,
-        .udelay                 = 2,            /* ~100 kHz */
-};
-static struct platform_device at91rm9200_twi_device = {
-        .name                   = "i2c-gpio",
-        .id                     = 0,
-        .dev.platform_data      = &pdata,
-};
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
-{
-        at91_set_GPIO_periph(AT91_PIN_PA25, 1);         /* TWD (SDA) */
-        at91_set_multi_drive(AT91_PIN_PA25, 1);
-        at91_set_GPIO_periph(AT91_PIN_PA26, 1);         /* TWCK (SCL) */
-        at91_set_multi_drive(AT91_PIN_PA26, 1);
-        i2c_register_board_info(0, devices, nr_devices);
-        platform_device_register(&at91rm9200_twi_device);
-}
-#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
-static struct resource twi_resources[] = {
-        [0] = {
-                .start  = AT91RM9200_BASE_TWI,
-                .end    = AT91RM9200_BASE_TWI + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TWI,
-                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TWI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91rm9200_twi_device = {
-        .name           = "i2c-at91rm9200",
-        .id             = 0,
-        .resource       = twi_resources,
-        .num_resources  = ARRAY_SIZE(twi_resources),
-};
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
-{
-        /* pins used for TWI interface */
-        at91_set_A_periph(AT91_PIN_PA25, 0);            /* TWD */
-        at91_set_multi_drive(AT91_PIN_PA25, 1);
-        at91_set_A_periph(AT91_PIN_PA26, 0);            /* TWCK */
-        at91_set_multi_drive(AT91_PIN_PA26, 1);
-        i2c_register_board_info(0, devices, nr_devices);
-        platform_device_register(&at91rm9200_twi_device);
-}
-#else
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
-#endif
-/* --------------------------------------------------------------------
- *  SPI
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
-static u64 spi_dmamask = DMA_BIT_MASK(32);
-static struct resource spi_resources[] = {
-        [0] = {
-                .start  = AT91RM9200_BASE_SPI,
-                .end    = AT91RM9200_BASE_SPI + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_SPI,
-                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_SPI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91rm9200_spi_device = {
-        .name           = "atmel_spi",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &spi_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = spi_resources,
-        .num_resources  = ARRAY_SIZE(spi_resources),
-};
-static const unsigned spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
-void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
-{
-        int i;
-        unsigned long cs_pin;
-        at91_set_A_periph(AT91_PIN_PA0, 0);     /* MISO */
-        at91_set_A_periph(AT91_PIN_PA1, 0);     /* MOSI */
-        at91_set_A_periph(AT91_PIN_PA2, 0);     /* SPCK */
-        /* Enable SPI chip-selects */
-        for (i = 0; i < nr_devices; i++) {
-                if (devices[i].controller_data)
-                        cs_pin = (unsigned long) devices[i].controller_data;
-                else
-                        cs_pin = spi_standard_cs[devices[i].chip_select];
-                if (devices[i].chip_select == 0)        /* for CS0 errata */
-                        at91_set_A_periph(cs_pin, 0);
-                else
-                        at91_set_gpio_output(cs_pin, 1);
-                /* pass chip-select pin to driver */
-                devices[i].controller_data = (void *) cs_pin;
-        }
-        spi_register_board_info(devices, nr_devices);
-        platform_device_register(&at91rm9200_spi_device);
-}
-#else
-void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
-#endif
-/* --------------------------------------------------------------------
- *  Timer/Counter blocks
- * -------------------------------------------------------------------- */
-#ifdef CONFIG_ATMEL_TCLIB
-static struct resource tcb0_resources[] = {
-        [0] = {
-                .start  = AT91RM9200_BASE_TCB0,
-                .end    = AT91RM9200_BASE_TCB0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC0,
-                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC0,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC1,
-                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC1,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC2,
-                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91rm9200_tcb0_device = {
-        .name           = "atmel_tcb",
-        .id             = 0,
-        .resource       = tcb0_resources,
-        .num_resources  = ARRAY_SIZE(tcb0_resources),
-};
-static struct resource tcb1_resources[] = {
-        [0] = {
-                .start  = AT91RM9200_BASE_TCB1,
-                .end    = AT91RM9200_BASE_TCB1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC3,
-                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC3,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC4,
-                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC4,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC5,
-                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC5,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91rm9200_tcb1_device = {
-        .name           = "atmel_tcb",
-        .id             = 1,
-        .resource       = tcb1_resources,
-        .num_resources  = ARRAY_SIZE(tcb1_resources),
-};
-static void __init at91_add_device_tc(void)
-{
-        platform_device_register(&at91rm9200_tcb0_device);
-        platform_device_register(&at91rm9200_tcb1_device);
-}
-#else
-static void __init at91_add_device_tc(void) { }
-#endif
-/* --------------------------------------------------------------------
- *  RTC
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
-static struct resource rtc_resources[] = {
-        [0] = {
-                .start  = AT91RM9200_BASE_RTC,
-                .end    = AT91RM9200_BASE_RTC + SZ_256 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
-                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91rm9200_rtc_device = {
-        .name           = "at91_rtc",
-        .id             = -1,
-        .resource       = rtc_resources,
-        .num_resources  = ARRAY_SIZE(rtc_resources),
-};
-static void __init at91_add_device_rtc(void)
-{
-        platform_device_register(&at91rm9200_rtc_device);
-}
-#else
-static void __init at91_add_device_rtc(void) {}
-#endif
-/* --------------------------------------------------------------------
- *  Watchdog
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_AT91RM9200_WATCHDOG) || defined(CONFIG_AT91RM9200_WATCHDOG_MODULE)
-static struct platform_device at91rm9200_wdt_device = {
-        .name           = "at91_wdt",
-        .id             = -1,
-        .num_resources  = 0,
-};
-static void __init at91_add_device_watchdog(void)
-{
-        platform_device_register(&at91rm9200_wdt_device);
-}
-#else
-static void __init at91_add_device_watchdog(void) {}
-#endif
-/* --------------------------------------------------------------------
- *  SSC -- Synchronous Serial Controller
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
-static u64 ssc0_dmamask = DMA_BIT_MASK(32);
-static struct resource ssc0_resources[] = {
-        [0] = {
-                .start  = AT91RM9200_BASE_SSC0,
-                .end    = AT91RM9200_BASE_SSC0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_SSC0,
-                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_SSC0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91rm9200_ssc0_device = {
-        .name   = "at91rm9200_ssc",
-        .id     = 0,
-        .dev    = {
-                .dma_mask               = &ssc0_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = ssc0_resources,
-        .num_resources  = ARRAY_SIZE(ssc0_resources),
-};
-static inline void configure_ssc0_pins(unsigned pins)
-{
-        if (pins & ATMEL_SSC_TF)
-                at91_set_A_periph(AT91_PIN_PB0, 1);
-        if (pins & ATMEL_SSC_TK)
-                at91_set_A_periph(AT91_PIN_PB1, 1);
-        if (pins & ATMEL_SSC_TD)
-                at91_set_A_periph(AT91_PIN_PB2, 1);
-        if (pins & ATMEL_SSC_RD)
-                at91_set_A_periph(AT91_PIN_PB3, 1);
-        if (pins & ATMEL_SSC_RK)
-                at91_set_A_periph(AT91_PIN_PB4, 1);
-        if (pins & ATMEL_SSC_RF)
-                at91_set_A_periph(AT91_PIN_PB5, 1);
-}
-static u64 ssc1_dmamask = DMA_BIT_MASK(32);
-static struct resource ssc1_resources[] = {
-        [0] = {
-                .start  = AT91RM9200_BASE_SSC1,
-                .end    = AT91RM9200_BASE_SSC1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_SSC1,
-                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_SSC1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91rm9200_ssc1_device = {
-        .name   = "at91rm9200_ssc",
-        .id     = 1,
-        .dev    = {
-                .dma_mask               = &ssc1_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = ssc1_resources,
-        .num_resources  = ARRAY_SIZE(ssc1_resources),
-};
-static inline void configure_ssc1_pins(unsigned pins)
-{
-        if (pins & ATMEL_SSC_TF)
-                at91_set_A_periph(AT91_PIN_PB6, 1);
-        if (pins & ATMEL_SSC_TK)
-                at91_set_A_periph(AT91_PIN_PB7, 1);
-        if (pins & ATMEL_SSC_TD)
-                at91_set_A_periph(AT91_PIN_PB8, 1);
-        if (pins & ATMEL_SSC_RD)
-                at91_set_A_periph(AT91_PIN_PB9, 1);
-        if (pins & ATMEL_SSC_RK)
-                at91_set_A_periph(AT91_PIN_PB10, 1);
-        if (pins & ATMEL_SSC_RF)
-                at91_set_A_periph(AT91_PIN_PB11, 1);
-}
-static u64 ssc2_dmamask = DMA_BIT_MASK(32);
-static struct resource ssc2_resources[] = {
-        [0] = {
-                .start  = AT91RM9200_BASE_SSC2,
-                .end    = AT91RM9200_BASE_SSC2 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_SSC2,
-                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_SSC2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91rm9200_ssc2_device = {
-        .name   = "at91rm9200_ssc",
-        .id     = 2,
-        .dev    = {
-                .dma_mask               = &ssc2_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = ssc2_resources,
-        .num_resources  = ARRAY_SIZE(ssc2_resources),
-};
-static inline void configure_ssc2_pins(unsigned pins)
-{
-        if (pins & ATMEL_SSC_TF)
-                at91_set_A_periph(AT91_PIN_PB12, 1);
-        if (pins & ATMEL_SSC_TK)
-                at91_set_A_periph(AT91_PIN_PB13, 1);
-        if (pins & ATMEL_SSC_TD)
-                at91_set_A_periph(AT91_PIN_PB14, 1);
-        if (pins & ATMEL_SSC_RD)
-                at91_set_A_periph(AT91_PIN_PB15, 1);
-        if (pins & ATMEL_SSC_RK)
-                at91_set_A_periph(AT91_PIN_PB16, 1);
-        if (pins & ATMEL_SSC_RF)
-                at91_set_A_periph(AT91_PIN_PB17, 1);
-}
-/*
- * SSC controllers are accessed through library code, instead of any
- * kind of all-singing/all-dancing driver.  For example one could be
- * used by a particular I2S audio codec's driver, while another one
- * on the same system might be used by a custom data capture driver.
- */
-void __init at91_add_device_ssc(unsigned id, unsigned pins)
-{
-        struct platform_device *pdev;
-        /*
-         * NOTE: caller is responsible for passing information matching
-         * "pins" to whatever will be using each particular controller.
-         */
-        switch (id) {
-        case AT91RM9200_ID_SSC0:
-                pdev = &at91rm9200_ssc0_device;
-                configure_ssc0_pins(pins);
-                break;
-        case AT91RM9200_ID_SSC1:
-                pdev = &at91rm9200_ssc1_device;
-                configure_ssc1_pins(pins);
-                break;
-        case AT91RM9200_ID_SSC2:
-                pdev = &at91rm9200_ssc2_device;
-                configure_ssc2_pins(pins);
-                break;
-        default:
-                return;
-        }
-        platform_device_register(pdev);
-}
-#else
-void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
-#endif
-/* --------------------------------------------------------------------
- *  UART
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_SERIAL_ATMEL)
-static struct resource dbgu_resources[] = {
-        [0] = {
-                .start  = AT91RM9200_BASE_DBGU,
-                .end    = AT91RM9200_BASE_DBGU + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
-                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data dbgu_data = {
-        .use_dma_tx     = 0,
-        .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
-};
-static u64 dbgu_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91rm9200_dbgu_device = {
-        .name           = "atmel_usart",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &dbgu_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &dbgu_data,
-        },
-        .resource       = dbgu_resources,
-        .num_resources  = ARRAY_SIZE(dbgu_resources),
-};
-static inline void configure_dbgu_pins(void)
-{
-        at91_set_A_periph(AT91_PIN_PA30, 0);            /* DRXD */
-        at91_set_A_periph(AT91_PIN_PA31, 1);            /* DTXD */
-}
-static struct resource uart0_resources[] = {
-        [0] = {
-                .start  = AT91RM9200_BASE_US0,
-                .end    = AT91RM9200_BASE_US0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_US0,
-                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_US0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart0_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static struct gpiod_lookup_table uart0_gpios_table = {
-        .dev_id = "atmel_usart",
-        .table = {
-                GPIO_LOOKUP("pioA", 21, "rts", GPIO_ACTIVE_LOW),
-                { },
-        },
-};
-static u64 uart0_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91rm9200_uart0_device = {
-        .name           = "atmel_usart",
-        .id             = 1,
-        .dev            = {
-                                .dma_mask               = &uart0_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart0_data,
-        },
-        .resource       = uart0_resources,
-        .num_resources  = ARRAY_SIZE(uart0_resources),
-};
-static inline void configure_usart0_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PA17, 1);            /* TXD0 */
-        at91_set_A_periph(AT91_PIN_PA18, 0);            /* RXD0 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_A_periph(AT91_PIN_PA20, 0);    /* CTS0 */
-        if (pins & ATMEL_UART_RTS) {
-                /*
-                 * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21.
-                 * We need to drive the pin manually. The serial driver will driver
-                 * this to high when initializing.
-                 */
-                gpiod_add_lookup_table(&uart0_gpios_table);
-        }
-}
-static struct resource uart1_resources[] = {
-        [0] = {
-                .start  = AT91RM9200_BASE_US1,
-                .end    = AT91RM9200_BASE_US1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_US1,
-                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_US1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart1_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static u64 uart1_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91rm9200_uart1_device = {
-        .name           = "atmel_usart",
-        .id             = 2,
-        .dev            = {
-                                .dma_mask               = &uart1_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart1_data,
-        },
-        .resource       = uart1_resources,
-        .num_resources  = ARRAY_SIZE(uart1_resources),
-};
-static inline void configure_usart1_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PB20, 1);            /* TXD1 */
-        at91_set_A_periph(AT91_PIN_PB21, 0);            /* RXD1 */
-        if (pins & ATMEL_UART_RI)
-                at91_set_A_periph(AT91_PIN_PB18, 0);    /* RI1 */
-        if (pins & ATMEL_UART_DTR)
-                at91_set_A_periph(AT91_PIN_PB19, 0);    /* DTR1 */
-        if (pins & ATMEL_UART_DCD)
-                at91_set_A_periph(AT91_PIN_PB23, 0);    /* DCD1 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_A_periph(AT91_PIN_PB24, 0);    /* CTS1 */
-        if (pins & ATMEL_UART_DSR)
-                at91_set_A_periph(AT91_PIN_PB25, 0);    /* DSR1 */
-        if (pins & ATMEL_UART_RTS)
-                at91_set_A_periph(AT91_PIN_PB26, 0);    /* RTS1 */
-}
-static struct resource uart2_resources[] = {
-        [0] = {
-                .start  = AT91RM9200_BASE_US2,
-                .end    = AT91RM9200_BASE_US2 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_US2,
-                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_US2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart2_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static u64 uart2_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91rm9200_uart2_device = {
-        .name           = "atmel_usart",
-        .id             = 3,
-        .dev            = {
-                                .dma_mask               = &uart2_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart2_data,
-        },
-        .resource       = uart2_resources,
-        .num_resources  = ARRAY_SIZE(uart2_resources),
-};
-static inline void configure_usart2_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PA22, 0);            /* RXD2 */
-        at91_set_A_periph(AT91_PIN_PA23, 1);            /* TXD2 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_B_periph(AT91_PIN_PA30, 0);    /* CTS2 */
-        if (pins & ATMEL_UART_RTS)
-                at91_set_B_periph(AT91_PIN_PA31, 0);    /* RTS2 */
-}
-static struct resource uart3_resources[] = {
-        [0] = {
-                .start  = AT91RM9200_BASE_US3,
-                .end    = AT91RM9200_BASE_US3 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_US3,
-                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_US3,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart3_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static u64 uart3_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91rm9200_uart3_device = {
-        .name           = "atmel_usart",
-        .id             = 4,
-        .dev            = {
-                                .dma_mask               = &uart3_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart3_data,
-        },
-        .resource       = uart3_resources,
-        .num_resources  = ARRAY_SIZE(uart3_resources),
-};
-static inline void configure_usart3_pins(unsigned pins)
-{
-        at91_set_B_periph(AT91_PIN_PA5, 1);             /* TXD3 */
-        at91_set_B_periph(AT91_PIN_PA6, 0);             /* RXD3 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_B_periph(AT91_PIN_PB1, 0);     /* CTS3 */
-        if (pins & ATMEL_UART_RTS)
-                at91_set_B_periph(AT91_PIN_PB0, 0);     /* RTS3 */
-}
-static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
-{
-        struct platform_device *pdev;
-        struct atmel_uart_data *pdata;
-        switch (id) {
-                case 0:         /* DBGU */
-                        pdev = &at91rm9200_dbgu_device;
-                        configure_dbgu_pins();
-                        break;
-                case AT91RM9200_ID_US0:
-                        pdev = &at91rm9200_uart0_device;
-                        configure_usart0_pins(pins);
-                        break;
-                case AT91RM9200_ID_US1:
-                        pdev = &at91rm9200_uart1_device;
-                        configure_usart1_pins(pins);
-                        break;
-                case AT91RM9200_ID_US2:
-                        pdev = &at91rm9200_uart2_device;
-                        configure_usart2_pins(pins);
-                        break;
-                case AT91RM9200_ID_US3:
-                        pdev = &at91rm9200_uart3_device;
-                        configure_usart3_pins(pins);
-                        break;
-                default:
-                        return;
-        }
-        pdata = pdev->dev.platform_data;
-        pdata->num = portnr;            /* update to mapped ID */
-        if (portnr < ATMEL_MAX_UART)
-                at91_uarts[portnr] = pdev;
-}
-void __init at91_add_device_serial(void)
-{
-        int i;
-        for (i = 0; i < ATMEL_MAX_UART; i++) {
-                if (at91_uarts[i])
-                        platform_device_register(at91_uarts[i]);
-        }
-}
-#else
-void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
-void __init at91_add_device_serial(void) {}
-#endif
-/* -------------------------------------------------------------------- */
-/*
- * These devices are always present and don't need any board-specific
- * setup.
- */
-static int __init at91_add_standard_devices(void)
-{
-        at91_add_device_rtc();
-        at91_add_device_watchdog();
-        at91_add_device_tc();
-        return 0;
-}
-arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index 7fd13aef9827..51761f8927b7 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -183,7 +183,6 @@ static struct clock_event_device clkevt = {
 void __iomem *at91_st_base;
 EXPORT_SYMBOL_GPL(at91_st_base);
-#ifdef CONFIG_OF
 static struct of_device_id at91rm9200_st_timer_ids[] = {
        { .compatible = "atmel,at91rm9200-st" },
        { /* sentinel */ }
@@ -219,28 +218,6 @@ node_err:
 err:
        return -EINVAL;
 }
-#else
-static int __init of_at91rm9200_st_init(void)
-{
-        return -EINVAL;
-}
-#endif
-void __init at91rm9200_ioremap_st(u32 addr)
-{
-#ifdef CONFIG_OF
-        struct device_node *np;
-        np = of_find_matching_node(NULL, at91rm9200_st_timer_ids);
-        if (np) {
-                of_node_put(np);
-                return;
-        }
-#endif
-        at91_st_base = ioremap(addr, 256);
-        if (!at91_st_base)
-                panic("Impossible to ioremap ST\n");
-}
 /*
 * ST (system timer) module supports both clockevents and clocksource.
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index aab1f969a7c3..78137c24d90b 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -10,305 +10,13 @@
 *
 */
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/clk/at91_pmc.h>
-#include <asm/proc-fns.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
 #include <asm/system_misc.h>
 #include <mach/cpu.h>
 #include <mach/at91_dbgu.h>
-#include <mach/at91sam9260.h>
 #include <mach/hardware.h>
-#include "at91_aic.h"
 #include "soc.h"
 #include "generic.h"
-#include "sam9_smc.h"
-#include "pm.h"
-#if defined(CONFIG_OLD_CLK_AT91)
-#include "clock.h"
-/* --------------------------------------------------------------------
- *  Clocks
- * -------------------------------------------------------------------- */
-/*
- * The peripheral clocks.
- */
-static struct clk pioA_clk = {
-        .name           = "pioA_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_PIOA,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
-        .name           = "pioB_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_PIOB,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
-        .name           = "pioC_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_PIOC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk adc_clk = {
-        .name           = "adc_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_ADC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk adc_op_clk = {
-        .name           = "adc_op_clk",
-        .type           = CLK_TYPE_PERIPHERAL,
-        .rate_hz        = 5000000,
-};
-static struct clk usart0_clk = {
-        .name           = "usart0_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_US0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
-        .name           = "usart1_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_US1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
-        .name           = "usart2_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_US2,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc_clk = {
-        .name           = "mci_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_MCI,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udc_clk = {
-        .name           = "udc_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_UDP,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi_clk = {
-        .name           = "twi_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_TWI,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
-        .name           = "spi0_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_SPI0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
-        .name           = "spi1_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_SPI1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc_clk = {
-        .name           = "ssc_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_SSC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc0_clk = {
-        .name           = "tc0_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_TC0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc1_clk = {
-        .name           = "tc1_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_TC1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc2_clk = {
-        .name           = "tc2_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_TC2,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ohci_clk = {
-        .name           = "ohci_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_UHP,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk macb_clk = {
-        .name           = "pclk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_EMAC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk isi_clk = {
-        .name           = "isi_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_ISI,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart3_clk = {
-        .name           = "usart3_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_US3,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart4_clk = {
-        .name           = "usart4_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_US4,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart5_clk = {
-        .name           = "usart5_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_US5,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc3_clk = {
-        .name           = "tc3_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_TC3,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc4_clk = {
-        .name           = "tc4_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_TC4,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc5_clk = {
-        .name           = "tc5_clk",
-        .pmc_mask       = 1 << AT91SAM9260_ID_TC5,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk *periph_clocks[] __initdata = {
-        &pioA_clk,
-        &pioB_clk,
-        &pioC_clk,
-        &adc_clk,
-        &adc_op_clk,
-        &usart0_clk,
-        &usart1_clk,
-        &usart2_clk,
-        &mmc_clk,
-        &udc_clk,
-        &twi_clk,
-        &spi0_clk,
-        &spi1_clk,
-        &ssc_clk,
-        &tc0_clk,
-        &tc1_clk,
-        &tc2_clk,
-        &ohci_clk,
-        &macb_clk,
-        &isi_clk,
-        &usart3_clk,
-        &usart4_clk,
-        &usart5_clk,
-        &tc3_clk,
-        &tc4_clk,
-        &tc5_clk,
-        // irq0 .. irq2
-};
-static struct clk_lookup periph_clocks_lookups[] = {
-        /* One additional fake clock for macb_hclk */
-        CLKDEV_CON_ID("hclk", &macb_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
-        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
-        CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
-        CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
-        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
-        CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
-        CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
-        CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc_clk),
-        CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc_clk),
-        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
-        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi_clk),
-        /* more usart lookup table for DT entries */
-        CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
-        CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
-        CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
-        CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
-        CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
-        CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
-        CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
-        /* more tc lookup table for DT entries */
-        CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
-        CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
-        CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
-        CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
-        CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
-        CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
-        CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
-        /* fake hclk clock */
-        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
-        CLKDEV_CON_ID("pioA", &pioA_clk),
-        CLKDEV_CON_ID("pioB", &pioB_clk),
-        CLKDEV_CON_ID("pioC", &pioC_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
-};
-static struct clk_lookup usart_clocks_lookups[] = {
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
-};
-/*
- * The two programmable clocks.
- * You must configure pin multiplexing to bring these signals out.
- */
-static struct clk pck0 = {
-        .name           = "pck0",
-        .pmc_mask       = AT91_PMC_PCK0,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 0,
-};
-static struct clk pck1 = {
-        .name           = "pck1",
-        .pmc_mask       = AT91_PMC_PCK1,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 1,
-};
-static void __init at91sam9260_register_clocks(void)
-{
-        int i;
-        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
-                clk_register(periph_clocks[i]);
-        clkdev_add_table(periph_clocks_lookups,
-                         ARRAY_SIZE(periph_clocks_lookups));
-        clkdev_add_table(usart_clocks_lookups,
-                         ARRAY_SIZE(usart_clocks_lookups));
-        clk_register(&pck0);
-        clk_register(&pck1);
-}
-#else
-#define at91sam9260_register_clocks NULL
-#endif
-/* --------------------------------------------------------------------
- *  GPIO
- * -------------------------------------------------------------------- */
-static struct at91_gpio_bank at91sam9260_gpio[] __initdata = {
-        {
-                .id             = AT91SAM9260_ID_PIOA,
-                .regbase        = AT91SAM9260_BASE_PIOA,
-        }, {
-                .id             = AT91SAM9260_ID_PIOB,
-                .regbase        = AT91SAM9260_BASE_PIOB,
-        }, {
-                .id             = AT91SAM9260_ID_PIOC,
-                .regbase        = AT91SAM9260_BASE_PIOC,
-        }
-};
 /* --------------------------------------------------------------------
 *  AT91SAM9260 processor initialization
@@ -340,119 +48,14 @@ static void __init at91sam9260_map_io(void)
                at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
 }
-static void __init at91sam9260_ioremap_registers(void)
-{
-        at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
-        at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
-        at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
-        at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
-        at91_pm_set_standby(at91sam9_sdram_standby);
-}
 static void __init at91sam9260_initialize(void)
 {
        arm_pm_idle = at91sam9_idle;
        at91_sysirq_mask_rtt(AT91SAM9260_BASE_RTT);
-        /* Register GPIO subsystem */
-        at91_gpio_init(at91sam9260_gpio, 3);
-}
-static struct resource rstc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9260_BASE_RSTC,
-                .end    = AT91SAM9260_BASE_RSTC + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91SAM9260_BASE_SDRAMC,
-                .end    = AT91SAM9260_BASE_SDRAMC + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device rstc_device = {
-        .name           = "at91-sam9260-reset",
-        .resource       = rstc_resources,
-        .num_resources  = ARRAY_SIZE(rstc_resources),
-};
-static struct resource shdwc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9260_BASE_SHDWC,
-                .end    = AT91SAM9260_BASE_SHDWC + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device shdwc_device = {
-        .name           = "at91-poweroff",
-        .resource       = shdwc_resources,
-        .num_resources  = ARRAY_SIZE(shdwc_resources),
-};
-static void __init at91sam9260_register_devices(void)
-{
-        platform_device_register(&rstc_device);
-        platform_device_register(&shdwc_device);
-}
-/* --------------------------------------------------------------------
- *  Interrupt initialization
- * -------------------------------------------------------------------- */
-/*
- * The default interrupt priority levels (0 = lowest, 7 = highest).
- */
-static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
-        7,      /* Advanced Interrupt Controller */
-        7,      /* System Peripherals */
-        1,      /* Parallel IO Controller A */
-        1,      /* Parallel IO Controller B */
-        1,      /* Parallel IO Controller C */
-        0,      /* Analog-to-Digital Converter */
-        5,      /* USART 0 */
-        5,      /* USART 1 */
-        5,      /* USART 2 */
-        0,      /* Multimedia Card Interface */
-        2,      /* USB Device Port */
-        6,      /* Two-Wire Interface */
-        5,      /* Serial Peripheral Interface 0 */
-        5,      /* Serial Peripheral Interface 1 */
-        5,      /* Serial Synchronous Controller */
-        0,
-        0,
-        0,      /* Timer Counter 0 */
-        0,      /* Timer Counter 1 */
-        0,      /* Timer Counter 2 */
-        2,      /* USB Host port */
-        3,      /* Ethernet */
-        0,      /* Image Sensor Interface */
-        5,      /* USART 3 */
-        5,      /* USART 4 */
-        5,      /* USART 5 */
-        0,      /* Timer Counter 3 */
-        0,      /* Timer Counter 4 */
-        0,      /* Timer Counter 5 */
-        0,      /* Advanced Interrupt Controller */
-        0,      /* Advanced Interrupt Controller */
-        0,      /* Advanced Interrupt Controller */
-};
-static void __init at91sam9260_init_time(void)
-{
-        at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
 }
 AT91_SOC_START(at91sam9260)
        .map_io = at91sam9260_map_io,
-        .default_irq_priority = at91sam9260_default_irq_priority,
-        .extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
-                    | (1 << AT91SAM9260_ID_IRQ2),
-        .ioremap_registers = at91sam9260_ioremap_registers,
-        .register_clocks = at91sam9260_register_clocks,
-        .register_devices = at91sam9260_register_devices,
        .init = at91sam9260_initialize,
-        .init_time = at91sam9260_init_time,
 AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
deleted file mode 100644
index ef88e0fe4e80..000000000000
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ /dev/null
@@ -1,1364 +0,0 @@
-/*
- * arch/arm/mach-at91/at91sam9260_devices.c
- *
- *  Copyright (C) 2006 Atmel
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/i2c-gpio.h>
-#include <linux/platform_data/at91_adc.h>
-#include <mach/cpu.h>
-#include <mach/at91sam9260.h>
-#include <mach/at91sam9260_matrix.h>
-#include <mach/at91_matrix.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/hardware.h>
-#include "board.h"
-#include "generic.h"
-#include "gpio.h"
-/* --------------------------------------------------------------------
- *  USB Host
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static u64 ohci_dmamask = DMA_BIT_MASK(32);
-static struct at91_usbh_data usbh_data;
-static struct resource usbh_resources[] = {
-        [0] = {
-                .start  = AT91SAM9260_UHP_BASE,
-                .end    = AT91SAM9260_UHP_BASE + SZ_1M - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_UHP,
-                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_UHP,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91_usbh_device = {
-        .name           = "at91_ohci",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &ohci_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &usbh_data,
-        },
-        .resource       = usbh_resources,
-        .num_resources  = ARRAY_SIZE(usbh_resources),
-};
-void __init at91_add_device_usbh(struct at91_usbh_data *data)
-{
-        int i;
-        if (!data)
-                return;
-        /* Enable overcurrent notification */
-        for (i = 0; i < data->ports; i++) {
-                if (gpio_is_valid(data->overcurrent_pin[i]))
-                        at91_set_gpio_input(data->overcurrent_pin[i], 1);
-        }
-        usbh_data = *data;
-        platform_device_register(&at91_usbh_device);
-}
-#else
-void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  USB Device (Gadget)
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
-static struct at91_udc_data udc_data;
-static struct resource udc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9260_BASE_UDP,
-                .end    = AT91SAM9260_BASE_UDP + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_UDP,
-                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_UDP,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91_udc_device = {
-        .name           = "at91_udc",
-        .id             = -1,
-        .dev            = {
-                                .platform_data          = &udc_data,
-        },
-        .resource       = udc_resources,
-        .num_resources  = ARRAY_SIZE(udc_resources),
-};
-void __init at91_add_device_udc(struct at91_udc_data *data)
-{
-        if (!data)
-                return;
-        if (gpio_is_valid(data->vbus_pin)) {
-                at91_set_gpio_input(data->vbus_pin, 0);
-                at91_set_deglitch(data->vbus_pin, 1);
-        }
-        /* Pullup pin is handled internally by USB device peripheral */
-        udc_data = *data;
-        platform_device_register(&at91_udc_device);
-}
-#else
-void __init at91_add_device_udc(struct at91_udc_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  Ethernet
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
-static u64 eth_dmamask = DMA_BIT_MASK(32);
-static struct macb_platform_data eth_data;
-static struct resource eth_resources[] = {
-        [0] = {
-                .start  = AT91SAM9260_BASE_EMAC,
-                .end    = AT91SAM9260_BASE_EMAC + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_EMAC,
-                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_EMAC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9260_eth_device = {
-        .name           = "macb",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &eth_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &eth_data,
-        },
-        .resource       = eth_resources,
-        .num_resources  = ARRAY_SIZE(eth_resources),
-};
-void __init at91_add_device_eth(struct macb_platform_data *data)
-{
-        if (!data)
-                return;
-        if (gpio_is_valid(data->phy_irq_pin)) {
-                at91_set_gpio_input(data->phy_irq_pin, 0);
-                at91_set_deglitch(data->phy_irq_pin, 1);
-        }
-        /* Pins used for MII and RMII */
-        at91_set_A_periph(AT91_PIN_PA19, 0);    /* ETXCK_EREFCK */
-        at91_set_A_periph(AT91_PIN_PA17, 0);    /* ERXDV */
-        at91_set_A_periph(AT91_PIN_PA14, 0);    /* ERX0 */
-        at91_set_A_periph(AT91_PIN_PA15, 0);    /* ERX1 */
-        at91_set_A_periph(AT91_PIN_PA18, 0);    /* ERXER */
-        at91_set_A_periph(AT91_PIN_PA16, 0);    /* ETXEN */
-        at91_set_A_periph(AT91_PIN_PA12, 0);    /* ETX0 */
-        at91_set_A_periph(AT91_PIN_PA13, 0);    /* ETX1 */
-        at91_set_A_periph(AT91_PIN_PA21, 0);    /* EMDIO */
-        at91_set_A_periph(AT91_PIN_PA20, 0);    /* EMDC */
-        if (!data->is_rmii) {
-                at91_set_B_periph(AT91_PIN_PA28, 0);    /* ECRS */
-                at91_set_B_periph(AT91_PIN_PA29, 0);    /* ECOL */
-                at91_set_B_periph(AT91_PIN_PA25, 0);    /* ERX2 */
-                at91_set_B_periph(AT91_PIN_PA26, 0);    /* ERX3 */
-                at91_set_B_periph(AT91_PIN_PA27, 0);    /* ERXCK */
-                at91_set_B_periph(AT91_PIN_PA23, 0);    /* ETX2 */
-                at91_set_B_periph(AT91_PIN_PA24, 0);    /* ETX3 */
-                at91_set_B_periph(AT91_PIN_PA22, 0);    /* ETXER */
-        }
-        eth_data = *data;
-        platform_device_register(&at91sam9260_eth_device);
-}
-#else
-void __init at91_add_device_eth(struct macb_platform_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  MMC / SD Slot for Atmel MCI Driver
- * -------------------------------------------------------------------- */
-#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
-static u64 mmc_dmamask = DMA_BIT_MASK(32);
-static struct mci_platform_data mmc_data;
-static struct resource mmc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9260_BASE_MCI,
-                .end    = AT91SAM9260_BASE_MCI + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI,
-                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9260_mmc_device = {
-        .name           = "atmel_mci",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &mmc_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &mmc_data,
-        },
-        .resource       = mmc_resources,
-        .num_resources  = ARRAY_SIZE(mmc_resources),
-};
-void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
-{
-        unsigned int i;
-        unsigned int slot_count = 0;
-        if (!data)
-                return;
-        for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
-                if (data->slot[i].bus_width) {
-                        /* input/irq */
-                        if (gpio_is_valid(data->slot[i].detect_pin)) {
-                                at91_set_gpio_input(data->slot[i].detect_pin, 1);
-                                at91_set_deglitch(data->slot[i].detect_pin, 1);
-                        }
-                        if (gpio_is_valid(data->slot[i].wp_pin))
-                                at91_set_gpio_input(data->slot[i].wp_pin, 1);
-                        switch (i) {
-                        case 0:
-                                /* CMD */
-                                at91_set_A_periph(AT91_PIN_PA7, 1);
-                                /* DAT0, maybe DAT1..DAT3 */
-                                at91_set_A_periph(AT91_PIN_PA6, 1);
-                                if (data->slot[i].bus_width == 4) {
-                                        at91_set_A_periph(AT91_PIN_PA9, 1);
-                                        at91_set_A_periph(AT91_PIN_PA10, 1);
-                                        at91_set_A_periph(AT91_PIN_PA11, 1);
-                                }
-                                slot_count++;
-                                break;
-                        case 1:
-                                /* CMD */
-                                at91_set_B_periph(AT91_PIN_PA1, 1);
-                                /* DAT0, maybe DAT1..DAT3 */
-                                at91_set_B_periph(AT91_PIN_PA0, 1);
-                                if (data->slot[i].bus_width == 4) {
-                                        at91_set_B_periph(AT91_PIN_PA5, 1);
-                                        at91_set_B_periph(AT91_PIN_PA4, 1);
-                                        at91_set_B_periph(AT91_PIN_PA3, 1);
-                                }
-                                slot_count++;
-                                break;
-                        default:
-                                printk(KERN_ERR
-                                        "AT91: SD/MMC slot %d not available\n", i);
-                                break;
-                        }
-                }
-        }
-        if (slot_count) {
-                /* CLK */
-                at91_set_A_periph(AT91_PIN_PA8, 0);
-                mmc_data = *data;
-                platform_device_register(&at91sam9260_mmc_device);
-        }
-}
-#else
-void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  NAND / SmartMedia
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
-static struct atmel_nand_data nand_data;
-#define NAND_BASE       AT91_CHIPSELECT_3
-static struct resource nand_resources[] = {
-        [0] = {
-                .start  = NAND_BASE,
-                .end    = NAND_BASE + SZ_256M - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91SAM9260_BASE_ECC,
-                .end    = AT91SAM9260_BASE_ECC + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct platform_device at91sam9260_nand_device = {
-        .name           = "atmel_nand",
-        .id             = -1,
-        .dev            = {
-                                .platform_data  = &nand_data,
-        },
-        .resource       = nand_resources,
-        .num_resources  = ARRAY_SIZE(nand_resources),
-};
-void __init at91_add_device_nand(struct atmel_nand_data *data)
-{
-        unsigned long csa;
-        if (!data)
-                return;
-        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
-        at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
-        /* enable pin */
-        if (gpio_is_valid(data->enable_pin))
-                at91_set_gpio_output(data->enable_pin, 1);
-        /* ready/busy pin */
-        if (gpio_is_valid(data->rdy_pin))
-                at91_set_gpio_input(data->rdy_pin, 1);
-        /* card detect pin */
-        if (gpio_is_valid(data->det_pin))
-                at91_set_gpio_input(data->det_pin, 1);
-        nand_data = *data;
-        platform_device_register(&at91sam9260_nand_device);
-}
-#else
-void __init at91_add_device_nand(struct atmel_nand_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  TWI (i2c)
- * -------------------------------------------------------------------- */
-/*
- * Prefer the GPIO code since the TWI controller isn't robust
- * (gets overruns and underruns under load) and can only issue
- * repeated STARTs in one scenario (the driver doesn't yet handle them).
- */
-#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
-static struct i2c_gpio_platform_data pdata = {
-        .sda_pin                = AT91_PIN_PA23,
-        .sda_is_open_drain      = 1,
-        .scl_pin                = AT91_PIN_PA24,
-        .scl_is_open_drain      = 1,
-        .udelay                 = 2,            /* ~100 kHz */
-};
-static struct platform_device at91sam9260_twi_device = {
-        .name                   = "i2c-gpio",
-        .id                     = 0,
-        .dev.platform_data      = &pdata,
-};
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
-{
-        at91_set_GPIO_periph(AT91_PIN_PA23, 1);         /* TWD (SDA) */
-        at91_set_multi_drive(AT91_PIN_PA23, 1);
-        at91_set_GPIO_periph(AT91_PIN_PA24, 1);         /* TWCK (SCL) */
-        at91_set_multi_drive(AT91_PIN_PA24, 1);
-        i2c_register_board_info(0, devices, nr_devices);
-        platform_device_register(&at91sam9260_twi_device);
-}
-#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
-static struct resource twi_resources[] = {
-        [0] = {
-                .start  = AT91SAM9260_BASE_TWI,
-                .end    = AT91SAM9260_BASE_TWI + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_TWI,
-                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_TWI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9260_twi_device = {
-        .id             = 0,
-        .resource       = twi_resources,
-        .num_resources  = ARRAY_SIZE(twi_resources),
-};
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
-{
-        /* IP version is not the same on 9260 and g20 */
-        if (cpu_is_at91sam9g20()) {
-                at91sam9260_twi_device.name = "i2c-at91sam9g20";
-        } else {
-                at91sam9260_twi_device.name = "i2c-at91sam9260";
-        }
-        /* pins used for TWI interface */
-        at91_set_A_periph(AT91_PIN_PA23, 0);            /* TWD */
-        at91_set_multi_drive(AT91_PIN_PA23, 1);
-        at91_set_A_periph(AT91_PIN_PA24, 0);            /* TWCK */
-        at91_set_multi_drive(AT91_PIN_PA24, 1);
-        i2c_register_board_info(0, devices, nr_devices);
-        platform_device_register(&at91sam9260_twi_device);
-}
-#else
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
-#endif
-/* --------------------------------------------------------------------
- *  SPI
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
-static u64 spi_dmamask = DMA_BIT_MASK(32);
-static struct resource spi0_resources[] = {
-        [0] = {
-                .start  = AT91SAM9260_BASE_SPI0,
-                .end    = AT91SAM9260_BASE_SPI0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI0,
-                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9260_spi0_device = {
-        .name           = "atmel_spi",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &spi_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = spi0_resources,
-        .num_resources  = ARRAY_SIZE(spi0_resources),
-};
-static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PC11, AT91_PIN_PC16, AT91_PIN_PC17 };
-static struct resource spi1_resources[] = {
-        [0] = {
-                .start  = AT91SAM9260_BASE_SPI1,
-                .end    = AT91SAM9260_BASE_SPI1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI1,
-                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9260_spi1_device = {
-        .name           = "atmel_spi",
-        .id             = 1,
-        .dev            = {
-                                .dma_mask               = &spi_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = spi1_resources,
-        .num_resources  = ARRAY_SIZE(spi1_resources),
-};
-static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PC5, AT91_PIN_PC4, AT91_PIN_PC3 };
-void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
-{
-        int i;
-        unsigned long cs_pin;
-        short enable_spi0 = 0;
-        short enable_spi1 = 0;
-        /* Choose SPI chip-selects */
-        for (i = 0; i < nr_devices; i++) {
-                if (devices[i].controller_data)
-                        cs_pin = (unsigned long) devices[i].controller_data;
-                else if (devices[i].bus_num == 0)
-                        cs_pin = spi0_standard_cs[devices[i].chip_select];
-                else
-                        cs_pin = spi1_standard_cs[devices[i].chip_select];
-                if (!gpio_is_valid(cs_pin))
-                        continue;
-                if (devices[i].bus_num == 0)
-                        enable_spi0 = 1;
-                else
-                        enable_spi1 = 1;
-                /* enable chip-select pin */
-                at91_set_gpio_output(cs_pin, 1);
-                /* pass chip-select pin to driver */
-                devices[i].controller_data = (void *) cs_pin;
-        }
-        spi_register_board_info(devices, nr_devices);
-        /* Configure SPI bus(es) */
-        if (enable_spi0) {
-                at91_set_A_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
-                at91_set_A_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
-                at91_set_A_periph(AT91_PIN_PA2, 0);     /* SPI1_SPCK */
-                platform_device_register(&at91sam9260_spi0_device);
-        }
-        if (enable_spi1) {
-                at91_set_A_periph(AT91_PIN_PB0, 0);     /* SPI1_MISO */
-                at91_set_A_periph(AT91_PIN_PB1, 0);     /* SPI1_MOSI */
-                at91_set_A_periph(AT91_PIN_PB2, 0);     /* SPI1_SPCK */
-                platform_device_register(&at91sam9260_spi1_device);
-        }
-}
-#else
-void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
-#endif
-/* --------------------------------------------------------------------
- *  Timer/Counter blocks
- * -------------------------------------------------------------------- */
-#ifdef CONFIG_ATMEL_TCLIB
-static struct resource tcb0_resources[] = {
-        [0] = {
-                .start  = AT91SAM9260_BASE_TCB0,
-                .end    = AT91SAM9260_BASE_TCB0 + SZ_256 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_TC0,
-                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_TC0,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_TC1,
-                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_TC1,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_TC2,
-                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_TC2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9260_tcb0_device = {
-        .name           = "atmel_tcb",
-        .id             = 0,
-        .resource       = tcb0_resources,
-        .num_resources  = ARRAY_SIZE(tcb0_resources),
-};
-static struct resource tcb1_resources[] = {
-        [0] = {
-                .start  = AT91SAM9260_BASE_TCB1,
-                .end    = AT91SAM9260_BASE_TCB1 + SZ_256 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_TC3,
-                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_TC3,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_TC4,
-                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_TC4,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_TC5,
-                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_TC5,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9260_tcb1_device = {
-        .name           = "atmel_tcb",
-        .id             = 1,
-        .resource       = tcb1_resources,
-        .num_resources  = ARRAY_SIZE(tcb1_resources),
-};
-static void __init at91_add_device_tc(void)
-{
-        platform_device_register(&at91sam9260_tcb0_device);
-        platform_device_register(&at91sam9260_tcb1_device);
-}
-#else
-static void __init at91_add_device_tc(void) { }
-#endif
-/* --------------------------------------------------------------------
- *  RTT
- * -------------------------------------------------------------------- */
-static struct resource rtt_resources[] = {
-        {
-                .start  = AT91SAM9260_BASE_RTT,
-                .end    = AT91SAM9260_BASE_RTT + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9260_rtt_device = {
-        .name           = "at91_rtt",
-        .id             = 0,
-        .resource       = rtt_resources,
-};
-#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
-static void __init at91_add_device_rtt_rtc(void)
-{
-        at91sam9260_rtt_device.name = "rtc-at91sam9";
-        /*
-         * The second resource is needed:
-         * GPBR will serve as the storage for RTC time offset
-         */
-        at91sam9260_rtt_device.num_resources = 3;
-        rtt_resources[1].start = AT91SAM9260_BASE_GPBR +
-                                 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
-        rtt_resources[1].end = rtt_resources[1].start + 3;
-        rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
-        rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
-}
-#else
-static void __init at91_add_device_rtt_rtc(void)
-{
-        /* Only one resource is needed: RTT not used as RTC */
-        at91sam9260_rtt_device.num_resources = 1;
-}
-#endif
-static void __init at91_add_device_rtt(void)
-{
-        at91_add_device_rtt_rtc();
-        platform_device_register(&at91sam9260_rtt_device);
-}
-/* --------------------------------------------------------------------
- *  Watchdog
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
-static struct resource wdt_resources[] = {
-        {
-                .start  = AT91SAM9260_BASE_WDT,
-                .end    = AT91SAM9260_BASE_WDT + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct platform_device at91sam9260_wdt_device = {
-        .name           = "at91_wdt",
-        .id             = -1,
-        .resource       = wdt_resources,
-        .num_resources  = ARRAY_SIZE(wdt_resources),
-};
-static void __init at91_add_device_watchdog(void)
-{
-        platform_device_register(&at91sam9260_wdt_device);
-}
-#else
-static void __init at91_add_device_watchdog(void) {}
-#endif
-/* --------------------------------------------------------------------
- *  SSC -- Synchronous Serial Controller
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
-static u64 ssc_dmamask = DMA_BIT_MASK(32);
-static struct resource ssc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9260_BASE_SSC,
-                .end    = AT91SAM9260_BASE_SSC + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_SSC,
-                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_SSC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9260_ssc_device = {
-        .name   = "at91rm9200_ssc",
-        .id     = 0,
-        .dev    = {
-                .dma_mask               = &ssc_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = ssc_resources,
-        .num_resources  = ARRAY_SIZE(ssc_resources),
-};
-static inline void configure_ssc_pins(unsigned pins)
-{
-        if (pins & ATMEL_SSC_TF)
-                at91_set_A_periph(AT91_PIN_PB17, 1);
-        if (pins & ATMEL_SSC_TK)
-                at91_set_A_periph(AT91_PIN_PB16, 1);
-        if (pins & ATMEL_SSC_TD)
-                at91_set_A_periph(AT91_PIN_PB18, 1);
-        if (pins & ATMEL_SSC_RD)
-                at91_set_A_periph(AT91_PIN_PB19, 1);
-        if (pins & ATMEL_SSC_RK)
-                at91_set_A_periph(AT91_PIN_PB20, 1);
-        if (pins & ATMEL_SSC_RF)
-                at91_set_A_periph(AT91_PIN_PB21, 1);
-}
-/*
- * SSC controllers are accessed through library code, instead of any
- * kind of all-singing/all-dancing driver.  For example one could be
- * used by a particular I2S audio codec's driver, while another one
- * on the same system might be used by a custom data capture driver.
- */
-void __init at91_add_device_ssc(unsigned id, unsigned pins)
-{
-        struct platform_device *pdev;
-        /*
-         * NOTE: caller is responsible for passing information matching
-         * "pins" to whatever will be using each particular controller.
-         */
-        switch (id) {
-        case AT91SAM9260_ID_SSC:
-                pdev = &at91sam9260_ssc_device;
-                configure_ssc_pins(pins);
-                break;
-        default:
-                return;
-        }
-        platform_device_register(pdev);
-}
-#else
-void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
-#endif
-/* --------------------------------------------------------------------
- *  UART
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_SERIAL_ATMEL)
-static struct resource dbgu_resources[] = {
-        [0] = {
-                .start  = AT91SAM9260_BASE_DBGU,
-                .end    = AT91SAM9260_BASE_DBGU + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
-                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data dbgu_data = {
-        .use_dma_tx     = 0,
-        .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
-};
-static u64 dbgu_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9260_dbgu_device = {
-        .name           = "atmel_usart",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &dbgu_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &dbgu_data,
-        },
-        .resource       = dbgu_resources,
-        .num_resources  = ARRAY_SIZE(dbgu_resources),
-};
-static inline void configure_dbgu_pins(void)
-{
-        at91_set_A_periph(AT91_PIN_PB14, 0);            /* DRXD */
-        at91_set_A_periph(AT91_PIN_PB15, 1);            /* DTXD */
-}
-static struct resource uart0_resources[] = {
-        [0] = {
-                .start  = AT91SAM9260_BASE_US0,
-                .end    = AT91SAM9260_BASE_US0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_US0,
-                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_US0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart0_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static u64 uart0_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9260_uart0_device = {
-        .name           = "atmel_usart",
-        .id             = 1,
-        .dev            = {
-                                .dma_mask               = &uart0_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart0_data,
-        },
-        .resource       = uart0_resources,
-        .num_resources  = ARRAY_SIZE(uart0_resources),
-};
-static inline void configure_usart0_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PB4, 1);             /* TXD0 */
-        at91_set_A_periph(AT91_PIN_PB5, 0);             /* RXD0 */
-        if (pins & ATMEL_UART_RTS)
-                at91_set_A_periph(AT91_PIN_PB26, 0);    /* RTS0 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_A_periph(AT91_PIN_PB27, 0);    /* CTS0 */
-        if (pins & ATMEL_UART_DTR)
-                at91_set_A_periph(AT91_PIN_PB24, 0);    /* DTR0 */
-        if (pins & ATMEL_UART_DSR)
-                at91_set_A_periph(AT91_PIN_PB22, 0);    /* DSR0 */
-        if (pins & ATMEL_UART_DCD)
-                at91_set_A_periph(AT91_PIN_PB23, 0);    /* DCD0 */
-        if (pins & ATMEL_UART_RI)
-                at91_set_A_periph(AT91_PIN_PB25, 0);    /* RI0 */
-}
-static struct resource uart1_resources[] = {
-        [0] = {
-                .start  = AT91SAM9260_BASE_US1,
-                .end    = AT91SAM9260_BASE_US1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_US1,
-                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_US1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart1_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static u64 uart1_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9260_uart1_device = {
-        .name           = "atmel_usart",
-        .id             = 2,
-        .dev            = {
-                                .dma_mask               = &uart1_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart1_data,
-        },
-        .resource       = uart1_resources,
-        .num_resources  = ARRAY_SIZE(uart1_resources),
-};
-static inline void configure_usart1_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PB6, 1);             /* TXD1 */
-        at91_set_A_periph(AT91_PIN_PB7, 0);             /* RXD1 */
-        if (pins & ATMEL_UART_RTS)
-                at91_set_A_periph(AT91_PIN_PB28, 0);    /* RTS1 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_A_periph(AT91_PIN_PB29, 0);    /* CTS1 */
-}
-static struct resource uart2_resources[] = {
-        [0] = {
-                .start  = AT91SAM9260_BASE_US2,
-                .end    = AT91SAM9260_BASE_US2 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_US2,
-                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_US2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart2_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static u64 uart2_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9260_uart2_device = {
-        .name           = "atmel_usart",
-        .id             = 3,
-        .dev            = {
-                                .dma_mask               = &uart2_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart2_data,
-        },
-        .resource       = uart2_resources,
-        .num_resources  = ARRAY_SIZE(uart2_resources),
-};
-static inline void configure_usart2_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PB8, 1);             /* TXD2 */
-        at91_set_A_periph(AT91_PIN_PB9, 0);             /* RXD2 */
-        if (pins & ATMEL_UART_RTS)
-                at91_set_A_periph(AT91_PIN_PA4, 0);     /* RTS2 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_A_periph(AT91_PIN_PA5, 0);     /* CTS2 */
-}
-static struct resource uart3_resources[] = {
-        [0] = {
-                .start  = AT91SAM9260_BASE_US3,
-                .end    = AT91SAM9260_BASE_US3 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_US3,
-                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_US3,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart3_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static u64 uart3_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9260_uart3_device = {
-        .name           = "atmel_usart",
-        .id             = 4,
-        .dev            = {
-                                .dma_mask               = &uart3_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart3_data,
-        },
-        .resource       = uart3_resources,
-        .num_resources  = ARRAY_SIZE(uart3_resources),
-};
-static inline void configure_usart3_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PB10, 1);            /* TXD3 */
-        at91_set_A_periph(AT91_PIN_PB11, 0);            /* RXD3 */
-        if (pins & ATMEL_UART_RTS)
-                at91_set_B_periph(AT91_PIN_PC8, 0);     /* RTS3 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_B_periph(AT91_PIN_PC10, 0);    /* CTS3 */
-}
-static struct resource uart4_resources[] = {
-        [0] = {
-                .start  = AT91SAM9260_BASE_US4,
-                .end    = AT91SAM9260_BASE_US4 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_US4,
-                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_US4,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart4_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static u64 uart4_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9260_uart4_device = {
-        .name           = "atmel_usart",
-        .id             = 5,
-        .dev            = {
-                                .dma_mask               = &uart4_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart4_data,
-        },
-        .resource       = uart4_resources,
-        .num_resources  = ARRAY_SIZE(uart4_resources),
-};
-static inline void configure_usart4_pins(void)
-{
-        at91_set_B_periph(AT91_PIN_PA31, 1);            /* TXD4 */
-        at91_set_B_periph(AT91_PIN_PA30, 0);            /* RXD4 */
-}
-static struct resource uart5_resources[] = {
-        [0] = {
-                .start  = AT91SAM9260_BASE_US5,
-                .end    = AT91SAM9260_BASE_US5 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_US5,
-                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_US5,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart5_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static u64 uart5_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9260_uart5_device = {
-        .name           = "atmel_usart",
-        .id             = 6,
-        .dev            = {
-                                .dma_mask               = &uart5_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart5_data,
-        },
-        .resource       = uart5_resources,
-        .num_resources  = ARRAY_SIZE(uart5_resources),
-};
-static inline void configure_usart5_pins(void)
-{
-        at91_set_A_periph(AT91_PIN_PB12, 1);            /* TXD5 */
-        at91_set_A_periph(AT91_PIN_PB13, 0);            /* RXD5 */
-}
-static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
-{
-        struct platform_device *pdev;
-        struct atmel_uart_data *pdata;
-        switch (id) {
-                case 0:         /* DBGU */
-                        pdev = &at91sam9260_dbgu_device;
-                        configure_dbgu_pins();
-                        break;
-                case AT91SAM9260_ID_US0:
-                        pdev = &at91sam9260_uart0_device;
-                        configure_usart0_pins(pins);
-                        break;
-                case AT91SAM9260_ID_US1:
-                        pdev = &at91sam9260_uart1_device;
-                        configure_usart1_pins(pins);
-                        break;
-                case AT91SAM9260_ID_US2:
-                        pdev = &at91sam9260_uart2_device;
-                        configure_usart2_pins(pins);
-                        break;
-                case AT91SAM9260_ID_US3:
-                        pdev = &at91sam9260_uart3_device;
-                        configure_usart3_pins(pins);
-                        break;
-                case AT91SAM9260_ID_US4:
-                        pdev = &at91sam9260_uart4_device;
-                        configure_usart4_pins();
-                        break;
-                case AT91SAM9260_ID_US5:
-                        pdev = &at91sam9260_uart5_device;
-                        configure_usart5_pins();
-                        break;
-                default:
-                        return;
-        }
-        pdata = pdev->dev.platform_data;
-        pdata->num = portnr;            /* update to mapped ID */
-        if (portnr < ATMEL_MAX_UART)
-                at91_uarts[portnr] = pdev;
-}
-void __init at91_add_device_serial(void)
-{
-        int i;
-        for (i = 0; i < ATMEL_MAX_UART; i++) {
-                if (at91_uarts[i])
-                        platform_device_register(at91_uarts[i]);
-        }
-}
-#else
-void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
-void __init at91_add_device_serial(void) {}
-#endif
-/* --------------------------------------------------------------------
- *  CF/IDE
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
-        defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
-static struct at91_cf_data cf0_data;
-static struct resource cf0_resources[] = {
-        [0] = {
-                .start  = AT91_CHIPSELECT_4,
-                .end    = AT91_CHIPSELECT_4 + SZ_256M - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct platform_device cf0_device = {
-        .id             = 0,
-        .dev            = {
-                                .platform_data  = &cf0_data,
-        },
-        .resource       = cf0_resources,
-        .num_resources  = ARRAY_SIZE(cf0_resources),
-};
-static struct at91_cf_data cf1_data;
-static struct resource cf1_resources[] = {
-        [0] = {
-                .start  = AT91_CHIPSELECT_5,
-                .end    = AT91_CHIPSELECT_5 + SZ_256M - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct platform_device cf1_device = {
-        .id             = 1,
-        .dev            = {
-                                .platform_data  = &cf1_data,
-        },
-        .resource       = cf1_resources,
-        .num_resources  = ARRAY_SIZE(cf1_resources),
-};
-void __init at91_add_device_cf(struct at91_cf_data *data)
-{
-        struct platform_device *pdev;
-        unsigned long csa;
-        if (!data)
-                return;
-        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
-        switch (data->chipselect) {
-        case 4:
-                at91_set_multi_drive(AT91_PIN_PC8, 0);
-                at91_set_A_periph(AT91_PIN_PC8, 0);
-                csa |= AT91_MATRIX_CS4A_SMC_CF1;
-                cf0_data = *data;
-                pdev = &cf0_device;
-                break;
-        case 5:
-                at91_set_multi_drive(AT91_PIN_PC9, 0);
-                at91_set_A_periph(AT91_PIN_PC9, 0);
-                csa |= AT91_MATRIX_CS5A_SMC_CF2;
-                cf1_data = *data;
-                pdev = &cf1_device;
-                break;
-        default:
-                printk(KERN_ERR "AT91 CF: bad chip-select requested (%u)\n",
-                       data->chipselect);
-                return;
-        }
-        at91_matrix_write(AT91_MATRIX_EBICSA, csa);
-        if (gpio_is_valid(data->rst_pin)) {
-                at91_set_multi_drive(data->rst_pin, 0);
-                at91_set_gpio_output(data->rst_pin, 1);
-        }
-        if (gpio_is_valid(data->irq_pin)) {
-                at91_set_gpio_input(data->irq_pin, 0);
-                at91_set_deglitch(data->irq_pin, 1);
-        }
-        if (gpio_is_valid(data->det_pin)) {
-                at91_set_gpio_input(data->det_pin, 0);
-                at91_set_deglitch(data->det_pin, 1);
-        }
-        at91_set_B_periph(AT91_PIN_PC6, 0);     /* CFCE1 */
-        at91_set_B_periph(AT91_PIN_PC7, 0);     /* CFCE2 */
-        at91_set_A_periph(AT91_PIN_PC10, 0);    /* CFRNW */
-        at91_set_A_periph(AT91_PIN_PC15, 1);    /* NWAIT */
-        if (IS_ENABLED(CONFIG_PATA_AT91) && (data->flags & AT91_CF_TRUE_IDE))
-                pdev->name = "pata_at91";
-        else
-                pdev->name = "at91_cf";
-        platform_device_register(pdev);
-}
-#else
-void __init at91_add_device_cf(struct at91_cf_data * data) {}
-#endif
-/* --------------------------------------------------------------------
- *  ADCs
- * -------------------------------------------------------------------- */
-#if IS_ENABLED(CONFIG_AT91_ADC)
-static struct at91_adc_data adc_data;
-static struct resource adc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9260_BASE_ADC,
-                .end    = AT91SAM9260_BASE_ADC + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_ADC,
-                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_ADC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91_adc_device = {
-        .name           = "at91sam9260-adc",
-        .id             = -1,
-        .dev            = {
-                                .platform_data          = &adc_data,
-        },
-        .resource       = adc_resources,
-        .num_resources  = ARRAY_SIZE(adc_resources),
-};
-static struct at91_adc_trigger at91_adc_triggers[] = {
-        [0] = {
-                .name = "timer-counter-0",
-                .value = 0x1,
-        },
-        [1] = {
-                .name = "timer-counter-1",
-                .value = 0x3,
-        },
-        [2] = {
-                .name = "timer-counter-2",
-                .value = 0x5,
-        },
-        [3] = {
-                .name = "external",
-                .value = 0xd,
-                .is_external = true,
-        },
-};
-void __init at91_add_device_adc(struct at91_adc_data *data)
-{
-        if (!data)
-                return;
-        if (test_bit(0, &data->channels_used))
-                at91_set_A_periph(AT91_PIN_PC0, 0);
-        if (test_bit(1, &data->channels_used))
-                at91_set_A_periph(AT91_PIN_PC1, 0);
-        if (test_bit(2, &data->channels_used))
-                at91_set_A_periph(AT91_PIN_PC2, 0);
-        if (test_bit(3, &data->channels_used))
-                at91_set_A_periph(AT91_PIN_PC3, 0);
-        if (data->use_external_triggers)
-                at91_set_A_periph(AT91_PIN_PA22, 0);
-        data->startup_time = 10;
-        data->trigger_number = 4;
-        data->trigger_list = at91_adc_triggers;
-        adc_data = *data;
-        platform_device_register(&at91_adc_device);
-}
-#else
-void __init at91_add_device_adc(struct at91_adc_data *data) {}
-#endif
-/* -------------------------------------------------------------------- */
-/*
- * These devices are always present and don't need any board-specific
- * setup.
- */
-static int __init at91_add_standard_devices(void)
-{
-        if (of_have_populated_dt())
-                return 0;
-        at91_add_device_rtt();
-        at91_add_device_watchdog();
-        at91_add_device_tc();
-        return 0;
-}
-arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index a8bd35963332..d29953ecb0c4 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -10,282 +10,12 @@
 *
 */
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/clk/at91_pmc.h>
-#include <asm/proc-fns.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
 #include <asm/system_misc.h>
 #include <mach/cpu.h>
-#include <mach/at91sam9261.h>
 #include <mach/hardware.h>
-#include "at91_aic.h"
 #include "soc.h"
 #include "generic.h"
-#include "sam9_smc.h"
-#include "pm.h"
-#if defined(CONFIG_OLD_CLK_AT91)
-#include "clock.h"
-/* --------------------------------------------------------------------
- *  Clocks
- * -------------------------------------------------------------------- */
-/*
- * The peripheral clocks.
- */
-static struct clk pioA_clk = {
-        .name           = "pioA_clk",
-        .pmc_mask       = 1 << AT91SAM9261_ID_PIOA,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
-        .name           = "pioB_clk",
-        .pmc_mask       = 1 << AT91SAM9261_ID_PIOB,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
-        .name           = "pioC_clk",
-        .pmc_mask       = 1 << AT91SAM9261_ID_PIOC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
-        .name           = "usart0_clk",
-        .pmc_mask       = 1 << AT91SAM9261_ID_US0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
-        .name           = "usart1_clk",
-        .pmc_mask       = 1 << AT91SAM9261_ID_US1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
-        .name           = "usart2_clk",
-        .pmc_mask       = 1 << AT91SAM9261_ID_US2,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc_clk = {
-        .name           = "mci_clk",
-        .pmc_mask       = 1 << AT91SAM9261_ID_MCI,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udc_clk = {
-        .name           = "udc_clk",
-        .pmc_mask       = 1 << AT91SAM9261_ID_UDP,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi_clk = {
-        .name           = "twi_clk",
-        .pmc_mask       = 1 << AT91SAM9261_ID_TWI,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
-        .name           = "spi0_clk",
-        .pmc_mask       = 1 << AT91SAM9261_ID_SPI0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
-        .name           = "spi1_clk",
-        .pmc_mask       = 1 << AT91SAM9261_ID_SPI1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
-        .name           = "ssc0_clk",
-        .pmc_mask       = 1 << AT91SAM9261_ID_SSC0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
-        .name           = "ssc1_clk",
-        .pmc_mask       = 1 << AT91SAM9261_ID_SSC1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc2_clk = {
-        .name           = "ssc2_clk",
-        .pmc_mask       = 1 << AT91SAM9261_ID_SSC2,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc0_clk = {
-        .name           = "tc0_clk",
-        .pmc_mask       = 1 << AT91SAM9261_ID_TC0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc1_clk = {
-        .name           = "tc1_clk",
-        .pmc_mask       = 1 << AT91SAM9261_ID_TC1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc2_clk = {
-        .name           = "tc2_clk",
-        .pmc_mask       = 1 << AT91SAM9261_ID_TC2,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ohci_clk = {
-        .name           = "ohci_clk",
-        .pmc_mask       = 1 << AT91SAM9261_ID_UHP,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk lcdc_clk = {
-        .name           = "lcdc_clk",
-        .pmc_mask       = 1 << AT91SAM9261_ID_LCDC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-/* HClocks */
-static struct clk hck0 = {
-        .name           = "hck0",
-        .pmc_mask       = AT91_PMC_HCK0,
-        .type           = CLK_TYPE_SYSTEM,
-        .id             = 0,
-};
-static struct clk hck1 = {
-        .name           = "hck1",
-        .pmc_mask       = AT91_PMC_HCK1,
-        .type           = CLK_TYPE_SYSTEM,
-        .id             = 1,
-};
-static struct clk *periph_clocks[] __initdata = {
-        &pioA_clk,
-        &pioB_clk,
-        &pioC_clk,
-        &usart0_clk,
-        &usart1_clk,
-        &usart2_clk,
-        &mmc_clk,
-        &udc_clk,
-        &twi_clk,
-        &spi0_clk,
-        &spi1_clk,
-        &ssc0_clk,
-        &ssc1_clk,
-        &ssc2_clk,
-        &tc0_clk,
-        &tc1_clk,
-        &tc2_clk,
-        &ohci_clk,
-        &lcdc_clk,
-        // irq0 .. irq2
-};
-static struct clk_lookup periph_clocks_lookups[] = {
-        CLKDEV_CON_DEV_ID("hclk", "at91sam9261-lcdfb.0", &hck1),
-        CLKDEV_CON_DEV_ID("hclk", "at91sam9g10-lcdfb.0", &hck1),
-        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
-        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
-        CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
-        CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
-        CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
-        CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
-        CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
-        CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc0_clk),
-        CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc1_clk),
-        CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc2_clk),
-        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
-        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261.0", &twi_clk),
-        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi_clk),
-        CLKDEV_CON_ID("pioA", &pioA_clk),
-        CLKDEV_CON_ID("pioB", &pioB_clk),
-        CLKDEV_CON_ID("pioC", &pioC_clk),
-        /* more lookup table for DT entries */
-        CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
-        CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
-        CLKDEV_CON_DEV_ID("usart", "ffffb400.serial", &usart1_clk),
-        CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
-        CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
-        CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
-        CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
-        CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &hck0),
-        CLKDEV_CON_DEV_ID("hclk", "600000.fb", &hck1),
-        CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
-};
-static struct clk_lookup usart_clocks_lookups[] = {
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
-};
-/*
- * The four programmable clocks.
- * You must configure pin multiplexing to bring these signals out.
- */
-static struct clk pck0 = {
-        .name           = "pck0",
-        .pmc_mask       = AT91_PMC_PCK0,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 0,
-};
-static struct clk pck1 = {
-        .name           = "pck1",
-        .pmc_mask       = AT91_PMC_PCK1,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 1,
-};
-static struct clk pck2 = {
-        .name           = "pck2",
-        .pmc_mask       = AT91_PMC_PCK2,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 2,
-};
-static struct clk pck3 = {
-        .name           = "pck3",
-        .pmc_mask       = AT91_PMC_PCK3,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 3,
-};
-static void __init at91sam9261_register_clocks(void)
-{
-        int i;
-        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
-                clk_register(periph_clocks[i]);
-        clkdev_add_table(periph_clocks_lookups,
-                         ARRAY_SIZE(periph_clocks_lookups));
-        clkdev_add_table(usart_clocks_lookups,
-                         ARRAY_SIZE(usart_clocks_lookups));
-        clk_register(&pck0);
-        clk_register(&pck1);
-        clk_register(&pck2);
-        clk_register(&pck3);
-        clk_register(&hck0);
-        clk_register(&hck1);
-}
-#else
-#define at91sam9261_register_clocks NULL
-#endif
-/* --------------------------------------------------------------------
- *  GPIO
- * -------------------------------------------------------------------- */
-static struct at91_gpio_bank at91sam9261_gpio[] __initdata = {
-        {
-                .id             = AT91SAM9261_ID_PIOA,
-                .regbase        = AT91SAM9261_BASE_PIOA,
-        }, {
-                .id             = AT91SAM9261_ID_PIOB,
-                .regbase        = AT91SAM9261_BASE_PIOB,
-        }, {
-                .id             = AT91SAM9261_ID_PIOC,
-                .regbase        = AT91SAM9261_BASE_PIOC,
-        }
-};
 /* --------------------------------------------------------------------
 *  AT91SAM9261 processor initialization
@@ -299,119 +29,14 @@ static void __init at91sam9261_map_io(void)
                at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
 }
-static void __init at91sam9261_ioremap_registers(void)
-{
-        at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
-        at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
-        at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
-        at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
-        at91_pm_set_standby(at91sam9_sdram_standby);
-}
 static void __init at91sam9261_initialize(void)
 {
        arm_pm_idle = at91sam9_idle;
        at91_sysirq_mask_rtt(AT91SAM9261_BASE_RTT);
-        /* Register GPIO subsystem */
-        at91_gpio_init(at91sam9261_gpio, 3);
-}
-static struct resource rstc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9261_BASE_RSTC,
-                .end    = AT91SAM9261_BASE_RSTC + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91SAM9261_BASE_SDRAMC,
-                .end    = AT91SAM9261_BASE_SDRAMC + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device rstc_device = {
-        .name           = "at91-sam9260-reset",
-        .resource       = rstc_resources,
-        .num_resources  = ARRAY_SIZE(rstc_resources),
-};
-static struct resource shdwc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9261_BASE_SHDWC,
-                .end    = AT91SAM9261_BASE_SHDWC + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device shdwc_device = {
-        .name           = "at91-poweroff",
-        .resource       = shdwc_resources,
-        .num_resources  = ARRAY_SIZE(shdwc_resources),
-};
-static void __init at91sam9261_register_devices(void)
-{
-        platform_device_register(&rstc_device);
-        platform_device_register(&shdwc_device);
-}
-/* --------------------------------------------------------------------
- *  Interrupt initialization
- * -------------------------------------------------------------------- */
-/*
- * The default interrupt priority levels (0 = lowest, 7 = highest).
- */
-static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
-        7,      /* Advanced Interrupt Controller */
-        7,      /* System Peripherals */
-        1,      /* Parallel IO Controller A */
-        1,      /* Parallel IO Controller B */
-        1,      /* Parallel IO Controller C */
-        0,
-        5,      /* USART 0 */
-        5,      /* USART 1 */
-        5,      /* USART 2 */
-        0,      /* Multimedia Card Interface */
-        2,      /* USB Device Port */
-        6,      /* Two-Wire Interface */
-        5,      /* Serial Peripheral Interface 0 */
-        5,      /* Serial Peripheral Interface 1 */
-        4,      /* Serial Synchronous Controller 0 */
-        4,      /* Serial Synchronous Controller 1 */
-        4,      /* Serial Synchronous Controller 2 */
-        0,      /* Timer Counter 0 */
-        0,      /* Timer Counter 1 */
-        0,      /* Timer Counter 2 */
-        2,      /* USB Host port */
-        3,      /* LCD Controller */
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,      /* Advanced Interrupt Controller */
-        0,      /* Advanced Interrupt Controller */
-        0,      /* Advanced Interrupt Controller */
-};
-static void __init at91sam9261_init_time(void)
-{
-        at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
 }
 AT91_SOC_START(at91sam9261)
        .map_io = at91sam9261_map_io,
-        .default_irq_priority = at91sam9261_default_irq_priority,
-        .extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
-                    | (1 << AT91SAM9261_ID_IRQ2),
-        .ioremap_registers = at91sam9261_ioremap_registers,
-        .register_clocks = at91sam9261_register_clocks,
-        .register_devices = at91sam9261_register_devices,
        .init = at91sam9261_initialize,
-        .init_time = at91sam9261_init_time,
 AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
deleted file mode 100644
index 29baacb5c359..000000000000
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ /dev/null
@@ -1,1098 +0,0 @@
-/*
- * arch/arm/mach-at91/at91sam9261_devices.c
- *
- *  Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
- *  Copyright (C) 2005 David Brownell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/i2c-gpio.h>
-#include <linux/fb.h>
-#include <video/atmel_lcdc.h>
-#include <mach/at91sam9261.h>
-#include <mach/at91sam9261_matrix.h>
-#include <mach/at91_matrix.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/hardware.h>
-#include "board.h"
-#include "generic.h"
-#include "gpio.h"
-/* --------------------------------------------------------------------
- *  USB Host
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static u64 ohci_dmamask = DMA_BIT_MASK(32);
-static struct at91_usbh_data usbh_data;
-static struct resource usbh_resources[] = {
-        [0] = {
-                .start  = AT91SAM9261_UHP_BASE,
-                .end    = AT91SAM9261_UHP_BASE + SZ_1M - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_UHP,
-                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_UHP,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9261_usbh_device = {
-        .name           = "at91_ohci",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &ohci_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &usbh_data,
-        },
-        .resource       = usbh_resources,
-        .num_resources  = ARRAY_SIZE(usbh_resources),
-};
-void __init at91_add_device_usbh(struct at91_usbh_data *data)
-{
-        int i;
-        if (!data)
-                return;
-        /* Enable overcurrent notification */
-        for (i = 0; i < data->ports; i++) {
-                if (gpio_is_valid(data->overcurrent_pin[i]))
-                        at91_set_gpio_input(data->overcurrent_pin[i], 1);
-        }
-        usbh_data = *data;
-        platform_device_register(&at91sam9261_usbh_device);
-}
-#else
-void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  USB Device (Gadget)
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
-static struct at91_udc_data udc_data;
-static struct resource udc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9261_BASE_UDP,
-                .end    = AT91SAM9261_BASE_UDP + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_UDP,
-                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_UDP,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9261_udc_device = {
-        .name           = "at91_udc",
-        .id             = -1,
-        .dev            = {
-                                .platform_data          = &udc_data,
-        },
-        .resource       = udc_resources,
-        .num_resources  = ARRAY_SIZE(udc_resources),
-};
-void __init at91_add_device_udc(struct at91_udc_data *data)
-{
-        if (!data)
-                return;
-        if (gpio_is_valid(data->vbus_pin)) {
-                at91_set_gpio_input(data->vbus_pin, 0);
-                at91_set_deglitch(data->vbus_pin, 1);
-        }
-        /* Pullup pin is handled internally by USB device peripheral */
-        udc_data = *data;
-        platform_device_register(&at91sam9261_udc_device);
-}
-#else
-void __init at91_add_device_udc(struct at91_udc_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  MMC / SD
- * -------------------------------------------------------------------- */
-#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
-static u64 mmc_dmamask = DMA_BIT_MASK(32);
-static struct mci_platform_data mmc_data;
-static struct resource mmc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9261_BASE_MCI,
-                .end    = AT91SAM9261_BASE_MCI + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_MCI,
-                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_MCI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9261_mmc_device = {
-        .name           = "atmel_mci",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &mmc_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &mmc_data,
-        },
-        .resource       = mmc_resources,
-        .num_resources  = ARRAY_SIZE(mmc_resources),
-};
-void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
-{
-        if (!data)
-                return;
-        if (data->slot[0].bus_width) {
-                /* input/irq */
-                if (gpio_is_valid(data->slot[0].detect_pin)) {
-                        at91_set_gpio_input(data->slot[0].detect_pin, 1);
-                        at91_set_deglitch(data->slot[0].detect_pin, 1);
-                }
-                if (gpio_is_valid(data->slot[0].wp_pin))
-                        at91_set_gpio_input(data->slot[0].wp_pin, 1);
-                /* CLK */
-                at91_set_B_periph(AT91_PIN_PA2, 0);
-                /* CMD */
-                at91_set_B_periph(AT91_PIN_PA1, 1);
-                /* DAT0, maybe DAT1..DAT3 */
-                at91_set_B_periph(AT91_PIN_PA0, 1);
-                if (data->slot[0].bus_width == 4) {
-                        at91_set_B_periph(AT91_PIN_PA4, 1);
-                        at91_set_B_periph(AT91_PIN_PA5, 1);
-                        at91_set_B_periph(AT91_PIN_PA6, 1);
-                }
-                mmc_data = *data;
-                platform_device_register(&at91sam9261_mmc_device);
-        }
-}
-#else
-void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  NAND / SmartMedia
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
-static struct atmel_nand_data nand_data;
-#define NAND_BASE       AT91_CHIPSELECT_3
-static struct resource nand_resources[] = {
-        {
-                .start  = NAND_BASE,
-                .end    = NAND_BASE + SZ_256M - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct platform_device atmel_nand_device = {
-        .name           = "atmel_nand",
-        .id             = -1,
-        .dev            = {
-                                .platform_data  = &nand_data,
-        },
-        .resource       = nand_resources,
-        .num_resources  = ARRAY_SIZE(nand_resources),
-};
-void __init at91_add_device_nand(struct atmel_nand_data *data)
-{
-        unsigned long csa;
-        if (!data)
-                return;
-        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
-        at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
-        /* enable pin */
-        if (gpio_is_valid(data->enable_pin))
-                at91_set_gpio_output(data->enable_pin, 1);
-        /* ready/busy pin */
-        if (gpio_is_valid(data->rdy_pin))
-                at91_set_gpio_input(data->rdy_pin, 1);
-        /* card detect pin */
-        if (gpio_is_valid(data->det_pin))
-                at91_set_gpio_input(data->det_pin, 1);
-        at91_set_A_periph(AT91_PIN_PC0, 0);             /* NANDOE */
-        at91_set_A_periph(AT91_PIN_PC1, 0);             /* NANDWE */
-        nand_data = *data;
-        platform_device_register(&atmel_nand_device);
-}
-#else
-void __init at91_add_device_nand(struct atmel_nand_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  TWI (i2c)
- * -------------------------------------------------------------------- */
-/*
- * Prefer the GPIO code since the TWI controller isn't robust
- * (gets overruns and underruns under load) and can only issue
- * repeated STARTs in one scenario (the driver doesn't yet handle them).
- */
-#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
-static struct i2c_gpio_platform_data pdata = {
-        .sda_pin                = AT91_PIN_PA7,
-        .sda_is_open_drain      = 1,
-        .scl_pin                = AT91_PIN_PA8,
-        .scl_is_open_drain      = 1,
-        .udelay                 = 2,            /* ~100 kHz */
-};
-static struct platform_device at91sam9261_twi_device = {
-        .name                   = "i2c-gpio",
-        .id                     = 0,
-        .dev.platform_data      = &pdata,
-};
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
-{
-        at91_set_GPIO_periph(AT91_PIN_PA7, 1);          /* TWD (SDA) */
-        at91_set_multi_drive(AT91_PIN_PA7, 1);
-        at91_set_GPIO_periph(AT91_PIN_PA8, 1);          /* TWCK (SCL) */
-        at91_set_multi_drive(AT91_PIN_PA8, 1);
-        i2c_register_board_info(0, devices, nr_devices);
-        platform_device_register(&at91sam9261_twi_device);
-}
-#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
-static struct resource twi_resources[] = {
-        [0] = {
-                .start  = AT91SAM9261_BASE_TWI,
-                .end    = AT91SAM9261_BASE_TWI + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_TWI,
-                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_TWI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9261_twi_device = {
-        .id             = 0,
-        .resource       = twi_resources,
-        .num_resources  = ARRAY_SIZE(twi_resources),
-};
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
-{
-        /* IP version is not the same on 9261 and g10 */
-        if (cpu_is_at91sam9g10()) {
-                at91sam9261_twi_device.name = "i2c-at91sam9g10";
-                /* I2C PIO must not be configured as open-drain on this chip */
-        } else {
-                at91sam9261_twi_device.name = "i2c-at91sam9261";
-                at91_set_multi_drive(AT91_PIN_PA7, 1);
-                at91_set_multi_drive(AT91_PIN_PA8, 1);
-        }
-        /* pins used for TWI interface */
-        at91_set_A_periph(AT91_PIN_PA7, 0);             /* TWD */
-        at91_set_A_periph(AT91_PIN_PA8, 0);             /* TWCK */
-        i2c_register_board_info(0, devices, nr_devices);
-        platform_device_register(&at91sam9261_twi_device);
-}
-#else
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
-#endif
-/* --------------------------------------------------------------------
- *  SPI
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
-static u64 spi_dmamask = DMA_BIT_MASK(32);
-static struct resource spi0_resources[] = {
-        [0] = {
-                .start  = AT91SAM9261_BASE_SPI0,
-                .end    = AT91SAM9261_BASE_SPI0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI0,
-                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9261_spi0_device = {
-        .name           = "atmel_spi",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &spi_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = spi0_resources,
-        .num_resources  = ARRAY_SIZE(spi0_resources),
-};
-static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
-static struct resource spi1_resources[] = {
-        [0] = {
-                .start  = AT91SAM9261_BASE_SPI1,
-                .end    = AT91SAM9261_BASE_SPI1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI1,
-                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9261_spi1_device = {
-        .name           = "atmel_spi",
-        .id             = 1,
-        .dev            = {
-                                .dma_mask               = &spi_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = spi1_resources,
-        .num_resources  = ARRAY_SIZE(spi1_resources),
-};
-static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB28, AT91_PIN_PA24, AT91_PIN_PA25, AT91_PIN_PA26 };
-void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
-{
-        int i;
-        unsigned long cs_pin;
-        short enable_spi0 = 0;
-        short enable_spi1 = 0;
-        /* Choose SPI chip-selects */
-        for (i = 0; i < nr_devices; i++) {
-                if (devices[i].controller_data)
-                        cs_pin = (unsigned long) devices[i].controller_data;
-                else if (devices[i].bus_num == 0)
-                        cs_pin = spi0_standard_cs[devices[i].chip_select];
-                else
-                        cs_pin = spi1_standard_cs[devices[i].chip_select];
-                if (!gpio_is_valid(cs_pin))
-                        continue;
-                if (devices[i].bus_num == 0)
-                        enable_spi0 = 1;
-                else
-                        enable_spi1 = 1;
-                /* enable chip-select pin */
-                at91_set_gpio_output(cs_pin, 1);
-                /* pass chip-select pin to driver */
-                devices[i].controller_data = (void *) cs_pin;
-        }
-        spi_register_board_info(devices, nr_devices);
-        /* Configure SPI bus(es) */
-        if (enable_spi0) {
-                at91_set_A_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
-                at91_set_A_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
-                at91_set_A_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
-                platform_device_register(&at91sam9261_spi0_device);
-        }
-        if (enable_spi1) {
-                at91_set_A_periph(AT91_PIN_PB30, 0);    /* SPI1_MISO */
-                at91_set_A_periph(AT91_PIN_PB31, 0);    /* SPI1_MOSI */
-                at91_set_A_periph(AT91_PIN_PB29, 0);    /* SPI1_SPCK */
-                platform_device_register(&at91sam9261_spi1_device);
-        }
-}
-#else
-void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
-#endif
-/* --------------------------------------------------------------------
- *  LCD Controller
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
-static u64 lcdc_dmamask = DMA_BIT_MASK(32);
-static struct atmel_lcdfb_pdata lcdc_data;
-static struct resource lcdc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9261_LCDC_BASE,
-                .end    = AT91SAM9261_LCDC_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_LCDC,
-                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_LCDC,
-                .flags  = IORESOURCE_IRQ,
-        },
-#if defined(CONFIG_FB_INTSRAM)
-        [2] = {
-                .start  = AT91SAM9261_SRAM_BASE,
-                .end    = AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-#endif
-};
-static struct platform_device at91_lcdc_device = {
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &lcdc_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &lcdc_data,
-        },
-        .resource       = lcdc_resources,
-        .num_resources  = ARRAY_SIZE(lcdc_resources),
-};
-void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data)
-{
-        if (!data) {
-                return;
-        }
-        if (cpu_is_at91sam9g10())
-                at91_lcdc_device.name = "at91sam9g10-lcdfb";
-        else
-                at91_lcdc_device.name = "at91sam9261-lcdfb";
-#if defined(CONFIG_FB_ATMEL_STN)
-        at91_set_A_periph(AT91_PIN_PB0, 0);     /* LCDVSYNC */
-        at91_set_A_periph(AT91_PIN_PB1, 0);     /* LCDHSYNC */
-        at91_set_A_periph(AT91_PIN_PB2, 0);     /* LCDDOTCK */
-        at91_set_A_periph(AT91_PIN_PB3, 0);     /* LCDDEN */
-        at91_set_A_periph(AT91_PIN_PB4, 0);     /* LCDCC */
-        at91_set_A_periph(AT91_PIN_PB5, 0);     /* LCDD0 */
-        at91_set_A_periph(AT91_PIN_PB6, 0);     /* LCDD1 */
-        at91_set_A_periph(AT91_PIN_PB7, 0);     /* LCDD2 */
-        at91_set_A_periph(AT91_PIN_PB8, 0);     /* LCDD3 */
-#else
-        at91_set_A_periph(AT91_PIN_PB1, 0);     /* LCDHSYNC */
-        at91_set_A_periph(AT91_PIN_PB2, 0);     /* LCDDOTCK */
-        at91_set_A_periph(AT91_PIN_PB3, 0);     /* LCDDEN */
-        at91_set_A_periph(AT91_PIN_PB4, 0);     /* LCDCC */
-        at91_set_A_periph(AT91_PIN_PB7, 0);     /* LCDD2 */
-        at91_set_A_periph(AT91_PIN_PB8, 0);     /* LCDD3 */
-        at91_set_A_periph(AT91_PIN_PB9, 0);     /* LCDD4 */
-        at91_set_A_periph(AT91_PIN_PB10, 0);    /* LCDD5 */
-        at91_set_A_periph(AT91_PIN_PB11, 0);    /* LCDD6 */
-        at91_set_A_periph(AT91_PIN_PB12, 0);    /* LCDD7 */
-        at91_set_A_periph(AT91_PIN_PB15, 0);    /* LCDD10 */
-        at91_set_A_periph(AT91_PIN_PB16, 0);    /* LCDD11 */
-        at91_set_A_periph(AT91_PIN_PB17, 0);    /* LCDD12 */
-        at91_set_A_periph(AT91_PIN_PB18, 0);    /* LCDD13 */
-        at91_set_A_periph(AT91_PIN_PB19, 0);    /* LCDD14 */
-        at91_set_A_periph(AT91_PIN_PB20, 0);    /* LCDD15 */
-        at91_set_B_periph(AT91_PIN_PB23, 0);    /* LCDD18 */
-        at91_set_B_periph(AT91_PIN_PB24, 0);    /* LCDD19 */
-        at91_set_B_periph(AT91_PIN_PB25, 0);    /* LCDD20 */
-        at91_set_B_periph(AT91_PIN_PB26, 0);    /* LCDD21 */
-        at91_set_B_periph(AT91_PIN_PB27, 0);    /* LCDD22 */
-        at91_set_B_periph(AT91_PIN_PB28, 0);    /* LCDD23 */
-#endif
-        if (ARRAY_SIZE(lcdc_resources) > 2) {
-                void __iomem *fb;
-                struct resource *fb_res = &lcdc_resources[2];
-                size_t fb_len = resource_size(fb_res);
-                fb = ioremap(fb_res->start, fb_len);
-                if (fb) {
-                        memset(fb, 0, fb_len);
-                        iounmap(fb);
-                }
-        }
-        lcdc_data = *data;
-        platform_device_register(&at91_lcdc_device);
-}
-#else
-void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  Timer/Counter block
- * -------------------------------------------------------------------- */
-#ifdef CONFIG_ATMEL_TCLIB
-static struct resource tcb_resources[] = {
-        [0] = {
-                .start  = AT91SAM9261_BASE_TCB0,
-                .end    = AT91SAM9261_BASE_TCB0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_TC0,
-                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_TC0,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_TC1,
-                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_TC1,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_TC2,
-                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_TC2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9261_tcb_device = {
-        .name           = "atmel_tcb",
-        .id             = 0,
-        .resource       = tcb_resources,
-        .num_resources  = ARRAY_SIZE(tcb_resources),
-};
-static void __init at91_add_device_tc(void)
-{
-        platform_device_register(&at91sam9261_tcb_device);
-}
-#else
-static void __init at91_add_device_tc(void) { }
-#endif
-/* --------------------------------------------------------------------
- *  RTT
- * -------------------------------------------------------------------- */
-static struct resource rtt_resources[] = {
-        {
-                .start  = AT91SAM9261_BASE_RTT,
-                .end    = AT91SAM9261_BASE_RTT + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-static struct platform_device at91sam9261_rtt_device = {
-        .name           = "at91_rtt",
-        .id             = 0,
-        .resource       = rtt_resources,
-};
-#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
-static void __init at91_add_device_rtt_rtc(void)
-{
-        at91sam9261_rtt_device.name = "rtc-at91sam9";
-        /*
-         * The second resource is needed:
-         * GPBR will serve as the storage for RTC time offset
-         */
-        at91sam9261_rtt_device.num_resources = 3;
-        rtt_resources[1].start = AT91SAM9261_BASE_GPBR +
-                                 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
-        rtt_resources[1].end = rtt_resources[1].start + 3;
-        rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
-        rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
-}
-#else
-static void __init at91_add_device_rtt_rtc(void)
-{
-        /* Only one resource is needed: RTT not used as RTC */
-        at91sam9261_rtt_device.num_resources = 1;
-}
-#endif
-static void __init at91_add_device_rtt(void)
-{
-        at91_add_device_rtt_rtc();
-        platform_device_register(&at91sam9261_rtt_device);
-}
-/* --------------------------------------------------------------------
- *  Watchdog
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
-static struct resource wdt_resources[] = {
-        {
-                .start  = AT91SAM9261_BASE_WDT,
-                .end    = AT91SAM9261_BASE_WDT + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct platform_device at91sam9261_wdt_device = {
-        .name           = "at91_wdt",
-        .id             = -1,
-        .resource       = wdt_resources,
-        .num_resources  = ARRAY_SIZE(wdt_resources),
-};
-static void __init at91_add_device_watchdog(void)
-{
-        platform_device_register(&at91sam9261_wdt_device);
-}
-#else
-static void __init at91_add_device_watchdog(void) {}
-#endif
-/* --------------------------------------------------------------------
- *  SSC -- Synchronous Serial Controller
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
-static u64 ssc0_dmamask = DMA_BIT_MASK(32);
-static struct resource ssc0_resources[] = {
-        [0] = {
-                .start  = AT91SAM9261_BASE_SSC0,
-                .end    = AT91SAM9261_BASE_SSC0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC0,
-                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9261_ssc0_device = {
-        .name   = "at91rm9200_ssc",
-        .id     = 0,
-        .dev    = {
-                .dma_mask               = &ssc0_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = ssc0_resources,
-        .num_resources  = ARRAY_SIZE(ssc0_resources),
-};
-static inline void configure_ssc0_pins(unsigned pins)
-{
-        if (pins & ATMEL_SSC_TF)
-                at91_set_A_periph(AT91_PIN_PB21, 1);
-        if (pins & ATMEL_SSC_TK)
-                at91_set_A_periph(AT91_PIN_PB22, 1);
-        if (pins & ATMEL_SSC_TD)
-                at91_set_A_periph(AT91_PIN_PB23, 1);
-        if (pins & ATMEL_SSC_RD)
-                at91_set_A_periph(AT91_PIN_PB24, 1);
-        if (pins & ATMEL_SSC_RK)
-                at91_set_A_periph(AT91_PIN_PB25, 1);
-        if (pins & ATMEL_SSC_RF)
-                at91_set_A_periph(AT91_PIN_PB26, 1);
-}
-static u64 ssc1_dmamask = DMA_BIT_MASK(32);
-static struct resource ssc1_resources[] = {
-        [0] = {
-                .start  = AT91SAM9261_BASE_SSC1,
-                .end    = AT91SAM9261_BASE_SSC1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC1,
-                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9261_ssc1_device = {
-        .name   = "at91rm9200_ssc",
-        .id     = 1,
-        .dev    = {
-                .dma_mask               = &ssc1_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = ssc1_resources,
-        .num_resources  = ARRAY_SIZE(ssc1_resources),
-};
-static inline void configure_ssc1_pins(unsigned pins)
-{
-        if (pins & ATMEL_SSC_TF)
-                at91_set_B_periph(AT91_PIN_PA17, 1);
-        if (pins & ATMEL_SSC_TK)
-                at91_set_B_periph(AT91_PIN_PA18, 1);
-        if (pins & ATMEL_SSC_TD)
-                at91_set_B_periph(AT91_PIN_PA19, 1);
-        if (pins & ATMEL_SSC_RD)
-                at91_set_B_periph(AT91_PIN_PA20, 1);
-        if (pins & ATMEL_SSC_RK)
-                at91_set_B_periph(AT91_PIN_PA21, 1);
-        if (pins & ATMEL_SSC_RF)
-                at91_set_B_periph(AT91_PIN_PA22, 1);
-}
-static u64 ssc2_dmamask = DMA_BIT_MASK(32);
-static struct resource ssc2_resources[] = {
-        [0] = {
-                .start  = AT91SAM9261_BASE_SSC2,
-                .end    = AT91SAM9261_BASE_SSC2 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC2,
-                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9261_ssc2_device = {
-        .name   = "at91rm9200_ssc",
-        .id     = 2,
-        .dev    = {
-                .dma_mask               = &ssc2_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = ssc2_resources,
-        .num_resources  = ARRAY_SIZE(ssc2_resources),
-};
-static inline void configure_ssc2_pins(unsigned pins)
-{
-        if (pins & ATMEL_SSC_TF)
-                at91_set_B_periph(AT91_PIN_PC25, 1);
-        if (pins & ATMEL_SSC_TK)
-                at91_set_B_periph(AT91_PIN_PC26, 1);
-        if (pins & ATMEL_SSC_TD)
-                at91_set_B_periph(AT91_PIN_PC27, 1);
-        if (pins & ATMEL_SSC_RD)
-                at91_set_B_periph(AT91_PIN_PC28, 1);
-        if (pins & ATMEL_SSC_RK)
-                at91_set_B_periph(AT91_PIN_PC29, 1);
-        if (pins & ATMEL_SSC_RF)
-                at91_set_B_periph(AT91_PIN_PC30, 1);
-}
-/*
- * SSC controllers are accessed through library code, instead of any
- * kind of all-singing/all-dancing driver.  For example one could be
- * used by a particular I2S audio codec's driver, while another one
- * on the same system might be used by a custom data capture driver.
- */
-void __init at91_add_device_ssc(unsigned id, unsigned pins)
-{
-        struct platform_device *pdev;
-        /*
-         * NOTE: caller is responsible for passing information matching
-         * "pins" to whatever will be using each particular controller.
-         */
-        switch (id) {
-        case AT91SAM9261_ID_SSC0:
-                pdev = &at91sam9261_ssc0_device;
-                configure_ssc0_pins(pins);
-                break;
-        case AT91SAM9261_ID_SSC1:
-                pdev = &at91sam9261_ssc1_device;
-                configure_ssc1_pins(pins);
-                break;
-        case AT91SAM9261_ID_SSC2:
-                pdev = &at91sam9261_ssc2_device;
-                configure_ssc2_pins(pins);
-                break;
-        default:
-                return;
-        }
-        platform_device_register(pdev);
-}
-#else
-void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
-#endif
-/* --------------------------------------------------------------------
- *  UART
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_SERIAL_ATMEL)
-static struct resource dbgu_resources[] = {
-        [0] = {
-                .start  = AT91SAM9261_BASE_DBGU,
-                .end    = AT91SAM9261_BASE_DBGU + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
-                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data dbgu_data = {
-        .use_dma_tx     = 0,
-        .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
-};
-static u64 dbgu_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9261_dbgu_device = {
-        .name           = "atmel_usart",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &dbgu_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &dbgu_data,
-        },
-        .resource       = dbgu_resources,
-        .num_resources  = ARRAY_SIZE(dbgu_resources),
-};
-static inline void configure_dbgu_pins(void)
-{
-        at91_set_A_periph(AT91_PIN_PA9, 0);             /* DRXD */
-        at91_set_A_periph(AT91_PIN_PA10, 1);            /* DTXD */
-}
-static struct resource uart0_resources[] = {
-        [0] = {
-                .start  = AT91SAM9261_BASE_US0,
-                .end    = AT91SAM9261_BASE_US0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_US0,
-                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_US0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart0_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static u64 uart0_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9261_uart0_device = {
-        .name           = "atmel_usart",
-        .id             = 1,
-        .dev            = {
-                                .dma_mask               = &uart0_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart0_data,
-        },
-        .resource       = uart0_resources,
-        .num_resources  = ARRAY_SIZE(uart0_resources),
-};
-static inline void configure_usart0_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PC8, 1);             /* TXD0 */
-        at91_set_A_periph(AT91_PIN_PC9, 0);             /* RXD0 */
-        if (pins & ATMEL_UART_RTS)
-                at91_set_A_periph(AT91_PIN_PC10, 0);    /* RTS0 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_A_periph(AT91_PIN_PC11, 0);    /* CTS0 */
-}
-static struct resource uart1_resources[] = {
-        [0] = {
-                .start  = AT91SAM9261_BASE_US1,
-                .end    = AT91SAM9261_BASE_US1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_US1,
-                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_US1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart1_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static u64 uart1_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9261_uart1_device = {
-        .name           = "atmel_usart",
-        .id             = 2,
-        .dev            = {
-                                .dma_mask               = &uart1_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart1_data,
-        },
-        .resource       = uart1_resources,
-        .num_resources  = ARRAY_SIZE(uart1_resources),
-};
-static inline void configure_usart1_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PC12, 1);            /* TXD1 */
-        at91_set_A_periph(AT91_PIN_PC13, 0);            /* RXD1 */
-        if (pins & ATMEL_UART_RTS)
-                at91_set_B_periph(AT91_PIN_PA12, 0);    /* RTS1 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_B_periph(AT91_PIN_PA13, 0);    /* CTS1 */
-}
-static struct resource uart2_resources[] = {
-        [0] = {
-                .start  = AT91SAM9261_BASE_US2,
-                .end    = AT91SAM9261_BASE_US2 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_US2,
-                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_US2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart2_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static u64 uart2_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9261_uart2_device = {
-        .name           = "atmel_usart",
-        .id             = 3,
-        .dev            = {
-                                .dma_mask               = &uart2_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart2_data,
-        },
-        .resource       = uart2_resources,
-        .num_resources  = ARRAY_SIZE(uart2_resources),
-};
-static inline void configure_usart2_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PC15, 0);            /* RXD2 */
-        at91_set_A_periph(AT91_PIN_PC14, 1);            /* TXD2 */
-        if (pins & ATMEL_UART_RTS)
-                at91_set_B_periph(AT91_PIN_PA15, 0);    /* RTS2*/
-        if (pins & ATMEL_UART_CTS)
-                at91_set_B_periph(AT91_PIN_PA16, 0);    /* CTS2 */
-}
-static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
-{
-        struct platform_device *pdev;
-        struct atmel_uart_data *pdata;
-        switch (id) {
-                case 0:         /* DBGU */
-                        pdev = &at91sam9261_dbgu_device;
-                        configure_dbgu_pins();
-                        break;
-                case AT91SAM9261_ID_US0:
-                        pdev = &at91sam9261_uart0_device;
-                        configure_usart0_pins(pins);
-                        break;
-                case AT91SAM9261_ID_US1:
-                        pdev = &at91sam9261_uart1_device;
-                        configure_usart1_pins(pins);
-                        break;
-                case AT91SAM9261_ID_US2:
-                        pdev = &at91sam9261_uart2_device;
-                        configure_usart2_pins(pins);
-                        break;
-                default:
-                        return;
-        }
-        pdata = pdev->dev.platform_data;
-        pdata->num = portnr;            /* update to mapped ID */
-        if (portnr < ATMEL_MAX_UART)
-                at91_uarts[portnr] = pdev;
-}
-void __init at91_add_device_serial(void)
-{
-        int i;
-        for (i = 0; i < ATMEL_MAX_UART; i++) {
-                if (at91_uarts[i])
-                        platform_device_register(at91_uarts[i]);
-        }
-}
-#else
-void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
-void __init at91_add_device_serial(void) {}
-#endif
-/* -------------------------------------------------------------------- */
-/*
- * These devices are always present and don't need any board-specific
- * setup.
- */
-static int __init at91_add_standard_devices(void)
-{
-        at91_add_device_rtt();
-        at91_add_device_watchdog();
-        at91_add_device_tc();
-        return 0;
-}
-arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index fbff228cc63e..e7ad14864083 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -10,304 +10,11 @@
 *
 */
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/clk/at91_pmc.h>
-#include <asm/proc-fns.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
 #include <asm/system_misc.h>
-#include <mach/at91sam9263.h>
 #include <mach/hardware.h>
-#include "at91_aic.h"
 #include "soc.h"
 #include "generic.h"
-#include "sam9_smc.h"
-#include "pm.h"
-#if defined(CONFIG_OLD_CLK_AT91)
-#include "clock.h"
-/* --------------------------------------------------------------------
- *  Clocks
- * -------------------------------------------------------------------- */
-/*
- * The peripheral clocks.
- */
-static struct clk pioA_clk = {
-        .name           = "pioA_clk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_PIOA,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
-        .name           = "pioB_clk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_PIOB,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioCDE_clk = {
-        .name           = "pioCDE_clk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_PIOCDE,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
-        .name           = "usart0_clk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_US0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
-        .name           = "usart1_clk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_US1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
-        .name           = "usart2_clk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_US2,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc0_clk = {
-        .name           = "mci0_clk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_MCI0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc1_clk = {
-        .name           = "mci1_clk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_MCI1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk can_clk = {
-        .name           = "can_clk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_CAN,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi_clk = {
-        .name           = "twi_clk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_TWI,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
-        .name           = "spi0_clk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_SPI0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
-        .name           = "spi1_clk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_SPI1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
-        .name           = "ssc0_clk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_SSC0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
-        .name           = "ssc1_clk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_SSC1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ac97_clk = {
-        .name           = "ac97_clk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_AC97C,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tcb_clk = {
-        .name           = "tcb_clk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_TCB,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pwm_clk = {
-        .name           = "pwm_clk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_PWMC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk macb_clk = {
-        .name           = "pclk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_EMAC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma_clk = {
-        .name           = "dma_clk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_DMA,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twodge_clk = {
-        .name           = "2dge_clk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_2DGE,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udc_clk = {
-        .name           = "udc_clk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_UDP,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk isi_clk = {
-        .name           = "isi_clk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_ISI,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk lcdc_clk = {
-        .name           = "lcdc_clk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_LCDC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ohci_clk = {
-        .name           = "ohci_clk",
-        .pmc_mask       = 1 << AT91SAM9263_ID_UHP,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk *periph_clocks[] __initdata = {
-        &pioA_clk,
-        &pioB_clk,
-        &pioCDE_clk,
-        &usart0_clk,
-        &usart1_clk,
-        &usart2_clk,
-        &mmc0_clk,
-        &mmc1_clk,
-        &can_clk,
-        &twi_clk,
-        &spi0_clk,
-        &spi1_clk,
-        &ssc0_clk,
-        &ssc1_clk,
-        &ac97_clk,
-        &tcb_clk,
-        &pwm_clk,
-        &macb_clk,
-        &twodge_clk,
-        &udc_clk,
-        &isi_clk,
-        &lcdc_clk,
-        &dma_clk,
-        &ohci_clk,
-        // irq0 .. irq1
-};
-static struct clk_lookup periph_clocks_lookups[] = {
-        /* One additional fake clock for macb_hclk */
-        CLKDEV_CON_ID("hclk", &macb_clk),
-        CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
-        CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
-        CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
-        CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
-        CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
-        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
-        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
-        CLKDEV_CON_DEV_ID(NULL, "at91sam9rl-pwm", &pwm_clk),
-        /* fake hclk clock */
-        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
-        CLKDEV_CON_ID("pioA", &pioA_clk),
-        CLKDEV_CON_ID("pioB", &pioB_clk),
-        CLKDEV_CON_ID("pioC", &pioCDE_clk),
-        CLKDEV_CON_ID("pioD", &pioCDE_clk),
-        CLKDEV_CON_ID("pioE", &pioCDE_clk),
-        /* more usart lookup table for DT entries */
-        CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
-        CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
-        CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
-        CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
-        /* more tc lookup table for DT entries */
-        CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb_clk),
-        CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "fff84000.mmc", &mmc1_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk),
-};
-static struct clk_lookup usart_clocks_lookups[] = {
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
-};
-/*
- * The four programmable clocks.
- * You must configure pin multiplexing to bring these signals out.
- */
-static struct clk pck0 = {
-        .name           = "pck0",
-        .pmc_mask       = AT91_PMC_PCK0,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 0,
-};
-static struct clk pck1 = {
-        .name           = "pck1",
-        .pmc_mask       = AT91_PMC_PCK1,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 1,
-};
-static struct clk pck2 = {
-        .name           = "pck2",
-        .pmc_mask       = AT91_PMC_PCK2,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 2,
-};
-static struct clk pck3 = {
-        .name           = "pck3",
-        .pmc_mask       = AT91_PMC_PCK3,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 3,
-};
-static void __init at91sam9263_register_clocks(void)
-{
-        int i;
-        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
-                clk_register(periph_clocks[i]);
-        clkdev_add_table(periph_clocks_lookups,
-                         ARRAY_SIZE(periph_clocks_lookups));
-        clkdev_add_table(usart_clocks_lookups,
-                         ARRAY_SIZE(usart_clocks_lookups));
-        clk_register(&pck0);
-        clk_register(&pck1);
-        clk_register(&pck2);
-        clk_register(&pck3);
-}
-#else
-#define at91sam9263_register_clocks NULL
-#endif
-/* --------------------------------------------------------------------
- *  GPIO
- * -------------------------------------------------------------------- */
-static struct at91_gpio_bank at91sam9263_gpio[] __initdata = {
-        {
-                .id             = AT91SAM9263_ID_PIOA,
-                .regbase        = AT91SAM9263_BASE_PIOA,
-        }, {
-                .id             = AT91SAM9263_ID_PIOB,
-                .regbase        = AT91SAM9263_BASE_PIOB,
-        }, {
-                .id             = AT91SAM9263_ID_PIOCDE,
-                .regbase        = AT91SAM9263_BASE_PIOC,
-        }, {
-                .id             = AT91SAM9263_ID_PIOCDE,
-                .regbase        = AT91SAM9263_BASE_PIOD,
-        }, {
-                .id             = AT91SAM9263_ID_PIOCDE,
-                .regbase        = AT91SAM9263_BASE_PIOE,
-        }
-};
 /* --------------------------------------------------------------------
 *  AT91SAM9263 processor initialization
@@ -319,121 +26,15 @@ static void __init at91sam9263_map_io(void)
        at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
 }
-static void __init at91sam9263_ioremap_registers(void)
-{
-        at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
-        at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
-        at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
-        at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
-        at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
-        at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
-        at91_pm_set_standby(at91sam9_sdram_standby);
-}
 static void __init at91sam9263_initialize(void)
 {
        arm_pm_idle = at91sam9_idle;
        at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT0);
        at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT1);
-        /* Register GPIO subsystem */
-        at91_gpio_init(at91sam9263_gpio, 5);
-}
-static struct resource rstc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9263_BASE_RSTC,
-                .end    = AT91SAM9263_BASE_RSTC + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91SAM9263_BASE_SDRAMC0,
-                .end    = AT91SAM9263_BASE_SDRAMC0 + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device rstc_device = {
-        .name           = "at91-sam9260-reset",
-        .resource       = rstc_resources,
-        .num_resources  = ARRAY_SIZE(rstc_resources),
-};
-static struct resource shdwc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9263_BASE_SHDWC,
-                .end    = AT91SAM9263_BASE_SHDWC + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device shdwc_device = {
-        .name           = "at91-poweroff",
-        .resource       = shdwc_resources,
-        .num_resources  = ARRAY_SIZE(shdwc_resources),
-};
-static void __init at91sam9263_register_devices(void)
-{
-        platform_device_register(&rstc_device);
-        platform_device_register(&shdwc_device);
-}
-/* --------------------------------------------------------------------
- *  Interrupt initialization
- * -------------------------------------------------------------------- */
-/*
- * The default interrupt priority levels (0 = lowest, 7 = highest).
- */
-static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
-        7,      /* Advanced Interrupt Controller (FIQ) */
-        7,      /* System Peripherals */
-        1,      /* Parallel IO Controller A */
-        1,      /* Parallel IO Controller B */
-        1,      /* Parallel IO Controller C, D and E */
-        0,
-        0,
-        5,      /* USART 0 */
-        5,      /* USART 1 */
-        5,      /* USART 2 */
-        0,      /* Multimedia Card Interface 0 */
-        0,      /* Multimedia Card Interface 1 */
-        3,      /* CAN */
-        6,      /* Two-Wire Interface */
-        5,      /* Serial Peripheral Interface 0 */
-        5,      /* Serial Peripheral Interface 1 */
-        4,      /* Serial Synchronous Controller 0 */
-        4,      /* Serial Synchronous Controller 1 */
-        5,      /* AC97 Controller */
-        0,      /* Timer Counter 0, 1 and 2 */
-        0,      /* Pulse Width Modulation Controller */
-        3,      /* Ethernet */
-        0,
-        0,      /* 2D Graphic Engine */
-        2,      /* USB Device Port */
-        0,      /* Image Sensor Interface */
-        3,      /* LDC Controller */
-        0,      /* DMA Controller */
-        0,
-        2,      /* USB Host port */
-        0,      /* Advanced Interrupt Controller (IRQ0) */
-        0,      /* Advanced Interrupt Controller (IRQ1) */
-};
-static void __init at91sam9263_init_time(void)
-{
-        at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
 }
 AT91_SOC_START(at91sam9263)
        .map_io = at91sam9263_map_io,
-        .default_irq_priority = at91sam9263_default_irq_priority,
-        .extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1),
-        .ioremap_registers = at91sam9263_ioremap_registers,
-        .register_clocks = at91sam9263_register_clocks,
-        .register_devices = at91sam9263_register_devices,
        .init = at91sam9263_initialize,
-        .init_time = at91sam9263_init_time,
 AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
deleted file mode 100644
index cef0e2f57068..000000000000
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ /dev/null
@@ -1,1538 +0,0 @@
-/*
- * arch/arm/mach-at91/at91sam9263_devices.c
- *
- *  Copyright (C) 2007 Atmel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/i2c-gpio.h>
-#include <linux/fb.h>
-#include <video/atmel_lcdc.h>
-#include <mach/at91sam9263.h>
-#include <mach/at91sam9263_matrix.h>
-#include <mach/at91_matrix.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/hardware.h>
-#include "board.h"
-#include "generic.h"
-#include "gpio.h"
-/* --------------------------------------------------------------------
- *  USB Host
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static u64 ohci_dmamask = DMA_BIT_MASK(32);
-static struct at91_usbh_data usbh_data;
-static struct resource usbh_resources[] = {
-        [0] = {
-                .start  = AT91SAM9263_UHP_BASE,
-                .end    = AT91SAM9263_UHP_BASE + SZ_1M - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_UHP,
-                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_UHP,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91_usbh_device = {
-        .name           = "at91_ohci",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &ohci_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &usbh_data,
-        },
-        .resource       = usbh_resources,
-        .num_resources  = ARRAY_SIZE(usbh_resources),
-};
-void __init at91_add_device_usbh(struct at91_usbh_data *data)
-{
-        int i;
-        if (!data)
-                return;
-        /* Enable VBus control for UHP ports */
-        for (i = 0; i < data->ports; i++) {
-                if (gpio_is_valid(data->vbus_pin[i]))
-                        at91_set_gpio_output(data->vbus_pin[i],
-                                             data->vbus_pin_active_low[i]);
-        }
-        /* Enable overcurrent notification */
-        for (i = 0; i < data->ports; i++) {
-                if (gpio_is_valid(data->overcurrent_pin[i]))
-                        at91_set_gpio_input(data->overcurrent_pin[i], 1);
-        }
-        usbh_data = *data;
-        platform_device_register(&at91_usbh_device);
-}
-#else
-void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  USB Device (Gadget)
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
-static struct at91_udc_data udc_data;
-static struct resource udc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9263_BASE_UDP,
-                .end    = AT91SAM9263_BASE_UDP + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_UDP,
-                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_UDP,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91_udc_device = {
-        .name           = "at91_udc",
-        .id             = -1,
-        .dev            = {
-                                .platform_data          = &udc_data,
-        },
-        .resource       = udc_resources,
-        .num_resources  = ARRAY_SIZE(udc_resources),
-};
-void __init at91_add_device_udc(struct at91_udc_data *data)
-{
-        if (!data)
-                return;
-        if (gpio_is_valid(data->vbus_pin)) {
-                at91_set_gpio_input(data->vbus_pin, 0);
-                at91_set_deglitch(data->vbus_pin, 1);
-        }
-        /* Pullup pin is handled internally by USB device peripheral */
-        udc_data = *data;
-        platform_device_register(&at91_udc_device);
-}
-#else
-void __init at91_add_device_udc(struct at91_udc_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  Ethernet
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
-static u64 eth_dmamask = DMA_BIT_MASK(32);
-static struct macb_platform_data eth_data;
-static struct resource eth_resources[] = {
-        [0] = {
-                .start  = AT91SAM9263_BASE_EMAC,
-                .end    = AT91SAM9263_BASE_EMAC + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_EMAC,
-                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_EMAC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9263_eth_device = {
-        .name           = "macb",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &eth_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &eth_data,
-        },
-        .resource       = eth_resources,
-        .num_resources  = ARRAY_SIZE(eth_resources),
-};
-void __init at91_add_device_eth(struct macb_platform_data *data)
-{
-        if (!data)
-                return;
-        if (gpio_is_valid(data->phy_irq_pin)) {
-                at91_set_gpio_input(data->phy_irq_pin, 0);
-                at91_set_deglitch(data->phy_irq_pin, 1);
-        }
-        /* Pins used for MII and RMII */
-        at91_set_A_periph(AT91_PIN_PE21, 0);    /* ETXCK_EREFCK */
-        at91_set_B_periph(AT91_PIN_PC25, 0);    /* ERXDV */
-        at91_set_A_periph(AT91_PIN_PE25, 0);    /* ERX0 */
-        at91_set_A_periph(AT91_PIN_PE26, 0);    /* ERX1 */
-        at91_set_A_periph(AT91_PIN_PE27, 0);    /* ERXER */
-        at91_set_A_periph(AT91_PIN_PE28, 0);    /* ETXEN */
-        at91_set_A_periph(AT91_PIN_PE23, 0);    /* ETX0 */
-        at91_set_A_periph(AT91_PIN_PE24, 0);    /* ETX1 */
-        at91_set_A_periph(AT91_PIN_PE30, 0);    /* EMDIO */
-        at91_set_A_periph(AT91_PIN_PE29, 0);    /* EMDC */
-        if (!data->is_rmii) {
-                at91_set_A_periph(AT91_PIN_PE22, 0);    /* ECRS */
-                at91_set_B_periph(AT91_PIN_PC26, 0);    /* ECOL */
-                at91_set_B_periph(AT91_PIN_PC22, 0);    /* ERX2 */
-                at91_set_B_periph(AT91_PIN_PC23, 0);    /* ERX3 */
-                at91_set_B_periph(AT91_PIN_PC27, 0);    /* ERXCK */
-                at91_set_B_periph(AT91_PIN_PC20, 0);    /* ETX2 */
-                at91_set_B_periph(AT91_PIN_PC21, 0);    /* ETX3 */
-                at91_set_B_periph(AT91_PIN_PC24, 0);    /* ETXER */
-        }
-        eth_data = *data;
-        platform_device_register(&at91sam9263_eth_device);
-}
-#else
-void __init at91_add_device_eth(struct macb_platform_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  MMC / SD
- * -------------------------------------------------------------------- */
-#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
-static u64 mmc_dmamask = DMA_BIT_MASK(32);
-static struct mci_platform_data mmc0_data, mmc1_data;
-static struct resource mmc0_resources[] = {
-        [0] = {
-                .start  = AT91SAM9263_BASE_MCI0,
-                .end    = AT91SAM9263_BASE_MCI0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI0,
-                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9263_mmc0_device = {
-        .name           = "atmel_mci",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &mmc_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &mmc0_data,
-        },
-        .resource       = mmc0_resources,
-        .num_resources  = ARRAY_SIZE(mmc0_resources),
-};
-static struct resource mmc1_resources[] = {
-        [0] = {
-                .start  = AT91SAM9263_BASE_MCI1,
-                .end    = AT91SAM9263_BASE_MCI1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI1,
-                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9263_mmc1_device = {
-        .name           = "atmel_mci",
-        .id             = 1,
-        .dev            = {
-                                .dma_mask               = &mmc_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &mmc1_data,
-        },
-        .resource       = mmc1_resources,
-        .num_resources  = ARRAY_SIZE(mmc1_resources),
-};
-void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
-{
-        unsigned int i;
-        unsigned int slot_count = 0;
-        if (!data)
-                return;
-        for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
-                if (!data->slot[i].bus_width)
-                        continue;
-                /* input/irq */
-                if (gpio_is_valid(data->slot[i].detect_pin)) {
-                        at91_set_gpio_input(data->slot[i].detect_pin,
-                                        1);
-                        at91_set_deglitch(data->slot[i].detect_pin,
-                                        1);
-                }
-                if (gpio_is_valid(data->slot[i].wp_pin))
-                        at91_set_gpio_input(data->slot[i].wp_pin, 1);
-                if (mmc_id == 0) {                              /* MCI0 */
-                        switch (i) {
-                        case 0:                                 /* slot A */
-                                /* CMD */
-                                at91_set_A_periph(AT91_PIN_PA1, 1);
-                                /* DAT0, maybe DAT1..DAT3 */
-                                at91_set_A_periph(AT91_PIN_PA0, 1);
-                                if (data->slot[i].bus_width == 4) {
-                                        at91_set_A_periph(AT91_PIN_PA3, 1);
-                                        at91_set_A_periph(AT91_PIN_PA4, 1);
-                                        at91_set_A_periph(AT91_PIN_PA5, 1);
-                                }
-                                slot_count++;
-                                break;
-                        case 1:                                 /* slot B */
-                                /* CMD */
-                                at91_set_A_periph(AT91_PIN_PA16, 1);
-                                /* DAT0, maybe DAT1..DAT3 */
-                                at91_set_A_periph(AT91_PIN_PA17, 1);
-                                if (data->slot[i].bus_width == 4) {
-                                        at91_set_A_periph(AT91_PIN_PA18, 1);
-                                        at91_set_A_periph(AT91_PIN_PA19, 1);
-                                        at91_set_A_periph(AT91_PIN_PA20, 1);
-                                }
-                                slot_count++;
-                                break;
-                        default:
-                                printk(KERN_ERR
-                                       "AT91: SD/MMC slot %d not available\n", i);
-                                break;
-                        }
-                        if (slot_count) {
-                                /* CLK */
-                                at91_set_A_periph(AT91_PIN_PA12, 0);
-                                mmc0_data = *data;
-                                platform_device_register(&at91sam9263_mmc0_device);
-                        }
-                } else if (mmc_id == 1) {                       /* MCI1 */
-                        switch (i) {
-                        case 0:                                 /* slot A */
-                                /* CMD */
-                                at91_set_A_periph(AT91_PIN_PA7, 1);
-                                /* DAT0, maybe DAT1..DAT3 */
-                                at91_set_A_periph(AT91_PIN_PA8, 1);
-                                if (data->slot[i].bus_width == 4) {
-                                        at91_set_A_periph(AT91_PIN_PA9, 1);
-                                        at91_set_A_periph(AT91_PIN_PA10, 1);
-                                        at91_set_A_periph(AT91_PIN_PA11, 1);
-                                }
-                                slot_count++;
-                                break;
-                        case 1:                                 /* slot B */
-                                /* CMD */
-                                at91_set_A_periph(AT91_PIN_PA21, 1);
-                                /* DAT0, maybe DAT1..DAT3 */
-                                at91_set_A_periph(AT91_PIN_PA22, 1);
-                                if (data->slot[i].bus_width == 4) {
-                                        at91_set_A_periph(AT91_PIN_PA23, 1);
-                                        at91_set_A_periph(AT91_PIN_PA24, 1);
-                                        at91_set_A_periph(AT91_PIN_PA25, 1);
-                                }
-                                slot_count++;
-                                break;
-                        default:
-                                printk(KERN_ERR
-                                       "AT91: SD/MMC slot %d not available\n", i);
-                                break;
-                        }
-                        if (slot_count) {
-                                /* CLK */
-                                at91_set_A_periph(AT91_PIN_PA6, 0);
-                                mmc1_data = *data;
-                                platform_device_register(&at91sam9263_mmc1_device);
-                        }
-                }
-        }
-}
-#else
-void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  Compact Flash (PCMCIA or IDE)
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
-        defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
-static struct at91_cf_data cf0_data;
-static struct resource cf0_resources[] = {
-        [0] = {
-                .start  = AT91_CHIPSELECT_4,
-                .end    = AT91_CHIPSELECT_4 + SZ_256M - 1,
-                .flags  = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
-        }
-};
-static struct platform_device cf0_device = {
-        .id             = 0,
-        .dev            = {
-                                .platform_data  = &cf0_data,
-        },
-        .resource       = cf0_resources,
-        .num_resources  = ARRAY_SIZE(cf0_resources),
-};
-static struct at91_cf_data cf1_data;
-static struct resource cf1_resources[] = {
-        [0] = {
-                .start  = AT91_CHIPSELECT_5,
-                .end    = AT91_CHIPSELECT_5 + SZ_256M - 1,
-                .flags  = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
-        }
-};
-static struct platform_device cf1_device = {
-        .id             = 1,
-        .dev            = {
-                                .platform_data  = &cf1_data,
-        },
-        .resource       = cf1_resources,
-        .num_resources  = ARRAY_SIZE(cf1_resources),
-};
-void __init at91_add_device_cf(struct at91_cf_data *data)
-{
-        unsigned long ebi0_csa;
-        struct platform_device *pdev;
-        if (!data)
-                return;
-        /*
-         * assign CS4 or CS5 to SMC with Compact Flash logic support,
-         * we assume SMC timings are configured by board code,
-         * except True IDE where timings are controlled by driver
-         */
-        ebi0_csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
-        switch (data->chipselect) {
-        case 4:
-                at91_set_A_periph(AT91_PIN_PD6, 0);  /* EBI0_NCS4/CFCS0 */
-                ebi0_csa |= AT91_MATRIX_EBI0_CS4A_SMC_CF1;
-                cf0_data = *data;
-                pdev = &cf0_device;
-                break;
-        case 5:
-                at91_set_A_periph(AT91_PIN_PD7, 0);  /* EBI0_NCS5/CFCS1 */
-                ebi0_csa |= AT91_MATRIX_EBI0_CS5A_SMC_CF2;
-                cf1_data = *data;
-                pdev = &cf1_device;
-                break;
-        default:
-                printk(KERN_ERR "AT91 CF: bad chip-select requested (%u)\n",
-                       data->chipselect);
-                return;
-        }
-        at91_matrix_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
-        if (gpio_is_valid(data->det_pin)) {
-                at91_set_gpio_input(data->det_pin, 1);
-                at91_set_deglitch(data->det_pin, 1);
-        }
-        if (gpio_is_valid(data->irq_pin)) {
-                at91_set_gpio_input(data->irq_pin, 1);
-                at91_set_deglitch(data->irq_pin, 1);
-        }
-        if (gpio_is_valid(data->vcc_pin))
-                /* initially off */
-                at91_set_gpio_output(data->vcc_pin, 0);
-        /* enable EBI controlled pins */
-        at91_set_A_periph(AT91_PIN_PD5, 1);  /* NWAIT */
-        at91_set_A_periph(AT91_PIN_PD8, 0);  /* CFCE1 */
-        at91_set_A_periph(AT91_PIN_PD9, 0);  /* CFCE2 */
-        at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */
-        pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "pata_at91" : "at91_cf";
-        platform_device_register(pdev);
-}
-#else
-void __init at91_add_device_cf(struct at91_cf_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  NAND / SmartMedia
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
-static struct atmel_nand_data nand_data;
-#define NAND_BASE       AT91_CHIPSELECT_3
-static struct resource nand_resources[] = {
-        [0] = {
-                .start  = NAND_BASE,
-                .end    = NAND_BASE + SZ_256M - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91SAM9263_BASE_ECC0,
-                .end    = AT91SAM9263_BASE_ECC0 + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct platform_device at91sam9263_nand_device = {
-        .name           = "atmel_nand",
-        .id             = -1,
-        .dev            = {
-                                .platform_data  = &nand_data,
-        },
-        .resource       = nand_resources,
-        .num_resources  = ARRAY_SIZE(nand_resources),
-};
-void __init at91_add_device_nand(struct atmel_nand_data *data)
-{
-        unsigned long csa;
-        if (!data)
-                return;
-        csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
-        at91_matrix_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
-        /* enable pin */
-        if (gpio_is_valid(data->enable_pin))
-                at91_set_gpio_output(data->enable_pin, 1);
-        /* ready/busy pin */
-        if (gpio_is_valid(data->rdy_pin))
-                at91_set_gpio_input(data->rdy_pin, 1);
-        /* card detect pin */
-        if (gpio_is_valid(data->det_pin))
-                at91_set_gpio_input(data->det_pin, 1);
-        nand_data = *data;
-        platform_device_register(&at91sam9263_nand_device);
-}
-#else
-void __init at91_add_device_nand(struct atmel_nand_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  TWI (i2c)
- * -------------------------------------------------------------------- */
-/*
- * Prefer the GPIO code since the TWI controller isn't robust
- * (gets overruns and underruns under load) and can only issue
- * repeated STARTs in one scenario (the driver doesn't yet handle them).
- */
-#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
-static struct i2c_gpio_platform_data pdata = {
-        .sda_pin                = AT91_PIN_PB4,
-        .sda_is_open_drain      = 1,
-        .scl_pin                = AT91_PIN_PB5,
-        .scl_is_open_drain      = 1,
-        .udelay                 = 2,            /* ~100 kHz */
-};
-static struct platform_device at91sam9263_twi_device = {
-        .name                   = "i2c-gpio",
-        .id                     = 0,
-        .dev.platform_data      = &pdata,
-};
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
-{
-        at91_set_GPIO_periph(AT91_PIN_PB4, 1);          /* TWD (SDA) */
-        at91_set_multi_drive(AT91_PIN_PB4, 1);
-        at91_set_GPIO_periph(AT91_PIN_PB5, 1);          /* TWCK (SCL) */
-        at91_set_multi_drive(AT91_PIN_PB5, 1);
-        i2c_register_board_info(0, devices, nr_devices);
-        platform_device_register(&at91sam9263_twi_device);
-}
-#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
-static struct resource twi_resources[] = {
-        [0] = {
-                .start  = AT91SAM9263_BASE_TWI,
-                .end    = AT91SAM9263_BASE_TWI + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_TWI,
-                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_TWI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9263_twi_device = {
-        .name           = "i2c-at91sam9260",
-        .id             = 0,
-        .resource       = twi_resources,
-        .num_resources  = ARRAY_SIZE(twi_resources),
-};
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
-{
-        /* pins used for TWI interface */
-        at91_set_A_periph(AT91_PIN_PB4, 0);             /* TWD */
-        at91_set_multi_drive(AT91_PIN_PB4, 1);
-        at91_set_A_periph(AT91_PIN_PB5, 0);             /* TWCK */
-        at91_set_multi_drive(AT91_PIN_PB5, 1);
-        i2c_register_board_info(0, devices, nr_devices);
-        platform_device_register(&at91sam9263_twi_device);
-}
-#else
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
-#endif
-/* --------------------------------------------------------------------
- *  SPI
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
-static u64 spi_dmamask = DMA_BIT_MASK(32);
-static struct resource spi0_resources[] = {
-        [0] = {
-                .start  = AT91SAM9263_BASE_SPI0,
-                .end    = AT91SAM9263_BASE_SPI0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI0,
-                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9263_spi0_device = {
-        .name           = "atmel_spi",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &spi_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = spi0_resources,
-        .num_resources  = ARRAY_SIZE(spi0_resources),
-};
-static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PB11 };
-static struct resource spi1_resources[] = {
-        [0] = {
-                .start  = AT91SAM9263_BASE_SPI1,
-                .end    = AT91SAM9263_BASE_SPI1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI1,
-                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9263_spi1_device = {
-        .name           = "atmel_spi",
-        .id             = 1,
-        .dev            = {
-                                .dma_mask               = &spi_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = spi1_resources,
-        .num_resources  = ARRAY_SIZE(spi1_resources),
-};
-static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
-void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
-{
-        int i;
-        unsigned long cs_pin;
-        short enable_spi0 = 0;
-        short enable_spi1 = 0;
-        /* Choose SPI chip-selects */
-        for (i = 0; i < nr_devices; i++) {
-                if (devices[i].controller_data)
-                        cs_pin = (unsigned long) devices[i].controller_data;
-                else if (devices[i].bus_num == 0)
-                        cs_pin = spi0_standard_cs[devices[i].chip_select];
-                else
-                        cs_pin = spi1_standard_cs[devices[i].chip_select];
-                if (!gpio_is_valid(cs_pin))
-                        continue;
-                if (devices[i].bus_num == 0)
-                        enable_spi0 = 1;
-                else
-                        enable_spi1 = 1;
-                /* enable chip-select pin */
-                at91_set_gpio_output(cs_pin, 1);
-                /* pass chip-select pin to driver */
-                devices[i].controller_data = (void *) cs_pin;
-        }
-        spi_register_board_info(devices, nr_devices);
-        /* Configure SPI bus(es) */
-        if (enable_spi0) {
-                at91_set_B_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
-                at91_set_B_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
-                at91_set_B_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
-                platform_device_register(&at91sam9263_spi0_device);
-        }
-        if (enable_spi1) {
-                at91_set_A_periph(AT91_PIN_PB12, 0);    /* SPI1_MISO */
-                at91_set_A_periph(AT91_PIN_PB13, 0);    /* SPI1_MOSI */
-                at91_set_A_periph(AT91_PIN_PB14, 0);    /* SPI1_SPCK */
-                platform_device_register(&at91sam9263_spi1_device);
-        }
-}
-#else
-void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
-#endif
-/* --------------------------------------------------------------------
- *  AC97
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
-static u64 ac97_dmamask = DMA_BIT_MASK(32);
-static struct ac97c_platform_data ac97_data;
-static struct resource ac97_resources[] = {
-        [0] = {
-                .start  = AT91SAM9263_BASE_AC97C,
-                .end    = AT91SAM9263_BASE_AC97C + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_AC97C,
-                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_AC97C,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9263_ac97_device = {
-        .name           = "atmel_ac97c",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &ac97_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &ac97_data,
-        },
-        .resource       = ac97_resources,
-        .num_resources  = ARRAY_SIZE(ac97_resources),
-};
-void __init at91_add_device_ac97(struct ac97c_platform_data *data)
-{
-        if (!data)
-                return;
-        at91_set_A_periph(AT91_PIN_PB0, 0);     /* AC97FS */
-        at91_set_A_periph(AT91_PIN_PB1, 0);     /* AC97CK */
-        at91_set_A_periph(AT91_PIN_PB2, 0);     /* AC97TX */
-        at91_set_A_periph(AT91_PIN_PB3, 0);     /* AC97RX */
-        /* reset */
-        if (gpio_is_valid(data->reset_pin))
-                at91_set_gpio_output(data->reset_pin, 0);
-        ac97_data = *data;
-        platform_device_register(&at91sam9263_ac97_device);
-}
-#else
-void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  CAN Controller
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_CAN_AT91) || defined(CONFIG_CAN_AT91_MODULE)
-static struct resource can_resources[] = {
-        [0] = {
-                .start  = AT91SAM9263_BASE_CAN,
-                .end    = AT91SAM9263_BASE_CAN + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_CAN,
-                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_CAN,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9263_can_device = {
-        .name           = "at91_can",
-        .id             = -1,
-        .resource       = can_resources,
-        .num_resources  = ARRAY_SIZE(can_resources),
-};
-void __init at91_add_device_can(struct at91_can_data *data)
-{
-        at91_set_A_periph(AT91_PIN_PA13, 0);    /* CANTX */
-        at91_set_A_periph(AT91_PIN_PA14, 0);    /* CANRX */
-        at91sam9263_can_device.dev.platform_data = data;
-        platform_device_register(&at91sam9263_can_device);
-}
-#else
-void __init at91_add_device_can(struct at91_can_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  LCD Controller
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
-static u64 lcdc_dmamask = DMA_BIT_MASK(32);
-static struct atmel_lcdfb_pdata lcdc_data;
-static struct resource lcdc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9263_LCDC_BASE,
-                .end    = AT91SAM9263_LCDC_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_LCDC,
-                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_LCDC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91_lcdc_device = {
-        .name           = "at91sam9263-lcdfb",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &lcdc_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &lcdc_data,
-        },
-        .resource       = lcdc_resources,
-        .num_resources  = ARRAY_SIZE(lcdc_resources),
-};
-void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data)
-{
-        if (!data)
-                return;
-        at91_set_A_periph(AT91_PIN_PC1, 0);     /* LCDHSYNC */
-        at91_set_A_periph(AT91_PIN_PC2, 0);     /* LCDDOTCK */
-        at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDDEN */
-        at91_set_B_periph(AT91_PIN_PB9, 0);     /* LCDCC */
-        at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDD2 */
-        at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDD3 */
-        at91_set_A_periph(AT91_PIN_PC8, 0);     /* LCDD4 */
-        at91_set_A_periph(AT91_PIN_PC9, 0);     /* LCDD5 */
-        at91_set_A_periph(AT91_PIN_PC10, 0);    /* LCDD6 */
-        at91_set_A_periph(AT91_PIN_PC11, 0);    /* LCDD7 */
-        at91_set_A_periph(AT91_PIN_PC14, 0);    /* LCDD10 */
-        at91_set_A_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
-        at91_set_A_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
-        at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD13 */
-        at91_set_A_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
-        at91_set_A_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
-        at91_set_A_periph(AT91_PIN_PC22, 0);    /* LCDD18 */
-        at91_set_A_periph(AT91_PIN_PC23, 0);    /* LCDD19 */
-        at91_set_A_periph(AT91_PIN_PC24, 0);    /* LCDD20 */
-        at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD21 */
-        at91_set_A_periph(AT91_PIN_PC26, 0);    /* LCDD22 */
-        at91_set_A_periph(AT91_PIN_PC27, 0);    /* LCDD23 */
-        lcdc_data = *data;
-        platform_device_register(&at91_lcdc_device);
-}
-#else
-void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  Image Sensor Interface
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_VIDEO_AT91_ISI) || defined(CONFIG_VIDEO_AT91_ISI_MODULE)
-struct resource isi_resources[] = {
-        [0] = {
-                .start  = AT91SAM9263_BASE_ISI,
-                .end    = AT91SAM9263_BASE_ISI + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_ISI,
-                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_ISI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9263_isi_device = {
-        .name           = "at91_isi",
-        .id             = -1,
-        .resource       = isi_resources,
-        .num_resources  = ARRAY_SIZE(isi_resources),
-};
-void __init at91_add_device_isi(struct isi_platform_data *data,
-                bool use_pck_as_mck)
-{
-        at91_set_A_periph(AT91_PIN_PE0, 0);     /* ISI_D0 */
-        at91_set_A_periph(AT91_PIN_PE1, 0);     /* ISI_D1 */
-        at91_set_A_periph(AT91_PIN_PE2, 0);     /* ISI_D2 */
-        at91_set_A_periph(AT91_PIN_PE3, 0);     /* ISI_D3 */
-        at91_set_A_periph(AT91_PIN_PE4, 0);     /* ISI_D4 */
-        at91_set_A_periph(AT91_PIN_PE5, 0);     /* ISI_D5 */
-        at91_set_A_periph(AT91_PIN_PE6, 0);     /* ISI_D6 */
-        at91_set_A_periph(AT91_PIN_PE7, 0);     /* ISI_D7 */
-        at91_set_A_periph(AT91_PIN_PE8, 0);     /* ISI_PCK */
-        at91_set_A_periph(AT91_PIN_PE9, 0);     /* ISI_HSYNC */
-        at91_set_A_periph(AT91_PIN_PE10, 0);    /* ISI_VSYNC */
-        at91_set_B_periph(AT91_PIN_PE12, 0);    /* ISI_PD8 */
-        at91_set_B_periph(AT91_PIN_PE13, 0);    /* ISI_PD9 */
-        at91_set_B_periph(AT91_PIN_PE14, 0);    /* ISI_PD10 */
-        at91_set_B_periph(AT91_PIN_PE15, 0);    /* ISI_PD11 */
-        if (use_pck_as_mck) {
-                at91_set_B_periph(AT91_PIN_PE11, 0);    /* ISI_MCK (PCK3) */
-                /* TODO: register the PCK for ISI_MCK and set its parent */
-        }
-}
-#else
-void __init at91_add_device_isi(struct isi_platform_data *data,
-                bool use_pck_as_mck) {}
-#endif
-/* --------------------------------------------------------------------
- *  Timer/Counter block
- * -------------------------------------------------------------------- */
-#ifdef CONFIG_ATMEL_TCLIB
-static struct resource tcb_resources[] = {
-        [0] = {
-                .start  = AT91SAM9263_BASE_TCB0,
-                .end    = AT91SAM9263_BASE_TCB0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_TCB,
-                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_TCB,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9263_tcb_device = {
-        .name           = "atmel_tcb",
-        .id             = 0,
-        .resource       = tcb_resources,
-        .num_resources  = ARRAY_SIZE(tcb_resources),
-};
-#if defined(CONFIG_OF)
-static struct of_device_id tcb_ids[] = {
-        { .compatible = "atmel,at91rm9200-tcb" },
-        { /*sentinel*/ }
-};
-#endif
-static void __init at91_add_device_tc(void)
-{
-#if defined(CONFIG_OF)
-        struct device_node *np;
-        np = of_find_matching_node(NULL, tcb_ids);
-        if (np) {
-                of_node_put(np);
-                return;
-        }
-#endif
-        platform_device_register(&at91sam9263_tcb_device);
-}
-#else
-static void __init at91_add_device_tc(void) { }
-#endif
-/* --------------------------------------------------------------------
- *  RTT
- * -------------------------------------------------------------------- */
-static struct resource rtt0_resources[] = {
-        {
-                .start  = AT91SAM9263_BASE_RTT0,
-                .end    = AT91SAM9263_BASE_RTT0 + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-static struct platform_device at91sam9263_rtt0_device = {
-        .name           = "at91_rtt",
-        .id             = 0,
-        .resource       = rtt0_resources,
-};
-static struct resource rtt1_resources[] = {
-        {
-                .start  = AT91SAM9263_BASE_RTT1,
-                .end    = AT91SAM9263_BASE_RTT1 + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-static struct platform_device at91sam9263_rtt1_device = {
-        .name           = "at91_rtt",
-        .id             = 1,
-        .resource       = rtt1_resources,
-};
-#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
-static void __init at91_add_device_rtt_rtc(void)
-{
-        struct platform_device *pdev;
-        struct resource *r;
-        switch (CONFIG_RTC_DRV_AT91SAM9_RTT) {
-        case 0:
-                /*
-                 * The second resource is needed only for the chosen RTT:
-                 * GPBR will serve as the storage for RTC time offset
-                 */
-                at91sam9263_rtt0_device.num_resources = 3;
-                at91sam9263_rtt1_device.num_resources = 1;
-                pdev = &at91sam9263_rtt0_device;
-                r = rtt0_resources;
-                break;
-        case 1:
-                at91sam9263_rtt0_device.num_resources = 1;
-                at91sam9263_rtt1_device.num_resources = 3;
-                pdev = &at91sam9263_rtt1_device;
-                r = rtt1_resources;
-                break;
-        default:
-                pr_err("at91sam9263: only supports 2 RTT (%d)\n",
-                       CONFIG_RTC_DRV_AT91SAM9_RTT);
-                return;
-        }
-        pdev->name = "rtc-at91sam9";
-        r[1].start = AT91SAM9263_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
-        r[1].end = r[1].start + 3;
-        r[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
-        r[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
-}
-#else
-static void __init at91_add_device_rtt_rtc(void)
-{
-        /* Only one resource is needed: RTT not used as RTC */
-        at91sam9263_rtt0_device.num_resources = 1;
-        at91sam9263_rtt1_device.num_resources = 1;
-}
-#endif
-static void __init at91_add_device_rtt(void)
-{
-        at91_add_device_rtt_rtc();
-        platform_device_register(&at91sam9263_rtt0_device);
-        platform_device_register(&at91sam9263_rtt1_device);
-}
-/* --------------------------------------------------------------------
- *  Watchdog
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
-static struct resource wdt_resources[] = {
-        {
-                .start  = AT91SAM9263_BASE_WDT,
-                .end    = AT91SAM9263_BASE_WDT + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct platform_device at91sam9263_wdt_device = {
-        .name           = "at91_wdt",
-        .id             = -1,
-        .resource       = wdt_resources,
-        .num_resources  = ARRAY_SIZE(wdt_resources),
-};
-static void __init at91_add_device_watchdog(void)
-{
-        platform_device_register(&at91sam9263_wdt_device);
-}
-#else
-static void __init at91_add_device_watchdog(void) {}
-#endif
-/* --------------------------------------------------------------------
- *  PWM
- * --------------------------------------------------------------------*/
-#if IS_ENABLED(CONFIG_PWM_ATMEL)
-static struct resource pwm_resources[] = {
-        [0] = {
-                .start  = AT91SAM9263_BASE_PWMC,
-                .end    = AT91SAM9263_BASE_PWMC + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_PWMC,
-                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_PWMC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9263_pwm0_device = {
-        .name   = "at91sam9rl-pwm",
-        .id     = -1,
-        .resource       = pwm_resources,
-        .num_resources  = ARRAY_SIZE(pwm_resources),
-};
-void __init at91_add_device_pwm(u32 mask)
-{
-        if (mask & (1 << AT91_PWM0))
-                at91_set_B_periph(AT91_PIN_PB7, 1);     /* enable PWM0 */
-        if (mask & (1 << AT91_PWM1))
-                at91_set_B_periph(AT91_PIN_PB8, 1);     /* enable PWM1 */
-        if (mask & (1 << AT91_PWM2))
-                at91_set_B_periph(AT91_PIN_PC29, 1);    /* enable PWM2 */
-        if (mask & (1 << AT91_PWM3))
-                at91_set_B_periph(AT91_PIN_PB29, 1);    /* enable PWM3 */
-        platform_device_register(&at91sam9263_pwm0_device);
-}
-#else
-void __init at91_add_device_pwm(u32 mask) {}
-#endif
-/* --------------------------------------------------------------------
- *  SSC -- Synchronous Serial Controller
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
-static u64 ssc0_dmamask = DMA_BIT_MASK(32);
-static struct resource ssc0_resources[] = {
-        [0] = {
-                .start  = AT91SAM9263_BASE_SSC0,
-                .end    = AT91SAM9263_BASE_SSC0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC0,
-                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9263_ssc0_device = {
-        .name   = "at91rm9200_ssc",
-        .id     = 0,
-        .dev    = {
-                .dma_mask               = &ssc0_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = ssc0_resources,
-        .num_resources  = ARRAY_SIZE(ssc0_resources),
-};
-static inline void configure_ssc0_pins(unsigned pins)
-{
-        if (pins & ATMEL_SSC_TF)
-                at91_set_B_periph(AT91_PIN_PB0, 1);
-        if (pins & ATMEL_SSC_TK)
-                at91_set_B_periph(AT91_PIN_PB1, 1);
-        if (pins & ATMEL_SSC_TD)
-                at91_set_B_periph(AT91_PIN_PB2, 1);
-        if (pins & ATMEL_SSC_RD)
-                at91_set_B_periph(AT91_PIN_PB3, 1);
-        if (pins & ATMEL_SSC_RK)
-                at91_set_B_periph(AT91_PIN_PB4, 1);
-        if (pins & ATMEL_SSC_RF)
-                at91_set_B_periph(AT91_PIN_PB5, 1);
-}
-static u64 ssc1_dmamask = DMA_BIT_MASK(32);
-static struct resource ssc1_resources[] = {
-        [0] = {
-                .start  = AT91SAM9263_BASE_SSC1,
-                .end    = AT91SAM9263_BASE_SSC1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC1,
-                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9263_ssc1_device = {
-        .name   = "at91rm9200_ssc",
-        .id     = 1,
-        .dev    = {
-                .dma_mask               = &ssc1_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = ssc1_resources,
-        .num_resources  = ARRAY_SIZE(ssc1_resources),
-};
-static inline void configure_ssc1_pins(unsigned pins)
-{
-        if (pins & ATMEL_SSC_TF)
-                at91_set_A_periph(AT91_PIN_PB6, 1);
-        if (pins & ATMEL_SSC_TK)
-                at91_set_A_periph(AT91_PIN_PB7, 1);
-        if (pins & ATMEL_SSC_TD)
-                at91_set_A_periph(AT91_PIN_PB8, 1);
-        if (pins & ATMEL_SSC_RD)
-                at91_set_A_periph(AT91_PIN_PB9, 1);
-        if (pins & ATMEL_SSC_RK)
-                at91_set_A_periph(AT91_PIN_PB10, 1);
-        if (pins & ATMEL_SSC_RF)
-                at91_set_A_periph(AT91_PIN_PB11, 1);
-}
-/*
- * SSC controllers are accessed through library code, instead of any
- * kind of all-singing/all-dancing driver.  For example one could be
- * used by a particular I2S audio codec's driver, while another one
- * on the same system might be used by a custom data capture driver.
- */
-void __init at91_add_device_ssc(unsigned id, unsigned pins)
-{
-        struct platform_device *pdev;
-        /*
-         * NOTE: caller is responsible for passing information matching
-         * "pins" to whatever will be using each particular controller.
-         */
-        switch (id) {
-        case AT91SAM9263_ID_SSC0:
-                pdev = &at91sam9263_ssc0_device;
-                configure_ssc0_pins(pins);
-                break;
-        case AT91SAM9263_ID_SSC1:
-                pdev = &at91sam9263_ssc1_device;
-                configure_ssc1_pins(pins);
-                break;
-        default:
-                return;
-        }
-        platform_device_register(pdev);
-}
-#else
-void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
-#endif
-/* --------------------------------------------------------------------
- *  UART
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_SERIAL_ATMEL)
-static struct resource dbgu_resources[] = {
-        [0] = {
-                .start  = AT91SAM9263_BASE_DBGU,
-                .end    = AT91SAM9263_BASE_DBGU + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
-                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data dbgu_data = {
-        .use_dma_tx     = 0,
-        .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
-};
-static u64 dbgu_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9263_dbgu_device = {
-        .name           = "atmel_usart",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &dbgu_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &dbgu_data,
-        },
-        .resource       = dbgu_resources,
-        .num_resources  = ARRAY_SIZE(dbgu_resources),
-};
-static inline void configure_dbgu_pins(void)
-{
-        at91_set_A_periph(AT91_PIN_PC30, 0);            /* DRXD */
-        at91_set_A_periph(AT91_PIN_PC31, 1);            /* DTXD */
-}
-static struct resource uart0_resources[] = {
-        [0] = {
-                .start  = AT91SAM9263_BASE_US0,
-                .end    = AT91SAM9263_BASE_US0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_US0,
-                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_US0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart0_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static u64 uart0_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9263_uart0_device = {
-        .name           = "atmel_usart",
-        .id             = 1,
-        .dev            = {
-                                .dma_mask               = &uart0_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart0_data,
-        },
-        .resource       = uart0_resources,
-        .num_resources  = ARRAY_SIZE(uart0_resources),
-};
-static inline void configure_usart0_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PA26, 1);            /* TXD0 */
-        at91_set_A_periph(AT91_PIN_PA27, 0);            /* RXD0 */
-        if (pins & ATMEL_UART_RTS)
-                at91_set_A_periph(AT91_PIN_PA28, 0);    /* RTS0 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_A_periph(AT91_PIN_PA29, 0);    /* CTS0 */
-}
-static struct resource uart1_resources[] = {
-        [0] = {
-                .start  = AT91SAM9263_BASE_US1,
-                .end    = AT91SAM9263_BASE_US1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_US1,
-                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_US1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart1_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static u64 uart1_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9263_uart1_device = {
-        .name           = "atmel_usart",
-        .id             = 2,
-        .dev            = {
-                                .dma_mask               = &uart1_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart1_data,
-        },
-        .resource       = uart1_resources,
-        .num_resources  = ARRAY_SIZE(uart1_resources),
-};
-static inline void configure_usart1_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PD0, 1);             /* TXD1 */
-        at91_set_A_periph(AT91_PIN_PD1, 0);             /* RXD1 */
-        if (pins & ATMEL_UART_RTS)
-                at91_set_B_periph(AT91_PIN_PD7, 0);     /* RTS1 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_B_periph(AT91_PIN_PD8, 0);     /* CTS1 */
-}
-static struct resource uart2_resources[] = {
-        [0] = {
-                .start  = AT91SAM9263_BASE_US2,
-                .end    = AT91SAM9263_BASE_US2 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_US2,
-                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_US2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart2_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static u64 uart2_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9263_uart2_device = {
-        .name           = "atmel_usart",
-        .id             = 3,
-        .dev            = {
-                                .dma_mask               = &uart2_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart2_data,
-        },
-        .resource       = uart2_resources,
-        .num_resources  = ARRAY_SIZE(uart2_resources),
-};
-static inline void configure_usart2_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PD2, 1);             /* TXD2 */
-        at91_set_A_periph(AT91_PIN_PD3, 0);             /* RXD2 */
-        if (pins & ATMEL_UART_RTS)
-                at91_set_B_periph(AT91_PIN_PD5, 0);     /* RTS2 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_B_periph(AT91_PIN_PD6, 0);     /* CTS2 */
-}
-static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
-{
-        struct platform_device *pdev;
-        struct atmel_uart_data *pdata;
-        switch (id) {
-                case 0:         /* DBGU */
-                        pdev = &at91sam9263_dbgu_device;
-                        configure_dbgu_pins();
-                        break;
-                case AT91SAM9263_ID_US0:
-                        pdev = &at91sam9263_uart0_device;
-                        configure_usart0_pins(pins);
-                        break;
-                case AT91SAM9263_ID_US1:
-                        pdev = &at91sam9263_uart1_device;
-                        configure_usart1_pins(pins);
-                        break;
-                case AT91SAM9263_ID_US2:
-                        pdev = &at91sam9263_uart2_device;
-                        configure_usart2_pins(pins);
-                        break;
-                default:
-                        return;
-        }
-        pdata = pdev->dev.platform_data;
-        pdata->num = portnr;            /* update to mapped ID */
-        if (portnr < ATMEL_MAX_UART)
-                at91_uarts[portnr] = pdev;
-}
-void __init at91_add_device_serial(void)
-{
-        int i;
-        for (i = 0; i < ATMEL_MAX_UART; i++) {
-                if (at91_uarts[i])
-                        platform_device_register(at91_uarts[i]);
-        }
-}
-#else
-void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
-void __init at91_add_device_serial(void) {}
-#endif
-/* -------------------------------------------------------------------- */
-/*
- * These devices are always present and don't need any board-specific
- * setup.
- */
-static int __init at91_add_standard_devices(void)
-{
-        if (of_have_populated_dt())
-                return 0;
-        at91_add_device_rtt();
-        at91_add_device_watchdog();
-        at91_add_device_tc();
-        return 0;
-}
-arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 405427ec05f8..b6117bea9a6f 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -10,356 +10,12 @@
 *
 */
-#include <linux/module.h>
-#include <linux/dma-mapping.h>
-#include <linux/clk/at91_pmc.h>
-#include <linux/platform_device.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
 #include <asm/system_misc.h>
-#include <mach/at91sam9g45.h>
+#include <asm/irq.h>
-#include <mach/cpu.h>
 #include <mach/hardware.h>
-#include "at91_aic.h"
 #include "soc.h"
 #include "generic.h"
-#include "sam9_smc.h"
-#include "pm.h"
-#if defined(CONFIG_OLD_CLK_AT91)
-#include "clock.h"
-/* --------------------------------------------------------------------
- *  Clocks
- * -------------------------------------------------------------------- */
-/*
- * The peripheral clocks.
- */
-static struct clk pioA_clk = {
-        .name           = "pioA_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_PIOA,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
-        .name           = "pioB_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_PIOB,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
-        .name           = "pioC_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_PIOC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioDE_clk = {
-        .name           = "pioDE_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_PIODE,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk trng_clk = {
-        .name           = "trng_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_TRNG,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
-        .name           = "usart0_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_US0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
-        .name           = "usart1_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_US1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
-        .name           = "usart2_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_US2,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart3_clk = {
-        .name           = "usart3_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_US3,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc0_clk = {
-        .name           = "mci0_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_MCI0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi0_clk = {
-        .name           = "twi0_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_TWI0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi1_clk = {
-        .name           = "twi1_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_TWI1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
-        .name           = "spi0_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_SPI0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
-        .name           = "spi1_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_SPI1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
-        .name           = "ssc0_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_SSC0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
-        .name           = "ssc1_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_SSC1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tcb0_clk = {
-        .name           = "tcb0_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_TCB,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pwm_clk = {
-        .name           = "pwm_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_PWMC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tsc_clk = {
-        .name           = "tsc_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_TSC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma_clk = {
-        .name           = "dma_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_DMA,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uhphs_clk = {
-        .name           = "uhphs_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_UHPHS,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk lcdc_clk = {
-        .name           = "lcdc_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_LCDC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ac97_clk = {
-        .name           = "ac97_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_AC97C,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk macb_clk = {
-        .name           = "pclk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_EMAC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk isi_clk = {
-        .name           = "isi_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_ISI,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udphs_clk = {
-        .name           = "udphs_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_UDPHS,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc1_clk = {
-        .name           = "mci1_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_MCI1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-/* Video decoder clock - Only for sam9m10/sam9m11 */
-static struct clk vdec_clk = {
-        .name           = "vdec_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_VDEC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk adc_op_clk = {
-        .name           = "adc_op_clk",
-        .type           = CLK_TYPE_PERIPHERAL,
-        .rate_hz        = 300000,
-};
-/* AES/TDES/SHA clock - Only for sam9m11/sam9g56 */
-static struct clk aestdessha_clk = {
-        .name           = "aestdessha_clk",
-        .pmc_mask       = 1 << AT91SAM9G45_ID_AESTDESSHA,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk *periph_clocks[] __initdata = {
-        &pioA_clk,
-        &pioB_clk,
-        &pioC_clk,
-        &pioDE_clk,
-        &trng_clk,
-        &usart0_clk,
-        &usart1_clk,
-        &usart2_clk,
-        &usart3_clk,
-        &mmc0_clk,
-        &twi0_clk,
-        &twi1_clk,
-        &spi0_clk,
-        &spi1_clk,
-        &ssc0_clk,
-        &ssc1_clk,
-        &tcb0_clk,
-        &pwm_clk,
-        &tsc_clk,
-        &dma_clk,
-        &uhphs_clk,
-        &lcdc_clk,
-        &ac97_clk,
-        &macb_clk,
-        &isi_clk,
-        &udphs_clk,
-        &mmc1_clk,
-        &adc_op_clk,
-        &aestdessha_clk,
-        // irq0
-};
-static struct clk_lookup periph_clocks_lookups[] = {
-        /* One additional fake clock for macb_hclk */
-        CLKDEV_CON_ID("hclk", &macb_clk),
-        /* One additional fake clock for ohci */
-        CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
-        CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
-        CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
-        CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
-        CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
-        CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
-        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
-        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
-        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk),
-        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk),
-        CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.0", &ssc0_clk),
-        CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.1", &ssc1_clk),
-        CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc0_clk),
-        CLKDEV_CON_DEV_ID("pclk", "fffa0000.ssc", &ssc1_clk),
-        CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
-        CLKDEV_CON_DEV_ID(NULL, "atmel_sha", &aestdessha_clk),
-        CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk),
-        CLKDEV_CON_DEV_ID(NULL, "atmel_aes", &aestdessha_clk),
-        CLKDEV_CON_DEV_ID(NULL, "at91sam9rl-pwm", &pwm_clk),
-        /* more usart lookup table for DT entries */
-        CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
-        CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
-        CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
-        CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
-        CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
-        /* more tc lookup table for DT entries */
-        CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
-        CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
-        CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
-        CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
-        CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk),
-        CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk),
-        /* fake hclk clock */
-        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk),
-        CLKDEV_CON_ID("pioA", &pioA_clk),
-        CLKDEV_CON_ID("pioB", &pioB_clk),
-        CLKDEV_CON_ID("pioC", &pioC_clk),
-        CLKDEV_CON_ID("pioD", &pioDE_clk),
-        CLKDEV_CON_ID("pioE", &pioDE_clk),
-        /* Fake adc clock */
-        CLKDEV_CON_ID("adc_clk", &tsc_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk),
-};
-static struct clk_lookup usart_clocks_lookups[] = {
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
-};
-/*
- * The two programmable clocks.
- * You must configure pin multiplexing to bring these signals out.
- */
-static struct clk pck0 = {
-        .name           = "pck0",
-        .pmc_mask       = AT91_PMC_PCK0,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 0,
-};
-static struct clk pck1 = {
-        .name           = "pck1",
-        .pmc_mask       = AT91_PMC_PCK1,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 1,
-};
-static void __init at91sam9g45_register_clocks(void)
-{
-        int i;
-        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
-                clk_register(periph_clocks[i]);
-        clkdev_add_table(periph_clocks_lookups,
-                         ARRAY_SIZE(periph_clocks_lookups));
-        clkdev_add_table(usart_clocks_lookups,
-                         ARRAY_SIZE(usart_clocks_lookups));
-        if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
-                clk_register(&vdec_clk);
-        clk_register(&pck0);
-        clk_register(&pck1);
-}
-#else
-#define at91sam9g45_register_clocks NULL
-#endif
-/* --------------------------------------------------------------------
- *  GPIO
- * -------------------------------------------------------------------- */
-static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
-        {
-                .id             = AT91SAM9G45_ID_PIOA,
-                .regbase        = AT91SAM9G45_BASE_PIOA,
-        }, {
-                .id             = AT91SAM9G45_ID_PIOB,
-                .regbase        = AT91SAM9G45_BASE_PIOB,
-        }, {
-                .id             = AT91SAM9G45_ID_PIOC,
-                .regbase        = AT91SAM9G45_BASE_PIOC,
-        }, {
-                .id             = AT91SAM9G45_ID_PIODE,
-                .regbase        = AT91SAM9G45_BASE_PIOD,
-        }, {
-                .id             = AT91SAM9G45_ID_PIODE,
-                .regbase        = AT91SAM9G45_BASE_PIOE,
-        }
-};
 /* --------------------------------------------------------------------
 *  AT91SAM9G45 processor initialization
@@ -370,125 +26,15 @@ static void __init at91sam9g45_map_io(void)
        at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
 }
-static void __init at91sam9g45_ioremap_registers(void)
-{
-        at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
-        at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
-        at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
-        at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
-        at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
-        at91_pm_set_standby(at91_ddr_standby);
-}
 static void __init at91sam9g45_initialize(void)
 {
        arm_pm_idle = at91sam9_idle;
        at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC);
        at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT);
-        /* Register GPIO subsystem */
-        at91_gpio_init(at91sam9g45_gpio, 5);
-}
-static struct resource rstc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_RSTC,
-                .end    = AT91SAM9G45_BASE_RSTC + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91SAM9G45_BASE_DDRSDRC1,
-                .end    = AT91SAM9G45_BASE_DDRSDRC1 + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start  = AT91SAM9G45_BASE_DDRSDRC0,
-                .end    = AT91SAM9G45_BASE_DDRSDRC0 + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device rstc_device = {
-        .name           = "at91-sam9g45-reset",
-        .resource       = rstc_resources,
-        .num_resources  = ARRAY_SIZE(rstc_resources),
-};
-static struct resource shdwc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_SHDWC,
-                .end    = AT91SAM9G45_BASE_SHDWC + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device shdwc_device = {
-        .name           = "at91-poweroff",
-        .resource       = shdwc_resources,
-        .num_resources  = ARRAY_SIZE(shdwc_resources),
-};
-static void __init at91sam9g45_register_devices(void)
-{
-        platform_device_register(&rstc_device);
-        platform_device_register(&shdwc_device);
-}
-/* --------------------------------------------------------------------
- *  Interrupt initialization
- * -------------------------------------------------------------------- */
-/*
- * The default interrupt priority levels (0 = lowest, 7 = highest).
- */
-static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
-        7,      /* Advanced Interrupt Controller (FIQ) */
-        7,      /* System Peripherals */
-        1,      /* Parallel IO Controller A */
-        1,      /* Parallel IO Controller B */
-        1,      /* Parallel IO Controller C */
-        1,      /* Parallel IO Controller D and E */
-        0,
-        5,      /* USART 0 */
-        5,      /* USART 1 */
-        5,      /* USART 2 */
-        5,      /* USART 3 */
-        0,      /* Multimedia Card Interface 0 */
-        6,      /* Two-Wire Interface 0 */
-        6,      /* Two-Wire Interface 1 */
-        5,      /* Serial Peripheral Interface 0 */
-        5,      /* Serial Peripheral Interface 1 */
-        4,      /* Serial Synchronous Controller 0 */
-        4,      /* Serial Synchronous Controller 1 */
-        0,      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
-        0,      /* Pulse Width Modulation Controller */
-        0,      /* Touch Screen Controller */
-        0,      /* DMA Controller */
-        2,      /* USB Host High Speed port */
-        3,      /* LDC Controller */
-        5,      /* AC97 Controller */
-        3,      /* Ethernet */
-        0,      /* Image Sensor Interface */
-        2,      /* USB Device High speed port */
-        0,      /* AESTDESSHA Crypto HW Accelerators */
-        0,      /* Multimedia Card Interface 1 */
-        0,
-        0,      /* Advanced Interrupt Controller (IRQ0) */
-};
-static void __init at91sam9g45_init_time(void)
-{
-        at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
 }
 AT91_SOC_START(at91sam9g45)
        .map_io = at91sam9g45_map_io,
-        .default_irq_priority = at91sam9g45_default_irq_priority,
-        .extern_irq = (1 << AT91SAM9G45_ID_IRQ0),
-        .ioremap_registers = at91sam9g45_ioremap_registers,
-        .register_clocks = at91sam9g45_register_clocks,
-        .register_devices = at91sam9g45_register_devices,
        .init = at91sam9g45_initialize,
-        .init_time = at91sam9g45_init_time,
 AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
deleted file mode 100644
index 21ab782cc8e9..000000000000
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ /dev/null
@@ -1,1915 +0,0 @@
-/*
- *  On-Chip devices setup code for the AT91SAM9G45 family
- *
- *  Copyright (C) 2009 Atmel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/i2c-gpio.h>
-#include <linux/atmel-mci.h>
-#include <linux/platform_data/crypto-atmel.h>
-#include <linux/platform_data/at91_adc.h>
-#include <linux/fb.h>
-#include <video/atmel_lcdc.h>
-#include <mach/at91sam9g45.h>
-#include <mach/at91sam9g45_matrix.h>
-#include <mach/at91_matrix.h>
-#include <mach/at91sam9_smc.h>
-#include <linux/platform_data/dma-atmel.h>
-#include <mach/atmel-mci.h>
-#include <mach/hardware.h>
-#include <media/atmel-isi.h>
-#include "board.h"
-#include "generic.h"
-#include "clock.h"
-#include "gpio.h"
-/* --------------------------------------------------------------------
- *  HDMAC - AHB DMA Controller
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
-static u64 hdmac_dmamask = DMA_BIT_MASK(32);
-static struct resource hdmac_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_DMA,
-                .end    = AT91SAM9G45_BASE_DMA + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at_hdmac_device = {
-        .name           = "at91sam9g45_dma",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &hdmac_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = hdmac_resources,
-        .num_resources  = ARRAY_SIZE(hdmac_resources),
-};
-void __init at91_add_device_hdmac(void)
-{
-        platform_device_register(&at_hdmac_device);
-}
-#else
-void __init at91_add_device_hdmac(void) {}
-#endif
-/* --------------------------------------------------------------------
- *  USB Host (OHCI)
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static u64 ohci_dmamask = DMA_BIT_MASK(32);
-static struct at91_usbh_data usbh_ohci_data;
-static struct resource usbh_ohci_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_OHCI_BASE,
-                .end    = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91_usbh_ohci_device = {
-        .name           = "at91_ohci",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &ohci_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &usbh_ohci_data,
-        },
-        .resource       = usbh_ohci_resources,
-        .num_resources  = ARRAY_SIZE(usbh_ohci_resources),
-};
-void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
-{
-        int i;
-        if (!data)
-                return;
-        /* Enable VBus control for UHP ports */
-        for (i = 0; i < data->ports; i++) {
-                if (gpio_is_valid(data->vbus_pin[i]))
-                        at91_set_gpio_output(data->vbus_pin[i],
-                                             data->vbus_pin_active_low[i]);
-        }
-        /* Enable overcurrent notification */
-        for (i = 0; i < data->ports; i++) {
-                if (gpio_is_valid(data->overcurrent_pin[i]))
-                        at91_set_gpio_input(data->overcurrent_pin[i], 1);
-        }
-        usbh_ohci_data = *data;
-        platform_device_register(&at91_usbh_ohci_device);
-}
-#else
-void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  USB Host HS (EHCI)
- *  Needs an OHCI host for low and full speed management
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
-static u64 ehci_dmamask = DMA_BIT_MASK(32);
-static struct at91_usbh_data usbh_ehci_data;
-static struct resource usbh_ehci_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_EHCI_BASE,
-                .end    = AT91SAM9G45_EHCI_BASE + SZ_1M - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91_usbh_ehci_device = {
-        .name           = "atmel-ehci",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &ehci_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &usbh_ehci_data,
-        },
-        .resource       = usbh_ehci_resources,
-        .num_resources  = ARRAY_SIZE(usbh_ehci_resources),
-};
-void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
-{
-        int i;
-        if (!data)
-                return;
-        /* Enable VBus control for UHP ports */
-        for (i = 0; i < data->ports; i++) {
-                if (gpio_is_valid(data->vbus_pin[i]))
-                        at91_set_gpio_output(data->vbus_pin[i],
-                                             data->vbus_pin_active_low[i]);
-        }
-        usbh_ehci_data = *data;
-        platform_device_register(&at91_usbh_ehci_device);
-}
-#else
-void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  USB HS Device (Gadget)
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
-static struct resource usba_udc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_UDPHS_FIFO,
-                .end    = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91SAM9G45_BASE_UDPHS,
-                .end    = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-#define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
-        [idx] = {                                               \
-                .name           = nam,                          \
-                .index          = idx,                          \
-                .fifo_size      = maxpkt,                       \
-                .nr_banks       = maxbk,                        \
-                .can_dma        = dma,                          \
-                .can_isoc       = isoc,                         \
-        }
-static struct usba_ep_data usba_udc_ep[] __initdata = {
-        EP("ep0", 0, 64, 1, 0, 0),
-        EP("ep1", 1, 1024, 2, 1, 1),
-        EP("ep2", 2, 1024, 2, 1, 1),
-        EP("ep3", 3, 1024, 3, 1, 0),
-        EP("ep4", 4, 1024, 3, 1, 0),
-        EP("ep5", 5, 1024, 3, 1, 1),
-        EP("ep6", 6, 1024, 3, 1, 1),
-};
-#undef EP
-/*
- * pdata doesn't have room for any endpoints, so we need to
- * append room for the ones we need right after it.
- */
-static struct {
-        struct usba_platform_data pdata;
-        struct usba_ep_data ep[7];
-} usba_udc_data;
-static struct platform_device at91_usba_udc_device = {
-        .name           = "atmel_usba_udc",
-        .id             = -1,
-        .dev            = {
-                                .platform_data  = &usba_udc_data.pdata,
-        },
-        .resource       = usba_udc_resources,
-        .num_resources  = ARRAY_SIZE(usba_udc_resources),
-};
-void __init at91_add_device_usba(struct usba_platform_data *data)
-{
-        usba_udc_data.pdata.vbus_pin = -EINVAL;
-        usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
-        memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
-        if (data && gpio_is_valid(data->vbus_pin)) {
-                at91_set_gpio_input(data->vbus_pin, 0);
-                at91_set_deglitch(data->vbus_pin, 1);
-                usba_udc_data.pdata.vbus_pin = data->vbus_pin;
-        }
-        /* Pullup pin is handled internally by USB device peripheral */
-        platform_device_register(&at91_usba_udc_device);
-}
-#else
-void __init at91_add_device_usba(struct usba_platform_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  Ethernet
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
-static u64 eth_dmamask = DMA_BIT_MASK(32);
-static struct macb_platform_data eth_data;
-static struct resource eth_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_EMAC,
-                .end    = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9g45_eth_device = {
-        .name           = "macb",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &eth_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &eth_data,
-        },
-        .resource       = eth_resources,
-        .num_resources  = ARRAY_SIZE(eth_resources),
-};
-void __init at91_add_device_eth(struct macb_platform_data *data)
-{
-        if (!data)
-                return;
-        if (gpio_is_valid(data->phy_irq_pin)) {
-                at91_set_gpio_input(data->phy_irq_pin, 0);
-                at91_set_deglitch(data->phy_irq_pin, 1);
-        }
-        /* Pins used for MII and RMII */
-        at91_set_A_periph(AT91_PIN_PA17, 0);    /* ETXCK_EREFCK */
-        at91_set_A_periph(AT91_PIN_PA15, 0);    /* ERXDV */
-        at91_set_A_periph(AT91_PIN_PA12, 0);    /* ERX0 */
-        at91_set_A_periph(AT91_PIN_PA13, 0);    /* ERX1 */
-        at91_set_A_periph(AT91_PIN_PA16, 0);    /* ERXER */
-        at91_set_A_periph(AT91_PIN_PA14, 0);    /* ETXEN */
-        at91_set_A_periph(AT91_PIN_PA10, 0);    /* ETX0 */
-        at91_set_A_periph(AT91_PIN_PA11, 0);    /* ETX1 */
-        at91_set_A_periph(AT91_PIN_PA19, 0);    /* EMDIO */
-        at91_set_A_periph(AT91_PIN_PA18, 0);    /* EMDC */
-        if (!data->is_rmii) {
-                at91_set_B_periph(AT91_PIN_PA29, 0);    /* ECRS */
-                at91_set_B_periph(AT91_PIN_PA30, 0);    /* ECOL */
-                at91_set_B_periph(AT91_PIN_PA8,  0);    /* ERX2 */
-                at91_set_B_periph(AT91_PIN_PA9,  0);    /* ERX3 */
-                at91_set_B_periph(AT91_PIN_PA28, 0);    /* ERXCK */
-                at91_set_B_periph(AT91_PIN_PA6,  0);    /* ETX2 */
-                at91_set_B_periph(AT91_PIN_PA7,  0);    /* ETX3 */
-                at91_set_B_periph(AT91_PIN_PA27, 0);    /* ETXER */
-        }
-        eth_data = *data;
-        platform_device_register(&at91sam9g45_eth_device);
-}
-#else
-void __init at91_add_device_eth(struct macb_platform_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  MMC / SD
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
-static u64 mmc_dmamask = DMA_BIT_MASK(32);
-static struct mci_platform_data mmc0_data, mmc1_data;
-static struct resource mmc0_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_MCI0,
-                .end    = AT91SAM9G45_BASE_MCI0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9g45_mmc0_device = {
-        .name           = "atmel_mci",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &mmc_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &mmc0_data,
-        },
-        .resource       = mmc0_resources,
-        .num_resources  = ARRAY_SIZE(mmc0_resources),
-};
-static struct resource mmc1_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_MCI1,
-                .end    = AT91SAM9G45_BASE_MCI1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9g45_mmc1_device = {
-        .name           = "atmel_mci",
-        .id             = 1,
-        .dev            = {
-                                .dma_mask               = &mmc_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &mmc1_data,
-        },
-        .resource       = mmc1_resources,
-        .num_resources  = ARRAY_SIZE(mmc1_resources),
-};
-/* Consider only one slot : slot 0 */
-void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
-{
-        if (!data)
-                return;
-        /* Must have at least one usable slot */
-        if (!data->slot[0].bus_width)
-                return;
-#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
-        {
-        struct at_dma_slave     *atslave;
-        struct mci_dma_data     *alt_atslave;
-        alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
-        atslave = &alt_atslave->sdata;
-        /* DMA slave channel configuration */
-        atslave->dma_dev = &at_hdmac_device.dev;
-        atslave->cfg = ATC_FIFOCFG_HALFFIFO
-                        | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
-        if (mmc_id == 0)        /* MCI0 */
-                atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
-                              | ATC_DST_PER(AT_DMA_ID_MCI0);
-        else                    /* MCI1 */
-                atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1)
-                              | ATC_DST_PER(AT_DMA_ID_MCI1);
-        data->dma_slave = alt_atslave;
-        }
-#endif
-        /* input/irq */
-        if (gpio_is_valid(data->slot[0].detect_pin)) {
-                at91_set_gpio_input(data->slot[0].detect_pin, 1);
-                at91_set_deglitch(data->slot[0].detect_pin, 1);
-        }
-        if (gpio_is_valid(data->slot[0].wp_pin))
-                at91_set_gpio_input(data->slot[0].wp_pin, 1);
-        if (mmc_id == 0) {              /* MCI0 */
-                /* CLK */
-                at91_set_A_periph(AT91_PIN_PA0, 0);
-                /* CMD */
-                at91_set_A_periph(AT91_PIN_PA1, 1);
-                /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
-                at91_set_A_periph(AT91_PIN_PA2, 1);
-                if (data->slot[0].bus_width == 4) {
-                        at91_set_A_periph(AT91_PIN_PA3, 1);
-                        at91_set_A_periph(AT91_PIN_PA4, 1);
-                        at91_set_A_periph(AT91_PIN_PA5, 1);
-                        if (data->slot[0].bus_width == 8) {
-                                at91_set_A_periph(AT91_PIN_PA6, 1);
-                                at91_set_A_periph(AT91_PIN_PA7, 1);
-                                at91_set_A_periph(AT91_PIN_PA8, 1);
-                                at91_set_A_periph(AT91_PIN_PA9, 1);
-                        }
-                }
-                mmc0_data = *data;
-                platform_device_register(&at91sam9g45_mmc0_device);
-        } else {                        /* MCI1 */
-                /* CLK */
-                at91_set_A_periph(AT91_PIN_PA31, 0);
-                /* CMD */
-                at91_set_A_periph(AT91_PIN_PA22, 1);
-                /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
-                at91_set_A_periph(AT91_PIN_PA23, 1);
-                if (data->slot[0].bus_width == 4) {
-                        at91_set_A_periph(AT91_PIN_PA24, 1);
-                        at91_set_A_periph(AT91_PIN_PA25, 1);
-                        at91_set_A_periph(AT91_PIN_PA26, 1);
-                        if (data->slot[0].bus_width == 8) {
-                                at91_set_A_periph(AT91_PIN_PA27, 1);
-                                at91_set_A_periph(AT91_PIN_PA28, 1);
-                                at91_set_A_periph(AT91_PIN_PA29, 1);
-                                at91_set_A_periph(AT91_PIN_PA30, 1);
-                        }
-                }
-                mmc1_data = *data;
-                platform_device_register(&at91sam9g45_mmc1_device);
-        }
-}
-#else
-void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  NAND / SmartMedia
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
-static struct atmel_nand_data nand_data;
-#define NAND_BASE       AT91_CHIPSELECT_3
-static struct resource nand_resources[] = {
-        [0] = {
-                .start  = NAND_BASE,
-                .end    = NAND_BASE + SZ_256M - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91SAM9G45_BASE_ECC,
-                .end    = AT91SAM9G45_BASE_ECC + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct platform_device at91sam9g45_nand_device = {
-        .name           = "atmel_nand",
-        .id             = -1,
-        .dev            = {
-                                .platform_data  = &nand_data,
-        },
-        .resource       = nand_resources,
-        .num_resources  = ARRAY_SIZE(nand_resources),
-};
-void __init at91_add_device_nand(struct atmel_nand_data *data)
-{
-        unsigned long csa;
-        if (!data)
-                return;
-        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
-        at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
-        /* enable pin */
-        if (gpio_is_valid(data->enable_pin))
-                at91_set_gpio_output(data->enable_pin, 1);
-        /* ready/busy pin */
-        if (gpio_is_valid(data->rdy_pin))
-                at91_set_gpio_input(data->rdy_pin, 1);
-        /* card detect pin */
-        if (gpio_is_valid(data->det_pin))
-                at91_set_gpio_input(data->det_pin, 1);
-        nand_data = *data;
-        platform_device_register(&at91sam9g45_nand_device);
-}
-#else
-void __init at91_add_device_nand(struct atmel_nand_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  TWI (i2c)
- * -------------------------------------------------------------------- */
-/*
- * Prefer the GPIO code since the TWI controller isn't robust
- * (gets overruns and underruns under load) and can only issue
- * repeated STARTs in one scenario (the driver doesn't yet handle them).
- */
-#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
-static struct i2c_gpio_platform_data pdata_i2c0 = {
-        .sda_pin                = AT91_PIN_PA20,
-        .sda_is_open_drain      = 1,
-        .scl_pin                = AT91_PIN_PA21,
-        .scl_is_open_drain      = 1,
-        .udelay                 = 5,            /* ~100 kHz */
-};
-static struct platform_device at91sam9g45_twi0_device = {
-        .name                   = "i2c-gpio",
-        .id                     = 0,
-        .dev.platform_data      = &pdata_i2c0,
-};
-static struct i2c_gpio_platform_data pdata_i2c1 = {
-        .sda_pin                = AT91_PIN_PB10,
-        .sda_is_open_drain      = 1,
-        .scl_pin                = AT91_PIN_PB11,
-        .scl_is_open_drain      = 1,
-        .udelay                 = 5,            /* ~100 kHz */
-};
-static struct platform_device at91sam9g45_twi1_device = {
-        .name                   = "i2c-gpio",
-        .id                     = 1,
-        .dev.platform_data      = &pdata_i2c1,
-};
-void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
-{
-        i2c_register_board_info(i2c_id, devices, nr_devices);
-        if (i2c_id == 0) {
-                at91_set_GPIO_periph(AT91_PIN_PA20, 1);         /* TWD (SDA) */
-                at91_set_multi_drive(AT91_PIN_PA20, 1);
-                at91_set_GPIO_periph(AT91_PIN_PA21, 1);         /* TWCK (SCL) */
-                at91_set_multi_drive(AT91_PIN_PA21, 1);
-                platform_device_register(&at91sam9g45_twi0_device);
-        } else {
-                at91_set_GPIO_periph(AT91_PIN_PB10, 1);         /* TWD (SDA) */
-                at91_set_multi_drive(AT91_PIN_PB10, 1);
-                at91_set_GPIO_periph(AT91_PIN_PB11, 1);         /* TWCK (SCL) */
-                at91_set_multi_drive(AT91_PIN_PB11, 1);
-                platform_device_register(&at91sam9g45_twi1_device);
-        }
-}
-#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
-static struct resource twi0_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_TWI0,
-                .end    = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9g45_twi0_device = {
-        .name           = "i2c-at91sam9g10",
-        .id             = 0,
-        .resource       = twi0_resources,
-        .num_resources  = ARRAY_SIZE(twi0_resources),
-};
-static struct resource twi1_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_TWI1,
-                .end    = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9g45_twi1_device = {
-        .name           = "i2c-at91sam9g10",
-        .id             = 1,
-        .resource       = twi1_resources,
-        .num_resources  = ARRAY_SIZE(twi1_resources),
-};
-void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
-{
-        i2c_register_board_info(i2c_id, devices, nr_devices);
-        /* pins used for TWI interface */
-        if (i2c_id == 0) {
-                at91_set_A_periph(AT91_PIN_PA20, 0);            /* TWD */
-                at91_set_A_periph(AT91_PIN_PA21, 0);            /* TWCK */
-                platform_device_register(&at91sam9g45_twi0_device);
-        } else {
-                at91_set_A_periph(AT91_PIN_PB10, 0);            /* TWD */
-                at91_set_A_periph(AT91_PIN_PB11, 0);            /* TWCK */
-                platform_device_register(&at91sam9g45_twi1_device);
-        }
-}
-#else
-void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
-#endif
-/* --------------------------------------------------------------------
- *  SPI
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
-static u64 spi_dmamask = DMA_BIT_MASK(32);
-static struct resource spi0_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_SPI0,
-                .end    = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9g45_spi0_device = {
-        .name           = "atmel_spi",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &spi_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = spi0_resources,
-        .num_resources  = ARRAY_SIZE(spi0_resources),
-};
-static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
-static struct resource spi1_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_SPI1,
-                .end    = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9g45_spi1_device = {
-        .name           = "atmel_spi",
-        .id             = 1,
-        .dev            = {
-                                .dma_mask               = &spi_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = spi1_resources,
-        .num_resources  = ARRAY_SIZE(spi1_resources),
-};
-static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
-void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
-{
-        int i;
-        unsigned long cs_pin;
-        short enable_spi0 = 0;
-        short enable_spi1 = 0;
-        /* Choose SPI chip-selects */
-        for (i = 0; i < nr_devices; i++) {
-                if (devices[i].controller_data)
-                        cs_pin = (unsigned long) devices[i].controller_data;
-                else if (devices[i].bus_num == 0)
-                        cs_pin = spi0_standard_cs[devices[i].chip_select];
-                else
-                        cs_pin = spi1_standard_cs[devices[i].chip_select];
-                if (!gpio_is_valid(cs_pin))
-                        continue;
-                if (devices[i].bus_num == 0)
-                        enable_spi0 = 1;
-                else
-                        enable_spi1 = 1;
-                /* enable chip-select pin */
-                at91_set_gpio_output(cs_pin, 1);
-                /* pass chip-select pin to driver */
-                devices[i].controller_data = (void *) cs_pin;
-        }
-        spi_register_board_info(devices, nr_devices);
-        /* Configure SPI bus(es) */
-        if (enable_spi0) {
-                at91_set_A_periph(AT91_PIN_PB0, 0);     /* SPI0_MISO */
-                at91_set_A_periph(AT91_PIN_PB1, 0);     /* SPI0_MOSI */
-                at91_set_A_periph(AT91_PIN_PB2, 0);     /* SPI0_SPCK */
-                platform_device_register(&at91sam9g45_spi0_device);
-        }
-        if (enable_spi1) {
-                at91_set_A_periph(AT91_PIN_PB14, 0);    /* SPI1_MISO */
-                at91_set_A_periph(AT91_PIN_PB15, 0);    /* SPI1_MOSI */
-                at91_set_A_periph(AT91_PIN_PB16, 0);    /* SPI1_SPCK */
-                platform_device_register(&at91sam9g45_spi1_device);
-        }
-}
-#else
-void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
-#endif
-/* --------------------------------------------------------------------
- *  AC97
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
-static u64 ac97_dmamask = DMA_BIT_MASK(32);
-static struct ac97c_platform_data ac97_data;
-static struct resource ac97_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_AC97C,
-                .end    = AT91SAM9G45_BASE_AC97C + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9g45_ac97_device = {
-        .name           = "atmel_ac97c",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &ac97_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &ac97_data,
-        },
-        .resource       = ac97_resources,
-        .num_resources  = ARRAY_SIZE(ac97_resources),
-};
-void __init at91_add_device_ac97(struct ac97c_platform_data *data)
-{
-        if (!data)
-                return;
-        at91_set_A_periph(AT91_PIN_PD8, 0);     /* AC97FS */
-        at91_set_A_periph(AT91_PIN_PD9, 0);     /* AC97CK */
-        at91_set_A_periph(AT91_PIN_PD7, 0);     /* AC97TX */
-        at91_set_A_periph(AT91_PIN_PD6, 0);     /* AC97RX */
-        /* reset */
-        if (gpio_is_valid(data->reset_pin))
-                at91_set_gpio_output(data->reset_pin, 0);
-        ac97_data = *data;
-        platform_device_register(&at91sam9g45_ac97_device);
-}
-#else
-void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  Image Sensor Interface
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
-static u64 isi_dmamask = DMA_BIT_MASK(32);
-static struct isi_platform_data isi_data;
-struct resource isi_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_ISI,
-                .end    = AT91SAM9G45_BASE_ISI + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9g45_isi_device = {
-        .name           = "atmel_isi",
-        .id             = 0,
-        .dev            = {
-                        .dma_mask               = &isi_dmamask,
-                        .coherent_dma_mask      = DMA_BIT_MASK(32),
-                        .platform_data          = &isi_data,
-        },
-        .resource       = isi_resources,
-        .num_resources  = ARRAY_SIZE(isi_resources),
-};
-static struct clk_lookup isi_mck_lookups[] = {
-        CLKDEV_CON_DEV_ID("isi_mck", "atmel_isi.0", NULL),
-};
-void __init at91_add_device_isi(struct isi_platform_data *data,
-                bool use_pck_as_mck)
-{
-        struct clk *pck;
-        struct clk *parent;
-        if (!data)
-                return;
-        isi_data = *data;
-        at91_set_A_periph(AT91_PIN_PB20, 0);    /* ISI_D0 */
-        at91_set_A_periph(AT91_PIN_PB21, 0);    /* ISI_D1 */
-        at91_set_A_periph(AT91_PIN_PB22, 0);    /* ISI_D2 */
-        at91_set_A_periph(AT91_PIN_PB23, 0);    /* ISI_D3 */
-        at91_set_A_periph(AT91_PIN_PB24, 0);    /* ISI_D4 */
-        at91_set_A_periph(AT91_PIN_PB25, 0);    /* ISI_D5 */
-        at91_set_A_periph(AT91_PIN_PB26, 0);    /* ISI_D6 */
-        at91_set_A_periph(AT91_PIN_PB27, 0);    /* ISI_D7 */
-        at91_set_A_periph(AT91_PIN_PB28, 0);    /* ISI_PCK */
-        at91_set_A_periph(AT91_PIN_PB30, 0);    /* ISI_HSYNC */
-        at91_set_A_periph(AT91_PIN_PB29, 0);    /* ISI_VSYNC */
-        at91_set_B_periph(AT91_PIN_PB8, 0);     /* ISI_PD8 */
-        at91_set_B_periph(AT91_PIN_PB9, 0);     /* ISI_PD9 */
-        at91_set_B_periph(AT91_PIN_PB10, 0);    /* ISI_PD10 */
-        at91_set_B_periph(AT91_PIN_PB11, 0);    /* ISI_PD11 */
-        platform_device_register(&at91sam9g45_isi_device);
-        if (use_pck_as_mck) {
-                at91_set_B_periph(AT91_PIN_PB31, 0);    /* ISI_MCK (PCK1) */
-                pck = clk_get(NULL, "pck1");
-                parent = clk_get(NULL, "plla");
-                BUG_ON(IS_ERR(pck) || IS_ERR(parent));
-                if (clk_set_parent(pck, parent)) {
-                        pr_err("Failed to set PCK's parent\n");
-                } else {
-                        /* Register PCK as ISI_MCK */
-                        isi_mck_lookups[0].clk = pck;
-                        clkdev_add_table(isi_mck_lookups,
-                                        ARRAY_SIZE(isi_mck_lookups));
-                }
-                clk_put(pck);
-                clk_put(parent);
-        }
-}
-#else
-void __init at91_add_device_isi(struct isi_platform_data *data,
-                bool use_pck_as_mck) {}
-#endif
-/* --------------------------------------------------------------------
- *  LCD Controller
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
-static u64 lcdc_dmamask = DMA_BIT_MASK(32);
-static struct atmel_lcdfb_pdata lcdc_data;
-static struct resource lcdc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_LCDC_BASE,
-                .end    = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91_lcdc_device = {
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &lcdc_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &lcdc_data,
-        },
-        .resource       = lcdc_resources,
-        .num_resources  = ARRAY_SIZE(lcdc_resources),
-};
-void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data)
-{
-        if (!data)
-                return;
-        if (cpu_is_at91sam9g45es())
-                at91_lcdc_device.name = "at91sam9g45es-lcdfb";
-        else
-                at91_lcdc_device.name = "at91sam9g45-lcdfb";
-        at91_set_A_periph(AT91_PIN_PE0, 0);     /* LCDDPWR */
-        at91_set_A_periph(AT91_PIN_PE2, 0);     /* LCDCC */
-        at91_set_A_periph(AT91_PIN_PE3, 0);     /* LCDVSYNC */
-        at91_set_A_periph(AT91_PIN_PE4, 0);     /* LCDHSYNC */
-        at91_set_A_periph(AT91_PIN_PE5, 0);     /* LCDDOTCK */
-        at91_set_A_periph(AT91_PIN_PE6, 0);     /* LCDDEN */
-        at91_set_A_periph(AT91_PIN_PE7, 0);     /* LCDD0 */
-        at91_set_A_periph(AT91_PIN_PE8, 0);     /* LCDD1 */
-        at91_set_A_periph(AT91_PIN_PE9, 0);     /* LCDD2 */
-        at91_set_A_periph(AT91_PIN_PE10, 0);    /* LCDD3 */
-        at91_set_A_periph(AT91_PIN_PE11, 0);    /* LCDD4 */
-        at91_set_A_periph(AT91_PIN_PE12, 0);    /* LCDD5 */
-        at91_set_A_periph(AT91_PIN_PE13, 0);    /* LCDD6 */
-        at91_set_A_periph(AT91_PIN_PE14, 0);    /* LCDD7 */
-        at91_set_A_periph(AT91_PIN_PE15, 0);    /* LCDD8 */
-        at91_set_A_periph(AT91_PIN_PE16, 0);    /* LCDD9 */
-        at91_set_A_periph(AT91_PIN_PE17, 0);    /* LCDD10 */
-        at91_set_A_periph(AT91_PIN_PE18, 0);    /* LCDD11 */
-        at91_set_A_periph(AT91_PIN_PE19, 0);    /* LCDD12 */
-        at91_set_A_periph(AT91_PIN_PE20, 0);    /* LCDD13 */
-        at91_set_A_periph(AT91_PIN_PE21, 0);    /* LCDD14 */
-        at91_set_A_periph(AT91_PIN_PE22, 0);    /* LCDD15 */
-        at91_set_A_periph(AT91_PIN_PE23, 0);    /* LCDD16 */
-        at91_set_A_periph(AT91_PIN_PE24, 0);    /* LCDD17 */
-        at91_set_A_periph(AT91_PIN_PE25, 0);    /* LCDD18 */
-        at91_set_A_periph(AT91_PIN_PE26, 0);    /* LCDD19 */
-        at91_set_A_periph(AT91_PIN_PE27, 0);    /* LCDD20 */
-        at91_set_A_periph(AT91_PIN_PE28, 0);    /* LCDD21 */
-        at91_set_A_periph(AT91_PIN_PE29, 0);    /* LCDD22 */
-        at91_set_A_periph(AT91_PIN_PE30, 0);    /* LCDD23 */
-        lcdc_data = *data;
-        platform_device_register(&at91_lcdc_device);
-}
-#else
-void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  Timer/Counter block
- * -------------------------------------------------------------------- */
-#ifdef CONFIG_ATMEL_TCLIB
-static struct resource tcb0_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_TCB0,
-                .end    = AT91SAM9G45_BASE_TCB0 + SZ_256 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9g45_tcb0_device = {
-        .name           = "atmel_tcb",
-        .id             = 0,
-        .resource       = tcb0_resources,
-        .num_resources  = ARRAY_SIZE(tcb0_resources),
-};
-/* TCB1 begins with TC3 */
-static struct resource tcb1_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_TCB1,
-                .end    = AT91SAM9G45_BASE_TCB1 + SZ_256 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9g45_tcb1_device = {
-        .name           = "atmel_tcb",
-        .id             = 1,
-        .resource       = tcb1_resources,
-        .num_resources  = ARRAY_SIZE(tcb1_resources),
-};
-static void __init at91_add_device_tc(void)
-{
-        platform_device_register(&at91sam9g45_tcb0_device);
-        platform_device_register(&at91sam9g45_tcb1_device);
-}
-#else
-static void __init at91_add_device_tc(void) { }
-#endif
-/* --------------------------------------------------------------------
- *  RTC
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
-static struct resource rtc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_RTC,
-                .end    = AT91SAM9G45_BASE_RTC + SZ_256 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
-                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9g45_rtc_device = {
-        .name           = "at91_rtc",
-        .id             = -1,
-        .resource       = rtc_resources,
-        .num_resources  = ARRAY_SIZE(rtc_resources),
-};
-static void __init at91_add_device_rtc(void)
-{
-        platform_device_register(&at91sam9g45_rtc_device);
-}
-#else
-static void __init at91_add_device_rtc(void) {}
-#endif
-/* --------------------------------------------------------------------
- *  ADC and touchscreen
- * -------------------------------------------------------------------- */
-#if IS_ENABLED(CONFIG_AT91_ADC)
-static struct at91_adc_data adc_data;
-static struct resource adc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_TSC,
-                .end    = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-static struct platform_device at91_adc_device = {
-        .name           = "at91sam9g45-adc",
-        .id             = -1,
-        .dev            = {
-                                .platform_data  = &adc_data,
-        },
-        .resource       = adc_resources,
-        .num_resources  = ARRAY_SIZE(adc_resources),
-};
-static struct at91_adc_trigger at91_adc_triggers[] = {
-        [0] = {
-                .name = "external-rising",
-                .value = 1,
-                .is_external = true,
-        },
-        [1] = {
-                .name = "external-falling",
-                .value = 2,
-                .is_external = true,
-        },
-        [2] = {
-                .name = "external-any",
-                .value = 3,
-                .is_external = true,
-        },
-        [3] = {
-                .name = "continuous",
-                .value = 6,
-                .is_external = false,
-        },
-};
-void __init at91_add_device_adc(struct at91_adc_data *data)
-{
-        if (!data)
-                return;
-        if (test_bit(0, &data->channels_used))
-                at91_set_gpio_input(AT91_PIN_PD20, 0);
-        if (test_bit(1, &data->channels_used))
-                at91_set_gpio_input(AT91_PIN_PD21, 0);
-        if (test_bit(2, &data->channels_used))
-                at91_set_gpio_input(AT91_PIN_PD22, 0);
-        if (test_bit(3, &data->channels_used))
-                at91_set_gpio_input(AT91_PIN_PD23, 0);
-        if (test_bit(4, &data->channels_used))
-                at91_set_gpio_input(AT91_PIN_PD24, 0);
-        if (test_bit(5, &data->channels_used))
-                at91_set_gpio_input(AT91_PIN_PD25, 0);
-        if (test_bit(6, &data->channels_used))
-                at91_set_gpio_input(AT91_PIN_PD26, 0);
-        if (test_bit(7, &data->channels_used))
-                at91_set_gpio_input(AT91_PIN_PD27, 0);
-        if (data->use_external_triggers)
-                at91_set_A_periph(AT91_PIN_PD28, 0);
-        data->startup_time = 40;
-        data->trigger_number = 4;
-        data->trigger_list = at91_adc_triggers;
-        adc_data = *data;
-        platform_device_register(&at91_adc_device);
-}
-#else
-void __init at91_add_device_adc(struct at91_adc_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  RTT
- * -------------------------------------------------------------------- */
-static struct resource rtt_resources[] = {
-        {
-                .start  = AT91SAM9G45_BASE_RTT,
-                .end    = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-static struct platform_device at91sam9g45_rtt_device = {
-        .name           = "at91_rtt",
-        .id             = 0,
-        .resource       = rtt_resources,
-};
-#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
-static void __init at91_add_device_rtt_rtc(void)
-{
-        at91sam9g45_rtt_device.name = "rtc-at91sam9";
-        /*
-         * The second resource is needed:
-         * GPBR will serve as the storage for RTC time offset
-         */
-        at91sam9g45_rtt_device.num_resources = 3;
-        rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
-                                 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
-        rtt_resources[1].end = rtt_resources[1].start + 3;
-        rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
-        rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
-}
-#else
-static void __init at91_add_device_rtt_rtc(void)
-{
-        /* Only one resource is needed: RTT not used as RTC */
-        at91sam9g45_rtt_device.num_resources = 1;
-}
-#endif
-static void __init at91_add_device_rtt(void)
-{
-        at91_add_device_rtt_rtc();
-        platform_device_register(&at91sam9g45_rtt_device);
-}
-/* --------------------------------------------------------------------
- *  TRNG
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_HW_RANDOM_ATMEL) || defined(CONFIG_HW_RANDOM_ATMEL_MODULE)
-static struct resource trng_resources[] = {
-        {
-                .start  = AT91SAM9G45_BASE_TRNG,
-                .end    = AT91SAM9G45_BASE_TRNG + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device at91sam9g45_trng_device = {
-        .name           = "atmel-trng",
-        .id             = -1,
-        .resource       = trng_resources,
-        .num_resources  = ARRAY_SIZE(trng_resources),
-};
-static void __init at91_add_device_trng(void)
-{
-        platform_device_register(&at91sam9g45_trng_device);
-}
-#else
-static void __init at91_add_device_trng(void) {}
-#endif
-/* --------------------------------------------------------------------
- *  Watchdog
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
-static struct resource wdt_resources[] = {
-        {
-                .start  = AT91SAM9G45_BASE_WDT,
-                .end    = AT91SAM9G45_BASE_WDT + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct platform_device at91sam9g45_wdt_device = {
-        .name           = "at91_wdt",
-        .id             = -1,
-        .resource       = wdt_resources,
-        .num_resources  = ARRAY_SIZE(wdt_resources),
-};
-static void __init at91_add_device_watchdog(void)
-{
-        platform_device_register(&at91sam9g45_wdt_device);
-}
-#else
-static void __init at91_add_device_watchdog(void) {}
-#endif
-/* --------------------------------------------------------------------
- *  PWM
- * --------------------------------------------------------------------*/
-#if IS_ENABLED(CONFIG_PWM_ATMEL)
-static struct resource pwm_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_PWMC,
-                .end    = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9g45_pwm0_device = {
-        .name   = "at91sam9rl-pwm",
-        .id     = -1,
-        .resource       = pwm_resources,
-        .num_resources  = ARRAY_SIZE(pwm_resources),
-};
-void __init at91_add_device_pwm(u32 mask)
-{
-        if (mask & (1 << AT91_PWM0))
-                at91_set_B_periph(AT91_PIN_PD24, 1);    /* enable PWM0 */
-        if (mask & (1 << AT91_PWM1))
-                at91_set_B_periph(AT91_PIN_PD31, 1);    /* enable PWM1 */
-        if (mask & (1 << AT91_PWM2))
-                at91_set_B_periph(AT91_PIN_PD26, 1);    /* enable PWM2 */
-        if (mask & (1 << AT91_PWM3))
-                at91_set_B_periph(AT91_PIN_PD0, 1);     /* enable PWM3 */
-        platform_device_register(&at91sam9g45_pwm0_device);
-}
-#else
-void __init at91_add_device_pwm(u32 mask) {}
-#endif
-/* --------------------------------------------------------------------
- *  SSC -- Synchronous Serial Controller
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
-static u64 ssc0_dmamask = DMA_BIT_MASK(32);
-static struct resource ssc0_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_SSC0,
-                .end    = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9g45_ssc0_device = {
-        .name   = "at91sam9g45_ssc",
-        .id     = 0,
-        .dev    = {
-                .dma_mask               = &ssc0_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = ssc0_resources,
-        .num_resources  = ARRAY_SIZE(ssc0_resources),
-};
-static inline void configure_ssc0_pins(unsigned pins)
-{
-        if (pins & ATMEL_SSC_TF)
-                at91_set_A_periph(AT91_PIN_PD1, 1);
-        if (pins & ATMEL_SSC_TK)
-                at91_set_A_periph(AT91_PIN_PD0, 1);
-        if (pins & ATMEL_SSC_TD)
-                at91_set_A_periph(AT91_PIN_PD2, 1);
-        if (pins & ATMEL_SSC_RD)
-                at91_set_A_periph(AT91_PIN_PD3, 1);
-        if (pins & ATMEL_SSC_RK)
-                at91_set_A_periph(AT91_PIN_PD4, 1);
-        if (pins & ATMEL_SSC_RF)
-                at91_set_A_periph(AT91_PIN_PD5, 1);
-}
-static u64 ssc1_dmamask = DMA_BIT_MASK(32);
-static struct resource ssc1_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_SSC1,
-                .end    = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9g45_ssc1_device = {
-        .name   = "at91sam9g45_ssc",
-        .id     = 1,
-        .dev    = {
-                .dma_mask               = &ssc1_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = ssc1_resources,
-        .num_resources  = ARRAY_SIZE(ssc1_resources),
-};
-static inline void configure_ssc1_pins(unsigned pins)
-{
-        if (pins & ATMEL_SSC_TF)
-                at91_set_A_periph(AT91_PIN_PD14, 1);
-        if (pins & ATMEL_SSC_TK)
-                at91_set_A_periph(AT91_PIN_PD12, 1);
-        if (pins & ATMEL_SSC_TD)
-                at91_set_A_periph(AT91_PIN_PD10, 1);
-        if (pins & ATMEL_SSC_RD)
-                at91_set_A_periph(AT91_PIN_PD11, 1);
-        if (pins & ATMEL_SSC_RK)
-                at91_set_A_periph(AT91_PIN_PD13, 1);
-        if (pins & ATMEL_SSC_RF)
-                at91_set_A_periph(AT91_PIN_PD15, 1);
-}
-/*
- * SSC controllers are accessed through library code, instead of any
- * kind of all-singing/all-dancing driver.  For example one could be
- * used by a particular I2S audio codec's driver, while another one
- * on the same system might be used by a custom data capture driver.
- */
-void __init at91_add_device_ssc(unsigned id, unsigned pins)
-{
-        struct platform_device *pdev;
-        /*
-         * NOTE: caller is responsible for passing information matching
-         * "pins" to whatever will be using each particular controller.
-         */
-        switch (id) {
-        case AT91SAM9G45_ID_SSC0:
-                pdev = &at91sam9g45_ssc0_device;
-                configure_ssc0_pins(pins);
-                break;
-        case AT91SAM9G45_ID_SSC1:
-                pdev = &at91sam9g45_ssc1_device;
-                configure_ssc1_pins(pins);
-                break;
-        default:
-                return;
-        }
-        platform_device_register(pdev);
-}
-#else
-void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
-#endif
-/* --------------------------------------------------------------------
- *  UART
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_SERIAL_ATMEL)
-static struct resource dbgu_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_DBGU,
-                .end    = AT91SAM9G45_BASE_DBGU + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
-                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data dbgu_data = {
-        .use_dma_tx     = 0,
-        .use_dma_rx     = 0,
-};
-static u64 dbgu_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9g45_dbgu_device = {
-        .name           = "atmel_usart",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &dbgu_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &dbgu_data,
-        },
-        .resource       = dbgu_resources,
-        .num_resources  = ARRAY_SIZE(dbgu_resources),
-};
-static inline void configure_dbgu_pins(void)
-{
-        at91_set_A_periph(AT91_PIN_PB12, 0);            /* DRXD */
-        at91_set_A_periph(AT91_PIN_PB13, 1);            /* DTXD */
-}
-static struct resource uart0_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_US0,
-                .end    = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart0_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static u64 uart0_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9g45_uart0_device = {
-        .name           = "atmel_usart",
-        .id             = 1,
-        .dev            = {
-                                .dma_mask               = &uart0_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart0_data,
-        },
-        .resource       = uart0_resources,
-        .num_resources  = ARRAY_SIZE(uart0_resources),
-};
-static inline void configure_usart0_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PB19, 1);            /* TXD0 */
-        at91_set_A_periph(AT91_PIN_PB18, 0);            /* RXD0 */
-        if (pins & ATMEL_UART_RTS)
-                at91_set_B_periph(AT91_PIN_PB17, 0);    /* RTS0 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_B_periph(AT91_PIN_PB15, 0);    /* CTS0 */
-}
-static struct resource uart1_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_US1,
-                .end    = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart1_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static u64 uart1_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9g45_uart1_device = {
-        .name           = "atmel_usart",
-        .id             = 2,
-        .dev            = {
-                                .dma_mask               = &uart1_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart1_data,
-        },
-        .resource       = uart1_resources,
-        .num_resources  = ARRAY_SIZE(uart1_resources),
-};
-static inline void configure_usart1_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PB4, 1);             /* TXD1 */
-        at91_set_A_periph(AT91_PIN_PB5, 0);             /* RXD1 */
-        if (pins & ATMEL_UART_RTS)
-                at91_set_A_periph(AT91_PIN_PD16, 0);    /* RTS1 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_A_periph(AT91_PIN_PD17, 0);    /* CTS1 */
-}
-static struct resource uart2_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_US2,
-                .end    = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart2_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static u64 uart2_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9g45_uart2_device = {
-        .name           = "atmel_usart",
-        .id             = 3,
-        .dev            = {
-                                .dma_mask               = &uart2_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart2_data,
-        },
-        .resource       = uart2_resources,
-        .num_resources  = ARRAY_SIZE(uart2_resources),
-};
-static inline void configure_usart2_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PB6, 1);             /* TXD2 */
-        at91_set_A_periph(AT91_PIN_PB7, 0);             /* RXD2 */
-        if (pins & ATMEL_UART_RTS)
-                at91_set_B_periph(AT91_PIN_PC9, 0);     /* RTS2 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_B_periph(AT91_PIN_PC11, 0);    /* CTS2 */
-}
-static struct resource uart3_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_US3,
-                .end    = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart3_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static u64 uart3_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9g45_uart3_device = {
-        .name           = "atmel_usart",
-        .id             = 4,
-        .dev            = {
-                                .dma_mask               = &uart3_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart3_data,
-        },
-        .resource       = uart3_resources,
-        .num_resources  = ARRAY_SIZE(uart3_resources),
-};
-static inline void configure_usart3_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PB8, 1);             /* TXD3 */
-        at91_set_A_periph(AT91_PIN_PB9, 0);             /* RXD3 */
-        if (pins & ATMEL_UART_RTS)
-                at91_set_B_periph(AT91_PIN_PA23, 0);    /* RTS3 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_B_periph(AT91_PIN_PA24, 0);    /* CTS3 */
-}
-static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
-{
-        struct platform_device *pdev;
-        struct atmel_uart_data *pdata;
-        switch (id) {
-                case 0:         /* DBGU */
-                        pdev = &at91sam9g45_dbgu_device;
-                        configure_dbgu_pins();
-                        break;
-                case AT91SAM9G45_ID_US0:
-                        pdev = &at91sam9g45_uart0_device;
-                        configure_usart0_pins(pins);
-                        break;
-                case AT91SAM9G45_ID_US1:
-                        pdev = &at91sam9g45_uart1_device;
-                        configure_usart1_pins(pins);
-                        break;
-                case AT91SAM9G45_ID_US2:
-                        pdev = &at91sam9g45_uart2_device;
-                        configure_usart2_pins(pins);
-                        break;
-                case AT91SAM9G45_ID_US3:
-                        pdev = &at91sam9g45_uart3_device;
-                        configure_usart3_pins(pins);
-                        break;
-                default:
-                        return;
-        }
-        pdata = pdev->dev.platform_data;
-        pdata->num = portnr;            /* update to mapped ID */
-        if (portnr < ATMEL_MAX_UART)
-                at91_uarts[portnr] = pdev;
-}
-void __init at91_add_device_serial(void)
-{
-        int i;
-        for (i = 0; i < ATMEL_MAX_UART; i++) {
-                if (at91_uarts[i])
-                        platform_device_register(at91_uarts[i]);
-        }
-}
-#else
-void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
-void __init at91_add_device_serial(void) {}
-#endif
-/* --------------------------------------------------------------------
- *  SHA1/SHA256
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_CRYPTO_DEV_ATMEL_SHA) || defined(CONFIG_CRYPTO_DEV_ATMEL_SHA_MODULE)
-static struct resource sha_resources[] = {
-        {
-                .start  = AT91SAM9G45_BASE_SHA,
-                .end    = AT91SAM9G45_BASE_SHA + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9g45_sha_device = {
-        .name   = "atmel_sha",
-        .id             = -1,
-        .resource       = sha_resources,
-        .num_resources  = ARRAY_SIZE(sha_resources),
-};
-static void __init at91_add_device_sha(void)
-{
-        platform_device_register(&at91sam9g45_sha_device);
-}
-#else
-static void __init at91_add_device_sha(void) {}
-#endif
-/* --------------------------------------------------------------------
- *  DES/TDES
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_CRYPTO_DEV_ATMEL_TDES) || defined(CONFIG_CRYPTO_DEV_ATMEL_TDES_MODULE)
-static struct resource tdes_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_TDES,
-                .end    = AT91SAM9G45_BASE_TDES + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9g45_tdes_device = {
-        .name   = "atmel_tdes",
-        .id             = -1,
-        .resource       = tdes_resources,
-        .num_resources  = ARRAY_SIZE(tdes_resources),
-};
-static void __init at91_add_device_tdes(void)
-{
-        platform_device_register(&at91sam9g45_tdes_device);
-}
-#else
-static void __init at91_add_device_tdes(void) {}
-#endif
-/* --------------------------------------------------------------------
- *  AES
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_CRYPTO_DEV_ATMEL_AES) || defined(CONFIG_CRYPTO_DEV_ATMEL_AES_MODULE)
-static struct crypto_platform_data aes_data;
-static struct crypto_dma_data alt_atslave;
-static u64 aes_dmamask = DMA_BIT_MASK(32);
-static struct resource aes_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_AES,
-                .end    = AT91SAM9G45_BASE_AES + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9g45_aes_device = {
-        .name   = "atmel_aes",
-        .id             = -1,
-        .dev    = {
-                .dma_mask               = &aes_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data          = &aes_data,
-        },
-        .resource       = aes_resources,
-        .num_resources  = ARRAY_SIZE(aes_resources),
-};
-static void __init at91_add_device_aes(void)
-{
-        struct at_dma_slave     *atslave;
-        /* DMA TX slave channel configuration */
-        atslave = &alt_atslave.txdata;
-        atslave->dma_dev = &at_hdmac_device.dev;
-        atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE  | ATC_SRC_H2SEL_HW |
-                                                ATC_SRC_PER(AT_DMA_ID_AES_RX);
-        /* DMA RX slave channel configuration */
-        atslave = &alt_atslave.rxdata;
-        atslave->dma_dev = &at_hdmac_device.dev;
-        atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE  | ATC_DST_H2SEL_HW |
-                                                ATC_DST_PER(AT_DMA_ID_AES_TX);
-        aes_data.dma_slave = &alt_atslave;
-        platform_device_register(&at91sam9g45_aes_device);
-}
-#else
-static void __init at91_add_device_aes(void) {}
-#endif
-/* -------------------------------------------------------------------- */
-/*
- * These devices are always present and don't need any board-specific
- * setup.
- */
-static int __init at91_add_standard_devices(void)
-{
-        if (of_have_populated_dt())
-                return 0;
-        at91_add_device_hdmac();
-        at91_add_device_rtc();
-        at91_add_device_rtt();
-        at91_add_device_trng();
-        at91_add_device_watchdog();
-        at91_add_device_tc();
-        at91_add_device_sha();
-        at91_add_device_tdes();
-        at91_add_device_aes();
-        return 0;
-}
-arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index c8988fe5ff70..dee569b1987e 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -6,219 +6,11 @@
 * Licensed under GPLv2 or later.
 */
-#include <linux/module.h>
+#include <asm/system_misc.h>
-#include <linux/dma-mapping.h>
+#include <mach/hardware.h>
-#include <linux/clk/at91_pmc.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <mach/at91sam9n12.h>
-#include <mach/cpu.h>
-#include "board.h"
 #include "soc.h"
 #include "generic.h"
-#include "sam9_smc.h"
-#if defined(CONFIG_OLD_CLK_AT91)
-#include "clock.h"
-/* --------------------------------------------------------------------
- *  Clocks
- * -------------------------------------------------------------------- */
-/*
- * The peripheral clocks.
- */
-static struct clk pioAB_clk = {
-        .name           = "pioAB_clk",
-        .pmc_mask       = 1 << AT91SAM9N12_ID_PIOAB,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioCD_clk = {
-        .name           = "pioCD_clk",
-        .pmc_mask       = 1 << AT91SAM9N12_ID_PIOCD,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
-        .name           = "usart0_clk",
-        .pmc_mask       = 1 << AT91SAM9N12_ID_USART0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
-        .name           = "usart1_clk",
-        .pmc_mask       = 1 << AT91SAM9N12_ID_USART1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
-        .name           = "usart2_clk",
-        .pmc_mask       = 1 << AT91SAM9N12_ID_USART2,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart3_clk = {
-        .name           = "usart3_clk",
-        .pmc_mask       = 1 << AT91SAM9N12_ID_USART3,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi0_clk = {
-        .name           = "twi0_clk",
-        .pmc_mask       = 1 << AT91SAM9N12_ID_TWI0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi1_clk = {
-        .name           = "twi1_clk",
-        .pmc_mask       = 1 << AT91SAM9N12_ID_TWI1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc_clk = {
-        .name           = "mci_clk",
-        .pmc_mask       = 1 << AT91SAM9N12_ID_MCI,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
-        .name           = "spi0_clk",
-        .pmc_mask       = 1 << AT91SAM9N12_ID_SPI0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
-        .name           = "spi1_clk",
-        .pmc_mask       = 1 << AT91SAM9N12_ID_SPI1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uart0_clk = {
-        .name           = "uart0_clk",
-        .pmc_mask       = 1 << AT91SAM9N12_ID_UART0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uart1_clk = {
-        .name           = "uart1_clk",
-        .pmc_mask       = 1 << AT91SAM9N12_ID_UART1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tcb_clk = {
-        .name           = "tcb_clk",
-        .pmc_mask       = 1 << AT91SAM9N12_ID_TCB,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pwm_clk = {
-        .name           = "pwm_clk",
-        .pmc_mask       = 1 << AT91SAM9N12_ID_PWM,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk adc_clk = {
-        .name           = "adc_clk",
-        .pmc_mask       = 1 << AT91SAM9N12_ID_ADC,
-        .type   = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma_clk = {
-        .name           = "dma_clk",
-        .pmc_mask       = 1 << AT91SAM9N12_ID_DMA,
-        .type   = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uhp_clk = {
-        .name           = "uhp",
-        .pmc_mask       = 1 << AT91SAM9N12_ID_UHP,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udp_clk = {
-        .name           = "udp_clk",
-        .pmc_mask       = 1 << AT91SAM9N12_ID_UDP,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk lcdc_clk = {
-        .name           = "lcdc_clk",
-        .pmc_mask       = 1 << AT91SAM9N12_ID_LCDC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc_clk = {
-        .name           = "ssc_clk",
-        .pmc_mask       = 1 << AT91SAM9N12_ID_SSC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk *periph_clocks[] __initdata = {
-        &pioAB_clk,
-        &pioCD_clk,
-        &usart0_clk,
-        &usart1_clk,
-        &usart2_clk,
-        &usart3_clk,
-        &twi0_clk,
-        &twi1_clk,
-        &mmc_clk,
-        &spi0_clk,
-        &spi1_clk,
-        &lcdc_clk,
-        &uart0_clk,
-        &uart1_clk,
-        &tcb_clk,
-        &pwm_clk,
-        &adc_clk,
-        &dma_clk,
-        &uhp_clk,
-        &udp_clk,
-        &ssc_clk,
-};
-static struct clk_lookup periph_clocks_lookups[] = {
-        /* lookup table for DT entries */
-        CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
-        CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
-        CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
-        CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
-        CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
-        CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
-        CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc_clk),
-        CLKDEV_CON_DEV_ID(NULL, "f0010000.ssc", &ssc_clk),
-        CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
-        CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
-        CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
-        /* additional fake clock for macb_hclk */
-        CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
-        CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
-        CLKDEV_CON_DEV_ID(NULL, "f8034000.pwm", &pwm_clk),
-};
-/*
- * The two programmable clocks.
- * You must configure pin multiplexing to bring these signals out.
- */
-static struct clk pck0 = {
-        .name           = "pck0",
-        .pmc_mask       = AT91_PMC_PCK0,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 0,
-};
-static struct clk pck1 = {
-        .name           = "pck1",
-        .pmc_mask       = AT91_PMC_PCK1,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 1,
-};
-static void __init at91sam9n12_register_clocks(void)
-{
-        int i;
-        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
-                clk_register(periph_clocks[i]);
-        clk_register(&pck0);
-        clk_register(&pck1);
-        clkdev_add_table(periph_clocks_lookups,
-                         ARRAY_SIZE(periph_clocks_lookups));
-}
-#else
-#define at91sam9n12_register_clocks NULL
-#endif
 /* --------------------------------------------------------------------
 *  AT91SAM9N12 processor initialization
@@ -236,6 +28,5 @@ static void __init at91sam9n12_initialize(void)
 AT91_SOC_START(at91sam9n12)
        .map_io = at91sam9n12_map_io,
-        .register_clocks = at91sam9n12_register_clocks,
        .init = at91sam9n12_initialize,
 AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index f553e4ea034b..f25b9aec9c50 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -9,284 +9,14 @@
 * more details.
 */
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/clk/at91_pmc.h>
-#include <asm/proc-fns.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
 #include <asm/system_misc.h>
+#include <asm/irq.h>
 #include <mach/cpu.h>
 #include <mach/at91_dbgu.h>
-#include <mach/at91sam9rl.h>
 #include <mach/hardware.h>
-#include "at91_aic.h"
 #include "soc.h"
 #include "generic.h"
-#include "sam9_smc.h"
-#include "pm.h"
-/* --------------------------------------------------------------------
- *  Clocks
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_OLD_CLK_AT91)
-#include "clock.h"
-/*
- * The peripheral clocks.
- */
-static struct clk pioA_clk = {
-        .name           = "pioA_clk",
-        .pmc_mask       = 1 << AT91SAM9RL_ID_PIOA,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
-        .name           = "pioB_clk",
-        .pmc_mask       = 1 << AT91SAM9RL_ID_PIOB,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
-        .name           = "pioC_clk",
-        .pmc_mask       = 1 << AT91SAM9RL_ID_PIOC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioD_clk = {
-        .name           = "pioD_clk",
-        .pmc_mask       = 1 << AT91SAM9RL_ID_PIOD,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
-        .name           = "usart0_clk",
-        .pmc_mask       = 1 << AT91SAM9RL_ID_US0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
-        .name           = "usart1_clk",
-        .pmc_mask       = 1 << AT91SAM9RL_ID_US1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
-        .name           = "usart2_clk",
-        .pmc_mask       = 1 << AT91SAM9RL_ID_US2,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart3_clk = {
-        .name           = "usart3_clk",
-        .pmc_mask       = 1 << AT91SAM9RL_ID_US3,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc_clk = {
-        .name           = "mci_clk",
-        .pmc_mask       = 1 << AT91SAM9RL_ID_MCI,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi0_clk = {
-        .name           = "twi0_clk",
-        .pmc_mask       = 1 << AT91SAM9RL_ID_TWI0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi1_clk = {
-        .name           = "twi1_clk",
-        .pmc_mask       = 1 << AT91SAM9RL_ID_TWI1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi_clk = {
-        .name           = "spi_clk",
-        .pmc_mask       = 1 << AT91SAM9RL_ID_SPI,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
-        .name           = "ssc0_clk",
-        .pmc_mask       = 1 << AT91SAM9RL_ID_SSC0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
-        .name           = "ssc1_clk",
-        .pmc_mask       = 1 << AT91SAM9RL_ID_SSC1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc0_clk = {
-        .name           = "tc0_clk",
-        .pmc_mask       = 1 << AT91SAM9RL_ID_TC0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc1_clk = {
-        .name           = "tc1_clk",
-        .pmc_mask       = 1 << AT91SAM9RL_ID_TC1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc2_clk = {
-        .name           = "tc2_clk",
-        .pmc_mask       = 1 << AT91SAM9RL_ID_TC2,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pwm_clk = {
-        .name           = "pwm_clk",
-        .pmc_mask       = 1 << AT91SAM9RL_ID_PWMC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tsc_clk = {
-        .name           = "tsc_clk",
-        .pmc_mask       = 1 << AT91SAM9RL_ID_TSC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma_clk = {
-        .name           = "dma_clk",
-        .pmc_mask       = 1 << AT91SAM9RL_ID_DMA,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udphs_clk = {
-        .name           = "udphs_clk",
-        .pmc_mask       = 1 << AT91SAM9RL_ID_UDPHS,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk lcdc_clk = {
-        .name           = "lcdc_clk",
-        .pmc_mask       = 1 << AT91SAM9RL_ID_LCDC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ac97_clk = {
-        .name           = "ac97_clk",
-        .pmc_mask       = 1 << AT91SAM9RL_ID_AC97C,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk adc_op_clk = {
-        .name           = "adc_op_clk",
-        .type           = CLK_TYPE_PERIPHERAL,
-        .rate_hz        = 1000000,
-};
-static struct clk *periph_clocks[] __initdata = {
-        &pioA_clk,
-        &pioB_clk,
-        &pioC_clk,
-        &pioD_clk,
-        &usart0_clk,
-        &usart1_clk,
-        &usart2_clk,
-        &usart3_clk,
-        &mmc_clk,
-        &twi0_clk,
-        &twi1_clk,
-        &spi_clk,
-        &ssc0_clk,
-        &ssc1_clk,
-        &tc0_clk,
-        &tc1_clk,
-        &tc2_clk,
-        &pwm_clk,
-        &tsc_clk,
-        &dma_clk,
-        &udphs_clk,
-        &lcdc_clk,
-        &ac97_clk,
-        &adc_op_clk,
-        // irq0
-};
-static struct clk_lookup periph_clocks_lookups[] = {
-        CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
-        CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
-        CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
-        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
-        CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
-        CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
-        CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
-        CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
-        CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
-        CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
-        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
-        CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
-        CLKDEV_CON_DEV_ID(NULL, "at91sam9rl-pwm", &pwm_clk),
-        CLKDEV_CON_ID("pioA", &pioA_clk),
-        CLKDEV_CON_ID("pioB", &pioB_clk),
-        CLKDEV_CON_ID("pioC", &pioC_clk),
-        CLKDEV_CON_ID("pioD", &pioD_clk),
-        /* more lookup table for DT entries */
-        CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
-        CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
-        CLKDEV_CON_DEV_ID("usart", "ffffb400.serial", &usart1_clk),
-        CLKDEV_CON_DEV_ID("usart", "ffffb800.serial", &usart2_clk),
-        CLKDEV_CON_DEV_ID("usart", "ffffbc00.serial", &usart3_clk),
-        CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
-        CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
-        CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "fffa4000.mmc", &mmc_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffa8000.i2c", &twi0_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi1_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffc8000.pwm", &pwm_clk),
-        CLKDEV_CON_DEV_ID(NULL, "ffffc800.pwm", &pwm_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
-        CLKDEV_CON_ID("adc_clk", &tsc_clk),
-};
-static struct clk_lookup usart_clocks_lookups[] = {
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
-};
-/*
- * The two programmable clocks.
- * You must configure pin multiplexing to bring these signals out.
- */
-static struct clk pck0 = {
-        .name           = "pck0",
-        .pmc_mask       = AT91_PMC_PCK0,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 0,
-};
-static struct clk pck1 = {
-        .name           = "pck1",
-        .pmc_mask       = AT91_PMC_PCK1,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 1,
-};
-static void __init at91sam9rl_register_clocks(void)
-{
-        int i;
-        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
-                clk_register(periph_clocks[i]);
-        clkdev_add_table(periph_clocks_lookups,
-                         ARRAY_SIZE(periph_clocks_lookups));
-        clkdev_add_table(usart_clocks_lookups,
-                         ARRAY_SIZE(usart_clocks_lookups));
-        clk_register(&pck0);
-        clk_register(&pck1);
-}
-#endif
-/* --------------------------------------------------------------------
- *  GPIO
- * -------------------------------------------------------------------- */
-static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
-        {
-                .id             = AT91SAM9RL_ID_PIOA,
-                .regbase        = AT91SAM9RL_BASE_PIOA,
-        }, {
-                .id             = AT91SAM9RL_ID_PIOB,
-                .regbase        = AT91SAM9RL_BASE_PIOB,
-        }, {
-                .id             = AT91SAM9RL_ID_PIOC,
-                .regbase        = AT91SAM9RL_BASE_PIOC,
-        }, {
-                .id             = AT91SAM9RL_ID_PIOD,
-                .regbase        = AT91SAM9RL_BASE_PIOD,
-        }
-};
 /* --------------------------------------------------------------------
 *  AT91SAM9RL processor initialization
@@ -309,121 +39,15 @@ static void __init at91sam9rl_map_io(void)
        at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
 }
-static void __init at91sam9rl_ioremap_registers(void)
-{
-        at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
-        at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
-        at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
-        at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
-        at91_pm_set_standby(at91sam9_sdram_standby);
-}
 static void __init at91sam9rl_initialize(void)
 {
        arm_pm_idle = at91sam9_idle;
        at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
        at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);
-        /* Register GPIO subsystem */
-        at91_gpio_init(at91sam9rl_gpio, 4);
-}
-static struct resource rstc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9RL_BASE_RSTC,
-                .end    = AT91SAM9RL_BASE_RSTC + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91SAM9RL_BASE_SDRAMC,
-                .end    = AT91SAM9RL_BASE_SDRAMC + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device rstc_device = {
-        .name           = "at91-sam9260-reset",
-        .resource       = rstc_resources,
-        .num_resources  = ARRAY_SIZE(rstc_resources),
-};
-static struct resource shdwc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9RL_BASE_SHDWC,
-                .end    = AT91SAM9RL_BASE_SHDWC + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device shdwc_device = {
-        .name           = "at91-poweroff",
-        .resource       = shdwc_resources,
-        .num_resources  = ARRAY_SIZE(shdwc_resources),
-};
-static void __init at91sam9rl_register_devices(void)
-{
-        platform_device_register(&rstc_device);
-        platform_device_register(&shdwc_device);
-}
-/* --------------------------------------------------------------------
- *  Interrupt initialization
- * -------------------------------------------------------------------- */
-/*
- * The default interrupt priority levels (0 = lowest, 7 = highest).
- */
-static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
-        7,      /* Advanced Interrupt Controller */
-        7,      /* System Peripherals */
-        1,      /* Parallel IO Controller A */
-        1,      /* Parallel IO Controller B */
-        1,      /* Parallel IO Controller C */
-        1,      /* Parallel IO Controller D */
-        5,      /* USART 0 */
-        5,      /* USART 1 */
-        5,      /* USART 2 */
-        5,      /* USART 3 */
-        0,      /* Multimedia Card Interface */
-        6,      /* Two-Wire Interface 0 */
-        6,      /* Two-Wire Interface 1 */
-        5,      /* Serial Peripheral Interface */
-        4,      /* Serial Synchronous Controller 0 */
-        4,      /* Serial Synchronous Controller 1 */
-        0,      /* Timer Counter 0 */
-        0,      /* Timer Counter 1 */
-        0,      /* Timer Counter 2 */
-        0,
-        0,      /* Touch Screen Controller */
-        0,      /* DMA Controller */
-        2,      /* USB Device High speed port */
-        2,      /* LCD Controller */
-        6,      /* AC97 Controller */
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,      /* Advanced Interrupt Controller */
-};
-static void __init at91sam9rl_init_time(void)
-{
-        at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
 }
 AT91_SOC_START(at91sam9rl)
        .map_io = at91sam9rl_map_io,
-        .default_irq_priority = at91sam9rl_default_irq_priority,
-        .extern_irq = (1 << AT91SAM9RL_ID_IRQ0),
-        .ioremap_registers = at91sam9rl_ioremap_registers,
-#if defined(CONFIG_OLD_CLK_AT91)
-        .register_clocks = at91sam9rl_register_clocks,
-#endif
-        .register_devices = at91sam9rl_register_devices,
        .init = at91sam9rl_initialize,
-        .init_time = at91sam9rl_init_time,
 AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
deleted file mode 100644
index 37d1c9ed4562..000000000000
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ /dev/null
@@ -1,1260 +0,0 @@
-/*
- *  Copyright (C) 2007 Atmel Corporation
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive for
- * more details.
- */
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/i2c-gpio.h>
-#include <linux/fb.h>
-#include <video/atmel_lcdc.h>
-#include <mach/at91sam9rl.h>
-#include <mach/at91sam9rl_matrix.h>
-#include <mach/at91_matrix.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/hardware.h>
-#include <linux/platform_data/dma-atmel.h>
-#include <linux/platform_data/at91_adc.h>
-#include "board.h"
-#include "generic.h"
-#include "gpio.h"
-/* --------------------------------------------------------------------
- *  HDMAC - AHB DMA Controller
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
-static u64 hdmac_dmamask = DMA_BIT_MASK(32);
-static struct resource hdmac_resources[] = {
-        [0] = {
-                .start  = AT91SAM9RL_BASE_DMA,
-                .end    = AT91SAM9RL_BASE_DMA + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_DMA,
-                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_DMA,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at_hdmac_device = {
-        .name           = "at91sam9rl_dma",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &hdmac_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = hdmac_resources,
-        .num_resources  = ARRAY_SIZE(hdmac_resources),
-};
-void __init at91_add_device_hdmac(void)
-{
-        platform_device_register(&at_hdmac_device);
-}
-#else
-void __init at91_add_device_hdmac(void) {}
-#endif
-/* --------------------------------------------------------------------
- *  USB HS Device (Gadget)
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
-static struct resource usba_udc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9RL_UDPHS_FIFO,
-                .end    = AT91SAM9RL_UDPHS_FIFO + SZ_512K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91SAM9RL_BASE_UDPHS,
-                .end    = AT91SAM9RL_BASE_UDPHS + SZ_1K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_UDPHS,
-                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_UDPHS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-#define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
-        [idx] = {                                               \
-                .name           = nam,                          \
-                .index          = idx,                          \
-                .fifo_size      = maxpkt,                       \
-                .nr_banks       = maxbk,                        \
-                .can_dma        = dma,                          \
-                .can_isoc       = isoc,                         \
-        }
-static struct usba_ep_data usba_udc_ep[] __initdata = {
-        EP("ep0", 0, 64, 1, 0, 0),
-        EP("ep1", 1, 1024, 2, 1, 1),
-        EP("ep2", 2, 1024, 2, 1, 1),
-        EP("ep3", 3, 1024, 3, 1, 0),
-        EP("ep4", 4, 1024, 3, 1, 0),
-        EP("ep5", 5, 1024, 3, 1, 1),
-        EP("ep6", 6, 1024, 3, 1, 1),
-};
-#undef EP
-/*
- * pdata doesn't have room for any endpoints, so we need to
- * append room for the ones we need right after it.
- */
-static struct {
-        struct usba_platform_data pdata;
-        struct usba_ep_data ep[7];
-} usba_udc_data;
-static struct platform_device at91_usba_udc_device = {
-        .name           = "atmel_usba_udc",
-        .id             = -1,
-        .dev            = {
-                                .platform_data  = &usba_udc_data.pdata,
-        },
-        .resource       = usba_udc_resources,
-        .num_resources  = ARRAY_SIZE(usba_udc_resources),
-};
-void __init at91_add_device_usba(struct usba_platform_data *data)
-{
-        /*
-         * Invalid pins are 0 on AT91, but the usba driver is shared
-         * with AVR32, which use negative values instead. Once/if
-         * gpio_is_valid() is ported to AT91, revisit this code.
-         */
-        usba_udc_data.pdata.vbus_pin = -EINVAL;
-        usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
-        memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
-        if (data && gpio_is_valid(data->vbus_pin)) {
-                at91_set_gpio_input(data->vbus_pin, 0);
-                at91_set_deglitch(data->vbus_pin, 1);
-                usba_udc_data.pdata.vbus_pin = data->vbus_pin;
-        }
-        /* Pullup pin is handled internally by USB device peripheral */
-        platform_device_register(&at91_usba_udc_device);
-}
-#else
-void __init at91_add_device_usba(struct usba_platform_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  MMC / SD
- * -------------------------------------------------------------------- */
-#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
-static u64 mmc_dmamask = DMA_BIT_MASK(32);
-static struct mci_platform_data mmc_data;
-static struct resource mmc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9RL_BASE_MCI,
-                .end    = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_MCI,
-                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_MCI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9rl_mmc_device = {
-        .name           = "atmel_mci",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &mmc_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &mmc_data,
-        },
-        .resource       = mmc_resources,
-        .num_resources  = ARRAY_SIZE(mmc_resources),
-};
-void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
-{
-        if (!data)
-                return;
-        if (data->slot[0].bus_width) {
-                /* input/irq */
-                if (gpio_is_valid(data->slot[0].detect_pin)) {
-                        at91_set_gpio_input(data->slot[0].detect_pin, 1);
-                        at91_set_deglitch(data->slot[0].detect_pin, 1);
-                }
-                if (gpio_is_valid(data->slot[0].wp_pin))
-                        at91_set_gpio_input(data->slot[0].wp_pin, 1);
-                /* CLK */
-                at91_set_A_periph(AT91_PIN_PA2, 0);
-                /* CMD */
-                at91_set_A_periph(AT91_PIN_PA1, 1);
-                /* DAT0, maybe DAT1..DAT3 */
-                at91_set_A_periph(AT91_PIN_PA0, 1);
-                if (data->slot[0].bus_width == 4) {
-                        at91_set_A_periph(AT91_PIN_PA3, 1);
-                        at91_set_A_periph(AT91_PIN_PA4, 1);
-                        at91_set_A_periph(AT91_PIN_PA5, 1);
-                }
-                mmc_data = *data;
-                platform_device_register(&at91sam9rl_mmc_device);
-        }
-}
-#else
-void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  NAND / SmartMedia
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
-static struct atmel_nand_data nand_data;
-#define NAND_BASE       AT91_CHIPSELECT_3
-static struct resource nand_resources[] = {
-        [0] = {
-                .start  = NAND_BASE,
-                .end    = NAND_BASE + SZ_256M - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91SAM9RL_BASE_ECC,
-                .end    = AT91SAM9RL_BASE_ECC + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct platform_device atmel_nand_device = {
-        .name           = "atmel_nand",
-        .id             = -1,
-        .dev            = {
-                                .platform_data  = &nand_data,
-        },
-        .resource       = nand_resources,
-        .num_resources  = ARRAY_SIZE(nand_resources),
-};
-void __init at91_add_device_nand(struct atmel_nand_data *data)
-{
-        unsigned long csa;
-        if (!data)
-                return;
-        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
-        at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
-        /* enable pin */
-        if (gpio_is_valid(data->enable_pin))
-                at91_set_gpio_output(data->enable_pin, 1);
-        /* ready/busy pin */
-        if (gpio_is_valid(data->rdy_pin))
-                at91_set_gpio_input(data->rdy_pin, 1);
-        /* card detect pin */
-        if (gpio_is_valid(data->det_pin))
-                at91_set_gpio_input(data->det_pin, 1);
-        at91_set_A_periph(AT91_PIN_PB4, 0);             /* NANDOE */
-        at91_set_A_periph(AT91_PIN_PB5, 0);             /* NANDWE */
-        nand_data = *data;
-        platform_device_register(&atmel_nand_device);
-}
-#else
-void __init at91_add_device_nand(struct atmel_nand_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  TWI (i2c)
- * -------------------------------------------------------------------- */
-/*
- * Prefer the GPIO code since the TWI controller isn't robust
- * (gets overruns and underruns under load) and can only issue
- * repeated STARTs in one scenario (the driver doesn't yet handle them).
- */
-#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
-static struct i2c_gpio_platform_data pdata = {
-        .sda_pin                = AT91_PIN_PA23,
-        .sda_is_open_drain      = 1,
-        .scl_pin                = AT91_PIN_PA24,
-        .scl_is_open_drain      = 1,
-        .udelay                 = 2,            /* ~100 kHz */
-};
-static struct platform_device at91sam9rl_twi_device = {
-        .name                   = "i2c-gpio",
-        .id                     = 0,
-        .dev.platform_data      = &pdata,
-};
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
-{
-        at91_set_GPIO_periph(AT91_PIN_PA23, 1);         /* TWD (SDA) */
-        at91_set_multi_drive(AT91_PIN_PA23, 1);
-        at91_set_GPIO_periph(AT91_PIN_PA24, 1);         /* TWCK (SCL) */
-        at91_set_multi_drive(AT91_PIN_PA24, 1);
-        i2c_register_board_info(0, devices, nr_devices);
-        platform_device_register(&at91sam9rl_twi_device);
-}
-#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
-static struct resource twi_resources[] = {
-        [0] = {
-                .start  = AT91SAM9RL_BASE_TWI0,
-                .end    = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_TWI0,
-                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_TWI0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9rl_twi_device = {
-        .name           = "i2c-at91sam9g20",
-        .id             = 0,
-        .resource       = twi_resources,
-        .num_resources  = ARRAY_SIZE(twi_resources),
-};
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
-{
-        /* pins used for TWI interface */
-        at91_set_A_periph(AT91_PIN_PA23, 0);            /* TWD */
-        at91_set_multi_drive(AT91_PIN_PA23, 1);
-        at91_set_A_periph(AT91_PIN_PA24, 0);            /* TWCK */
-        at91_set_multi_drive(AT91_PIN_PA24, 1);
-        i2c_register_board_info(0, devices, nr_devices);
-        platform_device_register(&at91sam9rl_twi_device);
-}
-#else
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
-#endif
-/* --------------------------------------------------------------------
- *  SPI
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
-static u64 spi_dmamask = DMA_BIT_MASK(32);
-static struct resource spi_resources[] = {
-        [0] = {
-                .start  = AT91SAM9RL_BASE_SPI,
-                .end    = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_SPI,
-                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_SPI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9rl_spi_device = {
-        .name           = "atmel_spi",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &spi_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = spi_resources,
-        .num_resources  = ARRAY_SIZE(spi_resources),
-};
-static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 };
-void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
-{
-        int i;
-        unsigned long cs_pin;
-        at91_set_A_periph(AT91_PIN_PA25, 0);    /* MISO */
-        at91_set_A_periph(AT91_PIN_PA26, 0);    /* MOSI */
-        at91_set_A_periph(AT91_PIN_PA27, 0);    /* SPCK */
-        /* Enable SPI chip-selects */
-        for (i = 0; i < nr_devices; i++) {
-                if (devices[i].controller_data)
-                        cs_pin = (unsigned long) devices[i].controller_data;
-                else
-                        cs_pin = spi_standard_cs[devices[i].chip_select];
-                if (!gpio_is_valid(cs_pin))
-                        continue;
-                /* enable chip-select pin */
-                at91_set_gpio_output(cs_pin, 1);
-                /* pass chip-select pin to driver */
-                devices[i].controller_data = (void *) cs_pin;
-        }
-        spi_register_board_info(devices, nr_devices);
-        platform_device_register(&at91sam9rl_spi_device);
-}
-#else
-void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
-#endif
-/* --------------------------------------------------------------------
- *  AC97
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
-static u64 ac97_dmamask = DMA_BIT_MASK(32);
-static struct ac97c_platform_data ac97_data;
-static struct resource ac97_resources[] = {
-        [0] = {
-                .start  = AT91SAM9RL_BASE_AC97C,
-                .end    = AT91SAM9RL_BASE_AC97C + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_AC97C,
-                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_AC97C,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9rl_ac97_device = {
-        .name           = "atmel_ac97c",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &ac97_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &ac97_data,
-        },
-        .resource       = ac97_resources,
-        .num_resources  = ARRAY_SIZE(ac97_resources),
-};
-void __init at91_add_device_ac97(struct ac97c_platform_data *data)
-{
-        if (!data)
-                return;
-        at91_set_A_periph(AT91_PIN_PD1, 0);     /* AC97FS */
-        at91_set_A_periph(AT91_PIN_PD2, 0);     /* AC97CK */
-        at91_set_A_periph(AT91_PIN_PD3, 0);     /* AC97TX */
-        at91_set_A_periph(AT91_PIN_PD4, 0);     /* AC97RX */
-        /* reset */
-        if (gpio_is_valid(data->reset_pin))
-                at91_set_gpio_output(data->reset_pin, 0);
-        ac97_data = *data;
-        platform_device_register(&at91sam9rl_ac97_device);
-}
-#else
-void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  LCD Controller
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
-static u64 lcdc_dmamask = DMA_BIT_MASK(32);
-static struct atmel_lcdfb_pdata lcdc_data;
-static struct resource lcdc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9RL_LCDC_BASE,
-                .end    = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_LCDC,
-                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_LCDC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91_lcdc_device = {
-        .name           = "at91sam9rl-lcdfb",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &lcdc_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &lcdc_data,
-        },
-        .resource       = lcdc_resources,
-        .num_resources  = ARRAY_SIZE(lcdc_resources),
-};
-void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data)
-{
-        if (!data) {
-                return;
-        }
-        at91_set_B_periph(AT91_PIN_PC1, 0);     /* LCDPWR */
-        at91_set_A_periph(AT91_PIN_PC5, 0);     /* LCDHSYNC */
-        at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDDOTCK */
-        at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDDEN */
-        at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDCC */
-        at91_set_B_periph(AT91_PIN_PC9, 0);     /* LCDD3 */
-        at91_set_B_periph(AT91_PIN_PC10, 0);    /* LCDD4 */
-        at91_set_B_periph(AT91_PIN_PC11, 0);    /* LCDD5 */
-        at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD6 */
-        at91_set_B_periph(AT91_PIN_PC13, 0);    /* LCDD7 */
-        at91_set_B_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
-        at91_set_B_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
-        at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
-        at91_set_B_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
-        at91_set_B_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
-        at91_set_B_periph(AT91_PIN_PC20, 0);    /* LCDD18 */
-        at91_set_B_periph(AT91_PIN_PC21, 0);    /* LCDD19 */
-        at91_set_B_periph(AT91_PIN_PC22, 0);    /* LCDD20 */
-        at91_set_B_periph(AT91_PIN_PC23, 0);    /* LCDD21 */
-        at91_set_B_periph(AT91_PIN_PC24, 0);    /* LCDD22 */
-        at91_set_B_periph(AT91_PIN_PC25, 0);    /* LCDD23 */
-        lcdc_data = *data;
-        platform_device_register(&at91_lcdc_device);
-}
-#else
-void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  Timer/Counter block
- * -------------------------------------------------------------------- */
-#ifdef CONFIG_ATMEL_TCLIB
-static struct resource tcb_resources[] = {
-        [0] = {
-                .start  = AT91SAM9RL_BASE_TCB0,
-                .end    = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC0,
-                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC0,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC1,
-                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC1,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC2,
-                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9rl_tcb_device = {
-        .name           = "atmel_tcb",
-        .id             = 0,
-        .resource       = tcb_resources,
-        .num_resources  = ARRAY_SIZE(tcb_resources),
-};
-static void __init at91_add_device_tc(void)
-{
-        platform_device_register(&at91sam9rl_tcb_device);
-}
-#else
-static void __init at91_add_device_tc(void) { }
-#endif
-/* --------------------------------------------------------------------
- *  ADC and Touchscreen
- * -------------------------------------------------------------------- */
-#if IS_ENABLED(CONFIG_AT91_ADC)
-static struct at91_adc_data adc_data;
-static struct resource adc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9RL_BASE_TSC,
-                .end    = AT91SAM9RL_BASE_TSC + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_TSC,
-                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_TSC,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-static struct platform_device at91_adc_device = {
-        .name           = "at91sam9rl-adc",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &adc_data,
-        },
-        .resource       = adc_resources,
-        .num_resources  = ARRAY_SIZE(adc_resources),
-};
-static struct at91_adc_trigger at91_adc_triggers[] = {
-        [0] = {
-                .name = "external-rising",
-                .value = 1,
-                .is_external = true,
-        },
-        [1] = {
-                .name = "external-falling",
-                .value = 2,
-                .is_external = true,
-        },
-        [2] = {
-                .name = "external-any",
-                .value = 3,
-                .is_external = true,
-        },
-        [3] = {
-                .name = "continuous",
-                .value = 6,
-                .is_external = false,
-        },
-};
-void __init at91_add_device_adc(struct at91_adc_data *data)
-{
-        if (!data)
-                return;
-        if (test_bit(0, &data->channels_used))
-                at91_set_A_periph(AT91_PIN_PA17, 0);
-        if (test_bit(1, &data->channels_used))
-                at91_set_A_periph(AT91_PIN_PA18, 0);
-        if (test_bit(2, &data->channels_used))
-                at91_set_A_periph(AT91_PIN_PA19, 0);
-        if (test_bit(3, &data->channels_used))
-                at91_set_A_periph(AT91_PIN_PA20, 0);
-        if (test_bit(4, &data->channels_used))
-                at91_set_A_periph(AT91_PIN_PD6, 0);
-        if (test_bit(5, &data->channels_used))
-                at91_set_A_periph(AT91_PIN_PD7, 0);
-        if (data->use_external_triggers)
-                at91_set_A_periph(AT91_PIN_PB15, 0);
-        data->startup_time = 40;
-        data->trigger_number = 4;
-        data->trigger_list = at91_adc_triggers;
-        adc_data = *data;
-        platform_device_register(&at91_adc_device);
-}
-#else
-void __init at91_add_device_adc(struct at91_adc_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  RTC
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
-static struct platform_device at91sam9rl_rtc_device = {
-        .name           = "at91_rtc",
-        .id             = -1,
-        .num_resources  = 0,
-};
-static void __init at91_add_device_rtc(void)
-{
-        platform_device_register(&at91sam9rl_rtc_device);
-}
-#else
-static void __init at91_add_device_rtc(void) {}
-#endif
-/* --------------------------------------------------------------------
- *  RTT
- * -------------------------------------------------------------------- */
-static struct resource rtt_resources[] = {
-        {
-                .start  = AT91SAM9RL_BASE_RTT,
-                .end    = AT91SAM9RL_BASE_RTT + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-static struct platform_device at91sam9rl_rtt_device = {
-        .name           = "at91_rtt",
-        .id             = 0,
-        .resource       = rtt_resources,
-};
-#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
-static void __init at91_add_device_rtt_rtc(void)
-{
-        at91sam9rl_rtt_device.name = "rtc-at91sam9";
-        /*
-         * The second resource is needed:
-         * GPBR will serve as the storage for RTC time offset
-         */
-        at91sam9rl_rtt_device.num_resources = 3;
-        rtt_resources[1].start = AT91SAM9RL_BASE_GPBR +
-                                 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
-        rtt_resources[1].end = rtt_resources[1].start + 3;
-        rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
-        rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
-}
-#else
-static void __init at91_add_device_rtt_rtc(void)
-{
-        /* Only one resource is needed: RTT not used as RTC */
-        at91sam9rl_rtt_device.num_resources = 1;
-}
-#endif
-static void __init at91_add_device_rtt(void)
-{
-        at91_add_device_rtt_rtc();
-        platform_device_register(&at91sam9rl_rtt_device);
-}
-/* --------------------------------------------------------------------
- *  Watchdog
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
-static struct resource wdt_resources[] = {
-        {
-                .start  = AT91SAM9RL_BASE_WDT,
-                .end    = AT91SAM9RL_BASE_WDT + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct platform_device at91sam9rl_wdt_device = {
-        .name           = "at91_wdt",
-        .id             = -1,
-        .resource       = wdt_resources,
-        .num_resources  = ARRAY_SIZE(wdt_resources),
-};
-static void __init at91_add_device_watchdog(void)
-{
-        platform_device_register(&at91sam9rl_wdt_device);
-}
-#else
-static void __init at91_add_device_watchdog(void) {}
-#endif
-/* --------------------------------------------------------------------
- *  PWM
- * --------------------------------------------------------------------*/
-#if IS_ENABLED(CONFIG_PWM_ATMEL)
-static struct resource pwm_resources[] = {
-        [0] = {
-                .start  = AT91SAM9RL_BASE_PWMC,
-                .end    = AT91SAM9RL_BASE_PWMC + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_PWMC,
-                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_PWMC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9rl_pwm0_device = {
-        .name   = "at91sam9rl-pwm",
-        .id     = -1,
-        .resource       = pwm_resources,
-        .num_resources  = ARRAY_SIZE(pwm_resources),
-};
-void __init at91_add_device_pwm(u32 mask)
-{
-        if (mask & (1 << AT91_PWM0))
-                at91_set_B_periph(AT91_PIN_PB8, 1);     /* enable PWM0 */
-        if (mask & (1 << AT91_PWM1))
-                at91_set_B_periph(AT91_PIN_PB9, 1);     /* enable PWM1 */
-        if (mask & (1 << AT91_PWM2))
-                at91_set_B_periph(AT91_PIN_PD5, 1);     /* enable PWM2 */
-        if (mask & (1 << AT91_PWM3))
-                at91_set_B_periph(AT91_PIN_PD8, 1);     /* enable PWM3 */
-        platform_device_register(&at91sam9rl_pwm0_device);
-}
-#else
-void __init at91_add_device_pwm(u32 mask) {}
-#endif
-/* --------------------------------------------------------------------
- *  SSC -- Synchronous Serial Controller
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
-static u64 ssc0_dmamask = DMA_BIT_MASK(32);
-static struct resource ssc0_resources[] = {
-        [0] = {
-                .start  = AT91SAM9RL_BASE_SSC0,
-                .end    = AT91SAM9RL_BASE_SSC0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC0,
-                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9rl_ssc0_device = {
-        .name   = "at91rm9200_ssc",
-        .id     = 0,
-        .dev    = {
-                .dma_mask               = &ssc0_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = ssc0_resources,
-        .num_resources  = ARRAY_SIZE(ssc0_resources),
-};
-static inline void configure_ssc0_pins(unsigned pins)
-{
-        if (pins & ATMEL_SSC_TF)
-                at91_set_A_periph(AT91_PIN_PC0, 1);
-        if (pins & ATMEL_SSC_TK)
-                at91_set_A_periph(AT91_PIN_PC1, 1);
-        if (pins & ATMEL_SSC_TD)
-                at91_set_A_periph(AT91_PIN_PA15, 1);
-        if (pins & ATMEL_SSC_RD)
-                at91_set_A_periph(AT91_PIN_PA16, 1);
-        if (pins & ATMEL_SSC_RK)
-                at91_set_B_periph(AT91_PIN_PA10, 1);
-        if (pins & ATMEL_SSC_RF)
-                at91_set_B_periph(AT91_PIN_PA22, 1);
-}
-static u64 ssc1_dmamask = DMA_BIT_MASK(32);
-static struct resource ssc1_resources[] = {
-        [0] = {
-                .start  = AT91SAM9RL_BASE_SSC1,
-                .end    = AT91SAM9RL_BASE_SSC1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC1,
-                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device at91sam9rl_ssc1_device = {
-        .name   = "at91rm9200_ssc",
-        .id     = 1,
-        .dev    = {
-                .dma_mask               = &ssc1_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = ssc1_resources,
-        .num_resources  = ARRAY_SIZE(ssc1_resources),
-};
-static inline void configure_ssc1_pins(unsigned pins)
-{
-        if (pins & ATMEL_SSC_TF)
-                at91_set_B_periph(AT91_PIN_PA29, 1);
-        if (pins & ATMEL_SSC_TK)
-                at91_set_B_periph(AT91_PIN_PA30, 1);
-        if (pins & ATMEL_SSC_TD)
-                at91_set_B_periph(AT91_PIN_PA13, 1);
-        if (pins & ATMEL_SSC_RD)
-                at91_set_B_periph(AT91_PIN_PA14, 1);
-        if (pins & ATMEL_SSC_RK)
-                at91_set_B_periph(AT91_PIN_PA9, 1);
-        if (pins & ATMEL_SSC_RF)
-                at91_set_B_periph(AT91_PIN_PA8, 1);
-}
-/*
- * SSC controllers are accessed through library code, instead of any
- * kind of all-singing/all-dancing driver.  For example one could be
- * used by a particular I2S audio codec's driver, while another one
- * on the same system might be used by a custom data capture driver.
- */
-void __init at91_add_device_ssc(unsigned id, unsigned pins)
-{
-        struct platform_device *pdev;
-        /*
-         * NOTE: caller is responsible for passing information matching
-         * "pins" to whatever will be using each particular controller.
-         */
-        switch (id) {
-        case AT91SAM9RL_ID_SSC0:
-                pdev = &at91sam9rl_ssc0_device;
-                configure_ssc0_pins(pins);
-                break;
-        case AT91SAM9RL_ID_SSC1:
-                pdev = &at91sam9rl_ssc1_device;
-                configure_ssc1_pins(pins);
-                break;
-        default:
-                return;
-        }
-        platform_device_register(pdev);
-}
-#else
-void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
-#endif
-/* --------------------------------------------------------------------
- *  UART
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_SERIAL_ATMEL)
-static struct resource dbgu_resources[] = {
-        [0] = {
-                .start  = AT91SAM9RL_BASE_DBGU,
-                .end    = AT91SAM9RL_BASE_DBGU + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
-                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data dbgu_data = {
-        .use_dma_tx     = 0,
-        .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
-};
-static u64 dbgu_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9rl_dbgu_device = {
-        .name           = "atmel_usart",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &dbgu_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &dbgu_data,
-        },
-        .resource       = dbgu_resources,
-        .num_resources  = ARRAY_SIZE(dbgu_resources),
-};
-static inline void configure_dbgu_pins(void)
-{
-        at91_set_A_periph(AT91_PIN_PA21, 0);            /* DRXD */
-        at91_set_A_periph(AT91_PIN_PA22, 1);            /* DTXD */
-}
-static struct resource uart0_resources[] = {
-        [0] = {
-                .start  = AT91SAM9RL_BASE_US0,
-                .end    = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_US0,
-                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_US0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart0_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static u64 uart0_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9rl_uart0_device = {
-        .name           = "atmel_usart",
-        .id             = 1,
-        .dev            = {
-                                .dma_mask               = &uart0_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart0_data,
-        },
-        .resource       = uart0_resources,
-        .num_resources  = ARRAY_SIZE(uart0_resources),
-};
-static inline void configure_usart0_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PA6, 1);             /* TXD0 */
-        at91_set_A_periph(AT91_PIN_PA7, 0);             /* RXD0 */
-        if (pins & ATMEL_UART_RTS)
-                at91_set_A_periph(AT91_PIN_PA9, 0);     /* RTS0 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_A_periph(AT91_PIN_PA10, 0);    /* CTS0 */
-        if (pins & ATMEL_UART_DSR)
-                at91_set_A_periph(AT91_PIN_PD14, 0);    /* DSR0 */
-        if (pins & ATMEL_UART_DTR)
-                at91_set_A_periph(AT91_PIN_PD15, 0);    /* DTR0 */
-        if (pins & ATMEL_UART_DCD)
-                at91_set_A_periph(AT91_PIN_PD16, 0);    /* DCD0 */
-        if (pins & ATMEL_UART_RI)
-                at91_set_A_periph(AT91_PIN_PD17, 0);    /* RI0 */
-}
-static struct resource uart1_resources[] = {
-        [0] = {
-                .start  = AT91SAM9RL_BASE_US1,
-                .end    = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_US1,
-                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_US1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart1_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static u64 uart1_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9rl_uart1_device = {
-        .name           = "atmel_usart",
-        .id             = 2,
-        .dev            = {
-                                .dma_mask               = &uart1_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart1_data,
-        },
-        .resource       = uart1_resources,
-        .num_resources  = ARRAY_SIZE(uart1_resources),
-};
-static inline void configure_usart1_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PA11, 1);            /* TXD1 */
-        at91_set_A_periph(AT91_PIN_PA12, 0);            /* RXD1 */
-        if (pins & ATMEL_UART_RTS)
-                at91_set_B_periph(AT91_PIN_PA18, 0);    /* RTS1 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_B_periph(AT91_PIN_PA19, 0);    /* CTS1 */
-}
-static struct resource uart2_resources[] = {
-        [0] = {
-                .start  = AT91SAM9RL_BASE_US2,
-                .end    = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_US2,
-                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_US2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart2_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static u64 uart2_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9rl_uart2_device = {
-        .name           = "atmel_usart",
-        .id             = 3,
-        .dev            = {
-                                .dma_mask               = &uart2_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart2_data,
-        },
-        .resource       = uart2_resources,
-        .num_resources  = ARRAY_SIZE(uart2_resources),
-};
-static inline void configure_usart2_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PA13, 1);            /* TXD2 */
-        at91_set_A_periph(AT91_PIN_PA14, 0);            /* RXD2 */
-        if (pins & ATMEL_UART_RTS)
-                at91_set_A_periph(AT91_PIN_PA29, 0);    /* RTS2 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_A_periph(AT91_PIN_PA30, 0);    /* CTS2 */
-}
-static struct resource uart3_resources[] = {
-        [0] = {
-                .start  = AT91SAM9RL_BASE_US3,
-                .end    = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_US3,
-                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_US3,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct atmel_uart_data uart3_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-static u64 uart3_dmamask = DMA_BIT_MASK(32);
-static struct platform_device at91sam9rl_uart3_device = {
-        .name           = "atmel_usart",
-        .id             = 4,
-        .dev            = {
-                                .dma_mask               = &uart3_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart3_data,
-        },
-        .resource       = uart3_resources,
-        .num_resources  = ARRAY_SIZE(uart3_resources),
-};
-static inline void configure_usart3_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PB0, 1);             /* TXD3 */
-        at91_set_A_periph(AT91_PIN_PB1, 0);             /* RXD3 */
-        if (pins & ATMEL_UART_RTS)
-                at91_set_B_periph(AT91_PIN_PD4, 0);     /* RTS3 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_B_periph(AT91_PIN_PD3, 0);     /* CTS3 */
-}
-static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
-{
-        struct platform_device *pdev;
-        struct atmel_uart_data *pdata;
-        switch (id) {
-                case 0:         /* DBGU */
-                        pdev = &at91sam9rl_dbgu_device;
-                        configure_dbgu_pins();
-                        break;
-                case AT91SAM9RL_ID_US0:
-                        pdev = &at91sam9rl_uart0_device;
-                        configure_usart0_pins(pins);
-                        break;
-                case AT91SAM9RL_ID_US1:
-                        pdev = &at91sam9rl_uart1_device;
-                        configure_usart1_pins(pins);
-                        break;
-                case AT91SAM9RL_ID_US2:
-                        pdev = &at91sam9rl_uart2_device;
-                        configure_usart2_pins(pins);
-                        break;
-                case AT91SAM9RL_ID_US3:
-                        pdev = &at91sam9rl_uart3_device;
-                        configure_usart3_pins(pins);
-                        break;
-                default:
-                        return;
-        }
-        pdata = pdev->dev.platform_data;
-        pdata->num = portnr;            /* update to mapped ID */
-        if (portnr < ATMEL_MAX_UART)
-                at91_uarts[portnr] = pdev;
-}
-void __init at91_add_device_serial(void)
-{
-        int i;
-        for (i = 0; i < ATMEL_MAX_UART; i++) {
-                if (at91_uarts[i])
-                        platform_device_register(at91_uarts[i]);
-        }
-}
-#else
-void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
-void __init at91_add_device_serial(void) {}
-#endif
-/* -------------------------------------------------------------------- */
-/*
- * These devices are always present and don't need any board-specific
- * setup.
- */
-static int __init at91_add_standard_devices(void)
-{
-        at91_add_device_hdmac();
-        at91_add_device_rtc();
-        at91_add_device_rtt();
-        at91_add_device_watchdog();
-        at91_add_device_tc();
-        return 0;
-}
-arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 028268ff3722..f0d5a69a7237 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -6,317 +6,11 @@
 * Licensed under GPLv2 or later.
 */
-#include <linux/module.h>
+#include <asm/system_misc.h>
-#include <linux/dma-mapping.h>
+#include <mach/hardware.h>
-#include <linux/clk/at91_pmc.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <mach/at91sam9x5.h>
-#include <mach/cpu.h>
-#include "board.h"
 #include "soc.h"
 #include "generic.h"
-#include "sam9_smc.h"
-#if defined(CONFIG_OLD_CLK_AT91)
-#include "clock.h"
-/* --------------------------------------------------------------------
- *  Clocks
- * -------------------------------------------------------------------- */
-/*
- * The peripheral clocks.
- */
-static struct clk pioAB_clk = {
-        .name           = "pioAB_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_PIOAB,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioCD_clk = {
-        .name           = "pioCD_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_PIOCD,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk smd_clk = {
-        .name           = "smd_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_SMD,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
-        .name           = "usart0_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_USART0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
-        .name           = "usart1_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_USART1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
-        .name           = "usart2_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_USART2,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-/* USART3 clock - Only for sam9g25/sam9x25 */
-static struct clk usart3_clk = {
-        .name           = "usart3_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_USART3,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi0_clk = {
-        .name           = "twi0_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_TWI0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi1_clk = {
-        .name           = "twi1_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_TWI1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi2_clk = {
-        .name           = "twi2_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_TWI2,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc0_clk = {
-        .name           = "mci0_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_MCI0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
-        .name           = "spi0_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_SPI0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
-        .name           = "spi1_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_SPI1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uart0_clk = {
-        .name           = "uart0_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_UART0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uart1_clk = {
-        .name           = "uart1_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_UART1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tcb0_clk = {
-        .name           = "tcb0_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_TCB,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pwm_clk = {
-        .name           = "pwm_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_PWM,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk adc_clk = {
-        .name           = "adc_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_ADC,
-        .type   = CLK_TYPE_PERIPHERAL,
-};
-static struct clk adc_op_clk = {
-        .name           = "adc_op_clk",
-        .type           = CLK_TYPE_PERIPHERAL,
-        .rate_hz        = 5000000,
-};
-static struct clk dma0_clk = {
-        .name           = "dma0_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_DMA0,
-        .type   = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma1_clk = {
-        .name           = "dma1_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_DMA1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uhphs_clk = {
-        .name           = "uhphs",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_UHPHS,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udphs_clk = {
-        .name           = "udphs_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_UDPHS,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-/* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
-static struct clk macb0_clk = {
-        .name           = "pclk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_EMAC0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-/* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
-static struct clk lcdc_clk = {
-        .name           = "lcdc_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_LCDC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-/* isi clock - Only for sam9g25 */
-static struct clk isi_clk = {
-        .name           = "isi_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_ISI,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc1_clk = {
-        .name           = "mci1_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_MCI1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-/* emac1 clock - Only for sam9x25 */
-static struct clk macb1_clk = {
-        .name           = "pclk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_EMAC1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc_clk = {
-        .name           = "ssc_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_SSC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-/* can0 clock - Only for sam9x35 */
-static struct clk can0_clk = {
-        .name           = "can0_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_CAN0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-/* can1 clock - Only for sam9x35 */
-static struct clk can1_clk = {
-        .name           = "can1_clk",
-        .pmc_mask       = 1 << AT91SAM9X5_ID_CAN1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk *periph_clocks[] __initdata = {
-        &pioAB_clk,
-        &pioCD_clk,
-        &smd_clk,
-        &usart0_clk,
-        &usart1_clk,
-        &usart2_clk,
-        &twi0_clk,
-        &twi1_clk,
-        &twi2_clk,
-        &mmc0_clk,
-        &spi0_clk,
-        &spi1_clk,
-        &uart0_clk,
-        &uart1_clk,
-        &tcb0_clk,
-        &pwm_clk,
-        &adc_clk,
-        &adc_op_clk,
-        &dma0_clk,
-        &dma1_clk,
-        &uhphs_clk,
-        &udphs_clk,
-        &mmc1_clk,
-        &ssc_clk,
-        // irq0
-};
-static struct clk_lookup periph_clocks_lookups[] = {
-        /* lookup table for DT entries */
-        CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
-        CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
-        CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
-        CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
-        CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
-        CLKDEV_CON_DEV_ID("usart", "f8040000.serial", &uart0_clk),
-        CLKDEV_CON_DEV_ID("usart", "f8044000.serial", &uart1_clk),
-        CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
-        CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc0_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "f000c000.mmc", &mmc1_clk),
-        CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
-        CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
-        CLKDEV_CON_DEV_ID("pclk", "f0010000.ssc", &ssc_clk),
-        CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
-        CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
-        CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
-        CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
-        /* additional fake clock for macb_hclk */
-        CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
-        CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
-        CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
-        CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
-        CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
-        CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
-        CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
-        CLKDEV_CON_DEV_ID(NULL, "f8034000.pwm", &pwm_clk),
-};
-/*
- * The two programmable clocks.
- * You must configure pin multiplexing to bring these signals out.
- */
-static struct clk pck0 = {
-        .name           = "pck0",
-        .pmc_mask       = AT91_PMC_PCK0,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 0,
-};
-static struct clk pck1 = {
-        .name           = "pck1",
-        .pmc_mask       = AT91_PMC_PCK1,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 1,
-};
-static void __init at91sam9x5_register_clocks(void)
-{
-        int i;
-        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
-                clk_register(periph_clocks[i]);
-        clkdev_add_table(periph_clocks_lookups,
-                         ARRAY_SIZE(periph_clocks_lookups));
-        if (cpu_is_at91sam9g25()
-        || cpu_is_at91sam9x25())
-                clk_register(&usart3_clk);
-        if (cpu_is_at91sam9g25()
-        || cpu_is_at91sam9x25()
-        || cpu_is_at91sam9g35()
-        || cpu_is_at91sam9x35())
-                clk_register(&macb0_clk);
-        if (cpu_is_at91sam9g15()
-        || cpu_is_at91sam9g35()
-        || cpu_is_at91sam9x35())
-                clk_register(&lcdc_clk);
-        if (cpu_is_at91sam9g25())
-                clk_register(&isi_clk);
-        if (cpu_is_at91sam9x25())
-                clk_register(&macb1_clk);
-        if (cpu_is_at91sam9x25()
-        || cpu_is_at91sam9x35()) {
-                clk_register(&can0_clk);
-                clk_register(&can1_clk);
-        }
-        clk_register(&pck0);
-        clk_register(&pck1);
-}
-#else
-#define at91sam9x5_register_clocks      NULL
-#endif
 /* --------------------------------------------------------------------
 *  AT91SAM9x5 processor initialization
@@ -338,6 +32,5 @@ static void __init at91sam9x5_initialize(void)
 AT91_SOC_START(at91sam9x5)
        .map_io = at91sam9x5_map_io,
-        .register_clocks = at91sam9x5_register_clocks,
        .init = at91sam9x5_initialize,
 AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
deleted file mode 100644
index 7523f1cdfe1d..000000000000
--- a/arch/arm/mach-at91/at91x40.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * arch/arm/mach-at91/at91x40.c
- *
- * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
- * Copyright (C) 2005 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <asm/proc-fns.h>
-#include <asm/system_misc.h>
-#include <asm/mach/arch.h>
-#include <mach/at91x40.h>
-#include <mach/at91_st.h>
-#include <mach/hardware.h>
-#include "at91_aic.h"
-#include "generic.h"
-/*
- * Export the clock functions for the AT91X40. Some external code common
- * to all AT91 family parts relys on this, like the gpio and serial support.
- */
-int clk_enable(struct clk *clk)
-{
-        return 0;
-}
-void clk_disable(struct clk *clk)
-{
-}
-unsigned long clk_get_rate(struct clk *clk)
-{
-        return AT91X40_MASTER_CLOCK;
-}
-static void at91x40_idle(void)
-{
-        /*
-         * Disable the processor clock.  The processor will be automatically
-         * re-enabled by an interrupt or by a reset.
-         */
-        __raw_writel(AT91_PS_CR_CPU, AT91_IO_P2V(AT91_PS_CR));
-        cpu_do_idle();
-}
-void __init at91x40_initialize(unsigned long main_clock)
-{
-        arm_pm_idle = at91x40_idle;
-}
-/*
- * The default interrupt priority levels (0 = lowest, 7 = highest).
- */
-static unsigned int at91x40_default_irq_priority[NR_AIC_IRQS] __initdata = {
-        7,      /* Advanced Interrupt Controller (FIQ) */
-        0,      /* System Peripherals */
-        0,      /* USART 0 */
-        0,      /* USART 1 */
-        2,      /* Timer Counter 0 */
-        2,      /* Timer Counter 1 */
-        2,      /* Timer Counter 2 */
-        0,      /* Watchdog timer */
-        0,      /* Parallel IO Controller A */
-        0,      /* Reserved */
-        0,      /* Reserved */
-        0,      /* Reserved */
-        0,      /* Reserved */
-        0,      /* Reserved */
-        0,      /* Reserved */
-        0,      /* Reserved */
-        0,      /* External IRQ0 */
-        0,      /* External IRQ1 */
-        0,      /* External IRQ2 */
-};
-void __init at91x40_init_interrupts(unsigned int priority[NR_AIC_IRQS])
-{
-        u32  extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1)
-                        | (1 << AT91X40_ID_IRQ2);
-        if (!priority)
-                priority = at91x40_default_irq_priority;
-        at91_aic_init(priority, extern_irq);
-}
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
deleted file mode 100644
index 07d0bf2ac2da..000000000000
--- a/arch/arm/mach-at91/at91x40_time.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * arch/arm/mach-at91/at91x40_time.c
- *
- * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/time.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/at91x40.h>
-#include <asm/mach/time.h>
-#include "at91_tc.h"
-#define at91_tc_read(field) \
-        __raw_readl(AT91_IO_P2V(AT91_TC) + field)
-#define at91_tc_write(field, value) \
-        __raw_writel(value, AT91_IO_P2V(AT91_TC) + field)
-/*
- *      3 counter/timer units present.
- */
-#define AT91_TC_CLK0BASE        0
-#define AT91_TC_CLK1BASE        0x40
-#define AT91_TC_CLK2BASE        0x80
-static u32 at91x40_gettimeoffset(void)
-{
-        return (at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 /
-                (AT91X40_MASTER_CLOCK / 128)) * 1000;
-}
-static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
-{
-        at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_SR);
-        timer_tick();
-        return IRQ_HANDLED;
-}
-static struct irqaction at91x40_timer_irq = {
-        .name           = "at91_tick",
-        .flags          = IRQF_TIMER,
-        .handler        = at91x40_timer_interrupt
-};
-void __init at91x40_timer_init(void)
-{
-        unsigned int v;
-        arch_gettimeoffset = at91x40_gettimeoffset;
-        at91_tc_write(AT91_TC_BCR, 0);
-        v = at91_tc_read(AT91_TC_BMR);
-        v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE;
-        at91_tc_write(AT91_TC_BMR, v);
-        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
-        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
-        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
-        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
-        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
-        setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq);
-        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
-}
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
deleted file mode 100644
index 3f6dbcc34022..000000000000
--- a/arch/arm/mach-at91/board-1arm.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-1arm.c
- *
- *  Copyright (C) 2005 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/cpu.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "generic.h"
-#include "gpio.h"
-static void __init onearm_init_early(void)
-{
-        /* Set cpu type: PQFP */
-        at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
-        /* Initialize processor: 18.432 MHz crystal */
-        at91_initialize(18432000);
-}
-static struct macb_platform_data __initdata onearm_eth_data = {
-        .phy_irq_pin    = AT91_PIN_PC4,
-        .is_rmii        = 1,
-};
-static struct at91_usbh_data __initdata onearm_usbh_data = {
-        .ports          = 1,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-static struct at91_udc_data __initdata onearm_udc_data = {
-        .vbus_pin       = AT91_PIN_PC2,
-        .pullup_pin     = AT91_PIN_PC3,
-};
-static void __init onearm_board_init(void)
-{
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */
-        at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        /* USART1 on ttyS2 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                           | ATMEL_UART_RI);
-        at91_add_device_serial();
-        /* Ethernet */
-        at91_add_device_eth(&onearm_eth_data);
-        /* USB Host */
-        at91_add_device_usbh(&onearm_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&onearm_udc_data);
-}
-MACHINE_START(ONEARM, "Ajeco 1ARM single board computer")
-        /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .init_time      = at91rm9200_timer_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = onearm_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = onearm_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
deleted file mode 100644
index e76e35ce81e7..000000000000
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-afeb-9260v1.c
- *
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2006 Atmel
- *  Copyright (C) 2008 Sergey Lapin
- *
- * A custom board designed as open hardware; PCBs and various information
- * is available at http://groups.google.com/group/arm9fpga-evolution-board/
- * Subversion repository: svn://194.85.238.22/home/users/george/svn/arm9eb
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/clk.h>
-#include <linux/dma-mapping.h>
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "generic.h"
-#include "gpio.h"
-static void __init afeb9260_init_early(void)
-{
-        /* Initialize processor: 18.432 MHz crystal */
-        at91_initialize(18432000);
-}
-/*
- * USB Host port
- */
-static struct at91_usbh_data __initdata afeb9260_usbh_data = {
-        .ports          = 1,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-/*
- * USB Device port
- */
-static struct at91_udc_data __initdata afeb9260_udc_data = {
-        .vbus_pin       = AT91_PIN_PC5,
-        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
-};
-/*
- * SPI devices.
- */
-static struct spi_board_info afeb9260_spi_devices[] = {
-        {       /* DataFlash chip */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 1,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-};
-/*
- * MACB Ethernet device
- */
-static struct macb_platform_data __initdata afeb9260_macb_data = {
-        .phy_irq_pin    = AT91_PIN_PA9,
-        .is_rmii        = 0,
-};
-/*
- * NAND flash
- */
-static struct mtd_partition __initdata afeb9260_nand_partition[] = {
-        {
-                .name   = "bootloader",
-                .offset = 0,
-                .size   = (640 * SZ_1K),
-        },
-        {
-                .name   = "kernel",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = SZ_2M,
-        },
-        {
-                .name   = "rootfs",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = MTDPART_SIZ_FULL,
-        },
-};
-static struct atmel_nand_data __initdata afeb9260_nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .rdy_pin        = AT91_PIN_PC13,
-        .enable_pin     = AT91_PIN_PC14,
-        .bus_width_16   = 0,
-        .ecc_mode       = NAND_ECC_SOFT,
-        .parts          = afeb9260_nand_partition,
-        .num_parts      = ARRAY_SIZE(afeb9260_nand_partition),
-        .det_pin        = -EINVAL,
-};
-/*
- * MCI (SD/MMC)
- */
-static struct mci_platform_data __initdata afeb9260_mci0_data = {
-        .slot[1] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PC9,
-                .wp_pin         = AT91_PIN_PC4,
-        },
-};
-static struct i2c_board_info __initdata afeb9260_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("tlv320aic23", 0x1a),
-        }, {
-                I2C_BOARD_INFO("fm3130", 0x68),
-        }, {
-                I2C_BOARD_INFO("24c64", 0x50),
-        },
-};
-/*
- * IDE (CF True IDE mode)
- */
-static struct at91_cf_data afeb9260_cf_data = {
-        .chipselect = 4,
-        .irq_pin    = AT91_PIN_PA6,
-        .det_pin        = -EINVAL,
-        .vcc_pin        = -EINVAL,
-        .rst_pin    = AT91_PIN_PA7,
-        .flags      = AT91_CF_TRUE_IDE,
-};
-static void __init afeb9260_board_init(void)
-{
-        at91_register_devices();
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1,
-                             ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR
-                           | ATMEL_UART_DCD | ATMEL_UART_RI);
-        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9260_ID_US1, 2,
-                        ATMEL_UART_CTS | ATMEL_UART_RTS);
-        at91_add_device_serial();
-        /* USB Host */
-        at91_add_device_usbh(&afeb9260_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&afeb9260_udc_data);
-        /* SPI */
-        at91_add_device_spi(afeb9260_spi_devices,
-                        ARRAY_SIZE(afeb9260_spi_devices));
-        /* NAND */
-        at91_add_device_nand(&afeb9260_nand_data);
-        /* Ethernet */
-        at91_add_device_eth(&afeb9260_macb_data);
-        /* Standard function's pin assignments are not
-         * appropriate for us and generic code provide
-         * no API to configure these pins any other way */
-        at91_set_B_periph(AT91_PIN_PA10, 0);    /* ETX2 */
-        at91_set_B_periph(AT91_PIN_PA11, 0);    /* ETX3 */
-        /* MMC */
-        at91_add_device_mci(0, &afeb9260_mci0_data);
-        /* I2C */
-        at91_add_device_i2c(afeb9260_i2c_devices,
-                        ARRAY_SIZE(afeb9260_i2c_devices));
-        /* Audio */
-        at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
-        /* IDE */
-        at91_add_device_cf(&afeb9260_cf_data);
-}
-MACHINE_START(AFEB9260, "Custom afeb9260 board")
-        /* Maintainer: Sergey Lapin <slapin@ossfans.org> */
-        .init_time      = at91_init_time,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = afeb9260_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = afeb9260_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
deleted file mode 100644
index ae827dd2d0d2..000000000000
--- a/arch/arm/mach-at91/board-cam60.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * KwikByte CAM60 (KB9260)
- *
- * based on board-sam9260ek.c
- *   Copyright (C) 2005 SAN People
- *   Copyright (C) 2006 Atmel
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/at91sam9_smc.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "sam9_smc.h"
-#include "generic.h"
-#include "gpio.h"
-static void __init cam60_init_early(void)
-{
-        /* Initialize processor: 10 MHz crystal */
-        at91_initialize(10000000);
-}
-/*
- * USB Host
- */
-static struct at91_usbh_data __initdata cam60_usbh_data = {
-        .ports          = 1,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-/*
- * SPI devices.
- */
-#if defined(CONFIG_MTD_DATAFLASH)
-static struct mtd_partition cam60_spi_partitions[] = {
-        {
-                .name   = "BOOT1",
-                .offset = 0,
-                .size   = 4 * 1056,
-        },
-        {
-                .name   = "BOOT2",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = 256 * 1056,
-        },
-        {
-                .name   = "kernel",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = 2222 * 1056,
-        },
-        {
-                .name   = "file system",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = MTDPART_SIZ_FULL,
-        },
-};
-static struct flash_platform_data cam60_spi_flash_platform_data = {
-        .name           = "spi_flash",
-        .parts          = cam60_spi_partitions,
-        .nr_parts       = ARRAY_SIZE(cam60_spi_partitions)
-};
-#endif
-static struct spi_board_info cam60_spi_devices[] __initdata = {
-#if defined(CONFIG_MTD_DATAFLASH)
-        {       /* DataFlash chip */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-                .platform_data  = &cam60_spi_flash_platform_data
-        },
-#endif
-};
-/*
- * MACB Ethernet device
- */
-static struct macb_platform_data cam60_macb_data __initdata = {
-        .phy_irq_pin    = AT91_PIN_PB5,
-        .is_rmii        = 0,
-};
-/*
- * NAND Flash
- */
-static struct mtd_partition __initdata cam60_nand_partition[] = {
-        {
-                .name   = "nand_fs",
-                .offset = 0,
-                .size   = MTDPART_SIZ_FULL,
-        },
-};
-static struct atmel_nand_data __initdata cam60_nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .det_pin        = -EINVAL,
-        .rdy_pin        = AT91_PIN_PA9,
-        .enable_pin     = AT91_PIN_PA7,
-        .ecc_mode       = NAND_ECC_SOFT,
-        .parts          = cam60_nand_partition,
-        .num_parts      = ARRAY_SIZE(cam60_nand_partition),
-};
-static struct sam9_smc_config __initdata cam60_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 1,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 1,
-        .ncs_read_pulse         = 3,
-        .nrd_pulse              = 3,
-        .ncs_write_pulse        = 3,
-        .nwe_pulse              = 3,
-        .read_cycle             = 5,
-        .write_cycle            = 5,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
-        .tdf_cycles             = 2,
-};
-static void __init cam60_add_device_nand(void)
-{
-        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(0, 3, &cam60_nand_smc_config);
-        at91_add_device_nand(&cam60_nand_data);
-}
-static void __init cam60_board_init(void)
-{
-        at91_register_devices();
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        at91_add_device_serial();
-        /* SPI */
-        at91_add_device_spi(cam60_spi_devices, ARRAY_SIZE(cam60_spi_devices));
-        /* Ethernet */
-        at91_add_device_eth(&cam60_macb_data);
-        /* USB Host */
-        /* enable USB power supply circuit */
-        at91_set_gpio_output(AT91_PIN_PB18, 1);
-        at91_add_device_usbh(&cam60_usbh_data);
-        /* NAND */
-        cam60_add_device_nand();
-}
-MACHINE_START(CAM60, "KwikByte CAM60")
-        /* Maintainer: KwikByte */
-        .init_time      = at91_init_time,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = cam60_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = cam60_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
deleted file mode 100644
index 47313d3ee037..000000000000
--- a/arch/arm/mach-at91/board-carmeva.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-carmeva.c
- *
- *  Copyright (c) 2005 Peer Georgi
- *                     Conitec Datasystems
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "generic.h"
-#include "gpio.h"
-static void __init carmeva_init_early(void)
-{
-        /* Initialize processor: 20.000 MHz crystal */
-        at91_initialize(20000000);
-}
-static struct macb_platform_data __initdata carmeva_eth_data = {
-        .phy_irq_pin    = AT91_PIN_PC4,
-        .is_rmii        = 1,
-};
-static struct at91_usbh_data __initdata carmeva_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-static struct at91_udc_data __initdata carmeva_udc_data = {
-        .vbus_pin       = AT91_PIN_PD12,
-        .pullup_pin     = AT91_PIN_PD9,
-};
-/* FIXME: user dependent */
-// static struct at91_cf_data __initdata carmeva_cf_data = {
-//      .det_pin        = AT91_PIN_PB0,
-//      .rst_pin        = AT91_PIN_PC5,
-        // .irq_pin     = -EINVAL,
-        // .vcc_pin     = -EINVAL,
-// };
-static struct mci_platform_data __initdata carmeva_mci0_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PB10,
-                .wp_pin         = AT91_PIN_PC14,
-        },
-};
-static struct spi_board_info carmeva_spi_devices[] = {
-        { /* DataFlash chip */
-                .modalias = "mtd_dataflash",
-                .chip_select  = 0,
-                .max_speed_hz = 10 * 1000 * 1000,
-        },
-        { /* User accessible spi - cs1 (250KHz) */
-                .modalias = "spi-cs1",
-                .chip_select  = 1,
-                .max_speed_hz = 250 *  1000,
-        },
-        { /* User accessible spi - cs2 (1MHz) */
-                .modalias = "spi-cs2",
-                .chip_select  = 2,
-                .max_speed_hz = 1 * 1000 *  1000,
-        },
-        { /* User accessible spi - cs3 (10MHz) */
-                .modalias = "spi-cs3",
-                .chip_select  = 3,
-                .max_speed_hz = 10 * 1000 *  1000,
-        },
-};
-static struct gpio_led carmeva_leds[] = {
-        { /* "user led 1", LED9 */
-                .name                   = "led9",
-                .gpio                   = AT91_PIN_PA21,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",
-        },
-        { /* "user led 2", LED10 */
-                .name                   = "led10",
-                .gpio                   = AT91_PIN_PA25,
-                .active_low             = 1,
-        },
-        { /* "user led 3", LED11 */
-                .name                   = "led11",
-                .gpio                   = AT91_PIN_PA26,
-                .active_low             = 1,
-        },
-        { /* "user led 4", LED12 */
-                .name                   = "led12",
-                .gpio                   = AT91_PIN_PA18,
-                .active_low             = 1,
-        }
-};
-static void __init carmeva_board_init(void)
-{
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                           | ATMEL_UART_RI);
-        at91_add_device_serial();
-        /* Ethernet */
-        at91_add_device_eth(&carmeva_eth_data);
-        /* USB Host */
-        at91_add_device_usbh(&carmeva_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&carmeva_udc_data);
-        /* I2C */
-        at91_add_device_i2c(NULL, 0);
-        /* SPI */
-        at91_add_device_spi(carmeva_spi_devices, ARRAY_SIZE(carmeva_spi_devices));
-        /* Compact Flash */
-//      at91_add_device_cf(&carmeva_cf_data);
-        /* MMC */
-        at91_add_device_mci(0, &carmeva_mci0_data);
-        /* LEDs */
-        at91_gpio_leds(carmeva_leds, ARRAY_SIZE(carmeva_leds));
-}
-MACHINE_START(CARMEVA, "Carmeva")
-        /* Maintainer: Conitec Datasystems */
-        .init_time      = at91rm9200_timer_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = carmeva_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = carmeva_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
deleted file mode 100644
index 731c8318f4f5..000000000000
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ /dev/null
@@ -1,386 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-cpu9krea.c
- *
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2006 Atmel
- *  Copyright (C) 2009 Eric Benard - eric@eukrea.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/clk.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/mtd/physmap.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91sam9260_matrix.h>
-#include <mach/at91_matrix.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "sam9_smc.h"
-#include "generic.h"
-#include "gpio.h"
-static void __init cpu9krea_init_early(void)
-{
-        /* Initialize processor: 18.432 MHz crystal */
-        at91_initialize(18432000);
-}
-/*
- * USB Host port
- */
-static struct at91_usbh_data __initdata cpu9krea_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-/*
- * USB Device port
- */
-static struct at91_udc_data __initdata cpu9krea_udc_data = {
-        .vbus_pin       = AT91_PIN_PC8,
-        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
-};
-/*
- * MACB Ethernet device
- */
-static struct macb_platform_data __initdata cpu9krea_macb_data = {
-        .phy_irq_pin    = -EINVAL,
-        .is_rmii        = 1,
-};
-/*
- * NAND flash
- */
-static struct atmel_nand_data __initdata cpu9krea_nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .rdy_pin        = AT91_PIN_PC13,
-        .enable_pin     = AT91_PIN_PC14,
-        .bus_width_16   = 0,
-        .det_pin        = -EINVAL,
-        .ecc_mode       = NAND_ECC_SOFT,
-};
-#ifdef CONFIG_MACH_CPU9260
-static struct sam9_smc_config __initdata cpu9krea_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 1,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 1,
-        .ncs_read_pulse         = 3,
-        .nrd_pulse              = 3,
-        .ncs_write_pulse        = 3,
-        .nwe_pulse              = 3,
-        .read_cycle             = 5,
-        .write_cycle            = 5,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
-                | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
-        .tdf_cycles             = 2,
-};
-#else
-static struct sam9_smc_config __initdata cpu9krea_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 2,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 2,
-        .ncs_read_pulse         = 4,
-        .nrd_pulse              = 4,
-        .ncs_write_pulse        = 4,
-        .nwe_pulse              = 4,
-        .read_cycle             = 7,
-        .write_cycle            = 7,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
-                | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
-        .tdf_cycles             = 3,
-};
-#endif
-static void __init cpu9krea_add_device_nand(void)
-{
-        sam9_smc_configure(0, 3, &cpu9krea_nand_smc_config);
-        at91_add_device_nand(&cpu9krea_nand_data);
-}
-/*
- * NOR flash
- */
-static struct physmap_flash_data cpuat9260_nor_data = {
-        .width          = 2,
-};
-#define NOR_BASE        AT91_CHIPSELECT_0
-#define NOR_SIZE        SZ_64M
-static struct resource nor_flash_resources[] = {
-        {
-                .start  = NOR_BASE,
-                .end    = NOR_BASE + NOR_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct platform_device cpu9krea_nor_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &cpuat9260_nor_data,
-        },
-        .resource       = nor_flash_resources,
-        .num_resources  = ARRAY_SIZE(nor_flash_resources),
-};
-#ifdef CONFIG_MACH_CPU9260
-static struct sam9_smc_config __initdata cpu9krea_nor_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 1,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 1,
-        .ncs_read_pulse         = 10,
-        .nrd_pulse              = 10,
-        .ncs_write_pulse        = 6,
-        .nwe_pulse              = 6,
-        .read_cycle             = 12,
-        .write_cycle            = 8,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
-                        | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE
-                        | AT91_SMC_DBW_16,
-        .tdf_cycles             = 2,
-};
-#else
-static struct sam9_smc_config __initdata cpu9krea_nor_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 1,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 1,
-        .ncs_read_pulse         = 13,
-        .nrd_pulse              = 13,
-        .ncs_write_pulse        = 8,
-        .nwe_pulse              = 8,
-        .read_cycle             = 15,
-        .write_cycle            = 10,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
-                        | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE
-                        | AT91_SMC_DBW_16,
-        .tdf_cycles             = 2,
-};
-#endif
-static __init void cpu9krea_add_device_nor(void)
-{
-        unsigned long csa;
-        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
-        at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
-        /* configure chip-select 0 (NOR) */
-        sam9_smc_configure(0, 0, &cpu9krea_nor_smc_config);
-        platform_device_register(&cpu9krea_nor_flash);
-}
-/*
- * LEDs
- */
-static struct gpio_led cpu9krea_leds[] = {
-        {       /* LED1 */
-                .name                   = "LED1",
-                .gpio                   = AT91_PIN_PC11,
-                .active_low             = 1,
-                .default_trigger        = "timer",
-        },
-        {       /* LED2 */
-                .name                   = "LED2",
-                .gpio                   = AT91_PIN_PC12,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",
-        },
-        {       /* LED3 */
-                .name                   = "LED3",
-                .gpio                   = AT91_PIN_PC7,
-                .active_low             = 1,
-                .default_trigger        = "none",
-        },
-        {       /* LED4 */
-                .name                   = "LED4",
-                .gpio                   = AT91_PIN_PC9,
-                .active_low             = 1,
-                .default_trigger        = "none",
-        }
-};
-static struct i2c_board_info __initdata cpu9krea_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("ds1339", 0x68),
-        },
-};
-/*
- * GPIO Buttons
- */
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button cpu9krea_buttons[] = {
-        {
-                .gpio           = AT91_PIN_PC3,
-                .code           = BTN_0,
-                .desc           = "BP1",
-                .active_low     = 1,
-                .wakeup         = 1,
-        },
-        {
-                .gpio           = AT91_PIN_PB20,
-                .code           = BTN_1,
-                .desc           = "BP2",
-                .active_low     = 1,
-                .wakeup         = 1,
-        }
-};
-static struct gpio_keys_platform_data cpu9krea_button_data = {
-        .buttons        = cpu9krea_buttons,
-        .nbuttons       = ARRAY_SIZE(cpu9krea_buttons),
-};
-static struct platform_device cpu9krea_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &cpu9krea_button_data,
-        }
-};
-static void __init cpu9krea_add_device_buttons(void)
-{
-        at91_set_gpio_input(AT91_PIN_PC3, 1);   /* BP1 */
-        at91_set_deglitch(AT91_PIN_PC3, 1);
-        at91_set_gpio_input(AT91_PIN_PB20, 1);  /* BP2 */
-        at91_set_deglitch(AT91_PIN_PB20, 1);
-        platform_device_register(&cpu9krea_button_device);
-}
-#else
-static void __init cpu9krea_add_device_buttons(void)
-{
-}
-#endif
-/*
- * MCI (SD/MMC)
- */
-static struct mci_platform_data __initdata cpu9krea_mci0_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PA29,
-                .wp_pin         = -EINVAL,
-        },
-};
-static void __init cpu9krea_board_init(void)
-{
-        at91_register_devices();
-        /* NOR */
-        cpu9krea_add_device_nor();
-        /* Serial */
-        /* DGBU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS |
-                ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR |
-                ATMEL_UART_DCD | ATMEL_UART_RI);
-        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS |
-                ATMEL_UART_RTS);
-        /* USART2 on ttyS3. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS |
-                ATMEL_UART_RTS);
-        /* USART3 on ttyS4. (Rx, Tx) */
-        at91_register_uart(AT91SAM9260_ID_US3, 4, 0);
-        /* USART4 on ttyS5. (Rx, Tx) */
-        at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
-        /* USART5 on ttyS6. (Rx, Tx) */
-        at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
-        at91_add_device_serial();
-        /* USB Host */
-        at91_add_device_usbh(&cpu9krea_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&cpu9krea_udc_data);
-        /* NAND */
-        cpu9krea_add_device_nand();
-        /* Ethernet */
-        at91_add_device_eth(&cpu9krea_macb_data);
-        /* MMC */
-        at91_add_device_mci(0, &cpu9krea_mci0_data);
-        /* I2C */
-        at91_add_device_i2c(cpu9krea_i2c_devices,
-                ARRAY_SIZE(cpu9krea_i2c_devices));
-        /* LEDs */
-        at91_gpio_leds(cpu9krea_leds, ARRAY_SIZE(cpu9krea_leds));
-        /* Push Buttons */
-        cpu9krea_add_device_buttons();
-}
-#ifdef CONFIG_MACH_CPU9260
-MACHINE_START(CPUAT9260, "Eukrea CPU9260")
-#else
-MACHINE_START(CPUAT9G20, "Eukrea CPU9G20")
-#endif
-        /* Maintainer: Eric Benard - EUKREA Electromatique */
-        .init_time      = at91_init_time,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = cpu9krea_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = cpu9krea_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
deleted file mode 100644
index c094350c9314..000000000000
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-cpuat91.c
- *
- *  Copyright (C) 2009 Eric Benard - eric@eukrea.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/plat-ram.h>
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
-#include <mach/cpu.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "generic.h"
-#include "gpio.h"
-static struct gpio_led cpuat91_leds[] = {
-        {
-                .name                   = "led1",
-                .default_trigger        = "heartbeat",
-                .active_low             = 1,
-                .gpio                   = AT91_PIN_PC0,
-        },
-};
-static void __init cpuat91_init_early(void)
-{
-        /* Set cpu type: PQFP */
-        at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
-        /* Initialize processor: 18.432 MHz crystal */
-        at91_initialize(18432000);
-}
-static struct macb_platform_data __initdata cpuat91_eth_data = {
-        .phy_irq_pin    = -EINVAL,
-        .is_rmii        = 1,
-};
-static struct at91_usbh_data __initdata cpuat91_usbh_data = {
-        .ports          = 1,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-static struct at91_udc_data __initdata cpuat91_udc_data = {
-        .vbus_pin       = AT91_PIN_PC15,
-        .pullup_pin     = AT91_PIN_PC14,
-};
-static struct mci_platform_data __initdata cpuat91_mci0_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PC2,
-                .wp_pin         = -EINVAL,
-        },
-};
-static struct physmap_flash_data cpuat91_flash_data = {
-        .width          = 2,
-};
-static struct resource cpuat91_flash_resource = {
-        .start          = AT91_CHIPSELECT_0,
-        .end            = AT91_CHIPSELECT_0 + SZ_16M - 1,
-        .flags          = IORESOURCE_MEM,
-};
-static struct platform_device cpuat91_norflash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev    = {
-                .platform_data  = &cpuat91_flash_data,
-        },
-        .resource       = &cpuat91_flash_resource,
-        .num_resources  = 1,
-};
-#ifdef CONFIG_MTD_PLATRAM
-struct platdata_mtd_ram at91_sram_pdata = {
-        .mapname        = "SRAM",
-        .bankwidth      = 2,
-};
-static struct resource at91_sram_resource[] = {
-        [0] = {
-                .start = AT91RM9200_SRAM_BASE,
-                .end   = AT91RM9200_SRAM_BASE + AT91RM9200_SRAM_SIZE - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-static struct platform_device at91_sram = {
-        .name           = "mtd-ram",
-        .id             = 0,
-        .resource       = at91_sram_resource,
-        .num_resources  = ARRAY_SIZE(at91_sram_resource),
-        .dev    = {
-                .platform_data = &at91_sram_pdata,
-        },
-};
-#endif /* MTD_PLATRAM */
-static struct platform_device *platform_devices[] __initdata = {
-        &cpuat91_norflash,
-#ifdef CONFIG_MTD_PLATRAM
-        &at91_sram,
-#endif /* CONFIG_MTD_PLATRAM */
-};
-static void __init cpuat91_board_init(void)
-{
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
-        at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS |
-                ATMEL_UART_RTS);
-        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS |
-                ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR |
-                ATMEL_UART_DCD | ATMEL_UART_RI);
-        /* USART2 on ttyS3 (Rx, Tx) */
-        at91_register_uart(AT91RM9200_ID_US2, 3, 0);
-        /* USART3 on ttyS4 (Rx, Tx, CTS, RTS) */
-        at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_CTS |
-                ATMEL_UART_RTS);
-        at91_add_device_serial();
-        /* LEDs. */
-        at91_gpio_leds(cpuat91_leds, ARRAY_SIZE(cpuat91_leds));
-        /* Ethernet */
-        at91_add_device_eth(&cpuat91_eth_data);
-        /* USB Host */
-        at91_add_device_usbh(&cpuat91_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&cpuat91_udc_data);
-        /* MMC */
-        at91_add_device_mci(0, &cpuat91_mci0_data);
-        /* I2C */
-        at91_add_device_i2c(NULL, 0);
-        /* Platform devices */
-        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-}
-MACHINE_START(CPUAT91, "Eukrea")
-        /* Maintainer: Eric Benard - EUKREA Electromatique */
-        .init_time      = at91rm9200_timer_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = cpuat91_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = cpuat91_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
deleted file mode 100644
index 0e35a45cf8d4..000000000000
--- a/arch/arm/mach-at91/board-csb337.c
+++ /dev/null
@@ -1,260 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-csb337.c
- *
- *  Copyright (C) 2005 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/mtd/physmap.h>
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "generic.h"
-#include "gpio.h"
-static void __init csb337_init_early(void)
-{
-        /* Initialize processor: 3.6864 MHz crystal */
-        at91_initialize(3686400);
-}
-static struct macb_platform_data __initdata csb337_eth_data = {
-        .phy_irq_pin    = AT91_PIN_PC2,
-        .is_rmii        = 0,
-        /* The CSB337 bootloader stores the MAC the wrong-way around */
-        .rev_eth_addr   = 1,
-};
-static struct at91_usbh_data __initdata csb337_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-static struct at91_udc_data __initdata csb337_udc_data = {
-        .pullup_pin     = AT91_PIN_PA24,
-        .vbus_pin       = -EINVAL,
-};
-static struct i2c_board_info __initdata csb337_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("ds1307", 0x68),
-        },
-};
-static struct at91_cf_data __initdata csb337_cf_data = {
-        /*
-         * connector P4 on the CSB 337 mates to
-         * connector P8 on the CSB 300CF
-         */
-        /* CSB337 specific */
-        .det_pin        = AT91_PIN_PC3,
-        /* CSB300CF specific */
-        .irq_pin        = AT91_PIN_PA19,
-        .vcc_pin        = AT91_PIN_PD0,
-        .rst_pin        = AT91_PIN_PD2,
-};
-static struct mci_platform_data __initdata csb337_mci0_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PD5,
-                .wp_pin         = AT91_PIN_PD6,
-        },
-};
-static struct spi_board_info csb337_spi_devices[] = {
-        {       /* CAN controller */
-                .modalias       = "sak82c900",
-                .chip_select    = 0,
-                .max_speed_hz   = 6 * 1000 * 1000,
-        },
-};
-#define CSB_FLASH_BASE  AT91_CHIPSELECT_0
-#define CSB_FLASH_SIZE  SZ_8M
-static struct mtd_partition csb_flash_partitions[] = {
-        {
-                .name           = "uMON flash",
-                .offset         = 0,
-                .size           = MTDPART_SIZ_FULL,
-                .mask_flags     = MTD_WRITEABLE,        /* read only */
-        }
-};
-static struct physmap_flash_data csb_flash_data = {
-        .width          = 2,
-        .parts          = csb_flash_partitions,
-        .nr_parts       = ARRAY_SIZE(csb_flash_partitions),
-};
-static struct resource csb_flash_resources[] = {
-        {
-                .start  = CSB_FLASH_BASE,
-                .end    = CSB_FLASH_BASE + CSB_FLASH_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct platform_device csb_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                                .platform_data = &csb_flash_data,
-                        },
-        .resource       = csb_flash_resources,
-        .num_resources  = ARRAY_SIZE(csb_flash_resources),
-};
-/*
- * GPIO Buttons (on CSB300)
- */
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button csb300_buttons[] = {
-        {
-                .gpio           = AT91_PIN_PB29,
-                .code           = BTN_0,
-                .desc           = "sw0",
-                .active_low     = 1,
-                .wakeup         = 1,
-        },
-        {
-                .gpio           = AT91_PIN_PB28,
-                .code           = BTN_1,
-                .desc           = "sw1",
-                .active_low     = 1,
-                .wakeup         = 1,
-        },
-        {
-                .gpio           = AT91_PIN_PA21,
-                .code           = BTN_2,
-                .desc           = "sw2",
-                .active_low     = 1,
-                .wakeup         = 1,
-        }
-};
-static struct gpio_keys_platform_data csb300_button_data = {
-        .buttons        = csb300_buttons,
-        .nbuttons       = ARRAY_SIZE(csb300_buttons),
-};
-static struct platform_device csb300_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &csb300_button_data,
-        }
-};
-static void __init csb300_add_device_buttons(void)
-{
-        at91_set_gpio_input(AT91_PIN_PB29, 1);  /* sw0 */
-        at91_set_deglitch(AT91_PIN_PB29, 1);
-        at91_set_gpio_input(AT91_PIN_PB28, 1);  /* sw1 */
-        at91_set_deglitch(AT91_PIN_PB28, 1);
-        at91_set_gpio_input(AT91_PIN_PA21, 1);  /* sw2 */
-        at91_set_deglitch(AT91_PIN_PA21, 1);
-        platform_device_register(&csb300_button_device);
-}
-#else
-static void __init csb300_add_device_buttons(void) {}
-#endif
-static struct gpio_led csb_leds[] = {
-        {       /* "led0", yellow */
-                .name                   = "led0",
-                .gpio                   = AT91_PIN_PB2,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",
-        },
-        {       /* "led1", green */
-                .name                   = "led1",
-                .gpio                   = AT91_PIN_PB1,
-                .active_low             = 1,
-                .default_trigger        = "mmc0",
-        },
-        {       /* "led2", yellow */
-                .name                   = "led2",
-                .gpio                   = AT91_PIN_PB0,
-                .active_low             = 1,
-                .default_trigger        = "ide-disk",
-        }
-};
-static void __init csb337_board_init(void)
-{
-        /* Serial */
-        /* DBGU on ttyS0 */
-        at91_register_uart(0, 0, 0);
-        at91_add_device_serial();
-        /* Ethernet */
-        at91_add_device_eth(&csb337_eth_data);
-        /* USB Host */
-        at91_add_device_usbh(&csb337_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&csb337_udc_data);
-        /* I2C */
-        at91_add_device_i2c(csb337_i2c_devices, ARRAY_SIZE(csb337_i2c_devices));
-        /* Compact Flash */
-        at91_set_gpio_input(AT91_PIN_PB22, 1);          /* IOIS16 */
-        at91_add_device_cf(&csb337_cf_data);
-        /* SPI */
-        at91_add_device_spi(csb337_spi_devices, ARRAY_SIZE(csb337_spi_devices));
-        /* MMC */
-        at91_add_device_mci(0, &csb337_mci0_data);
-        /* NOR flash */
-        platform_device_register(&csb_flash);
-        /* LEDs */
-        at91_gpio_leds(csb_leds, ARRAY_SIZE(csb_leds));
-        /* Switches on CSB300 */
-        csb300_add_device_buttons();
-}
-MACHINE_START(CSB337, "Cogent CSB337")
-        /* Maintainer: Bill Gatliff */
-        .init_time      = at91rm9200_timer_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = csb337_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = csb337_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
deleted file mode 100644
index 18d027f529a8..000000000000
--- a/arch/arm/mach-at91/board-csb637.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-csb637.c
- *
- *  Copyright (C) 2005 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "generic.h"
-#include "gpio.h"
-static void __init csb637_init_early(void)
-{
-        /* Initialize processor: 3.6864 MHz crystal */
-        at91_initialize(3686400);
-}
-static struct macb_platform_data __initdata csb637_eth_data = {
-        .phy_irq_pin    = AT91_PIN_PC0,
-        .is_rmii        = 0,
-};
-static struct at91_usbh_data __initdata csb637_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-static struct at91_udc_data __initdata csb637_udc_data = {
-        .vbus_pin     = AT91_PIN_PB28,
-        .pullup_pin   = AT91_PIN_PB1,
-};
-#define CSB_FLASH_BASE  AT91_CHIPSELECT_0
-#define CSB_FLASH_SIZE  SZ_16M
-static struct mtd_partition csb_flash_partitions[] = {
-        {
-                .name           = "uMON flash",
-                .offset         = 0,
-                .size           = MTDPART_SIZ_FULL,
-                .mask_flags     = MTD_WRITEABLE,        /* read only */
-        }
-};
-static struct physmap_flash_data csb_flash_data = {
-        .width          = 2,
-        .parts          = csb_flash_partitions,
-        .nr_parts       = ARRAY_SIZE(csb_flash_partitions),
-};
-static struct resource csb_flash_resources[] = {
-        {
-                .start  = CSB_FLASH_BASE,
-                .end    = CSB_FLASH_BASE + CSB_FLASH_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct platform_device csb_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                                .platform_data = &csb_flash_data,
-                        },
-        .resource       = csb_flash_resources,
-        .num_resources  = ARRAY_SIZE(csb_flash_resources),
-};
-static struct gpio_led csb_leds[] = {
-        {       /* "d1", red */
-                .name                   = "d1",
-                .gpio                   = AT91_PIN_PB2,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",
-        },
-};
-static void __init csb637_board_init(void)
-{
-        /* LED(s) */
-        at91_gpio_leds(csb_leds, ARRAY_SIZE(csb_leds));
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        at91_add_device_serial();
-        /* Ethernet */
-        at91_add_device_eth(&csb637_eth_data);
-        /* USB Host */
-        at91_add_device_usbh(&csb637_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&csb637_udc_data);
-        /* I2C */
-        at91_add_device_i2c(NULL, 0);
-        /* SPI */
-        at91_add_device_spi(NULL, 0);
-        /* NOR flash */
-        platform_device_register(&csb_flash);
-}
-MACHINE_START(CSB637, "Cogent CSB637")
-        /* Maintainer: Bill Gatliff */
-        .init_time      = at91rm9200_timer_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = csb637_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = csb637_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 226563f850b8..76dfe8f9af50 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -22,14 +22,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include "at91_aic.h"
 #include "generic.h"
 static void __init at91rm9200_dt_timer_init(void)
 {
-#if defined(CONFIG_COMMON_CLK)
        of_clk_init(NULL);
-#endif
        at91rm9200_timer_init();
 }
diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
index d3048ccdc41f..f99246aa9b38 100644
--- a/arch/arm/mach-at91/board-dt-sam9.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
@@ -21,8 +21,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include "at91_aic.h"
-#include "board.h"
 #include "generic.h"
 static const char *at91_dt_board_compat[] __initdata = {
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 129e2917506b..8fb9ef5333f1 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -24,7 +24,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include "at91_aic.h"
 #include "generic.h"
 static void __init sama5_dt_device_init(void)
diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c
deleted file mode 100644
index becf0a6a289e..000000000000
--- a/arch/arm/mach-at91/board-eb01.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * arch/arm/mach-at91/board-eb01.c
- *
- * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/irq.h>
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "generic.h"
-static void __init at91eb01_init_irq(void)
-{
-        at91x40_init_interrupts(NULL);
-}
-static void __init at91eb01_init_early(void)
-{
-        at91x40_initialize(40000000);
-}
-MACHINE_START(AT91EB01, "Atmel AT91 EB01")
-        /* Maintainer: Greg Ungerer <gerg@snapgear.com> */
-        .init_time      = at91x40_timer_init,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = at91eb01_init_early,
-        .init_irq       = at91eb01_init_irq,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
deleted file mode 100644
index aa457a8b22f5..000000000000
--- a/arch/arm/mach-at91/board-eb9200.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-eb9200.c
- *
- *  Copyright (C) 2005 SAN People, adapted for ATEB9200 from Embest
- *  by Andrew Patrikalakis
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/device.h>
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "generic.h"
-#include "gpio.h"
-static void __init eb9200_init_early(void)
-{
-        /* Initialize processor: 18.432 MHz crystal */
-        at91_initialize(18432000);
-}
-static struct macb_platform_data __initdata eb9200_eth_data = {
-        .phy_irq_pin    = AT91_PIN_PC4,
-        .is_rmii        = 1,
-};
-static struct at91_usbh_data __initdata eb9200_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-static struct at91_udc_data __initdata eb9200_udc_data = {
-        .vbus_pin       = AT91_PIN_PD4,
-        .pullup_pin     = AT91_PIN_PD5,
-};
-static struct at91_cf_data __initdata eb9200_cf_data = {
-        .irq_pin        = -EINVAL,
-        .det_pin        = AT91_PIN_PB0,
-        .vcc_pin        = -EINVAL,
-        .rst_pin        = AT91_PIN_PC5,
-};
-static struct mci_platform_data __initdata eb9200_mci0_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = -EINVAL,
-                .wp_pin         = -EINVAL,
-        },
-};
-static struct i2c_board_info __initdata eb9200_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("24c512", 0x50),
-        },
-};
-static void __init eb9200_board_init(void)
-{
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                        | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                        | ATMEL_UART_RI);
-        /* USART2 on ttyS2. (Rx, Tx) - IRDA */
-        at91_register_uart(AT91RM9200_ID_US2, 2, 0);
-        at91_add_device_serial();
-        /* Ethernet */
-        at91_add_device_eth(&eb9200_eth_data);
-        /* USB Host */
-        at91_add_device_usbh(&eb9200_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&eb9200_udc_data);
-        /* I2C */
-        at91_add_device_i2c(eb9200_i2c_devices, ARRAY_SIZE(eb9200_i2c_devices));
-        /* Compact Flash */
-        at91_add_device_cf(&eb9200_cf_data);
-        /* SPI */
-        at91_add_device_spi(NULL, 0);
-        /* MMC */
-        /* only supports 1 or 4 bit interface, not wired through to SPI */
-        at91_add_device_mci(0, &eb9200_mci0_data);
-}
-MACHINE_START(ATEB9200, "Embest ATEB9200")
-        .init_time      = at91rm9200_timer_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = eb9200_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = eb9200_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
deleted file mode 100644
index ede1373ccaba..000000000000
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * linux/arch/arm/mach-at91rm9200/board-ecbat91.c
- * Copyright (C) 2007 emQbit.com.
- *
- * We started from board-dk.c, which is Copyright (C) 2005 SAN People.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/cpu.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "generic.h"
-#include "gpio.h"
-static void __init ecb_at91init_early(void)
-{
-        /* Set cpu type: PQFP */
-        at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
-        /* Initialize processor: 18.432 MHz crystal */
-        at91_initialize(18432000);
-}
-static struct macb_platform_data __initdata ecb_at91eth_data = {
-        .phy_irq_pin    = AT91_PIN_PC4,
-        .is_rmii        = 0,
-};
-static struct at91_usbh_data __initdata ecb_at91usbh_data = {
-        .ports          = 1,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-static struct mci_platform_data __initdata ecbat91_mci0_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = -EINVAL,
-                .wp_pin         = -EINVAL,
-        },
-};
-#if defined(CONFIG_MTD_DATAFLASH)
-static struct mtd_partition __initdata my_flash0_partitions[] =
-{
-        {       /* 0x8400 */
-                .name   = "Darrell-loader",
-                .offset = 0,
-                .size   = 12 * 1056,
-        },
-        {
-                .name   = "U-boot",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = 110 * 1056,
-        },
-        {       /* 1336 (167 blocks) pages * 1056 bytes = 0x158700 bytes */
-                .name   = "UBoot-env",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = 8 * 1056,
-        },
-        {       /* 1336 (167 blocks) pages * 1056 bytes = 0x158700 bytes */
-                .name   = "Kernel",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = 1534 * 1056,
-        },
-        {       /* 190200 - jffs2 root filesystem */
-                .name   = "Filesystem",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = MTDPART_SIZ_FULL,     /* 26 sectors */
-        }
-};
-static struct flash_platform_data __initdata my_flash0_platform = {
-        .name           = "Removable flash card",
-        .parts          = my_flash0_partitions,
-        .nr_parts       = ARRAY_SIZE(my_flash0_partitions)
-};
-#endif
-static struct spi_board_info __initdata ecb_at91spi_devices[] = {
-        {       /* DataFlash chip */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 10 * 1000 * 1000,
-                .bus_num        = 0,
-#if defined(CONFIG_MTD_DATAFLASH)
-                .platform_data  = &my_flash0_platform,
-#endif
-        },
-        {       /* User accessible spi - cs1 (250KHz) */
-                .modalias       = "spi-cs1",
-                .chip_select    = 1,
-                .max_speed_hz   = 250 * 1000,
-        },
-        {       /* User accessible spi - cs2 (1MHz) */
-                .modalias       = "spi-cs2",
-                .chip_select    = 2,
-                .max_speed_hz   = 1 * 1000 * 1000,
-        },
-        {       /* User accessible spi - cs3 (10MHz) */
-                .modalias       = "spi-cs3",
-                .chip_select    = 3,
-                .max_speed_hz   = 10 * 1000 * 1000,
-        },
-};
-/*
- * LEDs
- */
-static struct gpio_led ecb_leds[] = {
-        {       /* D1 */
-                .name                   = "led1",
-                .gpio                   = AT91_PIN_PC7,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",
-        }
-};
-static void __init ecb_at91board_init(void)
-{
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx & Tx only) */
-        at91_register_uart(AT91RM9200_ID_US0, 1, 0);
-        at91_add_device_serial();
-        /* Ethernet */
-        at91_add_device_eth(&ecb_at91eth_data);
-        /* USB Host */
-        at91_add_device_usbh(&ecb_at91usbh_data);
-        /* I2C */
-        at91_add_device_i2c(NULL, 0);
-        /* MMC */
-        at91_add_device_mci(0, &ecbat91_mci0_data);
-        /* SPI */
-        at91_add_device_spi(ecb_at91spi_devices, ARRAY_SIZE(ecb_at91spi_devices));
-        /* LEDs */
-        at91_gpio_leds(ecb_leds, ARRAY_SIZE(ecb_leds));
-}
-MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
-        /* Maintainer: emQbit.com */
-        .init_time      = at91rm9200_timer_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = ecb_at91init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = ecb_at91board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
deleted file mode 100644
index 4e75321a8f2a..000000000000
--- a/arch/arm/mach-at91/board-eco920.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
- */
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
-#include <mach/cpu.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "generic.h"
-#include "gpio.h"
-static void __init eco920_init_early(void)
-{
-        /* Set cpu type: PQFP */
-        at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
-        at91_initialize(18432000);
-}
-static struct macb_platform_data __initdata eco920_eth_data = {
-        .phy_irq_pin    = AT91_PIN_PC2,
-        .is_rmii        = 1,
-};
-static struct at91_usbh_data __initdata eco920_usbh_data = {
-        .ports          = 1,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-static struct at91_udc_data __initdata eco920_udc_data = {
-        .vbus_pin       = AT91_PIN_PB12,
-        .pullup_pin     = AT91_PIN_PB13,
-};
-static struct mci_platform_data __initdata eco920_mci0_data = {
-        .slot[0] = {
-                .bus_width      = 1,
-                .detect_pin     = -EINVAL,
-                .wp_pin         = -EINVAL,
-        },
-};
-static struct physmap_flash_data eco920_flash_data = {
-        .width  = 2,
-};
-static struct resource eco920_flash_resource = {
-        .start          = 0x11000000,
-        .end            = 0x11ffffff,
-        .flags          = IORESOURCE_MEM,
-};
-static struct platform_device eco920_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &eco920_flash_data,
-        },
-        .resource       = &eco920_flash_resource,
-        .num_resources  = 1,
-};
-static struct spi_board_info eco920_spi_devices[] = {
-        {       /* CAN controller */
-                .modalias       = "tlv5638",
-                .chip_select    = 3,
-                .max_speed_hz   = 20 * 1000 * 1000,
-                .mode           = SPI_CPHA,
-        },
-};
-/*
- * LEDs
- */
-static struct gpio_led eco920_leds[] = {
-        {       /* D1 */
-                .name                   = "led1",
-                .gpio                   = AT91_PIN_PB0,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",
-        },
-        {       /* D2 */
-                .name                   = "led2",
-                .gpio                   = AT91_PIN_PB1,
-                .active_low             = 1,
-                .default_trigger        = "timer",
-        }
-};
-static void __init eco920_board_init(void)
-{
-        /* DBGU on ttyS0. (Rx & Tx only */
-        at91_register_uart(0, 0, 0);
-        at91_add_device_serial();
-        at91_add_device_eth(&eco920_eth_data);
-        at91_add_device_usbh(&eco920_usbh_data);
-        at91_add_device_udc(&eco920_udc_data);
-        at91_add_device_mci(0, &eco920_mci0_data);
-        platform_device_register(&eco920_flash);
-        at91_ramc_write(0, AT91_SMC_CSR(7),     AT91_SMC_RWHOLD_(1)
-                                | AT91_SMC_RWSETUP_(1)
-                                | AT91_SMC_DBW_8
-                                | AT91_SMC_WSEN
-                                | AT91_SMC_NWS_(15));
-        at91_set_A_periph(AT91_PIN_PC6, 1);
-        at91_set_gpio_input(AT91_PIN_PA23, 0);
-        at91_set_deglitch(AT91_PIN_PA23, 1);
-/* Initialization of the Static Memory Controller for Chip Select 3 */
-        at91_ramc_write(0, AT91_SMC_CSR(3),
-                AT91_SMC_DBW_16  |      /* 16 bit */
-                AT91_SMC_WSEN    |
-                AT91_SMC_NWS_(5) |      /* wait states */
-                AT91_SMC_TDF_(1)        /* float time */
-        );
-        at91_add_device_spi(eco920_spi_devices, ARRAY_SIZE(eco920_spi_devices));
-        /* LEDs */
-        at91_gpio_leds(eco920_leds, ARRAY_SIZE(eco920_leds));
-}
-MACHINE_START(ECO920, "eco920")
-        /* Maintainer: Sascha Hauer */
-        .init_time      = at91rm9200_timer_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = eco920_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = eco920_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
deleted file mode 100644
index a6aa4a2432f2..000000000000
--- a/arch/arm/mach-at91/board-flexibity.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-flexibity.c
- *
- *  Copyright (C) 2010-2011 Flexibity
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2006 Atmel
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/input.h>
-#include <linux/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "generic.h"
-#include "gpio.h"
-static void __init flexibity_init_early(void)
-{
-        /* Initialize processor: 18.432 MHz crystal */
-        at91_initialize(18432000);
-}
-/* USB Host port */
-static struct at91_usbh_data __initdata flexibity_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-/* USB Device port */
-static struct at91_udc_data __initdata flexibity_udc_data = {
-        .vbus_pin       = AT91_PIN_PC5,
-        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
-};
-/* I2C devices */
-static struct i2c_board_info __initdata flexibity_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("ds1307", 0x68),
-        },
-};
-/* SPI devices */
-static struct spi_board_info flexibity_spi_devices[] = {
-        {       /* DataFlash chip */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 1,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-};
-/* MCI (SD/MMC) */
-static struct mci_platform_data __initdata flexibity_mci0_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PC9,
-                .wp_pin         = AT91_PIN_PC4,
-        },
-};
-/* LEDs */
-static struct gpio_led flexibity_leds[] = {
-        {
-                .name                   = "usb1:green",
-                .gpio                   = AT91_PIN_PA12,
-                .active_low             = 1,
-                .default_trigger        = "default-on",
-        },
-        {
-                .name                   = "usb1:red",
-                .gpio                   = AT91_PIN_PA13,
-                .active_low             = 1,
-                .default_trigger        = "default-on",
-        },
-        {
-                .name                   = "usb2:green",
-                .gpio                   = AT91_PIN_PB26,
-                .active_low             = 1,
-                .default_trigger        = "default-on",
-        },
-        {
-                .name                   = "usb2:red",
-                .gpio                   = AT91_PIN_PB27,
-                .active_low             = 1,
-                .default_trigger        = "default-on",
-        },
-        {
-                .name                   = "usb3:green",
-                .gpio                   = AT91_PIN_PC8,
-                .active_low             = 1,
-                .default_trigger        = "default-on",
-        },
-        {
-                .name                   = "usb3:red",
-                .gpio                   = AT91_PIN_PC6,
-                .active_low             = 1,
-                .default_trigger        = "default-on",
-        },
-        {
-                .name                   = "usb4:green",
-                .gpio                   = AT91_PIN_PB4,
-                .active_low             = 1,
-                .default_trigger        = "default-on",
-        },
-        {
-                .name                   = "usb4:red",
-                .gpio                   = AT91_PIN_PB5,
-                .active_low             = 1,
-                .default_trigger        = "default-on",
-        }
-};
-static void __init flexibity_board_init(void)
-{
-        at91_register_devices();
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        at91_add_device_serial();
-        /* USB Host */
-        at91_add_device_usbh(&flexibity_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&flexibity_udc_data);
-        /* I2C */
-        at91_add_device_i2c(flexibity_i2c_devices,
-                ARRAY_SIZE(flexibity_i2c_devices));
-        /* SPI */
-        at91_add_device_spi(flexibity_spi_devices,
-                ARRAY_SIZE(flexibity_spi_devices));
-        /* MMC */
-        at91_add_device_mci(0, &flexibity_mci0_data);
-        /* LEDs */
-        at91_gpio_leds(flexibity_leds, ARRAY_SIZE(flexibity_leds));
-}
-MACHINE_START(FLEXIBITY, "Flexibity Connect")
-        /* Maintainer: Maxim Osipov */
-        .init_time      = at91_init_time,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = flexibity_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = flexibity_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
deleted file mode 100644
index bf5cc55c7db6..000000000000
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ /dev/null
@@ -1,585 +0,0 @@
-/*
- *  Copyright (C) 2010 Christian Glindkamp <christian.glindkamp@taskit.de>
- *                     taskit GmbH
- *                2010 Igor Plyatov <plyatov@gmail.com>
- *                     GeoSIG Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/w1-gpio.h>
-#include <linux/i2c.h>
-#include <linux/i2c/pcf857x.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/hardware.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "sam9_smc.h"
-#include "generic.h"
-#include "gsia18s.h"
-#include "stamp9g20.h"
-#include "gpio.h"
-static void __init gsia18s_init_early(void)
-{
-        stamp9g20_init_early();
-}
-/*
- * Two USB Host ports
- */
-static struct at91_usbh_data __initdata usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-/*
- * USB Device port
- */
-static struct at91_udc_data __initdata udc_data = {
-        .vbus_pin       = AT91_PIN_PA22,
-        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
-};
-/*
- * MACB Ethernet device
- */
-static struct macb_platform_data __initdata macb_data = {
-        .phy_irq_pin    = AT91_PIN_PA28,
-        .is_rmii        = 1,
-};
-/*
- * LEDs and GPOs
- */
-static struct gpio_led gpio_leds[] = {
-        {
-                .name                   = "gpo:spi1reset",
-                .gpio                   = AT91_PIN_PC1,
-                .active_low             = 0,
-                .default_trigger        = "none",
-                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
-        },
-        {
-                .name                   = "gpo:trig_net_out",
-                .gpio                   = AT91_PIN_PB20,
-                .active_low             = 0,
-                .default_trigger        = "none",
-                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
-        },
-        {
-                .name                   = "gpo:trig_net_dir",
-                .gpio                   = AT91_PIN_PB19,
-                .active_low             = 0,
-                .default_trigger        = "none",
-                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
-        },
-        {
-                .name                   = "gpo:charge_dis",
-                .gpio                   = AT91_PIN_PC2,
-                .active_low             = 0,
-                .default_trigger        = "none",
-                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
-        },
-        {
-                .name                   = "led:event",
-                .gpio                   = AT91_PIN_PB17,
-                .active_low             = 1,
-                .default_trigger        = "none",
-                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
-        },
-        {
-                .name                   = "led:lan",
-                .gpio                   = AT91_PIN_PB18,
-                .active_low             = 1,
-                .default_trigger        = "none",
-                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
-        },
-        {
-                .name                   = "led:error",
-                .gpio                   = AT91_PIN_PB16,
-                .active_low             = 1,
-                .default_trigger        = "none",
-                .default_state          = LEDS_GPIO_DEFSTATE_ON,
-        }
-};
-static struct gpio_led_platform_data gpio_led_info = {
-        .leds           = gpio_leds,
-        .num_leds       = ARRAY_SIZE(gpio_leds),
-};
-static struct platform_device leds = {
-        .name   = "leds-gpio",
-        .id     = 0,
-        .dev    = {
-                .platform_data  = &gpio_led_info,
-        }
-};
-static void __init gsia18s_leds_init(void)
-{
-        platform_device_register(&leds);
-}
-/* PCF8574 0x20 GPIO - U1 on the GS_IA18-CB_V3 board */
-static struct gpio_led pcf_gpio_leds1[] = {
-        { /* bit 0 */
-                .name                   = "gpo:hdc_power",
-                .gpio                   = PCF_GPIO_HDC_POWER,
-                .active_low             = 0,
-                .default_trigger        = "none",
-                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
-        },
-        { /* bit 1 */
-                .name                   = "gpo:wifi_setup",
-                .gpio                   = PCF_GPIO_WIFI_SETUP,
-                .active_low             = 1,
-                .default_trigger        = "none",
-                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
-        },
-        { /* bit 2 */
-                .name                   = "gpo:wifi_enable",
-                .gpio                   = PCF_GPIO_WIFI_ENABLE,
-                .active_low             = 1,
-                .default_trigger        = "none",
-                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
-        },
-        { /* bit 3      */
-                .name                   = "gpo:wifi_reset",
-                .gpio                   = PCF_GPIO_WIFI_RESET,
-                .active_low             = 1,
-                .default_trigger        = "none",
-                .default_state          = LEDS_GPIO_DEFSTATE_ON,
-        },
-        /* bit 4 used as GPI    */
-        { /* bit 5 */
-                .name                   = "gpo:gps_setup",
-                .gpio                   = PCF_GPIO_GPS_SETUP,
-                .active_low             = 1,
-                .default_trigger        = "none",
-                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
-        },
-        { /* bit 6 */
-                .name                   = "gpo:gps_standby",
-                .gpio                   = PCF_GPIO_GPS_STANDBY,
-                .active_low             = 0,
-                .default_trigger        = "none",
-                .default_state          = LEDS_GPIO_DEFSTATE_ON,
-        },
-        { /* bit 7 */
-                .name                   = "gpo:gps_power",
-                .gpio                   = PCF_GPIO_GPS_POWER,
-                .active_low             = 0,
-                .default_trigger        = "none",
-                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
-        }
-};
-static struct gpio_led_platform_data pcf_gpio_led_info1 = {
-        .leds           = pcf_gpio_leds1,
-        .num_leds       = ARRAY_SIZE(pcf_gpio_leds1),
-};
-static struct platform_device pcf_leds1 = {
-        .name   = "leds-gpio", /* GS_IA18-CB_board */
-        .id     = 1,
-        .dev    = {
-                .platform_data  = &pcf_gpio_led_info1,
-        }
-};
-/* PCF8574 0x22 GPIO - U1 on the GS_2G_OPT1-A_V0 board (Alarm) */
-static struct gpio_led pcf_gpio_leds2[] = {
-        { /* bit 0 */
-                .name                   = "gpo:alarm_1",
-                .gpio                   = PCF_GPIO_ALARM1,
-                .active_low             = 1,
-                .default_trigger        = "none",
-                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
-        },
-        { /* bit 1 */
-                .name                   = "gpo:alarm_2",
-                .gpio                   = PCF_GPIO_ALARM2,
-                .active_low             = 1,
-                .default_trigger        = "none",
-                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
-        },
-        { /* bit 2 */
-                .name                   = "gpo:alarm_3",
-                .gpio                   = PCF_GPIO_ALARM3,
-                .active_low             = 1,
-                .default_trigger        = "none",
-                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
-        },
-        { /* bit 3 */
-                .name                   = "gpo:alarm_4",
-                .gpio                   = PCF_GPIO_ALARM4,
-                .active_low             = 1,
-                .default_trigger        = "none",
-                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
-        },
-        /* bits 4, 5, 6 not used */
-        { /* bit 7 */
-                .name                   = "gpo:alarm_v_relay_on",
-                .gpio                   = PCF_GPIO_ALARM_V_RELAY_ON,
-                .active_low             = 0,
-                .default_trigger        = "none",
-                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
-        },
-};
-static struct gpio_led_platform_data pcf_gpio_led_info2 = {
-        .leds           = pcf_gpio_leds2,
-        .num_leds       = ARRAY_SIZE(pcf_gpio_leds2),
-};
-static struct platform_device pcf_leds2 = {
-        .name   = "leds-gpio",
-        .id     = 2,
-        .dev    = {
-                .platform_data  = &pcf_gpio_led_info2,
-        }
-};
-/* PCF8574 0x24 GPIO U1 on the GS_2G-OPT23-A_V0 board (Modem) */
-static struct gpio_led pcf_gpio_leds3[] = {
-        { /* bit 0 */
-                .name                   = "gpo:modem_power",
-                .gpio                   = PCF_GPIO_MODEM_POWER,
-                .active_low             = 1,
-                .default_trigger        = "none",
-                .default_state          = LEDS_GPIO_DEFSTATE_OFF,
-        },
-                /* bits 1 and 2 not used */
-        { /* bit 3 */
-                .name                   = "gpo:modem_reset",
-                .gpio                   = PCF_GPIO_MODEM_RESET,
-                .active_low             = 1,
-                .default_trigger        = "none",
-                .default_state          = LEDS_GPIO_DEFSTATE_ON,
-        },
-                /* bits 4, 5 and 6 not used */
-        { /* bit 7 */
-                .name                   = "gpo:trx_reset",
-                .gpio                   = PCF_GPIO_TRX_RESET,
-                .active_low             = 1,
-                .default_trigger        = "none",
-                .default_state          = LEDS_GPIO_DEFSTATE_ON,
-        }
-};
-static struct gpio_led_platform_data pcf_gpio_led_info3 = {
-        .leds           = pcf_gpio_leds3,
-        .num_leds       = ARRAY_SIZE(pcf_gpio_leds3),
-};
-static struct platform_device pcf_leds3 = {
-        .name   = "leds-gpio",
-        .id     = 3,
-        .dev    = {
-                .platform_data  = &pcf_gpio_led_info3,
-        }
-};
-static void __init gsia18s_pcf_leds_init(void)
-{
-        platform_device_register(&pcf_leds1);
-        platform_device_register(&pcf_leds2);
-        platform_device_register(&pcf_leds3);
-}
-/*
- * SPI busses.
- */
-static struct spi_board_info gsia18s_spi_devices[] = {
-        { /* User accessible spi0, cs0 used for communication with MSP RTC */
-                .modalias       = "spidev",
-                .bus_num        = 0,
-                .chip_select    = 0,
-                .max_speed_hz   = 580000,
-                .mode           = SPI_MODE_1,
-        },
-        { /* User accessible spi1, cs0 used for communication with int. DSP */
-                .modalias       = "spidev",
-                .bus_num        = 1,
-                .chip_select    = 0,
-                .max_speed_hz   = 5600000,
-                .mode           = SPI_MODE_0,
-        },
-        { /* User accessible spi1, cs1 used for communication with ext. DSP */
-                .modalias       = "spidev",
-                .bus_num        = 1,
-                .chip_select    = 1,
-                .max_speed_hz   = 5600000,
-                .mode           = SPI_MODE_0,
-        },
-        { /* User accessible spi1, cs2 used for communication with ext. DSP */
-                .modalias       = "spidev",
-                .bus_num        = 1,
-                .chip_select    = 2,
-                .max_speed_hz   = 5600000,
-                .mode           = SPI_MODE_0,
-        },
-        { /* User accessible spi1, cs3 used for communication with ext. DSP */
-                .modalias       = "spidev",
-                .bus_num        = 1,
-                .chip_select    = 3,
-                .max_speed_hz   = 5600000,
-                .mode           = SPI_MODE_0,
-        }
-};
-/*
- * GPI Buttons
- */
-static struct gpio_keys_button buttons[] = {
-        {
-                .gpio           = GPIO_TRIG_NET_IN,
-                .code           = BTN_1,
-                .desc           = "TRIG_NET_IN",
-                .type           = EV_KEY,
-                .active_low     = 0,
-                .wakeup         = 1,
-        },
-        { /* SW80 on the GS_IA18_S-MN board*/
-                .gpio           = GPIO_CARD_UNMOUNT_0,
-                .code           = BTN_2,
-                .desc           = "Card umount 0",
-                .type           = EV_KEY,
-                .active_low     = 1,
-                .wakeup         = 1,
-        },
-        { /* SW79 on the GS_IA18_S-MN board*/
-                .gpio           = GPIO_CARD_UNMOUNT_1,
-                .code           = BTN_3,
-                .desc           = "Card umount 1",
-                .type           = EV_KEY,
-                .active_low     = 1,
-                .wakeup         = 1,
-        },
-        { /* SW280 on the GS_IA18-CB board*/
-                .gpio           = GPIO_KEY_POWER,
-                .code           = KEY_POWER,
-                .desc           = "Power Off Button",
-                .type           = EV_KEY,
-                .active_low     = 0,
-                .wakeup         = 1,
-        }
-};
-static struct gpio_keys_platform_data button_data = {
-        .buttons        = buttons,
-        .nbuttons       = ARRAY_SIZE(buttons),
-};
-static struct platform_device button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &button_data,
-        }
-};
-static void __init gsia18s_add_device_buttons(void)
-{
-        at91_set_gpio_input(GPIO_TRIG_NET_IN, 1);
-        at91_set_deglitch(GPIO_TRIG_NET_IN, 1);
-        at91_set_gpio_input(GPIO_CARD_UNMOUNT_0, 1);
-        at91_set_deglitch(GPIO_CARD_UNMOUNT_0, 1);
-        at91_set_gpio_input(GPIO_CARD_UNMOUNT_1, 1);
-        at91_set_deglitch(GPIO_CARD_UNMOUNT_1, 1);
-        at91_set_gpio_input(GPIO_KEY_POWER, 0);
-        at91_set_deglitch(GPIO_KEY_POWER, 1);
-        platform_device_register(&button_device);
-}
-/*
- * I2C
- */
-static int pcf8574x_0x20_setup(struct i2c_client *client, int gpio,
-                                unsigned int ngpio, void *context)
-{
-        int status;
-        status = gpio_request(gpio + PCF_GPIO_ETH_DETECT, "eth_det");
-        if (status < 0) {
-                pr_err("error: can't request GPIO%d\n",
-                        gpio + PCF_GPIO_ETH_DETECT);
-                return status;
-        }
-        status = gpio_direction_input(gpio + PCF_GPIO_ETH_DETECT);
-        if (status < 0) {
-                pr_err("error: can't setup GPIO%d as input\n",
-                        gpio + PCF_GPIO_ETH_DETECT);
-                return status;
-        }
-        status = gpio_export(gpio + PCF_GPIO_ETH_DETECT, false);
-        if (status < 0) {
-                pr_err("error: can't export GPIO%d\n",
-                        gpio + PCF_GPIO_ETH_DETECT);
-                return status;
-        }
-        status = gpio_sysfs_set_active_low(gpio + PCF_GPIO_ETH_DETECT, 1);
-        if (status < 0) {
-                pr_err("error: gpio_sysfs_set active_low(GPIO%d, 1)\n",
-                        gpio + PCF_GPIO_ETH_DETECT);
-                return status;
-        }
-        return 0;
-}
-static int pcf8574x_0x20_teardown(struct i2c_client *client, int gpio,
-                                        unsigned ngpio, void *context)
-{
-        gpio_free(gpio + PCF_GPIO_ETH_DETECT);
-        return 0;
-}
-static struct pcf857x_platform_data pcf20_pdata = {
-        .gpio_base      = GS_IA18_S_PCF_GPIO_BASE0,
-        .n_latch        = (1 << 4),
-        .setup          = pcf8574x_0x20_setup,
-        .teardown       = pcf8574x_0x20_teardown,
-};
-static struct pcf857x_platform_data pcf22_pdata = {
-        .gpio_base      = GS_IA18_S_PCF_GPIO_BASE1,
-};
-static struct pcf857x_platform_data pcf24_pdata = {
-        .gpio_base      = GS_IA18_S_PCF_GPIO_BASE2,
-};
-static struct i2c_board_info __initdata gsia18s_i2c_devices[] = {
-        { /* U1 on the GS_IA18-CB_V3 board */
-                I2C_BOARD_INFO("pcf8574", 0x20),
-                .platform_data = &pcf20_pdata,
-        },
-        { /* U1 on the GS_2G_OPT1-A_V0 board (Alarm) */
-                I2C_BOARD_INFO("pcf8574", 0x22),
-                .platform_data = &pcf22_pdata,
-        },
-        { /* U1 on the GS_2G-OPT23-A_V0 board (Modem) */
-                I2C_BOARD_INFO("pcf8574", 0x24),
-                .platform_data = &pcf24_pdata,
-        },
-        { /* U161 on the GS_IA18_S-MN board */
-                I2C_BOARD_INFO("24c1024", 0x50),
-        },
-        { /* U162 on the GS_IA18_S-MN board */
-                I2C_BOARD_INFO("24c01", 0x53),
-        },
-};
-/*
- * Compact Flash
- */
-static struct at91_cf_data __initdata gsia18s_cf1_data = {
-        .irq_pin        = AT91_PIN_PA27,
-        .det_pin        = AT91_PIN_PB30,
-        .vcc_pin        = -EINVAL,
-        .rst_pin        = AT91_PIN_PB31,
-        .chipselect     = 5,
-        .flags          = AT91_CF_TRUE_IDE,
-};
-/* Power Off by RTC */
-static void gsia18s_power_off(void)
-{
-        pr_notice("Power supply will be switched off automatically now or after 60 seconds without ArmDAS.\n");
-        at91_set_gpio_output(AT91_PIN_PA25, 1);
-        /* Spin to death... */
-        while (1)
-                ;
-}
-static int __init gsia18s_power_off_init(void)
-{
-        pm_power_off = gsia18s_power_off;
-        return 0;
-}
-/* ---------------------------------------------------------------------------*/
-static void __init gsia18s_board_init(void)
-{
-        /*
-         * USART0 on ttyS1 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI).
-         * Used for Internal Analog Modem.
-         */
-        at91_register_uart(AT91SAM9260_ID_US0, 1,
-                                ATMEL_UART_CTS | ATMEL_UART_RTS |
-                                ATMEL_UART_DTR | ATMEL_UART_DSR |
-                                ATMEL_UART_DCD | ATMEL_UART_RI);
-        /*
-         * USART1 on ttyS2 (Rx, Tx, CTS, RTS).
-         * Used for GPS or WiFi or Data stream.
-         */
-        at91_register_uart(AT91SAM9260_ID_US1, 2,
-                                ATMEL_UART_CTS | ATMEL_UART_RTS);
-        /*
-         * USART2 on ttyS3 (Rx, Tx, CTS, RTS).
-         * Used for External Modem.
-         */
-        at91_register_uart(AT91SAM9260_ID_US2, 3,
-                                ATMEL_UART_CTS | ATMEL_UART_RTS);
-        /*
-         * USART3 on ttyS4 (Rx, Tx, RTS).
-         * Used for RS-485.
-         */
-        at91_register_uart(AT91SAM9260_ID_US3, 4, ATMEL_UART_RTS);
-        /*
-         * USART4 on ttyS5 (Rx, Tx).
-         * Used for TRX433 Radio Module.
-         */
-        at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
-        stamp9g20_board_init();
-        at91_add_device_usbh(&usbh_data);
-        at91_add_device_udc(&udc_data);
-        at91_add_device_eth(&macb_data);
-        gsia18s_leds_init();
-        gsia18s_pcf_leds_init();
-        gsia18s_add_device_buttons();
-        at91_add_device_i2c(gsia18s_i2c_devices,
-                                ARRAY_SIZE(gsia18s_i2c_devices));
-        at91_add_device_cf(&gsia18s_cf1_data);
-        at91_add_device_spi(gsia18s_spi_devices,
-                                ARRAY_SIZE(gsia18s_spi_devices));
-        gsia18s_power_off_init();
-}
-MACHINE_START(GSIA18S, "GS_IA18_S")
-        .init_time      = at91_init_time,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = gsia18s_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = gsia18s_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
deleted file mode 100644
index 93b1df42f639..000000000000
--- a/arch/arm/mach-at91/board-kafa.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-kafa.c
- *
- *  Copyright (C) 2006 Sperry-Sun
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/cpu.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "generic.h"
-#include "gpio.h"
-static void __init kafa_init_early(void)
-{
-        /* Set cpu type: PQFP */
-        at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
-        /* Initialize processor: 18.432 MHz crystal */
-        at91_initialize(18432000);
-}
-static struct macb_platform_data __initdata kafa_eth_data = {
-        .phy_irq_pin    = AT91_PIN_PC4,
-        .is_rmii        = 0,
-};
-static struct at91_usbh_data __initdata kafa_usbh_data = {
-        .ports          = 1,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-static struct at91_udc_data __initdata kafa_udc_data = {
-        .vbus_pin       = AT91_PIN_PB6,
-        .pullup_pin     = AT91_PIN_PB7,
-};
-/*
- * LEDs
- */
-static struct gpio_led kafa_leds[] = {
-        {       /* D1 */
-                .name                   = "led1",
-                .gpio                   = AT91_PIN_PB4,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",
-        },
-};
-static void __init kafa_board_init(void)
-{
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */
-        at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        at91_add_device_serial();
-        /* Ethernet */
-        at91_add_device_eth(&kafa_eth_data);
-        /* USB Host */
-        at91_add_device_usbh(&kafa_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&kafa_udc_data);
-        /* I2C */
-        at91_add_device_i2c(NULL, 0);
-        /* SPI */
-        at91_add_device_spi(NULL, 0);
-        /* LEDs */
-        at91_gpio_leds(kafa_leds, ARRAY_SIZE(kafa_leds));
-}
-MACHINE_START(KAFA, "Sperry-Sun KAFA")
-        /* Maintainer: Sergei Sharonov */
-        .init_time      = at91rm9200_timer_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = kafa_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = kafa_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
deleted file mode 100644
index d58d36225e08..000000000000
--- a/arch/arm/mach-at91/board-kb9202.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-kb9202.c
- *
- *  Copyright (c) 2005 kb_admin
- *                     KwikByte, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/cpu.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "generic.h"
-#include "gpio.h"
-static void __init kb9202_init_early(void)
-{
-        /* Set cpu type: PQFP */
-        at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
-        /* Initialize processor: 10 MHz crystal */
-        at91_initialize(10000000);
-}
-static struct macb_platform_data __initdata kb9202_eth_data = {
-        .phy_irq_pin    = AT91_PIN_PB29,
-        .is_rmii        = 0,
-};
-static struct at91_usbh_data __initdata kb9202_usbh_data = {
-        .ports          = 1,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-static struct at91_udc_data __initdata kb9202_udc_data = {
-        .vbus_pin       = AT91_PIN_PB24,
-        .pullup_pin     = AT91_PIN_PB22,
-};
-static struct mci_platform_data __initdata kb9202_mci0_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PB2,
-                .wp_pin         = -EINVAL,
-        },
-};
-static struct mtd_partition __initdata kb9202_nand_partition[] = {
-        {
-                .name   = "nand_fs",
-                .offset = 0,
-                .size   = MTDPART_SIZ_FULL,
-        },
-};
-static struct atmel_nand_data __initdata kb9202_nand_data = {
-        .ale            = 22,
-        .cle            = 21,
-        .det_pin        = -EINVAL,
-        .rdy_pin        = AT91_PIN_PC29,
-        .enable_pin     = AT91_PIN_PC28,
-        .ecc_mode       = NAND_ECC_SOFT,
-        .parts          = kb9202_nand_partition,
-        .num_parts      = ARRAY_SIZE(kb9202_nand_partition),
-};
-/*
- * LEDs
- */
-static struct gpio_led kb9202_leds[] = {
-        {       /* D1 */
-                .name                   = "led1",
-                .gpio                   = AT91_PIN_PC19,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",
-        },
-        {       /* D2 */
-                .name                   = "led2",
-                .gpio                   = AT91_PIN_PC18,
-                .active_low             = 1,
-                .default_trigger        = "timer",
-        }
-};
-static void __init kb9202_board_init(void)
-{
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1 (Rx & Tx only) */
-        at91_register_uart(AT91RM9200_ID_US0, 1, 0);
-        /* USART1 on ttyS2 (Rx & Tx only) - IRDA (optional) */
-        at91_register_uart(AT91RM9200_ID_US1, 2, 0);
-        /* USART3 on ttyS3 (Rx, Tx, CTS, RTS) - RS485 (optional) */
-        at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        at91_add_device_serial();
-        /* Ethernet */
-        at91_add_device_eth(&kb9202_eth_data);
-        /* USB Host */
-        at91_add_device_usbh(&kb9202_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&kb9202_udc_data);
-        /* MMC */
-        at91_add_device_mci(0, &kb9202_mci0_data);
-        /* I2C */
-        at91_add_device_i2c(NULL, 0);
-        /* SPI */
-        at91_add_device_spi(NULL, 0);
-        /* NAND */
-        at91_add_device_nand(&kb9202_nand_data);
-        /* LEDs */
-        at91_gpio_leds(kb9202_leds, ARRAY_SIZE(kb9202_leds));
-}
-MACHINE_START(KB9200, "KB920x")
-        /* Maintainer: KwikByte, Inc. */
-        .init_time      = at91rm9200_timer_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = kb9202_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = kb9202_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
deleted file mode 100644
index 9c26b94ce448..000000000000
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- *  Copyright (C) 2010 Christian Glindkamp <christian.glindkamp@taskit.de>
- *                     taskit GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/*
- * copied and adjusted from board-stamp9g20.c
- * by Peter Gsellmann <pgsellmann@portner-elektronik.at>
- */
-#include <linux/mm.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/w1-gpio.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/hardware.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "sam9_smc.h"
-#include "generic.h"
-#include "stamp9g20.h"
-#include "gpio.h"
-static void __init pcontrol_g20_init_early(void)
-{
-        stamp9g20_init_early();
-}
-static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { {
-        .ncs_read_setup         = 16,
-        .nrd_setup              = 18,
-        .ncs_write_setup        = 16,
-        .nwe_setup              = 18,
-        .ncs_read_pulse         = 63,
-        .nrd_pulse              = 55,
-        .ncs_write_pulse        = 63,
-        .nwe_pulse              = 55,
-        .read_cycle             = 127,
-        .write_cycle            = 127,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
-                        | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_SELECT
-                        | AT91_SMC_DBW_8 | AT91_SMC_PS_4
-                        | AT91_SMC_TDFMODE,
-        .tdf_cycles             = 3,
-}, {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 0,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 1,
-        .ncs_read_pulse         = 8,
-        .nrd_pulse              = 8,
-        .ncs_write_pulse        = 5,
-        .nwe_pulse              = 4,
-        .read_cycle             = 8,
-        .write_cycle            = 7,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
-                        | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_SELECT
-                        | AT91_SMC_DBW_16 | AT91_SMC_PS_8
-                        | AT91_SMC_TDFMODE,
-        .tdf_cycles             = 1,
-} };
-static void __init add_device_pcontrol(void)
-{
-        /* configure chip-select 4 (IO compatible to 8051  X4 ) */
-        sam9_smc_configure(0, 4, &pcontrol_smc_config[0]);
-        /* configure chip-select 7 (FerroRAM 256KiBx16bit MR2A16A  D4 ) */
-        sam9_smc_configure(0, 7, &pcontrol_smc_config[1]);
-}
-/*
- * USB Host port
- */
-static struct at91_usbh_data __initdata usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-/*
- * USB Device port
- */
-static struct at91_udc_data __initdata pcontrol_g20_udc_data = {
-        .vbus_pin       = AT91_PIN_PA22,        /* Detect +5V bus voltage */
-        .pullup_pin     = AT91_PIN_PA4,         /* K-state, active low */
-};
-/*
- * MACB Ethernet device
- */
-static struct macb_platform_data __initdata macb_data = {
-        .phy_irq_pin    = AT91_PIN_PA28,
-        .is_rmii        = 1,
-};
-/*
- * I2C devices: eeprom and phy/switch
- */
-static struct i2c_board_info __initdata pcontrol_g20_i2c_devices[] = {
-{               /* D7  address width=2, 8KiB */
-        I2C_BOARD_INFO("24c64", 0x50)
-}, {            /* D8  address width=1, 1 byte has 32 bits! */
-        I2C_BOARD_INFO("lan9303", 0x0a)
-}, };
-/*
- * LEDs
- */
-static struct gpio_led pcontrol_g20_leds[] = {
-        {
-                .name                   = "LED1",       /* red  H5 */
-                .gpio                   = AT91_PIN_PB18,
-                .active_low             = 1,
-                .default_trigger        = "none",       /* supervisor */
-        }, {
-                .name                   = "LED2",       /* yellow  H7 */
-                .gpio                   = AT91_PIN_PB19,
-                .active_low             = 1,
-                .default_trigger        = "mmc0",       /* SD-card activity */
-        }, {
-                .name                   = "LED3",       /* green  H2 */
-                .gpio                   = AT91_PIN_PB20,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",  /* blinky */
-        }, {
-                .name                   = "LED4",       /* red  H3 */
-                .gpio                   = AT91_PIN_PC6,
-                .active_low             = 1,
-                .default_trigger        = "none",       /* connection lost */
-        }, {
-                .name                   = "LED5",       /* yellow  H6 */
-                .gpio                   = AT91_PIN_PC7,
-                .active_low             = 1,
-                .default_trigger        = "none",       /* unsent data */
-        }, {
-                .name                   = "LED6",       /* green  H1 */
-                .gpio                   = AT91_PIN_PC9,
-                .active_low             = 1,
-                .default_trigger        = "none",       /* snafu */
-        }
-};
-/*
- * SPI devices
- */
-static struct spi_board_info pcontrol_g20_spi_devices[] = {
-        {
-                .modalias       = "spidev",     /* HMI port  X4 */
-                .chip_select    = 1,
-                .max_speed_hz   = 50 * 1000 * 1000,
-                .bus_num        = 0,
-        }, {
-                .modalias       = "spidev",     /* piggyback  A2 */
-                .chip_select    = 0,
-                .max_speed_hz   = 50 * 1000 * 1000,
-                .bus_num        = 1,
-        },
-};
-static void __init pcontrol_g20_board_init(void)
-{
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback  A2 */
-        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS
-                                                | ATMEL_UART_RTS);
-        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) isolated RS485  X5 */
-        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS
-                                                | ATMEL_UART_RTS);
-        /* USART2 on ttyS3. (Rx, Tx)  9bit-Bus  Multidrop-mode  X4 */
-        at91_register_uart(AT91SAM9260_ID_US4, 3, 0);
-        stamp9g20_board_init();
-        at91_add_device_usbh(&usbh_data);
-        at91_add_device_eth(&macb_data);
-        at91_add_device_i2c(pcontrol_g20_i2c_devices,
-                ARRAY_SIZE(pcontrol_g20_i2c_devices));
-        add_device_pcontrol();
-        at91_add_device_spi(pcontrol_g20_spi_devices,
-                ARRAY_SIZE(pcontrol_g20_spi_devices));
-        at91_add_device_udc(&pcontrol_g20_udc_data);
-        at91_gpio_leds(pcontrol_g20_leds,
-                ARRAY_SIZE(pcontrol_g20_leds));
-        /* piggyback  A2 */
-        at91_set_gpio_output(AT91_PIN_PB31, 1);
-}
-MACHINE_START(PCONTROL_G20, "PControl G20")
-        /* Maintainer: pgsellmann@portner-elektronik.at */
-        .init_time      = at91_init_time,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = pcontrol_g20_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = pcontrol_g20_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
deleted file mode 100644
index 2c0f2d554d84..000000000000
--- a/arch/arm/mach-at91/board-picotux200.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-picotux200.c
- *
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2007 Kleinhenz Elektronik GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/mtd/physmap.h>
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "generic.h"
-#include "gpio.h"
-static void __init picotux200_init_early(void)
-{
-        /* Initialize processor: 18.432 MHz crystal */
-        at91_initialize(18432000);
-}
-static struct macb_platform_data __initdata picotux200_eth_data = {
-        .phy_irq_pin    = AT91_PIN_PC4,
-        .is_rmii        = 1,
-};
-static struct at91_usbh_data __initdata picotux200_usbh_data = {
-        .ports          = 1,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-static struct mci_platform_data __initdata picotux200_mci0_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PB27,
-                .wp_pin         = AT91_PIN_PA17,
-        },
-};
-#define PICOTUX200_FLASH_BASE   AT91_CHIPSELECT_0
-#define PICOTUX200_FLASH_SIZE   SZ_4M
-static struct physmap_flash_data picotux200_flash_data = {
-        .width  = 2,
-};
-static struct resource picotux200_flash_resource = {
-        .start          = PICOTUX200_FLASH_BASE,
-        .end            = PICOTUX200_FLASH_BASE + PICOTUX200_FLASH_SIZE - 1,
-        .flags          = IORESOURCE_MEM,
-};
-static struct platform_device picotux200_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                                .platform_data  = &picotux200_flash_data,
-                        },
-        .resource       = &picotux200_flash_resource,
-        .num_resources  = 1,
-};
-static void __init picotux200_board_init(void)
-{
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                          | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                          | ATMEL_UART_RI);
-        at91_add_device_serial();
-        /* Ethernet */
-        at91_add_device_eth(&picotux200_eth_data);
-        /* USB Host */
-        at91_add_device_usbh(&picotux200_usbh_data);
-        /* I2C */
-        at91_add_device_i2c(NULL, 0);
-        /* MMC */
-        at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
-        at91_add_device_mci(0, &picotux200_mci0_data);
-        /* NOR Flash */
-        platform_device_register(&picotux200_flash);
-}
-MACHINE_START(PICOTUX2XX, "picotux 200")
-        /* Maintainer: Kleinhenz Elektronik GmbH */
-        .init_time      = at91rm9200_timer_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = picotux200_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = picotux200_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
deleted file mode 100644
index 953cea416754..000000000000
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-rm9200ek.c
- *
- *  Copyright (C) 2005 SAN People
- *
- *  Epson S1D framebuffer glue code is:
- *     Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/mtd/physmap.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "generic.h"
-#include "gpio.h"
-static void __init ek_init_early(void)
-{
-        /* Initialize processor: 18.432 MHz crystal */
-        at91_initialize(18432000);
-}
-static struct macb_platform_data __initdata ek_eth_data = {
-        .phy_irq_pin    = AT91_PIN_PC4,
-        .is_rmii        = 1,
-};
-static struct at91_usbh_data __initdata ek_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-static struct at91_udc_data __initdata ek_udc_data = {
-        .vbus_pin       = AT91_PIN_PD4,
-        .pullup_pin     = AT91_PIN_PD5,
-};
-#ifndef CONFIG_MTD_AT91_DATAFLASH_CARD
-static struct mci_platform_data __initdata ek_mci0_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PB27,
-                .wp_pin         = AT91_PIN_PA17,
-        }
-};
-#endif
-static struct spi_board_info ek_spi_devices[] = {
-        {       /* DataFlash chip */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 15 * 1000 * 1000,
-        },
-#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
-        {       /* DataFlash card */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 3,
-                .max_speed_hz   = 15 * 1000 * 1000,
-        },
-#endif
-};
-static struct i2c_board_info __initdata ek_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("ics1523", 0x26),
-        },
-        {
-                I2C_BOARD_INFO("dac3550", 0x4d),
-        }
-};
-#define EK_FLASH_BASE   AT91_CHIPSELECT_0
-#define EK_FLASH_SIZE   SZ_8M
-static struct physmap_flash_data ek_flash_data = {
-        .width          = 2,
-};
-static struct resource ek_flash_resource = {
-        .start          = EK_FLASH_BASE,
-        .end            = EK_FLASH_BASE + EK_FLASH_SIZE - 1,
-        .flags          = IORESOURCE_MEM,
-};
-static struct platform_device ek_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                                .platform_data  = &ek_flash_data,
-                        },
-        .resource       = &ek_flash_resource,
-        .num_resources  = 1,
-};
-static struct gpio_led ek_leds[] = {
-        {       /* "user led 1", DS2 */
-                .name                   = "green",
-                .gpio                   = AT91_PIN_PB0,
-                .active_low             = 1,
-                .default_trigger        = "mmc0",
-        },
-        {       /* "user led 2", DS4 */
-                .name                   = "yellow",
-                .gpio                   = AT91_PIN_PB1,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",
-        },
-        {       /* "user led 3", DS6 */
-                .name                   = "red",
-                .gpio                   = AT91_PIN_PB2,
-                .active_low             = 1,
-        }
-};
-static void __init ek_board_init(void)
-{
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                           | ATMEL_UART_RI);
-        at91_add_device_serial();
-        /* Ethernet */
-        at91_add_device_eth(&ek_eth_data);
-        /* USB Host */
-        at91_add_device_usbh(&ek_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&ek_udc_data);
-        at91_set_multi_drive(ek_udc_data.pullup_pin, 1);        /* pullup_pin is connected to reset */
-        /* I2C */
-        at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
-        /* SPI */
-        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
-#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
-        /* DataFlash card */
-        at91_set_gpio_output(AT91_PIN_PB22, 0);
-#else
-        /* MMC */
-        at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
-        at91_add_device_mci(0, &ek_mci0_data);
-#endif
-        /* NOR Flash */
-        platform_device_register(&ek_flash);
-        /* LEDs */
-        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
-        /* VGA */
-//      ek_add_device_video();
-}
-MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK")
-        /* Maintainer: SAN People/Atmel */
-        .init_time      = at91rm9200_timer_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = ek_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = ek_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
deleted file mode 100644
index c2166e3a236c..000000000000
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-sam9-l9260.c
- *
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2006 Atmel
- *  Copyright (C) 2007 Olimex Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/at91sam9_smc.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "sam9_smc.h"
-#include "generic.h"
-#include "gpio.h"
-static void __init ek_init_early(void)
-{
-        /* Initialize processor: 18.432 MHz crystal */
-        at91_initialize(18432000);
-}
-/*
- * USB Host port
- */
-static struct at91_usbh_data __initdata ek_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-/*
- * USB Device port
- */
-static struct at91_udc_data __initdata ek_udc_data = {
-        .vbus_pin       = AT91_PIN_PC5,
-        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
-};
-/*
- * SPI devices.
- */
-static struct spi_board_info ek_spi_devices[] = {
-#if !IS_ENABLED(CONFIG_MMC_ATMELMCI)
-        {       /* DataFlash chip */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 1,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
-        {       /* DataFlash card */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-#endif
-#endif
-};
-/*
- * MACB Ethernet device
- */
-static struct macb_platform_data __initdata ek_macb_data = {
-        .phy_irq_pin    = AT91_PIN_PA7,
-        .is_rmii        = 0,
-};
-/*
- * NAND flash
- */
-static struct mtd_partition __initdata ek_nand_partition[] = {
-        {
-                .name   = "Bootloader Area",
-                .offset = 0,
-                .size   = 10 * SZ_1M,
-        },
-        {
-                .name   = "User Area",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = MTDPART_SIZ_FULL,
-        },
-};
-static struct atmel_nand_data __initdata ek_nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .det_pin        = -EINVAL,
-        .rdy_pin        = AT91_PIN_PC13,
-        .enable_pin     = AT91_PIN_PC14,
-        .ecc_mode       = NAND_ECC_SOFT,
-        .parts          = ek_nand_partition,
-        .num_parts      = ARRAY_SIZE(ek_nand_partition),
-};
-static struct sam9_smc_config __initdata ek_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 1,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 1,
-        .ncs_read_pulse         = 3,
-        .nrd_pulse              = 3,
-        .ncs_write_pulse        = 3,
-        .nwe_pulse              = 3,
-        .read_cycle             = 5,
-        .write_cycle            = 5,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
-        .tdf_cycles             = 2,
-};
-static void __init ek_add_device_nand(void)
-{
-        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(0, 3, &ek_nand_smc_config);
-        at91_add_device_nand(&ek_nand_data);
-}
-/*
- * MCI (SD/MMC)
- */
-static struct mci_platform_data __initdata ek_mci0_data = {
-        .slot[1] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PC8,
-                .wp_pin         = AT91_PIN_PC4,
-        },
-};
-/*
- * LEDs
- */
-static struct gpio_led ek_leds[] = {
-        {       /* D1 */
-                .name                   = "led1",
-                .gpio                   = AT91_PIN_PA9,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",
-        },
-        {       /* D2 */
-                .name                   = "led2",
-                .gpio                   = AT91_PIN_PA6,
-                .active_low             = 1,
-                .default_trigger        = "timer",
-        }
-};
-static void __init ek_board_init(void)
-{
-        at91_register_devices();
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                           | ATMEL_UART_RI);
-        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
-        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        at91_add_device_serial();
-        /* USB Host */
-        at91_add_device_usbh(&ek_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&ek_udc_data);
-        /* SPI */
-        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
-        /* NAND */
-        ek_add_device_nand();
-        /* Ethernet */
-        at91_add_device_eth(&ek_macb_data);
-        /* MMC */
-        at91_add_device_mci(0, &ek_mci0_data);
-        /* I2C */
-        at91_add_device_i2c(NULL, 0);
-        /* LEDs */
-        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
-}
-MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
-        /* Maintainer: Olimex */
-        .init_time      = at91_init_time,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = ek_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = ek_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
deleted file mode 100644
index bf8a946b4cd0..000000000000
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ /dev/null
@@ -1,354 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-sam9260ek.c
- *
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2006 Atmel
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/at73c213.h>
-#include <linux/clk.h>
-#include <linux/platform_data/at24.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/system_rev.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "sam9_smc.h"
-#include "generic.h"
-#include "gpio.h"
-static void __init ek_init_early(void)
-{
-        /* Initialize processor: 18.432 MHz crystal */
-        at91_initialize(18432000);
-}
-/*
- * USB Host port
- */
-static struct at91_usbh_data __initdata ek_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-/*
- * USB Device port
- */
-static struct at91_udc_data __initdata ek_udc_data = {
-        .vbus_pin       = AT91_PIN_PC5,
-        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
-};
-/*
- * Audio
- */
-static struct at73c213_board_info at73c213_data = {
-        .ssc_id         = 0,
-        .shortname      = "AT91SAM9260-EK external DAC",
-};
-#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
-static void __init at73c213_set_clk(struct at73c213_board_info *info)
-{
-        struct clk *pck0;
-        struct clk *plla;
-        pck0 = clk_get(NULL, "pck0");
-        plla = clk_get(NULL, "plla");
-        /* AT73C213 MCK Clock */
-        at91_set_B_periph(AT91_PIN_PC1, 0);     /* PCK0 */
-        clk_set_parent(pck0, plla);
-        clk_put(plla);
-        info->dac_clk = pck0;
-}
-#else
-static void __init at73c213_set_clk(struct at73c213_board_info *info) {}
-#endif
-/*
- * SPI devices.
- */
-static struct spi_board_info ek_spi_devices[] = {
-#if !IS_ENABLED(CONFIG_MMC_ATMELMCI)
-        {       /* DataFlash chip */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 1,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
-        {       /* DataFlash card */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-#endif
-#endif
-#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
-        {       /* AT73C213 DAC */
-                .modalias       = "at73c213",
-                .chip_select    = 0,
-                .max_speed_hz   = 10 * 1000 * 1000,
-                .bus_num        = 1,
-                .mode           = SPI_MODE_1,
-                .platform_data  = &at73c213_data,
-        },
-#endif
-};
-/*
- * MACB Ethernet device
- */
-static struct macb_platform_data __initdata ek_macb_data = {
-        .phy_irq_pin    = AT91_PIN_PA7,
-        .is_rmii        = 1,
-};
-/*
- * NAND flash
- */
-static struct mtd_partition __initdata ek_nand_partition[] = {
-        {
-                .name   = "Partition 1",
-                .offset = 0,
-                .size   = SZ_256K,
-        },
-        {
-                .name   = "Partition 2",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = MTDPART_SIZ_FULL,
-        },
-};
-static struct atmel_nand_data __initdata ek_nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .det_pin        = -EINVAL,
-        .rdy_pin        = AT91_PIN_PC13,
-        .enable_pin     = AT91_PIN_PC14,
-        .ecc_mode       = NAND_ECC_SOFT,
-        .on_flash_bbt   = 1,
-        .parts          = ek_nand_partition,
-        .num_parts      = ARRAY_SIZE(ek_nand_partition),
-};
-static struct sam9_smc_config __initdata ek_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 1,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 1,
-        .ncs_read_pulse         = 3,
-        .nrd_pulse              = 3,
-        .ncs_write_pulse        = 3,
-        .nwe_pulse              = 3,
-        .read_cycle             = 5,
-        .write_cycle            = 5,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
-        .tdf_cycles             = 2,
-};
-static void __init ek_add_device_nand(void)
-{
-        ek_nand_data.bus_width_16 = board_have_nand_16bit();
-        /* setup bus-width (8 or 16) */
-        if (ek_nand_data.bus_width_16)
-                ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
-        else
-                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
-        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(0, 3, &ek_nand_smc_config);
-        at91_add_device_nand(&ek_nand_data);
-}
-/*
- * MCI (SD/MMC)
- */
-static struct mci_platform_data __initdata ek_mci0_data = {
-        .slot[1] = {
-                .bus_width      = 4,
-                .detect_pin     = -EINVAL,
-                .wp_pin         = -EINVAL,
-        },
-};
-/*
- * LEDs
- */
-static struct gpio_led ek_leds[] = {
-        {       /* "bottom" led, green, userled1 to be defined */
-                .name                   = "ds5",
-                .gpio                   = AT91_PIN_PA6,
-                .active_low             = 1,
-                .default_trigger        = "none",
-        },
-        {       /* "power" led, yellow */
-                .name                   = "ds1",
-                .gpio                   = AT91_PIN_PA9,
-                .default_trigger        = "heartbeat",
-        }
-};
-/*
- * I2C devices
- */
-static struct at24_platform_data at24c512 = {
-        .byte_len       = SZ_512K / 8,
-        .page_size      = 128,
-        .flags          = AT24_FLAG_ADDR16,
-};
-static struct i2c_board_info __initdata ek_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("24c512", 0x50),
-                .platform_data = &at24c512,
-        },
-        /* more devices can be added using expansion connectors */
-};
-/*
- * GPIO Buttons
- */
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button ek_buttons[] = {
-        {
-                .gpio           = AT91_PIN_PA30,
-                .code           = BTN_3,
-                .desc           = "Button 3",
-                .active_low     = 1,
-                .wakeup         = 1,
-        },
-        {
-                .gpio           = AT91_PIN_PA31,
-                .code           = BTN_4,
-                .desc           = "Button 4",
-                .active_low     = 1,
-                .wakeup         = 1,
-        }
-};
-static struct gpio_keys_platform_data ek_button_data = {
-        .buttons        = ek_buttons,
-        .nbuttons       = ARRAY_SIZE(ek_buttons),
-};
-static struct platform_device ek_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &ek_button_data,
-        }
-};
-static void __init ek_add_device_buttons(void)
-{
-        at91_set_gpio_input(AT91_PIN_PA30, 1);  /* btn3 */
-        at91_set_deglitch(AT91_PIN_PA30, 1);
-        at91_set_gpio_input(AT91_PIN_PA31, 1);  /* btn4 */
-        at91_set_deglitch(AT91_PIN_PA31, 1);
-        platform_device_register(&ek_button_device);
-}
-#else
-static void __init ek_add_device_buttons(void) {}
-#endif
-static void __init ek_board_init(void)
-{
-        at91_register_devices();
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                           | ATMEL_UART_RI);
-        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        at91_add_device_serial();
-        /* USB Host */
-        at91_add_device_usbh(&ek_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&ek_udc_data);
-        /* SPI */
-        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
-        /* NAND */
-        ek_add_device_nand();
-        /* Ethernet */
-        at91_add_device_eth(&ek_macb_data);
-        /* MMC */
-        at91_add_device_mci(0, &ek_mci0_data);
-        /* I2C */
-        at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
-        /* SSC (to AT73C213) */
-        at73c213_set_clk(&at73c213_data);
-        at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
-        /* LEDs */
-        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
-        /* Push Buttons */
-        ek_add_device_buttons();
-}
-MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
-        /* Maintainer: Atmel */
-        .init_time      = at91_init_time,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = ek_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = ek_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
deleted file mode 100644
index e85ada820bfb..000000000000
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ /dev/null
@@ -1,623 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-sam9261ek.c
- *
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2006 Atmel
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
-#include <linux/spi/at73c213.h>
-#include <linux/clk.h>
-#include <linux/dm9000.h>
-#include <linux/fb.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <video/atmel_lcdc.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/system_rev.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "sam9_smc.h"
-#include "generic.h"
-#include "gpio.h"
-static void __init ek_init_early(void)
-{
-        /* Initialize processor: 18.432 MHz crystal */
-        at91_initialize(18432000);
-}
-/*
- * DM9000 ethernet device
- */
-#if defined(CONFIG_DM9000)
-static struct resource dm9000_resource[] = {
-        [0] = {
-                .start  = AT91_CHIPSELECT_2,
-                .end    = AT91_CHIPSELECT_2 + 3,
-                .flags  = IORESOURCE_MEM
-        },
-        [1] = {
-                .start  = AT91_CHIPSELECT_2 + 0x44,
-                .end    = AT91_CHIPSELECT_2 + 0xFF,
-                .flags  = IORESOURCE_MEM
-        },
-        [2] = {
-                .flags  = IORESOURCE_IRQ
-                        | IORESOURCE_IRQ_LOWEDGE | IORESOURCE_IRQ_HIGHEDGE,
-        }
-};
-static struct dm9000_plat_data dm9000_platdata = {
-        .flags          = DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM,
-};
-static struct platform_device dm9000_device = {
-        .name           = "dm9000",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(dm9000_resource),
-        .resource       = dm9000_resource,
-        .dev            = {
-                .platform_data  = &dm9000_platdata,
-        }
-};
-/*
- * SMC timings for the DM9000.
- * Note: These timings were calculated for MASTER_CLOCK = 100000000 according to the DM9000 timings.
- */
-static struct sam9_smc_config __initdata dm9000_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 2,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 2,
-        .ncs_read_pulse         = 8,
-        .nrd_pulse              = 4,
-        .ncs_write_pulse        = 8,
-        .nwe_pulse              = 4,
-        .read_cycle             = 16,
-        .write_cycle            = 16,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16,
-        .tdf_cycles             = 1,
-};
-static void __init ek_add_device_dm9000(void)
-{
-        struct resource *r = &dm9000_resource[2];
-        /* Configure chip-select 2 (DM9000) */
-        sam9_smc_configure(0, 2, &dm9000_smc_config);
-        /* Configure Reset signal as output */
-        at91_set_gpio_output(AT91_PIN_PC10, 0);
-        /* Configure Interrupt pin as input, no pull-up */
-        at91_set_gpio_input(AT91_PIN_PC11, 0);
-        r->start = r->end = gpio_to_irq(AT91_PIN_PC11);
-        platform_device_register(&dm9000_device);
-}
-#else
-static void __init ek_add_device_dm9000(void) {}
-#endif /* CONFIG_DM9000 */
-/*
- * USB Host Port
- */
-static struct at91_usbh_data __initdata ek_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-/*
- * USB Device Port
- */
-static struct at91_udc_data __initdata ek_udc_data = {
-        .vbus_pin       = AT91_PIN_PB29,
-        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
-};
-/*
- * NAND flash
- */
-static struct mtd_partition __initdata ek_nand_partition[] = {
-        {
-                .name   = "Partition 1",
-                .offset = 0,
-                .size   = SZ_256K,
-        },
-        {
-                .name   = "Partition 2",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = MTDPART_SIZ_FULL,
-        },
-};
-static struct atmel_nand_data __initdata ek_nand_data = {
-        .ale            = 22,
-        .cle            = 21,
-        .det_pin        = -EINVAL,
-        .rdy_pin        = AT91_PIN_PC15,
-        .enable_pin     = AT91_PIN_PC14,
-        .ecc_mode       = NAND_ECC_SOFT,
-        .on_flash_bbt   = 1,
-        .parts          = ek_nand_partition,
-        .num_parts      = ARRAY_SIZE(ek_nand_partition),
-};
-static struct sam9_smc_config __initdata ek_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 1,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 1,
-        .ncs_read_pulse         = 3,
-        .nrd_pulse              = 3,
-        .ncs_write_pulse        = 3,
-        .nwe_pulse              = 3,
-        .read_cycle             = 5,
-        .write_cycle            = 5,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
-        .tdf_cycles             = 2,
-};
-static void __init ek_add_device_nand(void)
-{
-        ek_nand_data.bus_width_16 = board_have_nand_16bit();
-        /* setup bus-width (8 or 16) */
-        if (ek_nand_data.bus_width_16)
-                ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
-        else
-                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
-        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(0, 3, &ek_nand_smc_config);
-        at91_add_device_nand(&ek_nand_data);
-}
-/*
- * SPI related devices
- */
-#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
-/*
- * ADS7846 Touchscreen
- */
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-static int ads7843_pendown_state(void)
-{
-        return !at91_get_gpio_value(AT91_PIN_PC2);      /* Touchscreen PENIRQ */
-}
-static struct ads7846_platform_data ads_info = {
-        .model                  = 7843,
-        .x_min                  = 150,
-        .x_max                  = 3830,
-        .y_min                  = 190,
-        .y_max                  = 3830,
-        .vref_delay_usecs       = 100,
-        .x_plate_ohms           = 450,
-        .y_plate_ohms           = 250,
-        .pressure_max           = 15000,
-        .debounce_max           = 1,
-        .debounce_rep           = 0,
-        .debounce_tol           = (~0),
-        .get_pendown_state      = ads7843_pendown_state,
-};
-static void __init ek_add_device_ts(void)
-{
-        at91_set_B_periph(AT91_PIN_PC2, 1);     /* External IRQ0, with pullup */
-        at91_set_gpio_input(AT91_PIN_PA11, 1);  /* Touchscreen BUSY signal */
-}
-#else
-static void __init ek_add_device_ts(void) {}
-#endif
-/*
- * Audio
- */
-static struct at73c213_board_info at73c213_data = {
-        .ssc_id         = 1,
-        .shortname      = "AT91SAM9261/9G10-EK external DAC",
-};
-#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
-static void __init at73c213_set_clk(struct at73c213_board_info *info)
-{
-        struct clk *pck2;
-        struct clk *plla;
-        pck2 = clk_get(NULL, "pck2");
-        plla = clk_get(NULL, "plla");
-        /* AT73C213 MCK Clock */
-        at91_set_B_periph(AT91_PIN_PB31, 0);    /* PCK2 */
-        clk_set_parent(pck2, plla);
-        clk_put(plla);
-        info->dac_clk = pck2;
-}
-#else
-static void __init at73c213_set_clk(struct at73c213_board_info *info) {}
-#endif
-/*
- * SPI devices
- */
-static struct spi_board_info ek_spi_devices[] = {
-        {       /* DataFlash chip */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-        {
-                .modalias       = "ads7846",
-                .chip_select    = 2,
-                .max_speed_hz   = 125000 * 26,  /* (max sample rate @ 3V) * (cmd + data + overhead) */
-                .bus_num        = 0,
-                .platform_data  = &ads_info,
-                .irq            = NR_IRQS_LEGACY + AT91SAM9261_ID_IRQ0,
-                .controller_data = (void *) AT91_PIN_PA28,      /* CS pin */
-        },
-#endif
-#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
-        {       /* DataFlash card - jumper (J12) configurable to CS3 or CS0 */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 3,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-#elif defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
-        {       /* AT73C213 DAC */
-                .modalias       = "at73c213",
-                .chip_select    = 3,
-                .max_speed_hz   = 10 * 1000 * 1000,
-                .bus_num        = 0,
-                .mode           = SPI_MODE_1,
-                .platform_data  = &at73c213_data,
-                .controller_data = (void*) AT91_PIN_PA29,       /* default for CS3 is PA6, but it must be PA29 */
-        },
-#endif
-};
-#else /* CONFIG_SPI_ATMEL_* */
-/* spi0 and mmc/sd share the same PIO pins: cannot be used at the same time */
-/*
- * MCI (SD/MMC)
- * det_pin, wp_pin and vcc_pin are not connected
- */
-static struct mci_platform_data __initdata mci0_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = -EINVAL,
-                .wp_pin         = -EINVAL,
-        },
-};
-#endif /* CONFIG_SPI_ATMEL_* */
-/*
- * LCD Controller
- */
-#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
-#if defined(CONFIG_FB_ATMEL_STN)
-/* STN */
-static struct fb_videomode at91_stn_modes[] = {
-        {
-                .name           = "SP06Q002 @ 75",
-                .refresh        = 75,
-                .xres           = 320,          .yres           = 240,
-                .pixclock       = KHZ2PICOS(1440),
-                .left_margin    = 1,            .right_margin   = 1,
-                .upper_margin   = 0,            .lower_margin   = 0,
-                .hsync_len      = 1,            .vsync_len      = 1,
-                .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-};
-static struct fb_monspecs at91fb_default_stn_monspecs = {
-        .manufacturer   = "HIT",
-        .monitor        = "SP06Q002",
-        .modedb         = at91_stn_modes,
-        .modedb_len     = ARRAY_SIZE(at91_stn_modes),
-        .hfmin          = 15000,
-        .hfmax          = 64000,
-        .vfmin          = 50,
-        .vfmax          = 150,
-};
-#define AT91SAM9261_DEFAULT_STN_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
-                                        | ATMEL_LCDC_DISTYPE_STNMONO \
-                                        | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE \
-                                        | ATMEL_LCDC_IFWIDTH_4 \
-                                        | ATMEL_LCDC_SCANMOD_SINGLE)
-static void at91_lcdc_stn_power_control(struct atmel_lcdfb_pdata *pdata, int on)
-{
-        /* backlight */
-        if (on) {       /* power up */
-                at91_set_gpio_value(AT91_PIN_PC14, 0);
-                at91_set_gpio_value(AT91_PIN_PC15, 0);
-        } else {        /* power down */
-                at91_set_gpio_value(AT91_PIN_PC14, 1);
-                at91_set_gpio_value(AT91_PIN_PC15, 1);
-        }
-}
-static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = {
-        .default_bpp                    = 1,
-        .default_dmacon                 = ATMEL_LCDC_DMAEN,
-        .default_lcdcon2                = AT91SAM9261_DEFAULT_STN_LCDCON2,
-        .default_monspecs               = &at91fb_default_stn_monspecs,
-        .atmel_lcdfb_power_control      = at91_lcdc_stn_power_control,
-        .guard_time                     = 1,
-};
-#else
-/* TFT */
-static struct fb_videomode at91_tft_vga_modes[] = {
-        {
-                .name           = "TX09D50VM1CCA @ 60",
-                .refresh        = 60,
-                .xres           = 240,          .yres           = 320,
-                .pixclock       = KHZ2PICOS(4965),
-                .left_margin    = 1,            .right_margin   = 33,
-                .upper_margin   = 1,            .lower_margin   = 0,
-                .hsync_len      = 5,            .vsync_len      = 1,
-                .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-};
-static struct fb_monspecs at91fb_default_tft_monspecs = {
-        .manufacturer   = "HIT",
-        .monitor        = "TX09D50VM1CCA",
-        .modedb         = at91_tft_vga_modes,
-        .modedb_len     = ARRAY_SIZE(at91_tft_vga_modes),
-        .hfmin          = 15000,
-        .hfmax          = 64000,
-        .vfmin          = 50,
-        .vfmax          = 150,
-};
-#define AT91SAM9261_DEFAULT_TFT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
-                                        | ATMEL_LCDC_DISTYPE_TFT    \
-                                        | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
-static void at91_lcdc_tft_power_control(struct atmel_lcdfb_pdata *pdata, int on)
-{
-        if (on)
-                at91_set_gpio_value(AT91_PIN_PA12, 0);  /* power up */
-        else
-                at91_set_gpio_value(AT91_PIN_PA12, 1);  /* power down */
-}
-static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = {
-        .lcdcon_is_backlight            = true,
-        .default_bpp                    = 16,
-        .default_dmacon                 = ATMEL_LCDC_DMAEN,
-        .default_lcdcon2                = AT91SAM9261_DEFAULT_TFT_LCDCON2,
-        .default_monspecs               = &at91fb_default_tft_monspecs,
-        .atmel_lcdfb_power_control      = at91_lcdc_tft_power_control,
-        .guard_time                     = 1,
-};
-#endif
-#else
-static struct atmel_lcdfb_pdata __initdata ek_lcdc_data;
-#endif
-/*
- * GPIO Buttons
- */
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button ek_buttons[] = {
-        {
-                .gpio           = AT91_PIN_PA27,
-                .code           = BTN_0,
-                .desc           = "Button 0",
-                .active_low     = 1,
-                .wakeup         = 1,
-        },
-        {
-                .gpio           = AT91_PIN_PA26,
-                .code           = BTN_1,
-                .desc           = "Button 1",
-                .active_low     = 1,
-                .wakeup         = 1,
-        },
-        {
-                .gpio           = AT91_PIN_PA25,
-                .code           = BTN_2,
-                .desc           = "Button 2",
-                .active_low     = 1,
-                .wakeup         = 1,
-        },
-        {
-                .gpio           = AT91_PIN_PA24,
-                .code           = BTN_3,
-                .desc           = "Button 3",
-                .active_low     = 1,
-                .wakeup         = 1,
-        }
-};
-static struct gpio_keys_platform_data ek_button_data = {
-        .buttons        = ek_buttons,
-        .nbuttons       = ARRAY_SIZE(ek_buttons),
-};
-static struct platform_device ek_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &ek_button_data,
-        }
-};
-static void __init ek_add_device_buttons(void)
-{
-        at91_set_gpio_input(AT91_PIN_PA27, 1);  /* btn0 */
-        at91_set_deglitch(AT91_PIN_PA27, 1);
-        at91_set_gpio_input(AT91_PIN_PA26, 1);  /* btn1 */
-        at91_set_deglitch(AT91_PIN_PA26, 1);
-        at91_set_gpio_input(AT91_PIN_PA25, 1);  /* btn2 */
-        at91_set_deglitch(AT91_PIN_PA25, 1);
-        at91_set_gpio_input(AT91_PIN_PA24, 1);  /* btn3 */
-        at91_set_deglitch(AT91_PIN_PA24, 1);
-        platform_device_register(&ek_button_device);
-}
-#else
-static void __init ek_add_device_buttons(void) {}
-#endif
-/*
- * LEDs
- */
-static struct gpio_led ek_leds[] = {
-        {       /* "bottom" led, green, userled1 to be defined */
-                .name                   = "ds7",
-                .gpio                   = AT91_PIN_PA14,
-                .active_low             = 1,
-                .default_trigger        = "none",
-        },
-        {       /* "top" led, green, userled2 to be defined */
-                .name                   = "ds8",
-                .gpio                   = AT91_PIN_PA13,
-                .active_low             = 1,
-                .default_trigger        = "none",
-        },
-        {       /* "power" led, yellow */
-                .name                   = "ds1",
-                .gpio                   = AT91_PIN_PA23,
-                .default_trigger        = "heartbeat",
-        }
-};
-static void __init ek_board_init(void)
-{
-        at91_register_devices();
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        at91_add_device_serial();
-        if (cpu_is_at91sam9g10())
-                ek_lcdc_data.lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB;
-        /* USB Host */
-        at91_add_device_usbh(&ek_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&ek_udc_data);
-        /* I2C */
-        at91_add_device_i2c(NULL, 0);
-        /* NAND */
-        ek_add_device_nand();
-        /* DM9000 ethernet */
-        ek_add_device_dm9000();
-        /* spi0 and mmc/sd share the same PIO pins */
-#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
-        /* SPI */
-        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
-        /* Touchscreen */
-        ek_add_device_ts();
-        /* SSC (to AT73C213) */
-        at73c213_set_clk(&at73c213_data);
-        at91_add_device_ssc(AT91SAM9261_ID_SSC1, ATMEL_SSC_TX);
-#else
-        /* MMC */
-        at91_add_device_mci(0, &mci0_data);
-#endif
-        /* LCD Controller */
-        at91_add_device_lcdc(&ek_lcdc_data);
-        /* Push Buttons */
-        ek_add_device_buttons();
-        /* LEDs */
-        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
-}
-MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
-        /* Maintainer: Atmel */
-        .init_time      = at91_init_time,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = ek_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = ek_board_init,
-MACHINE_END
-MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
-        /* Maintainer: Atmel */
-        .init_time      = at91_init_time,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = ek_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = ek_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
deleted file mode 100644
index d76680f2a209..000000000000
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ /dev/null
@@ -1,493 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-sam9263ek.c
- *
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2007 Atmel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
-#include <linux/platform_data/at24.h>
-#include <linux/fb.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/leds.h>
-#include <linux/pwm.h>
-#include <linux/leds_pwm.h>
-#include <video/atmel_lcdc.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/system_rev.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "sam9_smc.h"
-#include "generic.h"
-#include "gpio.h"
-static void __init ek_init_early(void)
-{
-        /* Initialize processor: 16.367 MHz crystal */
-        at91_initialize(16367660);
-}
-/*
- * USB Host port
- */
-static struct at91_usbh_data __initdata ek_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = { AT91_PIN_PA24, AT91_PIN_PA21 },
-        .vbus_pin_active_low = {1, 1},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-/*
- * USB Device port
- */
-static struct at91_udc_data __initdata ek_udc_data = {
-        .vbus_pin       = AT91_PIN_PA25,
-        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
-};
-/*
- * ADS7846 Touchscreen
- */
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-static int ads7843_pendown_state(void)
-{
-        return !at91_get_gpio_value(AT91_PIN_PA15);     /* Touchscreen PENIRQ */
-}
-static struct ads7846_platform_data ads_info = {
-        .model                  = 7843,
-        .x_min                  = 150,
-        .x_max                  = 3830,
-        .y_min                  = 190,
-        .y_max                  = 3830,
-        .vref_delay_usecs       = 100,
-        .x_plate_ohms           = 450,
-        .y_plate_ohms           = 250,
-        .pressure_max           = 15000,
-        .debounce_max           = 1,
-        .debounce_rep           = 0,
-        .debounce_tol           = (~0),
-        .get_pendown_state      = ads7843_pendown_state,
-};
-static void __init ek_add_device_ts(void)
-{
-        at91_set_B_periph(AT91_PIN_PA15, 1);    /* External IRQ1, with pullup */
-        at91_set_gpio_input(AT91_PIN_PA31, 1);  /* Touchscreen BUSY signal */
-}
-#else
-static void __init ek_add_device_ts(void) {}
-#endif
-/*
- * SPI devices.
- */
-static struct spi_board_info ek_spi_devices[] = {
-#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
-        {       /* DataFlash card */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-#endif
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-        {
-                .modalias       = "ads7846",
-                .chip_select    = 3,
-                .max_speed_hz   = 125000 * 26,  /* (max sample rate @ 3V) * (cmd + data + overhead) */
-                .bus_num        = 0,
-                .platform_data  = &ads_info,
-                .irq            = NR_IRQS_LEGACY + AT91SAM9263_ID_IRQ1,
-        },
-#endif
-};
-/*
- * MCI (SD/MMC)
- */
-static struct mci_platform_data __initdata mci1_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PE18,
-                .wp_pin         = AT91_PIN_PE19,
-        },
-};
-/*
- * MACB Ethernet device
- */
-static struct macb_platform_data __initdata ek_macb_data = {
-        .phy_irq_pin    = AT91_PIN_PE31,
-        .is_rmii        = 1,
-};
-/*
- * NAND flash
- */
-static struct mtd_partition __initdata ek_nand_partition[] = {
-        {
-                .name   = "Partition 1",
-                .offset = 0,
-                .size   = SZ_64M,
-        },
-        {
-                .name   = "Partition 2",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = MTDPART_SIZ_FULL,
-        },
-};
-static struct atmel_nand_data __initdata ek_nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .det_pin        = -EINVAL,
-        .rdy_pin        = AT91_PIN_PA22,
-        .enable_pin     = AT91_PIN_PD15,
-        .ecc_mode       = NAND_ECC_SOFT,
-        .on_flash_bbt   = 1,
-        .parts          = ek_nand_partition,
-        .num_parts      = ARRAY_SIZE(ek_nand_partition),
-};
-static struct sam9_smc_config __initdata ek_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 1,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 1,
-        .ncs_read_pulse         = 3,
-        .nrd_pulse              = 3,
-        .ncs_write_pulse        = 3,
-        .nwe_pulse              = 3,
-        .read_cycle             = 5,
-        .write_cycle            = 5,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
-        .tdf_cycles             = 2,
-};
-static void __init ek_add_device_nand(void)
-{
-        ek_nand_data.bus_width_16 = board_have_nand_16bit();
-        /* setup bus-width (8 or 16) */
-        if (ek_nand_data.bus_width_16)
-                ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
-        else
-                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
-        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(0, 3, &ek_nand_smc_config);
-        at91_add_device_nand(&ek_nand_data);
-}
-/*
- * I2C devices
- */
-static struct at24_platform_data at24c512 = {
-        .byte_len       = SZ_512K / 8,
-        .page_size      = 128,
-        .flags          = AT24_FLAG_ADDR16,
-};
-static struct i2c_board_info __initdata ek_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("24c512", 0x50),
-                .platform_data = &at24c512,
-        },
-        /* more devices can be added using expansion connectors */
-};
-/*
- * LCD Controller
- */
-#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
-static struct fb_videomode at91_tft_vga_modes[] = {
-        {
-                .name           = "TX09D50VM1CCA @ 60",
-                .refresh        = 60,
-                .xres           = 240,          .yres           = 320,
-                .pixclock       = KHZ2PICOS(4965),
-                .left_margin    = 1,            .right_margin   = 33,
-                .upper_margin   = 1,            .lower_margin   = 0,
-                .hsync_len      = 5,            .vsync_len      = 1,
-                .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-};
-static struct fb_monspecs at91fb_default_monspecs = {
-        .manufacturer   = "HIT",
-        .monitor        = "TX09D70VM1CCA",
-        .modedb         = at91_tft_vga_modes,
-        .modedb_len     = ARRAY_SIZE(at91_tft_vga_modes),
-        .hfmin          = 15000,
-        .hfmax          = 64000,
-        .vfmin          = 50,
-        .vfmax          = 150,
-};
-#define AT91SAM9263_DEFAULT_LCDCON2     (ATMEL_LCDC_MEMOR_LITTLE \
-                                        | ATMEL_LCDC_DISTYPE_TFT \
-                                        | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
-static void at91_lcdc_power_control(struct atmel_lcdfb_pdata *pdata, int on)
-{
-        at91_set_gpio_value(AT91_PIN_PA30, on);
-}
-/* Driver datas */
-static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = {
-        .lcdcon_is_backlight            = true,
-        .default_bpp                    = 16,
-        .default_dmacon                 = ATMEL_LCDC_DMAEN,
-        .default_lcdcon2                = AT91SAM9263_DEFAULT_LCDCON2,
-        .default_monspecs               = &at91fb_default_monspecs,
-        .atmel_lcdfb_power_control      = at91_lcdc_power_control,
-        .guard_time                     = 1,
-};
-#else
-static struct atmel_lcdfb_pdata __initdata ek_lcdc_data;
-#endif
-/*
- * GPIO Buttons
- */
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button ek_buttons[] = {
-        {       /* BP1, "leftclic" */
-                .code           = BTN_LEFT,
-                .gpio           = AT91_PIN_PC5,
-                .active_low     = 1,
-                .desc           = "left_click",
-                .wakeup         = 1,
-        },
-        {       /* BP2, "rightclic" */
-                .code           = BTN_RIGHT,
-                .gpio           = AT91_PIN_PC4,
-                .active_low     = 1,
-                .desc           = "right_click",
-                .wakeup         = 1,
-        }
-};
-static struct gpio_keys_platform_data ek_button_data = {
-        .buttons        = ek_buttons,
-        .nbuttons       = ARRAY_SIZE(ek_buttons),
-};
-static struct platform_device ek_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &ek_button_data,
-        }
-};
-static void __init ek_add_device_buttons(void)
-{
-        at91_set_GPIO_periph(AT91_PIN_PC5, 1);  /* left button */
-        at91_set_deglitch(AT91_PIN_PC5, 1);
-        at91_set_GPIO_periph(AT91_PIN_PC4, 1);  /* right button */
-        at91_set_deglitch(AT91_PIN_PC4, 1);
-        platform_device_register(&ek_button_device);
-}
-#else
-static void __init ek_add_device_buttons(void) {}
-#endif
-/*
- * AC97
- * reset_pin is not connected: NRST
- */
-static struct ac97c_platform_data ek_ac97_data = {
-        .reset_pin      = -EINVAL,
-};
-/*
- * LEDs ... these could all be PWM-driven, for variable brightness
- */
-static struct gpio_led ek_leds[] = {
-        {       /* "right" led, green, userled2 (could be driven by pwm2) */
-                .name                   = "ds2",
-                .gpio                   = AT91_PIN_PC29,
-                .active_low             = 1,
-                .default_trigger        = "nand-disk",
-        },
-        {       /* "power" led, yellow (could be driven by pwm0) */
-                .name                   = "ds3",
-                .gpio                   = AT91_PIN_PB7,
-                .default_trigger        = "heartbeat",
-        },
-#if !IS_ENABLED(CONFIG_LEDS_PWM)
-        {
-                .name                   = "ds1",
-                .gpio                   = AT91_PIN_PB8,
-                .active_low             = 1,
-                .default_trigger        = "none",
-        }
-#endif
-};
-/*
- * PWM Leds
- */
-static struct pwm_lookup pwm_lookup[] = {
-        PWM_LOOKUP("at91sam9rl-pwm", 1, "leds_pwm", "ds1",
-                   5000, PWM_POLARITY_INVERSED),
-};
-#if IS_ENABLED(CONFIG_LEDS_PWM)
-static struct led_pwm pwm_leds[] = {
-        {
-                .name = "ds1",
-                .max_brightness = 255,
-        },
-};
-static struct led_pwm_platform_data pwm_data = {
-        .num_leds       = ARRAY_SIZE(pwm_leds),
-        .leds           = pwm_leds,
-};
-static struct platform_device leds_pwm = {
-        .name   = "leds_pwm",
-        .id     = -1,
-        .dev    = {
-                .platform_data = &pwm_data,
-        },
-};
-#endif
-/*
- * CAN
- */
-static void sam9263ek_transceiver_switch(int on)
-{
-        if (on) {
-                at91_set_gpio_output(AT91_PIN_PA18, 1); /* CANRXEN */
-                at91_set_gpio_output(AT91_PIN_PA19, 0); /* CANRS */
-        } else {
-                at91_set_gpio_output(AT91_PIN_PA18, 0); /* CANRXEN */
-                at91_set_gpio_output(AT91_PIN_PA19, 1); /* CANRS */
-        }
-}
-static struct at91_can_data ek_can_data = {
-        .transceiver_switch = sam9263ek_transceiver_switch,
-};
-static struct platform_device *devices[] __initdata = {
-#if IS_ENABLED(CONFIG_LEDS_PWM)
-        &leds_pwm,
-#endif
-};
-static void __init ek_board_init(void)
-{
-        at91_register_devices();
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        at91_add_device_serial();
-        /* USB Host */
-        at91_add_device_usbh(&ek_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&ek_udc_data);
-        /* SPI */
-        at91_set_gpio_output(AT91_PIN_PE20, 1);         /* select spi0 clock */
-        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
-        /* Touchscreen */
-        ek_add_device_ts();
-        /* MMC */
-        at91_add_device_mci(1, &mci1_data);
-        /* Ethernet */
-        at91_add_device_eth(&ek_macb_data);
-        /* NAND */
-        ek_add_device_nand();
-        /* I2C */
-        at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
-        /* LCD Controller */
-        at91_add_device_lcdc(&ek_lcdc_data);
-        /* Push Buttons */
-        ek_add_device_buttons();
-        /* AC97 */
-        at91_add_device_ac97(&ek_ac97_data);
-        /* LEDs */
-        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
-        pwm_add_table(pwm_lookup, ARRAY_SIZE(pwm_lookup));
-#if IS_ENABLED(CONFIG_LEDS_PWM)
-        at91_add_device_pwm(1 << AT91_PWM1);
-#endif
-        /* CAN */
-        at91_add_device_can(&ek_can_data);
-        /* Other platform devices */
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK")
-        /* Maintainer: Atmel */
-        .init_time      = at91_init_time,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = ek_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = ek_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
deleted file mode 100644
index 49f075213451..000000000000
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ /dev/null
@@ -1,429 +0,0 @@
-/*
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2008 Atmel
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/at73c213.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/clk.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/consumer.h>
-#include <linux/platform_data/at91_adc.h>
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/system_rev.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "sam9_smc.h"
-#include "generic.h"
-#include "gpio.h"
-/*
- * board revision encoding
- * bit 0:
- *      0 => 1 sd/mmc slot
- *      1 => 2 sd/mmc slots connectors (board from revision C)
- */
-#define HAVE_2MMC       (1 << 0)
-static int inline ek_have_2mmc(void)
-{
-        return machine_is_at91sam9g20ek_2mmc() || (system_rev & HAVE_2MMC);
-}
-static void __init ek_init_early(void)
-{
-        /* Initialize processor: 18.432 MHz crystal */
-        at91_initialize(18432000);
-}
-/*
- * USB Host port
- */
-static struct at91_usbh_data __initdata ek_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-/*
- * USB Device port
- */
-static struct at91_udc_data __initdata ek_udc_data = {
-        .vbus_pin       = AT91_PIN_PC5,
-        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
-};
-/*
- * SPI devices.
- */
-static struct spi_board_info ek_spi_devices[] = {
-#if !IS_ENABLED(CONFIG_MMC_ATMELMCI)
-        {       /* DataFlash chip */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 1,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
-        {       /* DataFlash card */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-#endif
-#endif
-};
-/*
- * MACB Ethernet device
- */
-static struct macb_platform_data __initdata ek_macb_data = {
-        .phy_irq_pin    = AT91_PIN_PA7,
-        .is_rmii        = 1,
-};
-static void __init ek_add_device_macb(void)
-{
-        if (ek_have_2mmc())
-                ek_macb_data.phy_irq_pin = AT91_PIN_PB0;
-        at91_add_device_eth(&ek_macb_data);
-}
-/*
- * NAND flash
- */
-static struct mtd_partition __initdata ek_nand_partition[] = {
-        {
-                .name   = "Bootstrap",
-                .offset = 0,
-                .size   = 4 * SZ_1M,
-        },
-        {
-                .name   = "Partition 1",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = 60 * SZ_1M,
-        },
-        {
-                .name   = "Partition 2",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = MTDPART_SIZ_FULL,
-        },
-};
-/* det_pin is not connected */
-static struct atmel_nand_data __initdata ek_nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .rdy_pin        = AT91_PIN_PC13,
-        .enable_pin     = AT91_PIN_PC14,
-        .det_pin        = -EINVAL,
-        .ecc_mode       = NAND_ECC_SOFT,
-        .on_flash_bbt   = 1,
-        .parts          = ek_nand_partition,
-        .num_parts      = ARRAY_SIZE(ek_nand_partition),
-};
-static struct sam9_smc_config __initdata ek_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 2,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 2,
-        .ncs_read_pulse         = 4,
-        .nrd_pulse              = 4,
-        .ncs_write_pulse        = 4,
-        .nwe_pulse              = 4,
-        .read_cycle             = 7,
-        .write_cycle            = 7,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
-        .tdf_cycles             = 3,
-};
-static void __init ek_add_device_nand(void)
-{
-        ek_nand_data.bus_width_16 = board_have_nand_16bit();
-        /* setup bus-width (8 or 16) */
-        if (ek_nand_data.bus_width_16)
-                ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
-        else
-                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
-        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(0, 3, &ek_nand_smc_config);
-        at91_add_device_nand(&ek_nand_data);
-}
-/*
- * MCI (SD/MMC)
- * wp_pin and vcc_pin are not connected
- */
-static struct mci_platform_data __initdata ek_mmc_data = {
-        .slot[1] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PC9,
-                .wp_pin         = -EINVAL,
-        },
-};
-static void __init ek_add_device_mmc(void)
-{
-        if (ek_have_2mmc()) {
-                ek_mmc_data.slot[0].bus_width = 4;
-                ek_mmc_data.slot[0].detect_pin = AT91_PIN_PC2;
-                ek_mmc_data.slot[0].wp_pin = -1;
-        }
-        at91_add_device_mci(0, &ek_mmc_data);
-}
-/*
- * LEDs
- */
-static struct gpio_led ek_leds[] = {
-        {       /* "bottom" led, green, userled1 to be defined */
-                .name                   = "ds5",
-                .gpio                   = AT91_PIN_PA6,
-                .active_low             = 1,
-                .default_trigger        = "none",
-        },
-        {       /* "power" led, yellow */
-                .name                   = "ds1",
-                .gpio                   = AT91_PIN_PA9,
-                .default_trigger        = "heartbeat",
-        }
-};
-static void __init ek_add_device_gpio_leds(void)
-{
-        if (ek_have_2mmc()) {
-                ek_leds[0].gpio = AT91_PIN_PB8;
-                ek_leds[1].gpio = AT91_PIN_PB9;
-        }
-        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
-}
-/*
- * GPIO Buttons
- */
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button ek_buttons[] = {
-        {
-                .gpio           = AT91_PIN_PA30,
-                .code           = BTN_3,
-                .desc           = "Button 3",
-                .active_low     = 1,
-                .wakeup         = 1,
-        },
-        {
-                .gpio           = AT91_PIN_PA31,
-                .code           = BTN_4,
-                .desc           = "Button 4",
-                .active_low     = 1,
-                .wakeup         = 1,
-        }
-};
-static struct gpio_keys_platform_data ek_button_data = {
-        .buttons        = ek_buttons,
-        .nbuttons       = ARRAY_SIZE(ek_buttons),
-};
-static struct platform_device ek_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &ek_button_data,
-        }
-};
-static void __init ek_add_device_buttons(void)
-{
-        at91_set_gpio_input(AT91_PIN_PA30, 1);  /* btn3 */
-        at91_set_deglitch(AT91_PIN_PA30, 1);
-        at91_set_gpio_input(AT91_PIN_PA31, 1);  /* btn4 */
-        at91_set_deglitch(AT91_PIN_PA31, 1);
-        platform_device_register(&ek_button_device);
-}
-#else
-static void __init ek_add_device_buttons(void) {}
-#endif
-/*
- * ADCs
- */
-static struct at91_adc_data ek_adc_data = {
-        .channels_used = BIT(0) | BIT(1) | BIT(2) | BIT(3),
-        .use_external_triggers = true,
-        .vref = 3300,
-};
-#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
-static struct regulator_consumer_supply ek_audio_consumer_supplies[] = {
-        REGULATOR_SUPPLY("AVDD", "0-001b"),
-        REGULATOR_SUPPLY("HPVDD", "0-001b"),
-        REGULATOR_SUPPLY("DBVDD", "0-001b"),
-        REGULATOR_SUPPLY("DCVDD", "0-001b"),
-};
-static struct regulator_init_data ek_avdd_reg_init_data = {
-        .constraints    = {
-                .name   = "3V3",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .consumer_supplies = ek_audio_consumer_supplies,
-        .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies),
-};
-static struct fixed_voltage_config ek_vdd_pdata = {
-        .supply_name    = "board-3V3",
-        .microvolts     = 3300000,
-        .gpio           = -EINVAL,
-        .enabled_at_boot = 0,
-        .init_data      = &ek_avdd_reg_init_data,
-};
-static struct platform_device ek_voltage_regulator = {
-        .name           = "reg-fixed-voltage",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &ek_vdd_pdata,
-        },
-};
-static void __init ek_add_regulators(void)
-{
-        platform_device_register(&ek_voltage_regulator);
-}
-#else
-static void __init ek_add_regulators(void) {}
-#endif
-static struct i2c_board_info __initdata ek_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("24c512", 0x50)
-        },
-        {
-                I2C_BOARD_INFO("wm8731", 0x1b)
-        },
-};
-static struct platform_device sam9g20ek_audio_device = {
-        .name   = "at91sam9g20ek-audio",
-        .id     = -1,
-};
-static void __init ek_add_device_audio(void)
-{
-        platform_device_register(&sam9g20ek_audio_device);
-}
-static void __init ek_board_init(void)
-{
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                           | ATMEL_UART_RI);
-        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        at91_add_device_serial();
-        /* USB Host */
-        at91_add_device_usbh(&ek_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&ek_udc_data);
-        /* SPI */
-        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
-        /* NAND */
-        ek_add_device_nand();
-        /* Ethernet */
-        ek_add_device_macb();
-        /* Regulators */
-        ek_add_regulators();
-        /* MMC */
-        ek_add_device_mmc();
-        /* I2C */
-        at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
-        /* LEDs */
-        ek_add_device_gpio_leds();
-        /* Push Buttons */
-        ek_add_device_buttons();
-        /* ADCs */
-        at91_add_device_adc(&ek_adc_data);
-        /* PCK0 provides MCLK to the WM8731 */
-        at91_set_B_periph(AT91_PIN_PC1, 0);
-        /* SSC (for WM8731) */
-        at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
-        ek_add_device_audio();
-}
-MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
-        /* Maintainer: Atmel */
-        .init_time      = at91_init_time,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = ek_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = ek_board_init,
-MACHINE_END
-MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
-        /* Maintainer: Atmel */
-        .init_time      = at91_init_time,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = ek_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = ek_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
deleted file mode 100644
index a517c7f7af92..000000000000
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ /dev/null
@@ -1,527 +0,0 @@
-/*
- *  Board-specific setup code for the AT91SAM9M10G45 Evaluation Kit family
- *
- *  Covers: * AT91SAM9G45-EKES  board
- *          * AT91SAM9M10G45-EK board
- *
- *  Copyright (C) 2009 Atmel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/fb.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/leds.h>
-#include <linux/atmel-mci.h>
-#include <linux/delay.h>
-#include <linux/pwm.h>
-#include <linux/leds_pwm.h>
-#include <linux/platform_data/at91_adc.h>
-#include <mach/hardware.h>
-#include <video/atmel_lcdc.h>
-#include <media/soc_camera.h>
-#include <media/atmel-isi.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/system_rev.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "sam9_smc.h"
-#include "generic.h"
-#include "gpio.h"
-static void __init ek_init_early(void)
-{
-        /* Initialize processor: 12.000 MHz crystal */
-        at91_initialize(12000000);
-}
-/*
- * USB HS Host port (common to OHCI & EHCI)
- */
-static struct at91_usbh_data __initdata ek_usbh_hs_data = {
-        .ports          = 2,
-        .vbus_pin       = {AT91_PIN_PD1, AT91_PIN_PD3},
-        .vbus_pin_active_low = {1, 1},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-/*
- * USB HS Device port
- */
-static struct usba_platform_data __initdata ek_usba_udc_data = {
-        .vbus_pin       = AT91_PIN_PB19,
-};
-/*
- * SPI devices.
- */
-static struct spi_board_info ek_spi_devices[] = {
-        {       /* DataFlash chip */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-};
-/*
- * MCI (SD/MMC)
- */
-static struct mci_platform_data __initdata mci0_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PD10,
-                .wp_pin         = -EINVAL,
-        },
-};
-static struct mci_platform_data __initdata mci1_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PD11,
-                .wp_pin         = AT91_PIN_PD29,
-        },
-};
-/*
- * MACB Ethernet device
- */
-static struct macb_platform_data __initdata ek_macb_data = {
-        .phy_irq_pin    = AT91_PIN_PD5,
-        .is_rmii        = 1,
-};
-/*
- * NAND flash
- */
-static struct mtd_partition __initdata ek_nand_partition[] = {
-        {
-                .name   = "Partition 1",
-                .offset = 0,
-                .size   = SZ_64M,
-        },
-        {
-                .name   = "Partition 2",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = MTDPART_SIZ_FULL,
-        },
-};
-/* det_pin is not connected */
-static struct atmel_nand_data __initdata ek_nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .rdy_pin        = AT91_PIN_PC8,
-        .enable_pin     = AT91_PIN_PC14,
-        .det_pin        = -EINVAL,
-        .ecc_mode       = NAND_ECC_SOFT,
-        .on_flash_bbt   = 1,
-        .parts          = ek_nand_partition,
-        .num_parts      = ARRAY_SIZE(ek_nand_partition),
-};
-static struct sam9_smc_config __initdata ek_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 2,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 2,
-        .ncs_read_pulse         = 4,
-        .nrd_pulse              = 4,
-        .ncs_write_pulse        = 4,
-        .nwe_pulse              = 4,
-        .read_cycle             = 7,
-        .write_cycle            = 7,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
-        .tdf_cycles             = 3,
-};
-static void __init ek_add_device_nand(void)
-{
-        ek_nand_data.bus_width_16 = board_have_nand_16bit();
-        /* setup bus-width (8 or 16) */
-        if (ek_nand_data.bus_width_16)
-                ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
-        else
-                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
-        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(0, 3, &ek_nand_smc_config);
-        at91_add_device_nand(&ek_nand_data);
-}
-/*
- *  ISI
- */
-static struct isi_platform_data __initdata isi_data = {
-        .frate                  = ISI_CFG1_FRATE_CAPTURE_ALL,
-        /* to use codec and preview path simultaneously */
-        .full_mode              = 1,
-        .data_width_flags       = ISI_DATAWIDTH_8 | ISI_DATAWIDTH_10,
-        /* ISI_MCK is provided by programmable clock or external clock */
-        .mck_hz                 = 25000000,
-};
-/*
- * soc-camera OV2640
- */
-#if defined(CONFIG_SOC_CAMERA_OV2640) || \
-        defined(CONFIG_SOC_CAMERA_OV2640_MODULE)
-static unsigned long isi_camera_query_bus_param(struct soc_camera_link *link)
-{
-        /* ISI board for ek using default 8-bits connection */
-        return SOCAM_DATAWIDTH_8;
-}
-static int i2c_camera_power(struct device *dev, int on)
-{
-        /* enable or disable the camera */
-        pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
-        at91_set_gpio_output(AT91_PIN_PD13, !on);
-        if (!on)
-                goto out;
-        /* If enabled, give a reset impulse */
-        at91_set_gpio_output(AT91_PIN_PD12, 0);
-        msleep(20);
-        at91_set_gpio_output(AT91_PIN_PD12, 1);
-        msleep(100);
-out:
-        return 0;
-}
-static struct i2c_board_info i2c_camera = {
-        I2C_BOARD_INFO("ov2640", 0x30),
-};
-static struct soc_camera_link iclink_ov2640 = {
-        .bus_id                 = 0,
-        .board_info             = &i2c_camera,
-        .i2c_adapter_id         = 0,
-        .power                  = i2c_camera_power,
-        .query_bus_param        = isi_camera_query_bus_param,
-};
-static struct platform_device isi_ov2640 = {
-        .name   = "soc-camera-pdrv",
-        .id     = 0,
-        .dev    = {
-                .platform_data = &iclink_ov2640,
-        },
-};
-#endif
-/*
- * LCD Controller
- */
-#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
-static struct fb_videomode at91_tft_vga_modes[] = {
-        {
-                .name           = "LG",
-                .refresh        = 60,
-                .xres           = 480,          .yres           = 272,
-                .pixclock       = KHZ2PICOS(9000),
-                .left_margin    = 1,            .right_margin   = 1,
-                .upper_margin   = 40,           .lower_margin   = 1,
-                .hsync_len      = 45,           .vsync_len      = 1,
-                .sync           = 0,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-};
-static struct fb_monspecs at91fb_default_monspecs = {
-        .manufacturer   = "LG",
-        .monitor        = "LB043WQ1",
-        .modedb         = at91_tft_vga_modes,
-        .modedb_len     = ARRAY_SIZE(at91_tft_vga_modes),
-        .hfmin          = 15000,
-        .hfmax          = 17640,
-        .vfmin          = 57,
-        .vfmax          = 67,
-};
-#define AT91SAM9G45_DEFAULT_LCDCON2     (ATMEL_LCDC_MEMOR_LITTLE \
-                                        | ATMEL_LCDC_DISTYPE_TFT \
-                                        | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
-/* Driver datas */
-static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = {
-        .lcdcon_is_backlight            = true,
-        .default_bpp                    = 32,
-        .default_dmacon                 = ATMEL_LCDC_DMAEN,
-        .default_lcdcon2                = AT91SAM9G45_DEFAULT_LCDCON2,
-        .default_monspecs               = &at91fb_default_monspecs,
-        .guard_time                     = 9,
-        .lcd_wiring_mode                = ATMEL_LCDC_WIRING_RGB,
-};
-#else
-static struct atmel_lcdfb_pdata __initdata ek_lcdc_data;
-#endif
-/*
- * ADCs and touchscreen
- */
-static struct at91_adc_data ek_adc_data = {
-        .channels_used = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7),
-        .use_external_triggers = true,
-        .vref = 3300,
-        .touchscreen_type = ATMEL_ADC_TOUCHSCREEN_4WIRE,
-};
-/*
- * GPIO Buttons
- */
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button ek_buttons[] = {
-        {       /* BP1, "leftclic" */
-                .code           = BTN_LEFT,
-                .gpio           = AT91_PIN_PB6,
-                .active_low     = 1,
-                .desc           = "left_click",
-                .wakeup         = 1,
-        },
-        {       /* BP2, "rightclic" */
-                .code           = BTN_RIGHT,
-                .gpio           = AT91_PIN_PB7,
-                .active_low     = 1,
-                .desc           = "right_click",
-                .wakeup         = 1,
-        },
-                /* BP3, "joystick" */
-        {
-                .code           = KEY_LEFT,
-                .gpio           = AT91_PIN_PB14,
-                .active_low     = 1,
-                .desc           = "Joystick Left",
-        },
-        {
-                .code           = KEY_RIGHT,
-                .gpio           = AT91_PIN_PB15,
-                .active_low     = 1,
-                .desc           = "Joystick Right",
-        },
-        {
-                .code           = KEY_UP,
-                .gpio           = AT91_PIN_PB16,
-                .active_low     = 1,
-                .desc           = "Joystick Up",
-        },
-        {
-                .code           = KEY_DOWN,
-                .gpio           = AT91_PIN_PB17,
-                .active_low     = 1,
-                .desc           = "Joystick Down",
-        },
-        {
-                .code           = KEY_ENTER,
-                .gpio           = AT91_PIN_PB18,
-                .active_low     = 1,
-                .desc           = "Joystick Press",
-        },
-};
-static struct gpio_keys_platform_data ek_button_data = {
-        .buttons        = ek_buttons,
-        .nbuttons       = ARRAY_SIZE(ek_buttons),
-};
-static struct platform_device ek_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &ek_button_data,
-        }
-};
-static void __init ek_add_device_buttons(void)
-{
-        int i;
-        for (i = 0; i < ARRAY_SIZE(ek_buttons); i++) {
-                at91_set_GPIO_periph(ek_buttons[i].gpio, 1);
-                at91_set_deglitch(ek_buttons[i].gpio, 1);
-        }
-        platform_device_register(&ek_button_device);
-}
-#else
-static void __init ek_add_device_buttons(void) {}
-#endif
-/*
- * AC97
- * reset_pin is not connected: NRST
- */
-static struct ac97c_platform_data ek_ac97_data = {
-        .reset_pin      = -EINVAL,
-};
-/*
- * LEDs ... these could all be PWM-driven, for variable brightness
- */
-static struct gpio_led ek_leds[] = {
-        {       /* "top" led, red, powerled */
-                .name                   = "d8",
-                .gpio                   = AT91_PIN_PD30,
-                .default_trigger        = "heartbeat",
-        },
-        {       /* "left" led, green, userled2, pwm3 */
-                .name                   = "d6",
-                .gpio                   = AT91_PIN_PD0,
-                .active_low             = 1,
-                .default_trigger        = "nand-disk",
-        },
-#if !IS_ENABLED(CONFIG_LEDS_PWM)
-        {       /* "right" led, green, userled1, pwm1 */
-                .name                   = "d7",
-                .gpio                   = AT91_PIN_PD31,
-                .active_low             = 1,
-                .default_trigger        = "mmc0",
-        },
-#endif
-};
-/*
- * PWM Leds
- */
-static struct pwm_lookup pwm_lookup[] = {
-        PWM_LOOKUP("at91sam9rl-pwm", 1, "leds_pwm", "d7",
-                   5000, PWM_POLARITY_INVERSED),
-};
-#if IS_ENABLED(CONFIG_LEDS_PWM)
-static struct led_pwm pwm_leds[] = {
-        {       /* "right" led, green, userled1, pwm1 */
-                .name = "d7",
-                .max_brightness = 255,
-        },
-};
-static struct led_pwm_platform_data pwm_data = {
-        .num_leds       = ARRAY_SIZE(pwm_leds),
-        .leds           = pwm_leds,
-};
-static struct platform_device leds_pwm = {
-        .name   = "leds_pwm",
-        .id     = -1,
-        .dev    = {
-                .platform_data = &pwm_data,
-        },
-};
-#endif
-static struct platform_device *devices[] __initdata = {
-#if defined(CONFIG_SOC_CAMERA_OV2640) || \
-        defined(CONFIG_SOC_CAMERA_OV2640_MODULE)
-        &isi_ov2640,
-#endif
-#if IS_ENABLED(CONFIG_LEDS_PWM)
-        &leds_pwm,
-#endif
-};
-static void __init ek_board_init(void)
-{
-        at91_register_devices();
-        /* Serial */
-        /* DGBU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 not connected on the -EK board */
-        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9G45_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        at91_add_device_serial();
-        /* USB HS Host */
-        at91_add_device_usbh_ohci(&ek_usbh_hs_data);
-        at91_add_device_usbh_ehci(&ek_usbh_hs_data);
-        /* USB HS Device */
-        at91_add_device_usba(&ek_usba_udc_data);
-        /* SPI */
-        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
-        /* MMC */
-        at91_add_device_mci(0, &mci0_data);
-        at91_add_device_mci(1, &mci1_data);
-        /* Ethernet */
-        at91_add_device_eth(&ek_macb_data);
-        /* NAND */
-        ek_add_device_nand();
-        /* I2C */
-        at91_add_device_i2c(0, NULL, 0);
-        /* ISI, using programmable clock as ISI_MCK */
-        at91_add_device_isi(&isi_data, true);
-        /* LCD Controller */
-        at91_add_device_lcdc(&ek_lcdc_data);
-        /* ADC and touchscreen */
-        at91_add_device_adc(&ek_adc_data);
-        /* Push Buttons */
-        ek_add_device_buttons();
-        /* AC97 */
-        at91_add_device_ac97(&ek_ac97_data);
-        /* LEDs */
-        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
-        pwm_add_table(pwm_lookup, ARRAY_SIZE(pwm_lookup));
-#if IS_ENABLED(CONFIG_LEDS_PWM)
-        at91_add_device_pwm(1 << AT91_PWM1);
-#endif
-        /* Other platform devices */
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
-        /* Maintainer: Atmel */
-        .init_time      = at91_init_time,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = ek_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = ek_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
deleted file mode 100644
index 8bca329b0293..000000000000
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ /dev/null
@@ -1,333 +0,0 @@
-/*
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2007 Atmel Corporation
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive for
- * more details.
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/fb.h>
-#include <linux/clk.h>
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-#include <linux/platform_data/at91_adc.h>
-#include <video/atmel_lcdc.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/at91sam9_smc.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "sam9_smc.h"
-#include "generic.h"
-#include "gpio.h"
-static void __init ek_init_early(void)
-{
-        /* Initialize processor: 12.000 MHz crystal */
-        at91_initialize(12000000);
-}
-/*
- * USB HS Device port
- */
-static struct usba_platform_data __initdata ek_usba_udc_data = {
-        .vbus_pin       = AT91_PIN_PA8,
-};
-/*
- * MCI (SD/MMC)
- */
-static struct mci_platform_data __initdata mci0_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PA15,
-                .wp_pin         = -EINVAL,
-        },
-};
-/*
- * NAND flash
- */
-static struct mtd_partition __initdata ek_nand_partition[] = {
-        {
-                .name   = "Partition 1",
-                .offset = 0,
-                .size   = SZ_256K,
-        },
-        {
-                .name   = "Partition 2",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = MTDPART_SIZ_FULL,
-        },
-};
-static struct atmel_nand_data __initdata ek_nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .det_pin        = -EINVAL,
-        .rdy_pin        = AT91_PIN_PD17,
-        .enable_pin     = AT91_PIN_PB6,
-        .ecc_mode       = NAND_ECC_SOFT,
-        .on_flash_bbt   = 1,
-        .parts          = ek_nand_partition,
-        .num_parts      = ARRAY_SIZE(ek_nand_partition),
-};
-static struct sam9_smc_config __initdata ek_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 1,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 1,
-        .ncs_read_pulse         = 3,
-        .nrd_pulse              = 3,
-        .ncs_write_pulse        = 3,
-        .nwe_pulse              = 3,
-        .read_cycle             = 5,
-        .write_cycle            = 5,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
-        .tdf_cycles             = 2,
-};
-static void __init ek_add_device_nand(void)
-{
-        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(0, 3, &ek_nand_smc_config);
-        at91_add_device_nand(&ek_nand_data);
-}
-/*
- * SPI devices
- */
-static struct spi_board_info ek_spi_devices[] = {
-        {       /* DataFlash chip */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-};
-/*
- * LCD Controller
- */
-#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
-static struct fb_videomode at91_tft_vga_modes[] = {
-        {
-                .name           = "TX09D50VM1CCA @ 60",
-                .refresh        = 60,
-                .xres           = 240,          .yres           = 320,
-                .pixclock       = KHZ2PICOS(4965),
-                .left_margin    = 1,            .right_margin   = 33,
-                .upper_margin   = 1,            .lower_margin   = 0,
-                .hsync_len      = 5,            .vsync_len      = 1,
-                .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-};
-static struct fb_monspecs at91fb_default_monspecs = {
-        .manufacturer   = "HIT",
-        .monitor        = "TX09D50VM1CCA",
-        .modedb         = at91_tft_vga_modes,
-        .modedb_len     = ARRAY_SIZE(at91_tft_vga_modes),
-        .hfmin          = 15000,
-        .hfmax          = 64000,
-        .vfmin          = 50,
-        .vfmax          = 150,
-};
-#define AT91SAM9RL_DEFAULT_LCDCON2      (ATMEL_LCDC_MEMOR_LITTLE \
-                                        | ATMEL_LCDC_DISTYPE_TFT \
-                                        | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
-static void at91_lcdc_power_control(struct atmel_lcdfb_pdata *pdata, int on)
-{
-        if (on)
-                at91_set_gpio_value(AT91_PIN_PC1, 0);   /* power up */
-        else
-                at91_set_gpio_value(AT91_PIN_PC1, 1);   /* power down */
-}
-/* Driver datas */
-static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = {
-        .lcdcon_is_backlight            = true,
-        .default_bpp                    = 16,
-        .default_dmacon                 = ATMEL_LCDC_DMAEN,
-        .default_lcdcon2                = AT91SAM9RL_DEFAULT_LCDCON2,
-        .default_monspecs               = &at91fb_default_monspecs,
-        .atmel_lcdfb_power_control      = at91_lcdc_power_control,
-        .guard_time                     = 1,
-        .lcd_wiring_mode                = ATMEL_LCDC_WIRING_RGB,
-};
-#else
-static struct atmel_lcdfb_pdata __initdata ek_lcdc_data;
-#endif
-/*
- * AC97
- * reset_pin is not connected: NRST
- */
-static struct ac97c_platform_data ek_ac97_data = {
-        .reset_pin      = -EINVAL,
-};
-/*
- * LEDs
- */
-static struct gpio_led ek_leds[] = {
-        {       /* "bottom" led, green, userled1 to be defined */
-                .name                   = "ds1",
-                .gpio                   = AT91_PIN_PD15,
-                .active_low             = 1,
-                .default_trigger        = "none",
-        },
-        {       /* "bottom" led, green, userled2 to be defined */
-                .name                   = "ds2",
-                .gpio                   = AT91_PIN_PD16,
-                .active_low             = 1,
-                .default_trigger        = "none",
-        },
-        {       /* "power" led, yellow */
-                .name                   = "ds3",
-                .gpio                   = AT91_PIN_PD14,
-                .default_trigger        = "heartbeat",
-        }
-};
-/*
- * ADC + Touchscreen
- */
-static struct at91_adc_data ek_adc_data = {
-        .channels_used = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5),
-        .use_external_triggers = true,
-        .vref = 3300,
-        .touchscreen_type = ATMEL_ADC_TOUCHSCREEN_4WIRE,
-};
-/*
- * GPIO Buttons
- */
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button ek_buttons[] = {
-        {
-                .gpio           = AT91_PIN_PB0,
-                .code           = BTN_2,
-                .desc           = "Right Click",
-                .active_low     = 1,
-                .wakeup         = 1,
-        },
-        {
-                .gpio           = AT91_PIN_PB1,
-                .code           = BTN_1,
-                .desc           = "Left Click",
-                .active_low     = 1,
-                .wakeup         = 1,
-        }
-};
-static struct gpio_keys_platform_data ek_button_data = {
-        .buttons        = ek_buttons,
-        .nbuttons       = ARRAY_SIZE(ek_buttons),
-};
-static struct platform_device ek_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &ek_button_data,
-        }
-};
-static void __init ek_add_device_buttons(void)
-{
-        at91_set_gpio_input(AT91_PIN_PB1, 1);   /* btn1 */
-        at91_set_deglitch(AT91_PIN_PB1, 1);
-        at91_set_gpio_input(AT91_PIN_PB0, 1);   /* btn2 */
-        at91_set_deglitch(AT91_PIN_PB0, 1);
-        platform_device_register(&ek_button_device);
-}
-#else
-static void __init ek_add_device_buttons(void) {}
-#endif
-static void __init ek_board_init(void)
-{
-        at91_register_devices();
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
-        at91_register_uart(AT91SAM9RL_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        at91_add_device_serial();
-        /* USB HS */
-        at91_add_device_usba(&ek_usba_udc_data);
-        /* I2C */
-        at91_add_device_i2c(NULL, 0);
-        /* NAND */
-        ek_add_device_nand();
-        /* SPI */
-        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
-        /* MMC */
-        at91_add_device_mci(0, &mci0_data);
-        /* LCD Controller */
-        at91_add_device_lcdc(&ek_lcdc_data);
-        /* AC97 */
-        at91_add_device_ac97(&ek_ac97_data);
-        /* Touch Screen Controller + ADC */
-        at91_add_device_adc(&ek_adc_data);
-        /* LEDs */
-        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
-        /* Push Buttons */
-        ek_add_device_buttons();
-}
-MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
-        /* Maintainer: Atmel */
-        .init_time      = at91_init_time,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = ek_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = ek_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
deleted file mode 100644
index b4aff840a1a0..000000000000
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-snapper9260.c
- *
- *  Copyright (C) 2010 Bluewater System Ltd
- *
- * Author: Andre Renaud <andre@bluewatersys.com>
- * Author: Ryan Mallon
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/platform_data/pca953x.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/hardware.h>
-#include <mach/at91sam9_smc.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "sam9_smc.h"
-#include "generic.h"
-#include "gpio.h"
-#define SNAPPER9260_IO_EXP_GPIO(x)      (NR_BUILTIN_GPIO + (x))
-static void __init snapper9260_init_early(void)
-{
-        at91_initialize(18432000);
-}
-static struct at91_usbh_data __initdata snapper9260_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-static struct at91_udc_data __initdata snapper9260_udc_data = {
-        .vbus_pin               = SNAPPER9260_IO_EXP_GPIO(5),
-        .vbus_active_low        = 1,
-        .vbus_polled            = 1,
-        .pullup_pin             = -EINVAL,
-};
-static struct macb_platform_data snapper9260_macb_data = {
-        .phy_irq_pin    = -EINVAL,
-        .is_rmii        = 1,
-};
-static struct mtd_partition __initdata snapper9260_nand_partitions[] = {
-        {
-                .name   = "Preboot",
-                .offset = 0,
-                .size   = SZ_128K,
-        },
-        {
-                .name   = "Bootloader",
-                .offset = MTDPART_OFS_APPEND,
-                .size   = SZ_256K,
-        },
-        {
-                .name   = "Environment",
-                .offset = MTDPART_OFS_APPEND,
-                .size   = SZ_128K,
-        },
-        {
-                .name   = "Kernel",
-                .offset = MTDPART_OFS_APPEND,
-                .size   = SZ_4M,
-        },
-        {
-                .name   = "Filesystem",
-                .offset = MTDPART_OFS_APPEND,
-                .size   = MTDPART_SIZ_FULL,
-        },
-};
-static struct atmel_nand_data __initdata snapper9260_nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .rdy_pin        = AT91_PIN_PC13,
-        .parts          = snapper9260_nand_partitions,
-        .num_parts      = ARRAY_SIZE(snapper9260_nand_partitions),
-        .bus_width_16   = 0,
-        .enable_pin     = -EINVAL,
-        .det_pin        = -EINVAL,
-        .ecc_mode       = NAND_ECC_SOFT,
-};
-static struct sam9_smc_config __initdata snapper9260_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 0,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 0,
-        .ncs_read_pulse         = 5,
-        .nrd_pulse              = 2,
-        .ncs_write_pulse        = 5,
-        .nwe_pulse              = 2,
-        .read_cycle             = 7,
-        .write_cycle            = 7,
-        .mode                   = (AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-                                   AT91_SMC_EXNWMODE_DISABLE),
-        .tdf_cycles             = 1,
-};
-static struct pca953x_platform_data snapper9260_io_expander_data = {
-        .gpio_base              = SNAPPER9260_IO_EXP_GPIO(0),
-};
-static struct i2c_board_info __initdata snapper9260_i2c_devices[] = {
-        {
-                /* IO expander */
-                I2C_BOARD_INFO("max7312", 0x28),
-                .platform_data = &snapper9260_io_expander_data,
-        },
-        {
-                /* Audio codec */
-                I2C_BOARD_INFO("tlv320aic23", 0x1a),
-        },
-};
-static struct i2c_board_info __initdata snapper9260_i2c_isl1208 = {
-                /* RTC */
-                I2C_BOARD_INFO("isl1208", 0x6f),
-};
-static void __init snapper9260_add_device_nand(void)
-{
-        at91_set_A_periph(AT91_PIN_PC14, 0);
-        sam9_smc_configure(0, 3, &snapper9260_nand_smc_config);
-        at91_add_device_nand(&snapper9260_nand_data);
-}
-static void __init snapper9260_board_init(void)
-{
-        at91_register_devices();
-        at91_add_device_i2c(snapper9260_i2c_devices,
-                            ARRAY_SIZE(snapper9260_i2c_devices));
-        snapper9260_i2c_isl1208.irq = gpio_to_irq(AT91_PIN_PA31);
-        i2c_register_board_info(0, &snapper9260_i2c_isl1208, 1);
-        /* Debug on ttyS0 */
-        at91_register_uart(0, 0, 0);
-        at91_register_uart(AT91SAM9260_ID_US0, 1,
-                           ATMEL_UART_CTS | ATMEL_UART_RTS);
-        at91_register_uart(AT91SAM9260_ID_US1, 2,
-                           ATMEL_UART_CTS | ATMEL_UART_RTS);
-        at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
-        at91_add_device_serial();
-        at91_add_device_usbh(&snapper9260_usbh_data);
-        at91_add_device_udc(&snapper9260_udc_data);
-        at91_add_device_eth(&snapper9260_macb_data);
-        at91_add_device_ssc(AT91SAM9260_ID_SSC, (ATMEL_SSC_TF | ATMEL_SSC_TK |
-                                                 ATMEL_SSC_TD | ATMEL_SSC_RD));
-        snapper9260_add_device_nand();
-}
-MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
-        .init_time      = at91_init_time,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = snapper9260_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = snapper9260_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
deleted file mode 100644
index e825641a1dee..000000000000
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- *  Copyright (C) 2010 Christian Glindkamp <christian.glindkamp@taskit.de>
- *                     taskit GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/mm.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/w1-gpio.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/hardware.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "sam9_smc.h"
-#include "generic.h"
-#include "gpio.h"
-void __init stamp9g20_init_early(void)
-{
-        /* Initialize processor: 18.432 MHz crystal */
-        at91_initialize(18432000);
-}
-/*
- * NAND flash
- */
-static struct atmel_nand_data __initdata nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .rdy_pin        = AT91_PIN_PC13,
-        .enable_pin     = AT91_PIN_PC14,
-        .bus_width_16   = 0,
-        .det_pin        = -EINVAL,
-        .ecc_mode       = NAND_ECC_SOFT,
-};
-static struct sam9_smc_config __initdata nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 2,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 2,
-        .ncs_read_pulse         = 4,
-        .nrd_pulse              = 4,
-        .ncs_write_pulse        = 4,
-        .nwe_pulse              = 4,
-        .read_cycle             = 7,
-        .write_cycle            = 7,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
-        .tdf_cycles             = 3,
-};
-static void __init add_device_nand(void)
-{
-        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(0, 3, &nand_smc_config);
-        at91_add_device_nand(&nand_data);
-}
-/*
- * MCI (SD/MMC)
- * det_pin, wp_pin and vcc_pin are not connected
- */
-static struct mci_platform_data __initdata mmc_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = -1,
-                .wp_pin         = -1,
-        },
-};
-/*
- * USB Host port
- */
-static struct at91_usbh_data __initdata usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-/*
- * USB Device port
- */
-static struct at91_udc_data __initdata portuxg20_udc_data = {
-        .vbus_pin       = AT91_PIN_PC7,
-        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
-};
-static struct at91_udc_data __initdata stamp9g20evb_udc_data = {
-        .vbus_pin       = AT91_PIN_PA22,
-        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
-};
-/*
- * MACB Ethernet device
- */
-static struct macb_platform_data __initdata macb_data = {
-        .phy_irq_pin    = AT91_PIN_PA28,
-        .is_rmii        = 1,
-};
-/*
- * LEDs
- */
-static struct gpio_led portuxg20_leds[] = {
-        {
-                .name                   = "LED2",
-                .gpio                   = AT91_PIN_PC5,
-                .default_trigger        = "none",
-        }, {
-                .name                   = "LED3",
-                .gpio                   = AT91_PIN_PC4,
-                .default_trigger        = "none",
-        }, {
-                .name                   = "LED4",
-                .gpio                   = AT91_PIN_PC10,
-                .default_trigger        = "heartbeat",
-        }
-};
-static struct gpio_led stamp9g20evb_leds[] = {
-        {
-                .name                   = "D8",
-                .gpio                   = AT91_PIN_PB18,
-                .active_low             = 1,
-                .default_trigger        = "none",
-        }, {
-                .name                   = "D9",
-                .gpio                   = AT91_PIN_PB19,
-                .active_low             = 1,
-                .default_trigger        = "none",
-        }, {
-                .name                   = "D10",
-                .gpio                   = AT91_PIN_PB20,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",
-        }
-};
-/*
- * SPI devices
- */
-static struct spi_board_info portuxg20_spi_devices[] = {
-        {
-                .modalias       = "spidev",
-                .chip_select    = 0,
-                .max_speed_hz   = 1 * 1000 * 1000,
-                .bus_num        = 0,
-        }, {
-                .modalias       = "spidev",
-                .chip_select    = 0,
-                .max_speed_hz   = 1 * 1000 * 1000,
-                .bus_num        = 1,
-        },
-};
-/*
- * Dallas 1-Wire
- */
-static struct w1_gpio_platform_data w1_gpio_pdata = {
-        .pin            = AT91_PIN_PA29,
-        .is_open_drain  = 1,
-        .ext_pullup_enable_pin  = -EINVAL,
-};
-static struct platform_device w1_device = {
-        .name                   = "w1-gpio",
-        .id                     = -1,
-        .dev.platform_data      = &w1_gpio_pdata,
-};
-void add_w1(void)
-{
-        at91_set_GPIO_periph(w1_gpio_pdata.pin, 1);
-        at91_set_multi_drive(w1_gpio_pdata.pin, 1);
-        platform_device_register(&w1_device);
-}
-void __init stamp9g20_board_init(void)
-{
-        /* Serial */
-        /* DGBU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        at91_add_device_serial();
-        /* NAND */
-        add_device_nand();
-        /* MMC */
-        at91_add_device_mci(0, &mmc_data);
-        /* W1 */
-        add_w1();
-}
-static void __init portuxg20_board_init(void)
-{
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                                                | ATMEL_UART_DTR | ATMEL_UART_DSR
-                                                | ATMEL_UART_DCD | ATMEL_UART_RI);
-        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
-        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */
-        at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        /* USART4 on ttyS5. (Rx, Tx only) */
-        at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
-        /* USART5 on ttyS6. (Rx, Tx only) */
-        at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
-        stamp9g20_board_init();
-        /* USB Host */
-        at91_add_device_usbh(&usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&portuxg20_udc_data);
-        /* Ethernet */
-        at91_add_device_eth(&macb_data);
-        /* I2C */
-        at91_add_device_i2c(NULL, 0);
-        /* SPI */
-        at91_add_device_spi(portuxg20_spi_devices, ARRAY_SIZE(portuxg20_spi_devices));
-        /* LEDs */
-        at91_gpio_leds(portuxg20_leds, ARRAY_SIZE(portuxg20_leds));
-}
-static void __init stamp9g20evb_board_init(void)
-{
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                                                | ATMEL_UART_DTR | ATMEL_UART_DSR
-                                                | ATMEL_UART_DCD | ATMEL_UART_RI);
-        stamp9g20_board_init();
-        /* USB Host */
-        at91_add_device_usbh(&usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&stamp9g20evb_udc_data);
-        /* Ethernet */
-        at91_add_device_eth(&macb_data);
-        /* I2C */
-        at91_add_device_i2c(NULL, 0);
-        /* LEDs */
-        at91_gpio_leds(stamp9g20evb_leds, ARRAY_SIZE(stamp9g20evb_leds));
-}
-MACHINE_START(PORTUXG20, "taskit PortuxG20")
-        /* Maintainer: taskit GmbH */
-        .init_time      = at91_init_time,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = stamp9g20_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = portuxg20_board_init,
-MACHINE_END
-MACHINE_START(STAMP9G20, "taskit Stamp9G20")
-        /* Maintainer: taskit GmbH */
-        .init_time      = at91_init_time,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = stamp9g20_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = stamp9g20evb_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
deleted file mode 100644
index 46fdb0c68a68..000000000000
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ /dev/null
@@ -1,597 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-yl-9200.c
- *
- * Adapted from various board files in arch/arm/mach-at91
- *
- * Modifications for YL-9200 platform:
- *  Copyright (C) 2007 S. Birtles
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
-#include <linux/mtd/physmap.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
-#include <mach/cpu.h>
-#include "at91_aic.h"
-#include "board.h"
-#include "generic.h"
-#include "gpio.h"
-static void __init yl9200_init_early(void)
-{
-        /* Set cpu type: PQFP */
-        at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
-        /* Initialize processor: 18.432 MHz crystal */
-        at91_initialize(18432000);
-}
-/*
- * LEDs
- */
-static struct gpio_led yl9200_leds[] = {
-        {       /* D2 */
-                .name                   = "led2",
-                .gpio                   = AT91_PIN_PB17,
-                .active_low             = 1,
-                .default_trigger        = "timer",
-        },
-        {       /* D3 */
-                .name                   = "led3",
-                .gpio                   = AT91_PIN_PB16,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",
-        },
-        {       /* D4 */
-                .name                   = "led4",
-                .gpio                   = AT91_PIN_PB15,
-                .active_low             = 1,
-        },
-        {       /* D5 */
-                .name                   = "led5",
-                .gpio                   = AT91_PIN_PB8,
-                .active_low             = 1,
-        }
-};
-/*
- * Ethernet
- */
-static struct macb_platform_data __initdata yl9200_eth_data = {
-        .phy_irq_pin            = AT91_PIN_PB28,
-        .is_rmii                = 1,
-};
-/*
- * USB Host
- */
-static struct at91_usbh_data __initdata yl9200_usbh_data = {
-        .ports                  = 1,    /* PQFP version of AT91RM9200 */
-        .vbus_pin               = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-/*
- * USB Device
- */
-static struct at91_udc_data __initdata yl9200_udc_data = {
-        .pullup_pin             = AT91_PIN_PC4,
-        .vbus_pin               = AT91_PIN_PC5,
-        .pullup_active_low      = 1,    /* Active Low due to PNP transistor (pg 7) */
-};
-/*
- * MMC
- */
-static struct mci_platform_data __initdata yl9200_mci0_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PB9,
-                .wp_pin         = -EINVAL,
-        },
-};
-/*
- * NAND Flash
- */
-static struct mtd_partition __initdata yl9200_nand_partition[] = {
-        {
-                .name   = "AT91 NAND partition 1, boot",
-                .offset = 0,
-                .size   = SZ_256K
-        },
-        {
-                .name   = "AT91 NAND partition 2, kernel",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = (2 * SZ_1M) - SZ_256K
-        },
-        {
-                .name   = "AT91 NAND partition 3, filesystem",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = 14 * SZ_1M
-        },
-        {
-                .name   = "AT91 NAND partition 4, storage",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = SZ_16M
-        },
-        {
-                .name   = "AT91 NAND partition 5, ext-fs",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = SZ_32M
-        }
-};
-static struct atmel_nand_data __initdata yl9200_nand_data = {
-        .ale            = 6,
-        .cle            = 7,
-        .det_pin        = -EINVAL,
-        .rdy_pin        = AT91_PIN_PC14,        /* R/!B (Sheet10) */
-        .enable_pin     = AT91_PIN_PC15,        /* !CE  (Sheet10) */
-        .ecc_mode       = NAND_ECC_SOFT,
-        .parts          = yl9200_nand_partition,
-        .num_parts      = ARRAY_SIZE(yl9200_nand_partition),
-};
-/*
- * NOR Flash
- */
-#define YL9200_FLASH_BASE       AT91_CHIPSELECT_0
-#define YL9200_FLASH_SIZE       SZ_16M
-static struct mtd_partition yl9200_flash_partitions[] = {
-        {
-                .name           = "Bootloader",
-                .offset         = 0,
-                .size           = SZ_256K,
-                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
-        },
-        {
-                .name           = "Kernel",
-                .offset         = MTDPART_OFS_NXTBLK,
-                .size           = (2 * SZ_1M) - SZ_256K
-        },
-        {
-                .name           = "Filesystem",
-                .offset         = MTDPART_OFS_NXTBLK,
-                .size           = MTDPART_SIZ_FULL
-        }
-};
-static struct physmap_flash_data yl9200_flash_data = {
-        .width          = 2,
-        .parts          = yl9200_flash_partitions,
-        .nr_parts       = ARRAY_SIZE(yl9200_flash_partitions),
-};
-static struct resource yl9200_flash_resources[] = {
-        {
-                .start  = YL9200_FLASH_BASE,
-                .end    = YL9200_FLASH_BASE + YL9200_FLASH_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-static struct platform_device yl9200_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                                .platform_data  = &yl9200_flash_data,
-                        },
-        .resource       = yl9200_flash_resources,
-        .num_resources  = ARRAY_SIZE(yl9200_flash_resources),
-};
-/*
- * I2C (TWI)
- */
-static struct i2c_board_info __initdata yl9200_i2c_devices[] = {
-        {       /* EEPROM */
-                I2C_BOARD_INFO("24c128", 0x50),
-        }
-};
-/*
- * GPIO Buttons
-*/
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button yl9200_buttons[] = {
-        {
-                .gpio           = AT91_PIN_PA24,
-                .code           = BTN_2,
-                .desc           = "SW2",
-                .active_low     = 1,
-                .wakeup         = 1,
-        },
-        {
-                .gpio           = AT91_PIN_PB1,
-                .code           = BTN_3,
-                .desc           = "SW3",
-                .active_low     = 1,
-                .wakeup         = 1,
-        },
-        {
-                .gpio           = AT91_PIN_PB2,
-                .code           = BTN_4,
-                .desc           = "SW4",
-                .active_low     = 1,
-                .wakeup         = 1,
-        },
-        {
-                .gpio           = AT91_PIN_PB6,
-                .code           = BTN_5,
-                .desc           = "SW5",
-                .active_low     = 1,
-                .wakeup         = 1,
-        }
-};
-static struct gpio_keys_platform_data yl9200_button_data = {
-        .buttons        = yl9200_buttons,
-        .nbuttons       = ARRAY_SIZE(yl9200_buttons),
-};
-static struct platform_device yl9200_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &yl9200_button_data,
-        }
-};
-static void __init yl9200_add_device_buttons(void)
-{
-        at91_set_gpio_input(AT91_PIN_PA24, 1);  /* SW2 */
-        at91_set_deglitch(AT91_PIN_PA24, 1);
-        at91_set_gpio_input(AT91_PIN_PB1, 1);   /* SW3 */
-        at91_set_deglitch(AT91_PIN_PB1, 1);
-        at91_set_gpio_input(AT91_PIN_PB2, 1);   /* SW4 */
-        at91_set_deglitch(AT91_PIN_PB2, 1);
-        at91_set_gpio_input(AT91_PIN_PB6, 1);   /* SW5 */
-        at91_set_deglitch(AT91_PIN_PB6, 1);
-        /* Enable buttons (Sheet 5) */
-        at91_set_gpio_output(AT91_PIN_PB7, 1);
-        platform_device_register(&yl9200_button_device);
-}
-#else
-static void __init yl9200_add_device_buttons(void) {}
-#endif
-/*
- * Touchscreen
- */
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-static int ads7843_pendown_state(void)
-{
-        return !at91_get_gpio_value(AT91_PIN_PB11);     /* Touchscreen PENIRQ */
-}
-static struct ads7846_platform_data ads_info = {
-        .model                  = 7843,
-        .x_min                  = 150,
-        .x_max                  = 3830,
-        .y_min                  = 190,
-        .y_max                  = 3830,
-        .vref_delay_usecs       = 100,
-        /* For a 8" touch-screen */
-        // .x_plate_ohms                = 603,
-        // .y_plate_ohms                = 332,
-        /* For a 10.4" touch-screen */
-        // .x_plate_ohms                = 611,
-        // .y_plate_ohms                = 325,
-        .x_plate_ohms           = 576,
-        .y_plate_ohms           = 366,
-        .pressure_max           = 15000, /* generally nonsense on the 7843 */
-        .debounce_max           = 1,
-        .debounce_rep           = 0,
-        .debounce_tol           = (~0),
-        .get_pendown_state      = ads7843_pendown_state,
-};
-static void __init yl9200_add_device_ts(void)
-{
-        at91_set_gpio_input(AT91_PIN_PB11, 1);  /* Touchscreen interrupt pin */
-        at91_set_gpio_input(AT91_PIN_PB10, 1);  /* Touchscreen BUSY signal - not used! */
-}
-#else
-static void __init yl9200_add_device_ts(void) {}
-#endif
-/*
- * SPI devices
- */
-static struct spi_board_info yl9200_spi_devices[] = {
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-        {       /* Touchscreen */
-                .modalias       = "ads7846",
-                .chip_select    = 0,
-                .max_speed_hz   = 5000 * 26,
-                .platform_data  = &ads_info,
-                .irq            = AT91_PIN_PB11,
-        },
-#endif
-        {       /* CAN */
-                .modalias       = "mcp2510",
-                .chip_select    = 1,
-                .max_speed_hz   = 25000 * 26,
-                .irq            = AT91_PIN_PC0,
-        }
-};
-/*
- * LCD / VGA
- *
- * EPSON S1D13806 FB (discontinued chip)
- * EPSON S1D13506 FB
- */
-#if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
-#include <video/s1d13xxxfb.h>
-static void yl9200_init_video(void)
-{
-        /* NWAIT Signal */
-        at91_set_A_periph(AT91_PIN_PC6, 0);
-        /* Initialization of the Static Memory Controller for Chip Select 2 */
-        at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16             /* 16 bit */
-                        | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4)    /* wait states */
-                        | AT91_SMC_TDF_(0x100)                  /* float time */
-        );
-}
-static struct s1d13xxxfb_regval yl9200_s1dfb_initregs[] =
-{
-        {S1DREG_MISC,                   0x00},  /* Miscellaneous Register*/
-        {S1DREG_COM_DISP_MODE,          0x01},  /* Display Mode Register, LCD only*/
-        {S1DREG_GPIO_CNF0,              0x00},  /* General IO Pins Configuration Register*/
-        {S1DREG_GPIO_CTL0,              0x00},  /* General IO Pins Control Register*/
-        {S1DREG_CLK_CNF,                0x11},  /* Memory Clock Configuration Register*/
-        {S1DREG_LCD_CLK_CNF,            0x10},  /* LCD Pixel Clock Configuration Register*/
-        {S1DREG_CRT_CLK_CNF,            0x12},  /* CRT/TV Pixel Clock Configuration Register*/
-        {S1DREG_MPLUG_CLK_CNF,          0x01},  /* MediaPlug Clock Configuration Register*/
-        {S1DREG_CPU2MEM_WST_SEL,        0x02},  /* CPU To Memory Wait State Select Register*/
-        {S1DREG_MEM_CNF,                0x00},  /* Memory Configuration Register*/
-        {S1DREG_SDRAM_REF_RATE,         0x04},  /* DRAM Refresh Rate Register, MCLK source*/
-        {S1DREG_SDRAM_TC0,              0x12},  /* DRAM Timings Control Register 0*/
-        {S1DREG_SDRAM_TC1,              0x02},  /* DRAM Timings Control Register 1*/
-        {S1DREG_PANEL_TYPE,             0x25},  /* Panel Type Register*/
-        {S1DREG_MOD_RATE,               0x00},  /* MOD Rate Register*/
-        {S1DREG_LCD_DISP_HWIDTH,        0x4F},  /* LCD Horizontal Display Width Register*/
-        {S1DREG_LCD_NDISP_HPER,         0x13},  /* LCD Horizontal Non-Display Period Register*/
-        {S1DREG_TFT_FPLINE_START,       0x01},  /* TFT FPLINE Start Position Register*/
-        {S1DREG_TFT_FPLINE_PWIDTH,      0x0c},  /* TFT FPLINE Pulse Width Register*/
-        {S1DREG_LCD_DISP_VHEIGHT0,      0xDF},  /* LCD Vertical Display Height Register 0*/
-        {S1DREG_LCD_DISP_VHEIGHT1,      0x01},  /* LCD Vertical Display Height Register 1*/
-        {S1DREG_LCD_NDISP_VPER,         0x2c},  /* LCD Vertical Non-Display Period Register*/
-        {S1DREG_TFT_FPFRAME_START,      0x0a},  /* TFT FPFRAME Start Position Register*/
-        {S1DREG_TFT_FPFRAME_PWIDTH,     0x02},  /* TFT FPFRAME Pulse Width Register*/
-        {S1DREG_LCD_DISP_MODE,          0x05},  /* LCD Display Mode Register*/
-        {S1DREG_LCD_MISC,               0x01},  /* LCD Miscellaneous Register*/
-        {S1DREG_LCD_DISP_START0,        0x00},  /* LCD Display Start Address Register 0*/
-        {S1DREG_LCD_DISP_START1,        0x00},  /* LCD Display Start Address Register 1*/
-        {S1DREG_LCD_DISP_START2,        0x00},  /* LCD Display Start Address Register 2*/
-        {S1DREG_LCD_MEM_OFF0,           0x80},  /* LCD Memory Address Offset Register 0*/
-        {S1DREG_LCD_MEM_OFF1,           0x02},  /* LCD Memory Address Offset Register 1*/
-        {S1DREG_LCD_PIX_PAN,            0x03},  /* LCD Pixel Panning Register*/
-        {S1DREG_LCD_DISP_FIFO_HTC,      0x00},  /* LCD Display FIFO High Threshold Control Register*/
-        {S1DREG_LCD_DISP_FIFO_LTC,      0x00},  /* LCD Display FIFO Low Threshold Control Register*/
-        {S1DREG_CRT_DISP_HWIDTH,        0x4F},  /* CRT/TV Horizontal Display Width Register*/
-        {S1DREG_CRT_NDISP_HPER,         0x13},  /* CRT/TV Horizontal Non-Display Period Register*/
-        {S1DREG_CRT_HRTC_START,         0x01},  /* CRT/TV HRTC Start Position Register*/
-        {S1DREG_CRT_HRTC_PWIDTH,        0x0B},  /* CRT/TV HRTC Pulse Width Register*/
-        {S1DREG_CRT_DISP_VHEIGHT0,      0xDF},  /* CRT/TV Vertical Display Height Register 0*/
-        {S1DREG_CRT_DISP_VHEIGHT1,      0x01},  /* CRT/TV Vertical Display Height Register 1*/
-        {S1DREG_CRT_NDISP_VPER,         0x2B},  /* CRT/TV Vertical Non-Display Period Register*/
-        {S1DREG_CRT_VRTC_START,         0x09},  /* CRT/TV VRTC Start Position Register*/
-        {S1DREG_CRT_VRTC_PWIDTH,        0x01},  /* CRT/TV VRTC Pulse Width Register*/
-        {S1DREG_TV_OUT_CTL,             0x18},  /* TV Output Control Register */
-        {S1DREG_CRT_DISP_MODE,          0x05},  /* CRT/TV Display Mode Register, 16BPP*/
-        {S1DREG_CRT_DISP_START0,        0x00},  /* CRT/TV Display Start Address Register 0*/
-        {S1DREG_CRT_DISP_START1,        0x00},  /* CRT/TV Display Start Address Register 1*/
-        {S1DREG_CRT_DISP_START2,        0x00},  /* CRT/TV Display Start Address Register 2*/
-        {S1DREG_CRT_MEM_OFF0,           0x80},  /* CRT/TV Memory Address Offset Register 0*/
-        {S1DREG_CRT_MEM_OFF1,           0x02},  /* CRT/TV Memory Address Offset Register 1*/
-        {S1DREG_CRT_PIX_PAN,            0x00},  /* CRT/TV Pixel Panning Register*/
-        {S1DREG_CRT_DISP_FIFO_HTC,      0x00},  /* CRT/TV Display FIFO High Threshold Control Register*/
-        {S1DREG_CRT_DISP_FIFO_LTC,      0x00},  /* CRT/TV Display FIFO Low Threshold Control Register*/
-        {S1DREG_LCD_CUR_CTL,            0x00},  /* LCD Ink/Cursor Control Register*/
-        {S1DREG_LCD_CUR_START,          0x01},  /* LCD Ink/Cursor Start Address Register*/
-        {S1DREG_LCD_CUR_XPOS0,          0x00},  /* LCD Cursor X Position Register 0*/
-        {S1DREG_LCD_CUR_XPOS1,          0x00},  /* LCD Cursor X Position Register 1*/
-        {S1DREG_LCD_CUR_YPOS0,          0x00},  /* LCD Cursor Y Position Register 0*/
-        {S1DREG_LCD_CUR_YPOS1,          0x00},  /* LCD Cursor Y Position Register 1*/
-        {S1DREG_LCD_CUR_BCTL0,          0x00},  /* LCD Ink/Cursor Blue Color 0 Register*/
-        {S1DREG_LCD_CUR_GCTL0,          0x00},  /* LCD Ink/Cursor Green Color 0 Register*/
-        {S1DREG_LCD_CUR_RCTL0,          0x00},  /* LCD Ink/Cursor Red Color 0 Register*/
-        {S1DREG_LCD_CUR_BCTL1,          0x1F},  /* LCD Ink/Cursor Blue Color 1 Register*/
-        {S1DREG_LCD_CUR_GCTL1,          0x3F},  /* LCD Ink/Cursor Green Color 1 Register*/
-        {S1DREG_LCD_CUR_RCTL1,          0x1F},  /* LCD Ink/Cursor Red Color 1 Register*/
-        {S1DREG_LCD_CUR_FIFO_HTC,       0x00},  /* LCD Ink/Cursor FIFO Threshold Register*/
-        {S1DREG_CRT_CUR_CTL,            0x00},  /* CRT/TV Ink/Cursor Control Register*/
-        {S1DREG_CRT_CUR_START,          0x01},  /* CRT/TV Ink/Cursor Start Address Register*/
-        {S1DREG_CRT_CUR_XPOS0,          0x00},  /* CRT/TV Cursor X Position Register 0*/
-        {S1DREG_CRT_CUR_XPOS1,          0x00},  /* CRT/TV Cursor X Position Register 1*/
-        {S1DREG_CRT_CUR_YPOS0,          0x00},  /* CRT/TV Cursor Y Position Register 0*/
-        {S1DREG_CRT_CUR_YPOS1,          0x00},  /* CRT/TV Cursor Y Position Register 1*/
-        {S1DREG_CRT_CUR_BCTL0,          0x00},  /* CRT/TV Ink/Cursor Blue Color 0 Register*/
-        {S1DREG_CRT_CUR_GCTL0,          0x00},  /* CRT/TV Ink/Cursor Green Color 0 Register*/
-        {S1DREG_CRT_CUR_RCTL0,          0x00},  /* CRT/TV Ink/Cursor Red Color 0 Register*/
-        {S1DREG_CRT_CUR_BCTL1,          0x1F},  /* CRT/TV Ink/Cursor Blue Color 1 Register*/
-        {S1DREG_CRT_CUR_GCTL1,          0x3F},  /* CRT/TV Ink/Cursor Green Color 1 Register*/
-        {S1DREG_CRT_CUR_RCTL1,          0x1F},  /* CRT/TV Ink/Cursor Red Color 1 Register*/
-        {S1DREG_CRT_CUR_FIFO_HTC,       0x00},  /* CRT/TV Ink/Cursor FIFO Threshold Register*/
-        {S1DREG_BBLT_CTL0,              0x00},  /* BitBlt Control Register 0*/
-        {S1DREG_BBLT_CTL1,              0x01},  /* BitBlt Control Register 1*/
-        {S1DREG_BBLT_CC_EXP,            0x00},  /* BitBlt ROP Code/Color Expansion Register*/
-        {S1DREG_BBLT_OP,                0x00},  /* BitBlt Operation Register*/
-        {S1DREG_BBLT_SRC_START0,        0x00},  /* BitBlt Source Start Address Register 0*/
-        {S1DREG_BBLT_SRC_START1,        0x00},  /* BitBlt Source Start Address Register 1*/
-        {S1DREG_BBLT_SRC_START2,        0x00},  /* BitBlt Source Start Address Register 2*/
-        {S1DREG_BBLT_DST_START0,        0x00},  /* BitBlt Destination Start Address Register 0*/
-        {S1DREG_BBLT_DST_START1,        0x00},  /* BitBlt Destination Start Address Register 1*/
-        {S1DREG_BBLT_DST_START2,        0x00},  /* BitBlt Destination Start Address Register 2*/
-        {S1DREG_BBLT_MEM_OFF0,          0x00},  /* BitBlt Memory Address Offset Register 0*/
-        {S1DREG_BBLT_MEM_OFF1,          0x00},  /* BitBlt Memory Address Offset Register 1*/
-        {S1DREG_BBLT_WIDTH0,            0x00},  /* BitBlt Width Register 0*/
-        {S1DREG_BBLT_WIDTH1,            0x00},  /* BitBlt Width Register 1*/
-        {S1DREG_BBLT_HEIGHT0,           0x00},  /* BitBlt Height Register 0*/
-        {S1DREG_BBLT_HEIGHT1,           0x00},  /* BitBlt Height Register 1*/
-        {S1DREG_BBLT_BGC0,              0x00},  /* BitBlt Background Color Register 0*/
-        {S1DREG_BBLT_BGC1,              0x00},  /* BitBlt Background Color Register 1*/
-        {S1DREG_BBLT_FGC0,              0x00},  /* BitBlt Foreground Color Register 0*/
-        {S1DREG_BBLT_FGC1,              0x00},  /* BitBlt Foreground Color Register 1*/
-        {S1DREG_LKUP_MODE,              0x00},  /* Look-Up Table Mode Register*/
-        {S1DREG_LKUP_ADDR,              0x00},  /* Look-Up Table Address Register*/
-        {S1DREG_PS_CNF,                 0x00},  /* Power Save Configuration Register*/
-        {S1DREG_PS_STATUS,              0x00},  /* Power Save Status Register*/
-        {S1DREG_CPU2MEM_WDOGT,          0x00},  /* CPU-to-Memory Access Watchdog Timer Register*/
-        {S1DREG_COM_DISP_MODE,          0x01},  /* Display Mode Register, LCD only*/
-};
-static struct s1d13xxxfb_pdata yl9200_s1dfb_pdata = {
-        .initregs               = yl9200_s1dfb_initregs,
-        .initregssize           = ARRAY_SIZE(yl9200_s1dfb_initregs),
-        .platform_init_video    = yl9200_init_video,
-};
-#define YL9200_FB_REG_BASE      AT91_CHIPSELECT_7
-#define YL9200_FB_VMEM_BASE     YL9200_FB_REG_BASE + SZ_2M
-#define YL9200_FB_VMEM_SIZE     SZ_2M
-static struct resource yl9200_s1dfb_resource[] = {
-        [0] = { /* video mem */
-                .name   = "s1d13xxxfb memory",
-                .start  = YL9200_FB_VMEM_BASE,
-                .end    = YL9200_FB_VMEM_BASE + YL9200_FB_VMEM_SIZE -1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = { /* video registers */
-                .name   = "s1d13xxxfb registers",
-                .start  = YL9200_FB_REG_BASE,
-                .end    = YL9200_FB_REG_BASE + SZ_512 -1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static u64 s1dfb_dmamask = DMA_BIT_MASK(32);
-static struct platform_device yl9200_s1dfb_device = {
-        .name           = "s1d13806fb",
-        .id             = -1,
-        .dev    = {
-                .dma_mask               = &s1dfb_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data          = &yl9200_s1dfb_pdata,
-        },
-        .resource       = yl9200_s1dfb_resource,
-        .num_resources  = ARRAY_SIZE(yl9200_s1dfb_resource),
-};
-void __init yl9200_add_device_video(void)
-{
-        platform_device_register(&yl9200_s1dfb_device);
-}
-#else
-void __init yl9200_add_device_video(void) {}
-#endif
-static void __init yl9200_board_init(void)
-{
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                        | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                        | ATMEL_UART_RI);
-        /* USART0 on ttyS2. (Rx & Tx only to JP3) */
-        at91_register_uart(AT91RM9200_ID_US0, 2, 0);
-        /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */
-        at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS);
-        at91_add_device_serial();
-        /* Ethernet */
-        at91_add_device_eth(&yl9200_eth_data);
-        /* USB Host */
-        at91_add_device_usbh(&yl9200_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&yl9200_udc_data);
-        /* I2C */
-        at91_add_device_i2c(yl9200_i2c_devices, ARRAY_SIZE(yl9200_i2c_devices));
-        /* MMC */
-        at91_add_device_mci(0, &yl9200_mci0_data);
-        /* NAND */
-        at91_add_device_nand(&yl9200_nand_data);
-        /* NOR Flash */
-        platform_device_register(&yl9200_flash);
-#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
-        /* SPI */
-        at91_add_device_spi(yl9200_spi_devices, ARRAY_SIZE(yl9200_spi_devices));
-        /* Touchscreen */
-        yl9200_add_device_ts();
-#endif
-        /* LEDs. */
-        at91_gpio_leds(yl9200_leds, ARRAY_SIZE(yl9200_leds));
-        /* Push Buttons */
-        yl9200_add_device_buttons();
-        /* VGA */
-        yl9200_add_device_video();
-}
-MACHINE_START(YL9200, "uCdragon YL-9200")
-        /* Maintainer: S.Birtles */
-        .init_time      = at91rm9200_timer_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = yl9200_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = yl9200_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board.h b/arch/arm/mach-at91/board.h
deleted file mode 100644
index 836e9a537e0c..000000000000
--- a/arch/arm/mach-at91/board.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/board.h
- *
- *  Copyright (C) 2005 HP Labs
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/*
- * These are data structures found in platform_device.dev.platform_data,
- * and describing board-specific data needed by drivers.  For example,
- * which pin is used for a given GPIO role.
- *
- * In 2.6, drivers should strongly avoid board-specific knowledge so
- * that supporting new boards normally won't require driver patches.
- * Most board-specific knowledge should be in arch/.../board-*.c files.
- */
-#ifndef __ASM_ARCH_BOARD_H
-#define __ASM_ARCH_BOARD_H
-#include <linux/platform_data/atmel.h>
- /* USB Device */
-extern void __init at91_add_device_udc(struct at91_udc_data *data);
- /* USB High Speed Device */
-extern void __init at91_add_device_usba(struct usba_platform_data *data);
- /* Compact Flash */
-extern void __init at91_add_device_cf(struct at91_cf_data *data);
- /* MMC / SD */
-  /* atmel-mci platform config */
-extern void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data);
-extern void __init at91_add_device_eth(struct macb_platform_data *data);
- /* USB Host */
-extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
-extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data);
-extern void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data);
-extern void __init at91_add_device_nand(struct atmel_nand_data *data);
- /* I2C*/
-#if defined(CONFIG_ARCH_AT91SAM9G45)
-extern void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices);
-#else
-extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices);
-#endif
- /* SPI */
-extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices);
- /* Serial */
-#define ATMEL_UART_CTS  0x01
-#define ATMEL_UART_RTS  0x02
-#define ATMEL_UART_DSR  0x04
-#define ATMEL_UART_DTR  0x08
-#define ATMEL_UART_DCD  0x10
-#define ATMEL_UART_RI   0x20
-extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins);
-extern struct platform_device *atmel_default_console_device;
-extern void __init at91_add_device_serial(void);
-/*
- * PWM
- */
-#define AT91_PWM0       0
-#define AT91_PWM1       1
-#define AT91_PWM2       2
-#define AT91_PWM3       3
-extern void __init at91_add_device_pwm(u32 mask);
-/*
- * SSC -- accessed through ssc_request(id).  Drivers don't bind to SSC
- * platform devices.  Their SSC ID is part of their configuration data,
- * along with information about which SSC signals they should use.
- */
-#define ATMEL_SSC_TK    0x01
-#define ATMEL_SSC_TF    0x02
-#define ATMEL_SSC_TD    0x04
-#define ATMEL_SSC_TX    (ATMEL_SSC_TK | ATMEL_SSC_TF | ATMEL_SSC_TD)
-#define ATMEL_SSC_RK    0x10
-#define ATMEL_SSC_RF    0x20
-#define ATMEL_SSC_RD    0x40
-#define ATMEL_SSC_RX    (ATMEL_SSC_RK | ATMEL_SSC_RF | ATMEL_SSC_RD)
-extern void __init at91_add_device_ssc(unsigned id, unsigned pins);
- /* LCD Controller */
-struct atmel_lcdfb_pdata;
-extern void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data);
- /* AC97 */
-extern void __init at91_add_device_ac97(struct ac97c_platform_data *data);
- /* ISI */
-struct isi_platform_data;
-extern void __init at91_add_device_isi(struct isi_platform_data *data,
-                bool use_pck_as_mck);
-/* CAN */
-extern void __init at91_add_device_can(struct at91_can_data *data);
- /* LEDs */
-extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
-#endif
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
deleted file mode 100644
index d66f102c352a..000000000000
--- a/arch/arm/mach-at91/clock.c
+++ /dev/null
@@ -1,977 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/clock.c
- *
- * Copyright (C) 2005 David Brownell
- * Copyright (C) 2005 Ivan Kokshaysky
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/fs.h>
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/spinlock.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/of_address.h>
-#include <linux/clk/at91_pmc.h>
-#include <mach/hardware.h>
-#include <mach/cpu.h>
-#include <asm/proc-fns.h>
-#include "clock.h"
-#include "generic.h"
-void __iomem *at91_pmc_base;
-EXPORT_SYMBOL_GPL(at91_pmc_base);
-/*
- * There's a lot more which can be done with clocks, including cpufreq
- * integration, slow clock mode support (for system suspend), letting
- * PLLB be used at other rates (on boards that don't need USB), etc.
- */
-#define clk_is_primary(x)       ((x)->type & CLK_TYPE_PRIMARY)
-#define clk_is_programmable(x)  ((x)->type & CLK_TYPE_PROGRAMMABLE)
-#define clk_is_peripheral(x)    ((x)->type & CLK_TYPE_PERIPHERAL)
-#define clk_is_sys(x)           ((x)->type & CLK_TYPE_SYSTEM)
-/*
- * Chips have some kind of clocks : group them by functionality
- */
-#define cpu_has_utmi()          (  cpu_is_at91sam9rl() \
-                                || cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5() \
-                                || cpu_is_sama5d3())
-#define cpu_has_1056M_plla()    (cpu_is_sama5d3())
-#define cpu_has_800M_plla()     (  cpu_is_at91sam9g20() \
-                                || cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5() \
-                                || cpu_is_at91sam9n12())
-#define cpu_has_300M_plla()     (cpu_is_at91sam9g10())
-#define cpu_has_240M_plla()     (cpu_is_at91sam9261() \
-                                || cpu_is_at91sam9263() \
-                                || cpu_is_at91sam9rl())
-#define cpu_has_210M_plla()     (cpu_is_at91sam9260())
-#define cpu_has_pllb()          (!(cpu_is_at91sam9rl() \
-                                || cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5() \
-                                || cpu_is_sama5d3()))
-#define cpu_has_upll()          (cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5() \
-                                || cpu_is_sama5d3())
-/* USB host HS & FS */
-#define cpu_has_uhp()           (!cpu_is_at91sam9rl())
-/* USB device FS only */
-#define cpu_has_udpfs()         (!(cpu_is_at91sam9rl() \
-                                || cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5() \
-                                || cpu_is_sama5d3()))
-#define cpu_has_plladiv2()      (cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5() \
-                                || cpu_is_at91sam9n12() \
-                                || cpu_is_sama5d3())
-#define cpu_has_mdiv3()         (cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5() \
-                                || cpu_is_at91sam9n12() \
-                                || cpu_is_sama5d3())
-#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \
-                                || cpu_is_at91sam9n12() \
-                                || cpu_is_sama5d3())
-static LIST_HEAD(clocks);
-static DEFINE_SPINLOCK(clk_lock);
-static u32 at91_pllb_usb_init;
-/*
- * Four primary clock sources:  two crystal oscillators (32K, main), and
- * two PLLs.  PLLA usually runs the master clock; and PLLB must run at
- * 48 MHz (unless no USB function clocks are needed).  The main clock and
- * both PLLs are turned off to run in "slow clock mode" (system suspend).
- */
-static struct clk clk32k = {
-        .name           = "clk32k",
-        .rate_hz        = AT91_SLOW_CLOCK,
-        .users          = 1,            /* always on */
-        .id             = 0,
-        .type           = CLK_TYPE_PRIMARY,
-};
-static struct clk main_clk = {
-        .name           = "main",
-        .pmc_mask       = AT91_PMC_MOSCS,       /* in PMC_SR */
-        .id             = 1,
-        .type           = CLK_TYPE_PRIMARY,
-};
-static struct clk plla = {
-        .name           = "plla",
-        .parent         = &main_clk,
-        .pmc_mask       = AT91_PMC_LOCKA,       /* in PMC_SR */
-        .id             = 2,
-        .type           = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
-};
-static void pllb_mode(struct clk *clk, int is_on)
-{
-        u32     value;
-        if (is_on) {
-                is_on = AT91_PMC_LOCKB;
-                value = at91_pllb_usb_init;
-        } else
-                value = 0;
-        // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
-        at91_pmc_write(AT91_CKGR_PLLBR, value);
-        do {
-                cpu_relax();
-        } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
-}
-static struct clk pllb = {
-        .name           = "pllb",
-        .parent         = &main_clk,
-        .pmc_mask       = AT91_PMC_LOCKB,       /* in PMC_SR */
-        .mode           = pllb_mode,
-        .id             = 3,
-        .type           = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
-};
-static void pmc_sys_mode(struct clk *clk, int is_on)
-{
-        if (is_on)
-                at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
-        else
-                at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
-}
-static void pmc_uckr_mode(struct clk *clk, int is_on)
-{
-        unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
-        if (is_on) {
-                is_on = AT91_PMC_LOCKU;
-                at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
-        } else
-                at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
-        do {
-                cpu_relax();
-        } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
-}
-/* USB function clocks (PLLB must be 48 MHz) */
-static struct clk udpck = {
-        .name           = "udpck",
-        .parent         = &pllb,
-        .mode           = pmc_sys_mode,
-};
-struct clk utmi_clk = {
-        .name           = "utmi_clk",
-        .parent         = &main_clk,
-        .pmc_mask       = AT91_PMC_UPLLEN,      /* in CKGR_UCKR */
-        .mode           = pmc_uckr_mode,
-        .type           = CLK_TYPE_PLL,
-};
-static struct clk uhpck = {
-        .name           = "uhpck",
-        /*.parent               = ... we choose parent at runtime */
-        .mode           = pmc_sys_mode,
-};
-/*
- * The master clock is divided from the CPU clock (by 1-4).  It's used for
- * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
- * (e.g baud rate generation).  It's sourced from one of the primary clocks.
- */
-struct clk mck = {
-        .name           = "mck",
-        .pmc_mask       = AT91_PMC_MCKRDY,      /* in PMC_SR */
-};
-static void pmc_periph_mode(struct clk *clk, int is_on)
-{
-        u32 regval = 0;
-        /*
-         * With sama5d3 devices, we are managing clock division so we have to
-         * use the Peripheral Control Register introduced from at91sam9x5
-         * devices.
-         */
-        if (cpu_is_sama5d3()) {
-                regval |= AT91_PMC_PCR_CMD; /* write command */
-                regval |= clk->pid & AT91_PMC_PCR_PID; /* peripheral selection */
-                regval |= AT91_PMC_PCR_DIV(clk->div);
-                if (is_on)
-                        regval |= AT91_PMC_PCR_EN; /* enable clock */
-                at91_pmc_write(AT91_PMC_PCR, regval);
-        } else {
-                if (is_on)
-                        at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
-                else
-                        at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
-        }
-}
-static struct clk __init *at91_css_to_clk(unsigned long css)
-{
-        switch (css) {
-                case AT91_PMC_CSS_SLOW:
-                        return &clk32k;
-                case AT91_PMC_CSS_MAIN:
-                        return &main_clk;
-                case AT91_PMC_CSS_PLLA:
-                        return &plla;
-                case AT91_PMC_CSS_PLLB:
-                        if (cpu_has_upll())
-                                /* CSS_PLLB == CSS_UPLL */
-                                return &utmi_clk;
-                        else if (cpu_has_pllb())
-                                return &pllb;
-                        break;
-                /* alternate PMC: can use master clock */
-                case AT91_PMC_CSS_MASTER:
-                        return &mck;
-        }
-        return NULL;
-}
-static int pmc_prescaler_divider(u32 reg)
-{
-        if (cpu_has_alt_prescaler()) {
-                return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
-        } else {
-                return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
-        }
-}
-static void __clk_enable(struct clk *clk)
-{
-        if (clk->parent)
-                __clk_enable(clk->parent);
-        if (clk->users++ == 0 && clk->mode)
-                clk->mode(clk, 1);
-}
-int clk_enable(struct clk *clk)
-{
-        unsigned long   flags;
-        spin_lock_irqsave(&clk_lock, flags);
-        __clk_enable(clk);
-        spin_unlock_irqrestore(&clk_lock, flags);
-        return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-static void __clk_disable(struct clk *clk)
-{
-        BUG_ON(clk->users == 0);
-        if (--clk->users == 0 && clk->mode)
-                clk->mode(clk, 0);
-        if (clk->parent)
-                __clk_disable(clk->parent);
-}
-void clk_disable(struct clk *clk)
-{
-        unsigned long   flags;
-        spin_lock_irqsave(&clk_lock, flags);
-        __clk_disable(clk);
-        spin_unlock_irqrestore(&clk_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-unsigned long clk_get_rate(struct clk *clk)
-{
-        unsigned long   flags;
-        unsigned long   rate;
-        spin_lock_irqsave(&clk_lock, flags);
-        for (;;) {
-                rate = clk->rate_hz;
-                if (rate || !clk->parent)
-                        break;
-                clk = clk->parent;
-        }
-        spin_unlock_irqrestore(&clk_lock, flags);
-        return rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-/*------------------------------------------------------------------------*/
-/*
- * For now, only the programmable clocks support reparenting (MCK could
- * do this too, with care) or rate changing (the PLLs could do this too,
- * ditto MCK but that's more for cpufreq).  Drivers may reparent to get
- * a better rate match; we don't.
- */
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long   flags;
-        unsigned        prescale;
-        unsigned long   actual;
-        unsigned long   prev = ULONG_MAX;
-        if (!clk_is_programmable(clk))
-                return -EINVAL;
-        spin_lock_irqsave(&clk_lock, flags);
-        actual = clk->parent->rate_hz;
-        for (prescale = 0; prescale < 7; prescale++) {
-                if (actual > rate)
-                        prev = actual;
-                if (actual && actual <= rate) {
-                        if ((prev - rate) < (rate - actual)) {
-                                actual = prev;
-                                prescale--;
-                        }
-                        break;
-                }
-                actual >>= 1;
-        }
-        spin_unlock_irqrestore(&clk_lock, flags);
-        return (prescale < 7) ? actual : -ENOENT;
-}
-EXPORT_SYMBOL(clk_round_rate);
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long   flags;
-        unsigned        prescale;
-        unsigned long   prescale_offset, css_mask;
-        unsigned long   actual;
-        if (!clk_is_programmable(clk))
-                return -EINVAL;
-        if (clk->users)
-                return -EBUSY;
-        if (cpu_has_alt_prescaler()) {
-                prescale_offset = PMC_ALT_PRES_OFFSET;
-                css_mask = AT91_PMC_ALT_PCKR_CSS;
-        } else {
-                prescale_offset = PMC_PRES_OFFSET;
-                css_mask = AT91_PMC_CSS;
-        }
-        spin_lock_irqsave(&clk_lock, flags);
-        actual = clk->parent->rate_hz;
-        for (prescale = 0; prescale < 7; prescale++) {
-                if (actual && actual <= rate) {
-                        u32     pckr;
-                        pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
-                        pckr &= css_mask;       /* keep clock selection */
-                        pckr |= prescale << prescale_offset;
-                        at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
-                        clk->rate_hz = actual;
-                        break;
-                }
-                actual >>= 1;
-        }
-        spin_unlock_irqrestore(&clk_lock, flags);
-        return (prescale < 7) ? actual : -ENOENT;
-}
-EXPORT_SYMBOL(clk_set_rate);
-struct clk *clk_get_parent(struct clk *clk)
-{
-        return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        unsigned long   flags;
-        if (clk->users)
-                return -EBUSY;
-        if (!clk_is_primary(parent) || !clk_is_programmable(clk))
-                return -EINVAL;
-        if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
-                return -EINVAL;
-        spin_lock_irqsave(&clk_lock, flags);
-        clk->rate_hz = parent->rate_hz;
-        clk->parent = parent;
-        at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
-        spin_unlock_irqrestore(&clk_lock, flags);
-        return 0;
-}
-EXPORT_SYMBOL(clk_set_parent);
-/* establish PCK0..PCKN parentage and rate */
-static void __init init_programmable_clock(struct clk *clk)
-{
-        struct clk      *parent;
-        u32             pckr;
-        unsigned int    css_mask;
-        if (cpu_has_alt_prescaler())
-                css_mask = AT91_PMC_ALT_PCKR_CSS;
-        else
-                css_mask = AT91_PMC_CSS;
-        pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
-        parent = at91_css_to_clk(pckr & css_mask);
-        clk->parent = parent;
-        clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
-}
-/*------------------------------------------------------------------------*/
-#ifdef CONFIG_DEBUG_FS
-static int at91_clk_show(struct seq_file *s, void *unused)
-{
-        u32             scsr, pcsr, pcsr1 = 0, uckr = 0, sr;
-        struct clk      *clk;
-        scsr = at91_pmc_read(AT91_PMC_SCSR);
-        pcsr = at91_pmc_read(AT91_PMC_PCSR);
-        if (cpu_is_sama5d3())
-                pcsr1 = at91_pmc_read(AT91_PMC_PCSR1);
-        sr = at91_pmc_read(AT91_PMC_SR);
-        seq_printf(s, "SCSR = %8x\n", scsr);
-        seq_printf(s, "PCSR = %8x\n", pcsr);
-        if (cpu_is_sama5d3())
-                seq_printf(s, "PCSR1 = %8x\n", pcsr1);
-        seq_printf(s, "MOR  = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
-        seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
-        seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
-        if (cpu_has_pllb())
-                seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
-        if (cpu_has_utmi()) {
-                uckr = at91_pmc_read(AT91_CKGR_UCKR);
-                seq_printf(s, "UCKR = %8x\n", uckr);
-        }
-        seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
-        if (cpu_has_upll() || cpu_is_at91sam9n12())
-                seq_printf(s, "USB  = %8x\n", at91_pmc_read(AT91_PMC_USB));
-        seq_printf(s, "SR   = %8x\n", sr);
-        seq_printf(s, "\n");
-        list_for_each_entry(clk, &clocks, node) {
-                char    *state;
-                if (clk->mode == pmc_sys_mode) {
-                        state = (scsr & clk->pmc_mask) ? "on" : "off";
-                } else if (clk->mode == pmc_periph_mode) {
-                        if (cpu_is_sama5d3()) {
-                                u32 pmc_mask = 1 << (clk->pid % 32);
-                                if (clk->pid > 31)
-                                        state = (pcsr1 & pmc_mask) ? "on" : "off";
-                                else
-                                        state = (pcsr & pmc_mask) ? "on" : "off";
-                        } else {
-                                state = (pcsr & clk->pmc_mask) ? "on" : "off";
-                        }
-                } else if (clk->mode == pmc_uckr_mode) {
-                        state = (uckr & clk->pmc_mask) ? "on" : "off";
-                } else if (clk->pmc_mask) {
-                        state = (sr & clk->pmc_mask) ? "on" : "off";
-                } else if (clk == &clk32k || clk == &main_clk) {
-                        state = "on";
-                } else {
-                        state = "";
-                }
-                seq_printf(s, "%-10s users=%2d %-3s %9lu Hz %s\n",
-                        clk->name, clk->users, state, clk_get_rate(clk),
-                        clk->parent ? clk->parent->name : "");
-        }
-        return 0;
-}
-static int at91_clk_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, at91_clk_show, NULL);
-}
-static const struct file_operations at91_clk_operations = {
-        .open           = at91_clk_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-static int __init at91_clk_debugfs_init(void)
-{
-        /* /sys/kernel/debug/at91_clk */
-        (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
-        return 0;
-}
-postcore_initcall(at91_clk_debugfs_init);
-#endif
-/*------------------------------------------------------------------------*/
-/* Register a new clock */
-static void __init at91_clk_add(struct clk *clk)
-{
-        list_add_tail(&clk->node, &clocks);
-        clk->cl.con_id = clk->name;
-        clk->cl.clk = clk;
-        clkdev_add(&clk->cl);
-}
-int __init clk_register(struct clk *clk)
-{
-        if (clk_is_peripheral(clk)) {
-                if (!clk->parent)
-                        clk->parent = &mck;
-                if (cpu_is_sama5d3())
-                        clk->rate_hz = DIV_ROUND_UP(clk->parent->rate_hz,
-                                                    1 << clk->div);
-                clk->mode = pmc_periph_mode;
-        }
-        else if (clk_is_sys(clk)) {
-                clk->parent = &mck;
-                clk->mode = pmc_sys_mode;
-        }
-        else if (clk_is_programmable(clk)) {
-                clk->mode = pmc_sys_mode;
-                init_programmable_clock(clk);
-        }
-        at91_clk_add(clk);
-        return 0;
-}
-/*------------------------------------------------------------------------*/
-static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
-{
-        unsigned mul, div;
-        div = reg & 0xff;
-        if (cpu_is_sama5d3())
-                mul = AT91_PMC3_MUL_GET(reg);
-        else
-                mul = AT91_PMC_MUL_GET(reg);
-        if (div && mul) {
-                freq /= div;
-                freq *= mul + 1;
-        } else
-                freq = 0;
-        return freq;
-}
-static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
-{
-        if (pll == &pllb && (reg & AT91_PMC_USB96M))
-                return freq / 2;
-        else if (pll == &utmi_clk || cpu_is_at91sam9n12())
-                return freq / (1 + ((reg & AT91_PMC_OHCIUSBDIV) >> 8));
-        else
-                return freq;
-}
-static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
-{
-        unsigned i, div = 0, mul = 0, diff = 1 << 30;
-        unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
-        /* PLL output max 240 MHz (or 180 MHz per errata) */
-        if (out_freq > 240000000)
-                goto fail;
-        for (i = 1; i < 256; i++) {
-                int diff1;
-                unsigned input, mul1;
-                /*
-                 * PLL input between 1MHz and 32MHz per spec, but lower
-                 * frequences seem necessary in some cases so allow 100K.
-                 * Warning: some newer products need 2MHz min.
-                 */
-                input = main_freq / i;
-                if (cpu_is_at91sam9g20() && input < 2000000)
-                        continue;
-                if (input < 100000)
-                        continue;
-                if (input > 32000000)
-                        continue;
-                mul1 = out_freq / input;
-                if (cpu_is_at91sam9g20() && mul > 63)
-                        continue;
-                if (mul1 > 2048)
-                        continue;
-                if (mul1 < 2)
-                        goto fail;
-                diff1 = out_freq - input * mul1;
-                if (diff1 < 0)
-                        diff1 = -diff1;
-                if (diff > diff1) {
-                        diff = diff1;
-                        div = i;
-                        mul = mul1;
-                        if (diff == 0)
-                                break;
-                }
-        }
-        if (i == 256 && diff > (out_freq >> 5))
-                goto fail;
-        return ret | ((mul - 1) << 16) | div;
-fail:
-        return 0;
-}
-static struct clk *const standard_pmc_clocks[] __initconst = {
-        /* four primary clocks */
-        &clk32k,
-        &main_clk,
-        &plla,
-        /* MCK */
-        &mck
-};
-/* PLLB generated USB full speed clock init */
-static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
-{
-        unsigned int reg;
-        /*
-         * USB clock init:  choose 48 MHz PLLB value,
-         * disable 48MHz clock during usb peripheral suspend.
-         *
-         * REVISIT:  assumes MCK doesn't derive from PLLB!
-         */
-        uhpck.parent = &pllb;
-        reg = at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2);
-        pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
-        if (cpu_is_at91rm9200()) {
-                reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
-                uhpck.pmc_mask = AT91RM9200_PMC_UHP;
-                udpck.pmc_mask = AT91RM9200_PMC_UDP;
-                at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
-        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
-                   cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
-                   cpu_is_at91sam9g10()) {
-                reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
-                uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
-                udpck.pmc_mask = AT91SAM926x_PMC_UDP;
-        } else if (cpu_is_at91sam9n12()) {
-                /* Divider for USB clock is in USB clock register for 9n12 */
-                reg = AT91_PMC_USBS_PLLB;
-                /* For PLLB output 96M, set usb divider 2 (USBDIV + 1) */
-                reg |= AT91_PMC_OHCIUSBDIV_2;
-                at91_pmc_write(AT91_PMC_USB, reg);
-                /* Still setup masks */
-                uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
-                udpck.pmc_mask = AT91SAM926x_PMC_UDP;
-        }
-        at91_pmc_write(AT91_CKGR_PLLBR, 0);
-        udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
-        uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
-}
-/* UPLL generated USB full speed clock init */
-static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
-{
-        /*
-         * USB clock init: choose 480 MHz from UPLL,
-         */
-        unsigned int usbr = AT91_PMC_USBS_UPLL;
-        /* Setup divider by 10 to reach 48 MHz */
-        usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
-        at91_pmc_write(AT91_PMC_USB, usbr);
-        /* Now set uhpck values */
-        uhpck.parent = &utmi_clk;
-        uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
-        uhpck.rate_hz = at91_usb_rate(&utmi_clk, utmi_clk.rate_hz, usbr);
-}
-static int __init at91_pmc_init(unsigned long main_clock)
-{
-        unsigned tmp, freq, mckr;
-        int i;
-        int pll_overclock = false;
-        /*
-         * When the bootloader initialized the main oscillator correctly,
-         * there's no problem using the cycle counter.  But if it didn't,
-         * or when using oscillator bypass mode, we must be told the speed
-         * of the main clock.
-         */
-        if (!main_clock) {
-                do {
-                        tmp = at91_pmc_read(AT91_CKGR_MCFR);
-                } while (!(tmp & AT91_PMC_MAINRDY));
-                main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
-        }
-        main_clk.rate_hz = main_clock;
-        /* report if PLLA is more than mildly overclocked */
-        plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
-        if (cpu_has_1056M_plla()) {
-                if (plla.rate_hz > 1056000000)
-                        pll_overclock = true;
-        } else if (cpu_has_800M_plla()) {
-                if (plla.rate_hz > 800000000)
-                        pll_overclock = true;
-        } else if (cpu_has_300M_plla()) {
-                if (plla.rate_hz > 300000000)
-                        pll_overclock = true;
-        } else if (cpu_has_240M_plla()) {
-                if (plla.rate_hz > 240000000)
-                        pll_overclock = true;
-        } else if (cpu_has_210M_plla()) {
-                if (plla.rate_hz > 210000000)
-                        pll_overclock = true;
-        } else {
-                if (plla.rate_hz > 209000000)
-                        pll_overclock = true;
-        }
-        if (pll_overclock)
-                pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
-        if (cpu_has_plladiv2()) {
-                mckr = at91_pmc_read(AT91_PMC_MCKR);
-                plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12));      /* plla divisor by 2 */
-        }
-        if (!cpu_has_pllb() && cpu_has_upll()) {
-                /* setup UTMI clock as the fourth primary clock
-                 * (instead of pllb) */
-                utmi_clk.type |= CLK_TYPE_PRIMARY;
-                utmi_clk.id = 3;
-        }
-        /*
-         * USB HS clock init
-         */
-        if (cpu_has_utmi()) {
-                /*
-                 * multiplier is hard-wired to 40
-                 * (obtain the USB High Speed 480 MHz when input is 12 MHz)
-                 */
-                utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
-                /* UTMI bias and PLL are managed at the same time */
-                if (cpu_has_upll())
-                        utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
-        }
-        /*
-         * USB FS clock init
-         */
-        if (cpu_has_pllb())
-                at91_pllb_usbfs_clock_init(main_clock);
-        if (cpu_has_upll())
-                /* assumes that we choose UPLL for USB and not PLLA */
-                at91_upll_usbfs_clock_init(main_clock);
-        /*
-         * MCK and CPU derive from one of those primary clocks.
-         * For now, assume this parentage won't change.
-         */
-        mckr = at91_pmc_read(AT91_PMC_MCKR);
-        mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
-        freq = mck.parent->rate_hz;
-        freq /= pmc_prescaler_divider(mckr);                                    /* prescale */
-        if (cpu_is_at91rm9200()) {
-                mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));       /* mdiv */
-        } else if (cpu_is_at91sam9g20()) {
-                mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
-                        freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;    /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
-                if (mckr & AT91_PMC_PDIV)
-                        freq /= 2;              /* processor clock division */
-        } else if (cpu_has_mdiv3()) {
-                mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
-                        freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
-        } else {
-                mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));              /* mdiv */
-        }
-        if (cpu_has_alt_prescaler()) {
-                /* Programmable clocks can use MCK */
-                mck.type |= CLK_TYPE_PRIMARY;
-                mck.id = 4;
-        }
-        /* Register the PMC's standard clocks */
-        for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
-                at91_clk_add(standard_pmc_clocks[i]);
-        if (cpu_has_pllb())
-                at91_clk_add(&pllb);
-        if (cpu_has_uhp())
-                at91_clk_add(&uhpck);
-        if (cpu_has_udpfs())
-                at91_clk_add(&udpck);
-        if (cpu_has_utmi())
-                at91_clk_add(&utmi_clk);
-        /* MCK and CPU clock are "always on" */
-        clk_enable(&mck);
-        printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
-                freq / 1000000, (unsigned) mck.rate_hz / 1000000,
-                (unsigned) main_clock / 1000000,
-                ((unsigned) main_clock % 1000000) / 1000);
-        return 0;
-}
-#if defined(CONFIG_OF)
-static struct of_device_id pmc_ids[] = {
-        { .compatible = "atmel,at91rm9200-pmc" },
-        { .compatible = "atmel,at91sam9260-pmc" },
-        { .compatible = "atmel,at91sam9g45-pmc" },
-        { .compatible = "atmel,at91sam9n12-pmc" },
-        { .compatible = "atmel,at91sam9x5-pmc" },
-        { .compatible = "atmel,sama5d3-pmc" },
-        { /*sentinel*/ }
-};
-static struct of_device_id osc_ids[] = {
-        { .compatible = "atmel,osc" },
-        { /*sentinel*/ }
-};
-int __init at91_dt_clock_init(void)
-{
-        struct device_node *np;
-        u32 main_clock = 0;
-        np = of_find_matching_node(NULL, pmc_ids);
-        if (!np)
-                panic("unable to find compatible pmc node in dtb\n");
-        at91_pmc_base = of_iomap(np, 0);
-        if (!at91_pmc_base)
-                panic("unable to map pmc cpu registers\n");
-        of_node_put(np);
-        /* retrieve the freqency of fixed clocks from device tree */
-        np = of_find_matching_node(NULL, osc_ids);
-        if (np) {
-                u32 rate;
-                if (!of_property_read_u32(np, "clock-frequency", &rate))
-                        main_clock = rate;
-        }
-        of_node_put(np);
-        return at91_pmc_init(main_clock);
-}
-#endif
-int __init at91_clock_init(unsigned long main_clock)
-{
-        at91_pmc_base = ioremap(AT91_PMC, 256);
-        if (!at91_pmc_base)
-                panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
-        return at91_pmc_init(main_clock);
-}
-/*
- * Several unused clocks may be active.  Turn them off.
- */
-static int __init at91_clock_reset(void)
-{
-        unsigned long pcdr = 0;
-        unsigned long pcdr1 = 0;
-        unsigned long scdr = 0;
-        struct clk *clk;
-        list_for_each_entry(clk, &clocks, node) {
-                if (clk->users > 0)
-                        continue;
-                if (clk->mode == pmc_periph_mode) {
-                        if (cpu_is_sama5d3()) {
-                                u32 pmc_mask = 1 << (clk->pid % 32);
-                                if (clk->pid > 31)
-                                        pcdr1 |= pmc_mask;
-                                else
-                                        pcdr |= pmc_mask;
-                        } else
-                                pcdr |= clk->pmc_mask;
-                }
-                if (clk->mode == pmc_sys_mode)
-                        scdr |= clk->pmc_mask;
-                pr_debug("Clocks: disable unused %s\n", clk->name);
-        }
-        at91_pmc_write(AT91_PMC_SCDR, scdr);
-        at91_pmc_write(AT91_PMC_PCDR, pcdr);
-        if (cpu_is_sama5d3())
-                at91_pmc_write(AT91_PMC_PCDR1, pcdr1);
-        return 0;
-}
-late_initcall(at91_clock_reset);
-void at91sam9_idle(void)
-{
-        at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
-        cpu_do_idle();
-}
diff --git a/arch/arm/mach-at91/clock.h b/arch/arm/mach-at91/clock.h
deleted file mode 100644
index a98a39bbd883..000000000000
--- a/arch/arm/mach-at91/clock.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/clock.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/clkdev.h>
-#define CLK_TYPE_PRIMARY        0x1
-#define CLK_TYPE_PLL            0x2
-#define CLK_TYPE_PROGRAMMABLE   0x4
-#define CLK_TYPE_PERIPHERAL     0x8
-#define CLK_TYPE_SYSTEM         0x10
-struct clk {
-        struct list_head node;
-        const char      *name;          /* unique clock name */
-        struct clk_lookup cl;
-        unsigned long   rate_hz;
-        unsigned        div;            /* parent clock divider */
-        struct clk      *parent;
-        unsigned        pid;            /* peripheral ID */
-        u32             pmc_mask;
-        void            (*mode)(struct clk *, int);
-        unsigned        id:3;           /* PCK0..4, or 32k/main/a/b */
-        unsigned        type;           /* clock type */
-        u16             users;
-};
-extern int __init clk_register(struct clk *clk);
-extern struct clk mck;
-extern struct clk utmi_clk;
-#define CLKDEV_CON_ID(_id, _clk)                        \
-        {                                               \
-                .con_id = _id,                          \
-                .clk = _clk,                            \
-        }
-#define CLKDEV_CON_DEV_ID(_con_id, _dev_id, _clk)       \
-        {                                               \
-                .con_id = _con_id,                      \
-                .dev_id = _dev_id,                      \
-                .clk = _clk,                            \
-        }
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 81959cf4a137..d53324210adf 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -11,7 +11,6 @@
 #ifndef _AT91_GENERIC_H
 #define _AT91_GENERIC_H
-#include <linux/clkdev.h>
 #include <linux/of.h>
 #include <linux/reboot.h>
@@ -23,71 +22,19 @@ extern void __init at91_init_sram(int bank, unsigned long base,
 /* Processors */
 extern void __init at91rm9200_set_type(int type);
-extern void __init at91_initialize(unsigned long main_clock);
-extern void __init at91x40_initialize(unsigned long main_clock);
 extern void __init at91rm9200_dt_initialize(void);
 extern void __init at91_dt_initialize(void);
 /* Interrupts */
-extern void __init at91_init_irq_default(void);
-extern void __init at91_init_interrupts(unsigned int priority[]);
-extern void __init at91x40_init_interrupts(unsigned int priority[]);
-extern void __init at91_aic_init(unsigned int priority[],
-                                 unsigned int ext_irq_mask);
-extern int  __init at91_aic_of_init(struct device_node *node,
-                                    struct device_node *parent);
-extern int  __init at91_aic5_of_init(struct device_node *node,
-                                    struct device_node *parent);
 extern void __init at91_sysirq_mask_rtc(u32 rtc_base);
 extern void __init at91_sysirq_mask_rtt(u32 rtt_base);
- /* Devices */
-extern void __init at91_register_devices(void);
 /* Timer */
-extern void __init at91_init_time(void);
-extern void at91rm9200_ioremap_st(u32 addr);
 extern void at91rm9200_timer_init(void);
-extern void at91sam926x_ioremap_pit(u32 addr);
-extern void at91sam926x_pit_init(int irq);
-extern void at91x40_timer_init(void);
- /* Clocks */
-#ifdef CONFIG_OLD_CLK_AT91
-extern int __init at91_clock_init(unsigned long main_clock);
-extern int __init at91_dt_clock_init(void);
-#else
-static int inline at91_clock_init(unsigned long main_clock) { return 0; }
-static int inline at91_dt_clock_init(void) { return 0; }
-#endif
-struct device;
- /* Power Management */
-extern void at91_irq_suspend(void);
-extern void at91_irq_resume(void);
 /* idle */
 extern void at91sam9_idle(void);
 /* Matrix */
 extern void at91_ioremap_matrix(u32 base_addr);
-/* Ram Controler */
-extern void at91_ioremap_ramc(int id, u32 addr, u32 size);
- /* GPIO */
-#define AT91RM9200_PQFP         3       /* AT91RM9200 PQFP package has 3 banks */
-#define AT91RM9200_BGA          4       /* AT91RM9200 BGA package has 4 banks */
-struct at91_gpio_bank {
-        unsigned short id;              /* peripheral ID */
-        unsigned long regbase;          /* offset from system peripheral base */
-};
-extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks);
-extern void __init at91_gpio_irq_setup(void);
-extern int  __init at91_gpio_of_irq_setup(struct device_node *node,
-                                          struct device_node *parent);
-extern u32 at91_get_extern_irq(void);
 #endif /* _AT91_GENERIC_H */
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
deleted file mode 100644
index d3f05aaad8ba..000000000000
--- a/arch/arm/mach-at91/gpio.c
+++ /dev/null
@@ -1,982 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/gpio.c
- *
- * Copyright (C) 2005 HP Labs
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include <linux/clk.h>
-#include <linux/errno.h>
-#include <linux/device.h>
-#include <linux/gpio.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/irqdomain.h>
-#include <linux/irqchip/chained_irq.h>
-#include <linux/of_address.h>
-#include <mach/hardware.h>
-#include <mach/at91_pio.h>
-#include "generic.h"
-#include "gpio.h"
-#define MAX_NB_GPIO_PER_BANK    32
-struct at91_gpio_chip {
-        struct gpio_chip        chip;
-        struct at91_gpio_chip   *next;          /* Bank sharing same clock */
-        int                     pioc_hwirq;     /* PIO bank interrupt identifier on AIC */
-        int                     pioc_virq;      /* PIO bank Linux virtual interrupt */
-        int                     pioc_idx;       /* PIO bank index */
-        void __iomem            *regbase;       /* PIO bank virtual address */
-        struct clk              *clock;         /* associated clock */
-        struct irq_domain       *domain;        /* associated irq domain */
-};
-#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
-static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset);
-static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
-static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
-static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
-static int at91_gpiolib_get_direction(struct gpio_chip *chip, unsigned offset);
-static int at91_gpiolib_direction_output(struct gpio_chip *chip,
-                                         unsigned offset, int val);
-static int at91_gpiolib_direction_input(struct gpio_chip *chip,
-                                        unsigned offset);
-static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
-#define AT91_GPIO_CHIP(name)                                            \
-        {                                                               \
-                .chip = {                                               \
-                        .label            = name,                       \
-                        .request          = at91_gpiolib_request,       \
-                        .get_direction    = at91_gpiolib_get_direction, \
-                        .direction_input  = at91_gpiolib_direction_input, \
-                        .direction_output = at91_gpiolib_direction_output, \
-                        .get              = at91_gpiolib_get,           \
-                        .set              = at91_gpiolib_set,           \
-                        .dbg_show         = at91_gpiolib_dbg_show,      \
-                        .to_irq           = at91_gpiolib_to_irq,        \
-                        .ngpio            = MAX_NB_GPIO_PER_BANK,       \
-                },                                                      \
-        }
-static struct at91_gpio_chip gpio_chip[] = {
-        AT91_GPIO_CHIP("pioA"),
-        AT91_GPIO_CHIP("pioB"),
-        AT91_GPIO_CHIP("pioC"),
-        AT91_GPIO_CHIP("pioD"),
-        AT91_GPIO_CHIP("pioE"),
-};
-static int gpio_banks;
-static unsigned long at91_gpio_caps;
-/* All PIO controllers support PIO3 features */
-#define AT91_GPIO_CAP_PIO3      (1 <<  0)
-#define has_pio3()      (at91_gpio_caps & AT91_GPIO_CAP_PIO3)
-/*--------------------------------------------------------------------------*/
-static inline void __iomem *pin_to_controller(unsigned pin)
-{
-        pin /= MAX_NB_GPIO_PER_BANK;
-        if (likely(pin < gpio_banks))
-                return gpio_chip[pin].regbase;
-        return NULL;
-}
-static inline unsigned pin_to_mask(unsigned pin)
-{
-        return 1 << (pin % MAX_NB_GPIO_PER_BANK);
-}
-static char peripheral_function(void __iomem *pio, unsigned mask)
-{
-        char    ret = 'X';
-        u8      select;
-        if (pio) {
-                if (has_pio3()) {
-                        select = !!(__raw_readl(pio + PIO_ABCDSR1) & mask);
-                        select |= (!!(__raw_readl(pio + PIO_ABCDSR2) & mask) << 1);
-                        ret = 'A' + select;
-                } else {
-                        ret = __raw_readl(pio + PIO_ABSR) & mask ?
-                                                        'B' : 'A';
-                }
-        }
-        return ret;
-}
-/*--------------------------------------------------------------------------*/
-/* Not all hardware capabilities are exposed through these calls; they
- * only encapsulate the most common features and modes.  (So if you
- * want to change signals in groups, do it directly.)
- *
- * Bootloaders will usually handle some of the pin multiplexing setup.
- * The intent is certainly that by the time Linux is fully booted, all
- * pins should have been fully initialized.  These setup calls should
- * only be used by board setup routines, or possibly in driver probe().
- *
- * For bootloaders doing all that setup, these calls could be inlined
- * as NOPs so Linux won't duplicate any setup code
- */
-/*
- * mux the pin to the "GPIO" peripheral role.
- */
-int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup)
-{
-        void __iomem    *pio = pin_to_controller(pin);
-        unsigned        mask = pin_to_mask(pin);
-        if (!pio)
-                return -EINVAL;
-        __raw_writel(mask, pio + PIO_IDR);
-        __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
-        __raw_writel(mask, pio + PIO_PER);
-        return 0;
-}
-EXPORT_SYMBOL(at91_set_GPIO_periph);
-/*
- * mux the pin to the "A" internal peripheral role.
- */
-int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
-{
-        void __iomem    *pio = pin_to_controller(pin);
-        unsigned        mask = pin_to_mask(pin);
-        if (!pio)
-                return -EINVAL;
-        __raw_writel(mask, pio + PIO_IDR);
-        __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
-        if (has_pio3()) {
-                __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
-                                                        pio + PIO_ABCDSR1);
-                __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
-                                                        pio + PIO_ABCDSR2);
-        } else {
-                __raw_writel(mask, pio + PIO_ASR);
-        }
-        __raw_writel(mask, pio + PIO_PDR);
-        return 0;
-}
-EXPORT_SYMBOL(at91_set_A_periph);
-/*
- * mux the pin to the "B" internal peripheral role.
- */
-int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
-{
-        void __iomem    *pio = pin_to_controller(pin);
-        unsigned        mask = pin_to_mask(pin);
-        if (!pio)
-                return -EINVAL;
-        __raw_writel(mask, pio + PIO_IDR);
-        __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
-        if (has_pio3()) {
-                __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
-                                                        pio + PIO_ABCDSR1);
-                __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
-                                                        pio + PIO_ABCDSR2);
-        } else {
-                __raw_writel(mask, pio + PIO_BSR);
-        }
-        __raw_writel(mask, pio + PIO_PDR);
-        return 0;
-}
-EXPORT_SYMBOL(at91_set_B_periph);
-/*
- * mux the pin to the "C" internal peripheral role.
- */
-int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup)
-{
-        void __iomem    *pio = pin_to_controller(pin);
-        unsigned        mask = pin_to_mask(pin);
-        if (!pio || !has_pio3())
-                return -EINVAL;
-        __raw_writel(mask, pio + PIO_IDR);
-        __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
-        __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
-        __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
-        __raw_writel(mask, pio + PIO_PDR);
-        return 0;
-}
-EXPORT_SYMBOL(at91_set_C_periph);
-/*
- * mux the pin to the "D" internal peripheral role.
- */
-int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup)
-{
-        void __iomem    *pio = pin_to_controller(pin);
-        unsigned        mask = pin_to_mask(pin);
-        if (!pio || !has_pio3())
-                return -EINVAL;
-        __raw_writel(mask, pio + PIO_IDR);
-        __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
-        __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
-        __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
-        __raw_writel(mask, pio + PIO_PDR);
-        return 0;
-}
-EXPORT_SYMBOL(at91_set_D_periph);
-/*
- * mux the pin to the gpio controller (instead of "A", "B", "C"
- * or "D" peripheral), and configure it for an input.
- */
-int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
-{
-        void __iomem    *pio = pin_to_controller(pin);
-        unsigned        mask = pin_to_mask(pin);
-        if (!pio)
-                return -EINVAL;
-        __raw_writel(mask, pio + PIO_IDR);
-        __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
-        __raw_writel(mask, pio + PIO_ODR);
-        __raw_writel(mask, pio + PIO_PER);
-        return 0;
-}
-EXPORT_SYMBOL(at91_set_gpio_input);
-/*
- * mux the pin to the gpio controller (instead of "A", "B", "C"
- * or "D" peripheral), and configure it for an output.
- */
-int __init_or_module at91_set_gpio_output(unsigned pin, int value)
-{
-        void __iomem    *pio = pin_to_controller(pin);
-        unsigned        mask = pin_to_mask(pin);
-        if (!pio)
-                return -EINVAL;
-        __raw_writel(mask, pio + PIO_IDR);
-        __raw_writel(mask, pio + PIO_PUDR);
-        __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
-        __raw_writel(mask, pio + PIO_OER);
-        __raw_writel(mask, pio + PIO_PER);
-        return 0;
-}
-EXPORT_SYMBOL(at91_set_gpio_output);
-/*
- * enable/disable the glitch filter; mostly used with IRQ handling.
- */
-int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
-{
-        void __iomem    *pio = pin_to_controller(pin);
-        unsigned        mask = pin_to_mask(pin);
-        if (!pio)
-                return -EINVAL;
-        if (has_pio3() && is_on)
-                __raw_writel(mask, pio + PIO_IFSCDR);
-        __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
-        return 0;
-}
-EXPORT_SYMBOL(at91_set_deglitch);
-/*
- * enable/disable the debounce filter;
- */
-int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div)
-{
-        void __iomem    *pio = pin_to_controller(pin);
-        unsigned        mask = pin_to_mask(pin);
-        if (!pio || !has_pio3())
-                return -EINVAL;
-        if (is_on) {
-                __raw_writel(mask, pio + PIO_IFSCER);
-                __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
-                __raw_writel(mask, pio + PIO_IFER);
-        } else {
-                __raw_writel(mask, pio + PIO_IFDR);
-        }
-        return 0;
-}
-EXPORT_SYMBOL(at91_set_debounce);
-/*
- * enable/disable the multi-driver; This is only valid for output and
- * allows the output pin to run as an open collector output.
- */
-int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
-{
-        void __iomem    *pio = pin_to_controller(pin);
-        unsigned        mask = pin_to_mask(pin);
-        if (!pio)
-                return -EINVAL;
-        __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
-        return 0;
-}
-EXPORT_SYMBOL(at91_set_multi_drive);
-/*
- * enable/disable the pull-down.
- * If pull-up already enabled while calling the function, we disable it.
- */
-int __init_or_module at91_set_pulldown(unsigned pin, int is_on)
-{
-        void __iomem    *pio = pin_to_controller(pin);
-        unsigned        mask = pin_to_mask(pin);
-        if (!pio || !has_pio3())
-                return -EINVAL;
-        /* Disable pull-up anyway */
-        __raw_writel(mask, pio + PIO_PUDR);
-        __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
-        return 0;
-}
-EXPORT_SYMBOL(at91_set_pulldown);
-/*
- * disable Schmitt trigger
- */
-int __init_or_module at91_disable_schmitt_trig(unsigned pin)
-{
-        void __iomem    *pio = pin_to_controller(pin);
-        unsigned        mask = pin_to_mask(pin);
-        if (!pio || !has_pio3())
-                return -EINVAL;
-        __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
-        return 0;
-}
-EXPORT_SYMBOL(at91_disable_schmitt_trig);
-/*
- * assuming the pin is muxed as a gpio output, set its value.
- */
-int at91_set_gpio_value(unsigned pin, int value)
-{
-        void __iomem    *pio = pin_to_controller(pin);
-        unsigned        mask = pin_to_mask(pin);
-        if (!pio)
-                return -EINVAL;
-        __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
-        return 0;
-}
-EXPORT_SYMBOL(at91_set_gpio_value);
-/*
- * read the pin's value (works even if it's not muxed as a gpio).
- */
-int at91_get_gpio_value(unsigned pin)
-{
-        void __iomem    *pio = pin_to_controller(pin);
-        unsigned        mask = pin_to_mask(pin);
-        u32             pdsr;
-        if (!pio)
-                return -EINVAL;
-        pdsr = __raw_readl(pio + PIO_PDSR);
-        return (pdsr & mask) != 0;
-}
-EXPORT_SYMBOL(at91_get_gpio_value);
-/*--------------------------------------------------------------------------*/
-#ifdef CONFIG_PM
-static u32 wakeups[MAX_GPIO_BANKS];
-static u32 backups[MAX_GPIO_BANKS];
-static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
-{
-        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
-        unsigned        mask = 1 << d->hwirq;
-        unsigned        bank = at91_gpio->pioc_idx;
-        if (unlikely(bank >= MAX_GPIO_BANKS))
-                return -EINVAL;
-        if (state)
-                wakeups[bank] |= mask;
-        else
-                wakeups[bank] &= ~mask;
-        irq_set_irq_wake(at91_gpio->pioc_virq, state);
-        return 0;
-}
-void at91_gpio_suspend(void)
-{
-        int i;
-        for (i = 0; i < gpio_banks; i++) {
-                void __iomem    *pio = gpio_chip[i].regbase;
-                backups[i] = __raw_readl(pio + PIO_IMR);
-                __raw_writel(backups[i], pio + PIO_IDR);
-                __raw_writel(wakeups[i], pio + PIO_IER);
-                if (!wakeups[i]) {
-                        clk_unprepare(gpio_chip[i].clock);
-                        clk_disable(gpio_chip[i].clock);
-                } else {
-#ifdef CONFIG_PM_DEBUG
-                        printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
-#endif
-                }
-        }
-}
-void at91_gpio_resume(void)
-{
-        int i;
-        for (i = 0; i < gpio_banks; i++) {
-                void __iomem    *pio = gpio_chip[i].regbase;
-                if (!wakeups[i]) {
-                        if (clk_prepare(gpio_chip[i].clock) == 0)
-                                clk_enable(gpio_chip[i].clock);
-                }
-                __raw_writel(wakeups[i], pio + PIO_IDR);
-                __raw_writel(backups[i], pio + PIO_IER);
-        }
-}
-#else
-#define gpio_irq_set_wake       NULL
-#endif
-/* Several AIC controller irqs are dispatched through this GPIO handler.
- * To use any AT91_PIN_* as an externally triggered IRQ, first call
- * at91_set_gpio_input() then maybe enable its glitch filter.
- * Then just request_irq() with the pin ID; it works like any ARM IRQ
- * handler.
- * First implementation always triggers on rising and falling edges
- * whereas the newer PIO3 can be additionally configured to trigger on
- * level, edge with any polarity.
- *
- * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
- * configuring them with at91_set_a_periph() or at91_set_b_periph().
- * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
- */
-static void gpio_irq_mask(struct irq_data *d)
-{
-        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
-        void __iomem    *pio = at91_gpio->regbase;
-        unsigned        mask = 1 << d->hwirq;
-        if (pio)
-                __raw_writel(mask, pio + PIO_IDR);
-}
-static void gpio_irq_unmask(struct irq_data *d)
-{
-        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
-        void __iomem    *pio = at91_gpio->regbase;
-        unsigned        mask = 1 << d->hwirq;
-        if (pio)
-                __raw_writel(mask, pio + PIO_IER);
-}
-static int gpio_irq_type(struct irq_data *d, unsigned type)
-{
-        switch (type) {
-        case IRQ_TYPE_NONE:
-        case IRQ_TYPE_EDGE_BOTH:
-                return 0;
-        default:
-                return -EINVAL;
-        }
-}
-/* Alternate irq type for PIO3 support */
-static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
-{
-        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
-        void __iomem    *pio = at91_gpio->regbase;
-        unsigned        mask = 1 << d->hwirq;
-        switch (type) {
-        case IRQ_TYPE_EDGE_RISING:
-                __raw_writel(mask, pio + PIO_ESR);
-                __raw_writel(mask, pio + PIO_REHLSR);
-                break;
-        case IRQ_TYPE_EDGE_FALLING:
-                __raw_writel(mask, pio + PIO_ESR);
-                __raw_writel(mask, pio + PIO_FELLSR);
-                break;
-        case IRQ_TYPE_LEVEL_LOW:
-                __raw_writel(mask, pio + PIO_LSR);
-                __raw_writel(mask, pio + PIO_FELLSR);
-                break;
-        case IRQ_TYPE_LEVEL_HIGH:
-                __raw_writel(mask, pio + PIO_LSR);
-                __raw_writel(mask, pio + PIO_REHLSR);
-                break;
-        case IRQ_TYPE_EDGE_BOTH:
-                /*
-                 * disable additional interrupt modes:
-                 * fall back to default behavior
-                 */
-                __raw_writel(mask, pio + PIO_AIMDR);
-                return 0;
-        case IRQ_TYPE_NONE:
-        default:
-                pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
-                return -EINVAL;
-        }
-        /* enable additional interrupt modes */
-        __raw_writel(mask, pio + PIO_AIMER);
-        return 0;
-}
-static struct irq_chip gpio_irqchip = {
-        .name           = "GPIO",
-        .irq_disable    = gpio_irq_mask,
-        .irq_mask       = gpio_irq_mask,
-        .irq_unmask     = gpio_irq_unmask,
-        /* .irq_set_type is set dynamically */
-        .irq_set_wake   = gpio_irq_set_wake,
-};
-static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
-{
-        struct irq_chip *chip = irq_desc_get_chip(desc);
-        struct irq_data *idata = irq_desc_get_irq_data(desc);
-        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
-        void __iomem    *pio = at91_gpio->regbase;
-        unsigned long   isr;
-        int             n;
-        chained_irq_enter(chip, desc);
-        for (;;) {
-                /* Reading ISR acks pending (edge triggered) GPIO interrupts.
-                 * When there none are pending, we're finished unless we need
-                 * to process multiple banks (like ID_PIOCDE on sam9263).
-                 */
-                isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
-                if (!isr) {
-                        if (!at91_gpio->next)
-                                break;
-                        at91_gpio = at91_gpio->next;
-                        pio = at91_gpio->regbase;
-                        continue;
-                }
-                n = find_first_bit(&isr, BITS_PER_LONG);
-                while (n < BITS_PER_LONG) {
-                        generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
-                        n = find_next_bit(&isr, BITS_PER_LONG, n + 1);
-                }
-        }
-        chained_irq_exit(chip, desc);
-        /* now it may re-trigger */
-}
-/*--------------------------------------------------------------------------*/
-#ifdef CONFIG_DEBUG_FS
-static void gpio_printf(struct seq_file *s, void __iomem *pio, unsigned mask)
-{
-        char    *trigger = NULL;
-        char    *polarity = NULL;
-        if (__raw_readl(pio + PIO_IMR) & mask) {
-                if (!has_pio3() || !(__raw_readl(pio + PIO_AIMMR) & mask )) {
-                        trigger = "edge";
-                        polarity = "both";
-                } else {
-                        if (__raw_readl(pio + PIO_ELSR) & mask) {
-                                trigger = "level";
-                                polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
-                                        "high" : "low";
-                        } else {
-                                trigger = "edge";
-                                polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
-                                                "rising" : "falling";
-                        }
-                }
-                seq_printf(s, "IRQ:%s-%s\t", trigger, polarity);
-        } else {
-                seq_printf(s, "GPIO:%s\t\t",
-                                __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
-        }
-}
-static int at91_gpio_show(struct seq_file *s, void *unused)
-{
-        int bank, j;
-        /* print heading */
-        seq_printf(s, "Pin\t");
-        for (bank = 0; bank < gpio_banks; bank++) {
-                seq_printf(s, "PIO%c\t\t", 'A' + bank);
-        };
-        seq_printf(s, "\n\n");
-        /* print pin status */
-        for (j = 0; j < 32; j++) {
-                seq_printf(s, "%i:\t", j);
-                for (bank = 0; bank < gpio_banks; bank++) {
-                        unsigned        pin  = (32 * bank) + j;
-                        void __iomem    *pio = pin_to_controller(pin);
-                        unsigned        mask = pin_to_mask(pin);
-                        if (__raw_readl(pio + PIO_PSR) & mask)
-                                gpio_printf(s, pio, mask);
-                        else
-                                seq_printf(s, "%c\t\t",
-                                                peripheral_function(pio, mask));
-                }
-                seq_printf(s, "\n");
-        }
-        return 0;
-}
-static int at91_gpio_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, at91_gpio_show, NULL);
-}
-static const struct file_operations at91_gpio_operations = {
-        .open           = at91_gpio_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-static int __init at91_gpio_debugfs_init(void)
-{
-        /* /sys/kernel/debug/at91_gpio */
-        (void) debugfs_create_file("at91_gpio", S_IFREG | S_IRUGO, NULL, NULL, &at91_gpio_operations);
-        return 0;
-}
-postcore_initcall(at91_gpio_debugfs_init);
-#endif
-/*--------------------------------------------------------------------------*/
-/*
- * This lock class tells lockdep that GPIO irqs are in a different
- * category than their parents, so it won't report false recursion.
- */
-static struct lock_class_key gpio_lock_class;
-/*
- * irqdomain initialization: pile up irqdomains on top of AIC range
- */
-static void __init at91_gpio_irqdomain(struct at91_gpio_chip *at91_gpio)
-{
-        int irq_base;
-        irq_base = irq_alloc_descs(-1, 0, at91_gpio->chip.ngpio, 0);
-        if (irq_base < 0)
-                panic("at91_gpio.%d: error %d: couldn't allocate IRQ numbers.\n",
-                        at91_gpio->pioc_idx, irq_base);
-        at91_gpio->domain = irq_domain_add_legacy(NULL, at91_gpio->chip.ngpio,
-                                                  irq_base, 0,
-                                                  &irq_domain_simple_ops, NULL);
-        if (!at91_gpio->domain)
-                panic("at91_gpio.%d: couldn't allocate irq domain.\n",
-                        at91_gpio->pioc_idx);
-}
-/*
- * Called from the processor-specific init to enable GPIO interrupt support.
- */
-void __init at91_gpio_irq_setup(void)
-{
-        unsigned                pioc;
-        int                     gpio_irqnbr = 0;
-        struct at91_gpio_chip   *this, *prev;
-        /* Setup proper .irq_set_type function */
-        if (has_pio3())
-                gpio_irqchip.irq_set_type = alt_gpio_irq_type;
-        else
-                gpio_irqchip.irq_set_type = gpio_irq_type;
-        for (pioc = 0, this = gpio_chip, prev = NULL;
-                        pioc++ < gpio_banks;
-                        prev = this, this++) {
-                int offset;
-                __raw_writel(~0, this->regbase + PIO_IDR);
-                /* setup irq domain for this GPIO controller */
-                at91_gpio_irqdomain(this);
-                for (offset = 0; offset < this->chip.ngpio; offset++) {
-                        unsigned int virq = irq_find_mapping(this->domain, offset);
-                        irq_set_lockdep_class(virq, &gpio_lock_class);
-                        /*
-                         * Can use the "simple" and not "edge" handler since it's
-                         * shorter, and the AIC handles interrupts sanely.
-                         */
-                        irq_set_chip_and_handler(virq, &gpio_irqchip,
-                                                 handle_simple_irq);
-                        set_irq_flags(virq, IRQF_VALID);
-                        irq_set_chip_data(virq, this);
-                        gpio_irqnbr++;
-                }
-                /* The toplevel handler handles one bank of GPIOs, except
-                 * on some SoC it can handles up to three...
-                 * We only set up the handler for the first of the list.
-                 */
-                if (prev && prev->next == this)
-                        continue;
-                this->pioc_virq = irq_create_mapping(NULL, this->pioc_hwirq);
-                irq_set_chip_data(this->pioc_virq, this);
-                irq_set_chained_handler(this->pioc_virq, gpio_irq_handler);
-        }
-        pr_info("AT91: %d gpio irqs in %d banks\n", gpio_irqnbr, gpio_banks);
-}
-/* gpiolib support */
-static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset)
-{
-        struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
-        void __iomem *pio = at91_gpio->regbase;
-        unsigned mask = 1 << offset;
-        __raw_writel(mask, pio + PIO_PER);
-        return 0;
-}
-static int at91_gpiolib_get_direction(struct gpio_chip *chip, unsigned offset)
-{
-        struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
-        void __iomem *pio = at91_gpio->regbase;
-        unsigned mask = 1 << offset;
-        u32 osr;
-        osr = __raw_readl(pio + PIO_OSR);
-        return !(osr & mask);
-}
-static int at91_gpiolib_direction_input(struct gpio_chip *chip,
-                                        unsigned offset)
-{
-        struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
-        void __iomem *pio = at91_gpio->regbase;
-        unsigned mask = 1 << offset;
-        __raw_writel(mask, pio + PIO_ODR);
-        return 0;
-}
-static int at91_gpiolib_direction_output(struct gpio_chip *chip,
-                                         unsigned offset, int val)
-{
-        struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
-        void __iomem *pio = at91_gpio->regbase;
-        unsigned mask = 1 << offset;
-        __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
-        __raw_writel(mask, pio + PIO_OER);
-        return 0;
-}
-static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset)
-{
-        struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
-        void __iomem *pio = at91_gpio->regbase;
-        unsigned mask = 1 << offset;
-        u32 pdsr;
-        pdsr = __raw_readl(pio + PIO_PDSR);
-        return (pdsr & mask) != 0;
-}
-static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
-{
-        struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
-        void __iomem *pio = at91_gpio->regbase;
-        unsigned mask = 1 << offset;
-        __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
-}
-static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
-{
-        int i;
-        for (i = 0; i < chip->ngpio; i++) {
-                unsigned pin = chip->base + i;
-                void __iomem *pio = pin_to_controller(pin);
-                unsigned mask = pin_to_mask(pin);
-                const char *gpio_label;
-                gpio_label = gpiochip_is_requested(chip, i);
-                if (gpio_label) {
-                        seq_printf(s, "[%s] GPIO%s%d: ",
-                                   gpio_label, chip->label, i);
-                        if (__raw_readl(pio + PIO_PSR) & mask)
-                                seq_printf(s, "[gpio] %s\n",
-                                           at91_get_gpio_value(pin) ?
-                                           "set" : "clear");
-                        else
-                                seq_printf(s, "[periph %c]\n",
-                                           peripheral_function(pio, mask));
-                }
-        }
-}
-static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-        struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
-        int virq;
-        if (offset < chip->ngpio)
-                virq = irq_create_mapping(at91_gpio->domain, offset);
-        else
-                virq = -ENXIO;
-        dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
-                                chip->label, offset + chip->base, virq);
-        return virq;
-}
-static int __init at91_gpio_setup_clk(int idx)
-{
-        struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
-        /* retreive PIO controller's clock */
-        at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label);
-        if (IS_ERR(at91_gpio->clock)) {
-                pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", idx);
-                goto err;
-        }
-        if (clk_prepare(at91_gpio->clock))
-                goto clk_prep_err;
-        /* enable PIO controller's clock */
-        if (clk_enable(at91_gpio->clock)) {
-                pr_err("at91_gpio.%d, failed to enable clock, ignoring.\n", idx);
-                goto clk_err;
-        }
-        return 0;
-clk_err:
-        clk_unprepare(at91_gpio->clock);
-clk_prep_err:
-        clk_put(at91_gpio->clock);
-err:
-        return -EINVAL;
-}
-static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq)
-{
-        struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
-        at91_gpio->chip.base = idx * MAX_NB_GPIO_PER_BANK;
-        at91_gpio->pioc_hwirq = pioc_hwirq;
-        at91_gpio->pioc_idx = idx;
-        at91_gpio->regbase = ioremap(regbase, 512);
-        if (!at91_gpio->regbase) {
-                pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", idx);
-                return;
-        }
-        if (at91_gpio_setup_clk(idx))
-                goto ioremap_err;
-        gpio_banks = max(gpio_banks, idx + 1);
-        return;
-ioremap_err:
-        iounmap(at91_gpio->regbase);
-}
-/*
- * Called from the processor-specific init to enable GPIO pin support.
- */
-void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
-{
-        unsigned i;
-        struct at91_gpio_chip *at91_gpio, *last = NULL;
-        BUG_ON(nr_banks > MAX_GPIO_BANKS);
-        if (of_have_populated_dt())
-                return;
-        for (i = 0; i < nr_banks; i++)
-                at91_gpio_init_one(i, data[i].regbase, data[i].id);
-        for (i = 0; i < gpio_banks; i++) {
-                at91_gpio = &gpio_chip[i];
-                /*
-                 * GPIO controller are grouped on some SoC:
-                 * PIOC, PIOD and PIOE can share the same IRQ line
-                 */
-                if (last && last->pioc_hwirq == at91_gpio->pioc_hwirq)
-                        last->next = at91_gpio;
-                last = at91_gpio;
-                gpiochip_add(&at91_gpio->chip);
-        }
-}
diff --git a/arch/arm/mach-at91/gpio.h b/arch/arm/mach-at91/gpio.h
deleted file mode 100644
index eed465ab0dd7..000000000000
--- a/arch/arm/mach-at91/gpio.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/gpio.h
- *
- *  Copyright (C) 2005 HP Labs
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#ifndef __ASM_ARCH_AT91RM9200_GPIO_H
-#define __ASM_ARCH_AT91RM9200_GPIO_H
-#include <linux/kernel.h>
-#include <asm/irq.h>
-#define MAX_GPIO_BANKS          5
-#define NR_BUILTIN_GPIO         (MAX_GPIO_BANKS * 32)
-/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
-#define AT91_PIN_PA0    (0x00 + 0)
-#define AT91_PIN_PA1    (0x00 + 1)
-#define AT91_PIN_PA2    (0x00 + 2)
-#define AT91_PIN_PA3    (0x00 + 3)
-#define AT91_PIN_PA4    (0x00 + 4)
-#define AT91_PIN_PA5    (0x00 + 5)
-#define AT91_PIN_PA6    (0x00 + 6)
-#define AT91_PIN_PA7    (0x00 + 7)
-#define AT91_PIN_PA8    (0x00 + 8)
-#define AT91_PIN_PA9    (0x00 + 9)
-#define AT91_PIN_PA10   (0x00 + 10)
-#define AT91_PIN_PA11   (0x00 + 11)
-#define AT91_PIN_PA12   (0x00 + 12)
-#define AT91_PIN_PA13   (0x00 + 13)
-#define AT91_PIN_PA14   (0x00 + 14)
-#define AT91_PIN_PA15   (0x00 + 15)
-#define AT91_PIN_PA16   (0x00 + 16)
-#define AT91_PIN_PA17   (0x00 + 17)
-#define AT91_PIN_PA18   (0x00 + 18)
-#define AT91_PIN_PA19   (0x00 + 19)
-#define AT91_PIN_PA20   (0x00 + 20)
-#define AT91_PIN_PA21   (0x00 + 21)
-#define AT91_PIN_PA22   (0x00 + 22)
-#define AT91_PIN_PA23   (0x00 + 23)
-#define AT91_PIN_PA24   (0x00 + 24)
-#define AT91_PIN_PA25   (0x00 + 25)
-#define AT91_PIN_PA26   (0x00 + 26)
-#define AT91_PIN_PA27   (0x00 + 27)
-#define AT91_PIN_PA28   (0x00 + 28)
-#define AT91_PIN_PA29   (0x00 + 29)
-#define AT91_PIN_PA30   (0x00 + 30)
-#define AT91_PIN_PA31   (0x00 + 31)
-#define AT91_PIN_PB0    (0x20 + 0)
-#define AT91_PIN_PB1    (0x20 + 1)
-#define AT91_PIN_PB2    (0x20 + 2)
-#define AT91_PIN_PB3    (0x20 + 3)
-#define AT91_PIN_PB4    (0x20 + 4)
-#define AT91_PIN_PB5    (0x20 + 5)
-#define AT91_PIN_PB6    (0x20 + 6)
-#define AT91_PIN_PB7    (0x20 + 7)
-#define AT91_PIN_PB8    (0x20 + 8)
-#define AT91_PIN_PB9    (0x20 + 9)
-#define AT91_PIN_PB10   (0x20 + 10)
-#define AT91_PIN_PB11   (0x20 + 11)
-#define AT91_PIN_PB12   (0x20 + 12)
-#define AT91_PIN_PB13   (0x20 + 13)
-#define AT91_PIN_PB14   (0x20 + 14)
-#define AT91_PIN_PB15   (0x20 + 15)
-#define AT91_PIN_PB16   (0x20 + 16)
-#define AT91_PIN_PB17   (0x20 + 17)
-#define AT91_PIN_PB18   (0x20 + 18)
-#define AT91_PIN_PB19   (0x20 + 19)
-#define AT91_PIN_PB20   (0x20 + 20)
-#define AT91_PIN_PB21   (0x20 + 21)
-#define AT91_PIN_PB22   (0x20 + 22)
-#define AT91_PIN_PB23   (0x20 + 23)
-#define AT91_PIN_PB24   (0x20 + 24)
-#define AT91_PIN_PB25   (0x20 + 25)
-#define AT91_PIN_PB26   (0x20 + 26)
-#define AT91_PIN_PB27   (0x20 + 27)
-#define AT91_PIN_PB28   (0x20 + 28)
-#define AT91_PIN_PB29   (0x20 + 29)
-#define AT91_PIN_PB30   (0x20 + 30)
-#define AT91_PIN_PB31   (0x20 + 31)
-#define AT91_PIN_PC0    (0x40 + 0)
-#define AT91_PIN_PC1    (0x40 + 1)
-#define AT91_PIN_PC2    (0x40 + 2)
-#define AT91_PIN_PC3    (0x40 + 3)
-#define AT91_PIN_PC4    (0x40 + 4)
-#define AT91_PIN_PC5    (0x40 + 5)
-#define AT91_PIN_PC6    (0x40 + 6)
-#define AT91_PIN_PC7    (0x40 + 7)
-#define AT91_PIN_PC8    (0x40 + 8)
-#define AT91_PIN_PC9    (0x40 + 9)
-#define AT91_PIN_PC10   (0x40 + 10)
-#define AT91_PIN_PC11   (0x40 + 11)
-#define AT91_PIN_PC12   (0x40 + 12)
-#define AT91_PIN_PC13   (0x40 + 13)
-#define AT91_PIN_PC14   (0x40 + 14)
-#define AT91_PIN_PC15   (0x40 + 15)
-#define AT91_PIN_PC16   (0x40 + 16)
-#define AT91_PIN_PC17   (0x40 + 17)
-#define AT91_PIN_PC18   (0x40 + 18)
-#define AT91_PIN_PC19   (0x40 + 19)
-#define AT91_PIN_PC20   (0x40 + 20)
-#define AT91_PIN_PC21   (0x40 + 21)
-#define AT91_PIN_PC22   (0x40 + 22)
-#define AT91_PIN_PC23   (0x40 + 23)
-#define AT91_PIN_PC24   (0x40 + 24)
-#define AT91_PIN_PC25   (0x40 + 25)
-#define AT91_PIN_PC26   (0x40 + 26)
-#define AT91_PIN_PC27   (0x40 + 27)
-#define AT91_PIN_PC28   (0x40 + 28)
-#define AT91_PIN_PC29   (0x40 + 29)
-#define AT91_PIN_PC30   (0x40 + 30)
-#define AT91_PIN_PC31   (0x40 + 31)
-#define AT91_PIN_PD0    (0x60 + 0)
-#define AT91_PIN_PD1    (0x60 + 1)
-#define AT91_PIN_PD2    (0x60 + 2)
-#define AT91_PIN_PD3    (0x60 + 3)
-#define AT91_PIN_PD4    (0x60 + 4)
-#define AT91_PIN_PD5    (0x60 + 5)
-#define AT91_PIN_PD6    (0x60 + 6)
-#define AT91_PIN_PD7    (0x60 + 7)
-#define AT91_PIN_PD8    (0x60 + 8)
-#define AT91_PIN_PD9    (0x60 + 9)
-#define AT91_PIN_PD10   (0x60 + 10)
-#define AT91_PIN_PD11   (0x60 + 11)
-#define AT91_PIN_PD12   (0x60 + 12)
-#define AT91_PIN_PD13   (0x60 + 13)
-#define AT91_PIN_PD14   (0x60 + 14)
-#define AT91_PIN_PD15   (0x60 + 15)
-#define AT91_PIN_PD16   (0x60 + 16)
-#define AT91_PIN_PD17   (0x60 + 17)
-#define AT91_PIN_PD18   (0x60 + 18)
-#define AT91_PIN_PD19   (0x60 + 19)
-#define AT91_PIN_PD20   (0x60 + 20)
-#define AT91_PIN_PD21   (0x60 + 21)
-#define AT91_PIN_PD22   (0x60 + 22)
-#define AT91_PIN_PD23   (0x60 + 23)
-#define AT91_PIN_PD24   (0x60 + 24)
-#define AT91_PIN_PD25   (0x60 + 25)
-#define AT91_PIN_PD26   (0x60 + 26)
-#define AT91_PIN_PD27   (0x60 + 27)
-#define AT91_PIN_PD28   (0x60 + 28)
-#define AT91_PIN_PD29   (0x60 + 29)
-#define AT91_PIN_PD30   (0x60 + 30)
-#define AT91_PIN_PD31   (0x60 + 31)
-#define AT91_PIN_PE0    (0x80 + 0)
-#define AT91_PIN_PE1    (0x80 + 1)
-#define AT91_PIN_PE2    (0x80 + 2)
-#define AT91_PIN_PE3    (0x80 + 3)
-#define AT91_PIN_PE4    (0x80 + 4)
-#define AT91_PIN_PE5    (0x80 + 5)
-#define AT91_PIN_PE6    (0x80 + 6)
-#define AT91_PIN_PE7    (0x80 + 7)
-#define AT91_PIN_PE8    (0x80 + 8)
-#define AT91_PIN_PE9    (0x80 + 9)
-#define AT91_PIN_PE10   (0x80 + 10)
-#define AT91_PIN_PE11   (0x80 + 11)
-#define AT91_PIN_PE12   (0x80 + 12)
-#define AT91_PIN_PE13   (0x80 + 13)
-#define AT91_PIN_PE14   (0x80 + 14)
-#define AT91_PIN_PE15   (0x80 + 15)
-#define AT91_PIN_PE16   (0x80 + 16)
-#define AT91_PIN_PE17   (0x80 + 17)
-#define AT91_PIN_PE18   (0x80 + 18)
-#define AT91_PIN_PE19   (0x80 + 19)
-#define AT91_PIN_PE20   (0x80 + 20)
-#define AT91_PIN_PE21   (0x80 + 21)
-#define AT91_PIN_PE22   (0x80 + 22)
-#define AT91_PIN_PE23   (0x80 + 23)
-#define AT91_PIN_PE24   (0x80 + 24)
-#define AT91_PIN_PE25   (0x80 + 25)
-#define AT91_PIN_PE26   (0x80 + 26)
-#define AT91_PIN_PE27   (0x80 + 27)
-#define AT91_PIN_PE28   (0x80 + 28)
-#define AT91_PIN_PE29   (0x80 + 29)
-#define AT91_PIN_PE30   (0x80 + 30)
-#define AT91_PIN_PE31   (0x80 + 31)
-#ifndef __ASSEMBLY__
-/* setup setup routines, called from board init or driver probe() */
-extern int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup);
-extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup);
-extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup);
-extern int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup);
-extern int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup);
-extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup);
-extern int __init_or_module at91_set_gpio_output(unsigned pin, int value);
-extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on);
-extern int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div);
-extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on);
-extern int __init_or_module at91_set_pulldown(unsigned pin, int is_on);
-extern int __init_or_module at91_disable_schmitt_trig(unsigned pin);
-/* callable at any time */
-extern int at91_set_gpio_value(unsigned pin, int value);
-extern int at91_get_gpio_value(unsigned pin);
-/* callable only from core power-management code */
-extern void at91_gpio_suspend(void);
-extern void at91_gpio_resume(void);
-#endif  /* __ASSEMBLY__ */
-#endif
diff --git a/arch/arm/mach-at91/gsia18s.h b/arch/arm/mach-at91/gsia18s.h
deleted file mode 100644
index 307c194926f9..000000000000
--- a/arch/arm/mach-at91/gsia18s.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Buttons */
-#define GPIO_TRIG_NET_IN                AT91_PIN_PB21
-#define GPIO_CARD_UNMOUNT_0             AT91_PIN_PB13
-#define GPIO_CARD_UNMOUNT_1             AT91_PIN_PB12
-#define GPIO_KEY_POWER                  AT91_PIN_PA25
-/* PCF8574 0x20 GPIO - U1 on the GS_IA18-CB_V3 board */
-#define GS_IA18_S_PCF_GPIO_BASE0        NR_BUILTIN_GPIO
-#define PCF_GPIO_HDC_POWER              (GS_IA18_S_PCF_GPIO_BASE0 + 0)
-#define PCF_GPIO_WIFI_SETUP             (GS_IA18_S_PCF_GPIO_BASE0 + 1)
-#define PCF_GPIO_WIFI_ENABLE            (GS_IA18_S_PCF_GPIO_BASE0 + 2)
-#define PCF_GPIO_WIFI_RESET             (GS_IA18_S_PCF_GPIO_BASE0 + 3)
-#define PCF_GPIO_ETH_DETECT             4 /* this is a GPI */
-#define PCF_GPIO_GPS_SETUP              (GS_IA18_S_PCF_GPIO_BASE0 + 5)
-#define PCF_GPIO_GPS_STANDBY            (GS_IA18_S_PCF_GPIO_BASE0 + 6)
-#define PCF_GPIO_GPS_POWER              (GS_IA18_S_PCF_GPIO_BASE0 + 7)
-/* PCF8574 0x22 GPIO - U1 on the GS_2G_OPT1-A_V0 board (Alarm) */
-#define GS_IA18_S_PCF_GPIO_BASE1        (GS_IA18_S_PCF_GPIO_BASE0 + 8)
-#define PCF_GPIO_ALARM1                 (GS_IA18_S_PCF_GPIO_BASE1 + 0)
-#define PCF_GPIO_ALARM2                 (GS_IA18_S_PCF_GPIO_BASE1 + 1)
-#define PCF_GPIO_ALARM3                 (GS_IA18_S_PCF_GPIO_BASE1 + 2)
-#define PCF_GPIO_ALARM4                 (GS_IA18_S_PCF_GPIO_BASE1 + 3)
-/* bits 4, 5, 6 not used */
-#define PCF_GPIO_ALARM_V_RELAY_ON       (GS_IA18_S_PCF_GPIO_BASE1 + 7)
-/* PCF8574 0x24 GPIO U1 on the GS_2G-OPT23-A_V0 board (Modem) */
-#define GS_IA18_S_PCF_GPIO_BASE2        (GS_IA18_S_PCF_GPIO_BASE1 + 8)
-#define PCF_GPIO_MODEM_POWER            (GS_IA18_S_PCF_GPIO_BASE2 + 0)
-#define PCF_GPIO_MODEM_RESET            (GS_IA18_S_PCF_GPIO_BASE2 + 3)
-/* bits 1, 2, 4, 5 not used */
-#define PCF_GPIO_TRX_RESET              (GS_IA18_S_PCF_GPIO_BASE2 + 6)
-/* bit 7 not used */
diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h
index 3b5948566e52..42925e8f78e4 100644
--- a/arch/arm/mach-at91/include/mach/at91_dbgu.h
+++ b/arch/arm/mach-at91/include/mach/at91_dbgu.h
@@ -16,7 +16,6 @@
 #ifndef AT91_DBGU_H
 #define AT91_DBGU_H
-#if !defined(CONFIG_ARCH_AT91X40)
 #define AT91_DBGU_CR            (0x00)  /* Control Register */
 #define AT91_DBGU_MR            (0x04)  /* Mode Register */
 #define AT91_DBGU_IER           (0x08)  /* Interrupt Enable Register */
@@ -34,8 +33,6 @@
 #define AT91_DBGU_FNR           (0x48)  /* Force NTRST Register [SAM9 only] */
 #define         AT91_DBGU_FNTRST        (1 << 0)                /* Force NTRST */
-#endif /* AT91_DBGU */
 /*
 * Some AT91 parts that don't have full DEBUG units still support the ID
 * and extensions register.
diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach/at91_ramc.h
index d8aeb278614e..e4492b151fee 100644
--- a/arch/arm/mach-at91/include/mach/at91_ramc.h
+++ b/arch/arm/mach-at91/include/mach/at91_ramc.h
@@ -25,8 +25,8 @@ extern void __iomem *at91_ramc_base[];
 #define AT91_MEMCTRL_SDRAMC     1
 #define AT91_MEMCTRL_DDRSDR     2
-#include <mach/at91rm9200_sdramc.h>
+#include <soc/at91/at91rm9200_sdramc.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <soc/at91/at91sam9_ddrsdr.h>
-#include <mach/at91sam9_sdramc.h>
+#include <soc/at91/at91sam9_sdramc.h>
 #endif /* __AT91_RAMC_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h b/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
deleted file mode 100644
index aa047f458f1b..000000000000
--- a/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Memory Controllers (SDRAMC only) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91RM9200_SDRAMC_H
-#define AT91RM9200_SDRAMC_H
-/* SDRAM Controller registers */
-#define AT91RM9200_SDRAMC_MR            0x90                    /* Mode Register */
-#define         AT91RM9200_SDRAMC_MODE  (0xf << 0)              /* Command Mode */
-#define                 AT91RM9200_SDRAMC_MODE_NORMAL           (0 << 0)
-#define                 AT91RM9200_SDRAMC_MODE_NOP              (1 << 0)
-#define                 AT91RM9200_SDRAMC_MODE_PRECHARGE        (2 << 0)
-#define                 AT91RM9200_SDRAMC_MODE_LMR              (3 << 0)
-#define                 AT91RM9200_SDRAMC_MODE_REFRESH  (4 << 0)
-#define         AT91RM9200_SDRAMC_DBW           (1   << 4)              /* Data Bus Width */
-#define                 AT91RM9200_SDRAMC_DBW_32        (0 << 4)
-#define                 AT91RM9200_SDRAMC_DBW_16        (1 << 4)
-#define AT91RM9200_SDRAMC_TR            0x94                    /* Refresh Timer Register */
-#define         AT91RM9200_SDRAMC_COUNT (0xfff << 0)            /* Refresh Timer Count */
-#define AT91RM9200_SDRAMC_CR            0x98                    /* Configuration Register */
-#define         AT91RM9200_SDRAMC_NC            (3   <<  0)             /* Number of Column Bits */
-#define                 AT91RM9200_SDRAMC_NC_8  (0 << 0)
-#define                 AT91RM9200_SDRAMC_NC_9  (1 << 0)
-#define                 AT91RM9200_SDRAMC_NC_10 (2 << 0)
-#define                 AT91RM9200_SDRAMC_NC_11 (3 << 0)
-#define         AT91RM9200_SDRAMC_NR            (3   <<  2)             /* Number of Row Bits */
-#define                 AT91RM9200_SDRAMC_NR_11 (0 << 2)
-#define                 AT91RM9200_SDRAMC_NR_12 (1 << 2)
-#define                 AT91RM9200_SDRAMC_NR_13 (2 << 2)
-#define         AT91RM9200_SDRAMC_NB            (1   <<  4)             /* Number of Banks */
-#define                 AT91RM9200_SDRAMC_NB_2  (0 << 4)
-#define                 AT91RM9200_SDRAMC_NB_4  (1 << 4)
-#define         AT91RM9200_SDRAMC_CAS           (3   <<  5)             /* CAS Latency */
-#define                 AT91RM9200_SDRAMC_CAS_2 (2 << 5)
-#define         AT91RM9200_SDRAMC_TWR           (0xf <<  7)             /* Write Recovery Delay */
-#define         AT91RM9200_SDRAMC_TRC           (0xf << 11)             /* Row Cycle Delay */
-#define         AT91RM9200_SDRAMC_TRP           (0xf << 15)             /* Row Precharge Delay */
-#define         AT91RM9200_SDRAMC_TRCD  (0xf << 19)             /* Row to Column Delay */
-#define         AT91RM9200_SDRAMC_TRAS  (0xf << 23)             /* Active to Precharge Delay */
-#define         AT91RM9200_SDRAMC_TXSR  (0xf << 27)             /* Exit Self Refresh to Active Delay */
-#define AT91RM9200_SDRAMC_SRR           0x9c                    /* Self Refresh Register */
-#define AT91RM9200_SDRAMC_LPR           0xa0                    /* Low Power Register */
-#define AT91RM9200_SDRAMC_IER           0xa4                    /* Interrupt Enable Register */
-#define AT91RM9200_SDRAMC_IDR           0xa8                    /* Interrupt Disable Register */
-#define AT91RM9200_SDRAMC_IMR           0xac                    /* Interrupt Mask Register */
-#define AT91RM9200_SDRAMC_ISR           0xb0                    /* Interrupt Status Register */
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
deleted file mode 100644
index 0210797abf2e..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Header file for the Atmel DDR/SDR SDRAM Controller
- *
- * Copyright (C) 2010 Atmel Corporation
- *      Nicolas Ferre <nicolas.ferre@atmel.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91SAM9_DDRSDR_H
-#define AT91SAM9_DDRSDR_H
-#define AT91_DDRSDRC_MR         0x00    /* Mode Register */
-#define         AT91_DDRSDRC_MODE       (0x7 << 0)              /* Command Mode */
-#define                 AT91_DDRSDRC_MODE_NORMAL        0
-#define                 AT91_DDRSDRC_MODE_NOP           1
-#define                 AT91_DDRSDRC_MODE_PRECHARGE     2
-#define                 AT91_DDRSDRC_MODE_LMR           3
-#define                 AT91_DDRSDRC_MODE_REFRESH       4
-#define                 AT91_DDRSDRC_MODE_EXT_LMR       5
-#define                 AT91_DDRSDRC_MODE_DEEP          6
-#define AT91_DDRSDRC_RTR        0x04    /* Refresh Timer Register */
-#define         AT91_DDRSDRC_COUNT      (0xfff << 0)            /* Refresh Timer Counter */
-#define AT91_DDRSDRC_CR         0x08    /* Configuration Register */
-#define         AT91_DDRSDRC_NC         (3 << 0)                /* Number of Column Bits */
-#define                 AT91_DDRSDRC_NC_SDR8    (0 << 0)
-#define                 AT91_DDRSDRC_NC_SDR9    (1 << 0)
-#define                 AT91_DDRSDRC_NC_SDR10   (2 << 0)
-#define                 AT91_DDRSDRC_NC_SDR11   (3 << 0)
-#define                 AT91_DDRSDRC_NC_DDR9    (0 << 0)
-#define                 AT91_DDRSDRC_NC_DDR10   (1 << 0)
-#define                 AT91_DDRSDRC_NC_DDR11   (2 << 0)
-#define                 AT91_DDRSDRC_NC_DDR12   (3 << 0)
-#define         AT91_DDRSDRC_NR         (3 << 2)                /* Number of Row Bits */
-#define                 AT91_DDRSDRC_NR_11      (0 << 2)
-#define                 AT91_DDRSDRC_NR_12      (1 << 2)
-#define                 AT91_DDRSDRC_NR_13      (2 << 2)
-#define                 AT91_DDRSDRC_NR_14      (3 << 2)
-#define         AT91_DDRSDRC_CAS        (7 << 4)                /* CAS Latency */
-#define                 AT91_DDRSDRC_CAS_2      (2 << 4)
-#define                 AT91_DDRSDRC_CAS_3      (3 << 4)
-#define                 AT91_DDRSDRC_CAS_25     (6 << 4)
-#define         AT91_DDRSDRC_RST_DLL    (1 << 7)                /* Reset DLL */
-#define         AT91_DDRSDRC_DICDS      (1 << 8)                /* Output impedance control */
-#define         AT91_DDRSDRC_DIS_DLL    (1 << 9)                /* Disable DLL [SAM9 Only] */
-#define         AT91_DDRSDRC_OCD        (1 << 12)               /* Off-Chip Driver [SAM9 Only] */
-#define         AT91_DDRSDRC_DQMS       (1 << 16)               /* Mask Data is Shared [SAM9 Only] */
-#define         AT91_DDRSDRC_ACTBST     (1 << 18)               /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */
-#define AT91_DDRSDRC_T0PR       0x0C    /* Timing 0 Register */
-#define         AT91_DDRSDRC_TRAS       (0xf <<  0)             /* Active to Precharge delay */
-#define         AT91_DDRSDRC_TRCD       (0xf <<  4)             /* Row to Column delay */
-#define         AT91_DDRSDRC_TWR        (0xf <<  8)             /* Write recovery delay */
-#define         AT91_DDRSDRC_TRC        (0xf << 12)             /* Row cycle delay */
-#define         AT91_DDRSDRC_TRP        (0xf << 16)             /* Row precharge delay */
-#define         AT91_DDRSDRC_TRRD       (0xf << 20)             /* Active BankA to BankB */
-#define         AT91_DDRSDRC_TWTR       (0x7 << 24)             /* Internal Write to Read delay */
-#define         AT91_DDRSDRC_RED_WRRD   (0x1 << 27)             /* Reduce Write to Read Delay [SAM9 Only] */
-#define         AT91_DDRSDRC_TMRD       (0xf << 28)             /* Load mode to active/refresh delay */
-#define AT91_DDRSDRC_T1PR       0x10    /* Timing 1 Register */
-#define         AT91_DDRSDRC_TRFC       (0x1f << 0)             /* Row Cycle Delay */
-#define         AT91_DDRSDRC_TXSNR      (0xff << 8)             /* Exit self-refresh to non-read */
-#define         AT91_DDRSDRC_TXSRD      (0xff << 16)            /* Exit self-refresh to read */
-#define         AT91_DDRSDRC_TXP        (0xf  << 24)            /* Exit power-down delay */
-#define AT91_DDRSDRC_T2PR       0x14    /* Timing 2 Register [SAM9 Only] */
-#define         AT91_DDRSDRC_TXARD      (0xf  << 0)             /* Exit active power down delay to read command in mode "Fast Exit" */
-#define         AT91_DDRSDRC_TXARDS     (0xf  << 4)             /* Exit active power down delay to read command in mode "Slow Exit" */
-#define         AT91_DDRSDRC_TRPA       (0xf  << 8)             /* Row Precharge All delay */
-#define         AT91_DDRSDRC_TRTP       (0x7  << 12)            /* Read to Precharge delay */
-#define AT91_DDRSDRC_LPR        0x1C    /* Low Power Register */
-#define         AT91_DDRSDRC_LPCB       (3 << 0)                /* Low-power Configurations */
-#define                 AT91_DDRSDRC_LPCB_DISABLE               0
-#define                 AT91_DDRSDRC_LPCB_SELF_REFRESH          1
-#define                 AT91_DDRSDRC_LPCB_POWER_DOWN            2
-#define                 AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN       3
-#define         AT91_DDRSDRC_CLKFR      (1 << 2)        /* Clock Frozen */
-#define         AT91_DDRSDRC_PASR       (7 << 4)        /* Partial Array Self Refresh */
-#define         AT91_DDRSDRC_TCSR       (3 << 8)        /* Temperature Compensated Self Refresh */
-#define         AT91_DDRSDRC_DS         (3 << 10)       /* Drive Strength */
-#define         AT91_DDRSDRC_TIMEOUT    (3 << 12)       /* Time to define when Low Power Mode is enabled */
-#define                 AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES       (0 << 12)
-#define                 AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES      (1 << 12)
-#define                 AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES     (2 << 12)
-#define         AT91_DDRSDRC_APDE       (1 << 16)        /* Active power down exit time */
-#define         AT91_DDRSDRC_UPD_MR     (3 << 20)        /* Update load mode register and extended mode register */
-#define AT91_DDRSDRC_MDR        0x20    /* Memory Device Register */
-#define         AT91_DDRSDRC_MD         (3 << 0)                /* Memory Device Type */
-#define                 AT91_DDRSDRC_MD_SDR             0
-#define                 AT91_DDRSDRC_MD_LOW_POWER_SDR   1
-#define                 AT91_DDRSDRC_MD_LOW_POWER_DDR   3
-#define                 AT91_DDRSDRC_MD_DDR2            6       /* [SAM9 Only] */
-#define         AT91_DDRSDRC_DBW        (1 << 4)                /* Data Bus Width */
-#define                 AT91_DDRSDRC_DBW_32BITS         (0 <<  4)
-#define                 AT91_DDRSDRC_DBW_16BITS         (1 <<  4)
-#define AT91_DDRSDRC_DLL        0x24    /* DLL Information Register */
-#define         AT91_DDRSDRC_MDINC      (1 << 0)                /* Master Delay increment */
-#define         AT91_DDRSDRC_MDDEC      (1 << 1)                /* Master Delay decrement */
-#define         AT91_DDRSDRC_MDOVF      (1 << 2)                /* Master Delay Overflow */
-#define         AT91_DDRSDRC_MDVAL      (0xff <<  8)            /* Master Delay value */
-#define AT91_DDRSDRC_HS         0x2C    /* High Speed Register [SAM9 Only] */
-#define         AT91_DDRSDRC_DIS_ATCP_RD        (1 << 2)        /* Anticip read access is disabled */
-#define AT91_DDRSDRC_DELAY(n)   (0x30 + (0x4 * (n)))    /* Delay I/O Register n */
-#define AT91_DDRSDRC_WPMR       0xE4    /* Write Protect Mode Register [SAM9 Only] */
-#define         AT91_DDRSDRC_WP         (1 << 0)                /* Write protect enable */
-#define         AT91_DDRSDRC_WPKEY      (0xffffff << 8)         /* Write protect key */
-#define         AT91_DDRSDRC_KEY        (0x444452 << 8)         /* Write protect key = "DDR" */
-#define AT91_DDRSDRC_WPSR       0xE8    /* Write Protect Status Register [SAM9 Only] */
-#define         AT91_DDRSDRC_WPVS       (1 << 0)                /* Write protect violation status */
-#define         AT91_DDRSDRC_WPVSRC     (0xffff << 8)           /* Write protect violation source */
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
deleted file mode 100644
index 3d085a9a7450..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
- *
- * Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
- *
- * SDRAM Controllers (SDRAMC) - System peripherals registers.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91SAM9_SDRAMC_H
-#define AT91SAM9_SDRAMC_H
-/* SDRAM Controller (SDRAMC) registers */
-#define AT91_SDRAMC_MR          0x00    /* SDRAM Controller Mode Register */
-#define         AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
-#define                 AT91_SDRAMC_MODE_NORMAL         0
-#define                 AT91_SDRAMC_MODE_NOP            1
-#define                 AT91_SDRAMC_MODE_PRECHARGE      2
-#define                 AT91_SDRAMC_MODE_LMR            3
-#define                 AT91_SDRAMC_MODE_REFRESH        4
-#define                 AT91_SDRAMC_MODE_EXT_LMR        5
-#define                 AT91_SDRAMC_MODE_DEEP           6
-#define AT91_SDRAMC_TR          0x04    /* SDRAM Controller Refresh Timer Register */
-#define         AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Counter */
-#define AT91_SDRAMC_CR          0x08    /* SDRAM Controller Configuration Register */
-#define         AT91_SDRAMC_NC          (3 << 0)                /* Number of Column Bits */
-#define                 AT91_SDRAMC_NC_8        (0 << 0)
-#define                 AT91_SDRAMC_NC_9        (1 << 0)
-#define                 AT91_SDRAMC_NC_10       (2 << 0)
-#define                 AT91_SDRAMC_NC_11       (3 << 0)
-#define         AT91_SDRAMC_NR          (3 << 2)                /* Number of Row Bits */
-#define                 AT91_SDRAMC_NR_11       (0 << 2)
-#define                 AT91_SDRAMC_NR_12       (1 << 2)
-#define                 AT91_SDRAMC_NR_13       (2 << 2)
-#define         AT91_SDRAMC_NB          (1 << 4)                /* Number of Banks */
-#define                 AT91_SDRAMC_NB_2        (0 << 4)
-#define                 AT91_SDRAMC_NB_4        (1 << 4)
-#define         AT91_SDRAMC_CAS         (3 << 5)                /* CAS Latency */
-#define                 AT91_SDRAMC_CAS_1       (1 << 5)
-#define                 AT91_SDRAMC_CAS_2       (2 << 5)
-#define                 AT91_SDRAMC_CAS_3       (3 << 5)
-#define         AT91_SDRAMC_DBW         (1 << 7)                /* Data Bus Width */
-#define                 AT91_SDRAMC_DBW_32      (0 << 7)
-#define                 AT91_SDRAMC_DBW_16      (1 << 7)
-#define         AT91_SDRAMC_TWR         (0xf <<  8)             /* Write Recovery Delay */
-#define         AT91_SDRAMC_TRC         (0xf << 12)             /* Row Cycle Delay */
-#define         AT91_SDRAMC_TRP         (0xf << 16)             /* Row Precharge Delay */
-#define         AT91_SDRAMC_TRCD        (0xf << 20)             /* Row to Column Delay */
-#define         AT91_SDRAMC_TRAS        (0xf << 24)             /* Active to Precharge Delay */
-#define         AT91_SDRAMC_TXSR        (0xf << 28)             /* Exit Self Refresh to Active Delay */
-#define AT91_SDRAMC_LPR         0x10    /* SDRAM Controller Low Power Register */
-#define         AT91_SDRAMC_LPCB                (3 << 0)        /* Low-power Configurations */
-#define                 AT91_SDRAMC_LPCB_DISABLE                0
-#define                 AT91_SDRAMC_LPCB_SELF_REFRESH           1
-#define                 AT91_SDRAMC_LPCB_POWER_DOWN             2
-#define                 AT91_SDRAMC_LPCB_DEEP_POWER_DOWN        3
-#define         AT91_SDRAMC_PASR                (7 << 4)        /* Partial Array Self Refresh */
-#define         AT91_SDRAMC_TCSR                (3 << 8)        /* Temperature Compensated Self Refresh */
-#define         AT91_SDRAMC_DS                  (3 << 10)       /* Drive Strength */
-#define         AT91_SDRAMC_TIMEOUT             (3 << 12)       /* Time to define when Low Power Mode is enabled */
-#define                 AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES        (0 << 12)
-#define                 AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES       (1 << 12)
-#define                 AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES      (2 << 12)
-#define AT91_SDRAMC_IER         0x14    /* SDRAM Controller Interrupt Enable Register */
-#define AT91_SDRAMC_IDR         0x18    /* SDRAM Controller Interrupt Disable Register */
-#define AT91_SDRAMC_IMR         0x1C    /* SDRAM Controller Interrupt Mask Register */
-#define AT91_SDRAMC_ISR         0x20    /* SDRAM Controller Interrupt Status Register */
-#define         AT91_SDRAMC_RES         (1 << 0)                /* Refresh Error Status */
-#define AT91_SDRAMC_MDR         0x24    /* SDRAM Memory Device Register */
-#define         AT91_SDRAMC_MD          (3 << 0)                /* Memory Device Type */
-#define                 AT91_SDRAMC_MD_SDRAM            0
-#define                 AT91_SDRAMC_MD_LOW_POWER_SDRAM  1
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h
deleted file mode 100644
index 38dca2bb027f..000000000000
--- a/arch/arm/mach-at91/include/mach/at91x40.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91x40.h
- *
- * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91X40_H
-#define AT91X40_H
-/*
- *      IRQ list.
- */
-#define AT91X40_ID_USART0       2       /* USART port 0 */
-#define AT91X40_ID_USART1       3       /* USART port 1 */
-#define AT91X40_ID_TC0          4       /* Timer/Counter 0 */
-#define AT91X40_ID_TC1          5       /* Timer/Counter 1*/
-#define AT91X40_ID_TC2          6       /* Timer/Counter 2*/
-#define AT91X40_ID_WD           7       /* Watchdog? */
-#define AT91X40_ID_PIOA         8       /* Parallel IO Controller A */
-#define AT91X40_ID_IRQ0         16      /* External IRQ 0 */
-#define AT91X40_ID_IRQ1         17      /* External IRQ 1 */
-#define AT91X40_ID_IRQ2         18      /* External IRQ 2 */
-/*
- * System Peripherals
- */
-#define AT91_BASE_SYS   0xffc00000
-#define AT91_EBI        0xffe00000      /* External Bus Interface */
-#define AT91_SF         0xfff00000      /* Special Function */
-#define AT91_USART1     0xfffcc000      /* USART 1 */
-#define AT91_USART0     0xfffd0000      /* USART 0 */
-#define AT91_TC         0xfffe0000      /* Timer Counter */
-#define AT91_PIOA       0xffff0000      /* PIO Controller A */
-#define AT91_PS         0xffff4000      /* Power Save */
-#define AT91_WD         0xffff8000      /* Watchdog Timer */
-/*
- * The AT91x40 series doesn't have a debug unit like the other AT91 parts.
- * But it does have a chip identify register and extension ID, so define at
- * least these here.
- */
-#define AT91_DBGU_CIDR  (AT91_SF + 0)   /* CIDR in PS segment */
-#define AT91_DBGU_EXID  (AT91_SF + 4)   /* EXID in PS segment */
-/*
- * Support defines for the simple Power Controller module.
- */
-#define AT91_PS_CR      (AT91_PS + 0)   /* PS Control register */
-#define AT91_PS_CR_CPU  (1 << 0)        /* CPU clock disable bit */
-#define AT91X40_MASTER_CLOCK    40000000
-#endif /* AT91X40_H */
diff --git a/arch/arm/mach-at91/include/mach/atmel-mci.h b/arch/arm/mach-at91/include/mach/atmel-mci.h
deleted file mode 100644
index 3069e4135573..000000000000
--- a/arch/arm/mach-at91/include/mach/atmel-mci.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef __MACH_ATMEL_MCI_H
-#define __MACH_ATMEL_MCI_H
-#include <linux/platform_data/dma-atmel.h>
-/**
- * struct mci_dma_data - DMA data for MCI interface
- */
-struct mci_dma_data {
-        struct at_dma_slave     sdata;
-};
-/* accessor macros */
-#define slave_data_ptr(s)       (&(s)->sdata)
-#define find_slave_dev(s)       ((s)->sdata.dma_dev)
-#endif /* __MACH_ATMEL_MCI_H */
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index b27e9ca65653..61914fb35f5d 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -62,7 +62,6 @@
 #define ARCH_EXID_SAMA5D43      0x00000003
 #define ARCH_EXID_SAMA5D44      0x00000004
-#define ARCH_FAMILY_AT91X92     0x09200000
 #define ARCH_FAMILY_AT91SAM9    0x01900000
 #define ARCH_FAMILY_AT91SAM9XE  0x02900000
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index c13797352688..cacbaa52418f 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -24,9 +24,6 @@
 /* sama5d4 */
 #define AT91_BASE_DBGU2 0xfc069000
-#if defined(CONFIG_ARCH_AT91X40)
-#include <mach/at91x40.h>
-#else
 #include <mach/at91rm9200.h>
 #include <mach/at91sam9260.h>
 #include <mach/at91sam9261.h>
@@ -51,8 +48,6 @@
 */
 #define AT91_BASE_SYS   0xffffc000
-#endif
 /*
 * On sama5d4 there is no system controller, we map some needed peripherals
 */
@@ -132,13 +127,8 @@
 * called as part of the generic suspend/resume path.
 */
 #ifndef __ASSEMBLY__
-#ifdef CONFIG_PINCTRL_AT91
 extern void at91_pinctrl_gpio_suspend(void);
 extern void at91_pinctrl_gpio_resume(void);
-#else
-static inline void at91_pinctrl_gpio_suspend(void) {}
-static inline void at91_pinctrl_gpio_resume(void) {}
-#endif
 #endif
 #endif
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
index acb2d890ad7e..4ebb609369e3 100644
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ b/arch/arm/mach-at91/include/mach/uncompress.h
@@ -31,7 +31,6 @@
 void __iomem *at91_uart;
-#if !defined(CONFIG_ARCH_AT91X40)
 static const u32 uarts_rm9200[] = {
        AT91_BASE_DBGU0,
        AT91RM9200_BASE_US0,
@@ -188,12 +187,6 @@ static inline void arch_decomp_setup(void)
        at91_uart = NULL;
 }
-#else
-static inline void arch_decomp_setup(void)
-{
-        at91_uart = NULL;
-}
-#endif
 /*
 * The following code assumes the serial port has already been
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
deleted file mode 100644
index cdb3ec9efd2b..000000000000
--- a/arch/arm/mach-at91/irq.c
+++ /dev/null
@@ -1,296 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/irq.c
- *
- *  Copyright (C) 2004 SAN People
- *  Copyright (C) 2004 ATMEL
- *  Copyright (C) Rick Bronson
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/mm.h>
-#include <linux/bitmap.h>
-#include <linux/types.h>
-#include <linux/irq.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/irqdomain.h>
-#include <linux/err.h>
-#include <linux/slab.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/setup.h>
-#include <asm/exception.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/map.h>
-#include "at91_aic.h"
-void __iomem *at91_aic_base;
-static struct irq_domain *at91_aic_domain;
-static struct device_node *at91_aic_np;
-static unsigned int n_irqs = NR_AIC_IRQS;
-#ifdef CONFIG_PM
-static unsigned long *wakeups;
-static unsigned long *backups;
-#define set_backup(bit) set_bit(bit, backups)
-#define clear_backup(bit) clear_bit(bit, backups)
-static int at91_aic_pm_init(void)
-{
-        backups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
-        if (!backups)
-                return -ENOMEM;
-        wakeups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
-        if (!wakeups) {
-                kfree(backups);
-                return -ENOMEM;
-        }
-        return 0;
-}
-static int at91_aic_set_wake(struct irq_data *d, unsigned value)
-{
-        if (unlikely(d->hwirq >= n_irqs))
-                return -EINVAL;
-        if (value)
-                set_bit(d->hwirq, wakeups);
-        else
-                clear_bit(d->hwirq, wakeups);
-        return 0;
-}
-void at91_irq_suspend(void)
-{
-        at91_aic_write(AT91_AIC_IDCR, *backups);
-        at91_aic_write(AT91_AIC_IECR, *wakeups);
-}
-void at91_irq_resume(void)
-{
-        at91_aic_write(AT91_AIC_IDCR, *wakeups);
-        at91_aic_write(AT91_AIC_IECR, *backups);
-}
-#else
-static inline int at91_aic_pm_init(void)
-{
-        return 0;
-}
-#define set_backup(bit)
-#define clear_backup(bit)
-#define at91_aic_set_wake       NULL
-#endif /* CONFIG_PM */
-asmlinkage void __exception_irq_entry
-at91_aic_handle_irq(struct pt_regs *regs)
-{
-        u32 irqnr;
-        u32 irqstat;
-        irqnr = at91_aic_read(AT91_AIC_IVR);
-        irqstat = at91_aic_read(AT91_AIC_ISR);
-        /*
-         * ISR value is 0 when there is no current interrupt or when there is
-         * a spurious interrupt
-         */
-        if (!irqstat)
-                at91_aic_write(AT91_AIC_EOICR, 0);
-        else
-                handle_IRQ(irqnr, regs);
-}
-static void at91_aic_mask_irq(struct irq_data *d)
-{
-        /* Disable interrupt on AIC */
-        at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq);
-        /* Update ISR cache */
-        clear_backup(d->hwirq);
-}
-static void at91_aic_unmask_irq(struct irq_data *d)
-{
-        /* Enable interrupt on AIC */
-        at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq);
-        /* Update ISR cache */
-        set_backup(d->hwirq);
-}
-static void at91_aic_eoi(struct irq_data *d)
-{
-        /*
-         * Mark end-of-interrupt on AIC, the controller doesn't care about
-         * the value written. Moreover it's a write-only register.
-         */
-        at91_aic_write(AT91_AIC_EOICR, 0);
-}
-static unsigned long *at91_extern_irq;
-u32 at91_get_extern_irq(void)
-{
-        if (!at91_extern_irq)
-                return 0;
-        return *at91_extern_irq;
-}
-#define is_extern_irq(hwirq) test_bit(hwirq, at91_extern_irq)
-static int at91_aic_compute_srctype(struct irq_data *d, unsigned type)
-{
-        int srctype;
-        switch (type) {
-        case IRQ_TYPE_LEVEL_HIGH:
-                srctype = AT91_AIC_SRCTYPE_HIGH;
-                break;
-        case IRQ_TYPE_EDGE_RISING:
-                srctype = AT91_AIC_SRCTYPE_RISING;
-                break;
-        case IRQ_TYPE_LEVEL_LOW:
-                if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq))               /* only supported on external interrupts */
-                        srctype = AT91_AIC_SRCTYPE_LOW;
-                else
-                        srctype = -EINVAL;
-                break;
-        case IRQ_TYPE_EDGE_FALLING:
-                if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq))               /* only supported on external interrupts */
-                        srctype = AT91_AIC_SRCTYPE_FALLING;
-                else
-                        srctype = -EINVAL;
-                break;
-        default:
-                srctype = -EINVAL;
-        }
-        return srctype;
-}
-static int at91_aic_set_type(struct irq_data *d, unsigned type)
-{
-        unsigned int smr;
-        int srctype;
-        srctype = at91_aic_compute_srctype(d, type);
-        if (srctype < 0)
-                return srctype;
-        smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE;
-        at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
-        return 0;
-}
-static struct irq_chip at91_aic_chip = {
-        .name           = "AIC",
-        .irq_mask       = at91_aic_mask_irq,
-        .irq_unmask     = at91_aic_unmask_irq,
-        .irq_set_type   = at91_aic_set_type,
-        .irq_set_wake   = at91_aic_set_wake,
-        .irq_eoi        = at91_aic_eoi,
-};
-static void __init at91_aic_hw_init(unsigned int spu_vector)
-{
-        int i;
-        /*
-         * Perform 8 End Of Interrupt Command to make sure AIC
-         * will not Lock out nIRQ
-         */
-        for (i = 0; i < 8; i++)
-                at91_aic_write(AT91_AIC_EOICR, 0);
-        /*
-         * Spurious Interrupt ID in Spurious Vector Register.
-         * When there is no current interrupt, the IRQ Vector Register
-         * reads the value stored in AIC_SPU
-         */
-        at91_aic_write(AT91_AIC_SPU, spu_vector);
-        /* No debugging in AIC: Debug (Protect) Control Register */
-        at91_aic_write(AT91_AIC_DCR, 0);
-        /* Disable and clear all interrupts initially */
-        at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
-        at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
-}
-/*
- * Initialize the AIC interrupt controller.
- */
-void __init at91_aic_init(unsigned int *priority, unsigned int ext_irq_mask)
-{
-        unsigned int i;
-        int irq_base;
-        at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs)
-                                  * sizeof(*at91_extern_irq), GFP_KERNEL);
-        if (at91_aic_pm_init() || at91_extern_irq == NULL)
-                panic("Unable to allocate bit maps\n");
-        *at91_extern_irq = ext_irq_mask;
-        at91_aic_base = ioremap(AT91_AIC, 512);
-        if (!at91_aic_base)
-                panic("Unable to ioremap AIC registers\n");
-        /* Add irq domain for AIC */
-        irq_base = irq_alloc_descs(-1, 0, n_irqs, 0);
-        if (irq_base < 0) {
-                WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n");
-                irq_base = 0;
-        }
-        at91_aic_domain = irq_domain_add_legacy(at91_aic_np, n_irqs,
-                                                irq_base, 0,
-                                                &irq_domain_simple_ops, NULL);
-        if (!at91_aic_domain)
-                panic("Unable to add AIC irq domain\n");
-        irq_set_default_host(at91_aic_domain);
-        /*
-         * The IVR is used by macro get_irqnr_and_base to read and verify.
-         * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
-         */
-        for (i = 0; i < n_irqs; i++) {
-                /* Put hardware irq number in Source Vector Register: */
-                at91_aic_write(AT91_AIC_SVR(i), NR_IRQS_LEGACY + i);
-                /* Active Low interrupt, with the specified priority */
-                at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
-                irq_set_chip_and_handler(NR_IRQS_LEGACY + i, &at91_aic_chip, handle_fasteoi_irq);
-                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-        }
-        at91_aic_hw_init(n_irqs);
-}
diff --git a/arch/arm/mach-at91/leds.c b/arch/arm/mach-at91/leds.c
deleted file mode 100644
index eb22e3357e87..000000000000
--- a/arch/arm/mach-at91/leds.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * LED driver for Atmel AT91-based boards.
- *
- *  Copyright (C) SAN People (Pty) Ltd
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
-*/
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include "board.h"
-#include "gpio.h"
-/* ------------------------------------------------------------------------- */
-#if defined(CONFIG_NEW_LEDS)
-/*
- * New cross-platform LED support.
- */
-static struct gpio_led_platform_data led_data;
-static struct platform_device at91_gpio_leds_device = {
-        .name                   = "leds-gpio",
-        .id                     = -1,
-        .dev.platform_data      = &led_data,
-};
-void __init at91_gpio_leds(struct gpio_led *leds, int nr)
-{
-        int i;
-        if (!nr)
-                return;
-        for (i = 0; i < nr; i++)
-                at91_set_gpio_output(leds[i].gpio, leds[i].active_low);
-        led_data.leds = leds;
-        led_data.num_leds = nr;
-        platform_device_register(&at91_gpio_leds_device);
-}
-#else
-void __init at91_gpio_leds(struct gpio_led *leds, int nr) {}
-#endif
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 4073ab7f38f3..9b15169a1c62 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -29,10 +29,8 @@
 #include <mach/cpu.h>
 #include <mach/hardware.h>
-#include "at91_aic.h"
 #include "generic.h"
 #include "pm.h"
-#include "gpio.h"
 static void (*at91_pm_standby)(void);
@@ -131,23 +129,7 @@ extern u32 at91_slow_clock_sz;
 static int at91_pm_enter(suspend_state_t state)
 {
-        if (of_have_populated_dt())
+        at91_pinctrl_gpio_suspend();
-                at91_pinctrl_gpio_suspend();
-        else
-                at91_gpio_suspend();
-        if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base) {
-                at91_irq_suspend();
-                pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
-                                /* remember all the always-wake irqs */
-                                (at91_pmc_read(AT91_PMC_PCSR)
-                                                | (1 << AT91_ID_FIQ)
-                                                | (1 << AT91_ID_SYS)
-                                                | (at91_get_extern_irq()))
-                                        & at91_aic_read(AT91_AIC_IMR),
-                                state);
-        }
        switch (state) {
                /*
@@ -212,21 +194,10 @@ static int at91_pm_enter(suspend_state_t state)
                        goto error;
        }
-        if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base)
-                pr_debug("AT91: PM - wakeup %08x\n",
-                         at91_aic_read(AT91_AIC_IPR) &
-                         at91_aic_read(AT91_AIC_IMR));
 error:
        target_state = PM_SUSPEND_ON;
-        if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base)
+        at91_pinctrl_gpio_resume();
-                at91_irq_resume();
-        if (of_have_populated_dt())
-                at91_pinctrl_gpio_resume();
-        else
-                at91_gpio_resume();
        return 0;
 }
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index c5101dcb4fb0..d2c89963af2d 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -14,7 +14,6 @@
 #include <asm/proc-fns.h>
 #include <mach/at91_ramc.h>
-#include <mach/at91rm9200_sdramc.h>
 #ifdef CONFIG_PM
 extern void at91_pm_set_standby(void (*at91_standby)(void));
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 961079250b83..ce25e85720fb 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -42,35 +42,9 @@ void __init at91rm9200_set_type(int type)
                at91_get_soc_subtype(&at91_soc_initdata));
 }
-void __init at91_init_irq_default(void)
-{
-        at91_init_interrupts(at91_boot_soc.default_irq_priority);
-}
-void __init at91_init_interrupts(unsigned int *priority)
-{
-        /* Initialize the AIC interrupt controller */
-        if (IS_ENABLED(CONFIG_OLD_IRQ_AT91))
-                at91_aic_init(priority, at91_boot_soc.extern_irq);
-        /* Enable GPIO interrupts */
-        at91_gpio_irq_setup();
-}
 void __iomem *at91_ramc_base[2];
 EXPORT_SYMBOL_GPL(at91_ramc_base);
-void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
-{
-        if (id < 0 || id > 1) {
-                pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
-                BUG();
-        }
-        at91_ramc_base[id] = ioremap(addr, size);
-        if (!at91_ramc_base[id])
-                panic(pr_fmt("Impossible to ioremap ramc.%d 0x%x\n"), id, addr);
-}
 static struct map_desc sram_desc[2] __initdata;
 void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
@@ -418,7 +392,6 @@ void __init at91_ioremap_matrix(u32 base_addr)
                panic(pr_fmt("Impossible to ioremap at91_matrix_base\n"));
 }
-#if defined(CONFIG_OF) && !defined(CONFIG_ARCH_AT91X40)
 static struct of_device_id ramc_ids[] = {
        { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
        { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
@@ -460,13 +433,6 @@ void __init at91rm9200_dt_initialize(void)
 {
        at91_dt_ramc();
-        /* Init clock subsystem */
-        at91_dt_clock_init();
-        /* Register the processor-specific clocks */
-        if (at91_boot_soc.register_clocks)
-                at91_boot_soc.register_clocks();
        at91_boot_soc.init();
 }
@@ -474,39 +440,6 @@ void __init at91_dt_initialize(void)
 {
        at91_dt_ramc();
-        /* Init clock subsystem */
-        at91_dt_clock_init();
-        /* Register the processor-specific clocks */
-        if (at91_boot_soc.register_clocks)
-                at91_boot_soc.register_clocks();
        if (at91_boot_soc.init)
                at91_boot_soc.init();
 }
-#endif
-void __init at91_initialize(unsigned long main_clock)
-{
-        at91_boot_soc.ioremap_registers();
-        /* Init clock subsystem */
-        at91_clock_init(main_clock);
-        /* Register the processor-specific clocks */
-        at91_boot_soc.register_clocks();
-        at91_boot_soc.init();
-        pinctrl_provide_dummies();
-}
-void __init at91_register_devices(void)
-{
-        at91_boot_soc.register_devices();
-}
-void __init at91_init_time(void)
-{
-        at91_boot_soc.init_time();
-}
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index 9a8fd97a8bef..ae6c0b2f1146 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -6,14 +6,8 @@
 struct at91_init_soc {
        int builtin;
-        u32 extern_irq;
-        unsigned int *default_irq_priority;
        void (*map_io)(void);
-        void (*ioremap_registers)(void);
-        void (*register_clocks)(void);
-        void (*register_devices)(void);
        void (*init)(void);
-        void (*init_time)(void);
 };
 extern struct at91_init_soc at91_boot_soc;
diff --git a/arch/arm/mach-at91/stamp9g20.h b/arch/arm/mach-at91/stamp9g20.h
deleted file mode 100644
index f62c0abca4b4..000000000000
--- a/arch/arm/mach-at91/stamp9g20.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_STAMP9G20_H
-#define __MACH_STAMP9G20_H
-void stamp9g20_init_early(void);
-void stamp9g20_board_init(void);
-#endif
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 2abad742516d..aaeec78c3ec4 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -5,8 +5,56 @@ menuconfig ARCH_BCM
 if ARCH_BCM
+comment "IPROC architected SoCs"
+config ARCH_BCM_IPROC
+        bool
+        select ARM_GIC
+        select CACHE_L2X0
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if SMP
+        select ARM_GLOBAL_TIMER
+        select CLKSRC_MMIO
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_AMBA
+        select PINCTRL
+        help
+          This enables support for systems based on Broadcom IPROC architected SoCs.
+          The IPROC complex contains one or more ARM CPUs along with common
+          core periperals. Application specific SoCs are created by adding a
+          uArchitecture containing peripherals outside of the IPROC complex.
+          Currently supported SoCs are Cygnus.
+config ARCH_BCM_CYGNUS
+        bool "Broadcom Cygnus Support" if ARCH_MULTI_V7
+        select ARCH_BCM_IPROC
+        help
+          Enable support for the Cygnus family,
+          which includes the following variants:
+          BCM11300, BCM11320, BCM11350, BCM11360,
+          BCM58300, BCM58302, BCM58303, BCM58305.
+config ARCH_BCM_5301X
+        bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
+        select ARCH_BCM_IPROC
+        help
+          Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
+          This is a network SoC line mostly used in home routers and
+          wifi access points, it's internal name is Northstar.
+          This inclused the following SoC: BCM53010, BCM53011, BCM53012,
+          BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707,
+          BCM4708 and BCM4709.
+          Do not confuse this with the BCM4760 which is a totally
+          different SoC or with the older BCM47XX and BCM53XX based
+          network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
+comment "KONA architected SoCs"
 config ARCH_BCM_MOBILE
-        bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
+        bool
        select ARCH_REQUIRE_GPIOLIB
        select ARM_ERRATA_754322
        select ARM_ERRATA_775420
@@ -15,16 +63,13 @@ config ARCH_BCM_MOBILE
        select TICK_ONESHOT
        select HAVE_ARM_ARCH_TIMER
        select PINCTRL
+        select ARCH_BCM_MOBILE_SMP if SMP
        help
          This enables support for systems based on Broadcom mobile SoCs.
-if ARCH_BCM_MOBILE
-menu "Broadcom Mobile SoC Selection"
 config ARCH_BCM_281XX
        bool "Broadcom BCM281XX SoC family"
-        default y
+        select ARCH_BCM_MOBILE
        select HAVE_SMP
        help
          Enable support for the BCM281XX family, which includes
@@ -33,7 +78,7 @@ config ARCH_BCM_281XX
 config ARCH_BCM_21664
        bool "Broadcom BCM21664 SoC family"
-        default y
+        select ARCH_BCM_MOBILE
        select HAVE_SMP
        help
          Enable support for the BCM21664 family, which includes
@@ -41,19 +86,18 @@ config ARCH_BCM_21664
 config ARCH_BCM_MOBILE_L2_CACHE
        bool "Broadcom mobile SoC level 2 cache support"
-        depends on (ARCH_BCM_281XX || ARCH_BCM_21664)
+        depends on ARCH_BCM_MOBILE
        default y
        select CACHE_L2X0
        select ARCH_BCM_MOBILE_SMC
 config ARCH_BCM_MOBILE_SMC
        bool
-        depends on ARCH_BCM_281XX || ARCH_BCM_21664
+        depends on ARCH_BCM_MOBILE
 config ARCH_BCM_MOBILE_SMP
-        bool "Broadcom mobile SoC SMP support"
+        bool
-        depends on (ARCH_BCM_281XX || ARCH_BCM_21664) && SMP
+        depends on ARCH_BCM_MOBILE
-        default y
        select HAVE_ARM_SCU
        select ARM_ERRATA_764369
        help
@@ -61,9 +105,7 @@ config ARCH_BCM_MOBILE_SMP
          Provided as an option so SMP support for SoCs of this type
          can be disabled for an SMP-enabled kernel.
-endmenu
+comment "Other Architectures"
-endif
 config ARCH_BCM2835
        bool "Broadcom BCM2835 family" if ARCH_MULTI_V6
@@ -78,27 +120,6 @@ config ARCH_BCM2835
          This enables support for the Broadcom BCM2835 SoC. This SoC is
          used in the Raspberry Pi and Roku 2 devices.
-config ARCH_BCM_5301X
-        bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
-        select ARM_GIC
-        select CACHE_L2X0
-        select HAVE_ARM_SCU if SMP
-        select HAVE_ARM_TWD if SMP
-        select ARM_GLOBAL_TIMER
-        select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
-        help
-          Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
-          This is a network SoC line mostly used in home routers and
-          wifi access points, it's internal name is Northstar.
-          This inclused the following SoC: BCM53010, BCM53011, BCM53012,
-          BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707,
-          BCM4708 and BCM4709.
-          Do not confuse this with the BCM4760 which is a totally
-          different SoC or with the older BCM47XX and BCM53XX based
-          network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
 config ARCH_BCM_63XX
        bool "Broadcom BCM63xx DSL SoC" if ARCH_MULTI_V7
        depends on MMU
@@ -118,13 +139,11 @@ config ARCH_BCM_63XX
 config ARCH_BRCMSTB
        bool "Broadcom BCM7XXX based boards" if ARCH_MULTI_V7
-        depends on MMU
        select ARM_GIC
-        select MIGHT_HAVE_PCI
-        select HAVE_SMP
        select HAVE_ARM_ARCH_TIMER
        select BRCMSTB_GISB_ARB
        select BRCMSTB_L2_IRQ
+        select BCM7120_L2_IRQ
        help
          Say Y if you intend to run the kernel on a Broadcom ARM-based STB
          chipset.
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 300ae4b79ae6..4c38674c73ec 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -10,6 +10,9 @@
 # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
+# Cygnus
+obj-$(CONFIG_ARCH_BCM_CYGNUS) +=  bcm_cygnus.o
 # BCM281XX
 obj-$(CONFIG_ARCH_BCM_281XX)    += board_bcm281xx.o
@@ -38,5 +41,7 @@ obj-$(CONFIG_ARCH_BCM_5301X)	+= bcm_5301x.o
 obj-$(CONFIG_ARCH_BCM_63XX)     := bcm63xx.o
 ifeq ($(CONFIG_ARCH_BRCMSTB),y)
+CFLAGS_platsmp-brcmstb.o        += -march=armv7-a
 obj-y                           += brcmstb.o
+obj-$(CONFIG_SMP)               += headsmp-brcmstb.o platsmp-brcmstb.o
 endif
diff --git a/arch/arm/mach-bcm/bcm_cygnus.c b/arch/arm/mach-bcm/bcm_cygnus.c
new file mode 100644
index 000000000000..30dc58be51b8
--- /dev/null
+++ b/arch/arm/mach-bcm/bcm_cygnus.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <asm/mach/arch.h>
+static const char const *bcm_cygnus_dt_compat[] = {
+        "brcm,cygnus",
+        NULL,
+};
+DT_MACHINE_START(BCM_CYGNUS_DT, "Broadcom Cygnus SoC")
+        .l2c_aux_val    = 0,
+        .l2c_aux_mask   = ~0,
+        .dt_compat = bcm_cygnus_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-bcm/brcmstb.h b/arch/arm/mach-bcm/brcmstb.h
new file mode 100644
index 000000000000..ec0c3d112b36
--- /dev/null
+++ b/arch/arm/mach-bcm/brcmstb.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2013-2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __BRCMSTB_H__
+#define __BRCMSTB_H__
+void brcmstb_secondary_startup(void);
+#endif /* __BRCMSTB_H__ */
diff --git a/arch/arm/mach-bcm/headsmp-brcmstb.S b/arch/arm/mach-bcm/headsmp-brcmstb.S
new file mode 100644
index 000000000000..199c1ea58248
--- /dev/null
+++ b/arch/arm/mach-bcm/headsmp-brcmstb.S
@@ -0,0 +1,33 @@
+/*
+ * SMP boot code for secondary CPUs
+ * Based on arch/arm/mach-tegra/headsmp.S
+ *
+ * Copyright (C) 2010 NVIDIA, Inc.
+ * Copyright (C) 2013-2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <asm/assembler.h>
+#include <linux/linkage.h>
+#include <linux/init.h>
+        .section ".text.head", "ax"
+ENTRY(brcmstb_secondary_startup)
+        /*
+         * Ensure CPU is in a sane state by disabling all IRQs and switching
+         * into SVC mode.
+         */
+        setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0
+        bl      v7_invalidate_l1
+        b       secondary_startup
+ENDPROC(brcmstb_secondary_startup)
diff --git a/arch/arm/mach-bcm/platsmp-brcmstb.c b/arch/arm/mach-bcm/platsmp-brcmstb.c
new file mode 100644
index 000000000000..31c87a284a34
--- /dev/null
+++ b/arch/arm/mach-bcm/platsmp-brcmstb.c
@@ -0,0 +1,329 @@
+/*
+ * Broadcom STB CPU SMP and hotplug support for ARM
+ *
+ * Copyright (C) 2013-2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/printk.h>
+#include <linux/regmap.h>
+#include <linux/smp.h>
+#include <linux/mfd/syscon.h>
+#include <asm/cacheflush.h>
+#include <asm/cp15.h>
+#include <asm/mach-types.h>
+#include <asm/smp_plat.h>
+#include "brcmstb.h"
+enum {
+        ZONE_MAN_CLKEN_MASK             = BIT(0),
+        ZONE_MAN_RESET_CNTL_MASK        = BIT(1),
+        ZONE_MAN_MEM_PWR_MASK           = BIT(4),
+        ZONE_RESERVED_1_MASK            = BIT(5),
+        ZONE_MAN_ISO_CNTL_MASK          = BIT(6),
+        ZONE_MANUAL_CONTROL_MASK        = BIT(7),
+        ZONE_PWR_DN_REQ_MASK            = BIT(9),
+        ZONE_PWR_UP_REQ_MASK            = BIT(10),
+        ZONE_BLK_RST_ASSERT_MASK        = BIT(12),
+        ZONE_PWR_OFF_STATE_MASK         = BIT(25),
+        ZONE_PWR_ON_STATE_MASK          = BIT(26),
+        ZONE_DPG_PWR_STATE_MASK         = BIT(28),
+        ZONE_MEM_PWR_STATE_MASK         = BIT(29),
+        ZONE_RESET_STATE_MASK           = BIT(31),
+        CPU0_PWR_ZONE_CTRL_REG          = 1,
+        CPU_RESET_CONFIG_REG            = 2,
+};
+static void __iomem *cpubiuctrl_block;
+static void __iomem *hif_cont_block;
+static u32 cpu0_pwr_zone_ctrl_reg;
+static u32 cpu_rst_cfg_reg;
+static u32 hif_cont_reg;
+#ifdef CONFIG_HOTPLUG_CPU
+/*
+ * We must quiesce a dying CPU before it can be killed by the boot CPU. Because
+ * one or more cache may be disabled, we must flush to ensure coherency. We
+ * cannot use traditionl completion structures or spinlocks as they rely on
+ * coherency.
+ */
+static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state);
+static int per_cpu_sw_state_rd(u32 cpu)
+{
+        sync_cache_r(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
+        return per_cpu(per_cpu_sw_state, cpu);
+}
+static void per_cpu_sw_state_wr(u32 cpu, int val)
+{
+        dmb();
+        per_cpu(per_cpu_sw_state, cpu) = val;
+        sync_cache_w(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
+}
+#else
+static inline void per_cpu_sw_state_wr(u32 cpu, int val) { }
+#endif
+static void __iomem *pwr_ctrl_get_base(u32 cpu)
+{
+        void __iomem *base = cpubiuctrl_block + cpu0_pwr_zone_ctrl_reg;
+        base += (cpu_logical_map(cpu) * 4);
+        return base;
+}
+static u32 pwr_ctrl_rd(u32 cpu)
+{
+        void __iomem *base = pwr_ctrl_get_base(cpu);
+        return readl_relaxed(base);
+}
+static void pwr_ctrl_wr(u32 cpu, u32 val)
+{
+        void __iomem *base = pwr_ctrl_get_base(cpu);
+        writel(val, base);
+}
+static void cpu_rst_cfg_set(u32 cpu, int set)
+{
+        u32 val;
+        val = readl_relaxed(cpubiuctrl_block + cpu_rst_cfg_reg);
+        if (set)
+                val |= BIT(cpu_logical_map(cpu));
+        else
+                val &= ~BIT(cpu_logical_map(cpu));
+        writel_relaxed(val, cpubiuctrl_block + cpu_rst_cfg_reg);
+}
+static void cpu_set_boot_addr(u32 cpu, unsigned long boot_addr)
+{
+        const int reg_ofs = cpu_logical_map(cpu) * 8;
+        writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs);
+        writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs);
+}
+static void brcmstb_cpu_boot(u32 cpu)
+{
+        /* Mark this CPU as "up" */
+        per_cpu_sw_state_wr(cpu, 1);
+        /*
+         * Set the reset vector to point to the secondary_startup
+         * routine
+         */
+        cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup));
+        /* Unhalt the cpu */
+        cpu_rst_cfg_set(cpu, 0);
+}
+static void brcmstb_cpu_power_on(u32 cpu)
+{
+        /*
+         * The secondary cores power was cut, so we must go through
+         * power-on initialization.
+         */
+        u32 tmp;
+        /* Request zone power up */
+        pwr_ctrl_wr(cpu, ZONE_PWR_UP_REQ_MASK);
+        /* Wait for the power up FSM to complete */
+        do {
+                tmp = pwr_ctrl_rd(cpu);
+        } while (!(tmp & ZONE_PWR_ON_STATE_MASK));
+}
+static int brcmstb_cpu_get_power_state(u32 cpu)
+{
+        int tmp = pwr_ctrl_rd(cpu);
+        return (tmp & ZONE_RESET_STATE_MASK) ? 0 : 1;
+}
+#ifdef CONFIG_HOTPLUG_CPU
+static void brcmstb_cpu_die(u32 cpu)
+{
+        v7_exit_coherency_flush(all);
+        per_cpu_sw_state_wr(cpu, 0);
+        /* Sit and wait to die */
+        wfi();
+        /* We should never get here... */
+        while (1)
+                ;
+}
+static int brcmstb_cpu_kill(u32 cpu)
+{
+        u32 tmp;
+        while (per_cpu_sw_state_rd(cpu))
+                ;
+        /* Program zone reset */
+        pwr_ctrl_wr(cpu, ZONE_RESET_STATE_MASK | ZONE_BLK_RST_ASSERT_MASK |
+                              ZONE_PWR_DN_REQ_MASK);
+        /* Verify zone reset */
+        tmp = pwr_ctrl_rd(cpu);
+        if (!(tmp & ZONE_RESET_STATE_MASK))
+                pr_err("%s: Zone reset bit for CPU %d not asserted!\n",
+                        __func__, cpu);
+        /* Wait for power down */
+        do {
+                tmp = pwr_ctrl_rd(cpu);
+        } while (!(tmp & ZONE_PWR_OFF_STATE_MASK));
+        /* Flush pipeline before resetting CPU */
+        mb();
+        /* Assert reset on the CPU */
+        cpu_rst_cfg_set(cpu, 1);
+        return 1;
+}
+#endif /* CONFIG_HOTPLUG_CPU */
+static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
+{
+        int rc = 0;
+        char *name;
+        struct device_node *syscon_np = NULL;
+        name = "syscon-cpu";
+        syscon_np = of_parse_phandle(np, name, 0);
+        if (!syscon_np) {
+                pr_err("can't find phandle %s\n", name);
+                rc = -EINVAL;
+                goto cleanup;
+        }
+        cpubiuctrl_block = of_iomap(syscon_np, 0);
+        if (!cpubiuctrl_block) {
+                pr_err("iomap failed for cpubiuctrl_block\n");
+                rc = -EINVAL;
+                goto cleanup;
+        }
+        rc = of_property_read_u32_index(np, name, CPU0_PWR_ZONE_CTRL_REG,
+                                        &cpu0_pwr_zone_ctrl_reg);
+        if (rc) {
+                pr_err("failed to read 1st entry from %s property (%d)\n", name,
+                        rc);
+                rc = -EINVAL;
+                goto cleanup;
+        }
+        rc = of_property_read_u32_index(np, name, CPU_RESET_CONFIG_REG,
+                                        &cpu_rst_cfg_reg);
+        if (rc) {
+                pr_err("failed to read 2nd entry from %s property (%d)\n", name,
+                        rc);
+                rc = -EINVAL;
+                goto cleanup;
+        }
+cleanup:
+        of_node_put(syscon_np);
+        return rc;
+}
+static int __init setup_hifcont_regs(struct device_node *np)
+{
+        int rc = 0;
+        char *name;
+        struct device_node *syscon_np = NULL;
+        name = "syscon-cont";
+        syscon_np = of_parse_phandle(np, name, 0);
+        if (!syscon_np) {
+                pr_err("can't find phandle %s\n", name);
+                rc = -EINVAL;
+                goto cleanup;
+        }
+        hif_cont_block = of_iomap(syscon_np, 0);
+        if (!hif_cont_block) {
+                pr_err("iomap failed for hif_cont_block\n");
+                rc = -EINVAL;
+                goto cleanup;
+        }
+        /* Offset is at top of hif_cont_block */
+        hif_cont_reg = 0;
+cleanup:
+        of_node_put(syscon_np);
+        return rc;
+}
+static void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus)
+{
+        int rc;
+        struct device_node *np;
+        char *name;
+        name = "brcm,brcmstb-smpboot";
+        np = of_find_compatible_node(NULL, NULL, name);
+        if (!np) {
+                pr_err("can't find compatible node %s\n", name);
+                return;
+        }
+        rc = setup_hifcpubiuctrl_regs(np);
+        if (rc)
+                return;
+        rc = setup_hifcont_regs(np);
+        if (rc)
+                return;
+}
+static int brcmstb_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        /* Missing the brcm,brcmstb-smpboot DT node? */
+        if (!cpubiuctrl_block || !hif_cont_block)
+                return -ENODEV;
+        /* Bring up power to the core if necessary */
+        if (brcmstb_cpu_get_power_state(cpu) == 0)
+                brcmstb_cpu_power_on(cpu);
+        brcmstb_cpu_boot(cpu);
+        return 0;
+}
+static struct smp_operations brcmstb_smp_ops __initdata = {
+        .smp_prepare_cpus       = brcmstb_cpu_ctrl_setup,
+        .smp_boot_secondary     = brcmstb_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_kill               = brcmstb_cpu_kill,
+        .cpu_die                = brcmstb_cpu_die,
+#endif
+};
+CPU_METHOD_OF_DECLARE(brcmstb_smp, "brcm,brahma-b15", &brcmstb_smp_ops);
diff --git a/arch/arm/mach-berlin/Kconfig b/arch/arm/mach-berlin/Kconfig
index 24f85be71671..3e40a947f3ea 100644
--- a/arch/arm/mach-berlin/Kconfig
+++ b/arch/arm/mach-berlin/Kconfig
@@ -1,10 +1,11 @@
 menuconfig ARCH_BERLIN
        bool "Marvell Berlin SoCs" if ARCH_MULTI_V7
+        select ARCH_HAS_RESET_CONTROLLER
        select ARCH_REQUIRE_GPIOLIB
        select ARM_GIC
-        select GENERIC_IRQ_CHIP
        select DW_APB_ICTL
        select DW_APB_TIMER_OF
+        select GENERIC_IRQ_CHIP
        select PINCTRL
 if ARCH_BERLIN
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 5623131c4f0b..f8f62fbaa915 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -80,8 +80,8 @@ static int da830_evm_usb_ocic_notify(da8xx_ocic_handler_t handler)
                                    IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
                                    "OHCI over-current indicator", NULL);
                if (error)
-                        printk(KERN_ERR "%s: could not request IRQ to watch "
+                        pr_err("%s: could not request IRQ to watch over-current indicator changes\n",
-                               "over-current indicator changes\n", __func__);
+                               __func__);
        } else
                free_irq(irq, NULL);
@@ -145,8 +145,7 @@ static __init void da830_evm_usb_init(void)
        /* USB_REFCLKIN is not used. */
        ret = davinci_cfg_reg(DA830_USB0_DRVVBUS);
        if (ret)
-                pr_warning("%s: USB 2.0 PinMux setup failed: %d\n",
+                pr_warn("%s: USB 2.0 PinMux setup failed: %d\n", __func__, ret);
-                           __func__, ret);
        else {
                /*
                 * TPS2065 switch @ 5V supplies 1 A (sustains 1.5 A),
@@ -154,37 +153,35 @@ static __init void da830_evm_usb_init(void)
                 */
                ret = da8xx_register_usb20(1000, 3);
                if (ret)
-                        pr_warning("%s: USB 2.0 registration failed: %d\n",
+                        pr_warn("%s: USB 2.0 registration failed: %d\n",
-                                   __func__, ret);
+                                __func__, ret);
        }
        ret = davinci_cfg_reg_list(da830_evm_usb11_pins);
        if (ret) {
-                pr_warning("%s: USB 1.1 PinMux setup failed: %d\n",
+                pr_warn("%s: USB 1.1 PinMux setup failed: %d\n", __func__, ret);
-                           __func__, ret);
                return;
        }
        ret = gpio_request(ON_BD_USB_DRV, "ON_BD_USB_DRV");
        if (ret) {
-                printk(KERN_ERR "%s: failed to request GPIO for USB 1.1 port "
+                pr_err("%s: failed to request GPIO for USB 1.1 port power control: %d\n",
-                       "power control: %d\n", __func__, ret);
+                       __func__, ret);
                return;
        }
        gpio_direction_output(ON_BD_USB_DRV, 0);
        ret = gpio_request(ON_BD_USB_OVC, "ON_BD_USB_OVC");
        if (ret) {
-                printk(KERN_ERR "%s: failed to request GPIO for USB 1.1 port "
+                pr_err("%s: failed to request GPIO for USB 1.1 port over-current indicator: %d\n",
-                       "over-current indicator: %d\n", __func__, ret);
+                       __func__, ret);
                return;
        }
        gpio_direction_input(ON_BD_USB_OVC);
        ret = da8xx_register_usb11(&da830_evm_usb11_pdata);
        if (ret)
-                pr_warning("%s: USB 1.1 registration failed: %d\n",
+                pr_warn("%s: USB 1.1 registration failed: %d\n", __func__, ret);
-                           __func__, ret);
 }
 static const short da830_evm_mcasp1_pins[] = {
@@ -252,31 +249,29 @@ static inline void da830_evm_init_mmc(void)
        ret = davinci_cfg_reg_list(da830_evm_mmc_sd_pins);
        if (ret) {
-                pr_warning("da830_evm_init: mmc/sd mux setup failed: %d\n",
+                pr_warn("%s: mmc/sd mux setup failed: %d\n", __func__, ret);
-                                ret);
                return;
        }
        ret = gpio_request(DA830_MMCSD_WP_PIN, "MMC WP");
        if (ret) {
-                pr_warning("da830_evm_init: can not open GPIO %d\n",
+                pr_warn("%s: can not open GPIO %d\n",
-                           DA830_MMCSD_WP_PIN);
+                        __func__, DA830_MMCSD_WP_PIN);
                return;
        }
        gpio_direction_input(DA830_MMCSD_WP_PIN);
        ret = gpio_request(DA830_MMCSD_CD_PIN, "MMC CD\n");
        if (ret) {
-                pr_warning("da830_evm_init: can not open GPIO %d\n",
+                pr_warn("%s: can not open GPIO %d\n",
-                           DA830_MMCSD_CD_PIN);
+                        __func__, DA830_MMCSD_CD_PIN);
                return;
        }
        gpio_direction_input(DA830_MMCSD_CD_PIN);
        ret = da8xx_register_mmcsd0(&da830_evm_mmc_config);
        if (ret) {
-                pr_warning("da830_evm_init: mmc/sd registration failed: %d\n",
+                pr_warn("%s: mmc/sd registration failed: %d\n", __func__, ret);
-                                ret);
                gpio_free(DA830_MMCSD_WP_PIN);
        }
 }
@@ -404,23 +399,21 @@ static inline void da830_evm_init_nand(int mux_mode)
        int ret;
        if (HAS_MMC) {
-                pr_warning("WARNING: both MMC/SD and NAND are "
+                pr_warn("WARNING: both MMC/SD and NAND are enabled, but they share AEMIF pins\n"
-                                "enabled, but they share AEMIF pins.\n"
+                        "\tDisable MMC/SD for NAND support\n");
-                                "\tDisable MMC/SD for NAND support.\n");
                return;
        }
        ret = davinci_cfg_reg_list(da830_evm_emif25_pins);
        if (ret)
-                pr_warning("da830_evm_init: emif25 mux setup failed: %d\n",
+                pr_warn("%s: emif25 mux setup failed: %d\n", __func__, ret);
-                                ret);
        ret = platform_device_register(&da830_evm_nand_device);
        if (ret)
-                pr_warning("da830_evm_init: NAND device not registered.\n");
+                pr_warn("%s: NAND device not registered\n", __func__);
        if (davinci_aemif_setup(&da830_evm_nand_device))
-                pr_warn("%s: Cannot configure AEMIF.\n", __func__);
+                pr_warn("%s: Cannot configure AEMIF\n", __func__);
        gpio_direction_output(mux_mode, 1);
 }
@@ -435,12 +428,11 @@ static inline void da830_evm_init_lcdc(int mux_mode)
        ret = davinci_cfg_reg_list(da830_lcdcntl_pins);
        if (ret)
-                pr_warning("da830_evm_init: lcdcntl mux setup failed: %d\n",
+                pr_warn("%s: lcdcntl mux setup failed: %d\n", __func__, ret);
-                                ret);
        ret = da8xx_register_lcdc(&sharp_lcd035q3dg01_pdata);
        if (ret)
-                pr_warning("da830_evm_init: lcd setup failed: %d\n", ret);
+                pr_warn("%s: lcd setup failed: %d\n", __func__, ret);
        gpio_direction_output(mux_mode, 0);
 }
@@ -598,22 +590,19 @@ static __init void da830_evm_init(void)
        ret = da830_register_gpio();
        if (ret)
-                pr_warn("da830_evm_init: GPIO init failed: %d\n", ret);
+                pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
        ret = da830_register_edma(da830_edma_rsv);
        if (ret)
-                pr_warning("da830_evm_init: edma registration failed: %d\n",
+                pr_warn("%s: edma registration failed: %d\n", __func__, ret);
-                                ret);
        ret = davinci_cfg_reg_list(da830_i2c0_pins);
        if (ret)
-                pr_warning("da830_evm_init: i2c0 mux setup failed: %d\n",
+                pr_warn("%s: i2c0 mux setup failed: %d\n", __func__, ret);
-                                ret);
        ret = da8xx_register_i2c(0, &da830_evm_i2c_0_pdata);
        if (ret)
-                pr_warning("da830_evm_init: i2c0 registration failed: %d\n",
+                pr_warn("%s: i2c0 registration failed: %d\n", __func__, ret);
-                                ret);
        da830_evm_usb_init();
@@ -622,18 +611,16 @@ static __init void da830_evm_init(void)
        ret = davinci_cfg_reg_list(da830_cpgmac_pins);
        if (ret)
-                pr_warning("da830_evm_init: cpgmac mux setup failed: %d\n",
+                pr_warn("%s: cpgmac mux setup failed: %d\n", __func__, ret);
-                                ret);
        ret = da8xx_register_emac();
        if (ret)
-                pr_warning("da830_evm_init: emac registration failed: %d\n",
+                pr_warn("%s: emac registration failed: %d\n", __func__, ret);
-                                ret);
        ret = da8xx_register_watchdog();
        if (ret)
-                pr_warning("da830_evm_init: watchdog registration failed: %d\n",
+                pr_warn("%s: watchdog registration failed: %d\n",
-                                ret);
+                        __func__, ret);
        davinci_serial_init(da8xx_serial_device);
        i2c_register_board_info(1, da830_evm_i2c_devices,
@@ -641,8 +628,7 @@ static __init void da830_evm_init(void)
        ret = davinci_cfg_reg_list(da830_evm_mcasp1_pins);
        if (ret)
-                pr_warning("da830_evm_init: mcasp1 mux setup failed: %d\n",
+                pr_warn("%s: mcasp1 mux setup failed: %d\n", __func__, ret);
-                                ret);
        da8xx_register_mcasp(1, &da830_evm_snd_data);
@@ -650,18 +636,17 @@ static __init void da830_evm_init(void)
        ret = da8xx_register_rtc();
        if (ret)
-                pr_warning("da830_evm_init: rtc setup failed: %d\n", ret);
+                pr_warn("%s: rtc setup failed: %d\n", __func__, ret);
        ret = spi_register_board_info(da830evm_spi_info,
                                      ARRAY_SIZE(da830evm_spi_info));
        if (ret)
-                pr_warn("%s: spi info registration failed: %d\n", __func__,
+                pr_warn("%s: spi info registration failed: %d\n",
-                        ret);
+                        __func__, ret);
        ret = da8xx_register_spi_bus(0, ARRAY_SIZE(da830evm_spi_info));
        if (ret)
-                pr_warning("da830_evm_init: spi 0 registration failed: %d\n",
+                pr_warn("%s: spi 0 registration failed: %d\n", __func__, ret);
-                           ret);
 }
 #ifdef CONFIG_SERIAL_8250_CONSOLE
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index fa11415e906a..6b5a97da9fe3 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -452,8 +452,7 @@ static void da850_evm_ui_keys_init(unsigned gpio)
        for (i = 0; i < DA850_N_UI_PB; i++) {
                button = &da850_evm_ui_keys[i];
                button->code = KEY_F8 - i;
-                button->desc = (char *)
+                button->desc = da850_evm_ui_exp[DA850_EVM_UI_EXP_PB8 + i];
-                                da850_evm_ui_exp[DA850_EVM_UI_EXP_PB8 + i];
                button->gpio = gpio + DA850_EVM_UI_EXP_PB8 + i;
        }
 }
@@ -628,15 +627,13 @@ static void da850_evm_bb_keys_init(unsigned gpio)
        struct gpio_keys_button *button;
        button = &da850_evm_bb_keys[0];
-        button->desc = (char *)
+        button->desc = da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_PB1];
-                da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_PB1];
        button->gpio = gpio + DA850_EVM_BB_EXP_USER_PB1;
        for (i = 0; i < DA850_N_BB_USER_SW; i++) {
                button = &da850_evm_bb_keys[i + 1];
                button->code = SW_LID + i;
-                button->desc = (char *)
+                button->desc = da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_SW1 + i];
-                                da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_SW1 + i];
                button->gpio = gpio + DA850_EVM_BB_EXP_USER_SW1 + i;
        }
 }
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 06d63d5651f3..b46b4d25f93e 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -294,7 +294,7 @@ static struct vpbe_output dm355evm_vpbe_outputs[] = {
                .default_mode   = "ntsc",
                .num_modes      = ARRAY_SIZE(dm355evm_enc_preset_timing),
                .modes          = dm355evm_enc_preset_timing,
-                .if_params      = V4L2_MBUS_FMT_FIXED,
+                .if_params      = MEDIA_BUS_FMT_FIXED,
        },
 };
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index e08a8684ead2..a756003595e9 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -485,7 +485,7 @@ static struct vpbe_output dm365evm_vpbe_outputs[] = {
                .default_mode   = "ntsc",
                .num_modes      = ARRAY_SIZE(dm365evm_enc_std_timing),
                .modes          = dm365evm_enc_std_timing,
-                .if_params      = V4L2_MBUS_FMT_FIXED,
+                .if_params      = MEDIA_BUS_FMT_FIXED,
        },
        {
                .output         = {
@@ -498,7 +498,7 @@ static struct vpbe_output dm365evm_vpbe_outputs[] = {
                .default_mode   = "480p59_94",
                .num_modes      = ARRAY_SIZE(dm365evm_enc_preset_timing),
                .modes          = dm365evm_enc_preset_timing,
-                .if_params      = V4L2_MBUS_FMT_FIXED,
+                .if_params      = MEDIA_BUS_FMT_FIXED,
        },
 };
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index e583e58b5e1e..1a0898c1c17e 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -767,9 +767,8 @@ static __init void davinci_evm_init(void)
        if (HAS_ATA) {
                if (HAS_NAND || HAS_NOR)
-                        pr_warning("WARNING: both IDE and Flash are "
+                        pr_warn("WARNING: both IDE and Flash are enabled, but they share AEMIF pins\n"
-                                "enabled, but they share AEMIF pins.\n"
+                                "\tDisable IDE for NAND/NOR support\n");
-                                "\tDisable IDE for NAND/NOR support.\n");
                davinci_init_ide();
        } else if (HAS_NAND || HAS_NOR) {
                davinci_cfg_reg(DM644X_HPIEN_DISABLE);
@@ -780,13 +779,12 @@ static __init void davinci_evm_init(void)
                        platform_device_register(&davinci_evm_nandflash_device);
                        if (davinci_aemif_setup(&davinci_evm_nandflash_device))
-                                pr_warn("%s: Cannot configure AEMIF.\n",
+                                pr_warn("%s: Cannot configure AEMIF\n",
                                        __func__);
                        evm_leds[7].default_trigger = "nand-disk";
                        if (HAS_NOR)
-                                pr_warning("WARNING: both NAND and NOR flash "
+                                pr_warn("WARNING: both NAND and NOR flash are enabled; disable one of them.\n");
-                                        "are enabled; disable one of them.\n");
                } else if (HAS_NOR)
                        platform_device_register(&davinci_evm_norflash_device);
        }
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index 96fc00a167f5..8cfbfe084535 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -8,6 +8,8 @@
 * any kind, whether express or implied.
 */
+#define pr_fmt(fmt) "MityOMAPL138: " fmt
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/console.h>
@@ -107,7 +109,7 @@ static void mityomapl138_cpufreq_init(const char *partnum)
        ret = da850_register_cpufreq("pll0_sysclk3");
        if (ret)
-                pr_warning("cpufreq registration failed: %d\n", ret);
+                pr_warn("cpufreq registration failed: %d\n", ret);
 }
 #else
 static void mityomapl138_cpufreq_init(const char *partnum) { }
@@ -121,33 +123,31 @@ static void read_factory_config(struct memory_accessor *a, void *context)
        ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
        if (ret != sizeof(struct factory_config)) {
-                pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n",
+                pr_warn("Read Factory Config Failed: %d\n", ret);
-                                ret);
                goto bad_config;
        }
        if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
-                pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n",
+                pr_warn("Factory Config Magic Wrong (%X)\n",
-                                factory_config.magic);
+                        factory_config.magic);
                goto bad_config;
        }
        if (factory_config.version != FACTORY_CONFIG_VERSION) {
-                pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n",
+                pr_warn("Factory Config Version Wrong (%X)\n",
-                                factory_config.version);
+                        factory_config.version);
                goto bad_config;
        }
-        pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac);
+        pr_info("Found MAC = %pM\n", factory_config.mac);
        if (is_valid_ether_addr(factory_config.mac))
                memcpy(soc_info->emac_pdata->mac_addr,
                        factory_config.mac, ETH_ALEN);
        else
-                pr_warning("MityOMAPL138: Invalid MAC found "
+                pr_warn("Invalid MAC found in factory config block\n");
-                                "in factory config block\n");
        partnum = factory_config.partnum;
-        pr_info("MityOMAPL138: Part Number = %s\n", partnum);
+        pr_info("Part Number = %s\n", partnum);
 bad_config:
        /* default maximum speed is valid for all platforms */
@@ -435,7 +435,7 @@ static void __init mityomapl138_setup_nand(void)
                                 ARRAY_SIZE(mityomapl138_devices));
        if (davinci_aemif_setup(&mityomapl138_nandflash_device))
-                pr_warn("%s: Cannot configure AEMIF.\n", __func__);
+                pr_warn("%s: Cannot configure AEMIF\n", __func__);
 }
 static const short mityomap_mii_pins[] = {
@@ -478,7 +478,7 @@ static void __init mityomapl138_config_emac(void)
        }
        if (ret) {
-                pr_warning("mii/rmii mux setup failed: %d\n", ret);
+                pr_warn("mii/rmii mux setup failed: %d\n", ret);
                return;
        }
@@ -489,7 +489,7 @@ static void __init mityomapl138_config_emac(void)
        ret = da8xx_register_emac();
        if (ret)
-                pr_warning("emac registration failed: %d\n", ret);
+                pr_warn("emac registration failed: %d\n", ret);
 }
 static struct davinci_pm_config da850_pm_pdata = {
@@ -511,21 +511,21 @@ static void __init mityomapl138_init(void)
        /* for now, no special EDMA channels are reserved */
        ret = da850_register_edma(NULL);
        if (ret)
-                pr_warning("edma registration failed: %d\n", ret);
+                pr_warn("edma registration failed: %d\n", ret);
        ret = da8xx_register_watchdog();
        if (ret)
-                pr_warning("watchdog registration failed: %d\n", ret);
+                pr_warn("watchdog registration failed: %d\n", ret);
        davinci_serial_init(da8xx_serial_device);
        ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
        if (ret)
-                pr_warning("i2c0 registration failed: %d\n", ret);
+                pr_warn("i2c0 registration failed: %d\n", ret);
        ret = pmic_tps65023_init();
        if (ret)
-                pr_warning("TPS65023 PMIC init failed: %d\n", ret);
+                pr_warn("TPS65023 PMIC init failed: %d\n", ret);
        mityomapl138_setup_nand();
@@ -537,22 +537,21 @@ static void __init mityomapl138_init(void)
        ret = da8xx_register_spi_bus(1,
                                     ARRAY_SIZE(mityomapl138_spi_flash_info));
        if (ret)
-                pr_warning("spi 1 registration failed: %d\n", ret);
+                pr_warn("spi 1 registration failed: %d\n", ret);
        mityomapl138_config_emac();
        ret = da8xx_register_rtc();
        if (ret)
-                pr_warning("rtc setup failed: %d\n", ret);
+                pr_warn("rtc setup failed: %d\n", ret);
        ret = da8xx_register_cpuidle();
        if (ret)
-                pr_warning("cpuidle registration failed: %d\n", ret);
+                pr_warn("cpuidle registration failed: %d\n", ret);
        ret = da850_register_pm(&da850_pm_device);
        if (ret)
-                pr_warning("da850_evm_init: suspend registration failed: %d\n",
+                pr_warn("suspend registration failed: %d\n", ret);
-                                ret);
 }
 #ifdef CONFIG_SERIAL_8250_CONSOLE
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index bb680af98374..8fcdcf87c47c 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -183,9 +183,8 @@ static __init void davinci_ntosd2_init(void)
        if (HAS_ATA) {
                if (HAS_NAND)
-                        pr_warning("WARNING: both IDE and Flash are "
+                        pr_warn("WARNING: both IDE and Flash are enabled, but they share AEMIF pins\n"
-                                "enabled, but they share AEMIF pins.\n"
+                                "\tDisable IDE for NAND/NOR support\n");
-                                "\tDisable IDE for NAND/NOR support.\n");
                davinci_init_ide();
        } else if (HAS_NAND) {
                davinci_cfg_reg(DM644X_HPIEN_DISABLE);
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 985e5fd00fb2..c70bb0a4dfb4 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -564,7 +564,7 @@ int davinci_set_refclk_rate(unsigned long rate)
        refclk = clk_get(NULL, "ref");
        if (IS_ERR(refclk)) {
-                pr_err("%s: failed to get reference clock.\n", __func__);
+                pr_err("%s: failed to get reference clock\n", __func__);
                return PTR_ERR(refclk);
        }
diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c
index f1ac1c94ac0f..b4675fc28f83 100644
--- a/arch/arm/mach-davinci/cpuidle.c
+++ b/arch/arm/mach-davinci/cpuidle.c
@@ -66,7 +66,6 @@ static struct cpuidle_driver davinci_idle_driver = {
                .enter                  = davinci_enter_idle,
                .exit_latency           = 10,
                .target_residency       = 10000,
-                .flags                  = CPUIDLE_FLAG_TIME_VALID,
                .name                   = "DDR SR",
                .desc                   = "WFI and DDR Self Refresh",
        },
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 2f3ed3a58d57..9cbeda798584 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -785,14 +785,13 @@ static struct resource dm355_v4l2_disp_resources[] = {
        },
 };
-static int dm355_vpbe_setup_pinmux(enum v4l2_mbus_pixelcode if_type,
+static int dm355_vpbe_setup_pinmux(u32 if_type, int field)
-                            int field)
 {
        switch (if_type) {
-        case V4L2_MBUS_FMT_SGRBG8_1X8:
+        case MEDIA_BUS_FMT_SGRBG8_1X8:
                davinci_cfg_reg(DM355_VOUT_FIELD_G70);
                break;
-        case V4L2_MBUS_FMT_YUYV10_1X20:
+        case MEDIA_BUS_FMT_YUYV10_1X20:
                if (field)
                        davinci_cfg_reg(DM355_VOUT_FIELD);
                else
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 0ae8114f5cc9..e3a3c54b6832 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1306,16 +1306,15 @@ static struct resource dm365_v4l2_disp_resources[] = {
        },
 };
-static int dm365_vpbe_setup_pinmux(enum v4l2_mbus_pixelcode if_type,
+static int dm365_vpbe_setup_pinmux(u32 if_type, int field)
-                            int field)
 {
        switch (if_type) {
-        case V4L2_MBUS_FMT_SGRBG8_1X8:
+        case MEDIA_BUS_FMT_SGRBG8_1X8:
                davinci_cfg_reg(DM365_VOUT_FIELD_G81);
                davinci_cfg_reg(DM365_VOUT_COUTL_EN);
                davinci_cfg_reg(DM365_VOUT_COUTH_EN);
                break;
-        case V4L2_MBUS_FMT_YUYV10_1X20:
+        case MEDIA_BUS_FMT_YUYV10_1X20:
                if (field)
                        davinci_cfg_reg(DM365_VOUT_FIELD);
                else
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index f34a8dcdae2b..a8eb909a2b6c 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -15,6 +15,9 @@
 *
 * Copyright (C) 2008 Texas Instruments.
 */
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/spinlock.h>
@@ -46,7 +49,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
        }
        if (index >= soc_info->pinmux_pins_num) {
-                printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
+                pr_err("Invalid pin mux index: %lu (%lu)\n",
                       index, soc_info->pinmux_pins_num);
                dump_stack();
                return -ENODEV;
@@ -55,7 +58,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
        cfg = &soc_info->pinmux_pins[index];
        if (cfg->name == NULL) {
-                printk(KERN_ERR "No entry for the specified index\n");
+                pr_err("No entry for the specified index\n");
                return -ENODEV;
        }
@@ -82,15 +85,15 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
        if (warn) {
 #ifdef CONFIG_DAVINCI_MUX_WARNINGS
-                printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
+                pr_warn("initialized %s\n", cfg->name);
 #endif
        }
 #ifdef CONFIG_DAVINCI_MUX_DEBUG
        if (cfg->debug || warn) {
-                printk(KERN_WARNING "MUX: Setting register %s\n", cfg->name);
+                pr_warn("Setting register %s\n", cfg->name);
-                printk(KERN_WARNING "      %s (0x%08x) = 0x%08x -> 0x%08x\n",
+                pr_warn("   %s (0x%08x) = 0x%08x -> 0x%08x\n",
-                       cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
+                        cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
        }
 #endif
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 24ad30f32ae3..160c9602f490 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -342,8 +342,6 @@ void __init davinci_timer_init(void)
        struct davinci_soc_info *soc_info = &davinci_soc_info;
        unsigned int clockevent_id;
        unsigned int clocksource_id;
-        static char err[] __initdata = KERN_ERR
-                "%s: can't register clocksource!\n";
        int i;
        clockevent_id = soc_info->timer_info->clockevent_id;
@@ -364,12 +362,12 @@ void __init davinci_timer_init(void)
                /* Only bottom timers can use compare regs */
                if (IS_TIMER_TOP(clockevent_id))
-                        pr_warning("davinci_timer_init: Invalid use"
+                        pr_warn("%s: Invalid use of system timers.  Results unpredictable.\n",
-                                " of system timers.  Results unpredictable.\n");
+                                __func__);
                else if ((dtip[event_timer].cmp_off == 0)
                                || (dtip[event_timer].cmp_irq == 0))
-                        pr_warning("davinci_timer_init:  Invalid timer instance"
+                        pr_warn("%s: Invalid timer instance setup.  Results unpredictable.\n",
-                                " setup.  Results unpredictable.\n");
+                                __func__);
                else {
                        timers[TID_CLOCKEVENT].opts |= TIMER_OPTS_USE_COMPARE;
                        clockevent_davinci.features = CLOCK_EVT_FEAT_ONESHOT;
@@ -389,7 +387,8 @@ void __init davinci_timer_init(void)
        clocksource_davinci.name = id_to_name[clocksource_id];
        if (clocksource_register_hz(&clocksource_davinci,
                                    davinci_clock_tick_rate))
-                printk(err, clocksource_davinci.name);
+                pr_err("%s: can't register clocksource!\n",
+                       clocksource_davinci.name);
        sched_clock_register(davinci_read_sched_clock, 32,
                          davinci_clock_tick_rate);
diff --git a/arch/arm/mach-ebsa110/include/mach/io.h b/arch/arm/mach-ebsa110/include/mach/io.h
index 11bb0799424b..69975784acfa 100644
--- a/arch/arm/mach-ebsa110/include/mach/io.h
+++ b/arch/arm/mach-ebsa110/include/mach/io.h
@@ -29,9 +29,9 @@ u8  __readb(const volatile void __iomem *addr);
 u16 __readw(const volatile void __iomem *addr);
 u32 __readl(const volatile void __iomem *addr);
-void __writeb(u8  val, void __iomem *addr);
+void __writeb(u8  val, volatile void __iomem *addr);
-void __writew(u16 val, void __iomem *addr);
+void __writew(u16 val, volatile void __iomem *addr);
-void __writel(u32 val, void __iomem *addr);
+void __writel(u32 val, volatile void __iomem *addr);
 /*
 * Argh, someone forgot the IOCS16 line.  We therefore have to handle
@@ -62,20 +62,31 @@ void __writel(u32 val, void __iomem *addr);
 #define writew(v,b)             __writew(v,b)
 #define writel(v,b)             __writel(v,b)
+#define insb insb
 extern void insb(unsigned int port, void *buf, int sz);
+#define insw insw
 extern void insw(unsigned int port, void *buf, int sz);
+#define insl insl
 extern void insl(unsigned int port, void *buf, int sz);
+#define outsb outsb
 extern void outsb(unsigned int port, const void *buf, int sz);
+#define outsw outsw
 extern void outsw(unsigned int port, const void *buf, int sz);
+#define outsl outsl
 extern void outsl(unsigned int port, const void *buf, int sz);
 /* can't support writesb atm */
-extern void writesw(void __iomem *addr, const void *data, int wordlen);
+#define writesw writesw
-extern void writesl(void __iomem *addr, const void *data, int longlen);
+extern void writesw(volatile void __iomem *addr, const void *data, int wordlen);
+#define writesl writesl
+extern void writesl(volatile void __iomem *addr, const void *data, int longlen);
 /* can't support readsb atm */
-extern void readsw(const void __iomem *addr, void *data, int wordlen);
+#define readsw readsw
-extern void readsl(const void __iomem *addr, void *data, int longlen);
+extern void readsw(const volatile void __iomem *addr, void *data, int wordlen);
+#define readsl readsl
+extern void readsl(const volatile void __iomem *addr, void *data, int longlen);
 #endif
diff --git a/arch/arm/mach-ebsa110/io.c b/arch/arm/mach-ebsa110/io.c
index 756cc377a73d..b57980b435fd 100644
--- a/arch/arm/mach-ebsa110/io.c
+++ b/arch/arm/mach-ebsa110/io.c
@@ -102,7 +102,7 @@ EXPORT_SYMBOL(__readb);
 EXPORT_SYMBOL(__readw);
 EXPORT_SYMBOL(__readl);
-void readsw(const void __iomem *addr, void *data, int len)
+void readsw(const volatile void __iomem *addr, void *data, int len)
 {
        void __iomem *a = __isamem_convert_addr(addr);
@@ -112,7 +112,7 @@ void readsw(const void __iomem *addr, void *data, int len)
 }
 EXPORT_SYMBOL(readsw);
-void readsl(const void __iomem *addr, void *data, int len)
+void readsl(const volatile void __iomem *addr, void *data, int len)
 {
        void __iomem *a = __isamem_convert_addr(addr);
@@ -122,7 +122,7 @@ void readsl(const void __iomem *addr, void *data, int len)
 }
 EXPORT_SYMBOL(readsl);
-void __writeb(u8 val, void __iomem *addr)
+void __writeb(u8 val, volatile void __iomem *addr)
 {
        void __iomem *a = __isamem_convert_addr(addr);
@@ -132,7 +132,7 @@ void __writeb(u8 val, void __iomem *addr)
                __raw_writeb(val, a);
 }
-void __writew(u16 val, void __iomem *addr)
+void __writew(u16 val, volatile void __iomem *addr)
 {
        void __iomem *a = __isamem_convert_addr(addr);
@@ -142,7 +142,7 @@ void __writew(u16 val, void __iomem *addr)
        __raw_writew(val, a);
 }
-void __writel(u32 val, void __iomem *addr)
+void __writel(u32 val, volatile void __iomem *addr)
 {
        void __iomem *a = __isamem_convert_addr(addr);
@@ -157,7 +157,7 @@ EXPORT_SYMBOL(__writeb);
 EXPORT_SYMBOL(__writew);
 EXPORT_SYMBOL(__writel);
-void writesw(void __iomem *addr, const void *data, int len)
+void writesw(volatile void __iomem *addr, const void *data, int len)
 {
        void __iomem *a = __isamem_convert_addr(addr);
@@ -167,7 +167,7 @@ void writesw(void __iomem *addr, const void *data, int len)
 }
 EXPORT_SYMBOL(writesw);
-void writesl(void __iomem *addr, const void *data, int len)
+void writesl(volatile void __iomem *addr, const void *data, int len)
 {
        void __iomem *a = __isamem_convert_addr(addr);
diff --git a/arch/arm/mach-ep93xx/dma.c b/arch/arm/mach-ep93xx/dma.c
index d8bfd02f5047..88a4c9b089a5 100644
--- a/arch/arm/mach-ep93xx/dma.c
+++ b/arch/arm/mach-ep93xx/dma.c
@@ -66,11 +66,15 @@ static struct ep93xx_dma_platform_data ep93xx_dma_m2p_data = {
        .num_channels           = ARRAY_SIZE(ep93xx_dma_m2p_channels),
 };
+static u64 ep93xx_dma_m2p_mask = DMA_BIT_MASK(32);
 static struct platform_device ep93xx_dma_m2p_device = {
        .name                   = "ep93xx-dma-m2p",
        .id                     = -1,
        .dev                    = {
-                .platform_data  = &ep93xx_dma_m2p_data,
+                .platform_data          = &ep93xx_dma_m2p_data,
+                .dma_mask               = &ep93xx_dma_m2p_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
        },
 };
@@ -93,11 +97,15 @@ static struct ep93xx_dma_platform_data ep93xx_dma_m2m_data = {
        .num_channels           = ARRAY_SIZE(ep93xx_dma_m2m_channels),
 };
+static u64 ep93xx_dma_m2m_mask = DMA_BIT_MASK(32);
 static struct platform_device ep93xx_dma_m2m_device = {
        .name                   = "ep93xx-dma-m2m",
        .id                     = -1,
        .dev                    = {
-                .platform_data  = &ep93xx_dma_m2m_data,
+                .platform_data          = &ep93xx_dma_m2m_data,
+                .dma_mask               = &ep93xx_dma_m2m_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
        },
 };
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 2d0240f241b8..b9e3f1c61baf 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -24,6 +24,7 @@ menuconfig ARCH_EXYNOS
        select PM_GENERIC_DOMAINS if PM_RUNTIME
        select S5P_DEV_MFC
        select SRAM
+        select MFD_SYSCON
        help
          Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
@@ -75,6 +76,11 @@ config SOC_EXYNOS4412
        default y
        depends on ARCH_EXYNOS4
+config SOC_EXYNOS4415
+        bool "SAMSUNG EXYNOS4415"
+        default y
+        depends on ARCH_EXYNOS4
 config SOC_EXYNOS5250
        bool "SAMSUNG EXYNOS5250"
        default y
@@ -123,4 +129,9 @@ config EXYNOS5420_MCPM
          This is needed to provide CPU and cluster power management
          on Exynos5420 implementing big.LITTLE.
+config EXYNOS_CPU_SUSPEND
+        bool
+        select ARM_CPU_SUSPEND
+        default PM_SLEEP || ARM_EXYNOS_CPUIDLE
 endif
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 27ae6144679c..bcefb5473ee4 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -11,16 +11,15 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include -I$(srctree)
 obj-$(CONFIG_ARCH_EXYNOS)       += exynos.o pmu.o exynos-smc.o firmware.o
-obj-$(CONFIG_PM_SLEEP)          += pm.o sleep.o
+obj-$(CONFIG_EXYNOS_CPU_SUSPEND) += pm.o sleep.o
+obj-$(CONFIG_PM_SLEEP)          += suspend.o
 obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
-obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
-CFLAGS_hotplug.o                += -march=armv7-a
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_exynos-smc.o             :=-Wa,-march=armv7-a$(plus_sec)
+AFLAGS_sleep.o                  :=-Wa,-march=armv7-a$(plus_sec)
 obj-$(CONFIG_EXYNOS5420_MCPM)   += mcpm-exynos.o
 CFLAGS_mcpm-exynos.o            += -march=armv7-a
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 47b904b3b973..865f878063cc 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,7 +12,6 @@
 #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
 #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
-#include <linux/reboot.h>
 #include <linux/of.h>
 #define EXYNOS3250_SOC_ID       0xE3472000
@@ -111,11 +110,19 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK)
 #define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \
                          soc_is_exynos5420() || soc_is_exynos5800())
+extern u32 cp15_save_diag;
+extern u32 cp15_save_power;
 extern void __iomem *sysram_ns_base_addr;
 extern void __iomem *sysram_base_addr;
 extern void __iomem *pmu_base_addr;
 void exynos_sysram_init(void);
+enum {
+        FW_DO_IDLE_SLEEP,
+        FW_DO_IDLE_AFTR,
+};
 void exynos_firmware_init(void);
 extern u32 exynos_get_eint_wake_mask(void);
@@ -127,34 +134,20 @@ static inline void exynos_pm_init(void) {}
 #endif
 extern void exynos_cpu_resume(void);
+extern void exynos_cpu_resume_ns(void);
 extern struct smp_operations exynos_smp_ops;
-extern void exynos_cpu_die(unsigned int cpu);
-/* PMU(Power Management Unit) support */
-#define PMU_TABLE_END   (-1U)
-enum sys_powerdown {
-        SYS_AFTR,
-        SYS_LPA,
-        SYS_SLEEP,
-        NUM_SYS_POWERDOWN,
-};
-struct exynos_pmu_conf {
-        unsigned int offset;
-        unsigned int val[NUM_SYS_POWERDOWN];
-};
-extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
 extern void exynos_cpu_power_down(int cpu);
 extern void exynos_cpu_power_up(int cpu);
 extern int  exynos_cpu_power_state(int cpu);
 extern void exynos_cluster_power_down(int cluster);
 extern void exynos_cluster_power_up(int cluster);
 extern int  exynos_cluster_power_state(int cluster);
+extern void exynos_cpu_save_register(void);
+extern void exynos_cpu_restore_register(void);
+extern void exynos_pm_central_suspend(void);
+extern int exynos_pm_central_resume(void);
 extern void exynos_enter_aftr(void);
 extern void s5p_init_cpu(void __iomem *cpuid_addr);
diff --git a/arch/arm/mach-exynos/exynos-pmu.h b/arch/arm/mach-exynos/exynos-pmu.h
new file mode 100644
index 000000000000..a2ab0d52b230
--- /dev/null
+++ b/arch/arm/mach-exynos/exynos-pmu.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Header for EXYNOS PMU Driver support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __EXYNOS_PMU_H
+#define __EXYNOS_PMU_H
+enum sys_powerdown {
+        SYS_AFTR,
+        SYS_LPA,
+        SYS_SLEEP,
+        NUM_SYS_POWERDOWN,
+};
+extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
+#endif /* __EXYNOS_PMU_H */
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 6b283eb3202e..c13d0837fa8c 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -41,41 +41,11 @@ static struct map_desc exynos4_iodesc[] __initdata = {
                .length         = SZ_64K,
                .type           = MT_DEVICE,
        }, {
-                .virtual        = (unsigned long)S3C_VA_TIMER,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_WATCHDOG,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
                .virtual        = (unsigned long)S5P_VA_SROMC,
                .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
                .length         = SZ_4K,
                .type           = MT_DEVICE,
        }, {
-                .virtual        = (unsigned long)S5P_VA_SYSTIMER,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_GIC_CPU,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
-                .length         = SZ_64K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_GIC_DIST,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
-                .length         = SZ_64K,
-                .type           = MT_DEVICE,
-        }, {
                .virtual        = (unsigned long)S5P_VA_CMU,
                .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
                .length         = SZ_128K,
@@ -86,11 +56,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
                .length         = SZ_8K,
                .type           = MT_DEVICE,
        }, {
-                .virtual        = (unsigned long)S5P_VA_L2CC,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
                .virtual        = (unsigned long)S5P_VA_DMC0,
                .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
                .length         = SZ_64K,
@@ -100,11 +65,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
                .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
                .length         = SZ_64K,
                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
        },
 };
@@ -115,16 +75,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
                .length         = SZ_64K,
                .type           = MT_DEVICE,
        }, {
-                .virtual        = (unsigned long)S3C_VA_TIMER,
-                .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_WATCHDOG,
-                .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
                .virtual        = (unsigned long)S5P_VA_SROMC,
                .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
                .length         = SZ_4K,
@@ -137,28 +87,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
        },
 };
-static void exynos_restart(enum reboot_mode mode, const char *cmd)
-{
-        struct device_node *np;
-        u32 val = 0x1;
-        void __iomem *addr = pmu_base_addr + EXYNOS_SWRESET;
-        if (of_machine_is_compatible("samsung,exynos5440")) {
-                u32 status;
-                np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
-                addr = of_iomap(np, 0) + 0xbc;
-                status = __raw_readl(addr);
-                addr = of_iomap(np, 0) + 0xcc;
-                val = __raw_readl(addr);
-                val = (val & 0xffff0000) | (status & 0xffff);
-        }
-        __raw_writel(val, addr);
-}
 static struct platform_device exynos_cpuidle = {
        .name              = "exynos_cpuidle",
 #ifdef CONFIG_ARM_EXYNOS_CPUIDLE
@@ -252,6 +180,7 @@ static const struct of_device_id exynos_dt_pmu_match[] = {
        { .compatible = "samsung,exynos4210-pmu" },
        { .compatible = "samsung,exynos4212-pmu" },
        { .compatible = "samsung,exynos4412-pmu" },
+        { .compatible = "samsung,exynos4415-pmu" },
        { .compatible = "samsung,exynos5250-pmu" },
        { .compatible = "samsung,exynos5260-pmu" },
        { .compatible = "samsung,exynos5410-pmu" },
@@ -318,7 +247,10 @@ static void __init exynos_dt_machine_init(void)
                exynos_sysram_init();
        if (of_machine_is_compatible("samsung,exynos4210") ||
-                        of_machine_is_compatible("samsung,exynos5250"))
+            of_machine_is_compatible("samsung,exynos4212") ||
+            (of_machine_is_compatible("samsung,exynos4412") &&
+             of_machine_is_compatible("samsung,trats2")) ||
+            of_machine_is_compatible("samsung,exynos5250"))
                platform_device_register(&exynos_cpuidle);
        platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
@@ -333,6 +265,7 @@ static char const *exynos_dt_compat[] __initconst = {
        "samsung,exynos4210",
        "samsung,exynos4212",
        "samsung,exynos4412",
+        "samsung,exynos4415",
        "samsung,exynos5",
        "samsung,exynos5250",
        "samsung,exynos5260",
@@ -378,7 +311,6 @@ DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
        .init_machine   = exynos_dt_machine_init,
        .init_late      = exynos_init_late,
        .dt_compat      = exynos_dt_compat,
-        .restart        = exynos_restart,
        .reserve        = exynos_reserve,
        .dt_fixup       = exynos_dt_fixup,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index e8797bb78871..766f57d2f029 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -14,16 +14,44 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <asm/cacheflush.h>
+#include <asm/cputype.h>
 #include <asm/firmware.h>
+#include <asm/suspend.h>
 #include <mach/map.h>
 #include "common.h"
 #include "smc.h"
-static int exynos_do_idle(void)
+#define EXYNOS_SLEEP_MAGIC      0x00000bad
+#define EXYNOS_AFTR_MAGIC       0xfcba0d10
+#define EXYNOS_BOOT_ADDR        0x8
+#define EXYNOS_BOOT_FLAG        0xc
+static void exynos_save_cp15(void)
 {
-        exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
+        /* Save Power control and Diagnostic registers */
+        asm ("mrc p15, 0, %0, c15, c0, 0\n"
+             "mrc p15, 0, %1, c15, c0, 1\n"
+             : "=r" (cp15_save_power), "=r" (cp15_save_diag)
+             : : "cc");
+}
+static int exynos_do_idle(unsigned long mode)
+{
+        switch (mode) {
+        case FW_DO_IDLE_AFTR:
+                if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
+                        exynos_save_cp15();
+                __raw_writel(virt_to_phys(exynos_cpu_resume_ns),
+                             sysram_ns_base_addr + 0x24);
+                __raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
+                exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);
+                break;
+        case FW_DO_IDLE_SLEEP:
+                exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
+        }
        return 0;
 }
@@ -69,10 +97,43 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
        return 0;
 }
+static int exynos_cpu_suspend(unsigned long arg)
+{
+        flush_cache_all();
+        outer_flush_all();
+        exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
+        pr_info("Failed to suspend the system\n");
+        writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
+        return 1;
+}
+static int exynos_suspend(void)
+{
+        if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
+                exynos_save_cp15();
+        writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
+        writel(virt_to_phys(exynos_cpu_resume_ns),
+                sysram_ns_base_addr + EXYNOS_BOOT_ADDR);
+        return cpu_suspend(0, exynos_cpu_suspend);
+}
+static int exynos_resume(void)
+{
+        writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
+        return 0;
+}
 static const struct firmware_ops exynos_firmware_ops = {
-        .do_idle                = exynos_do_idle,
+        .do_idle                = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_do_idle : NULL,
        .set_cpu_boot_addr      = exynos_set_cpu_boot_addr,
        .cpu_boot               = exynos_cpu_boot,
+        .suspend                = IS_ENABLED(CONFIG_PM_SLEEP) ? exynos_suspend : NULL,
+        .resume                 = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_resume : NULL,
 };
 void __init exynos_firmware_init(void)
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
deleted file mode 100644
index 4d86961a7957..000000000000
--- a/arch/arm/mach-exynos/hotplug.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- *  Cloned from linux/arch/arm/mach-realview/hotplug.c
- *
- *  Copyright (C) 2002 ARM Ltd.
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
-#include <linux/io.h>
-#include <asm/cacheflush.h>
-#include <asm/cp15.h>
-#include <asm/smp_plat.h>
-#include "common.h"
-#include "regs-pmu.h"
-static inline void cpu_leave_lowpower(void)
-{
-        unsigned int v;
-        asm volatile(
-        "mrc    p15, 0, %0, c1, c0, 0\n"
-        "       orr     %0, %0, %1\n"
-        "       mcr     p15, 0, %0, c1, c0, 0\n"
-        "       mrc     p15, 0, %0, c1, c0, 1\n"
-        "       orr     %0, %0, %2\n"
-        "       mcr     p15, 0, %0, c1, c0, 1\n"
-          : "=&r" (v)
-          : "Ir" (CR_C), "Ir" (0x40)
-          : "cc");
-}
-static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
-{
-        u32 mpidr = cpu_logical_map(cpu);
-        u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
-        for (;;) {
-                /* Turn the CPU off on next WFI instruction. */
-                exynos_cpu_power_down(core_id);
-                wfi();
-                if (pen_release == core_id) {
-                        /*
-                         * OK, proper wakeup, we're done
-                         */
-                        break;
-                }
-                /*
-                 * Getting here, means that we have come out of WFI without
-                 * having been woken up - this shouldn't happen
-                 *
-                 * Just note it happening - when we're woken, we can report
-                 * its occurrence.
-                 */
-                (*spurious)++;
-        }
-}
-/*
- * platform-specific code to shutdown a CPU
- *
- * Called with IRQs disabled
- */
-void __ref exynos_cpu_die(unsigned int cpu)
-{
-        int spurious = 0;
-        v7_exit_coherency_flush(louis);
-        platform_do_lowpower(cpu, &spurious);
-        /*
-         * bring this CPU back into the world of cache
-         * coherency, and then restore interrupts
-         */
-        cpu_leave_lowpower();
-        if (spurious)
-                pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
-}
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index f0b7e92bad6c..1ad3f496ef56 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -30,40 +30,17 @@
 #define EXYNOS4_PA_CMU                  0x10030000
 #define EXYNOS5_PA_CMU                  0x10010000
-#define EXYNOS4_PA_SYSTIMER             0x10050000
-#define EXYNOS4_PA_WATCHDOG             0x10060000
-#define EXYNOS5_PA_WATCHDOG             0x101D0000
 #define EXYNOS4_PA_DMC0                 0x10400000
 #define EXYNOS4_PA_DMC1                 0x10410000
-#define EXYNOS4_PA_COMBINER             0x10440000
-#define EXYNOS5_PA_COMBINER             0x10440000
-#define EXYNOS4_PA_GIC_CPU              0x10480000
-#define EXYNOS4_PA_GIC_DIST             0x10490000
-#define EXYNOS5_PA_GIC_CPU              0x10482000
-#define EXYNOS5_PA_GIC_DIST             0x10481000
 #define EXYNOS4_PA_COREPERI             0x10500000
 #define EXYNOS4_PA_L2CC                 0x10502000
 #define EXYNOS4_PA_SROMC                0x12570000
 #define EXYNOS5_PA_SROMC                0x12250000
-#define EXYNOS4_PA_HSPHY                0x125B0000
-#define EXYNOS4_PA_UART                 0x13800000
-#define EXYNOS5_PA_UART                 0x12C00000
-#define EXYNOS4_PA_TIMER                0x139D0000
-#define EXYNOS5_PA_TIMER                0x12DD0000
 /* Compatibility UART */
 #define EXYNOS5440_PA_UART0             0x000B0000
-#define S3C_VA_UARTx(x)                 (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index dc9a764a7c37..b0d3c2e876fb 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -15,6 +15,7 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/of_address.h>
+#include <linux/syscore_ops.h>
 #include <asm/cputype.h>
 #include <asm/cp15.h>
@@ -30,6 +31,8 @@
 #define EXYNOS5420_USE_ARM_CORE_DOWN_STATE      BIT(29)
 #define EXYNOS5420_USE_L2_COMMON_UP_STATE       BIT(30)
+static void __iomem *ns_sram_base_addr;
 /*
 * The common v7_exit_coherency_flush API could not be used because of the
 * Erratum 799270 workaround. This macro is the same as the common one (in
@@ -318,10 +321,26 @@ static const struct of_device_id exynos_dt_mcpm_match[] = {
        {},
 };
+static void exynos_mcpm_setup_entry_point(void)
+{
+        /*
+         * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
+         * as part of secondary_cpu_start().  Let's redirect it to the
+         * mcpm_entry_point(). This is done during both secondary boot-up as
+         * well as system resume.
+         */
+        __raw_writel(0xe59f0000, ns_sram_base_addr);     /* ldr r0, [pc, #0] */
+        __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx  r0 */
+        __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);
+}
+static struct syscore_ops exynos_mcpm_syscore_ops = {
+        .resume = exynos_mcpm_setup_entry_point,
+};
 static int __init exynos_mcpm_init(void)
 {
        struct device_node *node;
-        void __iomem *ns_sram_base_addr;
        unsigned int value, i;
        int ret;
@@ -387,16 +406,9 @@ static int __init exynos_mcpm_init(void)
                pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i));
        }
-        /*
+        exynos_mcpm_setup_entry_point();
-         * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
-         * as part of secondary_cpu_start().  Let's redirect it to the
-         * mcpm_entry_point().
-         */
-        __raw_writel(0xe59f0000, ns_sram_base_addr);     /* ldr r0, [pc, #0] */
-        __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx  r0 */
-        __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);
-        iounmap(ns_sram_base_addr);
+        register_syscore_ops(&exynos_mcpm_syscore_ops);
        return ret;
 }
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 41ae28d69e6f..7a1ebfeeeeb8 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -22,6 +22,7 @@
 #include <linux/of_address.h>
 #include <asm/cacheflush.h>
+#include <asm/cp15.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 #include <asm/firmware.h>
@@ -33,6 +34,88 @@
 extern void exynos4_secondary_startup(void);
+/*
+ * Set or clear the USE_DELAYED_RESET_ASSERTION option, set on Exynos4 SoCs
+ * during hot-(un)plugging CPUx.
+ *
+ * The feature can be cleared safely during first boot of secondary CPU.
+ *
+ * Exynos4 SoCs require setting USE_DELAYED_RESET_ASSERTION during powering
+ * down a CPU so the CPU idle clock down feature could properly detect global
+ * idle state when CPUx is off.
+ */
+static void exynos_set_delayed_reset_assertion(u32 core_id, bool enable)
+{
+        if (soc_is_exynos4()) {
+                unsigned int tmp;
+                tmp = pmu_raw_readl(EXYNOS_ARM_CORE_OPTION(core_id));
+                if (enable)
+                        tmp |= S5P_USE_DELAYED_RESET_ASSERTION;
+                else
+                        tmp &= ~(S5P_USE_DELAYED_RESET_ASSERTION);
+                pmu_raw_writel(tmp, EXYNOS_ARM_CORE_OPTION(core_id));
+        }
+}
+#ifdef CONFIG_HOTPLUG_CPU
+static inline void cpu_leave_lowpower(u32 core_id)
+{
+        unsigned int v;
+        asm volatile(
+        "mrc    p15, 0, %0, c1, c0, 0\n"
+        "       orr     %0, %0, %1\n"
+        "       mcr     p15, 0, %0, c1, c0, 0\n"
+        "       mrc     p15, 0, %0, c1, c0, 1\n"
+        "       orr     %0, %0, %2\n"
+        "       mcr     p15, 0, %0, c1, c0, 1\n"
+          : "=&r" (v)
+          : "Ir" (CR_C), "Ir" (0x40)
+          : "cc");
+         exynos_set_delayed_reset_assertion(core_id, false);
+}
+static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
+{
+        u32 mpidr = cpu_logical_map(cpu);
+        u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        for (;;) {
+                /* Turn the CPU off on next WFI instruction. */
+                exynos_cpu_power_down(core_id);
+                /*
+                 * Exynos4 SoCs require setting
+                 * USE_DELAYED_RESET_ASSERTION so the CPU idle
+                 * clock down feature could properly detect
+                 * global idle state when CPUx is off.
+                 */
+                exynos_set_delayed_reset_assertion(core_id, true);
+                wfi();
+                if (pen_release == core_id) {
+                        /*
+                         * OK, proper wakeup, we're done
+                         */
+                        break;
+                }
+                /*
+                 * Getting here, means that we have come out of WFI without
+                 * having been woken up - this shouldn't happen
+                 *
+                 * Just note it happening - when we're woken, we can report
+                 * its occurrence.
+                 */
+                (*spurious)++;
+        }
+}
+#endif /* CONFIG_HOTPLUG_CPU */
 /**
 * exynos_core_power_down : power down the specified cpu
 * @cpu : the cpu to power down
@@ -43,6 +126,18 @@ extern void exynos4_secondary_startup(void);
 */
 void exynos_cpu_power_down(int cpu)
 {
+        if (cpu == 0 && (of_machine_is_compatible("samsung,exynos5420") ||
+                of_machine_is_compatible("samsung,exynos5800"))) {
+                /*
+                 * Bypass power down for CPU0 during suspend. Check for
+                 * the SYS_PWR_REG value to decide if we are suspending
+                 * the system.
+                 */
+                int val = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
+                if (!(val & S5P_CORE_LOCAL_PWR_EN))
+                        return;
+        }
        pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
 }
@@ -121,6 +216,26 @@ static inline void __iomem *cpu_boot_reg(int cpu)
 }
 /*
+ * Set wake up by local power mode and execute software reset for given core.
+ *
+ * Currently this is needed only when booting secondary CPU on Exynos3250.
+ */
+static void exynos_core_restart(u32 core_id)
+{
+        u32 val;
+        if (!of_machine_is_compatible("samsung,exynos3250"))
+                return;
+        val = pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(core_id));
+        val |= S5P_CORE_WAKEUP_FROM_LOCAL_CFG;
+        pmu_raw_writel(val, EXYNOS_ARM_CORE_STATUS(core_id));
+        pr_info("CPU%u: Software reset\n", core_id);
+        pmu_raw_writel(EXYNOS_CORE_PO_RESET(core_id), EXYNOS_SWRESET);
+}
+/*
 * Write pen_release in a way that is guaranteed to be visible to all
 * observers, irrespective of whether they're taking part in coherency
 * or not.  This is necessary for the hotplug code to work reliably.
@@ -196,6 +311,9 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
                        return -ETIMEDOUT;
                }
        }
+        exynos_core_restart(core_id);
        /*
         * Send the secondary CPU a soft interrupt, thereby causing
         * the boot monitor to read the system wide flags register,
@@ -237,6 +355,9 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
                udelay(10);
        }
+        /* No harm if this is called during first boot of secondary CPU */
+        exynos_set_delayed_reset_assertion(core_id, false);
        /*
         * now the secondary core is starting up let it run its
         * calibrations, then wait for it to finish
@@ -318,6 +439,33 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
        }
 }
+#ifdef CONFIG_HOTPLUG_CPU
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+static void exynos_cpu_die(unsigned int cpu)
+{
+        int spurious = 0;
+        u32 mpidr = cpu_logical_map(cpu);
+        u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        v7_exit_coherency_flush(louis);
+        platform_do_lowpower(cpu, &spurious);
+        /*
+         * bring this CPU back into the world of cache
+         * coherency, and then restore interrupts
+         */
+        cpu_leave_lowpower(core_id);
+        if (spurious)
+                pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
+}
+#endif /* CONFIG_HOTPLUG_CPU */
 struct smp_operations exynos_smp_ops __initdata = {
        .smp_init_cpus          = exynos_smp_init_cpus,
        .smp_prepare_cpus       = exynos_smp_prepare_cpus,
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index abefacb45976..86f3ecd88f78 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
 *              http://www.samsung.com
 *
 * EXYNOS - Power Management support
@@ -15,109 +15,45 @@
 #include <linux/init.h>
 #include <linux/suspend.h>
-#include <linux/syscore_ops.h>
 #include <linux/cpu_pm.h>
 #include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
 #include <linux/err.h>
-#include <linux/clk.h>
-#include <asm/cacheflush.h>
+#include <asm/firmware.h>
-#include <asm/hardware/cache-l2x0.h>
 #include <asm/smp_scu.h>
 #include <asm/suspend.h>
 #include <plat/pm-common.h>
-#include <plat/regs-srom.h>
-#include <mach/map.h>
 #include "common.h"
+#include "exynos-pmu.h"
 #include "regs-pmu.h"
 #include "regs-sys.h"
-/**
+static inline void __iomem *exynos_boot_vector_addr(void)
- * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
- * @hwirq: Hardware IRQ signal of the GIC
- * @mask: Mask in PMU wake-up mask register
- */
-struct exynos_wkup_irq {
-        unsigned int hwirq;
-        u32 mask;
-};
-static struct sleep_save exynos5_sys_save[] = {
-        SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
-};
-static struct sleep_save exynos_core_save[] = {
-        /* SROM side */
-        SAVE_ITEM(S5P_SROM_BW),
-        SAVE_ITEM(S5P_SROM_BC0),
-        SAVE_ITEM(S5P_SROM_BC1),
-        SAVE_ITEM(S5P_SROM_BC2),
-        SAVE_ITEM(S5P_SROM_BC3),
-};
-/*
- * GIC wake-up support
- */
-static u32 exynos_irqwake_intmask = 0xffffffff;
-static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
-        { 76, BIT(1) }, /* RTC alarm */
-        { 77, BIT(2) }, /* RTC tick */
-        { /* sentinel */ },
-};
-static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
-        { 75, BIT(1) }, /* RTC alarm */
-        { 76, BIT(2) }, /* RTC tick */
-        { /* sentinel */ },
-};
-static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
 {
-        const struct exynos_wkup_irq *wkup_irq;
+        if (samsung_rev() == EXYNOS4210_REV_1_1)
+                return pmu_base_addr + S5P_INFORM7;
-        if (soc_is_exynos5250())
+        else if (samsung_rev() == EXYNOS4210_REV_1_0)
-                wkup_irq = exynos5250_wkup_irq;
+                return sysram_base_addr + 0x24;
-        else
+        return pmu_base_addr + S5P_INFORM0;
-                wkup_irq = exynos4_wkup_irq;
-        while (wkup_irq->mask) {
-                if (wkup_irq->hwirq == data->hwirq) {
-                        if (!state)
-                                exynos_irqwake_intmask |= wkup_irq->mask;
-                        else
-                                exynos_irqwake_intmask &= ~wkup_irq->mask;
-                        return 0;
-                }
-                ++wkup_irq;
-        }
-        return -ENOENT;
 }
-#define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
+static inline void __iomem *exynos_boot_vector_flag(void)
-                        pmu_base_addr + S5P_INFORM7 : \
+{
-                        (samsung_rev() == EXYNOS4210_REV_1_0 ? \
+        if (samsung_rev() == EXYNOS4210_REV_1_1)
-                        (sysram_base_addr + 0x24) : \
+                return pmu_base_addr + S5P_INFORM6;
-                        pmu_base_addr + S5P_INFORM0))
+        else if (samsung_rev() == EXYNOS4210_REV_1_0)
-#define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
+                return sysram_base_addr + 0x20;
-                        pmu_base_addr + S5P_INFORM6 : \
+        return pmu_base_addr + S5P_INFORM1;
-                        (samsung_rev() == EXYNOS4210_REV_1_0 ? \
+}
-                        (sysram_base_addr + 0x20) : \
-                        pmu_base_addr + S5P_INFORM1))
 #define S5P_CHECK_AFTR  0xFCBA0D10
-#define S5P_CHECK_SLEEP 0x00000BAD
 /* For Cortex-A9 Diagnostic and Power control register */
 static unsigned int save_arm_register[2];
-static void exynos_cpu_save_register(void)
+void exynos_cpu_save_register(void)
 {
        unsigned long tmp;
@@ -134,7 +70,7 @@ static void exynos_cpu_save_register(void)
        save_arm_register[1] = tmp;
 }
-static void exynos_cpu_restore_register(void)
+void exynos_cpu_restore_register(void)
 {
        unsigned long tmp;
@@ -153,7 +89,7 @@ static void exynos_cpu_restore_register(void)
                      : "cc");
 }
-static void exynos_pm_central_suspend(void)
+void exynos_pm_central_suspend(void)
 {
        unsigned long tmp;
@@ -161,9 +97,13 @@ static void exynos_pm_central_suspend(void)
        tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
        tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
        pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+        /* Setting SEQ_OPTION register */
+        pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
+                       S5P_CENTRAL_SEQ_OPTION);
 }
-static int exynos_pm_central_resume(void)
+int exynos_pm_central_resume(void)
 {
        unsigned long tmp;
@@ -194,17 +134,26 @@ static void exynos_set_wakeupmask(long mask)
 static void exynos_cpu_set_boot_vector(long flags)
 {
-        __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
+        __raw_writel(virt_to_phys(exynos_cpu_resume),
-        __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
+                     exynos_boot_vector_addr());
+        __raw_writel(flags, exynos_boot_vector_flag());
 }
 static int exynos_aftr_finisher(unsigned long flags)
 {
+        int ret;
        exynos_set_wakeupmask(0x0000ff3e);
-        exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
        /* Set value of power down register for aftr mode */
        exynos_sys_powerdown_conf(SYS_AFTR);
-        cpu_do_idle();
+        ret = call_firmware_op(do_idle, FW_DO_IDLE_AFTR);
+        if (ret == -ENOSYS) {
+                if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
+                        exynos_cpu_save_register();
+                exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
+                cpu_do_idle();
+        }
        return 1;
 }
@@ -214,196 +163,16 @@ void exynos_enter_aftr(void)
        cpu_pm_enter();
        exynos_pm_central_suspend();
-        if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
-                exynos_cpu_save_register();
        cpu_suspend(0, exynos_aftr_finisher);
        if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
                scu_enable(S5P_VA_SCU);
-                exynos_cpu_restore_register();
+                if (call_firmware_op(resume) == -ENOSYS)
+                        exynos_cpu_restore_register();
        }
        exynos_pm_central_resume();
        cpu_pm_exit();
 }
-static int exynos_cpu_suspend(unsigned long arg)
-{
-#ifdef CONFIG_CACHE_L2X0
-        outer_flush_all();
-#endif
-        if (soc_is_exynos5250())
-                flush_cache_all();
-        /* issue the standby signal into the pm unit. */
-        cpu_do_idle();
-        pr_info("Failed to suspend the system\n");
-        return 1; /* Aborting suspend */
-}
-static void exynos_pm_prepare(void)
-{
-        unsigned int tmp;
-        /* Set wake-up mask registers */
-        pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
-        pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
-        s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
-        if (soc_is_exynos5250()) {
-                s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
-                /* Disable USE_RETENTION of JPEG_MEM_OPTION */
-                tmp = pmu_raw_readl(EXYNOS5_JPEG_MEM_OPTION);
-                tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
-                pmu_raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
-        }
-        /* Set value of power down register for sleep mode */
-        exynos_sys_powerdown_conf(SYS_SLEEP);
-        pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
-        /* ensure at least INFORM0 has the resume address */
-        pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
-}
-static int exynos_pm_suspend(void)
-{
-        unsigned long tmp;
-        exynos_pm_central_suspend();
-        /* Setting SEQ_OPTION register */
-        tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
-        pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
-        if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
-                exynos_cpu_save_register();
-        return 0;
-}
-static void exynos_pm_resume(void)
-{
-        if (exynos_pm_central_resume())
-                goto early_wakeup;
-        if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
-                exynos_cpu_restore_register();
-        /* For release retention */
-        pmu_raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
-        pmu_raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
-        pmu_raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
-        pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
-        pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
-        pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
-        pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
-        if (soc_is_exynos5250())
-                s3c_pm_do_restore(exynos5_sys_save,
-                        ARRAY_SIZE(exynos5_sys_save));
-        s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
-        if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
-                scu_enable(S5P_VA_SCU);
-early_wakeup:
-        /* Clear SLEEP mode set in INFORM1 */
-        pmu_raw_writel(0x0, S5P_INFORM1);
-        return;
-}
-static struct syscore_ops exynos_pm_syscore_ops = {
-        .suspend        = exynos_pm_suspend,
-        .resume         = exynos_pm_resume,
-};
-/*
- * Suspend Ops
- */
-static int exynos_suspend_enter(suspend_state_t state)
-{
-        int ret;
-        s3c_pm_debug_init();
-        S3C_PMDBG("%s: suspending the system...\n", __func__);
-        S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
-                        exynos_irqwake_intmask, exynos_get_eint_wake_mask());
-        if (exynos_irqwake_intmask == -1U
-            && exynos_get_eint_wake_mask() == -1U) {
-                pr_err("%s: No wake-up sources!\n", __func__);
-                pr_err("%s: Aborting sleep\n", __func__);
-                return -EINVAL;
-        }
-        s3c_pm_save_uarts();
-        exynos_pm_prepare();
-        flush_cache_all();
-        s3c_pm_check_store();
-        ret = cpu_suspend(0, exynos_cpu_suspend);
-        if (ret)
-                return ret;
-        s3c_pm_restore_uarts();
-        S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
-                        pmu_raw_readl(S5P_WAKEUP_STAT));
-        s3c_pm_check_restore();
-        S3C_PMDBG("%s: resuming the system...\n", __func__);
-        return 0;
-}
-static int exynos_suspend_prepare(void)
-{
-        s3c_pm_check_prepare();
-        return 0;
-}
-static void exynos_suspend_finish(void)
-{
-        s3c_pm_check_cleanup();
-}
-static const struct platform_suspend_ops exynos_suspend_ops = {
-        .enter          = exynos_suspend_enter,
-        .prepare        = exynos_suspend_prepare,
-        .finish         = exynos_suspend_finish,
-        .valid          = suspend_valid_only_mem,
-};
-void __init exynos_pm_init(void)
-{
-        u32 tmp;
-        /* Platform-specific GIC callback */
-        gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
-        /* All wakeup disable */
-        tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
-        tmp |= ((0xFF << 8) | (0x1F << 1));
-        pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
-        register_syscore_ops(&exynos_pm_syscore_ops);
-        suspend_set_ops(&exynos_suspend_ops);
-}
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index ff9d23f0a7d9..c15761ca2f18 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
 *              http://www.samsung.com/
 *
 * EXYNOS - CPU PMU(Power Management Unit) support
@@ -10,12 +10,136 @@
 */
 #include <linux/io.h>
-#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/notifier.h>
+#include <linux/reboot.h>
-#include "common.h"
+#include "exynos-pmu.h"
 #include "regs-pmu.h"
-static const struct exynos_pmu_conf *exynos_pmu_config;
+#define PMU_TABLE_END   (-1U)
+struct exynos_pmu_conf {
+        unsigned int offset;
+        u8 val[NUM_SYS_POWERDOWN];
+};
+struct exynos_pmu_data {
+        const struct exynos_pmu_conf *pmu_config;
+        const struct exynos_pmu_conf *pmu_config_extra;
+        void (*pmu_init)(void);
+        void (*powerdown_conf)(enum sys_powerdown);
+        void (*powerdown_conf_extra)(enum sys_powerdown);
+};
+struct exynos_pmu_context {
+        struct device *dev;
+        const struct exynos_pmu_data *pmu_data;
+};
+static void __iomem *pmu_base_addr;
+static struct exynos_pmu_context *pmu_context;
+static inline void pmu_raw_writel(u32 val, u32 offset)
+{
+        writel_relaxed(val, pmu_base_addr + offset);
+}
+static inline u32 pmu_raw_readl(u32 offset)
+{
+        return readl_relaxed(pmu_base_addr + offset);
+}
+static struct exynos_pmu_conf exynos3250_pmu_config[] = {
+        /* { .offset = offset, .val = { AFTR, W-AFTR, SLEEP } */
+        { EXYNOS3_ARM_CORE0_SYS_PWR_REG,                { 0x0, 0x0, 0x2} },
+        { EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
+        { EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+        { EXYNOS3_ARM_CORE1_SYS_PWR_REG,                { 0x0, 0x0, 0x2} },
+        { EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
+        { EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
+        { EXYNOS3_ISP_ARM_SYS_PWR_REG,                  { 0x1, 0x0, 0x0} },
+        { EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG,    { 0x0, 0x0, 0x0} },
+        { EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
+        { EXYNOS3_ARM_COMMON_SYS_PWR_REG,               { 0x0, 0x0, 0x2} },
+        { EXYNOS3_ARM_L2_SYS_PWR_REG,                   { 0x0, 0x0, 0x3} },
+        { EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG,             { 0x1, 0x1, 0x0} },
+        { EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG,             { 0x1, 0x1, 0x0} },
+        { EXYNOS3_CMU_RESET_SYS_PWR_REG,                { 0x1, 0x1, 0x0} },
+        { EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG,           { 0x1, 0x1, 0x1} },
+        { EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG,            { 0x1, 0x1, 0x1} },
+        { EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG,       { 0x1, 0x1, 0x1} },
+        { EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG,     { 0x1, 0x0, 0x0} },
+        { EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG,     { 0x1, 0x0, 0x0} },
+        { EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG,        { 0x1, 0x1, 0x0} },
+        { EXYNOS3_APLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
+        { EXYNOS3_MPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
+        { EXYNOS3_BPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
+        { EXYNOS3_VPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x1, 0x0} },
+        { EXYNOS3_EPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
+        { EXYNOS3_UPLL_SYSCLK_SYS_PWR_REG,              { 0x1, 0x1, 0x1} },
+        { EXYNOS3_EPLLUSER_SYSCLK_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
+        { EXYNOS3_MPLLUSER_SYSCLK_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
+        { EXYNOS3_BPLLUSER_SYSCLK_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
+        { EXYNOS3_CMU_CLKSTOP_CAM_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
+        { EXYNOS3_CMU_CLKSTOP_MFC_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
+        { EXYNOS3_CMU_CLKSTOP_G3D_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
+        { EXYNOS3_CMU_CLKSTOP_LCD0_SYS_PWR_REG,         { 0x1, 0x0, 0x0} },
+        { EXYNOS3_CMU_CLKSTOP_ISP_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
+        { EXYNOS3_CMU_CLKSTOP_MAUDIO_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
+        { EXYNOS3_CMU_RESET_CAM_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
+        { EXYNOS3_CMU_RESET_MFC_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
+        { EXYNOS3_CMU_RESET_G3D_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
+        { EXYNOS3_CMU_RESET_LCD0_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
+        { EXYNOS3_CMU_RESET_ISP_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
+        { EXYNOS3_CMU_RESET_MAUDIO_SYS_PWR_REG,         { 0x1, 0x0, 0x0} },
+        { EXYNOS3_TOP_BUS_SYS_PWR_REG,                  { 0x3, 0x0, 0x0} },
+        { EXYNOS3_TOP_RETENTION_SYS_PWR_REG,            { 0x1, 0x1, 0x1} },
+        { EXYNOS3_TOP_PWR_SYS_PWR_REG,                  { 0x3, 0x3, 0x3} },
+        { EXYNOS3_TOP_BUS_COREBLK_SYS_PWR_REG,          { 0x3, 0x0, 0x0} },
+        { EXYNOS3_TOP_RETENTION_COREBLK_SYS_PWR_REG,    { 0x1, 0x1, 0x1} },
+        { EXYNOS3_TOP_PWR_COREBLK_SYS_PWR_REG,          { 0x3, 0x3, 0x3} },
+        { EXYNOS3_LOGIC_RESET_SYS_PWR_REG,              { 0x1, 0x1, 0x0} },
+        { EXYNOS3_OSCCLK_GATE_SYS_PWR_REG,              { 0x1, 0x1, 0x1} },
+        { EXYNOS3_LOGIC_RESET_COREBLK_SYS_PWR_REG,      { 0x1, 0x1, 0x0} },
+        { EXYNOS3_OSCCLK_GATE_COREBLK_SYS_PWR_REG,      { 0x1, 0x0, 0x1} },
+        { EXYNOS3_PAD_RETENTION_DRAM_SYS_PWR_REG,       { 0x1, 0x1, 0x0} },
+        { EXYNOS3_PAD_RETENTION_MAUDIO_SYS_PWR_REG,     { 0x1, 0x1, 0x0} },
+        { EXYNOS3_PAD_RETENTION_GPIO_SYS_PWR_REG,       { 0x1, 0x1, 0x0} },
+        { EXYNOS3_PAD_RETENTION_UART_SYS_PWR_REG,       { 0x1, 0x1, 0x0} },
+        { EXYNOS3_PAD_RETENTION_MMC0_SYS_PWR_REG,       { 0x1, 0x1, 0x0} },
+        { EXYNOS3_PAD_RETENTION_MMC1_SYS_PWR_REG,       { 0x1, 0x1, 0x0} },
+        { EXYNOS3_PAD_RETENTION_MMC2_SYS_PWR_REG,       { 0x1, 0x1, 0x0} },
+        { EXYNOS3_PAD_RETENTION_SPI_SYS_PWR_REG,        { 0x1, 0x1, 0x0} },
+        { EXYNOS3_PAD_RETENTION_EBIA_SYS_PWR_REG,       { 0x1, 0x1, 0x0} },
+        { EXYNOS3_PAD_RETENTION_EBIB_SYS_PWR_REG,       { 0x1, 0x1, 0x0} },
+        { EXYNOS3_PAD_RETENTION_JTAG_SYS_PWR_REG,       { 0x1, 0x1, 0x0} },
+        { EXYNOS3_PAD_ISOLATION_SYS_PWR_REG,            { 0x1, 0x1, 0x0} },
+        { EXYNOS3_PAD_ALV_SEL_SYS_PWR_REG,              { 0x1, 0x1, 0x0} },
+        { EXYNOS3_XUSBXTI_SYS_PWR_REG,                  { 0x1, 0x1, 0x0} },
+        { EXYNOS3_XXTI_SYS_PWR_REG,                     { 0x1, 0x1, 0x0} },
+        { EXYNOS3_EXT_REGULATOR_SYS_PWR_REG,            { 0x1, 0x1, 0x0} },
+        { EXYNOS3_EXT_REGULATOR_COREBLK_SYS_PWR_REG,    { 0x1, 0x1, 0x0} },
+        { EXYNOS3_GPIO_MODE_SYS_PWR_REG,                { 0x1, 0x1, 0x0} },
+        { EXYNOS3_GPIO_MODE_MAUDIO_SYS_PWR_REG,         { 0x1, 0x1, 0x0} },
+        { EXYNOS3_TOP_ASB_RESET_SYS_PWR_REG,            { 0x1, 0x1, 0x0} },
+        { EXYNOS3_TOP_ASB_ISOLATION_SYS_PWR_REG,        { 0x1, 0x1, 0x0} },
+        { EXYNOS3_TOP_ASB_RESET_COREBLK_SYS_PWR_REG,    { 0x1, 0x1, 0x0} },
+        { EXYNOS3_TOP_ASB_ISOLATION_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
+        { EXYNOS3_CAM_SYS_PWR_REG,                      { 0x7, 0x0, 0x0} },
+        { EXYNOS3_MFC_SYS_PWR_REG,                      { 0x7, 0x0, 0x0} },
+        { EXYNOS3_G3D_SYS_PWR_REG,                      { 0x7, 0x0, 0x0} },
+        { EXYNOS3_LCD0_SYS_PWR_REG,                     { 0x7, 0x0, 0x0} },
+        { EXYNOS3_ISP_SYS_PWR_REG,                      { 0x7, 0x0, 0x0} },
+        { EXYNOS3_MAUDIO_SYS_PWR_REG,                   { 0x7, 0x0, 0x0} },
+        { EXYNOS3_CMU_SYSCLK_ISP_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
+        { PMU_TABLE_END,},
+};
 static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
        /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
@@ -264,6 +388,7 @@ static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
        { EXYNOS5_INTRAM_MEM_SYS_PWR_REG,               { 0x3, 0x0, 0x0} },
        { EXYNOS5_INTROM_MEM_SYS_PWR_REG,               { 0x3, 0x0, 0x0} },
        { EXYNOS5_JPEG_MEM_SYS_PWR_REG,                 { 0x3, 0x0, 0x0} },
+        { EXYNOS5_JPEG_MEM_OPTION,                      { 0x10, 0x10, 0x0} },
        { EXYNOS5_HSI_MEM_SYS_PWR_REG,                  { 0x3, 0x0, 0x0} },
        { EXYNOS5_MCUIOP_MEM_SYS_PWR_REG,               { 0x3, 0x0, 0x0} },
        { EXYNOS5_SATA_MEM_SYS_PWR_REG,                 { 0x3, 0x0, 0x0} },
@@ -315,6 +440,189 @@ static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
        { PMU_TABLE_END,},
 };
+static struct exynos_pmu_conf exynos5420_pmu_config[] = {
+        /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
+        { EXYNOS5_ARM_CORE0_SYS_PWR_REG,                        { 0x0, 0x0, 0x0} },
+        { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
+        { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG,        { 0x0, 0x0, 0x0} },
+        { EXYNOS5_ARM_CORE1_SYS_PWR_REG,                        { 0x0, 0x0, 0x0} },
+        { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
+        { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG,        { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_ARM_CORE2_SYS_PWR_REG,                     { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG,       { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG,     { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_ARM_CORE3_SYS_PWR_REG,                     { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG,       { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG,     { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_KFC_CORE0_SYS_PWR_REG,                     { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG,       { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG,     { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_KFC_CORE1_SYS_PWR_REG,                     { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG,       { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG,     { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_KFC_CORE2_SYS_PWR_REG,                     { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG,       { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG,     { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_KFC_CORE3_SYS_PWR_REG,                     { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG,       { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG,     { 0x0, 0x0, 0x0} },
+        { EXYNOS5_ISP_ARM_SYS_PWR_REG,                          { 0x1, 0x0, 0x0} },
+        { EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
+        { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
+        { EXYNOS5420_ARM_COMMON_SYS_PWR_REG,                    { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_KFC_COMMON_SYS_PWR_REG,                    { 0x0, 0x0, 0x0} },
+        { EXYNOS5_ARM_L2_SYS_PWR_REG,                           { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_KFC_L2_SYS_PWR_REG,                        { 0x0, 0x0, 0x0} },
+        { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG,                     { 0x1, 0x0, 0x0} },
+        { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG,                     { 0x1, 0x0, 0x1} },
+        { EXYNOS5_CMU_RESET_SYS_PWR_REG,                        { 0x1, 0x1, 0x0} },
+        { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG,              { 0x1, 0x0, 0x0} },
+        { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG,              { 0x1, 0x0, 0x1} },
+        { EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG,                 { 0x1, 0x1, 0x0} },
+        { EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG,                   { 0x1, 0x0, 0x1} },
+        { EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG,                    { 0x1, 0x1, 0x1} },
+        { EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG,                   { 0x1, 0x0, 0x1} },
+        { EXYNOS5_APLL_SYSCLK_SYS_PWR_REG,                      { 0x1, 0x0, 0x0} },
+        { EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG,                      { 0x1, 0x0, 0x0} },
+        { EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG,                      { 0x1, 0x0, 0x0} },
+        { EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG,                      { 0x1, 0x1, 0x0} },
+        { EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG,                      { 0x1, 0x0, 0x0} },
+        { EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG,                      { 0x1, 0x0, 0x0} },
+        { EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG,                   { 0x1, 0x0, 0x0} },
+        { EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG,                   { 0x1, 0x0, 0x0} },
+        { EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG,                   { 0x1, 0x0, 0x0} },
+        { EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG,                  { 0x1, 0x0, 0x0} },
+        { EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG,                  { 0x1, 0x0, 0x0} },
+        { EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG,                   { 0x1, 0x0, 0x0} },
+        { EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG,                   { 0x1, 0x0, 0x0} },
+        { EXYNOS5_TOP_BUS_SYS_PWR_REG,                          { 0x3, 0x0, 0x0} },
+        { EXYNOS5_TOP_RETENTION_SYS_PWR_REG,                    { 0x1, 0x1, 0x1} },
+        { EXYNOS5_TOP_PWR_SYS_PWR_REG,                          { 0x3, 0x3, 0x0} },
+        { EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG,                   { 0x3, 0x0, 0x0} },
+        { EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG,             { 0x1, 0x0, 0x1} },
+        { EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG,                   { 0x3, 0x0, 0x0} },
+        { EXYNOS5_LOGIC_RESET_SYS_PWR_REG,                      { 0x1, 0x1, 0x0} },
+        { EXYNOS5_OSCCLK_GATE_SYS_PWR_REG,                      { 0x1, 0x0, 0x1} },
+        { EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG,               { 0x1, 0x0, 0x0} },
+        { EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG,               { 0x1, 0x0, 0x0} },
+        { EXYNOS5420_INTRAM_MEM_SYS_PWR_REG,                    { 0x3, 0x0, 0x3} },
+        { EXYNOS5420_INTROM_MEM_SYS_PWR_REG,                    { 0x3, 0x0, 0x3} },
+        { EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG,               { 0x1, 0x0, 0x0} },
+        { EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG,                { 0x1, 0x1, 0x0} },
+        { EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG,            { 0x1, 0x1, 0x0} },
+        { EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
+        { EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
+        { EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
+        { EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
+        { EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
+        { EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_REG,             { 0x1, 0x0, 0x0} },
+        { EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
+        { EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
+        { EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_REG,             { 0x1, 0x0, 0x0} },
+        { EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_SYS_PWR_REG,    { 0x1, 0x0, 0x0} },
+        { EXYNOS5_PAD_ISOLATION_SYS_PWR_REG,                    { 0x1, 0x1, 0x0} },
+        { EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG,             { 0x1, 0x0, 0x0} },
+        { EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG,                      { 0x1, 0x0, 0x0} },
+        { EXYNOS5_XUSBXTI_SYS_PWR_REG,                          { 0x1, 0x1, 0x0} },
+        { EXYNOS5_XXTI_SYS_PWR_REG,                             { 0x1, 0x1, 0x0} },
+        { EXYNOS5_EXT_REGULATOR_SYS_PWR_REG,                    { 0x1, 0x1, 0x0} },
+        { EXYNOS5_GPIO_MODE_SYS_PWR_REG,                        { 0x1, 0x0, 0x0} },
+        { EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG,                 { 0x1, 0x1, 0x0} },
+        { EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG,                    { 0x1, 0x1, 0x0} },
+        { EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG,                    { 0x1, 0x1, 0x0} },
+        { EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG,                { 0x1, 0x0, 0x0} },
+        { EXYNOS5_GSCL_SYS_PWR_REG,                             { 0x7, 0x0, 0x0} },
+        { EXYNOS5_ISP_SYS_PWR_REG,                              { 0x7, 0x0, 0x0} },
+        { EXYNOS5_MFC_SYS_PWR_REG,                              { 0x7, 0x0, 0x0} },
+        { EXYNOS5_G3D_SYS_PWR_REG,                              { 0x7, 0x0, 0x0} },
+        { EXYNOS5420_DISP1_SYS_PWR_REG,                         { 0x7, 0x0, 0x0} },
+        { EXYNOS5420_MAU_SYS_PWR_REG,                           { 0x7, 0x7, 0x0} },
+        { EXYNOS5420_G2D_SYS_PWR_REG,                           { 0x7, 0x0, 0x0} },
+        { EXYNOS5420_MSC_SYS_PWR_REG,                           { 0x7, 0x0, 0x0} },
+        { EXYNOS5420_FSYS_SYS_PWR_REG,                          { 0x7, 0x0, 0x0} },
+        { EXYNOS5420_FSYS2_SYS_PWR_REG,                         { 0x7, 0x0, 0x0} },
+        { EXYNOS5420_PSGEN_SYS_PWR_REG,                         { 0x7, 0x0, 0x0} },
+        { EXYNOS5420_PERIC_SYS_PWR_REG,                         { 0x7, 0x0, 0x0} },
+        { EXYNOS5420_WCORE_SYS_PWR_REG,                         { 0x7, 0x0, 0x0} },
+        { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,                 { 0x0, 0x0, 0x0} },
+        { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,                  { 0x0, 0x0, 0x0} },
+        { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,                  { 0x0, 0x0, 0x0} },
+        { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,                  { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG,             { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG,               { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG,               { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG,               { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG,              { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG,             { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG,             { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG,             { 0x0, 0x0, 0x0} },
+        { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,                  { 0x0, 0x0, 0x0} },
+        { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,                   { 0x0, 0x0, 0x0} },
+        { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,                   { 0x0, 0x0, 0x0} },
+        { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,                   { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG,              { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG,                { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG,                { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG,                { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG,               { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG,              { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG,              { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG,              { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG,              { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG,               { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG,               { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG,               { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG,               { 0x0, 0x0, 0x0} },
+        { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,                   { 0x0, 0x0, 0x0} },
+        { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,                    { 0x0, 0x0, 0x0} },
+        { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,                    { 0x0, 0x0, 0x0} },
+        { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,                    { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG,               { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG,                 { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG,                 { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG,                 { 0x0, 0x0, 0x0} },
+        { EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG,                { 0x0, 0x0, 0x0} },
+        { PMU_TABLE_END,},
+};
+static unsigned int const exynos3250_list_feed[] = {
+        EXYNOS3_ARM_CORE_OPTION(0),
+        EXYNOS3_ARM_CORE_OPTION(1),
+        EXYNOS3_ARM_CORE_OPTION(2),
+        EXYNOS3_ARM_CORE_OPTION(3),
+        EXYNOS3_ARM_COMMON_OPTION,
+        EXYNOS3_TOP_PWR_OPTION,
+        EXYNOS3_CORE_TOP_PWR_OPTION,
+        S5P_CAM_OPTION,
+        S5P_MFC_OPTION,
+        S5P_G3D_OPTION,
+        S5P_LCD0_OPTION,
+        S5P_ISP_OPTION,
+};
+static void exynos3250_powerdown_conf_extra(enum sys_powerdown mode)
+{
+        unsigned int i;
+        unsigned int tmp;
+        /* Enable only SC_FEEDBACK */
+        for (i = 0; i < ARRAY_SIZE(exynos3250_list_feed); i++) {
+                tmp = pmu_raw_readl(exynos3250_list_feed[i]);
+                tmp &= ~(EXYNOS3_OPTION_USE_SC_COUNTER);
+                tmp |= EXYNOS3_OPTION_USE_SC_FEEDBACK;
+                pmu_raw_writel(tmp, exynos3250_list_feed[i]);
+        }
+        if (mode != SYS_SLEEP)
+                return;
+        pmu_raw_writel(XUSBXTI_DURATION, EXYNOS3_XUSBXTI_DURATION);
+        pmu_raw_writel(XXTI_DURATION, EXYNOS3_XXTI_DURATION);
+        pmu_raw_writel(EXT_REGULATOR_DURATION, EXYNOS3_EXT_REGULATOR_DURATION);
+        pmu_raw_writel(EXT_REGULATOR_COREBLK_DURATION,
+                       EXYNOS3_EXT_REGULATOR_COREBLK_DURATION);
+}
 static unsigned int const exynos5_list_both_cnt_feed[] = {
        EXYNOS5_ARM_CORE0_OPTION,
        EXYNOS5_ARM_CORE1_OPTION,
@@ -329,13 +637,82 @@ static unsigned int const exynos5_list_both_cnt_feed[] = {
        EXYNOS5_TOP_PWR_SYSMEM_OPTION,
 };
-static unsigned int const exynos5_list_diable_wfi_wfe[] = {
+static unsigned int const exynos5_list_disable_wfi_wfe[] = {
        EXYNOS5_ARM_CORE1_OPTION,
        EXYNOS5_FSYS_ARM_OPTION,
        EXYNOS5_ISP_ARM_OPTION,
 };
-static void exynos5_init_pmu(void)
+static unsigned int const exynos5420_list_disable_pmu_reg[] = {
+        EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,
+        EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,
+        EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,
+        EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG,
+        EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG,
+        EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG,
+        EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG,
+        EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG,
+        EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG,
+        EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG,
+        EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG,
+        EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,
+        EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,
+        EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,
+        EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG,
+        EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG,
+        EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG,
+        EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG,
+        EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG,
+        EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG,
+        EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG,
+        EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG,
+        EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG,
+        EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG,
+        EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG,
+        EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG,
+        EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG,
+        EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,
+        EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,
+        EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,
+        EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG,
+        EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG,
+        EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG,
+        EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG,
+        EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG,
+};
+static void exynos5_power_off(void)
+{
+        unsigned int tmp;
+        pr_info("Power down.\n");
+        tmp = pmu_raw_readl(EXYNOS_PS_HOLD_CONTROL);
+        tmp ^= (1 << 8);
+        pmu_raw_writel(tmp, EXYNOS_PS_HOLD_CONTROL);
+        /* Wait a little so we don't give a false warning below */
+        mdelay(100);
+        pr_err("Power down failed, please power off system manually.\n");
+        while (1)
+                ;
+}
+void exynos5420_powerdown_conf(enum sys_powerdown mode)
+{
+        u32 this_cluster;
+        this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
+        /*
+         * set the cluster id to IROM register to ensure that we wake
+         * up with the current cluster.
+         */
+        pmu_raw_writel(this_cluster, EXYNOS_IROM_DATA2);
+}
+static void exynos5_powerdown_conf(enum sys_powerdown mode)
 {
        unsigned int i;
        unsigned int tmp;
@@ -343,7 +720,7 @@ static void exynos5_init_pmu(void)
        /*
         * Enable both SC_FEEDBACK and SC_COUNTER
         */
-        for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) {
+        for (i = 0; i < ARRAY_SIZE(exynos5_list_both_cnt_feed); i++) {
                tmp = pmu_raw_readl(exynos5_list_both_cnt_feed[i]);
                tmp |= (EXYNOS5_USE_SC_FEEDBACK |
                        EXYNOS5_USE_SC_COUNTER);
@@ -360,11 +737,11 @@ static void exynos5_init_pmu(void)
        /*
         * Disable WFI/WFE on XXX_OPTION
         */
-        for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) {
+        for (i = 0; i < ARRAY_SIZE(exynos5_list_disable_wfi_wfe); i++) {
-                tmp = pmu_raw_readl(exynos5_list_diable_wfi_wfe[i]);
+                tmp = pmu_raw_readl(exynos5_list_disable_wfi_wfe[i]);
                tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
                         EXYNOS5_OPTION_USE_STANDBYWFI);
-                pmu_raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
+                pmu_raw_writel(tmp, exynos5_list_disable_wfi_wfe[i]);
        }
 }
@@ -372,51 +749,257 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
 {
        unsigned int i;
-        if (soc_is_exynos5250())
+        const struct exynos_pmu_data *pmu_data = pmu_context->pmu_data;
-                exynos5_init_pmu();
+        if (pmu_data->powerdown_conf)
+                pmu_data->powerdown_conf(mode);
+        if (pmu_data->pmu_config) {
+                for (i = 0; (pmu_data->pmu_config[i].offset != PMU_TABLE_END); i++)
+                        pmu_raw_writel(pmu_data->pmu_config[i].val[mode],
+                                        pmu_data->pmu_config[i].offset);
+        }
-        for (i = 0; (exynos_pmu_config[i].offset != PMU_TABLE_END) ; i++)
+        if (pmu_data->powerdown_conf_extra)
-                pmu_raw_writel(exynos_pmu_config[i].val[mode],
+                pmu_data->powerdown_conf_extra(mode);
-                                exynos_pmu_config[i].offset);
-        if (soc_is_exynos4412()) {
+        if (pmu_data->pmu_config_extra) {
-                for (i = 0; exynos4412_pmu_config[i].offset != PMU_TABLE_END ; i++)
+                for (i = 0; pmu_data->pmu_config_extra[i].offset != PMU_TABLE_END; i++)
-                        pmu_raw_writel(exynos4412_pmu_config[i].val[mode],
+                        pmu_raw_writel(pmu_data->pmu_config_extra[i].val[mode],
-                                        exynos4412_pmu_config[i].offset);
+                                        pmu_data->pmu_config_extra[i].offset);
        }
 }
-static int __init exynos_pmu_init(void)
+static void exynos3250_pmu_init(void)
+{
+        unsigned int value;
+        /*
+         * To prevent from issuing new bus request form L2 memory system
+         * If core status is power down, should be set '1' to L2 power down
+         */
+        value = pmu_raw_readl(EXYNOS3_ARM_COMMON_OPTION);
+        value |= EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
+        pmu_raw_writel(value, EXYNOS3_ARM_COMMON_OPTION);
+        /* Enable USE_STANDBY_WFI for all CORE */
+        pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
+        /*
+         * Set PSHOLD port for output high
+         */
+        value = pmu_raw_readl(S5P_PS_HOLD_CONTROL);
+        value |= S5P_PS_HOLD_OUTPUT_HIGH;
+        pmu_raw_writel(value, S5P_PS_HOLD_CONTROL);
+        /*
+         * Enable signal for PSHOLD port
+         */
+        value = pmu_raw_readl(S5P_PS_HOLD_CONTROL);
+        value |= S5P_PS_HOLD_EN;
+        pmu_raw_writel(value, S5P_PS_HOLD_CONTROL);
+}
+static void exynos5250_pmu_init(void)
 {
        unsigned int value;
+        /*
+         * When SYS_WDTRESET is set, watchdog timer reset request
+         * is ignored by power management unit.
+         */
+        value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
+        value &= ~EXYNOS5_SYS_WDTRESET;
+        pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
+        value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
+        value &= ~EXYNOS5_SYS_WDTRESET;
+        pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
+}
+static void exynos5420_pmu_init(void)
+{
+        unsigned int value;
+        int i;
+        /*
+         * Set the CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers
+         * for local power blocks to Low initially as per Table 8-4:
+         * "System-Level Power-Down Configuration Registers".
+         */
+        for (i = 0; i < ARRAY_SIZE(exynos5420_list_disable_pmu_reg); i++)
+                pmu_raw_writel(0, exynos5420_list_disable_pmu_reg[i]);
+        /* Enable USE_STANDBY_WFI for all CORE */
+        pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
+        value  = pmu_raw_readl(EXYNOS_L2_OPTION(0));
+        value &= ~EXYNOS5_USE_RETENTION;
+        pmu_raw_writel(value, EXYNOS_L2_OPTION(0));
+        value = pmu_raw_readl(EXYNOS_L2_OPTION(1));
+        value &= ~EXYNOS5_USE_RETENTION;
+        pmu_raw_writel(value, EXYNOS_L2_OPTION(1));
+        /*
+         * If L2_COMMON is turned off, clocks related to ATB async
+         * bridge are gated. Thus, when ISP power is gated, LPI
+         * may get stuck.
+         */
+        value = pmu_raw_readl(EXYNOS5420_LPI_MASK);
+        value |= EXYNOS5420_ATB_ISP_ARM;
+        pmu_raw_writel(value, EXYNOS5420_LPI_MASK);
+        value  = pmu_raw_readl(EXYNOS5420_LPI_MASK1);
+        value |= EXYNOS5420_ATB_KFC;
+        pmu_raw_writel(value, EXYNOS5420_LPI_MASK1);
+        /* Prevent issue of new bus request from L2 memory */
+        value = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
+        value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
+        pmu_raw_writel(value, EXYNOS5420_ARM_COMMON_OPTION);
+        value = pmu_raw_readl(EXYNOS5420_KFC_COMMON_OPTION);
+        value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
+        pmu_raw_writel(value, EXYNOS5420_KFC_COMMON_OPTION);
+        /* This setting is to reduce suspend/resume time */
+        pmu_raw_writel(DUR_WAIT_RESET, EXYNOS5420_LOGIC_RESET_DURATION3);
+        /* Serialized CPU wakeup of Eagle */
+        pmu_raw_writel(SPREAD_ENABLE, EXYNOS5420_ARM_INTR_SPREAD_ENABLE);
+        pmu_raw_writel(SPREAD_USE_STANDWFI,
+                        EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI);
+        pmu_raw_writel(0x1, EXYNOS5420_UP_SCHEDULER);
+        pm_power_off = exynos5_power_off;
+        pr_info("EXYNOS5420 PMU initialized\n");
+}
+static int pmu_restart_notify(struct notifier_block *this,
+                unsigned long code, void *unused)
+{
+        pmu_raw_writel(0x1, EXYNOS_SWRESET);
+        return NOTIFY_DONE;
+}
+static const struct exynos_pmu_data exynos3250_pmu_data = {
+        .pmu_config     = exynos3250_pmu_config,
+        .pmu_init       = exynos3250_pmu_init,
+        .powerdown_conf_extra   = exynos3250_powerdown_conf_extra,
+};
-        exynos_pmu_config = exynos4210_pmu_config;
+static const struct exynos_pmu_data exynos4210_pmu_data = {
+        .pmu_config     = exynos4210_pmu_config,
-        if (soc_is_exynos4210()) {
+};
-                exynos_pmu_config = exynos4210_pmu_config;
-                pr_info("EXYNOS4210 PMU Initialize\n");
+static const struct exynos_pmu_data exynos4212_pmu_data = {
-        } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+        .pmu_config     = exynos4x12_pmu_config,
-                exynos_pmu_config = exynos4x12_pmu_config;
+};
-                pr_info("EXYNOS4x12 PMU Initialize\n");
-        } else if (soc_is_exynos5250()) {
+static const struct exynos_pmu_data exynos4412_pmu_data = {
-                /*
+        .pmu_config             = exynos4x12_pmu_config,
-                 * When SYS_WDTRESET is set, watchdog timer reset request
+        .pmu_config_extra       = exynos4412_pmu_config,
-                 * is ignored by power management unit.
+};
-                 */
-                value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
+static const struct exynos_pmu_data exynos5250_pmu_data = {
-                value &= ~EXYNOS5_SYS_WDTRESET;
+        .pmu_config     = exynos5250_pmu_config,
-                pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
+        .pmu_init       = exynos5250_pmu_init,
+        .powerdown_conf = exynos5_powerdown_conf,
-                value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
+};
-                value &= ~EXYNOS5_SYS_WDTRESET;
-                pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
+static struct exynos_pmu_data exynos5420_pmu_data = {
+        .pmu_config     = exynos5420_pmu_config,
-                exynos_pmu_config = exynos5250_pmu_config;
+        .pmu_init       = exynos5420_pmu_init,
-                pr_info("EXYNOS5250 PMU Initialize\n");
+        .powerdown_conf = exynos5420_powerdown_conf,
-        } else {
+};
-                pr_info("EXYNOS: PMU not supported\n");
+/*
+ * PMU platform driver and devicetree bindings.
+ */
+static const struct of_device_id exynos_pmu_of_device_ids[] = {
+        {
+                .compatible = "samsung,exynos3250-pmu",
+                .data = &exynos3250_pmu_data,
+        }, {
+                .compatible = "samsung,exynos4210-pmu",
+                .data = &exynos4210_pmu_data,
+        }, {
+                .compatible = "samsung,exynos4212-pmu",
+                .data = &exynos4212_pmu_data,
+        }, {
+                .compatible = "samsung,exynos4412-pmu",
+                .data = &exynos4412_pmu_data,
+        }, {
+                .compatible = "samsung,exynos5250-pmu",
+                .data = &exynos5250_pmu_data,
+        }, {
+                .compatible = "samsung,exynos5420-pmu",
+                .data = &exynos5420_pmu_data,
+        },
+        { /*sentinel*/ },
+};
+/*
+ * Exynos PMU restart notifier, handles restart functionality
+ */
+static struct notifier_block pmu_restart_handler = {
+        .notifier_call = pmu_restart_notify,
+        .priority = 128,
+};
+static int exynos_pmu_probe(struct platform_device *pdev)
+{
+        const struct of_device_id *match;
+        struct device *dev = &pdev->dev;
+        struct resource *res;
+        int ret;
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        pmu_base_addr = devm_ioremap_resource(dev, res);
+        if (IS_ERR(pmu_base_addr))
+                return PTR_ERR(pmu_base_addr);
+        pmu_context = devm_kzalloc(&pdev->dev,
+                        sizeof(struct exynos_pmu_context),
+                        GFP_KERNEL);
+        if (!pmu_context) {
+                dev_err(dev, "Cannot allocate memory.\n");
+                return -ENOMEM;
        }
+        pmu_context->dev = dev;
+        match = of_match_node(exynos_pmu_of_device_ids, dev->of_node);
+        pmu_context->pmu_data = match->data;
+        if (pmu_context->pmu_data->pmu_init)
+                pmu_context->pmu_data->pmu_init();
+        platform_set_drvdata(pdev, pmu_context);
+        ret = register_restart_handler(&pmu_restart_handler);
+        if (ret)
+                dev_warn(dev, "can't register restart handler err=%d\n", ret);
+        dev_dbg(dev, "Exynos PMU Driver probe done\n");
        return 0;
 }
-arch_initcall(exynos_pmu_init);
+static struct platform_driver exynos_pmu_driver = {
+        .driver  = {
+                .name   = "exynos-pmu",
+                .owner  = THIS_MODULE,
+                .of_match_table = exynos_pmu_of_device_ids,
+        },
+        .probe = exynos_pmu_probe,
+};
+static int __init exynos_pmu_init(void)
+{
+        return platform_driver_register(&exynos_pmu_driver);
+}
+postcore_initcall(exynos_pmu_init);
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 96a1569262b5..b5f4406fc1b5 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -19,8 +19,24 @@
 #define S5P_CENTRAL_SEQ_OPTION                  0x0208
 #define S5P_USE_STANDBY_WFI0                    (1 << 16)
+#define S5P_USE_STANDBY_WFI1                    (1 << 17)
+#define S5P_USE_STANDBY_WFI2                    (1 << 19)
+#define S5P_USE_STANDBY_WFI3                    (1 << 20)
 #define S5P_USE_STANDBY_WFE0                    (1 << 24)
+#define S5P_USE_STANDBY_WFE1                    (1 << 25)
+#define S5P_USE_STANDBY_WFE2                    (1 << 27)
+#define S5P_USE_STANDBY_WFE3                    (1 << 28)
+#define S5P_USE_STANDBY_WFI_ALL \
+        (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFI1 | \
+         S5P_USE_STANDBY_WFI2 | S5P_USE_STANDBY_WFI3 | \
+         S5P_USE_STANDBY_WFE0 | S5P_USE_STANDBY_WFE1 | \
+         S5P_USE_STANDBY_WFE2 | S5P_USE_STANDBY_WFE3)
+#define S5P_USE_DELAYED_RESET_ASSERTION         BIT(12)
+#define EXYNOS_CORE_PO_RESET(n)                 ((1 << 4) << n)
+#define EXYNOS_WAKEUP_FROM_LOWPWR               (1 << 28)
 #define EXYNOS_SWRESET                          0x0400
 #define EXYNOS5440_SWRESET                      0x00C4
@@ -35,6 +51,7 @@
 #define S5P_INFORM7                             0x081C
 #define S5P_PMU_SPARE3                          0x090C
+#define EXYNOS_IROM_DATA2                       0x0988
 #define S5P_ARM_CORE0_LOWPWR                    0x1000
 #define S5P_DIS_IRQ_CORE0                       0x1004
 #define S5P_DIS_IRQ_CENTRAL0                    0x1008
@@ -106,6 +123,8 @@
                        (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
 #define EXYNOS_ARM_CORE_STATUS(_nr)             \
                        (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
+#define EXYNOS_ARM_CORE_OPTION(_nr)             \
+                        (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x8)
 #define EXYNOS_ARM_COMMON_CONFIGURATION         0x2500
 #define EXYNOS_COMMON_CONFIGURATION(_nr)        \
@@ -115,6 +134,31 @@
 #define EXYNOS_COMMON_OPTION(_nr)               \
                        (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8)
+#define EXYNOS_CORE_LOCAL_PWR_EN                0x3
+#define EXYNOS_ARM_COMMON_STATUS                0x2504
+#define EXYNOS_COMMON_OPTION(_nr)               \
+                        (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8)
+#define EXYNOS_ARM_L2_CONFIGURATION             0x2600
+#define EXYNOS_L2_CONFIGURATION(_nr)            \
+                        (EXYNOS_ARM_L2_CONFIGURATION + ((_nr) * 0x80))
+#define EXYNOS_L2_STATUS(_nr)                   \
+                        (EXYNOS_L2_CONFIGURATION(_nr) + 0x4)
+#define EXYNOS_L2_OPTION(_nr)                   \
+                        (EXYNOS_L2_CONFIGURATION(_nr) + 0x8)
+#define EXYNOS_L2_COMMON_PWR_EN                 0x3
+#define EXYNOS_ARM_CORE_X_STATUS_OFFSET         0x4
+#define EXYNOS5_APLL_SYSCLK_CONFIGURATION       0x2A00
+#define EXYNOS5_APLL_SYSCLK_STATUS              0x2A04
+#define EXYNOS5_ARM_L2_OPTION                   0x2608
+#define EXYNOS5_USE_RETENTION                   BIT(4)
+#define EXYNOS5_L2RSTDISABLE_VALUE              BIT(3)
 #define S5P_PAD_RET_MAUDIO_OPTION               0x3028
 #define S5P_PAD_RET_GPIO_OPTION                 0x3108
 #define S5P_PAD_RET_UART_OPTION                 0x3128
@@ -123,7 +167,19 @@
 #define S5P_PAD_RET_EBIA_OPTION                 0x3188
 #define S5P_PAD_RET_EBIB_OPTION                 0x31A8
+#define S5P_PS_HOLD_CONTROL                     0x330C
+#define S5P_PS_HOLD_EN                          (1 << 31)
+#define S5P_PS_HOLD_OUTPUT_HIGH                 (3 << 8)
+#define S5P_CAM_OPTION                          0x3C08
+#define S5P_MFC_OPTION                          0x3C48
+#define S5P_G3D_OPTION                          0x3C68
+#define S5P_LCD0_OPTION                         0x3C88
+#define S5P_LCD1_OPTION                         0x3CA8
+#define S5P_ISP_OPTION                          S5P_LCD1_OPTION
 #define S5P_CORE_LOCAL_PWR_EN                   0x3
+#define S5P_CORE_WAKEUP_FROM_LOCAL_CFG          (0x3 << 8)
 /* Only for EXYNOS4210 */
 #define S5P_CMU_CLKSTOP_LCD1_LOWPWR     0x1154
@@ -182,11 +238,116 @@
 #define S5P_DIS_IRQ_CORE3                       0x1034
 #define S5P_DIS_IRQ_CENTRAL3                    0x1038
+/* Only for EXYNOS3XXX */
+#define EXYNOS3_ARM_CORE0_SYS_PWR_REG                   0x1000
+#define EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG     0x1004
+#define EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG   0x1008
+#define EXYNOS3_ARM_CORE1_SYS_PWR_REG                   0x1010
+#define EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG     0x1014
+#define EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG   0x1018
+#define EXYNOS3_ISP_ARM_SYS_PWR_REG                     0x1050
+#define EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG       0x1054
+#define EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG     0x1058
+#define EXYNOS3_ARM_COMMON_SYS_PWR_REG                  0x1080
+#define EXYNOS3_ARM_L2_SYS_PWR_REG                      0x10C0
+#define EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG                0x1100
+#define EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG                0x1104
+#define EXYNOS3_CMU_RESET_SYS_PWR_REG                   0x110C
+#define EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG        0x1110
+#define EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG        0x1114
+#define EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG           0x111C
+#define EXYNOS3_APLL_SYSCLK_SYS_PWR_REG                 0x1120
+#define EXYNOS3_MPLL_SYSCLK_SYS_PWR_REG                 0x1124
+#define EXYNOS3_VPLL_SYSCLK_SYS_PWR_REG                 0x1128
+#define EXYNOS3_EPLL_SYSCLK_SYS_PWR_REG                 0x112C
+#define EXYNOS3_MPLLUSER_SYSCLK_SYS_PWR_REG             0x1130
+#define EXYNOS3_BPLLUSER_SYSCLK_SYS_PWR_REG             0x1134
+#define EXYNOS3_EPLLUSER_SYSCLK_SYS_PWR_REG             0x1138
+#define EXYNOS3_CMU_CLKSTOP_CAM_SYS_PWR_REG             0x1140
+#define EXYNOS3_CMU_CLKSTOP_MFC_SYS_PWR_REG             0x1148
+#define EXYNOS3_CMU_CLKSTOP_G3D_SYS_PWR_REG             0x114C
+#define EXYNOS3_CMU_CLKSTOP_LCD0_SYS_PWR_REG            0x1150
+#define EXYNOS3_CMU_CLKSTOP_ISP_SYS_PWR_REG             0x1154
+#define EXYNOS3_CMU_CLKSTOP_MAUDIO_SYS_PWR_REG          0x1158
+#define EXYNOS3_CMU_RESET_CAM_SYS_PWR_REG               0x1160
+#define EXYNOS3_CMU_RESET_MFC_SYS_PWR_REG               0x1168
+#define EXYNOS3_CMU_RESET_G3D_SYS_PWR_REG               0x116C
+#define EXYNOS3_CMU_RESET_LCD0_SYS_PWR_REG              0x1170
+#define EXYNOS3_CMU_RESET_ISP_SYS_PWR_REG               0x1174
+#define EXYNOS3_CMU_RESET_MAUDIO_SYS_PWR_REG            0x1178
+#define EXYNOS3_TOP_BUS_SYS_PWR_REG                     0x1180
+#define EXYNOS3_TOP_RETENTION_SYS_PWR_REG               0x1184
+#define EXYNOS3_TOP_PWR_SYS_PWR_REG                     0x1188
+#define EXYNOS3_TOP_BUS_COREBLK_SYS_PWR_REG             0x1190
+#define EXYNOS3_TOP_RETENTION_COREBLK_SYS_PWR_REG       0x1194
+#define EXYNOS3_TOP_PWR_COREBLK_SYS_PWR_REG             0x1198
+#define EXYNOS3_LOGIC_RESET_SYS_PWR_REG                 0x11A0
+#define EXYNOS3_OSCCLK_GATE_SYS_PWR_REG                 0x11A4
+#define EXYNOS3_LOGIC_RESET_COREBLK_SYS_PWR_REG         0x11B0
+#define EXYNOS3_OSCCLK_GATE_COREBLK_SYS_PWR_REG         0x11B4
+#define EXYNOS3_PAD_RETENTION_DRAM_SYS_PWR_REG          0x1200
+#define EXYNOS3_PAD_RETENTION_MAUDIO_SYS_PWR_REG        0x1204
+#define EXYNOS3_PAD_RETENTION_SPI_SYS_PWR_REG           0x1208
+#define EXYNOS3_PAD_RETENTION_MMC2_SYS_PWR_REG          0x1218
+#define EXYNOS3_PAD_RETENTION_GPIO_SYS_PWR_REG          0x1220
+#define EXYNOS3_PAD_RETENTION_UART_SYS_PWR_REG          0x1224
+#define EXYNOS3_PAD_RETENTION_MMC0_SYS_PWR_REG          0x1228
+#define EXYNOS3_PAD_RETENTION_MMC1_SYS_PWR_REG          0x122C
+#define EXYNOS3_PAD_RETENTION_EBIA_SYS_PWR_REG          0x1230
+#define EXYNOS3_PAD_RETENTION_EBIB_SYS_PWR_REG          0x1234
+#define EXYNOS3_PAD_RETENTION_JTAG_SYS_PWR_REG          0x1238
+#define EXYNOS3_PAD_ISOLATION_SYS_PWR_REG               0x1240
+#define EXYNOS3_PAD_ALV_SEL_SYS_PWR_REG                 0x1260
+#define EXYNOS3_XUSBXTI_SYS_PWR_REG                     0x1280
+#define EXYNOS3_XXTI_SYS_PWR_REG                        0x1284
+#define EXYNOS3_EXT_REGULATOR_SYS_PWR_REG               0x12C0
+#define EXYNOS3_EXT_REGULATOR_COREBLK_SYS_PWR_REG       0x12C4
+#define EXYNOS3_GPIO_MODE_SYS_PWR_REG                   0x1300
+#define EXYNOS3_GPIO_MODE_MAUDIO_SYS_PWR_REG            0x1340
+#define EXYNOS3_TOP_ASB_RESET_SYS_PWR_REG               0x1344
+#define EXYNOS3_TOP_ASB_ISOLATION_SYS_PWR_REG           0x1348
+#define EXYNOS3_TOP_ASB_RESET_COREBLK_SYS_PWR_REG       0x1350
+#define EXYNOS3_TOP_ASB_ISOLATION_COREBLK_SYS_PWR_REG   0x1354
+#define EXYNOS3_CAM_SYS_PWR_REG                         0x1380
+#define EXYNOS3_MFC_SYS_PWR_REG                         0x1388
+#define EXYNOS3_G3D_SYS_PWR_REG                         0x138C
+#define EXYNOS3_LCD0_SYS_PWR_REG                        0x1390
+#define EXYNOS3_ISP_SYS_PWR_REG                         0x1394
+#define EXYNOS3_MAUDIO_SYS_PWR_REG                      0x1398
+#define EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG              0x13B0
+#define EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG               0x13B4
+#define EXYNOS3_CMU_SYSCLK_ISP_SYS_PWR_REG              0x13B8
+#define EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG          0x13C0
+#define EXYNOS3_BPLL_SYSCLK_SYS_PWR_REG                 0x13C4
+#define EXYNOS3_UPLL_SYSCLK_SYS_PWR_REG                 0x13C8
+#define EXYNOS3_ARM_CORE0_OPTION                        0x2008
+#define EXYNOS3_ARM_CORE_OPTION(_nr)    \
+                        (EXYNOS3_ARM_CORE0_OPTION + ((_nr) * 0x80))
+#define EXYNOS3_ARM_COMMON_OPTION                       0x2408
+#define EXYNOS3_TOP_PWR_OPTION                          0x2C48
+#define EXYNOS3_CORE_TOP_PWR_OPTION                     0x2CA8
+#define EXYNOS3_XUSBXTI_DURATION                        0x341C
+#define EXYNOS3_XXTI_DURATION                           0x343C
+#define EXYNOS3_EXT_REGULATOR_DURATION                  0x361C
+#define EXYNOS3_EXT_REGULATOR_COREBLK_DURATION          0x363C
+#define XUSBXTI_DURATION                                0x00000BB8
+#define XXTI_DURATION                                   XUSBXTI_DURATION
+#define EXT_REGULATOR_DURATION                          0x00001D4C
+#define EXT_REGULATOR_COREBLK_DURATION                  EXT_REGULATOR_DURATION
+/* for XXX_OPTION */
+#define EXYNOS3_OPTION_USE_SC_COUNTER                   (1 << 0)
+#define EXYNOS3_OPTION_USE_SC_FEEDBACK                  (1 << 1)
+#define EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_IN_PWDN   (1 << 7)
 /* For EXYNOS5 */
 #define EXYNOS5_AUTO_WDTRESET_DISABLE                           0x0408
 #define EXYNOS5_MASK_WDTRESET_REQUEST                           0x040C
+#define EXYNOS5_USE_RETENTION                   BIT(4)
 #define EXYNOS5_SYS_WDTRESET                                    (1 << 20)
 #define EXYNOS5_ARM_CORE0_SYS_PWR_REG                           0x1000
@@ -326,4 +487,204 @@ static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
                 + MPIDR_AFFINITY_LEVEL(mpidr, 0));
 }
+/* Only for EXYNOS5420 */
+#define EXYNOS5420_ISP_ARM_OPTION                               0x2488
+#define EXYNOS5420_L2RSTDISABLE_VALUE                           BIT(3)
+#define EXYNOS5420_LPI_MASK                                     0x0004
+#define EXYNOS5420_LPI_MASK1                                    0x0008
+#define EXYNOS5420_UFS                                          BIT(8)
+#define EXYNOS5420_ATB_KFC                                      BIT(13)
+#define EXYNOS5420_ATB_ISP_ARM                                  BIT(19)
+#define EXYNOS5420_EMULATION                                    BIT(31)
+#define ATB_ISP_ARM                                             BIT(12)
+#define ATB_KFC                                                 BIT(13)
+#define ATB_NOC                                                 BIT(14)
+#define EXYNOS5420_ARM_INTR_SPREAD_ENABLE                       0x0100
+#define EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI               0x0104
+#define EXYNOS5420_UP_SCHEDULER                                 0x0120
+#define SPREAD_ENABLE                                           0xF
+#define SPREAD_USE_STANDWFI                                     0xF
+#define EXYNOS5420_BB_CON1                                      0x0784
+#define EXYNOS5420_BB_SEL_EN                                    BIT(31)
+#define EXYNOS5420_BB_PMOS_EN                                   BIT(7)
+#define EXYNOS5420_BB_1300X                                     0XF
+#define EXYNOS5420_ARM_CORE2_SYS_PWR_REG                        0x1020
+#define EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG          0x1024
+#define EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG        0x1028
+#define EXYNOS5420_ARM_CORE3_SYS_PWR_REG                        0x1030
+#define EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG          0x1034
+#define EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG        0x1038
+#define EXYNOS5420_KFC_CORE0_SYS_PWR_REG                        0x1040
+#define EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG          0x1044
+#define EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG        0x1048
+#define EXYNOS5420_KFC_CORE1_SYS_PWR_REG                        0x1050
+#define EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG          0x1054
+#define EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG        0x1058
+#define EXYNOS5420_KFC_CORE2_SYS_PWR_REG                        0x1060
+#define EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG          0x1064
+#define EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG        0x1068
+#define EXYNOS5420_KFC_CORE3_SYS_PWR_REG                        0x1070
+#define EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG          0x1074
+#define EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG        0x1078
+#define EXYNOS5420_ISP_ARM_SYS_PWR_REG                          0x1090
+#define EXYNOS5420_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG            0x1094
+#define EXYNOS5420_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG          0x1098
+#define EXYNOS5420_ARM_COMMON_SYS_PWR_REG                       0x10A0
+#define EXYNOS5420_KFC_COMMON_SYS_PWR_REG                       0x10B0
+#define EXYNOS5420_KFC_L2_SYS_PWR_REG                           0x10D0
+#define EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG                      0x1158
+#define EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG                      0x115C
+#define EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG                      0x1160
+#define EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG                      0x1174
+#define EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG                      0x1178
+#define EXYNOS5420_INTRAM_MEM_SYS_PWR_REG                       0x11B8
+#define EXYNOS5420_INTROM_MEM_SYS_PWR_REG                       0x11BC
+#define EXYNOS5420_ONENANDXL_MEM_SYS_PWR                        0x11C0
+#define EXYNOS5420_USBDEV_MEM_SYS_PWR                           0x11CC
+#define EXYNOS5420_USBDEV1_MEM_SYS_PWR                          0x11D0
+#define EXYNOS5420_SDMMC_MEM_SYS_PWR                            0x11D4
+#define EXYNOS5420_CSSYS_MEM_SYS_PWR                            0x11D8
+#define EXYNOS5420_SECSS_MEM_SYS_PWR                            0x11DC
+#define EXYNOS5420_ROTATOR_MEM_SYS_PWR                          0x11E0
+#define EXYNOS5420_INTRAM_MEM_SYS_PWR                           0x11E4
+#define EXYNOS5420_INTROM_MEM_SYS_PWR                           0x11E8
+#define EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG               0x1208
+#define EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG               0x1210
+#define EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG               0x1214
+#define EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_REG               0x1218
+#define EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_REG               0x121C
+#define EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_REG               0x1220
+#define EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_REG                0x1224
+#define EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_REG               0x1228
+#define EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_REG               0x122C
+#define EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_REG                0x1230
+#define EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_SYS_PWR_REG       0x1234
+#define EXYNOS5420_DISP1_SYS_PWR_REG                            0x1410
+#define EXYNOS5420_MAU_SYS_PWR_REG                              0x1414
+#define EXYNOS5420_G2D_SYS_PWR_REG                              0x1418
+#define EXYNOS5420_MSC_SYS_PWR_REG                              0x141C
+#define EXYNOS5420_FSYS_SYS_PWR_REG                             0x1420
+#define EXYNOS5420_FSYS2_SYS_PWR_REG                            0x1424
+#define EXYNOS5420_PSGEN_SYS_PWR_REG                            0x1428
+#define EXYNOS5420_PERIC_SYS_PWR_REG                            0x142C
+#define EXYNOS5420_WCORE_SYS_PWR_REG                            0x1430
+#define EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG                0x1490
+#define EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG                  0x1494
+#define EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG                  0x1498
+#define EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG                  0x149C
+#define EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG                 0x14A0
+#define EXYNOS5420_CMU_CLKSTOP_FSYS2_SYS_PWR_REG                0x14A4
+#define EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG                0x14A8
+#define EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG                0x14AC
+#define EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG                0x14B0
+#define EXYNOS5420_CMU_SYSCLK_TOPPWR_SYS_PWR_REG                0x14BC
+#define EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG                 0x14D0
+#define EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG                   0x14D4
+#define EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG                   0x14D8
+#define EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG                   0x14DC
+#define EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG                  0x14E0
+#define EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG                 0x14E4
+#define EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG                 0x14E8
+#define EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG                 0x14EC
+#define EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG                 0x14F0
+#define EXYNOS5420_CMU_SYSCLK_SYSMEM_TOPPWR_SYS_PWR_REG         0x14F4
+#define EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG                  0x1570
+#define EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG                  0x1574
+#define EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG                  0x1578
+#define EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG                  0x157C
+#define EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG                  0x1590
+#define EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG                    0x1594
+#define EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG                    0x1598
+#define EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG                    0x159C
+#define EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG                   0x15A0
+#define EXYNOS5420_SFR_AXI_CGDIS1                               0x15E4
+#define EXYNOS_ARM_CORE2_CONFIGURATION                          0x2100
+#define EXYNOS5420_ARM_CORE2_OPTION                             0x2108
+#define EXYNOS_ARM_CORE3_CONFIGURATION                          0x2180
+#define EXYNOS5420_ARM_CORE3_OPTION                             0x2188
+#define EXYNOS5420_ARM_COMMON_STATUS                            0x2504
+#define EXYNOS5420_ARM_COMMON_OPTION                            0x2508
+#define EXYNOS5420_KFC_COMMON_STATUS                            0x2584
+#define EXYNOS5420_KFC_COMMON_OPTION                            0x2588
+#define EXYNOS5420_LOGIC_RESET_DURATION3                        0x2D1C
+#define EXYNOS5420_PAD_RET_GPIO_OPTION                          0x30C8
+#define EXYNOS5420_PAD_RET_UART_OPTION                          0x30E8
+#define EXYNOS5420_PAD_RET_MMCA_OPTION                          0x3108
+#define EXYNOS5420_PAD_RET_MMCB_OPTION                          0x3128
+#define EXYNOS5420_PAD_RET_MMCC_OPTION                          0x3148
+#define EXYNOS5420_PAD_RET_HSI_OPTION                           0x3168
+#define EXYNOS5420_PAD_RET_SPI_OPTION                           0x31C8
+#define EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION                  0x31E8
+#define EXYNOS_PAD_RET_DRAM_OPTION                              0x3008
+#define EXYNOS_PAD_RET_MAUDIO_OPTION                            0x3028
+#define EXYNOS_PAD_RET_JTAG_OPTION                              0x3048
+#define EXYNOS_PAD_RET_GPIO_OPTION                              0x3108
+#define EXYNOS_PAD_RET_UART_OPTION                              0x3128
+#define EXYNOS_PAD_RET_MMCA_OPTION                              0x3148
+#define EXYNOS_PAD_RET_MMCB_OPTION                              0x3168
+#define EXYNOS_PAD_RET_EBIA_OPTION                              0x3188
+#define EXYNOS_PAD_RET_EBIB_OPTION                              0x31A8
+#define EXYNOS_PS_HOLD_CONTROL                                  0x330C
+/* For SYS_PWR_REG */
+#define EXYNOS_SYS_PWR_CFG                                      BIT(0)
+#define EXYNOS5420_MFC_CONFIGURATION                            0x4060
+#define EXYNOS5420_MFC_STATUS                                   0x4064
+#define EXYNOS5420_MFC_OPTION                                   0x4068
+#define EXYNOS5420_G3D_CONFIGURATION                            0x4080
+#define EXYNOS5420_G3D_STATUS                                   0x4084
+#define EXYNOS5420_G3D_OPTION                                   0x4088
+#define EXYNOS5420_DISP0_CONFIGURATION                          0x40A0
+#define EXYNOS5420_DISP0_STATUS                                 0x40A4
+#define EXYNOS5420_DISP0_OPTION                                 0x40A8
+#define EXYNOS5420_DISP1_CONFIGURATION                          0x40C0
+#define EXYNOS5420_DISP1_STATUS                                 0x40C4
+#define EXYNOS5420_DISP1_OPTION                                 0x40C8
+#define EXYNOS5420_MAU_CONFIGURATION                            0x40E0
+#define EXYNOS5420_MAU_STATUS                                   0x40E4
+#define EXYNOS5420_MAU_OPTION                                   0x40E8
+#define EXYNOS5420_FSYS2_OPTION                                 0x4168
+#define EXYNOS5420_PSGEN_OPTION                                 0x4188
+/* For EXYNOS_CENTRAL_SEQ_OPTION */
+#define EXYNOS5_USE_STANDBYWFI_ARM_CORE0                        BIT(16)
+#define EXYNOS5_USE_STANDBYWFI_ARM_CORE1                        BUT(17)
+#define EXYNOS5_USE_STANDBYWFE_ARM_CORE0                        BIT(24)
+#define EXYNOS5_USE_STANDBYWFE_ARM_CORE1                        BIT(25)
+#define EXYNOS5420_ARM_USE_STANDBY_WFI0                         BIT(4)
+#define EXYNOS5420_ARM_USE_STANDBY_WFI1                         BIT(5)
+#define EXYNOS5420_ARM_USE_STANDBY_WFI2                         BIT(6)
+#define EXYNOS5420_ARM_USE_STANDBY_WFI3                         BIT(7)
+#define EXYNOS5420_KFC_USE_STANDBY_WFI0                         BIT(8)
+#define EXYNOS5420_KFC_USE_STANDBY_WFI1                         BIT(9)
+#define EXYNOS5420_KFC_USE_STANDBY_WFI2                         BIT(10)
+#define EXYNOS5420_KFC_USE_STANDBY_WFI3                         BIT(11)
+#define EXYNOS5420_ARM_USE_STANDBY_WFE0                         BIT(16)
+#define EXYNOS5420_ARM_USE_STANDBY_WFE1                         BIT(17)
+#define EXYNOS5420_ARM_USE_STANDBY_WFE2                         BIT(18)
+#define EXYNOS5420_ARM_USE_STANDBY_WFE3                         BIT(19)
+#define EXYNOS5420_KFC_USE_STANDBY_WFE0                         BIT(20)
+#define EXYNOS5420_KFC_USE_STANDBY_WFE1                         BIT(21)
+#define EXYNOS5420_KFC_USE_STANDBY_WFE2                         BIT(22)
+#define EXYNOS5420_KFC_USE_STANDBY_WFE3                         BIT(23)
+#define DUR_WAIT_RESET                          0xF
+#define EXYNOS5420_USE_STANDBY_WFI_ALL  (EXYNOS5420_ARM_USE_STANDBY_WFI0    \
+                                         | EXYNOS5420_ARM_USE_STANDBY_WFI1  \
+                                         | EXYNOS5420_ARM_USE_STANDBY_WFI2  \
+                                         | EXYNOS5420_ARM_USE_STANDBY_WFI3  \
+                                         | EXYNOS5420_KFC_USE_STANDBY_WFI0  \
+                                         | EXYNOS5420_KFC_USE_STANDBY_WFI1  \
+                                         | EXYNOS5420_KFC_USE_STANDBY_WFI2  \
+                                         | EXYNOS5420_KFC_USE_STANDBY_WFI3)
 #endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S
index 108a45f4bb62..e3c373082bbe 100644
--- a/arch/arm/mach-exynos/sleep.S
+++ b/arch/arm/mach-exynos/sleep.S
@@ -16,6 +16,7 @@
 */
 #include <linux/linkage.h>
+#include "smc.h"
 #define CPU_MASK        0xff0ffff0
 #define CPU_CORTEX_A9   0x410fc090
@@ -55,3 +56,30 @@ ENTRY(exynos_cpu_resume)
 #endif
        b       cpu_resume
 ENDPROC(exynos_cpu_resume)
+        .align
+ENTRY(exynos_cpu_resume_ns)
+        mrc     p15, 0, r0, c0, c0, 0
+        ldr     r1, =CPU_MASK
+        and     r0, r0, r1
+        ldr     r1, =CPU_CORTEX_A9
+        cmp     r0, r1
+        bne     skip_cp15
+        adr     r0, cp15_save_power
+        ldr     r1, [r0]
+        adr     r0, cp15_save_diag
+        ldr     r2, [r0]
+        mov     r0, #SMC_CMD_C15RESUME
+        dsb
+        smc     #0
+skip_cp15:
+        b       cpu_resume
+ENDPROC(exynos_cpu_resume_ns)
+        .globl cp15_save_diag
+cp15_save_diag:
+        .long   0       @ cp15 diagnostic
+        .globl cp15_save_power
+cp15_save_power:
+        .long   0       @ cp15 power control
diff --git a/arch/arm/mach-exynos/smc.h b/arch/arm/mach-exynos/smc.h
index 13a1dc8ecbf2..f7b82f9c1e21 100644
--- a/arch/arm/mach-exynos/smc.h
+++ b/arch/arm/mach-exynos/smc.h
@@ -26,6 +26,10 @@
 #define SMC_CMD_L2X0INVALL      (-24)
 #define SMC_CMD_L2X0DEBUG       (-25)
+#ifndef __ASSEMBLY__
 extern void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3);
+#endif /* __ASSEMBLY__ */
 #endif
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
new file mode 100644
index 000000000000..f8e7dcd17055
--- /dev/null
+++ b/arch/arm/mach-exynos/suspend.c
@@ -0,0 +1,566 @@
+/*
+ * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS - Suspend support
+ *
+ * Based on arch/arm/mach-s3c2410/pm.c
+ * Copyright (c) 2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/suspend.h>
+#include <linux/syscore_ops.h>
+#include <linux/cpu_pm.h>
+#include <linux/io.h>
+#include <linux/irqchip/arm-gic.h>
+#include <linux/err.h>
+#include <linux/regulator/machine.h>
+#include <asm/cacheflush.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/firmware.h>
+#include <asm/mcpm.h>
+#include <asm/smp_scu.h>
+#include <asm/suspend.h>
+#include <plat/pm-common.h>
+#include <plat/regs-srom.h>
+#include "common.h"
+#include "regs-pmu.h"
+#include "regs-sys.h"
+#include "exynos-pmu.h"
+#define S5P_CHECK_SLEEP 0x00000BAD
+#define REG_TABLE_END (-1U)
+#define EXYNOS5420_CPU_STATE    0x28
+/**
+ * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
+ * @hwirq: Hardware IRQ signal of the GIC
+ * @mask: Mask in PMU wake-up mask register
+ */
+struct exynos_wkup_irq {
+        unsigned int hwirq;
+        u32 mask;
+};
+static struct sleep_save exynos5_sys_save[] = {
+        SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
+};
+static struct sleep_save exynos_core_save[] = {
+        /* SROM side */
+        SAVE_ITEM(S5P_SROM_BW),
+        SAVE_ITEM(S5P_SROM_BC0),
+        SAVE_ITEM(S5P_SROM_BC1),
+        SAVE_ITEM(S5P_SROM_BC2),
+        SAVE_ITEM(S5P_SROM_BC3),
+};
+struct exynos_pm_data {
+        const struct exynos_wkup_irq *wkup_irq;
+        struct sleep_save *extra_save;
+        int num_extra_save;
+        unsigned int wake_disable_mask;
+        unsigned int *release_ret_regs;
+        void (*pm_prepare)(void);
+        void (*pm_resume_prepare)(void);
+        void (*pm_resume)(void);
+        int (*pm_suspend)(void);
+        int (*cpu_suspend)(unsigned long);
+};
+struct exynos_pm_data *pm_data;
+static int exynos5420_cpu_state;
+static unsigned int exynos_pmu_spare3;
+/*
+ * GIC wake-up support
+ */
+static u32 exynos_irqwake_intmask = 0xffffffff;
+static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
+        { 76, BIT(1) }, /* RTC alarm */
+        { 77, BIT(2) }, /* RTC tick */
+        { /* sentinel */ },
+};
+static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
+        { 75, BIT(1) }, /* RTC alarm */
+        { 76, BIT(2) }, /* RTC tick */
+        { /* sentinel */ },
+};
+unsigned int exynos_release_ret_regs[] = {
+        S5P_PAD_RET_MAUDIO_OPTION,
+        S5P_PAD_RET_GPIO_OPTION,
+        S5P_PAD_RET_UART_OPTION,
+        S5P_PAD_RET_MMCA_OPTION,
+        S5P_PAD_RET_MMCB_OPTION,
+        S5P_PAD_RET_EBIA_OPTION,
+        S5P_PAD_RET_EBIB_OPTION,
+        REG_TABLE_END,
+};
+unsigned int exynos5420_release_ret_regs[] = {
+        EXYNOS_PAD_RET_DRAM_OPTION,
+        EXYNOS_PAD_RET_MAUDIO_OPTION,
+        EXYNOS_PAD_RET_JTAG_OPTION,
+        EXYNOS5420_PAD_RET_GPIO_OPTION,
+        EXYNOS5420_PAD_RET_UART_OPTION,
+        EXYNOS5420_PAD_RET_MMCA_OPTION,
+        EXYNOS5420_PAD_RET_MMCB_OPTION,
+        EXYNOS5420_PAD_RET_MMCC_OPTION,
+        EXYNOS5420_PAD_RET_HSI_OPTION,
+        EXYNOS_PAD_RET_EBIA_OPTION,
+        EXYNOS_PAD_RET_EBIB_OPTION,
+        EXYNOS5420_PAD_RET_SPI_OPTION,
+        EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION,
+        REG_TABLE_END,
+};
+static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
+{
+        const struct exynos_wkup_irq *wkup_irq;
+        if (!pm_data->wkup_irq)
+                return -ENOENT;
+        wkup_irq = pm_data->wkup_irq;
+        while (wkup_irq->mask) {
+                if (wkup_irq->hwirq == data->hwirq) {
+                        if (!state)
+                                exynos_irqwake_intmask |= wkup_irq->mask;
+                        else
+                                exynos_irqwake_intmask &= ~wkup_irq->mask;
+                        return 0;
+                }
+                ++wkup_irq;
+        }
+        return -ENOENT;
+}
+static int exynos_cpu_do_idle(void)
+{
+        /* issue the standby signal into the pm unit. */
+        cpu_do_idle();
+        pr_info("Failed to suspend the system\n");
+        return 1; /* Aborting suspend */
+}
+static void exynos_flush_cache_all(void)
+{
+        flush_cache_all();
+        outer_flush_all();
+}
+static int exynos_cpu_suspend(unsigned long arg)
+{
+        exynos_flush_cache_all();
+        return exynos_cpu_do_idle();
+}
+static int exynos5420_cpu_suspend(unsigned long arg)
+{
+        /* MCPM works with HW CPU identifiers */
+        unsigned int mpidr = read_cpuid_mpidr();
+        unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+        unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        __raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
+        if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
+                mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
+                /*
+                 * Residency value passed to mcpm_cpu_suspend back-end
+                 * has to be given clear semantics. Set to 0 as a
+                 * temporary value.
+                 */
+                mcpm_cpu_suspend(0);
+        }
+        pr_info("Failed to suspend the system\n");
+        /* return value != 0 means failure */
+        return 1;
+}
+static void exynos_pm_set_wakeup_mask(void)
+{
+        /* Set wake-up mask registers */
+        pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
+        pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
+}
+static void exynos_pm_enter_sleep_mode(void)
+{
+        /* Set value of power down register for sleep mode */
+        exynos_sys_powerdown_conf(SYS_SLEEP);
+        pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
+}
+static void exynos_pm_prepare(void)
+{
+        /* Set wake-up mask registers */
+        exynos_pm_set_wakeup_mask();
+        s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
+         if (pm_data->extra_save)
+                s3c_pm_do_save(pm_data->extra_save,
+                                pm_data->num_extra_save);
+        exynos_pm_enter_sleep_mode();
+        /* ensure at least INFORM0 has the resume address */
+        pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
+}
+static void exynos5420_pm_prepare(void)
+{
+        unsigned int tmp;
+        /* Set wake-up mask registers */
+        exynos_pm_set_wakeup_mask();
+        s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
+        exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
+        /*
+         * The cpu state needs to be saved and restored so that the
+         * secondary CPUs will enter low power start. Though the U-Boot
+         * is setting the cpu state with low power flag, the kernel
+         * needs to restore it back in case, the primary cpu fails to
+         * suspend for any reason.
+         */
+        exynos5420_cpu_state = __raw_readl(sysram_base_addr +
+                                                EXYNOS5420_CPU_STATE);
+        exynos_pm_enter_sleep_mode();
+        /* ensure at least INFORM0 has the resume address */
+        if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
+                pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
+        tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION);
+        tmp &= ~EXYNOS5_USE_RETENTION;
+        pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
+        tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
+        tmp |= EXYNOS5420_UFS;
+        pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
+        tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
+        tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE;
+        pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION);
+        tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
+        tmp |= EXYNOS5420_EMULATION;
+        pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
+        tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
+        tmp |= EXYNOS5420_EMULATION;
+        pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
+}
+static int exynos_pm_suspend(void)
+{
+        exynos_pm_central_suspend();
+        if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
+                exynos_cpu_save_register();
+        return 0;
+}
+static int exynos5420_pm_suspend(void)
+{
+        u32 this_cluster;
+        exynos_pm_central_suspend();
+        /* Setting SEQ_OPTION register */
+        this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
+        if (!this_cluster)
+                pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0,
+                                S5P_CENTRAL_SEQ_OPTION);
+        else
+                pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0,
+                                S5P_CENTRAL_SEQ_OPTION);
+        return 0;
+}
+static void exynos_pm_release_retention(void)
+{
+        unsigned int i;
+        for (i = 0; (pm_data->release_ret_regs[i] != REG_TABLE_END); i++)
+                pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR,
+                                pm_data->release_ret_regs[i]);
+}
+static void exynos_pm_resume(void)
+{
+        u32 cpuid = read_cpuid_part();
+        if (exynos_pm_central_resume())
+                goto early_wakeup;
+        /* For release retention */
+        exynos_pm_release_retention();
+        if (pm_data->extra_save)
+                s3c_pm_do_restore_core(pm_data->extra_save,
+                                        pm_data->num_extra_save);
+        s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
+        if (cpuid == ARM_CPU_PART_CORTEX_A9)
+                scu_enable(S5P_VA_SCU);
+        if (call_firmware_op(resume) == -ENOSYS
+            && cpuid == ARM_CPU_PART_CORTEX_A9)
+                exynos_cpu_restore_register();
+early_wakeup:
+        /* Clear SLEEP mode set in INFORM1 */
+        pmu_raw_writel(0x0, S5P_INFORM1);
+}
+static void exynos5420_prepare_pm_resume(void)
+{
+        if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
+                WARN_ON(mcpm_cpu_powered_up());
+}
+static void exynos5420_pm_resume(void)
+{
+        unsigned long tmp;
+        /* Restore the CPU0 low power state register */
+        tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
+        pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
+                EXYNOS5_ARM_CORE0_SYS_PWR_REG);
+        /* Restore the sysram cpu state register */
+        __raw_writel(exynos5420_cpu_state,
+                sysram_base_addr + EXYNOS5420_CPU_STATE);
+        pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
+                        S5P_CENTRAL_SEQ_OPTION);
+        if (exynos_pm_central_resume())
+                goto early_wakeup;
+        /* For release retention */
+        exynos_pm_release_retention();
+        pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3);
+        s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
+early_wakeup:
+        tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
+        tmp &= ~EXYNOS5420_UFS;
+        pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
+        tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
+        tmp &= ~EXYNOS5420_EMULATION;
+        pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
+        tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
+        tmp &= ~EXYNOS5420_EMULATION;
+        pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
+        /* Clear SLEEP mode set in INFORM1 */
+        pmu_raw_writel(0x0, S5P_INFORM1);
+}
+/*
+ * Suspend Ops
+ */
+static int exynos_suspend_enter(suspend_state_t state)
+{
+        int ret;
+        s3c_pm_debug_init();
+        S3C_PMDBG("%s: suspending the system...\n", __func__);
+        S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
+                        exynos_irqwake_intmask, exynos_get_eint_wake_mask());
+        if (exynos_irqwake_intmask == -1U
+            && exynos_get_eint_wake_mask() == -1U) {
+                pr_err("%s: No wake-up sources!\n", __func__);
+                pr_err("%s: Aborting sleep\n", __func__);
+                return -EINVAL;
+        }
+        s3c_pm_save_uarts();
+        if (pm_data->pm_prepare)
+                pm_data->pm_prepare();
+        flush_cache_all();
+        s3c_pm_check_store();
+        ret = call_firmware_op(suspend);
+        if (ret == -ENOSYS)
+                ret = cpu_suspend(0, pm_data->cpu_suspend);
+        if (ret)
+                return ret;
+        if (pm_data->pm_resume_prepare)
+                pm_data->pm_resume_prepare();
+        s3c_pm_restore_uarts();
+        S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
+                        pmu_raw_readl(S5P_WAKEUP_STAT));
+        s3c_pm_check_restore();
+        S3C_PMDBG("%s: resuming the system...\n", __func__);
+        return 0;
+}
+static int exynos_suspend_prepare(void)
+{
+        int ret;
+        /*
+         * REVISIT: It would be better if struct platform_suspend_ops
+         * .prepare handler get the suspend_state_t as a parameter to
+         * avoid hard-coding the suspend to mem state. It's safe to do
+         * it now only because the suspend_valid_only_mem function is
+         * used as the .valid callback used to check if a given state
+         * is supported by the platform anyways.
+         */
+        ret = regulator_suspend_prepare(PM_SUSPEND_MEM);
+        if (ret) {
+                pr_err("Failed to prepare regulators for suspend (%d)\n", ret);
+                return ret;
+        }
+        s3c_pm_check_prepare();
+        return 0;
+}
+static void exynos_suspend_finish(void)
+{
+        int ret;
+        s3c_pm_check_cleanup();
+        ret = regulator_suspend_finish();
+        if (ret)
+                pr_warn("Failed to resume regulators from suspend (%d)\n", ret);
+}
+static const struct platform_suspend_ops exynos_suspend_ops = {
+        .enter          = exynos_suspend_enter,
+        .prepare        = exynos_suspend_prepare,
+        .finish         = exynos_suspend_finish,
+        .valid          = suspend_valid_only_mem,
+};
+static const struct exynos_pm_data exynos4_pm_data = {
+        .wkup_irq       = exynos4_wkup_irq,
+        .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
+        .release_ret_regs = exynos_release_ret_regs,
+        .pm_suspend     = exynos_pm_suspend,
+        .pm_resume      = exynos_pm_resume,
+        .pm_prepare     = exynos_pm_prepare,
+        .cpu_suspend    = exynos_cpu_suspend,
+};
+static const struct exynos_pm_data exynos5250_pm_data = {
+        .wkup_irq       = exynos5250_wkup_irq,
+        .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
+        .release_ret_regs = exynos_release_ret_regs,
+        .extra_save     = exynos5_sys_save,
+        .num_extra_save = ARRAY_SIZE(exynos5_sys_save),
+        .pm_suspend     = exynos_pm_suspend,
+        .pm_resume      = exynos_pm_resume,
+        .pm_prepare     = exynos_pm_prepare,
+        .cpu_suspend    = exynos_cpu_suspend,
+};
+static struct exynos_pm_data exynos5420_pm_data = {
+        .wkup_irq       = exynos5250_wkup_irq,
+        .wake_disable_mask = (0x7F << 7) | (0x1F << 1),
+        .release_ret_regs = exynos5420_release_ret_regs,
+        .pm_resume_prepare = exynos5420_prepare_pm_resume,
+        .pm_resume      = exynos5420_pm_resume,
+        .pm_suspend     = exynos5420_pm_suspend,
+        .pm_prepare     = exynos5420_pm_prepare,
+        .cpu_suspend    = exynos5420_cpu_suspend,
+};
+static struct of_device_id exynos_pmu_of_device_ids[] = {
+        {
+                .compatible = "samsung,exynos4210-pmu",
+                .data = &exynos4_pm_data,
+        }, {
+                .compatible = "samsung,exynos4212-pmu",
+                .data = &exynos4_pm_data,
+        }, {
+                .compatible = "samsung,exynos4412-pmu",
+                .data = &exynos4_pm_data,
+        }, {
+                .compatible = "samsung,exynos5250-pmu",
+                .data = &exynos5250_pm_data,
+        }, {
+                .compatible = "samsung,exynos5420-pmu",
+                .data = &exynos5420_pm_data,
+        },
+        { /*sentinel*/ },
+};
+static struct syscore_ops exynos_pm_syscore_ops;
+void __init exynos_pm_init(void)
+{
+        const struct of_device_id *match;
+        u32 tmp;
+        of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match);
+        if (!match) {
+                pr_err("Failed to find PMU node\n");
+                return;
+        }
+        pm_data = (struct exynos_pm_data *) match->data;
+        /* Platform-specific GIC callback */
+        gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
+        /* All wakeup disable */
+        tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
+        tmp |= pm_data->wake_disable_mask;
+        pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
+        exynos_pm_syscore_ops.suspend   = pm_data->pm_suspend;
+        exynos_pm_syscore_ops.resume    = pm_data->pm_resume;
+        register_syscore_ops(&exynos_pm_syscore_ops);
+        suspend_set_ops(&exynos_suspend_ops);
+}
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 11b2957f792b..e8627e04e1e6 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -633,12 +633,41 @@ config SOC_VF610
        bool "Vybrid Family VF610 support"
        select ARM_GIC
        select PINCTRL_VF610
-        select VF_PIT_TIMER
        select PL310_ERRATA_769419 if CACHE_L2X0
        help
          This enable support for Freescale Vybrid VF610 processor.
+choice
+        prompt "Clocksource for scheduler clock"
+        depends on SOC_VF610
+        default VF_USE_ARM_GLOBAL_TIMER
+        config VF_USE_ARM_GLOBAL_TIMER
+                bool "Use ARM Global Timer"
+                select ARM_GLOBAL_TIMER
+                select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
+                help
+                  Use the ARM Global Timer as clocksource
+        config VF_USE_PIT_TIMER
+                bool "Use PIT timer"
+                select VF_PIT_TIMER
+                help
+                  Use SoC Periodic Interrupt Timer (PIT) as clocksource
+endchoice
+config SOC_LS1021A
+        bool "Freescale LS1021A support"
+        select ARM_GIC
+        select HAVE_ARM_ARCH_TIMER
+        select PCI_DOMAINS if PCI
+        select ZONE_DMA if ARM_LPAE
+        help
+          This enable support for Freescale LS1021A processor.
 endif
 source "arch/arm/mach-imx/devices/Kconfig"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 6e4fcd8339cd..f5ac685a29fc 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -12,7 +12,7 @@ obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-
 obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
 imx5-pm-$(CONFIG_PM) += pm-imx5.o
-obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o $(imx5-pm-y)
+obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o clk-cpu.o $(imx5-pm-y)
 obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
                            clk-pfd.o clk-busy.o clk.o \
@@ -89,7 +89,7 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
 obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
 obj-$(CONFIG_HAVE_IMX_SRC) += src.o
-ifdef CONFIG_SOC_IMX6
+ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),)
 AFLAGS_headsmp.o :=-Wa,-march=armv7-a
 obj-$(CONFIG_SMP) += headsmp.o platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
@@ -110,4 +110,6 @@ obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
 obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
+obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o
 obj-y += devices/
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
index 8259a625a920..7f262fe4ba77 100644
--- a/arch/arm/mach-imx/anatop.c
+++ b/arch/arm/mach-imx/anatop.c
@@ -30,8 +30,11 @@
 #define ANADIG_DIGPROG_IMX6SL   0x280
 #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG    0x40000
+#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN       0x8
 #define BM_ANADIG_REG_CORE_FET_ODRIVE           0x20000000
 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG    0x1000
+/* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */
+#define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS    0x2000
 #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B    0x80000
 #define BM_ANADIG_USB_CHRG_DETECT_EN_B          0x100000
@@ -56,16 +59,43 @@ static void imx_anatop_enable_fet_odrive(bool enable)
                BM_ANADIG_REG_CORE_FET_ODRIVE);
 }
+static inline void imx_anatop_enable_2p5_pulldown(bool enable)
+{
+        regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR),
+                BM_ANADIG_REG_2P5_ENABLE_PULLDOWN);
+}
+static inline void imx_anatop_disconnect_high_snvs(bool enable)
+{
+        regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR),
+                BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS);
+}
 void imx_anatop_pre_suspend(void)
 {
-        imx_anatop_enable_weak2p5(true);
+        if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
+                imx_anatop_enable_2p5_pulldown(true);
+        else
+                imx_anatop_enable_weak2p5(true);
        imx_anatop_enable_fet_odrive(true);
+        if (cpu_is_imx6sl())
+                imx_anatop_disconnect_high_snvs(true);
 }
 void imx_anatop_post_resume(void)
 {
+        if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
+                imx_anatop_enable_2p5_pulldown(false);
+        else
+                imx_anatop_enable_weak2p5(false);
        imx_anatop_enable_fet_odrive(false);
-        imx_anatop_enable_weak2p5(false);
+        if (cpu_is_imx6sl())
+                imx_anatop_disconnect_high_snvs(false);
 }
 static void imx_anatop_usb_chrg_detect_disable(void)
diff --git a/arch/arm/mach-imx/clk-cpu.c b/arch/arm/mach-imx/clk-cpu.c
new file mode 100644
index 000000000000..aa1c345e2a19
--- /dev/null
+++ b/arch/arm/mach-imx/clk-cpu.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2014 Lucas Stach <l.stach@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+struct clk_cpu {
+        struct clk_hw   hw;
+        struct clk      *div;
+        struct clk      *mux;
+        struct clk      *pll;
+        struct clk      *step;
+};
+static inline struct clk_cpu *to_clk_cpu(struct clk_hw *hw)
+{
+        return container_of(hw, struct clk_cpu, hw);
+}
+static unsigned long clk_cpu_recalc_rate(struct clk_hw *hw,
+                                         unsigned long parent_rate)
+{
+        struct clk_cpu *cpu = to_clk_cpu(hw);
+        return clk_get_rate(cpu->div);
+}
+static long clk_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long *prate)
+{
+        struct clk_cpu *cpu = to_clk_cpu(hw);
+        return clk_round_rate(cpu->pll, rate);
+}
+static int clk_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
+                            unsigned long parent_rate)
+{
+        struct clk_cpu *cpu = to_clk_cpu(hw);
+        int ret;
+        /* switch to PLL bypass clock */
+        ret = clk_set_parent(cpu->mux, cpu->step);
+        if (ret)
+                return ret;
+        /* reprogram PLL */
+        ret = clk_set_rate(cpu->pll, rate);
+        if (ret) {
+                clk_set_parent(cpu->mux, cpu->pll);
+                return ret;
+        }
+        /* switch back to PLL clock */
+        clk_set_parent(cpu->mux, cpu->pll);
+        /* Ensure the divider is what we expect */
+        clk_set_rate(cpu->div, rate);
+        return 0;
+}
+static const struct clk_ops clk_cpu_ops = {
+        .recalc_rate    = clk_cpu_recalc_rate,
+        .round_rate     = clk_cpu_round_rate,
+        .set_rate       = clk_cpu_set_rate,
+};
+struct clk *imx_clk_cpu(const char *name, const char *parent_name,
+                struct clk *div, struct clk *mux, struct clk *pll,
+                struct clk *step)
+{
+        struct clk_cpu *cpu;
+        struct clk *clk;
+        struct clk_init_data init;
+        cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
+        if (!cpu)
+                return ERR_PTR(-ENOMEM);
+        cpu->div = div;
+        cpu->mux = mux;
+        cpu->pll = pll;
+        cpu->step = step;
+        init.name = name;
+        init.ops = &clk_cpu_ops;
+        init.flags = 0;
+        init.parent_names = &parent_name;
+        init.num_parents = 1;
+        cpu->hw.init = &init;
+        clk = clk_register(NULL, &cpu->hw);
+        if (IS_ERR(clk))
+                kfree(cpu);
+        return clk;
+}
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 72d65214223e..0f7e536147cb 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -125,6 +125,8 @@ static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw",
 static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", };
 static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
 static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
+static const char *step_sels[] = { "lp_apm", };
+static const char *cpu_podf_sels[] = { "pll1_sw", "step_sel" };
 static struct clk *clk[IMX5_CLK_END];
 static struct clk_onecell_data clk_data;
@@ -193,7 +195,9 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base)
        clk[IMX5_CLK_USB_PHY_PODF]      = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
        clk[IMX5_CLK_USB_PHY_SEL]       = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
                                                usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
-        clk[IMX5_CLK_CPU_PODF]          = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
+        clk[IMX5_CLK_STEP_SEL]          = imx_clk_mux("step_sel", MXC_CCM_CCSR, 7, 2, step_sels, ARRAY_SIZE(step_sels));
+        clk[IMX5_CLK_CPU_PODF_SEL]      = imx_clk_mux("cpu_podf_sel", MXC_CCM_CCSR, 2, 1, cpu_podf_sels, ARRAY_SIZE(cpu_podf_sels));
+        clk[IMX5_CLK_CPU_PODF]          = imx_clk_divider("cpu_podf", "cpu_podf_sel", MXC_CCM_CACRR, 0, 3);
        clk[IMX5_CLK_DI_PRED]           = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
        clk[IMX5_CLK_IIM_GATE]          = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
        clk[IMX5_CLK_UART1_IPG_GATE]    = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
@@ -537,6 +541,11 @@ static void __init mx53_clocks_init(struct device_node *np)
        clk[IMX5_CLK_CKO2]              = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
        clk[IMX5_CLK_SPDIF_XTAL_SEL]    = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
                                                mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
+        clk[IMX5_CLK_ARM]               = imx_clk_cpu("arm", "cpu_podf",
+                                                clk[IMX5_CLK_CPU_PODF],
+                                                clk[IMX5_CLK_CPU_PODF_SEL],
+                                                clk[IMX5_CLK_PLL1_SW],
+                                                clk[IMX5_CLK_STEP_SEL]);
        imx_check_clocks(clk, ARRAY_SIZE(clk));
@@ -551,6 +560,9 @@ static void __init mx53_clocks_init(struct device_node *np)
        /* move can bus clk to 24MHz */
        clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]);
+        /* make sure step clock is running from 24MHz */
+        clk_set_parent(clk[IMX5_CLK_STEP_SEL], clk[IMX5_CLK_LP_APM]);
        clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
        imx_print_silicon_rev("i.MX53", mx53_revision());
        clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 4e79da7c5e30..5951660d1bd2 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -145,7 +145,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
                post_div_table[2].div = 1;
                video_div_table[1].div = 1;
                video_div_table[2].div = 1;
-        };
+        }
        clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
        clk[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index 57de74da0acf..0ad6e5442fd8 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -69,7 +69,6 @@ static int clk_pllv3_prepare(struct clk_hw *hw)
 {
        struct clk_pllv3 *pll = to_clk_pllv3(hw);
        u32 val;
-        int ret;
        val = readl_relaxed(pll->base);
        if (pll->powerup_set)
@@ -78,11 +77,7 @@ static int clk_pllv3_prepare(struct clk_hw *hw)
                val &= ~BM_PLL_POWER;
        writel_relaxed(val, pll->base);
-        ret = clk_pllv3_wait_lock(pll);
+        return clk_pllv3_wait_lock(pll);
-        if (ret)
-                return ret;
-        return 0;
 }
 static void clk_pllv3_unprepare(struct clk_hw *hw)
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
index 409637254594..5937ddee1a99 100644
--- a/arch/arm/mach-imx/clk-vf610.c
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -120,6 +120,17 @@ static unsigned int const clks_init_on[] __initconst = {
        VF610_CLK_DDR_SEL,
 };
+static struct clk * __init vf610_get_fixed_clock(
+                                struct device_node *ccm_node, const char *name)
+{
+        struct clk *clk = of_clk_get_by_name(ccm_node, name);
+        /* Backward compatibility if device tree is missing clks assignments */
+        if (IS_ERR(clk))
+                clk = imx_obtain_fixed_clock(name, 0);
+        return clk;
+};
 static void __init vf610_clocks_init(struct device_node *ccm_node)
 {
        struct device_node *np;
@@ -130,13 +141,13 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
        clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000);
        clk[VF610_CLK_FIRC] = imx_clk_fixed("firc", 24000000);
-        clk[VF610_CLK_SXOSC] = imx_obtain_fixed_clock("sxosc", 0);
+        clk[VF610_CLK_SXOSC] = vf610_get_fixed_clock(ccm_node, "sxosc");
-        clk[VF610_CLK_FXOSC] = imx_obtain_fixed_clock("fxosc", 0);
+        clk[VF610_CLK_FXOSC] = vf610_get_fixed_clock(ccm_node, "fxosc");
-        clk[VF610_CLK_AUDIO_EXT] = imx_obtain_fixed_clock("audio_ext", 0);
+        clk[VF610_CLK_AUDIO_EXT] = vf610_get_fixed_clock(ccm_node, "audio_ext");
-        clk[VF610_CLK_ENET_EXT] = imx_obtain_fixed_clock("enet_ext", 0);
+        clk[VF610_CLK_ENET_EXT] = vf610_get_fixed_clock(ccm_node, "enet_ext");
        /* Clock source from external clock via LVDs PAD */
-        clk[VF610_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
+        clk[VF610_CLK_ANACLK1] = vf610_get_fixed_clock(ccm_node, "anaclk1");
        clk[VF610_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2);
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 4cdf8b6a74e8..5ef82e2f8fc5 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -131,4 +131,8 @@ static inline struct clk *imx_clk_fixed_factor(const char *name,
                        CLK_SET_RATE_PARENT, mult, div);
 }
+struct clk *imx_clk_cpu(const char *name, const char *parent_name,
+                struct clk *div, struct clk *mux, struct clk *pll,
+                struct clk *step);
 #endif
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 1dabf435c592..cfcdb623d78f 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -61,7 +61,6 @@ struct platform_device *mxc_register_gpio(char *name, int id,
 void mxc_set_cpu_type(unsigned int type);
 void mxc_restart(enum reboot_mode, const char *);
 void mxc_arch_reset_init(void __iomem *);
-void mxc_arch_reset_init_dt(void);
 int mx51_revision(void);
 int mx53_revision(void);
 void imx_set_aips(void __iomem *);
@@ -108,14 +107,15 @@ void imx_gpc_pre_suspend(bool arm_power_off);
 void imx_gpc_post_resume(void);
 void imx_gpc_mask_all(void);
 void imx_gpc_restore_all(void);
-void imx_gpc_irq_mask(struct irq_data *d);
+void imx_gpc_hwirq_mask(unsigned int hwirq);
-void imx_gpc_irq_unmask(struct irq_data *d);
+void imx_gpc_hwirq_unmask(unsigned int hwirq);
 void imx_anatop_init(void);
 void imx_anatop_pre_suspend(void);
 void imx_anatop_post_resume(void);
 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
 void imx6q_set_int_mem_clk_lpm(bool enable);
 void imx6sl_set_wait_clk(bool enter);
+int imx_mmdc_get_ddr_type(void);
 void imx_cpu_die(unsigned int cpu);
 int imx_cpu_kill(unsigned int cpu);
@@ -157,5 +157,6 @@ static inline void imx_init_l2cache(void) {}
 #endif
 extern struct smp_operations imx_smp_ops;
+extern struct smp_operations ls1021a_smp_ops;
 #endif
diff --git a/arch/arm/mach-imx/cpuidle-imx5.c b/arch/arm/mach-imx/cpuidle-imx5.c
index 5a47e3c6172f..3feca526d16b 100644
--- a/arch/arm/mach-imx/cpuidle-imx5.c
+++ b/arch/arm/mach-imx/cpuidle-imx5.c
@@ -24,7 +24,6 @@ static struct cpuidle_driver imx5_cpuidle_driver = {
                .enter            = imx5_cpuidle_enter,
                .exit_latency     = 2,
                .target_residency = 1,
-                .flags            = CPUIDLE_FLAG_TIME_VALID,
                .name             = "IMX5 SRPG",
                .desc             = "CPU state retained,powered off",
        },
diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c
index aa935787b743..d76d08623f9f 100644
--- a/arch/arm/mach-imx/cpuidle-imx6q.c
+++ b/arch/arm/mach-imx/cpuidle-imx6q.c
@@ -53,8 +53,7 @@ static struct cpuidle_driver imx6q_cpuidle_driver = {
                {
                        .exit_latency = 50,
                        .target_residency = 75,
-                        .flags = CPUIDLE_FLAG_TIME_VALID |
+                        .flags = CPUIDLE_FLAG_TIMER_STOP,
-                                 CPUIDLE_FLAG_TIMER_STOP,
                        .enter = imx6q_enter_wait,
                        .name = "WAIT",
                        .desc = "Clock off",
diff --git a/arch/arm/mach-imx/cpuidle-imx6sl.c b/arch/arm/mach-imx/cpuidle-imx6sl.c
index d4b6b8171fa9..7d92e6584551 100644
--- a/arch/arm/mach-imx/cpuidle-imx6sl.c
+++ b/arch/arm/mach-imx/cpuidle-imx6sl.c
@@ -40,8 +40,7 @@ static struct cpuidle_driver imx6sl_cpuidle_driver = {
                {
                        .exit_latency = 50,
                        .target_residency = 75,
-                        .flags = CPUIDLE_FLAG_TIME_VALID |
+                        .flags = CPUIDLE_FLAG_TIMER_STOP,
-                                CPUIDLE_FLAG_TIMER_STOP,
                        .enter = imx6sl_enter_wait,
                        .name = "WAIT",
                        .desc = "Clock off",
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 82ea74e68482..5f3602ec74fa 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -56,14 +56,14 @@ void imx_gpc_post_resume(void)
 static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
 {
-        unsigned int idx = d->irq / 32 - 1;
+        unsigned int idx = d->hwirq / 32 - 1;
        u32 mask;
        /* Sanity check for SPI irq */
-        if (d->irq < 32)
+        if (d->hwirq < 32)
                return -EINVAL;
-        mask = 1 << d->irq % 32;
+        mask = 1 << d->hwirq % 32;
        gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
                                  gpc_wake_irqs[idx] & ~mask;
@@ -91,34 +91,44 @@ void imx_gpc_restore_all(void)
                writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
 }
-void imx_gpc_irq_unmask(struct irq_data *d)
+void imx_gpc_hwirq_unmask(unsigned int hwirq)
 {
        void __iomem *reg;
        u32 val;
-        /* Sanity check for SPI irq */
+        reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
-        if (d->irq < 32)
-                return;
-        reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
        val = readl_relaxed(reg);
-        val &= ~(1 << d->irq % 32);
+        val &= ~(1 << hwirq % 32);
        writel_relaxed(val, reg);
 }
-void imx_gpc_irq_mask(struct irq_data *d)
+void imx_gpc_hwirq_mask(unsigned int hwirq)
 {
        void __iomem *reg;
        u32 val;
+        reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
+        val = readl_relaxed(reg);
+        val |= 1 << (hwirq % 32);
+        writel_relaxed(val, reg);
+}
+static void imx_gpc_irq_unmask(struct irq_data *d)
+{
+        /* Sanity check for SPI irq */
+        if (d->hwirq < 32)
+                return;
+        imx_gpc_hwirq_unmask(d->hwirq);
+}
+static void imx_gpc_irq_mask(struct irq_data *d)
+{
        /* Sanity check for SPI irq */
-        if (d->irq < 32)
+        if (d->hwirq < 32)
                return;
-        reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
+        imx_gpc_hwirq_mask(d->hwirq);
-        val = readl_relaxed(reg);
-        val |= 1 << (d->irq % 32);
-        writel_relaxed(val, reg);
 }
 void __init imx_gpc_init(void)
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c
index cf8032bae277..25defbdb06c4 100644
--- a/arch/arm/mach-imx/imx25-dt.c
+++ b/arch/arm/mach-imx/imx25-dt.c
@@ -17,13 +17,6 @@
 #include "common.h"
 #include "mx25.h"
-static void __init imx25_dt_init(void)
-{
-        mxc_arch_reset_init_dt();
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
 static const char * const imx25_dt_board_compat[] __initconst = {
        "fsl,imx25",
        NULL
@@ -33,7 +26,5 @@ DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
        .map_io         = mx25_map_io,
        .init_early     = imx25_init_early,
        .init_irq       = mx25_init_irq,
-        .init_machine   = imx25_dt_init,
        .dt_compat      = imx25_dt_board_compat,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index dc8f1a6f45f2..bd42d1bd10af 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -22,8 +22,6 @@ static void __init imx27_dt_init(void)
 {
        struct platform_device_info devinfo = { .name = "cpufreq-dt", };
-        mxc_arch_reset_init_dt();
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
        platform_device_register_full(&devinfo);
@@ -40,5 +38,4 @@ DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)")
        .init_irq       = mx27_init_irq,
        .init_machine   = imx27_dt_init,
        .dt_compat      = imx27_dt_board_compat,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index 418dbc82adc4..32100222a017 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -18,13 +18,6 @@
 #include "common.h"
 #include "mx31.h"
-static void __init imx31_dt_init(void)
-{
-        mxc_arch_reset_init_dt();
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
 static const char * const imx31_dt_board_compat[] __initconst = {
        "fsl,imx31",
        NULL
@@ -40,7 +33,5 @@ DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)")
        .init_early     = imx31_init_early,
        .init_irq       = mx31_init_irq,
        .init_time      = imx31_dt_timer_init,
-        .init_machine   = imx31_dt_init,
        .dt_compat      = imx31_dt_board_compat,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/imx35-dt.c b/arch/arm/mach-imx/imx35-dt.c
index 584fbe105579..e9396037235d 100644
--- a/arch/arm/mach-imx/imx35-dt.c
+++ b/arch/arm/mach-imx/imx35-dt.c
@@ -20,14 +20,6 @@
 #include "common.h"
 #include "mx35.h"
-static void __init imx35_dt_init(void)
-{
-        mxc_arch_reset_init_dt();
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             NULL, NULL);
-}
 static void __init imx35_irq_init(void)
 {
        imx_init_l2cache();
@@ -43,7 +35,5 @@ DT_MACHINE_START(IMX35_DT, "Freescale i.MX35 (Device Tree Support)")
        .map_io         = mx35_map_io,
        .init_early     = imx35_init_early,
        .init_irq       = imx35_irq_init,
-        .init_machine   = imx35_dt_init,
        .dt_compat      = imx35_dt_board_compat,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/iomux-imx31.c b/arch/arm/mach-imx/iomux-imx31.c
index 1657fe64cd0f..d6a30753ca7c 100644
--- a/arch/arm/mach-imx/iomux-imx31.c
+++ b/arch/arm/mach-imx/iomux-imx31.c
@@ -44,9 +44,11 @@ static unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
 /*
 * set the mode for a IOMUX pin.
 */
-int mxc_iomux_mode(unsigned int pin_mode)
+void mxc_iomux_mode(unsigned int pin_mode)
 {
-        u32 field, l, mode, ret = 0;
+        u32 field;
+        u32 l;
+        u32 mode;
        void __iomem *reg;
        reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
@@ -61,8 +63,6 @@ int mxc_iomux_mode(unsigned int pin_mode)
        __raw_writel(l, reg);
        spin_unlock(&gpio_mux_lock);
-        return ret;
 }
 /*
diff --git a/arch/arm/mach-imx/iomux-mx3.h b/arch/arm/mach-imx/iomux-mx3.h
index f79f78a1c0ed..0a5adba61e0b 100644
--- a/arch/arm/mach-imx/iomux-mx3.h
+++ b/arch/arm/mach-imx/iomux-mx3.h
@@ -144,7 +144,7 @@ void mxc_iomux_set_gpr(enum iomux_gp_func, bool en);
 * It is called by the setup functions and should not be called directly anymore.
 * It is here visible for backward compatibility
 */
-int mxc_iomux_mode(unsigned int pin_mode);
+void mxc_iomux_mode(unsigned int pin_mode);
 #define IOMUX_PADNUM_MASK       0x1ff
 #define IOMUX_GPIONUM_SHIFT     9
diff --git a/arch/arm/mach-imx/mach-imx50.c b/arch/arm/mach-imx/mach-imx50.c
index b1e56a94a382..ecf58b9e974b 100644
--- a/arch/arm/mach-imx/mach-imx50.c
+++ b/arch/arm/mach-imx/mach-imx50.c
@@ -16,13 +16,6 @@
 #include "common.h"
-static void __init imx50_dt_init(void)
-{
-        mxc_arch_reset_init_dt();
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
 static const char * const imx50_dt_board_compat[] __initconst = {
        "fsl,imx50",
        NULL
@@ -30,7 +23,5 @@ static const char * const imx50_dt_board_compat[] __initconst = {
 DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)")
        .init_irq       = tzic_init_irq,
-        .init_machine   = imx50_dt_init,
        .dt_compat      = imx50_dt_board_compat,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx51.c b/arch/arm/mach-imx/mach-imx51.c
index 2c5fcaf8675b..b015129e4045 100644
--- a/arch/arm/mach-imx/mach-imx51.c
+++ b/arch/arm/mach-imx/mach-imx51.c
@@ -53,7 +53,6 @@ static void __init imx51_dt_init(void)
 {
        struct platform_device_info devinfo = { .name = "cpufreq-dt", };
-        mxc_arch_reset_init_dt();
        imx51_ipu_mipi_setup();
        imx_src_init();
@@ -78,5 +77,4 @@ DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
        .init_machine   = imx51_dt_init,
        .init_late      = imx51_init_late,
        .dt_compat      = imx51_dt_board_compat,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index 03dd6ea13acc..86316a979297 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -30,7 +30,6 @@ static void __init imx53_init_early(void)
 static void __init imx53_dt_init(void)
 {
-        mxc_arch_reset_init_dt();
        imx_src_init();
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
@@ -41,6 +40,8 @@ static void __init imx53_dt_init(void)
 static void __init imx53_init_late(void)
 {
        imx53_pm_init();
+        platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
 }
 static const char * const imx53_dt_board_compat[] __initconst = {
@@ -54,5 +55,4 @@ DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
        .init_machine   = imx53_dt_init,
        .init_late      = imx53_init_late,
        .dt_compat      = imx53_dt_board_compat,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index d51c6e99a2e9..5057d61298b7 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -268,8 +268,6 @@ static void __init imx6q_init_machine(void)
        imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
                              imx_get_soc_revision());
-        mxc_arch_reset_init_dt();
        parent = imx_soc_device_init();
        if (parent == NULL)
                pr_warn("failed to initialize soc device\n");
@@ -409,5 +407,4 @@ DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
        .init_machine   = imx6q_init_machine,
        .init_late      = imx6q_init_late,
        .dt_compat      = imx6q_dt_compat,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index ed263a21d928..24bfaaf944c8 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -48,8 +48,6 @@ static void __init imx6sl_init_machine(void)
 {
        struct device *parent;
-        mxc_arch_reset_init_dt();
        parent = imx_soc_device_init();
        if (parent == NULL)
                pr_warn("failed to initialize soc device\n");
@@ -76,10 +74,8 @@ static const char * const imx6sl_dt_compat[] __initconst = {
 };
 DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)")
-        .map_io         = debug_ll_io_init,
        .init_irq       = imx6sl_init_irq,
        .init_machine   = imx6sl_init_machine,
        .init_late      = imx6sl_init_late,
        .dt_compat      = imx6sl_dt_compat,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c
index 3de3b7369aef..7a96c6577234 100644
--- a/arch/arm/mach-imx/mach-imx6sx.c
+++ b/arch/arm/mach-imx/mach-imx6sx.c
@@ -8,24 +8,73 @@
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
+#include <linux/phy.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include "common.h"
 #include "cpuidle.h"
+static int ar8031_phy_fixup(struct phy_device *dev)
+{
+        u16 val;
+        /* Set RGMII IO voltage to 1.8V */
+        phy_write(dev, 0x1d, 0x1f);
+        phy_write(dev, 0x1e, 0x8);
+        /* introduce tx clock delay */
+        phy_write(dev, 0x1d, 0x5);
+        val = phy_read(dev, 0x1e);
+        val |= 0x0100;
+        phy_write(dev, 0x1e, val);
+        return 0;
+}
+#define PHY_ID_AR8031   0x004dd074
+static void __init imx6sx_enet_phy_init(void)
+{
+        if (IS_BUILTIN(CONFIG_PHYLIB))
+                phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
+                                           ar8031_phy_fixup);
+}
+static void __init imx6sx_enet_clk_sel(void)
+{
+        struct regmap *gpr;
+        gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sx-iomuxc-gpr");
+        if (!IS_ERR(gpr)) {
+                regmap_update_bits(gpr, IOMUXC_GPR1,
+                                   IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK, 0);
+                regmap_update_bits(gpr, IOMUXC_GPR1,
+                                   IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK, 0);
+        } else {
+                pr_err("failed to find fsl,imx6sx-iomux-gpr regmap\n");
+        }
+}
+static inline void imx6sx_enet_init(void)
+{
+        imx6sx_enet_phy_init();
+        imx6sx_enet_clk_sel();
+}
 static void __init imx6sx_init_machine(void)
 {
        struct device *parent;
-        mxc_arch_reset_init_dt();
        parent = imx_soc_device_init();
        if (parent == NULL)
                pr_warn("failed to initialize soc device\n");
        of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
+        imx6sx_enet_init();
        imx_anatop_init();
        imx6sx_pm_init();
 }
@@ -53,10 +102,8 @@ static const char * const imx6sx_dt_compat[] __initconst = {
 };
 DT_MACHINE_START(IMX6SX, "Freescale i.MX6 SoloX (Device Tree)")
-        .map_io         = debug_ll_io_init,
        .init_irq       = imx6sx_init_irq,
        .init_machine   = imx6sx_init_machine,
        .dt_compat      = imx6sx_dt_compat,
        .init_late      = imx6sx_init_late,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-ls1021a.c b/arch/arm/mach-imx/mach-ls1021a.c
new file mode 100644
index 000000000000..b89c858ebfd6
--- /dev/null
+++ b/arch/arm/mach-imx/mach-ls1021a.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <asm/mach/arch.h>
+#include "common.h"
+static const char * const ls1021a_dt_compat[] __initconst = {
+        "fsl,ls1021a",
+        NULL,
+};
+DT_MACHINE_START(LS1021A, "Freescale LS1021A")
+        .smp            = smp_ops(ls1021a_smp_ops),
+        .dt_compat      = ls1021a_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c
index ee7e57b752a7..c11ab6a1dc87 100644
--- a/arch/arm/mach-imx/mach-vf610.c
+++ b/arch/arm/mach-imx/mach-vf610.c
@@ -12,14 +12,6 @@
 #include <asm/mach/arch.h>
 #include <asm/hardware/cache-l2x0.h>
-#include "common.h"
-static void __init vf610_init_machine(void)
-{
-        mxc_arch_reset_init_dt();
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
 static const char * const vf610_dt_compat[] __initconst = {
        "fsl,vf610",
        NULL,
@@ -28,7 +20,5 @@ static const char * const vf610_dt_compat[] __initconst = {
 DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF610 (Device Tree)")
        .l2c_aux_val    = 0,
        .l2c_aux_mask   = ~0,
-        .init_machine   = vf610_init_machine,
        .dt_compat      = vf610_dt_compat,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c
index 7a9686ad994c..3729d90cfa46 100644
--- a/arch/arm/mach-imx/mmdc.c
+++ b/arch/arm/mach-imx/mmdc.c
@@ -21,6 +21,12 @@
 #define BP_MMDC_MAPSR_PSD       0
 #define BP_MMDC_MAPSR_PSS       4
+#define MMDC_MDMISC             0x18
+#define BM_MMDC_MDMISC_DDR_TYPE 0x18
+#define BP_MMDC_MDMISC_DDR_TYPE 0x3
+static int ddr_type;
 static int imx_mmdc_probe(struct platform_device *pdev)
 {
        struct device_node *np = pdev->dev.of_node;
@@ -31,6 +37,12 @@ static int imx_mmdc_probe(struct platform_device *pdev)
        mmdc_base = of_iomap(np, 0);
        WARN_ON(!mmdc_base);
+        reg = mmdc_base + MMDC_MDMISC;
+        /* Get ddr type */
+        val = readl_relaxed(reg);
+        ddr_type = (val & BM_MMDC_MDMISC_DDR_TYPE) >>
+                 BP_MMDC_MDMISC_DDR_TYPE;
        reg = mmdc_base + MMDC_MAPSR;
        /* Enable automatic power saving */
@@ -51,6 +63,11 @@ static int imx_mmdc_probe(struct platform_device *pdev)
        return 0;
 }
+int imx_mmdc_get_ddr_type(void)
+{
+        return ddr_type;
+}
 static struct of_device_id imx_mmdc_dt_ids[] = {
        { .compatible = "fsl,imx6q-mmdc", },
        { /* sentinel */ }
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index 17a41ca65acf..4c1343df2ba4 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -55,6 +55,8 @@
 #define IMX_CHIP_REVISION_3_3           0x33
 #define IMX_CHIP_REVISION_UNKNOWN       0xff
+#define IMX_DDR_TYPE_LPDDR2             1
 #ifndef __ASSEMBLY__
 extern unsigned int __mxc_cpu_type;
 #endif
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 771bd25c1025..7f270015fe58 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -11,7 +11,10 @@
 */
 #include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/of.h>
 #include <linux/smp.h>
 #include <asm/cacheflush.h>
 #include <asm/page.h>
 #include <asm/smp_scu.h>
@@ -94,3 +97,33 @@ struct smp_operations  imx_smp_ops __initdata = {
        .cpu_kill               = imx_cpu_kill,
 #endif
 };
+#define DCFG_CCSR_SCRATCHRW1    0x200
+static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+        return 0;
+}
+static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)
+{
+        struct device_node *np;
+        void __iomem *dcfg_base;
+        unsigned long paddr;
+        np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
+        dcfg_base = of_iomap(np, 0);
+        BUG_ON(!dcfg_base);
+        paddr = virt_to_phys(secondary_startup);
+        writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
+        iounmap(dcfg_base);
+}
+struct smp_operations  ls1021a_smp_ops __initdata = {
+        .smp_prepare_cpus       = ls1021a_smp_prepare_cpus,
+        .smp_boot_secondary     = ls1021a_boot_secondary,
+};
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index 5c3af8f993d0..5d2c1bd5f5ef 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -88,7 +88,7 @@ struct imx6_pm_base {
 };
 struct imx6_pm_socdata {
-        u32 cpu_type;
+        u32 ddr_type;
        const char *mmdc_compat;
        const char *src_compat;
        const char *iomuxc_compat;
@@ -138,7 +138,6 @@ static const u32 imx6sx_mmdc_io_offset[] __initconst = {
 };
 static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
-        .cpu_type = MXC_CPU_IMX6Q,
        .mmdc_compat = "fsl,imx6q-mmdc",
        .src_compat = "fsl,imx6q-src",
        .iomuxc_compat = "fsl,imx6q-iomuxc",
@@ -148,7 +147,6 @@ static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
 };
 static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
-        .cpu_type = MXC_CPU_IMX6DL,
        .mmdc_compat = "fsl,imx6q-mmdc",
        .src_compat = "fsl,imx6q-src",
        .iomuxc_compat = "fsl,imx6dl-iomuxc",
@@ -158,7 +156,6 @@ static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
 };
 static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
-        .cpu_type = MXC_CPU_IMX6SL,
        .mmdc_compat = "fsl,imx6sl-mmdc",
        .src_compat = "fsl,imx6sl-src",
        .iomuxc_compat = "fsl,imx6sl-iomuxc",
@@ -168,7 +165,6 @@ static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
 };
 static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
-        .cpu_type = MXC_CPU_IMX6SX,
        .mmdc_compat = "fsl,imx6sx-mmdc",
        .src_compat = "fsl,imx6sx-src",
        .iomuxc_compat = "fsl,imx6sx-iomuxc",
@@ -187,7 +183,7 @@ static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
 struct imx6_cpu_pm_info {
        phys_addr_t pbase; /* The physical address of pm_info. */
        phys_addr_t resume_addr; /* The physical resume address for asm code */
-        u32 cpu_type;
+        u32 ddr_type;
        u32 pm_info_size; /* Size of pm_info. */
        struct imx6_pm_base mmdc_base;
        struct imx6_pm_base src_base;
@@ -261,7 +257,6 @@ static void imx6q_enable_wb(bool enable)
 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
 {
-        struct irq_data *iomuxc_irq_data = irq_get_irq_data(32);
        u32 val = readl_relaxed(ccm_base + CLPCR);
        val &= ~BM_CLPCR_LPM;
@@ -316,9 +311,9 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
         * 3) Software should mask IRQ #32 right after CCM Low-Power mode
         *    is set (set bits 0-1 of CCM_CLPCR).
         */
-        imx_gpc_irq_unmask(iomuxc_irq_data);
+        imx_gpc_hwirq_unmask(32);
        writel_relaxed(val, ccm_base + CLPCR);
-        imx_gpc_irq_mask(iomuxc_irq_data);
+        imx_gpc_hwirq_mask(32);
        return 0;
 }
@@ -522,7 +517,7 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
                goto pl310_cache_map_failed;
        }
-        pm_info->cpu_type = socdata->cpu_type;
+        pm_info->ddr_type = imx_mmdc_get_ddr_type();
        pm_info->mmdc_io_num = socdata->mmdc_io_num;
        mmdc_offset_array = socdata->mmdc_io_offset;
diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S
index ca4ea2daf25b..b99987b023fa 100644
--- a/arch/arm/mach-imx/suspend-imx6.S
+++ b/arch/arm/mach-imx/suspend-imx6.S
@@ -45,7 +45,7 @@
 */
 #define PM_INFO_PBASE_OFFSET                    0x0
 #define PM_INFO_RESUME_ADDR_OFFSET              0x4
-#define PM_INFO_CPU_TYPE_OFFSET                 0x8
+#define PM_INFO_DDR_TYPE_OFFSET                 0x8
 #define PM_INFO_PM_INFO_SIZE_OFFSET             0xC
 #define PM_INFO_MX6Q_MMDC_P_OFFSET              0x10
 #define PM_INFO_MX6Q_MMDC_V_OFFSET              0x14
@@ -110,7 +110,7 @@
        ldreq   r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
        ldrne   r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
-        cmp     r3, #MXC_CPU_IMX6SL
+        cmp     r3, #IMX_DDR_TYPE_LPDDR2
        bne     4f
        /* reset read FIFO, RST_RD_FIFO */
@@ -151,7 +151,7 @@
 ENTRY(imx6_suspend)
        ldr     r1, [r0, #PM_INFO_PBASE_OFFSET]
        ldr     r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
-        ldr     r3, [r0, #PM_INFO_CPU_TYPE_OFFSET]
+        ldr     r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]
        ldr     r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET]
        /*
@@ -209,8 +209,8 @@ poll_dvfs_set:
        ldr     r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
        ldr     r8, =PM_INFO_MMDC_IO_VAL_OFFSET
        add     r8, r8, r0
-        /* i.MX6SL's last 3 IOs need special setting */
+        /* LPDDR2's last 3 IOs need special setting */
-        cmp     r3, #MXC_CPU_IMX6SL
+        cmp     r3, #IMX_DDR_TYPE_LPDDR2
        subeq   r7, r7, #0x3
 set_mmdc_io_lpm:
        ldr     r9, [r8], #0x8
@@ -218,7 +218,7 @@ set_mmdc_io_lpm:
        subs    r7, r7, #0x1
        bne     set_mmdc_io_lpm
-        cmp     r3, #MXC_CPU_IMX6SL
+        cmp     r3, #IMX_DDR_TYPE_LPDDR2
        bne     set_mmdc_io_lpm_done
        ldr     r6, =0x1000
        ldr     r9, [r8], #0x8
@@ -324,7 +324,7 @@ resume:
        str     r7, [r11, #MX6Q_SRC_GPR1]
        str     r7, [r11, #MX6Q_SRC_GPR2]
-        ldr     r3, [r0, #PM_INFO_CPU_TYPE_OFFSET]
+        ldr     r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]
        mov     r5, #0x1
        resume_mmdc
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index d14c33fd6b03..51c35013b673 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -89,21 +89,6 @@ void __init mxc_arch_reset_init(void __iomem *base)
                clk_prepare(wdog_clk);
 }
-void __init mxc_arch_reset_init_dt(void)
-{
-        struct device_node *np;
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx21-wdt");
-        wdog_base = of_iomap(np, 0);
-        WARN_ON(!wdog_base);
-        wdog_clk = of_clk_get(np, 0);
-        if (IS_ERR(wdog_clk))
-                pr_warn("%s: failed to get wdog clock\n", __func__);
-        else
-                clk_prepare(wdog_clk);
-}
 #ifdef CONFIG_CACHE_L2X0
 void __init imx_init_l2cache(void)
 {
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig
index c455e974bbfe..02d083489a26 100644
--- a/arch/arm/mach-integrator/Kconfig
+++ b/arch/arm/mach-integrator/Kconfig
@@ -1,3 +1,26 @@
+config ARCH_INTEGRATOR
+        bool "ARM Ltd. Integrator family" if (ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V6)
+        select ARM_AMBA
+        select ARM_PATCH_PHYS_VIRT if MMU
+        select AUTO_ZRELADDR
+        select COMMON_CLK
+        select COMMON_CLK_VERSATILE
+        select GENERIC_CLOCKEVENTS
+        select HAVE_TCM
+        select ICST
+        select MFD_SYSCON
+        select MULTI_IRQ_HANDLER
+        select PLAT_VERSATILE
+        select POWER_RESET
+        select POWER_RESET_VERSATILE
+        select POWER_SUPPLY
+        select SOC_INTEGRATOR_CM
+        select SPARSE_IRQ
+        select USE_OF
+        select VERSATILE_FPGA_IRQ
+        help
+          Support for ARM's Integrator platform.
 if ARCH_INTEGRATOR
 menu "Integrator Options"
diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile
index ec759ded7b60..1ebe45356b09 100644
--- a/arch/arm/mach-integrator/Makefile
+++ b/arch/arm/mach-integrator/Makefile
@@ -4,7 +4,7 @@
 # Object file lists.
-obj-y                                   := core.o lm.o leds.o
+obj-y                                   := core.o lm.o
 obj-$(CONFIG_ARCH_INTEGRATOR_AP)        += integrator_ap.o
 obj-$(CONFIG_ARCH_INTEGRATOR_CP)        += integrator_cp.o
diff --git a/arch/arm/mach-integrator/cm.h b/arch/arm/mach-integrator/cm.h
index 4ecff7bff482..5b8ba8247f45 100644
--- a/arch/arm/mach-integrator/cm.h
+++ b/arch/arm/mach-integrator/cm.h
@@ -11,7 +11,6 @@ void cm_clear_irqs(void);
 #define CM_CTRL_LED                     (1 << 0)
 #define CM_CTRL_nMBDET                  (1 << 1)
 #define CM_CTRL_REMAP                   (1 << 2)
-#define CM_CTRL_RESET                   (1 << 3)
 /*
 * Integrator/AP,PP2 specific
diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
index ad0ac5547b2c..96c9dc56cabf 100644
--- a/arch/arm/mach-integrator/common.h
+++ b/arch/arm/mach-integrator/common.h
@@ -4,5 +4,3 @@ extern struct amba_pl010_data ap_uart_data;
 void integrator_init_early(void);
 int integrator_init(bool is_cp);
 void integrator_reserve(void);
-void integrator_restart(enum reboot_mode, const char *);
-void integrator_init_sysfs(struct device *parent, u32 id);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index e3f3aca43efb..948872a419c1 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -60,40 +60,6 @@ void cm_control(u32 mask, u32 set)
        raw_spin_unlock_irqrestore(&cm_lock, flags);
 }
-static const char *integrator_arch_str(u32 id)
-{
-        switch ((id >> 16) & 0xff) {
-        case 0x00:
-                return "ASB little-endian";
-        case 0x01:
-                return "AHB little-endian";
-        case 0x03:
-                return "AHB-Lite system bus, bi-endian";
-        case 0x04:
-                return "AHB";
-        case 0x08:
-                return "AHB system bus, ASB processor bus";
-        default:
-                return "Unknown";
-        }
-}
-static const char *integrator_fpga_str(u32 id)
-{
-        switch ((id >> 12) & 0xf) {
-        case 0x01:
-                return "XC4062";
-        case 0x02:
-                return "XC4085";
-        case 0x03:
-                return "XVC600";
-        case 0x04:
-                return "EPM7256AE (Altera PLD)";
-        default:
-                return "Unknown";
-        }
-}
 void cm_clear_irqs(void)
 {
        /* disable core module IRQs */
@@ -109,7 +75,6 @@ static const struct of_device_id cm_match[] = {
 void cm_init(void)
 {
        struct device_node *cm = of_find_matching_node(NULL, cm_match);
-        u32 val;
        if (!cm) {
                pr_crit("no core module node found in device tree\n");
@@ -121,13 +86,6 @@ void cm_init(void)
                return;
        }
        cm_clear_irqs();
-        val = readl(cm_base + INTEGRATOR_HDR_ID_OFFSET);
-        pr_info("Detected ARM core module:\n");
-        pr_info("    Manufacturer: %02x\n", (val >> 24));
-        pr_info("    Architecture: %s\n", integrator_arch_str(val));
-        pr_info("    FPGA: %s\n", integrator_fpga_str(val));
-        pr_info("    Build: %02x\n", (val >> 4) & 0xFF);
-        pr_info("    Rev: %c\n", ('A' + (val & 0x03)));
 }
 /*
@@ -139,64 +97,3 @@ void __init integrator_reserve(void)
 {
        memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
 }
-/*
- * To reset, we hit the on-board reset register in the system FPGA
- */
-void integrator_restart(enum reboot_mode mode, const char *cmd)
-{
-        cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
-}
-static u32 integrator_id;
-static ssize_t intcp_get_manf(struct device *dev,
-                              struct device_attribute *attr,
-                              char *buf)
-{
-        return sprintf(buf, "%02x\n", integrator_id >> 24);
-}
-static struct device_attribute intcp_manf_attr =
-        __ATTR(manufacturer,  S_IRUGO, intcp_get_manf,  NULL);
-static ssize_t intcp_get_arch(struct device *dev,
-                              struct device_attribute *attr,
-                              char *buf)
-{
-        return sprintf(buf, "%s\n", integrator_arch_str(integrator_id));
-}
-static struct device_attribute intcp_arch_attr =
-        __ATTR(architecture,  S_IRUGO, intcp_get_arch,  NULL);
-static ssize_t intcp_get_fpga(struct device *dev,
-                              struct device_attribute *attr,
-                              char *buf)
-{
-        return sprintf(buf, "%s\n", integrator_fpga_str(integrator_id));
-}
-static struct device_attribute intcp_fpga_attr =
-        __ATTR(fpga,  S_IRUGO, intcp_get_fpga,  NULL);
-static ssize_t intcp_get_build(struct device *dev,
-                               struct device_attribute *attr,
-                               char *buf)
-{
-        return sprintf(buf, "%02x\n", (integrator_id >> 4) & 0xFF);
-}
-static struct device_attribute intcp_build_attr =
-        __ATTR(build,  S_IRUGO, intcp_get_build,  NULL);
-void integrator_init_sysfs(struct device *parent, u32 id)
-{
-        integrator_id = id;
-        device_create_file(parent, &intcp_manf_attr);
-        device_create_file(parent, &intcp_arch_attr);
-        device_create_file(parent, &intcp_fpga_attr);
-        device_create_file(parent, &intcp_build_attr);
-}
diff --git a/arch/arm/mach-integrator/include/mach/uncompress.h b/arch/arm/mach-integrator/include/mach/uncompress.h
deleted file mode 100644
index 8f3cc9954c16..000000000000
--- a/arch/arm/mach-integrator/include/mach/uncompress.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- *  arch/arm/mach-integrator/include/mach/uncompress.h
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define AMBA_UART_DR    (*(volatile unsigned char *)0x16000000)
-#define AMBA_UART_LCRH  (*(volatile unsigned char *)0x16000008)
-#define AMBA_UART_LCRM  (*(volatile unsigned char *)0x1600000c)
-#define AMBA_UART_LCRL  (*(volatile unsigned char *)0x16000010)
-#define AMBA_UART_CR    (*(volatile unsigned char *)0x16000014)
-#define AMBA_UART_FR    (*(volatile unsigned char *)0x16000018)
-/*
- * This does not append a newline
- */
-static void putc(int c)
-{
-        while (AMBA_UART_FR & (1 << 5))
-                barrier();
-        AMBA_UART_DR = c;
-}
-static inline void flush(void)
-{
-        while (AMBA_UART_FR & (1 << 3))
-                barrier();
-}
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 8ca290b479b1..30003ba447a5 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -27,22 +27,15 @@
 #include <linux/syscore_ops.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/kmi.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/irqchip.h>
 #include <linux/mtd/physmap.h>
-#include <linux/clk.h>
 #include <linux/platform_data/clk-integrator.h>
 #include <linux/of_irq.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
 #include <linux/stat.h>
-#include <linux/sys_soc.h>
 #include <linux/termios.h>
-#include <linux/sched_clock.h>
-#include <linux/clk-provider.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/setup.h>
@@ -89,11 +82,6 @@ static void __iomem *ebi_base;
 static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
        {
-                .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
-                .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        }, {
                .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
                .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
                .length         = SZ_4K,
@@ -257,188 +245,10 @@ struct amba_pl010_data ap_uart_data = {
        .set_mctrl = integrator_uart_set_mctrl,
 };
-/*
- * Where is the timer (VA)?
- */
-#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
-#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
-#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
-static unsigned long timer_reload;
-static u64 notrace integrator_read_sched_clock(void)
-{
-        return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
-}
-static void integrator_clocksource_init(unsigned long inrate,
-                                        void __iomem *base)
-{
-        u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
-        unsigned long rate = inrate;
-        if (rate >= 1500000) {
-                rate /= 16;
-                ctrl |= TIMER_CTRL_DIV16;
-        }
-        writel(0xffff, base + TIMER_LOAD);
-        writel(ctrl, base + TIMER_CTRL);
-        clocksource_mmio_init(base + TIMER_VALUE, "timer2",
-                        rate, 200, 16, clocksource_mmio_readl_down);
-        sched_clock_register(integrator_read_sched_clock, 16, rate);
-}
-static void __iomem * clkevt_base;
-/*
- * IRQ handler for the timer
- */
-static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
-{
-        struct clock_event_device *evt = dev_id;
-        /* clear the interrupt */
-        writel(1, clkevt_base + TIMER_INTCLR);
-        evt->event_handler(evt);
-        return IRQ_HANDLED;
-}
-static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
-{
-        u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
-        /* Disable timer */
-        writel(ctrl, clkevt_base + TIMER_CTRL);
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                /* Enable the timer and start the periodic tick */
-                writel(timer_reload, clkevt_base + TIMER_LOAD);
-                ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
-                writel(ctrl, clkevt_base + TIMER_CTRL);
-                break;
-        case CLOCK_EVT_MODE_ONESHOT:
-                /* Leave the timer disabled, .set_next_event will enable it */
-                ctrl &= ~TIMER_CTRL_PERIODIC;
-                writel(ctrl, clkevt_base + TIMER_CTRL);
-                break;
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_SHUTDOWN:
-        case CLOCK_EVT_MODE_RESUME:
-        default:
-                /* Just leave in disabled state */
-                break;
-        }
-}
-static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
-{
-        unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
-        writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
-        writel(next, clkevt_base + TIMER_LOAD);
-        writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
-        return 0;
-}
-static struct clock_event_device integrator_clockevent = {
-        .name           = "timer1",
-        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .set_mode       = clkevt_set_mode,
-        .set_next_event = clkevt_set_next_event,
-        .rating         = 300,
-};
-static struct irqaction integrator_timer_irq = {
-        .name           = "timer",
-        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = integrator_timer_interrupt,
-        .dev_id         = &integrator_clockevent,
-};
-static void integrator_clockevent_init(unsigned long inrate,
-                                void __iomem *base, int irq)
-{
-        unsigned long rate = inrate;
-        unsigned int ctrl = 0;
-        clkevt_base = base;
-        /* Calculate and program a divisor */
-        if (rate > 0x100000 * HZ) {
-                rate /= 256;
-                ctrl |= TIMER_CTRL_DIV256;
-        } else if (rate > 0x10000 * HZ) {
-                rate /= 16;
-                ctrl |= TIMER_CTRL_DIV16;
-        }
-        timer_reload = rate / HZ;
-        writel(ctrl, clkevt_base + TIMER_CTRL);
-        setup_irq(irq, &integrator_timer_irq);
-        clockevents_config_and_register(&integrator_clockevent,
-                                        rate,
-                                        1,
-                                        0xffffU);
-}
 void __init ap_init_early(void)
 {
 }
-static void __init ap_of_timer_init(void)
-{
-        struct device_node *node;
-        const char *path;
-        void __iomem *base;
-        int err;
-        int irq;
-        struct clk *clk;
-        unsigned long rate;
-        of_clk_init(NULL);
-        err = of_property_read_string(of_aliases,
-                                "arm,timer-primary", &path);
-        if (WARN_ON(err))
-                return;
-        node = of_find_node_by_path(path);
-        base = of_iomap(node, 0);
-        if (WARN_ON(!base))
-                return;
-        clk = of_clk_get(node, 0);
-        BUG_ON(IS_ERR(clk));
-        clk_prepare_enable(clk);
-        rate = clk_get_rate(clk);
-        writel(0, base + TIMER_CTRL);
-        integrator_clocksource_init(rate, base);
-        err = of_property_read_string(of_aliases,
-                                "arm,timer-secondary", &path);
-        if (WARN_ON(err))
-                return;
-        node = of_find_node_by_path(path);
-        base = of_iomap(node, 0);
-        if (WARN_ON(!base))
-                return;
-        irq = irq_of_parse_and_map(node, 0);
-        clk = of_clk_get(node, 0);
-        BUG_ON(IS_ERR(clk));
-        clk_prepare_enable(clk);
-        rate = clk_get_rate(clk);
-        writel(0, base + TIMER_CTRL);
-        integrator_clockevent_init(rate, base, irq);
-}
 static void __init ap_init_irq_of(void)
 {
        cm_init();
@@ -477,10 +287,6 @@ static void __init ap_init_of(void)
        unsigned long sc_dec;
        struct device_node *syscon;
        struct device_node *ebi;
-        struct device *parent;
-        struct soc_device *soc_dev;
-        struct soc_device_attribute *soc_dev_attr;
-        u32 ap_sc_id;
        int i;
        syscon = of_find_matching_node(NULL, ap_syscon_match);
@@ -500,28 +306,6 @@ static void __init ap_init_of(void)
        of_platform_populate(NULL, of_default_bus_match_table,
                        ap_auxdata_lookup, NULL);
-        ap_sc_id = readl(ap_syscon_base);
-        soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
-        if (!soc_dev_attr)
-                return;
-        soc_dev_attr->soc_id = "XVC";
-        soc_dev_attr->machine = "Integrator/AP";
-        soc_dev_attr->family = "Integrator";
-        soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
-                                           'A' + (ap_sc_id & 0x0f));
-        soc_dev = soc_device_register(soc_dev_attr);
-        if (IS_ERR(soc_dev)) {
-                kfree(soc_dev_attr->revision);
-                kfree(soc_dev_attr);
-                return;
-        }
-        parent = soc_device_to_device(soc_dev);
-        integrator_init_sysfs(parent, ap_sc_id);
        sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
        for (i = 0; i < 4; i++) {
                struct lm_device *lmdev;
@@ -553,8 +337,6 @@ DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
        .map_io         = ap_map_io,
        .init_early     = ap_init_early,
        .init_irq       = ap_init_irq_of,
-        .init_time      = ap_of_timer_init,
        .init_machine   = ap_init_of,
-        .restart        = integrator_restart,
        .dt_compat      = ap_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index cca02eb75eb5..b5fb71a36ee6 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -27,7 +27,6 @@
 #include <linux/of_irq.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
-#include <linux/sys_soc.h>
 #include <linux/sched_clock.h>
 #include <asm/setup.h>
@@ -274,10 +273,6 @@ static const struct of_device_id intcp_syscon_match[] = {
 static void __init intcp_init_of(void)
 {
        struct device_node *cpcon;
-        struct device *parent;
-        struct soc_device *soc_dev;
-        struct soc_device_attribute *soc_dev_attr;
-        u32 intcp_sc_id;
        cpcon = of_find_matching_node(NULL, intcp_syscon_match);
        if (!cpcon)
@@ -289,28 +284,6 @@ static void __init intcp_init_of(void)
        of_platform_populate(NULL, of_default_bus_match_table,
                             intcp_auxdata_lookup, NULL);
-        intcp_sc_id = readl(intcp_con_base);
-        soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
-        if (!soc_dev_attr)
-                return;
-        soc_dev_attr->soc_id = "XCV";
-        soc_dev_attr->machine = "Integrator/CP";
-        soc_dev_attr->family = "Integrator";
-        soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
-                                           'A' + (intcp_sc_id & 0x0f));
-        soc_dev = soc_device_register(soc_dev_attr);
-        if (IS_ERR(soc_dev)) {
-                kfree(soc_dev_attr->revision);
-                kfree(soc_dev_attr);
-                return;
-        }
-        parent = soc_device_to_device(soc_dev);
-        integrator_init_sysfs(parent, intcp_sc_id);
 }
 static const char * intcp_dt_board_compat[] = {
@@ -324,6 +297,5 @@ DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
        .init_early     = intcp_init_early,
        .init_irq       = intcp_init_irq_of,
        .init_machine   = intcp_init_of,
-        .restart        = integrator_restart,
        .dt_compat      = intcp_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-integrator/leds.c b/arch/arm/mach-integrator/leds.c
deleted file mode 100644
index f1dcb57a59e2..000000000000
--- a/arch/arm/mach-integrator/leds.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Driver for the 4 user LEDs found on the Integrator AP/CP baseboard
- * Based on Versatile and RealView machine LED code
- *
- * License terms: GNU General Public License (GPL) version 2
- * Author: Bryan Wu <bryan.wu@canonical.com>
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/leds.h>
-#include "hardware.h"
-#include "cm.h"
-#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
-#define ALPHA_REG __io_address(INTEGRATOR_DBG_BASE)
-#define LEDREG  (__io_address(INTEGRATOR_DBG_BASE) + INTEGRATOR_DBG_LEDS_OFFSET)
-struct integrator_led {
-        struct led_classdev     cdev;
-        u8                      mask;
-};
-/*
- * The triggers lines up below will only be used if the
- * LED triggers are compiled in.
- */
-static const struct {
-        const char *name;
-        const char *trigger;
-} integrator_leds[] = {
-        { "integrator:green0", "heartbeat", },
-        { "integrator:yellow", },
-        { "integrator:red", },
-        { "integrator:green1", },
-        { "integrator:core_module", "cpu0", },
-};
-static void integrator_led_set(struct led_classdev *cdev,
-                              enum led_brightness b)
-{
-        struct integrator_led *led = container_of(cdev,
-                                                 struct integrator_led, cdev);
-        u32 reg = __raw_readl(LEDREG);
-        if (b != LED_OFF)
-                reg |= led->mask;
-        else
-                reg &= ~led->mask;
-        while (__raw_readl(ALPHA_REG) & 1)
-                cpu_relax();
-        __raw_writel(reg, LEDREG);
-}
-static enum led_brightness integrator_led_get(struct led_classdev *cdev)
-{
-        struct integrator_led *led = container_of(cdev,
-                                                 struct integrator_led, cdev);
-        u32 reg = __raw_readl(LEDREG);
-        return (reg & led->mask) ? LED_FULL : LED_OFF;
-}
-static void cm_led_set(struct led_classdev *cdev,
-                              enum led_brightness b)
-{
-        if (b != LED_OFF)
-                cm_control(CM_CTRL_LED, CM_CTRL_LED);
-        else
-                cm_control(CM_CTRL_LED, 0);
-}
-static enum led_brightness cm_led_get(struct led_classdev *cdev)
-{
-        u32 reg = cm_get();
-        return (reg & CM_CTRL_LED) ? LED_FULL : LED_OFF;
-}
-static int __init integrator_leds_init(void)
-{
-        int i;
-        for (i = 0; i < ARRAY_SIZE(integrator_leds); i++) {
-                struct integrator_led *led;
-                led = kzalloc(sizeof(*led), GFP_KERNEL);
-                if (!led)
-                        break;
-                led->cdev.name = integrator_leds[i].name;
-                if (i == 4) { /* Setting for LED in core module */
-                        led->cdev.brightness_set = cm_led_set;
-                        led->cdev.brightness_get = cm_led_get;
-                } else {
-                        led->cdev.brightness_set = integrator_led_set;
-                        led->cdev.brightness_get = integrator_led_get;
-                }
-                led->cdev.default_trigger = integrator_leds[i].trigger;
-                led->mask = BIT(i);
-                if (led_classdev_register(NULL, &led->cdev) < 0) {
-                        kfree(led);
-                        break;
-                }
-        }
-        return 0;
-}
-/*
- * Since we may have triggers on any subsystem, defer registration
- * until after subsystem_init.
- */
-fs_initcall(integrator_leds_init);
-#endif
diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c
index e7730cf9c15d..9f89e76dfbb9 100644
--- a/arch/arm/mach-iop13xx/msi.c
+++ b/arch/arm/mach-iop13xx/msi.c
@@ -126,10 +126,10 @@ static void iop13xx_msi_nop(struct irq_data *d)
 static struct irq_chip iop13xx_msi_chip = {
        .name = "PCI-MSI",
        .irq_ack = iop13xx_msi_nop,
-        .irq_enable = unmask_msi_irq,
+        .irq_enable = pci_msi_unmask_irq,
-        .irq_disable = mask_msi_irq,
+        .irq_disable = pci_msi_mask_irq,
-        .irq_mask = mask_msi_irq,
+        .irq_mask = pci_msi_mask_irq,
-        .irq_unmask = unmask_msi_irq,
+        .irq_unmask = pci_msi_unmask_irq,
 };
 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
@@ -153,7 +153,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
        id = iop13xx_cpu_id();
        msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f);
-        write_msi_msg(irq, &msg);
+        pci_write_msi_msg(irq, &msg);
        irq_set_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq);
        return 0;
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index fc4b7b24265e..8537d4c41e34 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -652,7 +652,7 @@ static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size,
        return (void __iomem *)addr;
 }
-static void ixp4xx_iounmap(void __iomem *addr)
+static void ixp4xx_iounmap(volatile void __iomem *addr)
 {
        if (!is_pci_memory((__force u32)addr))
                __iounmap(addr);
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
index 7d11979da030..6a722860e34d 100644
--- a/arch/arm/mach-ixp4xx/include/mach/io.h
+++ b/arch/arm/mach-ixp4xx/include/mach/io.h
@@ -58,6 +58,10 @@ static inline int is_pci_memory(u32 addr)
 #define writew(v, p)                    __indirect_writew(v, p)
 #define writel(v, p)                    __indirect_writel(v, p)
+#define writeb_relaxed(v, p)            __indirect_writeb(v, p)
+#define writew_relaxed(v, p)            __indirect_writew(v, p)
+#define writel_relaxed(v, p)            __indirect_writel(v, p)
 #define writesb(p, v, l)                __indirect_writesb(p, v, l)
 #define writesw(p, v, l)                __indirect_writesw(p, v, l)
 #define writesl(p, v, l)                __indirect_writesl(p, v, l)
@@ -66,6 +70,10 @@ static inline int is_pci_memory(u32 addr)
 #define readw(p)                        __indirect_readw(p)
 #define readl(p)                        __indirect_readl(p)
+#define readb_relaxed(p)                __indirect_readb(p)
+#define readw_relaxed(p)                __indirect_readw(p)
+#define readl_relaxed(p)                __indirect_readl(p)
 #define readsb(p, v, l)                 __indirect_readsb(p, v, l)
 #define readsw(p, v, l)                 __indirect_readsw(p, v, l)
 #define readsl(p, v, l)                 __indirect_readsl(p, v, l)
@@ -99,7 +107,7 @@ static inline void __indirect_writew(u16 value, volatile void __iomem *p)
        u32 n, byte_enables, data;
        if (!is_pci_memory(addr)) {
-                __raw_writew(value, addr);
+                __raw_writew(value, p);
                return;
        }
@@ -164,7 +172,7 @@ static inline unsigned short __indirect_readw(const volatile void __iomem *p)
        u32 n, byte_enables, data;
        if (!is_pci_memory(addr))
-                return __raw_readw(addr);
+                return __raw_readw(p);
        n = addr % 4;
        byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
@@ -226,6 +234,7 @@ static inline void __indirect_readsl(const volatile void __iomem *bus_addr,
 * I/O functions.
 */
+#define outb outb
 static inline void outb(u8 value, u32 addr)
 {
        u32 n, byte_enables, data;
@@ -235,12 +244,14 @@ static inline void outb(u8 value, u32 addr)
        ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
 }
+#define outsb outsb
 static inline void outsb(u32 io_addr, const u8 *vaddr, u32 count)
 {
        while (count--)
                outb(*vaddr++, io_addr);
 }
+#define outw outw
 static inline void outw(u16 value, u32 addr)
 {
        u32 n, byte_enables, data;
@@ -250,23 +261,27 @@ static inline void outw(u16 value, u32 addr)
        ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
 }
+#define outsw outsw
 static inline void outsw(u32 io_addr, const u16 *vaddr, u32 count)
 {
        while (count--)
                outw(cpu_to_le16(*vaddr++), io_addr);
 }
+#define outl outl
 static inline void outl(u32 value, u32 addr)
 {
        ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value);
 }
+#define outsl outsl
 static inline void outsl(u32 io_addr, const u32 *vaddr, u32 count)
 {
        while (count--)
                outl(cpu_to_le32(*vaddr++), io_addr);
 }
+#define inb inb
 static inline u8 inb(u32 addr)
 {
        u32 n, byte_enables, data;
@@ -278,12 +293,14 @@ static inline u8 inb(u32 addr)
        return data >> (8*n);
 }
+#define insb insb
 static inline void insb(u32 io_addr, u8 *vaddr, u32 count)
 {
        while (count--)
                *vaddr++ = inb(io_addr);
 }
+#define inw inw
 static inline u16 inw(u32 addr)
 {
        u32 n, byte_enables, data;
@@ -295,12 +312,14 @@ static inline u16 inw(u32 addr)
        return data>>(8*n);
 }
+#define insw insw
 static inline void insw(u32 io_addr, u16 *vaddr, u32 count)
 {
        while (count--)
                *vaddr++ = le16_to_cpu(inw(io_addr));
 }
+#define inl inl
 static inline u32 inl(u32 addr)
 {
        u32 data;
@@ -310,6 +329,7 @@ static inline u32 inl(u32 addr)
        return data;
 }
+#define insl insl
 static inline void insl(u32 io_addr, u32 *vaddr, u32 count)
 {
        while (count--)
diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig
index 98a156afaa94..ea955f6db8b7 100644
--- a/arch/arm/mach-keystone/Kconfig
+++ b/arch/arm/mach-keystone/Kconfig
@@ -9,6 +9,8 @@ config ARCH_KEYSTONE
        select COMMON_CLK_KEYSTONE
        select ARCH_SUPPORTS_BIG_ENDIAN
        select ZONE_DMA if ARM_LPAE
+        select MIGHT_HAVE_PCI
+        select PCI_DOMAINS if PCI
        help
          Support for boards based on the Texas Instruments Keystone family of
          SoCs.
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 2c043a210db0..f73f588f649c 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -1,6 +1,6 @@
 config ARCH_MEDIATEK
-        bool "Mediatek MT6589 SoC" if ARCH_MULTI_V7
+        bool "Mediatek MT65xx & MT81xx SoC" if ARCH_MULTI_V7
        select ARM_GIC
        select MTK_TIMER
        help
-          Support for Mediatek Cortex-A7 Quad-Core-SoC MT6589.
+          Support for Mediatek MT65xx & MT81xx SoCs
diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
index f2acf075350d..a9549005097e 100644
--- a/arch/arm/mach-mediatek/mediatek.c
+++ b/arch/arm/mach-mediatek/mediatek.c
@@ -19,6 +19,9 @@
 static const char * const mediatek_board_dt_compat[] = {
        "mediatek,mt6589",
+        "mediatek,mt6592",
+        "mediatek,mt8127",
+        "mediatek,mt8135",
        NULL,
 };
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 2c1154e1794a..18301dc9d2e7 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -2,6 +2,7 @@ menuconfig ARCH_MESON
        bool "Amlogic Meson SoCs" if ARCH_MULTI_V7
        select GENERIC_IRQ_CHIP
        select ARM_GIC
+        select CACHE_L2X0
 if ARCH_MESON
@@ -10,4 +11,9 @@ config MACH_MESON6
        default ARCH_MESON
        select MESON6_TIMER
+config MACH_MESON8
+        bool "Amlogic Meson8 SoCs support"
+        default ARCH_MESON
+        select MESON6_TIMER
 endif
diff --git a/arch/arm/mach-meson/meson.c b/arch/arm/mach-meson/meson.c
index 5ee064f5a89f..5d6affe6a694 100644
--- a/arch/arm/mach-meson/meson.c
+++ b/arch/arm/mach-meson/meson.c
@@ -16,12 +16,14 @@
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
-static const char * const m6_common_board_compat[] = {
+static const char * const meson_common_board_compat[] = {
        "amlogic,meson6",
+        "amlogic,meson8",
        NULL,
 };
-DT_MACHINE_START(AML8726_MX, "Amlogic Meson6 platform")
+DT_MACHINE_START(MESON, "Amlogic Meson platform")
-        .dt_compat      = m6_common_board_compat,
+        .dt_compat      = meson_common_board_compat,
+        .l2c_aux_val    = 0,
+        .l2c_aux_mask   = ~0,
 MACHINE_END
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index e24136b42765..b4f01497ce0b 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -7,7 +7,7 @@ CFLAGS_pmsu.o			:= -march=armv7-a
 obj-$(CONFIG_MACH_MVEBU_ANY)     += system-controller.o mvebu-soc-id.o
 ifeq ($(CONFIG_MACH_MVEBU_V7),y)
-obj-y                            += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o pmsu_ll.o
+obj-y                            += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o pmsu_ll.o pm.o pm-board.o
 obj-$(CONFIG_SMP)                += platsmp.o headsmp.o platsmp-a9.o headsmp-a9.o
 endif
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index 84cd90d9b860..c55bbf81de0e 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -16,14 +16,8 @@
 #define __MACH_ARMADA_370_XP_H
 #ifdef CONFIG_SMP
-#include <linux/cpumask.h>
-#define ARMADA_XP_MAX_CPUS 4
 void armada_xp_secondary_startup(void);
 extern struct smp_operations armada_xp_smp_ops;
 #endif
-int armada_370_xp_pmsu_idle_enter(unsigned long deepidle);
 #endif /* __MACH_ARMADA_370_XP_H */
diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c
index d0d39f150fab..89a139ed7d5b 100644
--- a/arch/arm/mach-mvebu/board-v7.c
+++ b/arch/arm/mach-mvebu/board-v7.c
@@ -16,10 +16,12 @@
 #include <linux/init.h>
 #include <linux/clk-provider.h>
 #include <linux/of_address.h>
+#include <linux/of_fdt.h>
 #include <linux/of_platform.h>
 #include <linux/io.h>
 #include <linux/clocksource.h>
 #include <linux/dma-mapping.h>
+#include <linux/memblock.h>
 #include <linux/mbus.h>
 #include <linux/signal.h>
 #include <linux/slab.h>
@@ -57,6 +59,54 @@ void __iomem *mvebu_get_scu_base(void)
 }
 /*
+ * When returning from suspend, the platform goes through the
+ * bootloader, which executes its DDR3 training code. This code has
+ * the unfortunate idea of using the first 10 KB of each DRAM bank to
+ * exercise the RAM and calculate the optimal timings. Therefore, this
+ * area of RAM is overwritten, and shouldn't be used by the kernel if
+ * suspend/resume is supported.
+ */
+#ifdef CONFIG_SUSPEND
+#define MVEBU_DDR_TRAINING_AREA_SZ (10 * SZ_1K)
+static int __init mvebu_scan_mem(unsigned long node, const char *uname,
+                                 int depth, void *data)
+{
+        const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
+        const __be32 *reg, *endp;
+        int l;
+        if (type == NULL || strcmp(type, "memory"))
+                return 0;
+        reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l);
+        if (reg == NULL)
+                reg = of_get_flat_dt_prop(node, "reg", &l);
+        if (reg == NULL)
+                return 0;
+        endp = reg + (l / sizeof(__be32));
+        while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) {
+                u64 base, size;
+                base = dt_mem_next_cell(dt_root_addr_cells, &reg);
+                size = dt_mem_next_cell(dt_root_size_cells, &reg);
+                memblock_reserve(base, MVEBU_DDR_TRAINING_AREA_SZ);
+        }
+        return 0;
+}
+static void __init mvebu_memblock_reserve(void)
+{
+        of_scan_flat_dt(mvebu_scan_mem, NULL);
+}
+#else
+static void __init mvebu_memblock_reserve(void) {}
+#endif
+/*
 * Early versions of Armada 375 SoC have a bug where the BootROM
 * leaves an external data abort pending. The kernel is hit by this
 * data abort as soon as it enters userspace, because it unmasks the
@@ -124,76 +174,12 @@ static void __init i2c_quirk(void)
        return;
 }
-#define A375_Z1_THERMAL_FIXUP_OFFSET 0xc
-static void __init thermal_quirk(void)
-{
-        struct device_node *np;
-        u32 dev, rev;
-        int res;
-        /*
-         * The early SoC Z1 revision needs a quirk to be applied in order
-         * for the thermal controller to work properly. This quirk breaks
-         * the thermal support if applied on a SoC that doesn't need it,
-         * so we enforce the SoC revision to be known.
-         */
-        res = mvebu_get_soc_id(&dev, &rev);
-        if (res < 0 || (res == 0 && rev > ARMADA_375_Z1_REV))
-                return;
-        for_each_compatible_node(np, NULL, "marvell,armada375-thermal") {
-                struct property *prop;
-                __be32 newval, *newprop, *oldprop;
-                int len;
-                /*
-                 * The register offset is at a wrong location. This quirk
-                 * creates a new reg property as a clone of the previous
-                 * one and corrects the offset.
-                 */
-                oldprop = (__be32 *)of_get_property(np, "reg", &len);
-                if (!oldprop)
-                        continue;
-                /* Create a duplicate of the 'reg' property */
-                prop = kzalloc(sizeof(*prop), GFP_KERNEL);
-                prop->length = len;
-                prop->name = kstrdup("reg", GFP_KERNEL);
-                prop->value = kzalloc(len, GFP_KERNEL);
-                memcpy(prop->value, oldprop, len);
-                /* Fixup the register offset of the second entry */
-                oldprop += 2;
-                newprop = (__be32 *)prop->value + 2;
-                newval = cpu_to_be32(be32_to_cpu(*oldprop) -
-                                     A375_Z1_THERMAL_FIXUP_OFFSET);
-                *newprop = newval;
-                of_update_property(np, prop);
-                /*
-                 * The thermal controller needs some quirk too, so let's change
-                 * the compatible string to reflect this and allow the driver
-                 * the take the necessary action.
-                 */
-                prop = kzalloc(sizeof(*prop), GFP_KERNEL);
-                prop->name = kstrdup("compatible", GFP_KERNEL);
-                prop->length = sizeof("marvell,armada375-z1-thermal");
-                prop->value = kstrdup("marvell,armada375-z1-thermal",
-                                                GFP_KERNEL);
-                of_update_property(np, prop);
-        }
-        return;
-}
 static void __init mvebu_dt_init(void)
 {
        if (of_machine_is_compatible("marvell,armadaxp"))
                i2c_quirk();
-        if (of_machine_is_compatible("marvell,a375-db")) {
+        if (of_machine_is_compatible("marvell,a375-db"))
                external_abort_quirk();
-                thermal_quirk();
-        }
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
@@ -206,10 +192,16 @@ static const char * const armada_370_xp_dt_compat[] = {
 DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)")
        .l2c_aux_val    = 0,
        .l2c_aux_mask   = ~0,
+/*
+ * The following field (.smp) is still needed to ensure backward
+ * compatibility with old Device Trees that were not specifying the
+ * cpus enable-method property.
+ */
        .smp            = smp_ops(armada_xp_smp_ops),
        .init_machine   = mvebu_dt_init,
        .init_irq       = mvebu_init_irq,
        .restart        = mvebu_restart,
+        .reserve        = mvebu_memblock_reserve,
        .dt_compat      = armada_370_xp_dt_compat,
 MACHINE_END
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 044b51185fcc..3585cb394e9b 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -1,5 +1,6 @@
 /*
- * Coherency fabric (Aurora) support for Armada 370 and XP platforms.
+ * Coherency fabric (Aurora) support for Armada 370, 375, 38x and XP
+ * platforms.
 *
 * Copyright (C) 2012 Marvell
 *
@@ -11,7 +12,7 @@
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
- * The Armada 370 and Armada XP SOCs have a coherency fabric which is
+ * The Armada 370, 375, 38x and XP SOCs have a coherency fabric which is
 * responsible for ensuring hardware coherency between all CPUs and between
 * CPUs and I/O masters. This file initializes the coherency fabric and
 * supplies basic routines for configuring and controlling hardware coherency
@@ -28,12 +29,10 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/mbus.h>
-#include <linux/clk.h>
 #include <linux/pci.h>
 #include <asm/smp_plat.h>
 #include <asm/cacheflush.h>
 #include <asm/mach/map.h>
-#include "armada-370-xp.h"
 #include "coherency.h"
 #include "mvebu-soc-id.h"
@@ -42,8 +41,6 @@ void __iomem *coherency_base;
 static void __iomem *coherency_cpu_base;
 /* Coherency fabric registers */
-#define COHERENCY_FABRIC_CFG_OFFSET                0x4
 #define IO_SYNC_BARRIER_CTL_OFFSET                 0x0
 enum {
@@ -79,157 +76,8 @@ int set_cpu_coherent(void)
        return ll_enable_coherency();
 }
-/*
- * The below code implements the I/O coherency workaround on Armada
- * 375. This workaround consists in using the two channels of the
- * first XOR engine to trigger a XOR transaction that serves as the
- * I/O coherency barrier.
- */
-static void __iomem *xor_base, *xor_high_base;
-static dma_addr_t coherency_wa_buf_phys[CONFIG_NR_CPUS];
-static void *coherency_wa_buf[CONFIG_NR_CPUS];
-static bool coherency_wa_enabled;
-#define XOR_CONFIG(chan)            (0x10 + (chan * 4))
-#define XOR_ACTIVATION(chan)        (0x20 + (chan * 4))
-#define WINDOW_BAR_ENABLE(chan)     (0x240 + ((chan) << 2))
-#define WINDOW_BASE(w)              (0x250 + ((w) << 2))
-#define WINDOW_SIZE(w)              (0x270 + ((w) << 2))
-#define WINDOW_REMAP_HIGH(w)        (0x290 + ((w) << 2))
-#define WINDOW_OVERRIDE_CTRL(chan)  (0x2A0 + ((chan) << 2))
-#define XOR_DEST_POINTER(chan)      (0x2B0 + (chan * 4))
-#define XOR_BLOCK_SIZE(chan)        (0x2C0 + (chan * 4))
-#define XOR_INIT_VALUE_LOW           0x2E0
-#define XOR_INIT_VALUE_HIGH          0x2E4
-static inline void mvebu_hwcc_armada375_sync_io_barrier_wa(void)
-{
-        int idx = smp_processor_id();
-        /* Write '1' to the first word of the buffer */
-        writel(0x1, coherency_wa_buf[idx]);
-        /* Wait until the engine is idle */
-        while ((readl(xor_base + XOR_ACTIVATION(idx)) >> 4) & 0x3)
-                ;
-        dmb();
-        /* Trigger channel */
-        writel(0x1, xor_base + XOR_ACTIVATION(idx));
-        /* Poll the data until it is cleared by the XOR transaction */
-        while (readl(coherency_wa_buf[idx]))
-                ;
-}
-static void __init armada_375_coherency_init_wa(void)
-{
-        const struct mbus_dram_target_info *dram;
-        struct device_node *xor_node;
-        struct property *xor_status;
-        struct clk *xor_clk;
-        u32 win_enable = 0;
-        int i;
-        pr_warn("enabling coherency workaround for Armada 375 Z1, one XOR engine disabled\n");
-        /*
-         * Since the workaround uses one XOR engine, we grab a
-         * reference to its Device Tree node first.
-         */
-        xor_node = of_find_compatible_node(NULL, NULL, "marvell,orion-xor");
-        BUG_ON(!xor_node);
-        /*
-         * Then we mark it as disabled so that the real XOR driver
-         * will not use it.
-         */
-        xor_status = kzalloc(sizeof(struct property), GFP_KERNEL);
-        BUG_ON(!xor_status);
-        xor_status->value = kstrdup("disabled", GFP_KERNEL);
-        BUG_ON(!xor_status->value);
-        xor_status->length = 8;
-        xor_status->name = kstrdup("status", GFP_KERNEL);
-        BUG_ON(!xor_status->name);
-        of_update_property(xor_node, xor_status);
-        /*
-         * And we remap the registers, get the clock, and do the
-         * initial configuration of the XOR engine.
-         */
-        xor_base = of_iomap(xor_node, 0);
-        xor_high_base = of_iomap(xor_node, 1);
-        xor_clk = of_clk_get_by_name(xor_node, NULL);
-        BUG_ON(!xor_clk);
-        clk_prepare_enable(xor_clk);
-        dram = mv_mbus_dram_info();
-        for (i = 0; i < 8; i++) {
-                writel(0, xor_base + WINDOW_BASE(i));
-                writel(0, xor_base + WINDOW_SIZE(i));
-                if (i < 4)
-                        writel(0, xor_base + WINDOW_REMAP_HIGH(i));
-        }
-        for (i = 0; i < dram->num_cs; i++) {
-                const struct mbus_dram_window *cs = dram->cs + i;
-                writel((cs->base & 0xffff0000) |
-                       (cs->mbus_attr << 8) |
-                       dram->mbus_dram_target_id, xor_base + WINDOW_BASE(i));
-                writel((cs->size - 1) & 0xffff0000, xor_base + WINDOW_SIZE(i));
-                win_enable |= (1 << i);
-                win_enable |= 3 << (16 + (2 * i));
-        }
-        writel(win_enable, xor_base + WINDOW_BAR_ENABLE(0));
-        writel(win_enable, xor_base + WINDOW_BAR_ENABLE(1));
-        writel(0, xor_base + WINDOW_OVERRIDE_CTRL(0));
-        writel(0, xor_base + WINDOW_OVERRIDE_CTRL(1));
-        for (i = 0; i < CONFIG_NR_CPUS; i++) {
-                coherency_wa_buf[i] = kzalloc(PAGE_SIZE, GFP_KERNEL);
-                BUG_ON(!coherency_wa_buf[i]);
-                /*
-                 * We can't use the DMA mapping API, since we don't
-                 * have a valid 'struct device' pointer
-                 */
-                coherency_wa_buf_phys[i] =
-                        virt_to_phys(coherency_wa_buf[i]);
-                BUG_ON(!coherency_wa_buf_phys[i]);
-                /*
-                 * Configure the XOR engine for memset operation, with
-                 * a 128 bytes block size
-                 */
-                writel(0x444, xor_base + XOR_CONFIG(i));
-                writel(128, xor_base + XOR_BLOCK_SIZE(i));
-                writel(coherency_wa_buf_phys[i],
-                       xor_base + XOR_DEST_POINTER(i));
-        }
-        writel(0x0, xor_base + XOR_INIT_VALUE_LOW);
-        writel(0x0, xor_base + XOR_INIT_VALUE_HIGH);
-        coherency_wa_enabled = true;
-}
 static inline void mvebu_hwcc_sync_io_barrier(void)
 {
-        if (coherency_wa_enabled) {
-                mvebu_hwcc_armada375_sync_io_barrier_wa();
-                return;
-        }
        writel(0x1, coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET);
        while (readl(coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET) & 0x1);
 }
@@ -361,25 +209,41 @@ static int coherency_type(void)
 {
        struct device_node *np;
        const struct of_device_id *match;
+        int type;
-        np = of_find_matching_node_and_match(NULL, of_coherency_table, &match);
+        /*
-        if (np) {
+         * The coherency fabric is needed:
-                int type = (int) match->data;
+         * - For coherency between processors on Armada XP, so only
+         *   when SMP is enabled.
+         * - For coherency between the processor and I/O devices, but
+         *   this coherency requires many pre-requisites (write
+         *   allocate cache policy, shareable pages, SMP bit set) that
+         *   are only meant in SMP situations.
+         *
+         * Note that this means that on Armada 370, there is currently
+         * no way to use hardware I/O coherency, because even when
+         * CONFIG_SMP is enabled, is_smp() returns false due to the
+         * Armada 370 being a single-core processor. To lift this
+         * limitation, we would have to find a way to make the cache
+         * policy set to write-allocate (on all Armada SoCs), and to
+         * set the shareable attribute in page tables (on all Armada
+         * SoCs except the Armada 370). Unfortunately, such decisions
+         * are taken very early in the kernel boot process, at a point
+         * where we don't know yet on which SoC we are running.
-                /* Armada 370/XP coherency works in both UP and SMP */
+         */
-                if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP)
+        if (!is_smp())
-                        return type;
+                return COHERENCY_FABRIC_TYPE_NONE;
-                /* Armada 375 coherency works only on SMP */
+        np = of_find_matching_node_and_match(NULL, of_coherency_table, &match);
-                else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 && is_smp())
+        if (!np)
-                        return type;
+                return COHERENCY_FABRIC_TYPE_NONE;
-                /* Armada 380 coherency works only on SMP */
+        type = (int) match->data;
-                else if (type == COHERENCY_FABRIC_TYPE_ARMADA_380 && is_smp())
-                        return type;
-        }
-        return COHERENCY_FABRIC_TYPE_NONE;
+        of_node_put(np);
+        return type;
 }
 int coherency_available(void)
@@ -407,22 +271,9 @@ int __init coherency_init(void)
 static int __init coherency_late_init(void)
 {
-        int type = coherency_type();
+        if (coherency_available())
+                bus_register_notifier(&platform_bus_type,
-        if (type == COHERENCY_FABRIC_TYPE_NONE)
+                                      &mvebu_hwcc_nb);
-                return 0;
-        if (type == COHERENCY_FABRIC_TYPE_ARMADA_375) {
-                u32 dev, rev;
-                if (mvebu_get_soc_id(&dev, &rev) == 0 &&
-                    rev == ARMADA_375_Z1_REV)
-                        armada_375_coherency_init_wa();
-        }
-        bus_register_notifier(&platform_bus_type,
-                              &mvebu_hwcc_nb);
        return 0;
 }
diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
index f5d881b5d0f7..8b2fbc8b6bc6 100644
--- a/arch/arm/mach-mvebu/coherency_ll.S
+++ b/arch/arm/mach-mvebu/coherency_ll.S
@@ -24,7 +24,10 @@
 #include <asm/cp15.h>
        .text
-/* Returns the coherency base address in r1 (r0 is untouched) */
+/*
+ * Returns the coherency base address in r1 (r0 is untouched), or 0 if
+ * the coherency fabric is not enabled.
+ */
 ENTRY(ll_get_coherency_base)
        mrc     p15, 0, r1, c1, c0, 0
        tst     r1, #CR_M @ Check MMU bit enabled
@@ -32,8 +35,13 @@ ENTRY(ll_get_coherency_base)
        /*
         * MMU is disabled, use the physical address of the coherency
-         * base address.
+         * base address. However, if the coherency fabric isn't mapped
+         * (i.e its virtual address is zero), it means coherency is
+         * not enabled, so we return 0.
         */
+        ldr     r1, =coherency_base
+        cmp     r1, #0
+        beq     2f
        adr     r1, 3f
        ldr     r3, [r1]
        ldr     r1, [r1, r3]
@@ -85,6 +93,9 @@ ENTRY(ll_add_cpu_to_smp_group)
         */
        mov     r0, lr
        bl      ll_get_coherency_base
+        /* Bail out if the coherency is not enabled */
+        cmp     r1, #0
+        reteq   r0
        bl      ll_get_coherency_cpumask
        mov     lr, r0
        add     r0, r1, #ARMADA_XP_CFB_CFG_REG_OFFSET
@@ -107,6 +118,9 @@ ENTRY(ll_enable_coherency)
         */
        mov r0, lr
        bl      ll_get_coherency_base
+        /* Bail out if the coherency is not enabled */
+        cmp     r1, #0
+        reteq   r0
        bl      ll_get_coherency_cpumask
        mov lr, r0
        add     r0, r1, #ARMADA_XP_CFB_CTL_REG_OFFSET
@@ -131,6 +145,9 @@ ENTRY(ll_disable_coherency)
         */
        mov     r0, lr
        bl      ll_get_coherency_base
+        /* Bail out if the coherency is not enabled */
+        cmp     r1, #0
+        reteq   r0
        bl      ll_get_coherency_cpumask
        mov     lr, r0
        add     r0, r1, #ARMADA_XP_CFB_CTL_REG_OFFSET
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index 3ccb40c3bf94..3e0aca1f288a 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -25,4 +25,6 @@ int mvebu_system_controller_get_soc_id(u32 *dev, u32 *rev);
 void __iomem *mvebu_get_scu_base(void);
+int mvebu_pm_init(void (*board_pm_enter)(void __iomem *sdram_reg, u32 srcmd));
 #endif
diff --git a/arch/arm/mach-mvebu/cpu-reset.c b/arch/arm/mach-mvebu/cpu-reset.c
index 60fb53787004..4a2cadd6b48e 100644
--- a/arch/arm/mach-mvebu/cpu-reset.c
+++ b/arch/arm/mach-mvebu/cpu-reset.c
@@ -15,7 +15,6 @@
 #include <linux/of_address.h>
 #include <linux/io.h>
 #include <linux/resource.h>
-#include "armada-370-xp.h"
 static void __iomem *cpu_reset_base;
 static size_t cpu_reset_size;
diff --git a/arch/arm/mach-mvebu/headsmp-a9.S b/arch/arm/mach-mvebu/headsmp-a9.S
index be51c998c0cd..08d5ed46b996 100644
--- a/arch/arm/mach-mvebu/headsmp-a9.S
+++ b/arch/arm/mach-mvebu/headsmp-a9.S
@@ -22,5 +22,6 @@
 ENTRY(mvebu_cortex_a9_secondary_startup)
 ARM_BE8(setend  be)
        bl      v7_invalidate_l1
+        bl      armada_38x_scu_power_up
        b       secondary_startup
 ENDPROC(mvebu_cortex_a9_secondary_startup)
diff --git a/arch/arm/mach-mvebu/platsmp-a9.c b/arch/arm/mach-mvebu/platsmp-a9.c
index 47a71a924b96..2ec1a42b4321 100644
--- a/arch/arm/mach-mvebu/platsmp-a9.c
+++ b/arch/arm/mach-mvebu/platsmp-a9.c
@@ -43,21 +43,70 @@ static int __cpuinit mvebu_cortex_a9_boot_secondary(unsigned int cpu,
        else
                mvebu_pmsu_set_cpu_boot_addr(hw_cpu, mvebu_cortex_a9_secondary_startup);
        smp_wmb();
+        /*
+         * Doing this before deasserting the CPUs is needed to wake up CPUs
+         * in the offline state after using CPU hotplug.
+         */
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
        ret = mvebu_cpu_reset_deassert(hw_cpu);
        if (ret) {
                pr_err("Could not start the secondary CPU: %d\n", ret);
                return ret;
        }
-        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
        return 0;
 }
+/*
+ * When a CPU is brought back online, either through CPU hotplug, or
+ * because of the boot of a kexec'ed kernel, the PMSU configuration
+ * for this CPU might be in the deep idle state, preventing this CPU
+ * from receiving interrupts. Here, we therefore take out the current
+ * CPU from this state, which was entered by armada_38x_cpu_die()
+ * below.
+ */
+static void armada_38x_secondary_init(unsigned int cpu)
+{
+        mvebu_v7_pmsu_idle_exit();
+}
+#ifdef CONFIG_HOTPLUG_CPU
+static void armada_38x_cpu_die(unsigned int cpu)
+{
+        /*
+         * CPU hotplug is implemented by putting offline CPUs into the
+         * deep idle sleep state.
+         */
+        armada_38x_do_cpu_suspend(true);
+}
+/*
+ * We need a dummy function, so that platform_can_cpu_hotplug() knows
+ * we support CPU hotplug. However, the function does not need to do
+ * anything, because CPUs going offline can enter the deep idle state
+ * by themselves, without any help from a still alive CPU.
+ */
+static int armada_38x_cpu_kill(unsigned int cpu)
+{
+        return 1;
+}
+#endif
 static struct smp_operations mvebu_cortex_a9_smp_ops __initdata = {
        .smp_boot_secondary     = mvebu_cortex_a9_boot_secondary,
 };
+static struct smp_operations armada_38x_smp_ops __initdata = {
+        .smp_boot_secondary     = mvebu_cortex_a9_boot_secondary,
+        .smp_secondary_init     = armada_38x_secondary_init,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = armada_38x_cpu_die,
+        .cpu_kill               = armada_38x_cpu_kill,
+#endif
+};
 CPU_METHOD_OF_DECLARE(mvebu_armada_375_smp, "marvell,armada-375-smp",
                      &mvebu_cortex_a9_smp_ops);
 CPU_METHOD_OF_DECLARE(mvebu_armada_380_smp, "marvell,armada-380-smp",
-                      &mvebu_cortex_a9_smp_ops);
+                      &armada_38x_smp_ops);
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index 895dc373c8a1..58cc8c1575eb 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -30,10 +30,12 @@
 #include "pmsu.h"
 #include "coherency.h"
+#define ARMADA_XP_MAX_CPUS 4
 #define AXP_BOOTROM_BASE 0xfff00000
 #define AXP_BOOTROM_SIZE 0x100000
-static struct clk *__init get_cpu_clk(int cpu)
+static struct clk *get_cpu_clk(int cpu)
 {
        struct clk *cpu_clk;
        struct device_node *np = of_get_cpu_node(cpu, NULL);
@@ -46,29 +48,28 @@ static struct clk *__init get_cpu_clk(int cpu)
        return cpu_clk;
 }
-static void __init set_secondary_cpus_clock(void)
+static void set_secondary_cpu_clock(unsigned int cpu)
 {
-        int thiscpu, cpu;
+        int thiscpu;
        unsigned long rate;
        struct clk *cpu_clk;
-        thiscpu = smp_processor_id();
+        thiscpu = get_cpu();
        cpu_clk = get_cpu_clk(thiscpu);
        if (!cpu_clk)
-                return;
+                goto out;
        clk_prepare_enable(cpu_clk);
        rate = clk_get_rate(cpu_clk);
-        /* set all the other CPU clk to the same rate than the boot CPU */
+        cpu_clk = get_cpu_clk(cpu);
-        for_each_possible_cpu(cpu) {
+        if (!cpu_clk)
-                if (cpu == thiscpu)
+                goto out;
-                        continue;
+        clk_set_rate(cpu_clk, rate);
-                cpu_clk = get_cpu_clk(cpu);
+        clk_prepare_enable(cpu_clk);
-                if (!cpu_clk)
-                        return;
+out:
-                clk_set_rate(cpu_clk, rate);
+        put_cpu();
-                clk_prepare_enable(cpu_clk);
-        }
 }
 static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
@@ -78,6 +79,7 @@ static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
        pr_info("Booting CPU %d\n", cpu);
        hw_cpu = cpu_logical_map(cpu);
+        set_secondary_cpu_clock(hw_cpu);
        mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_xp_secondary_startup);
        /*
@@ -126,7 +128,6 @@ static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
        struct resource res;
        int err;
-        set_secondary_cpus_clock();
        flush_cache_all();
        set_cpu_coherent();
diff --git a/arch/arm/mach-mvebu/pm-board.c b/arch/arm/mach-mvebu/pm-board.c
new file mode 100644
index 000000000000..6dfd4ab97b2a
--- /dev/null
+++ b/arch/arm/mach-mvebu/pm-board.c
@@ -0,0 +1,141 @@
+/*
+ * Board-level suspend/resume support.
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_gpio.h>
+#include <linux/slab.h>
+#include "common.h"
+#define ARMADA_XP_GP_PIC_NR_GPIOS 3
+static void __iomem *gpio_ctrl;
+static int pic_gpios[ARMADA_XP_GP_PIC_NR_GPIOS];
+static int pic_raw_gpios[ARMADA_XP_GP_PIC_NR_GPIOS];
+static void mvebu_armada_xp_gp_pm_enter(void __iomem *sdram_reg, u32 srcmd)
+{
+        u32 reg, ackcmd;
+        int i;
+        /* Put 001 as value on the GPIOs */
+        reg = readl(gpio_ctrl);
+        for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++)
+                reg &= ~BIT(pic_raw_gpios[i]);
+        reg |= BIT(pic_raw_gpios[0]);
+        writel(reg, gpio_ctrl);
+        /* Prepare writing 111 to the GPIOs */
+        ackcmd = readl(gpio_ctrl);
+        for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++)
+                ackcmd |= BIT(pic_raw_gpios[i]);
+        /*
+         * Wait a while, the PIC needs quite a bit of time between the
+         * two GPIO commands.
+         */
+        mdelay(3000);
+        asm volatile (
+                /* Align to a cache line */
+                ".balign 32\n\t"
+                /* Enter self refresh */
+                "str %[srcmd], [%[sdram_reg]]\n\t"
+                /*
+                 * Wait 100 cycles for DDR to enter self refresh, by
+                 * doing 50 times two instructions.
+                 */
+                "mov r1, #50\n\t"
+                "1: subs r1, r1, #1\n\t"
+                "bne 1b\n\t"
+                /* Issue the command ACK */
+                "str %[ackcmd], [%[gpio_ctrl]]\n\t"
+                /* Trap the processor */
+                "b .\n\t"
+                : : [srcmd] "r" (srcmd), [sdram_reg] "r" (sdram_reg),
+                  [ackcmd] "r" (ackcmd), [gpio_ctrl] "r" (gpio_ctrl) : "r1");
+}
+static int mvebu_armada_xp_gp_pm_init(void)
+{
+        struct device_node *np;
+        struct device_node *gpio_ctrl_np;
+        int ret = 0, i;
+        if (!of_machine_is_compatible("marvell,axp-gp"))
+                return -ENODEV;
+        np = of_find_node_by_name(NULL, "pm_pic");
+        if (!np)
+                return -ENODEV;
+        for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++) {
+                char *name;
+                struct of_phandle_args args;
+                pic_gpios[i] = of_get_named_gpio(np, "ctrl-gpios", i);
+                if (pic_gpios[i] < 0) {
+                        ret = -ENODEV;
+                        goto out;
+                }
+                name = kasprintf(GFP_KERNEL, "pic-pin%d", i);
+                if (!name) {
+                        ret = -ENOMEM;
+                        goto out;
+                }
+                ret = gpio_request(pic_gpios[i], name);
+                if (ret < 0) {
+                        kfree(name);
+                        goto out;
+                }
+                ret = gpio_direction_output(pic_gpios[i], 0);
+                if (ret < 0) {
+                        gpio_free(pic_gpios[i]);
+                        kfree(name);
+                        goto out;
+                }
+                ret = of_parse_phandle_with_fixed_args(np, "ctrl-gpios", 2,
+                                                       i, &args);
+                if (ret < 0) {
+                        gpio_free(pic_gpios[i]);
+                        kfree(name);
+                        goto out;
+                }
+                gpio_ctrl_np = args.np;
+                pic_raw_gpios[i] = args.args[0];
+        }
+        gpio_ctrl = of_iomap(gpio_ctrl_np, 0);
+        if (!gpio_ctrl)
+                return -ENOMEM;
+        mvebu_pm_init(mvebu_armada_xp_gp_pm_enter);
+out:
+        of_node_put(np);
+        return ret;
+}
+late_initcall(mvebu_armada_xp_gp_pm_init);
diff --git a/arch/arm/mach-mvebu/pm.c b/arch/arm/mach-mvebu/pm.c
new file mode 100644
index 000000000000..6573a8f11f70
--- /dev/null
+++ b/arch/arm/mach-mvebu/pm.c
@@ -0,0 +1,218 @@
+/*
+ * Suspend/resume support. Currently supporting Armada XP only.
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/cpu_pm.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mbus.h>
+#include <linux/of_address.h>
+#include <linux/suspend.h>
+#include <asm/cacheflush.h>
+#include <asm/outercache.h>
+#include <asm/suspend.h>
+#include "coherency.h"
+#include "pmsu.h"
+#define SDRAM_CONFIG_OFFS                  0x0
+#define  SDRAM_CONFIG_SR_MODE_BIT          BIT(24)
+#define SDRAM_OPERATION_OFFS               0x18
+#define  SDRAM_OPERATION_SELF_REFRESH      0x7
+#define SDRAM_DLB_EVICTION_OFFS            0x30c
+#define  SDRAM_DLB_EVICTION_THRESHOLD_MASK 0xff
+static void (*mvebu_board_pm_enter)(void __iomem *sdram_reg, u32 srcmd);
+static void __iomem *sdram_ctrl;
+static int mvebu_pm_powerdown(unsigned long data)
+{
+        u32 reg, srcmd;
+        flush_cache_all();
+        outer_flush_all();
+        /*
+         * Issue a Data Synchronization Barrier instruction to ensure
+         * that all state saving has been completed.
+         */
+        dsb();
+        /* Flush the DLB and wait ~7 usec */
+        reg = readl(sdram_ctrl + SDRAM_DLB_EVICTION_OFFS);
+        reg &= ~SDRAM_DLB_EVICTION_THRESHOLD_MASK;
+        writel(reg, sdram_ctrl + SDRAM_DLB_EVICTION_OFFS);
+        udelay(7);
+        /* Set DRAM in battery backup mode */
+        reg = readl(sdram_ctrl + SDRAM_CONFIG_OFFS);
+        reg &= ~SDRAM_CONFIG_SR_MODE_BIT;
+        writel(reg, sdram_ctrl + SDRAM_CONFIG_OFFS);
+        /* Prepare to go to self-refresh */
+        srcmd = readl(sdram_ctrl + SDRAM_OPERATION_OFFS);
+        srcmd &= ~0x1F;
+        srcmd |= SDRAM_OPERATION_SELF_REFRESH;
+        mvebu_board_pm_enter(sdram_ctrl + SDRAM_OPERATION_OFFS, srcmd);
+        return 0;
+}
+#define BOOT_INFO_ADDR      0x3000
+#define BOOT_MAGIC_WORD     0xdeadb002
+#define BOOT_MAGIC_LIST_END 0xffffffff
+/*
+ * Those registers are accessed before switching the internal register
+ * base, which is why we hardcode the 0xd0000000 base address, the one
+ * used by the SoC out of reset.
+ */
+#define MBUS_WINDOW_12_CTRL       0xd00200b0
+#define MBUS_INTERNAL_REG_ADDRESS 0xd0020080
+#define SDRAM_WIN_BASE_REG(x)   (0x20180 + (0x8*x))
+#define SDRAM_WIN_CTRL_REG(x)   (0x20184 + (0x8*x))
+static phys_addr_t mvebu_internal_reg_base(void)
+{
+        struct device_node *np;
+        __be32 in_addr[2];
+        np = of_find_node_by_name(NULL, "internal-regs");
+        BUG_ON(!np);
+        /*
+         * Ask the DT what is the internal register address on this
+         * platform. In the mvebu-mbus DT binding, 0xf0010000
+         * corresponds to the internal register window.
+         */
+        in_addr[0] = cpu_to_be32(0xf0010000);
+        in_addr[1] = 0x0;
+        return of_translate_address(np, in_addr);
+}
+static void mvebu_pm_store_bootinfo(void)
+{
+        u32 *store_addr;
+        phys_addr_t resume_pc;
+        store_addr = phys_to_virt(BOOT_INFO_ADDR);
+        resume_pc = virt_to_phys(armada_370_xp_cpu_resume);
+        /*
+         * The bootloader expects the first two words to be a magic
+         * value (BOOT_MAGIC_WORD), followed by the address of the
+         * resume code to jump to. Then, it expects a sequence of
+         * (address, value) pairs, which can be used to restore the
+         * value of certain registers. This sequence must end with the
+         * BOOT_MAGIC_LIST_END magic value.
+         */
+        writel(BOOT_MAGIC_WORD, store_addr++);
+        writel(resume_pc, store_addr++);
+        /*
+         * Some platforms remap their internal register base address
+         * to 0xf1000000. However, out of reset, window 12 starts at
+         * 0xf0000000 and ends at 0xf7ffffff, which would overlap with
+         * the internal registers. Therefore, disable window 12.
+         */
+        writel(MBUS_WINDOW_12_CTRL, store_addr++);
+        writel(0x0, store_addr++);
+        /*
+         * Set the internal register base address to the value
+         * expected by Linux, as read from the Device Tree.
+         */
+        writel(MBUS_INTERNAL_REG_ADDRESS, store_addr++);
+        writel(mvebu_internal_reg_base(), store_addr++);
+        /*
+         * Ask the mvebu-mbus driver to store the SDRAM window
+         * configuration, which has to be restored by the bootloader
+         * before re-entering the kernel on resume.
+         */
+        store_addr += mvebu_mbus_save_cpu_target(store_addr);
+        writel(BOOT_MAGIC_LIST_END, store_addr);
+}
+static int mvebu_pm_enter(suspend_state_t state)
+{
+        if (state != PM_SUSPEND_MEM)
+                return -EINVAL;
+        cpu_pm_enter();
+        mvebu_pm_store_bootinfo();
+        cpu_suspend(0, mvebu_pm_powerdown);
+        outer_resume();
+        mvebu_v7_pmsu_idle_exit();
+        set_cpu_coherent();
+        cpu_pm_exit();
+        return 0;
+}
+static const struct platform_suspend_ops mvebu_pm_ops = {
+        .enter = mvebu_pm_enter,
+        .valid = suspend_valid_only_mem,
+};
+int mvebu_pm_init(void (*board_pm_enter)(void __iomem *sdram_reg, u32 srcmd))
+{
+        struct device_node *np;
+        struct resource res;
+        if (!of_machine_is_compatible("marvell,armadaxp"))
+                return -ENODEV;
+        np = of_find_compatible_node(NULL, NULL,
+                                     "marvell,armada-xp-sdram-controller");
+        if (!np)
+                return -ENODEV;
+        if (of_address_to_resource(np, 0, &res)) {
+                of_node_put(np);
+                return -ENODEV;
+        }
+        if (!request_mem_region(res.start, resource_size(&res),
+                                np->full_name)) {
+                of_node_put(np);
+                return -EBUSY;
+        }
+        sdram_ctrl = ioremap(res.start, resource_size(&res));
+        if (!sdram_ctrl) {
+                release_mem_region(res.start, resource_size(&res));
+                of_node_put(np);
+                return -ENOMEM;
+        }
+        of_node_put(np);
+        mvebu_board_pm_enter = board_pm_enter;
+        suspend_set_ops(&mvebu_pm_ops);
+        return 0;
+}
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index bbd8664d1bac..d8ab605a44fa 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -20,6 +20,7 @@
 #include <linux/clk.h>
 #include <linux/cpu_pm.h>
+#include <linux/cpufreq-dt.h>
 #include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/io.h>
@@ -39,7 +40,6 @@
 #include <asm/suspend.h>
 #include <asm/tlbflush.h>
 #include "common.h"
-#include "armada-370-xp.h"
 #define PMSU_BASE_OFFSET    0x100
@@ -312,7 +312,7 @@ static int armada_370_xp_cpu_suspend(unsigned long deepidle)
        return cpu_suspend(deepidle, armada_370_xp_pmsu_idle_enter);
 }
-static int armada_38x_do_cpu_suspend(unsigned long deepidle)
+int armada_38x_do_cpu_suspend(unsigned long deepidle)
 {
        unsigned long flags = 0;
@@ -572,6 +572,10 @@ int mvebu_pmsu_dfs_request(int cpu)
        return 0;
 }
+struct cpufreq_dt_platform_data cpufreq_dt_pd = {
+        .independent_clocks = true,
+};
 static int __init armada_xp_pmsu_cpufreq_init(void)
 {
        struct device_node *np;
@@ -644,7 +648,8 @@ static int __init armada_xp_pmsu_cpufreq_init(void)
                }
        }
-        platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
+        platform_device_register_data(NULL, "cpufreq-dt", -1,
+                                      &cpufreq_dt_pd, sizeof(cpufreq_dt_pd));
        return 0;
 }
diff --git a/arch/arm/mach-mvebu/pmsu.h b/arch/arm/mach-mvebu/pmsu.h
index 6b58c1fe2b0d..ea79269c2702 100644
--- a/arch/arm/mach-mvebu/pmsu.h
+++ b/arch/arm/mach-mvebu/pmsu.h
@@ -17,5 +17,8 @@ int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target,
                             phys_addr_t resume_addr_reg);
 void mvebu_v7_pmsu_idle_exit(void);
+void armada_370_xp_cpu_resume(void);
+int armada_370_xp_pmsu_idle_enter(unsigned long deepidle);
+int armada_38x_do_cpu_suspend(unsigned long deepidle);
 #endif  /* __MACH_370_XP_PMSU_H */
diff --git a/arch/arm/mach-mvebu/pmsu_ll.S b/arch/arm/mach-mvebu/pmsu_ll.S
index a945756cfb45..88651221dbdd 100644
--- a/arch/arm/mach-mvebu/pmsu_ll.S
+++ b/arch/arm/mach-mvebu/pmsu_ll.S
@@ -12,12 +12,32 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
+ENTRY(armada_38x_scu_power_up)
+        mrc     p15, 4, r1, c15, c0     @ get SCU base address
+        orr     r1, r1, #0x8            @ SCU CPU Power Status Register
+        mrc     15, 0, r0, cr0, cr0, 5  @ get the CPU ID
+        and     r0, r0, #15
+        add     r1, r1, r0
+        mov     r0, #0x0
+        strb    r0, [r1]                @ switch SCU power state to Normal mode
+        ret     lr
+ENDPROC(armada_38x_scu_power_up)
 /*
 * This is the entry point through which CPUs exiting cpuidle deep
 * idle state are going.
 */
 ENTRY(armada_370_xp_cpu_resume)
 ARM_BE8(setend  be )                    @ go BE8 if entered LE
+        /*
+         * Disable the MMU that might have been enabled in BootROM if
+         * this code is used in the resume path of a suspend/resume
+         * cycle.
+         */
+        mrc     p15, 0, r1, c1, c0, 0
+        bic     r1, #1
+        mcr     p15, 0, r1, c1, c0, 0
        bl      ll_add_cpu_to_smp_group
        bl      ll_enable_coherency
        b       cpu_resume
@@ -27,13 +47,7 @@ ENTRY(armada_38x_cpu_resume)
        /* do we need it for Armada 38x*/
 ARM_BE8(setend  be )                    @ go BE8 if entered LE
        bl      v7_invalidate_l1
-        mrc     p15, 4, r1, c15, c0     @ get SCU base address
+        bl      armada_38x_scu_power_up
-        orr     r1, r1, #0x8            @ SCU CPU Power Status Register
-        mrc     15, 0, r0, cr0, cr0, 5  @ get the CPU ID
-        and     r0, r0, #15
-        add     r1, r1, r0
-        mov     r0, #0x0
-        strb    r0, [r1]                @ switch SCU power state to Normal mode
        b       cpu_resume
 ENDPROC(armada_38x_cpu_resume)
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 9116ca476d7c..9bda46f1fab7 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -144,6 +144,7 @@ static int __init cpu8815_mmcsd_init(void)
 device_initcall(cpu8815_mmcsd_init);
 static const char * cpu8815_board_compat[] = {
+        "st,nomadik-nhk-15",
        "calaosystems,usb-s8815",
        NULL,
 };
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f4d06aea8460..6e249324fdd7 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -79,7 +79,9 @@ config ARCH_OMAP2PLUS
        select CLKSRC_MMIO
        select GENERIC_IRQ_CHIP
        select MACH_OMAP_GENERIC
+        select MEMORY
        select OMAP_DM_TIMER
+        select OMAP_GPMC
        select PINCTRL
        select SOC_BUS
        select TI_PRIV_EDMA
@@ -235,12 +237,6 @@ config MACH_TOUCHBOOK
        default y
        select OMAP_PACKAGE_CBB
-config MACH_OMAP_3430SDP
-        bool "OMAP 3430 SDP board"
-        depends on ARCH_OMAP3
-        default y
-        select OMAP_PACKAGE_CBB
 config MACH_NOKIA_N810
       bool
@@ -282,16 +278,6 @@ config MACH_SBC3530
        default y
        select OMAP_PACKAGE_CUS
-config MACH_TI8168EVM
-        bool "TI8168 Evaluation Module"
-        depends on SOC_TI81XX
-        default y
-config MACH_TI8148EVM
-        bool "TI8148 Evaluation Module"
-        depends on SOC_TI81XX
-        default y
 config OMAP3_EMU
        bool "OMAP3 debugging peripherals"
        depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index d9e94122073e..08cc94474d17 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -6,7 +6,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
        -I$(srctree)/arch/arm/plat-omap/include
 # Common support
-obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o gpmc.o timer.o pm.o \
+obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o timer.o pm.o \
         common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
         omap_device.o sram.o drm.o
@@ -113,7 +113,7 @@ obj-y					+= prm_common.o cm_common.o
 obj-$(CONFIG_ARCH_OMAP2)                += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += vc3xxx_data.o vp3xxx_data.o
-omap-prcm-4-5-common                    =  cminst44xx.o cm44xx.o prm44xx.o \
+omap-prcm-4-5-common                    =  cminst44xx.o prm44xx.o \
                                           prcm_mpu44xx.o prminst44xx.o \
                                           vc44xx_data.o vp44xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += $(omap-prcm-4-5-common)
@@ -246,7 +246,6 @@ obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o
 obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o
 obj-$(CONFIG_MACH_OVERO)                += board-overo.o
 obj-$(CONFIG_MACH_OMAP3_PANDORA)        += board-omap3pandora.o
-obj-$(CONFIG_MACH_OMAP_3430SDP)         += board-3430sdp.o
 obj-$(CONFIG_MACH_NOKIA_N8X0)           += board-n8x0.o
 obj-$(CONFIG_MACH_NOKIA_RX51)           += board-rx51.o sdram-nokia.o
 obj-$(CONFIG_MACH_NOKIA_RX51)           += board-rx51-peripherals.o
@@ -260,8 +259,6 @@ obj-$(CONFIG_MACH_OMAP3517EVM)		+= board-am3517evm.o
 obj-$(CONFIG_MACH_CRANEBOARD)           += board-am3517crane.o
 obj-$(CONFIG_MACH_SBC3530)              += board-omap3stalker.o
-obj-$(CONFIG_MACH_TI8168EVM)            += board-ti8168evm.o
-obj-$(CONFIG_MACH_TI8148EVM)            += board-ti8168evm.o
 # Platform specific device init code
@@ -284,9 +281,6 @@ obj-y					+= $(onenand-m) $(onenand-y)
 nand-$(CONFIG_MTD_NAND_OMAP2)           := gpmc-nand.o
 obj-y                                   += $(nand-m) $(nand-y)
-smc91x-$(CONFIG_SMC91X)                 := gpmc-smc91x.o
-obj-y                                   += $(smc91x-m) $(smc91x-y)
 smsc911x-$(CONFIG_SMSC911X)             := gpmc-smsc911x.o
 obj-y                                   += $(smsc911x-m) $(smsc911x-y)
 ifneq ($(CONFIG_HWSPINLOCK_OMAP),)
diff --git a/arch/arm/mach-omap2/am33xx-restart.c b/arch/arm/mach-omap2/am33xx-restart.c
index c88d8df753c2..5bace6a45ffb 100644
--- a/arch/arm/mach-omap2/am33xx-restart.c
+++ b/arch/arm/mach-omap2/am33xx-restart.c
@@ -9,8 +9,7 @@
 #include <linux/reboot.h>
 #include "common.h"
-#include "prm-regbits-33xx.h"
+#include "prm.h"
-#include "prm33xx.h"
 /**
 * am3xx_restart - trigger a software restart of the SoC
@@ -24,12 +23,5 @@ void am33xx_restart(enum reboot_mode mode, const char *cmd)
 {
        /* TODO: Handle mode and cmd if necessary */
-        am33xx_prm_rmw_reg_bits(AM33XX_RST_GLOBAL_WARM_SW_MASK,
+        omap_prm_reset_system();
-                                AM33XX_RST_GLOBAL_WARM_SW_MASK,
-                                AM33XX_PRM_DEVICE_MOD,
-                                AM33XX_PRM_RSTCTRL_OFFSET);
-        /* OCP barrier */
-        (void)am33xx_prm_read_reg(AM33XX_PRM_DEVICE_MOD,
-                                  AM33XX_PRM_RSTCTRL_OFFSET);
 }
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
deleted file mode 100644
index d21a3048d06b..000000000000
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ /dev/null
@@ -1,632 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/board-3430sdp.c
- *
- * Copyright (C) 2007 Texas Instruments
- *
- * Modified from mach-omap2/board-generic.c
- *
- * Initial code: Syed Mohammed Khasim
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/input.h>
-#include <linux/input/matrix_keypad.h>
-#include <linux/spi/spi.h>
-#include <linux/i2c/twl.h>
-#include <linux/regulator/machine.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <linux/platform_data/omap-twl4030.h>
-#include <linux/usb/phy.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include "common.h"
-#include <linux/omap-dma.h>
-#include <video/omapdss.h>
-#include <video/omap-panel-data.h>
-#include "gpmc.h"
-#include "gpmc-smc91x.h"
-#include "soc.h"
-#include "board-flash.h"
-#include "mux.h"
-#include "sdram-qimonda-hyb18m512160af-6.h"
-#include "hsmmc.h"
-#include "pm.h"
-#include "control.h"
-#include "common-board-devices.h"
-#define CONFIG_DISABLE_HFCLK 1
-#define SDP3430_TS_GPIO_IRQ_SDPV1       3
-#define SDP3430_TS_GPIO_IRQ_SDPV2       2
-#define ENABLE_VAUX3_DEDICATED  0x03
-#define ENABLE_VAUX3_DEV_GRP    0x20
-#define TWL4030_MSECURE_GPIO 22
-static uint32_t board_keymap[] = {
-        KEY(0, 0, KEY_LEFT),
-        KEY(0, 1, KEY_RIGHT),
-        KEY(0, 2, KEY_A),
-        KEY(0, 3, KEY_B),
-        KEY(0, 4, KEY_C),
-        KEY(1, 0, KEY_DOWN),
-        KEY(1, 1, KEY_UP),
-        KEY(1, 2, KEY_E),
-        KEY(1, 3, KEY_F),
-        KEY(1, 4, KEY_G),
-        KEY(2, 0, KEY_ENTER),
-        KEY(2, 1, KEY_I),
-        KEY(2, 2, KEY_J),
-        KEY(2, 3, KEY_K),
-        KEY(2, 4, KEY_3),
-        KEY(3, 0, KEY_M),
-        KEY(3, 1, KEY_N),
-        KEY(3, 2, KEY_O),
-        KEY(3, 3, KEY_P),
-        KEY(3, 4, KEY_Q),
-        KEY(4, 0, KEY_R),
-        KEY(4, 1, KEY_4),
-        KEY(4, 2, KEY_T),
-        KEY(4, 3, KEY_U),
-        KEY(4, 4, KEY_D),
-        KEY(5, 0, KEY_V),
-        KEY(5, 1, KEY_W),
-        KEY(5, 2, KEY_L),
-        KEY(5, 3, KEY_S),
-        KEY(5, 4, KEY_H),
-        0
-};
-static struct matrix_keymap_data board_map_data = {
-        .keymap                 = board_keymap,
-        .keymap_size            = ARRAY_SIZE(board_keymap),
-};
-static struct twl4030_keypad_data sdp3430_kp_data = {
-        .keymap_data    = &board_map_data,
-        .rows           = 5,
-        .cols           = 6,
-        .rep            = 1,
-};
-#define SDP3430_LCD_PANEL_BACKLIGHT_GPIO        8
-#define SDP3430_LCD_PANEL_ENABLE_GPIO           5
-static void __init sdp3430_display_init(void)
-{
-        int r;
-        /*
-         * the backlight GPIO doesn't directly go to the panel, it enables
-         * an internal circuit on 3430sdp to create the signal V_BKL_28V,
-         * this is connected to LED+ pin of the sharp panel. This GPIO
-         * is left enabled in the board file, and not passed to the panel
-         * as platform_data.
-         */
-        r = gpio_request_one(SDP3430_LCD_PANEL_BACKLIGHT_GPIO,
-                                GPIOF_OUT_INIT_HIGH, "LCD Backlight");
-        if (r)
-                pr_err("failed to get LCD Backlight GPIO\n");
-}
-static struct panel_sharp_ls037v7dw01_platform_data sdp3430_lcd_pdata = {
-        .name                   = "lcd",
-        .source                 = "dpi.0",
-        .data_lines             = 16,
-        .resb_gpio              = SDP3430_LCD_PANEL_ENABLE_GPIO,
-        .ini_gpio               = -1,
-        .mo_gpio                = -1,
-        .lr_gpio                = -1,
-        .ud_gpio                = -1,
-};
-static struct platform_device sdp3430_lcd_device = {
-        .name                   = "panel-sharp-ls037v7dw01",
-        .id                     = 0,
-        .dev.platform_data      = &sdp3430_lcd_pdata,
-};
-static struct connector_dvi_platform_data sdp3430_dvi_connector_pdata = {
-        .name                   = "dvi",
-        .source                 = "tfp410.0",
-        .i2c_bus_num            = -1,
-};
-static struct platform_device sdp3430_dvi_connector_device = {
-        .name                   = "connector-dvi",
-        .id                     = 0,
-        .dev.platform_data      = &sdp3430_dvi_connector_pdata,
-};
-static struct encoder_tfp410_platform_data sdp3430_tfp410_pdata = {
-        .name                   = "tfp410.0",
-        .source                 = "dpi.0",
-        .data_lines             = 24,
-        .power_down_gpio        = -1,
-};
-static struct platform_device sdp3430_tfp410_device = {
-        .name                   = "tfp410",
-        .id                     = 0,
-        .dev.platform_data      = &sdp3430_tfp410_pdata,
-};
-static struct connector_atv_platform_data sdp3430_tv_pdata = {
-        .name = "tv",
-        .source = "venc.0",
-        .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO,
-        .invert_polarity = false,
-};
-static struct platform_device sdp3430_tv_connector_device = {
-        .name                   = "connector-analog-tv",
-        .id                     = 0,
-        .dev.platform_data      = &sdp3430_tv_pdata,
-};
-static struct omap_dss_board_info sdp3430_dss_data = {
-        .default_display_name = "lcd",
-};
-static struct omap2_hsmmc_info mmc[] = {
-        {
-                .mmc            = 1,
-                /* 8 bits (default) requires S6.3 == ON,
-                 * so the SIM card isn't used; else 4 bits.
-                 */
-                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-                .gpio_wp        = 4,
-                .deferred       = true,
-        },
-        {
-                .mmc            = 2,
-                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-                .gpio_wp        = 7,
-                .deferred       = true,
-        },
-        {}      /* Terminator */
-};
-static struct omap_tw4030_pdata omap_twl4030_audio_data = {
-        .voice_connected = true,
-        .custom_routing = true,
-        .has_hs         = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT,
-        .has_hf         = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT,
-        .has_mainmic    = true,
-        .has_submic     = true,
-        .has_hsmic      = true,
-        .has_linein     = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT,
-};
-static int sdp3430_twl_gpio_setup(struct device *dev,
-                unsigned gpio, unsigned ngpio)
-{
-        /* gpio + 0 is "mmc0_cd" (input/IRQ),
-         * gpio + 1 is "mmc1_cd" (input/IRQ)
-         */
-        mmc[0].gpio_cd = gpio + 0;
-        mmc[1].gpio_cd = gpio + 1;
-        omap_hsmmc_late_init(mmc);
-        /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
-        gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "sub_lcd_en_bkl");
-        /* gpio + 15 is "sub_lcd_nRST" (output) */
-        gpio_request_one(gpio + 15, GPIOF_OUT_INIT_LOW, "sub_lcd_nRST");
-        omap_twl4030_audio_data.jack_detect = gpio + 2;
-        omap_twl4030_audio_init("SDP3430", &omap_twl4030_audio_data);
-        return 0;
-}
-static struct twl4030_gpio_platform_data sdp3430_gpio_data = {
-        .pulldowns      = BIT(2) | BIT(6) | BIT(8) | BIT(13)
-                                | BIT(16) | BIT(17),
-        .setup          = sdp3430_twl_gpio_setup,
-};
-/* regulator consumer mappings */
-/* ads7846 on SPI */
-static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
-        REGULATOR_SUPPLY("vcc", "spi1.0"),
-};
-static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
-        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
-};
-static struct regulator_consumer_supply sdp3430_vsim_supplies[] = {
-        REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
-};
-static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = {
-        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
-};
-/*
- * Apply all the fixed voltages since most versions of U-Boot
- * don't bother with that initialization.
- */
-/* VAUX1 for mainboard (irda and sub-lcd) */
-static struct regulator_init_data sdp3430_vaux1 = {
-        .constraints = {
-                .min_uV                 = 2800000,
-                .max_uV                 = 2800000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-};
-/* VAUX2 for camera module */
-static struct regulator_init_data sdp3430_vaux2 = {
-        .constraints = {
-                .min_uV                 = 2800000,
-                .max_uV                 = 2800000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-};
-/* VAUX3 for LCD board */
-static struct regulator_init_data sdp3430_vaux3 = {
-        .constraints = {
-                .min_uV                 = 2800000,
-                .max_uV                 = 2800000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies          = ARRAY_SIZE(sdp3430_vaux3_supplies),
-        .consumer_supplies              = sdp3430_vaux3_supplies,
-};
-/* VAUX4 for OMAP VDD_CSI2 (camera) */
-static struct regulator_init_data sdp3430_vaux4 = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-};
-/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
-static struct regulator_init_data sdp3430_vmmc1 = {
-        .constraints = {
-                .min_uV                 = 1850000,
-                .max_uV                 = 3150000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(sdp3430_vmmc1_supplies),
-        .consumer_supplies      = sdp3430_vmmc1_supplies,
-};
-/* VMMC2 for MMC2 card */
-static struct regulator_init_data sdp3430_vmmc2 = {
-        .constraints = {
-                .min_uV                 = 1850000,
-                .max_uV                 = 1850000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(sdp3430_vmmc2_supplies),
-        .consumer_supplies      = sdp3430_vmmc2_supplies,
-};
-/* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
-static struct regulator_init_data sdp3430_vsim = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 3000000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(sdp3430_vsim_supplies),
-        .consumer_supplies      = sdp3430_vsim_supplies,
-};
-static struct twl4030_platform_data sdp3430_twldata = {
-        /* platform_data for children goes here */
-        .gpio           = &sdp3430_gpio_data,
-        .keypad         = &sdp3430_kp_data,
-        .vaux1          = &sdp3430_vaux1,
-        .vaux2          = &sdp3430_vaux2,
-        .vaux3          = &sdp3430_vaux3,
-        .vaux4          = &sdp3430_vaux4,
-        .vmmc1          = &sdp3430_vmmc1,
-        .vmmc2          = &sdp3430_vmmc2,
-        .vsim           = &sdp3430_vsim,
-};
-static int __init omap3430_i2c_init(void)
-{
-        /* i2c1 for PMIC only */
-        omap3_pmic_get_config(&sdp3430_twldata,
-                        TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
-                        TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO,
-                        TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
-        sdp3430_twldata.vdac->constraints.apply_uV = true;
-        sdp3430_twldata.vpll2->constraints.apply_uV = true;
-        sdp3430_twldata.vpll2->constraints.name = "VDVI";
-        sdp3430_twldata.audio->codec->hs_extmute = 1;
-        sdp3430_twldata.audio->codec->hs_extmute_gpio = -EINVAL;
-        omap3_pmic_init("twl4030", &sdp3430_twldata);
-        /* i2c2 on camera connector (for sensor control) and optional isp1301 */
-        omap_register_i2c_bus(2, 400, NULL, 0);
-        /* i2c3 on display connector (for DVI, tfp410) */
-        omap_register_i2c_bus(3, 400, NULL, 0);
-        return 0;
-}
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
-static struct omap_smc91x_platform_data board_smc91x_data = {
-        .cs             = 3,
-        .flags          = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 |
-                                IORESOURCE_IRQ_LOWLEVEL,
-};
-static void __init board_smc91x_init(void)
-{
-        if (omap_rev() > OMAP3430_REV_ES1_0)
-                board_smc91x_data.gpio_irq = 6;
-        else
-                board_smc91x_data.gpio_irq = 29;
-        gpmc_smc91x_init(&board_smc91x_data);
-}
-#else
-static inline void board_smc91x_init(void)
-{
-}
-#endif
-static void enable_board_wakeup_source(void)
-{
-        /* T2 interrupt line (keypad) */
-        omap_mux_init_signal("sys_nirq",
-                OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
-}
-static struct usbhs_phy_data phy_data[] __initdata = {
-        {
-                .port = 1,
-                .reset_gpio = 57,
-                .vcc_gpio = -EINVAL,
-        },
-        {
-                .port = 2,
-                .reset_gpio = 61,
-                .vcc_gpio = -EINVAL,
-        },
-};
-static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-};
-#ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#else
-#define board_mux       NULL
-#endif
-/*
- * SDP3430 V2 Board CS organization
- * Different from SDP3430 V1. Now 4 switches used to specify CS
- *
- * See also the Switch S8 settings in the comments.
- */
-static char chip_sel_3430[][GPMC_CS_NUM] = {
-        {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */
-        {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */
-        {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */
-};
-static struct mtd_partition sdp_nor_partitions[] = {
-        /* bootloader (U-Boot, etc) in first sector */
-        {
-                .name           = "Bootloader-NOR",
-                .offset         = 0,
-                .size           = SZ_256K,
-                .mask_flags     = MTD_WRITEABLE, /* force read-only */
-        },
-        /* bootloader params in the next sector */
-        {
-                .name           = "Params-NOR",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = SZ_256K,
-                .mask_flags     = 0,
-        },
-        /* kernel */
-        {
-                .name           = "Kernel-NOR",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = SZ_2M,
-                .mask_flags     = 0
-        },
-        /* file system */
-        {
-                .name           = "Filesystem-NOR",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = MTDPART_SIZ_FULL,
-                .mask_flags     = 0
-        }
-};
-static struct mtd_partition sdp_onenand_partitions[] = {
-        {
-                .name           = "X-Loader-OneNAND",
-                .offset         = 0,
-                .size           = 4 * (64 * 2048),
-                .mask_flags     = MTD_WRITEABLE  /* force read-only */
-        },
-        {
-                .name           = "U-Boot-OneNAND",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 2 * (64 * 2048),
-                .mask_flags     = MTD_WRITEABLE  /* force read-only */
-        },
-        {
-                .name           = "U-Boot Environment-OneNAND",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 1 * (64 * 2048),
-        },
-        {
-                .name           = "Kernel-OneNAND",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 16 * (64 * 2048),
-        },
-        {
-                .name           = "File System-OneNAND",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = MTDPART_SIZ_FULL,
-        },
-};
-static struct mtd_partition sdp_nand_partitions[] = {
-        /* All the partition sizes are listed in terms of NAND block size */
-        {
-                .name           = "X-Loader-NAND",
-                .offset         = 0,
-                .size           = 4 * (64 * 2048),
-                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
-        },
-        {
-                .name           = "U-Boot-NAND",
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
-                .size           = 10 * (64 * 2048),
-                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
-        },
-        {
-                .name           = "Boot Env-NAND",
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x1c0000 */
-                .size           = 6 * (64 * 2048),
-        },
-        {
-                .name           = "Kernel-NAND",
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x280000 */
-                .size           = 40 * (64 * 2048),
-        },
-        {
-                .name           = "File System - NAND",
-                .size           = MTDPART_SIZ_FULL,
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x780000 */
-        },
-};
-static struct flash_partitions sdp_flash_partitions[] = {
-        {
-                .parts = sdp_nor_partitions,
-                .nr_parts = ARRAY_SIZE(sdp_nor_partitions),
-        },
-        {
-                .parts = sdp_onenand_partitions,
-                .nr_parts = ARRAY_SIZE(sdp_onenand_partitions),
-        },
-        {
-                .parts = sdp_nand_partitions,
-                .nr_parts = ARRAY_SIZE(sdp_nand_partitions),
-        },
-};
-static void __init omap_3430sdp_init(void)
-{
-        int gpio_pendown;
-        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
-        omap_hsmmc_init(mmc);
-        omap3430_i2c_init();
-        omap_display_init(&sdp3430_dss_data);
-        platform_device_register(&sdp3430_lcd_device);
-        platform_device_register(&sdp3430_tfp410_device);
-        platform_device_register(&sdp3430_dvi_connector_device);
-        platform_device_register(&sdp3430_tv_connector_device);
-        if (omap_rev() > OMAP3430_REV_ES1_0)
-                gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV2;
-        else
-                gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1;
-        omap_ads7846_init(1, gpio_pendown, 310, NULL);
-        omap_serial_init();
-        omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL);
-        usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
-        usb_musb_init(NULL);
-        board_smc91x_init();
-        board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
-        sdp3430_display_init();
-        enable_board_wakeup_source();
-        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
-        usbhs_init(&usbhs_bdata);
-}
-MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
-        /* Maintainer: Syed Khasim - Texas Instruments Inc */
-        .atag_offset    = 0x100,
-        .reserve        = omap_reserve,
-        .map_io         = omap3_map_io,
-        .init_early     = omap3430_init_early,
-        .init_irq       = omap3_init_irq,
-        .init_machine   = omap_3430sdp_init,
-        .init_late      = omap3430_init_late,
-        .init_time      = omap3_sync32k_timer_init,
-        .restart        = omap3xxx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 212c3160de18..8168ddabaeda 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -24,6 +24,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/omap-gpmc.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index c6df8eec4553..91738a14ecbe 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -25,6 +25,7 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
+#include <linux/omap-gpmc.h>
 #include <linux/platform_data/gpio-omap.h>
 #include <linux/platform_data/at24.h>
@@ -51,8 +52,6 @@
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
-#include "gpmc.h"
-#include "gpmc-nand.h"
 #define CM_T35_GPIO_PENDOWN             57
 #define SB_T35_USB_HUB_RESET_GPIO       167
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 8a2c1677964c..794756df8529 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -28,6 +28,7 @@
 #include <linux/delay.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
+#include <linux/omap-gpmc.h>
 #include <linux/rtc-v3020.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
@@ -41,7 +42,6 @@
 #include "common.h"
 #include <linux/platform_data/mtd-nand-omap2.h>
-#include "gpmc.h"
 #include "am35xx.h"
@@ -50,7 +50,6 @@
 #include "hsmmc.h"
 #include "common-board-devices.h"
 #include "am35xx-emac.h"
-#include "gpmc-nand.h"
 #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
 static struct gpio_led cm_t3517_leds[] = {
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index 2d245c2e641c..70b21cc279ba 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -13,6 +13,7 @@
 */
 #include <linux/kernel.h>
+#include <linux/omap-gpmc.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
 #include <linux/io.h>
@@ -23,8 +24,6 @@
 #include "soc.h"
 #include "common.h"
 #include "board-flash.h"
-#include "gpmc-onenand.h"
-#include "gpmc-nand.h"
 #define REG_FPGA_REV                    0x10
 #define REG_FPGA_DIP_SWITCH_INPUT2      0x60
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index 2fb5d41a9fae..ea9aaebe11e7 100644
--- a/arch/arm/mach-omap2/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -12,7 +12,6 @@
 */
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
-#include "gpmc.h"
 #define PDC_NOR         1
 #define PDC_NAND        2
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 97767a27ca9d..b6443a4e0c78 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -21,8 +21,9 @@
 #include <linux/i2c.h>
 #include <linux/spi/spi.h>
 #include <linux/usb/musb.h>
+#include <linux/mmc/host.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
-#include <linux/platform_data/mtd-onenand-omap2.h>
+#include <linux/platform_data/mmc-omap.h>
 #include <linux/mfd/menelaus.h>
 #include <sound/tlv320aic3x.h>
@@ -32,7 +33,6 @@
 #include "common.h"
 #include "mmc.h"
 #include "soc.h"
-#include "gpmc-onenand.h"
 #include "common-board-devices.h"
 #define TUSB6010_ASYNC_CS       1
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index f32201656cf3..7f1708738c30 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -24,6 +24,7 @@
 #include <linux/spi/spi.h>
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
+#include <linux/omap-gpmc.h>
 #include <linux/wl12xx.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
@@ -51,7 +52,6 @@
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
-#include "gpmc-nand.h"
 #define PANDORA_WIFI_IRQ_GPIO           21
 #define PANDORA_WIFI_NRESET_GPIO        23
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index ddfc8df83c6a..14edcd7a2a1d 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -23,6 +23,8 @@
 #include <linux/regulator/machine.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
+#include <linux/gpio/machine.h>
+#include <linux/omap-gpmc.h>
 #include <linux/mmc/host.h>
 #include <linux/power/isp1704_charger.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
@@ -32,13 +34,11 @@
 #include "common.h"
 #include <linux/omap-dma.h>
-#include "gpmc-smc91x.h"
 #include "board-rx51.h"
 #include <sound/tlv320aic3x.h>
 #include <sound/tpa6130a2-plat.h>
-#include <media/radio-si4713.h>
 #include <media/si4713.h>
 #include <linux/platform_data/leds-lp55xx.h>
@@ -55,8 +55,6 @@
 #include "omap-pm.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
-#include "gpmc.h"
-#include "gpmc-onenand.h"
 #include "soc.h"
 #include "omap-secure.h"
@@ -484,7 +482,7 @@ static struct omap_mux_partition *partition;
 * Current flows to eMMC when eMMC is off and the data lines are pulled up,
 * so pull them down. N.B. we pull 8 lines because we are using 8 lines.
 */
-static void rx51_mmc2_remux(struct device *dev, int slot, int power_on)
+static void rx51_mmc2_remux(struct device *dev, int power_on)
 {
        if (power_on)
                omap_mux_write_array(partition, rx51_mmc2_on_mux);
@@ -500,7 +498,6 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
                .cover_only     = true,
                .gpio_cd        = 160,
                .gpio_wp        = -EINVAL,
-                .power_saving   = true,
        },
        {
                .name           = "internal",
@@ -510,7 +507,6 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
                .gpio_cd        = -EINVAL,
                .gpio_wp        = -EINVAL,
                .nonremovable   = true,
-                .power_saving   = true,
                .remux          = rx51_mmc2_remux,
        },
        {}      /* Terminator */
@@ -760,46 +756,17 @@ static struct regulator_init_data rx51_vintdig = {
        },
 };
-static const char * const si4713_supply_names[] = {
+static struct gpiod_lookup_table rx51_fmtx_gpios_table = {
-        "vio",
+        .dev_id = "2-0063",
-        "vdd",
+        .table = {
-};
+                GPIO_LOOKUP("gpio.6", 3, "reset", GPIO_ACTIVE_HIGH), /* 163 */
+                { },
-static struct si4713_platform_data rx51_si4713_i2c_data __initdata_or_module = {
-        .supplies       = ARRAY_SIZE(si4713_supply_names),
-        .supply_names   = si4713_supply_names,
-        .gpio_reset     = RX51_FMTX_RESET_GPIO,
-};
-static struct i2c_board_info rx51_si4713_board_info __initdata_or_module = {
-        I2C_BOARD_INFO("si4713", SI4713_I2C_ADDR_BUSEN_HIGH),
-        .platform_data  = &rx51_si4713_i2c_data,
-};
-static struct radio_si4713_platform_data rx51_si4713_data __initdata_or_module = {
-        .i2c_bus        = 2,
-        .subdev_board_info = &rx51_si4713_board_info,
-};
-static struct platform_device rx51_si4713_dev __initdata_or_module = {
-        .name   = "radio-si4713",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &rx51_si4713_data,
        },
 };
-static __init void rx51_init_si4713(void)
+static __init void rx51_gpio_init(void)
 {
-        int err;
+        gpiod_add_lookup_table(&rx51_fmtx_gpios_table);
-        err = gpio_request_one(RX51_FMTX_IRQ, GPIOF_DIR_IN, "si4713 irq");
-        if (err) {
-                printk(KERN_ERR "Cannot request si4713 irq gpio. %d\n", err);
-                return;
-        }
-        rx51_si4713_board_info.irq = gpio_to_irq(RX51_FMTX_IRQ);
-        platform_device_register(&rx51_si4713_dev);
 }
 static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n)
@@ -1029,7 +996,19 @@ static struct aic3x_pdata rx51_aic3x_data2 = {
        .gpio_reset = 60,
 };
+#if IS_ENABLED(CONFIG_I2C_SI4713) && IS_ENABLED(CONFIG_PLATFORM_SI4713)
+static struct si4713_platform_data rx51_si4713_platform_data = {
+        .is_platform_device = true
+};
+#endif
 static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = {
+#if IS_ENABLED(CONFIG_I2C_SI4713) && IS_ENABLED(CONFIG_PLATFORM_SI4713)
+        {
+                I2C_BOARD_INFO("si4713", 0x63),
+                .platform_data = &rx51_si4713_platform_data,
+        },
+#endif
        {
                I2C_BOARD_INFO("tlv320aic3x", 0x18),
                .platform_data = &rx51_aic3x_data,
@@ -1070,6 +1049,10 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_3[] = {
 static int __init rx51_i2c_init(void)
 {
+#if IS_ENABLED(CONFIG_I2C_SI4713) && IS_ENABLED(CONFIG_PLATFORM_SI4713)
+        int err;
+#endif
        if ((system_rev >= SYSTEM_REV_S_USES_VAUX3 && system_rev < 0x100) ||
            system_rev >= SYSTEM_REV_B_USES_VAUX3) {
                rx51_twldata.vaux3 = &rx51_vaux3_mmc;
@@ -1087,6 +1070,14 @@ static int __init rx51_i2c_init(void)
        rx51_twldata.vdac->constraints.name = "VDAC";
        omap_pmic_init(1, 2200, "twl5030", 7 + OMAP_INTC_START, &rx51_twldata);
+#if IS_ENABLED(CONFIG_I2C_SI4713) && IS_ENABLED(CONFIG_PLATFORM_SI4713)
+        err = gpio_request_one(RX51_FMTX_IRQ, GPIOF_DIR_IN, "si4713 irq");
+        if (err) {
+                printk(KERN_ERR "Cannot request si4713 irq gpio. %d\n", err);
+                return err;
+        }
+        rx51_peripherals_i2c_board_info_2[0].irq = gpio_to_irq(RX51_FMTX_IRQ);
+#endif
        omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
                              ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));
 #if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE)
@@ -1146,33 +1137,6 @@ static struct omap_onenand_platform_data board_onenand_data[] = {
 };
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
-static struct omap_smc91x_platform_data board_smc91x_data = {
-        .cs             = 1,
-        .gpio_irq       = 54,
-        .gpio_pwrdwn    = 86,
-        .gpio_reset     = 164,
-        .flags          = GPMC_TIMINGS_SMC91C96 | IORESOURCE_IRQ_HIGHLEVEL,
-};
-static void __init board_smc91x_init(void)
-{
-        omap_mux_init_gpio(54, OMAP_PIN_INPUT_PULLDOWN);
-        omap_mux_init_gpio(86, OMAP_PIN_OUTPUT);
-        omap_mux_init_gpio(164, OMAP_PIN_OUTPUT);
-        gpmc_smc91x_init(&board_smc91x_data);
-}
-#else
-static inline void board_smc91x_init(void)
-{
-}
-#endif
 static struct gpio rx51_wl1251_gpios[] __initdata = {
        { RX51_WL1251_IRQ_GPIO,   GPIOF_IN,             "wl1251 irq"    },
 };
@@ -1300,14 +1264,13 @@ static void __init rx51_init_omap3_rom_rng(void)
 void __init rx51_peripherals_init(void)
 {
+        rx51_gpio_init();
        rx51_i2c_init();
        regulator_has_full_constraints();
        gpmc_onenand_init(board_onenand_data);
-        board_smc91x_init();
        rx51_add_gpio_keys();
        rx51_init_wl1251();
        rx51_init_tsc2005();
-        rx51_init_si4713();
        rx51_init_lirc();
        spi_register_board_info(rx51_peripherals_spi_board_info,
                                ARRAY_SIZE(rx51_peripherals_spi_board_info));
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
deleted file mode 100644
index 6273c286e1d8..000000000000
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Code for TI8168/TI8148 EVM.
- *
- * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/usb/musb.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include "common.h"
-static struct omap_musb_board_data musb_board_data = {
-        .set_phy_power  = ti81xx_musb_phy_power,
-        .interface_type = MUSB_INTERFACE_ULPI,
-        .mode           = MUSB_OTG,
-        .power          = 500,
-};
-static void __init ti81xx_evm_init(void)
-{
-        omap_serial_init();
-        omap_sdrc_init(NULL, NULL);
-        usb_musb_init(&musb_board_data);
-}
-MACHINE_START(TI8168EVM, "ti8168evm")
-        /* Maintainer: Texas Instruments */
-        .atag_offset    = 0x100,
-        .map_io         = ti81xx_map_io,
-        .init_early     = ti81xx_init_early,
-        .init_irq       = ti81xx_init_irq,
-        .init_time      = omap3_sync32k_timer_init,
-        .init_machine   = ti81xx_evm_init,
-        .init_late      = ti81xx_init_late,
-        .restart        = omap44xx_restart,
-MACHINE_END
-MACHINE_START(TI8148EVM, "ti8148evm")
-        /* Maintainer: Texas Instruments */
-        .atag_offset    = 0x100,
-        .map_io         = ti81xx_map_io,
-        .init_early     = ti81xx_init_early,
-        .init_irq       = ti81xx_init_irq,
-        .init_time      = omap3_sync32k_timer_init,
-        .init_machine   = ti81xx_evm_init,
-        .init_late      = ti81xx_init_late,
-        .restart        = omap44xx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index eb8c75ec3b1a..5c5ebb4db5f7 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -257,6 +257,9 @@ static const struct clk_ops dpll1_ck_ops = {
        .get_parent     = &omap2_init_dpll_parent,
        .recalc_rate    = &omap3_dpll_recalc,
        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .set_parent     = &omap3_noncore_dpll_set_parent,
+        .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
+        .determine_rate = &omap3_noncore_dpll_determine_rate,
        .round_rate     = &omap2_dpll_round_rate,
 };
@@ -367,6 +370,9 @@ static const struct clk_ops dpll4_ck_ops = {
        .get_parent     = &omap2_init_dpll_parent,
        .recalc_rate    = &omap3_dpll_recalc,
        .set_rate       = &omap3_dpll4_set_rate,
+        .set_parent     = &omap3_noncore_dpll_set_parent,
+        .set_rate_and_parent    = &omap3_dpll4_set_rate_and_parent,
+        .determine_rate = &omap3_noncore_dpll_determine_rate,
        .round_rate     = &omap2_dpll_round_rate,
 };
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 500530d1364a..6ad5b4dbd33e 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -171,7 +171,8 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
                _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit),
                                     idlest_val, __clk_get_name(clk->hw.clk));
        } else {
-                cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit);
+                omap_cm_wait_module_ready(0, prcm_mod, idlest_reg_id,
+                                          idlest_bit);
        };
 }
@@ -771,4 +772,8 @@ void __init ti_clk_init_features(void)
                ti_clk_features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
        else if (cpu_is_omap34xx())
                ti_clk_features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
+        /* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */
+        if (omap_rev() == OMAP3430_REV_ES1_0)
+                ti_clk_features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM;
 }
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 4592a2762592..641337c6cde9 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -234,6 +234,7 @@ struct ti_clk_features {
 };
 #define TI_CLK_DPLL_HAS_FREQSEL         (1 << 0)
+#define TI_CLK_DPLL4_DENY_REPROGRAM     (1 << 1)
 extern struct ti_clk_features ti_clk_features;
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index 0b02b4161d71..a9e86db5daf9 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -38,6 +38,18 @@
 /* needed by omap3_core_dpll_m2_set_rate() */
 struct clk *sdrc_ick_p, *arm_fck_p;
+/**
+ * omap3_dpll4_set_rate - set rate for omap3 per-dpll
+ * @hw: clock to change
+ * @rate: target rate for clock
+ * @parent_rate: rate of the parent clock
+ *
+ * Check if the current SoC supports the per-dpll reprogram operation
+ * or not, and then do the rate change if supported. Returns -EINVAL
+ * if not supported, 0 for success, and potential error codes from the
+ * clock rate change.
+ */
 int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,
                                unsigned long parent_rate)
 {
@@ -46,7 +58,7 @@ int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,
         * on 3430ES1 prevents us from changing DPLL multipliers or dividers
         * on DPLL4.
         */
-        if (omap_rev() == OMAP3430_REV_ES1_0) {
+        if (ti_clk_features.flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
                pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
                return -EINVAL;
        }
@@ -54,6 +66,30 @@ int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,
        return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
 }
+/**
+ * omap3_dpll4_set_rate_and_parent - set rate and parent for omap3 per-dpll
+ * @hw: clock to change
+ * @rate: target rate for clock
+ * @parent_rate: rate of the parent clock
+ * @index: parent index, 0 - reference clock, 1 - bypass clock
+ *
+ * Check if the current SoC support the per-dpll reprogram operation
+ * or not, and then do the rate + parent change if supported. Returns
+ * -EINVAL if not supported, 0 for success, and potential error codes
+ * from the clock rate change.
+ */
+int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
+                                    unsigned long parent_rate, u8 index)
+{
+        if (ti_clk_features.flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
+                pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
+                return -EINVAL;
+        }
+        return omap3_noncore_dpll_set_rate_and_parent(hw, rate, parent_rate,
+                                                      index);
+}
 void __init omap3_clk_lock_dpll5(void)
 {
        struct clk *dpll5_clk;
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 93473f9a551c..6222e87a79b6 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -45,17 +45,29 @@ extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2);
 * struct cm_ll_data - fn ptrs to per-SoC CM function implementations
 * @split_idlest_reg: ptr to the SoC CM-specific split_idlest_reg impl
 * @wait_module_ready: ptr to the SoC CM-specific wait_module_ready impl
+ * @wait_module_idle: ptr to the SoC CM-specific wait_module_idle impl
+ * @module_enable: ptr to the SoC CM-specific module_enable impl
+ * @module_disable: ptr to the SoC CM-specific module_disable impl
 */
 struct cm_ll_data {
        int (*split_idlest_reg)(void __iomem *idlest_reg, s16 *prcm_inst,
                                u8 *idlest_reg_id);
-        int (*wait_module_ready)(s16 prcm_mod, u8 idlest_id, u8 idlest_shift);
+        int (*wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg,
+                                 u8 idlest_shift);
+        int (*wait_module_idle)(u8 part, s16 prcm_mod, u16 idlest_reg,
+                                u8 idlest_shift);
+        void (*module_enable)(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
+        void (*module_disable)(u8 part, u16 inst, u16 clkctrl_offs);
 };
 extern int cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst,
                               u8 *idlest_reg_id);
-extern int cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift);
+int omap_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_reg,
+                              u8 idlest_shift);
+int omap_cm_wait_module_idle(u8 part, s16 prcm_mod, u16 idlest_reg,
+                             u8 idlest_shift);
+int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
+int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs);
 extern int cm_register(struct cm_ll_data *cld);
 extern int cm_unregister(struct cm_ll_data *cld);
diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h
index 5ae8fe39d6ee..a5949927b661 100644
--- a/arch/arm/mach-omap2/cm1_44xx.h
+++ b/arch/arm/mach-omap2/cm1_44xx.h
@@ -25,8 +25,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
-#include "cm_44xx_54xx.h"
 /* CM1 base address */
 #define OMAP4430_CM1_BASE               0x4a004000
diff --git a/arch/arm/mach-omap2/cm1_54xx.h b/arch/arm/mach-omap2/cm1_54xx.h
index 90b3348e6672..fd245dfa7391 100644
--- a/arch/arm/mach-omap2/cm1_54xx.h
+++ b/arch/arm/mach-omap2/cm1_54xx.h
@@ -22,8 +22,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
-#include "cm_44xx_54xx.h"
 /* CM1 base address */
 #define OMAP54XX_CM_CORE_AON_BASE               0x4a004000
diff --git a/arch/arm/mach-omap2/cm1_7xx.h b/arch/arm/mach-omap2/cm1_7xx.h
index ca6fa1febaac..2f1c09eea021 100644
--- a/arch/arm/mach-omap2/cm1_7xx.h
+++ b/arch/arm/mach-omap2/cm1_7xx.h
@@ -23,8 +23,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
-#include "cm_44xx_54xx.h"
 /* CM1 base address */
 #define DRA7XX_CM_CORE_AON_BASE         0x4a005000
diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h
index ee5136d7cdda..7521abf3d830 100644
--- a/arch/arm/mach-omap2/cm2_44xx.h
+++ b/arch/arm/mach-omap2/cm2_44xx.h
@@ -25,8 +25,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
-#include "cm_44xx_54xx.h"
 /* CM2 base address */
 #define OMAP4430_CM2_BASE               0x4a008000
diff --git a/arch/arm/mach-omap2/cm2_54xx.h b/arch/arm/mach-omap2/cm2_54xx.h
index 2683231b299b..ff4040c196d8 100644
--- a/arch/arm/mach-omap2/cm2_54xx.h
+++ b/arch/arm/mach-omap2/cm2_54xx.h
@@ -21,8 +21,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM2_54XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM2_54XX_H
-#include "cm_44xx_54xx.h"
 /* CM2 base address */
 #define OMAP54XX_CM_CORE_BASE           0x4a008000
diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
index e966e3a3c931..ce63fdb68056 100644
--- a/arch/arm/mach-omap2/cm2_7xx.h
+++ b/arch/arm/mach-omap2/cm2_7xx.h
@@ -22,8 +22,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
-#include "cm_44xx_54xx.h"
 /* CM2 base address */
 #define DRA7XX_CM_CORE_BASE             0x4a008000
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index 8be6ea50c092..a96d901b1d5d 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -53,7 +53,7 @@ static void _write_clktrctrl(u8 c, s16 module, u32 mask)
        omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
 }
-bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
+static bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
 {
        u32 v;
@@ -64,12 +64,12 @@ bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
        return (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
 }
-void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
+static void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
 {
        _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
 }
-void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
+static void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
 {
        _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
 }
@@ -150,7 +150,7 @@ static int _omap2xxx_apll_enable(u8 enable_bit, u8 status_bit)
        v |= m;
        omap2_cm_write_mod_reg(v, PLL_MOD, CM_CLKEN);
-        omap2xxx_cm_wait_module_ready(PLL_MOD, 1, status_bit);
+        omap2xxx_cm_wait_module_ready(0, PLL_MOD, 1, status_bit);
        /*
         * REVISIT: Should we return an error code if
@@ -204,8 +204,9 @@ void omap2xxx_cm_apll96_disable(void)
 * XXX This function is only needed until absolute register addresses are
 * removed from the OMAP struct clk records.
 */
-int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst,
+static int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
-                                 u8 *idlest_reg_id)
+                                        s16 *prcm_inst,
+                                        u8 *idlest_reg_id)
 {
        unsigned long offs;
        u8 idlest_offs;
@@ -238,6 +239,7 @@ int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst,
 /**
 * omap2xxx_cm_wait_module_ready - wait for a module to leave idle or standby
+ * @part: PRCM partition, ignored for OMAP2
 * @prcm_mod: PRCM module offset
 * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
@@ -246,7 +248,8 @@ int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst,
 * (@prcm_mod, @idlest_id, @idlest_shift) is clocked.  Return 0 upon
 * success or -EBUSY if the module doesn't enable in time.
 */
-int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
+int omap2xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
+                                  u8 idlest_shift)
 {
        int ena = 0, i = 0;
        u8 cm_idlest_reg;
diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h
index 891d81c3c8f4..c89502b168ae 100644
--- a/arch/arm/mach-omap2/cm2xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx.h
@@ -46,9 +46,6 @@
 #ifndef __ASSEMBLER__
-extern void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
-extern void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
 extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
 extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
@@ -57,11 +54,8 @@ extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
 extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
 extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
-extern bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
+int omap2xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
-extern int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
+                                  u8 idlest_shift);
-                                         u8 idlest_shift);
-extern int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
-                                        s16 *prcm_inst, u8 *idlest_reg_id);
 extern int omap2xxx_cm_fclks_active(void);
 extern int omap2xxx_cm_mpu_retention_allowed(void);
 extern u32 omap2xxx_cm_get_core_clk_src(void);
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index b3f99e93def0..b9ad463a368a 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -96,13 +96,12 @@ static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask)
 /**
 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
 * @inst: CM instance register offset (*_INST macro)
- * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
 *
 * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
 * bit 0.
 */
-static u32 _clkctrl_idlest(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+static u32 _clkctrl_idlest(u16 inst, u16 clkctrl_offs)
 {
        u32 v = am33xx_cm_read_reg(inst, clkctrl_offs);
        v &= AM33XX_IDLEST_MASK;
@@ -113,17 +112,16 @@ static u32 _clkctrl_idlest(u16 inst, s16 cdoffs, u16 clkctrl_offs)
 /**
 * _is_module_ready - can module registers be accessed without causing an abort?
 * @inst: CM instance register offset (*_INST macro)
- * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
 *
 * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
 * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
 */
-static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+static bool _is_module_ready(u16 inst, u16 clkctrl_offs)
 {
        u32 v;
-        v = _clkctrl_idlest(inst, cdoffs, clkctrl_offs);
+        v = _clkctrl_idlest(inst, clkctrl_offs);
        return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
                v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
@@ -158,7 +156,7 @@ static void _clktrctrl_write(u8 c, u16 inst, u16 cdoffs)
 * Returns true if the clockdomain referred to by (@inst, @cdoffs)
 * is in hardware-supervised idle mode, or 0 otherwise.
 */
-bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs)
+static bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs)
 {
        u32 v;
@@ -177,7 +175,7 @@ bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs)
 * Put a clockdomain referred to by (@inst, @cdoffs) into
 * hardware-supervised idle mode.  No return value.
 */
-void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs)
+static void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs)
 {
        _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs);
 }
@@ -191,7 +189,7 @@ void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs)
 * software-supervised idle mode, i.e., controlled manually by the
 * Linux OMAP clockdomain code.  No return value.
 */
-void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs)
+static void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs)
 {
        _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs);
 }
@@ -204,7 +202,7 @@ void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs)
 * Put a clockdomain referred to by (@inst, @cdoffs) into idle
 * No return value.
 */
-void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs)
+static void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs)
 {
        _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs);
 }
@@ -217,7 +215,7 @@ void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs)
 * Take a clockdomain referred to by (@inst, @cdoffs) out of idle,
 * waking it up.  No return value.
 */
-void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs)
+static void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs)
 {
        _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs);
 }
@@ -228,20 +226,22 @@ void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs)
 /**
 * am33xx_cm_wait_module_ready - wait for a module to be in 'func' state
+ * @part: PRCM partition, ignored for AM33xx
 * @inst: CM instance register offset (*_INST macro)
- * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ * @bit_shift: bit shift for the register, ignored for AM33xx
 *
 * Wait for the module IDLEST to be functional. If the idle state is in any
 * the non functional state (trans, idle or disabled), module and thus the
 * sysconfig cannot be accessed and will probably lead to an "imprecise
 * external abort"
 */
-int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+static int am33xx_cm_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs,
+                                       u8 bit_shift)
 {
        int i = 0;
-        omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs),
+        omap_test_timeout(_is_module_ready(inst, clkctrl_offs),
                          MAX_MODULE_READY_TIME, i);
        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
@@ -250,22 +250,24 @@ int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
 /**
 * am33xx_cm_wait_module_idle - wait for a module to be in 'disabled'
 * state
+ * @part: CM partition, ignored for AM33xx
 * @inst: CM instance register offset (*_INST macro)
- * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ * @bit_shift: bit shift for the register, ignored for AM33xx
 *
 * Wait for the module IDLEST to be disabled. Some PRCM transition,
 * like reset assertion or parent clock de-activation must wait the
 * module to be fully disabled.
 */
-int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+static int am33xx_cm_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs,
+                                      u8 bit_shift)
 {
        int i = 0;
        if (!clkctrl_offs)
                return 0;
-        omap_test_timeout((_clkctrl_idlest(inst, cdoffs, clkctrl_offs) ==
+        omap_test_timeout((_clkctrl_idlest(inst, clkctrl_offs) ==
                                CLKCTRL_IDLEST_DISABLED),
                                MAX_MODULE_READY_TIME, i);
@@ -275,13 +277,14 @@ int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs)
 /**
 * am33xx_cm_module_enable - Enable the modulemode inside CLKCTRL
 * @mode: Module mode (SW or HW)
+ * @part: CM partition, ignored for AM33xx
 * @inst: CM instance register offset (*_INST macro)
- * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
 *
 * No return value.
 */
-void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs)
+static void am33xx_cm_module_enable(u8 mode, u8 part, u16 inst,
+                                    u16 clkctrl_offs)
 {
        u32 v;
@@ -293,13 +296,13 @@ void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs)
 /**
 * am33xx_cm_module_disable - Disable the module inside CLKCTRL
+ * @part: CM partition, ignored for AM33xx
 * @inst: CM instance register offset (*_INST macro)
- * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
 *
 * No return value.
 */
-void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+static void am33xx_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs)
 {
        u32 v;
@@ -362,3 +365,21 @@ struct clkdm_ops am33xx_clkdm_operations = {
        .clkdm_clk_enable       = am33xx_clkdm_clk_enable,
        .clkdm_clk_disable      = am33xx_clkdm_clk_disable,
 };
+static struct cm_ll_data am33xx_cm_ll_data = {
+        .wait_module_ready      = &am33xx_cm_wait_module_ready,
+        .wait_module_idle       = &am33xx_cm_wait_module_idle,
+        .module_enable          = &am33xx_cm_module_enable,
+        .module_disable         = &am33xx_cm_module_disable,
+};
+int __init am33xx_cm_init(void)
+{
+        return cm_register(&am33xx_cm_ll_data);
+}
+static void __exit am33xx_cm_exit(void)
+{
+        cm_unregister(&am33xx_cm_ll_data);
+}
+__exitcall(am33xx_cm_exit);
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index bd2441790779..046b4b2bc9d9 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -374,41 +374,6 @@
 #ifndef __ASSEMBLER__
-bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs);
+int am33xx_cm_init(void);
-void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs);
-void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs);
-void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs);
-void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs);
-#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
-extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
-                                        u16 clkctrl_offs);
-extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
-                                        u16 clkctrl_offs);
-extern void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
-                                        u16 clkctrl_offs);
-extern int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
-                                        u16 clkctrl_offs);
-#else
-static inline int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
-                                        u16 clkctrl_offs)
-{
-        return 0;
-}
-static inline void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
-                                        u16 clkctrl_offs)
-{
-}
-static inline void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
-                                        u16 clkctrl_offs)
-{
-}
-static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
-                                        u16 clkctrl_offs)
-{
-        return 0;
-}
-#endif
 #endif /* ASSEMBLER */
 #endif
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index 129a4e7f6ef5..ebead8f035f9 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -42,7 +42,7 @@ static void _write_clktrctrl(u8 c, s16 module, u32 mask)
        omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
 }
-bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
+static bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
 {
        u32 v;
@@ -53,22 +53,22 @@ bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
        return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
 }
-void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
+static void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
 {
        _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
 }
-void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
+static void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
 {
        _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
 }
-void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask)
+static void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask)
 {
        _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask);
 }
-void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
+static void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
 {
        _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
 }
@@ -79,6 +79,7 @@ void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
 /**
 * omap3xxx_cm_wait_module_ready - wait for a module to leave idle or standby
+ * @part: PRCM partition, ignored for OMAP3
 * @prcm_mod: PRCM module offset
 * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
@@ -87,7 +88,8 @@ void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
 * (@prcm_mod, @idlest_id, @idlest_shift) is clocked.  Return 0 upon
 * success or -EBUSY if the module doesn't enable in time.
 */
-int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
+static int omap3xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
+                                         u8 idlest_shift)
 {
        int ena = 0, i = 0;
        u8 cm_idlest_reg;
@@ -116,8 +118,9 @@ int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
 * XXX This function is only needed until absolute register addresses are
 * removed from the OMAP struct clk records.
 */
-int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst,
+static int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
-                                 u8 *idlest_reg_id)
+                                        s16 *prcm_inst,
+                                        u8 *idlest_reg_id)
 {
        unsigned long offs;
        u8 idlest_offs;
diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h
index 7a16b5598127..734a8581c0c4 100644
--- a/arch/arm/mach-omap2/cm3xxx.h
+++ b/arch/arm/mach-omap2/cm3xxx.h
@@ -68,18 +68,6 @@
 #ifndef __ASSEMBLER__
-extern void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
-extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
-extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
-extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
-extern bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
-extern int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
-                                         u8 idlest_shift);
-extern int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
-                                        s16 *prcm_inst, u8 *idlest_reg_id);
 extern void omap3_cm_save_context(void);
 extern void omap3_cm_restore_context(void);
 extern void omap3_cm_save_scratchpad_contents(u32 *ptr);
diff --git a/arch/arm/mach-omap2/cm44xx.c b/arch/arm/mach-omap2/cm44xx.c
deleted file mode 100644
index fe5cc7bae489..000000000000
--- a/arch/arm/mach-omap2/cm44xx.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * OMAP4 CM1, CM2 module low-level functions
- *
- * Copyright (C) 2010 Nokia Corporation
- * Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * These functions are intended to be used only by the cminst44xx.c file.
- * XXX Perhaps we should just move them there and make them static.
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include "cm.h"
-#include "cm1_44xx.h"
-#include "cm2_44xx.h"
-/* CM1 hardware module low-level functions */
-/* Read a register in CM1 */
-u32 omap4_cm1_read_inst_reg(s16 inst, u16 reg)
-{
-        return readl_relaxed(cm_base + inst + reg);
-}
-/* Write into a register in CM1 */
-void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 reg)
-{
-        writel_relaxed(val, cm_base + inst + reg);
-}
-/* Read a register in CM2 */
-u32 omap4_cm2_read_inst_reg(s16 inst, u16 reg)
-{
-        return readl_relaxed(cm2_base + inst + reg);
-}
-/* Write into a register in CM2 */
-void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 reg)
-{
-        writel_relaxed(val, cm2_base + inst + reg);
-}
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
index 3380beeace6e..728d06a4af19 100644
--- a/arch/arm/mach-omap2/cm44xx.h
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -23,4 +23,7 @@
 #define OMAP4_CM_CLKSTCTRL                              0x0000
 #define OMAP4_CM_STATICDEP                              0x0004
+void omap_cm_base_init(void);
+int omap4_cm_init(void);
 #endif
diff --git a/arch/arm/mach-omap2/cm_44xx_54xx.h b/arch/arm/mach-omap2/cm_44xx_54xx.h
deleted file mode 100644
index cbb211690321..000000000000
--- a/arch/arm/mach-omap2/cm_44xx_54xx.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * OMAP44xx and OMAP54xx CM1/CM2 function prototypes
- *
- * Copyright (C) 2009-2013 Texas Instruments, Inc.
- * Copyright (C) 2009-2010 Nokia Corporation
- *
- * Paul Walmsley (paul@pwsan.com)
- * Rajendra Nayak (rnayak@ti.com)
- * Benoit Cousson (b-cousson@ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#ifndef __ARCH_ARM_MACH_OMAP2_CM_44XX_54XX_H
-#define __ARCH_ARM_MACH_OMAP2_CM_44XX_55XX_H
-/* CM1 Function prototypes */
-extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
-/* CM2 Function prototypes */
-extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
-#endif
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index 8f6c4710877e..8fe02fcedc48 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -72,9 +72,10 @@ int cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst,
 }
 /**
- * cm_wait_module_ready - wait for a module to leave idle or standby
+ * omap_cm_wait_module_ready - wait for a module to leave idle or standby
+ * @part: PRCM partition
 * @prcm_mod: PRCM module offset
- * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
+ * @idlest_reg: CM_IDLESTx register
 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
 *
 * Wait for the PRCM to indicate that the module identified by
@@ -83,7 +84,8 @@ int cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst,
 * no per-SoC wait_module_ready() function pointer has been registered
 * or if the idlest register is unknown on the SoC.
 */
-int cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
+int omap_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_reg,
+                              u8 idlest_shift)
 {
        if (!cm_ll_data->wait_module_ready) {
                WARN_ONCE(1, "cm: %s: no low-level function defined\n",
@@ -91,7 +93,79 @@ int cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
                return -EINVAL;
        }
-        return cm_ll_data->wait_module_ready(prcm_mod, idlest_id, idlest_shift);
+        return cm_ll_data->wait_module_ready(part, prcm_mod, idlest_reg,
+                                             idlest_shift);
+}
+/**
+ * omap_cm_wait_module_idle - wait for a module to enter idle or standby
+ * @part: PRCM partition
+ * @prcm_mod: PRCM module offset
+ * @idlest_reg: CM_IDLESTx register
+ * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
+ *
+ * Wait for the PRCM to indicate that the module identified by
+ * (@prcm_mod, @idlest_id, @idlest_shift) is no longer clocked.  Return
+ * 0 upon success, -EBUSY if the module doesn't enable in time, or
+ * -EINVAL if no per-SoC wait_module_idle() function pointer has been
+ * registered or if the idlest register is unknown on the SoC.
+ */
+int omap_cm_wait_module_idle(u8 part, s16 prcm_mod, u16 idlest_reg,
+                             u8 idlest_shift)
+{
+        if (!cm_ll_data->wait_module_idle) {
+                WARN_ONCE(1, "cm: %s: no low-level function defined\n",
+                          __func__);
+                return -EINVAL;
+        }
+        return cm_ll_data->wait_module_idle(part, prcm_mod, idlest_reg,
+                                            idlest_shift);
+}
+/**
+ * omap_cm_module_enable - enable a module
+ * @mode: target mode for the module
+ * @part: PRCM partition
+ * @inst: PRCM instance
+ * @clkctrl_offs: CM_CLKCTRL register offset for the module
+ *
+ * Enables clocks for a module identified by (@part, @inst, @clkctrl_offs)
+ * making its IO space accessible. Return 0 upon success, -EINVAL if no
+ * per-SoC module_enable() function pointer has been registered.
+ */
+int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs)
+{
+        if (!cm_ll_data->module_enable) {
+                WARN_ONCE(1, "cm: %s: no low-level function defined\n",
+                          __func__);
+                return -EINVAL;
+        }
+        cm_ll_data->module_enable(mode, part, inst, clkctrl_offs);
+        return 0;
+}
+/**
+ * omap_cm_module_disable - disable a module
+ * @part: PRCM partition
+ * @inst: PRCM instance
+ * @clkctrl_offs: CM_CLKCTRL register offset for the module
+ *
+ * Disables clocks for a module identified by (@part, @inst, @clkctrl_offs)
+ * makings its IO space inaccessible. Return 0 upon success, -EINVAL if
+ * no per-SoC module_disable() function pointer has been registered.
+ */
+int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs)
+{
+        if (!cm_ll_data->module_disable) {
+                WARN_ONCE(1, "cm: %s: no low-level function defined\n",
+                          __func__);
+                return -EINVAL;
+        }
+        cm_ll_data->module_disable(part, inst, clkctrl_offs);
+        return 0;
 }
 /**
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 12aca56942c0..95a8cff66aff 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -26,7 +26,6 @@
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
 #include "cm44xx.h"
-#include "cminst44xx.h"
 #include "cm-regbits-34xx.h"
 #include "prcm44xx.h"
 #include "prm44xx.h"
@@ -74,17 +73,18 @@ void omap_cm_base_init(void)
 /* Private functions */
+static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx);
 /**
 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
 * @inst: CM instance register offset (*_INST macro)
- * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
 *
 * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
 * bit 0.
 */
-static u32 _clkctrl_idlest(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
+static u32 _clkctrl_idlest(u8 part, u16 inst, u16 clkctrl_offs)
 {
        u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
        v &= OMAP4430_IDLEST_MASK;
@@ -96,26 +96,23 @@ static u32 _clkctrl_idlest(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
 * _is_module_ready - can module registers be accessed without causing an abort?
 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
 * @inst: CM instance register offset (*_INST macro)
- * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
 *
 * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
 * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
 */
-static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
+static bool _is_module_ready(u8 part, u16 inst, u16 clkctrl_offs)
 {
        u32 v;
-        v = _clkctrl_idlest(part, inst, cdoffs, clkctrl_offs);
+        v = _clkctrl_idlest(part, inst, clkctrl_offs);
        return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
                v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
 }
-/* Public functions */
 /* Read a register in a CM instance */
-u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx)
+static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx)
 {
        BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
               part == OMAP4430_INVALID_PRCM_PARTITION ||
@@ -124,7 +121,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx)
 }
 /* Write into a register in a CM instance */
-void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx)
+static void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx)
 {
        BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
               part == OMAP4430_INVALID_PRCM_PARTITION ||
@@ -133,8 +130,8 @@ void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx)
 }
 /* Read-modify-write a register in CM1. Caller must lock */
-u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst,
+static u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst,
-                                   s16 idx)
+                                          s16 idx)
 {
        u32 v;
@@ -146,17 +143,18 @@ u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst,
        return v;
 }
-u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx)
+static u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx)
 {
        return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx);
 }
-u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx)
+static u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst,
+                                            s16 idx)
 {
        return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx);
 }
-u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask)
+static u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask)
 {
        u32 v;
@@ -200,7 +198,7 @@ static void _clktrctrl_write(u8 c, u8 part, u16 inst, u16 cdoffs)
 * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs)
 * is in hardware-supervised idle mode, or 0 otherwise.
 */
-bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs)
+static bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs)
 {
        u32 v;
@@ -220,7 +218,7 @@ bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs)
 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into
 * hardware-supervised idle mode.  No return value.
 */
-void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs)
+static void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs)
 {
        _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs);
 }
@@ -235,7 +233,7 @@ void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs)
 * software-supervised idle mode, i.e., controlled manually by the
 * Linux OMAP clockdomain code.  No return value.
 */
-void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs)
+static void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs)
 {
        _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs);
 }
@@ -249,7 +247,7 @@ void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs)
 * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle,
 * waking it up.  No return value.
 */
-void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs)
+static void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs)
 {
        _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs);
 }
@@ -258,7 +256,7 @@ void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs)
 *
 */
-void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs)
+static void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs)
 {
        _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs);
 }
@@ -267,23 +265,23 @@ void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs)
 * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state
 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
 * @inst: CM instance register offset (*_INST macro)
- * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ * @bit_shift: bit shift for the register, ignored for OMAP4+
 *
 * Wait for the module IDLEST to be functional. If the idle state is in any
 * the non functional state (trans, idle or disabled), module and thus the
 * sysconfig cannot be accessed and will probably lead to an "imprecise
 * external abort"
 */
-int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs,
+static int omap4_cminst_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs,
-                                   u16 clkctrl_offs)
+                                          u8 bit_shift)
 {
        int i = 0;
        if (!clkctrl_offs)
                return 0;
-        omap_test_timeout(_is_module_ready(part, inst, cdoffs, clkctrl_offs),
+        omap_test_timeout(_is_module_ready(part, inst, clkctrl_offs),
                          MAX_MODULE_READY_TIME, i);
        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
@@ -294,21 +292,22 @@ int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs,
 * state
 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
 * @inst: CM instance register offset (*_INST macro)
- * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ * @bit_shift: Bit shift for the register, ignored for OMAP4+
 *
 * Wait for the module IDLEST to be disabled. Some PRCM transition,
 * like reset assertion or parent clock de-activation must wait the
 * module to be fully disabled.
 */
-int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
+static int omap4_cminst_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs,
+                                         u8 bit_shift)
 {
        int i = 0;
        if (!clkctrl_offs)
                return 0;
-        omap_test_timeout((_clkctrl_idlest(part, inst, cdoffs, clkctrl_offs) ==
+        omap_test_timeout((_clkctrl_idlest(part, inst, clkctrl_offs) ==
                           CLKCTRL_IDLEST_DISABLED),
                          MAX_MODULE_DISABLE_TIME, i);
@@ -320,13 +319,12 @@ int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_off
 * @mode: Module mode (SW or HW)
 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
 * @inst: CM instance register offset (*_INST macro)
- * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
 *
 * No return value.
 */
-void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
+static void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst,
-                            u16 clkctrl_offs)
+                                       u16 clkctrl_offs)
 {
        u32 v;
@@ -340,13 +338,11 @@ void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
 * omap4_cminst_module_disable - Disable the module inside CLKCTRL
 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
 * @inst: CM instance register offset (*_INST macro)
- * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
 *
 * No return value.
 */
-void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
+static void omap4_cminst_module_disable(u8 part, u16 inst, u16 clkctrl_offs)
-                             u16 clkctrl_offs)
 {
        u32 v;
@@ -510,3 +506,21 @@ struct clkdm_ops am43xx_clkdm_operations = {
        .clkdm_clk_enable       = omap4_clkdm_clk_enable,
        .clkdm_clk_disable      = omap4_clkdm_clk_disable,
 };
+static struct cm_ll_data omap4xxx_cm_ll_data = {
+        .wait_module_ready      = &omap4_cminst_wait_module_ready,
+        .wait_module_idle       = &omap4_cminst_wait_module_idle,
+        .module_enable          = &omap4_cminst_module_enable,
+        .module_disable         = &omap4_cminst_module_disable,
+};
+int __init omap4_cm_init(void)
+{
+        return cm_register(&omap4xxx_cm_ll_data);
+}
+static void __exit omap4_cm_exit(void)
+{
+        cm_unregister(&omap4xxx_cm_ll_data);
+}
+__exitcall(omap4_cm_exit);
diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
deleted file mode 100644
index 7f56ea444bc4..000000000000
--- a/arch/arm/mach-omap2/cminst44xx.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * OMAP4 Clock Management (CM) function prototypes
- *
- * Copyright (C) 2010 Nokia Corporation
- * Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
-#define __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
-bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs);
-void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs);
-void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs);
-void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs);
-void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs);
-extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
-extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
-                                         u16 clkctrl_offs);
-extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
-                                       u16 clkctrl_offs);
-extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
-                                        u16 clkctrl_offs);
-/*
- * In an ideal world, we would not export these low-level functions,
- * but this will probably take some time to fix properly
- */
-u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx);
-void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx);
-u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
-                                   u16 inst, s16 idx);
-u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst,
-                                   s16 idx);
-u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst,
-                                     s16 idx);
-extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx,
-                                           u32 mask);
-extern void omap_cm_base_init(void);
-#endif
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index e18709d3b95d..aa7b379e2661 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -265,7 +265,6 @@ static struct cpuidle_driver omap3_idle_driver = {
                        .enter            = omap3_enter_idle_bm,
                        .exit_latency     = 2 + 2,
                        .target_residency = 5,
-                        .flags            = CPUIDLE_FLAG_TIME_VALID,
                        .name             = "C1",
                        .desc             = "MPU ON + CORE ON",
                },
@@ -273,7 +272,6 @@ static struct cpuidle_driver omap3_idle_driver = {
                        .enter            = omap3_enter_idle_bm,
                        .exit_latency     = 10 + 10,
                        .target_residency = 30,
-                        .flags            = CPUIDLE_FLAG_TIME_VALID,
                        .name             = "C2",
                        .desc             = "MPU ON + CORE ON",
                },
@@ -281,7 +279,6 @@ static struct cpuidle_driver omap3_idle_driver = {
                        .enter            = omap3_enter_idle_bm,
                        .exit_latency     = 50 + 50,
                        .target_residency = 300,
-                        .flags            = CPUIDLE_FLAG_TIME_VALID,
                        .name             = "C3",
                        .desc             = "MPU RET + CORE ON",
                },
@@ -289,7 +286,6 @@ static struct cpuidle_driver omap3_idle_driver = {
                        .enter            = omap3_enter_idle_bm,
                        .exit_latency     = 1500 + 1800,
                        .target_residency = 4000,
-                        .flags            = CPUIDLE_FLAG_TIME_VALID,
                        .name             = "C4",
                        .desc             = "MPU OFF + CORE ON",
                },
@@ -297,7 +293,6 @@ static struct cpuidle_driver omap3_idle_driver = {
                        .enter            = omap3_enter_idle_bm,
                        .exit_latency     = 2500 + 7500,
                        .target_residency = 12000,
-                        .flags            = CPUIDLE_FLAG_TIME_VALID,
                        .name             = "C5",
                        .desc             = "MPU RET + CORE RET",
                },
@@ -305,7 +300,6 @@ static struct cpuidle_driver omap3_idle_driver = {
                        .enter            = omap3_enter_idle_bm,
                        .exit_latency     = 3000 + 8500,
                        .target_residency = 15000,
-                        .flags            = CPUIDLE_FLAG_TIME_VALID,
                        .name             = "C6",
                        .desc             = "MPU OFF + CORE RET",
                },
@@ -313,7 +307,6 @@ static struct cpuidle_driver omap3_idle_driver = {
                        .enter            = omap3_enter_idle_bm,
                        .exit_latency     = 10000 + 30000,
                        .target_residency = 30000,
-                        .flags            = CPUIDLE_FLAG_TIME_VALID,
                        .name             = "C7",
                        .desc             = "MPU OFF + CORE OFF",
                },
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index 2498ab025fa2..01e398a868bc 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -196,7 +196,6 @@ static struct cpuidle_driver omap4_idle_driver = {
                        /* C1 - CPU0 ON + CPU1 ON + MPU ON */
                        .exit_latency = 2 + 2,
                        .target_residency = 5,
-                        .flags = CPUIDLE_FLAG_TIME_VALID,
                        .enter = omap_enter_idle_simple,
                        .name = "C1",
                        .desc = "CPUx ON, MPUSS ON"
@@ -205,7 +204,7 @@ static struct cpuidle_driver omap4_idle_driver = {
                        /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
                        .exit_latency = 328 + 440,
                        .target_residency = 960,
-                        .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
+                        .flags = CPUIDLE_FLAG_COUPLED,
                        .enter = omap_enter_idle_coupled,
                        .name = "C2",
                        .desc = "CPUx OFF, MPUSS CSWR",
@@ -214,7 +213,7 @@ static struct cpuidle_driver omap4_idle_driver = {
                        /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
                        .exit_latency = 460 + 518,
                        .target_residency = 1100,
-                        .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
+                        .flags = CPUIDLE_FLAG_COUPLED,
                        .enter = omap_enter_idle_coupled,
                        .name = "C3",
                        .desc = "CPUx OFF, MPUSS OSWR",
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 324f02bf8a51..1afb50d6d636 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -49,7 +49,7 @@ static int __init omap3_l3_init(void)
         * To avoid code running on other OMAPs in
         * multi-omap builds
         */
-        if (!(cpu_is_omap34xx()))
+        if (!(cpu_is_omap34xx()) || of_have_populated_dt())
                return -ENODEV;
        snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
@@ -67,62 +67,6 @@ static int __init omap3_l3_init(void)
 }
 omap_postcore_initcall(omap3_l3_init);
-static int __init omap4_l3_init(void)
-{
-        int i;
-        struct omap_hwmod *oh[3];
-        struct platform_device *pdev;
-        char oh_name[L3_MODULES_MAX_LEN];
-        /* If dtb is there, the devices will be created dynamically */
-        if (of_have_populated_dt())
-                return -ENODEV;
-        /*
-         * To avoid code running on other OMAPs in
-         * multi-omap builds
-         */
-        if (!cpu_is_omap44xx() && !soc_is_omap54xx())
-                return -ENODEV;
-        for (i = 0; i < L3_MODULES; i++) {
-                snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
-                oh[i] = omap_hwmod_lookup(oh_name);
-                if (!(oh[i]))
-                        pr_err("could not look up %s\n", oh_name);
-        }
-        pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL, 0);
-        WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
-        return PTR_RET(pdev);
-}
-omap_postcore_initcall(omap4_l3_init);
-#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
-static struct resource omap2cam_resources[] = {
-        {
-                .start          = OMAP24XX_CAMERA_BASE,
-                .end            = OMAP24XX_CAMERA_BASE + 0xfff,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = 24 + OMAP_INTC_START,
-                .flags          = IORESOURCE_IRQ,
-        }
-};
-static struct platform_device omap2cam_device = {
-        .name           = "omap24xxcam",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(omap2cam_resources),
-        .resource       = omap2cam_resources,
-};
-#endif
 #if defined(CONFIG_IOMMU_API)
 #include <linux/platform_data/iommu-omap.h>
@@ -245,14 +189,6 @@ int omap3_init_camera(struct isp_platform_data *pdata)
 #endif
-static inline void omap_init_camera(void)
-{
-#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
-        if (cpu_is_omap24xx())
-                platform_device_register(&omap2cam_device);
-#endif
-}
 #if defined(CONFIG_OMAP2PLUS_MBOX) || defined(CONFIG_OMAP2PLUS_MBOX_MODULE)
 static inline void __init omap_init_mbox(void)
 {
@@ -431,7 +367,6 @@ static int __init omap2_init_devices(void)
         * in alphabetical order so they're easier to sort through.
         */
        omap_init_audio();
-        omap_init_camera();
        /* If dtb is there, the devices will be created dynamically */
        if (!of_have_populated_dt()) {
                omap_init_mbox();
@@ -445,3 +380,29 @@ static int __init omap2_init_devices(void)
        return 0;
 }
 omap_arch_initcall(omap2_init_devices);
+static int __init omap_gpmc_init(void)
+{
+        struct omap_hwmod *oh;
+        struct platform_device *pdev;
+        char *oh_name = "gpmc";
+        /*
+         * if the board boots up with a populated DT, do not
+         * manually add the device from this initcall
+         */
+        if (of_have_populated_dt())
+                return -ENODEV;
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh) {
+                pr_err("Could not look up %s\n", oh_name);
+                return -ENODEV;
+        }
+        pdev = omap_device_build("omap-gpmc", -1, oh, NULL, 0);
+        WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
+        return PTR_RET(pdev);
+}
+omap_postcore_initcall(omap_gpmc_init);
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index ac3d789ac3cd..20e120d071dd 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -460,25 +460,24 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw)
 /* Non-CORE DPLL rate set code */
 /**
- * omap3_noncore_dpll_set_rate - set non-core DPLL rate
+ * omap3_noncore_dpll_determine_rate - determine rate for a DPLL
- * @clk: struct clk * of DPLL to set
+ * @hw: pointer to the clock to determine rate for
- * @rate: rounded target rate
+ * @rate: target rate for the DPLL
+ * @best_parent_rate: pointer for returning best parent rate
+ * @best_parent_clk: pointer for returning best parent clock
 *
- * Set the DPLL CLKOUT to the target rate.  If the DPLL can enter
+ * Determines which DPLL mode to use for reaching a desired target rate.
- * low-power bypass, and the target rate is the bypass source clock
+ * Checks whether the DPLL shall be in bypass or locked mode, and if
- * rate, then configure the DPLL for bypass.  Otherwise, round the
+ * locked, calculates the M,N values for the DPLL via round-rate.
- * target rate if it hasn't been done already, then program and lock
+ * Returns a positive clock rate with success, negative error value
- * the DPLL.  Returns -EINVAL upon error, or 0 upon success.
+ * in failure.
 */
-int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
+long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate,
-                                        unsigned long parent_rate)
+                                       unsigned long *best_parent_rate,
+                                       struct clk **best_parent_clk)
 {
        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
-        struct clk *new_parent = NULL;
-        unsigned long rrate;
-        u16 freqsel = 0;
        struct dpll_data *dd;
-        int ret;
        if (!hw || !rate)
                return -EINVAL;
@@ -489,61 +488,121 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
        if (__clk_get_rate(dd->clk_bypass) == rate &&
            (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
-                pr_debug("%s: %s: set rate: entering bypass.\n",
+                *best_parent_clk = dd->clk_bypass;
-                         __func__, __clk_get_name(hw->clk));
+        } else {
+                rate = omap2_dpll_round_rate(hw, rate, best_parent_rate);
+                *best_parent_clk = dd->clk_ref;
+        }
+        *best_parent_rate = rate;
+        return rate;
+}
+/**
+ * omap3_noncore_dpll_set_parent - set parent for a DPLL clock
+ * @hw: pointer to the clock to set parent for
+ * @index: parent index to select
+ *
+ * Sets parent for a DPLL clock. This sets the DPLL into bypass or
+ * locked mode. Returns 0 with success, negative error value otherwise.
+ */
+int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index)
+{
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+        int ret;
-                __clk_prepare(dd->clk_bypass);
+        if (!hw)
-                clk_enable(dd->clk_bypass);
+                return -EINVAL;
+        if (index)
                ret = _omap3_noncore_dpll_bypass(clk);
-                if (!ret)
+        else
-                        new_parent = dd->clk_bypass;
+                ret = _omap3_noncore_dpll_lock(clk);
-                clk_disable(dd->clk_bypass);
-                __clk_unprepare(dd->clk_bypass);
-        } else {
-                __clk_prepare(dd->clk_ref);
-                clk_enable(dd->clk_ref);
-                /* XXX this check is probably pointless in the CCF context */
-                if (dd->last_rounded_rate != rate) {
-                        rrate = __clk_round_rate(hw->clk, rate);
-                        if (rrate != rate) {
-                                pr_warn("%s: %s: final rate %lu does not match desired rate %lu\n",
-                                        __func__, __clk_get_name(hw->clk),
-                                        rrate, rate);
-                                rate = rrate;
-                        }
-                }
-                if (dd->last_rounded_rate == 0)
+        return ret;
-                        return -EINVAL;
+}
-                /* Freqsel is available only on OMAP343X devices */
+/**
-                if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) {
+ * omap3_noncore_dpll_set_rate - set rate for a DPLL clock
-                        freqsel = _omap3_dpll_compute_freqsel(clk,
+ * @hw: pointer to the clock to set parent for
-                                                dd->last_rounded_n);
+ * @rate: target rate for the clock
-                        WARN_ON(!freqsel);
+ * @parent_rate: rate of the parent clock
-                }
+ *
+ * Sets rate for a DPLL clock. First checks if the clock parent is
+ * reference clock (in bypass mode, the rate of the clock can't be
+ * changed) and proceeds with the rate change operation. Returns 0
+ * with success, negative error value otherwise.
+ */
+int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long parent_rate)
+{
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+        struct dpll_data *dd;
+        u16 freqsel = 0;
+        int ret;
+        if (!hw || !rate)
+                return -EINVAL;
+        dd = clk->dpll_data;
+        if (!dd)
+                return -EINVAL;
-                pr_debug("%s: %s: set rate: locking rate to %lu.\n",
+        if (__clk_get_parent(hw->clk) != dd->clk_ref)
-                         __func__, __clk_get_name(hw->clk), rate);
+                return -EINVAL;
+        if (dd->last_rounded_rate == 0)
+                return -EINVAL;
-                ret = omap3_noncore_dpll_program(clk, freqsel);
+        /* Freqsel is available only on OMAP343X devices */
-                if (!ret)
+        if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) {
-                        new_parent = dd->clk_ref;
+                freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
-                clk_disable(dd->clk_ref);
+                WARN_ON(!freqsel);
-                __clk_unprepare(dd->clk_ref);
        }
-        /*
-        * FIXME - this is all wrong.  common code handles reparenting and
-        * migrating prepare/enable counts.  dplls should be a multiplexer
-        * clock and this should be a set_parent operation so that all of that
-        * stuff is inherited for free
-        */
-        if (!ret && clk_get_parent(hw->clk) != new_parent)
+        pr_debug("%s: %s: set rate: locking rate to %lu.\n", __func__,
-                __clk_reparent(hw->clk, new_parent);
+                 __clk_get_name(hw->clk), rate);
-        return 0;
+        ret = omap3_noncore_dpll_program(clk, freqsel);
+        return ret;
+}
+/**
+ * omap3_noncore_dpll_set_rate_and_parent - set rate and parent for a DPLL clock
+ * @hw: pointer to the clock to set rate and parent for
+ * @rate: target rate for the DPLL
+ * @parent_rate: clock rate of the DPLL parent
+ * @index: new parent index for the DPLL, 0 - reference, 1 - bypass
+ *
+ * Sets rate and parent for a DPLL clock. If new parent is the bypass
+ * clock, only selects the parent. Otherwise proceeds with a rate
+ * change, as this will effectively also change the parent as the
+ * DPLL is put into locked mode. Returns 0 with success, negative error
+ * value otherwise.
+ */
+int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
+                                           unsigned long rate,
+                                           unsigned long parent_rate,
+                                           u8 index)
+{
+        int ret;
+        if (!hw || !rate)
+                return -EINVAL;
+        /*
+         * clk-ref at index[0], in which case we only need to set rate,
+         * the parent will be changed automatically with the lock sequence.
+         * With clk-bypass case we only need to change parent.
+         */
+        if (index)
+                ret = omap3_noncore_dpll_set_parent(hw, index);
+        else
+                ret = omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
+        return ret;
 }
 /* DPLL autoidle read/set code */
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index 4613f1e86988..535822fcf4bb 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -207,3 +207,44 @@ out:
        return dd->last_rounded_rate;
 }
+/**
+ * omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL
+ * @hw: pointer to the clock to determine rate for
+ * @rate: target rate for the DPLL
+ * @best_parent_rate: pointer for returning best parent rate
+ * @best_parent_clk: pointer for returning best parent clock
+ *
+ * Determines which DPLL mode to use for reaching a desired rate.
+ * Checks whether the DPLL shall be in bypass or locked mode, and if
+ * locked, calculates the M,N values for the DPLL via round-rate.
+ * Returns a positive clock rate with success, negative error value
+ * in failure.
+ */
+long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,
+                                        unsigned long *best_parent_rate,
+                                        struct clk **best_parent_clk)
+{
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+        struct dpll_data *dd;
+        if (!hw || !rate)
+                return -EINVAL;
+        dd = clk->dpll_data;
+        if (!dd)
+                return -EINVAL;
+        if (__clk_get_rate(dd->clk_bypass) == rate &&
+            (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
+                *best_parent_clk = dd->clk_bypass;
+        } else {
+                rate = omap4_dpll_regm4xen_round_rate(hw, rate,
+                                                      best_parent_rate);
+                *best_parent_clk = dd->clk_ref;
+        }
+        *best_parent_rate = rate;
+        return rate;
+}
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index cb7764314f17..d5951b17b736 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -12,14 +12,13 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/omap-gpmc.h>
 #include <linux/mtd/nand.h>
 #include <linux/platform_data/mtd-nand-omap2.h>
 #include <asm/mach/flash.h>
-#include "gpmc.h"
 #include "soc.h"
-#include "gpmc-nand.h"
 /* minimum size for IO mapping */
 #define NAND_IO_SIZE    4
diff --git a/arch/arm/mach-omap2/gpmc-nand.h b/arch/arm/mach-omap2/gpmc-nand.h
deleted file mode 100644
index d59e1281e851..000000000000
--- a/arch/arm/mach-omap2/gpmc-nand.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- *  arch/arm/mach-omap2/gpmc-nand.h
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-#ifndef __OMAP2_GPMC_NAND_H
-#define __OMAP2_GPMC_NAND_H
-#include "gpmc.h"
-#include <linux/platform_data/mtd-nand-omap2.h>
-#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
-extern int gpmc_nand_init(struct omap_nand_platform_data *d,
-                          struct gpmc_timings *gpmc_t);
-#else
-static inline int gpmc_nand_init(struct omap_nand_platform_data *d,
-                                 struct gpmc_timings *gpmc_t)
-{
-        return 0;
-}
-#endif
-#endif
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 8b6876c98ce1..53d197e0c1f3 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -15,14 +15,13 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/onenand_regs.h>
 #include <linux/io.h>
+#include <linux/omap-gpmc.h>
 #include <linux/platform_data/mtd-onenand-omap2.h>
 #include <linux/err.h>
 #include <asm/mach/flash.h>
-#include "gpmc.h"
 #include "soc.h"
-#include "gpmc-onenand.h"
 #define ONENAND_IO_SIZE SZ_128K
diff --git a/arch/arm/mach-omap2/gpmc-onenand.h b/arch/arm/mach-omap2/gpmc-onenand.h
deleted file mode 100644
index 216f23a8b45c..000000000000
--- a/arch/arm/mach-omap2/gpmc-onenand.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- *  arch/arm/mach-omap2/gpmc-onenand.h
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-#ifndef __OMAP2_GPMC_ONENAND_H
-#define __OMAP2_GPMC_ONENAND_H
-#include <linux/platform_data/mtd-onenand-omap2.h>
-#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
-extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
-#else
-#define board_onenand_data      NULL
-static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
-{
-}
-#endif
-#endif
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
deleted file mode 100644
index 61a063595e66..000000000000
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/gpmc-smc91x.c
- *
- * Copyright (C) 2009 Nokia Corporation
- * Contact:     Tony Lindgren
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/smc91x.h>
-#include "gpmc.h"
-#include "gpmc-smc91x.h"
-#include "soc.h"
-static struct omap_smc91x_platform_data *gpmc_cfg;
-static struct resource gpmc_smc91x_resources[] = {
-        [0] = {
-                .flags          = IORESOURCE_MEM,
-        },
-        [1] = {
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-static struct smc91x_platdata gpmc_smc91x_info = {
-        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_IO_SHIFT_0,
-        .leda   = RPC_LED_100_10,
-        .ledb   = RPC_LED_TX_RX,
-};
-static struct platform_device gpmc_smc91x_device = {
-        .name           = "smc91x",
-        .id             = -1,
-        .dev            = {
-                .platform_data = &gpmc_smc91x_info,
-        },
-        .num_resources  = ARRAY_SIZE(gpmc_smc91x_resources),
-        .resource       = gpmc_smc91x_resources,
-};
-static struct gpmc_settings smc91x_settings = {
-        .device_width = GPMC_DEVWIDTH_16BIT,
-};
-/*
- * Set the gpmc timings for smc91c96. The timings are taken
- * from the data sheet available at:
- * http://www.smsc.com/main/catalog/lan91c96.html
- * REVISIT: Level shifters can add at least to the access latency.
- */
-static int smc91c96_gpmc_retime(void)
-{
-        struct gpmc_timings t;
-        struct gpmc_device_timings dev_t;
-        const int t3 = 10;      /* Figure 12.2 read and 12.4 write */
-        const int t4_r = 20;    /* Figure 12.2 read */
-        const int t4_w = 5;     /* Figure 12.4 write */
-        const int t5 = 25;      /* Figure 12.2 read */
-        const int t6 = 15;      /* Figure 12.2 read */
-        const int t7 = 5;       /* Figure 12.4 write */
-        const int t8 = 5;       /* Figure 12.4 write */
-        const int t20 = 185;    /* Figure 12.2 read and 12.4 write */
-        /*
-         * FIXME: Calculate the address and data bus muxed timings.
-         * Note that at least adv_rd_off needs to be changed according
-         * to omap3430 TRM Figure 11-11. Are the sdp boards using the
-         * FPGA in between smc91x and omap as the timings are different
-         * from above?
-         */
-        if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
-                return 0;
-        memset(&dev_t, 0, sizeof(dev_t));
-        dev_t.t_oeasu = t3 * 1000;
-        dev_t.t_oe = t5 * 1000;
-        dev_t.t_cez_r = t4_r * 1000;
-        dev_t.t_oez = t6 * 1000;
-        dev_t.t_rd_cycle = (t20 - t3) * 1000;
-        dev_t.t_weasu = t3 * 1000;
-        dev_t.t_wpl = t7 * 1000;
-        dev_t.t_wph = t8 * 1000;
-        dev_t.t_cez_w = t4_w * 1000;
-        dev_t.t_wr_cycle = (t20 - t3) * 1000;
-        gpmc_calc_timings(&t, &smc91x_settings, &dev_t);
-        return gpmc_cs_set_timings(gpmc_cfg->cs, &t);
-}
-/*
- * Initialize smc91x device connected to the GPMC. Note that we
- * assume that pin multiplexing is done in the board-*.c file,
- * or in the bootloader.
- */
-void __init gpmc_smc91x_init(struct omap_smc91x_platform_data *board_data)
-{
-        unsigned long cs_mem_base;
-        int ret;
-        gpmc_cfg = board_data;
-        if (gpmc_cfg->flags & GPMC_TIMINGS_SMC91C96)
-                gpmc_cfg->retime = smc91c96_gpmc_retime;
-        if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
-                printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
-                return;
-        }
-        gpmc_smc91x_resources[0].start = cs_mem_base + 0x300;
-        gpmc_smc91x_resources[0].end = cs_mem_base + 0x30f;
-        gpmc_smc91x_resources[1].flags |= (gpmc_cfg->flags & IRQF_TRIGGER_MASK);
-        if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
-                smc91x_settings.mux_add_data = GPMC_MUX_AD;
-        if (gpmc_cfg->flags & GPMC_READ_MON)
-                smc91x_settings.wait_on_read = true;
-        if (gpmc_cfg->flags & GPMC_WRITE_MON)
-                smc91x_settings.wait_on_write = true;
-        if (gpmc_cfg->wait_pin)
-                smc91x_settings.wait_pin = gpmc_cfg->wait_pin;
-        ret = gpmc_cs_program_settings(gpmc_cfg->cs, &smc91x_settings);
-        if (ret < 0)
-                goto free1;
-        if (gpmc_cfg->retime) {
-                ret = gpmc_cfg->retime();
-                if (ret != 0)
-                        goto free1;
-        }
-        if (gpio_request_one(gpmc_cfg->gpio_irq, GPIOF_IN, "SMC91X irq") < 0)
-                goto free1;
-        gpmc_smc91x_resources[1].start = gpio_to_irq(gpmc_cfg->gpio_irq);
-        if (gpmc_cfg->gpio_pwrdwn) {
-                ret = gpio_request_one(gpmc_cfg->gpio_pwrdwn,
-                                       GPIOF_OUT_INIT_LOW, "SMC91X powerdown");
-                if (ret)
-                        goto free2;
-        }
-        if (gpmc_cfg->gpio_reset) {
-                ret = gpio_request_one(gpmc_cfg->gpio_reset,
-                                       GPIOF_OUT_INIT_LOW, "SMC91X reset");
-                if (ret)
-                        goto free3;
-                gpio_set_value(gpmc_cfg->gpio_reset, 1);
-                msleep(100);
-                gpio_set_value(gpmc_cfg->gpio_reset, 0);
-        }
-        if (platform_device_register(&gpmc_smc91x_device) < 0) {
-                printk(KERN_ERR "Unable to register smc91x device\n");
-                gpio_free(gpmc_cfg->gpio_reset);
-                goto free3;
-        }
-        return;
-free3:
-        if (gpmc_cfg->gpio_pwrdwn)
-                gpio_free(gpmc_cfg->gpio_pwrdwn);
-free2:
-        gpio_free(gpmc_cfg->gpio_irq);
-free1:
-        gpmc_cs_free(gpmc_cfg->cs);
-        printk(KERN_ERR "Could not initialize smc91x\n");
-}
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.h b/arch/arm/mach-omap2/gpmc-smc91x.h
deleted file mode 100644
index b64fbee4d567..000000000000
--- a/arch/arm/mach-omap2/gpmc-smc91x.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/gpmc-smc91x.h
- *
- * Copyright (C) 2009 Nokia Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_OMAP_GPMC_SMC91X_H__
-#define GPMC_TIMINGS_SMC91C96   (1 << 4)
-#define GPMC_MUX_ADD_DATA       (1 << 5) /* GPMC_CONFIG1_MUXADDDATA */
-#define GPMC_READ_MON           (1 << 6) /* GPMC_CONFIG1_WAIT_READ_MON */
-#define GPMC_WRITE_MON          (1 << 7) /* GPMC_CONFIG1_WAIT_WRITE_MON */
-struct omap_smc91x_platform_data {
-        int     cs;
-        int     gpio_irq;
-        int     gpio_pwrdwn;
-        int     gpio_reset;
-        int     wait_pin;       /* Optional GPMC_CONFIG1_WAITPINSELECT */
-        u32     flags;
-        int     (*retime)(void);
-};
-#if defined(CONFIG_SMC91X) || \
-        defined(CONFIG_SMC91X_MODULE)
-extern void gpmc_smc91x_init(struct omap_smc91x_platform_data *d);
-#else
-#define board_smc91x_data       NULL
-static inline void gpmc_smc91x_init(struct omap_smc91x_platform_data *d)
-{
-}
-#endif
-#endif
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
deleted file mode 100644
index 5fa3755261ce..000000000000
--- a/arch/arm/mach-omap2/gpmc.c
+++ /dev/null
@@ -1,1891 +0,0 @@
-/*
- * GPMC support functions
- *
- * Copyright (C) 2005-2006 Nokia Corporation
- *
- * Author: Juha Yrjola
- *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#undef DEBUG
-#include <linux/irq.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/ioport.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_mtd.h>
-#include <linux/of_device.h>
-#include <linux/mtd/nand.h>
-#include <linux/pm_runtime.h>
-#include <linux/platform_data/mtd-nand-omap2.h>
-#include <asm/mach-types.h>
-#include "soc.h"
-#include "common.h"
-#include "omap_device.h"
-#include "gpmc.h"
-#include "gpmc-nand.h"
-#include "gpmc-onenand.h"
-#define DEVICE_NAME             "omap-gpmc"
-/* GPMC register offsets */
-#define GPMC_REVISION           0x00
-#define GPMC_SYSCONFIG          0x10
-#define GPMC_SYSSTATUS          0x14
-#define GPMC_IRQSTATUS          0x18
-#define GPMC_IRQENABLE          0x1c
-#define GPMC_TIMEOUT_CONTROL    0x40
-#define GPMC_ERR_ADDRESS        0x44
-#define GPMC_ERR_TYPE           0x48
-#define GPMC_CONFIG             0x50
-#define GPMC_STATUS             0x54
-#define GPMC_PREFETCH_CONFIG1   0x1e0
-#define GPMC_PREFETCH_CONFIG2   0x1e4
-#define GPMC_PREFETCH_CONTROL   0x1ec
-#define GPMC_PREFETCH_STATUS    0x1f0
-#define GPMC_ECC_CONFIG         0x1f4
-#define GPMC_ECC_CONTROL        0x1f8
-#define GPMC_ECC_SIZE_CONFIG    0x1fc
-#define GPMC_ECC1_RESULT        0x200
-#define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
-#define GPMC_ECC_BCH_RESULT_1   0x244   /* not available on OMAP2 */
-#define GPMC_ECC_BCH_RESULT_2   0x248   /* not available on OMAP2 */
-#define GPMC_ECC_BCH_RESULT_3   0x24c   /* not available on OMAP2 */
-#define GPMC_ECC_BCH_RESULT_4   0x300   /* not available on OMAP2 */
-#define GPMC_ECC_BCH_RESULT_5   0x304   /* not available on OMAP2 */
-#define GPMC_ECC_BCH_RESULT_6   0x308   /* not available on OMAP2 */
-/* GPMC ECC control settings */
-#define GPMC_ECC_CTRL_ECCCLEAR          0x100
-#define GPMC_ECC_CTRL_ECCDISABLE        0x000
-#define GPMC_ECC_CTRL_ECCREG1           0x001
-#define GPMC_ECC_CTRL_ECCREG2           0x002
-#define GPMC_ECC_CTRL_ECCREG3           0x003
-#define GPMC_ECC_CTRL_ECCREG4           0x004
-#define GPMC_ECC_CTRL_ECCREG5           0x005
-#define GPMC_ECC_CTRL_ECCREG6           0x006
-#define GPMC_ECC_CTRL_ECCREG7           0x007
-#define GPMC_ECC_CTRL_ECCREG8           0x008
-#define GPMC_ECC_CTRL_ECCREG9           0x009
-#define GPMC_CONFIG2_CSEXTRADELAY               BIT(7)
-#define GPMC_CONFIG3_ADVEXTRADELAY              BIT(7)
-#define GPMC_CONFIG4_OEEXTRADELAY               BIT(7)
-#define GPMC_CONFIG4_WEEXTRADELAY               BIT(23)
-#define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN        BIT(6)
-#define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN        BIT(7)
-#define GPMC_CS0_OFFSET         0x60
-#define GPMC_CS_SIZE            0x30
-#define GPMC_BCH_SIZE           0x10
-#define GPMC_MEM_END            0x3FFFFFFF
-#define GPMC_CHUNK_SHIFT        24              /* 16 MB */
-#define GPMC_SECTION_SHIFT      28              /* 128 MB */
-#define CS_NUM_SHIFT            24
-#define ENABLE_PREFETCH         (0x1 << 7)
-#define DMA_MPU_MODE            2
-#define GPMC_REVISION_MAJOR(l)          ((l >> 4) & 0xf)
-#define GPMC_REVISION_MINOR(l)          (l & 0xf)
-#define GPMC_HAS_WR_ACCESS              0x1
-#define GPMC_HAS_WR_DATA_MUX_BUS        0x2
-#define GPMC_HAS_MUX_AAD                0x4
-#define GPMC_NR_WAITPINS                4
-/* XXX: Only NAND irq has been considered,currently these are the only ones used
- */
-#define GPMC_NR_IRQ             2
-struct gpmc_client_irq  {
-        unsigned                irq;
-        u32                     bitmask;
-};
-/* Structure to save gpmc cs context */
-struct gpmc_cs_config {
-        u32 config1;
-        u32 config2;
-        u32 config3;
-        u32 config4;
-        u32 config5;
-        u32 config6;
-        u32 config7;
-        int is_valid;
-};
-/*
- * Structure to save/restore gpmc context
- * to support core off on OMAP3
- */
-struct omap3_gpmc_regs {
-        u32 sysconfig;
-        u32 irqenable;
-        u32 timeout_ctrl;
-        u32 config;
-        u32 prefetch_config1;
-        u32 prefetch_config2;
-        u32 prefetch_control;
-        struct gpmc_cs_config cs_context[GPMC_CS_NUM];
-};
-static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
-static struct irq_chip gpmc_irq_chip;
-static int gpmc_irq_start;
-static struct resource  gpmc_mem_root;
-static struct resource  gpmc_cs_mem[GPMC_CS_NUM];
-static DEFINE_SPINLOCK(gpmc_mem_lock);
-/* Define chip-selects as reserved by default until probe completes */
-static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
-static unsigned int gpmc_cs_num = GPMC_CS_NUM;
-static unsigned int gpmc_nr_waitpins;
-static struct device *gpmc_dev;
-static int gpmc_irq;
-static resource_size_t phys_base, mem_size;
-static unsigned gpmc_capability;
-static void __iomem *gpmc_base;
-static struct clk *gpmc_l3_clk;
-static irqreturn_t gpmc_handle_irq(int irq, void *dev);
-static void gpmc_write_reg(int idx, u32 val)
-{
-        writel_relaxed(val, gpmc_base + idx);
-}
-static u32 gpmc_read_reg(int idx)
-{
-        return readl_relaxed(gpmc_base + idx);
-}
-void gpmc_cs_write_reg(int cs, int idx, u32 val)
-{
-        void __iomem *reg_addr;
-        reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
-        writel_relaxed(val, reg_addr);
-}
-static u32 gpmc_cs_read_reg(int cs, int idx)
-{
-        void __iomem *reg_addr;
-        reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
-        return readl_relaxed(reg_addr);
-}
-/* TODO: Add support for gpmc_fck to clock framework and use it */
-static unsigned long gpmc_get_fclk_period(void)
-{
-        unsigned long rate = clk_get_rate(gpmc_l3_clk);
-        if (rate == 0) {
-                printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
-                return 0;
-        }
-        rate /= 1000;
-        rate = 1000000000 / rate;       /* In picoseconds */
-        return rate;
-}
-static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
-{
-        unsigned long tick_ps;
-        /* Calculate in picosecs to yield more exact results */
-        tick_ps = gpmc_get_fclk_period();
-        return (time_ns * 1000 + tick_ps - 1) / tick_ps;
-}
-static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
-{
-        unsigned long tick_ps;
-        /* Calculate in picosecs to yield more exact results */
-        tick_ps = gpmc_get_fclk_period();
-        return (time_ps + tick_ps - 1) / tick_ps;
-}
-unsigned int gpmc_ticks_to_ns(unsigned int ticks)
-{
-        return ticks * gpmc_get_fclk_period() / 1000;
-}
-static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
-{
-        return ticks * gpmc_get_fclk_period();
-}
-static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
-{
-        unsigned long ticks = gpmc_ps_to_ticks(time_ps);
-        return ticks * gpmc_get_fclk_period();
-}
-static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
-{
-        u32 l;
-        l = gpmc_cs_read_reg(cs, reg);
-        if (value)
-                l |= mask;
-        else
-                l &= ~mask;
-        gpmc_cs_write_reg(cs, reg, l);
-}
-static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
-{
-        gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
-                           GPMC_CONFIG1_TIME_PARA_GRAN,
-                           p->time_para_granularity);
-        gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
-                           GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
-        gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
-                           GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
-        gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
-                           GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
-        gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
-                           GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
-        gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
-                           GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
-                           p->cycle2cyclesamecsen);
-        gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
-                           GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
-                           p->cycle2cyclediffcsen);
-}
-#ifdef DEBUG
-static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
-                               int time, const char *name)
-#else
-static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
-                               int time)
-#endif
-{
-        u32 l;
-        int ticks, mask, nr_bits;
-        if (time == 0)
-                ticks = 0;
-        else
-                ticks = gpmc_ns_to_ticks(time);
-        nr_bits = end_bit - st_bit + 1;
-        if (ticks >= 1 << nr_bits) {
-#ifdef DEBUG
-                printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
-                                cs, name, time, ticks, 1 << nr_bits);
-#endif
-                return -1;
-        }
-        mask = (1 << nr_bits) - 1;
-        l = gpmc_cs_read_reg(cs, reg);
-#ifdef DEBUG
-        printk(KERN_INFO
-                "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
-               cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
-                        (l >> st_bit) & mask, time);
-#endif
-        l &= ~(mask << st_bit);
-        l |= ticks << st_bit;
-        gpmc_cs_write_reg(cs, reg, l);
-        return 0;
-}
-#ifdef DEBUG
-#define GPMC_SET_ONE(reg, st, end, field) \
-        if (set_gpmc_timing_reg(cs, (reg), (st), (end),         \
-                        t->field, #field) < 0)                  \
-                return -1
-#else
-#define GPMC_SET_ONE(reg, st, end, field) \
-        if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
-                return -1
-#endif
-int gpmc_calc_divider(unsigned int sync_clk)
-{
-        int div;
-        u32 l;
-        l = sync_clk + (gpmc_get_fclk_period() - 1);
-        div = l / gpmc_get_fclk_period();
-        if (div > 4)
-                return -1;
-        if (div <= 0)
-                div = 1;
-        return div;
-}
-int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
-{
-        int div;
-        u32 l;
-        div = gpmc_calc_divider(t->sync_clk);
-        if (div < 0)
-                return div;
-        GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
-        GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
-        GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
-        GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
-        GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
-        GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
-        GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
-        GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
-        GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
-        GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
-        GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
-        GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
-        GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
-        GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
-        GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
-        GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
-        GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring);
-        GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation);
-        if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
-                GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
-        if (gpmc_capability & GPMC_HAS_WR_ACCESS)
-                GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
-        /* caller is expected to have initialized CONFIG1 to cover
-         * at least sync vs async
-         */
-        l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-        if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
-#ifdef DEBUG
-                printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
-                                cs, (div * gpmc_get_fclk_period()) / 1000, div);
-#endif
-                l &= ~0x03;
-                l |= (div - 1);
-                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
-        }
-        gpmc_cs_bool_timings(cs, &t->bool_timings);
-        return 0;
-}
-static int gpmc_cs_enable_mem(int cs, u32 base, u32 size)
-{
-        u32 l;
-        u32 mask;
-        /*
-         * Ensure that base address is aligned on a
-         * boundary equal to or greater than size.
-         */
-        if (base & (size - 1))
-                return -EINVAL;
-        mask = (1 << GPMC_SECTION_SHIFT) - size;
-        l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
-        l &= ~0x3f;
-        l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
-        l &= ~(0x0f << 8);
-        l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
-        l |= GPMC_CONFIG7_CSVALID;
-        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
-        return 0;
-}
-static void gpmc_cs_disable_mem(int cs)
-{
-        u32 l;
-        l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
-        l &= ~GPMC_CONFIG7_CSVALID;
-        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
-}
-static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
-{
-        u32 l;
-        u32 mask;
-        l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
-        *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
-        mask = (l >> 8) & 0x0f;
-        *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
-}
-static int gpmc_cs_mem_enabled(int cs)
-{
-        u32 l;
-        l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
-        return l & GPMC_CONFIG7_CSVALID;
-}
-static void gpmc_cs_set_reserved(int cs, int reserved)
-{
-        gpmc_cs_map &= ~(1 << cs);
-        gpmc_cs_map |= (reserved ? 1 : 0) << cs;
-}
-static bool gpmc_cs_reserved(int cs)
-{
-        return gpmc_cs_map & (1 << cs);
-}
-static unsigned long gpmc_mem_align(unsigned long size)
-{
-        int order;
-        size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
-        order = GPMC_CHUNK_SHIFT - 1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-        size = 1 << order;
-        return size;
-}
-static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
-{
-        struct resource *res = &gpmc_cs_mem[cs];
-        int r;
-        size = gpmc_mem_align(size);
-        spin_lock(&gpmc_mem_lock);
-        res->start = base;
-        res->end = base + size - 1;
-        r = request_resource(&gpmc_mem_root, res);
-        spin_unlock(&gpmc_mem_lock);
-        return r;
-}
-static int gpmc_cs_delete_mem(int cs)
-{
-        struct resource *res = &gpmc_cs_mem[cs];
-        int r;
-        spin_lock(&gpmc_mem_lock);
-        r = release_resource(res);
-        res->start = 0;
-        res->end = 0;
-        spin_unlock(&gpmc_mem_lock);
-        return r;
-}
-/**
- * gpmc_cs_remap - remaps a chip-select physical base address
- * @cs:         chip-select to remap
- * @base:       physical base address to re-map chip-select to
- *
- * Re-maps a chip-select to a new physical base address specified by
- * "base". Returns 0 on success and appropriate negative error code
- * on failure.
- */
-static int gpmc_cs_remap(int cs, u32 base)
-{
-        int ret;
-        u32 old_base, size;
-        if (cs > gpmc_cs_num) {
-                pr_err("%s: requested chip-select is disabled\n", __func__);
-                return -ENODEV;
-        }
-        /*
-         * Make sure we ignore any device offsets from the GPMC partition
-         * allocated for the chip select and that the new base confirms
-         * to the GPMC 16MB minimum granularity.
-         */ 
-        base &= ~(SZ_16M - 1);
-        gpmc_cs_get_memconf(cs, &old_base, &size);
-        if (base == old_base)
-                return 0;
-        gpmc_cs_disable_mem(cs);
-        ret = gpmc_cs_delete_mem(cs);
-        if (ret < 0)
-                return ret;
-        ret = gpmc_cs_insert_mem(cs, base, size);
-        if (ret < 0)
-                return ret;
-        ret = gpmc_cs_enable_mem(cs, base, size);
-        if (ret < 0)
-                return ret;
-        return 0;
-}
-int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
-{
-        struct resource *res = &gpmc_cs_mem[cs];
-        int r = -1;
-        if (cs > gpmc_cs_num) {
-                pr_err("%s: requested chip-select is disabled\n", __func__);
-                return -ENODEV;
-        }
-        size = gpmc_mem_align(size);
-        if (size > (1 << GPMC_SECTION_SHIFT))
-                return -ENOMEM;
-        spin_lock(&gpmc_mem_lock);
-        if (gpmc_cs_reserved(cs)) {
-                r = -EBUSY;
-                goto out;
-        }
-        if (gpmc_cs_mem_enabled(cs))
-                r = adjust_resource(res, res->start & ~(size - 1), size);
-        if (r < 0)
-                r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
-                                      size, NULL, NULL);
-        if (r < 0)
-                goto out;
-        r = gpmc_cs_enable_mem(cs, res->start, resource_size(res));
-        if (r < 0) {
-                release_resource(res);
-                goto out;
-        }
-        *base = res->start;
-        gpmc_cs_set_reserved(cs, 1);
-out:
-        spin_unlock(&gpmc_mem_lock);
-        return r;
-}
-EXPORT_SYMBOL(gpmc_cs_request);
-void gpmc_cs_free(int cs)
-{
-        struct resource *res = &gpmc_cs_mem[cs];
-        spin_lock(&gpmc_mem_lock);
-        if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
-                printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
-                BUG();
-                spin_unlock(&gpmc_mem_lock);
-                return;
-        }
-        gpmc_cs_disable_mem(cs);
-        if (res->flags)
-                release_resource(res);
-        gpmc_cs_set_reserved(cs, 0);
-        spin_unlock(&gpmc_mem_lock);
-}
-EXPORT_SYMBOL(gpmc_cs_free);
-/**
- * gpmc_configure - write request to configure gpmc
- * @cmd: command type
- * @wval: value to write
- * @return status of the operation
- */
-int gpmc_configure(int cmd, int wval)
-{
-        u32 regval;
-        switch (cmd) {
-        case GPMC_ENABLE_IRQ:
-                gpmc_write_reg(GPMC_IRQENABLE, wval);
-                break;
-        case GPMC_SET_IRQ_STATUS:
-                gpmc_write_reg(GPMC_IRQSTATUS, wval);
-                break;
-        case GPMC_CONFIG_WP:
-                regval = gpmc_read_reg(GPMC_CONFIG);
-                if (wval)
-                        regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
-                else
-                        regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
-                gpmc_write_reg(GPMC_CONFIG, regval);
-                break;
-        default:
-                pr_err("%s: command not supported\n", __func__);
-                return -EINVAL;
-        }
-        return 0;
-}
-EXPORT_SYMBOL(gpmc_configure);
-void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
-{
-        int i;
-        reg->gpmc_status = gpmc_base + GPMC_STATUS;
-        reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
-                                GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
-        reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
-                                GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
-        reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
-                                GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
-        reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
-        reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
-        reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
-        reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
-        reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
-        reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
-        reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
-        reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
-        for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
-                reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
-                                           GPMC_BCH_SIZE * i;
-                reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
-                                           GPMC_BCH_SIZE * i;
-                reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
-                                           GPMC_BCH_SIZE * i;
-                reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
-                                           GPMC_BCH_SIZE * i;
-                reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
-                                           i * GPMC_BCH_SIZE;
-                reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
-                                           i * GPMC_BCH_SIZE;
-                reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
-                                           i * GPMC_BCH_SIZE;
-        }
-}
-int gpmc_get_client_irq(unsigned irq_config)
-{
-        int i;
-        if (hweight32(irq_config) > 1)
-                return 0;
-        for (i = 0; i < GPMC_NR_IRQ; i++)
-                if (gpmc_client_irq[i].bitmask & irq_config)
-                        return gpmc_client_irq[i].irq;
-        return 0;
-}
-static int gpmc_irq_endis(unsigned irq, bool endis)
-{
-        int i;
-        u32 regval;
-        for (i = 0; i < GPMC_NR_IRQ; i++)
-                if (irq == gpmc_client_irq[i].irq) {
-                        regval = gpmc_read_reg(GPMC_IRQENABLE);
-                        if (endis)
-                                regval |= gpmc_client_irq[i].bitmask;
-                        else
-                                regval &= ~gpmc_client_irq[i].bitmask;
-                        gpmc_write_reg(GPMC_IRQENABLE, regval);
-                        break;
-                }
-        return 0;
-}
-static void gpmc_irq_disable(struct irq_data *p)
-{
-        gpmc_irq_endis(p->irq, false);
-}
-static void gpmc_irq_enable(struct irq_data *p)
-{
-        gpmc_irq_endis(p->irq, true);
-}
-static void gpmc_irq_noop(struct irq_data *data) { }
-static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
-static int gpmc_setup_irq(void)
-{
-        int i;
-        u32 regval;
-        if (!gpmc_irq)
-                return -EINVAL;
-        gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
-        if (gpmc_irq_start < 0) {
-                pr_err("irq_alloc_descs failed\n");
-                return gpmc_irq_start;
-        }
-        gpmc_irq_chip.name = "gpmc";
-        gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
-        gpmc_irq_chip.irq_enable = gpmc_irq_enable;
-        gpmc_irq_chip.irq_disable = gpmc_irq_disable;
-        gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
-        gpmc_irq_chip.irq_ack = gpmc_irq_noop;
-        gpmc_irq_chip.irq_mask = gpmc_irq_noop;
-        gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
-        gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
-        gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
-        for (i = 0; i < GPMC_NR_IRQ; i++) {
-                gpmc_client_irq[i].irq = gpmc_irq_start + i;
-                irq_set_chip_and_handler(gpmc_client_irq[i].irq,
-                                        &gpmc_irq_chip, handle_simple_irq);
-                set_irq_flags(gpmc_client_irq[i].irq,
-                                IRQF_VALID | IRQF_NOAUTOEN);
-        }
-        /* Disable interrupts */
-        gpmc_write_reg(GPMC_IRQENABLE, 0);
-        /* clear interrupts */
-        regval = gpmc_read_reg(GPMC_IRQSTATUS);
-        gpmc_write_reg(GPMC_IRQSTATUS, regval);
-        return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
-}
-static int gpmc_free_irq(void)
-{
-        int i;
-        if (gpmc_irq)
-                free_irq(gpmc_irq, NULL);
-        for (i = 0; i < GPMC_NR_IRQ; i++) {
-                irq_set_handler(gpmc_client_irq[i].irq, NULL);
-                irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
-                irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
-        }
-        irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
-        return 0;
-}
-static void gpmc_mem_exit(void)
-{
-        int cs;
-        for (cs = 0; cs < gpmc_cs_num; cs++) {
-                if (!gpmc_cs_mem_enabled(cs))
-                        continue;
-                gpmc_cs_delete_mem(cs);
-        }
-}
-static void gpmc_mem_init(void)
-{
-        int cs;
-        /*
-         * The first 1MB of GPMC address space is typically mapped to
-         * the internal ROM. Never allocate the first page, to
-         * facilitate bug detection; even if we didn't boot from ROM.
-         */
-        gpmc_mem_root.start = SZ_1M;
-        gpmc_mem_root.end = GPMC_MEM_END;
-        /* Reserve all regions that has been set up by bootloader */
-        for (cs = 0; cs < gpmc_cs_num; cs++) {
-                u32 base, size;
-                if (!gpmc_cs_mem_enabled(cs))
-                        continue;
-                gpmc_cs_get_memconf(cs, &base, &size);
-                if (gpmc_cs_insert_mem(cs, base, size)) {
-                        pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
-                                __func__, cs, base, base + size);
-                        gpmc_cs_disable_mem(cs);
-                }
-        }
-}
-static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
-{
-        u32 temp;
-        int div;
-        div = gpmc_calc_divider(sync_clk);
-        temp = gpmc_ps_to_ticks(time_ps);
-        temp = (temp + div - 1) / div;
-        return gpmc_ticks_to_ps(temp * div);
-}
-/* XXX: can the cycles be avoided ? */
-static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
-                                       struct gpmc_device_timings *dev_t,
-                                       bool mux)
-{
-        u32 temp;
-        /* adv_rd_off */
-        temp = dev_t->t_avdp_r;
-        /* XXX: mux check required ? */
-        if (mux) {
-                /* XXX: t_avdp not to be required for sync, only added for tusb
-                 * this indirectly necessitates requirement of t_avdp_r and
-                 * t_avdp_w instead of having a single t_avdp
-                 */
-                temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
-                temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
-        }
-        gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
-        /* oe_on */
-        temp = dev_t->t_oeasu; /* XXX: remove this ? */
-        if (mux) {
-                temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
-                temp = max_t(u32, temp, gpmc_t->adv_rd_off +
-                                gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
-        }
-        gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
-        /* access */
-        /* XXX: any scope for improvement ?, by combining oe_on
-         * and clk_activation, need to check whether
-         * access = clk_activation + round to sync clk ?
-         */
-        temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
-        temp += gpmc_t->clk_activation;
-        if (dev_t->cyc_oe)
-                temp = max_t(u32, temp, gpmc_t->oe_on +
-                                gpmc_ticks_to_ps(dev_t->cyc_oe));
-        gpmc_t->access = gpmc_round_ps_to_ticks(temp);
-        gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
-        gpmc_t->cs_rd_off = gpmc_t->oe_off;
-        /* rd_cycle */
-        temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
-        temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
-                                                        gpmc_t->access;
-        /* XXX: barter t_ce_rdyz with t_cez_r ? */
-        if (dev_t->t_ce_rdyz)
-                temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
-        gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
-        return 0;
-}
-static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
-                                        struct gpmc_device_timings *dev_t,
-                                        bool mux)
-{
-        u32 temp;
-        /* adv_wr_off */
-        temp = dev_t->t_avdp_w;
-        if (mux) {
-                temp = max_t(u32, temp,
-                        gpmc_t->clk_activation + dev_t->t_avdh);
-                temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
-        }
-        gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
-        /* wr_data_mux_bus */
-        temp = max_t(u32, dev_t->t_weasu,
-                        gpmc_t->clk_activation + dev_t->t_rdyo);
-        /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
-         * and in that case remember to handle we_on properly
-         */
-        if (mux) {
-                temp = max_t(u32, temp,
-                        gpmc_t->adv_wr_off + dev_t->t_aavdh);
-                temp = max_t(u32, temp, gpmc_t->adv_wr_off +
-                                gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
-        }
-        gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
-        /* we_on */
-        if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
-                gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
-        else
-                gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
-        /* wr_access */
-        /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
-        gpmc_t->wr_access = gpmc_t->access;
-        /* we_off */
-        temp = gpmc_t->we_on + dev_t->t_wpl;
-        temp = max_t(u32, temp,
-                        gpmc_t->wr_access + gpmc_ticks_to_ps(1));
-        temp = max_t(u32, temp,
-                gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
-        gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
-        gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
-                                                        dev_t->t_wph);
-        /* wr_cycle */
-        temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
-        temp += gpmc_t->wr_access;
-        /* XXX: barter t_ce_rdyz with t_cez_w ? */
-        if (dev_t->t_ce_rdyz)
-                temp = max_t(u32, temp,
-                                 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
-        gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
-        return 0;
-}
-static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
-                                        struct gpmc_device_timings *dev_t,
-                                        bool mux)
-{
-        u32 temp;
-        /* adv_rd_off */
-        temp = dev_t->t_avdp_r;
-        if (mux)
-                temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
-        gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
-        /* oe_on */
-        temp = dev_t->t_oeasu;
-        if (mux)
-                temp = max_t(u32, temp,
-                        gpmc_t->adv_rd_off + dev_t->t_aavdh);
-        gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
-        /* access */
-        temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
-                                gpmc_t->oe_on + dev_t->t_oe);
-        temp = max_t(u32, temp,
-                                gpmc_t->cs_on + dev_t->t_ce);
-        temp = max_t(u32, temp,
-                                gpmc_t->adv_on + dev_t->t_aa);
-        gpmc_t->access = gpmc_round_ps_to_ticks(temp);
-        gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
-        gpmc_t->cs_rd_off = gpmc_t->oe_off;
-        /* rd_cycle */
-        temp = max_t(u32, dev_t->t_rd_cycle,
-                        gpmc_t->cs_rd_off + dev_t->t_cez_r);
-        temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
-        gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
-        return 0;
-}
-static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
-                                         struct gpmc_device_timings *dev_t,
-                                         bool mux)
-{
-        u32 temp;
-        /* adv_wr_off */
-        temp = dev_t->t_avdp_w;
-        if (mux)
-                temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
-        gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
-        /* wr_data_mux_bus */
-        temp = dev_t->t_weasu;
-        if (mux) {
-                temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
-                temp = max_t(u32, temp, gpmc_t->adv_wr_off +
-                                gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
-        }
-        gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
-        /* we_on */
-        if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
-                gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
-        else
-                gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
-        /* we_off */
-        temp = gpmc_t->we_on + dev_t->t_wpl;
-        gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
-        gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
-                                                        dev_t->t_wph);
-        /* wr_cycle */
-        temp = max_t(u32, dev_t->t_wr_cycle,
-                                gpmc_t->cs_wr_off + dev_t->t_cez_w);
-        gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
-        return 0;
-}
-static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
-                        struct gpmc_device_timings *dev_t)
-{
-        u32 temp;
-        gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
-                                                gpmc_get_fclk_period();
-        gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
-                                        dev_t->t_bacc,
-                                        gpmc_t->sync_clk);
-        temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
-        gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
-        if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
-                return 0;
-        if (dev_t->ce_xdelay)
-                gpmc_t->bool_timings.cs_extra_delay = true;
-        if (dev_t->avd_xdelay)
-                gpmc_t->bool_timings.adv_extra_delay = true;
-        if (dev_t->oe_xdelay)
-                gpmc_t->bool_timings.oe_extra_delay = true;
-        if (dev_t->we_xdelay)
-                gpmc_t->bool_timings.we_extra_delay = true;
-        return 0;
-}
-static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
-                                    struct gpmc_device_timings *dev_t,
-                                    bool sync)
-{
-        u32 temp;
-        /* cs_on */
-        gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
-        /* adv_on */
-        temp = dev_t->t_avdasu;
-        if (dev_t->t_ce_avd)
-                temp = max_t(u32, temp,
-                                gpmc_t->cs_on + dev_t->t_ce_avd);
-        gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
-        if (sync)
-                gpmc_calc_sync_common_timings(gpmc_t, dev_t);
-        return 0;
-}
-/* TODO: remove this function once all peripherals are confirmed to
- * work with generic timing. Simultaneously gpmc_cs_set_timings()
- * has to be modified to handle timings in ps instead of ns
-*/
-static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
-{
-        t->cs_on /= 1000;
-        t->cs_rd_off /= 1000;
-        t->cs_wr_off /= 1000;
-        t->adv_on /= 1000;
-        t->adv_rd_off /= 1000;
-        t->adv_wr_off /= 1000;
-        t->we_on /= 1000;
-        t->we_off /= 1000;
-        t->oe_on /= 1000;
-        t->oe_off /= 1000;
-        t->page_burst_access /= 1000;
-        t->access /= 1000;
-        t->rd_cycle /= 1000;
-        t->wr_cycle /= 1000;
-        t->bus_turnaround /= 1000;
-        t->cycle2cycle_delay /= 1000;
-        t->wait_monitoring /= 1000;
-        t->clk_activation /= 1000;
-        t->wr_access /= 1000;
-        t->wr_data_mux_bus /= 1000;
-}
-int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
-                      struct gpmc_settings *gpmc_s,
-                      struct gpmc_device_timings *dev_t)
-{
-        bool mux = false, sync = false;
-        if (gpmc_s) {
-                mux = gpmc_s->mux_add_data ? true : false;
-                sync = (gpmc_s->sync_read || gpmc_s->sync_write);
-        }
-        memset(gpmc_t, 0, sizeof(*gpmc_t));
-        gpmc_calc_common_timings(gpmc_t, dev_t, sync);
-        if (gpmc_s && gpmc_s->sync_read)
-                gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
-        else
-                gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
-        if (gpmc_s && gpmc_s->sync_write)
-                gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
-        else
-                gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
-        /* TODO: remove, see function definition */
-        gpmc_convert_ps_to_ns(gpmc_t);
-        return 0;
-}
-/**
- * gpmc_cs_program_settings - programs non-timing related settings
- * @cs:         GPMC chip-select to program
- * @p:          pointer to GPMC settings structure
- *
- * Programs non-timing related settings for a GPMC chip-select, such as
- * bus-width, burst configuration, etc. Function should be called once
- * for each chip-select that is being used and must be called before
- * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
- * register will be initialised to zero by this function. Returns 0 on
- * success and appropriate negative error code on failure.
- */
-int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
-{
-        u32 config1;
-        if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
-                pr_err("%s: invalid width %d!", __func__, p->device_width);
-                return -EINVAL;
-        }
-        /* Address-data multiplexing not supported for NAND devices */
-        if (p->device_nand && p->mux_add_data) {
-                pr_err("%s: invalid configuration!\n", __func__);
-                return -EINVAL;
-        }
-        if ((p->mux_add_data > GPMC_MUX_AD) ||
-            ((p->mux_add_data == GPMC_MUX_AAD) &&
-             !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
-                pr_err("%s: invalid multiplex configuration!\n", __func__);
-                return -EINVAL;
-        }
-        /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
-        if (p->burst_read || p->burst_write) {
-                switch (p->burst_len) {
-                case GPMC_BURST_4:
-                case GPMC_BURST_8:
-                case GPMC_BURST_16:
-                        break;
-                default:
-                        pr_err("%s: invalid page/burst-length (%d)\n",
-                               __func__, p->burst_len);
-                        return -EINVAL;
-                }
-        }
-        if (p->wait_pin > gpmc_nr_waitpins) {
-                pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
-                return -EINVAL;
-        }
-        config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
-        if (p->sync_read)
-                config1 |= GPMC_CONFIG1_READTYPE_SYNC;
-        if (p->sync_write)
-                config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
-        if (p->wait_on_read)
-                config1 |= GPMC_CONFIG1_WAIT_READ_MON;
-        if (p->wait_on_write)
-                config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
-        if (p->wait_on_read || p->wait_on_write)
-                config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
-        if (p->device_nand)
-                config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
-        if (p->mux_add_data)
-                config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
-        if (p->burst_read)
-                config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
-        if (p->burst_write)
-                config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
-        if (p->burst_read || p->burst_write) {
-                config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
-                config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
-        }
-        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
-        return 0;
-}
-#ifdef CONFIG_OF
-static const struct of_device_id gpmc_dt_ids[] = {
-        { .compatible = "ti,omap2420-gpmc" },
-        { .compatible = "ti,omap2430-gpmc" },
-        { .compatible = "ti,omap3430-gpmc" },   /* omap3430 & omap3630 */
-        { .compatible = "ti,omap4430-gpmc" },   /* omap4430 & omap4460 & omap543x */
-        { .compatible = "ti,am3352-gpmc" },     /* am335x devices */
-        { }
-};
-MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
-/**
- * gpmc_read_settings_dt - read gpmc settings from device-tree
- * @np:         pointer to device-tree node for a gpmc child device
- * @p:          pointer to gpmc settings structure
- *
- * Reads the GPMC settings for a GPMC child device from device-tree and
- * stores them in the GPMC settings structure passed. The GPMC settings
- * structure is initialised to zero by this function and so any
- * previously stored settings will be cleared.
- */
-void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
-{
-        memset(p, 0, sizeof(struct gpmc_settings));
-        p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
-        p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
-        of_property_read_u32(np, "gpmc,device-width", &p->device_width);
-        of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
-        if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
-                p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
-                p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
-                p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
-                if (!p->burst_read && !p->burst_write)
-                        pr_warn("%s: page/burst-length set but not used!\n",
-                                __func__);
-        }
-        if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
-                p->wait_on_read = of_property_read_bool(np,
-                                                        "gpmc,wait-on-read");
-                p->wait_on_write = of_property_read_bool(np,
-                                                         "gpmc,wait-on-write");
-                if (!p->wait_on_read && !p->wait_on_write)
-                        pr_debug("%s: rd/wr wait monitoring not enabled!\n",
-                                 __func__);
-        }
-}
-static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
-                                                struct gpmc_timings *gpmc_t)
-{
-        struct gpmc_bool_timings *p;
-        if (!np || !gpmc_t)
-                return;
-        memset(gpmc_t, 0, sizeof(*gpmc_t));
-        /* minimum clock period for syncronous mode */
-        of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
-        /* chip select timtings */
-        of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
-        of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
-        of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
-        /* ADV signal timings */
-        of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
-        of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
-        of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
-        /* WE signal timings */
-        of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
-        of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
-        /* OE signal timings */
-        of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
-        of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
-        /* access and cycle timings */
-        of_property_read_u32(np, "gpmc,page-burst-access-ns",
-                             &gpmc_t->page_burst_access);
-        of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
-        of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
-        of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
-        of_property_read_u32(np, "gpmc,bus-turnaround-ns",
-                             &gpmc_t->bus_turnaround);
-        of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
-                             &gpmc_t->cycle2cycle_delay);
-        of_property_read_u32(np, "gpmc,wait-monitoring-ns",
-                             &gpmc_t->wait_monitoring);
-        of_property_read_u32(np, "gpmc,clk-activation-ns",
-                             &gpmc_t->clk_activation);
-        /* only applicable to OMAP3+ */
-        of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
-        of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
-                             &gpmc_t->wr_data_mux_bus);
-        /* bool timing parameters */
-        p = &gpmc_t->bool_timings;
-        p->cycle2cyclediffcsen =
-                of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
-        p->cycle2cyclesamecsen =
-                of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
-        p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
-        p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
-        p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
-        p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
-        p->time_para_granularity =
-                of_property_read_bool(np, "gpmc,time-para-granularity");
-}
-#if IS_ENABLED(CONFIG_MTD_NAND)
-static const char * const nand_xfer_types[] = {
-        [NAND_OMAP_PREFETCH_POLLED]             = "prefetch-polled",
-        [NAND_OMAP_POLLED]                      = "polled",
-        [NAND_OMAP_PREFETCH_DMA]                = "prefetch-dma",
-        [NAND_OMAP_PREFETCH_IRQ]                = "prefetch-irq",
-};
-static int gpmc_probe_nand_child(struct platform_device *pdev,
-                                 struct device_node *child)
-{
-        u32 val;
-        const char *s;
-        struct gpmc_timings gpmc_t;
-        struct omap_nand_platform_data *gpmc_nand_data;
-        if (of_property_read_u32(child, "reg", &val) < 0) {
-                dev_err(&pdev->dev, "%s has no 'reg' property\n",
-                        child->full_name);
-                return -ENODEV;
-        }
-        gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
-                                      GFP_KERNEL);
-        if (!gpmc_nand_data)
-                return -ENOMEM;
-        gpmc_nand_data->cs = val;
-        gpmc_nand_data->of_node = child;
-        /* Detect availability of ELM module */
-        gpmc_nand_data->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
-        if (gpmc_nand_data->elm_of_node == NULL)
-                gpmc_nand_data->elm_of_node =
-                                        of_parse_phandle(child, "elm_id", 0);
-        if (gpmc_nand_data->elm_of_node == NULL)
-                pr_warn("%s: ti,elm-id property not found\n", __func__);
-        /* select ecc-scheme for NAND */
-        if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
-                pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
-                return -ENODEV;
-        }
-        if (!strcmp(s, "sw"))
-                gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
-        else if (!strcmp(s, "ham1") ||
-                 !strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
-                gpmc_nand_data->ecc_opt =
-                                OMAP_ECC_HAM1_CODE_HW;
-        else if (!strcmp(s, "bch4"))
-                if (gpmc_nand_data->elm_of_node)
-                        gpmc_nand_data->ecc_opt =
-                                OMAP_ECC_BCH4_CODE_HW;
-                else
-                        gpmc_nand_data->ecc_opt =
-                                OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
-        else if (!strcmp(s, "bch8"))
-                if (gpmc_nand_data->elm_of_node)
-                        gpmc_nand_data->ecc_opt =
-                                OMAP_ECC_BCH8_CODE_HW;
-                else
-                        gpmc_nand_data->ecc_opt =
-                                OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
-        else if (!strcmp(s, "bch16"))
-                if (gpmc_nand_data->elm_of_node)
-                        gpmc_nand_data->ecc_opt =
-                                OMAP_ECC_BCH16_CODE_HW;
-                else
-                        pr_err("%s: BCH16 requires ELM support\n", __func__);
-        else
-                pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__);
-        /* select data transfer mode for NAND controller */
-        if (!of_property_read_string(child, "ti,nand-xfer-type", &s))
-                for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++)
-                        if (!strcasecmp(s, nand_xfer_types[val])) {
-                                gpmc_nand_data->xfer_type = val;
-                                break;
-                        }
-        gpmc_nand_data->flash_bbt = of_get_nand_on_flash_bbt(child);
-        val = of_get_nand_bus_width(child);
-        if (val == 16)
-                gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
-        gpmc_read_timings_dt(child, &gpmc_t);
-        gpmc_nand_init(gpmc_nand_data, &gpmc_t);
-        return 0;
-}
-#else
-static int gpmc_probe_nand_child(struct platform_device *pdev,
-                                 struct device_node *child)
-{
-        return 0;
-}
-#endif
-#if IS_ENABLED(CONFIG_MTD_ONENAND)
-static int gpmc_probe_onenand_child(struct platform_device *pdev,
-                                 struct device_node *child)
-{
-        u32 val;
-        struct omap_onenand_platform_data *gpmc_onenand_data;
-        if (of_property_read_u32(child, "reg", &val) < 0) {
-                dev_err(&pdev->dev, "%s has no 'reg' property\n",
-                        child->full_name);
-                return -ENODEV;
-        }
-        gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
-                                         GFP_KERNEL);
-        if (!gpmc_onenand_data)
-                return -ENOMEM;
-        gpmc_onenand_data->cs = val;
-        gpmc_onenand_data->of_node = child;
-        gpmc_onenand_data->dma_channel = -1;
-        if (!of_property_read_u32(child, "dma-channel", &val))
-                gpmc_onenand_data->dma_channel = val;
-        gpmc_onenand_init(gpmc_onenand_data);
-        return 0;
-}
-#else
-static int gpmc_probe_onenand_child(struct platform_device *pdev,
-                                    struct device_node *child)
-{
-        return 0;
-}
-#endif
-/**
- * gpmc_probe_generic_child - configures the gpmc for a child device
- * @pdev:       pointer to gpmc platform device
- * @child:      pointer to device-tree node for child device
- *
- * Allocates and configures a GPMC chip-select for a child device.
- * Returns 0 on success and appropriate negative error code on failure.
- */
-static int gpmc_probe_generic_child(struct platform_device *pdev,
-                                struct device_node *child)
-{
-        struct gpmc_settings gpmc_s;
-        struct gpmc_timings gpmc_t;
-        struct resource res;
-        unsigned long base;
-        int ret, cs;
-        if (of_property_read_u32(child, "reg", &cs) < 0) {
-                dev_err(&pdev->dev, "%s has no 'reg' property\n",
-                        child->full_name);
-                return -ENODEV;
-        }
-        if (of_address_to_resource(child, 0, &res) < 0) {
-                dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
-                        child->full_name);
-                return -ENODEV;
-        }
-        ret = gpmc_cs_request(cs, resource_size(&res), &base);
-        if (ret < 0) {
-                dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
-                return ret;
-        }
-        /*
-         * For some GPMC devices we still need to rely on the bootloader
-         * timings because the devices can be connected via FPGA. So far
-         * the list is smc91x on the omap2 SDP boards, and 8250 on zooms.
-         * REVISIT: Add timing support from slls644g.pdf and from the
-         * lan91c96 manual.
-         */
-        if (of_device_is_compatible(child, "ns16550a") ||
-            of_device_is_compatible(child, "smsc,lan91c94") ||
-            of_device_is_compatible(child, "smsc,lan91c111")) {
-                dev_warn(&pdev->dev,
-                         "%s using bootloader timings on CS%d\n",
-                         child->name, cs);
-                goto no_timings;
-        }
-        /*
-         * FIXME: gpmc_cs_request() will map the CS to an arbitary
-         * location in the gpmc address space. When booting with
-         * device-tree we want the NOR flash to be mapped to the
-         * location specified in the device-tree blob. So remap the
-         * CS to this location. Once DT migration is complete should
-         * just make gpmc_cs_request() map a specific address.
-         */
-        ret = gpmc_cs_remap(cs, res.start);
-        if (ret < 0) {
-                dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
-                        cs, &res.start);
-                goto err;
-        }
-        gpmc_read_settings_dt(child, &gpmc_s);
-        ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
-        if (ret < 0)
-                goto err;
-        ret = gpmc_cs_program_settings(cs, &gpmc_s);
-        if (ret < 0)
-                goto err;
-        gpmc_read_timings_dt(child, &gpmc_t);
-        gpmc_cs_set_timings(cs, &gpmc_t);
-no_timings:
-        if (of_platform_device_create(child, NULL, &pdev->dev))
-                return 0;
-        dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
-        ret = -ENODEV;
-err:
-        gpmc_cs_free(cs);
-        return ret;
-}
-static int gpmc_probe_dt(struct platform_device *pdev)
-{
-        int ret;
-        struct device_node *child;
-        const struct of_device_id *of_id =
-                of_match_device(gpmc_dt_ids, &pdev->dev);
-        if (!of_id)
-                return 0;
-        ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
-                                   &gpmc_cs_num);
-        if (ret < 0) {
-                pr_err("%s: number of chip-selects not defined\n", __func__);
-                return ret;
-        } else if (gpmc_cs_num < 1) {
-                pr_err("%s: all chip-selects are disabled\n", __func__);
-                return -EINVAL;
-        } else if (gpmc_cs_num > GPMC_CS_NUM) {
-                pr_err("%s: number of supported chip-selects cannot be > %d\n",
-                                         __func__, GPMC_CS_NUM);
-                return -EINVAL;
-        }
-        ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
-                                   &gpmc_nr_waitpins);
-        if (ret < 0) {
-                pr_err("%s: number of wait pins not found!\n", __func__);
-                return ret;
-        }
-        for_each_available_child_of_node(pdev->dev.of_node, child) {
-                if (!child->name)
-                        continue;
-                if (of_node_cmp(child->name, "nand") == 0)
-                        ret = gpmc_probe_nand_child(pdev, child);
-                else if (of_node_cmp(child->name, "onenand") == 0)
-                        ret = gpmc_probe_onenand_child(pdev, child);
-                else if (of_node_cmp(child->name, "ethernet") == 0 ||
-                         of_node_cmp(child->name, "nor") == 0 ||
-                         of_node_cmp(child->name, "uart") == 0)
-                        ret = gpmc_probe_generic_child(pdev, child);
-                if (WARN(ret < 0, "%s: probing gpmc child %s failed\n",
-                         __func__, child->full_name))
-                        of_node_put(child);
-        }
-        return 0;
-}
-#else
-static int gpmc_probe_dt(struct platform_device *pdev)
-{
-        return 0;
-}
-#endif
-static int gpmc_probe(struct platform_device *pdev)
-{
-        int rc;
-        u32 l;
-        struct resource *res;
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (res == NULL)
-                return -ENOENT;
-        phys_base = res->start;
-        mem_size = resource_size(res);
-        gpmc_base = devm_ioremap_resource(&pdev->dev, res);
-        if (IS_ERR(gpmc_base))
-                return PTR_ERR(gpmc_base);
-        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-        if (res == NULL)
-                dev_warn(&pdev->dev, "Failed to get resource: irq\n");
-        else
-                gpmc_irq = res->start;
-        gpmc_l3_clk = clk_get(&pdev->dev, "fck");
-        if (IS_ERR(gpmc_l3_clk)) {
-                dev_err(&pdev->dev, "error: clk_get\n");
-                gpmc_irq = 0;
-                return PTR_ERR(gpmc_l3_clk);
-        }
-        pm_runtime_enable(&pdev->dev);
-        pm_runtime_get_sync(&pdev->dev);
-        gpmc_dev = &pdev->dev;
-        l = gpmc_read_reg(GPMC_REVISION);
-        /*
-         * FIXME: Once device-tree migration is complete the below flags
-         * should be populated based upon the device-tree compatible
-         * string. For now just use the IP revision. OMAP3+ devices have
-         * the wr_access and wr_data_mux_bus register fields. OMAP4+
-         * devices support the addr-addr-data multiplex protocol.
-         *
-         * GPMC IP revisions:
-         * - OMAP24xx                   = 2.0
-         * - OMAP3xxx                   = 5.0
-         * - OMAP44xx/54xx/AM335x       = 6.0
-         */
-        if (GPMC_REVISION_MAJOR(l) > 0x4)
-                gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
-        if (GPMC_REVISION_MAJOR(l) > 0x5)
-                gpmc_capability |= GPMC_HAS_MUX_AAD;
-        dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
-                 GPMC_REVISION_MINOR(l));
-        gpmc_mem_init();
-        if (gpmc_setup_irq() < 0)
-                dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
-        /* Now the GPMC is initialised, unreserve the chip-selects */
-        gpmc_cs_map = 0;
-        if (!pdev->dev.of_node) {
-                gpmc_cs_num      = GPMC_CS_NUM;
-                gpmc_nr_waitpins = GPMC_NR_WAITPINS;
-        }
-        rc = gpmc_probe_dt(pdev);
-        if (rc < 0) {
-                pm_runtime_put_sync(&pdev->dev);
-                clk_put(gpmc_l3_clk);
-                dev_err(gpmc_dev, "failed to probe DT parameters\n");
-                return rc;
-        }
-        return 0;
-}
-static int gpmc_remove(struct platform_device *pdev)
-{
-        gpmc_free_irq();
-        gpmc_mem_exit();
-        pm_runtime_put_sync(&pdev->dev);
-        pm_runtime_disable(&pdev->dev);
-        gpmc_dev = NULL;
-        return 0;
-}
-#ifdef CONFIG_PM_SLEEP
-static int gpmc_suspend(struct device *dev)
-{
-        omap3_gpmc_save_context();
-        pm_runtime_put_sync(dev);
-        return 0;
-}
-static int gpmc_resume(struct device *dev)
-{
-        pm_runtime_get_sync(dev);
-        omap3_gpmc_restore_context();
-        return 0;
-}
-#endif
-static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
-static struct platform_driver gpmc_driver = {
-        .probe          = gpmc_probe,
-        .remove         = gpmc_remove,
-        .driver         = {
-                .name   = DEVICE_NAME,
-                .owner  = THIS_MODULE,
-                .of_match_table = of_match_ptr(gpmc_dt_ids),
-                .pm     = &gpmc_pm_ops,
-        },
-};
-static __init int gpmc_init(void)
-{
-        return platform_driver_register(&gpmc_driver);
-}
-static __exit void gpmc_exit(void)
-{
-        platform_driver_unregister(&gpmc_driver);
-}
-omap_postcore_initcall(gpmc_init);
-module_exit(gpmc_exit);
-static int __init omap_gpmc_init(void)
-{
-        struct omap_hwmod *oh;
-        struct platform_device *pdev;
-        char *oh_name = "gpmc";
-        /*
-         * if the board boots up with a populated DT, do not
-         * manually add the device from this initcall
-         */
-        if (of_have_populated_dt())
-                return -ENODEV;
-        oh = omap_hwmod_lookup(oh_name);
-        if (!oh) {
-                pr_err("Could not look up %s\n", oh_name);
-                return -ENODEV;
-        }
-        pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0);
-        WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
-        return PTR_RET(pdev);
-}
-omap_postcore_initcall(omap_gpmc_init);
-static irqreturn_t gpmc_handle_irq(int irq, void *dev)
-{
-        int i;
-        u32 regval;
-        regval = gpmc_read_reg(GPMC_IRQSTATUS);
-        if (!regval)
-                return IRQ_NONE;
-        for (i = 0; i < GPMC_NR_IRQ; i++)
-                if (regval & gpmc_client_irq[i].bitmask)
-                        generic_handle_irq(gpmc_client_irq[i].irq);
-        gpmc_write_reg(GPMC_IRQSTATUS, regval);
-        return IRQ_HANDLED;
-}
-static struct omap3_gpmc_regs gpmc_context;
-void omap3_gpmc_save_context(void)
-{
-        int i;
-        gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
-        gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
-        gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
-        gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
-        gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
-        gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
-        gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
-        for (i = 0; i < gpmc_cs_num; i++) {
-                gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
-                if (gpmc_context.cs_context[i].is_valid) {
-                        gpmc_context.cs_context[i].config1 =
-                                gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
-                        gpmc_context.cs_context[i].config2 =
-                                gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
-                        gpmc_context.cs_context[i].config3 =
-                                gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
-                        gpmc_context.cs_context[i].config4 =
-                                gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
-                        gpmc_context.cs_context[i].config5 =
-                                gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
-                        gpmc_context.cs_context[i].config6 =
-                                gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
-                        gpmc_context.cs_context[i].config7 =
-                                gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
-                }
-        }
-}
-void omap3_gpmc_restore_context(void)
-{
-        int i;
-        gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
-        gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
-        gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
-        gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
-        gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
-        gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
-        gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
-        for (i = 0; i < gpmc_cs_num; i++) {
-                if (gpmc_context.cs_context[i].is_valid) {
-                        gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
-                                gpmc_context.cs_context[i].config1);
-                        gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
-                                gpmc_context.cs_context[i].config2);
-                        gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
-                                gpmc_context.cs_context[i].config3);
-                        gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
-                                gpmc_context.cs_context[i].config4);
-                        gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
-                                gpmc_context.cs_context[i].config5);
-                        gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
-                                gpmc_context.cs_context[i].config6);
-                        gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
-                                gpmc_context.cs_context[i].config7);
-                }
-        }
-}
diff --git a/arch/arm/mach-omap2/gpmc.h b/arch/arm/mach-omap2/gpmc.h
index 707f6d58edd5..9caa41a6cb04 100644
--- a/arch/arm/mach-omap2/gpmc.h
+++ b/arch/arm/mach-omap2/gpmc.h
@@ -6,226 +6,9 @@
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
+ *
+ * Do not include this file in any new code, this will get removed
+ * once omap3 boots in device tree only mode.
+ *
 */
+#include <linux/omap-gpmc.h>
-#ifndef __OMAP2_GPMC_H
-#define __OMAP2_GPMC_H
-#include <linux/platform_data/mtd-nand-omap2.h>
-/* Maximum Number of Chip Selects */
-#define GPMC_CS_NUM             8
-#define GPMC_CS_CONFIG1         0x00
-#define GPMC_CS_CONFIG2         0x04
-#define GPMC_CS_CONFIG3         0x08
-#define GPMC_CS_CONFIG4         0x0c
-#define GPMC_CS_CONFIG5         0x10
-#define GPMC_CS_CONFIG6         0x14
-#define GPMC_CS_CONFIG7         0x18
-#define GPMC_CS_NAND_COMMAND    0x1c
-#define GPMC_CS_NAND_ADDRESS    0x20
-#define GPMC_CS_NAND_DATA       0x24
-/* Control Commands */
-#define GPMC_CONFIG_RDY_BSY     0x00000001
-#define GPMC_CONFIG_DEV_SIZE    0x00000002
-#define GPMC_CONFIG_DEV_TYPE    0x00000003
-#define GPMC_SET_IRQ_STATUS     0x00000004
-#define GPMC_CONFIG_WP          0x00000005
-#define GPMC_ENABLE_IRQ         0x0000000d
-/* ECC commands */
-#define GPMC_ECC_READ           0 /* Reset Hardware ECC for read */
-#define GPMC_ECC_WRITE          1 /* Reset Hardware ECC for write */
-#define GPMC_ECC_READSYN        2 /* Reset before syndrom is read back */
-#define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
-#define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
-#define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
-#define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
-#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
-#define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
-#define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
-#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
-#define GPMC_CONFIG1_PAGE_LEN(val)      ((val & 3) << 23)
-#define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
-#define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
-#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
-#define GPMC_CONFIG1_WAIT_PIN_SEL(val)  ((val & 3) << 16)
-#define GPMC_CONFIG1_DEVICESIZE(val)    ((val & 3) << 12)
-#define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
-#define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
-#define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
-#define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
-#define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
-#define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
-#define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
-#define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
-#define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
-#define GPMC_CONFIG7_CSVALID            (1 << 6)
-#define GPMC_DEVICETYPE_NOR             0
-#define GPMC_DEVICETYPE_NAND            2
-#define GPMC_CONFIG_WRITEPROTECT        0x00000010
-#define WR_RD_PIN_MONITORING            0x00600000
-#define GPMC_IRQ_FIFOEVENTENABLE        0x01
-#define GPMC_IRQ_COUNT_EVENT            0x02
-#define GPMC_BURST_4                    4       /* 4 word burst */
-#define GPMC_BURST_8                    8       /* 8 word burst */
-#define GPMC_BURST_16                   16      /* 16 word burst */
-#define GPMC_DEVWIDTH_8BIT              1       /* 8-bit device width */
-#define GPMC_DEVWIDTH_16BIT             2       /* 16-bit device width */
-#define GPMC_MUX_AAD                    1       /* Addr-Addr-Data multiplex */
-#define GPMC_MUX_AD                     2       /* Addr-Data multiplex */
-/* bool type time settings */
-struct gpmc_bool_timings {
-        bool cycle2cyclediffcsen;
-        bool cycle2cyclesamecsen;
-        bool we_extra_delay;
-        bool oe_extra_delay;
-        bool adv_extra_delay;
-        bool cs_extra_delay;
-        bool time_para_granularity;
-};
-/*
- * Note that all values in this struct are in nanoseconds except sync_clk
- * (which is in picoseconds), while the register values are in gpmc_fck cycles.
- */
-struct gpmc_timings {
-        /* Minimum clock period for synchronous mode (in picoseconds) */
-        u32 sync_clk;
-        /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
-        u32 cs_on;              /* Assertion time */
-        u32 cs_rd_off;          /* Read deassertion time */
-        u32 cs_wr_off;          /* Write deassertion time */
-        /* ADV signal timings corresponding to GPMC_CONFIG3 */
-        u32 adv_on;             /* Assertion time */
-        u32 adv_rd_off;         /* Read deassertion time */
-        u32 adv_wr_off;         /* Write deassertion time */
-        /* WE signals timings corresponding to GPMC_CONFIG4 */
-        u32 we_on;              /* WE assertion time */
-        u32 we_off;             /* WE deassertion time */
-        /* OE signals timings corresponding to GPMC_CONFIG4 */
-        u32 oe_on;              /* OE assertion time */
-        u32 oe_off;             /* OE deassertion time */
-        /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
-        u32 page_burst_access;  /* Multiple access word delay */
-        u32 access;             /* Start-cycle to first data valid delay */
-        u32 rd_cycle;           /* Total read cycle time */
-        u32 wr_cycle;           /* Total write cycle time */
-        u32 bus_turnaround;
-        u32 cycle2cycle_delay;
-        u32 wait_monitoring;
-        u32 clk_activation;
-        /* The following are only on OMAP3430 */
-        u32 wr_access;          /* WRACCESSTIME */
-        u32 wr_data_mux_bus;    /* WRDATAONADMUXBUS */
-        struct gpmc_bool_timings bool_timings;
-};
-/* Device timings in picoseconds */
-struct gpmc_device_timings {
-        u32 t_ceasu;    /* address setup to CS valid */
-        u32 t_avdasu;   /* address setup to ADV valid */
-        /* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
-         * of tusb using these timings even for sync whilst
-         * ideally for adv_rd/(wr)_off it should have considered
-         * t_avdh instead. This indirectly necessitates r/w
-         * variations of t_avdp as it is possible to have one
-         * sync & other async
-         */
-        u32 t_avdp_r;   /* ADV low time (what about t_cer ?) */
-        u32 t_avdp_w;
-        u32 t_aavdh;    /* address hold time */
-        u32 t_oeasu;    /* address setup to OE valid */
-        u32 t_aa;       /* access time from ADV assertion */
-        u32 t_iaa;      /* initial access time */
-        u32 t_oe;       /* access time from OE assertion */
-        u32 t_ce;       /* access time from CS asertion */
-        u32 t_rd_cycle; /* read cycle time */
-        u32 t_cez_r;    /* read CS deassertion to high Z */
-        u32 t_cez_w;    /* write CS deassertion to high Z */
-        u32 t_oez;      /* OE deassertion to high Z */
-        u32 t_weasu;    /* address setup to WE valid */
-        u32 t_wpl;      /* write assertion time */
-        u32 t_wph;      /* write deassertion time */
-        u32 t_wr_cycle; /* write cycle time */
-        u32 clk;
-        u32 t_bacc;     /* burst access valid clock to output delay */
-        u32 t_ces;      /* CS setup time to clk */
-        u32 t_avds;     /* ADV setup time to clk */
-        u32 t_avdh;     /* ADV hold time from clk */
-        u32 t_ach;      /* address hold time from clk */
-        u32 t_rdyo;     /* clk to ready valid */
-        u32 t_ce_rdyz;  /* XXX: description ?, or use t_cez instead */
-        u32 t_ce_avd;   /* CS on to ADV on delay */
-        /* XXX: check the possibility of combining
-         * cyc_aavhd_oe & cyc_aavdh_we
-         */
-        u8 cyc_aavdh_oe;/* read address hold time in cycles */
-        u8 cyc_aavdh_we;/* write address hold time in cycles */
-        u8 cyc_oe;      /* access time from OE assertion in cycles */
-        u8 cyc_wpl;     /* write deassertion time in cycles */
-        u32 cyc_iaa;    /* initial access time in cycles */
-        /* extra delays */
-        bool ce_xdelay;
-        bool avd_xdelay;
-        bool oe_xdelay;
-        bool we_xdelay;
-};
-struct gpmc_settings {
-        bool burst_wrap;        /* enables wrap bursting */
-        bool burst_read;        /* enables read page/burst mode */
-        bool burst_write;       /* enables write page/burst mode */
-        bool device_nand;       /* device is NAND */
-        bool sync_read;         /* enables synchronous reads */
-        bool sync_write;        /* enables synchronous writes */
-        bool wait_on_read;      /* monitor wait on reads */
-        bool wait_on_write;     /* monitor wait on writes */
-        u32 burst_len;          /* page/burst length */
-        u32 device_width;       /* device bus width (8 or 16 bit) */
-        u32 mux_add_data;       /* multiplex address & data */
-        u32 wait_pin;           /* wait-pin to be used */
-};
-extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
-                             struct gpmc_settings *gpmc_s,
-                             struct gpmc_device_timings *dev_t);
-extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
-extern int gpmc_get_client_irq(unsigned irq_config);
-extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
-extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
-extern int gpmc_calc_divider(unsigned int sync_clk);
-extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
-extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
-extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
-extern void gpmc_cs_free(int cs);
-extern void omap3_gpmc_save_context(void);
-extern void omap3_gpmc_restore_context(void);
-extern int gpmc_configure(int cmd, int wval);
-extern void gpmc_read_settings_dt(struct device_node *np,
-                                  struct gpmc_settings *p);
-#endif
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 07d4c7b35754..dc6e79c4484a 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -14,14 +14,15 @@
 #include <linux/string.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
+#include <linux/mmc/host.h>
 #include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/hsmmc-omap.h>
 #include "soc.h"
 #include "omap_device.h"
 #include "omap-pm.h"
 #include "mux.h"
-#include "mmc.h"
 #include "hsmmc.h"
 #include "control.h"
@@ -32,25 +33,14 @@ static u16 control_devconf1_offset;
 #define HSMMC_NAME_LEN  9
-#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
+static void omap_hsmmc1_before_set_reg(struct device *dev,
+                                       int power_on, int vdd)
-static int hsmmc_get_context_loss(struct device *dev)
-{
-        return omap_pm_get_dev_context_loss_count(dev);
-}
-#else
-#define hsmmc_get_context_loss NULL
-#endif
-static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
-                                  int power_on, int vdd)
 {
        u32 reg, prog_io;
-        struct omap_mmc_platform_data *mmc = dev->platform_data;
+        struct omap_hsmmc_platform_data *mmc = dev->platform_data;
-        if (mmc->slots[0].remux)
+        if (mmc->remux)
-                mmc->slots[0].remux(dev, slot, power_on);
+                mmc->remux(dev, power_on);
        /*
         * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
@@ -72,7 +62,7 @@ static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
                        omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
                }
-                if (mmc->slots[0].internal_clock) {
+                if (mmc->internal_clock) {
                        reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
                        reg |= OMAP2_MMCSDIO1ADPCLKISEL;
                        omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
@@ -96,8 +86,7 @@ static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
        }
 }
-static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
+static void omap_hsmmc1_after_set_reg(struct device *dev, int power_on, int vdd)
-                                 int power_on, int vdd)
 {
        u32 reg;
@@ -120,34 +109,32 @@ static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
        }
 }
-static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
+static void hsmmc2_select_input_clk_src(struct omap_hsmmc_platform_data *mmc)
 {
        u32 reg;
        reg = omap_ctrl_readl(control_devconf1_offset);
-        if (mmc->slots[0].internal_clock)
+        if (mmc->internal_clock)
                reg |= OMAP2_MMCSDIO2ADPCLKISEL;
        else
                reg &= ~OMAP2_MMCSDIO2ADPCLKISEL;
        omap_ctrl_writel(reg, control_devconf1_offset);
 }
-static void hsmmc2_before_set_reg(struct device *dev, int slot,
+static void hsmmc2_before_set_reg(struct device *dev, int power_on, int vdd)
-                                   int power_on, int vdd)
 {
-        struct omap_mmc_platform_data *mmc = dev->platform_data;
+        struct omap_hsmmc_platform_data *mmc = dev->platform_data;
-        if (mmc->slots[0].remux)
+        if (mmc->remux)
-                mmc->slots[0].remux(dev, slot, power_on);
+                mmc->remux(dev, power_on);
        if (power_on)
                hsmmc2_select_input_clk_src(mmc);
 }
-static int am35x_hsmmc2_set_power(struct device *dev, int slot,
+static int am35x_hsmmc2_set_power(struct device *dev, int power_on, int vdd)
-                                  int power_on, int vdd)
 {
-        struct omap_mmc_platform_data *mmc = dev->platform_data;
+        struct omap_hsmmc_platform_data *mmc = dev->platform_data;
        if (power_on)
                hsmmc2_select_input_clk_src(mmc);
@@ -155,23 +142,22 @@ static int am35x_hsmmc2_set_power(struct device *dev, int slot,
        return 0;
 }
-static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
+static int nop_mmc_set_power(struct device *dev, int power_on, int vdd)
-                                                        int vdd)
 {
        return 0;
 }
-static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
+static inline void omap_hsmmc_mux(struct omap_hsmmc_platform_data
-                        int controller_nr)
+                                  *mmc_controller, int controller_nr)
 {
-        if (gpio_is_valid(mmc_controller->slots[0].switch_pin) &&
+        if (gpio_is_valid(mmc_controller->switch_pin) &&
-                (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
+            (mmc_controller->switch_pin < OMAP_MAX_GPIO_LINES))
-                omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
+                omap_mux_init_gpio(mmc_controller->switch_pin,
-                                        OMAP_PIN_INPUT_PULLUP);
+                                   OMAP_PIN_INPUT_PULLUP);
-        if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) &&
+        if (gpio_is_valid(mmc_controller->gpio_wp) &&
-                (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
+            (mmc_controller->gpio_wp < OMAP_MAX_GPIO_LINES))
-                omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
+                omap_mux_init_gpio(mmc_controller->gpio_wp,
-                                        OMAP_PIN_INPUT_PULLUP);
+                                   OMAP_PIN_INPUT_PULLUP);
        if (cpu_is_omap34xx()) {
                if (controller_nr == 0) {
                        omap_mux_init_signal("sdmmc1_clk",
@@ -180,7 +166,7 @@ static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
                                OMAP_PIN_INPUT_PULLUP);
                        omap_mux_init_signal("sdmmc1_dat0",
                                OMAP_PIN_INPUT_PULLUP);
-                        if (mmc_controller->slots[0].caps &
+                        if (mmc_controller->caps &
                                (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
                                omap_mux_init_signal("sdmmc1_dat1",
                                        OMAP_PIN_INPUT_PULLUP);
@@ -189,7 +175,7 @@ static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
                                omap_mux_init_signal("sdmmc1_dat3",
                                        OMAP_PIN_INPUT_PULLUP);
                        }
-                        if (mmc_controller->slots[0].caps &
+                        if (mmc_controller->caps &
                                                MMC_CAP_8_BIT_DATA) {
                                omap_mux_init_signal("sdmmc1_dat4",
                                        OMAP_PIN_INPUT_PULLUP);
@@ -214,7 +200,7 @@ static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
                         * For 8 wire configurations, Lines DAT4, 5, 6 and 7
                         * need to be muxed in the board-*.c files
                         */
-                        if (mmc_controller->slots[0].caps &
+                        if (mmc_controller->caps &
                                (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
                                omap_mux_init_signal("sdmmc2_dat1",
                                        OMAP_PIN_INPUT_PULLUP);
@@ -223,7 +209,7 @@ static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
                                omap_mux_init_signal("sdmmc2_dat3",
                                        OMAP_PIN_INPUT_PULLUP);
                        }
-                        if (mmc_controller->slots[0].caps &
+                        if (mmc_controller->caps &
                                                        MMC_CAP_8_BIT_DATA) {
                                omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
                                        OMAP_PIN_INPUT_PULLUP);
@@ -243,7 +229,7 @@ static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
 }
 static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
-                                        struct omap_mmc_platform_data *mmc)
+                                        struct omap_hsmmc_platform_data *mmc)
 {
        char *hc_name;
@@ -259,38 +245,22 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
        else
                snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
                                                                c->mmc, 1);
-        mmc->slots[0].name = hc_name;
+        mmc->name = hc_name;
-        mmc->nr_slots = 1;
+        mmc->caps = c->caps;
-        mmc->slots[0].caps = c->caps;
+        mmc->internal_clock = !c->ext_clock;
-        mmc->slots[0].pm_caps = c->pm_caps;
-        mmc->slots[0].internal_clock = !c->ext_clock;
-        mmc->max_freq = c->max_freq;
        mmc->reg_offset = 0;
-        mmc->get_context_loss_count = hsmmc_get_context_loss;
-        mmc->slots[0].switch_pin = c->gpio_cd;
+        mmc->switch_pin = c->gpio_cd;
-        mmc->slots[0].gpio_wp = c->gpio_wp;
+        mmc->gpio_wp = c->gpio_wp;
-        mmc->slots[0].remux = c->remux;
+        mmc->remux = c->remux;
-        mmc->slots[0].init_card = c->init_card;
+        mmc->init_card = c->init_card;
        if (c->cover_only)
-                mmc->slots[0].cover = 1;
+                mmc->cover = 1;
        if (c->nonremovable)
-                mmc->slots[0].nonremovable = 1;
+                mmc->nonremovable = 1;
-        if (c->power_saving)
-                mmc->slots[0].power_saving = 1;
-        if (c->no_off)
-                mmc->slots[0].no_off = 1;
-        if (c->no_off_init)
-                mmc->slots[0].no_regulator_off_init = c->no_off_init;
-        if (c->vcc_aux_disable_is_sleep)
-                mmc->slots[0].vcc_aux_disable_is_sleep = 1;
        /*
         * NOTE:  MMC slots should have a Vcc regulator set up.
@@ -300,42 +270,42 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
         * temporary HACK: ocr_mask instead of fixed supply
         */
        if (soc_is_am35xx())
-                mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
+                mmc->ocr_mask = MMC_VDD_165_195 |
                                         MMC_VDD_26_27 |
                                         MMC_VDD_27_28 |
                                         MMC_VDD_29_30 |
                                         MMC_VDD_30_31 |
                                         MMC_VDD_31_32;
        else
-                mmc->slots[0].ocr_mask = c->ocr_mask;
+                mmc->ocr_mask = c->ocr_mask;
        if (!soc_is_am35xx())
-                mmc->slots[0].features |= HSMMC_HAS_PBIAS;
+                mmc->features |= HSMMC_HAS_PBIAS;
        switch (c->mmc) {
        case 1:
-                if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
+                if (mmc->features & HSMMC_HAS_PBIAS) {
                        /* on-chip level shifting via PBIAS0/PBIAS1 */
-                        mmc->slots[0].before_set_reg =
+                        mmc->before_set_reg =
                                        omap_hsmmc1_before_set_reg;
-                        mmc->slots[0].after_set_reg =
+                        mmc->after_set_reg =
                                        omap_hsmmc1_after_set_reg;
                }
                if (soc_is_am35xx())
-                        mmc->slots[0].set_power = nop_mmc_set_power;
+                        mmc->set_power = nop_mmc_set_power;
                /* OMAP3630 HSMMC1 supports only 4-bit */
                if (cpu_is_omap3630() &&
                                (c->caps & MMC_CAP_8_BIT_DATA)) {
                        c->caps &= ~MMC_CAP_8_BIT_DATA;
                        c->caps |= MMC_CAP_4_BIT_DATA;
-                        mmc->slots[0].caps = c->caps;
+                        mmc->caps = c->caps;
                }
                break;
        case 2:
                if (soc_is_am35xx())
-                        mmc->slots[0].set_power = am35x_hsmmc2_set_power;
+                        mmc->set_power = am35x_hsmmc2_set_power;
                if (c->ext_clock)
                        c->transceiver = 1;
@@ -343,17 +313,17 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
                        c->caps &= ~MMC_CAP_8_BIT_DATA;
                        c->caps |= MMC_CAP_4_BIT_DATA;
                }
-                if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
+                if (mmc->features & HSMMC_HAS_PBIAS) {
                        /* off-chip level shifting, or none */
-                        mmc->slots[0].before_set_reg = hsmmc2_before_set_reg;
+                        mmc->before_set_reg = hsmmc2_before_set_reg;
-                        mmc->slots[0].after_set_reg = NULL;
+                        mmc->after_set_reg = NULL;
                }
                break;
        case 3:
        case 4:
        case 5:
-                mmc->slots[0].before_set_reg = NULL;
+                mmc->before_set_reg = NULL;
-                mmc->slots[0].after_set_reg = NULL;
+                mmc->after_set_reg = NULL;
                break;
        default:
                pr_err("MMC%d configuration not supported!\n", c->mmc);
@@ -368,7 +338,7 @@ static int omap_hsmmc_done;
 void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
 {
        struct platform_device *pdev;
-        struct omap_mmc_platform_data *mmc_pdata;
+        struct omap_hsmmc_platform_data *mmc_pdata;
        int res;
        if (omap_hsmmc_done != 1)
@@ -388,8 +358,8 @@ void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
                if (!mmc_pdata)
                        continue;
-                mmc_pdata->slots[0].switch_pin = c->gpio_cd;
+                mmc_pdata->switch_pin = c->gpio_cd;
-                mmc_pdata->slots[0].gpio_wp = c->gpio_wp;
+                mmc_pdata->gpio_wp = c->gpio_wp;
                res = omap_device_register(pdev);
                if (res)
@@ -408,12 +378,12 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
        struct omap_device *od;
        struct platform_device *pdev;
        char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
-        struct omap_mmc_platform_data *mmc_data;
+        struct omap_hsmmc_platform_data *mmc_data;
-        struct omap_mmc_dev_attr *mmc_dev_attr;
+        struct omap_hsmmc_dev_attr *mmc_dev_attr;
        char *name;
        int res;
-        mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
+        mmc_data = kzalloc(sizeof(*mmc_data), GFP_KERNEL);
        if (!mmc_data) {
                pr_err("Cannot allocate memory for mmc device!\n");
                return;
@@ -463,7 +433,7 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
        }
        res = platform_device_add_data(pdev, mmc_data,
-                              sizeof(struct omap_mmc_platform_data));
+                              sizeof(struct omap_hsmmc_platform_data));
        if (res) {
                pr_err("Could not add pdata for %s\n", name);
                goto put_pdev;
@@ -489,7 +459,7 @@ put_pdev:
        platform_device_put(pdev);
 free_name:
-        kfree(mmc_data->slots[0].name);
+        kfree(mmc_data->name);
 free_mmc:
        kfree(mmc_data);
diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h
index 7f2e790e0929..148cd9b15499 100644
--- a/arch/arm/mach-omap2/hsmmc.h
+++ b/arch/arm/mach-omap2/hsmmc.h
@@ -12,25 +12,18 @@ struct omap2_hsmmc_info {
        u8      mmc;            /* controller 1/2/3 */
        u32     caps;           /* 4/8 wires and any additional host
                                 * capabilities OR'd (ref. linux/mmc/host.h) */
-        u32     pm_caps;        /* PM capabilities */
        bool    transceiver;    /* MMC-2 option */
        bool    ext_clock;      /* use external pin for input clock */
        bool    cover_only;     /* No card detect - just cover switch */
        bool    nonremovable;   /* Nonremovable e.g. eMMC */
-        bool    power_saving;   /* Try to sleep or power off when possible */
-        bool    no_off;         /* power_saving and power is not to go off */
-        bool    no_off_init;    /* no power off when not in MMC sleep state */
-        bool    vcc_aux_disable_is_sleep; /* Regulator off remapped to sleep */
        bool    deferred;       /* mmc needs a deferred probe */
        int     gpio_cd;        /* or -EINVAL */
        int     gpio_wp;        /* or -EINVAL */
        char    *name;          /* or NULL for default */
        struct platform_device *pdev;   /* mmc controller instance */
        int     ocr_mask;       /* temporary HACK */
-        int     max_freq;       /* maximum clock, if constrained by external
-                                 * circuitry, or 0 for default */
        /* Remux (pad configuration) when powering on/off */
-        void (*remux)(struct device *dev, int slot, int power_on);
+        void (*remux)(struct device *dev, int power_on);
        /* init some special card */
        void (*init_card)(struct mmc_card *card);
 };
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 03cbb16898a3..4fc838354e31 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -45,13 +45,15 @@
 #include "sram.h"
 #include "cm2xxx.h"
 #include "cm3xxx.h"
+#include "cm33xx.h"
+#include "cm44xx.h"
 #include "prm.h"
 #include "cm.h"
 #include "prcm_mpu44xx.h"
 #include "prminst44xx.h"
-#include "cminst44xx.h"
 #include "prm2xxx.h"
 #include "prm3xxx.h"
+#include "prm33xx.h"
 #include "prm44xx.h"
 #include "opp2xxx.h"
@@ -565,6 +567,8 @@ void __init am33xx_init_early(void)
        omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
        omap3xxx_check_revision();
        am33xx_check_features();
+        am33xx_prm_init();
+        am33xx_cm_init();
        am33xx_powerdomains_init();
        am33xx_clockdomains_init();
        am33xx_hwmod_init();
@@ -591,6 +595,8 @@ void __init am43xx_init_early(void)
        omap_cm_base_init();
        omap3xxx_check_revision();
        am33xx_check_features();
+        omap44xx_prm_init();
+        omap4_cm_init();
        am43xx_powerdomains_init();
        am43xx_clockdomains_init();
        am43xx_hwmod_init();
@@ -620,6 +626,7 @@ void __init omap4430_init_early(void)
        omap_cm_base_init();
        omap4xxx_check_revision();
        omap4xxx_check_features();
+        omap4_cm_init();
        omap4_pm_init_early();
        omap44xx_prm_init();
        omap44xx_voltagedomains_init();
@@ -655,6 +662,7 @@ void __init omap5_init_early(void)
        omap_cm_base_init();
        omap44xx_prm_init();
        omap5xxx_check_revision();
+        omap4_cm_init();
        omap54xx_voltagedomains_init();
        omap54xx_powerdomains_init();
        omap54xx_clockdomains_init();
@@ -686,6 +694,7 @@ void __init dra7xx_init_early(void)
        omap_cm_base_init();
        omap44xx_prm_init();
        dra7xxx_check_revision();
+        omap4_cm_init();
        dra7xx_powerdomains_init();
        dra7xx_clockdomains_init();
        dra7xx_hwmod_init();
diff --git a/arch/arm/mach-omap2/mmc.h b/arch/arm/mach-omap2/mmc.h
index 0cd4b089da9c..30d39b97e7dd 100644
--- a/arch/arm/mach-omap2/mmc.h
+++ b/arch/arm/mach-omap2/mmc.h
@@ -1,5 +1,3 @@
-#include <linux/mmc/host.h>
-#include <linux/platform_data/mmc-omap.h>
 #define OMAP24XX_NR_MMC         2
 #define OMAP2420_MMC_SIZE       OMAP1_MMC_SIZE
@@ -7,14 +5,6 @@
 #define OMAP4_MMC_REG_OFFSET    0x100
-#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
-void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data);
-#else
-static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
-{
-}
-#endif
 struct omap_hwmod;
 int omap_msdi_reset(struct omap_hwmod *oh);
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 6944ae3674e8..79f49d904a06 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -227,7 +227,7 @@ static void __init save_l2x0_context(void)
 int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 {
        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
-        unsigned int save_state = 0;
+        unsigned int save_state = 0, cpu_logic_state = PWRDM_POWER_RET;
        unsigned int wakeup_cpu;
        if (omap_rev() == OMAP4430_REV_ES1_0)
@@ -239,6 +239,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
                save_state = 0;
                break;
        case PWRDM_POWER_OFF:
+                cpu_logic_state = PWRDM_POWER_OFF;
                save_state = 1;
                break;
        case PWRDM_POWER_RET:
@@ -270,6 +271,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
        cpu_clear_prev_logic_pwrst(cpu);
        pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
+        pwrdm_set_logic_retst(pm_info->pwrdm, cpu_logic_state);
        set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume));
        omap_pm_ops.scu_prepare(cpu, power_state);
        l2x0_pwrst_prepare(cpu, save_state);
diff --git a/arch/arm/mach-omap2/omap2-restart.c b/arch/arm/mach-omap2/omap2-restart.c
index 68423e26399d..d937b2e4040b 100644
--- a/arch/arm/mach-omap2/omap2-restart.c
+++ b/arch/arm/mach-omap2/omap2-restart.c
@@ -15,7 +15,7 @@
 #include "soc.h"
 #include "common.h"
-#include "prm2xxx.h"
+#include "prm.h"
 /*
 * reset_virt_prcm_set_ck, reset_sys_ck: pointers to the virt_prcm_set
@@ -40,8 +40,7 @@ void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
        /* XXX Should save the cmd argument for use after the reboot */
-        omap2xxx_prm_dpll_reset(); /* never returns */
+        omap_prm_reset_system();
-        while (1);
 }
 /**
diff --git a/arch/arm/mach-omap2/omap3-restart.c b/arch/arm/mach-omap2/omap3-restart.c
index 5de2a0c2979d..103a49f68bcb 100644
--- a/arch/arm/mach-omap2/omap3-restart.c
+++ b/arch/arm/mach-omap2/omap3-restart.c
@@ -14,10 +14,8 @@
 #include <linux/init.h>
 #include <linux/reboot.h>
-#include "iomap.h"
-#include "common.h"
 #include "control.h"
-#include "prm3xxx.h"
+#include "prm.h"
 /* Global address base setup code */
@@ -32,6 +30,5 @@
 void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
 {
        omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
-        omap3xxx_prm_dpll3_reset(); /* never returns */
+        omap_prm_reset_system();
-        while (1);
 }
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 16b20cedc38d..b7cb44abe49b 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -36,7 +36,6 @@
 #include "soc.h"
 #include "iomap.h"
 #include "common.h"
-#include "mmc.h"
 #include "prminst44xx.h"
 #include "prcm_mpu44xx.h"
 #include "omap4-sar-layout.h"
diff --git a/arch/arm/mach-omap2/omap4-restart.c b/arch/arm/mach-omap2/omap4-restart.c
index 41dfd7da8170..a99e7f7fb5be 100644
--- a/arch/arm/mach-omap2/omap4-restart.c
+++ b/arch/arm/mach-omap2/omap4-restart.c
@@ -9,7 +9,7 @@
 #include <linux/types.h>
 #include <linux/reboot.h>
-#include "prminst44xx.h"
+#include "prm.h"
 /**
 * omap44xx_restart - trigger a software restart of the SoC
@@ -22,7 +22,5 @@
 void omap44xx_restart(enum reboot_mode mode, const char *cmd)
 {
        /* XXX Should save 'cmd' into scratchpad for use after reboot */
-        omap4_prminst_global_warm_sw_reset(); /* never returns */
+        omap_prm_reset_system();
-        while (1)
-                ;
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 716247ed9e0c..cbb908dc5cf0 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -153,7 +153,6 @@
 #include "powerdomain.h"
 #include "cm2xxx.h"
 #include "cm3xxx.h"
-#include "cminst44xx.h"
 #include "cm33xx.h"
 #include "prm.h"
 #include "prm3xxx.h"
@@ -979,31 +978,9 @@ static void _omap4_enable_module(struct omap_hwmod *oh)
        pr_debug("omap_hwmod: %s: %s: %d\n",
                 oh->name, __func__, oh->prcm.omap4.modulemode);
-        omap4_cminst_module_enable(oh->prcm.omap4.modulemode,
+        omap_cm_module_enable(oh->prcm.omap4.modulemode,
-                                   oh->clkdm->prcm_partition,
+                              oh->clkdm->prcm_partition,
-                                   oh->clkdm->cm_inst,
+                              oh->clkdm->cm_inst, oh->prcm.omap4.clkctrl_offs);
-                                   oh->clkdm->clkdm_offs,
-                                   oh->prcm.omap4.clkctrl_offs);
-}
-/**
- * _am33xx_enable_module - enable CLKCTRL modulemode on AM33XX
- * @oh: struct omap_hwmod *
- *
- * Enables the PRCM module mode related to the hwmod @oh.
- * No return value.
- */
-static void _am33xx_enable_module(struct omap_hwmod *oh)
-{
-        if (!oh->clkdm || !oh->prcm.omap4.modulemode)
-                return;
-        pr_debug("omap_hwmod: %s: %s: %d\n",
-                 oh->name, __func__, oh->prcm.omap4.modulemode);
-        am33xx_cm_module_enable(oh->prcm.omap4.modulemode, oh->clkdm->cm_inst,
-                                oh->clkdm->clkdm_offs,
-                                oh->prcm.omap4.clkctrl_offs);
 }
 /**
@@ -1026,35 +1003,9 @@ static int _omap4_wait_target_disable(struct omap_hwmod *oh)
        if (oh->flags & HWMOD_NO_IDLEST)
                return 0;
-        return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition,
+        return omap_cm_wait_module_idle(oh->clkdm->prcm_partition,
-                                             oh->clkdm->cm_inst,
+                                        oh->clkdm->cm_inst,
-                                             oh->clkdm->clkdm_offs,
+                                        oh->prcm.omap4.clkctrl_offs, 0);
-                                             oh->prcm.omap4.clkctrl_offs);
-}
-/**
- * _am33xx_wait_target_disable - wait for a module to be disabled on AM33XX
- * @oh: struct omap_hwmod *
- *
- * Wait for a module @oh to enter slave idle.  Returns 0 if the module
- * does not have an IDLEST bit or if the module successfully enters
- * slave idle; otherwise, pass along the return value of the
- * appropriate *_cm*_wait_module_idle() function.
- */
-static int _am33xx_wait_target_disable(struct omap_hwmod *oh)
-{
-        if (!oh)
-                return -EINVAL;
-        if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
-                return 0;
-        if (oh->flags & HWMOD_NO_IDLEST)
-                return 0;
-        return am33xx_cm_wait_module_idle(oh->clkdm->cm_inst,
-                                             oh->clkdm->clkdm_offs,
-                                             oh->prcm.omap4.clkctrl_offs);
 }
 /**
@@ -1859,10 +1810,8 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
        pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
-        omap4_cminst_module_disable(oh->clkdm->prcm_partition,
+        omap_cm_module_disable(oh->clkdm->prcm_partition, oh->clkdm->cm_inst,
-                                    oh->clkdm->cm_inst,
+                               oh->prcm.omap4.clkctrl_offs);
-                                    oh->clkdm->clkdm_offs,
-                                    oh->prcm.omap4.clkctrl_offs);
        v = _omap4_wait_target_disable(oh);
        if (v)
@@ -1873,36 +1822,6 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
 }
 /**
- * _am33xx_disable_module - enable CLKCTRL modulemode on AM33XX
- * @oh: struct omap_hwmod *
- *
- * Disable the PRCM module mode related to the hwmod @oh.
- * Return EINVAL if the modulemode is not supported and 0 in case of success.
- */
-static int _am33xx_disable_module(struct omap_hwmod *oh)
-{
-        int v;
-        if (!oh->clkdm || !oh->prcm.omap4.modulemode)
-                return -EINVAL;
-        pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
-        if (_are_any_hardreset_lines_asserted(oh))
-                return 0;
-        am33xx_cm_module_disable(oh->clkdm->cm_inst, oh->clkdm->clkdm_offs,
-                                 oh->prcm.omap4.clkctrl_offs);
-        v = _am33xx_wait_target_disable(oh);
-        if (v)
-                pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
-                        oh->name);
-        return 0;
-}
-/**
 * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit
 * @oh: struct omap_hwmod *
 *
@@ -2065,10 +1984,7 @@ static void _reconfigure_io_chain(void)
        spin_lock_irqsave(&io_chain_lock, flags);
-        if (cpu_is_omap34xx())
+        omap_prm_reconfigure_io_chain();
-                omap3xxx_prm_reconfigure_io_chain();
-        else if (cpu_is_omap44xx())
-                omap44xx_prm_reconfigure_io_chain();
        spin_unlock_irqrestore(&io_chain_lock, flags);
 }
@@ -2719,11 +2635,33 @@ static int __init _setup(struct omap_hwmod *oh, void *data)
        if (oh->_state != _HWMOD_STATE_INITIALIZED)
                return 0;
+        if (oh->parent_hwmod) {
+                int r;
+                r = _enable(oh->parent_hwmod);
+                WARN(r, "hwmod: %s: setup: failed to enable parent hwmod %s\n",
+                     oh->name, oh->parent_hwmod->name);
+        }
        _setup_iclk_autoidle(oh);
        if (!_setup_reset(oh))
                _setup_postsetup(oh);
+        if (oh->parent_hwmod) {
+                u8 postsetup_state;
+                postsetup_state = oh->parent_hwmod->_postsetup_state;
+                if (postsetup_state == _HWMOD_STATE_IDLE)
+                        _idle(oh->parent_hwmod);
+                else if (postsetup_state == _HWMOD_STATE_DISABLED)
+                        _shutdown(oh->parent_hwmod);
+                else if (postsetup_state != _HWMOD_STATE_ENABLED)
+                        WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n",
+                             oh->parent_hwmod->name, postsetup_state);
+        }
        return 0;
 }
@@ -2832,12 +2770,10 @@ static int __init _add_link(struct omap_hwmod_ocp_if *oi)
        _alloc_links(&ml, &sl);
        ml->ocp_if = oi;
-        INIT_LIST_HEAD(&ml->node);
        list_add(&ml->node, &oi->master->master_ports);
        oi->master->masters_cnt++;
        sl->ocp_if = oi;
-        INIT_LIST_HEAD(&sl->node);
        list_add(&sl->node, &oi->slave->slave_ports);
        oi->slave->slaves_cnt++;
@@ -2927,34 +2863,7 @@ static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois)
 /* Static functions intended only for use in soc_ops field function pointers */
 /**
- * _omap2xxx_wait_target_ready - wait for a module to leave slave idle
+ * _omap2xxx_3xxx_wait_target_ready - wait for a module to leave slave idle
- * @oh: struct omap_hwmod *
- *
- * Wait for a module @oh to leave slave idle.  Returns 0 if the module
- * does not have an IDLEST bit or if the module successfully leaves
- * slave idle; otherwise, pass along the return value of the
- * appropriate *_cm*_wait_module_ready() function.
- */
-static int _omap2xxx_wait_target_ready(struct omap_hwmod *oh)
-{
-        if (!oh)
-                return -EINVAL;
-        if (oh->flags & HWMOD_NO_IDLEST)
-                return 0;
-        if (!_find_mpu_rt_port(oh))
-                return 0;
-        /* XXX check module SIDLEMODE, hardreset status, enabled clocks */
-        return omap2xxx_cm_wait_module_ready(oh->prcm.omap2.module_offs,
-                                             oh->prcm.omap2.idlest_reg_id,
-                                             oh->prcm.omap2.idlest_idle_bit);
-}
-/**
- * _omap3xxx_wait_target_ready - wait for a module to leave slave idle
 * @oh: struct omap_hwmod *
 *
 * Wait for a module @oh to leave slave idle.  Returns 0 if the module
@@ -2962,7 +2871,7 @@ static int _omap2xxx_wait_target_ready(struct omap_hwmod *oh)
 * slave idle; otherwise, pass along the return value of the
 * appropriate *_cm*_wait_module_ready() function.
 */
-static int _omap3xxx_wait_target_ready(struct omap_hwmod *oh)
+static int _omap2xxx_3xxx_wait_target_ready(struct omap_hwmod *oh)
 {
        if (!oh)
                return -EINVAL;
@@ -2975,9 +2884,9 @@ static int _omap3xxx_wait_target_ready(struct omap_hwmod *oh)
        /* XXX check module SIDLEMODE, hardreset status, enabled clocks */
-        return omap3xxx_cm_wait_module_ready(oh->prcm.omap2.module_offs,
+        return omap_cm_wait_module_ready(0, oh->prcm.omap2.module_offs,
-                                             oh->prcm.omap2.idlest_reg_id,
+                                         oh->prcm.omap2.idlest_reg_id,
-                                             oh->prcm.omap2.idlest_idle_bit);
+                                         oh->prcm.omap2.idlest_idle_bit);
 }
 /**
@@ -3002,37 +2911,9 @@ static int _omap4_wait_target_ready(struct omap_hwmod *oh)
        /* XXX check module SIDLEMODE, hardreset status */
-        return omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition,
+        return omap_cm_wait_module_ready(oh->clkdm->prcm_partition,
-                                              oh->clkdm->cm_inst,
+                                         oh->clkdm->cm_inst,
-                                              oh->clkdm->clkdm_offs,
+                                         oh->prcm.omap4.clkctrl_offs, 0);
-                                              oh->prcm.omap4.clkctrl_offs);
-}
-/**
- * _am33xx_wait_target_ready - wait for a module to leave slave idle
- * @oh: struct omap_hwmod *
- *
- * Wait for a module @oh to leave slave idle.  Returns 0 if the module
- * does not have an IDLEST bit or if the module successfully leaves
- * slave idle; otherwise, pass along the return value of the
- * appropriate *_cm*_wait_module_ready() function.
- */
-static int _am33xx_wait_target_ready(struct omap_hwmod *oh)
-{
-        if (!oh || !oh->clkdm)
-                return -EINVAL;
-        if (oh->flags & HWMOD_NO_IDLEST)
-                return 0;
-        if (!_find_mpu_rt_port(oh))
-                return 0;
-        /* XXX check module SIDLEMODE, hardreset status */
-        return am33xx_cm_wait_module_ready(oh->clkdm->cm_inst,
-                                              oh->clkdm->clkdm_offs,
-                                              oh->prcm.omap4.clkctrl_offs);
 }
 /**
@@ -3049,8 +2930,8 @@ static int _am33xx_wait_target_ready(struct omap_hwmod *oh)
 static int _omap2_assert_hardreset(struct omap_hwmod *oh,
                                   struct omap_hwmod_rst_info *ohri)
 {
-        return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
+        return omap_prm_assert_hardreset(ohri->rst_shift, 0,
-                                          ohri->rst_shift);
+                                         oh->prcm.omap2.module_offs, 0);
 }
 /**
@@ -3067,9 +2948,8 @@ static int _omap2_assert_hardreset(struct omap_hwmod *oh,
 static int _omap2_deassert_hardreset(struct omap_hwmod *oh,
                                     struct omap_hwmod_rst_info *ohri)
 {
-        return omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
+        return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, 0,
-                                            ohri->rst_shift,
+                                           oh->prcm.omap2.module_offs, 0, 0);
-                                            ohri->st_shift);
 }
 /**
@@ -3087,8 +2967,8 @@ static int _omap2_deassert_hardreset(struct omap_hwmod *oh,
 static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh,
                                        struct omap_hwmod_rst_info *ohri)
 {
-        return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
+        return omap_prm_is_hardreset_asserted(ohri->st_shift, 0,
-                                               ohri->st_shift);
+                                              oh->prcm.omap2.module_offs, 0);
 }
 /**
@@ -3109,10 +2989,10 @@ static int _omap4_assert_hardreset(struct omap_hwmod *oh,
        if (!oh->clkdm)
                return -EINVAL;
-        return omap4_prminst_assert_hardreset(ohri->rst_shift,
+        return omap_prm_assert_hardreset(ohri->rst_shift,
-                                oh->clkdm->pwrdm.ptr->prcm_partition,
+                                         oh->clkdm->pwrdm.ptr->prcm_partition,
-                                oh->clkdm->pwrdm.ptr->prcm_offs,
+                                         oh->clkdm->pwrdm.ptr->prcm_offs,
-                                oh->prcm.omap4.rstctrl_offs);
+                                         oh->prcm.omap4.rstctrl_offs);
 }
 /**
@@ -3136,10 +3016,10 @@ static int _omap4_deassert_hardreset(struct omap_hwmod *oh,
        if (ohri->st_shift)
                pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
                       oh->name, ohri->name);
-        return omap4_prminst_deassert_hardreset(ohri->rst_shift,
+        return omap_prm_deassert_hardreset(ohri->rst_shift, 0,
-                                oh->clkdm->pwrdm.ptr->prcm_partition,
+                                           oh->clkdm->pwrdm.ptr->prcm_partition,
-                                oh->clkdm->pwrdm.ptr->prcm_offs,
+                                           oh->clkdm->pwrdm.ptr->prcm_offs,
-                                oh->prcm.omap4.rstctrl_offs);
+                                           oh->prcm.omap4.rstctrl_offs, 0);
 }
 /**
@@ -3160,10 +3040,11 @@ static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh,
        if (!oh->clkdm)
                return -EINVAL;
-        return omap4_prminst_is_hardreset_asserted(ohri->rst_shift,
+        return omap_prm_is_hardreset_asserted(ohri->rst_shift,
-                                oh->clkdm->pwrdm.ptr->prcm_partition,
+                                              oh->clkdm->pwrdm.ptr->
-                                oh->clkdm->pwrdm.ptr->prcm_offs,
+                                              prcm_partition,
-                                oh->prcm.omap4.rstctrl_offs);
+                                              oh->clkdm->pwrdm.ptr->prcm_offs,
+                                              oh->prcm.omap4.rstctrl_offs);
 }
 /**
@@ -3182,9 +3063,9 @@ static int _am33xx_assert_hardreset(struct omap_hwmod *oh,
                                   struct omap_hwmod_rst_info *ohri)
 {
-        return am33xx_prm_assert_hardreset(ohri->rst_shift,
+        return omap_prm_assert_hardreset(ohri->rst_shift, 0,
-                                oh->clkdm->pwrdm.ptr->prcm_offs,
+                                         oh->clkdm->pwrdm.ptr->prcm_offs,
-                                oh->prcm.omap4.rstctrl_offs);
+                                         oh->prcm.omap4.rstctrl_offs);
 }
 /**
@@ -3202,11 +3083,10 @@ static int _am33xx_assert_hardreset(struct omap_hwmod *oh,
 static int _am33xx_deassert_hardreset(struct omap_hwmod *oh,
                                     struct omap_hwmod_rst_info *ohri)
 {
-        return am33xx_prm_deassert_hardreset(ohri->rst_shift,
+        return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, 0,
-                                ohri->st_shift,
+                                           oh->clkdm->pwrdm.ptr->prcm_offs,
-                                oh->clkdm->pwrdm.ptr->prcm_offs,
+                                           oh->prcm.omap4.rstctrl_offs,
-                                oh->prcm.omap4.rstctrl_offs,
+                                           oh->prcm.omap4.rstst_offs);
-                                oh->prcm.omap4.rstst_offs);
 }
 /**
@@ -3224,9 +3104,9 @@ static int _am33xx_deassert_hardreset(struct omap_hwmod *oh,
 static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh,
                                        struct omap_hwmod_rst_info *ohri)
 {
-        return am33xx_prm_is_hardreset_asserted(ohri->rst_shift,
+        return omap_prm_is_hardreset_asserted(ohri->rst_shift, 0,
-                                oh->clkdm->pwrdm.ptr->prcm_offs,
+                                              oh->clkdm->pwrdm.ptr->prcm_offs,
-                                oh->prcm.omap4.rstctrl_offs);
+                                              oh->prcm.omap4.rstctrl_offs);
 }
 /* Public functions */
@@ -4234,12 +4114,12 @@ int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx)
 void __init omap_hwmod_init(void)
 {
        if (cpu_is_omap24xx()) {
-                soc_ops.wait_target_ready = _omap2xxx_wait_target_ready;
+                soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready;
                soc_ops.assert_hardreset = _omap2_assert_hardreset;
                soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
                soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
        } else if (cpu_is_omap34xx()) {
-                soc_ops.wait_target_ready = _omap3xxx_wait_target_ready;
+                soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready;
                soc_ops.assert_hardreset = _omap2_assert_hardreset;
                soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
                soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
@@ -4258,14 +4138,14 @@ void __init omap_hwmod_init(void)
                soc_ops.enable_module = _omap4_enable_module;
                soc_ops.disable_module = _omap4_disable_module;
                soc_ops.wait_target_ready = _omap4_wait_target_ready;
-                soc_ops.assert_hardreset = _am33xx_assert_hardreset;
+                soc_ops.assert_hardreset = _omap4_assert_hardreset;
-                soc_ops.deassert_hardreset = _am33xx_deassert_hardreset;
+                soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
-                soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted;
+                soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
                soc_ops.init_clkdm = _init_clkdm;
        } else if (soc_is_am33xx()) {
-                soc_ops.enable_module = _am33xx_enable_module;
+                soc_ops.enable_module = _omap4_enable_module;
-                soc_ops.disable_module = _am33xx_disable_module;
+                soc_ops.disable_module = _omap4_disable_module;
-                soc_ops.wait_target_ready = _am33xx_wait_target_ready;
+                soc_ops.wait_target_ready = _omap4_wait_target_ready;
                soc_ops.assert_hardreset = _am33xx_assert_hardreset;
                soc_ops.deassert_hardreset = _am33xx_deassert_hardreset;
                soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted;
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 512f809a3f4d..35ca6efbec31 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -633,6 +633,7 @@ struct omap_hwmod_link {
 * @flags: hwmod flags (documented below)
 * @_lock: spinlock serializing operations on this hwmod
 * @node: list node for hwmod list (internal use)
+ * @parent_hwmod: (temporary) a pointer to the hierarchical parent of this hwmod
 *
 * @main_clk refers to this module's "main clock," which for our
 * purposes is defined as "the functional clock needed for register
@@ -643,6 +644,12 @@ struct omap_hwmod_link {
 * the omap_hwmod code and should not be set during initialization.
 *
 * @masters and @slaves are now deprecated.
+ *
+ * @parent_hwmod is temporary; there should be no need for it, as this
+ * information should already be expressed in the OCP interface
+ * structures.  @parent_hwmod is present as a workaround until we improve
+ * handling for hwmods with multiple parents (e.g., OMAP4+ DSS with
+ * multiple register targets across different interconnects).
 */
 struct omap_hwmod {
        const char                      *name;
@@ -680,6 +687,7 @@ struct omap_hwmod {
        u8                              _int_flags;
        u8                              _state;
        u8                              _postsetup_state;
+        struct omap_hwmod               *parent_hwmod;
 };
 struct omap_hwmod *omap_hwmod_lookup(const char *name);
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index c2555cb95e71..79127b35fe60 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -15,12 +15,12 @@
 #include <linux/i2c-omap.h>
 #include <linux/platform_data/asoc-ti-mcbsp.h>
+#include <linux/platform_data/hsmmc-omap.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/omap-dma.h>
 #include <plat/dmtimer.h>
 #include "omap_hwmod.h"
-#include "mmc.h"
 #include "l3_2xxx.h"
 #include "soc.h"
@@ -372,7 +372,7 @@ static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
        { .role = "dbck", .clk = "mmchsdb1_fck" },
 };
-static struct omap_mmc_dev_attr mmc1_dev_attr = {
+static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
        .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
index a579b89ce9b7..cabc5695b504 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
@@ -15,10 +15,10 @@
 */
 #include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/hsmmc-omap.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include "omap_hwmod.h"
 #include "i2c.h"
-#include "mmc.h"
 #include "wd_timer.h"
 #include "cm33xx.h"
 #include "prm33xx.h"
@@ -836,7 +836,7 @@ static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
 };
 /* mmc0 */
-static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
+static struct omap_hsmmc_dev_attr am33xx_mmc0_dev_attr = {
        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
@@ -854,7 +854,7 @@ struct omap_hwmod am33xx_mmc0_hwmod = {
 };
 /* mmc1 */
-static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
+static struct omap_hsmmc_dev_attr am33xx_mmc1_dev_attr = {
        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
@@ -872,7 +872,7 @@ struct omap_hwmod am33xx_mmc1_hwmod = {
 };
 /* mmc2 */
-static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
+static struct omap_hsmmc_dev_attr am33xx_mmc2_dev_attr = {
        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
 struct omap_hwmod am33xx_mmc2_hwmod = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 6b406ca4bd3b..0cf7b563dcd1 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -27,7 +27,6 @@
 #include "prm33xx.h"
 #include "prm-regbits-33xx.h"
 #include "i2c.h"
-#include "mmc.h"
 #include "wd_timer.h"
 #include "omap_hwmod_33xx_43xx_common_data.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 2a78b093c0ce..11468eea3871 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -18,6 +18,7 @@
 #include <linux/i2c-omap.h>
 #include <linux/power/smartreflex.h>
 #include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/hsmmc-omap.h>
 #include <linux/omap-dma.h>
 #include "l3_3xxx.h"
@@ -37,7 +38,6 @@
 #include "cm-regbits-34xx.h"
 #include "i2c.h"
-#include "mmc.h"
 #include "wd_timer.h"
 #include "serial.h"
@@ -1786,12 +1786,12 @@ static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
        { .role = "dbck", .clk = "omap_32k_fck", },
 };
-static struct omap_mmc_dev_attr mmc1_dev_attr = {
+static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
        .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
 /* See 35xx errata 2.1.1.128 in SPRZ278F */
-static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
+static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = {
        .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
                  OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
 };
@@ -1854,7 +1854,7 @@ static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
 };
 /* See 35xx errata 2.1.1.128 in SPRZ278F */
-static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
+static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = {
        .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
index fea01aa3ef42..5c6c8410160e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -417,6 +417,37 @@ static struct omap_hwmod am43xx_qspi_hwmod = {
        },
 };
+/*
+ * 'adc/tsc' class
+ * TouchScreen Controller (Analog-To-Digital Converter)
+ */
+static struct omap_hwmod_class_sysconfig am43xx_adc_tsc_sysc = {
+        .rev_offs       = 0x00,
+        .sysc_offs      = 0x10,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+static struct omap_hwmod_class am43xx_adc_tsc_hwmod_class = {
+        .name           = "adc_tsc",
+        .sysc           = &am43xx_adc_tsc_sysc,
+};
+static struct omap_hwmod am43xx_adc_tsc_hwmod = {
+        .name           = "adc_tsc",
+        .class          = &am43xx_adc_tsc_hwmod_class,
+        .clkdm_name     = "l3s_tsc_clkdm",
+        .main_clk       = "adc_tsc_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
 /* dss */
 static struct omap_hwmod am43xx_dss_core_hwmod = {
@@ -547,6 +578,13 @@ static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
+static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am43xx_adc_tsc_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .user           = OCP_USER_MPU,
+};
 static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
        .master         = &am43xx_l4_hs_hwmod,
        .slave          = &am33xx_cpgmac0_hwmod,
@@ -789,6 +827,7 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
        &am43xx_l4_wkup__i2c1,
        &am43xx_l4_wkup__gpio0,
        &am43xx_l4_wkup__wd_timer1,
+        &am43xx_l4_wkup__adc_tsc,
        &am43xx_l3_s__qspi,
        &am33xx_l4_per__dcan0,
        &am33xx_l4_per__dcan1,
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 44e5634bba34..c314b3c31117 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/hsmmc-omap.h>
 #include <linux/power/smartreflex.h>
 #include <linux/i2c-omap.h>
@@ -39,7 +40,6 @@
 #include "prm44xx.h"
 #include "prm-regbits-44xx.h"
 #include "i2c.h"
-#include "mmc.h"
 #include "wd_timer.h"
 /* Base offset for all OMAP4 interrupts external to MPUSS */
@@ -589,6 +589,7 @@ static struct omap_hwmod omap44xx_dss_hwmod = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
                        .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
        .opt_clks       = dss_opt_clks,
@@ -647,7 +648,8 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
                        .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
                },
        },
-        .dev_attr       = &omap44xx_dss_dispc_dev_attr
+        .dev_attr       = &omap44xx_dss_dispc_dev_attr,
+        .parent_hwmod   = &omap44xx_dss_hwmod,
 };
 /*
@@ -701,6 +703,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
        },
        .opt_clks       = dss_dsi1_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
+        .parent_hwmod   = &omap44xx_dss_hwmod,
 };
 /* dss_dsi2 */
@@ -733,6 +736,7 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
        },
        .opt_clks       = dss_dsi2_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
+        .parent_hwmod   = &omap44xx_dss_hwmod,
 };
 /*
@@ -790,6 +794,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
        },
        .opt_clks       = dss_hdmi_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
+        .parent_hwmod   = &omap44xx_dss_hwmod,
 };
 /*
@@ -819,7 +824,7 @@ static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 };
 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
-        { .role = "ick", .clk = "dss_fck" },
+        { .role = "ick", .clk = "l3_div_ck" },
 };
 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
@@ -836,6 +841,7 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
        },
        .opt_clks       = dss_rfbi_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
+        .parent_hwmod   = &omap44xx_dss_hwmod,
 };
 /*
@@ -859,6 +865,7 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
                        .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
                },
        },
+        .parent_hwmod   = &omap44xx_dss_hwmod,
 };
 /*
@@ -1952,7 +1959,7 @@ static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
 };
 /* mmc1 dev_attr */
-static struct omap_mmc_dev_attr mmc1_dev_attr = {
+static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
        .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
@@ -3671,7 +3678,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
        .master         = &omap44xx_l3_main_2_hwmod,
        .slave          = &omap44xx_dss_hwmod,
-        .clk            = "dss_fck",
+        .clk            = "l3_div_ck",
        .addr           = omap44xx_dss_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
@@ -3707,7 +3714,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
        .master         = &omap44xx_l3_main_2_hwmod,
        .slave          = &omap44xx_dss_dispc_hwmod,
-        .clk            = "dss_fck",
+        .clk            = "l3_div_ck",
        .addr           = omap44xx_dss_dispc_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
@@ -3743,7 +3750,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
        .master         = &omap44xx_l3_main_2_hwmod,
        .slave          = &omap44xx_dss_dsi1_hwmod,
-        .clk            = "dss_fck",
+        .clk            = "l3_div_ck",
        .addr           = omap44xx_dss_dsi1_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
@@ -3779,7 +3786,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
        .master         = &omap44xx_l3_main_2_hwmod,
        .slave          = &omap44xx_dss_dsi2_hwmod,
-        .clk            = "dss_fck",
+        .clk            = "l3_div_ck",
        .addr           = omap44xx_dss_dsi2_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
@@ -3815,7 +3822,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
        .master         = &omap44xx_l3_main_2_hwmod,
        .slave          = &omap44xx_dss_hdmi_hwmod,
-        .clk            = "dss_fck",
+        .clk            = "l3_div_ck",
        .addr           = omap44xx_dss_hdmi_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
@@ -3851,7 +3858,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
        .master         = &omap44xx_l3_main_2_hwmod,
        .slave          = &omap44xx_dss_rfbi_hwmod,
-        .clk            = "dss_fck",
+        .clk            = "l3_div_ck",
        .addr           = omap44xx_dss_rfbi_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
@@ -3887,7 +3894,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
        .master         = &omap44xx_l3_main_2_hwmod,
        .slave          = &omap44xx_dss_venc_hwmod,
-        .clk            = "dss_fck",
+        .clk            = "l3_div_ck",
        .addr           = omap44xx_dss_venc_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index 1103aa0e0d29..3e9523084b2a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -19,6 +19,7 @@
 #include <linux/io.h>
 #include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/hsmmc-omap.h>
 #include <linux/power/smartreflex.h>
 #include <linux/i2c-omap.h>
@@ -33,7 +34,6 @@
 #include "cm2_54xx.h"
 #include "prm54xx.h"
 #include "i2c.h"
-#include "mmc.h"
 #include "wd_timer.h"
 /* Base offset for all OMAP5 interrupts external to MPUSS */
@@ -421,6 +421,7 @@ static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
        .opt_clks       = dss_dispc_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
        .dev_attr       = &dss_dispc_dev_attr,
+        .parent_hwmod   = &omap54xx_dss_hwmod,
 };
 /*
@@ -462,6 +463,7 @@ static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
        },
        .opt_clks       = dss_dsi1_a_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_a_opt_clks),
+        .parent_hwmod   = &omap54xx_dss_hwmod,
 };
 /* dss_dsi1_c */
@@ -482,6 +484,7 @@ static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
        },
        .opt_clks       = dss_dsi1_c_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_c_opt_clks),
+        .parent_hwmod   = &omap54xx_dss_hwmod,
 };
 /*
@@ -521,6 +524,7 @@ static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
        },
        .opt_clks       = dss_hdmi_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
+        .parent_hwmod   = &omap54xx_dss_hwmod,
 };
 /*
@@ -560,6 +564,7 @@ static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
        },
        .opt_clks       = dss_rfbi_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
+        .parent_hwmod   = &omap54xx_dss_hwmod,
 };
 /*
@@ -1269,7 +1274,7 @@ static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
 };
 /* mmc1 dev_attr */
-static struct omap_mmc_dev_attr mmc1_dev_attr = {
+static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
        .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 5684f112654b..ffd6604cd546 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -19,6 +19,7 @@
 #include <linux/io.h>
 #include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/hsmmc-omap.h>
 #include <linux/power/smartreflex.h>
 #include <linux/i2c-omap.h>
@@ -33,7 +34,6 @@
 #include "cm2_7xx.h"
 #include "prm7xx.h"
 #include "i2c.h"
-#include "mmc.h"
 #include "wd_timer.h"
 #include "soc.h"
@@ -1301,7 +1301,7 @@ static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
 };
 /* mmc1 dev_attr */
-static struct omap_mmc_dev_attr mmc1_dev_attr = {
+static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
        .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
@@ -2075,6 +2075,70 @@ static struct omap_hwmod dra7xx_uart6_hwmod = {
        },
 };
+/* uart7 */
+static struct omap_hwmod dra7xx_uart7_hwmod = {
+        .name           = "uart7",
+        .class          = &dra7xx_uart_hwmod_class,
+        .clkdm_name     = "l4per2_clkdm",
+        .main_clk       = "uart7_gfclk_mux",
+        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* uart8 */
+static struct omap_hwmod dra7xx_uart8_hwmod = {
+        .name           = "uart8",
+        .class          = &dra7xx_uart_hwmod_class,
+        .clkdm_name     = "l4per2_clkdm",
+        .main_clk       = "uart8_gfclk_mux",
+        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* uart9 */
+static struct omap_hwmod dra7xx_uart9_hwmod = {
+        .name           = "uart9",
+        .class          = &dra7xx_uart_hwmod_class,
+        .clkdm_name     = "l4per2_clkdm",
+        .main_clk       = "uart9_gfclk_mux",
+        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/* uart10 */
+static struct omap_hwmod dra7xx_uart10_hwmod = {
+        .name           = "uart10",
+        .class          = &dra7xx_uart_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .main_clk       = "uart10_gfclk_mux",
+        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
 /*
 * 'usb_otg_ss' class
 *
@@ -3095,6 +3159,38 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
+/* l4_per2 -> uart7 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
+        .master         = &dra7xx_l4_per2_hwmod,
+        .slave          = &dra7xx_uart7_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per2 -> uart8 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
+        .master         = &dra7xx_l4_per2_hwmod,
+        .slave          = &dra7xx_uart8_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per2 -> uart9 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
+        .master         = &dra7xx_l4_per2_hwmod,
+        .slave          = &dra7xx_uart9_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_wkup -> uart10 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
+        .master         = &dra7xx_l4_wkup_hwmod,
+        .slave          = &dra7xx_uart10_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
 /* l4_per3 -> usb_otg_ss1 */
 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
        .master         = &dra7xx_l4_per3_hwmod,
@@ -3259,6 +3355,10 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
        &dra7xx_l4_per1__uart4,
        &dra7xx_l4_per1__uart5,
        &dra7xx_l4_per1__uart6,
+        &dra7xx_l4_per2__uart7,
+        &dra7xx_l4_per2__uart8,
+        &dra7xx_l4_per2__uart9,
+        &dra7xx_l4_wkup__uart10,
        &dra7xx_l4_per3__usb_otg_ss1,
        &dra7xx_l4_per3__usb_otg_ss2,
        &dra7xx_l4_per3__usb_otg_ss3,
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index 50640b38f0bf..1a19fa096bab 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -21,6 +21,8 @@
  *
  */
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 #include <linux/types.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
@@ -97,13 +99,13 @@ void am35x_musb_phy_power(u8 on)
                omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
-                pr_info(KERN_INFO "Waiting for PHY clock good...\n");
+                pr_info("Waiting for PHY clock good...\n");
                while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
                                & CONF2_PHYCLKGD)) {
                        cpu_relax();
                        if (time_after(jiffies, timeout)) {
-                                pr_err(KERN_ERR "musb PHY clock good timed out\n");
+                                pr_err("musb PHY clock good timed out\n");
                                break;
                        }
                }
@@ -145,7 +147,7 @@ void am35x_set_mode(u8 musb_mode)
                devconf2 |= CONF2_NO_OVERRIDE;
                break;
        default:
-                pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);
+                pr_info("Unsupported mode %u\n", musb_mode);
        }
        omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index cec9d6c6442c..3d7eee1d3cfa 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -13,6 +13,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
+#include <linux/ti_wilink_st.h>
 #include <linux/wl12xx.h>
 #include <linux/platform_data/pinctrl-single.h>
@@ -130,17 +131,45 @@ static void __init omap3_sbc_t3730_legacy_init(void)
 {
        omap3_sbc_t3x_usb_hub_init(167, "sb-t35 usb hub");
        legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 136);
-        omap_ads7846_init(1, 57, 0, NULL);
 }
 static void __init omap3_sbc_t3530_legacy_init(void)
 {
        omap3_sbc_t3x_usb_hub_init(167, "sb-t35 usb hub");
-        omap_ads7846_init(1, 57, 0, NULL);
 }
-static void __init omap3_igep0020_legacy_init(void)
+struct ti_st_plat_data wilink_pdata = {
+        .nshutdown_gpio = 137,
+        .dev_name = "/dev/ttyO1",
+        .flow_cntrl = 1,
+        .baud_rate = 300000,
+};
+static struct platform_device wl18xx_device = {
+        .name   = "kim",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &wilink_pdata,
+        }
+};
+static struct platform_device btwilink_device = {
+        .name   = "btwilink",
+        .id     = -1,
+};
+static void __init omap3_igep0020_rev_f_legacy_init(void)
+{
+        legacy_init_wl12xx(0, 0, 177);
+        platform_device_register(&wl18xx_device);
+        platform_device_register(&btwilink_device);
+}
+static void __init omap3_igep0030_rev_g_legacy_init(void)
 {
+        legacy_init_wl12xx(0, 0, 136);
+        platform_device_register(&wl18xx_device);
+        platform_device_register(&btwilink_device);
 }
 static void __init omap3_evm_legacy_init(void)
@@ -218,7 +247,6 @@ static void __init omap3_sbc_t3517_legacy_init(void)
        hsmmc2_internal_input_clk();
        omap3_sbc_t3517_wifi_init();
        legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 145);
-        omap_ads7846_init(1, 57, 0, NULL);
 }
 static void __init am3517_evm_legacy_init(void)
@@ -390,7 +418,8 @@ static struct pdata_init pdata_quirks[] __initdata = {
        { "nokia,omap3-n900", nokia_n900_legacy_init, },
        { "nokia,omap3-n9", hsmmc2_internal_input_clk, },
        { "nokia,omap3-n950", hsmmc2_internal_input_clk, },
-        { "isee,omap3-igep0020", omap3_igep0020_legacy_init, },
+        { "isee,omap3-igep0020-rev-f", omap3_igep0020_rev_f_legacy_init, },
+        { "isee,omap3-igep0030-rev-g", omap3_igep0030_rev_g_legacy_init, },
        { "ti,omap3-evm-37xx", omap3_evm_legacy_init, },
        { "ti,omap3-zoom3", omap3_zoom_legacy_init, },
        { "ti,am3517-evm", am3517_evm_legacy_init, },
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 175564c88a30..88721df6001d 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -29,6 +29,7 @@
 #include <linux/delay.h>
 #include <linux/slab.h>
 #include <linux/omap-dma.h>
+#include <linux/omap-gpmc.h>
 #include <linux/platform_data/gpio-omap.h>
 #include <trace/events/power.h>
@@ -43,7 +44,6 @@
 #include "common.h"
 #include "cm3xxx.h"
 #include "cm-regbits-34xx.h"
-#include "gpmc.h"
 #include "prm-regbits-34xx.h"
 #include "prm3xxx.h"
 #include "pm.h"
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 503097c72b82..d697cecf762b 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -37,6 +37,16 @@ struct power_state {
        struct list_head node;
 };
+/**
+ * struct static_dep_map - Static dependency map
+ * @from:       from clockdomain
+ * @to:         to clockdomain
+  */
+struct static_dep_map {
+        const char *from;
+        const char *to;
+};
 static u32 cpu_suspend_state = PWRDM_POWER_OFF;
 static LIST_HEAD(pwrst_list);
@@ -148,94 +158,61 @@ static void omap_default_idle(void)
        omap_do_wfi();
 }
-/**
+/*
- * omap4_init_static_deps - Add OMAP4 static dependencies
+ * The dynamic dependency between MPUSS -> MEMIF and
- *
+ * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
- * Add needed static clockdomain dependencies on OMAP4 devices.
+ * expected. The hardware recommendation is to enable static
- * Return: 0 on success or 'err' on failures
+ * dependencies for these to avoid system lock ups or random crashes.
+ * The L4 wakeup depedency is added to workaround the OCP sync hardware
+ * BUG with 32K synctimer which lead to incorrect timer value read
+ * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
+ * are part of L4 wakeup clockdomain.
 */
-static inline int omap4_init_static_deps(void)
+static const struct static_dep_map omap4_static_dep_map[] = {
-{
+        {.from = "mpuss_clkdm", .to = "l3_emif_clkdm"},
-        struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
+        {.from = "mpuss_clkdm", .to = "l3_1_clkdm"},
-        struct clockdomain *ducati_clkdm, *l3_2_clkdm;
+        {.from = "mpuss_clkdm", .to = "l3_2_clkdm"},
-        int ret = 0;
+        {.from = "ducati_clkdm", .to = "l3_1_clkdm"},
+        {.from = "ducati_clkdm", .to = "l3_2_clkdm"},
-        if (omap_rev() == OMAP4430_REV_ES1_0) {
+        {.from  = NULL} /* TERMINATION */
-                WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
+};
-                return -ENODEV;
-        }
-        pr_err("Power Management for TI OMAP4.\n");
-        /*
-         * OMAP4 chip PM currently works only with certain (newer)
-         * versions of bootloaders. This is due to missing code in the
-         * kernel to properly reset and initialize some devices.
-         * http://www.spinics.net/lists/arm-kernel/msg218641.html
-         */
-        pr_warn("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n");
-        ret = pwrdm_for_each(pwrdms_setup, NULL);
-        if (ret) {
-                pr_err("Failed to setup powerdomains\n");
-                return ret;
-        }
-        /*
-         * The dynamic dependency between MPUSS -> MEMIF and
-         * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
-         * expected. The hardware recommendation is to enable static
-         * dependencies for these to avoid system lock ups or random crashes.
-         * The L4 wakeup depedency is added to workaround the OCP sync hardware
-         * BUG with 32K synctimer which lead to incorrect timer value read
-         * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
-         * are part of L4 wakeup clockdomain.
-         */
-        mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
-        emif_clkdm = clkdm_lookup("l3_emif_clkdm");
-        l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
-        l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
-        ducati_clkdm = clkdm_lookup("ducati_clkdm");
-        if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
-                (!l3_2_clkdm) || (!ducati_clkdm))
-                return -EINVAL;
-        ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
-        ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
-        ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
-        ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
-        ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
-        if (ret) {
-                pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n");
-                return -EINVAL;
-        }
-        return ret;
+static const struct static_dep_map omap5_dra7_static_dep_map[] = {
-}
+        {.from = "mpu_clkdm", .to = "emif_clkdm"},
+        {.from  = NULL} /* TERMINATION */
+};
 /**
- * omap5_dra7_init_static_deps - Init static clkdm dependencies on OMAP5 and
+ * omap4plus_init_static_deps() - Initialize a static dependency map
- *                               DRA7
+ * @map:        Mapping of clock domains
- *
- * The dynamic dependency between MPUSS -> EMIF is broken and has
- * not worked as expected. The hardware recommendation is to
- * enable static dependencies for these to avoid system
- * lock ups or random crashes.
 */
-static inline int omap5_dra7_init_static_deps(void)
+static inline int omap4plus_init_static_deps(const struct static_dep_map *map)
 {
-        struct clockdomain *mpuss_clkdm, *emif_clkdm;
        int ret;
+        struct clockdomain *from, *to;
+        if (!map)
+                return 0;
-        mpuss_clkdm = clkdm_lookup("mpu_clkdm");
+        while (map->from) {
-        emif_clkdm = clkdm_lookup("emif_clkdm");
+                from = clkdm_lookup(map->from);
-        if (!mpuss_clkdm || !emif_clkdm)
+                to = clkdm_lookup(map->to);
-                return -EINVAL;
+                if (!from || !to) {
+                        pr_err("Failed lookup %s or %s for wakeup dependency\n",
+                               map->from, map->to);
+                        return -EINVAL;
+                }
+                ret = clkdm_add_wkdep(from, to);
+                if (ret) {
+                        pr_err("Failed to add %s -> %s wakeup dependency(%d)\n",
+                               map->from, map->to, ret);
+                        return ret;
+                }
-        ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
+                map++;
-        if (ret)
+        };
-                pr_err("Failed to add MPUSS -> EMIF wakeup dependency\n");
-        return ret;
+        return 0;
 }
 /**
@@ -272,6 +249,15 @@ int __init omap4_pm_init(void)
        pr_info("Power Management for TI OMAP4+ devices.\n");
+        /*
+         * OMAP4 chip PM currently works only with certain (newer)
+         * versions of bootloaders. This is due to missing code in the
+         * kernel to properly reset and initialize some devices.
+         * http://www.spinics.net/lists/arm-kernel/msg218641.html
+         */
+        if (cpu_is_omap44xx())
+                pr_warn("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n");
        ret = pwrdm_for_each(pwrdms_setup, NULL);
        if (ret) {
                pr_err("Failed to setup powerdomains.\n");
@@ -279,9 +265,9 @@ int __init omap4_pm_init(void)
        }
        if (cpu_is_omap44xx())
-                ret = omap4_init_static_deps();
+                ret = omap4plus_init_static_deps(omap4_static_dep_map);
        else if (soc_is_omap54xx() || soc_is_dra7xx())
-                ret = omap5_dra7_init_static_deps();
+                ret = omap4plus_init_static_deps(omap5_dra7_static_dep_map);
        if (ret) {
                pr_err("Failed to initialise static dependencies.\n");
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 48480d557b61..77752e49d8d4 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -29,6 +29,7 @@ int of_prcm_init(void);
 * PRM_HAS_VOLTAGE: has voltage domains
 */
 #define PRM_HAS_IO_WAKEUP       (1 << 0)
+#define PRM_HAS_VOLTAGE         (1 << 1)
 /*
 * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
@@ -127,6 +128,8 @@ struct prm_reset_src_map {
 * @was_any_context_lost_old: ptr to the SoC PRM context loss test fn
 * @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn
 * @late_init: ptr to the late init function
+ * @assert_hardreset: ptr to the SoC PRM hardreset assert impl
+ * @deassert_hardreset: ptr to the SoC PRM hardreset deassert impl
 *
 * XXX @was_any_context_lost_old and @clear_context_loss_flags_old are
 * deprecated.
@@ -136,14 +139,27 @@ struct prm_ll_data {
        bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx);
        void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx);
        int (*late_init)(void);
+        int (*assert_hardreset)(u8 shift, u8 part, s16 prm_mod, u16 offset);
+        int (*deassert_hardreset)(u8 shift, u8 st_shift, u8 part, s16 prm_mod,
+                                  u16 offset, u16 st_offset);
+        int (*is_hardreset_asserted)(u8 shift, u8 part, s16 prm_mod,
+                                     u16 offset);
+        void (*reset_system)(void);
 };
 extern int prm_register(struct prm_ll_data *pld);
 extern int prm_unregister(struct prm_ll_data *pld);
+int omap_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset);
+int omap_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 prm_mod,
+                                u16 offset, u16 st_offset);
+int omap_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset);
 extern u32 prm_read_reset_sources(void);
 extern bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx);
 extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx);
+void omap_prm_reset_system(void);
+void omap_prm_reconfigure_io_chain(void);
 #endif
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
index 86958050547a..af0f15278fc2 100644
--- a/arch/arm/mach-omap2/prm2xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx.c
@@ -106,7 +106,7 @@ static int omap2xxx_pwrst_to_common_pwrst(u8 omap2xxx_pwrst)
 * Set the DPLL reset bit, which should reboot the SoC.  This is the
 * recommended way to restart the SoC.  No return value.
 */
-void omap2xxx_prm_dpll_reset(void)
+static void omap2xxx_prm_dpll_reset(void)
 {
        omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, WKUP_MOD,
                                   OMAP2_RM_RSTCTRL);
@@ -212,6 +212,10 @@ struct pwrdm_ops omap2_pwrdm_operations = {
 static struct prm_ll_data omap2xxx_prm_ll_data = {
        .read_reset_sources = &omap2xxx_prm_read_reset_sources,
+        .assert_hardreset = &omap2_prm_assert_hardreset,
+        .deassert_hardreset = &omap2_prm_deassert_hardreset,
+        .is_hardreset_asserted = &omap2_prm_is_hardreset_asserted,
+        .reset_system = &omap2xxx_prm_dpll_reset,
 };
 int __init omap2xxx_prm_init(void)
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
index d73414139292..1d51643062f7 100644
--- a/arch/arm/mach-omap2/prm2xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx.h
@@ -124,7 +124,6 @@
 extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
 extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
-extern void omap2xxx_prm_dpll_reset(void);
 void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
 extern int __init omap2xxx_prm_init(void);
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index c13b4e293ffa..cc3341f263cd 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -24,14 +24,16 @@
 /**
 * omap2_prm_is_hardreset_asserted - read the HW reset line state of
 * submodules contained in the hwmod module
- * @prm_mod: PRM submodule base (e.g. CORE_MOD)
 * @shift: register bit shift corresponding to the reset line to check
+ * @part: PRM partition, ignored for OMAP2
+ * @prm_mod: PRM submodule base (e.g. CORE_MOD)
+ * @offset: register offset, ignored for OMAP2
 *
 * Returns 1 if the (sub)module hardreset line is currently asserted,
 * 0 if the (sub)module hardreset line is not currently asserted, or
 * -EINVAL if called while running on a non-OMAP2/3 chip.
 */
-int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
+int omap2_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset)
 {
        return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
                                       (1 << shift));
@@ -39,8 +41,10 @@ int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
 /**
 * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
- * @prm_mod: PRM submodule base (e.g. CORE_MOD)
 * @shift: register bit shift corresponding to the reset line to assert
+ * @part: PRM partition, ignored for OMAP2
+ * @prm_mod: PRM submodule base (e.g. CORE_MOD)
+ * @offset: register offset, ignored for OMAP2
 *
 * Some IPs like dsp or iva contain processors that require an HW
 * reset line to be asserted / deasserted in order to fully enable the
@@ -49,7 +53,7 @@ int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
 * place the submodule into reset.  Returns 0 upon success or -EINVAL
 * upon an argument error.
 */
-int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
+int omap2_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset)
 {
        u32 mask;
@@ -64,6 +68,10 @@ int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
 * @prm_mod: PRM submodule base (e.g. CORE_MOD)
 * @rst_shift: register bit shift corresponding to the reset line to deassert
 * @st_shift: register bit shift for the status of the deasserted submodule
+ * @part: PRM partition, not used for OMAP2
+ * @prm_mod: PRM submodule base (e.g. CORE_MOD)
+ * @rst_offset: reset register offset, not used for OMAP2
+ * @st_offset: reset status register offset, not used for OMAP2
 *
 * Some IPs like dsp or iva contain processors that require an HW
 * reset line to be asserted / deasserted in order to fully enable the
@@ -74,7 +82,8 @@ int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
 * of reset, or -EBUSY if the submodule did not exit reset promptly.
 */
-int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
+int omap2_prm_deassert_hardreset(u8 rst_shift, u8 st_shift, u8 part,
+                                 s16 prm_mod, u16 rst_offset, u16 st_offset)
 {
        u32 rst, st;
        int c;
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index 1a3a96392b97..f57e29b0e041 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -100,9 +100,12 @@ static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
 }
 /* These omap2_ PRM functions apply to both OMAP2 and 3 */
-extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
+int omap2_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset);
-extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
+int omap2_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod,
-extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
+                               u16 offset);
+int omap2_prm_deassert_hardreset(u8 rst_shift, u8 st_shift, u8 part,
+                                 s16 prm_mod, u16 reset_offset,
+                                 u16 st_offset);
 extern int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
 extern int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 62709cd2f9c5..02f628601b09 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -23,20 +23,24 @@
 #include "prm33xx.h"
 #include "prm-regbits-33xx.h"
+#define AM33XX_PRM_RSTCTRL_OFFSET               0x0000
+#define AM33XX_RST_GLOBAL_WARM_SW_MASK          (1 << 0)
 /* Read a register in a PRM instance */
-u32 am33xx_prm_read_reg(s16 inst, u16 idx)
+static u32 am33xx_prm_read_reg(s16 inst, u16 idx)
 {
        return readl_relaxed(prm_base + inst + idx);
 }
 /* Write into a register in a PRM instance */
-void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
+static void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
 {
        writel_relaxed(val, prm_base + inst + idx);
 }
 /* Read-modify-write a register in PRM. Caller must lock */
-u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
+static u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
 {
        u32 v;
@@ -52,6 +56,7 @@ u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
 * am33xx_prm_is_hardreset_asserted - read the HW reset line state of
 * submodules contained in the hwmod module
 * @shift: register bit shift corresponding to the reset line to check
+ * @part: PRM partition, ignored for AM33xx
 * @inst: CM instance register offset (*_INST macro)
 * @rstctrl_offs: RM_RSTCTRL register address offset for this module
 *
@@ -59,7 +64,8 @@ u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
 * 0 if the (sub)module hardreset line is not currently asserted, or
 * -EINVAL upon parameter error.
 */
-int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, u16 rstctrl_offs)
+static int am33xx_prm_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
+                                            u16 rstctrl_offs)
 {
        u32 v;
@@ -73,6 +79,7 @@ int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, u16 rstctrl_offs)
 /**
 * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
 * @shift: register bit shift corresponding to the reset line to assert
+ * @part: CM partition, ignored for AM33xx
 * @inst: CM instance register offset (*_INST macro)
 * @rstctrl_reg: RM_RSTCTRL register address for this module
 *
@@ -83,7 +90,8 @@ int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, u16 rstctrl_offs)
 * place the submodule into reset.  Returns 0 upon success or -EINVAL
 * upon an argument error.
 */
-int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs)
+static int am33xx_prm_assert_hardreset(u8 shift, u8 part, s16 inst,
+                                       u16 rstctrl_offs)
 {
        u32 mask = 1 << shift;
@@ -96,6 +104,8 @@ int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs)
 * am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and
 * wait
 * @shift: register bit shift corresponding to the reset line to deassert
+ * @st_shift: reset status register bit shift corresponding to the reset line
+ * @part: PRM partition, not used for AM33xx
 * @inst: CM instance register offset (*_INST macro)
 * @rstctrl_reg: RM_RSTCTRL register address for this module
 * @rstst_reg: RM_RSTST register address for this module
@@ -109,14 +119,15 @@ int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs)
 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
 * of reset, or -EBUSY if the submodule did not exit reset promptly.
 */
-int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
+static int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part,
-                u16 rstctrl_offs, u16 rstst_offs)
+                                         s16 inst, u16 rstctrl_offs,
+                                         u16 rstst_offs)
 {
        int c;
        u32 mask = 1 << st_shift;
        /* Check the current status to avoid  de-asserting the line twice */
-        if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0)
+        if (am33xx_prm_is_hardreset_asserted(shift, 0, inst, rstctrl_offs) == 0)
                return -EEXIST;
        /* Clear the reset status by writing 1 to the status bit */
@@ -128,7 +139,7 @@ int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
        am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
        /* wait the status to be set */
-        omap_test_timeout(am33xx_prm_is_hardreset_asserted(st_shift, inst,
+        omap_test_timeout(am33xx_prm_is_hardreset_asserted(st_shift, 0, inst,
                                                           rstst_offs),
                          MAX_MODULE_HARDRESET_WAIT, c);
@@ -325,6 +336,23 @@ static int am33xx_check_vcvp(void)
        return 0;
 }
+/**
+ * am33xx_prm_global_warm_sw_reset - reboot the device via warm reset
+ *
+ * Immediately reboots the device through warm reset.
+ */
+static void am33xx_prm_global_warm_sw_reset(void)
+{
+        am33xx_prm_rmw_reg_bits(AM33XX_RST_GLOBAL_WARM_SW_MASK,
+                                AM33XX_RST_GLOBAL_WARM_SW_MASK,
+                                AM33XX_PRM_DEVICE_MOD,
+                                AM33XX_PRM_RSTCTRL_OFFSET);
+        /* OCP barrier */
+        (void)am33xx_prm_read_reg(AM33XX_PRM_DEVICE_MOD,
+                                  AM33XX_PRM_RSTCTRL_OFFSET);
+}
 struct pwrdm_ops am33xx_pwrdm_operations = {
        .pwrdm_set_next_pwrst           = am33xx_pwrdm_set_next_pwrst,
        .pwrdm_read_next_pwrst          = am33xx_pwrdm_read_next_pwrst,
@@ -342,3 +370,21 @@ struct pwrdm_ops am33xx_pwrdm_operations = {
        .pwrdm_wait_transition          = am33xx_pwrdm_wait_transition,
        .pwrdm_has_voltdm               = am33xx_check_vcvp,
 };
+static struct prm_ll_data am33xx_prm_ll_data = {
+        .assert_hardreset               = am33xx_prm_assert_hardreset,
+        .deassert_hardreset             = am33xx_prm_deassert_hardreset,
+        .is_hardreset_asserted          = am33xx_prm_is_hardreset_asserted,
+        .reset_system                   = am33xx_prm_global_warm_sw_reset,
+};
+int __init am33xx_prm_init(void)
+{
+        return prm_register(&am33xx_prm_ll_data);
+}
+static void __exit am33xx_prm_exit(void)
+{
+        prm_unregister(&am33xx_prm_ll_data);
+}
+__exitcall(am33xx_prm_exit);
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
index 9b9918dfb119..98ac41f271da 100644
--- a/arch/arm/mach-omap2/prm33xx.h
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -118,14 +118,7 @@
 #define AM33XX_PM_CEFUSE_PWRSTST                AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
 #ifndef __ASSEMBLER__
-extern u32 am33xx_prm_read_reg(s16 inst, u16 idx);
+int am33xx_prm_init(void);
-extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx);
-extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
-extern void am33xx_prm_global_warm_sw_reset(void);
-extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst,
-                u16 rstctrl_offs);
-extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
-extern int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
-                u16 rstctrl_offs, u16 rstst_offs);
 #endif /* ASSEMBLER */
 #endif
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index ff08da385a2d..c5e00c6714b1 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -30,6 +30,11 @@
 #include "cm3xxx.h"
 #include "cm-regbits-34xx.h"
+static void omap3xxx_prm_read_pending_irqs(unsigned long *events);
+static void omap3xxx_prm_ocp_barrier(void);
+static void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
+static void omap3xxx_prm_restore_irqen(u32 *saved_mask);
 static const struct omap_prcm_irq omap3_prcm_irqs[] = {
        OMAP_PRCM_IRQ("wkup",   0,      0),
        OMAP_PRCM_IRQ("io",     9,      1),
@@ -131,7 +136,7 @@ u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
 * recommended way to restart the SoC, considering Errata i520.  No
 * return value.
 */
-void omap3xxx_prm_dpll3_reset(void)
+static void omap3xxx_prm_dpll3_reset(void)
 {
        omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, OMAP3430_GR_MOD,
                                   OMAP2_RM_RSTCTRL);
@@ -147,7 +152,7 @@ void omap3xxx_prm_dpll3_reset(void)
 * MPU IRQs, and store the result into the u32 pointed to by @events.
 * No return value.
 */
-void omap3xxx_prm_read_pending_irqs(unsigned long *events)
+static void omap3xxx_prm_read_pending_irqs(unsigned long *events)
 {
        u32 mask, st;
@@ -166,7 +171,7 @@ void omap3xxx_prm_read_pending_irqs(unsigned long *events)
 * block, to avoid race conditions after acknowledging or clearing IRQ
 * bits.  No return value.
 */
-void omap3xxx_prm_ocp_barrier(void)
+static void omap3xxx_prm_ocp_barrier(void)
 {
        omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
 }
@@ -182,7 +187,7 @@ void omap3xxx_prm_ocp_barrier(void)
 * returning; otherwise, spurious interrupts might occur.  No return
 * value.
 */
-void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
+static void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
 {
        saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
                                               OMAP3_PRM_IRQENABLE_MPU_OFFSET);
@@ -202,7 +207,7 @@ void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
 * barrier should be needed here; any pending PRM interrupts will fire
 * once the writes reach the PRM.  No return value.
 */
-void omap3xxx_prm_restore_irqen(u32 *saved_mask)
+static void omap3xxx_prm_restore_irqen(u32 *saved_mask)
 {
        omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
                                OMAP3_PRM_IRQENABLE_MPU_OFFSET);
@@ -375,7 +380,7 @@ void __init omap3_prm_init_pm(bool has_uart4, bool has_iva)
 * The ST_IO_CHAIN bit does not exist in 3430 before es3.1. The only
 * thing we can do is toggle EN_IO bit for earlier omaps.
 */
-void omap3430_pre_es3_1_reconfigure_io_chain(void)
+static void omap3430_pre_es3_1_reconfigure_io_chain(void)
 {
        omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
                                     PM_WKEN);
@@ -393,7 +398,7 @@ void omap3430_pre_es3_1_reconfigure_io_chain(void)
 * deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit.  No
 * return value. These registers are only available in 3430 es3.1 and later.
 */
-void omap3_prm_reconfigure_io_chain(void)
+static void omap3_prm_reconfigure_io_chain(void)
 {
        int i = 0;
@@ -416,15 +421,6 @@ void omap3_prm_reconfigure_io_chain(void)
 }
 /**
- * omap3xxx_prm_reconfigure_io_chain - reconfigure I/O chain
- */
-void omap3xxx_prm_reconfigure_io_chain(void)
-{
-        if (omap3_prcm_irq_setup.reconfigure_io_chain)
-                omap3_prcm_irq_setup.reconfigure_io_chain();
-}
-/**
 * omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
 *
 * Activates the I/O wakeup event latches and allows events logged by
@@ -664,6 +660,10 @@ static int omap3xxx_prm_late_init(void);
 static struct prm_ll_data omap3xxx_prm_ll_data = {
        .read_reset_sources = &omap3xxx_prm_read_reset_sources,
        .late_init = &omap3xxx_prm_late_init,
+        .assert_hardreset = &omap2_prm_assert_hardreset,
+        .deassert_hardreset = &omap2_prm_deassert_hardreset,
+        .is_hardreset_asserted = &omap2_prm_is_hardreset_asserted,
+        .reset_system = &omap3xxx_prm_dpll3_reset,
 };
 int __init omap3xxx_prm_init(void)
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index bc37d42a8704..cfde3f4a03cc 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -144,22 +144,6 @@ extern u32 omap3_prm_vcvp_read(u8 offset);
 extern void omap3_prm_vcvp_write(u32 val, u8 offset);
 extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
-#ifdef CONFIG_ARCH_OMAP3
-void omap3xxx_prm_reconfigure_io_chain(void);
-#else
-static inline void omap3xxx_prm_reconfigure_io_chain(void)
-{
-}
-#endif
-/* PRM interrupt-related functions */
-extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
-extern void omap3xxx_prm_ocp_barrier(void);
-extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
-extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
-extern void omap3xxx_prm_dpll3_reset(void);
 extern int __init omap3xxx_prm_init(void);
 extern u32 omap3xxx_prm_get_reset_sources(void);
 int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits);
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 0958d070d3db..cc170fb81ff7 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -32,6 +32,12 @@
 /* Static data */
+static void omap44xx_prm_read_pending_irqs(unsigned long *events);
+static void omap44xx_prm_ocp_barrier(void);
+static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
+static void omap44xx_prm_restore_irqen(u32 *saved_mask);
+static void omap44xx_prm_reconfigure_io_chain(void);
 static const struct omap_prcm_irq omap4_prcm_irqs[] = {
        OMAP_PRCM_IRQ("io",     9,      1),
 };
@@ -80,19 +86,19 @@ static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
 /* PRM low-level functions */
 /* Read a register in a CM/PRM instance in the PRM module */
-u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
+static u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
 {
        return readl_relaxed(prm_base + inst + reg);
 }
 /* Write into a register in a CM/PRM instance in the PRM module */
-void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
+static void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
 {
        writel_relaxed(val, prm_base + inst + reg);
 }
 /* Read-modify-write a register in a PRM module. Caller must lock */
-u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
+static u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
 {
        u32 v;
@@ -207,7 +213,7 @@ static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs)
 * MPU IRQs, and store the result into the two u32s pointed to by @events.
 * No return value.
 */
-void omap44xx_prm_read_pending_irqs(unsigned long *events)
+static void omap44xx_prm_read_pending_irqs(unsigned long *events)
 {
        events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET,
                                          OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
@@ -224,7 +230,7 @@ void omap44xx_prm_read_pending_irqs(unsigned long *events)
 * block, to avoid race conditions after acknowledging or clearing IRQ
 * bits.  No return value.
 */
-void omap44xx_prm_ocp_barrier(void)
+static void omap44xx_prm_ocp_barrier(void)
 {
        omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
                                OMAP4_REVISION_PRM_OFFSET);
@@ -241,7 +247,7 @@ void omap44xx_prm_ocp_barrier(void)
 * interrupts reaches the PRM before returning; otherwise, spurious
 * interrupts might occur.  No return value.
 */
-void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
+static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
 {
        saved_mask[0] =
                omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
@@ -270,7 +276,7 @@ void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
 * No OCP barrier should be needed here; any pending PRM interrupts will fire
 * once the writes reach the PRM.  No return value.
 */
-void omap44xx_prm_restore_irqen(u32 *saved_mask)
+static void omap44xx_prm_restore_irqen(u32 *saved_mask)
 {
        omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_OCP_SOCKET_INST,
                                 OMAP4_PRM_IRQENABLE_MPU_OFFSET);
@@ -287,7 +293,7 @@ void omap44xx_prm_restore_irqen(u32 *saved_mask)
 * deasserting WUCLKIN and waiting for WUCLKOUT to be deasserted.
 * No return value. XXX Are the final two steps necessary?
 */
-void omap44xx_prm_reconfigure_io_chain(void)
+static void omap44xx_prm_reconfigure_io_chain(void)
 {
        int i = 0;
        s32 inst = omap4_prmst_get_prm_dev_inst();
@@ -652,11 +658,10 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
 static int omap4_check_vcvp(void)
 {
-        /* No VC/VP on dra7xx devices */
+        if (prm_features & PRM_HAS_VOLTAGE)
-        if (soc_is_dra7xx())
+                return 1;
-                return 0;
-        return 1;
+        return 0;
 }
 struct pwrdm_ops omap4_pwrdm_operations = {
@@ -689,6 +694,10 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
        .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old,
        .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old,
        .late_init = &omap44xx_prm_late_init,
+        .assert_hardreset       = omap4_prminst_assert_hardreset,
+        .deassert_hardreset     = omap4_prminst_deassert_hardreset,
+        .is_hardreset_asserted  = omap4_prminst_is_hardreset_asserted,
+        .reset_system           = omap4_prminst_global_warm_sw_reset,
 };
 int __init omap44xx_prm_init(void)
@@ -696,6 +705,9 @@ int __init omap44xx_prm_init(void)
        if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx())
                prm_features |= PRM_HAS_IO_WAKEUP;
+        if (!soc_is_dra7xx())
+                prm_features |= PRM_HAS_VOLTAGE;
        return prm_register(&omap44xx_prm_ll_data);
 }
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h
index 8d95aa543ef5..f7512515fde5 100644
--- a/arch/arm/mach-omap2/prm44xx_54xx.h
+++ b/arch/arm/mach-omap2/prm44xx_54xx.h
@@ -26,10 +26,6 @@
 /* Function prototypes */
 #ifndef __ASSEMBLER__
-extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
 /* OMAP4/OMAP5-specific VP functions */
 u32 omap4_prm_vp_check_txdone(u8 vp_id);
 void omap4_prm_vp_clear_txdone(u8 vp_id);
@@ -42,21 +38,6 @@ extern u32 omap4_prm_vcvp_read(u8 offset);
 extern void omap4_prm_vcvp_write(u32 val, u8 offset);
 extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
-#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
-        defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
-void omap44xx_prm_reconfigure_io_chain(void);
-#else
-static inline void omap44xx_prm_reconfigure_io_chain(void)
-{
-}
-#endif
-/* PRM interrupt-related functions */
-extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
-extern void omap44xx_prm_ocp_barrier(void);
-extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
-extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
 extern int __init omap44xx_prm_init(void);
 extern u32 omap44xx_prm_get_reset_sources(void);
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index ee2b5222eac0..779940cb6e56 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -423,6 +423,105 @@ void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx)
 }
 /**
+ * omap_prm_assert_hardreset - assert hardreset for an IP block
+ * @shift: register bit shift corresponding to the reset line
+ * @part: PRM partition
+ * @prm_mod: PRM submodule base or instance offset
+ * @offset: register offset
+ *
+ * Asserts a hardware reset line for an IP block.
+ */
+int omap_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset)
+{
+        if (!prm_ll_data->assert_hardreset) {
+                WARN_ONCE(1, "prm: %s: no mapping function defined\n",
+                          __func__);
+                return -EINVAL;
+        }
+        return prm_ll_data->assert_hardreset(shift, part, prm_mod, offset);
+}
+/**
+ * omap_prm_deassert_hardreset - deassert hardreset for an IP block
+ * @shift: register bit shift corresponding to the reset line
+ * @st_shift: reset status bit shift corresponding to the reset line
+ * @part: PRM partition
+ * @prm_mod: PRM submodule base or instance offset
+ * @offset: register offset
+ * @st_offset: status register offset
+ *
+ * Deasserts a hardware reset line for an IP block.
+ */
+int omap_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 prm_mod,
+                                u16 offset, u16 st_offset)
+{
+        if (!prm_ll_data->deassert_hardreset) {
+                WARN_ONCE(1, "prm: %s: no mapping function defined\n",
+                          __func__);
+                return -EINVAL;
+        }
+        return prm_ll_data->deassert_hardreset(shift, st_shift, part, prm_mod,
+                                               offset, st_offset);
+}
+/**
+ * omap_prm_is_hardreset_asserted - check the hardreset status for an IP block
+ * @shift: register bit shift corresponding to the reset line
+ * @part: PRM partition
+ * @prm_mod: PRM submodule base or instance offset
+ * @offset: register offset
+ *
+ * Checks if a hardware reset line for an IP block is enabled or not.
+ */
+int omap_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset)
+{
+        if (!prm_ll_data->is_hardreset_asserted) {
+                WARN_ONCE(1, "prm: %s: no mapping function defined\n",
+                          __func__);
+                return -EINVAL;
+        }
+        return prm_ll_data->is_hardreset_asserted(shift, part, prm_mod, offset);
+}
+/**
+ * omap_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
+ *
+ * Clear any previously-latched I/O wakeup events and ensure that the
+ * I/O wakeup gates are aligned with the current mux settings.
+ * Calls SoC specific I/O chain reconfigure function if available,
+ * otherwise does nothing.
+ */
+void omap_prm_reconfigure_io_chain(void)
+{
+        if (!prcm_irq_setup || !prcm_irq_setup->reconfigure_io_chain)
+                return;
+        prcm_irq_setup->reconfigure_io_chain();
+}
+/**
+ * omap_prm_reset_system - trigger global SW reset
+ *
+ * Triggers SoC specific global warm reset to reboot the device.
+ */
+void omap_prm_reset_system(void)
+{
+        if (!prm_ll_data->reset_system) {
+                WARN_ONCE(1, "prm: %s: no mapping function defined\n",
+                          __func__);
+                return;
+        }
+        prm_ll_data->reset_system();
+        while (1)
+                cpu_relax();
+}
+/**
 * prm_register - register per-SoC low-level data with the PRM
 * @pld: low-level per-SoC OMAP PRM data & function pointers to register
 *
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 225e0258d76d..8adf7b1a1dce 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -148,8 +148,12 @@ int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
 /**
 * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
 * wait
- * @rstctrl_reg: RM_RSTCTRL register address for this module
 * @shift: register bit shift corresponding to the reset line to deassert
+ * @st_shift: status bit offset, not used for OMAP4+
+ * @part: PRM partition
+ * @inst: PRM instance offset
+ * @rstctrl_offs: reset register offset
+ * @st_offs: reset status register offset, not used for OMAP4+
 *
 * Some IPs like dsp, ipu or iva contain processors that require an HW
 * reset line to be asserted / deasserted in order to fully enable the
@@ -160,8 +164,8 @@ int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
 * of reset, or -EBUSY if the submodule did not exit reset promptly.
 */
-int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
+int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst,
-                                     u16 rstctrl_offs)
+                                     u16 rstctrl_offs, u16 st_offs)
 {
        int c;
        u32 mask = 1 << shift;
diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h
index 583aa3774571..fb1c9d7a2f9d 100644
--- a/arch/arm/mach-omap2/prminst44xx.h
+++ b/arch/arm/mach-omap2/prminst44xx.h
@@ -30,8 +30,9 @@ extern int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
                                               u16 rstctrl_offs);
 extern int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
                                          u16 rstctrl_offs);
-extern int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
+int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part,
-                                            u16 rstctrl_offs);
+                                     s16 inst, u16 rstctrl_offs,
+                                     u16 rstst_offs);
 extern void omap_prm_base_init(void);
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index a388f8c1bcb3..57dee0c7cd2b 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -263,9 +263,6 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
        omap_up.dma_rx_timeout = info->dma_rx_timeout;
        omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
        omap_up.autosuspend_timeout = info->autosuspend_timeout;
-        omap_up.DTR_gpio = info->DTR_gpio;
-        omap_up.DTR_inverted = info->DTR_inverted;
-        omap_up.DTR_present = info->DTR_present;
        pdata = &omap_up;
        pdata_size = sizeof(struct omap_uart_port_info);
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index e6690a44917d..83efe914bf7d 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -4,6 +4,17 @@ menu "Intel PXA2xx/PXA3xx Implementations"
 comment "Intel/Marvell Dev Platforms (sorted by hardware release time)"
+config MACH_PXA27X_DT
+        bool "Support PXA27x platforms from device tree"
+        select CPU_PXA27x
+        select POWER_SUPPLY
+        select PXA27x
+        select USE_OF
+        help
+          Include support for Marvell PXA27x based platforms using
+          the device tree. Needn't select any other machine while
+          MACH_PXA27X_DT is enabled.
 config MACH_PXA3XX_DT
        bool "Support PXA3xx platforms from device tree"
        select CPU_PXA300
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 2fe1824c6dcb..eb0bf7678a99 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_CPU_PXA930)	+= pxa930.o
 # Device Tree support
 obj-$(CONFIG_MACH_PXA3XX_DT)    += pxa-dt.o
+obj-$(CONFIG_MACH_PXA27X_DT)    += pxa-dt.o
 # Intel/Marvell Dev Platforms
 obj-$(CONFIG_ARCH_LUBBOCK)      += lubbock.o
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 6915a9f6b3a3..51531ecffca8 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -378,7 +378,7 @@ static void __init em_x270_init_nand(void)
        err = gpio_request(GPIO11_NAND_CS, "NAND CS");
        if (err) {
-                pr_warning("EM-X270: failed to request NAND CS gpio\n");
+                pr_warn("EM-X270: failed to request NAND CS gpio\n");
                return;
        }
@@ -386,7 +386,7 @@ static void __init em_x270_init_nand(void)
        err = gpio_request(nand_rb, "NAND R/B");
        if (err) {
-                pr_warning("EM-X270: failed to request NAND R/B gpio\n");
+                pr_warn("EM-X270: failed to request NAND R/B gpio\n");
                gpio_free(GPIO11_NAND_CS);
                return;
        }
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index 8963984d1f43..7a9fa1aa4e41 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -13,11 +13,11 @@
 struct irq_data;
-extern void pxa_timer_init(void);
-extern void __init pxa_map_io(void);
 extern unsigned int get_clk_frequency_khz(int info);
+extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *,
+                                             unsigned int));
+extern void __init pxa_map_io(void);
+extern void pxa_timer_init(void);
 #define SET_BANK(__nr,__start,__size) \
        mi->bank[__nr].start = (__start), \
@@ -25,6 +25,43 @@ extern unsigned int get_clk_frequency_khz(int info);
 #define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
+#define pxa25x_handle_irq icip_handle_irq
+extern void __init pxa25x_init_irq(void);
+extern void __init pxa25x_map_io(void);
+extern void __init pxa26x_init_irq(void);
+#define pxa27x_handle_irq ichp_handle_irq
+extern void __init pxa27x_dt_init_irq(void);
+extern unsigned pxa27x_get_clk_frequency_khz(int);
+extern void __init pxa27x_init_irq(void);
+extern void __init pxa27x_map_io(void);
+#define pxa3xx_handle_irq ichp_handle_irq
+extern void __init pxa3xx_dt_init_irq(void);
+extern void __init pxa3xx_init_irq(void);
+extern void __init pxa3xx_map_io(void);
+extern struct syscore_ops pxa_irq_syscore_ops;
+extern struct syscore_ops pxa2xx_mfp_syscore_ops;
+extern struct syscore_ops pxa3xx_mfp_syscore_ops;
+void __init pxa_set_ffuart_info(void *info);
+void __init pxa_set_btuart_info(void *info);
+void __init pxa_set_stuart_info(void *info);
+void __init pxa_set_hwuart_info(void *info);
+void pxa_restart(enum reboot_mode, const char *);
+#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
+extern void pxa2xx_clear_reset_status(unsigned int);
+#else
+static inline void pxa2xx_clear_reset_status(unsigned int mask) {}
+#endif
+/*
+ * Once fully converted to the clock framework, all these functions should be
+ * removed, and replaced with a clk_get(NULL, "core").
+ */
 #ifdef CONFIG_PXA25x
 extern unsigned pxa25x_get_clk_frequency_khz(int);
 #else
@@ -32,30 +69,12 @@ extern unsigned pxa25x_get_clk_frequency_khz(int);
 #endif
 #ifdef CONFIG_PXA27x
-extern unsigned pxa27x_get_clk_frequency_khz(int);
 #else
 #define pxa27x_get_clk_frequency_khz(x)         (0)
 #endif
-#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
-extern void pxa2xx_clear_reset_status(unsigned int);
-#else
-static inline void pxa2xx_clear_reset_status(unsigned int mask) {}
-#endif
 #ifdef CONFIG_PXA3xx
-extern unsigned pxa3xx_get_clk_frequency_khz(int);
+extern unsigned pxa3xx_get_clk_frequency_khz(int);
 #else
 #define pxa3xx_get_clk_frequency_khz(x)         (0)
 #endif
-extern struct syscore_ops pxa_irq_syscore_ops;
-extern struct syscore_ops pxa2xx_mfp_syscore_ops;
-extern struct syscore_ops pxa3xx_mfp_syscore_ops;
-void __init pxa_set_ffuart_info(void *info);
-void __init pxa_set_btuart_info(void *info);
-void __init pxa_set_stuart_info(void *info);
-void __init pxa_set_hwuart_info(void *info);
-void pxa_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
index 00b92dad7b81..f6c76a3ee3b2 100644
--- a/arch/arm/mach-pxa/gumstix.c
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -140,8 +140,7 @@ static void gumstix_setup_bt_clock(void)
        int timeout = 500;
        if (!(OSCC & OSCC_OOK))
-                pr_warning("32kHz clock was not on. Bootloader may need to "
+                pr_warn("32kHz clock was not on. Bootloader may need to be updated\n");
-                                "be updated\n");
        else
                return;
diff --git a/arch/arm/mach-pxa/include/mach/pxa25x.h b/arch/arm/mach-pxa/include/mach/pxa25x.h
index 3ac0baac7350..5a341752e32c 100644
--- a/arch/arm/mach-pxa/include/mach/pxa25x.h
+++ b/arch/arm/mach-pxa/include/mach/pxa25x.h
@@ -6,12 +6,4 @@
 #include <mach/mfp-pxa25x.h>
 #include <mach/irqs.h>
-extern void __init pxa25x_map_io(void);
-extern void __init pxa25x_init_irq(void);
-#ifdef CONFIG_CPU_PXA26x
-extern void __init pxa26x_init_irq(void);
-#endif
-#define pxa25x_handle_irq       icip_handle_irq
 #endif /* __MACH_PXA25x_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa27x.h b/arch/arm/mach-pxa/include/mach/pxa27x.h
index 7cff640582b8..599b925a657c 100644
--- a/arch/arm/mach-pxa/include/mach/pxa27x.h
+++ b/arch/arm/mach-pxa/include/mach/pxa27x.h
@@ -19,11 +19,7 @@
 #define ARB_CORE_PARK           (1<<24)    /* Be parked with core when idle */
 #define ARB_LOCK_FLAG           (1<<23)    /* Only Locking masters gain access to the bus */
-extern void __init pxa27x_map_io(void);
-extern void __init pxa27x_init_irq(void);
 extern int __init pxa27x_set_pwrmode(unsigned int mode);
 extern void pxa27x_cpu_pm_enter(suspend_state_t state);
-#define pxa27x_handle_irq       ichp_handle_irq
 #endif /* __MACH_PXA27x_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx.h b/arch/arm/mach-pxa/include/mach/pxa3xx.h
index 6dd7fa163e29..b4143fb6631f 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx.h
@@ -5,9 +5,4 @@
 #include <mach/pxa3xx-regs.h>
 #include <mach/irqs.h>
-extern void __init pxa3xx_map_io(void);
-extern void __init pxa3xx_init_irq(void);
-#define pxa3xx_handle_irq       ichp_handle_irq
 #endif /* __MACH_PXA3XX_H */
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index ef0426a159d4..666b78972c40 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -93,8 +93,8 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c)
                break;
        default:
                /* warning and fall through, treat as MFP_LPM_DEFAULT */
-                pr_warning("%s: GPIO%d: unsupported low power mode\n",
+                pr_warn("%s: GPIO%d: unsupported low power mode\n",
-                                __func__, gpio);
+                        __func__, gpio);
                break;
        }
@@ -107,14 +107,12 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c)
         * configurations of those pins not able to wakeup
         */
        if ((c & MFP_LPM_CAN_WAKEUP) && !gpio_desc[gpio].can_wakeup) {
-                pr_warning("%s: GPIO%d unable to wakeup\n",
+                pr_warn("%s: GPIO%d unable to wakeup\n", __func__, gpio);
-                                __func__, gpio);
                return -EINVAL;
        }
        if ((c & MFP_LPM_CAN_WAKEUP) && is_out) {
-                pr_warning("%s: output GPIO%d unable to wakeup\n",
+                pr_warn("%s: output GPIO%d unable to wakeup\n", __func__, gpio);
-                                __func__, gpio);
                return -EINVAL;
        }
@@ -126,7 +124,7 @@ static inline int __mfp_validate(int mfp)
        int gpio = mfp_to_gpio(mfp);
        if ((mfp > MFP_PIN_GPIO127) || !gpio_desc[gpio].valid) {
-                pr_warning("%s: GPIO%d is invalid pin\n", __func__, gpio);
+                pr_warn("%s: GPIO%d is invalid pin\n", __func__, gpio);
                return -1;
        }
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 131991629116..29019beae591 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -446,7 +446,7 @@ static void __init poodle_init(void)
        ret = platform_add_devices(devices, ARRAY_SIZE(devices));
        if (ret)
-                pr_warning("poodle: Unable to register LoCoMo device\n");
+                pr_warn("poodle: Unable to register LoCoMo device\n");
        pxa_set_fb_info(&poodle_locomo_device.dev, &poodle_fb_info);
        pxa_set_udc_info(&udc_info);
diff --git a/arch/arm/mach-pxa/pxa-dt.c b/arch/arm/mach-pxa/pxa-dt.c
index f6a2c4b1c1dc..7e0e5bd0c9de 100644
--- a/arch/arm/mach-pxa/pxa-dt.c
+++ b/arch/arm/mach-pxa/pxa-dt.c
@@ -15,13 +15,10 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/irqs.h>
-#include <mach/pxa3xx.h>
 #include "generic.h"
 #ifdef CONFIG_PXA3xx
-extern void __init pxa3xx_dt_init_irq(void);
 static const struct of_dev_auxdata pxa3xx_auxdata_lookup[] __initconst = {
        OF_DEV_AUXDATA("mrvl,pxa-uart",         0x40100000, "pxa2xx-uart.0", NULL),
        OF_DEV_AUXDATA("mrvl,pxa-uart",         0x40200000, "pxa2xx-uart.1", NULL),
@@ -61,3 +58,18 @@ DT_MACHINE_START(PXA_DT, "Marvell PXA3xx (Device Tree Support)")
        .dt_compat      = pxa3xx_dt_board_compat,
 MACHINE_END
 #endif
+#ifdef CONFIG_PXA27x
+static const char * const pxa27x_dt_board_compat[] __initconst = {
+        "marvell,pxa270",
+        NULL,
+};
+DT_MACHINE_START(PXA27X_DT, "Marvell PXA2xx (Device Tree Support)")
+        .map_io         = pxa27x_map_io,
+        .init_irq       = pxa27x_dt_init_irq,
+        .handle_irq     = pxa27x_handle_irq,
+        .restart        = pxa_restart,
+        .dt_compat      = pxa27x_dt_board_compat,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index b040d7d14888..af423a48c2e3 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -398,6 +398,12 @@ void __init pxa27x_init_irq(void)
        pxa_init_irq(34, pxa27x_set_wake);
 }
+void __init pxa27x_dt_init_irq(void)
+{
+        if (IS_ENABLED(CONFIG_OF))
+                pxa_dt_irq_init(pxa27x_set_wake);
+}
 static struct map_desc pxa27x_io_desc[] __initdata = {
        {       /* Mem Ctl */
                .virtual        = (unsigned long)SMEMC_VIRT,
diff --git a/arch/arm/mach-pxa/pxa3xx-ulpi.c b/arch/arm/mach-pxa/pxa3xx-ulpi.c
index e329ccefd364..614003e8b081 100644
--- a/arch/arm/mach-pxa/pxa3xx-ulpi.c
+++ b/arch/arm/mach-pxa/pxa3xx-ulpi.c
@@ -74,7 +74,7 @@ static int pxa310_ulpi_poll(void)
                cpu_relax();
        }
-        pr_warning("%s: ULPI access timed out!\n", __func__);
+        pr_warn("%s: ULPI access timed out!\n", __func__);
        return -ETIMEDOUT;
 }
@@ -84,7 +84,7 @@ static int pxa310_ulpi_read(struct usb_phy *otg, u32 reg)
        int err;
        if (pxa310_ulpi_get_phymode() != SYNCH) {
-                pr_warning("%s: PHY is not in SYNCH mode!\n", __func__);
+                pr_warn("%s: PHY is not in SYNCH mode!\n", __func__);
                return -EBUSY;
        }
@@ -101,7 +101,7 @@ static int pxa310_ulpi_read(struct usb_phy *otg, u32 reg)
 static int pxa310_ulpi_write(struct usb_phy *otg, u32 val, u32 reg)
 {
        if (pxa310_ulpi_get_phymode() != SYNCH) {
-                pr_warning("%s: PHY is not in SYNCH mode!\n", __func__);
+                pr_warn("%s: PHY is not in SYNCH mode!\n", __func__);
                return -EBUSY;
        }
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index 8386dc30b3e4..a762b23ac830 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -521,7 +521,7 @@ static void __init raumfeld_w1_init(void)
                                "W1 external pullup enable");
        if (ret < 0)
-                pr_warning("Unable to request GPIO_W1_PULLUP_ENABLE\n");
+                pr_warn("Unable to request GPIO_W1_PULLUP_ENABLE\n");
        else
                gpio_direction_output(GPIO_W1_PULLUP_ENABLE, 0);
@@ -600,7 +600,7 @@ static void __init raumfeld_lcd_init(void)
        ret = gpio_request(GPIO_TFT_VA_EN, "display VA enable");
        if (ret < 0)
-                pr_warning("Unable to request GPIO_TFT_VA_EN\n");
+                pr_warn("Unable to request GPIO_TFT_VA_EN\n");
        else
                gpio_direction_output(GPIO_TFT_VA_EN, 1);
@@ -608,7 +608,7 @@ static void __init raumfeld_lcd_init(void)
        ret = gpio_request(GPIO_DISPLAY_ENABLE, "display enable");
        if (ret < 0)
-                pr_warning("Unable to request GPIO_DISPLAY_ENABLE\n");
+                pr_warn("Unable to request GPIO_DISPLAY_ENABLE\n");
        else
                gpio_direction_output(GPIO_DISPLAY_ENABLE, 1);
@@ -814,17 +814,17 @@ static void __init raumfeld_power_init(void)
        /* Set PEN2 high to enable maximum charge current */
        ret = gpio_request(GPIO_CHRG_PEN2, "CHRG_PEN2");
        if (ret < 0)
-                pr_warning("Unable to request GPIO_CHRG_PEN2\n");
+                pr_warn("Unable to request GPIO_CHRG_PEN2\n");
        else
                gpio_direction_output(GPIO_CHRG_PEN2, 1);
        ret = gpio_request(GPIO_CHARGE_DC_OK, "CABLE_DC_OK");
        if (ret < 0)
-                pr_warning("Unable to request GPIO_CHARGE_DC_OK\n");
+                pr_warn("Unable to request GPIO_CHARGE_DC_OK\n");
        ret = gpio_request(GPIO_CHARGE_USB_SUSP, "CHARGE_USB_SUSP");
        if (ret < 0)
-                pr_warning("Unable to request GPIO_CHARGE_USB_SUSP\n");
+                pr_warn("Unable to request GPIO_CHARGE_USB_SUSP\n");
        else
                gpio_direction_output(GPIO_CHARGE_USB_SUSP, 0);
@@ -976,19 +976,19 @@ static void __init raumfeld_audio_init(void)
        ret = gpio_request(GPIO_CODEC_RESET, "cs4270 reset");
        if (ret < 0)
-                pr_warning("unable to request GPIO_CODEC_RESET\n");
+                pr_warn("unable to request GPIO_CODEC_RESET\n");
        else
                gpio_direction_output(GPIO_CODEC_RESET, 1);
        ret = gpio_request(GPIO_SPDIF_RESET, "ak4104 s/pdif reset");
        if (ret < 0)
-                pr_warning("unable to request GPIO_SPDIF_RESET\n");
+                pr_warn("unable to request GPIO_SPDIF_RESET\n");
        else
                gpio_direction_output(GPIO_SPDIF_RESET, 1);
        ret = gpio_request(GPIO_MCLK_RESET, "MCLK reset");
        if (ret < 0)
-                pr_warning("unable to request GPIO_MCLK_RESET\n");
+                pr_warn("unable to request GPIO_MCLK_RESET\n");
        else
                gpio_direction_output(GPIO_MCLK_RESET, 1);
@@ -1019,20 +1019,20 @@ static void __init raumfeld_common_init(void)
        ret = gpio_request(GPIO_W2W_RESET, "Wi2Wi reset");
        if (ret < 0)
-                pr_warning("Unable to request GPIO_W2W_RESET\n");
+                pr_warn("Unable to request GPIO_W2W_RESET\n");
        else
                gpio_direction_output(GPIO_W2W_RESET, 0);
        ret = gpio_request(GPIO_W2W_PDN, "Wi2Wi powerup");
        if (ret < 0)
-                pr_warning("Unable to request GPIO_W2W_PDN\n");
+                pr_warn("Unable to request GPIO_W2W_PDN\n");
        else
                gpio_direction_output(GPIO_W2W_PDN, 0);
        /* this can be used to switch off the device */
        ret = gpio_request(GPIO_SHUTDOWN_SUPPLY, "supply shutdown");
        if (ret < 0)
-                pr_warning("Unable to request GPIO_SHUTDOWN_SUPPLY\n");
+                pr_warn("Unable to request GPIO_SHUTDOWN_SUPPLY\n");
        else
                gpio_direction_output(GPIO_SHUTDOWN_SUPPLY, 0);
@@ -1051,7 +1051,7 @@ static void __init raumfeld_controller_init(void)
        ret = gpio_request(GPIO_SHUTDOWN_BATT, "battery shutdown");
        if (ret < 0)
-                pr_warning("Unable to request GPIO_SHUTDOWN_BATT\n");
+                pr_warn("Unable to request GPIO_SHUTDOWN_BATT\n");
        else
                gpio_direction_output(GPIO_SHUTDOWN_BATT, 0);
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 840c3a48e720..962a7f31f596 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -924,6 +924,14 @@ static inline void spitz_i2c_init(void) {}
 #endif
 /******************************************************************************
+ * Audio devices
+ ******************************************************************************/
+static inline void spitz_audio_init(void)
+{
+        platform_device_register_simple("spitz-audio", -1, NULL, 0);
+}
+/******************************************************************************
 * Machine init
 ******************************************************************************/
 static void spitz_poweroff(void)
@@ -970,6 +978,7 @@ static void __init spitz_init(void)
        spitz_nor_init();
        spitz_nand_init();
        spitz_i2c_init();
+        spitz_audio_init();
 }
 static void __init spitz_fixup(struct tag *tags, char **cmdline)
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index c158a6e3e0aa..7780d1faa06f 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -30,7 +30,7 @@
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
-#include <linux/pda_power.h>
+#include <linux/power/gpio-charger.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/pxa2xx_spi.h>
 #include <linux/input/matrix_keypad.h>
@@ -361,44 +361,17 @@ static struct pxaficp_platform_data tosa_ficp_platform_data = {
 /*
 * Tosa AC IN
 */
-static int tosa_power_init(struct device *dev)
-{
-        int ret = gpio_request(TOSA_GPIO_AC_IN, "ac in");
-        if (ret)
-                goto err_gpio_req;
-        ret = gpio_direction_input(TOSA_GPIO_AC_IN);
-        if (ret)
-                goto err_gpio_in;
-        return 0;
-err_gpio_in:
-        gpio_free(TOSA_GPIO_AC_IN);
-err_gpio_req:
-        return ret;
-}
-static void tosa_power_exit(struct device *dev)
-{
-        gpio_free(TOSA_GPIO_AC_IN);
-}
-static int tosa_power_ac_online(void)
-{
-        return gpio_get_value(TOSA_GPIO_AC_IN) == 0;
-}
 static char *tosa_ac_supplied_to[] = {
        "main-battery",
        "backup-battery",
        "jacket-battery",
 };
-static struct pda_power_pdata tosa_power_data = {
+static struct gpio_charger_platform_data tosa_power_data = {
-        .init                   = tosa_power_init,
+        .name                   = "charger",
-        .is_ac_online           = tosa_power_ac_online,
+        .type                   = POWER_SUPPLY_TYPE_MAINS,
-        .exit                   = tosa_power_exit,
+        .gpio                   = TOSA_GPIO_AC_IN,
+        .gpio_active_low        = 1,
        .supplied_to            = tosa_ac_supplied_to,
        .num_supplicants        = ARRAY_SIZE(tosa_ac_supplied_to),
 };
@@ -415,7 +388,7 @@ static struct resource tosa_power_resource[] = {
 };
 static struct platform_device tosa_power_device = {
-        .name                   = "pda-power",
+        .name                   = "gpio-charger",
        .id                     = -1,
        .dev.platform_data      = &tosa_power_data,
        .resource               = tosa_power_resource,
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index 9db2029aa632..565925f37dc5 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -1,6 +1,19 @@
 menu "RealView platform type"
        depends on ARCH_REALVIEW
+config REALVIEW_DT
+        bool "Support RealView(R) Device Tree based boot"
+        select ARM_GIC
+        select MFD_SYSCON
+        select POWER_RESET
+        select POWER_RESET_VERSATILE
+        select POWER_SUPPLY
+        select SOC_REALVIEW
+        select USE_OF
+        help
+          Include support for booting the ARM(R) RealView(R) evaluation
+          boards using a device tree machine description.
 config MACH_REALVIEW_EB
        bool "Support RealView(R) Emulation Baseboard"
        select ARM_GIC
diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile
index 541fa4c109ef..e07fdf7ae8a7 100644
--- a/arch/arm/mach-realview/Makefile
+++ b/arch/arm/mach-realview/Makefile
@@ -3,6 +3,7 @@
 #
 obj-y                                   := core.o
+obj-$(CONFIG_REALVIEW_DT)               += realview-dt.o
 obj-$(CONFIG_MACH_REALVIEW_EB)          += realview_eb.o
 obj-$(CONFIG_MACH_REALVIEW_PB11MP)      += realview_pb11mp.o
 obj-$(CONFIG_MACH_REALVIEW_PB1176)      += realview_pb1176.o
diff --git a/arch/arm/mach-realview/realview-dt.c b/arch/arm/mach-realview/realview-dt.c
new file mode 100644
index 000000000000..cc28b89dd48f
--- /dev/null
+++ b/arch/arm/mach-realview/realview-dt.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2014 Linaro Ltd.
+ *
+ * Author: Linus Walleij <linus.walleij@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/cache-l2x0.h>
+#include "core.h"
+static const char *realview_dt_platform_compat[] __initconst = {
+        "arm,realview-eb",
+        "arm,realview-pb1176",
+        "arm,realview-pb11mp",
+        "arm,realview-pba8",
+        "arm,realview-pbx",
+        NULL,
+};
+DT_MACHINE_START(REALVIEW_DT, "ARM RealView Machine (Device Tree Support)")
+#ifdef CONFIG_ZONE_DMA
+        .dma_zone_size  = SZ_256M,
+#endif
+        .dt_compat      = realview_dt_platform_compat,
+        .l2c_aux_val = 0x0,
+        .l2c_aux_mask = ~0x0,
+MACHINE_END
diff --git a/arch/arm/mach-rockchip/headsmp.S b/arch/arm/mach-rockchip/headsmp.S
index 73206e360e31..46c22dedf632 100644
--- a/arch/arm/mach-rockchip/headsmp.S
+++ b/arch/arm/mach-rockchip/headsmp.S
@@ -16,7 +16,10 @@
 #include <linux/init.h>
 ENTRY(rockchip_secondary_startup)
-        bl      v7_invalidate_l1
+        mrc     p15, 0, r0, c0, c0, 0   @ read main ID register
+        ldr     r1, =0x00000c09         @ Cortex-A9 primary part number
+        teq     r0, r1
+        beq     v7_invalidate_l1
        b       secondary_startup
 ENDPROC(rockchip_secondary_startup)
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 189684f55927..f26fcdca2445 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -19,7 +19,11 @@
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/reset.h>
+#include <linux/cpu.h>
 #include <asm/cacheflush.h>
 #include <asm/cp15.h>
 #include <asm/smp_scu.h>
@@ -37,23 +41,78 @@ static int ncores;
 #define PMU_PWRDN_SCU           4
-static void __iomem *pmu_base_addr;
+static struct regmap *pmu;
-static inline bool pmu_power_domain_is_on(int pd)
+static int pmu_power_domain_is_on(int pd)
 {
-        return !(readl_relaxed(pmu_base_addr + PMU_PWRDN_ST) & BIT(pd));
+        u32 val;
+        int ret;
+        ret = regmap_read(pmu, PMU_PWRDN_ST, &val);
+        if (ret < 0)
+                return ret;
+        return !(val & BIT(pd));
 }
-static void pmu_set_power_domain(int pd, bool on)
+struct reset_control *rockchip_get_core_reset(int cpu)
 {
-        u32 val = readl_relaxed(pmu_base_addr + PMU_PWRDN_CON);
+        struct device *dev = get_cpu_device(cpu);
-        if (on)
+        struct device_node *np;
-                val &= ~BIT(pd);
+        /* The cpu device is only available after the initial core bringup */
+        if (dev)
+                np = dev->of_node;
        else
-                val |=  BIT(pd);
+                np = of_get_cpu_node(cpu, 0);
-        writel(val, pmu_base_addr + PMU_PWRDN_CON);
-        while (pmu_power_domain_is_on(pd) != on) { }
+        return of_reset_control_get(np, NULL);
+}
+static int pmu_set_power_domain(int pd, bool on)
+{
+        u32 val = (on) ? 0 : BIT(pd);
+        int ret;
+        /*
+         * We need to soft reset the cpu when we turn off the cpu power domain,
+         * or else the active processors might be stalled when the individual
+         * processor is powered down.
+         */
+        if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
+                struct reset_control *rstc = rockchip_get_core_reset(pd);
+                if (IS_ERR(rstc)) {
+                        pr_err("%s: could not get reset control for core %d\n",
+                               __func__, pd);
+                        return PTR_ERR(rstc);
+                }
+                if (on)
+                        reset_control_deassert(rstc);
+                else
+                        reset_control_assert(rstc);
+                reset_control_put(rstc);
+        }
+        ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
+        if (ret < 0) {
+                pr_err("%s: could not update power domain\n", __func__);
+                return ret;
+        }
+        ret = -1;
+        while (ret != on) {
+                ret = pmu_power_domain_is_on(pd);
+                if (ret < 0) {
+                        pr_err("%s: could not read power domain state\n",
+                                 __func__);
+                        return ret;
+                }
+        }
+        return 0;
 }
 /*
@@ -63,7 +122,9 @@ static void pmu_set_power_domain(int pd, bool on)
 static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
                                             struct task_struct *idle)
 {
-        if (!sram_base_addr || !pmu_base_addr) {
+        int ret;
+        if (!sram_base_addr || !pmu) {
                pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
                return -ENXIO;
        }
@@ -75,7 +136,24 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
        }
        /* start the core */
-        pmu_set_power_domain(0 + cpu, true);
+        ret = pmu_set_power_domain(0 + cpu, true);
+        if (ret < 0)
+                return ret;
+        if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
+                /* We communicate with the bootrom to active the cpus other
+                 * than cpu0, after a blob of initialize code, they will
+                 * stay at wfe state, once they are actived, they will check
+                 * the mailbox:
+                 * sram_base_addr + 4: 0xdeadbeaf
+                 * sram_base_addr + 8: start address for pc
+                 * */
+                udelay(10);
+                writel(virt_to_phys(rockchip_secondary_startup),
+                        sram_base_addr + 8);
+                writel(0xDEADBEAF, sram_base_addr + 4);
+                dsb_sev();
+        }
        return 0;
 }
@@ -110,8 +188,6 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
                return -EINVAL;
        }
-        sram_base_addr = of_iomap(node, 0);
        /* set the boot function for the sram code */
        rockchip_boot_fn = virt_to_phys(rockchip_secondary_startup);
@@ -125,54 +201,115 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
        return 0;
 }
-static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
+static struct regmap_config rockchip_pmu_regmap_config = {
+        .reg_bits = 32,
+        .val_bits = 32,
+        .reg_stride = 4,
+};
+static int __init rockchip_smp_prepare_pmu(void)
 {
        struct device_node *node;
-        unsigned int i;
+        void __iomem *pmu_base;
-        node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
+        /*
+         * This function is only called via smp_ops->smp_prepare_cpu().
+         * That only happens if a "/cpus" device tree node exists
+         * and has an "enable-method" property that selects the SMP
+         * operations defined herein.
+         */
+        node = of_find_node_by_path("/cpus");
+        pmu = syscon_regmap_lookup_by_phandle(node, "rockchip,pmu");
+        of_node_put(node);
+        if (!IS_ERR(pmu))
+                return 0;
+        pmu = syscon_regmap_lookup_by_compatible("rockchip,rk3066-pmu");
+        if (!IS_ERR(pmu))
+                return 0;
+        /* fallback, create our own regmap for the pmu area */
+        pmu = NULL;
+        node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
        if (!node) {
-                pr_err("%s: missing scu\n", __func__);
+                pr_err("%s: could not find pmu dt node\n", __func__);
-                return;
+                return -ENODEV;
        }
-        scu_base_addr = of_iomap(node, 0);
+        pmu_base = of_iomap(node, 0);
-        if (!scu_base_addr) {
+        if (!pmu_base) {
-                pr_err("%s: could not map scu registers\n", __func__);
+                pr_err("%s: could not map pmu registers\n", __func__);
-                return;
+                return -ENOMEM;
        }
-        node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
+        pmu = regmap_init_mmio(NULL, pmu_base, &rockchip_pmu_regmap_config);
-        if (!node) {
+        if (IS_ERR(pmu)) {
-                pr_err("%s: could not find sram dt node\n", __func__);
+                int ret = PTR_ERR(pmu);
-                return;
+                iounmap(pmu_base);
+                pmu = NULL;
+                pr_err("%s: regmap init failed\n", __func__);
+                return ret;
        }
-        if (rockchip_smp_prepare_sram(node))
+        return 0;
-                return;
+}
-        node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
+static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
+{
+        struct device_node *node;
+        unsigned int i;
+        node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
        if (!node) {
-                pr_err("%s: could not find pmu dt node\n", __func__);
+                pr_err("%s: could not find sram dt node\n", __func__);
                return;
        }
-        pmu_base_addr = of_iomap(node, 0);
+        sram_base_addr = of_iomap(node, 0);
-        if (!pmu_base_addr) {
+        if (!sram_base_addr) {
-                pr_err("%s: could not map pmu registers\n", __func__);
+                pr_err("%s: could not map sram registers\n", __func__);
                return;
        }
-        /* enable the SCU power domain */
+        if (rockchip_smp_prepare_pmu())
-        pmu_set_power_domain(PMU_PWRDN_SCU, true);
+                return;
-        /*
-         * While the number of cpus is gathered from dt, also get the number
-         * of cores from the scu to verify this value when booting the cores.
-         */
-        ncores = scu_get_core_count(scu_base_addr);
-        scu_enable(scu_base_addr);
+        if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
+                if (rockchip_smp_prepare_sram(node))
+                        return;
+                /* enable the SCU power domain */
+                pmu_set_power_domain(PMU_PWRDN_SCU, true);
+                node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
+                if (!node) {
+                        pr_err("%s: missing scu\n", __func__);
+                        return;
+                }
+                scu_base_addr = of_iomap(node, 0);
+                if (!scu_base_addr) {
+                        pr_err("%s: could not map scu registers\n", __func__);
+                        return;
+                }
+                /*
+                 * While the number of cpus is gathered from dt, also get the
+                 * number of cores from the scu to verify this value when
+                 * booting the cores.
+                 */
+                ncores = scu_get_core_count(scu_base_addr);
+                pr_err("%s: ncores %d\n", __func__, ncores);
+                scu_enable(scu_base_addr);
+        } else {
+                unsigned int l2ctlr;
+                asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
+                ncores = ((l2ctlr >> 24) & 0x3) + 1;
+        }
        /* Make sure that all cores except the first are really off */
        for (i = 1; i < ncores; i++)
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
index 8ab9e0e7ff04..d226b71d21d5 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -24,6 +24,12 @@
 #include <asm/hardware/cache-l2x0.h>
 #include "core.h"
+static void __init rockchip_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        platform_device_register_simple("cpufreq-dt", 0, NULL, 0);
+}
 static const char * const rockchip_board_dt_compat[] = {
        "rockchip,rk2928",
        "rockchip,rk3066a",
@@ -37,4 +43,5 @@ DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
        .l2c_aux_val    = 0,
        .l2c_aux_mask   = ~0,
        .dt_compat      = rockchip_board_dt_compat,
+        .init_machine   = rockchip_dt_init,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/h1940-bluetooth.c b/arch/arm/mach-s3c24xx/h1940-bluetooth.c
index b4d14b864367..9c8b1279a4ba 100644
--- a/arch/arm/mach-s3c24xx/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c24xx/h1940-bluetooth.c
@@ -41,7 +41,7 @@ static void h1940bt_enable(int on)
                mdelay(10);
                gpio_set_value(S3C2410_GPH(1), 0);
-                h1940_led_blink_set(-EINVAL, GPIO_LED_BLINK, NULL, NULL);
+                h1940_led_blink_set(NULL, GPIO_LED_BLINK, NULL, NULL);
        }
        else {
                gpio_set_value(S3C2410_GPH(1), 1);
@@ -50,7 +50,7 @@ static void h1940bt_enable(int on)
                mdelay(10);
                gpio_set_value(H1940_LATCH_BLUETOOTH_POWER, 0);
-                h1940_led_blink_set(-EINVAL, GPIO_LED_NO_BLINK_LOW, NULL, NULL);
+                h1940_led_blink_set(NULL, GPIO_LED_NO_BLINK_LOW, NULL, NULL);
        }
 }
diff --git a/arch/arm/mach-s3c24xx/h1940.h b/arch/arm/mach-s3c24xx/h1940.h
index 2950cc466840..596d9f64c5b6 100644
--- a/arch/arm/mach-s3c24xx/h1940.h
+++ b/arch/arm/mach-s3c24xx/h1940.h
@@ -19,8 +19,10 @@
 #define H1940_SUSPEND_RESUMEAT          (0x30081000)
 #define H1940_SUSPEND_CHECK             (0x30080000)
+struct gpio_desc;
 extern void h1940_pm_return(void);
-extern int h1940_led_blink_set(unsigned gpio, int state,
+extern int h1940_led_blink_set(struct gpio_desc *desc, int state,
                               unsigned long *delay_on,
                               unsigned long *delay_off);
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index d35ddc1d9991..d40d4f5244c6 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -359,10 +359,11 @@ static struct platform_device h1940_battery = {
 static DEFINE_SPINLOCK(h1940_blink_spin);
-int h1940_led_blink_set(unsigned gpio, int state,
+int h1940_led_blink_set(struct gpio_desc *desc, int state,
        unsigned long *delay_on, unsigned long *delay_off)
 {
        int blink_gpio, check_gpio1, check_gpio2;
+        int gpio = desc ? desc_to_gpio(desc) : -EINVAL;
        switch (gpio) {
        case H1940_LATCH_LED_GREEN:
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index c3f2682d0c62..1d35ff375a01 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -250,9 +250,10 @@ static void rx1950_disable_charger(void)
 static DEFINE_SPINLOCK(rx1950_blink_spin);
-static int rx1950_led_blink_set(unsigned gpio, int state,
+static int rx1950_led_blink_set(struct gpio_desc *desc, int state,
        unsigned long *delay_on, unsigned long *delay_off)
 {
+        int gpio = desc_to_gpio(desc);
        int blink_gpio, check_gpio;
        switch (gpio) {
diff --git a/arch/arm/mach-s3c64xx/cpuidle.c b/arch/arm/mach-s3c64xx/cpuidle.c
index 3c8ab07c2012..2eb072440dfa 100644
--- a/arch/arm/mach-s3c64xx/cpuidle.c
+++ b/arch/arm/mach-s3c64xx/cpuidle.c
@@ -48,7 +48,6 @@ static struct cpuidle_driver s3c64xx_cpuidle_driver = {
                        .enter            = s3c64xx_enter_idle,
                        .exit_latency     = 1,
                        .target_residency = 1,
-                        .flags            = CPUIDLE_FLAG_TIME_VALID,
                        .name             = "IDLE",
                        .desc             = "System active, ARM gated",
                },
diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c
index ff02e2da99f2..b704433c529c 100644
--- a/arch/arm/mach-sa1100/pci-nanoengine.c
+++ b/arch/arm/mach-sa1100/pci-nanoengine.c
@@ -33,12 +33,12 @@
 static DEFINE_SPINLOCK(nano_lock);
 static int nanoengine_get_pci_address(struct pci_bus *bus,
-        unsigned int devfn, int where, unsigned long *address)
+        unsigned int devfn, int where, void __iomem **address)
 {
        int ret = PCIBIOS_DEVICE_NOT_FOUND;
        unsigned int busnr = bus->number;
-        *address = NANO_PCI_CONFIG_SPACE_VIRT +
+        *address = (void __iomem *)NANO_PCI_CONFIG_SPACE_VIRT +
                ((bus->number << 16) | (devfn << 8) | (where & ~3));
        ret = (busnr > 255 || devfn > 255 || where > 255) ?
@@ -51,7 +51,7 @@ static int nanoengine_read_config(struct pci_bus *bus, unsigned int devfn, int w
        int size, u32 *val)
 {
        int ret;
-        unsigned long address;
+        void __iomem *address;
        unsigned long flags;
        u32 v;
@@ -85,7 +85,7 @@ static int nanoengine_write_config(struct pci_bus *bus, unsigned int devfn, int
        int size, u32 val)
 {
        int ret;
-        unsigned long address;
+        void __iomem *address;
        unsigned long flags;
        unsigned shift;
        u32 v;
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 21f457b56c01..1b4fafe524ff 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -1,5 +1,6 @@
 config ARCH_SHMOBILE
        bool
+        select ZONE_DMA if ARM_LPAE
 config PM_RCAR
        bool
@@ -18,6 +19,7 @@ config ARCH_RCAR_GEN2
        select PM_RCAR if PM || SMP
        select RENESAS_IRQC
        select SYS_SUPPORTS_SH_CMT
+        select PCI_DOMAINS if PCI
 config ARCH_RMOBILE
        bool
@@ -36,7 +38,6 @@ menuconfig ARCH_SHMOBILE_MULTI
        select NO_IOPORT_MAP
        select PINCTRL
        select ARCH_REQUIRE_GPIOLIB
-        select ARCH_HAS_OPP
 if ARCH_SHMOBILE_MULTI
@@ -73,11 +74,6 @@ config ARCH_R8A7794
 comment "Renesas ARM SoCs Board Type"
-config MACH_KOELSCH
-        bool "Koelsch board"
-        depends on ARCH_R8A7791
-        select MICREL_PHY if SH_ETH
 config MACH_LAGER
        bool "Lager board"
        depends on ARCH_R8A7790
@@ -145,14 +141,6 @@ config ARCH_R8A7790
        select MIGHT_HAVE_PCI
        select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
-config ARCH_R8A7791
-        bool "R-Car M2-W (R8A77910)"
-        select ARCH_RCAR_GEN2
-        select ARCH_WANT_OPTIONAL_GPIOLIB
-        select ARM_GIC
-        select MIGHT_HAVE_PCI
-        select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
 comment "Renesas ARM SoCs Board Type"
 config MACH_APE6EVM
@@ -227,12 +215,6 @@ config MACH_LAGER
        select MICREL_PHY if SH_ETH
        select SND_SOC_AK4642 if SND_SIMPLE_CARD
-config MACH_KOELSCH
-        bool "Koelsch board"
-        depends on ARCH_R8A7791
-        select USE_OF
-        select MICREL_PHY if SH_ETH
 config MACH_KZM9G
        bool "KZM-A9-GT board"
        depends on ARCH_SH73A0
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index e20f2786ec72..b55cac0e5b2b 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -19,8 +19,8 @@ obj-$(CONFIG_ARCH_EMEV2)	+= setup-emev2.o
 obj-$(CONFIG_ARCH_R7S72100)     += setup-r7s72100.o
 # Clock objects
-obj-y                           += clock.o
 ifndef CONFIG_COMMON_CLK
+obj-y                           += clock.o
 obj-$(CONFIG_ARCH_SH7372)       += clock-sh7372.o
 obj-$(CONFIG_ARCH_SH73A0)       += clock-sh73a0.o
 obj-$(CONFIG_ARCH_R8A73A4)      += clock-r8a73a4.o
@@ -28,7 +28,6 @@ obj-$(CONFIG_ARCH_R8A7740)	+= clock-r8a7740.o
 obj-$(CONFIG_ARCH_R8A7778)      += clock-r8a7778.o
 obj-$(CONFIG_ARCH_R8A7779)      += clock-r8a7779.o
 obj-$(CONFIG_ARCH_R8A7790)      += clock-r8a7790.o
-obj-$(CONFIG_ARCH_R8A7791)      += clock-r8a7791.o
 endif
 # CPU reset vector handling objects
@@ -36,6 +35,7 @@ cpu-y				:= platsmp.o headsmp.o
 # Shared SoC family objects
 obj-$(CONFIG_ARCH_RCAR_GEN2)    += setup-rcar-gen2.o platsmp-apmu.o $(cpu-y)
+CFLAGS_setup-rcar-gen2.o        += -march=armv7-a
 # SMP objects
 smp-y                           := $(cpu-y)
@@ -57,7 +57,6 @@ obj-$(CONFIG_ARCH_SH7372)	+= entry-intc.o sleep-sh7372.o
 # Board objects
 ifdef CONFIG_ARCH_SHMOBILE_MULTI
-obj-$(CONFIG_MACH_KOELSCH)      += board-koelsch-reference.o
 obj-$(CONFIG_MACH_LAGER)        += board-lager-reference.o
 obj-$(CONFIG_MACH_MARZEN)       += board-marzen-reference.o
 else
@@ -69,7 +68,6 @@ obj-$(CONFIG_MACH_BOCKW_REFERENCE)	+= board-bockw-reference.o
 obj-$(CONFIG_MACH_MARZEN)       += board-marzen.o
 obj-$(CONFIG_MACH_LAGER)        += board-lager.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA)      += board-armadillo800eva.o
-obj-$(CONFIG_MACH_KOELSCH)      += board-koelsch.o
 obj-$(CONFIG_MACH_KZM9G)        += board-kzm9g.o
 obj-$(CONFIG_MACH_KZM9G_REFERENCE)      += board-kzm9g-reference.o
 endif
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index de9a23852fc8..57d00ed6ec0c 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -5,7 +5,6 @@ loadaddr-$(CONFIG_MACH_APE6EVM_REFERENCE) += 0x40008000
 loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000
 loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
 loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
-loadaddr-$(CONFIG_MACH_KOELSCH) += 0x40008000
 loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
 loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
 loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000
diff --git a/arch/arm/mach-shmobile/board-ape6evm-reference.c b/arch/arm/mach-shmobile/board-ape6evm-reference.c
index a6503d8c77de..3b68370b03a0 100644
--- a/arch/arm/mach-shmobile/board-ape6evm-reference.c
+++ b/arch/arm/mach-shmobile/board-ape6evm-reference.c
@@ -12,10 +12,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/gpio.h>
@@ -48,7 +44,6 @@ static void __init ape6evm_add_standard_devices(void)
        clk_put(parent);
        clk_put(mp);
-        r8a73a4_add_dt_devices();
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
index b222f68d55b7..66f67816a844 100644
--- a/arch/arm/mach-shmobile/board-ape6evm.c
+++ b/arch/arm/mach-shmobile/board-ape6evm.c
@@ -12,10 +12,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/gpio.h>
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index e70983534403..6d949f1c850b 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -12,53 +12,48 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
 */
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/err.h>
-#include <linux/kernel.h>
-#include <linux/input.h>
-#include <linux/platform_data/st1232_pdata.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
-#include <linux/regulator/driver.h>
+#include <linux/i2c-gpio.h>
+#include <linux/input.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/mfd/tmio.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sh_mmcif.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/pinctrl/machine.h>
+#include <linux/platform_data/st1232_pdata.h>
+#include <linux/platform_device.h>
 #include <linux/pwm.h>
 #include <linux/pwm_backlight.h>
+#include <linux/reboot.h>
+#include <linux/regulator/driver.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/gpio-regulator.h>
 #include <linux/regulator/machine.h>
 #include <linux/sh_eth.h>
-#include <linux/videodev2.h>
 #include <linux/usb/renesas_usbhs.h>
-#include <linux/mfd/tmio.h>
+#include <linux/videodev2.h>
-#include <linux/mmc/host.h>
-#include <linux/mmc/sh_mmcif.h>
-#include <linux/mmc/sh_mobile_sdhi.h>
-#include <linux/i2c-gpio.h>
-#include <linux/reboot.h>
-#include <media/mt9t112.h>
+#include <asm/hardware/cache-l2x0.h>
-#include <media/sh_mobile_ceu.h>
-#include <media/soc_camera.h>
-#include <asm/page.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <asm/hardware/cache-l2x0.h>
+#include <asm/page.h>
-#include <video/sh_mobile_lcdc.h>
+#include <media/mt9t112.h>
-#include <video/sh_mobile_hdmi.h>
+#include <media/sh_mobile_ceu.h>
+#include <media/soc_camera.h>
 #include <sound/sh_fsi.h>
 #include <sound/simple_card.h>
+#include <video/sh_mobile_hdmi.h>
+#include <video/sh_mobile_lcdc.h>
 #include "common.h"
 #include "irqs.h"
@@ -1234,8 +1229,15 @@ static void __init eva_init(void)
        static struct pm_domain_device domain_devices[] __initdata = {
                { "A4LC", &lcdc0_device },
                { "A4LC", &hdmi_lcdc_device },
+                { "A4MP", &hdmi_device },
+                { "A4MP", &fsi_device },
+                { "A4R",  &ceu0_device },
+                { "A4S",  &sh_eth_device },
+                { "A3SP", &pwm_device },
+                { "A3SP", &sdhi0_device },
+                { "A3SP", &sh_mmcif_device },
        };
-        struct platform_device *usb = NULL;
+        struct platform_device *usb = NULL, *sdhi1 = NULL;
        regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
                                     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
@@ -1304,6 +1306,7 @@ static void __init eva_init(void)
                platform_device_register(&vcc_sdhi1);
                platform_device_register(&sdhi1_device);
+                sdhi1 = &sdhi1_device;
        }
@@ -1324,6 +1327,8 @@ static void __init eva_init(void)
                                       ARRAY_SIZE(domain_devices));
        if (usb)
                rmobile_add_device_to_domain("A3SP", usb);
+        if (sdhi1)
+                rmobile_add_device_to_domain("A3SP", sdhi1);
        r8a7740_pm_init();
 }
diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c
index 79c47847f200..d649ade4a202 100644
--- a/arch/arm/mach-shmobile/board-bockw-reference.c
+++ b/arch/arm/mach-shmobile/board-bockw-reference.c
@@ -12,10 +12,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/of_platform.h>
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
index 1cf2c75dacfb..f27b5a833bf0 100644
--- a/arch/arm/mach-shmobile/board-bockw.c
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -13,10 +13,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/mfd/tmio.h>
diff --git a/arch/arm/mach-shmobile/board-koelsch-reference.c b/arch/arm/mach-shmobile/board-koelsch-reference.c
deleted file mode 100644
index 46aa540133d6..000000000000
--- a/arch/arm/mach-shmobile/board-koelsch-reference.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Koelsch board support - Reference DT implementation
- *
- * Copyright (C) 2013  Renesas Electronics Corporation
- * Copyright (C) 2013  Renesas Solutions Corp.
- * Copyright (C) 2013  Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/dma-mapping.h>
-#include <linux/kernel.h>
-#include <linux/of_platform.h>
-#include <linux/platform_data/rcar-du.h>
-#include <asm/mach/arch.h>
-#include "clock.h"
-#include "common.h"
-#include "irqs.h"
-#include "r8a7791.h"
-#include "rcar-gen2.h"
-/* DU */
-static struct rcar_du_encoder_data koelsch_du_encoders[] = {
-        {
-                .type = RCAR_DU_ENCODER_NONE,
-                .output = RCAR_DU_OUTPUT_LVDS0,
-                .connector.lvds.panel = {
-                        .width_mm = 210,
-                        .height_mm = 158,
-                        .mode = {
-                                .pixelclock = 65000000,
-                                .hactive = 1024,
-                                .hfront_porch = 20,
-                                .hback_porch = 160,
-                                .hsync_len = 136,
-                                .vactive = 768,
-                                .vfront_porch = 3,
-                                .vback_porch = 29,
-                                .vsync_len = 6,
-                        },
-                },
-        },
-};
-static struct rcar_du_platform_data koelsch_du_pdata = {
-        .encoders = koelsch_du_encoders,
-        .num_encoders = ARRAY_SIZE(koelsch_du_encoders),
-};
-static const struct resource du_resources[] __initconst = {
-        DEFINE_RES_MEM(0xfeb00000, 0x40000),
-        DEFINE_RES_MEM_NAMED(0xfeb90000, 0x1c, "lvds.0"),
-        DEFINE_RES_IRQ(gic_spi(256)),
-        DEFINE_RES_IRQ(gic_spi(268)),
-};
-static void __init koelsch_add_du_device(void)
-{
-        struct platform_device_info info = {
-                .name = "rcar-du-r8a7791",
-                .id = -1,
-                .res = du_resources,
-                .num_res = ARRAY_SIZE(du_resources),
-                .data = &koelsch_du_pdata,
-                .size_data = sizeof(koelsch_du_pdata),
-                .dma_mask = DMA_BIT_MASK(32),
-        };
-        platform_device_register_full(&info);
-}
-/*
- * This is a really crude hack to provide clkdev support to platform
- * devices until they get moved to DT.
- */
-static const struct clk_name clk_names[] __initconst = {
-        { "du0", "du.0", "rcar-du-r8a7791" },
-        { "du1", "du.1", "rcar-du-r8a7791" },
-        { "lvds0", "lvds.0", "rcar-du-r8a7791" },
-};
-static void __init koelsch_add_standard_devices(void)
-{
-        shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false);
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-        koelsch_add_du_device();
-}
-static const char * const koelsch_boards_compat_dt[] __initconst = {
-        "renesas,koelsch",
-        "renesas,koelsch-reference",
-        NULL,
-};
-DT_MACHINE_START(KOELSCH_DT, "koelsch")
-        .smp            = smp_ops(r8a7791_smp_ops),
-        .init_early     = shmobile_init_delay,
-        .init_time      = rcar_gen2_timer_init,
-        .init_machine   = koelsch_add_standard_devices,
-        .init_late      = shmobile_init_late,
-        .reserve        = rcar_gen2_reserve,
-        .dt_compat      = koelsch_boards_compat_dt,
-MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-koelsch.c b/arch/arm/mach-shmobile/board-koelsch.c
deleted file mode 100644
index 7111b5c1d67b..000000000000
--- a/arch/arm/mach-shmobile/board-koelsch.c
+++ /dev/null
@@ -1,527 +0,0 @@
-/*
- * Koelsch board support
- *
- * Copyright (C) 2013  Renesas Electronics Corporation
- * Copyright (C) 2013-2014  Renesas Solutions Corp.
- * Copyright (C) 2013  Magnus Damm
- * Copyright (C) 2014  Cogent Embedded, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/irq.h>
-#include <linux/kernel.h>
-#include <linux/leds.h>
-#include <linux/mfd/tmio.h>
-#include <linux/mmc/host.h>
-#include <linux/mmc/sh_mobile_sdhi.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/phy.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/platform_data/gpio-rcar.h>
-#include <linux/platform_data/rcar-du.h>
-#include <linux/platform_device.h>
-#include <linux/regulator/driver.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/gpio-regulator.h>
-#include <linux/regulator/machine.h>
-#include <linux/sh_eth.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/rspi.h>
-#include <linux/spi/spi.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include "common.h"
-#include "irqs.h"
-#include "r8a7791.h"
-#include "rcar-gen2.h"
-/* DU */
-static struct rcar_du_encoder_data koelsch_du_encoders[] = {
-        {
-                .type = RCAR_DU_ENCODER_NONE,
-                .output = RCAR_DU_OUTPUT_LVDS0,
-                .connector.lvds.panel = {
-                        .width_mm = 210,
-                        .height_mm = 158,
-                        .mode = {
-                                .pixelclock = 65000000,
-                                .hactive = 1024,
-                                .hfront_porch = 20,
-                                .hback_porch = 160,
-                                .hsync_len = 136,
-                                .vactive = 768,
-                                .vfront_porch = 3,
-                                .vback_porch = 29,
-                                .vsync_len = 6,
-                        },
-                },
-        },
-};
-static const struct rcar_du_platform_data koelsch_du_pdata __initconst = {
-        .encoders = koelsch_du_encoders,
-        .num_encoders = ARRAY_SIZE(koelsch_du_encoders),
-};
-static const struct resource du_resources[] __initconst = {
-        DEFINE_RES_MEM(0xfeb00000, 0x40000),
-        DEFINE_RES_MEM_NAMED(0xfeb90000, 0x1c, "lvds.0"),
-        DEFINE_RES_IRQ(gic_spi(256)),
-        DEFINE_RES_IRQ(gic_spi(268)),
-};
-static void __init koelsch_add_du_device(void)
-{
-        struct platform_device_info info = {
-                .name = "rcar-du-r8a7791",
-                .id = -1,
-                .res = du_resources,
-                .num_res = ARRAY_SIZE(du_resources),
-                .data = &koelsch_du_pdata,
-                .size_data = sizeof(koelsch_du_pdata),
-                .dma_mask = DMA_BIT_MASK(32),
-        };
-        platform_device_register_full(&info);
-}
-/* Ether */
-static const struct sh_eth_plat_data ether_pdata __initconst = {
-        .phy                    = 0x1,
-        .phy_irq                = irq_pin(0),
-        .edmac_endian           = EDMAC_LITTLE_ENDIAN,
-        .phy_interface          = PHY_INTERFACE_MODE_RMII,
-        .ether_link_active_low  = 1,
-};
-static const struct resource ether_resources[] __initconst = {
-        DEFINE_RES_MEM(0xee700000, 0x400),
-        DEFINE_RES_IRQ(gic_spi(162)),
-};
-static const struct platform_device_info ether_info __initconst = {
-        .name           = "r8a7791-ether",
-        .id             = -1,
-        .res            = ether_resources,
-        .num_res        = ARRAY_SIZE(ether_resources),
-        .data           = &ether_pdata,
-        .size_data      = sizeof(ether_pdata),
-        .dma_mask       = DMA_BIT_MASK(32),
-};
-/* LEDS */
-static struct gpio_led koelsch_leds[] = {
-        {
-                .name           = "led8",
-                .gpio           = RCAR_GP_PIN(2, 21),
-                .default_state  = LEDS_GPIO_DEFSTATE_ON,
-        }, {
-                .name           = "led7",
-                .gpio           = RCAR_GP_PIN(2, 20),
-                .default_state  = LEDS_GPIO_DEFSTATE_ON,
-        }, {
-                .name           = "led6",
-                .gpio           = RCAR_GP_PIN(2, 19),
-                .default_state  = LEDS_GPIO_DEFSTATE_ON,
-        },
-};
-static const struct gpio_led_platform_data koelsch_leds_pdata __initconst = {
-        .leds           = koelsch_leds,
-        .num_leds       = ARRAY_SIZE(koelsch_leds),
-};
-/* GPIO KEY */
-#define GPIO_KEY(c, g, d, ...) \
-        { .code = c, .gpio = g, .desc = d, .active_low = 1, \
-          .wakeup = 1, .debounce_interval = 20 }
-static struct gpio_keys_button gpio_buttons[] = {
-        GPIO_KEY(KEY_4,         RCAR_GP_PIN(5, 3),      "SW2-pin4"),
-        GPIO_KEY(KEY_3,         RCAR_GP_PIN(5, 2),      "SW2-pin3"),
-        GPIO_KEY(KEY_2,         RCAR_GP_PIN(5, 1),      "SW2-pin2"),
-        GPIO_KEY(KEY_1,         RCAR_GP_PIN(5, 0),      "SW2-pin1"),
-        GPIO_KEY(KEY_G,         RCAR_GP_PIN(7, 6),      "SW36"),
-        GPIO_KEY(KEY_F,         RCAR_GP_PIN(7, 5),      "SW35"),
-        GPIO_KEY(KEY_E,         RCAR_GP_PIN(7, 4),      "SW34"),
-        GPIO_KEY(KEY_D,         RCAR_GP_PIN(7, 3),      "SW33"),
-        GPIO_KEY(KEY_C,         RCAR_GP_PIN(7, 2),      "SW32"),
-        GPIO_KEY(KEY_B,         RCAR_GP_PIN(7, 1),      "SW31"),
-        GPIO_KEY(KEY_A,         RCAR_GP_PIN(7, 0),      "SW30"),
-};
-static const struct gpio_keys_platform_data koelsch_keys_pdata __initconst = {
-        .buttons        = gpio_buttons,
-        .nbuttons       = ARRAY_SIZE(gpio_buttons),
-};
-/* QSPI */
-static const struct resource qspi_resources[] __initconst = {
-        DEFINE_RES_MEM(0xe6b10000, 0x1000),
-        DEFINE_RES_IRQ_NAMED(gic_spi(184), "mux"),
-};
-static const struct rspi_plat_data qspi_pdata __initconst = {
-        .num_chipselect = 1,
-};
-/* SPI Flash memory (Spansion S25FL512SAGMFIG11 64 MiB) */
-static struct mtd_partition spi_flash_part[] = {
-        {
-                .name           = "loader",
-                .offset         = 0x00000000,
-                .size           = 512 * 1024,
-                .mask_flags     = MTD_WRITEABLE,
-        },
-        {
-                .name           = "bootenv",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 512 * 1024,
-                .mask_flags     = MTD_WRITEABLE,
-        },
-        {
-                .name           = "data",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = MTDPART_SIZ_FULL,
-        },
-};
-static const struct flash_platform_data spi_flash_data = {
-        .name           = "m25p80",
-        .parts          = spi_flash_part,
-        .nr_parts       = ARRAY_SIZE(spi_flash_part),
-        .type           = "s25fl512s",
-};
-static const struct spi_board_info spi_info[] __initconst = {
-        {
-                .modalias       = "m25p80",
-                .platform_data  = &spi_flash_data,
-                .mode           = SPI_MODE_0 | SPI_TX_QUAD | SPI_RX_QUAD,
-                .max_speed_hz   = 30000000,
-                .bus_num        = 0,
-                .chip_select    = 0,
-        },
-};
-/* SATA0 */
-static const struct resource sata0_resources[] __initconst = {
-        DEFINE_RES_MEM(0xee300000, 0x2000),
-        DEFINE_RES_IRQ(gic_spi(105)),
-};
-static const struct platform_device_info sata0_info __initconst = {
-        .name           = "sata-r8a7791",
-        .id             = 0,
-        .res            = sata0_resources,
-        .num_res        = ARRAY_SIZE(sata0_resources),
-        .dma_mask       = DMA_BIT_MASK(32),
-};
-/* I2C */
-static const struct resource i2c_resources[] __initconst = {
-        /* I2C0 */
-        DEFINE_RES_MEM(0xE6508000, 0x40),
-        DEFINE_RES_IRQ(gic_spi(287)),
-        /* I2C1 */
-        DEFINE_RES_MEM(0xE6518000, 0x40),
-        DEFINE_RES_IRQ(gic_spi(288)),
-        /* I2C2 */
-        DEFINE_RES_MEM(0xE6530000, 0x40),
-        DEFINE_RES_IRQ(gic_spi(286)),
-        /* I2C3 */
-        DEFINE_RES_MEM(0xE6540000, 0x40),
-        DEFINE_RES_IRQ(gic_spi(290)),
-        /* I2C4 */
-        DEFINE_RES_MEM(0xE6520000, 0x40),
-        DEFINE_RES_IRQ(gic_spi(19)),
-        /* I2C5 */
-        DEFINE_RES_MEM(0xE6528000, 0x40),
-        DEFINE_RES_IRQ(gic_spi(20)),
-};
-static void __init koelsch_add_i2c(unsigned idx)
-{
-        unsigned res_idx = idx * 2;
-        BUG_ON(res_idx >= ARRAY_SIZE(i2c_resources));
-        platform_device_register_simple("i2c-rcar_gen2", idx,
-                                        i2c_resources + res_idx, 2);
-}
-#define SDHI_REGULATOR(idx, vdd_pin, vccq_pin)                          \
-static struct regulator_consumer_supply vcc_sdhi##idx##_consumer =      \
-        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi." #idx);               \
-                                                                        \
-static struct regulator_init_data vcc_sdhi##idx##_init_data = {         \
-        .constraints = {                                                \
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,              \
-        },                                                              \
-        .consumer_supplies      = &vcc_sdhi##idx##_consumer,            \
-        .num_consumer_supplies  = 1,                                    \
-};                                                                      \
-                                                                        \
-static const struct fixed_voltage_config vcc_sdhi##idx##_info __initconst = {\
-        .supply_name    = "SDHI" #idx "Vcc",                            \
-        .microvolts     = 3300000,                                      \
-        .gpio           = vdd_pin,                                      \
-        .enable_high    = 1,                                            \
-        .init_data      = &vcc_sdhi##idx##_init_data,                   \
-};                                                                      \
-                                                                        \
-static struct regulator_consumer_supply vccq_sdhi##idx##_consumer =     \
-        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi." #idx);              \
-                                                                        \
-static struct regulator_init_data vccq_sdhi##idx##_init_data = {        \
-        .constraints = {                                                \
-                .input_uV       = 3300000,                              \
-                .min_uV         = 1800000,                              \
-                .max_uV         = 3300000,                              \
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |            \
-                                  REGULATOR_CHANGE_STATUS,              \
-        },                                                              \
-        .consumer_supplies      = &vccq_sdhi##idx##_consumer,           \
-        .num_consumer_supplies  = 1,                                    \
-};                                                                      \
-                                                                        \
-static struct gpio vccq_sdhi##idx##_gpio =                              \
-        { vccq_pin, GPIOF_OUT_INIT_HIGH, "vccq-sdhi" #idx };            \
-                                                                        \
-static struct gpio_regulator_state vccq_sdhi##idx##_states[] = {        \
-        { .value = 1800000, .gpios = 0 },                               \
-        { .value = 3300000, .gpios = 1 },                               \
-};                                                                      \
-                                                                        \
-static const struct gpio_regulator_config vccq_sdhi##idx##_info __initconst = {\
-        .supply_name    = "vqmmc",                                      \
-        .gpios          = &vccq_sdhi##idx##_gpio,                       \
-        .nr_gpios       = 1,                                            \
-        .states         = vccq_sdhi##idx##_states,                      \
-        .nr_states      = ARRAY_SIZE(vccq_sdhi##idx##_states),          \
-        .type           = REGULATOR_VOLTAGE,                            \
-        .init_data      = &vccq_sdhi##idx##_init_data,                  \
-};
-SDHI_REGULATOR(0, RCAR_GP_PIN(7, 17), RCAR_GP_PIN(2, 12));
-SDHI_REGULATOR(1, RCAR_GP_PIN(7, 18), RCAR_GP_PIN(2, 13));
-SDHI_REGULATOR(2, RCAR_GP_PIN(7, 19), RCAR_GP_PIN(2, 26));
-/* SDHI0 */
-static struct sh_mobile_sdhi_info sdhi0_info __initdata = {
-        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
-                          MMC_CAP_POWER_OFF_CARD,
-        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
-};
-static struct resource sdhi0_resources[] __initdata = {
-        DEFINE_RES_MEM(0xee100000, 0x200),
-        DEFINE_RES_IRQ(gic_spi(165)),
-};
-/* SDHI1 */
-static struct sh_mobile_sdhi_info sdhi1_info __initdata = {
-        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
-                          MMC_CAP_POWER_OFF_CARD,
-        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
-};
-static struct resource sdhi1_resources[] __initdata = {
-        DEFINE_RES_MEM(0xee140000, 0x100),
-        DEFINE_RES_IRQ(gic_spi(167)),
-};
-/* SDHI2 */
-static struct sh_mobile_sdhi_info sdhi2_info __initdata = {
-        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
-                          MMC_CAP_POWER_OFF_CARD,
-        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT |
-                          TMIO_MMC_WRPROTECT_DISABLE,
-};
-static struct resource sdhi2_resources[] __initdata = {
-        DEFINE_RES_MEM(0xee160000, 0x100),
-        DEFINE_RES_IRQ(gic_spi(168)),
-};
-static const struct pinctrl_map koelsch_pinctrl_map[] = {
-        /* DU */
-        PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7791", "pfc-r8a7791",
-                                  "du_rgb666", "du"),
-        PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7791", "pfc-r8a7791",
-                                  "du_sync", "du"),
-        PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7791", "pfc-r8a7791",
-                                  "du_clk_out_0", "du"),
-        /* Ether */
-        PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791",
-                                  "eth_link", "eth"),
-        PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791",
-                                  "eth_mdio", "eth"),
-        PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791",
-                                  "eth_rmii", "eth"),
-        PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791",
-                                  "intc_irq0", "intc"),
-        /* QSPI */
-        PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7791",
-                                  "qspi_ctrl", "qspi"),
-        PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7791",
-                                  "qspi_data4", "qspi"),
-        /* SCIF0 (CN19: DEBUG SERIAL0) */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7791",
-                                  "scif0_data_d", "scif0"),
-        /* SCIF1 (CN20: DEBUG SERIAL1) */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7791",
-                                  "scif1_data_d", "scif1"),
-        /* I2C1 */
-        PIN_MAP_MUX_GROUP_DEFAULT("i2c-rcar_gen2.1", "pfc-r8a7791",
-                                  "i2c1_e", "i2c1"),
-        /* I2C2 */
-        PIN_MAP_MUX_GROUP_DEFAULT("i2c-rcar_gen2.2", "pfc-r8a7791",
-                                  "i2c2", "i2c2"),
-        /* I2C4 */
-        PIN_MAP_MUX_GROUP_DEFAULT("i2c-rcar_gen2.4", "pfc-r8a7791",
-                                  "i2c4_c", "i2c4"),
-        /* SDHI0 */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7791",
-                                  "sdhi0_data4", "sdhi0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7791",
-                                  "sdhi0_ctrl", "sdhi0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7791",
-                                  "sdhi0_cd", "sdhi0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7791",
-                                  "sdhi0_wp", "sdhi0"),
-        /* SDHI2 */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7791",
-                                  "sdhi1_data4", "sdhi1"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7791",
-                                  "sdhi1_ctrl", "sdhi1"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7791",
-                                  "sdhi1_cd", "sdhi1"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7791",
-                                  "sdhi1_wp", "sdhi1"),
-        /* SDHI2 */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7791",
-                                  "sdhi2_data4", "sdhi2"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7791",
-                                  "sdhi2_ctrl", "sdhi2"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7791",
-                                  "sdhi2_cd", "sdhi2"),
-};
-static void __init koelsch_add_standard_devices(void)
-{
-        r8a7791_clock_init();
-        pinctrl_register_mappings(koelsch_pinctrl_map,
-                                  ARRAY_SIZE(koelsch_pinctrl_map));
-        r8a7791_pinmux_init();
-        r8a7791_add_standard_devices();
-        platform_device_register_full(&ether_info);
-        platform_device_register_data(NULL, "leds-gpio", -1,
-                                      &koelsch_leds_pdata,
-                                      sizeof(koelsch_leds_pdata));
-        platform_device_register_data(NULL, "gpio-keys", -1,
-                                      &koelsch_keys_pdata,
-                                      sizeof(koelsch_keys_pdata));
-        platform_device_register_resndata(NULL, "qspi", 0,
-                                          qspi_resources,
-                                          ARRAY_SIZE(qspi_resources),
-                                          &qspi_pdata, sizeof(qspi_pdata));
-        spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
-        koelsch_add_du_device();
-        platform_device_register_full(&sata0_info);
-        koelsch_add_i2c(1);
-        koelsch_add_i2c(2);
-        koelsch_add_i2c(4);
-        koelsch_add_i2c(5);
-        platform_device_register_data(NULL, "reg-fixed-voltage", 0,
-                                      &vcc_sdhi0_info, sizeof(struct fixed_voltage_config));
-        platform_device_register_data(NULL, "reg-fixed-voltage", 1,
-                                      &vcc_sdhi1_info, sizeof(struct fixed_voltage_config));
-        platform_device_register_data(NULL, "reg-fixed-voltage", 2,
-                                      &vcc_sdhi2_info, sizeof(struct fixed_voltage_config));
-        platform_device_register_data(NULL, "gpio-regulator", 0,
-                                      &vccq_sdhi0_info, sizeof(struct gpio_regulator_config));
-        platform_device_register_data(NULL, "gpio-regulator", 1,
-                                      &vccq_sdhi1_info, sizeof(struct gpio_regulator_config));
-        platform_device_register_data(NULL, "gpio-regulator", 2,
-                                      &vccq_sdhi2_info, sizeof(struct gpio_regulator_config));
-        platform_device_register_resndata(NULL, "sh_mobile_sdhi", 0,
-                                          sdhi0_resources, ARRAY_SIZE(sdhi0_resources),
-                                          &sdhi0_info, sizeof(struct sh_mobile_sdhi_info));
-        platform_device_register_resndata(NULL, "sh_mobile_sdhi", 1,
-                                          sdhi1_resources, ARRAY_SIZE(sdhi1_resources),
-                                          &sdhi1_info, sizeof(struct sh_mobile_sdhi_info));
-        platform_device_register_resndata(NULL, "sh_mobile_sdhi", 2,
-                                          sdhi2_resources, ARRAY_SIZE(sdhi2_resources),
-                                          &sdhi2_info, sizeof(struct sh_mobile_sdhi_info));
-}
-/*
- * Ether LEDs on the Koelsch board are named LINK and ACTIVE which corresponds
- * to non-default 01 setting of the Micrel KSZ8041 PHY control register 1 bits
- * 14-15. We have to set them back to 01 from the default 00 value each time
- * the PHY is reset. It's also important because the PHY's LED0 signal is
- * connected to SoC's ETH_LINK signal and in the PHY's default mode it will
- * bounce on and off after each packet, which we apparently want to avoid.
- */
-static int koelsch_ksz8041_fixup(struct phy_device *phydev)
-{
-        u16 phyctrl1 = phy_read(phydev, 0x1e);
-        phyctrl1 &= ~0xc000;
-        phyctrl1 |= 0x4000;
-        return phy_write(phydev, 0x1e, phyctrl1);
-}
-static void __init koelsch_init(void)
-{
-        koelsch_add_standard_devices();
-        irq_set_irq_type(irq_pin(0), IRQ_TYPE_LEVEL_LOW);
-        if (IS_ENABLED(CONFIG_PHYLIB))
-                phy_register_fixup_for_id("r8a7791-ether-ff:01",
-                                          koelsch_ksz8041_fixup);
-}
-static const char * const koelsch_boards_compat_dt[] __initconst = {
-        "renesas,koelsch",
-        NULL,
-};
-DT_MACHINE_START(KOELSCH_DT, "koelsch")
-        .smp            = smp_ops(r8a7791_smp_ops),
-        .init_early     = shmobile_init_delay,
-        .init_time      = rcar_gen2_timer_init,
-        .init_machine   = koelsch_init,
-        .init_late      = shmobile_init_late,
-        .reserve        = rcar_gen2_reserve,
-        .dt_compat      = koelsch_boards_compat_dt,
-MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index d9cdf9a97e23..2e82e44ab852 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -14,10 +14,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/delay.h>
@@ -43,6 +39,13 @@ static void __init kzm_init(void)
 #endif
 }
+#define RESCNT2 IOMEM(0xe6188020)
+static void kzm9g_restart(enum reboot_mode mode, const char *cmd)
+{
+        /* Do soft power on reset */
+        writel((1 << 31), RESCNT2);
+}
 static const char *kzm9g_boards_compat_dt[] __initdata = {
        "renesas,kzm9g-reference",
        NULL,
@@ -54,5 +57,6 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g-reference")
        .init_early     = shmobile_init_delay,
        .init_machine   = kzm_init,
        .init_late      = shmobile_init_late,
+        .restart        = kzm9g_restart,
        .dt_compat      = kzm9g_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 77e36fa0b142..7c9b63bdde9f 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -11,10 +11,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/delay.h>
diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c
index bc4b48357dde..fa06bdba61df 100644
--- a/arch/arm/mach-shmobile/board-lager-reference.c
+++ b/arch/arm/mach-shmobile/board-lager-reference.c
@@ -12,100 +12,17 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
-#include <linux/dma-mapping.h>
 #include <linux/init.h>
 #include <linux/of_platform.h>
-#include <linux/platform_data/rcar-du.h>
 #include <asm/mach/arch.h>
-#include "clock.h"
 #include "common.h"
-#include "irqs.h"
 #include "r8a7790.h"
 #include "rcar-gen2.h"
-/* DU */
-static struct rcar_du_encoder_data lager_du_encoders[] = {
-        {
-                .type = RCAR_DU_ENCODER_VGA,
-                .output = RCAR_DU_OUTPUT_DPAD0,
-        }, {
-                .type = RCAR_DU_ENCODER_NONE,
-                .output = RCAR_DU_OUTPUT_LVDS1,
-                .connector.lvds.panel = {
-                        .width_mm = 210,
-                        .height_mm = 158,
-                        .mode = {
-                                .pixelclock = 65000000,
-                                .hactive = 1024,
-                                .hfront_porch = 20,
-                                .hback_porch = 160,
-                                .hsync_len = 136,
-                                .vactive = 768,
-                                .vfront_porch = 3,
-                                .vback_porch = 29,
-                                .vsync_len = 6,
-                        },
-                },
-        },
-};
-static struct rcar_du_platform_data lager_du_pdata = {
-        .encoders = lager_du_encoders,
-        .num_encoders = ARRAY_SIZE(lager_du_encoders),
-};
-static const struct resource du_resources[] __initconst = {
-        DEFINE_RES_MEM(0xfeb00000, 0x70000),
-        DEFINE_RES_MEM_NAMED(0xfeb90000, 0x1c, "lvds.0"),
-        DEFINE_RES_MEM_NAMED(0xfeb94000, 0x1c, "lvds.1"),
-        DEFINE_RES_IRQ(gic_spi(256)),
-        DEFINE_RES_IRQ(gic_spi(268)),
-        DEFINE_RES_IRQ(gic_spi(269)),
-};
-static void __init lager_add_du_device(void)
-{
-        struct platform_device_info info = {
-                .name = "rcar-du-r8a7790",
-                .id = -1,
-                .res = du_resources,
-                .num_res = ARRAY_SIZE(du_resources),
-                .data = &lager_du_pdata,
-                .size_data = sizeof(lager_du_pdata),
-                .dma_mask = DMA_BIT_MASK(32),
-        };
-        platform_device_register_full(&info);
-}
-/*
- * This is a really crude hack to provide clkdev support to platform
- * devices until they get moved to DT.
- */
-static const struct clk_name clk_names[] __initconst = {
-        { "du0", "du.0", "rcar-du-r8a7790" },
-        { "du1", "du.1", "rcar-du-r8a7790" },
-        { "du2", "du.2", "rcar-du-r8a7790" },
-        { "lvds0", "lvds.0", "rcar-du-r8a7790" },
-        { "lvds1", "lvds.1", "rcar-du-r8a7790" },
-};
-static void __init lager_add_standard_devices(void)
-{
-        shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false);
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-        lager_add_du_device();
-}
 static const char *lager_boards_compat_dt[] __initdata = {
        "renesas,lager",
        "renesas,lager-reference",
@@ -116,7 +33,6 @@ DT_MACHINE_START(LAGER_DT, "lager")
        .smp            = smp_ops(r8a7790_smp_ops),
        .init_early     = shmobile_init_delay,
        .init_time      = rcar_gen2_timer_init,
-        .init_machine   = lager_add_standard_devices,
        .init_late      = shmobile_init_late,
        .reserve        = rcar_gen2_reserve,
        .dt_compat      = lager_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index 571327b1c942..b47262afb240 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -13,10 +13,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/gpio.h>
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index ca5d34b92aa7..a1c1dfb6a67a 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -16,10 +16,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/delay.h>
 #include <linux/kernel.h>
@@ -1153,7 +1149,7 @@ static struct soc_camera_platform_info camera_info = {
        .format_name = "UYVY",
        .format_depth = 16,
        .format = {
-                .code = V4L2_MBUS_FMT_UYVY8_2X8,
+                .code = MEDIA_BUS_FMT_UYVY8_2X8,
                .colorspace = V4L2_COLORSPACE_SMPTE170M,
                .field = V4L2_FIELD_NONE,
                .width = 640,
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index 38d9cdd26587..b15eb923263f 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -13,10 +13,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/clk/shmobile.h>
@@ -26,7 +22,6 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
-#include "clock.h"
 #include "common.h"
 #include "irqs.h"
 #include "r8a7779.h"
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index ce33d7825c49..994dc7d86ae2 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -13,10 +13,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index c2330ea1802c..1cf44dc6d718 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -12,10 +12,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/init.h>
 #include <linux/io.h>
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 19df9cb30495..9cac8247c72b 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -12,10 +12,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
 #include <linux/init.h>
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index 67980a08a601..e8510c35558c 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -17,10 +17,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
 /*
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index c51f9db3f66f..fa8ab2cc9187 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -12,10 +12,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
 #include <linux/bitops.h>
 #include <linux/init.h>
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index f62265200592..f9bbc5f0a9a1 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -12,10 +12,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/init.h>
 #include <linux/io.h>
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
deleted file mode 100644
index 453b23129cfa..000000000000
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ /dev/null
@@ -1,342 +0,0 @@
-/*
- * r8a7791 clock framework support
- *
- * Copyright (C) 2013  Renesas Electronics Corporation
- * Copyright (C) 2013  Renesas Solutions Corp.
- * Copyright (C) 2013  Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/sh_clk.h>
-#include <linux/clkdev.h>
-#include "clock.h"
-#include "common.h"
-#include "rcar-gen2.h"
-/*
- *   MD         EXTAL           PLL0    PLL1    PLL3
- * 14 13 19     (MHz)           *1      *1
- *---------------------------------------------------
- * 0  0  0      15 x 1          x172/2  x208/2  x106
- * 0  0  1      15 x 1          x172/2  x208/2  x88
- * 0  1  0      20 x 1          x130/2  x156/2  x80
- * 0  1  1      20 x 1          x130/2  x156/2  x66
- * 1  0  0      26 / 2          x200/2  x240/2  x122
- * 1  0  1      26 / 2          x200/2  x240/2  x102
- * 1  1  0      30 / 2          x172/2  x208/2  x106
- * 1  1  1      30 / 2          x172/2  x208/2  x88
- *
- * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
- *      see "p1 / 2" on R8A7791_CLOCK_ROOT() below
- */
-#define CPG_BASE 0xe6150000
-#define CPG_LEN 0x1000
-#define SMSTPCR0        0xE6150130
-#define SMSTPCR1        0xE6150134
-#define SMSTPCR2        0xe6150138
-#define SMSTPCR3        0xE615013C
-#define SMSTPCR5        0xE6150144
-#define SMSTPCR7        0xe615014c
-#define SMSTPCR8        0xE6150990
-#define SMSTPCR9        0xE6150994
-#define SMSTPCR10       0xE6150998
-#define SMSTPCR11       0xE615099C
-#define MSTPSR1         IOMEM(0xe6150038)
-#define MSTPSR2         IOMEM(0xe6150040)
-#define MSTPSR3         IOMEM(0xe6150048)
-#define MSTPSR5         IOMEM(0xe615003c)
-#define MSTPSR7         IOMEM(0xe61501c4)
-#define MSTPSR8         IOMEM(0xe61509a0)
-#define MSTPSR9         IOMEM(0xe61509a4)
-#define MSTPSR11        IOMEM(0xe61509ac)
-#define SDCKCR          0xE6150074
-#define SD1CKCR         0xE6150078
-#define SD2CKCR         0xE615026c
-#define MMC0CKCR        0xE6150240
-#define MMC1CKCR        0xE6150244
-#define SSPCKCR         0xE6150248
-#define SSPRSCKCR       0xE615024C
-static struct clk_mapping cpg_mapping = {
-        .phys   = CPG_BASE,
-        .len    = CPG_LEN,
-};
-static struct clk extal_clk = {
-        /* .rate will be updated on r8a7791_clock_init() */
-        .mapping        = &cpg_mapping,
-};
-static struct sh_clk_ops followparent_clk_ops = {
-        .recalc = followparent_recalc,
-};
-static struct clk main_clk = {
-        /* .parent will be set r8a73a4_clock_init */
-        .ops    = &followparent_clk_ops,
-};
-/*
- * clock ratio of these clock will be updated
- * on r8a7791_clock_init()
- */
-SH_FIXED_RATIO_CLK_SET(pll1_clk,                main_clk,       1, 1);
-SH_FIXED_RATIO_CLK_SET(pll3_clk,                main_clk,       1, 1);
-SH_FIXED_RATIO_CLK_SET(qspi_clk,                pll1_clk,       1, 1);
-/* fixed ratio clock */
-SH_FIXED_RATIO_CLK_SET(extal_div2_clk,          extal_clk,      1, 2);
-SH_FIXED_RATIO_CLK_SET(cp_clk,                  extal_clk,      1, 2);
-SH_FIXED_RATIO_CLK_SET(pll1_div2_clk,           pll1_clk,       1, 2);
-SH_FIXED_RATIO_CLK_SET(hp_clk,                  pll1_clk,       1, 12);
-SH_FIXED_RATIO_CLK_SET(p_clk,                   pll1_clk,       1, 24);
-SH_FIXED_RATIO_CLK_SET(rclk_clk,                pll1_clk,       1, (48 * 1024));
-SH_FIXED_RATIO_CLK_SET(mp_clk,                  pll1_div2_clk,  1, 15);
-SH_FIXED_RATIO_CLK_SET(zg_clk,                  pll1_clk,       1, 3);
-SH_FIXED_RATIO_CLK_SET(zx_clk,                  pll1_clk,       1, 3);
-SH_FIXED_RATIO_CLK_SET(zs_clk,                  pll1_clk,       1, 6);
-static struct clk *main_clks[] = {
-        &extal_clk,
-        &extal_div2_clk,
-        &main_clk,
-        &pll1_clk,
-        &pll1_div2_clk,
-        &pll3_clk,
-        &hp_clk,
-        &p_clk,
-        &qspi_clk,
-        &rclk_clk,
-        &mp_clk,
-        &cp_clk,
-        &zg_clk,
-        &zx_clk,
-        &zs_clk,
-};
-/* SDHI (DIV4) clock */
-static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
-static struct clk_div_mult_table div4_div_mult_table = {
-        .divisors = divisors,
-        .nr_divisors = ARRAY_SIZE(divisors),
-};
-static struct clk_div4_table div4_table = {
-        .div_mult_table = &div4_div_mult_table,
-};
-enum {
-        DIV4_SDH, DIV4_SD0,
-        DIV4_NR
-};
-static struct clk div4_clks[DIV4_NR] = {
-        [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
-        [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
-};
-/* DIV6 clocks */
-enum {
-        DIV6_SD1, DIV6_SD2,
-        DIV6_NR
-};
-static struct clk div6_clks[DIV6_NR] = {
-        [DIV6_SD1]      = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0),
-        [DIV6_SD2]      = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
-};
-/* MSTP */
-enum {
-        MSTP1108, MSTP1107, MSTP1106,
-        MSTP931, MSTP930, MSTP929, MSTP928, MSTP927, MSTP925,
-        MSTP917,
-        MSTP815, MSTP814,
-        MSTP813,
-        MSTP811, MSTP810, MSTP809,
-        MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
-        MSTP719, MSTP718, MSTP715, MSTP714,
-        MSTP522,
-        MSTP314, MSTP312, MSTP311,
-        MSTP216, MSTP207, MSTP206,
-        MSTP204, MSTP203, MSTP202,
-        MSTP124,
-        MSTP_NR
-};
-static struct clk mstp_clks[MSTP_NR] = {
-        [MSTP1108] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 8, MSTPSR11, 0), /* SCIFA5 */
-        [MSTP1107] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 7, MSTPSR11, 0), /* SCIFA4 */
-        [MSTP1106] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 6, MSTPSR11, 0), /* SCIFA3 */
-        [MSTP931] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
-        [MSTP930] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
-        [MSTP929] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
-        [MSTP928] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
-        [MSTP927] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */
-        [MSTP925] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */
-        [MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
-        [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
-        [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
-        [MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
-        [MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
-        [MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
-        [MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 9, MSTPSR8, 0), /* VIN2 */
-        [MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
-        [MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
-        [MSTP723] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 23, MSTPSR7, 0), /* DU1 */
-        [MSTP721] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 21, MSTPSR7, 0), /* SCIF0 */
-        [MSTP720] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 20, MSTPSR7, 0), /* SCIF1 */
-        [MSTP719] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 19, MSTPSR7, 0), /* SCIF2 */
-        [MSTP718] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 18, MSTPSR7, 0), /* SCIF3 */
-        [MSTP715] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 15, MSTPSR7, 0), /* SCIF4 */
-        [MSTP714] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 14, MSTPSR7, 0), /* SCIF5 */
-        [MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
-        [MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */
-        [MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD1], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI1 */
-        [MSTP311] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD2], SMSTPCR3, 11, MSTPSR3, 0), /* SDHI2 */
-        [MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
-        [MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
-        [MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
-        [MSTP204] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 4, MSTPSR2, 0), /* SCIFA0 */
-        [MSTP203] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 3, MSTPSR2, 0), /* SCIFA1 */
-        [MSTP202] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 2, MSTPSR2, 0), /* SCIFA2 */
-        [MSTP124] = SH_CLK_MSTP32_STS(&rclk_clk, SMSTPCR1, 24, MSTPSR1, 0), /* CMT0 */
-};
-static struct clk_lookup lookups[] = {
-        /* main clocks */
-        CLKDEV_CON_ID("extal",          &extal_clk),
-        CLKDEV_CON_ID("extal_div2",     &extal_div2_clk),
-        CLKDEV_CON_ID("main",           &main_clk),
-        CLKDEV_CON_ID("pll1",           &pll1_clk),
-        CLKDEV_CON_ID("pll1_div2",      &pll1_div2_clk),
-        CLKDEV_CON_ID("pll3",           &pll3_clk),
-        CLKDEV_CON_ID("zg",             &zg_clk),
-        CLKDEV_CON_ID("zs",             &zs_clk),
-        CLKDEV_CON_ID("hp",             &hp_clk),
-        CLKDEV_CON_ID("p",              &p_clk),
-        CLKDEV_CON_ID("qspi",           &qspi_clk),
-        CLKDEV_CON_ID("rclk",           &rclk_clk),
-        CLKDEV_CON_ID("mp",             &mp_clk),
-        CLKDEV_CON_ID("cp",             &cp_clk),
-        CLKDEV_CON_ID("peripheral_clk", &hp_clk),
-        /* MSTP */
-        CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7791", &mstp_clks[MSTP726]),
-        CLKDEV_ICK_ID("du.0", "rcar-du-r8a7791", &mstp_clks[MSTP724]),
-        CLKDEV_ICK_ID("du.1", "rcar-du-r8a7791", &mstp_clks[MSTP723]),
-        CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
-        CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
-        CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */
-        CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), /* SCIFB1 */
-        CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), /* SCIFB2 */
-        CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]), /* SCIFA2 */
-        CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]), /* SCIF0 */
-        CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), /* SCIF1 */
-        CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP719]), /* SCIF2 */
-        CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP718]), /* SCIF3 */
-        CLKDEV_DEV_ID("sh-sci.10", &mstp_clks[MSTP715]), /* SCIF4 */
-        CLKDEV_DEV_ID("sh-sci.11", &mstp_clks[MSTP714]), /* SCIF5 */
-        CLKDEV_DEV_ID("sh-sci.12", &mstp_clks[MSTP1106]), /* SCIFA3 */
-        CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1107]), /* SCIFA4 */
-        CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1108]), /* SCIFA5 */
-        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
-        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP312]),
-        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]),
-        CLKDEV_ICK_ID("fck", "sh-cmt-48-gen2.0", &mstp_clks[MSTP124]),
-        CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
-        CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
-        CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
-        CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]),
-        CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]),
-        CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
-        CLKDEV_DEV_ID("i2c-rcar_gen2.4", &mstp_clks[MSTP927]),
-        CLKDEV_DEV_ID("i2c-rcar_gen2.5", &mstp_clks[MSTP925]),
-        CLKDEV_DEV_ID("r8a7791-ether", &mstp_clks[MSTP813]), /* Ether */
-        CLKDEV_DEV_ID("r8a7791-vin.0", &mstp_clks[MSTP811]),
-        CLKDEV_DEV_ID("r8a7791-vin.1", &mstp_clks[MSTP810]),
-        CLKDEV_DEV_ID("r8a7791-vin.2", &mstp_clks[MSTP809]),
-        CLKDEV_DEV_ID("sata-r8a7791.0", &mstp_clks[MSTP815]),
-        CLKDEV_DEV_ID("sata-r8a7791.1", &mstp_clks[MSTP814]),
-};
-#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31)              \
-        extal_clk.rate  = e * 1000 * 1000;                      \
-        main_clk.parent = m;                                    \
-        SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1);           \
-        if (mode & MD(19))                                      \
-                SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1);      \
-        else                                                    \
-                SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
-void __init r8a7791_clock_init(void)
-{
-        u32 mode = rcar_gen2_read_mode_pins();
-        int k, ret = 0;
-        switch (mode & (MD(14) | MD(13))) {
-        case 0:
-                R8A7791_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
-                break;
-        case MD(13):
-                R8A7791_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
-                break;
-        case MD(14):
-                R8A7791_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102);
-                break;
-        case MD(13) | MD(14):
-                R8A7791_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88);
-                break;
-        }
-        if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
-                SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
-        else
-                SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
-        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
-                ret = clk_register(main_clks[k]);
-        if (!ret)
-                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
-        if (!ret)
-                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
-        if (!ret)
-                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-        if (!ret)
-                shmobile_clk_init();
-        else
-                goto epanic;
-        return;
-epanic:
-        panic("failed to setup r8a7791 clocks\n");
-}
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 7071676145c4..3bc92f46060e 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -11,10 +11,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
 #include <linux/init.h>
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 02a6f45a0b9e..6b4c1f313cc9 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -11,10 +11,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
 #include <linux/init.h>
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c
index 806f94038cc4..34f056fc3756 100644
--- a/arch/arm/mach-shmobile/clock.c
+++ b/arch/arm/mach-shmobile/clock.c
@@ -14,41 +14,13 @@
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
 */
+#include <linux/export.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
-#ifdef CONFIG_COMMON_CLK
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include "clock.h"
-void __init shmobile_clk_workaround(const struct clk_name *clks,
-                                    int nr_clks, bool enable)
-{
-        const struct clk_name *clkn;
-        struct clk *clk;
-        unsigned int i;
-        for (i = 0; i < nr_clks; ++i) {
-                clkn = clks + i;
-                clk = clk_get(NULL, clkn->clk);
-                if (!IS_ERR(clk)) {
-                        clk_register_clkdev(clk, clkn->con_id, clkn->dev_id);
-                        if (enable)
-                                clk_prepare_enable(clk);
-                        clk_put(clk);
-                }
-        }
-}
-#else /* CONFIG_COMMON_CLK */
 #include <linux/sh_clk.h>
-#include <linux/export.h>
 #include "clock.h"
 #include "common.h"
@@ -84,5 +56,3 @@ void __clk_put(struct clk *clk)
 {
 }
 EXPORT_SYMBOL(__clk_put);
-#endif /* CONFIG_COMMON_CLK */
diff --git a/arch/arm/mach-shmobile/clock.h b/arch/arm/mach-shmobile/clock.h
index 31b6417463e6..cf3552ea1019 100644
--- a/arch/arm/mach-shmobile/clock.h
+++ b/arch/arm/mach-shmobile/clock.h
@@ -1,19 +1,6 @@
 #ifndef CLOCK_H
 #define CLOCK_H
-#ifdef CONFIG_COMMON_CLK
-/* temporary clock configuration helper for platform devices */
-struct clk_name {
-        const char *clk;
-        const char *con_id;
-        const char *dev_id;
-};
-void shmobile_clk_workaround(const struct clk_name *clks, int nr_clks,
-                             bool enable);
-#else /* CONFIG_COMMON_CLK */
 /* legacy clock implementation */
 struct clk;
@@ -52,5 +39,4 @@ do {			\
        (p)->div = d;   \
 } while (0)
-#endif /* CONFIG_COMMON_CLK */
 #endif
diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index 72087c79ad7b..309025efd4cf 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -19,11 +19,6 @@ extern void shmobile_boot_scu(void);
 extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus);
 extern void shmobile_smp_scu_cpu_die(unsigned int cpu);
 extern int shmobile_smp_scu_cpu_kill(unsigned int cpu);
-extern void shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus);
-extern int shmobile_smp_apmu_boot_secondary(unsigned int cpu,
-                                            struct task_struct *idle);
-extern void shmobile_smp_apmu_cpu_die(unsigned int cpu);
-extern int shmobile_smp_apmu_cpu_kill(unsigned int cpu);
 struct clk;
 extern int shmobile_clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);
diff --git a/arch/arm/mach-shmobile/console.c b/arch/arm/mach-shmobile/console.c
index f2e79f2376e1..e329ccbd0a67 100644
--- a/arch/arm/mach-shmobile/console.c
+++ b/arch/arm/mach-shmobile/console.c
@@ -11,10 +11,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/kernel.h>
 #include <linux/init.h>
diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S
index f45dde701d7b..69df8bfac167 100644
--- a/arch/arm/mach-shmobile/headsmp-scu.S
+++ b/arch/arm/mach-shmobile/headsmp-scu.S
@@ -12,11 +12,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
 */
 #include <linux/linkage.h>
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index e2af00b1bd9d..1ccf49cb485f 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -11,10 +11,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/kernel.h>
 #include <linux/init.h>
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index 44457a94897b..9e3618028acc 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -11,10 +11,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/kernel.h>
 #include <linux/init.h>
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
index 2c06810d3a70..f483b560b066 100644
--- a/arch/arm/mach-shmobile/platsmp-apmu.c
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -1,6 +1,7 @@
 /*
 * SMP support for SoCs with APMU
 *
+ * Copyright (C) 2014  Renesas Electronics Corporation
 * Copyright (C) 2013  Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
@@ -22,6 +23,7 @@
 #include <asm/smp_plat.h>
 #include <asm/suspend.h>
 #include "common.h"
+#include "platsmp-apmu.h"
 static struct {
        void __iomem *iomem;
@@ -83,28 +85,15 @@ static void apmu_init_cpu(struct resource *res, int cpu, int bit)
        pr_debug("apmu ioremap %d %d %pr\n", cpu, bit, res);
 }
-static struct {
+static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit),
-        struct resource iomem;
+                           struct rcar_apmu_config *apmu_config, int num)
-        int cpus[4];
-} apmu_config[] = {
-        {
-                .iomem = DEFINE_RES_MEM(0xe6152000, 0x88),
-                .cpus = { 0, 1, 2, 3 },
-        },
-        {
-                .iomem = DEFINE_RES_MEM(0xe6151000, 0x88),
-                .cpus = { 0x100, 0x101, 0x102, 0x103 },
-        }
-};
-static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit))
 {
        u32 id;
        int k;
        int bit, index;
        bool is_allowed;
-        for (k = 0; k < ARRAY_SIZE(apmu_config); k++) {
+        for (k = 0; k < num; k++) {
                /* only enable the cluster that includes the boot CPU */
                is_allowed = false;
                for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) {
@@ -128,14 +117,16 @@ static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit))
        }
 }
-void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus)
+void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
+                                           struct rcar_apmu_config *apmu_config,
+                                           int num)
 {
        /* install boot code shared by all CPUs */
        shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
        shmobile_boot_arg = MPIDR_HWID_BITMASK;
        /* perform per-cpu setup */
-        apmu_parse_cfg(apmu_init_cpu);
+        apmu_parse_cfg(apmu_init_cpu, apmu_config, num);
 }
 #ifdef CONFIG_SMP
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.h b/arch/arm/mach-shmobile/platsmp-apmu.h
new file mode 100644
index 000000000000..76512c9a2545
--- /dev/null
+++ b/arch/arm/mach-shmobile/platsmp-apmu.h
@@ -0,0 +1,32 @@
+/*
+ * rmobile apmu definition
+ *
+ * Copyright (C) 2014  Renesas Electronics Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef PLATSMP_APMU_H
+#define PLATSMP_APMU_H
+struct rcar_apmu_config {
+        struct resource iomem;
+        int cpus[4];
+};
+extern void shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
+                                           struct rcar_apmu_config *apmu_config,
+                                           int num);
+extern int shmobile_smp_apmu_boot_secondary(unsigned int cpu,
+                                            struct task_struct *idle);
+extern void shmobile_smp_apmu_cpu_die(unsigned int cpu);
+extern int shmobile_smp_apmu_cpu_kill(unsigned int cpu);
+#endif /* PLATSMP_APMU_H */
diff --git a/arch/arm/mach-shmobile/pm-r8a7740.c b/arch/arm/mach-shmobile/pm-r8a7740.c
index e3f146448237..ac2eecd6f5ea 100644
--- a/arch/arm/mach-shmobile/pm-r8a7740.c
+++ b/arch/arm/mach-shmobile/pm-r8a7740.c
@@ -14,10 +14,10 @@
 #include "pm-rmobile.h"
 #if defined(CONFIG_PM) && !defined(CONFIG_ARCH_MULTIPLATFORM)
-static int r8a7740_pd_a4s_suspend(void)
+static int r8a7740_pd_a3sm_suspend(void)
 {
        /*
-         * The A4S domain contains the CPU core and therefore it should
+         * The A3SM domain contains the CPU core and therefore it should
         * only be turned off if the CPU is not in use.
         */
        return -EBUSY;
@@ -32,29 +32,65 @@ static int r8a7740_pd_a3sp_suspend(void)
        return console_suspend_enabled ? 0 : -EBUSY;
 }
+static int r8a7740_pd_d4_suspend(void)
+{
+        /*
+         * The D4 domain contains the Coresight-ETM hardware block and
+         * therefore it should only be turned off if the debug module is
+         * not in use.
+         */
+        return -EBUSY;
+}
 static struct rmobile_pm_domain r8a7740_pm_domains[] = {
        {
                .genpd.name     = "A4LC",
                .bit_shift      = 1,
        }, {
+                .genpd.name     = "A4MP",
+                .bit_shift      = 2,
+        }, {
+                .genpd.name     = "D4",
+                .bit_shift      = 3,
+                .gov            = &pm_domain_always_on_gov,
+                .suspend        = r8a7740_pd_d4_suspend,
+        }, {
+                .genpd.name     = "A4R",
+                .bit_shift      = 5,
+        }, {
+                .genpd.name     = "A3RV",
+                .bit_shift      = 6,
+        }, {
                .genpd.name     = "A4S",
                .bit_shift      = 10,
-                .gov            = &pm_domain_always_on_gov,
                .no_debug       = true,
-                .suspend        = r8a7740_pd_a4s_suspend,
        }, {
                .genpd.name     = "A3SP",
                .bit_shift      = 11,
                .gov            = &pm_domain_always_on_gov,
                .no_debug       = true,
                .suspend        = r8a7740_pd_a3sp_suspend,
+        }, {
+                .genpd.name     = "A3SM",
+                .bit_shift      = 12,
+                .gov            = &pm_domain_always_on_gov,
+                .suspend        = r8a7740_pd_a3sm_suspend,
+        }, {
+                .genpd.name     = "A3SG",
+                .bit_shift      = 13,
+        }, {
+                .genpd.name     = "A4SU",
+                .bit_shift      = 20,
        },
 };
 void __init r8a7740_init_pm_domains(void)
 {
        rmobile_init_domains(r8a7740_pm_domains, ARRAY_SIZE(r8a7740_pm_domains));
+        pm_genpd_add_subdomain_names("A4R", "A3RV");
        pm_genpd_add_subdomain_names("A4S", "A3SP");
+        pm_genpd_add_subdomain_names("A4S", "A3SM");
+        pm_genpd_add_subdomain_names("A4S", "A3SG");
 }
 #endif /* CONFIG_PM && !CONFIG_ARCH_MULTIPLATFORM */
diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c
index 82fe3d7f9662..44a74c4c5a01 100644
--- a/arch/arm/mach-shmobile/pm-r8a7779.c
+++ b/arch/arm/mach-shmobile/pm-r8a7779.c
@@ -83,9 +83,8 @@ static void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd)
 {
        struct generic_pm_domain *genpd = &r8a7779_pd->genpd;
+        genpd->flags = GENPD_FLAG_PM_CLK;
        pm_genpd_init(genpd, NULL, false);
-        genpd->dev_ops.stop = pm_clk_suspend;
-        genpd->dev_ops.start = pm_clk_resume;
        genpd->dev_ops.active_wakeup = pd_active_wakeup;
        genpd->power_off = pd_power_down;
        genpd->power_on = pd_power_up;
diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c
index 717e6413d29c..6f7d56ecf969 100644
--- a/arch/arm/mach-shmobile/pm-rmobile.c
+++ b/arch/arm/mach-shmobile/pm-rmobile.c
@@ -106,9 +106,8 @@ static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
        struct generic_pm_domain *genpd = &rmobile_pd->genpd;
        struct dev_power_governor *gov = rmobile_pd->gov;
+        genpd->flags = GENPD_FLAG_PM_CLK;
        pm_genpd_init(genpd, gov ? : &simple_qos_governor, false);
-        genpd->dev_ops.stop             = pm_clk_suspend;
-        genpd->dev_ops.start            = pm_clk_resume;
        genpd->dev_ops.active_wakeup    = rmobile_pd_active_wakeup;
        genpd->power_off                = rmobile_pd_power_down;
        genpd->power_on                 = rmobile_pd_power_up;
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
index 7e5c2676c489..0e37da654ed5 100644
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -423,7 +423,6 @@ static struct cpuidle_driver sh7372_cpuidle_driver = {
                .desc = "Core Standby Mode",
                .exit_latency = 10,
                .target_residency = 20 + 10,
-                .flags = CPUIDLE_FLAG_TIME_VALID,
                .enter = sh7372_enter_core_standby,
        },
        .states[2] = {
@@ -431,7 +430,6 @@ static struct cpuidle_driver sh7372_cpuidle_driver = {
                .desc = "A3SM PLL ON",
                .exit_latency = 20,
                .target_residency = 30 + 20,
-                .flags = CPUIDLE_FLAG_TIME_VALID,
                .enter = sh7372_enter_a3sm_pll_on,
        },
        .states[3] = {
@@ -439,7 +437,6 @@ static struct cpuidle_driver sh7372_cpuidle_driver = {
                .desc = "A3SM PLL OFF",
                .exit_latency = 120,
                .target_residency = 30 + 120,
-                .flags = CPUIDLE_FLAG_TIME_VALID,
                .enter = sh7372_enter_a3sm_pll_off,
        },
        .states[4] = {
@@ -447,7 +444,6 @@ static struct cpuidle_driver sh7372_cpuidle_driver = {
                .desc = "A4S PLL OFF",
                .exit_latency = 240,
                .target_residency = 30 + 240,
-                .flags = CPUIDLE_FLAG_TIME_VALID,
                .enter = sh7372_enter_a4s,
                .disabled = true,
        },
diff --git a/arch/arm/mach-shmobile/r8a73a4.h b/arch/arm/mach-shmobile/r8a73a4.h
index 5fafd6fcedf7..70dcd847a86e 100644
--- a/arch/arm/mach-shmobile/r8a73a4.h
+++ b/arch/arm/mach-shmobile/r8a73a4.h
@@ -11,7 +11,6 @@ enum {
 };
 void r8a73a4_add_standard_devices(void);
-void r8a73a4_add_dt_devices(void);
 void r8a73a4_clock_init(void);
 void r8a73a4_pinmux_init(void);
diff --git a/arch/arm/mach-shmobile/r8a7740.h b/arch/arm/mach-shmobile/r8a7740.h
index f369b4b0863d..ca7805ad7ea3 100644
--- a/arch/arm/mach-shmobile/r8a7740.h
+++ b/arch/arm/mach-shmobile/r8a7740.h
@@ -10,10 +10,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #ifndef __ASM_R8A7740_H__
diff --git a/arch/arm/mach-shmobile/r8a7778.h b/arch/arm/mach-shmobile/r8a7778.h
index f4076a50e970..f64fedb1f2cc 100644
--- a/arch/arm/mach-shmobile/r8a7778.h
+++ b/arch/arm/mach-shmobile/r8a7778.h
@@ -11,10 +11,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #ifndef __ASM_R8A7778_H__
 #define __ASM_R8A7778_H__
@@ -71,7 +67,6 @@ extern void r8a7778_add_standard_devices_dt(void);
 extern void r8a7778_add_dt_devices(void);
 extern void r8a7778_init_late(void);
-extern void r8a7778_init_delay(void);
 extern void r8a7778_init_irq_dt(void);
 extern void r8a7778_clock_init(void);
 extern void r8a7778_init_irq_extpin(int irlm);
diff --git a/arch/arm/mach-shmobile/r8a7791.h b/arch/arm/mach-shmobile/r8a7791.h
index c1bf7abefa5a..6cf11eb69d10 100644
--- a/arch/arm/mach-shmobile/r8a7791.h
+++ b/arch/arm/mach-shmobile/r8a7791.h
@@ -1,9 +1,6 @@
 #ifndef __ASM_R8A7791_H__
 #define __ASM_R8A7791_H__
-void r8a7791_add_standard_devices(void);
-void r8a7791_clock_init(void);
-void r8a7791_pinmux_init(void);
 void r8a7791_pm_init(void);
 extern struct smp_operations r8a7791_smp_ops;
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index b06a9e8f59a5..aad97be9cbe1 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -11,10 +11,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/kernel.h>
 #include <linux/init.h>
diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c
index 4122104359f9..171174777b6f 100644
--- a/arch/arm/mach-shmobile/setup-r7s72100.c
+++ b/arch/arm/mach-shmobile/setup-r7s72100.c
@@ -12,10 +12,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index 53f40b70680d..c27682291cbf 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -12,10 +12,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/irq.h>
 #include <linux/kernel.h>
@@ -180,18 +176,13 @@ static struct resource cmt1_resources[] = {
        DEFINE_RES_IRQ(gic_spi(120)),
 };
-#define r8a7790_register_cmt(idx)                                       \
+#define r8a73a4_register_cmt(idx)                                       \
        platform_device_register_resndata(NULL, "sh-cmt-48-gen2",       \
                                          idx, cmt##idx##_resources,    \
                                          ARRAY_SIZE(cmt##idx##_resources), \
                                          &cmt##idx##_platform_data,    \
                                          sizeof(struct sh_timer_config))
-void __init r8a73a4_add_dt_devices(void)
-{
-        r8a7790_register_cmt(1);
-}
 /* DMA */
 static const struct sh_dmae_slave_config dma_slaves[] = {
        {
@@ -282,7 +273,7 @@ static struct resource dma_resources[] = {
 void __init r8a73a4_add_standard_devices(void)
 {
-        r8a73a4_add_dt_devices();
+        r8a73a4_register_cmt(1);
        r8a73a4_register_scif(0);
        r8a73a4_register_scif(1);
        r8a73a4_register_scif(2);
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 8894e1b7ab0e..79ad93dfdae4 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -12,10 +12,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
@@ -71,6 +67,7 @@ static struct map_desc r8a7740_io_desc[] __initdata = {
 void __init r8a7740_map_io(void)
 {
+        debug_ll_io_init();
        iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
 }
@@ -746,6 +743,12 @@ static void r8a7740_i2c_workaround(struct platform_device *pdev)
 void __init r8a7740_add_standard_devices(void)
 {
        static struct pm_domain_device domain_devices[] __initdata = {
+                { "A4R",  &tmu0_device },
+                { "A4R",  &i2c0_device },
+                { "A4S",  &irqpin0_device },
+                { "A4S",  &irqpin1_device },
+                { "A4S",  &irqpin2_device },
+                { "A4S",  &irqpin3_device },
                { "A3SP", &scif0_device },
                { "A3SP", &scif1_device },
                { "A3SP", &scif2_device },
@@ -756,6 +759,11 @@ void __init r8a7740_add_standard_devices(void)
                { "A3SP", &scif7_device },
                { "A3SP", &scif8_device },
                { "A3SP", &i2c1_device },
+                { "A3SP", &ipmmu_device },
+                { "A3SP", &dma0_device },
+                { "A3SP", &dma1_device },
+                { "A3SP", &dma2_device },
+                { "A3SP", &usb_dma_device },
        };
        /* I2C work-around */
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 85fe016d6a87..170bd146ba17 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -13,10 +13,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/kernel.h>
@@ -292,8 +288,6 @@ void __init r8a7778_add_dt_devices(void)
                l2x0_init(base, 0x00400000, 0xc20f0fff);
        }
 #endif
-        r8a7778_register_tmu(0);
 }
 /* HPB-DMA */
@@ -501,6 +495,7 @@ static void __init r8a7778_register_hpb_dmae(void)
 void __init r8a7778_add_standard_devices(void)
 {
        r8a7778_add_dt_devices();
+        r8a7778_register_tmu(0);
        r8a7778_register_scif(0);
        r8a7778_register_scif(1);
        r8a7778_register_scif(2);
@@ -572,11 +567,6 @@ void __init r8a7778_init_irq_extpin(int irlm)
                        &irqpin_platform_data, sizeof(irqpin_platform_data));
 }
-void __init r8a7778_init_delay(void)
-{
-        shmobile_init_delay();
-}
 #ifdef CONFIG_USE_OF
 #define INT2SMSKCR0     0x82288 /* 0xfe782288 */
 #define INT2SMSKCR1     0x8228c /* 0xfe78228c */
@@ -608,7 +598,7 @@ static const char *r8a7778_compat_dt[] __initdata = {
 };
 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
-        .init_early     = r8a7778_init_delay,
+        .init_early     = shmobile_init_delay,
        .init_irq       = r8a7778_init_irq_dt,
        .init_late      = shmobile_init_late,
        .dt_compat      = r8a7778_compat_dt,
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 136078ab9407..6156d172cf31 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -13,10 +13,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -52,14 +48,14 @@
 #include "r8a7779.h"
 static struct map_desc r8a7779_io_desc[] __initdata = {
-        /* 2M entity map for 0xf0000000 (MPCORE) */
+        /* 2M identity mapping for 0xf0000000 (MPCORE) */
        {
                .virtual        = 0xf0000000,
                .pfn            = __phys_to_pfn(0xf0000000),
                .length         = SZ_2M,
                .type           = MT_DEVICE_NONSHARED
        },
-        /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
+        /* 16M identity mapping for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
        {
                .virtual        = 0xfe000000,
                .pfn            = __phys_to_pfn(0xfe000000),
@@ -70,6 +66,7 @@ static struct map_desc r8a7779_io_desc[] __initdata = {
 void __init r8a7779_map_io(void)
 {
+        debug_ll_io_init();
        iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
 }
@@ -683,7 +680,7 @@ void __init r8a7779_add_early_devices(void)
        /* Early serial console setup is not included here due to
         * memory map collisions. The SCIF serial ports in r8a7779
-         * are difficult to entity map 1:1 due to collision with the
+         * are difficult to identity map 1:1 due to collision with the
         * virtual memory range used by the coherent DMA code on ARM.
         *
         * Anyone wanting to debug early can remove UPF_IOREMAP from
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 877fdeb985d0..ec7d97dca4de 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -12,10 +12,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/irq.h>
diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c
index 35d78639244f..ef8eb3af586d 100644
--- a/arch/arm/mach-shmobile/setup-r8a7791.c
+++ b/arch/arm/mach-shmobile/setup-r8a7791.c
@@ -13,198 +13,16 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
-#include <linux/irq.h>
+#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/of_platform.h>
-#include <linux/platform_data/gpio-rcar.h>
-#include <linux/platform_data/irq-renesas-irqc.h>
-#include <linux/serial_sci.h>
-#include <linux/sh_timer.h>
 #include <asm/mach/arch.h>
 #include "common.h"
-#include "irqs.h"
 #include "r8a7791.h"
 #include "rcar-gen2.h"
-static const struct resource pfc_resources[] __initconst = {
-        DEFINE_RES_MEM(0xe6060000, 0x250),
-};
-#define r8a7791_register_pfc()                                          \
-        platform_device_register_simple("pfc-r8a7791", -1, pfc_resources, \
-                                        ARRAY_SIZE(pfc_resources))
-#define R8A7791_GPIO(idx, base, nr)                                     \
-static const struct resource r8a7791_gpio##idx##_resources[] __initconst = { \
-        DEFINE_RES_MEM((base), 0x50),                                   \
-        DEFINE_RES_IRQ(gic_spi(4 + (idx))),                             \
-};                                                                      \
-                                                                        \
-static const struct gpio_rcar_config                                    \
-r8a7791_gpio##idx##_platform_data __initconst = {                       \
-        .gpio_base      = 32 * (idx),                                   \
-        .irq_base       = 0,                                            \
-        .number_of_pins = (nr),                                         \
-        .pctl_name      = "pfc-r8a7791",                                \
-        .has_both_edge_trigger = 1,                                     \
-};                                                                      \
-R8A7791_GPIO(0, 0xe6050000, 32);
-R8A7791_GPIO(1, 0xe6051000, 32);
-R8A7791_GPIO(2, 0xe6052000, 32);
-R8A7791_GPIO(3, 0xe6053000, 32);
-R8A7791_GPIO(4, 0xe6054000, 32);
-R8A7791_GPIO(5, 0xe6055000, 32);
-R8A7791_GPIO(6, 0xe6055400, 32);
-R8A7791_GPIO(7, 0xe6055800, 26);
-#define r8a7791_register_gpio(idx)                                      \
-        platform_device_register_resndata(NULL, "gpio_rcar", idx,       \
-                r8a7791_gpio##idx##_resources,                          \
-                ARRAY_SIZE(r8a7791_gpio##idx##_resources),              \
-                &r8a7791_gpio##idx##_platform_data,                     \
-                sizeof(r8a7791_gpio##idx##_platform_data))
-void __init r8a7791_pinmux_init(void)
-{
-        r8a7791_register_pfc();
-        r8a7791_register_gpio(0);
-        r8a7791_register_gpio(1);
-        r8a7791_register_gpio(2);
-        r8a7791_register_gpio(3);
-        r8a7791_register_gpio(4);
-        r8a7791_register_gpio(5);
-        r8a7791_register_gpio(6);
-        r8a7791_register_gpio(7);
-}
-#define __R8A7791_SCIF(scif_type, index, baseaddr, irq)                 \
-static struct plat_sci_port scif##index##_platform_data = {             \
-        .type           = scif_type,                                    \
-        .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,              \
-        .scscr          = SCSCR_RE | SCSCR_TE,                          \
-};                                                                      \
-                                                                        \
-static struct resource scif##index##_resources[] = {                    \
-        DEFINE_RES_MEM(baseaddr, 0x100),                                \
-        DEFINE_RES_IRQ(irq),                                            \
-}
-#define R8A7791_SCIF(index, baseaddr, irq)                              \
-        __R8A7791_SCIF(PORT_SCIF, index, baseaddr, irq)
-#define R8A7791_SCIFA(index, baseaddr, irq)                             \
-        __R8A7791_SCIF(PORT_SCIFA, index, baseaddr, irq)
-#define R8A7791_SCIFB(index, baseaddr, irq)                             \
-        __R8A7791_SCIF(PORT_SCIFB, index, baseaddr, irq)
-R8A7791_SCIFA(0,  0xe6c40000, gic_spi(144)); /* SCIFA0 */
-R8A7791_SCIFA(1,  0xe6c50000, gic_spi(145)); /* SCIFA1 */
-R8A7791_SCIFB(2,  0xe6c20000, gic_spi(148)); /* SCIFB0 */
-R8A7791_SCIFB(3,  0xe6c30000, gic_spi(149)); /* SCIFB1 */
-R8A7791_SCIFB(4,  0xe6ce0000, gic_spi(150)); /* SCIFB2 */
-R8A7791_SCIFA(5,  0xe6c60000, gic_spi(151)); /* SCIFA2 */
-R8A7791_SCIF(6,   0xe6e60000, gic_spi(152)); /* SCIF0 */
-R8A7791_SCIF(7,   0xe6e68000, gic_spi(153)); /* SCIF1 */
-R8A7791_SCIF(8,   0xe6e58000, gic_spi(22)); /* SCIF2 */
-R8A7791_SCIF(9,   0xe6ea8000, gic_spi(23)); /* SCIF3 */
-R8A7791_SCIF(10,  0xe6ee0000, gic_spi(24)); /* SCIF4 */
-R8A7791_SCIF(11,  0xe6ee8000, gic_spi(25)); /* SCIF5 */
-R8A7791_SCIFA(12, 0xe6c70000, gic_spi(29)); /* SCIFA3 */
-R8A7791_SCIFA(13, 0xe6c78000, gic_spi(30)); /* SCIFA4 */
-R8A7791_SCIFA(14, 0xe6c80000, gic_spi(31)); /* SCIFA5 */
-#define r8a7791_register_scif(index)                                           \
-        platform_device_register_resndata(NULL, "sh-sci", index,               \
-                                          scif##index##_resources,             \
-                                          ARRAY_SIZE(scif##index##_resources), \
-                                          &scif##index##_platform_data,        \
-                                          sizeof(scif##index##_platform_data))
-static struct sh_timer_config cmt0_platform_data = {
-        .channels_mask = 0x60,
-};
-static struct resource cmt0_resources[] = {
-        DEFINE_RES_MEM(0xffca0000, 0x1004),
-        DEFINE_RES_IRQ(gic_spi(142)),
-};
-#define r8a7791_register_cmt(idx)                                       \
-        platform_device_register_resndata(NULL, "sh-cmt-48-gen2",       \
-                                          idx, cmt##idx##_resources,    \
-                                          ARRAY_SIZE(cmt##idx##_resources), \
-                                          &cmt##idx##_platform_data,    \
-                                          sizeof(struct sh_timer_config))
-static struct renesas_irqc_config irqc0_data = {
-        .irq_base = irq_pin(0), /* IRQ0 -> IRQ9 */
-};
-static struct resource irqc0_resources[] = {
-        DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
-        DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
-        DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
-        DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
-        DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
-        DEFINE_RES_IRQ(gic_spi(12)), /* IRQ4 */
-        DEFINE_RES_IRQ(gic_spi(13)), /* IRQ5 */
-        DEFINE_RES_IRQ(gic_spi(14)), /* IRQ6 */
-        DEFINE_RES_IRQ(gic_spi(15)), /* IRQ7 */
-        DEFINE_RES_IRQ(gic_spi(16)), /* IRQ8 */
-        DEFINE_RES_IRQ(gic_spi(17)), /* IRQ9 */
-};
-#define r8a7791_register_irqc(idx)                                      \
-        platform_device_register_resndata(NULL, "renesas_irqc",         \
-                                          idx, irqc##idx##_resources,   \
-                                          ARRAY_SIZE(irqc##idx##_resources), \
-                                          &irqc##idx##_data,            \
-                                          sizeof(struct renesas_irqc_config))
-static const struct resource thermal_resources[] __initconst = {
-        DEFINE_RES_MEM(0xe61f0000, 0x14),
-        DEFINE_RES_MEM(0xe61f0100, 0x38),
-        DEFINE_RES_IRQ(gic_spi(69)),
-};
-#define r8a7791_register_thermal()                                      \
-        platform_device_register_simple("rcar_thermal", -1,             \
-                                        thermal_resources,              \
-                                        ARRAY_SIZE(thermal_resources))
-void __init r8a7791_add_standard_devices(void)
-{
-        r8a7791_register_scif(0);
-        r8a7791_register_scif(1);
-        r8a7791_register_scif(2);
-        r8a7791_register_scif(3);
-        r8a7791_register_scif(4);
-        r8a7791_register_scif(5);
-        r8a7791_register_scif(6);
-        r8a7791_register_scif(7);
-        r8a7791_register_scif(8);
-        r8a7791_register_scif(9);
-        r8a7791_register_scif(10);
-        r8a7791_register_scif(11);
-        r8a7791_register_scif(12);
-        r8a7791_register_scif(13);
-        r8a7791_register_scif(14);
-        r8a7791_register_cmt(0);
-        r8a7791_register_irqc(0);
-        r8a7791_register_thermal();
-}
-#ifdef CONFIG_USE_OF
 static const char *r8a7791_boards_compat_dt[] __initdata = {
        "renesas,r8a7791",
        NULL,
@@ -218,4 +36,3 @@ DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)")
        .reserve        = rcar_gen2_reserve,
        .dt_compat      = r8a7791_boards_compat_dt,
 MACHINE_END
-#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 42d5b4308923..3dd6edd9bd1d 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -3,6 +3,7 @@
 *
 * Copyright (C) 2013  Renesas Solutions Corp.
 * Copyright (C) 2013  Magnus Damm
+ * Copyright (C) 2014  Ulrich Hecht
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -12,10 +13,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/clk/shmobile.h>
@@ -24,6 +21,7 @@
 #include <linux/dma-contiguous.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/of.h>
 #include <linux/of_fdt.h>
 #include <asm/mach/arch.h>
 #include "common.h"
@@ -54,37 +52,61 @@ void __init rcar_gen2_timer_init(void)
 {
 #if defined(CONFIG_ARM_ARCH_TIMER) || defined(CONFIG_COMMON_CLK)
        u32 mode = rcar_gen2_read_mode_pins();
+        bool is_e2 = (bool)of_find_compatible_node(NULL, NULL,
+                "renesas,r8a7794");
 #endif
 #ifdef CONFIG_ARM_ARCH_TIMER
        void __iomem *base;
        int extal_mhz = 0;
        u32 freq;
-        /* At Linux boot time the r8a7790 arch timer comes up
+        if (is_e2) {
-         * with the counter disabled. Moreover, it may also report
+                freq = 260000000 / 8;   /* ZS / 8 */
-         * a potentially incorrect fixed 13 MHz frequency. To be
+                /* CNTVOFF has to be initialized either from non-secure
-         * correct these registers need to be updated to use the
+                 * Hypervisor mode or secure Monitor mode with SCR.NS==1.
-         * frequency EXTAL / 2 which can be determined by the MD pins.
+                 * If TrustZone is enabled then it should be handled by the
-         */
+                 * secure code.
+                 */
-        switch (mode & (MD(14) | MD(13))) {
+                asm volatile(
-        case 0:
+                "       cps     0x16\n"
-                extal_mhz = 15;
+                "       mrc     p15, 0, r1, c1, c1, 0\n"
-                break;
+                "       orr     r0, r1, #1\n"
-        case MD(13):
+                "       mcr     p15, 0, r0, c1, c1, 0\n"
-                extal_mhz = 20;
+                "       isb\n"
-                break;
+                "       mov     r0, #0\n"
-        case MD(14):
+                "       mcrr    p15, 4, r0, r0, c14\n"
-                extal_mhz = 26;
+                "       isb\n"
-                break;
+                "       mcr     p15, 0, r1, c1, c1, 0\n"
-        case MD(13) | MD(14):
+                "       isb\n"
-                extal_mhz = 30;
+                "       cps     0x13\n"
-                break;
+                        : : : "r0", "r1");
+        } else {
+                /* At Linux boot time the r8a7790 arch timer comes up
+                 * with the counter disabled. Moreover, it may also report
+                 * a potentially incorrect fixed 13 MHz frequency. To be
+                 * correct these registers need to be updated to use the
+                 * frequency EXTAL / 2 which can be determined by the MD pins.
+                 */
+                switch (mode & (MD(14) | MD(13))) {
+                case 0:
+                        extal_mhz = 15;
+                        break;
+                case MD(13):
+                        extal_mhz = 20;
+                        break;
+                case MD(14):
+                        extal_mhz = 26;
+                        break;
+                case MD(13) | MD(14):
+                        extal_mhz = 30;
+                        break;
+                }
+                /* The arch timer frequency equals EXTAL / 2 */
+                freq = extal_mhz * (1000000 / 2);
        }
-        /* The arch timer frequency equals EXTAL / 2 */
-        freq = extal_mhz * (1000000 / 2);
        /* Remap "armgcnt address map" space */
        base = ioremap(0xe6080000, PAGE_SIZE);
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index d646c8d12423..458a2cfad417 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -12,10 +12,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -47,7 +43,7 @@
 #include "sh7372.h"
 static struct map_desc sh7372_io_desc[] __initdata = {
-        /* create a 1:1 entity map for 0xe6xxxxxx
+        /* create a 1:1 identity mapping for 0xe6xxxxxx
         * used by CPGA, INTC and PFC.
         */
        {
@@ -60,6 +56,7 @@ static struct map_desc sh7372_io_desc[] __initdata = {
 void __init sh7372_map_io(void)
 {
+        debug_ll_io_init();
        iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
 }
@@ -1012,6 +1009,7 @@ DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
        .init_irq       = sh7372_init_irq,
        .handle_irq     = shmobile_handle_irq_intc,
        .init_machine   = sh7372_add_standard_devices_dt,
+        .init_late      = shmobile_init_late,
        .dt_compat      = sh7372_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 328657d011d5..93ebe3430bfe 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -13,10 +13,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -46,7 +42,7 @@
 #include "sh73a0.h"
 static struct map_desc sh73a0_io_desc[] __initdata = {
-        /* create a 1:1 entity map for 0xe6xxxxxx
+        /* create a 1:1 identity mapping for 0xe6xxxxxx
         * used by CPGA, INTC and PFC.
         */
        {
@@ -59,6 +55,7 @@ static struct map_desc sh73a0_io_desc[] __initdata = {
 void __init sh73a0_map_io(void)
 {
+        debug_ll_io_init();
        iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
 }
@@ -760,17 +757,12 @@ void __init sh73a0_add_standard_devices(void)
                            ARRAY_SIZE(sh73a0_late_devices));
 }
-void __init sh73a0_init_delay(void)
-{
-        shmobile_init_delay();
-}
 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 void __init __weak sh73a0_register_twd(void) { }
 void __init sh73a0_earlytimer_init(void)
 {
-        sh73a0_init_delay();
+        shmobile_init_delay();
        sh73a0_clock_init();
        shmobile_earlytimer_init();
        sh73a0_register_twd();
@@ -795,6 +787,13 @@ void __init sh73a0_add_standard_devices_dt(void)
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
+#define RESCNT2 IOMEM(0xe6188020)
+static void sh73a0_restart(enum reboot_mode mode, const char *cmd)
+{
+        /* Do soft power on reset */
+        writel((1 << 31), RESCNT2);
+}
 static const char *sh73a0_boards_compat_dt[] __initdata = {
        "renesas,sh73a0",
        NULL,
@@ -803,9 +802,10 @@ static const char *sh73a0_boards_compat_dt[] __initdata = {
 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
        .smp            = smp_ops(sh73a0_smp_ops),
        .map_io         = sh73a0_map_io,
-        .init_early     = sh73a0_init_delay,
+        .init_early     = shmobile_init_delay,
        .init_machine   = sh73a0_add_standard_devices_dt,
        .init_late      = shmobile_init_late,
+        .restart        = sh73a0_restart,
        .dt_compat      = sh73a0_boards_compat_dt,
 MACHINE_END
 #endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/sh73a0.h b/arch/arm/mach-shmobile/sh73a0.h
index 359b582dc270..f037c64b14fc 100644
--- a/arch/arm/mach-shmobile/sh73a0.h
+++ b/arch/arm/mach-shmobile/sh73a0.h
@@ -71,7 +71,6 @@ enum {
 #define SH73A0_PINT0_IRQ(irq) ((irq) + 700)
 #define SH73A0_PINT1_IRQ(irq) ((irq) + 732)
-extern void sh73a0_init_delay(void);
 extern void sh73a0_init_irq(void);
 extern void sh73a0_init_irq_dt(void);
 extern void sh73a0_map_io(void);
diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S
index 9782862899e8..146b8de16432 100644
--- a/arch/arm/mach-shmobile/sleep-sh7372.S
+++ b/arch/arm/mach-shmobile/sleep-sh7372.S
@@ -22,11 +22,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
 */
 #include <linux/linkage.h>
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index 6ff1df1df9a7..baff3b5efed8 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -12,10 +12,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/kernel.h>
 #include <linux/init.h>
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 3100e355c3fd..3f761f839043 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -12,10 +12,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/kernel.h>
 #include <linux/init.h>
diff --git a/arch/arm/mach-shmobile/smp-r8a7790.c b/arch/arm/mach-shmobile/smp-r8a7790.c
index 2311694636e1..9c3da1345b8b 100644
--- a/arch/arm/mach-shmobile/smp-r8a7790.c
+++ b/arch/arm/mach-shmobile/smp-r8a7790.c
@@ -21,6 +21,7 @@
 #include <asm/smp_plat.h>
 #include "common.h"
+#include "platsmp-apmu.h"
 #include "pm-rcar.h"
 #include "r8a7790.h"
@@ -34,10 +35,23 @@ static struct rcar_sysc_ch r8a7790_ca7_scu = {
        .isr_bit = 21, /* CA7-SCU */
 };
+static struct rcar_apmu_config r8a7790_apmu_config[] = {
+        {
+                .iomem = DEFINE_RES_MEM(0xe6152000, 0x88),
+                .cpus = { 0, 1, 2, 3 },
+        },
+        {
+                .iomem = DEFINE_RES_MEM(0xe6151000, 0x88),
+                .cpus = { 0x100, 0x0101, 0x102, 0x103 },
+        }
+};
 static void __init r8a7790_smp_prepare_cpus(unsigned int max_cpus)
 {
        /* let APMU code install data related to shmobile_boot_vector */
-        shmobile_smp_apmu_prepare_cpus(max_cpus);
+        shmobile_smp_apmu_prepare_cpus(max_cpus,
+                                       r8a7790_apmu_config,
+                                       ARRAY_SIZE(r8a7790_apmu_config));
        /* turn on power to SCU */
        r8a7790_pm_init();
diff --git a/arch/arm/mach-shmobile/smp-r8a7791.c b/arch/arm/mach-shmobile/smp-r8a7791.c
index f743386166fb..7e49e0a52e32 100644
--- a/arch/arm/mach-shmobile/smp-r8a7791.c
+++ b/arch/arm/mach-shmobile/smp-r8a7791.c
@@ -21,13 +21,23 @@
 #include <asm/smp_plat.h>
 #include "common.h"
+#include "platsmp-apmu.h"
 #include "r8a7791.h"
 #include "rcar-gen2.h"
+static struct rcar_apmu_config r8a7791_apmu_config[] = {
+        {
+                .iomem = DEFINE_RES_MEM(0xe6152000, 0x88),
+                .cpus = { 0, 1 },
+        }
+};
 static void __init r8a7791_smp_prepare_cpus(unsigned int max_cpus)
 {
        /* let APMU code install data related to shmobile_boot_vector */
-        shmobile_smp_apmu_prepare_cpus(max_cpus);
+        shmobile_smp_apmu_prepare_cpus(max_cpus,
+                                       r8a7791_apmu_config,
+                                       ARRAY_SIZE(r8a7791_apmu_config));
        r8a7791_pm_init();
 }
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 22d8f87b23e9..c16dbfe9836c 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -12,10 +12,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/kernel.h>
 #include <linux/init.h>
diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c
index 87c6be1e79bd..f1d027aa7a81 100644
--- a/arch/arm/mach-shmobile/timer.c
+++ b/arch/arm/mach-shmobile/timer.c
@@ -12,11 +12,6 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
 */
 #include <linux/platform_device.h>
 #include <linux/clocksource.h>
@@ -45,6 +40,7 @@ void __init shmobile_init_delay(void)
        struct device_node *np, *cpus;
        bool is_a7_a8_a9 = false;
        bool is_a15 = false;
+        bool has_arch_timer = false;
        u32 max_freq = 0;
        cpus = of_find_node_by_path("/cpus");
@@ -57,12 +53,16 @@ void __init shmobile_init_delay(void)
                if (!of_property_read_u32(np, "clock-frequency", &freq))
                        max_freq = max(max_freq, freq);
-                if (of_device_is_compatible(np, "arm,cortex-a7") ||
+                if (of_device_is_compatible(np, "arm,cortex-a8") ||
-                    of_device_is_compatible(np, "arm,cortex-a8") ||
+                    of_device_is_compatible(np, "arm,cortex-a9")) {
-                    of_device_is_compatible(np, "arm,cortex-a9"))
                        is_a7_a8_a9 = true;
-                else if (of_device_is_compatible(np, "arm,cortex-a15"))
+                } else if (of_device_is_compatible(np, "arm,cortex-a7")) {
+                        is_a7_a8_a9 = true;
+                        has_arch_timer = true;
+                } else if (of_device_is_compatible(np, "arm,cortex-a15")) {
                        is_a15 = true;
+                        has_arch_timer = true;
+                }
        }
        of_node_put(cpus);
@@ -70,10 +70,12 @@ void __init shmobile_init_delay(void)
        if (!max_freq)
                return;
-        if (is_a7_a8_a9)
+        if (!has_arch_timer || !IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) {
-                shmobile_setup_delay_hz(max_freq, 1, 3);
+                if (is_a7_a8_a9)
-        else if (is_a15 && !IS_ENABLED(CONFIG_ARM_ARCH_TIMER))
+                        shmobile_setup_delay_hz(max_freq, 1, 3);
-                shmobile_setup_delay_hz(max_freq, 2, 4);
+                else if (is_a15)
+                        shmobile_setup_delay_hz(max_freq, 2, 4);
+        }
 }
 static void __init shmobile_late_time_init(void)
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 60c443dadb58..483cb467bf65 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -21,6 +21,7 @@
 #define __MACH_CORE_H
 #define SOCFPGA_RSTMGR_CTRL     0x04
+#define SOCFPGA_RSTMGR_MODMPURST        0x10
 #define SOCFPGA_RSTMGR_MODPERRST        0x14
 #define SOCFPGA_RSTMGR_BRGMODRST        0x1c
@@ -28,6 +29,8 @@
 #define RSTMGR_CTRL_SWCOLDRSTREQ        0x1     /* Cold Reset */
 #define RSTMGR_CTRL_SWWARMRSTREQ        0x2     /* Warm Reset */
+#define RSTMGR_MPUMODRST_CPU1           0x2     /* CPU1 Reset */
 extern void socfpga_secondary_startup(void);
 extern void __iomem *socfpga_scu_base_addr;
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index 16ca97b039f9..c64d89b7c0ca 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -34,17 +34,21 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
        int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
        if (socfpga_cpu1start_addr) {
+                /* This will put CPU #1 into reset. */
+                writel(RSTMGR_MPUMODRST_CPU1,
+                       rst_manager_base_addr + SOCFPGA_RSTMGR_MODMPURST);
                memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
-                __raw_writel(virt_to_phys(socfpga_secondary_startup),
+                writel(virt_to_phys(socfpga_secondary_startup),
-                        (sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff)));
+                       sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff));
                flush_cache_all();
                smp_wmb();
                outer_clean_range(0, trampoline_size);
-                /* This will release CPU #1 out of reset.*/
+                /* This will release CPU #1 out of reset. */
-                __raw_writel(0, rst_manager_base_addr + 0x10);
+                writel(0, rst_manager_base_addr + SOCFPGA_RSTMGR_MODMPURST);
        }
        return 0;
@@ -86,10 +90,9 @@ static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus)
 */
 static void socfpga_cpu_die(unsigned int cpu)
 {
-        cpu_do_idle();
+        /* Do WFI. If we wake up early, go back into WFI */
+        while (1)
-        /* We should have never returned from idle */
+                cpu_do_idle();
-        panic("cpu %d unexpectedly exit from shutdown\n", cpu);
 }
 struct smp_operations socfpga_smp_ops __initdata = {
diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
index 878e9ec97d0f..8825bc9e2553 100644
--- a/arch/arm/mach-sti/Kconfig
+++ b/arch/arm/mach-sti/Kconfig
@@ -42,4 +42,14 @@ config SOC_STIH416
          and other digital audio/video applications using Flattened Device
          Trees.
+config SOC_STIH407
+        bool "STiH407 STMicroelectronics Consumer Electronics family"
+        default y
+        select STIH407_RESET
+        help
+          This enables support for STMicroelectronics Digital Consumer
+          Electronics family StiH407 parts, targetted at set-top-box
+          and other digital audio/video applications using Flattened Device
+          Trees.
 endif
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 1aaa1e15ef70..a77604fbaf25 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -42,4 +42,11 @@ config MACH_SUN8I
        select MFD_SUN6I_PRCM
        select RESET_CONTROLLER
+config MACH_SUN9I
+        bool "Allwinner (sun9i) SoCs support"
+        default ARCH_SUNXI
+        select ARCH_HAS_RESET_CONTROLLER
+        select ARM_GIC
+        select RESET_CONTROLLER
 endif
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
index c53077bb8c3f..e44d028555a4 100644
--- a/arch/arm/mach-sunxi/platsmp.c
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -116,7 +116,7 @@ static int sun6i_smp_boot_secondary(unsigned int cpu,
        return 0;
 }
-struct smp_operations sun6i_smp_ops __initdata = {
+static struct smp_operations sun6i_smp_ops __initdata = {
        .smp_prepare_cpus       = sun6i_smp_prepare_cpus,
        .smp_boot_secondary     = sun6i_smp_boot_secondary,
 };
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index d7598aeed803..1f986758784a 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -63,3 +63,12 @@ static const char * const sun8i_board_dt_compat[] = {
 DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i (A23) Family")
        .dt_compat      = sun8i_board_dt_compat,
 MACHINE_END
+static const char * const sun9i_board_dt_compat[] = {
+        "allwinner,sun9i-a80",
+        NULL,
+};
+DT_MACHINE_START(SUN9I_DT, "Allwinner sun9i Family")
+        .dt_compat      = sun9i_board_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 095399618ca5..d0be9a1ef6b8 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -2,6 +2,7 @@ menuconfig ARCH_TEGRA
        bool "NVIDIA Tegra" if ARCH_MULTI_V7
        select ARCH_REQUIRE_GPIOLIB
        select ARCH_SUPPORTS_TRUSTED_FOUNDATIONS
+        select ARM_AMBA
        select ARM_GIC
        select CLKSRC_MMIO
        select HAVE_ARM_SCU if SMP
@@ -59,12 +60,4 @@ config ARCH_TEGRA_124_SOC
          Support for NVIDIA Tegra T124 processor family, based on the
          ARM CortexA15MP CPU
-config TEGRA_AHB
-        bool "Enable AHB driver for NVIDIA Tegra SoCs"
-        default y
-        help
-          Adds AHB configuration functionality for NVIDIA Tegra SoCs,
-          which controls AHB bus master arbitration and some
-          performance parameters(priority, prefech size).
 endif
diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
index e3ebdce3e71f..f2b586d7b15d 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra114.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra114.c
@@ -49,7 +49,7 @@ static int tegra114_idle_power_down(struct cpuidle_device *dev,
        call_firmware_op(prepare_idle);
        /* Do suspend by ourselves if the firmware does not implement it */
-        if (call_firmware_op(do_idle) == -ENOSYS)
+        if (call_firmware_op(do_idle, 0) == -ENOSYS)
                cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
@@ -75,7 +75,6 @@ static struct cpuidle_driver tegra_idle_driver = {
                        .exit_latency           = 500,
                        .target_residency       = 1000,
                        .power_usage            = 0,
-                        .flags                  = CPUIDLE_FLAG_TIME_VALID,
                        .name                   = "powered-down",
                        .desc                   = "CPU power gated",
                },
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index b30bf5cba65b..4f25a7c7ca0f 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -59,8 +59,7 @@ static struct cpuidle_driver tegra_idle_driver = {
                        .exit_latency     = 5000,
                        .target_residency = 10000,
                        .power_usage      = 0,
-                        .flags            = CPUIDLE_FLAG_TIME_VALID |
+                        .flags            = CPUIDLE_FLAG_COUPLED,
-                        CPUIDLE_FLAG_COUPLED,
                        .name             = "powered-down",
                        .desc             = "CPU power gated",
                },
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index 35561274f6cf..f8815ed65d9d 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -56,7 +56,6 @@ static struct cpuidle_driver tegra_idle_driver = {
                        .exit_latency           = 2000,
                        .target_residency       = 2200,
                        .power_usage            = 0,
-                        .flags                  = CPUIDLE_FLAG_TIME_VALID,
                        .name                   = "powered-down",
                        .desc                   = "CPU power gated",
                },
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 7b2baab0f0bd..71be4af5e975 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -51,6 +51,7 @@ ENTRY(tegra_resume)
 THUMB( it      ne )
        bne     cpu_resume                      @ no
+        tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
        /* Are we on Tegra20? */
        cmp     r6, #TEGRA20
        beq     1f                              @ Yes
diff --git a/arch/arm/mach-u300/dummyspichip.c b/arch/arm/mach-u300/dummyspichip.c
index ec0283cf9a32..131996805690 100644
--- a/arch/arm/mach-u300/dummyspichip.c
+++ b/arch/arm/mach-u300/dummyspichip.c
@@ -80,8 +80,8 @@ static ssize_t dummy_looptest(struct device *dev,
                "in 8bit mode\n");
        status = spi_w8r8(spi, 0xAA);
        if (status < 0)
-                pr_warning("Siple test 1: FAILURE: spi_write_then_read "
+                pr_warn("Simple test 1: FAILURE: spi_write_then_read failed with status %d\n",
-                           "failed with status %d\n", status);
+                        status);
        else
                pr_info("Simple test 1: SUCCESS!\n");
@@ -89,8 +89,8 @@ static ssize_t dummy_looptest(struct device *dev,
                "in 8bit mode (full FIFO)\n");
        status = spi_write_then_read(spi, &txbuf[0], 8, &rxbuf[0], 8);
        if (status < 0)
-                pr_warning("Simple test 2: FAILURE: spi_write_then_read() "
+                pr_warn("Simple test 2: FAILURE: spi_write_then_read() failed with status %d\n",
-                           "failed with status %d\n", status);
+                        status);
        else
                pr_info("Simple test 2: SUCCESS!\n");
@@ -98,8 +98,8 @@ static ssize_t dummy_looptest(struct device *dev,
                "in 8bit mode (see if we overflow FIFO)\n");
        status = spi_write_then_read(spi, &txbuf[0], 14, &rxbuf[0], 14);
        if (status < 0)
-                pr_warning("Simple test 3: FAILURE: failed with status %d "
+                pr_warn("Simple test 3: FAILURE: failed with status %d (probably FIFO overrun)\n",
-                           "(probably FIFO overrun)\n", status);
+                        status);
        else
                pr_info("Simple test 3: SUCCESS!\n");
@@ -107,14 +107,14 @@ static ssize_t dummy_looptest(struct device *dev,
                "bytes garbage with spi_read() in 8bit mode\n");
        status = spi_write(spi, &txbuf[0], 8);
        if (status < 0)
-                pr_warning("Simple test 4 step 1: FAILURE: spi_write() "
+                pr_warn("Simple test 4 step 1: FAILURE: spi_write() failed with status %d\n",
-                           "failed with status %d\n", status);
+                        status);
        else
                pr_info("Simple test 4 step 1: SUCCESS!\n");
        status = spi_read(spi, &rxbuf[0], 8);
        if (status < 0)
-                pr_warning("Simple test 4 step 2: FAILURE: spi_read() "
+                pr_warn("Simple test 4 step 2: FAILURE: spi_read() failed with status %d\n",
-                           "failed with status %d\n", status);
+                        status);
        else
                pr_info("Simple test 4 step 2: SUCCESS!\n");
@@ -122,16 +122,14 @@ static ssize_t dummy_looptest(struct device *dev,
                "14 bytes garbage with spi_read() in 8bit mode\n");
        status = spi_write(spi, &txbuf[0], 14);
        if (status < 0)
-                pr_warning("Simple test 5 step 1: FAILURE: spi_write() "
+                pr_warn("Simple test 5 step 1: FAILURE: spi_write() failed with status %d (probably FIFO overrun)\n",
-                           "failed with status %d (probably FIFO overrun)\n",
+                        status);
-                           status);
        else
                pr_info("Simple test 5 step 1: SUCCESS!\n");
        status = spi_read(spi, &rxbuf[0], 14);
        if (status < 0)
-                pr_warning("Simple test 5 step 2: FAILURE: spi_read() "
+                pr_warn("Simple test 5 step 2: FAILURE: spi_read() failed with status %d (probably FIFO overrun)\n",
-                           "failed with status %d (probably FIFO overrun)\n",
+                        status);
-                           status);
        else
                pr_info("Simple test 5: SUCCESS!\n");
@@ -140,16 +138,14 @@ static ssize_t dummy_looptest(struct device *dev,
                DMA_TEST_SIZE, DMA_TEST_SIZE);
        status = spi_write(spi, &bigtxbuf_virtual[0], DMA_TEST_SIZE);
        if (status < 0)
-                pr_warning("Simple test 6 step 1: FAILURE: spi_write() "
+                pr_warn("Simple test 6 step 1: FAILURE: spi_write() failed with status %d (probably FIFO overrun)\n",
-                           "failed with status %d (probably FIFO overrun)\n",
+                        status);
-                           status);
        else
                pr_info("Simple test 6 step 1: SUCCESS!\n");
        status = spi_read(spi, &bigrxbuf_virtual[0], DMA_TEST_SIZE);
        if (status < 0)
-                pr_warning("Simple test 6 step 2: FAILURE: spi_read() "
+                pr_warn("Simple test 6 step 2: FAILURE: spi_read() failed with status %d (probably FIFO overrun)\n",
-                           "failed with status %d (probably FIFO overrun)\n",
+                        status);
-                           status);
        else
                pr_info("Simple test 6: SUCCESS!\n");
@@ -169,18 +165,17 @@ static ssize_t dummy_looptest(struct device *dev,
                pr_info("Simple test 7: SUCCESS! (expected failure with "
                        "status EIO)\n");
        else if (status < 0)
-                pr_warning("Siple test 7: FAILURE: spi_write_then_read "
+                pr_warn("Simple test 7: FAILURE: spi_write_then_read failed with status %d\n",
-                           "failed with status %d\n", status);
+                        status);
        else
-                pr_warning("Siple test 7: FAILURE: spi_write_then_read "
+                pr_warn("Simple test 7: FAILURE: spi_write_then_read succeeded but it was expected to fail!\n");
-                           "succeeded but it was expected to fail!\n");
        pr_info("Simple test 8: write 8 bytes, read back 8 bytes garbage "
                "in 16bit mode (full FIFO)\n");
        status = spi_write_then_read(spi, &txbuf[0], 8, &rxbuf[0], 8);
        if (status < 0)
-                pr_warning("Simple test 8: FAILURE: spi_write_then_read() "
+                pr_warn("Simple test 8: FAILURE: spi_write_then_read() failed with status %d\n",
-                           "failed with status %d\n", status);
+                        status);
        else
                pr_info("Simple test 8: SUCCESS!\n");
@@ -188,8 +183,8 @@ static ssize_t dummy_looptest(struct device *dev,
                "in 16bit mode (see if we overflow FIFO)\n");
        status = spi_write_then_read(spi, &txbuf[0], 14, &rxbuf[0], 14);
        if (status < 0)
-                pr_warning("Simple test 9: FAILURE: failed with status %d "
+                pr_warn("Simple test 9: FAILURE: failed with status %d (probably FIFO overrun)\n",
-                           "(probably FIFO overrun)\n", status);
+                        status);
        else
                pr_info("Simple test 9: SUCCESS!\n");
@@ -198,17 +193,15 @@ static ssize_t dummy_looptest(struct device *dev,
               DMA_TEST_SIZE, DMA_TEST_SIZE);
        status = spi_write(spi, &bigtxbuf_virtual[0], DMA_TEST_SIZE);
        if (status < 0)
-                pr_warning("Simple test 10 step 1: FAILURE: spi_write() "
+                pr_warn("Simple test 10 step 1: FAILURE: spi_write() failed with status %d (probably FIFO overrun)\n",
-                           "failed with status %d (probably FIFO overrun)\n",
+                        status);
-                           status);
        else
                pr_info("Simple test 10 step 1: SUCCESS!\n");
        status = spi_read(spi, &bigrxbuf_virtual[0], DMA_TEST_SIZE);
        if (status < 0)
-                pr_warning("Simple test 10 step 2: FAILURE: spi_read() "
+                pr_warn("Simple test 10 step 2: FAILURE: spi_read() failed with status %d (probably FIFO overrun)\n",
-                           "failed with status %d (probably FIFO overrun)\n",
+                        status);
-                           status);
        else
                pr_info("Simple test 10: SUCCESS!\n");
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 699e8601dbf0..c9ac19b24e5a 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -32,6 +32,7 @@ config UX500_SOC_DB8500
        select PINCTRL_AB8540
        select REGULATOR
        select REGULATOR_DB8500_PRCMU
+        select PM_GENERIC_DOMAINS if PM
 config MACH_MOP500
        bool "U8500 Development platform, MOP500 versions"
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 9741de956b3e..4418a5078833 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -9,5 +9,6 @@ obj-$(CONFIG_MACH_MOP500)	+= board-mop500-regulators.o \
                                board-mop500-audio.o
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
+obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
 CFLAGS_hotplug.o                += -march=armv7-a
diff --git a/arch/arm/mach-ux500/pm.c b/arch/arm/mach-ux500/pm.c
index b80a9a2e356e..2cb587b50905 100644
--- a/arch/arm/mach-ux500/pm.c
+++ b/arch/arm/mach-ux500/pm.c
@@ -17,6 +17,7 @@
 #include <linux/platform_data/arm-ux500-pm.h>
 #include "db8500-regs.h"
+#include "pm_domains.h"
 /* ARM WFI Standby signal register */
 #define PRCM_ARM_WFI_STANDBY    (prcmu_base + 0x130)
@@ -191,4 +192,7 @@ void __init ux500_pm_init(u32 phy_base, u32 size)
        /* Set up ux500 suspend callbacks. */
        suspend_set_ops(UX500_SUSPEND_OPS);
+        /* Initialize ux500 power domains */
+        ux500_pm_domains_init();
 }
diff --git a/arch/arm/mach-ux500/pm_domains.c b/arch/arm/mach-ux500/pm_domains.c
new file mode 100644
index 000000000000..0d4b5b46f15b
--- /dev/null
+++ b/arch/arm/mach-ux500/pm_domains.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2014 Linaro Ltd.
+ *
+ * Author: Ulf Hansson <ulf.hansson@linaro.org>
+ * License terms: GNU General Public License (GPL) version 2
+ *
+ * Implements PM domains using the generic PM domain for ux500.
+ */
+#include <linux/printk.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/pm_domain.h>
+#include <dt-bindings/arm/ux500_pm_domains.h>
+#include "pm_domains.h"
+static int pd_power_off(struct generic_pm_domain *domain)
+{
+        /*
+         * Handle the gating of the PM domain regulator here.
+         *
+         * Drivers/subsystems handling devices in the PM domain needs to perform
+         * register context save/restore from their respective runtime PM
+         * callbacks, to be able to enable PM domain gating/ungating.
+         */
+        return 0;
+}
+static int pd_power_on(struct generic_pm_domain *domain)
+{
+        /*
+         * Handle the ungating of the PM domain regulator here.
+         *
+         * Drivers/subsystems handling devices in the PM domain needs to perform
+         * register context save/restore from their respective runtime PM
+         * callbacks, to be able to enable PM domain gating/ungating.
+         */
+        return 0;
+}
+static struct generic_pm_domain ux500_pm_domain_vape = {
+        .name = "VAPE",
+        .power_off = pd_power_off,
+        .power_on = pd_power_on,
+};
+static struct generic_pm_domain *ux500_pm_domains[NR_DOMAINS] = {
+        [DOMAIN_VAPE] = &ux500_pm_domain_vape,
+};
+static struct of_device_id ux500_pm_domain_matches[] = {
+        { .compatible = "stericsson,ux500-pm-domains", },
+        { },
+};
+int __init ux500_pm_domains_init(void)
+{
+        struct device_node *np;
+        struct genpd_onecell_data *genpd_data;
+        int i;
+        np = of_find_matching_node(NULL, ux500_pm_domain_matches);
+        if (!np)
+                return -ENODEV;
+        genpd_data = kzalloc(sizeof(*genpd_data), GFP_KERNEL);
+        if (!genpd_data)
+                return -ENOMEM;
+        genpd_data->domains = ux500_pm_domains;
+        genpd_data->num_domains = ARRAY_SIZE(ux500_pm_domains);
+        for (i = 0; i < ARRAY_SIZE(ux500_pm_domains); ++i)
+                pm_genpd_init(ux500_pm_domains[i], NULL, false);
+        of_genpd_add_provider_onecell(np, genpd_data);
+        return 0;
+}
diff --git a/arch/arm/mach-ux500/pm_domains.h b/arch/arm/mach-ux500/pm_domains.h
new file mode 100644
index 000000000000..263d3ba97177
--- /dev/null
+++ b/arch/arm/mach-ux500/pm_domains.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2014 Linaro Ltd.
+ *
+ * Author: Ulf Hansson <ulf.hansson@linaro.org>
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#ifndef __MACH_UX500_PM_DOMAINS_H
+#define __MACH_UX500_PM_DOMAINS_H
+#ifdef CONFIG_PM_GENERIC_DOMAINS
+extern int __init ux500_pm_domains_init(void);
+#else
+static inline int ux500_pm_domains_init(void) { return 0; }
+#endif
+#endif
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index b2cfba16c4e8..d6b16d9a7838 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -16,6 +16,7 @@ menuconfig ARCH_VEXPRESS
        select POWER_RESET
        select POWER_RESET_VEXPRESS
        select POWER_SUPPLY
+        select REGULATOR if MMC_ARMMMCI
        select REGULATOR_FIXED_VOLTAGE if REGULATOR
        select VEXPRESS_CONFIG
        select VEXPRESS_SYSCFG
@@ -49,9 +50,6 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
          build a working kernel, you must also enable relevant core
          tile support or Flattened Device Tree based support options.
-config ARCH_VEXPRESS_CA9X4
-        bool "Versatile Express Cortex-A9x4 tile"
 config ARCH_VEXPRESS_DCSCB
        bool "Dual Cluster System Control Block (DCSCB) support"
        depends on MCPM
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index fc649bc09d0c..f5c1006dd6a1 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -1,11 +1,10 @@
 #
 # Makefile for the linux kernel.
 #
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := \
        -I$(srctree)/arch/arm/plat-versatile/include
 obj-y                                   := v2m.o
-obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)       += ct-ca9x4.o
 obj-$(CONFIG_ARCH_VEXPRESS_DCSCB)       += dcscb.o      dcscb_setup.o
 CFLAGS_dcscb.o                          += -march=armv7-a
 CFLAGS_REMOVE_dcscb.o                   = -pg
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index 152fad91b3ae..2a11d3ac8c68 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -1,12 +1,5 @@
-/* 2MB large area for motherboard's peripherals static mapping */
-#define V2M_PERIPH 0xf8000000
-/* Tile's peripherals static mappings should start here */
-#define V2T_PERIPH 0xf8200000
 bool vexpress_smp_init_ops(void);
-extern struct smp_operations    vexpress_smp_ops;
 extern struct smp_operations    vexpress_smp_dt_ops;
 extern void vexpress_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
deleted file mode 100644
index 27bea049380a..000000000000
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/*
- * Versatile Express Core Tile Cortex A9x4 Support
- */
-#include <linux/init.h>
-#include <linux/gfp.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/clcd.h>
-#include <linux/platform_data/video-clcd-versatile.h>
-#include <linux/clkdev.h>
-#include <linux/vexpress.h>
-#include <linux/irqchip/arm-gic.h>
-#include <asm/hardware/arm_timer.h>
-#include <asm/hardware/cache-l2x0.h>
-#include <asm/smp_scu.h>
-#include <asm/smp_twd.h>
-#include <mach/ct-ca9x4.h>
-#include <asm/hardware/timer-sp.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-#include "core.h"
-#include <mach/motherboard.h>
-#include <mach/irqs.h>
-static struct map_desc ct_ca9x4_io_desc[] __initdata = {
-        {
-                .virtual        = V2T_PERIPH,
-                .pfn            = __phys_to_pfn(CT_CA9X4_MPIC),
-                .length         = SZ_8K,
-                .type           = MT_DEVICE,
-        },
-};
-static void __init ct_ca9x4_map_io(void)
-{
-        iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
-}
-static void __init ca9x4_l2_init(void)
-{
-#ifdef CONFIG_CACHE_L2X0
-        void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
-        if (l2x0_base) {
-                /* set RAM latencies to 1 cycle for this core tile. */
-                writel(0, l2x0_base + L310_TAG_LATENCY_CTRL);
-                writel(0, l2x0_base + L310_DATA_LATENCY_CTRL);
-                l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
-        } else {
-                pr_err("L2C: unable to map L2 cache controller\n");
-        }
-#endif
-}
-#ifdef CONFIG_HAVE_ARM_TWD
-static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, A9_MPCORE_TWD, IRQ_LOCALTIMER);
-static void __init ca9x4_twd_init(void)
-{
-        int err = twd_local_timer_register(&twd_local_timer);
-        if (err)
-                pr_err("twd_local_timer_register failed %d\n", err);
-}
-#else
-#define ca9x4_twd_init()        do {} while(0)
-#endif
-static void __init ct_ca9x4_init_irq(void)
-{
-        gic_init(0, 29, ioremap(A9_MPCORE_GIC_DIST, SZ_4K),
-                 ioremap(A9_MPCORE_GIC_CPU, SZ_256));
-        ca9x4_twd_init();
-        ca9x4_l2_init();
-}
-static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
-{
-        unsigned long framesize = 1024 * 768 * 2;
-        fb->panel = versatile_clcd_get_panel("XVGA");
-        if (!fb->panel)
-                return -EINVAL;
-        return versatile_clcd_setup_dma(fb, framesize);
-}
-static struct clcd_board ct_ca9x4_clcd_data = {
-        .name           = "CT-CA9X4",
-        .caps           = CLCD_CAP_5551 | CLCD_CAP_565,
-        .check          = clcdfb_check,
-        .decode         = clcdfb_decode,
-        .setup          = ct_ca9x4_clcd_setup,
-        .mmap           = versatile_clcd_mmap_dma,
-        .remove         = versatile_clcd_remove_dma,
-};
-static AMBA_AHB_DEVICE(clcd, "ct:clcd", 0, CT_CA9X4_CLCDC, IRQ_CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
-static AMBA_APB_DEVICE(dmc, "ct:dmc", 0, CT_CA9X4_DMC, IRQ_CT_CA9X4_DMC, NULL);
-static AMBA_APB_DEVICE(smc, "ct:smc", 0, CT_CA9X4_SMC, IRQ_CT_CA9X4_SMC, NULL);
-static AMBA_APB_DEVICE(gpio, "ct:gpio", 0, CT_CA9X4_GPIO, IRQ_CT_CA9X4_GPIO, NULL);
-static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
-        &clcd_device,
-        &dmc_device,
-        &smc_device,
-        &gpio_device,
-};
-static struct resource pmu_resources[] = {
-        [0] = {
-                .start  = IRQ_CT_CA9X4_PMU_CPU0,
-                .end    = IRQ_CT_CA9X4_PMU_CPU0,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [1] = {
-                .start  = IRQ_CT_CA9X4_PMU_CPU1,
-                .end    = IRQ_CT_CA9X4_PMU_CPU1,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .start  = IRQ_CT_CA9X4_PMU_CPU2,
-                .end    = IRQ_CT_CA9X4_PMU_CPU2,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = IRQ_CT_CA9X4_PMU_CPU3,
-                .end    = IRQ_CT_CA9X4_PMU_CPU3,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device pmu_device = {
-        .name           = "arm-pmu",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(pmu_resources),
-        .resource       = pmu_resources,
-};
-static struct clk_lookup osc1_lookup = {
-        .dev_id         = "ct:clcd",
-};
-static struct platform_device osc1_device = {
-        .name           = "vexpress-osc",
-        .id             = 1,
-        .num_resources  = 1,
-        .resource       = (struct resource []) {
-                VEXPRESS_RES_FUNC(0xf, 1),
-        },
-        .dev.platform_data = &osc1_lookup,
-};
-static void __init ct_ca9x4_init(void)
-{
-        int i;
-        for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
-                amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
-        platform_device_register(&pmu_device);
-        vexpress_syscfg_device_register(&osc1_device);
-}
-#ifdef CONFIG_SMP
-static void *ct_ca9x4_scu_base __initdata;
-static void __init ct_ca9x4_init_cpu_map(void)
-{
-        int i, ncores;
-        ct_ca9x4_scu_base = ioremap(A9_MPCORE_SCU, SZ_128);
-        if (WARN_ON(!ct_ca9x4_scu_base))
-                return;
-        ncores = scu_get_core_count(ct_ca9x4_scu_base);
-        if (ncores > nr_cpu_ids) {
-                pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
-                        ncores, nr_cpu_ids);
-                ncores = nr_cpu_ids;
-        }
-        for (i = 0; i < ncores; ++i)
-                set_cpu_possible(i, true);
-}
-static void __init ct_ca9x4_smp_enable(unsigned int max_cpus)
-{
-        scu_enable(ct_ca9x4_scu_base);
-}
-#endif
-struct ct_desc ct_ca9x4_desc __initdata = {
-        .id             = V2M_CT_ID_CA9,
-        .name           = "CA9x4",
-        .map_io         = ct_ca9x4_map_io,
-        .init_irq       = ct_ca9x4_init_irq,
-        .init_tile      = ct_ca9x4_init,
-#ifdef CONFIG_SMP
-        .init_cpu_map   = ct_ca9x4_init_cpu_map,
-        .smp_enable     = ct_ca9x4_smp_enable,
-#endif
-};
diff --git a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
deleted file mode 100644
index 84acf8439d4b..000000000000
--- a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#ifndef __MACH_CT_CA9X4_H
-#define __MACH_CT_CA9X4_H
-/*
- * Physical base addresses
- */
-#define CT_CA9X4_CLCDC          (0x10020000)
-#define CT_CA9X4_AXIRAM         (0x10060000)
-#define CT_CA9X4_DMC            (0x100e0000)
-#define CT_CA9X4_SMC            (0x100e1000)
-#define CT_CA9X4_SCC            (0x100e2000)
-#define CT_CA9X4_SP804_TIMER    (0x100e4000)
-#define CT_CA9X4_SP805_WDT      (0x100e5000)
-#define CT_CA9X4_TZPC           (0x100e6000)
-#define CT_CA9X4_GPIO           (0x100e8000)
-#define CT_CA9X4_FASTAXI        (0x100e9000)
-#define CT_CA9X4_SLOWAXI        (0x100ea000)
-#define CT_CA9X4_TZASC          (0x100ec000)
-#define CT_CA9X4_CORESIGHT      (0x10200000)
-#define CT_CA9X4_MPIC           (0x1e000000)
-#define CT_CA9X4_SYSTIMER       (0x1e004000)
-#define CT_CA9X4_SYSWDT         (0x1e007000)
-#define CT_CA9X4_L2CC           (0x1e00a000)
-#define A9_MPCORE_SCU           (CT_CA9X4_MPIC + 0x0000)
-#define A9_MPCORE_GIC_CPU       (CT_CA9X4_MPIC + 0x0100)
-#define A9_MPCORE_GIT           (CT_CA9X4_MPIC + 0x0200)
-#define A9_MPCORE_TWD           (CT_CA9X4_MPIC + 0x0600)
-#define A9_MPCORE_GIC_DIST      (CT_CA9X4_MPIC + 0x1000)
-/*
- * Interrupts.  Those in {} are for AMBA devices
- */
-#define IRQ_CT_CA9X4_CLCDC      { 76 }
-#define IRQ_CT_CA9X4_DMC        { 0 }
-#define IRQ_CT_CA9X4_SMC        { 77, 78 }
-#define IRQ_CT_CA9X4_TIMER0     80
-#define IRQ_CT_CA9X4_TIMER1     81
-#define IRQ_CT_CA9X4_GPIO       { 82 }
-#define IRQ_CT_CA9X4_PMU_CPU0   92
-#define IRQ_CT_CA9X4_PMU_CPU1   93
-#define IRQ_CT_CA9X4_PMU_CPU2   94
-#define IRQ_CT_CA9X4_PMU_CPU3   95
-extern struct ct_desc ct_ca9x4_desc;
-#endif
diff --git a/arch/arm/mach-vexpress/include/mach/hardware.h b/arch/arm/mach-vexpress/include/mach/hardware.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-vexpress/include/mach/hardware.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-vexpress/include/mach/irqs.h b/arch/arm/mach-vexpress/include/mach/irqs.h
deleted file mode 100644
index f8f7f782eb55..000000000000
--- a/arch/arm/mach-vexpress/include/mach/irqs.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#define IRQ_LOCALTIMER          29
-#define IRQ_LOCALWDOG           30
-#ifndef CONFIG_SPARSE_IRQ
-#define NR_IRQS 256
-#endif
diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h
deleted file mode 100644
index 68abc8b72781..000000000000
--- a/arch/arm/mach-vexpress/include/mach/motherboard.h
+++ /dev/null
@@ -1,88 +0,0 @@
-#ifndef __MACH_MOTHERBOARD_H
-#define __MACH_MOTHERBOARD_H
-/*
- * Physical addresses, offset from V2M_PA_CS0-3
- */
-#define V2M_NOR0                (V2M_PA_CS0)
-#define V2M_NOR1                (V2M_PA_CS1)
-#define V2M_SRAM                (V2M_PA_CS2)
-#define V2M_VIDEO_SRAM          (V2M_PA_CS3 + 0x00000000)
-#define V2M_LAN9118             (V2M_PA_CS3 + 0x02000000)
-#define V2M_ISP1761             (V2M_PA_CS3 + 0x03000000)
-/*
- * Physical addresses, offset from V2M_PA_CS7
- */
-#define V2M_SYSREGS             (V2M_PA_CS7 + 0x00000000)
-#define V2M_SYSCTL              (V2M_PA_CS7 + 0x00001000)
-#define V2M_SERIAL_BUS_PCI      (V2M_PA_CS7 + 0x00002000)
-#define V2M_AACI                (V2M_PA_CS7 + 0x00004000)
-#define V2M_MMCI                (V2M_PA_CS7 + 0x00005000)
-#define V2M_KMI0                (V2M_PA_CS7 + 0x00006000)
-#define V2M_KMI1                (V2M_PA_CS7 + 0x00007000)
-#define V2M_UART0               (V2M_PA_CS7 + 0x00009000)
-#define V2M_UART1               (V2M_PA_CS7 + 0x0000a000)
-#define V2M_UART2               (V2M_PA_CS7 + 0x0000b000)
-#define V2M_UART3               (V2M_PA_CS7 + 0x0000c000)
-#define V2M_WDT                 (V2M_PA_CS7 + 0x0000f000)
-#define V2M_TIMER01             (V2M_PA_CS7 + 0x00011000)
-#define V2M_TIMER23             (V2M_PA_CS7 + 0x00012000)
-#define V2M_SERIAL_BUS_DVI      (V2M_PA_CS7 + 0x00016000)
-#define V2M_RTC                 (V2M_PA_CS7 + 0x00017000)
-#define V2M_CF                  (V2M_PA_CS7 + 0x0001a000)
-#define V2M_CLCD                (V2M_PA_CS7 + 0x0001f000)
-/*
- * Interrupts.  Those in {} are for AMBA devices
- */
-#define IRQ_V2M_WDT             { (32 + 0) }
-#define IRQ_V2M_TIMER0          (32 + 2)
-#define IRQ_V2M_TIMER1          (32 + 2)
-#define IRQ_V2M_TIMER2          (32 + 3)
-#define IRQ_V2M_TIMER3          (32 + 3)
-#define IRQ_V2M_RTC             { (32 + 4) }
-#define IRQ_V2M_UART0           { (32 + 5) }
-#define IRQ_V2M_UART1           { (32 + 6) }
-#define IRQ_V2M_UART2           { (32 + 7) }
-#define IRQ_V2M_UART3           { (32 + 8) }
-#define IRQ_V2M_MMCI            { (32 + 9), (32 + 10) }
-#define IRQ_V2M_AACI            { (32 + 11) }
-#define IRQ_V2M_KMI0            { (32 + 12) }
-#define IRQ_V2M_KMI1            { (32 + 13) }
-#define IRQ_V2M_CLCD            { (32 + 14) }
-#define IRQ_V2M_LAN9118         (32 + 15)
-#define IRQ_V2M_ISP1761         (32 + 16)
-#define IRQ_V2M_PCIE            (32 + 17)
-/*
- * Core tile IDs
- */
-#define V2M_CT_ID_CA9           0x0c000191
-#define V2M_CT_ID_UNSUPPORTED   0xff000191
-#define V2M_CT_ID_MASK          0xff000fff
-struct ct_desc {
-        u32                     id;
-        const char              *name;
-        void                    (*map_io)(void);
-        void                    (*init_early)(void);
-        void                    (*init_irq)(void);
-        void                    (*init_tile)(void);
-#ifdef CONFIG_SMP
-        void                    (*init_cpu_map)(void);
-        void                    (*smp_enable)(unsigned int);
-#endif
-};
-extern struct ct_desc *ct_desc;
-#endif
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index a1f3804fd5a5..83188cf1875d 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -19,48 +19,10 @@
 #include <asm/smp_scu.h>
 #include <asm/mach/map.h>
-#include <mach/motherboard.h>
 #include <plat/platsmp.h>
 #include "core.h"
-/*
- * Initialise the CPU possible map early - this describes the CPUs
- * which may be present or become present in the system.
- */
-static void __init vexpress_smp_init_cpus(void)
-{
-        ct_desc->init_cpu_map();
-}
-static void __init vexpress_smp_prepare_cpus(unsigned int max_cpus)
-{
-        /*
-         * Initialise the present map, which describes the set of CPUs
-         * actually populated at the present time.
-         */
-        ct_desc->smp_enable(max_cpus);
-        /*
-         * Write the address of secondary startup into the
-         * system-wide flags register. The boot monitor waits
-         * until it receives a soft interrupt, and then the
-         * secondary CPU branches to this address.
-         */
-        vexpress_flags_set(virt_to_phys(versatile_secondary_startup));
-}
-struct smp_operations __initdata vexpress_smp_ops = {
-        .smp_init_cpus          = vexpress_smp_init_cpus,
-        .smp_prepare_cpus       = vexpress_smp_prepare_cpus,
-        .smp_secondary_init     = versatile_secondary_init,
-        .smp_boot_secondary     = versatile_boot_secondary,
-#ifdef CONFIG_HOTPLUG_CPU
-        .cpu_die                = vexpress_cpu_die,
-#endif
-};
 bool __init vexpress_smp_init_ops(void)
 {
 #ifdef CONFIG_MCPM
@@ -79,8 +41,6 @@ bool __init vexpress_smp_init_ops(void)
        return false;
 }
-#if defined(CONFIG_OF)
 static const struct of_device_id vexpress_smp_dt_scu_match[] __initconst = {
        { .compatible = "arm,cortex-a5-scu", },
        { .compatible = "arm,cortex-a9-scu", },
@@ -112,5 +72,3 @@ struct smp_operations __initdata vexpress_smp_dt_ops = {
        .cpu_die                = vexpress_cpu_die,
 #endif
 };
-#endif
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 6ff681a24ba7..a0400f4cca89 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -1,380 +1,7 @@
-/*
- * Versatile Express V2M Motherboard Support
- */
-#include <linux/device.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/mmci.h>
-#include <linux/io.h>
-#include <linux/smp.h>
-#include <linux/init.h>
-#include <linux/of_address.h>
-#include <linux/of_fdt.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <linux/platform_device.h>
-#include <linux/ata_platform.h>
-#include <linux/smsc911x.h>
-#include <linux/spinlock.h>
-#include <linux/usb/isp1760.h>
-#include <linux/mtd/physmap.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-#include <linux/vexpress.h>
-#include <linux/clkdev.h>
-#include <asm/mach-types.h>
-#include <asm/sizes.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-#include <asm/hardware/arm_timer.h>
-#include <asm/hardware/cache-l2x0.h>
-#include <asm/hardware/timer-sp.h>
-#include <mach/ct-ca9x4.h>
-#include <mach/motherboard.h>
-#include <plat/sched_clock.h>
-#include <plat/platsmp.h>
 #include "core.h"
-#define V2M_PA_CS0      0x40000000
-#define V2M_PA_CS1      0x44000000
-#define V2M_PA_CS2      0x48000000
-#define V2M_PA_CS3      0x4c000000
-#define V2M_PA_CS7      0x10000000
-static struct map_desc v2m_io_desc[] __initdata = {
-        {
-                .virtual        = V2M_PERIPH,
-                .pfn            = __phys_to_pfn(V2M_PA_CS7),
-                .length         = SZ_128K,
-                .type           = MT_DEVICE,
-        },
-};
-static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
-{
-        if (WARN_ON(!base || irq == NO_IRQ))
-                return;
-        sp804_clocksource_init(base + TIMER_2_BASE, "v2m-timer1");
-        sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0");
-}
-static struct resource v2m_pcie_i2c_resource = {
-        .start  = V2M_SERIAL_BUS_PCI,
-        .end    = V2M_SERIAL_BUS_PCI + SZ_4K - 1,
-        .flags  = IORESOURCE_MEM,
-};
-static struct platform_device v2m_pcie_i2c_device = {
-        .name           = "versatile-i2c",
-        .id             = 0,
-        .num_resources  = 1,
-        .resource       = &v2m_pcie_i2c_resource,
-};
-static struct resource v2m_ddc_i2c_resource = {
-        .start  = V2M_SERIAL_BUS_DVI,
-        .end    = V2M_SERIAL_BUS_DVI + SZ_4K - 1,
-        .flags  = IORESOURCE_MEM,
-};
-static struct platform_device v2m_ddc_i2c_device = {
-        .name           = "versatile-i2c",
-        .id             = 1,
-        .num_resources  = 1,
-        .resource       = &v2m_ddc_i2c_resource,
-};
-static struct resource v2m_eth_resources[] = {
-        {
-                .start  = V2M_LAN9118,
-                .end    = V2M_LAN9118 + SZ_64K - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_V2M_LAN9118,
-                .end    = IRQ_V2M_LAN9118,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct smsc911x_platform_config v2m_eth_config = {
-        .flags          = SMSC911X_USE_32BIT,
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
-        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-};
-static struct platform_device v2m_eth_device = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .resource       = v2m_eth_resources,
-        .num_resources  = ARRAY_SIZE(v2m_eth_resources),
-        .dev.platform_data = &v2m_eth_config,
-};
-static struct regulator_consumer_supply v2m_eth_supplies[] = {
-        REGULATOR_SUPPLY("vddvario", "smsc911x"),
-        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
-};
-static struct resource v2m_usb_resources[] = {
-        {
-                .start  = V2M_ISP1761,
-                .end    = V2M_ISP1761 + SZ_128K - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_V2M_ISP1761,
-                .end    = IRQ_V2M_ISP1761,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct isp1760_platform_data v2m_usb_config = {
-        .is_isp1761             = true,
-        .bus_width_16           = false,
-        .port1_otg              = true,
-        .analog_oc              = false,
-        .dack_polarity_high     = false,
-        .dreq_polarity_high     = false,
-};
-static struct platform_device v2m_usb_device = {
-        .name           = "isp1760",
-        .id             = -1,
-        .resource       = v2m_usb_resources,
-        .num_resources  = ARRAY_SIZE(v2m_usb_resources),
-        .dev.platform_data = &v2m_usb_config,
-};
-static struct physmap_flash_data v2m_flash_data = {
-        .width          = 4,
-};
-static struct resource v2m_flash_resources[] = {
-        {
-                .start  = V2M_NOR0,
-                .end    = V2M_NOR0 + SZ_64M - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = V2M_NOR1,
-                .end    = V2M_NOR1 + SZ_64M - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device v2m_flash_device = {
-        .name           = "physmap-flash",
-        .id             = -1,
-        .resource       = v2m_flash_resources,
-        .num_resources  = ARRAY_SIZE(v2m_flash_resources),
-        .dev.platform_data = &v2m_flash_data,
-};
-static struct pata_platform_info v2m_pata_data = {
-        .ioport_shift   = 2,
-};
-static struct resource v2m_pata_resources[] = {
-        {
-                .start  = V2M_CF,
-                .end    = V2M_CF + 0xff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = V2M_CF + 0x100,
-                .end    = V2M_CF + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device v2m_cf_device = {
-        .name           = "pata_platform",
-        .id             = -1,
-        .resource       = v2m_pata_resources,
-        .num_resources  = ARRAY_SIZE(v2m_pata_resources),
-        .dev.platform_data = &v2m_pata_data,
-};
-static struct mmci_platform_data v2m_mmci_data = {
-        .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
-        .status         = vexpress_get_mci_cardin,
-        .gpio_cd        = -1,
-        .gpio_wp        = -1,
-};
-static struct resource v2m_sysreg_resources[] = {
-        {
-                .start  = V2M_SYSREGS,
-                .end    = V2M_SYSREGS + 0xfff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device v2m_sysreg_device = {
-        .name           = "vexpress-sysreg",
-        .id             = -1,
-        .resource       = v2m_sysreg_resources,
-        .num_resources  = ARRAY_SIZE(v2m_sysreg_resources),
-};
-static struct platform_device v2m_muxfpga_device = {
-        .name           = "vexpress-muxfpga",
-        .id             = 0,
-        .num_resources  = 1,
-        .resource       = (struct resource []) {
-                VEXPRESS_RES_FUNC(0, 7),
-        }
-};
-static struct platform_device v2m_shutdown_device = {
-        .name           = "vexpress-shutdown",
-        .id             = 0,
-        .num_resources  = 1,
-        .resource       = (struct resource []) {
-                VEXPRESS_RES_FUNC(0, 8),
-        }
-};
-static struct platform_device v2m_reboot_device = {
-        .name           = "vexpress-reboot",
-        .id             = 0,
-        .num_resources  = 1,
-        .resource       = (struct resource []) {
-                VEXPRESS_RES_FUNC(0, 9),
-        }
-};
-static struct platform_device v2m_dvimode_device = {
-        .name           = "vexpress-dvimode",
-        .id             = 0,
-        .num_resources  = 1,
-        .resource       = (struct resource []) {
-                VEXPRESS_RES_FUNC(0, 11),
-        }
-};
-static AMBA_APB_DEVICE(aaci,  "mb:aaci",  0, V2M_AACI, IRQ_V2M_AACI, NULL);
-static AMBA_APB_DEVICE(mmci,  "mb:mmci",  0, V2M_MMCI, IRQ_V2M_MMCI, &v2m_mmci_data);
-static AMBA_APB_DEVICE(kmi0,  "mb:kmi0",  0, V2M_KMI0, IRQ_V2M_KMI0, NULL);
-static AMBA_APB_DEVICE(kmi1,  "mb:kmi1",  0, V2M_KMI1, IRQ_V2M_KMI1, NULL);
-static AMBA_APB_DEVICE(uart0, "mb:uart0", 0, V2M_UART0, IRQ_V2M_UART0, NULL);
-static AMBA_APB_DEVICE(uart1, "mb:uart1", 0, V2M_UART1, IRQ_V2M_UART1, NULL);
-static AMBA_APB_DEVICE(uart2, "mb:uart2", 0, V2M_UART2, IRQ_V2M_UART2, NULL);
-static AMBA_APB_DEVICE(uart3, "mb:uart3", 0, V2M_UART3, IRQ_V2M_UART3, NULL);
-static AMBA_APB_DEVICE(wdt,   "mb:wdt",   0, V2M_WDT, IRQ_V2M_WDT, NULL);
-static AMBA_APB_DEVICE(rtc,   "mb:rtc",   0, V2M_RTC, IRQ_V2M_RTC, NULL);
-static struct amba_device *v2m_amba_devs[] __initdata = {
-        &aaci_device,
-        &mmci_device,
-        &kmi0_device,
-        &kmi1_device,
-        &uart0_device,
-        &uart1_device,
-        &uart2_device,
-        &uart3_device,
-        &wdt_device,
-        &rtc_device,
-};
-static void __init v2m_timer_init(void)
-{
-        vexpress_clk_init(ioremap(V2M_SYSCTL, SZ_4K));
-        v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
-}
-static void __init v2m_init_early(void)
-{
-        if (ct_desc->init_early)
-                ct_desc->init_early();
-        versatile_sched_clock_init(vexpress_get_24mhz_clock_base(), 24000000);
-}
-struct ct_desc *ct_desc;
-static struct ct_desc *ct_descs[] __initdata = {
-#ifdef CONFIG_ARCH_VEXPRESS_CA9X4
-        &ct_ca9x4_desc,
-#endif
-};
-static void __init v2m_populate_ct_desc(void)
-{
-        int i;
-        u32 current_tile_id;
-        ct_desc = NULL;
-        current_tile_id = vexpress_get_procid(VEXPRESS_SITE_MASTER)
-                                & V2M_CT_ID_MASK;
-        for (i = 0; i < ARRAY_SIZE(ct_descs) && !ct_desc; ++i)
-                if (ct_descs[i]->id == current_tile_id)
-                        ct_desc = ct_descs[i];
-        if (!ct_desc)
-                panic("vexpress: this kernel does not support core tile ID 0x%08x when booting via ATAGs.\n"
-                      "You may need a device tree blob or a different kernel to boot on this board.\n",
-                      current_tile_id);
-}
-static void __init v2m_map_io(void)
-{
-        iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
-        vexpress_sysreg_early_init(ioremap(V2M_SYSREGS, SZ_4K));
-        v2m_populate_ct_desc();
-        ct_desc->map_io();
-}
-static void __init v2m_init_irq(void)
-{
-        ct_desc->init_irq();
-}
-static void __init v2m_init(void)
-{
-        int i;
-        regulator_register_fixed(0, v2m_eth_supplies,
-                        ARRAY_SIZE(v2m_eth_supplies));
-        platform_device_register(&v2m_sysreg_device);
-        platform_device_register(&v2m_pcie_i2c_device);
-        platform_device_register(&v2m_ddc_i2c_device);
-        platform_device_register(&v2m_flash_device);
-        platform_device_register(&v2m_cf_device);
-        platform_device_register(&v2m_eth_device);
-        platform_device_register(&v2m_usb_device);
-        for (i = 0; i < ARRAY_SIZE(v2m_amba_devs); i++)
-                amba_device_register(v2m_amba_devs[i], &iomem_resource);
-        vexpress_syscfg_device_register(&v2m_muxfpga_device);
-        vexpress_syscfg_device_register(&v2m_shutdown_device);
-        vexpress_syscfg_device_register(&v2m_reboot_device);
-        vexpress_syscfg_device_register(&v2m_dvimode_device);
-        ct_desc->init_tile();
-}
-MACHINE_START(VEXPRESS, "ARM-Versatile Express")
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(vexpress_smp_ops),
-        .map_io         = v2m_map_io,
-        .init_early     = v2m_init_early,
-        .init_irq       = v2m_init_irq,
-        .init_time      = v2m_timer_init,
-        .init_machine   = v2m_init,
-MACHINE_END
-static void __init v2m_dt_init(void)
-{
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
 static const char * const v2m_dt_match[] __initconst = {
        "arm,vexpress",
        NULL,
@@ -386,5 +13,4 @@ DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
        .l2c_aux_mask   = 0xfe0fffff,
        .smp            = smp_ops(vexpress_smp_dt_ops),
        .smp_init       = smp_init_ops(vexpress_smp_init_ops),
-        .init_machine   = v2m_dt_init,
 MACHINE_END
diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
index c85fb3f7d5cd..b03a97eb7501 100644
--- a/arch/arm/mach-zynq/Makefile
+++ b/arch/arm/mach-zynq/Makefile
@@ -4,6 +4,4 @@
 # Common support
 obj-y                           := common.o slcr.o pm.o
-CFLAGS_REMOVE_hotplug.o         =-march=armv6k
-CFLAGS_hotplug.o                =-Wa,-march=armv7-a -mcpu=cortex-a9
 obj-$(CONFIG_SMP)               += headsmp.o platsmp.o
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index 2bc71273c73c..382c60e9aa16 100644
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -29,7 +29,6 @@ extern void zynq_slcr_cpu_state_write(int cpu, bool die);
 extern u32 zynq_slcr_get_device_id(void);
 #ifdef CONFIG_SMP
-extern void secondary_startup(void);
 extern char zynq_secondary_trampoline;
 extern char zynq_secondary_trampoline_jump;
 extern char zynq_secondary_trampoline_end;
diff --git a/arch/arm/mach-zynq/hotplug.c b/arch/arm/mach-zynq/hotplug.c
deleted file mode 100644
index b685c89f11e4..000000000000
--- a/arch/arm/mach-zynq/hotplug.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (C) 2012-2013 Xilinx
- *
- * based on linux/arch/arm/mach-realview/hotplug.c
- *
- * Copyright (C) 2002 ARM Ltd.
- * All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <asm/proc-fns.h>
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 7eb94e6fc376..ab906b801047 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -21,7 +21,7 @@ config CPU_ARM7TDMI
 # ARM720T
 config CPU_ARM720T
-        bool "Support ARM720T processor" if ARCH_INTEGRATOR
+        bool "Support ARM720T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
        select CPU_32v4T
        select CPU_ABRT_LV4T
        select CPU_CACHE_V4
@@ -39,7 +39,7 @@ config CPU_ARM720T
 # ARM740T
 config CPU_ARM740T
-        bool "Support ARM740T processor" if ARCH_INTEGRATOR
+        bool "Support ARM740T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
        depends on !MMU
        select CPU_32v4T
        select CPU_ABRT_LV4T
@@ -71,7 +71,7 @@ config CPU_ARM9TDMI
 # ARM920T
 config CPU_ARM920T
-        bool "Support ARM920T processor" if ARCH_INTEGRATOR
+        bool "Support ARM920T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
        select CPU_32v4T
        select CPU_ABRT_EV4T
        select CPU_CACHE_V4WT
@@ -89,7 +89,7 @@ config CPU_ARM920T
 # ARM922T
 config CPU_ARM922T
-        bool "Support ARM922T processor" if ARCH_INTEGRATOR
+        bool "Support ARM922T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
        select CPU_32v4T
        select CPU_ABRT_EV4T
        select CPU_CACHE_V4WT
@@ -127,7 +127,7 @@ config CPU_ARM925T
 # ARM926T
 config CPU_ARM926T
-        bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
+        bool "Support ARM926T processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V5) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB)
        select CPU_32v5
        select CPU_ABRT_EV5TJ
        select CPU_CACHE_VIVT
@@ -163,7 +163,7 @@ config CPU_FA526
 # ARM940T
 config CPU_ARM940T
-        bool "Support ARM940T processor" if ARCH_INTEGRATOR
+        bool "Support ARM940T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
        depends on !MMU
        select CPU_32v4T
        select CPU_ABRT_NOMMU
@@ -181,7 +181,7 @@ config CPU_ARM940T
 # ARM946E-S
 config CPU_ARM946E
-        bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
+        bool "Support ARM946E-S processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
        depends on !MMU
        select CPU_32v5
        select CPU_ABRT_NOMMU
@@ -198,7 +198,7 @@ config CPU_ARM946E
 # ARM1020 - needs validating
 config CPU_ARM1020
-        bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR
+        bool "Support ARM1020T (rev 0) processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
        select CPU_32v5
        select CPU_ABRT_EV4T
        select CPU_CACHE_V4WT
@@ -216,7 +216,7 @@ config CPU_ARM1020
 # ARM1020E - needs validating
 config CPU_ARM1020E
-        bool "Support ARM1020E processor" if ARCH_INTEGRATOR
+        bool "Support ARM1020E processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
        depends on n
        select CPU_32v5
        select CPU_ABRT_EV4T
@@ -229,7 +229,7 @@ config CPU_ARM1020E
 # ARM1022E
 config CPU_ARM1022
-        bool "Support ARM1022E processor" if ARCH_INTEGRATOR
+        bool "Support ARM1022E processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
        select CPU_32v5
        select CPU_ABRT_EV4T
        select CPU_CACHE_VIVT
@@ -247,7 +247,7 @@ config CPU_ARM1022
 # ARM1026EJ-S
 config CPU_ARM1026
-        bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR
+        bool "Support ARM1026EJ-S processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
        select CPU_32v5
        select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
        select CPU_CACHE_VIVT
@@ -358,7 +358,7 @@ config CPU_PJ4B
 # ARMv6
 config CPU_V6
-        bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
+        bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
        select CPU_32v6
        select CPU_ABRT_EV6
        select CPU_CACHE_V6
@@ -371,7 +371,7 @@ config CPU_V6
 # ARMv6k
 config CPU_V6K
-        bool "Support ARM V6K processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
+        bool "Support ARM V6K processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
        select CPU_32v6
        select CPU_32v6K
        select CPU_ABRT_EV6
@@ -385,7 +385,7 @@ config CPU_V6K
 # ARMv7
 config CPU_V7
-        bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
+        bool "Support ARM V7 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V7) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
        select CPU_32v6K
        select CPU_32v7
        select CPU_ABRT_EV7
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index e048f6198d68..5168a52a17f9 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -306,9 +306,10 @@ EXPORT_SYMBOL(orion_gpio_set_blink);
 #define ORION_BLINK_HALF_PERIOD 100 /* ms */
-int orion_gpio_led_blink_set(unsigned gpio, int state,
+int orion_gpio_led_blink_set(struct gpio_desc *desc, int state,
        unsigned long *delay_on, unsigned long *delay_off)
 {
+        unsigned gpio = desc_to_gpio(desc);
        if (delay_on && delay_off && !*delay_on && !*delay_off)
                *delay_on = *delay_off = ORION_BLINK_HALF_PERIOD;
@@ -505,9 +506,9 @@ static void orion_gpio_unmask_irq(struct irq_data *d)
        u32 mask = d->mask;
        irq_gc_lock(gc);
-        reg_val = irq_reg_readl(gc->reg_base + ct->regs.mask);
+        reg_val = irq_reg_readl(gc, ct->regs.mask);
        reg_val |= mask;
-        irq_reg_writel(reg_val, gc->reg_base + ct->regs.mask);
+        irq_reg_writel(gc, reg_val, ct->regs.mask);
        irq_gc_unlock(gc);
 }
@@ -519,9 +520,9 @@ static void orion_gpio_mask_irq(struct irq_data *d)
        u32 reg_val;
        irq_gc_lock(gc);
-        reg_val = irq_reg_readl(gc->reg_base + ct->regs.mask);
+        reg_val = irq_reg_readl(gc, ct->regs.mask);
        reg_val &= ~mask;
-        irq_reg_writel(reg_val, gc->reg_base + ct->regs.mask);
+        irq_reg_writel(gc, reg_val, ct->regs.mask);
        irq_gc_unlock(gc);
 }
diff --git a/arch/arm/plat-orion/include/plat/orion-gpio.h b/arch/arm/plat-orion/include/plat/orion-gpio.h
index e763988b04b9..e856b073a9c8 100644
--- a/arch/arm/plat-orion/include/plat/orion-gpio.h
+++ b/arch/arm/plat-orion/include/plat/orion-gpio.h
@@ -14,12 +14,15 @@
 #include <linux/init.h>
 #include <linux/types.h>
 #include <linux/irqdomain.h>
+struct gpio_desc;
 /*
 * Orion-specific GPIO API extensions.
 */
 void orion_gpio_set_unused(unsigned pin);
 void orion_gpio_set_blink(unsigned pin, int blink);
-int orion_gpio_led_blink_set(unsigned gpio, int state,
+int orion_gpio_led_blink_set(struct gpio_desc *desc, int state,
        unsigned long *delay_on, unsigned long *delay_off);
 #define GPIO_INPUT_OK           (1 << 0)
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index f0a008496993..87746c37f030 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_SAMSUNG_DMADEV)	+= dma-ops.o
 # PM support
 obj-$(CONFIG_PM_SLEEP)          += pm-common.o
+obj-$(CONFIG_EXYNOS_CPU_SUSPEND) += pm-common.o
 obj-$(CONFIG_SAMSUNG_PM)        += pm.o
 obj-$(CONFIG_SAMSUNG_PM_GPIO)   += pm-gpio.o
 obj-$(CONFIG_SAMSUNG_PM_CHECK)  += pm-check.o
diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h
index f5b9d3ff9cd4..f5cf2bd208e0 100644
--- a/arch/arm/plat-samsung/include/plat/map-s5p.h
+++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
@@ -15,43 +15,22 @@
 #define S5P_VA_CHIPID           S3C_ADDR(0x02000000)
 #define S5P_VA_CMU              S3C_ADDR(0x02100000)
-#define S5P_VA_GPIO             S3C_ADDR(0x02200000)
-#define S5P_VA_GPIO1            S5P_VA_GPIO
-#define S5P_VA_GPIO2            S3C_ADDR(0x02240000)
-#define S5P_VA_GPIO3            S3C_ADDR(0x02280000)
-#define S5P_VA_SYSRAM           S3C_ADDR(0x02400000)
-#define S5P_VA_SYSRAM_NS        S3C_ADDR(0x02410000)
 #define S5P_VA_DMC0             S3C_ADDR(0x02440000)
 #define S5P_VA_DMC1             S3C_ADDR(0x02480000)
 #define S5P_VA_SROMC            S3C_ADDR(0x024C0000)
-#define S5P_VA_SYSTIMER         S3C_ADDR(0x02500000)
-#define S5P_VA_L2CC             S3C_ADDR(0x02600000)
-#define S5P_VA_COMBINER_BASE    S3C_ADDR(0x02700000)
-#define S5P_VA_COMBINER(x)      (S5P_VA_COMBINER_BASE + ((x) >> 2) * 0x10)
 #define S5P_VA_COREPERI_BASE    S3C_ADDR(0x02800000)
 #define S5P_VA_COREPERI(x)      (S5P_VA_COREPERI_BASE + (x))
 #define S5P_VA_SCU              S5P_VA_COREPERI(0x0)
 #define S5P_VA_TWD              S5P_VA_COREPERI(0x600)
-#define S5P_VA_GIC_CPU          S3C_ADDR(0x02810000)
-#define S5P_VA_GIC_DIST         S3C_ADDR(0x02820000)
 #define VA_VIC(x)               (S3C_VA_IRQ + ((x) * 0x10000))
 #define VA_VIC0                 VA_VIC(0)
 #define VA_VIC1                 VA_VIC(1)
 #define VA_VIC2                 VA_VIC(2)
 #define VA_VIC3                 VA_VIC(3)
-#define S5P_VA_UART(x)          (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
-#define S5P_VA_UART0            S5P_VA_UART(0)
-#define S5P_VA_UART1            S5P_VA_UART(1)
-#define S5P_VA_UART2            S5P_VA_UART(2)
-#define S5P_VA_UART3            S5P_VA_UART(3)
 #ifndef S3C_UART_OFFSET
 #define S3C_UART_OFFSET         (0x400)
 #endif
diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig
index a301ca2c7d00..49b8ef91584a 100644
--- a/arch/arm/plat-versatile/Kconfig
+++ b/arch/arm/plat-versatile/Kconfig
@@ -4,6 +4,6 @@ config PLAT_VERSATILE_CLOCK
        bool
 config PLAT_VERSATILE_SCHED_CLOCK
-        def_bool y
+        bool
 endif
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 9532f8d5857e..6b1ebd964c10 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -24,9 +24,9 @@ config ARM64
        select GENERIC_CLOCKEVENTS_BROADCAST if SMP
        select GENERIC_CPU_AUTOPROBE
        select GENERIC_EARLY_IOREMAP
-        select GENERIC_IOMAP
        select GENERIC_IRQ_PROBE
        select GENERIC_IRQ_SHOW
+        select GENERIC_PCI_IOMAP
        select GENERIC_SCHED_CLOCK
        select GENERIC_SMP_IDLE_THREAD
        select GENERIC_STRNCPY_FROM_USER
@@ -34,13 +34,16 @@ config ARM64
        select GENERIC_TIME_VSYSCALL
        select HANDLE_DOMAIN_IRQ
        select HARDIRQS_SW_RESEND
+        select HAVE_ALIGNED_STRUCT_PAGE if SLUB
        select HAVE_ARCH_AUDITSYSCALL
        select HAVE_ARCH_JUMP_LABEL
        select HAVE_ARCH_KGDB
+        select HAVE_ARCH_SECCOMP_FILTER
        select HAVE_ARCH_TRACEHOOK
        select HAVE_BPF_JIT
        select HAVE_C_RECORDMCOUNT
        select HAVE_CC_STACKPROTECTOR
+        select HAVE_CMPXCHG_DOUBLE
        select HAVE_DEBUG_BUGVERBOSE
        select HAVE_DEBUG_KMEMLEAK
        select HAVE_DMA_API_DEBUG
@@ -142,6 +145,11 @@ source "kernel/Kconfig.freezer"
 menu "Platform selection"
+config ARCH_SEATTLE
+        bool "AMD Seattle SoC Family"
+        help
+          This enables support for AMD Seattle SOC Family
 config ARCH_THUNDER
        bool "Cavium Inc. Thunder SoC Family"
        help
@@ -166,9 +174,6 @@ endmenu
 menu "Bus support"
-config ARM_AMBA
-        bool
 config PCI
        bool "PCI support"
        help
@@ -193,6 +198,114 @@ endmenu
 menu "Kernel Features"
+menu "ARM errata workarounds via the alternatives framework"
+config ARM64_ERRATUM_826319
+        bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
+        default y
+        help
+          This option adds an alternative code sequence to work around ARM
+          erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
+          AXI master interface and an L2 cache.
+          If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
+          and is unable to accept a certain write via this interface, it will
+          not progress on read data presented on the read data channel and the
+          system can deadlock.
+          The workaround promotes data cache clean instructions to
+          data cache clean-and-invalidate.
+          Please note that this does not necessarily enable the workaround,
+          as it depends on the alternative framework, which will only patch
+          the kernel if an affected CPU is detected.
+          If unsure, say Y.
+config ARM64_ERRATUM_827319
+        bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
+        default y
+        help
+          This option adds an alternative code sequence to work around ARM
+          erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
+          master interface and an L2 cache.
+          Under certain conditions this erratum can cause a clean line eviction
+          to occur at the same time as another transaction to the same address
+          on the AMBA 5 CHI interface, which can cause data corruption if the
+          interconnect reorders the two transactions.
+          The workaround promotes data cache clean instructions to
+          data cache clean-and-invalidate.
+          Please note that this does not necessarily enable the workaround,
+          as it depends on the alternative framework, which will only patch
+          the kernel if an affected CPU is detected.
+          If unsure, say Y.
+config ARM64_ERRATUM_824069
+        bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
+        default y
+        help
+          This option adds an alternative code sequence to work around ARM
+          erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
+          to a coherent interconnect.
+          If a Cortex-A53 processor is executing a store or prefetch for
+          write instruction at the same time as a processor in another
+          cluster is executing a cache maintenance operation to the same
+          address, then this erratum might cause a clean cache line to be
+          incorrectly marked as dirty.
+          The workaround promotes data cache clean instructions to
+          data cache clean-and-invalidate.
+          Please note that this option does not necessarily enable the
+          workaround, as it depends on the alternative framework, which will
+          only patch the kernel if an affected CPU is detected.
+          If unsure, say Y.
+config ARM64_ERRATUM_819472
+        bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
+        default y
+        help
+          This option adds an alternative code sequence to work around ARM
+          erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
+          present when it is connected to a coherent interconnect.
+          If the processor is executing a load and store exclusive sequence at
+          the same time as a processor in another cluster is executing a cache
+          maintenance operation to the same address, then this erratum might
+          cause data corruption.
+          The workaround promotes data cache clean instructions to
+          data cache clean-and-invalidate.
+          Please note that this does not necessarily enable the workaround,
+          as it depends on the alternative framework, which will only patch
+          the kernel if an affected CPU is detected.
+          If unsure, say Y.
+config ARM64_ERRATUM_832075
+        bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
+        default y
+        help
+          This option adds an alternative code sequence to work around ARM
+          erratum 832075 on Cortex-A57 parts up to r1p2.
+          Affected Cortex-A57 parts might deadlock when exclusive load/store
+          instructions to Write-Back memory are mixed with Device loads.
+          The workaround is to promote device loads to use Load-Acquire
+          semantics.
+          Please note that this does not necessarily enable the workaround,
+          as it depends on the alternative framework, which will only patch
+          the kernel if an affected CPU is detected.
+          If unsure, say Y.
+endmenu
 choice
        prompt "Page size"
        default ARM64_4K_PAGES
@@ -345,6 +458,19 @@ config ARCH_HAS_CACHE_LINE_SIZE
 source "mm/Kconfig"
+config SECCOMP
+        bool "Enable seccomp to safely compute untrusted bytecode"
+        ---help---
+          This kernel feature is useful for number crunching applications
+          that may need to compute untrusted bytecode during their
+          execution. By using pipes or other transports made available to
+          the process as file descriptors supporting the read/write
+          syscalls, it's possible to isolate those applications in
+          their own address space using seccomp. Once seccomp is
+          enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
+          and the task is only allowed to execute a few safe syscalls
+          defined by each seccomp mode.
 config XEN_DOM0
        def_bool y
        depends on XEN
@@ -361,6 +487,58 @@ config FORCE_MAX_ZONEORDER
        default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
        default "11"
+menuconfig ARMV8_DEPRECATED
+        bool "Emulate deprecated/obsolete ARMv8 instructions"
+        depends on COMPAT
+        help
+          Legacy software support may require certain instructions
+          that have been deprecated or obsoleted in the architecture.
+          Enable this config to enable selective emulation of these
+          features.
+          If unsure, say Y
+if ARMV8_DEPRECATED
+config SWP_EMULATION
+        bool "Emulate SWP/SWPB instructions"
+        help
+          ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
+          they are always undefined. Say Y here to enable software
+          emulation of these instructions for userspace using LDXR/STXR.
+          In some older versions of glibc [<=2.8] SWP is used during futex
+          trylock() operations with the assumption that the code will not
+          be preempted. This invalid assumption may be more likely to fail
+          with SWP emulation enabled, leading to deadlock of the user
+          application.
+          NOTE: when accessing uncached shared regions, LDXR/STXR rely
+          on an external transaction monitoring block called a global
+          monitor to maintain update atomicity. If your system does not
+          implement a global monitor, this option can cause programs that
+          perform SWP operations to uncached memory to deadlock.
+          If unsure, say Y
+config CP15_BARRIER_EMULATION
+        bool "Emulate CP15 Barrier instructions"
+        help
+          The CP15 barrier instructions - CP15ISB, CP15DSB, and
+          CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
+          strongly recommended to use the ISB, DSB, and DMB
+          instructions instead.
+          Say Y here to enable software emulation of these
+          instructions for AArch32 userspace code. When this option is
+          enabled, CP15 barrier usage is traced which can help
+          identify software that needs updating.
+          If unsure, say Y
+endif
 endmenu
 menu "Boot options"
@@ -401,6 +579,17 @@ config EFI
          allow the kernel to be booted as an EFI application. This
          is only useful on systems that have UEFI firmware.
+config DMI
+        bool "Enable support for SMBIOS (DMI) tables"
+        depends on EFI
+        default y
+        help
+          This enables SMBIOS/DMI feature for systems.
+          This option is only useful on systems that have UEFI firmware.
+          However, even with this option, the resultant kernel should
+          continue to boot on existing non-UEFI platforms.
 endmenu
 menu "Userspace binary formats"
diff --git a/arch/arm64/Kconfig.debug b/arch/arm64/Kconfig.debug
index 0a12933e50ed..5fdd6dce8061 100644
--- a/arch/arm64/Kconfig.debug
+++ b/arch/arm64/Kconfig.debug
@@ -6,6 +6,18 @@ config FRAME_POINTER
        bool
        default y
+config ARM64_PTDUMP
+        bool "Export kernel pagetable layout to userspace via debugfs"
+        depends on DEBUG_KERNEL
+        select DEBUG_FS
+        help
+          Say Y here if you want to show the kernel pagetable layout in a
+          debugfs file. This information is only useful for kernel developers
+          who are working in architecture specific areas of the kernel.
+          It is probably not a good idea to enable this feature in a production
+          kernel.
+          If in doubt, say "N"
 config STRICT_DEVMEM
        bool "Filter access to /dev/mem"
        depends on MMU
diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index 20901ffed182..1c43cec971b5 100644
--- a/arch/arm64/Makefile
+++ b/arch/arm64/Makefile
@@ -70,8 +70,13 @@ zinstall install: vmlinux
 %.dtb: scripts
        $(Q)$(MAKE) $(build)=$(boot)/dts $(boot)/dts/$@
-dtbs: scripts
+PHONY += dtbs dtbs_install
-        $(Q)$(MAKE) $(build)=$(boot)/dts dtbs
+dtbs: prepare scripts
+        $(Q)$(MAKE) $(build)=$(boot)/dts
+dtbs_install:
+        $(Q)$(MAKE) $(dtbinst)=$(boot)/dts
 PHONY += vdso_install
 vdso_install:
@@ -85,6 +90,7 @@ define archhelp
  echo  '* Image.gz      - Compressed kernel image (arch/$(ARCH)/boot/Image.gz)'
  echo  '  Image         - Uncompressed kernel image (arch/$(ARCH)/boot/Image)'
  echo  '* dtbs          - Build device tree blobs for enabled boards'
+  echo  '  dtbs_install  - Install dtbs to $(INSTALL_DTBS_PATH)'
  echo  '  install       - Install uncompressed kernel'
  echo  '  zinstall      - Install compressed kernel'
  echo  '                  Install using (your) ~/bin/installkernel or'
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index f8001a62029c..3b8d427c3985 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,10 +1,8 @@
-dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb
+dts-dirs += amd
-dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
+dts-dirs += apm
-dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
+dts-dirs += arm
+dts-dirs += cavium
-targets += dtbs
+always          := $(dtb-y)
-targets += $(dtb-y)
+subdir-y        := $(dts-dirs)
+clean-files     := *.dtb
-dtbs: $(addprefix $(obj)/, $(dtb-y))
-clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile
new file mode 100644
index 000000000000..cfdf701e05df
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive.dtb
+always          := $(dtb-y)
+subdir-y        := $(dts-dirs)
+clean-files     := *.dtb
diff --git a/arch/arm64/boot/dts/amd/amd-overdrive.dts b/arch/arm64/boot/dts/amd/amd-overdrive.dts
new file mode 100644
index 000000000000..564a3f7df71d
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/amd-overdrive.dts
@@ -0,0 +1,66 @@
+/*
+ * DTS file for AMD Seattle Overdrive Development Board
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ */
+/dts-v1/;
+/include/ "amd-seattle-soc.dtsi"
+/ {
+        model = "AMD Seattle Development Board (Overdrive)";
+        compatible = "amd,seattle-overdrive", "amd,seattle";
+        chosen {
+                stdout-path = &serial0;
+                linux,pci-probe-only;
+        };
+};
+&ccp0 {
+        status = "ok";
+};
+&gpio0 {
+        status = "ok";
+};
+&gpio1 {
+        status = "ok";
+};
+&i2c0 {
+        status = "ok";
+};
+&pcie0 {
+        status = "ok";
+};
+&spi0 {
+        status = "ok";
+};
+&spi1 {
+        status = "ok";
+        sdcard0: sdcard@0 {
+                compatible = "mmc-spi-slot";
+                reg = <0>;
+                spi-max-frequency = <20000000>;
+                voltage-ranges = <3200 3400>;
+                gpios = <&gpio0 7 0>;
+                interrupt-parent = <&gpio0>;
+                interrupts = <7 3>;
+                pl022,hierarchy = <0>;
+                pl022,interface = <0>;
+                pl022,com-mode = <0x0>;
+                pl022,rx-level-trig = <0>;
+                pl022,tx-level-trig = <0>;
+        };
+};
+&v2m0 {
+        arm,msi-base-spi = <64>;
+        arm,msi-num-spis = <256>;
+};
diff --git a/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi
new file mode 100644
index 000000000000..f623c46525a6
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi
@@ -0,0 +1,54 @@
+/*
+ * DTS file for AMD Seattle Clocks
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ */
+        adl3clk_100mhz: clk100mhz_0 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <100000000>;
+                clock-output-names = "adl3clk_100mhz";
+        };
+        ccpclk_375mhz: clk375mhz {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <375000000>;
+                clock-output-names = "ccpclk_375mhz";
+        };
+        sataclk_333mhz: clk333mhz {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <333000000>;
+                clock-output-names = "sataclk_333mhz";
+        };
+        pcieclk_500mhz: clk500mhz_0 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <500000000>;
+                clock-output-names = "pcieclk_500mhz";
+        };
+        dmaclk_500mhz: clk500mhz_1 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <500000000>;
+                clock-output-names = "dmaclk_500mhz";
+        };
+        miscclk_250mhz: clk250mhz_4 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <250000000>;
+                clock-output-names = "miscclk_250mhz";
+        };
+        uartspiclk_100mhz: clk100mhz_1 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <100000000>;
+                clock-output-names = "uartspiclk_100mhz";
+        };
diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
new file mode 100644
index 000000000000..2874d92881fd
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
@@ -0,0 +1,172 @@
+/*
+ * DTS file for AMD Seattle SoC
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ */
+/ {
+        compatible = "amd,seattle";
+        interrupt-parent = <&gic0>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+        gic0: interrupt-controller@e1101000 {
+                compatible = "arm,gic-400", "arm,cortex-a15-gic";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                #address-cells = <2>;
+                #size-cells = <2>;
+                reg = <0x0 0xe1110000 0 0x1000>,
+                      <0x0 0xe112f000 0 0x2000>,
+                      <0x0 0xe1140000 0 0x10000>,
+                      <0x0 0xe1160000 0 0x10000>;
+                interrupts = <1 9 0xf04>;
+                ranges = <0 0 0 0xe1100000 0 0x100000>;
+                v2m0: v2m@e0080000 {
+                        compatible = "arm,gic-v2m-frame";
+                        msi-controller;
+                        reg = <0x0 0x00080000 0 0x1000>;
+                };
+        };
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupts = <1 13 0xff04>,
+                             <1 14 0xff04>,
+                             <1 11 0xff04>,
+                             <1 10 0xff04>;
+        };
+        pmu {
+                compatible = "arm,armv8-pmuv3";
+                interrupts = <0 7 4>,
+                             <0 8 4>,
+                             <0 9 4>,
+                             <0 10 4>,
+                             <0 11 4>,
+                             <0 12 4>,
+                             <0 13 4>,
+                             <0 14 4>;
+        };
+        smb0: smb {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+                /* DDR range is 40-bit addressing */
+                dma-ranges = <0x80 0x0 0x80 0x0 0x7f 0xffffffff>;
+                /include/ "amd-seattle-clks.dtsi"
+                sata0: sata@e0300000 {
+                        compatible = "snps,dwc-ahci";
+                        reg = <0 0xe0300000 0 0x800>;
+                        interrupts = <0 355 4>;
+                        clocks = <&sataclk_333mhz>;
+                        dma-coherent;
+                };
+                i2c0: i2c@e1000000 {
+                        status = "disabled";
+                        compatible = "snps,designware-i2c";
+                        reg = <0 0xe1000000 0 0x1000>;
+                        interrupts = <0 357 4>;
+                        clocks = <&uartspiclk_100mhz>;
+                };
+                serial0: serial@e1010000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0 0xe1010000 0 0x1000>;
+                        interrupts = <0 328 4>;
+                        clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>;
+                        clock-names = "uartclk", "apb_pclk";
+                };
+                spi0: ssp@e1020000 {
+                        status = "disabled";
+                        compatible = "arm,pl022", "arm,primecell";
+                        #gpio-cells = <2>;
+                        reg = <0 0xe1020000 0 0x1000>;
+                        spi-controller;
+                        interrupts = <0 330 4>;
+                        clocks = <&uartspiclk_100mhz>;
+                        clock-names = "apb_pclk";
+                };
+                spi1: ssp@e1030000 {
+                        status = "disabled";
+                        compatible = "arm,pl022", "arm,primecell";
+                        #gpio-cells = <2>;
+                        reg = <0 0xe1030000 0 0x1000>;
+                        spi-controller;
+                        interrupts = <0 329 4>;
+                        clocks = <&uartspiclk_100mhz>;
+                        clock-names = "apb_pclk";
+                        num-cs = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+                gpio0: gpio@e1040000 {
+                        status = "disabled";
+                        compatible = "arm,pl061", "arm,primecell";
+                        #gpio-cells = <2>;
+                        reg = <0 0xe1040000 0 0x1000>;
+                        gpio-controller;
+                        interrupts = <0 359 4>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&uartspiclk_100mhz>;
+                        clock-names = "apb_pclk";
+                };
+                gpio1: gpio@e1050000 {
+                        status = "disabled";
+                        compatible = "arm,pl061", "arm,primecell";
+                        #gpio-cells = <2>;
+                        reg = <0 0xe1050000 0 0x1000>;
+                        gpio-controller;
+                        interrupts = <0 358 4>;
+                        clocks = <&uartspiclk_100mhz>;
+                        clock-names = "apb_pclk";
+                };
+                ccp0: ccp@e0100000 {
+                        status = "disabled";
+                        compatible = "amd,ccp-seattle-v1a";
+                        reg = <0 0xe0100000 0 0x10000>;
+                        interrupts = <0 3 4>;
+                        dma-coherent;
+                };
+                pcie0: pcie@f0000000 {
+                        compatible = "pci-host-ecam-generic";
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        #interrupt-cells = <1>;
+                        device_type = "pci";
+                        bus-range = <0 0x7f>;
+                        msi-parent = <&v2m0>;
+                        reg = <0 0xf0000000 0 0x10000000>;
+                        interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                        interrupt-map =
+                                <0x1000 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>,
+                                <0x1000 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>,
+                                <0x1000 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>,
+                                <0x1000 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>;
+                        dma-coherent;
+                        dma-ranges = <0x43000000 0x80 0x0 0x80 0x0 0x7f 0xffffffff>;
+                        ranges =
+                                /* I/O Memory (size=64K) */
+                                <0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>,
+                                /* 32-bit MMIO (size=2G) */
+                                <0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>,
+                                /* 64-bit MMIO (size= 124G) */
+                                <0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>;
+                };
+        };
+};
diff --git a/arch/arm64/boot/dts/apm/Makefile b/arch/arm64/boot/dts/apm/Makefile
new file mode 100644
index 000000000000..a2afabbc1717
--- /dev/null
+++ b/arch/arm64/boot/dts/apm/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
+always          := $(dtb-y)
+subdir-y        := $(dts-dirs)
+clean-files     := *.dtb
diff --git a/arch/arm64/boot/dts/apm-mustang.dts b/arch/arm64/boot/dts/apm/apm-mustang.dts
index 2e25de0800b9..2e25de0800b9 100644
--- a/arch/arm64/boot/dts/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm/apm-mustang.dts
diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index f1ad9c2ab2e9..f1ad9c2ab2e9 100644
--- a/arch/arm64/boot/dts/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile
new file mode 100644
index 000000000000..301a0dada1fe
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/Makefile
@@ -0,0 +1,7 @@
+dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
+always          := $(dtb-y)
+subdir-y        := $(dts-dirs)
+clean-files     := *.dtb
diff --git a/arch/arm64/boot/dts/foundation-v8.dts b/arch/arm64/boot/dts/arm/foundation-v8.dts
index 4a060906809d..27f32962e55c 100644
--- a/arch/arm64/boot/dts/foundation-v8.dts
+++ b/arch/arm64/boot/dts/arm/foundation-v8.dts
@@ -78,10 +78,10 @@
        timer {
                compatible = "arm,armv8-timer";
-                interrupts = <1 13 0xff01>,
+                interrupts = <1 13 0xf08>,
-                             <1 14 0xff01>,
+                             <1 14 0xf08>,
-                             <1 11 0xff01>,
+                             <1 11 0xf08>,
-                             <1 10 0xff01>;
+                             <1 10 0xf08>;
                clock-frequency = <100000000>;
        };
diff --git a/arch/arm64/boot/dts/arm/juno-clocks.dtsi b/arch/arm64/boot/dts/arm/juno-clocks.dtsi
new file mode 100644
index 000000000000..ea2b5666a16f
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/juno-clocks.dtsi
@@ -0,0 +1,44 @@
+/*
+ * ARM Juno Platform clocks
+ *
+ * Copyright (c) 2013-2014 ARM Ltd
+ *
+ * This file is licensed under a dual GPLv2 or BSD license.
+ *
+ */
+        /* SoC fixed clocks */
+        soc_uartclk: refclk72738khz {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <7273800>;
+                clock-output-names = "juno:uartclk";
+        };
+        soc_usb48mhz: clk48mhz {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <48000000>;
+                clock-output-names = "clk48mhz";
+        };
+        soc_smc50mhz: clk50mhz {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <50000000>;
+                clock-output-names = "smc_clk";
+        };
+        soc_refclk100mhz: refclk100mhz {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <100000000>;
+                clock-output-names = "apb_pclk";
+        };
+        soc_faxiclk: refclk533mhz {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <533000000>;
+                clock-output-names = "faxi_clk";
+        };
diff --git a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi
new file mode 100644
index 000000000000..c138b95a8356
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi
@@ -0,0 +1,129 @@
+/*
+ * ARM Juno Platform motherboard peripherals
+ *
+ * Copyright (c) 2013-2014 ARM Ltd
+ *
+ * This file is licensed under a dual GPLv2 or BSD license.
+ *
+ */
+                mb_clk24mhz: clk24mhz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <24000000>;
+                        clock-output-names = "juno_mb:clk24mhz";
+                };
+                mb_clk25mhz: clk25mhz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <25000000>;
+                        clock-output-names = "juno_mb:clk25mhz";
+                };
+                motherboard {
+                        compatible = "arm,vexpress,v2p-p1", "simple-bus";
+                        #address-cells = <2>;  /* SMB chipselect number and offset */
+                        #size-cells = <1>;
+                        #interrupt-cells = <1>;
+                        ranges;
+                        model = "V2M-Juno";
+                        arm,hbi = <0x252>;
+                        arm,vexpress,site = <0>;
+                        arm,v2m-memory-map = "rs1";
+                        mb_fixed_3v3: fixedregulator@0 {
+                                compatible = "regulator-fixed";
+                                regulator-name = "MCC_SB_3V3";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        ethernet@2,00000000 {
+                                compatible = "smsc,lan9118", "smsc,lan9115";
+                                reg = <2 0x00000000 0x10000>;
+                                interrupts = <3>;
+                                phy-mode = "mii";
+                                reg-io-width = <4>;
+                                smsc,irq-active-high;
+                                smsc,irq-push-pull;
+                                clocks = <&mb_clk25mhz>;
+                                vdd33a-supply = <&mb_fixed_3v3>;
+                                vddvario-supply = <&mb_fixed_3v3>;
+                        };
+                        usb@5,00000000 {
+                                compatible = "nxp,usb-isp1763";
+                                reg = <5 0x00000000 0x20000>;
+                                bus-width = <16>;
+                                interrupts = <4>;
+                        };
+                        iofpga@3,00000000 {
+                                compatible = "arm,amba-bus", "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 3 0 0x200000>;
+                                mmci@050000 {
+                                        compatible = "arm,pl180", "arm,primecell";
+                                        reg = <0x050000 0x1000>;
+                                        interrupts = <5>;
+                                        /* cd-gpios = <&v2m_mmc_gpios 0 0>;
+                                        wp-gpios = <&v2m_mmc_gpios 1 0>; */
+                                        max-frequency = <12000000>;
+                                        vmmc-supply = <&mb_fixed_3v3>;
+                                        clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
+                                        clock-names = "mclk", "apb_pclk";
+                                };
+                                kmi@060000 {
+                                        compatible = "arm,pl050", "arm,primecell";
+                                        reg = <0x060000 0x1000>;
+                                        interrupts = <8>;
+                                        clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
+                                        clock-names = "KMIREFCLK", "apb_pclk";
+                                };
+                                kmi@070000 {
+                                        compatible = "arm,pl050", "arm,primecell";
+                                        reg = <0x070000 0x1000>;
+                                        interrupts = <8>;
+                                        clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
+                                        clock-names = "KMIREFCLK", "apb_pclk";
+                                };
+                                wdt@0f0000 {
+                                        compatible = "arm,sp805", "arm,primecell";
+                                        reg = <0x0f0000 0x10000>;
+                                        interrupts = <7>;
+                                        clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
+                                        clock-names = "wdogclk", "apb_pclk";
+                                };
+                                v2m_timer01: timer@110000 {
+                                        compatible = "arm,sp804", "arm,primecell";
+                                        reg = <0x110000 0x10000>;
+                                        interrupts = <9>;
+                                        clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
+                                        clock-names = "timclken1", "apb_pclk";
+                                };
+                                v2m_timer23: timer@120000 {
+                                        compatible = "arm,sp804", "arm,primecell";
+                                        reg = <0x120000 0x10000>;
+                                        interrupts = <9>;
+                                        clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
+                                        clock-names = "timclken1", "apb_pclk";
+                                };
+                                rtc@170000 {
+                                        compatible = "arm,pl031", "arm,primecell";
+                                        reg = <0x170000 0x10000>;
+                                        interrupts = <0>;
+                                        clocks = <&soc_smc50mhz>;
+                                        clock-names = "apb_pclk";
+                                };
+                        };
+                };
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
new file mode 100644
index 000000000000..cb3073e4e7a8
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -0,0 +1,218 @@
+/*
+ * ARM Ltd. Juno Platform
+ *
+ * Copyright (c) 2013-2014 ARM Ltd.
+ *
+ * This file is licensed under a dual GPLv2 or BSD license.
+ */
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+/ {
+        model = "ARM Juno development board (r0)";
+        compatible = "arm,juno", "arm,vexpress";
+        interrupt-parent = <&gic>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+        aliases {
+                serial0 = &soc_uart0;
+        };
+        chosen {
+                stdout-path = &soc_uart0;
+        };
+        psci {
+                compatible = "arm,psci-0.2";
+                method = "smc";
+        };
+        cpus {
+                #address-cells = <2>;
+                #size-cells = <0>;
+                A57_0: cpu@0 {
+                        compatible = "arm,cortex-a57","arm,armv8";
+                        reg = <0x0 0x0>;
+                        device_type = "cpu";
+                        enable-method = "psci";
+                };
+                A57_1: cpu@1 {
+                        compatible = "arm,cortex-a57","arm,armv8";
+                        reg = <0x0 0x1>;
+                        device_type = "cpu";
+                        enable-method = "psci";
+                };
+                A53_0: cpu@100 {
+                        compatible = "arm,cortex-a53","arm,armv8";
+                        reg = <0x0 0x100>;
+                        device_type = "cpu";
+                        enable-method = "psci";
+                };
+                A53_1: cpu@101 {
+                        compatible = "arm,cortex-a53","arm,armv8";
+                        reg = <0x0 0x101>;
+                        device_type = "cpu";
+                        enable-method = "psci";
+                };
+                A53_2: cpu@102 {
+                        compatible = "arm,cortex-a53","arm,armv8";
+                        reg = <0x0 0x102>;
+                        device_type = "cpu";
+                        enable-method = "psci";
+                };
+                A53_3: cpu@103 {
+                        compatible = "arm,cortex-a53","arm,armv8";
+                        reg = <0x0 0x103>;
+                        device_type = "cpu";
+                        enable-method = "psci";
+                };
+        };
+        memory@80000000 {
+                device_type = "memory";
+                /* last 16MB of the first memory area is reserved for secure world use by firmware */
+                reg = <0x00000000 0x80000000 0x0 0x7f000000>,
+                      <0x00000008 0x80000000 0x1 0x80000000>;
+        };
+        gic: interrupt-controller@2c001000 {
+                compatible = "arm,gic-400", "arm,cortex-a15-gic";
+                reg = <0x0 0x2c010000 0 0x1000>,
+                      <0x0 0x2c02f000 0 0x2000>,
+                      <0x0 0x2c04f000 0 0x2000>,
+                      <0x0 0x2c06f000 0 0x2000>;
+                #address-cells = <0>;
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+        };
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+        };
+        pmu {
+                compatible = "arm,armv8-pmuv3";
+                interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
+        };
+        /include/ "juno-clocks.dtsi"
+        dma@7ff00000 {
+                compatible = "arm,pl330", "arm,primecell";
+                reg = <0x0 0x7ff00000 0 0x1000>;
+                #dma-cells = <1>;
+                #dma-channels = <8>;
+                #dma-requests = <32>;
+                interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&soc_faxiclk>;
+                clock-names = "apb_pclk";
+        };
+        soc_uart0: uart@7ff80000 {
+                compatible = "arm,pl011", "arm,primecell";
+                reg = <0x0 0x7ff80000 0x0 0x1000>;
+                interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
+                clock-names = "uartclk", "apb_pclk";
+        };
+        i2c@7ffa0000 {
+                compatible = "snps,designware-i2c";
+                reg = <0x0 0x7ffa0000 0x0 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+                clock-frequency = <400000>;
+                i2c-sda-hold-time-ns = <500>;
+                clocks = <&soc_smc50mhz>;
+                dvi0: dvi-transmitter@70 {
+                        compatible = "nxp,tda998x";
+                        reg = <0x70>;
+                };
+                dvi1: dvi-transmitter@71 {
+                        compatible = "nxp,tda998x";
+                        reg = <0x71>;
+                };
+        };
+        ohci@7ffb0000 {
+                compatible = "generic-ohci";
+                reg = <0x0 0x7ffb0000 0x0 0x10000>;
+                interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&soc_usb48mhz>;
+        };
+        ehci@7ffc0000 {
+                compatible = "generic-ehci";
+                reg = <0x0 0x7ffc0000 0x0 0x10000>;
+                interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&soc_usb48mhz>;
+        };
+        memory-controller@7ffd0000 {
+                compatible = "arm,pl354", "arm,primecell";
+                reg = <0 0x7ffd0000 0 0x1000>;
+                interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&soc_smc50mhz>;
+                clock-names = "apb_pclk";
+        };
+        smb {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges = <0 0 0 0x08000000 0x04000000>,
+                         <1 0 0 0x14000000 0x04000000>,
+                         <2 0 0 0x18000000 0x04000000>,
+                         <3 0 0 0x1c000000 0x04000000>,
+                         <4 0 0 0x0c000000 0x04000000>,
+                         <5 0 0 0x10000000 0x04000000>;
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 15>;
+                interrupt-map = <0 0  0 &gic 0  68 IRQ_TYPE_LEVEL_HIGH>,
+                                <0 0  1 &gic 0  69 IRQ_TYPE_LEVEL_HIGH>,
+                                <0 0  2 &gic 0  70 IRQ_TYPE_LEVEL_HIGH>,
+                                <0 0  3 &gic 0 160 IRQ_TYPE_LEVEL_HIGH>,
+                                <0 0  4 &gic 0 161 IRQ_TYPE_LEVEL_HIGH>,
+                                <0 0  5 &gic 0 162 IRQ_TYPE_LEVEL_HIGH>,
+                                <0 0  6 &gic 0 163 IRQ_TYPE_LEVEL_HIGH>,
+                                <0 0  7 &gic 0 164 IRQ_TYPE_LEVEL_HIGH>,
+                                <0 0  8 &gic 0 165 IRQ_TYPE_LEVEL_HIGH>,
+                                <0 0  9 &gic 0 166 IRQ_TYPE_LEVEL_HIGH>,
+                                <0 0 10 &gic 0 167 IRQ_TYPE_LEVEL_HIGH>,
+                                <0 0 11 &gic 0 168 IRQ_TYPE_LEVEL_HIGH>,
+                                <0 0 12 &gic 0 169 IRQ_TYPE_LEVEL_HIGH>;
+                /include/ "juno-motherboard.dtsi"
+        };
+};
diff --git a/arch/arm64/boot/dts/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
index 572005ea2217..efc59b3baf63 100644
--- a/arch/arm64/boot/dts/rtsm_ve-aemv8a.dts
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
@@ -81,10 +81,10 @@
        timer {
                compatible = "arm,armv8-timer";
-                interrupts = <1 13 0xff01>,
+                interrupts = <1 13 0xf08>,
-                             <1 14 0xff01>,
+                             <1 14 0xf08>,
-                             <1 11 0xff01>,
+                             <1 11 0xf08>,
-                             <1 10 0xff01>;
+                             <1 10 0xf08>;
                clock-frequency = <100000000>;
        };
diff --git a/arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
index c46cbb29f3c6..c46cbb29f3c6 100644
--- a/arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
diff --git a/arch/arm64/boot/dts/cavium/Makefile b/arch/arm64/boot/dts/cavium/Makefile
new file mode 100644
index 000000000000..e34f89ddabb2
--- /dev/null
+++ b/arch/arm64/boot/dts/cavium/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb
+always          := $(dtb-y)
+subdir-y        := $(dts-dirs)
+clean-files     := *.dtb
diff --git a/arch/arm64/boot/dts/thunder-88xx.dts b/arch/arm64/boot/dts/cavium/thunder-88xx.dts
index 800ba65991f7..800ba65991f7 100644
--- a/arch/arm64/boot/dts/thunder-88xx.dts
+++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dts
diff --git a/arch/arm64/boot/dts/thunder-88xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
index d8c0bdc51882..d8c0bdc51882 100644
--- a/arch/arm64/boot/dts/thunder-88xx.dtsi
+++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
diff --git a/arch/arm64/boot/dts/include/dt-bindings b/arch/arm64/boot/dts/include/dt-bindings
new file mode 120000
index 000000000000..08c00e4972fa
--- /dev/null
+++ b/arch/arm64/boot/dts/include/dt-bindings
@@ -0,0 +1 @@
+../../../../../include/dt-bindings
+\ No newline at end of file
diff --git a/arch/arm64/crypto/Kconfig b/arch/arm64/crypto/Kconfig
index 5562652c5316..a38b02ce5f9a 100644
--- a/arch/arm64/crypto/Kconfig
+++ b/arch/arm64/crypto/Kconfig
@@ -27,20 +27,19 @@ config CRYPTO_AES_ARM64_CE
        tristate "AES core cipher using ARMv8 Crypto Extensions"
        depends on ARM64 && KERNEL_MODE_NEON
        select CRYPTO_ALGAPI
-        select CRYPTO_AES
 config CRYPTO_AES_ARM64_CE_CCM
        tristate "AES in CCM mode using ARMv8 Crypto Extensions"
        depends on ARM64 && KERNEL_MODE_NEON
        select CRYPTO_ALGAPI
-        select CRYPTO_AES
+        select CRYPTO_AES_ARM64_CE
        select CRYPTO_AEAD
 config CRYPTO_AES_ARM64_CE_BLK
        tristate "AES in ECB/CBC/CTR/XTS modes using ARMv8 Crypto Extensions"
        depends on ARM64 && KERNEL_MODE_NEON
        select CRYPTO_BLKCIPHER
-        select CRYPTO_AES
+        select CRYPTO_AES_ARM64_CE
        select CRYPTO_ABLK_HELPER
 config CRYPTO_AES_ARM64_NEON_BLK
diff --git a/arch/arm64/crypto/aes-ce-ccm-glue.c b/arch/arm64/crypto/aes-ce-ccm-glue.c
index 9e6cdde9b43d..0ac73b838fa3 100644
--- a/arch/arm64/crypto/aes-ce-ccm-glue.c
+++ b/arch/arm64/crypto/aes-ce-ccm-glue.c
@@ -16,6 +16,8 @@
 #include <linux/crypto.h>
 #include <linux/module.h>
+#include "aes-ce-setkey.h"
 static int num_rounds(struct crypto_aes_ctx *ctx)
 {
        /*
@@ -48,7 +50,7 @@ static int ccm_setkey(struct crypto_aead *tfm, const u8 *in_key,
        struct crypto_aes_ctx *ctx = crypto_aead_ctx(tfm);
        int ret;
-        ret = crypto_aes_expand_key(ctx, in_key, key_len);
+        ret = ce_aes_expandkey(ctx, in_key, key_len);
        if (!ret)
                return 0;
diff --git a/arch/arm64/crypto/aes-ce-cipher.c b/arch/arm64/crypto/aes-ce-cipher.c
index 2075e1acae6b..ce47792a983d 100644
--- a/arch/arm64/crypto/aes-ce-cipher.c
+++ b/arch/arm64/crypto/aes-ce-cipher.c
@@ -14,6 +14,8 @@
 #include <linux/crypto.h>
 #include <linux/module.h>
+#include "aes-ce-setkey.h"
 MODULE_DESCRIPTION("Synchronous AES cipher using ARMv8 Crypto Extensions");
 MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
 MODULE_LICENSE("GPL v2");
@@ -124,6 +126,114 @@ static void aes_cipher_decrypt(struct crypto_tfm *tfm, u8 dst[], u8 const src[])
        kernel_neon_end();
 }
+/*
+ * aes_sub() - use the aese instruction to perform the AES sbox substitution
+ *             on each byte in 'input'
+ */
+static u32 aes_sub(u32 input)
+{
+        u32 ret;
+        __asm__("dup    v1.4s, %w[in]           ;"
+                "movi   v0.16b, #0              ;"
+                "aese   v0.16b, v1.16b          ;"
+                "umov   %w[out], v0.4s[0]       ;"
+        :       [out]   "=r"(ret)
+        :       [in]    "r"(input)
+        :               "v0","v1");
+        return ret;
+}
+int ce_aes_expandkey(struct crypto_aes_ctx *ctx, const u8 *in_key,
+                     unsigned int key_len)
+{
+        /*
+         * The AES key schedule round constants
+         */
+        static u8 const rcon[] = {
+                0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36,
+        };
+        u32 kwords = key_len / sizeof(u32);
+        struct aes_block *key_enc, *key_dec;
+        int i, j;
+        if (key_len != AES_KEYSIZE_128 &&
+            key_len != AES_KEYSIZE_192 &&
+            key_len != AES_KEYSIZE_256)
+                return -EINVAL;
+        memcpy(ctx->key_enc, in_key, key_len);
+        ctx->key_length = key_len;
+        kernel_neon_begin_partial(2);
+        for (i = 0; i < sizeof(rcon); i++) {
+                u32 *rki = ctx->key_enc + (i * kwords);
+                u32 *rko = rki + kwords;
+                rko[0] = ror32(aes_sub(rki[kwords - 1]), 8) ^ rcon[i] ^ rki[0];
+                rko[1] = rko[0] ^ rki[1];
+                rko[2] = rko[1] ^ rki[2];
+                rko[3] = rko[2] ^ rki[3];
+                if (key_len == AES_KEYSIZE_192) {
+                        if (i >= 7)
+                                break;
+                        rko[4] = rko[3] ^ rki[4];
+                        rko[5] = rko[4] ^ rki[5];
+                } else if (key_len == AES_KEYSIZE_256) {
+                        if (i >= 6)
+                                break;
+                        rko[4] = aes_sub(rko[3]) ^ rki[4];
+                        rko[5] = rko[4] ^ rki[5];
+                        rko[6] = rko[5] ^ rki[6];
+                        rko[7] = rko[6] ^ rki[7];
+                }
+        }
+        /*
+         * Generate the decryption keys for the Equivalent Inverse Cipher.
+         * This involves reversing the order of the round keys, and applying
+         * the Inverse Mix Columns transformation on all but the first and
+         * the last one.
+         */
+        key_enc = (struct aes_block *)ctx->key_enc;
+        key_dec = (struct aes_block *)ctx->key_dec;
+        j = num_rounds(ctx);
+        key_dec[0] = key_enc[j];
+        for (i = 1, j--; j > 0; i++, j--)
+                __asm__("ld1    {v0.16b}, %[in]         ;"
+                        "aesimc v1.16b, v0.16b          ;"
+                        "st1    {v1.16b}, %[out]        ;"
+                :       [out]   "=Q"(key_dec[i])
+                :       [in]    "Q"(key_enc[j])
+                :               "v0","v1");
+        key_dec[i] = key_enc[0];
+        kernel_neon_end();
+        return 0;
+}
+EXPORT_SYMBOL(ce_aes_expandkey);
+int ce_aes_setkey(struct crypto_tfm *tfm, const u8 *in_key,
+                  unsigned int key_len)
+{
+        struct crypto_aes_ctx *ctx = crypto_tfm_ctx(tfm);
+        int ret;
+        ret = ce_aes_expandkey(ctx, in_key, key_len);
+        if (!ret)
+                return 0;
+        tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
+        return -EINVAL;
+}
+EXPORT_SYMBOL(ce_aes_setkey);
 static struct crypto_alg aes_alg = {
        .cra_name               = "aes",
        .cra_driver_name        = "aes-ce",
@@ -135,7 +245,7 @@ static struct crypto_alg aes_alg = {
        .cra_cipher = {
                .cia_min_keysize        = AES_MIN_KEY_SIZE,
                .cia_max_keysize        = AES_MAX_KEY_SIZE,
-                .cia_setkey             = crypto_aes_set_key,
+                .cia_setkey             = ce_aes_setkey,
                .cia_encrypt            = aes_cipher_encrypt,
                .cia_decrypt            = aes_cipher_decrypt
        }
diff --git a/arch/arm64/crypto/aes-ce-setkey.h b/arch/arm64/crypto/aes-ce-setkey.h
new file mode 100644
index 000000000000..f08a6471d034
--- /dev/null
+++ b/arch/arm64/crypto/aes-ce-setkey.h
@@ -0,0 +1,5 @@
+int ce_aes_setkey(struct crypto_tfm *tfm, const u8 *in_key,
+                  unsigned int key_len);
+int ce_aes_expandkey(struct crypto_aes_ctx *ctx, const u8 *in_key,
+                     unsigned int key_len);
diff --git a/arch/arm64/crypto/aes-glue.c b/arch/arm64/crypto/aes-glue.c
index 79cd911ef88c..801aae32841f 100644
--- a/arch/arm64/crypto/aes-glue.c
+++ b/arch/arm64/crypto/aes-glue.c
@@ -16,9 +16,13 @@
 #include <linux/module.h>
 #include <linux/cpufeature.h>
+#include "aes-ce-setkey.h"
 #ifdef USE_V8_CRYPTO_EXTENSIONS
 #define MODE                    "ce"
 #define PRIO                    300
+#define aes_setkey              ce_aes_setkey
+#define aes_expandkey           ce_aes_expandkey
 #define aes_ecb_encrypt         ce_aes_ecb_encrypt
 #define aes_ecb_decrypt         ce_aes_ecb_decrypt
 #define aes_cbc_encrypt         ce_aes_cbc_encrypt
@@ -30,6 +34,8 @@ MODULE_DESCRIPTION("AES-ECB/CBC/CTR/XTS using ARMv8 Crypto Extensions");
 #else
 #define MODE                    "neon"
 #define PRIO                    200
+#define aes_setkey              crypto_aes_set_key
+#define aes_expandkey           crypto_aes_expand_key
 #define aes_ecb_encrypt         neon_aes_ecb_encrypt
 #define aes_ecb_decrypt         neon_aes_ecb_decrypt
 #define aes_cbc_encrypt         neon_aes_cbc_encrypt
@@ -79,10 +85,10 @@ static int xts_set_key(struct crypto_tfm *tfm, const u8 *in_key,
        struct crypto_aes_xts_ctx *ctx = crypto_tfm_ctx(tfm);
        int ret;
-        ret = crypto_aes_expand_key(&ctx->key1, in_key, key_len / 2);
+        ret = aes_expandkey(&ctx->key1, in_key, key_len / 2);
        if (!ret)
-                ret = crypto_aes_expand_key(&ctx->key2, &in_key[key_len / 2],
+                ret = aes_expandkey(&ctx->key2, &in_key[key_len / 2],
-                                            key_len / 2);
+                                    key_len / 2);
        if (!ret)
                return 0;
@@ -288,7 +294,7 @@ static struct crypto_alg aes_algs[] = { {
                .min_keysize    = AES_MIN_KEY_SIZE,
                .max_keysize    = AES_MAX_KEY_SIZE,
                .ivsize         = AES_BLOCK_SIZE,
-                .setkey         = crypto_aes_set_key,
+                .setkey         = aes_setkey,
                .encrypt        = ecb_encrypt,
                .decrypt        = ecb_decrypt,
        },
@@ -306,7 +312,7 @@ static struct crypto_alg aes_algs[] = { {
                .min_keysize    = AES_MIN_KEY_SIZE,
                .max_keysize    = AES_MAX_KEY_SIZE,
                .ivsize         = AES_BLOCK_SIZE,
-                .setkey         = crypto_aes_set_key,
+                .setkey         = aes_setkey,
                .encrypt        = cbc_encrypt,
                .decrypt        = cbc_decrypt,
        },
@@ -324,7 +330,7 @@ static struct crypto_alg aes_algs[] = { {
                .min_keysize    = AES_MIN_KEY_SIZE,
                .max_keysize    = AES_MAX_KEY_SIZE,
                .ivsize         = AES_BLOCK_SIZE,
-                .setkey         = crypto_aes_set_key,
+                .setkey         = aes_setkey,
                .encrypt        = ctr_encrypt,
                .decrypt        = ctr_encrypt,
        },
diff --git a/arch/arm64/include/asm/alternative-asm.h b/arch/arm64/include/asm/alternative-asm.h
new file mode 100644
index 000000000000..919a67855b63
--- /dev/null
+++ b/arch/arm64/include/asm/alternative-asm.h
@@ -0,0 +1,29 @@
+#ifndef __ASM_ALTERNATIVE_ASM_H
+#define __ASM_ALTERNATIVE_ASM_H
+#ifdef __ASSEMBLY__
+.macro altinstruction_entry orig_offset alt_offset feature orig_len alt_len
+        .word \orig_offset - .
+        .word \alt_offset - .
+        .hword \feature
+        .byte \orig_len
+        .byte \alt_len
+.endm
+.macro alternative_insn insn1 insn2 cap
+661:    \insn1
+662:    .pushsection .altinstructions, "a"
+        altinstruction_entry 661b, 663f, \cap, 662b-661b, 664f-663f
+        .popsection
+        .pushsection .altinstr_replacement, "ax"
+663:    \insn2
+664:    .popsection
+        .if ((664b-663b) != (662b-661b))
+                .error "Alternatives instruction length mismatch"
+        .endif
+.endm
+#endif  /*  __ASSEMBLY__  */
+#endif /* __ASM_ALTERNATIVE_ASM_H */
diff --git a/arch/arm64/include/asm/alternative.h b/arch/arm64/include/asm/alternative.h
new file mode 100644
index 000000000000..d261f01e2bae
--- /dev/null
+++ b/arch/arm64/include/asm/alternative.h
@@ -0,0 +1,44 @@
+#ifndef __ASM_ALTERNATIVE_H
+#define __ASM_ALTERNATIVE_H
+#include <linux/types.h>
+#include <linux/stddef.h>
+#include <linux/stringify.h>
+struct alt_instr {
+        s32 orig_offset;        /* offset to original instruction */
+        s32 alt_offset;         /* offset to replacement instruction */
+        u16 cpufeature;         /* cpufeature bit set for replacement */
+        u8  orig_len;           /* size of original instruction(s) */
+        u8  alt_len;            /* size of new instruction(s), <= orig_len */
+};
+void apply_alternatives_all(void);
+void apply_alternatives(void *start, size_t length);
+void free_alternatives_memory(void);
+#define ALTINSTR_ENTRY(feature)                                               \
+        " .word 661b - .\n"                             /* label           */ \
+        " .word 663f - .\n"                             /* new instruction */ \
+        " .hword " __stringify(feature) "\n"            /* feature bit     */ \
+        " .byte 662b-661b\n"                            /* source len      */ \
+        " .byte 664f-663f\n"                            /* replacement len */
+/* alternative assembly primitive: */
+#define ALTERNATIVE(oldinstr, newinstr, feature)                        \
+        "661:\n\t"                                                      \
+        oldinstr "\n"                                                   \
+        "662:\n"                                                        \
+        ".pushsection .altinstructions,\"a\"\n"                         \
+        ALTINSTR_ENTRY(feature)                                         \
+        ".popsection\n"                                                 \
+        ".pushsection .altinstr_replacement, \"a\"\n"                   \
+        "663:\n\t"                                                      \
+        newinstr "\n"                                                   \
+        "664:\n\t"                                                      \
+        ".popsection\n\t"                                               \
+        ".if ((664b-663b) != (662b-661b))\n\t"                          \
+        "       .error \"Alternatives instruction length mismatch\"\n\t"\
+        ".endif\n"
+#endif /* __ASM_ALTERNATIVE_H */
diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
index f19097134b02..b1fa4e614718 100644
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@ -104,6 +104,15 @@ static inline void arch_timer_set_cntkctl(u32 cntkctl)
        asm volatile("msr       cntkctl_el1, %0" : : "r" (cntkctl));
 }
+static inline u64 arch_counter_get_cntpct(void)
+{
+        /*
+         * AArch64 kernel and user space mandate the use of CNTVCT.
+         */
+        BUG();
+        return 0;
+}
 static inline u64 arch_counter_get_cntvct(void)
 {
        u64 cval;
diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
index 88cc05b5f3ac..bde449936e2f 100644
--- a/arch/arm64/include/asm/cache.h
+++ b/arch/arm64/include/asm/cache.h
@@ -32,6 +32,8 @@
 #ifndef __ASSEMBLY__
+#define __read_mostly __attribute__((__section__(".data..read_mostly")))
 static inline int cache_line_size(void)
 {
        u32 cwg = cache_type_cwg();
diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h
index 689b6379188c..7ae31a2cc6c0 100644
--- a/arch/arm64/include/asm/cacheflush.h
+++ b/arch/arm64/include/asm/cacheflush.h
@@ -73,7 +73,7 @@ extern void flush_cache_all(void);
 extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 extern void flush_icache_range(unsigned long start, unsigned long end);
 extern void __flush_dcache_area(void *addr, size_t len);
-extern void __flush_cache_user_range(unsigned long start, unsigned long end);
+extern long __flush_cache_user_range(unsigned long start, unsigned long end);
 static inline void flush_cache_mm(struct mm_struct *mm)
 {
diff --git a/arch/arm64/include/asm/cmpxchg.h b/arch/arm64/include/asm/cmpxchg.h
index ddb9d7830558..cb9593079f29 100644
--- a/arch/arm64/include/asm/cmpxchg.h
+++ b/arch/arm64/include/asm/cmpxchg.h
@@ -19,6 +19,7 @@
 #define __ASM_CMPXCHG_H
 #include <linux/bug.h>
+#include <linux/mmdebug.h>
 #include <asm/barrier.h>
@@ -152,6 +153,51 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
        return oldval;
 }
+#define system_has_cmpxchg_double()     1
+static inline int __cmpxchg_double(volatile void *ptr1, volatile void *ptr2,
+                unsigned long old1, unsigned long old2,
+                unsigned long new1, unsigned long new2, int size)
+{
+        unsigned long loop, lost;
+        switch (size) {
+        case 8:
+                VM_BUG_ON((unsigned long *)ptr2 - (unsigned long *)ptr1 != 1);
+                do {
+                        asm volatile("// __cmpxchg_double8\n"
+                        "       ldxp    %0, %1, %2\n"
+                        "       eor     %0, %0, %3\n"
+                        "       eor     %1, %1, %4\n"
+                        "       orr     %1, %0, %1\n"
+                        "       mov     %w0, #0\n"
+                        "       cbnz    %1, 1f\n"
+                        "       stxp    %w0, %5, %6, %2\n"
+                        "1:\n"
+                                : "=&r"(loop), "=&r"(lost), "+Q" (*(u64 *)ptr1)
+                                : "r" (old1), "r"(old2), "r"(new1), "r"(new2));
+                } while (loop);
+                break;
+        default:
+                BUILD_BUG();
+        }
+        return !lost;
+}
+static inline int __cmpxchg_double_mb(volatile void *ptr1, volatile void *ptr2,
+                        unsigned long old1, unsigned long old2,
+                        unsigned long new1, unsigned long new2, int size)
+{
+        int ret;
+        smp_mb();
+        ret = __cmpxchg_double(ptr1, ptr2, old1, old2, new1, new2, size);
+        smp_mb();
+        return ret;
+}
 static inline unsigned long __cmpxchg_mb(volatile void *ptr, unsigned long old,
                                         unsigned long new, int size)
 {
@@ -182,6 +228,33 @@ static inline unsigned long __cmpxchg_mb(volatile void *ptr, unsigned long old,
        __ret; \
 })
+#define cmpxchg_double(ptr1, ptr2, o1, o2, n1, n2) \
+({\
+        int __ret;\
+        __ret = __cmpxchg_double_mb((ptr1), (ptr2), (unsigned long)(o1), \
+                        (unsigned long)(o2), (unsigned long)(n1), \
+                        (unsigned long)(n2), sizeof(*(ptr1)));\
+        __ret; \
+})
+#define cmpxchg_double_local(ptr1, ptr2, o1, o2, n1, n2) \
+({\
+        int __ret;\
+        __ret = __cmpxchg_double((ptr1), (ptr2), (unsigned long)(o1), \
+                        (unsigned long)(o2), (unsigned long)(n1), \
+                        (unsigned long)(n2), sizeof(*(ptr1)));\
+        __ret; \
+})
+#define this_cpu_cmpxchg_1(ptr, o, n) cmpxchg_local(raw_cpu_ptr(&(ptr)), o, n)
+#define this_cpu_cmpxchg_2(ptr, o, n) cmpxchg_local(raw_cpu_ptr(&(ptr)), o, n)
+#define this_cpu_cmpxchg_4(ptr, o, n) cmpxchg_local(raw_cpu_ptr(&(ptr)), o, n)
+#define this_cpu_cmpxchg_8(ptr, o, n) cmpxchg_local(raw_cpu_ptr(&(ptr)), o, n)
+#define this_cpu_cmpxchg_double_8(ptr1, ptr2, o1, o2, n1, n2) \
+        cmpxchg_double_local(raw_cpu_ptr(&(ptr1)), raw_cpu_ptr(&(ptr2)), \
+                                o1, o2, n1, n2)
 #define cmpxchg64(ptr,o,n)              cmpxchg((ptr),(o),(n))
 #define cmpxchg64_local(ptr,o,n)        cmpxchg_local((ptr),(o),(n))
diff --git a/arch/arm64/include/asm/compat.h b/arch/arm64/include/asm/compat.h
index 56de5aadede2..3fb053fa6e98 100644
--- a/arch/arm64/include/asm/compat.h
+++ b/arch/arm64/include/asm/compat.h
@@ -205,6 +205,13 @@ typedef struct compat_siginfo {
                        compat_long_t _band;    /* POLL_IN, POLL_OUT, POLL_MSG */
                        int _fd;
                } _sigpoll;
+                /* SIGSYS */
+                struct {
+                        compat_uptr_t _call_addr; /* calling user insn */
+                        int _syscall;   /* triggering system call number */
+                        compat_uint_t _arch;    /* AUDIT_ARCH_* of syscall */
+                } _sigsys;
        } _sifields;
 } compat_siginfo_t;
diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
index 056443086019..ace70682499b 100644
--- a/arch/arm64/include/asm/cpu.h
+++ b/arch/arm64/include/asm/cpu.h
@@ -30,6 +30,8 @@ struct cpuinfo_arm64 {
        u32             reg_dczid;
        u32             reg_midr;
+        u64             reg_id_aa64dfr0;
+        u64             reg_id_aa64dfr1;
        u64             reg_id_aa64isar0;
        u64             reg_id_aa64isar1;
        u64             reg_id_aa64mmfr0;
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index cd4ac0516488..07547ccc1f2b 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -21,9 +21,38 @@
 #define MAX_CPU_FEATURES        (8 * sizeof(elf_hwcap))
 #define cpu_feature(x)          ilog2(HWCAP_ ## x)
+#define ARM64_WORKAROUND_CLEAN_CACHE            0
+#define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE    1
+#define ARM64_NCAPS                             2
+#ifndef __ASSEMBLY__
+extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
 static inline bool cpu_have_feature(unsigned int num)
 {
        return elf_hwcap & (1UL << num);
 }
+static inline bool cpus_have_cap(unsigned int num)
+{
+        if (num >= ARM64_NCAPS)
+                return false;
+        return test_bit(num, cpu_hwcaps);
+}
+static inline void cpus_set_cap(unsigned int num)
+{
+        if (num >= ARM64_NCAPS)
+                pr_warn("Attempt to set an illegal CPU capability (%d >= %d)\n",
+                        num, ARM64_NCAPS);
+        else
+                __set_bit(num, cpu_hwcaps);
+}
+void check_local_cpu_errata(void);
+#endif /* __ASSEMBLY__ */
 #endif
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 379d0b874328..8adb986a3086 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -57,6 +57,11 @@
 #define MIDR_IMPLEMENTOR(midr)  \
        (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
+#define MIDR_CPU_PART(imp, partnum) \
+        (((imp)                 << MIDR_IMPLEMENTOR_SHIFT) | \
+        (0xf                    << MIDR_ARCHITECTURE_SHIFT) | \
+        ((partnum)              << MIDR_PARTNUM_SHIFT))
 #define ARM_CPU_IMP_ARM         0x41
 #define ARM_CPU_IMP_APM         0x50
diff --git a/arch/arm64/include/asm/dmi.h b/arch/arm64/include/asm/dmi.h
new file mode 100644
index 000000000000..69d37d87b159
--- /dev/null
+++ b/arch/arm64/include/asm/dmi.h
@@ -0,0 +1,31 @@
+/*
+ * arch/arm64/include/asm/dmi.h
+ *
+ * Copyright (C) 2013 Linaro Limited.
+ * Written by: Yi Li (yi.li@linaro.org)
+ *
+ * based on arch/ia64/include/asm/dmi.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_DMI_H
+#define __ASM_DMI_H
+#include <linux/io.h>
+#include <linux/slab.h>
+/*
+ * According to section 2.3.6 of the UEFI spec, the firmware should not
+ * request a virtual mapping for configuration tables such as SMBIOS.
+ * This means we have to map them before use.
+ */
+#define dmi_early_remap(x, l)           ioremap_cache(x, l)
+#define dmi_early_unmap(x, l)           iounmap(x)
+#define dmi_remap(x, l)                 ioremap_cache(x, l)
+#define dmi_unmap(x)                    iounmap(x)
+#define dmi_alloc(l)                    kzalloc(l, GFP_KERNEL)
+#endif
diff --git a/arch/arm64/include/asm/fixmap.h b/arch/arm64/include/asm/fixmap.h
index 5f7bfe6df723..9ef6eca905ca 100644
--- a/arch/arm64/include/asm/fixmap.h
+++ b/arch/arm64/include/asm/fixmap.h
@@ -31,6 +31,7 @@
 *
 */
 enum fixed_addresses {
+        FIX_HOLE,
        FIX_EARLYCON_MEM_BASE,
        __end_of_permanent_fixed_addresses,
@@ -56,10 +57,11 @@ enum fixed_addresses {
 #define FIXMAP_PAGE_IO     __pgprot(PROT_DEVICE_nGnRE)
-extern void __early_set_fixmap(enum fixed_addresses idx,
+void __init early_fixmap_init(void);
-                               phys_addr_t phys, pgprot_t flags);
-#define __set_fixmap __early_set_fixmap
+#define __early_set_fixmap __set_fixmap
+extern void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot);
 #include <asm-generic/fixmap.h>
diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
index 024c46183c3c..0ad735166d9f 100644
--- a/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@ -30,6 +30,7 @@
 #define COMPAT_HWCAP_IDIVA      (1 << 17)
 #define COMPAT_HWCAP_IDIVT      (1 << 18)
 #define COMPAT_HWCAP_IDIV       (COMPAT_HWCAP_IDIVA|COMPAT_HWCAP_IDIVT)
+#define COMPAT_HWCAP_LPAE       (1 << 20)
 #define COMPAT_HWCAP_EVTSTRM    (1 << 21)
 #define COMPAT_HWCAP2_AES       (1 << 0)
diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
index 56a9e63b6c33..e2ff32a93b5c 100644
--- a/arch/arm64/include/asm/insn.h
+++ b/arch/arm64/include/asm/insn.h
@@ -354,6 +354,16 @@ bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn);
 int aarch64_insn_patch_text_nosync(void *addr, u32 insn);
 int aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt);
 int aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt);
+bool aarch32_insn_is_wide(u32 insn);
+#define A32_RN_OFFSET   16
+#define A32_RT_OFFSET   12
+#define A32_RT2_OFFSET   0
+u32 aarch32_insn_extract_reg_num(u32 insn, int offset);
+u32 aarch32_insn_mcr_extract_opc2(u32 insn);
+u32 aarch32_insn_mcr_extract_crm(u32 insn);
 #endif /* __ASSEMBLY__ */
 #endif  /* __ASM_INSN_H */
diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
index 79f1d519221f..949c406d4df4 100644
--- a/arch/arm64/include/asm/io.h
+++ b/arch/arm64/include/asm/io.h
@@ -28,57 +28,80 @@
 #include <asm/barrier.h>
 #include <asm/pgtable.h>
 #include <asm/early_ioremap.h>
+#include <asm/alternative.h>
+#include <asm/cpufeature.h>
 #include <xen/xen.h>
 /*
 * Generic IO read/write.  These perform native-endian accesses.
 */
+#define __raw_writeb __raw_writeb
 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
 {
        asm volatile("strb %w0, [%1]" : : "r" (val), "r" (addr));
 }
+#define __raw_writew __raw_writew
 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
 {
        asm volatile("strh %w0, [%1]" : : "r" (val), "r" (addr));
 }
+#define __raw_writel __raw_writel
 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
 {
        asm volatile("str %w0, [%1]" : : "r" (val), "r" (addr));
 }
+#define __raw_writeq __raw_writeq
 static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
 {
        asm volatile("str %0, [%1]" : : "r" (val), "r" (addr));
 }
+#define __raw_readb __raw_readb
 static inline u8 __raw_readb(const volatile void __iomem *addr)
 {
        u8 val;
-        asm volatile("ldrb %w0, [%1]" : "=r" (val) : "r" (addr));
+        asm volatile(ALTERNATIVE("ldrb %w0, [%1]",
+                                 "ldarb %w0, [%1]",
+                                 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
+                     : "=r" (val) : "r" (addr));
        return val;
 }
+#define __raw_readw __raw_readw
 static inline u16 __raw_readw(const volatile void __iomem *addr)
 {
        u16 val;
-        asm volatile("ldrh %w0, [%1]" : "=r" (val) : "r" (addr));
+        asm volatile(ALTERNATIVE("ldrh %w0, [%1]",
+                                 "ldarh %w0, [%1]",
+                                 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
+                     : "=r" (val) : "r" (addr));
        return val;
 }
+#define __raw_readl __raw_readl
 static inline u32 __raw_readl(const volatile void __iomem *addr)
 {
        u32 val;
-        asm volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr));
+        asm volatile(ALTERNATIVE("ldr %w0, [%1]",
+                                 "ldar %w0, [%1]",
+                                 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
+                     : "=r" (val) : "r" (addr));
        return val;
 }
+#define __raw_readq __raw_readq
 static inline u64 __raw_readq(const volatile void __iomem *addr)
 {
        u64 val;
-        asm volatile("ldr %0, [%1]" : "=r" (val) : "r" (addr));
+        asm volatile(ALTERNATIVE("ldr %0, [%1]",
+                                 "ldar %0, [%1]",
+                                 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
+                     : "=r" (val) : "r" (addr));
        return val;
 }
@@ -125,94 +148,6 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
 #define IO_SPACE_LIMIT          (SZ_32M - 1)
 #define PCI_IOBASE              ((void __iomem *)(MODULES_VADDR - SZ_32M))
-static inline u8 inb(unsigned long addr)
-{
-        return readb(addr + PCI_IOBASE);
-}
-static inline u16 inw(unsigned long addr)
-{
-        return readw(addr + PCI_IOBASE);
-}
-static inline u32 inl(unsigned long addr)
-{
-        return readl(addr + PCI_IOBASE);
-}
-static inline void outb(u8 b, unsigned long addr)
-{
-        writeb(b, addr + PCI_IOBASE);
-}
-static inline void outw(u16 b, unsigned long addr)
-{
-        writew(b, addr + PCI_IOBASE);
-}
-static inline void outl(u32 b, unsigned long addr)
-{
-        writel(b, addr + PCI_IOBASE);
-}
-#define inb_p(addr)     inb(addr)
-#define inw_p(addr)     inw(addr)
-#define inl_p(addr)     inl(addr)
-#define outb_p(x, addr) outb((x), (addr))
-#define outw_p(x, addr) outw((x), (addr))
-#define outl_p(x, addr) outl((x), (addr))
-static inline void insb(unsigned long addr, void *buffer, int count)
-{
-        u8 *buf = buffer;
-        while (count--)
-                *buf++ = __raw_readb(addr + PCI_IOBASE);
-}
-static inline void insw(unsigned long addr, void *buffer, int count)
-{
-        u16 *buf = buffer;
-        while (count--)
-                *buf++ = __raw_readw(addr + PCI_IOBASE);
-}
-static inline void insl(unsigned long addr, void *buffer, int count)
-{
-        u32 *buf = buffer;
-        while (count--)
-                *buf++ = __raw_readl(addr + PCI_IOBASE);
-}
-static inline void outsb(unsigned long addr, const void *buffer, int count)
-{
-        const u8 *buf = buffer;
-        while (count--)
-                __raw_writeb(*buf++, addr + PCI_IOBASE);
-}
-static inline void outsw(unsigned long addr, const void *buffer, int count)
-{
-        const u16 *buf = buffer;
-        while (count--)
-                __raw_writew(*buf++, addr + PCI_IOBASE);
-}
-static inline void outsl(unsigned long addr, const void *buffer, int count)
-{
-        const u32 *buf = buffer;
-        while (count--)
-                __raw_writel(*buf++, addr + PCI_IOBASE);
-}
-#define insb_p(port,to,len)     insb(port,to,len)
-#define insw_p(port,to,len)     insw(port,to,len)
-#define insl_p(port,to,len)     insl(port,to,len)
-#define outsb_p(port,from,len)  outsb(port,from,len)
-#define outsw_p(port,from,len)  outsw(port,from,len)
-#define outsl_p(port,from,len)  outsl(port,from,len)
 /*
 * String version of I/O memory access operations.
 */
@@ -236,18 +171,14 @@ extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size);
 #define ioremap_wc(addr, size)          __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
 #define iounmap                         __iounmap
-#define ARCH_HAS_IOREMAP_WC
-#include <asm-generic/iomap.h>
 /*
- * More restrictive address range checking than the default implementation
+ * io{read,write}{16,32}be() macros
- * (PHYS_OFFSET and PHYS_MASK taken into account).
 */
-#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
+#define ioread16be(p)           ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
-extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
+#define ioread32be(p)           ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
-extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
-extern int devmem_is_allowed(unsigned long pfn);
+#define iowrite16be(v,p)        ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
+#define iowrite32be(v,p)        ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
 /*
 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
@@ -260,6 +191,18 @@ extern int devmem_is_allowed(unsigned long pfn);
 */
 #define xlate_dev_kmem_ptr(p)   p
+#include <asm-generic/io.h>
+/*
+ * More restrictive address range checking than the default implementation
+ * (PHYS_OFFSET and PHYS_MASK taken into account).
+ */
+#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
+extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
+extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
+extern int devmem_is_allowed(unsigned long pfn);
 struct bio_vec;
 extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
                                      const struct bio_vec *vec2);
diff --git a/arch/arm64/include/asm/irq.h b/arch/arm64/include/asm/irq.h
index e1f7ecdde11f..94c53674a31d 100644
--- a/arch/arm64/include/asm/irq.h
+++ b/arch/arm64/include/asm/irq.h
@@ -3,7 +3,8 @@
 #include <asm-generic/irq.h>
-extern void (*handle_arch_irq)(struct pt_regs *);
+struct pt_regs;
 extern void migrate_irqs(void);
 extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index 7fd3e27e3ccc..8afb863f5a9e 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -18,6 +18,7 @@
 #ifndef __ARM64_KVM_ARM_H__
 #define __ARM64_KVM_ARM_H__
+#include <asm/memory.h>
 #include <asm/types.h>
 /* Hyp Configuration Register (HCR) bits */
@@ -160,9 +161,9 @@
 #endif
 #define VTTBR_BADDR_SHIFT (VTTBR_X - 1)
-#define VTTBR_BADDR_MASK  (((1LLU << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT)
+#define VTTBR_BADDR_MASK  (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT)
-#define VTTBR_VMID_SHIFT  (48LLU)
+#define VTTBR_VMID_SHIFT  (UL(48))
-#define VTTBR_VMID_MASK   (0xffLLU << VTTBR_VMID_SHIFT)
+#define VTTBR_VMID_MASK   (UL(0xFF) << VTTBR_VMID_SHIFT)
 /* Hyp System Trap Register */
 #define HSTR_EL2_TTEE   (1 << 16)
@@ -185,13 +186,13 @@
 /* Exception Syndrome Register (ESR) bits */
 #define ESR_EL2_EC_SHIFT        (26)
-#define ESR_EL2_EC              (0x3fU << ESR_EL2_EC_SHIFT)
+#define ESR_EL2_EC              (UL(0x3f) << ESR_EL2_EC_SHIFT)
-#define ESR_EL2_IL              (1U << 25)
+#define ESR_EL2_IL              (UL(1) << 25)
 #define ESR_EL2_ISS             (ESR_EL2_IL - 1)
 #define ESR_EL2_ISV_SHIFT       (24)
-#define ESR_EL2_ISV             (1U << ESR_EL2_ISV_SHIFT)
+#define ESR_EL2_ISV             (UL(1) << ESR_EL2_ISV_SHIFT)
 #define ESR_EL2_SAS_SHIFT       (22)
-#define ESR_EL2_SAS             (3U << ESR_EL2_SAS_SHIFT)
+#define ESR_EL2_SAS             (UL(3) << ESR_EL2_SAS_SHIFT)
 #define ESR_EL2_SSE             (1 << 21)
 #define ESR_EL2_SRT_SHIFT       (16)
 #define ESR_EL2_SRT_MASK        (0x1f << ESR_EL2_SRT_SHIFT)
@@ -205,16 +206,16 @@
 #define ESR_EL2_FSC_TYPE        (0x3c)
 #define ESR_EL2_CV_SHIFT        (24)
-#define ESR_EL2_CV              (1U << ESR_EL2_CV_SHIFT)
+#define ESR_EL2_CV              (UL(1) << ESR_EL2_CV_SHIFT)
 #define ESR_EL2_COND_SHIFT      (20)
-#define ESR_EL2_COND            (0xfU << ESR_EL2_COND_SHIFT)
+#define ESR_EL2_COND            (UL(0xf) << ESR_EL2_COND_SHIFT)
 #define FSC_FAULT       (0x04)
 #define FSC_PERM        (0x0c)
 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
-#define HPFAR_MASK      (~0xFUL)
+#define HPFAR_MASK      (~UL(0xf))
 #define ESR_EL2_EC_UNKNOWN      (0x00)
 #define ESR_EL2_EC_WFI          (0x01)
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index a62cd077457b..6486b2bfd562 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -120,11 +120,13 @@ extern phys_addr_t		memstart_addr;
 * translation for translating DMA addresses.  Use the driver
 * DMA support - see dma-mapping.h.
 */
+#define virt_to_phys virt_to_phys
 static inline phys_addr_t virt_to_phys(const volatile void *x)
 {
        return __virt_to_phys((unsigned long)(x));
 }
+#define phys_to_virt phys_to_virt
 static inline void *phys_to_virt(phys_addr_t x)
 {
        return (void *)(__phys_to_virt(x));
diff --git a/arch/arm64/include/asm/opcodes.h b/arch/arm64/include/asm/opcodes.h
new file mode 100644
index 000000000000..4e603ea36ad3
--- /dev/null
+++ b/arch/arm64/include/asm/opcodes.h
@@ -0,0 +1 @@
+#include <../../arm/include/asm/opcodes.h>
diff --git a/arch/arm64/include/asm/percpu.h b/arch/arm64/include/asm/percpu.h
index 5279e5733386..09da25bc596f 100644
--- a/arch/arm64/include/asm/percpu.h
+++ b/arch/arm64/include/asm/percpu.h
@@ -44,6 +44,221 @@ static inline unsigned long __my_cpu_offset(void)
 #endif /* CONFIG_SMP */
+#define PERCPU_OP(op, asm_op)                                           \
+static inline unsigned long __percpu_##op(void *ptr,                    \
+                        unsigned long val, int size)                    \
+{                                                                       \
+        unsigned long loop, ret;                                        \
+                                                                        \
+        switch (size) {                                                 \
+        case 1:                                                         \
+                do {                                                    \
+                        asm ("//__per_cpu_" #op "_1\n"                  \
+                        "ldxrb    %w[ret], %[ptr]\n"                    \
+                        #asm_op " %w[ret], %w[ret], %w[val]\n"          \
+                        "stxrb    %w[loop], %w[ret], %[ptr]\n"          \
+                        : [loop] "=&r" (loop), [ret] "=&r" (ret),       \
+                          [ptr] "+Q"(*(u8 *)ptr)                        \
+                        : [val] "Ir" (val));                            \
+                } while (loop);                                         \
+                break;                                                  \
+        case 2:                                                         \
+                do {                                                    \
+                        asm ("//__per_cpu_" #op "_2\n"                  \
+                        "ldxrh    %w[ret], %[ptr]\n"                    \
+                        #asm_op " %w[ret], %w[ret], %w[val]\n"          \
+                        "stxrh    %w[loop], %w[ret], %[ptr]\n"          \
+                        : [loop] "=&r" (loop), [ret] "=&r" (ret),       \
+                          [ptr]  "+Q"(*(u16 *)ptr)                      \
+                        : [val] "Ir" (val));                            \
+                } while (loop);                                         \
+                break;                                                  \
+        case 4:                                                         \
+                do {                                                    \
+                        asm ("//__per_cpu_" #op "_4\n"                  \
+                        "ldxr     %w[ret], %[ptr]\n"                    \
+                        #asm_op " %w[ret], %w[ret], %w[val]\n"          \
+                        "stxr     %w[loop], %w[ret], %[ptr]\n"          \
+                        : [loop] "=&r" (loop), [ret] "=&r" (ret),       \
+                          [ptr] "+Q"(*(u32 *)ptr)                       \
+                        : [val] "Ir" (val));                            \
+                } while (loop);                                         \
+                break;                                                  \
+        case 8:                                                         \
+                do {                                                    \
+                        asm ("//__per_cpu_" #op "_8\n"                  \
+                        "ldxr     %[ret], %[ptr]\n"                     \
+                        #asm_op " %[ret], %[ret], %[val]\n"             \
+                        "stxr     %w[loop], %[ret], %[ptr]\n"           \
+                        : [loop] "=&r" (loop), [ret] "=&r" (ret),       \
+                          [ptr] "+Q"(*(u64 *)ptr)                       \
+                        : [val] "Ir" (val));                            \
+                } while (loop);                                         \
+                break;                                                  \
+        default:                                                        \
+                BUILD_BUG();                                            \
+        }                                                               \
+                                                                        \
+        return ret;                                                     \
+}
+PERCPU_OP(add, add)
+PERCPU_OP(and, and)
+PERCPU_OP(or, orr)
+#undef PERCPU_OP
+static inline unsigned long __percpu_read(void *ptr, int size)
+{
+        unsigned long ret;
+        switch (size) {
+        case 1:
+                ret = ACCESS_ONCE(*(u8 *)ptr);
+                break;
+        case 2:
+                ret = ACCESS_ONCE(*(u16 *)ptr);
+                break;
+        case 4:
+                ret = ACCESS_ONCE(*(u32 *)ptr);
+                break;
+        case 8:
+                ret = ACCESS_ONCE(*(u64 *)ptr);
+                break;
+        default:
+                BUILD_BUG();
+        }
+        return ret;
+}
+static inline void __percpu_write(void *ptr, unsigned long val, int size)
+{
+        switch (size) {
+        case 1:
+                ACCESS_ONCE(*(u8 *)ptr) = (u8)val;
+                break;
+        case 2:
+                ACCESS_ONCE(*(u16 *)ptr) = (u16)val;
+                break;
+        case 4:
+                ACCESS_ONCE(*(u32 *)ptr) = (u32)val;
+                break;
+        case 8:
+                ACCESS_ONCE(*(u64 *)ptr) = (u64)val;
+                break;
+        default:
+                BUILD_BUG();
+        }
+}
+static inline unsigned long __percpu_xchg(void *ptr, unsigned long val,
+                                                int size)
+{
+        unsigned long ret, loop;
+        switch (size) {
+        case 1:
+                do {
+                        asm ("//__percpu_xchg_1\n"
+                        "ldxrb %w[ret], %[ptr]\n"
+                        "stxrb %w[loop], %w[val], %[ptr]\n"
+                        : [loop] "=&r"(loop), [ret] "=&r"(ret),
+                          [ptr] "+Q"(*(u8 *)ptr)
+                        : [val] "r" (val));
+                } while (loop);
+                break;
+        case 2:
+                do {
+                        asm ("//__percpu_xchg_2\n"
+                        "ldxrh %w[ret], %[ptr]\n"
+                        "stxrh %w[loop], %w[val], %[ptr]\n"
+                        : [loop] "=&r"(loop), [ret] "=&r"(ret),
+                          [ptr] "+Q"(*(u16 *)ptr)
+                        : [val] "r" (val));
+                } while (loop);
+                break;
+        case 4:
+                do {
+                        asm ("//__percpu_xchg_4\n"
+                        "ldxr %w[ret], %[ptr]\n"
+                        "stxr %w[loop], %w[val], %[ptr]\n"
+                        : [loop] "=&r"(loop), [ret] "=&r"(ret),
+                          [ptr] "+Q"(*(u32 *)ptr)
+                        : [val] "r" (val));
+                } while (loop);
+                break;
+        case 8:
+                do {
+                        asm ("//__percpu_xchg_8\n"
+                        "ldxr %[ret], %[ptr]\n"
+                        "stxr %w[loop], %[val], %[ptr]\n"
+                        : [loop] "=&r"(loop), [ret] "=&r"(ret),
+                          [ptr] "+Q"(*(u64 *)ptr)
+                        : [val] "r" (val));
+                } while (loop);
+                break;
+        default:
+                BUILD_BUG();
+        }
+        return ret;
+}
+#define _percpu_add(pcp, val) \
+        __percpu_add(raw_cpu_ptr(&(pcp)), val, sizeof(pcp))
+#define _percpu_add_return(pcp, val) (typeof(pcp)) (_percpu_add(pcp, val))
+#define _percpu_and(pcp, val) \
+        __percpu_and(raw_cpu_ptr(&(pcp)), val, sizeof(pcp))
+#define _percpu_or(pcp, val) \
+        __percpu_or(raw_cpu_ptr(&(pcp)), val, sizeof(pcp))
+#define _percpu_read(pcp) (typeof(pcp)) \
+        (__percpu_read(raw_cpu_ptr(&(pcp)), sizeof(pcp)))
+#define _percpu_write(pcp, val) \
+        __percpu_write(raw_cpu_ptr(&(pcp)), (unsigned long)(val), sizeof(pcp))
+#define _percpu_xchg(pcp, val) (typeof(pcp)) \
+        (__percpu_xchg(raw_cpu_ptr(&(pcp)), (unsigned long)(val), sizeof(pcp)))
+#define this_cpu_add_1(pcp, val) _percpu_add(pcp, val)
+#define this_cpu_add_2(pcp, val) _percpu_add(pcp, val)
+#define this_cpu_add_4(pcp, val) _percpu_add(pcp, val)
+#define this_cpu_add_8(pcp, val) _percpu_add(pcp, val)
+#define this_cpu_add_return_1(pcp, val) _percpu_add_return(pcp, val)
+#define this_cpu_add_return_2(pcp, val) _percpu_add_return(pcp, val)
+#define this_cpu_add_return_4(pcp, val) _percpu_add_return(pcp, val)
+#define this_cpu_add_return_8(pcp, val) _percpu_add_return(pcp, val)
+#define this_cpu_and_1(pcp, val) _percpu_and(pcp, val)
+#define this_cpu_and_2(pcp, val) _percpu_and(pcp, val)
+#define this_cpu_and_4(pcp, val) _percpu_and(pcp, val)
+#define this_cpu_and_8(pcp, val) _percpu_and(pcp, val)
+#define this_cpu_or_1(pcp, val) _percpu_or(pcp, val)
+#define this_cpu_or_2(pcp, val) _percpu_or(pcp, val)
+#define this_cpu_or_4(pcp, val) _percpu_or(pcp, val)
+#define this_cpu_or_8(pcp, val) _percpu_or(pcp, val)
+#define this_cpu_read_1(pcp) _percpu_read(pcp)
+#define this_cpu_read_2(pcp) _percpu_read(pcp)
+#define this_cpu_read_4(pcp) _percpu_read(pcp)
+#define this_cpu_read_8(pcp) _percpu_read(pcp)
+#define this_cpu_write_1(pcp, val) _percpu_write(pcp, val)
+#define this_cpu_write_2(pcp, val) _percpu_write(pcp, val)
+#define this_cpu_write_4(pcp, val) _percpu_write(pcp, val)
+#define this_cpu_write_8(pcp, val) _percpu_write(pcp, val)
+#define this_cpu_xchg_1(pcp, val) _percpu_xchg(pcp, val)
+#define this_cpu_xchg_2(pcp, val) _percpu_xchg(pcp, val)
+#define this_cpu_xchg_4(pcp, val) _percpu_xchg(pcp, val)
+#define this_cpu_xchg_8(pcp, val) _percpu_xchg(pcp, val)
 #include <asm-generic/percpu.h>
 #endif /* __ASM_PERCPU_H */
diff --git a/arch/arm64/include/asm/pgalloc.h b/arch/arm64/include/asm/pgalloc.h
index d5bed02073d6..e20df38a8ff3 100644
--- a/arch/arm64/include/asm/pgalloc.h
+++ b/arch/arm64/include/asm/pgalloc.h
@@ -26,11 +26,13 @@
 #define check_pgt_cache()               do { } while (0)
+#define PGALLOC_GFP     (GFP_KERNEL | __GFP_NOTRACK | __GFP_REPEAT | __GFP_ZERO)
 #if CONFIG_ARM64_PGTABLE_LEVELS > 2
 static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
 {
-        return (pmd_t *)get_zeroed_page(GFP_KERNEL | __GFP_REPEAT);
+        return (pmd_t *)__get_free_page(PGALLOC_GFP);
 }
 static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
@@ -50,7 +52,7 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
 static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
 {
-        return (pud_t *)get_zeroed_page(GFP_KERNEL | __GFP_REPEAT);
+        return (pud_t *)__get_free_page(PGALLOC_GFP);
 }
 static inline void pud_free(struct mm_struct *mm, pud_t *pud)
@@ -69,8 +71,6 @@ static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pud_t *pud)
 extern pgd_t *pgd_alloc(struct mm_struct *mm);
 extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
-#define PGALLOC_GFP     (GFP_KERNEL | __GFP_NOTRACK | __GFP_REPEAT | __GFP_ZERO)
 static inline pte_t *
 pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr)
 {
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 41a43bf26492..df22314f57cf 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -279,6 +279,7 @@ void pmdp_splitting_flush(struct vm_area_struct *vma, unsigned long address,
 #endif /* CONFIG_HAVE_RCU_TABLE_FREE */
 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
+#define pmd_dirty(pmd)          pte_dirty(pmd_pte(pmd))
 #define pmd_young(pmd)          pte_young(pmd_pte(pmd))
 #define pmd_wrprotect(pmd)      pte_pmd(pte_wrprotect(pmd_pte(pmd)))
 #define pmd_mksplitting(pmd)    pte_pmd(pte_mkspecial(pmd_pte(pmd)))
diff --git a/arch/arm64/include/asm/seccomp.h b/arch/arm64/include/asm/seccomp.h
new file mode 100644
index 000000000000..c76fac979629
--- /dev/null
+++ b/arch/arm64/include/asm/seccomp.h
@@ -0,0 +1,25 @@
+/*
+ * arch/arm64/include/asm/seccomp.h
+ *
+ * Copyright (C) 2014 Linaro Limited
+ * Author: AKASHI Takahiro <takahiro.akashi@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _ASM_SECCOMP_H
+#define _ASM_SECCOMP_H
+#include <asm/unistd.h>
+#ifdef CONFIG_COMPAT
+#define __NR_seccomp_read_32            __NR_compat_read
+#define __NR_seccomp_write_32           __NR_compat_write
+#define __NR_seccomp_exit_32            __NR_compat_exit
+#define __NR_seccomp_sigreturn_32       __NR_compat_rt_sigreturn
+#endif /* CONFIG_COMPAT */
+#include <asm-generic/seccomp.h>
+#endif /* _ASM_SECCOMP_H */
diff --git a/arch/arm64/include/asm/tlb.h b/arch/arm64/include/asm/tlb.h
index a82c0c5c8b52..c028fe37456f 100644
--- a/arch/arm64/include/asm/tlb.h
+++ b/arch/arm64/include/asm/tlb.h
@@ -19,10 +19,6 @@
 #ifndef __ASM_TLB_H
 #define __ASM_TLB_H
-#define  __tlb_remove_pmd_tlb_entry __tlb_remove_pmd_tlb_entry
-#include <asm-generic/tlb.h>
 #include <linux/pagemap.h>
 #include <linux/swap.h>
@@ -37,71 +33,22 @@ static inline void __tlb_remove_table(void *_table)
 #define tlb_remove_entry(tlb, entry)    tlb_remove_page(tlb, entry)
 #endif /* CONFIG_HAVE_RCU_TABLE_FREE */
-/*
+#include <asm-generic/tlb.h>
- * There's three ways the TLB shootdown code is used:
- *  1. Unmapping a range of vmas.  See zap_page_range(), unmap_region().
- *     tlb->fullmm = 0, and tlb_start_vma/tlb_end_vma will be called.
- *  2. Unmapping all vmas.  See exit_mmap().
- *     tlb->fullmm = 1, and tlb_start_vma/tlb_end_vma will be called.
- *     Page tables will be freed.
- *  3. Unmapping argument pages.  See shift_arg_pages().
- *     tlb->fullmm = 0, but tlb_start_vma/tlb_end_vma will not be called.
- */
 static inline void tlb_flush(struct mmu_gather *tlb)
 {
        if (tlb->fullmm) {
                flush_tlb_mm(tlb->mm);
-        } else if (tlb->end > 0) {
+        } else {
                struct vm_area_struct vma = { .vm_mm = tlb->mm, };
                flush_tlb_range(&vma, tlb->start, tlb->end);
-                tlb->start = TASK_SIZE;
-                tlb->end = 0;
-        }
-}
-static inline void tlb_add_flush(struct mmu_gather *tlb, unsigned long addr)
-{
-        if (!tlb->fullmm) {
-                tlb->start = min(tlb->start, addr);
-                tlb->end = max(tlb->end, addr + PAGE_SIZE);
-        }
-}
-/*
- * Memorize the range for the TLB flush.
- */
-static inline void __tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep,
-                                          unsigned long addr)
-{
-        tlb_add_flush(tlb, addr);
-}
-/*
- * In the case of tlb vma handling, we can optimise these away in the
- * case where we're doing a full MM flush.  When we're doing a munmap,
- * the vmas are adjusted to only cover the region to be torn down.
- */
-static inline void tlb_start_vma(struct mmu_gather *tlb,
-                                 struct vm_area_struct *vma)
-{
-        if (!tlb->fullmm) {
-                tlb->start = TASK_SIZE;
-                tlb->end = 0;
        }
 }
-static inline void tlb_end_vma(struct mmu_gather *tlb,
-                               struct vm_area_struct *vma)
-{
-        if (!tlb->fullmm)
-                tlb_flush(tlb);
-}
 static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
                                  unsigned long addr)
 {
        pgtable_page_dtor(pte);
-        tlb_add_flush(tlb, addr);
        tlb_remove_entry(tlb, pte);
 }
@@ -109,7 +56,6 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
 static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
                                  unsigned long addr)
 {
-        tlb_add_flush(tlb, addr);
        tlb_remove_entry(tlb, virt_to_page(pmdp));
 }
 #endif
@@ -118,15 +64,8 @@ static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
 static inline void __pud_free_tlb(struct mmu_gather *tlb, pud_t *pudp,
                                  unsigned long addr)
 {
-        tlb_add_flush(tlb, addr);
        tlb_remove_entry(tlb, virt_to_page(pudp));
 }
 #endif
-static inline void __tlb_remove_pmd_tlb_entry(struct mmu_gather *tlb, pmd_t *pmdp,
-                                                unsigned long address)
-{
-        tlb_add_flush(tlb, address);
-}
 #endif
diff --git a/arch/arm64/include/asm/traps.h b/arch/arm64/include/asm/traps.h
index 10ca8ff93cc2..232e4ba5d314 100644
--- a/arch/arm64/include/asm/traps.h
+++ b/arch/arm64/include/asm/traps.h
@@ -18,6 +18,22 @@
 #ifndef __ASM_TRAP_H
 #define __ASM_TRAP_H
+#include <linux/list.h>
+struct pt_regs;
+struct undef_hook {
+        struct list_head node;
+        u32 instr_mask;
+        u32 instr_val;
+        u64 pstate_mask;
+        u64 pstate_val;
+        int (*fn)(struct pt_regs *regs, u32 instr);
+};
+void register_undef_hook(struct undef_hook *hook);
+void unregister_undef_hook(struct undef_hook *hook);
 static inline int in_exception_text(unsigned long ptr)
 {
        extern char __exception_text_start[];
diff --git a/arch/arm64/include/asm/unistd.h b/arch/arm64/include/asm/unistd.h
index 6d2bf419431d..49c9aefd24a5 100644
--- a/arch/arm64/include/asm/unistd.h
+++ b/arch/arm64/include/asm/unistd.h
@@ -31,6 +31,9 @@
 * Compat syscall numbers used by the AArch64 kernel.
 */
 #define __NR_compat_restart_syscall     0
+#define __NR_compat_exit                1
+#define __NR_compat_read                3
+#define __NR_compat_write               4
 #define __NR_compat_sigreturn           119
 #define __NR_compat_rt_sigreturn        173
diff --git a/arch/arm64/include/asm/unistd32.h b/arch/arm64/include/asm/unistd32.h
index 9dfdac4a74a1..8893cebcea5b 100644
--- a/arch/arm64/include/asm/unistd32.h
+++ b/arch/arm64/include/asm/unistd32.h
@@ -787,7 +787,8 @@ __SYSCALL(__NR_sched_setattr, sys_sched_setattr)
 __SYSCALL(__NR_sched_getattr, sys_sched_getattr)
 #define __NR_renameat2 382
 __SYSCALL(__NR_renameat2, sys_renameat2)
-                        /* 383 for seccomp */
+#define __NR_seccomp 383
+__SYSCALL(__NR_seccomp, sys_seccomp)
 #define __NR_getrandom 384
 __SYSCALL(__NR_getrandom, sys_getrandom)
 #define __NR_memfd_create 385
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index 5bd029b43644..eaa77ed7766a 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -5,6 +5,7 @@
 CPPFLAGS_vmlinux.lds    := -DTEXT_OFFSET=$(TEXT_OFFSET)
 AFLAGS_head.o           := -DTEXT_OFFSET=$(TEXT_OFFSET)
 CFLAGS_efi-stub.o       := -DTEXT_OFFSET=$(TEXT_OFFSET)
+CFLAGS_armv8_deprecated.o := -I$(src)
 CFLAGS_REMOVE_ftrace.o = -pg
 CFLAGS_REMOVE_insn.o = -pg
@@ -15,10 +16,11 @@ arm64-obj-y		:= cputable.o debug-monitors.o entry.o irq.o fpsimd.o	\
                           entry-fpsimd.o process.o ptrace.o setup.o signal.o   \
                           sys.o stacktrace.o time.o traps.o io.o vdso.o        \
                           hyp-stub.o psci.o cpu_ops.o insn.o return_address.o  \
-                           cpuinfo.o
+                           cpuinfo.o cpu_errata.o alternative.o
 arm64-obj-$(CONFIG_COMPAT)              += sys32.o kuser32.o signal32.o         \
-                                           sys_compat.o
+                                           sys_compat.o                         \
+                                           ../../arm/kernel/opcodes.o
 arm64-obj-$(CONFIG_FUNCTION_TRACER)     += ftrace.o entry-ftrace.o
 arm64-obj-$(CONFIG_MODULES)             += arm64ksyms.o module.o
 arm64-obj-$(CONFIG_SMP)                 += smp.o smp_spin_table.o topology.o
@@ -31,6 +33,7 @@ arm64-obj-$(CONFIG_JUMP_LABEL)		+= jump_label.o
 arm64-obj-$(CONFIG_KGDB)                += kgdb.o
 arm64-obj-$(CONFIG_EFI)                 += efi.o efi-stub.o efi-entry.o
 arm64-obj-$(CONFIG_PCI)                 += pci.o
+arm64-obj-$(CONFIG_ARMV8_DEPRECATED)    += armv8_deprecated.o
 obj-y                                   += $(arm64-obj-y) vdso/
 obj-m                                   += $(arm64-obj-m)
diff --git a/arch/arm64/kernel/alternative.c b/arch/arm64/kernel/alternative.c
new file mode 100644
index 000000000000..ad7821d64a1d
--- /dev/null
+++ b/arch/arm64/kernel/alternative.c
@@ -0,0 +1,85 @@
+/*
+ * alternative runtime patching
+ * inspired by the x86 version
+ *
+ * Copyright (C) 2014 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#define pr_fmt(fmt) "alternatives: " fmt
+#include <linux/init.h>
+#include <linux/cpu.h>
+#include <asm/cacheflush.h>
+#include <asm/alternative.h>
+#include <asm/cpufeature.h>
+#include <linux/stop_machine.h>
+extern struct alt_instr __alt_instructions[], __alt_instructions_end[];
+struct alt_region {
+        struct alt_instr *begin;
+        struct alt_instr *end;
+};
+static int __apply_alternatives(void *alt_region)
+{
+        struct alt_instr *alt;
+        struct alt_region *region = alt_region;
+        u8 *origptr, *replptr;
+        for (alt = region->begin; alt < region->end; alt++) {
+                if (!cpus_have_cap(alt->cpufeature))
+                        continue;
+                BUG_ON(alt->alt_len > alt->orig_len);
+                pr_info_once("patching kernel code\n");
+                origptr = (u8 *)&alt->orig_offset + alt->orig_offset;
+                replptr = (u8 *)&alt->alt_offset + alt->alt_offset;
+                memcpy(origptr, replptr, alt->alt_len);
+                flush_icache_range((uintptr_t)origptr,
+                                   (uintptr_t)(origptr + alt->alt_len));
+        }
+        return 0;
+}
+void apply_alternatives_all(void)
+{
+        struct alt_region region = {
+                .begin  = __alt_instructions,
+                .end    = __alt_instructions_end,
+        };
+        /* better not try code patching on a live SMP system */
+        stop_machine(__apply_alternatives, &region, NULL);
+}
+void apply_alternatives(void *start, size_t length)
+{
+        struct alt_region region = {
+                .begin  = start,
+                .end    = start + length,
+        };
+        __apply_alternatives(&region);
+}
+void free_alternatives_memory(void)
+{
+        free_reserved_area(__alt_instructions, __alt_instructions_end,
+                           0, "alternatives");
+}
diff --git a/arch/arm64/kernel/armv8_deprecated.c b/arch/arm64/kernel/armv8_deprecated.c
new file mode 100644
index 000000000000..c363671d7509
--- /dev/null
+++ b/arch/arm64/kernel/armv8_deprecated.c
@@ -0,0 +1,553 @@
+/*
+ *  Copyright (C) 2014 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/cpu.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/perf_event.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/sysctl.h>
+#include <asm/insn.h>
+#include <asm/opcodes.h>
+#include <asm/system_misc.h>
+#include <asm/traps.h>
+#include <asm/uaccess.h>
+#define CREATE_TRACE_POINTS
+#include "trace-events-emulation.h"
+/*
+ * The runtime support for deprecated instruction support can be in one of
+ * following three states -
+ *
+ * 0 = undef
+ * 1 = emulate (software emulation)
+ * 2 = hw (supported in hardware)
+ */
+enum insn_emulation_mode {
+        INSN_UNDEF,
+        INSN_EMULATE,
+        INSN_HW,
+};
+enum legacy_insn_status {
+        INSN_DEPRECATED,
+        INSN_OBSOLETE,
+};
+struct insn_emulation_ops {
+        const char              *name;
+        enum legacy_insn_status status;
+        struct undef_hook       *hooks;
+        int                     (*set_hw_mode)(bool enable);
+};
+struct insn_emulation {
+        struct list_head node;
+        struct insn_emulation_ops *ops;
+        int current_mode;
+        int min;
+        int max;
+};
+static LIST_HEAD(insn_emulation);
+static int nr_insn_emulated;
+static DEFINE_RAW_SPINLOCK(insn_emulation_lock);
+static void register_emulation_hooks(struct insn_emulation_ops *ops)
+{
+        struct undef_hook *hook;
+        BUG_ON(!ops->hooks);
+        for (hook = ops->hooks; hook->instr_mask; hook++)
+                register_undef_hook(hook);
+        pr_notice("Registered %s emulation handler\n", ops->name);
+}
+static void remove_emulation_hooks(struct insn_emulation_ops *ops)
+{
+        struct undef_hook *hook;
+        BUG_ON(!ops->hooks);
+        for (hook = ops->hooks; hook->instr_mask; hook++)
+                unregister_undef_hook(hook);
+        pr_notice("Removed %s emulation handler\n", ops->name);
+}
+static int update_insn_emulation_mode(struct insn_emulation *insn,
+                                       enum insn_emulation_mode prev)
+{
+        int ret = 0;
+        switch (prev) {
+        case INSN_UNDEF: /* Nothing to be done */
+                break;
+        case INSN_EMULATE:
+                remove_emulation_hooks(insn->ops);
+                break;
+        case INSN_HW:
+                if (insn->ops->set_hw_mode) {
+                        insn->ops->set_hw_mode(false);
+                        pr_notice("Disabled %s support\n", insn->ops->name);
+                }
+                break;
+        }
+        switch (insn->current_mode) {
+        case INSN_UNDEF:
+                break;
+        case INSN_EMULATE:
+                register_emulation_hooks(insn->ops);
+                break;
+        case INSN_HW:
+                if (insn->ops->set_hw_mode && insn->ops->set_hw_mode(true))
+                        pr_notice("Enabled %s support\n", insn->ops->name);
+                else
+                        ret = -EINVAL;
+                break;
+        }
+        return ret;
+}
+static void register_insn_emulation(struct insn_emulation_ops *ops)
+{
+        unsigned long flags;
+        struct insn_emulation *insn;
+        insn = kzalloc(sizeof(*insn), GFP_KERNEL);
+        insn->ops = ops;
+        insn->min = INSN_UNDEF;
+        switch (ops->status) {
+        case INSN_DEPRECATED:
+                insn->current_mode = INSN_EMULATE;
+                insn->max = INSN_HW;
+                break;
+        case INSN_OBSOLETE:
+                insn->current_mode = INSN_UNDEF;
+                insn->max = INSN_EMULATE;
+                break;
+        }
+        raw_spin_lock_irqsave(&insn_emulation_lock, flags);
+        list_add(&insn->node, &insn_emulation);
+        nr_insn_emulated++;
+        raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
+        /* Register any handlers if required */
+        update_insn_emulation_mode(insn, INSN_UNDEF);
+}
+static int emulation_proc_handler(struct ctl_table *table, int write,
+                                  void __user *buffer, size_t *lenp,
+                                  loff_t *ppos)
+{
+        int ret = 0;
+        struct insn_emulation *insn = (struct insn_emulation *) table->data;
+        enum insn_emulation_mode prev_mode = insn->current_mode;
+        table->data = &insn->current_mode;
+        ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
+        if (ret || !write || prev_mode == insn->current_mode)
+                goto ret;
+        ret = update_insn_emulation_mode(insn, prev_mode);
+        if (ret) {
+                /* Mode change failed, revert to previous mode. */
+                insn->current_mode = prev_mode;
+                update_insn_emulation_mode(insn, INSN_UNDEF);
+        }
+ret:
+        table->data = insn;
+        return ret;
+}
+static struct ctl_table ctl_abi[] = {
+        {
+                .procname = "abi",
+                .mode = 0555,
+        },
+        { }
+};
+static void register_insn_emulation_sysctl(struct ctl_table *table)
+{
+        unsigned long flags;
+        int i = 0;
+        struct insn_emulation *insn;
+        struct ctl_table *insns_sysctl, *sysctl;
+        insns_sysctl = kzalloc(sizeof(*sysctl) * (nr_insn_emulated + 1),
+                              GFP_KERNEL);
+        raw_spin_lock_irqsave(&insn_emulation_lock, flags);
+        list_for_each_entry(insn, &insn_emulation, node) {
+                sysctl = &insns_sysctl[i];
+                sysctl->mode = 0644;
+                sysctl->maxlen = sizeof(int);
+                sysctl->procname = insn->ops->name;
+                sysctl->data = insn;
+                sysctl->extra1 = &insn->min;
+                sysctl->extra2 = &insn->max;
+                sysctl->proc_handler = emulation_proc_handler;
+                i++;
+        }
+        raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
+        table->child = insns_sysctl;
+        register_sysctl_table(table);
+}
+/*
+ *  Implement emulation of the SWP/SWPB instructions using load-exclusive and
+ *  store-exclusive.
+ *
+ *  Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
+ *  Where: Rt  = destination
+ *         Rt2 = source
+ *         Rn  = address
+ */
+/*
+ * Error-checking SWP macros implemented using ldxr{b}/stxr{b}
+ */
+#define __user_swpX_asm(data, addr, res, temp, B)               \
+        __asm__ __volatile__(                                   \
+        "       mov             %w2, %w1\n"                     \
+        "0:     ldxr"B"         %w1, [%3]\n"                    \
+        "1:     stxr"B"         %w0, %w2, [%3]\n"               \
+        "       cbz             %w0, 2f\n"                      \
+        "       mov             %w0, %w4\n"                     \
+        "2:\n"                                                  \
+        "       .pushsection     .fixup,\"ax\"\n"               \
+        "       .align          2\n"                            \
+        "3:     mov             %w0, %w5\n"                     \
+        "       b               2b\n"                           \
+        "       .popsection"                                    \
+        "       .pushsection     __ex_table,\"a\"\n"            \
+        "       .align          3\n"                            \
+        "       .quad           0b, 3b\n"                       \
+        "       .quad           1b, 3b\n"                       \
+        "       .popsection"                                    \
+        : "=&r" (res), "+r" (data), "=&r" (temp)                \
+        : "r" (addr), "i" (-EAGAIN), "i" (-EFAULT)              \
+        : "memory")
+#define __user_swp_asm(data, addr, res, temp) \
+        __user_swpX_asm(data, addr, res, temp, "")
+#define __user_swpb_asm(data, addr, res, temp) \
+        __user_swpX_asm(data, addr, res, temp, "b")
+/*
+ * Bit 22 of the instruction encoding distinguishes between
+ * the SWP and SWPB variants (bit set means SWPB).
+ */
+#define TYPE_SWPB (1 << 22)
+/*
+ * Set up process info to signal segmentation fault - called on access error.
+ */
+static void set_segfault(struct pt_regs *regs, unsigned long addr)
+{
+        siginfo_t info;
+        down_read(&current->mm->mmap_sem);
+        if (find_vma(current->mm, addr) == NULL)
+                info.si_code = SEGV_MAPERR;
+        else
+                info.si_code = SEGV_ACCERR;
+        up_read(&current->mm->mmap_sem);
+        info.si_signo = SIGSEGV;
+        info.si_errno = 0;
+        info.si_addr  = (void *) instruction_pointer(regs);
+        pr_debug("SWP{B} emulation: access caused memory abort!\n");
+        arm64_notify_die("Illegal memory access", regs, &info, 0);
+}
+static int emulate_swpX(unsigned int address, unsigned int *data,
+                        unsigned int type)
+{
+        unsigned int res = 0;
+        if ((type != TYPE_SWPB) && (address & 0x3)) {
+                /* SWP to unaligned address not permitted */
+                pr_debug("SWP instruction on unaligned pointer!\n");
+                return -EFAULT;
+        }
+        while (1) {
+                unsigned long temp;
+                if (type == TYPE_SWPB)
+                        __user_swpb_asm(*data, address, res, temp);
+                else
+                        __user_swp_asm(*data, address, res, temp);
+                if (likely(res != -EAGAIN) || signal_pending(current))
+                        break;
+                cond_resched();
+        }
+        return res;
+}
+/*
+ * swp_handler logs the id of calling process, dissects the instruction, sanity
+ * checks the memory location, calls emulate_swpX for the actual operation and
+ * deals with fixup/error handling before returning
+ */
+static int swp_handler(struct pt_regs *regs, u32 instr)
+{
+        u32 destreg, data, type, address = 0;
+        int rn, rt2, res = 0;
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
+        type = instr & TYPE_SWPB;
+        switch (arm_check_condition(instr, regs->pstate)) {
+        case ARM_OPCODE_CONDTEST_PASS:
+                break;
+        case ARM_OPCODE_CONDTEST_FAIL:
+                /* Condition failed - return to next instruction */
+                goto ret;
+        case ARM_OPCODE_CONDTEST_UNCOND:
+                /* If unconditional encoding - not a SWP, undef */
+                return -EFAULT;
+        default:
+                return -EINVAL;
+        }
+        rn = aarch32_insn_extract_reg_num(instr, A32_RN_OFFSET);
+        rt2 = aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET);
+        address = (u32)regs->user_regs.regs[rn];
+        data    = (u32)regs->user_regs.regs[rt2];
+        destreg = aarch32_insn_extract_reg_num(instr, A32_RT_OFFSET);
+        pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n",
+                rn, address, destreg,
+                aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET), data);
+        /* Check access in reasonable access range for both SWP and SWPB */
+        if (!access_ok(VERIFY_WRITE, (address & ~3), 4)) {
+                pr_debug("SWP{B} emulation: access to 0x%08x not allowed!\n",
+                        address);
+                goto fault;
+        }
+        res = emulate_swpX(address, &data, type);
+        if (res == -EFAULT)
+                goto fault;
+        else if (res == 0)
+                regs->user_regs.regs[destreg] = data;
+ret:
+        if (type == TYPE_SWPB)
+                trace_instruction_emulation("swpb", regs->pc);
+        else
+                trace_instruction_emulation("swp", regs->pc);
+        pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n",
+                        current->comm, (unsigned long)current->pid, regs->pc);
+        regs->pc += 4;
+        return 0;
+fault:
+        set_segfault(regs, address);
+        return 0;
+}
+/*
+ * Only emulate SWP/SWPB executed in ARM state/User mode.
+ * The kernel must be SWP free and SWP{B} does not exist in Thumb.
+ */
+static struct undef_hook swp_hooks[] = {
+        {
+                .instr_mask     = 0x0fb00ff0,
+                .instr_val      = 0x01000090,
+                .pstate_mask    = COMPAT_PSR_MODE_MASK,
+                .pstate_val     = COMPAT_PSR_MODE_USR,
+                .fn             = swp_handler
+        },
+        { }
+};
+static struct insn_emulation_ops swp_ops = {
+        .name = "swp",
+        .status = INSN_OBSOLETE,
+        .hooks = swp_hooks,
+        .set_hw_mode = NULL,
+};
+static int cp15barrier_handler(struct pt_regs *regs, u32 instr)
+{
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
+        switch (arm_check_condition(instr, regs->pstate)) {
+        case ARM_OPCODE_CONDTEST_PASS:
+                break;
+        case ARM_OPCODE_CONDTEST_FAIL:
+                /* Condition failed - return to next instruction */
+                goto ret;
+        case ARM_OPCODE_CONDTEST_UNCOND:
+                /* If unconditional encoding - not a barrier instruction */
+                return -EFAULT;
+        default:
+                return -EINVAL;
+        }
+        switch (aarch32_insn_mcr_extract_crm(instr)) {
+        case 10:
+                /*
+                 * dmb - mcr p15, 0, Rt, c7, c10, 5
+                 * dsb - mcr p15, 0, Rt, c7, c10, 4
+                 */
+                if (aarch32_insn_mcr_extract_opc2(instr) == 5) {
+                        dmb(sy);
+                        trace_instruction_emulation(
+                                "mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc);
+                } else {
+                        dsb(sy);
+                        trace_instruction_emulation(
+                                "mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc);
+                }
+                break;
+        case 5:
+                /*
+                 * isb - mcr p15, 0, Rt, c7, c5, 4
+                 *
+                 * Taking an exception or returning from one acts as an
+                 * instruction barrier. So no explicit barrier needed here.
+                 */
+                trace_instruction_emulation(
+                        "mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc);
+                break;
+        }
+ret:
+        pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n",
+                        current->comm, (unsigned long)current->pid, regs->pc);
+        regs->pc += 4;
+        return 0;
+}
+#define SCTLR_EL1_CP15BEN (1 << 5)
+static inline void config_sctlr_el1(u32 clear, u32 set)
+{
+        u32 val;
+        asm volatile("mrs %0, sctlr_el1" : "=r" (val));
+        val &= ~clear;
+        val |= set;
+        asm volatile("msr sctlr_el1, %0" : : "r" (val));
+}
+static void enable_cp15_ben(void *info)
+{
+        config_sctlr_el1(0, SCTLR_EL1_CP15BEN);
+}
+static void disable_cp15_ben(void *info)
+{
+        config_sctlr_el1(SCTLR_EL1_CP15BEN, 0);
+}
+static int cpu_hotplug_notify(struct notifier_block *b,
+                              unsigned long action, void *hcpu)
+{
+        switch (action) {
+        case CPU_STARTING:
+        case CPU_STARTING_FROZEN:
+                enable_cp15_ben(NULL);
+                return NOTIFY_DONE;
+        case CPU_DYING:
+        case CPU_DYING_FROZEN:
+                disable_cp15_ben(NULL);
+                return NOTIFY_DONE;
+        }
+        return NOTIFY_OK;
+}
+static struct notifier_block cpu_hotplug_notifier = {
+        .notifier_call = cpu_hotplug_notify,
+};
+static int cp15_barrier_set_hw_mode(bool enable)
+{
+        if (enable) {
+                register_cpu_notifier(&cpu_hotplug_notifier);
+                on_each_cpu(enable_cp15_ben, NULL, true);
+        } else {
+                unregister_cpu_notifier(&cpu_hotplug_notifier);
+                on_each_cpu(disable_cp15_ben, NULL, true);
+        }
+        return true;
+}
+static struct undef_hook cp15_barrier_hooks[] = {
+        {
+                .instr_mask     = 0x0fff0fdf,
+                .instr_val      = 0x0e070f9a,
+                .pstate_mask    = COMPAT_PSR_MODE_MASK,
+                .pstate_val     = COMPAT_PSR_MODE_USR,
+                .fn             = cp15barrier_handler,
+        },
+        {
+                .instr_mask     = 0x0fff0fff,
+                .instr_val      = 0x0e070f95,
+                .pstate_mask    = COMPAT_PSR_MODE_MASK,
+                .pstate_val     = COMPAT_PSR_MODE_USR,
+                .fn             = cp15barrier_handler,
+        },
+        { }
+};
+static struct insn_emulation_ops cp15_barrier_ops = {
+        .name = "cp15_barrier",
+        .status = INSN_DEPRECATED,
+        .hooks = cp15_barrier_hooks,
+        .set_hw_mode = cp15_barrier_set_hw_mode,
+};
+/*
+ * Invoked as late_initcall, since not needed before init spawned.
+ */
+static int __init armv8_deprecated_init(void)
+{
+        if (IS_ENABLED(CONFIG_SWP_EMULATION))
+                register_insn_emulation(&swp_ops);
+        if (IS_ENABLED(CONFIG_CP15_BARRIER_EMULATION))
+                register_insn_emulation(&cp15_barrier_ops);
+        register_insn_emulation_sysctl(ctl_abi);
+        return 0;
+}
+late_initcall(armv8_deprecated_init);
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
new file mode 100644
index 000000000000..fa62637e63a8
--- /dev/null
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -0,0 +1,111 @@
+/*
+ * Contains CPU specific errata definitions
+ *
+ * Copyright (C) 2014 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#define pr_fmt(fmt) "alternatives: " fmt
+#include <linux/types.h>
+#include <asm/cpu.h>
+#include <asm/cputype.h>
+#include <asm/cpufeature.h>
+#define MIDR_CORTEX_A53 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
+#define MIDR_CORTEX_A57 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
+/*
+ * Add a struct or another datatype to the union below if you need
+ * different means to detect an affected CPU.
+ */
+struct arm64_cpu_capabilities {
+        const char *desc;
+        u16 capability;
+        bool (*is_affected)(struct arm64_cpu_capabilities *);
+        union {
+                struct {
+                        u32 midr_model;
+                        u32 midr_range_min, midr_range_max;
+                };
+        };
+};
+#define CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
+                        MIDR_ARCHITECTURE_MASK)
+static bool __maybe_unused
+is_affected_midr_range(struct arm64_cpu_capabilities *entry)
+{
+        u32 midr = read_cpuid_id();
+        if ((midr & CPU_MODEL_MASK) != entry->midr_model)
+                return false;
+        midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
+        return (midr >= entry->midr_range_min && midr <= entry->midr_range_max);
+}
+#define MIDR_RANGE(model, min, max) \
+        .is_affected = is_affected_midr_range, \
+        .midr_model = model, \
+        .midr_range_min = min, \
+        .midr_range_max = max
+struct arm64_cpu_capabilities arm64_errata[] = {
+#if     defined(CONFIG_ARM64_ERRATUM_826319) || \
+        defined(CONFIG_ARM64_ERRATUM_827319) || \
+        defined(CONFIG_ARM64_ERRATUM_824069)
+        {
+        /* Cortex-A53 r0p[012] */
+                .desc = "ARM errata 826319, 827319, 824069",
+                .capability = ARM64_WORKAROUND_CLEAN_CACHE,
+                MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02),
+        },
+#endif
+#ifdef CONFIG_ARM64_ERRATUM_819472
+        {
+        /* Cortex-A53 r0p[01] */
+                .desc = "ARM errata 819472",
+                .capability = ARM64_WORKAROUND_CLEAN_CACHE,
+                MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01),
+        },
+#endif
+#ifdef CONFIG_ARM64_ERRATUM_832075
+        {
+        /* Cortex-A57 r0p0 - r1p2 */
+                .desc = "ARM erratum 832075",
+                .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
+                MIDR_RANGE(MIDR_CORTEX_A57, 0x00, 0x12),
+        },
+#endif
+        {
+        }
+};
+void check_local_cpu_errata(void)
+{
+        struct arm64_cpu_capabilities *cpus = arm64_errata;
+        int i;
+        for (i = 0; cpus[i].desc; i++) {
+                if (!cpus[i].is_affected(&cpus[i]))
+                        continue;
+                if (!cpus_have_cap(cpus[i].capability))
+                        pr_info("enabling workaround for %s\n", cpus[i].desc);
+                cpus_set_cap(cpus[i].capability);
+        }
+}
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 504fdaa8367e..57b641747534 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -18,6 +18,7 @@
 #include <asm/cachetype.h>
 #include <asm/cpu.h>
 #include <asm/cputype.h>
+#include <asm/cpufeature.h>
 #include <linux/bitops.h>
 #include <linux/bug.h>
@@ -111,6 +112,15 @@ static void cpuinfo_sanity_check(struct cpuinfo_arm64 *cur)
        diff |= CHECK(cntfrq, boot, cur, cpu);
        /*
+         * The kernel uses self-hosted debug features and expects CPUs to
+         * support identical debug features. We presently need CTX_CMPs, WRPs,
+         * and BRPs to be identical.
+         * ID_AA64DFR1 is currently RES0.
+         */
+        diff |= CHECK(id_aa64dfr0, boot, cur, cpu);
+        diff |= CHECK(id_aa64dfr1, boot, cur, cpu);
+        /*
         * Even in big.LITTLE, processors should be identical instruction-set
         * wise.
         */
@@ -143,7 +153,12 @@ static void cpuinfo_sanity_check(struct cpuinfo_arm64 *cur)
        diff |= CHECK(id_isar3, boot, cur, cpu);
        diff |= CHECK(id_isar4, boot, cur, cpu);
        diff |= CHECK(id_isar5, boot, cur, cpu);
-        diff |= CHECK(id_mmfr0, boot, cur, cpu);
+        /*
+         * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
+         * ACTLR formats could differ across CPUs and therefore would have to
+         * be trapped for virtualization anyway.
+         */
+        diff |= CHECK_MASK(id_mmfr0, 0xff0fffff, boot, cur, cpu);
        diff |= CHECK(id_mmfr1, boot, cur, cpu);
        diff |= CHECK(id_mmfr2, boot, cur, cpu);
        diff |= CHECK(id_mmfr3, boot, cur, cpu);
@@ -155,7 +170,7 @@ static void cpuinfo_sanity_check(struct cpuinfo_arm64 *cur)
         * pretend to support them.
         */
        WARN_TAINT_ONCE(diff, TAINT_CPU_OUT_OF_SPEC,
-                        "Unsupported CPU feature variation.");
+                        "Unsupported CPU feature variation.\n");
 }
 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
@@ -165,6 +180,8 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
        info->reg_dczid = read_cpuid(DCZID_EL0);
        info->reg_midr = read_cpuid_id();
+        info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
+        info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
        info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
        info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
        info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
@@ -186,6 +203,8 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
        info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
        cpuinfo_detect_icache_policy(info);
+        check_local_cpu_errata();
 }
 void cpuinfo_store_cpu(void)
diff --git a/arch/arm64/kernel/efi-entry.S b/arch/arm64/kernel/efi-entry.S
index d18a44940968..8ce9b0577442 100644
--- a/arch/arm64/kernel/efi-entry.S
+++ b/arch/arm64/kernel/efi-entry.S
@@ -61,7 +61,8 @@ ENTRY(efi_stub_entry)
         */
        mov     x20, x0         // DTB address
        ldr     x0, [sp, #16]   // relocated _text address
-        mov     x21, x0
+        ldr     x21, =stext_offset
+        add     x21, x0, x21
        /*
         * Calculate size of the kernel Image (same for original and copy).
diff --git a/arch/arm64/kernel/efi.c b/arch/arm64/kernel/efi.c
index 95c49ebc660d..6fac253bc783 100644
--- a/arch/arm64/kernel/efi.c
+++ b/arch/arm64/kernel/efi.c
@@ -11,6 +11,7 @@
 *
 */
+#include <linux/dmi.h>
 #include <linux/efi.h>
 #include <linux/export.h>
 #include <linux/memblock.h>
@@ -112,8 +113,6 @@ static int __init uefi_init(void)
                efi.systab->hdr.revision & 0xffff, vendor);
        retval = efi_config_init(NULL);
-        if (retval == 0)
-                set_bit(EFI_CONFIG_TABLES, &efi.flags);
 out:
        early_memunmap(efi.systab,  sizeof(efi_system_table_t));
@@ -125,17 +124,17 @@ out:
 */
 static __init int is_reserve_region(efi_memory_desc_t *md)
 {
-        if (!is_normal_ram(md))
+        switch (md->type) {
+        case EFI_LOADER_CODE:
+        case EFI_LOADER_DATA:
+        case EFI_BOOT_SERVICES_CODE:
+        case EFI_BOOT_SERVICES_DATA:
+        case EFI_CONVENTIONAL_MEMORY:
                return 0;
+        default:
-        if (md->attribute & EFI_MEMORY_RUNTIME)
+                break;
-                return 1;
+        }
+        return is_normal_ram(md);
-        if (md->type == EFI_ACPI_RECLAIM_MEMORY ||
-            md->type == EFI_RESERVED_TYPE)
-                return 1;
-        return 0;
 }
 static __init void reserve_regions(void)
@@ -471,3 +470,17 @@ err_unmap:
        return -1;
 }
 early_initcall(arm64_enter_virtual_mode);
+static int __init arm64_dmi_init(void)
+{
+        /*
+         * On arm64, DMI depends on UEFI, and dmi_scan_machine() needs to
+         * be called early because dmi_id_init(), which is an arch_initcall
+         * itself, depends on dmi_scan_machine() having been called already.
+         */
+        dmi_scan_machine();
+        if (dmi_available)
+                dmi_set_dump_stack_arch_desc();
+        return 0;
+}
+core_initcall(arm64_dmi_init);
diff --git a/arch/arm64/kernel/entry-ftrace.S b/arch/arm64/kernel/entry-ftrace.S
index 38e704e597f7..08cafc518b9a 100644
--- a/arch/arm64/kernel/entry-ftrace.S
+++ b/arch/arm64/kernel/entry-ftrace.S
@@ -98,8 +98,8 @@
 ENTRY(_mcount)
        mcount_enter
-        ldr     x0, =ftrace_trace_function
+        adrp    x0, ftrace_trace_function
-        ldr     x2, [x0]
+        ldr     x2, [x0, #:lo12:ftrace_trace_function]
        adr     x0, ftrace_stub
        cmp     x0, x2                  // if (ftrace_trace_function
        b.eq    skip_ftrace_call        //     != ftrace_stub) {
@@ -115,14 +115,15 @@ skip_ftrace_call:			//   return;
        mcount_exit                     //   return;
                                        // }
 skip_ftrace_call:
-        ldr     x1, =ftrace_graph_return
+        adrp    x1, ftrace_graph_return
-        ldr     x2, [x1]                //   if ((ftrace_graph_return
+        ldr     x2, [x1, #:lo12:ftrace_graph_return]
-        cmp     x0, x2                  //        != ftrace_stub)
+        cmp     x0, x2                  //   if ((ftrace_graph_return
-        b.ne    ftrace_graph_caller
+        b.ne    ftrace_graph_caller     //        != ftrace_stub)
-        ldr     x1, =ftrace_graph_entry //     || (ftrace_graph_entry
+        adrp    x1, ftrace_graph_entry  //     || (ftrace_graph_entry
-        ldr     x2, [x1]                //        != ftrace_graph_entry_stub))
+        adrp    x0, ftrace_graph_entry_stub //     != ftrace_graph_entry_stub))
-        ldr     x0, =ftrace_graph_entry_stub
+        ldr     x2, [x1, #:lo12:ftrace_graph_entry]
+        add     x0, x0, #:lo12:ftrace_graph_entry_stub
        cmp     x0, x2
        b.ne    ftrace_graph_caller     //     ftrace_graph_caller();
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index 726b910fe6ec..fd4fa374e5d2 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -64,25 +64,26 @@
 #define BAD_ERROR       3
        .macro  kernel_entry, el, regsize = 64
-        sub     sp, sp, #S_FRAME_SIZE - S_LR    // room for LR, SP, SPSR, ELR
+        sub     sp, sp, #S_FRAME_SIZE
        .if     \regsize == 32
        mov     w0, w0                          // zero upper 32 bits of x0
        .endif
-        push    x28, x29
+        stp     x0, x1, [sp, #16 * 0]
-        push    x26, x27
+        stp     x2, x3, [sp, #16 * 1]
-        push    x24, x25
+        stp     x4, x5, [sp, #16 * 2]
-        push    x22, x23
+        stp     x6, x7, [sp, #16 * 3]
-        push    x20, x21
+        stp     x8, x9, [sp, #16 * 4]
-        push    x18, x19
+        stp     x10, x11, [sp, #16 * 5]
-        push    x16, x17
+        stp     x12, x13, [sp, #16 * 6]
-        push    x14, x15
+        stp     x14, x15, [sp, #16 * 7]
-        push    x12, x13
+        stp     x16, x17, [sp, #16 * 8]
-        push    x10, x11
+        stp     x18, x19, [sp, #16 * 9]
-        push    x8, x9
+        stp     x20, x21, [sp, #16 * 10]
-        push    x6, x7
+        stp     x22, x23, [sp, #16 * 11]
-        push    x4, x5
+        stp     x24, x25, [sp, #16 * 12]
-        push    x2, x3
+        stp     x26, x27, [sp, #16 * 13]
-        push    x0, x1
+        stp     x28, x29, [sp, #16 * 14]
        .if     \el == 0
        mrs     x21, sp_el0
        get_thread_info tsk                     // Ensure MDSCR_EL1.SS is clear,
@@ -118,33 +119,31 @@
        .if     \el == 0
        ct_user_enter
        ldr     x23, [sp, #S_SP]                // load return stack pointer
+        msr     sp_el0, x23
        .endif
+        msr     elr_el1, x21                    // set up the return data
+        msr     spsr_el1, x22
        .if     \ret
        ldr     x1, [sp, #S_X1]                 // preserve x0 (syscall return)
-        add     sp, sp, S_X2
        .else
-        pop     x0, x1
+        ldp     x0, x1, [sp, #16 * 0]
        .endif
-        pop     x2, x3                          // load the rest of the registers
+        ldp     x2, x3, [sp, #16 * 1]
-        pop     x4, x5
+        ldp     x4, x5, [sp, #16 * 2]
-        pop     x6, x7
+        ldp     x6, x7, [sp, #16 * 3]
-        pop     x8, x9
+        ldp     x8, x9, [sp, #16 * 4]
-        msr     elr_el1, x21                    // set up the return data
+        ldp     x10, x11, [sp, #16 * 5]
-        msr     spsr_el1, x22
+        ldp     x12, x13, [sp, #16 * 6]
-        .if     \el == 0
+        ldp     x14, x15, [sp, #16 * 7]
-        msr     sp_el0, x23
+        ldp     x16, x17, [sp, #16 * 8]
-        .endif
+        ldp     x18, x19, [sp, #16 * 9]
-        pop     x10, x11
+        ldp     x20, x21, [sp, #16 * 10]
-        pop     x12, x13
+        ldp     x22, x23, [sp, #16 * 11]
-        pop     x14, x15
+        ldp     x24, x25, [sp, #16 * 12]
-        pop     x16, x17
+        ldp     x26, x27, [sp, #16 * 13]
-        pop     x18, x19
+        ldp     x28, x29, [sp, #16 * 14]
-        pop     x20, x21
+        ldr     lr, [sp, #S_LR]
-        pop     x22, x23
+        add     sp, sp, #S_FRAME_SIZE           // restore sp
-        pop     x24, x25
-        pop     x26, x27
-        pop     x28, x29
-        ldr     lr, [sp], #S_FRAME_SIZE - S_LR  // load LR and restore SP
        eret                                    // return to kernel
        .endm
@@ -168,7 +167,8 @@ tsk	.req	x28		// current thread_info
 * Interrupt handling.
 */
        .macro  irq_handler
-        ldr     x1, handle_arch_irq
+        adrp    x1, handle_arch_irq
+        ldr     x1, [x1, #:lo12:handle_arch_irq]
        mov     x0, sp
        blr     x1
        .endm
@@ -455,8 +455,8 @@ el0_da:
        bic     x0, x26, #(0xff << 56)
        mov     x1, x25
        mov     x2, sp
-        adr     lr, ret_to_user
+        bl      do_mem_abort
-        b       do_mem_abort
+        b       ret_to_user
 el0_ia:
        /*
         * Instruction abort handling
@@ -468,8 +468,8 @@ el0_ia:
        mov     x0, x26
        orr     x1, x25, #1 << 24               // use reserved ISS bit for instruction aborts
        mov     x2, sp
-        adr     lr, ret_to_user
+        bl      do_mem_abort
-        b       do_mem_abort
+        b       ret_to_user
 el0_fpsimd_acc:
        /*
         * Floating Point or Advanced SIMD access
@@ -478,8 +478,8 @@ el0_fpsimd_acc:
        ct_user_exit
        mov     x0, x25
        mov     x1, sp
-        adr     lr, ret_to_user
+        bl      do_fpsimd_acc
-        b       do_fpsimd_acc
+        b       ret_to_user
 el0_fpsimd_exc:
        /*
         * Floating Point or Advanced SIMD exception
@@ -488,8 +488,8 @@ el0_fpsimd_exc:
        ct_user_exit
        mov     x0, x25
        mov     x1, sp
-        adr     lr, ret_to_user
+        bl      do_fpsimd_exc
-        b       do_fpsimd_exc
+        b       ret_to_user
 el0_sp_pc:
        /*
         * Stack or PC alignment exception handling
@@ -500,8 +500,8 @@ el0_sp_pc:
        mov     x0, x26
        mov     x1, x25
        mov     x2, sp
-        adr     lr, ret_to_user
+        bl      do_sp_pc_abort
-        b       do_sp_pc_abort
+        b       ret_to_user
 el0_undef:
        /*
         * Undefined instruction
@@ -510,8 +510,8 @@ el0_undef:
        enable_dbg_and_irq
        ct_user_exit
        mov     x0, sp
-        adr     lr, ret_to_user
+        bl      do_undefinstr
-        b       do_undefinstr
+        b       ret_to_user
 el0_dbg:
        /*
         * Debug exception handling
@@ -530,8 +530,8 @@ el0_inv:
        mov     x0, sp
        mov     x1, #BAD_SYNC
        mrs     x2, esr_el1
-        adr     lr, ret_to_user
+        bl      bad_mode
-        b       bad_mode
+        b       ret_to_user
 ENDPROC(el0_sync)
        .align  6
@@ -653,14 +653,15 @@ el0_svc_naked:					// compat entry point
        ldr     x16, [tsk, #TI_FLAGS]           // check for syscall hooks
        tst     x16, #_TIF_SYSCALL_WORK
        b.ne    __sys_trace
-        adr     lr, ret_fast_syscall            // return address
        cmp     scno, sc_nr                     // check upper syscall limit
        b.hs    ni_sys
        ldr     x16, [stbl, scno, lsl #3]       // address in the syscall table
-        br      x16                             // call sys_* routine
+        blr     x16                             // call sys_* routine
+        b       ret_fast_syscall
 ni_sys:
        mov     x0, sp
-        b       do_ni_syscall
+        bl      do_ni_syscall
+        b       ret_fast_syscall
 ENDPROC(el0_svc)
        /*
@@ -668,26 +669,38 @@ ENDPROC(el0_svc)
         * switches, and waiting for our parent to respond.
         */
 __sys_trace:
-        mov     x0, sp
+        mov     w0, #-1                         // set default errno for
+        cmp     scno, x0                        // user-issued syscall(-1)
+        b.ne    1f
+        mov     x0, #-ENOSYS
+        str     x0, [sp, #S_X0]
+1:      mov     x0, sp
        bl      syscall_trace_enter
-        adr     lr, __sys_trace_return          // return address
+        cmp     w0, #-1                         // skip the syscall?
+        b.eq    __sys_trace_return_skipped
        uxtw    scno, w0                        // syscall number (possibly new)
        mov     x1, sp                          // pointer to regs
        cmp     scno, sc_nr                     // check upper syscall limit
-        b.hs    ni_sys
+        b.hs    __ni_sys_trace
        ldp     x0, x1, [sp]                    // restore the syscall args
        ldp     x2, x3, [sp, #S_X2]
        ldp     x4, x5, [sp, #S_X4]
        ldp     x6, x7, [sp, #S_X6]
        ldr     x16, [stbl, scno, lsl #3]       // address in the syscall table
-        br      x16                             // call sys_* routine
+        blr     x16                             // call sys_* routine
 __sys_trace_return:
-        str     x0, [sp]                        // save returned x0
+        str     x0, [sp, #S_X0]                 // save returned x0
+__sys_trace_return_skipped:
        mov     x0, sp
        bl      syscall_trace_exit
        b       ret_to_user
+__ni_sys_trace:
+        mov     x0, sp
+        bl      do_ni_syscall
+        b       __sys_trace_return
 /*
 * Special system call wrappers.
 */
@@ -695,6 +708,3 @@ ENTRY(sys_rt_sigreturn_wrapper)
        mov     x0, sp
        b       sys_rt_sigreturn
 ENDPROC(sys_rt_sigreturn_wrapper)
-ENTRY(handle_arch_irq)
-        .quad   0
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 0a6e4f924df8..8ce88e08c030 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -132,6 +132,8 @@ efi_head:
 #endif
 #ifdef CONFIG_EFI
+        .globl  stext_offset
+        .set    stext_offset, stext - efi_head
        .align 3
 pe_header:
        .ascii  "PE"
@@ -155,12 +157,12 @@ optional_header:
        .long   0                               // SizeOfInitializedData
        .long   0                               // SizeOfUninitializedData
        .long   efi_stub_entry - efi_head       // AddressOfEntryPoint
-        .long   stext - efi_head                // BaseOfCode
+        .long   stext_offset                    // BaseOfCode
 extra_header_fields:
        .quad   0                               // ImageBase
-        .long   0x20                            // SectionAlignment
+        .long   0x1000                          // SectionAlignment
-        .long   0x8                             // FileAlignment
+        .long   PECOFF_FILE_ALIGNMENT           // FileAlignment
        .short  0                               // MajorOperatingSystemVersion
        .short  0                               // MinorOperatingSystemVersion
        .short  0                               // MajorImageVersion
@@ -172,7 +174,7 @@ extra_header_fields:
        .long   _end - efi_head                 // SizeOfImage
        // Everything before the kernel image is considered part of the header
-        .long   stext - efi_head                // SizeOfHeaders
+        .long   stext_offset                    // SizeOfHeaders
        .long   0                               // CheckSum
        .short  0xa                             // Subsystem (EFI application)
        .short  0                               // DllCharacteristics
@@ -217,16 +219,24 @@ section_table:
        .byte   0
        .byte   0                       // end of 0 padding of section name
        .long   _end - stext            // VirtualSize
-        .long   stext - efi_head        // VirtualAddress
+        .long   stext_offset            // VirtualAddress
        .long   _edata - stext          // SizeOfRawData
-        .long   stext - efi_head        // PointerToRawData
+        .long   stext_offset            // PointerToRawData
        .long   0               // PointerToRelocations (0 for executables)
        .long   0               // PointerToLineNumbers (0 for executables)
        .short  0               // NumberOfRelocations  (0 for executables)
        .short  0               // NumberOfLineNumbers  (0 for executables)
        .long   0xe0500020      // Characteristics (section flags)
-        .align 5
+        /*
+         * EFI will load stext onwards at the 4k section alignment
+         * described in the PE/COFF header. To ensure that instruction
+         * sequences using an adrp and a :lo12: immediate will function
+         * correctly at this alignment, we must ensure that stext is
+         * placed at a 4k boundary in the Image to begin with.
+         */
+        .align 12
 #endif
 ENTRY(stext)
@@ -238,7 +248,13 @@ ENTRY(stext)
        mov     x0, x22
        bl      lookup_processor_type
        mov     x23, x0                         // x23=current cpu_table
-        cbz     x23, __error_p                  // invalid processor (x23=0)?
+        /*
+         * __error_p may end up out of range for cbz if text areas are
+         * aligned up to section sizes.
+         */
+        cbnz    x23, 1f                         // invalid processor (x23=0)?
+        b       __error_p
+1:
        bl      __vet_fdt
        bl      __create_page_tables            // x25=TTBR0, x26=TTBR1
        /*
@@ -250,13 +266,214 @@ ENTRY(stext)
         */
        ldr     x27, __switch_data              // address to jump to after
                                                // MMU has been enabled
-        adr     lr, __enable_mmu                // return (PIC) address
+        adrp    lr, __enable_mmu                // return (PIC) address
+        add     lr, lr, #:lo12:__enable_mmu
        ldr     x12, [x23, #CPU_INFO_SETUP]
        add     x12, x12, x28                   // __virt_to_phys
        br      x12                             // initialise processor
 ENDPROC(stext)
 /*
+ * Determine validity of the x21 FDT pointer.
+ * The dtb must be 8-byte aligned and live in the first 512M of memory.
+ */
+__vet_fdt:
+        tst     x21, #0x7
+        b.ne    1f
+        cmp     x21, x24
+        b.lt    1f
+        mov     x0, #(1 << 29)
+        add     x0, x0, x24
+        cmp     x21, x0
+        b.ge    1f
+        ret
+1:
+        mov     x21, #0
+        ret
+ENDPROC(__vet_fdt)
+/*
+ * Macro to create a table entry to the next page.
+ *
+ *      tbl:    page table address
+ *      virt:   virtual address
+ *      shift:  #imm page table shift
+ *      ptrs:   #imm pointers per table page
+ *
+ * Preserves:   virt
+ * Corrupts:    tmp1, tmp2
+ * Returns:     tbl -> next level table page address
+ */
+        .macro  create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
+        lsr     \tmp1, \virt, #\shift
+        and     \tmp1, \tmp1, #\ptrs - 1        // table index
+        add     \tmp2, \tbl, #PAGE_SIZE
+        orr     \tmp2, \tmp2, #PMD_TYPE_TABLE   // address of next table and entry type
+        str     \tmp2, [\tbl, \tmp1, lsl #3]
+        add     \tbl, \tbl, #PAGE_SIZE          // next level table page
+        .endm
+/*
+ * Macro to populate the PGD (and possibily PUD) for the corresponding
+ * block entry in the next level (tbl) for the given virtual address.
+ *
+ * Preserves:   tbl, next, virt
+ * Corrupts:    tmp1, tmp2
+ */
+        .macro  create_pgd_entry, tbl, virt, tmp1, tmp2
+        create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2
+#if SWAPPER_PGTABLE_LEVELS == 3
+        create_table_entry \tbl, \virt, TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2
+#endif
+        .endm
+/*
+ * Macro to populate block entries in the page table for the start..end
+ * virtual range (inclusive).
+ *
+ * Preserves:   tbl, flags
+ * Corrupts:    phys, start, end, pstate
+ */
+        .macro  create_block_map, tbl, flags, phys, start, end
+        lsr     \phys, \phys, #BLOCK_SHIFT
+        lsr     \start, \start, #BLOCK_SHIFT
+        and     \start, \start, #PTRS_PER_PTE - 1       // table index
+        orr     \phys, \flags, \phys, lsl #BLOCK_SHIFT  // table entry
+        lsr     \end, \end, #BLOCK_SHIFT
+        and     \end, \end, #PTRS_PER_PTE - 1           // table end index
+9999:   str     \phys, [\tbl, \start, lsl #3]           // store the entry
+        add     \start, \start, #1                      // next entry
+        add     \phys, \phys, #BLOCK_SIZE               // next block
+        cmp     \start, \end
+        b.ls    9999b
+        .endm
+/*
+ * Setup the initial page tables. We only setup the barest amount which is
+ * required to get the kernel running. The following sections are required:
+ *   - identity mapping to enable the MMU (low address, TTBR0)
+ *   - first few MB of the kernel linear mapping to jump to once the MMU has
+ *     been enabled, including the FDT blob (TTBR1)
+ *   - pgd entry for fixed mappings (TTBR1)
+ */
+__create_page_tables:
+        pgtbl   x25, x26, x28                   // idmap_pg_dir and swapper_pg_dir addresses
+        mov     x27, lr
+        /*
+         * Invalidate the idmap and swapper page tables to avoid potential
+         * dirty cache lines being evicted.
+         */
+        mov     x0, x25
+        add     x1, x26, #SWAPPER_DIR_SIZE
+        bl      __inval_cache_range
+        /*
+         * Clear the idmap and swapper page tables.
+         */
+        mov     x0, x25
+        add     x6, x26, #SWAPPER_DIR_SIZE
+1:      stp     xzr, xzr, [x0], #16
+        stp     xzr, xzr, [x0], #16
+        stp     xzr, xzr, [x0], #16
+        stp     xzr, xzr, [x0], #16
+        cmp     x0, x6
+        b.lo    1b
+        ldr     x7, =MM_MMUFLAGS
+        /*
+         * Create the identity mapping.
+         */
+        mov     x0, x25                         // idmap_pg_dir
+        ldr     x3, =KERNEL_START
+        add     x3, x3, x28                     // __pa(KERNEL_START)
+        create_pgd_entry x0, x3, x5, x6
+        ldr     x6, =KERNEL_END
+        mov     x5, x3                          // __pa(KERNEL_START)
+        add     x6, x6, x28                     // __pa(KERNEL_END)
+        create_block_map x0, x7, x3, x5, x6
+        /*
+         * Map the kernel image (starting with PHYS_OFFSET).
+         */
+        mov     x0, x26                         // swapper_pg_dir
+        mov     x5, #PAGE_OFFSET
+        create_pgd_entry x0, x5, x3, x6
+        ldr     x6, =KERNEL_END
+        mov     x3, x24                         // phys offset
+        create_block_map x0, x7, x3, x5, x6
+        /*
+         * Map the FDT blob (maximum 2MB; must be within 512MB of
+         * PHYS_OFFSET).
+         */
+        mov     x3, x21                         // FDT phys address
+        and     x3, x3, #~((1 << 21) - 1)       // 2MB aligned
+        mov     x6, #PAGE_OFFSET
+        sub     x5, x3, x24                     // subtract PHYS_OFFSET
+        tst     x5, #~((1 << 29) - 1)           // within 512MB?
+        csel    x21, xzr, x21, ne               // zero the FDT pointer
+        b.ne    1f
+        add     x5, x5, x6                      // __va(FDT blob)
+        add     x6, x5, #1 << 21                // 2MB for the FDT blob
+        sub     x6, x6, #1                      // inclusive range
+        create_block_map x0, x7, x3, x5, x6
+1:
+        /*
+         * Since the page tables have been populated with non-cacheable
+         * accesses (MMU disabled), invalidate the idmap and swapper page
+         * tables again to remove any speculatively loaded cache lines.
+         */
+        mov     x0, x25
+        add     x1, x26, #SWAPPER_DIR_SIZE
+        bl      __inval_cache_range
+        mov     lr, x27
+        ret
+ENDPROC(__create_page_tables)
+        .ltorg
+        .align  3
+        .type   __switch_data, %object
+__switch_data:
+        .quad   __mmap_switched
+        .quad   __bss_start                     // x6
+        .quad   __bss_stop                      // x7
+        .quad   processor_id                    // x4
+        .quad   __fdt_pointer                   // x5
+        .quad   memstart_addr                   // x6
+        .quad   init_thread_union + THREAD_START_SP // sp
+/*
+ * The following fragment of code is executed with the MMU on in MMU mode, and
+ * uses absolute addresses; this is not position independent.
+ */
+__mmap_switched:
+        adr     x3, __switch_data + 8
+        ldp     x6, x7, [x3], #16
+1:      cmp     x6, x7
+        b.hs    2f
+        str     xzr, [x6], #8                   // Clear BSS
+        b       1b
+2:
+        ldp     x4, x5, [x3], #16
+        ldr     x6, [x3], #8
+        ldr     x16, [x3]
+        mov     sp, x16
+        str     x22, [x4]                       // Save processor ID
+        str     x21, [x5]                       // Save FDT pointer
+        str     x24, [x6]                       // Save PHYS_OFFSET
+        mov     x29, #0
+        b       start_kernel
+ENDPROC(__mmap_switched)
+/*
+ * end early head section, begin head code that is also used for
+ * hotplug and needs to have the same protections as the text region
+ */
+        .section ".text","ax"
+/*
 * If we're fortunate enough to boot at EL2, ensure that the world is
 * sane before dropping to EL1.
 *
@@ -331,7 +548,8 @@ CPU_LE(	movk	x0, #0x30d0, lsl #16	)	// Clear EE and E0E on LE systems
        msr     vttbr_el2, xzr
        /* Hypervisor stub */
-        adr     x0, __hyp_stub_vectors
+        adrp    x0, __hyp_stub_vectors
+        add     x0, x0, #:lo12:__hyp_stub_vectors
        msr     vbar_el2, x0
        /* spsr */
@@ -492,183 +710,6 @@ ENDPROC(__calc_phys_offset)
        .quad   PAGE_OFFSET
 /*
- * Macro to create a table entry to the next page.
- *
- *      tbl:    page table address
- *      virt:   virtual address
- *      shift:  #imm page table shift
- *      ptrs:   #imm pointers per table page
- *
- * Preserves:   virt
- * Corrupts:    tmp1, tmp2
- * Returns:     tbl -> next level table page address
- */
-        .macro  create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
-        lsr     \tmp1, \virt, #\shift
-        and     \tmp1, \tmp1, #\ptrs - 1        // table index
-        add     \tmp2, \tbl, #PAGE_SIZE
-        orr     \tmp2, \tmp2, #PMD_TYPE_TABLE   // address of next table and entry type
-        str     \tmp2, [\tbl, \tmp1, lsl #3]
-        add     \tbl, \tbl, #PAGE_SIZE          // next level table page
-        .endm
-/*
- * Macro to populate the PGD (and possibily PUD) for the corresponding
- * block entry in the next level (tbl) for the given virtual address.
- *
- * Preserves:   tbl, next, virt
- * Corrupts:    tmp1, tmp2
- */
-        .macro  create_pgd_entry, tbl, virt, tmp1, tmp2
-        create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2
-#if SWAPPER_PGTABLE_LEVELS == 3
-        create_table_entry \tbl, \virt, TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2
-#endif
-        .endm
-/*
- * Macro to populate block entries in the page table for the start..end
- * virtual range (inclusive).
- *
- * Preserves:   tbl, flags
- * Corrupts:    phys, start, end, pstate
- */
-        .macro  create_block_map, tbl, flags, phys, start, end
-        lsr     \phys, \phys, #BLOCK_SHIFT
-        lsr     \start, \start, #BLOCK_SHIFT
-        and     \start, \start, #PTRS_PER_PTE - 1       // table index
-        orr     \phys, \flags, \phys, lsl #BLOCK_SHIFT  // table entry
-        lsr     \end, \end, #BLOCK_SHIFT
-        and     \end, \end, #PTRS_PER_PTE - 1           // table end index
-9999:   str     \phys, [\tbl, \start, lsl #3]           // store the entry
-        add     \start, \start, #1                      // next entry
-        add     \phys, \phys, #BLOCK_SIZE               // next block
-        cmp     \start, \end
-        b.ls    9999b
-        .endm
-/*
- * Setup the initial page tables. We only setup the barest amount which is
- * required to get the kernel running. The following sections are required:
- *   - identity mapping to enable the MMU (low address, TTBR0)
- *   - first few MB of the kernel linear mapping to jump to once the MMU has
- *     been enabled, including the FDT blob (TTBR1)
- *   - pgd entry for fixed mappings (TTBR1)
- */
-__create_page_tables:
-        pgtbl   x25, x26, x28                   // idmap_pg_dir and swapper_pg_dir addresses
-        mov     x27, lr
-        /*
-         * Invalidate the idmap and swapper page tables to avoid potential
-         * dirty cache lines being evicted.
-         */
-        mov     x0, x25
-        add     x1, x26, #SWAPPER_DIR_SIZE
-        bl      __inval_cache_range
-        /*
-         * Clear the idmap and swapper page tables.
-         */
-        mov     x0, x25
-        add     x6, x26, #SWAPPER_DIR_SIZE
-1:      stp     xzr, xzr, [x0], #16
-        stp     xzr, xzr, [x0], #16
-        stp     xzr, xzr, [x0], #16
-        stp     xzr, xzr, [x0], #16
-        cmp     x0, x6
-        b.lo    1b
-        ldr     x7, =MM_MMUFLAGS
-        /*
-         * Create the identity mapping.
-         */
-        mov     x0, x25                         // idmap_pg_dir
-        ldr     x3, =KERNEL_START
-        add     x3, x3, x28                     // __pa(KERNEL_START)
-        create_pgd_entry x0, x3, x5, x6
-        ldr     x6, =KERNEL_END
-        mov     x5, x3                          // __pa(KERNEL_START)
-        add     x6, x6, x28                     // __pa(KERNEL_END)
-        create_block_map x0, x7, x3, x5, x6
-        /*
-         * Map the kernel image (starting with PHYS_OFFSET).
-         */
-        mov     x0, x26                         // swapper_pg_dir
-        mov     x5, #PAGE_OFFSET
-        create_pgd_entry x0, x5, x3, x6
-        ldr     x6, =KERNEL_END
-        mov     x3, x24                         // phys offset
-        create_block_map x0, x7, x3, x5, x6
-        /*
-         * Map the FDT blob (maximum 2MB; must be within 512MB of
-         * PHYS_OFFSET).
-         */
-        mov     x3, x21                         // FDT phys address
-        and     x3, x3, #~((1 << 21) - 1)       // 2MB aligned
-        mov     x6, #PAGE_OFFSET
-        sub     x5, x3, x24                     // subtract PHYS_OFFSET
-        tst     x5, #~((1 << 29) - 1)           // within 512MB?
-        csel    x21, xzr, x21, ne               // zero the FDT pointer
-        b.ne    1f
-        add     x5, x5, x6                      // __va(FDT blob)
-        add     x6, x5, #1 << 21                // 2MB for the FDT blob
-        sub     x6, x6, #1                      // inclusive range
-        create_block_map x0, x7, x3, x5, x6
-1:
-        /*
-         * Since the page tables have been populated with non-cacheable
-         * accesses (MMU disabled), invalidate the idmap and swapper page
-         * tables again to remove any speculatively loaded cache lines.
-         */
-        mov     x0, x25
-        add     x1, x26, #SWAPPER_DIR_SIZE
-        bl      __inval_cache_range
-        mov     lr, x27
-        ret
-ENDPROC(__create_page_tables)
-        .ltorg
-        .align  3
-        .type   __switch_data, %object
-__switch_data:
-        .quad   __mmap_switched
-        .quad   __bss_start                     // x6
-        .quad   __bss_stop                      // x7
-        .quad   processor_id                    // x4
-        .quad   __fdt_pointer                   // x5
-        .quad   memstart_addr                   // x6
-        .quad   init_thread_union + THREAD_START_SP // sp
-/*
- * The following fragment of code is executed with the MMU on in MMU mode, and
- * uses absolute addresses; this is not position independent.
- */
-__mmap_switched:
-        adr     x3, __switch_data + 8
-        ldp     x6, x7, [x3], #16
-1:      cmp     x6, x7
-        b.hs    2f
-        str     xzr, [x6], #8                   // Clear BSS
-        b       1b
-2:
-        ldp     x4, x5, [x3], #16
-        ldr     x6, [x3], #8
-        ldr     x16, [x3]
-        mov     sp, x16
-        str     x22, [x4]                       // Save processor ID
-        str     x21, [x5]                       // Save FDT pointer
-        str     x24, [x6]                       // Save PHYS_OFFSET
-        mov     x29, #0
-        b       start_kernel
-ENDPROC(__mmap_switched)
-/*
 * Exception handling. Something went wrong and we can't proceed. We ought to
 * tell the user, but since we don't have any guarantee that we're even
 * running on the right architecture, we do virtually nothing.
@@ -715,22 +756,3 @@ __lookup_processor_type_data:
        .quad   .
        .quad   cpu_table
        .size   __lookup_processor_type_data, . - __lookup_processor_type_data
-/*
- * Determine validity of the x21 FDT pointer.
- * The dtb must be 8-byte aligned and live in the first 512M of memory.
- */
-__vet_fdt:
-        tst     x21, #0x7
-        b.ne    1f
-        cmp     x21, x24
-        b.lt    1f
-        mov     x0, #(1 << 29)
-        add     x0, x0, x24
-        cmp     x21, x0
-        b.ge    1f
-        ret
-1:
-        mov     x21, #0
-        ret
-ENDPROC(__vet_fdt)
diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c
index 8cd27fedc8b6..7e9327a0986d 100644
--- a/arch/arm64/kernel/insn.c
+++ b/arch/arm64/kernel/insn.c
@@ -960,3 +960,29 @@ u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
        return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
 }
+bool aarch32_insn_is_wide(u32 insn)
+{
+        return insn >= 0xe800;
+}
+/*
+ * Macros/defines for extracting register numbers from instruction.
+ */
+u32 aarch32_insn_extract_reg_num(u32 insn, int offset)
+{
+        return (insn & (0xf << offset)) >> offset;
+}
+#define OPC2_MASK       0x7
+#define OPC2_OFFSET     5
+u32 aarch32_insn_mcr_extract_opc2(u32 insn)
+{
+        return (insn & (OPC2_MASK << OPC2_OFFSET)) >> OPC2_OFFSET;
+}
+#define CRM_MASK        0xf
+u32 aarch32_insn_mcr_extract_crm(u32 insn)
+{
+        return insn & CRM_MASK;
+}
diff --git a/arch/arm64/kernel/io.c b/arch/arm64/kernel/io.c
index 7d37ead4d199..354be2a872ae 100644
--- a/arch/arm64/kernel/io.c
+++ b/arch/arm64/kernel/io.c
@@ -25,12 +25,26 @@
 */
 void __memcpy_fromio(void *to, const volatile void __iomem *from, size_t count)
 {
-        unsigned char *t = to;
+        while (count && (!IS_ALIGNED((unsigned long)from, 8) ||
-        while (count) {
+                         !IS_ALIGNED((unsigned long)to, 8))) {
+                *(u8 *)to = __raw_readb(from);
+                from++;
+                to++;
                count--;
-                *t = readb(from);
+        }
-                t++;
+        while (count >= 8) {
+                *(u64 *)to = __raw_readq(from);
+                from += 8;
+                to += 8;
+                count -= 8;
+        }
+        while (count) {
+                *(u8 *)to = __raw_readb(from);
                from++;
+                to++;
+                count--;
        }
 }
 EXPORT_SYMBOL(__memcpy_fromio);
@@ -40,12 +54,26 @@ EXPORT_SYMBOL(__memcpy_fromio);
 */
 void __memcpy_toio(volatile void __iomem *to, const void *from, size_t count)
 {
-        const unsigned char *f = from;
+        while (count && (!IS_ALIGNED((unsigned long)to, 8) ||
-        while (count) {
+                         !IS_ALIGNED((unsigned long)from, 8))) {
+                __raw_writeb(*(volatile u8 *)from, to);
+                from++;
+                to++;
                count--;
-                writeb(*f, to);
+        }
-                f++;
+        while (count >= 8) {
+                __raw_writeq(*(volatile u64 *)from, to);
+                from += 8;
+                to += 8;
+                count -= 8;
+        }
+        while (count) {
+                __raw_writeb(*(volatile u8 *)from, to);
+                from++;
                to++;
+                count--;
        }
 }
 EXPORT_SYMBOL(__memcpy_toio);
@@ -55,10 +83,28 @@ EXPORT_SYMBOL(__memcpy_toio);
 */
 void __memset_io(volatile void __iomem *dst, int c, size_t count)
 {
-        while (count) {
+        u64 qc = (u8)c;
+        qc |= qc << 8;
+        qc |= qc << 16;
+        qc |= qc << 32;
+        while (count && !IS_ALIGNED((unsigned long)dst, 8)) {
+                __raw_writeb(c, dst);
+                dst++;
                count--;
-                writeb(c, dst);
+        }
+        while (count >= 8) {
+                __raw_writeq(qc, dst);
+                dst += 8;
+                count -= 8;
+        }
+        while (count) {
+                __raw_writeb(c, dst);
                dst++;
+                count--;
        }
 }
 EXPORT_SYMBOL(__memset_io);
diff --git a/arch/arm64/kernel/irq.c b/arch/arm64/kernel/irq.c
index 071a6ec13bd8..240b75c0e94f 100644
--- a/arch/arm64/kernel/irq.c
+++ b/arch/arm64/kernel/irq.c
@@ -40,6 +40,8 @@ int arch_show_interrupts(struct seq_file *p, int prec)
        return 0;
 }
+void (*handle_arch_irq)(struct pt_regs *) = NULL;
 void __init set_handle_irq(void (*handle_irq)(struct pt_regs *))
 {
        if (handle_arch_irq)
diff --git a/arch/arm64/kernel/jump_label.c b/arch/arm64/kernel/jump_label.c
index 263a166291fb..4f1fec7a46db 100644
--- a/arch/arm64/kernel/jump_label.c
+++ b/arch/arm64/kernel/jump_label.c
@@ -22,9 +22,8 @@
 #ifdef HAVE_JUMP_LABEL
-static void __arch_jump_label_transform(struct jump_entry *entry,
+void arch_jump_label_transform(struct jump_entry *entry,
-                                        enum jump_label_type type,
+                               enum jump_label_type type)
-                                        bool is_static)
 {
        void *addr = (void *)entry->code;
        u32 insn;
@@ -37,22 +36,18 @@ static void __arch_jump_label_transform(struct jump_entry *entry,
                insn = aarch64_insn_gen_nop();
        }
-        if (is_static)
+        aarch64_insn_patch_text(&addr, &insn, 1);
-                aarch64_insn_patch_text_nosync(addr, insn);
-        else
-                aarch64_insn_patch_text(&addr, &insn, 1);
-}
-void arch_jump_label_transform(struct jump_entry *entry,
-                               enum jump_label_type type)
-{
-        __arch_jump_label_transform(entry, type, false);
 }
 void arch_jump_label_transform_static(struct jump_entry *entry,
                                      enum jump_label_type type)
 {
-        __arch_jump_label_transform(entry, type, true);
+        /*
+         * We use the architected A64 NOP in arch_static_branch, so there's no
+         * need to patch an identical A64 NOP over the top of it here. The core
+         * will call arch_jump_label_transform from a module notifier if the
+         * NOP needs to be replaced by a branch.
+         */
 }
 #endif  /* HAVE_JUMP_LABEL */
diff --git a/arch/arm64/kernel/module.c b/arch/arm64/kernel/module.c
index 1eb1cc955139..fd027b101de5 100644
--- a/arch/arm64/kernel/module.c
+++ b/arch/arm64/kernel/module.c
@@ -26,6 +26,7 @@
 #include <linux/moduleloader.h>
 #include <linux/vmalloc.h>
 #include <asm/insn.h>
+#include <asm/sections.h>
 #define AARCH64_INSN_IMM_MOVNZ          AARCH64_INSN_IMM_MAX
 #define AARCH64_INSN_IMM_MOVK           AARCH64_INSN_IMM_16
@@ -394,3 +395,20 @@ overflow:
               me->name, (int)ELF64_R_TYPE(rel[i].r_info), val);
        return -ENOEXEC;
 }
+int module_finalize(const Elf_Ehdr *hdr,
+                    const Elf_Shdr *sechdrs,
+                    struct module *me)
+{
+        const Elf_Shdr *s, *se;
+        const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
+        for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) {
+                if (strcmp(".altinstructions", secstrs + s->sh_name) == 0) {
+                        apply_alternatives((void *)s->sh_addr, s->sh_size);
+                        return 0;
+                }
+        }
+        return 0;
+}
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index aa29ecb4f800..25a5308744b1 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -169,8 +169,14 @@ armpmu_event_set_period(struct perf_event *event,
                ret = 1;
        }
-        if (left > (s64)armpmu->max_period)
+        /*
-                left = armpmu->max_period;
+         * Limit the maximum period to prevent the counter value
+         * from overtaking the one we are about to program. In
+         * effect we are reducing max_period to account for
+         * interrupt latency (and we are being very conservative).
+         */
+        if (left > (armpmu->max_period >> 1))
+                left = armpmu->max_period >> 1;
        local64_set(&hwc->prev_count, (u64)-left);
diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c
index 8a4ae8e73213..d882b833dbdb 100644
--- a/arch/arm64/kernel/ptrace.c
+++ b/arch/arm64/kernel/ptrace.c
@@ -27,6 +27,7 @@
 #include <linux/smp.h>
 #include <linux/ptrace.h>
 #include <linux/user.h>
+#include <linux/seccomp.h>
 #include <linux/security.h>
 #include <linux/init.h>
 #include <linux/signal.h>
@@ -551,6 +552,32 @@ static int tls_set(struct task_struct *target, const struct user_regset *regset,
        return ret;
 }
+static int system_call_get(struct task_struct *target,
+                           const struct user_regset *regset,
+                           unsigned int pos, unsigned int count,
+                           void *kbuf, void __user *ubuf)
+{
+        int syscallno = task_pt_regs(target)->syscallno;
+        return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+                                   &syscallno, 0, -1);
+}
+static int system_call_set(struct task_struct *target,
+                           const struct user_regset *regset,
+                           unsigned int pos, unsigned int count,
+                           const void *kbuf, const void __user *ubuf)
+{
+        int syscallno, ret;
+        ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &syscallno, 0, -1);
+        if (ret)
+                return ret;
+        task_pt_regs(target)->syscallno = syscallno;
+        return ret;
+}
 enum aarch64_regset {
        REGSET_GPR,
        REGSET_FPR,
@@ -559,6 +586,7 @@ enum aarch64_regset {
        REGSET_HW_BREAK,
        REGSET_HW_WATCH,
 #endif
+        REGSET_SYSTEM_CALL,
 };
 static const struct user_regset aarch64_regsets[] = {
@@ -608,6 +636,14 @@ static const struct user_regset aarch64_regsets[] = {
                .set = hw_break_set,
        },
 #endif
+        [REGSET_SYSTEM_CALL] = {
+                .core_note_type = NT_ARM_SYSTEM_CALL,
+                .n = 1,
+                .size = sizeof(int),
+                .align = sizeof(int),
+                .get = system_call_get,
+                .set = system_call_set,
+        },
 };
 static const struct user_regset_view user_aarch64_view = {
@@ -1114,6 +1150,10 @@ static void tracehook_report_syscall(struct pt_regs *regs,
 asmlinkage int syscall_trace_enter(struct pt_regs *regs)
 {
+        /* Do the secure computing check first; failures should be fast. */
+        if (secure_computing() == -1)
+                return -1;
        if (test_thread_flag(TIF_SYSCALL_TRACE))
                tracehook_report_syscall(regs, PTRACE_SYSCALL_ENTER);
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index 2437196cc5d4..b80991166754 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -43,12 +43,14 @@
 #include <linux/of_fdt.h>
 #include <linux/of_platform.h>
 #include <linux/efi.h>
+#include <linux/personality.h>
 #include <asm/fixmap.h>
 #include <asm/cpu.h>
 #include <asm/cputype.h>
 #include <asm/elf.h>
 #include <asm/cputable.h>
+#include <asm/cpufeature.h>
 #include <asm/cpu_ops.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
@@ -72,13 +74,15 @@ EXPORT_SYMBOL_GPL(elf_hwcap);
                                 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
                                 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
                                 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
-                                 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV)
+                                 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
+                                 COMPAT_HWCAP_LPAE)
 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
 unsigned int compat_elf_hwcap2 __read_mostly;
 #endif
+DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
 static const char *cpu_name;
-static const char *machine_name;
 phys_addr_t __fdt_pointer __initdata;
 /*
@@ -116,12 +120,16 @@ void __init early_print(const char *str, ...)
 void __init smp_setup_processor_id(void)
 {
+        u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
+        cpu_logical_map(0) = mpidr;
        /*
         * clear __my_cpu_offset on boot CPU to avoid hang caused by
         * using percpu variable early, for example, lockdep will
         * access percpu variable inside lock_release
         */
        set_my_cpu_offset(0);
+        pr_info("Booting Linux on physical CPU 0x%lx\n", (unsigned long)mpidr);
 }
 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
@@ -311,7 +319,7 @@ static void __init setup_machine_fdt(phys_addr_t dt_phys)
                        cpu_relax();
        }
-        machine_name = of_flat_dt_get_machine_name();
+        dump_stack_set_arch_desc("%s (DT)", of_flat_dt_get_machine_name());
 }
 /*
@@ -376,6 +384,7 @@ void __init setup_arch(char **cmdline_p)
        *cmdline_p = boot_command_line;
+        early_fixmap_init();
        early_ioremap_init();
        parse_early_param();
@@ -398,7 +407,6 @@ void __init setup_arch(char **cmdline_p)
        psci_init();
-        cpu_logical_map(0) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
        cpu_read_bootcpu_ops();
 #ifdef CONFIG_SMP
        smp_init_cpus();
@@ -447,14 +455,50 @@ static const char *hwcap_str[] = {
        NULL
 };
+#ifdef CONFIG_COMPAT
+static const char *compat_hwcap_str[] = {
+        "swp",
+        "half",
+        "thumb",
+        "26bit",
+        "fastmult",
+        "fpa",
+        "vfp",
+        "edsp",
+        "java",
+        "iwmmxt",
+        "crunch",
+        "thumbee",
+        "neon",
+        "vfpv3",
+        "vfpv3d16",
+        "tls",
+        "vfpv4",
+        "idiva",
+        "idivt",
+        "vfpd32",
+        "lpae",
+        "evtstrm"
+};
+static const char *compat_hwcap2_str[] = {
+        "aes",
+        "pmull",
+        "sha1",
+        "sha2",
+        "crc32",
+        NULL
+};
+#endif /* CONFIG_COMPAT */
 static int c_show(struct seq_file *m, void *v)
 {
-        int i;
+        int i, j;
-        seq_printf(m, "Processor\t: %s rev %d (%s)\n",
-                   cpu_name, read_cpuid_id() & 15, ELF_PLATFORM);
        for_each_online_cpu(i) {
+                struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
+                u32 midr = cpuinfo->reg_midr;
                /*
                 * glibc reads /proc/cpuinfo to determine the number of
                 * online processors, looking for lines beginning with
@@ -463,24 +507,38 @@ static int c_show(struct seq_file *m, void *v)
 #ifdef CONFIG_SMP
                seq_printf(m, "processor\t: %d\n", i);
 #endif
-        }
-        /* dump out the processor features */
-        seq_puts(m, "Features\t: ");
-        for (i = 0; hwcap_str[i]; i++)
-                if (elf_hwcap & (1 << i))
-                        seq_printf(m, "%s ", hwcap_str[i]);
-        seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
-        seq_printf(m, "CPU architecture: AArch64\n");
-        seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15);
-        seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff);
-        seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
-        seq_puts(m, "\n");
+                /*
+                 * Dump out the common processor features in a single line.
-        seq_printf(m, "Hardware\t: %s\n", machine_name);
+                 * Userspace should read the hwcaps with getauxval(AT_HWCAP)
+                 * rather than attempting to parse this, but there's a body of
+                 * software which does already (at least for 32-bit).
+                 */
+                seq_puts(m, "Features\t:");
+                if (personality(current->personality) == PER_LINUX32) {
+#ifdef CONFIG_COMPAT
+                        for (j = 0; compat_hwcap_str[j]; j++)
+                                if (compat_elf_hwcap & (1 << j))
+                                        seq_printf(m, " %s", compat_hwcap_str[j]);
+                        for (j = 0; compat_hwcap2_str[j]; j++)
+                                if (compat_elf_hwcap2 & (1 << j))
+                                        seq_printf(m, " %s", compat_hwcap2_str[j]);
+#endif /* CONFIG_COMPAT */
+                } else {
+                        for (j = 0; hwcap_str[j]; j++)
+                                if (elf_hwcap & (1 << j))
+                                        seq_printf(m, " %s", hwcap_str[j]);
+                }
+                seq_puts(m, "\n");
+                seq_printf(m, "CPU implementer\t: 0x%02x\n",
+                           MIDR_IMPLEMENTOR(midr));
+                seq_printf(m, "CPU architecture: 8\n");
+                seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
+                seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
+                seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
+        }
        return 0;
 }
diff --git a/arch/arm64/kernel/signal32.c b/arch/arm64/kernel/signal32.c
index 1b9ad02837cf..5a1ba6e80d4e 100644
--- a/arch/arm64/kernel/signal32.c
+++ b/arch/arm64/kernel/signal32.c
@@ -186,6 +186,12 @@ int copy_siginfo_to_user32(compat_siginfo_t __user *to, const siginfo_t *from)
                err |= __put_user(from->si_uid, &to->si_uid);
                err |= __put_user((compat_uptr_t)(unsigned long)from->si_ptr, &to->si_ptr);
                break;
+        case __SI_SYS:
+                err |= __put_user((compat_uptr_t)(unsigned long)
+                                from->si_call_addr, &to->si_call_addr);
+                err |= __put_user(from->si_syscall, &to->si_syscall);
+                err |= __put_user(from->si_arch, &to->si_arch);
+                break;
        default: /* this is just in case for now ... */
                err |= __put_user(from->si_pid, &to->si_pid);
                err |= __put_user(from->si_uid, &to->si_uid);
diff --git a/arch/arm64/kernel/sleep.S b/arch/arm64/kernel/sleep.S
index a564b440416a..ede186cdd452 100644
--- a/arch/arm64/kernel/sleep.S
+++ b/arch/arm64/kernel/sleep.S
@@ -147,14 +147,12 @@ cpu_resume_after_mmu:
        ret
 ENDPROC(cpu_resume_after_mmu)
-        .data
 ENTRY(cpu_resume)
        bl      el2_setup               // if in EL2 drop to EL1 cleanly
 #ifdef CONFIG_SMP
        mrs     x1, mpidr_el1
-        adr     x4, mpidr_hash_ptr
+        adrp    x8, mpidr_hash
-        ldr     x5, [x4]
+        add x8, x8, #:lo12:mpidr_hash // x8 = struct mpidr_hash phys address
-        add     x8, x4, x5              // x8 = struct mpidr_hash phys address
        /* retrieve mpidr_hash members to compute the hash */
        ldr     x2, [x8, #MPIDR_HASH_MASK]
        ldp     w3, w4, [x8, #MPIDR_HASH_SHIFTS]
@@ -164,14 +162,15 @@ ENTRY(cpu_resume)
 #else
        mov     x7, xzr
 #endif
-        adr     x0, sleep_save_sp
+        adrp    x0, sleep_save_sp
+        add     x0, x0, #:lo12:sleep_save_sp
        ldr     x0, [x0, #SLEEP_SAVE_SP_PHYS]
        ldr     x0, [x0, x7, lsl #3]
        /* load sp from context */
        ldr     x2, [x0, #CPU_CTX_SP]
-        adr     x1, sleep_idmap_phys
+        adrp    x1, sleep_idmap_phys
        /* load physical address of identity map page table in x1 */
-        ldr     x1, [x1]
+        ldr     x1, [x1, #:lo12:sleep_idmap_phys]
        mov     sp, x2
        /*
         * cpu_do_resume expects x0 to contain context physical address
@@ -180,26 +179,3 @@ ENTRY(cpu_resume)
        bl      cpu_do_resume           // PC relative jump, MMU off
        b       cpu_resume_mmu          // Resume MMU, never returns
 ENDPROC(cpu_resume)
-        .align 3
-mpidr_hash_ptr:
-        /*
-         * offset of mpidr_hash symbol from current location
-         * used to obtain run-time mpidr_hash address with MMU off
-         */
-        .quad   mpidr_hash - .
-/*
- * physical address of identity mapped page tables
- */
-        .type   sleep_idmap_phys, #object
-ENTRY(sleep_idmap_phys)
-        .quad   0
-/*
- * struct sleep_save_sp {
- *      phys_addr_t *save_ptr_stash;
- *      phys_addr_t save_ptr_stash_phys;
- * };
- */
-        .type   sleep_save_sp, #object
-ENTRY(sleep_save_sp)
-        .space  SLEEP_SAVE_SP_SZ        // struct sleep_save_sp
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index b06d1d90ee8c..7ae6ee085261 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -37,6 +37,7 @@
 #include <linux/of.h>
 #include <linux/irq_work.h>
+#include <asm/alternative.h>
 #include <asm/atomic.h>
 #include <asm/cacheflush.h>
 #include <asm/cpu.h>
@@ -309,6 +310,7 @@ void cpu_die(void)
 void __init smp_cpus_done(unsigned int max_cpus)
 {
        pr_info("SMP: Total of %d processors activated.\n", num_online_cpus());
+        apply_alternatives_all();
 }
 void __init smp_prepare_boot_cpu(void)
diff --git a/arch/arm64/kernel/suspend.c b/arch/arm64/kernel/suspend.c
index 13ad4dbb1615..3771b72b6569 100644
--- a/arch/arm64/kernel/suspend.c
+++ b/arch/arm64/kernel/suspend.c
@@ -126,8 +126,8 @@ int __cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
        return ret;
 }
-extern struct sleep_save_sp sleep_save_sp;
+struct sleep_save_sp sleep_save_sp;
-extern phys_addr_t sleep_idmap_phys;
+phys_addr_t sleep_idmap_phys;
 static int __init cpu_suspend_init(void)
 {
diff --git a/arch/arm64/kernel/sys_compat.c b/arch/arm64/kernel/sys_compat.c
index dc47e53e9e28..28c511b06edf 100644
--- a/arch/arm64/kernel/sys_compat.c
+++ b/arch/arm64/kernel/sys_compat.c
@@ -28,29 +28,39 @@
 #include <asm/cacheflush.h>
 #include <asm/unistd.h>
-static inline void
+static long
-do_compat_cache_op(unsigned long start, unsigned long end, int flags)
+__do_compat_cache_op(unsigned long start, unsigned long end)
 {
-        struct mm_struct *mm = current->active_mm;
+        long ret;
-        struct vm_area_struct *vma;
-        if (end < start || flags)
+        do {
-                return;
+                unsigned long chunk = min(PAGE_SIZE, end - start);
-        down_read(&mm->mmap_sem);
+                if (fatal_signal_pending(current))
-        vma = find_vma(mm, start);
+                        return 0;
-        if (vma && vma->vm_start < end) {
-                if (start < vma->vm_start)
+                ret = __flush_cache_user_range(start, start + chunk);
-                        start = vma->vm_start;
+                if (ret)
-                if (end > vma->vm_end)
+                        return ret;
-                        end = vma->vm_end;
-                up_read(&mm->mmap_sem);
+                cond_resched();
-                __flush_cache_user_range(start & PAGE_MASK, PAGE_ALIGN(end));
+                start += chunk;
-                return;
+        } while (start < end);
-        }
-        up_read(&mm->mmap_sem);
+        return 0;
 }
+static inline long
+do_compat_cache_op(unsigned long start, unsigned long end, int flags)
+{
+        if (end < start || flags)
+                return -EINVAL;
+        if (!access_ok(VERIFY_READ, start, end - start))
+                return -EFAULT;
+        return __do_compat_cache_op(start, end);
+}
 /*
 * Handle all unrecognised system calls.
 */
@@ -74,8 +84,7 @@ long compat_arm_syscall(struct pt_regs *regs)
         * the specified region).
         */
        case __ARM_NR_compat_cacheflush:
-                do_compat_cache_op(regs->regs[0], regs->regs[1], regs->regs[2]);
+                return do_compat_cache_op(regs->regs[0], regs->regs[1], regs->regs[2]);
-                return 0;
        case __ARM_NR_compat_set_tls:
                current->thread.tp_value = regs->regs[0];
diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c
index b6ee26b0939a..fcb8f7b42271 100644
--- a/arch/arm64/kernel/topology.c
+++ b/arch/arm64/kernel/topology.c
@@ -255,12 +255,15 @@ void store_cpu_topology(unsigned int cpuid)
                /* Multiprocessor system : Multi-threads per core */
                cpuid_topo->thread_id  = MPIDR_AFFINITY_LEVEL(mpidr, 0);
                cpuid_topo->core_id    = MPIDR_AFFINITY_LEVEL(mpidr, 1);
-                cpuid_topo->cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
+                cpuid_topo->cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 2) |
+                                         MPIDR_AFFINITY_LEVEL(mpidr, 3) << 8;
        } else {
                /* Multiprocessor system : Single-thread per core */
                cpuid_topo->thread_id  = -1;
                cpuid_topo->core_id    = MPIDR_AFFINITY_LEVEL(mpidr, 0);
-                cpuid_topo->cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+                cpuid_topo->cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 1) |
+                                         MPIDR_AFFINITY_LEVEL(mpidr, 2) << 8 |
+                                         MPIDR_AFFINITY_LEVEL(mpidr, 3) << 16;
        }
        pr_debug("CPU%u: cluster %d core %d thread %d mpidr %#016llx\n",
diff --git a/arch/arm64/kernel/trace-events-emulation.h b/arch/arm64/kernel/trace-events-emulation.h
new file mode 100644
index 000000000000..ae1dd598ea65
--- /dev/null
+++ b/arch/arm64/kernel/trace-events-emulation.h
@@ -0,0 +1,35 @@
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM emulation
+#if !defined(_TRACE_EMULATION_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_EMULATION_H
+#include <linux/tracepoint.h>
+TRACE_EVENT(instruction_emulation,
+        TP_PROTO(const char *instr, u64 addr),
+        TP_ARGS(instr, addr),
+        TP_STRUCT__entry(
+                __string(instr, instr)
+                __field(u64, addr)
+        ),
+        TP_fast_assign(
+                __assign_str(instr, instr);
+                __entry->addr = addr;
+        ),
+        TP_printk("instr=\"%s\" addr=0x%llx", __get_str(instr), __entry->addr)
+);
+#endif /* _TRACE_EMULATION_H */
+/* This part must be outside protection */
+#undef TRACE_INCLUDE_PATH
+#undef TRACE_INCLUDE_FILE
+#define TRACE_INCLUDE_PATH .
+#define TRACE_INCLUDE_FILE trace-events-emulation
+#include <trace/define_trace.h>
diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index de1b085e7963..0a801e3743d5 100644
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -259,6 +259,69 @@ void arm64_notify_die(const char *str, struct pt_regs *regs,
        }
 }
+static LIST_HEAD(undef_hook);
+static DEFINE_RAW_SPINLOCK(undef_lock);
+void register_undef_hook(struct undef_hook *hook)
+{
+        unsigned long flags;
+        raw_spin_lock_irqsave(&undef_lock, flags);
+        list_add(&hook->node, &undef_hook);
+        raw_spin_unlock_irqrestore(&undef_lock, flags);
+}
+void unregister_undef_hook(struct undef_hook *hook)
+{
+        unsigned long flags;
+        raw_spin_lock_irqsave(&undef_lock, flags);
+        list_del(&hook->node);
+        raw_spin_unlock_irqrestore(&undef_lock, flags);
+}
+static int call_undef_hook(struct pt_regs *regs)
+{
+        struct undef_hook *hook;
+        unsigned long flags;
+        u32 instr;
+        int (*fn)(struct pt_regs *regs, u32 instr) = NULL;
+        void __user *pc = (void __user *)instruction_pointer(regs);
+        if (!user_mode(regs))
+                return 1;
+        if (compat_thumb_mode(regs)) {
+                /* 16-bit Thumb instruction */
+                if (get_user(instr, (u16 __user *)pc))
+                        goto exit;
+                instr = le16_to_cpu(instr);
+                if (aarch32_insn_is_wide(instr)) {
+                        u32 instr2;
+                        if (get_user(instr2, (u16 __user *)(pc + 2)))
+                                goto exit;
+                        instr2 = le16_to_cpu(instr2);
+                        instr = (instr << 16) | instr2;
+                }
+        } else {
+                /* 32-bit ARM instruction */
+                if (get_user(instr, (u32 __user *)pc))
+                        goto exit;
+                instr = le32_to_cpu(instr);
+        }
+        raw_spin_lock_irqsave(&undef_lock, flags);
+        list_for_each_entry(hook, &undef_hook, node)
+                if ((instr & hook->instr_mask) == hook->instr_val &&
+                        (regs->pstate & hook->pstate_mask) == hook->pstate_val)
+                        fn = hook->fn;
+        raw_spin_unlock_irqrestore(&undef_lock, flags);
+exit:
+        return fn ? fn(regs, instr) : 1;
+}
 asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
 {
        siginfo_t info;
@@ -268,6 +331,9 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
        if (!aarch32_break_handler(regs))
                return;
+        if (call_undef_hook(regs) == 0)
+                return;
        if (show_unhandled_signals && unhandled_signal(current, SIGILL) &&
            printk_ratelimit()) {
                pr_info("%s[%d]: undefined instruction: pc=%p\n",
diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
index edf8715ba39b..9965ec87cbec 100644
--- a/arch/arm64/kernel/vmlinux.lds.S
+++ b/arch/arm64/kernel/vmlinux.lds.S
@@ -11,8 +11,9 @@
 #include "image.h"
-#define ARM_EXIT_KEEP(x)
+/* .exit.text needed in case of alternative patching */
-#define ARM_EXIT_DISCARD(x)     x
+#define ARM_EXIT_KEEP(x)        x
+#define ARM_EXIT_DISCARD(x)
 OUTPUT_ARCH(aarch64)
 ENTRY(_text)
@@ -32,6 +33,22 @@ jiffies = jiffies_64;
        *(.hyp.text)                                    \
        VMLINUX_SYMBOL(__hyp_text_end) = .;
+/*
+ * The size of the PE/COFF section that covers the kernel image, which
+ * runs from stext to _edata, must be a round multiple of the PE/COFF
+ * FileAlignment, which we set to its minimum value of 0x200. 'stext'
+ * itself is 4 KB aligned, so padding out _edata to a 0x200 aligned
+ * boundary should be sufficient.
+ */
+PECOFF_FILE_ALIGNMENT = 0x200;
+#ifdef CONFIG_EFI
+#define PECOFF_EDATA_PADDING    \
+        .pecoff_edata_padding : { BYTE(0); . = ALIGN(PECOFF_FILE_ALIGNMENT); }
+#else
+#define PECOFF_EDATA_PADDING
+#endif
 SECTIONS
 {
        /*
@@ -100,9 +117,21 @@ SECTIONS
        . = ALIGN(PAGE_SIZE);
        __init_end = .;
+        . = ALIGN(4);
+        .altinstructions : {
+                __alt_instructions = .;
+                *(.altinstructions)
+                __alt_instructions_end = .;
+        }
+        .altinstr_replacement : {
+                *(.altinstr_replacement)
+        }
+        . = ALIGN(PAGE_SIZE);
        _data = .;
        _sdata = .;
        RW_DATA_SECTION(64, PAGE_SIZE, THREAD_SIZE)
+        PECOFF_EDATA_PADDING
        _edata = .;
        BSS_SECTION(0, 0, 0)
diff --git a/arch/arm64/kvm/hyp.S b/arch/arm64/kvm/hyp.S
index b72aa9f9215c..fbe909fb0a1a 100644
--- a/arch/arm64/kvm/hyp.S
+++ b/arch/arm64/kvm/hyp.S
@@ -761,10 +761,10 @@
 .macro activate_traps
        ldr     x2, [x0, #VCPU_HCR_EL2]
        msr     hcr_el2, x2
-        ldr     x2, =(CPTR_EL2_TTA)
+        mov     x2, #CPTR_EL2_TTA
        msr     cptr_el2, x2
-        ldr     x2, =(1 << 15)  // Trap CP15 Cr=15
+        mov     x2, #(1 << 15)  // Trap CP15 Cr=15
        msr     hstr_el2, x2
        mrs     x2, mdcr_el2
diff --git a/arch/arm64/mm/Makefile b/arch/arm64/mm/Makefile
index c56179ed2c09..773d37a14039 100644
--- a/arch/arm64/mm/Makefile
+++ b/arch/arm64/mm/Makefile
@@ -3,3 +3,4 @@ obj-y				:= dma-mapping.o extable.o fault.o init.o \
                                   ioremap.o mmap.o pgd.o mmu.o \
                                   context.o proc.o pageattr.o
 obj-$(CONFIG_HUGETLB_PAGE)      += hugetlbpage.o
+obj-$(CONFIG_ARM64_PTDUMP)      += dump.o
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
index 23663837acff..2560e1e1562e 100644
--- a/arch/arm64/mm/cache.S
+++ b/arch/arm64/mm/cache.S
@@ -17,9 +17,12 @@
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
+#include <linux/errno.h>
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
+#include <asm/cpufeature.h>
+#include <asm/alternative-asm.h>
 #include "proc-macros.S"
@@ -138,9 +141,12 @@ USER(9f, ic	ivau, x4	)		// invalidate I line PoU
        add     x4, x4, x2
        cmp     x4, x1
        b.lo    1b
-9:                                              // ignore any faulting cache operation
        dsb     ish
        isb
+        mov     x0, #0
+        ret
+9:
+        mov     x0, #-EFAULT
        ret
 ENDPROC(flush_icache_range)
 ENDPROC(__flush_cache_user_range)
@@ -210,7 +216,7 @@ __dma_clean_range:
        dcache_line_size x2, x3
        sub     x3, x2, #1
        bic     x0, x0, x3
-1:      dc      cvac, x0                        // clean D / U line
+1:      alternative_insn "dc cvac, x0", "dc civac, x0", ARM64_WORKAROUND_CLEAN_CACHE
        add     x0, x0, x2
        cmp     x0, x1
        b.lo    1b
diff --git a/arch/arm64/mm/dump.c b/arch/arm64/mm/dump.c
new file mode 100644
index 000000000000..bf69601be546
--- /dev/null
+++ b/arch/arm64/mm/dump.c
@@ -0,0 +1,332 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Debug helper to dump the current kernel pagetables of the system
+ * so that we can see what the various memory ranges are set to.
+ *
+ * Derived from x86 and arm implementation:
+ * (C) Copyright 2008 Intel Corporation
+ *
+ * Author: Arjan van de Ven <arjan@linux.intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2
+ * of the License.
+ */
+#include <linux/debugfs.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/seq_file.h>
+#include <asm/fixmap.h>
+#include <asm/pgtable.h>
+#define LOWEST_ADDR     (UL(0xffffffffffffffff) << VA_BITS)
+struct addr_marker {
+        unsigned long start_address;
+        const char *name;
+};
+enum address_markers_idx {
+        VMALLOC_START_NR = 0,
+        VMALLOC_END_NR,
+#ifdef CONFIG_SPARSEMEM_VMEMMAP
+        VMEMMAP_START_NR,
+        VMEMMAP_END_NR,
+#endif
+        PCI_START_NR,
+        PCI_END_NR,
+        FIXADDR_START_NR,
+        FIXADDR_END_NR,
+        MODULES_START_NR,
+        MODUELS_END_NR,
+        KERNEL_SPACE_NR,
+};
+static struct addr_marker address_markers[] = {
+        { VMALLOC_START,        "vmalloc() Area" },
+        { VMALLOC_END,          "vmalloc() End" },
+#ifdef CONFIG_SPARSEMEM_VMEMMAP
+        { 0,                    "vmemmap start" },
+        { 0,                    "vmemmap end" },
+#endif
+        { (unsigned long) PCI_IOBASE,           "PCI I/O start" },
+        { (unsigned long) PCI_IOBASE + SZ_16M,  "PCI I/O end" },
+        { FIXADDR_START,        "Fixmap start" },
+        { FIXADDR_TOP,          "Fixmap end" },
+        { MODULES_VADDR,        "Modules start" },
+        { MODULES_END,          "Modules end" },
+        { PAGE_OFFSET,          "Kernel Mapping" },
+        { -1,                   NULL },
+};
+struct pg_state {
+        struct seq_file *seq;
+        const struct addr_marker *marker;
+        unsigned long start_address;
+        unsigned level;
+        u64 current_prot;
+};
+struct prot_bits {
+        u64             mask;
+        u64             val;
+        const char      *set;
+        const char      *clear;
+};
+static const struct prot_bits pte_bits[] = {
+        {
+                .mask   = PTE_USER,
+                .val    = PTE_USER,
+                .set    = "USR",
+                .clear  = "   ",
+        }, {
+                .mask   = PTE_RDONLY,
+                .val    = PTE_RDONLY,
+                .set    = "ro",
+                .clear  = "RW",
+        }, {
+                .mask   = PTE_PXN,
+                .val    = PTE_PXN,
+                .set    = "NX",
+                .clear  = "x ",
+        }, {
+                .mask   = PTE_SHARED,
+                .val    = PTE_SHARED,
+                .set    = "SHD",
+                .clear  = "   ",
+        }, {
+                .mask   = PTE_AF,
+                .val    = PTE_AF,
+                .set    = "AF",
+                .clear  = "  ",
+        }, {
+                .mask   = PTE_NG,
+                .val    = PTE_NG,
+                .set    = "NG",
+                .clear  = "  ",
+        }, {
+                .mask   = PTE_UXN,
+                .val    = PTE_UXN,
+                .set    = "UXN",
+        }, {
+                .mask   = PTE_ATTRINDX_MASK,
+                .val    = PTE_ATTRINDX(MT_DEVICE_nGnRnE),
+                .set    = "DEVICE/nGnRnE",
+        }, {
+                .mask   = PTE_ATTRINDX_MASK,
+                .val    = PTE_ATTRINDX(MT_DEVICE_nGnRE),
+                .set    = "DEVICE/nGnRE",
+        }, {
+                .mask   = PTE_ATTRINDX_MASK,
+                .val    = PTE_ATTRINDX(MT_DEVICE_GRE),
+                .set    = "DEVICE/GRE",
+        }, {
+                .mask   = PTE_ATTRINDX_MASK,
+                .val    = PTE_ATTRINDX(MT_NORMAL_NC),
+                .set    = "MEM/NORMAL-NC",
+        }, {
+                .mask   = PTE_ATTRINDX_MASK,
+                .val    = PTE_ATTRINDX(MT_NORMAL),
+                .set    = "MEM/NORMAL",
+        }
+};
+struct pg_level {
+        const struct prot_bits *bits;
+        size_t num;
+        u64 mask;
+};
+static struct pg_level pg_level[] = {
+        {
+        }, { /* pgd */
+                .bits   = pte_bits,
+                .num    = ARRAY_SIZE(pte_bits),
+        }, { /* pud */
+                .bits   = pte_bits,
+                .num    = ARRAY_SIZE(pte_bits),
+        }, { /* pmd */
+                .bits   = pte_bits,
+                .num    = ARRAY_SIZE(pte_bits),
+        }, { /* pte */
+                .bits   = pte_bits,
+                .num    = ARRAY_SIZE(pte_bits),
+        },
+};
+static void dump_prot(struct pg_state *st, const struct prot_bits *bits,
+                        size_t num)
+{
+        unsigned i;
+        for (i = 0; i < num; i++, bits++) {
+                const char *s;
+                if ((st->current_prot & bits->mask) == bits->val)
+                        s = bits->set;
+                else
+                        s = bits->clear;
+                if (s)
+                        seq_printf(st->seq, " %s", s);
+        }
+}
+static void note_page(struct pg_state *st, unsigned long addr, unsigned level,
+                                u64 val)
+{
+        static const char units[] = "KMGTPE";
+        u64 prot = val & pg_level[level].mask;
+        if (addr < LOWEST_ADDR)
+                return;
+        if (!st->level) {
+                st->level = level;
+                st->current_prot = prot;
+                st->start_address = addr;
+                seq_printf(st->seq, "---[ %s ]---\n", st->marker->name);
+        } else if (prot != st->current_prot || level != st->level ||
+                   addr >= st->marker[1].start_address) {
+                const char *unit = units;
+                unsigned long delta;
+                if (st->current_prot) {
+                        seq_printf(st->seq, "0x%16lx-0x%16lx   ",
+                                   st->start_address, addr);
+                        delta = (addr - st->start_address) >> 10;
+                        while (!(delta & 1023) && unit[1]) {
+                                delta >>= 10;
+                                unit++;
+                        }
+                        seq_printf(st->seq, "%9lu%c", delta, *unit);
+                        if (pg_level[st->level].bits)
+                                dump_prot(st, pg_level[st->level].bits,
+                                          pg_level[st->level].num);
+                        seq_puts(st->seq, "\n");
+                }
+                if (addr >= st->marker[1].start_address) {
+                        st->marker++;
+                        seq_printf(st->seq, "---[ %s ]---\n", st->marker->name);
+                }
+                st->start_address = addr;
+                st->current_prot = prot;
+                st->level = level;
+        }
+        if (addr >= st->marker[1].start_address) {
+                st->marker++;
+                seq_printf(st->seq, "---[ %s ]---\n", st->marker->name);
+        }
+}
+static void walk_pte(struct pg_state *st, pmd_t *pmd, unsigned long start)
+{
+        pte_t *pte = pte_offset_kernel(pmd, 0);
+        unsigned long addr;
+        unsigned i;
+        for (i = 0; i < PTRS_PER_PTE; i++, pte++) {
+                addr = start + i * PAGE_SIZE;
+                note_page(st, addr, 4, pte_val(*pte));
+        }
+}
+static void walk_pmd(struct pg_state *st, pud_t *pud, unsigned long start)
+{
+        pmd_t *pmd = pmd_offset(pud, 0);
+        unsigned long addr;
+        unsigned i;
+        for (i = 0; i < PTRS_PER_PMD; i++, pmd++) {
+                addr = start + i * PMD_SIZE;
+                if (pmd_none(*pmd) || pmd_sect(*pmd) || pmd_bad(*pmd))
+                        note_page(st, addr, 3, pmd_val(*pmd));
+                else
+                        walk_pte(st, pmd, addr);
+        }
+}
+static void walk_pud(struct pg_state *st, pgd_t *pgd, unsigned long start)
+{
+        pud_t *pud = pud_offset(pgd, 0);
+        unsigned long addr;
+        unsigned i;
+        for (i = 0; i < PTRS_PER_PUD; i++, pud++) {
+                addr = start + i * PUD_SIZE;
+                if (pud_none(*pud) || pud_sect(*pud) || pud_bad(*pud))
+                        note_page(st, addr, 2, pud_val(*pud));
+                else
+                        walk_pmd(st, pud, addr);
+        }
+}
+static void walk_pgd(struct pg_state *st, struct mm_struct *mm, unsigned long start)
+{
+        pgd_t *pgd = pgd_offset(mm, 0);
+        unsigned i;
+        unsigned long addr;
+        for (i = 0; i < PTRS_PER_PGD; i++, pgd++) {
+                addr = start + i * PGDIR_SIZE;
+                if (pgd_none(*pgd) || pgd_bad(*pgd))
+                        note_page(st, addr, 1, pgd_val(*pgd));
+                else
+                        walk_pud(st, pgd, addr);
+        }
+}
+static int ptdump_show(struct seq_file *m, void *v)
+{
+        struct pg_state st = {
+                .seq = m,
+                .marker = address_markers,
+        };
+        walk_pgd(&st, &init_mm, LOWEST_ADDR);
+        note_page(&st, 0, 0, 0);
+        return 0;
+}
+static int ptdump_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, ptdump_show, NULL);
+}
+static const struct file_operations ptdump_fops = {
+        .open           = ptdump_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+static int ptdump_init(void)
+{
+        struct dentry *pe;
+        unsigned i, j;
+        for (i = 0; i < ARRAY_SIZE(pg_level); i++)
+                if (pg_level[i].bits)
+                        for (j = 0; j < pg_level[i].num; j++)
+                                pg_level[i].mask |= pg_level[i].bits[j].mask;
+        address_markers[VMEMMAP_START_NR].start_address =
+                                (unsigned long)virt_to_page(PAGE_OFFSET);
+        address_markers[VMEMMAP_END_NR].start_address =
+                                (unsigned long)virt_to_page(high_memory);
+        pe = debugfs_create_file("kernel_page_tables", 0400, NULL, NULL,
+                                 &ptdump_fops);
+        return pe ? 0 : -ENOMEM;
+}
+device_initcall(ptdump_init);
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index 41cb6d3d6075..c11cd27ca8f5 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -380,7 +380,7 @@ static struct fault_info {
        { do_bad,               SIGBUS,  0,             "level 1 address size fault"    },
        { do_bad,               SIGBUS,  0,             "level 2 address size fault"    },
        { do_bad,               SIGBUS,  0,             "level 3 address size fault"    },
-        { do_translation_fault, SIGSEGV, SEGV_MAPERR,   "input address range fault"     },
+        { do_translation_fault, SIGSEGV, SEGV_MAPERR,   "level 0 translation fault"     },
        { do_translation_fault, SIGSEGV, SEGV_MAPERR,   "level 1 translation fault"     },
        { do_translation_fault, SIGSEGV, SEGV_MAPERR,   "level 2 translation fault"     },
        { do_page_fault,        SIGSEGV, SEGV_MAPERR,   "level 3 translation fault"     },
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index 494297c698ca..bac492c12fcc 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -39,6 +39,7 @@
 #include <asm/setup.h>
 #include <asm/sizes.h>
 #include <asm/tlb.h>
+#include <asm/alternative.h>
 #include "mm.h"
@@ -325,6 +326,7 @@ void __init mem_init(void)
 void free_initmem(void)
 {
        free_initmem_default(0);
+        free_alternatives_memory();
 }
 #ifdef CONFIG_BLK_DEV_INITRD
diff --git a/arch/arm64/mm/ioremap.c b/arch/arm64/mm/ioremap.c
index 4a07630a6616..cbb99c8f1e04 100644
--- a/arch/arm64/mm/ioremap.c
+++ b/arch/arm64/mm/ioremap.c
@@ -103,97 +103,10 @@ void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size)
 }
 EXPORT_SYMBOL(ioremap_cache);
-static pte_t bm_pte[PTRS_PER_PTE] __page_aligned_bss;
+/*
-#if CONFIG_ARM64_PGTABLE_LEVELS > 2
+ * Must be called after early_fixmap_init
-static pmd_t bm_pmd[PTRS_PER_PMD] __page_aligned_bss;
+ */
-#endif
-#if CONFIG_ARM64_PGTABLE_LEVELS > 3
-static pud_t bm_pud[PTRS_PER_PUD] __page_aligned_bss;
-#endif
-static inline pud_t * __init early_ioremap_pud(unsigned long addr)
-{
-        pgd_t *pgd;
-        pgd = pgd_offset_k(addr);
-        BUG_ON(pgd_none(*pgd) || pgd_bad(*pgd));
-        return pud_offset(pgd, addr);
-}
-static inline pmd_t * __init early_ioremap_pmd(unsigned long addr)
-{
-        pud_t *pud = early_ioremap_pud(addr);
-        BUG_ON(pud_none(*pud) || pud_bad(*pud));
-        return pmd_offset(pud, addr);
-}
-static inline pte_t * __init early_ioremap_pte(unsigned long addr)
-{
-        pmd_t *pmd = early_ioremap_pmd(addr);
-        BUG_ON(pmd_none(*pmd) || pmd_bad(*pmd));
-        return pte_offset_kernel(pmd, addr);
-}
 void __init early_ioremap_init(void)
 {
-        pgd_t *pgd;
-        pud_t *pud;
-        pmd_t *pmd;
-        unsigned long addr = fix_to_virt(FIX_BTMAP_BEGIN);
-        pgd = pgd_offset_k(addr);
-        pgd_populate(&init_mm, pgd, bm_pud);
-        pud = pud_offset(pgd, addr);
-        pud_populate(&init_mm, pud, bm_pmd);
-        pmd = pmd_offset(pud, addr);
-        pmd_populate_kernel(&init_mm, pmd, bm_pte);
-        /*
-         * The boot-ioremap range spans multiple pmds, for which
-         * we are not prepared:
-         */
-        BUILD_BUG_ON((__fix_to_virt(FIX_BTMAP_BEGIN) >> PMD_SHIFT)
-                     != (__fix_to_virt(FIX_BTMAP_END) >> PMD_SHIFT));
-        if (pmd != early_ioremap_pmd(fix_to_virt(FIX_BTMAP_END))) {
-                WARN_ON(1);
-                pr_warn("pmd %p != %p\n",
-                        pmd, early_ioremap_pmd(fix_to_virt(FIX_BTMAP_END)));
-                pr_warn("fix_to_virt(FIX_BTMAP_BEGIN): %08lx\n",
-                        fix_to_virt(FIX_BTMAP_BEGIN));
-                pr_warn("fix_to_virt(FIX_BTMAP_END):   %08lx\n",
-                        fix_to_virt(FIX_BTMAP_END));
-                pr_warn("FIX_BTMAP_END:       %d\n", FIX_BTMAP_END);
-                pr_warn("FIX_BTMAP_BEGIN:     %d\n",
-                        FIX_BTMAP_BEGIN);
-        }
        early_ioremap_setup();
 }
-void __init __early_set_fixmap(enum fixed_addresses idx,
-                               phys_addr_t phys, pgprot_t flags)
-{
-        unsigned long addr = __fix_to_virt(idx);
-        pte_t *pte;
-        if (idx >= __end_of_fixed_addresses) {
-                BUG();
-                return;
-        }
-        pte = early_ioremap_pte(addr);
-        if (pgprot_val(flags))
-                set_pte(pte, pfn_pte(phys >> PAGE_SHIFT, flags));
-        else {
-                pte_clear(&init_mm, addr, pte);
-                flush_tlb_kernel_range(addr, addr+PAGE_SIZE);
-        }
-}
diff --git a/arch/arm64/mm/mm.h b/arch/arm64/mm/mm.h
index d519f4f50c8c..50c3351df9c7 100644
--- a/arch/arm64/mm/mm.h
+++ b/arch/arm64/mm/mm.h
@@ -1,2 +1 @@
 extern void __init bootmem_init(void);
-extern void __init arm64_swiotlb_init(void);
diff --git a/arch/arm64/mm/mmap.c b/arch/arm64/mm/mmap.c
index 1d73662f00ff..54922d1275b8 100644
--- a/arch/arm64/mm/mmap.c
+++ b/arch/arm64/mm/mmap.c
@@ -47,22 +47,14 @@ static int mmap_is_legacy(void)
        return sysctl_legacy_va_layout;
 }
-/*
- * Since get_random_int() returns the same value within a 1 jiffy window, we
- * will almost always get the same randomisation for the stack and mmap
- * region. This will mean the relative distance between stack and mmap will be
- * the same.
- *
- * To avoid this we can shift the randomness by 1 bit.
- */
 static unsigned long mmap_rnd(void)
 {
        unsigned long rnd = 0;
        if (current->flags & PF_RANDOMIZE)
-                rnd = (long)get_random_int() & (STACK_RND_MASK >> 1);
+                rnd = (long)get_random_int() & STACK_RND_MASK;
-        return rnd << (PAGE_SHIFT + 1);
+        return rnd << PAGE_SHIFT;
 }
 static unsigned long mmap_base(void)
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index f4f8b500f74c..6032f3e3056a 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -28,6 +28,7 @@
 #include <linux/io.h>
 #include <asm/cputype.h>
+#include <asm/fixmap.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
 #include <asm/sizes.h>
@@ -463,3 +464,96 @@ void vmemmap_free(unsigned long start, unsigned long end)
 {
 }
 #endif  /* CONFIG_SPARSEMEM_VMEMMAP */
+static pte_t bm_pte[PTRS_PER_PTE] __page_aligned_bss;
+#if CONFIG_ARM64_PGTABLE_LEVELS > 2
+static pmd_t bm_pmd[PTRS_PER_PMD] __page_aligned_bss;
+#endif
+#if CONFIG_ARM64_PGTABLE_LEVELS > 3
+static pud_t bm_pud[PTRS_PER_PUD] __page_aligned_bss;
+#endif
+static inline pud_t * fixmap_pud(unsigned long addr)
+{
+        pgd_t *pgd = pgd_offset_k(addr);
+        BUG_ON(pgd_none(*pgd) || pgd_bad(*pgd));
+        return pud_offset(pgd, addr);
+}
+static inline pmd_t * fixmap_pmd(unsigned long addr)
+{
+        pud_t *pud = fixmap_pud(addr);
+        BUG_ON(pud_none(*pud) || pud_bad(*pud));
+        return pmd_offset(pud, addr);
+}
+static inline pte_t * fixmap_pte(unsigned long addr)
+{
+        pmd_t *pmd = fixmap_pmd(addr);
+        BUG_ON(pmd_none(*pmd) || pmd_bad(*pmd));
+        return pte_offset_kernel(pmd, addr);
+}
+void __init early_fixmap_init(void)
+{
+        pgd_t *pgd;
+        pud_t *pud;
+        pmd_t *pmd;
+        unsigned long addr = FIXADDR_START;
+        pgd = pgd_offset_k(addr);
+        pgd_populate(&init_mm, pgd, bm_pud);
+        pud = pud_offset(pgd, addr);
+        pud_populate(&init_mm, pud, bm_pmd);
+        pmd = pmd_offset(pud, addr);
+        pmd_populate_kernel(&init_mm, pmd, bm_pte);
+        /*
+         * The boot-ioremap range spans multiple pmds, for which
+         * we are not preparted:
+         */
+        BUILD_BUG_ON((__fix_to_virt(FIX_BTMAP_BEGIN) >> PMD_SHIFT)
+                     != (__fix_to_virt(FIX_BTMAP_END) >> PMD_SHIFT));
+        if ((pmd != fixmap_pmd(fix_to_virt(FIX_BTMAP_BEGIN)))
+             || pmd != fixmap_pmd(fix_to_virt(FIX_BTMAP_END))) {
+                WARN_ON(1);
+                pr_warn("pmd %p != %p, %p\n",
+                        pmd, fixmap_pmd(fix_to_virt(FIX_BTMAP_BEGIN)),
+                        fixmap_pmd(fix_to_virt(FIX_BTMAP_END)));
+                pr_warn("fix_to_virt(FIX_BTMAP_BEGIN): %08lx\n",
+                        fix_to_virt(FIX_BTMAP_BEGIN));
+                pr_warn("fix_to_virt(FIX_BTMAP_END):   %08lx\n",
+                        fix_to_virt(FIX_BTMAP_END));
+                pr_warn("FIX_BTMAP_END:       %d\n", FIX_BTMAP_END);
+                pr_warn("FIX_BTMAP_BEGIN:     %d\n", FIX_BTMAP_BEGIN);
+        }
+}
+void __set_fixmap(enum fixed_addresses idx,
+                               phys_addr_t phys, pgprot_t flags)
+{
+        unsigned long addr = __fix_to_virt(idx);
+        pte_t *pte;
+        if (idx >= __end_of_fixed_addresses) {
+                BUG();
+                return;
+        }
+        pte = fixmap_pte(addr);
+        if (pgprot_val(flags)) {
+                set_pte(pte, pfn_pte(phys >> PAGE_SHIFT, flags));
+        } else {
+                pte_clear(&init_mm, addr, pte);
+                flush_tlb_kernel_range(addr, addr+PAGE_SIZE);
+        }
+}
diff --git a/arch/arm64/mm/pgd.c b/arch/arm64/mm/pgd.c
index 6682b361d3ac..71ca104f97bd 100644
--- a/arch/arm64/mm/pgd.c
+++ b/arch/arm64/mm/pgd.c
@@ -35,9 +35,9 @@ static struct kmem_cache *pgd_cache;
 pgd_t *pgd_alloc(struct mm_struct *mm)
 {
        if (PGD_SIZE == PAGE_SIZE)
-                return (pgd_t *)get_zeroed_page(GFP_KERNEL);
+                return (pgd_t *)__get_free_page(PGALLOC_GFP);
        else
-                return kmem_cache_zalloc(pgd_cache, GFP_KERNEL);
+                return kmem_cache_alloc(pgd_cache, PGALLOC_GFP);
 }
 void pgd_free(struct mm_struct *mm, pgd_t *pgd)
diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c
index 41f1e3e2ea24..edba042b2325 100644
--- a/arch/arm64/net/bpf_jit_comp.c
+++ b/arch/arm64/net/bpf_jit_comp.c
@@ -60,7 +60,7 @@ struct jit_ctx {
        const struct bpf_prog *prog;
        int idx;
        int tmp_used;
-        int body_offset;
+        int epilogue_offset;
        int *offset;
        u32 *image;
 };
@@ -130,8 +130,8 @@ static void jit_fill_hole(void *area, unsigned int size)
 static inline int epilogue_offset(const struct jit_ctx *ctx)
 {
-        int to = ctx->offset[ctx->prog->len - 1];
+        int to = ctx->epilogue_offset;
-        int from = ctx->idx - ctx->body_offset;
+        int from = ctx->idx;
        return to - from;
 }
@@ -463,6 +463,8 @@ emit_cond_jmp:
        }
        /* function return */
        case BPF_JMP | BPF_EXIT:
+                /* Optimization: when last instruction is EXIT,
+                   simply fallthrough to epilogue. */
                if (i == ctx->prog->len - 1)
                        break;
                jmp_offset = epilogue_offset(ctx);
@@ -685,11 +687,13 @@ void bpf_int_jit_compile(struct bpf_prog *prog)
        /* 1. Initial fake pass to compute ctx->idx. */
-        /* Fake pass to fill in ctx->offset. */
+        /* Fake pass to fill in ctx->offset and ctx->tmp_used. */
        if (build_body(&ctx))
                goto out;
        build_prologue(&ctx);
+        ctx.epilogue_offset = ctx.idx;
        build_epilogue(&ctx);
        /* Now we know the actual image size. */
@@ -706,7 +710,6 @@ void bpf_int_jit_compile(struct bpf_prog *prog)
        build_prologue(&ctx);
-        ctx.body_offset = ctx.idx;
        if (build_body(&ctx)) {
                bpf_jit_binary_free(header);
                goto out;
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index 37b75602adf6..cc92cdb9994c 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -17,7 +17,7 @@
 #include <linux/spi/spi.h>
 #include <linux/usb/atmel_usba_udc.h>
-#include <mach/atmel-mci.h>
+#include <linux/platform_data/mmc-atmel-mci.h>
 #include <linux/atmel-mci.h>
 #include <asm/io.h>
diff --git a/arch/avr32/mach-at32ap/include/mach/atmel-mci.h b/arch/avr32/mach-at32ap/include/mach/atmel-mci.h
deleted file mode 100644
index 11d7f4b28dc8..000000000000
--- a/arch/avr32/mach-at32ap/include/mach/atmel-mci.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef __MACH_ATMEL_MCI_H
-#define __MACH_ATMEL_MCI_H
-#include <linux/platform_data/dma-dw.h>
-/**
- * struct mci_dma_data - DMA data for MCI interface
- */
-struct mci_dma_data {
-        struct dw_dma_slave     sdata;
-};
-/* accessor macros */
-#define slave_data_ptr(s)       (&(s)->sdata)
-#define find_slave_dev(s)       ((s)->sdata.dma_dev)
-#endif /* __MACH_ATMEL_MCI_H */
diff --git a/arch/cris/include/asm/io.h b/arch/cris/include/asm/io.h
index e59dba12ce94..752a3f45df60 100644
--- a/arch/cris/include/asm/io.h
+++ b/arch/cris/include/asm/io.h
@@ -112,6 +112,9 @@ static inline void writel(unsigned int b, volatile void __iomem *addr)
        else
                *(volatile unsigned int __force *) addr = b;
 }
+#define writeb_relaxed(b, addr) writeb(b, addr)
+#define writew_relaxed(b, addr) writew(b, addr)
+#define writel_relaxed(b, addr) writel(b, addr)
 #define __raw_writeb writeb
 #define __raw_writew writew
 #define __raw_writel writel
diff --git a/arch/frv/include/asm/io.h b/arch/frv/include/asm/io.h
index 8cb50a2fbcb2..99bb7efaf9b7 100644
--- a/arch/frv/include/asm/io.h
+++ b/arch/frv/include/asm/io.h
@@ -243,6 +243,9 @@ static inline void writel(uint32_t datum, volatile void __iomem *addr)
                __flush_PCI_writes();
 }
+#define writeb_relaxed writeb
+#define writew_relaxed writew
+#define writel_relaxed writel
 /* Values for nocacheflag and cmode */
 #define IOMAP_FULL_CACHING              0
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index c84c88bbbbd7..536d13b0bea6 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -11,7 +11,6 @@ config IA64
        select PCI if (!IA64_HP_SIM)
        select ACPI if (!IA64_HP_SIM)
        select ARCH_MIGHT_HAVE_ACPI_PDC if ACPI
-        select PM if (!IA64_HP_SIM)
        select HAVE_UNSTABLE_SCHED_CLOCK
        select HAVE_IDE
        select HAVE_OPROFILE
@@ -233,6 +232,7 @@ config IA64_SGI_UV
 config IA64_HP_SIM
        bool "Ski-simulator"
        select SWIOTLB
+        depends on !PM_RUNTIME
 endchoice
diff --git a/arch/ia64/include/asm/io.h b/arch/ia64/include/asm/io.h
index bee0acd52f7e..80a7e34be009 100644
--- a/arch/ia64/include/asm/io.h
+++ b/arch/ia64/include/asm/io.h
@@ -393,6 +393,10 @@ __writeq (unsigned long val, volatile void __iomem *addr)
 #define writew(v,a)     __writew((v), (a))
 #define writel(v,a)     __writel((v), (a))
 #define writeq(v,a)     __writeq((v), (a))
+#define writeb_relaxed(v,a)     __writeb((v), (a))
+#define writew_relaxed(v,a)     __writew((v), (a))
+#define writel_relaxed(v,a)     __writel((v), (a))
+#define writeq_relaxed(v,a)     __writeq((v), (a))
 #define __raw_writeb    writeb
 #define __raw_writew    writew
 #define __raw_writel    writel
diff --git a/arch/ia64/include/asm/uaccess.h b/arch/ia64/include/asm/uaccess.h
index 449c8c0fa2bd..103bedc59644 100644
--- a/arch/ia64/include/asm/uaccess.h
+++ b/arch/ia64/include/asm/uaccess.h
@@ -365,15 +365,15 @@ ia64_done_with_exception (struct pt_regs *regs)
 }
 #define ARCH_HAS_TRANSLATE_MEM_PTR      1
-static __inline__ char *
+static __inline__ void *
-xlate_dev_mem_ptr (unsigned long p)
+xlate_dev_mem_ptr(phys_addr_t p)
 {
        struct page *page;
-        char * ptr;
+        void *ptr;
        page = pfn_to_page(p >> PAGE_SHIFT);
        if (PageUncached(page))
-                ptr = (char *)p + __IA64_UNCACHED_OFFSET;
+                ptr = (void *)p + __IA64_UNCACHED_OFFSET;
        else
                ptr = __va(p);
@@ -383,15 +383,15 @@ xlate_dev_mem_ptr (unsigned long p)
 /*
 * Convert a virtual cached kernel memory pointer to an uncached pointer
 */
-static __inline__ char *
+static __inline__ void *
-xlate_dev_kmem_ptr (char * p)
+xlate_dev_kmem_ptr(void *p)
 {
        struct page *page;
-        char * ptr;
+        void *ptr;
        page = virt_to_page((unsigned long)p);
        if (PageUncached(page))
-                ptr = (char *)__pa(p) + __IA64_UNCACHED_OFFSET;
+                ptr = (void *)__pa(p) + __IA64_UNCACHED_OFFSET;
        else
                ptr = p;
diff --git a/arch/ia64/include/uapi/asm/siginfo.h b/arch/ia64/include/uapi/asm/siginfo.h
index 4ea6225196bb..bce9bc1a66c4 100644
--- a/arch/ia64/include/uapi/asm/siginfo.h
+++ b/arch/ia64/include/uapi/asm/siginfo.h
@@ -63,6 +63,10 @@ typedef struct siginfo {
                        unsigned int _flags;    /* see below */
                        unsigned long _isr;     /* isr */
                        short _addr_lsb;        /* lsb of faulting address */
+                        struct {
+                                void __user *_lower;
+                                void __user *_upper;
+                        } _addr_bnd;
                } _sigfault;
                /* SIGPOLL */
@@ -110,9 +114,9 @@ typedef struct siginfo {
 /*
 * SIGSEGV si_codes
 */
-#define __SEGV_PSTKOVF  (__SI_FAULT|3)  /* paragraph stack overflow */
+#define __SEGV_PSTKOVF  (__SI_FAULT|4)  /* paragraph stack overflow */
 #undef NSIGSEGV
-#define NSIGSEGV        3
+#define NSIGSEGV        4
 #undef NSIGTRAP
 #define NSIGTRAP        4
diff --git a/arch/ia64/kernel/msi_ia64.c b/arch/ia64/kernel/msi_ia64.c
index 8c3730c3c63d..8ae36ea177d3 100644
--- a/arch/ia64/kernel/msi_ia64.c
+++ b/arch/ia64/kernel/msi_ia64.c
@@ -35,7 +35,7 @@ static int ia64_set_msi_irq_affinity(struct irq_data *idata,
        data |= MSI_DATA_VECTOR(irq_to_vector(irq));
        msg.data = data;
-        write_msi_msg(irq, &msg);
+        pci_write_msi_msg(irq, &msg);
        cpumask_copy(idata->affinity, cpumask_of(cpu));
        return 0;
@@ -71,7 +71,7 @@ int ia64_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
                MSI_DATA_DELIVERY_FIXED |
                MSI_DATA_VECTOR(vector);
-        write_msi_msg(irq, &msg);
+        pci_write_msi_msg(irq, &msg);
        irq_set_chip_and_handler(irq, &ia64_msi_chip, handle_edge_irq);
        return 0;
@@ -102,8 +102,8 @@ static int ia64_msi_retrigger_irq(struct irq_data *data)
 */
 static struct irq_chip ia64_msi_chip = {
        .name                   = "PCI-MSI",
-        .irq_mask               = mask_msi_irq,
+        .irq_mask               = pci_msi_mask_irq,
-        .irq_unmask             = unmask_msi_irq,
+        .irq_unmask             = pci_msi_unmask_irq,
        .irq_ack                = ia64_ack_msi_irq,
 #ifdef CONFIG_SMP
        .irq_set_affinity       = ia64_set_msi_irq_affinity,
diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c
index 5845ffea67c3..dc063fe6646a 100644
--- a/arch/ia64/kernel/perfmon.c
+++ b/arch/ia64/kernel/perfmon.c
@@ -2662,7 +2662,7 @@ pfm_context_create(pfm_context_t *ctx, void *arg, int count, struct pt_regs *reg
        ret = -ENOMEM;
-        fd = get_unused_fd();
+        fd = get_unused_fd_flags(0);
        if (fd < 0)
                return fd;
diff --git a/arch/ia64/sn/kernel/msi_sn.c b/arch/ia64/sn/kernel/msi_sn.c
index 446e7799928c..a0eb27b66d13 100644
--- a/arch/ia64/sn/kernel/msi_sn.c
+++ b/arch/ia64/sn/kernel/msi_sn.c
@@ -145,7 +145,7 @@ int sn_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *entry)
        msg.data = 0x100 + irq;
        irq_set_msi_desc(irq, entry);
-        write_msi_msg(irq, &msg);
+        pci_write_msi_msg(irq, &msg);
        irq_set_chip_and_handler(irq, &sn_msi_chip, handle_edge_irq);
        return 0;
@@ -205,7 +205,7 @@ static int sn_set_msi_irq_affinity(struct irq_data *data,
        msg.address_hi = (u32)(bus_addr >> 32);
        msg.address_lo = (u32)(bus_addr & 0x00000000ffffffff);
-        write_msi_msg(irq, &msg);
+        pci_write_msi_msg(irq, &msg);
        cpumask_copy(data->affinity, cpu_mask);
        return 0;
@@ -228,8 +228,8 @@ static int sn_msi_retrigger_irq(struct irq_data *data)
 static struct irq_chip sn_msi_chip = {
        .name                   = "PCI-MSI",
-        .irq_mask               = mask_msi_irq,
+        .irq_mask               = pci_msi_mask_irq,
-        .irq_unmask             = unmask_msi_irq,
+        .irq_unmask             = pci_msi_unmask_irq,
        .irq_ack                = sn_ack_msi_irq,
 #ifdef CONFIG_SMP
        .irq_set_affinity       = sn_set_msi_irq_affinity,
diff --git a/arch/m32r/include/asm/io.h b/arch/m32r/include/asm/io.h
index 4010f1fc5b65..6e7787f3dac7 100644
--- a/arch/m32r/include/asm/io.h
+++ b/arch/m32r/include/asm/io.h
@@ -161,6 +161,9 @@ static inline void _writel(unsigned long l, unsigned long addr)
 #define __raw_writeb writeb
 #define __raw_writew writew
 #define __raw_writel writel
+#define writeb_relaxed writeb
+#define writew_relaxed writew
+#define writel_relaxed writel
 #define ioread8 read
 #define ioread16 readw
diff --git a/arch/m68k/atari/config.c b/arch/m68k/atari/config.c
index 01a62161b08a..192b00f098f4 100644
--- a/arch/m68k/atari/config.c
+++ b/arch/m68k/atari/config.c
@@ -858,6 +858,24 @@ static struct platform_device *atari_netusbee_devices[] __initdata = {
 };
 #endif /* CONFIG_ATARI_ETHERNEC */
+#ifdef CONFIG_ATARI_SCSI
+static const struct resource atari_scsi_st_rsrc[] __initconst = {
+        {
+                .flags = IORESOURCE_IRQ,
+                .start = IRQ_MFP_FSCSI,
+                .end   = IRQ_MFP_FSCSI,
+        },
+};
+static const struct resource atari_scsi_tt_rsrc[] __initconst = {
+        {
+                .flags = IORESOURCE_IRQ,
+                .start = IRQ_TT_MFP_SCSI,
+                .end   = IRQ_TT_MFP_SCSI,
+        },
+};
+#endif
 int __init atari_platform_init(void)
 {
        int rv = 0;
@@ -892,6 +910,15 @@ int __init atari_platform_init(void)
        }
 #endif
+#ifdef CONFIG_ATARI_SCSI
+        if (ATARIHW_PRESENT(ST_SCSI))
+                platform_device_register_simple("atari_scsi", -1,
+                        atari_scsi_st_rsrc, ARRAY_SIZE(atari_scsi_st_rsrc));
+        else if (ATARIHW_PRESENT(TT_SCSI))
+                platform_device_register_simple("atari_scsi", -1,
+                        atari_scsi_tt_rsrc, ARRAY_SIZE(atari_scsi_tt_rsrc));
+#endif
        return rv;
 }
diff --git a/arch/m68k/atari/stdma.c b/arch/m68k/atari/stdma.c
index ddbf43ca8858..e5a66596b116 100644
--- a/arch/m68k/atari/stdma.c
+++ b/arch/m68k/atari/stdma.c
@@ -59,6 +59,31 @@ static irqreturn_t stdma_int (int irq, void *dummy);
 /************************* End of Prototypes **************************/
+/**
+ * stdma_try_lock - attempt to acquire ST DMA interrupt "lock"
+ * @handler: interrupt handler to use after acquisition
+ *
+ * Returns !0 if lock was acquired; otherwise 0.
+ */
+int stdma_try_lock(irq_handler_t handler, void *data)
+{
+        unsigned long flags;
+        local_irq_save(flags);
+        if (stdma_locked) {
+                local_irq_restore(flags);
+                return 0;
+        }
+        stdma_locked   = 1;
+        stdma_isr      = handler;
+        stdma_isr_data = data;
+        local_irq_restore(flags);
+        return 1;
+}
+EXPORT_SYMBOL(stdma_try_lock);
 /*
 * Function: void stdma_lock( isrfunc isr, void *data )
@@ -78,19 +103,10 @@ static irqreturn_t stdma_int (int irq, void *dummy);
 void stdma_lock(irq_handler_t handler, void *data)
 {
-        unsigned long flags;
-        local_irq_save(flags);          /* protect lock */
        /* Since the DMA is used for file system purposes, we
         have to sleep uninterruptible (there may be locked
         buffers) */
-        wait_event(stdma_wait, !stdma_locked);
+        wait_event(stdma_wait, stdma_try_lock(handler, data));
-        stdma_locked   = 1;
-        stdma_isr      = handler;
-        stdma_isr_data = data;
-        local_irq_restore(flags);
 }
 EXPORT_SYMBOL(stdma_lock);
@@ -122,22 +138,25 @@ void stdma_release(void)
 EXPORT_SYMBOL(stdma_release);
-/*
+/**
- * Function: int stdma_others_waiting( void )
+ * stdma_is_locked_by - allow lock holder to check whether it needs to release.
- *
+ * @handler: interrupt handler previously used to acquire lock.
- * Purpose: Check if someone waits for the ST-DMA lock.
- *
- * Inputs: none
- *
- * Returns: 0 if no one is waiting, != 0 otherwise
 *
+ * Returns !0 if locked for the given handler; 0 otherwise.
 */
-int stdma_others_waiting(void)
+int stdma_is_locked_by(irq_handler_t handler)
 {
-        return waitqueue_active(&stdma_wait);
+        unsigned long flags;
+        int result;
+        local_irq_save(flags);
+        result = stdma_locked && (stdma_isr == handler);
+        local_irq_restore(flags);
+        return result;
 }
-EXPORT_SYMBOL(stdma_others_waiting);
+EXPORT_SYMBOL(stdma_is_locked_by);
 /*
diff --git a/arch/m68k/include/asm/atari_stdma.h b/arch/m68k/include/asm/atari_stdma.h
index 8e389b7fa70c..d24e34d870dc 100644
--- a/arch/m68k/include/asm/atari_stdma.h
+++ b/arch/m68k/include/asm/atari_stdma.h
@@ -8,11 +8,11 @@
 /***************************** Prototypes *****************************/
+int stdma_try_lock(irq_handler_t, void *);
 void stdma_lock(irq_handler_t handler, void *data);
 void stdma_release( void );
-int stdma_others_waiting( void );
 int stdma_islocked( void );
-void *stdma_locked_by( void );
+int stdma_is_locked_by(irq_handler_t);
 void stdma_init( void );
 /************************* End of Prototypes **************************/
diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h
index c70cc9155003..bccd5a914eb6 100644
--- a/arch/m68k/include/asm/io.h
+++ b/arch/m68k/include/asm/io.h
@@ -3,3 +3,11 @@
 #else
 #include <asm/io_mm.h>
 #endif
+#define readb_relaxed(addr)     readb(addr)
+#define readw_relaxed(addr)     readw(addr)
+#define readl_relaxed(addr)     readl(addr)
+#define writeb_relaxed(b, addr) writeb(b, addr)
+#define writew_relaxed(b, addr) writew(b, addr)
+#define writel_relaxed(b, addr) writel(b, addr)
diff --git a/arch/m68k/include/asm/io_no.h b/arch/m68k/include/asm/io_no.h
index be4b5a813ad4..a93c8cde4d38 100644
--- a/arch/m68k/include/asm/io_no.h
+++ b/arch/m68k/include/asm/io_no.h
@@ -40,10 +40,6 @@ static inline unsigned int _swapl(volatile unsigned long v)
 #define readl(addr) \
    ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
-#define readb_relaxed(addr) readb(addr)
-#define readw_relaxed(addr) readw(addr)
-#define readl_relaxed(addr) readl(addr)
 #define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
 #define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
 #define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
diff --git a/arch/m68k/include/asm/macintosh.h b/arch/m68k/include/asm/macintosh.h
index d323b2c2d07d..29c7c6c3a5f2 100644
--- a/arch/m68k/include/asm/macintosh.h
+++ b/arch/m68k/include/asm/macintosh.h
@@ -53,6 +53,10 @@ struct mac_model
 #define MAC_SCSI_QUADRA         2
 #define MAC_SCSI_QUADRA2        3
 #define MAC_SCSI_QUADRA3        4
+#define MAC_SCSI_IIFX           5
+#define MAC_SCSI_DUO            6
+#define MAC_SCSI_CCL            7
+#define MAC_SCSI_LATE           8
 #define MAC_IDE_NONE            0
 #define MAC_IDE_QUADRA          1
diff --git a/arch/m68k/mac/config.c b/arch/m68k/mac/config.c
index a471eab1a4dd..e9c3756139fc 100644
--- a/arch/m68k/mac/config.c
+++ b/arch/m68k/mac/config.c
@@ -278,7 +278,7 @@ static struct mac_model mac_data_table[] = {
                .name           = "IIfx",
                .adb_type       = MAC_ADB_IOP,
                .via_type       = MAC_VIA_IICI,
-                .scsi_type      = MAC_SCSI_OLD,
+                .scsi_type      = MAC_SCSI_IIFX,
                .scc_type       = MAC_SCC_IOP,
                .nubus_type     = MAC_NUBUS,
                .floppy_type    = MAC_FLOPPY_SWIM_IOP,
@@ -329,7 +329,7 @@ static struct mac_model mac_data_table[] = {
                .name           = "Color Classic",
                .adb_type       = MAC_ADB_CUDA,
                .via_type       = MAC_VIA_IICI,
-                .scsi_type      = MAC_SCSI_OLD,
+                .scsi_type      = MAC_SCSI_CCL,
                .scc_type       = MAC_SCC_II,
                .nubus_type     = MAC_NUBUS,
                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
@@ -338,7 +338,7 @@ static struct mac_model mac_data_table[] = {
                .name           = "Color Classic II",
                .adb_type       = MAC_ADB_CUDA,
                .via_type       = MAC_VIA_IICI,
-                .scsi_type      = MAC_SCSI_OLD,
+                .scsi_type      = MAC_SCSI_CCL,
                .scc_type       = MAC_SCC_II,
                .nubus_type     = MAC_NUBUS,
                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
@@ -526,7 +526,7 @@ static struct mac_model mac_data_table[] = {
                .name           = "Performa 520",
                .adb_type       = MAC_ADB_CUDA,
                .via_type       = MAC_VIA_IICI,
-                .scsi_type      = MAC_SCSI_OLD,
+                .scsi_type      = MAC_SCSI_CCL,
                .scc_type       = MAC_SCC_II,
                .nubus_type     = MAC_NUBUS,
                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
@@ -535,7 +535,7 @@ static struct mac_model mac_data_table[] = {
                .name           = "Performa 550",
                .adb_type       = MAC_ADB_CUDA,
                .via_type       = MAC_VIA_IICI,
-                .scsi_type      = MAC_SCSI_OLD,
+                .scsi_type      = MAC_SCSI_CCL,
                .scc_type       = MAC_SCC_II,
                .nubus_type     = MAC_NUBUS,
                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
@@ -567,7 +567,7 @@ static struct mac_model mac_data_table[] = {
                .name           = "TV",
                .adb_type       = MAC_ADB_CUDA,
                .via_type       = MAC_VIA_IICI,
-                .scsi_type      = MAC_SCSI_OLD,
+                .scsi_type      = MAC_SCSI_CCL,
                .scc_type       = MAC_SCC_II,
                .nubus_type     = MAC_NUBUS,
                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
@@ -712,7 +712,7 @@ static struct mac_model mac_data_table[] = {
                .name           = "PowerBook 190",
                .adb_type       = MAC_ADB_PB2,
                .via_type       = MAC_VIA_QUADRA,
-                .scsi_type      = MAC_SCSI_OLD,
+                .scsi_type      = MAC_SCSI_LATE,
                .ide_type       = MAC_IDE_BABOON,
                .scc_type       = MAC_SCC_QUADRA,
                .nubus_type     = MAC_NUBUS,
@@ -722,7 +722,7 @@ static struct mac_model mac_data_table[] = {
                .name           = "PowerBook 520",
                .adb_type       = MAC_ADB_PB2,
                .via_type       = MAC_VIA_QUADRA,
-                .scsi_type      = MAC_SCSI_OLD,
+                .scsi_type      = MAC_SCSI_LATE,
                .scc_type       = MAC_SCC_QUADRA,
                .ether_type     = MAC_ETHER_SONIC,
                .nubus_type     = MAC_NUBUS,
@@ -740,7 +740,7 @@ static struct mac_model mac_data_table[] = {
                .name           = "PowerBook Duo 210",
                .adb_type       = MAC_ADB_PB2,
                .via_type       = MAC_VIA_IICI,
-                .scsi_type      = MAC_SCSI_OLD,
+                .scsi_type      = MAC_SCSI_DUO,
                .scc_type       = MAC_SCC_QUADRA,
                .nubus_type     = MAC_NUBUS,
                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
@@ -749,7 +749,7 @@ static struct mac_model mac_data_table[] = {
                .name           = "PowerBook Duo 230",
                .adb_type       = MAC_ADB_PB2,
                .via_type       = MAC_VIA_IICI,
-                .scsi_type      = MAC_SCSI_OLD,
+                .scsi_type      = MAC_SCSI_DUO,
                .scc_type       = MAC_SCC_QUADRA,
                .nubus_type     = MAC_NUBUS,
                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
@@ -758,7 +758,7 @@ static struct mac_model mac_data_table[] = {
                .name           = "PowerBook Duo 250",
                .adb_type       = MAC_ADB_PB2,
                .via_type       = MAC_VIA_IICI,
-                .scsi_type      = MAC_SCSI_OLD,
+                .scsi_type      = MAC_SCSI_DUO,
                .scc_type       = MAC_SCC_QUADRA,
                .nubus_type     = MAC_NUBUS,
                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
@@ -767,7 +767,7 @@ static struct mac_model mac_data_table[] = {
                .name           = "PowerBook Duo 270c",
                .adb_type       = MAC_ADB_PB2,
                .via_type       = MAC_VIA_IICI,
-                .scsi_type      = MAC_SCSI_OLD,
+                .scsi_type      = MAC_SCSI_DUO,
                .scc_type       = MAC_SCC_QUADRA,
                .nubus_type     = MAC_NUBUS,
                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
@@ -776,7 +776,7 @@ static struct mac_model mac_data_table[] = {
                .name           = "PowerBook Duo 280",
                .adb_type       = MAC_ADB_PB2,
                .via_type       = MAC_VIA_IICI,
-                .scsi_type      = MAC_SCSI_OLD,
+                .scsi_type      = MAC_SCSI_DUO,
                .scc_type       = MAC_SCC_QUADRA,
                .nubus_type     = MAC_NUBUS,
                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
@@ -785,7 +785,7 @@ static struct mac_model mac_data_table[] = {
                .name           = "PowerBook Duo 280c",
                .adb_type       = MAC_ADB_PB2,
                .via_type       = MAC_VIA_IICI,
-                .scsi_type      = MAC_SCSI_OLD,
+                .scsi_type      = MAC_SCSI_DUO,
                .scc_type       = MAC_SCC_QUADRA,
                .nubus_type     = MAC_NUBUS,
                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
@@ -929,6 +929,70 @@ static struct platform_device swim_pdev = {
        .resource       = &swim_rsrc,
 };
+static const struct resource mac_scsi_iifx_rsrc[] __initconst = {
+        {
+                .flags = IORESOURCE_IRQ,
+                .start = IRQ_MAC_SCSI,
+                .end   = IRQ_MAC_SCSI,
+        }, {
+                .flags = IORESOURCE_MEM,
+                .start = 0x50008000,
+                .end   = 0x50009FFF,
+        },
+};
+static const struct resource mac_scsi_duo_rsrc[] __initconst = {
+        {
+                .flags = IORESOURCE_MEM,
+                .start = 0xFEE02000,
+                .end   = 0xFEE03FFF,
+        },
+};
+static const struct resource mac_scsi_old_rsrc[] __initconst = {
+        {
+                .flags = IORESOURCE_IRQ,
+                .start = IRQ_MAC_SCSI,
+                .end   = IRQ_MAC_SCSI,
+        }, {
+                .flags = IORESOURCE_MEM,
+                .start = 0x50010000,
+                .end   = 0x50011FFF,
+        }, {
+                .flags = IORESOURCE_MEM,
+                .start = 0x50006000,
+                .end   = 0x50007FFF,
+        },
+};
+static const struct resource mac_scsi_late_rsrc[] __initconst = {
+        {
+                .flags = IORESOURCE_IRQ,
+                .start = IRQ_MAC_SCSI,
+                .end   = IRQ_MAC_SCSI,
+        }, {
+                .flags = IORESOURCE_MEM,
+                .start = 0x50010000,
+                .end   = 0x50011FFF,
+        },
+};
+static const struct resource mac_scsi_ccl_rsrc[] __initconst = {
+        {
+                .flags = IORESOURCE_IRQ,
+                .start = IRQ_MAC_SCSI,
+                .end   = IRQ_MAC_SCSI,
+        }, {
+                .flags = IORESOURCE_MEM,
+                .start = 0x50F10000,
+                .end   = 0x50F11FFF,
+        }, {
+                .flags = IORESOURCE_MEM,
+                .start = 0x50F06000,
+                .end   = 0x50F07FFF,
+        },
+};
 static struct platform_device esp_0_pdev = {
        .name           = "mac_esp",
        .id             = 0,
@@ -1000,6 +1064,60 @@ int __init mac_platform_init(void)
                    (macintosh_config->ident == MAC_MODEL_Q950))
                        platform_device_register(&esp_1_pdev);
                break;
+        case MAC_SCSI_IIFX:
+                /* Addresses from The Guide to Mac Family Hardware.
+                 * $5000 8000 - $5000 9FFF: SCSI DMA
+                 * $5000 C000 - $5000 DFFF: Alternate SCSI (DMA)
+                 * $5000 E000 - $5000 FFFF: Alternate SCSI (Hsk)
+                 * The SCSI DMA custom IC embeds the 53C80 core. mac_scsi does
+                 * not make use of its DMA or hardware handshaking logic.
+                 */
+                platform_device_register_simple("mac_scsi", 0,
+                        mac_scsi_iifx_rsrc, ARRAY_SIZE(mac_scsi_iifx_rsrc));
+                break;
+        case MAC_SCSI_DUO:
+                /* Addresses from the Duo Dock II Developer Note.
+                 * $FEE0 2000 - $FEE0 3FFF: normal mode
+                 * $FEE0 4000 - $FEE0 5FFF: pseudo DMA without /DRQ
+                 * $FEE0 6000 - $FEE0 7FFF: pseudo DMA with /DRQ
+                 * The NetBSD code indicates that both 5380 chips share
+                 * an IRQ (?) which would need careful handling (see mac_esp).
+                 */
+                platform_device_register_simple("mac_scsi", 1,
+                        mac_scsi_duo_rsrc, ARRAY_SIZE(mac_scsi_duo_rsrc));
+                /* fall through */
+        case MAC_SCSI_OLD:
+                /* Addresses from Developer Notes for Duo System,
+                 * PowerBook 180 & 160, 140 & 170, Macintosh IIsi
+                 * and also from The Guide to Mac Family Hardware for
+                 * SE/30, II, IIx, IIcx, IIci.
+                 * $5000 6000 - $5000 7FFF: pseudo-DMA with /DRQ
+                 * $5001 0000 - $5001 1FFF: normal mode
+                 * $5001 2000 - $5001 3FFF: pseudo-DMA without /DRQ
+                 * GMFH says that $5000 0000 - $50FF FFFF "wraps
+                 * $5000 0000 - $5001 FFFF eight times" (!)
+                 * mess.org says IIci and Color Classic do not alias
+                 * I/O address space.
+                 */
+                platform_device_register_simple("mac_scsi", 0,
+                        mac_scsi_old_rsrc, ARRAY_SIZE(mac_scsi_old_rsrc));
+                break;
+        case MAC_SCSI_LATE:
+                /* PDMA logic in 68040 PowerBooks is somehow different to
+                 * '030 models. It's probably more like Quadras (see mac_esp).
+                 */
+                platform_device_register_simple("mac_scsi", 0,
+                        mac_scsi_late_rsrc, ARRAY_SIZE(mac_scsi_late_rsrc));
+                break;
+        case MAC_SCSI_CCL:
+                /* Addresses from the Color Classic Developer Note.
+                 * $50F0 6000 - $50F0 7FFF: SCSI handshake
+                 * $50F1 0000 - $50F1 1FFF: SCSI
+                 * $50F1 2000 - $50F1 3FFF: SCSI DMA
+                 */
+                platform_device_register_simple("mac_scsi", 0,
+                        mac_scsi_ccl_rsrc, ARRAY_SIZE(mac_scsi_ccl_rsrc));
+                break;
        }
        /*
diff --git a/arch/m68k/mm/init.c b/arch/m68k/mm/init.c
index acaff6a49e35..b09a3cb29b68 100644
--- a/arch/m68k/mm/init.c
+++ b/arch/m68k/mm/init.c
@@ -94,7 +94,6 @@ void __init paging_init(void)
        high_memory = (void *) end_mem;
        empty_zero_page = alloc_bootmem_pages(PAGE_SIZE);
-        memset(empty_zero_page, 0, PAGE_SIZE);
        /*
         * Set up SFC/DFC registers (user data space).
diff --git a/arch/m68k/sun3/config.c b/arch/m68k/sun3/config.c
index f59ec58083f8..a8b942bf7163 100644
--- a/arch/m68k/sun3/config.c
+++ b/arch/m68k/sun3/config.c
@@ -16,6 +16,7 @@
 #include <linux/console.h>
 #include <linux/init.h>
 #include <linux/bootmem.h>
+#include <linux/platform_device.h>
 #include <asm/oplib.h>
 #include <asm/setup.h>
@@ -27,6 +28,7 @@
 #include <asm/sun3mmu.h>
 #include <asm/rtc.h>
 #include <asm/machdep.h>
+#include <asm/machines.h>
 #include <asm/idprom.h>
 #include <asm/intersil.h>
 #include <asm/irq.h>
@@ -169,3 +171,61 @@ static void __init sun3_sched_init(irq_handler_t timer_routine)
        intersil_clear();
 }
+#ifdef CONFIG_SUN3_SCSI
+static const struct resource sun3_scsi_vme_rsrc[] __initconst = {
+        {
+                .flags = IORESOURCE_IRQ,
+                .start = SUN3_VEC_VMESCSI0,
+                .end   = SUN3_VEC_VMESCSI0,
+        }, {
+                .flags = IORESOURCE_MEM,
+                .start = 0xff200000,
+                .end   = 0xff200021,
+        }, {
+                .flags = IORESOURCE_IRQ,
+                .start = SUN3_VEC_VMESCSI1,
+                .end   = SUN3_VEC_VMESCSI1,
+        }, {
+                .flags = IORESOURCE_MEM,
+                .start = 0xff204000,
+                .end   = 0xff204021,
+        },
+};
+/*
+ * Int: level 2 autovector
+ * IO: type 1, base 0x00140000, 5 bits phys space: A<4..0>
+ */
+static const struct resource sun3_scsi_rsrc[] __initconst = {
+        {
+                .flags = IORESOURCE_IRQ,
+                .start = 2,
+                .end   = 2,
+        }, {
+                .flags = IORESOURCE_MEM,
+                .start = 0x00140000,
+                .end   = 0x0014001f,
+        },
+};
+int __init sun3_platform_init(void)
+{
+        switch (idprom->id_machtype) {
+        case SM_SUN3 | SM_3_160:
+        case SM_SUN3 | SM_3_260:
+                platform_device_register_simple("sun3_scsi_vme", -1,
+                        sun3_scsi_vme_rsrc, ARRAY_SIZE(sun3_scsi_vme_rsrc));
+                break;
+        case SM_SUN3 | SM_3_50:
+        case SM_SUN3 | SM_3_60:
+                platform_device_register_simple("sun3_scsi", -1,
+                        sun3_scsi_rsrc, ARRAY_SIZE(sun3_scsi_rsrc));
+                break;
+        }
+        return 0;
+}
+arch_initcall(sun3_platform_init);
+#endif
diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h
index 433751b2a003..940f5fc1d1da 100644
--- a/arch/microblaze/include/asm/io.h
+++ b/arch/microblaze/include/asm/io.h
@@ -69,12 +69,4 @@ extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
 #include <asm-generic/io.h>
-#define readb_relaxed   readb
-#define readw_relaxed   readw
-#define readl_relaxed   readl
-#define writeb_relaxed  writeb
-#define writew_relaxed  writew
-#define writel_relaxed  writel
 #endif /* _ASM_MICROBLAZE_IO_H */
diff --git a/arch/microblaze/include/asm/tlb.h b/arch/microblaze/include/asm/tlb.h
index 8aa97817cc8c..99b6ded54849 100644
--- a/arch/microblaze/include/asm/tlb.h
+++ b/arch/microblaze/include/asm/tlb.h
@@ -14,7 +14,6 @@
 #define tlb_flush(tlb)  flush_tlb_mm((tlb)->mm)
 #include <linux/pagemap.h>
-#include <asm-generic/tlb.h>
 #ifdef CONFIG_MMU
 #define tlb_start_vma(tlb, vma)         do { } while (0)
@@ -22,4 +21,6 @@
 #define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
 #endif
+#include <asm-generic/tlb.h>
 #endif /* _ASM_MICROBLAZE_TLB_H */
diff --git a/arch/mips/include/asm/idle.h b/arch/mips/include/asm/idle.h
index 1c967abd545c..a2d18ab57ac6 100644
--- a/arch/mips/include/asm/idle.h
+++ b/arch/mips/include/asm/idle.h
@@ -22,7 +22,6 @@ extern int mips_cpuidle_wait_enter(struct cpuidle_device *dev,
        .exit_latency           = 1,\
        .target_residency       = 1,\
        .power_usage            = UINT_MAX,\
-        .flags                  = CPUIDLE_FLAG_TIME_VALID,\
        .name                   = "wait",\
        .desc                   = "MIPS wait",\
 }
diff --git a/arch/mips/include/uapi/asm/siginfo.h b/arch/mips/include/uapi/asm/siginfo.h
index e81174432bab..d08f83f19db5 100644
--- a/arch/mips/include/uapi/asm/siginfo.h
+++ b/arch/mips/include/uapi/asm/siginfo.h
@@ -92,6 +92,10 @@ typedef struct siginfo {
                        int _trapno;    /* TRAP # which caused the signal */
 #endif
                        short _addr_lsb;
+                        struct {
+                                void __user *_lower;
+                                void __user *_upper;
+                        } _addr_bnd;
                } _sigfault;
                /* SIGPOLL, SIGXFSZ (To do ...)  */
diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c
index 63bbe07a1ccd..cffaaf4aae3c 100644
--- a/arch/mips/pci/msi-octeon.c
+++ b/arch/mips/pci/msi-octeon.c
@@ -178,7 +178,7 @@ msi_irq_allocated:
        pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
        irq_set_msi_desc(irq, desc);
-        write_msi_msg(irq, &msg);
+        pci_write_msi_msg(irq, &msg);
        return 0;
 }
diff --git a/arch/mips/pci/msi-xlp.c b/arch/mips/pci/msi-xlp.c
index f7ac3edda1b2..6a40f24c91b4 100644
--- a/arch/mips/pci/msi-xlp.c
+++ b/arch/mips/pci/msi-xlp.c
@@ -217,7 +217,7 @@ static void xlp_msix_mask_ack(struct irq_data *d)
        msixvec = nlm_irq_msixvec(d->irq);
        link = nlm_irq_msixlink(msixvec);
-        mask_msi_irq(d);
+        pci_msi_mask_irq(d);
        md = irq_data_get_irq_handler_data(d);
        /* Ack MSI on bridge */
@@ -239,10 +239,10 @@ static void xlp_msix_mask_ack(struct irq_data *d)
 static struct irq_chip xlp_msix_chip = {
        .name           = "XLP-MSIX",
-        .irq_enable     = unmask_msi_irq,
+        .irq_enable     = pci_msi_unmask_irq,
-        .irq_disable    = mask_msi_irq,
+        .irq_disable    = pci_msi_mask_irq,
        .irq_mask_ack   = xlp_msix_mask_ack,
-        .irq_unmask     = unmask_msi_irq,
+        .irq_unmask     = pci_msi_unmask_irq,
 };
 void arch_teardown_msi_irq(unsigned int irq)
@@ -345,7 +345,7 @@ static int xlp_setup_msi(uint64_t lnkbase, int node, int link,
        if (ret < 0)
                return ret;
-        write_msi_msg(xirq, &msg);
+        pci_write_msi_msg(xirq, &msg);
        return 0;
 }
@@ -446,7 +446,7 @@ static int xlp_setup_msix(uint64_t lnkbase, int node, int link,
        if (ret < 0)
                return ret;
-        write_msi_msg(xirq, &msg);
+        pci_write_msi_msg(xirq, &msg);
        return 0;
 }
diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c
index 0dde80332d3a..26d2dabef281 100644
--- a/arch/mips/pci/pci-xlr.c
+++ b/arch/mips/pci/pci-xlr.c
@@ -260,7 +260,7 @@ int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
        if (ret < 0)
                return ret;
-        write_msi_msg(irq, &msg);
+        pci_write_msi_msg(irq, &msg);
        return 0;
 }
 #endif
diff --git a/arch/mn10300/include/asm/io.h b/arch/mn10300/include/asm/io.h
index e6ed0d897ccc..897ba3c12b32 100644
--- a/arch/mn10300/include/asm/io.h
+++ b/arch/mn10300/include/asm/io.h
@@ -67,6 +67,10 @@ static inline void writel(u32 b, volatile void __iomem *addr)
 #define __raw_writew writew
 #define __raw_writel writel
+#define writeb_relaxed writeb
+#define writew_relaxed writew
+#define writel_relaxed writel
 /*****************************************************************************/
 /*
 * traditional input/output functions
diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig
new file mode 100644
index 000000000000..2361acf6d2b1
--- /dev/null
+++ b/arch/nios2/Kconfig
@@ -0,0 +1,206 @@
+config NIOS2
+        def_bool y
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select CLKSRC_OF
+        select GENERIC_ATOMIC64
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_CPU_DEVICES
+        select GENERIC_IRQ_PROBE
+        select GENERIC_IRQ_SHOW
+        select HAVE_ARCH_TRACEHOOK
+        select IRQ_DOMAIN
+        select MODULES_USE_ELF_RELA
+        select OF
+        select OF_EARLY_FLATTREE
+        select SOC_BUS
+        select SPARSE_IRQ
+        select USB_ARCH_HAS_HCD if USB_SUPPORT
+config GENERIC_CSUM
+        def_bool y
+config GENERIC_HWEIGHT
+        def_bool y
+config GENERIC_CALIBRATE_DELAY
+        def_bool y
+config NO_IOPORT_MAP
+        def_bool y
+config HAS_DMA
+        def_bool y
+config FPU
+        def_bool n
+config SWAP
+        def_bool n
+config RWSEM_GENERIC_SPINLOCK
+        def_bool y
+config TRACE_IRQFLAGS_SUPPORT
+        def_bool n
+source "init/Kconfig"
+menu "Kernel features"
+source "kernel/Kconfig.preempt"
+source "kernel/Kconfig.freezer"
+source "kernel/Kconfig.hz"
+source "mm/Kconfig"
+config FORCE_MAX_ZONEORDER
+        int "Maximum zone order"
+        range 9 20
+        default "11"
+        help
+          The kernel memory allocator divides physically contiguous memory
+          blocks into "zones", where each zone is a power of two number of
+          pages.  This option selects the largest power of two that the kernel
+          keeps in the memory allocator.  If you need to allocate very large
+          blocks of physically contiguous memory, then you may need to
+          increase this value.
+          This config option is actually maximum order plus one. For example,
+          a value of 11 means that the largest free memory block is 2^10 pages.
+endmenu
+source "arch/nios2/platform/Kconfig.platform"
+menu "Processor type and features"
+config MMU
+        def_bool y
+config NR_CPUS
+        int
+        default "1"
+config NIOS2_ALIGNMENT_TRAP
+        bool "Catch alignment trap"
+        default y
+        help
+          Nios II CPUs cannot fetch/store data which is not bus aligned,
+          i.e., a 2 or 4 byte fetch must start at an address divisible by
+          2 or 4. Any non-aligned load/store instructions will be trapped and
+          emulated in software if you say Y here, which has a performance
+          impact.
+comment "Boot options"
+config CMDLINE_BOOL
+        bool "Default bootloader kernel arguments"
+        default y
+config CMDLINE
+        string "Default kernel command string"
+        default ""
+        depends on CMDLINE_BOOL
+        help
+          On some platforms, there is currently no way for the boot loader to
+          pass arguments to the kernel. For these platforms, you can supply
+          some command-line options at build time by entering them here.  In
+          other cases you can specify kernel args so that you don't have
+          to set them up in board prom initialization routines.
+config CMDLINE_FORCE
+        bool "Force default kernel command string"
+        depends on CMDLINE_BOOL
+        help
+          Set this to have arguments from the default kernel command string
+          override those passed by the boot loader.
+config NIOS2_CMDLINE_IGNORE_DTB
+        bool "Ignore kernel command string from DTB"
+        depends on CMDLINE_BOOL
+        depends on !CMDLINE_FORCE
+        default y
+        help
+          Set this to ignore the bootargs property from the devicetree's
+          chosen node and fall back to CMDLINE if nothing is passed.
+config NIOS2_PASS_CMDLINE
+        bool "Passed kernel command line from u-boot"
+        default n
+        help
+          Use bootargs env variable from u-boot for kernel command line.
+          will override "Default kernel command string".
+          Say N if you are unsure.
+endmenu
+menu "Advanced setup"
+config ADVANCED_OPTIONS
+        bool "Prompt for advanced kernel configuration options"
+        help
+comment "Default settings for advanced configuration options are used"
+        depends on !ADVANCED_OPTIONS
+config NIOS2_KERNEL_MMU_REGION_BASE_BOOL
+        bool "Set custom kernel MMU region base address"
+        depends on ADVANCED_OPTIONS
+        help
+          This option allows you to set the virtual address of the kernel MMU region.
+          Say N here unless you know what you are doing.
+config NIOS2_KERNEL_MMU_REGION_BASE
+        hex "Virtual base address of the kernel MMU region " if NIOS2_KERNEL_MMU_REGION_BASE_BOOL
+        default "0x80000000"
+        help
+          This option allows you to set the virtual base address of the kernel MMU region.
+config NIOS2_KERNEL_REGION_BASE_BOOL
+        bool "Set custom kernel region base address"
+        depends on ADVANCED_OPTIONS
+        help
+          This option allows you to set the virtual address of the kernel region.
+          Say N here unless you know what you are doing.
+config NIOS2_KERNEL_REGION_BASE
+        hex "Virtual base address of the kernel region " if NIOS2_KERNEL_REGION_BASE_BOOL
+        default "0xc0000000"
+config NIOS2_IO_REGION_BASE_BOOL
+        bool "Set custom I/O region base address"
+        depends on ADVANCED_OPTIONS
+        help
+          This option allows you to set the virtual address of the I/O region.
+          Say N here unless you know what you are doing.
+config NIOS2_IO_REGION_BASE
+        hex "Virtual base address of the I/O region" if NIOS2_IO_REGION_BASE_BOOL
+        default "0xe0000000"
+endmenu
+menu "Executable file formats"
+source "fs/Kconfig.binfmt"
+endmenu
+source "net/Kconfig"
+source "drivers/Kconfig"
+source "fs/Kconfig"
+source "arch/nios2/Kconfig.debug"
+source "security/Kconfig"
+source "crypto/Kconfig"
+source "lib/Kconfig"
diff --git a/arch/nios2/Kconfig.debug b/arch/nios2/Kconfig.debug
new file mode 100644
index 000000000000..8d4e6bacd997
--- /dev/null
+++ b/arch/nios2/Kconfig.debug
@@ -0,0 +1,17 @@
+menu "Kernel hacking"
+config TRACE_IRQFLAGS_SUPPORT
+        def_bool y
+source "lib/Kconfig.debug"
+config DEBUG_STACK_USAGE
+        bool "Enable stack utilization instrumentation"
+        depends on DEBUG_KERNEL
+        help
+          Enables the display of the minimum amount of free stack which each
+          task has ever had available in the sysrq-T and sysrq-P debug output.
+          This option will slow down process creation somewhat.
+endmenu
diff --git a/arch/nios2/Makefile b/arch/nios2/Makefile
new file mode 100644
index 000000000000..e142c9ee51fa
--- /dev/null
+++ b/arch/nios2/Makefile
@@ -0,0 +1,73 @@
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.  See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+# Copyright (C) 2013 Altera Corporation
+# Copyright (C) 1994, 95, 96, 2003 by Wind River Systems
+# Written by Fredrik Markstrom
+#
+# This file is included by the global makefile so that you can add your own
+# architecture-specific flags and dependencies. Remember to do have actions
+# for "archclean" cleaning up for this architecture.
+#
+# Nios2 port by Wind River Systems Inc trough:
+#   fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
+UTS_SYSNAME = Linux
+export MMU
+LIBGCC          := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
+KBUILD_CFLAGS += -pipe -D__linux__ -D__ELF__
+KBUILD_CFLAGS += $(if $(CONFIG_NIOS2_HW_MUL_SUPPORT),-mhw-mul,-mno-hw-mul)
+KBUILD_CFLAGS += $(if $(CONFIG_NIOS2_HW_MULX_SUPPORT),-mhw-mulx,-mno-hw-mulx)
+KBUILD_CFLAGS += $(if $(CONFIG_NIOS2_HW_DIV_SUPPORT),-mhw-div,-mno-hw-div)
+KBUILD_CFLAGS += $(if $(CONFIG_NIOS2_FPU_SUPPORT),-mcustom-fpu-cfg=60-1,)
+KBUILD_CFLAGS += -fno-optimize-sibling-calls
+KBUILD_CFLAGS += -DUTS_SYSNAME=\"$(UTS_SYSNAME)\"
+KBUILD_CFLAGS += -fno-builtin
+KBUILD_CFLAGS += -G 0
+head-y          := arch/nios2/kernel/head.o
+libs-y          += arch/nios2/lib/ $(LIBGCC)
+core-y          += arch/nios2/kernel/ arch/nios2/mm/
+core-y          += arch/nios2/platform/
+INSTALL_PATH ?= /tftpboot
+nios2-boot := arch/$(ARCH)/boot
+BOOT_TARGETS = vmImage zImage
+PHONY += $(BOOT_TARGETS) install
+KBUILD_IMAGE := $(nios2-boot)/vmImage
+ifneq ($(CONFIG_NIOS2_DTB_SOURCE),"")
+        core-y  += $(nios2-boot)/
+endif
+all: vmImage
+archclean:
+        $(Q)$(MAKE) $(clean)=$(nios2-boot)
+%.dtb:
+        $(Q)$(MAKE) $(build)=$(nios2-boot) $(nios2-boot)/$@
+dtbs:
+        $(Q)$(MAKE) $(build)=$(nios2-boot) $(nios2-boot)/$@
+$(BOOT_TARGETS): vmlinux
+        $(Q)$(MAKE) $(build)=$(nios2-boot) $(nios2-boot)/$@
+install:
+        $(Q)$(MAKE) $(build)=$(nios2-boot) BOOTIMAGE=$(KBUILD_IMAGE) install
+define archhelp
+  echo  '* vmImage         - Kernel-only image for U-Boot ($(KBUILD_IMAGE))'
+  echo  '  install         - Install kernel using'
+  echo  '                     (your) ~/bin/$(INSTALLKERNEL) or'
+  echo  '                     (distribution) /sbin/$(INSTALLKERNEL) or'
+  echo  '                     install to $$(INSTALL_PATH)'
+  echo  '  dtbs            - Build device tree blobs for enabled boards'
+endef
diff --git a/arch/nios2/boot/Makefile b/arch/nios2/boot/Makefile
new file mode 100644
index 000000000000..59392dc0bdcb
--- /dev/null
+++ b/arch/nios2/boot/Makefile
@@ -0,0 +1,52 @@
+#
+# arch/nios2/boot/Makefile
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.  See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+UIMAGE_LOADADDR = $(shell $(NM) vmlinux | awk '$$NF == "_stext" {print $$1}')
+UIMAGE_ENTRYADDR = $(shell $(NM) vmlinux | awk '$$NF == "_start" {print $$1}')
+UIMAGE_COMPRESSION = gzip
+OBJCOPYFLAGS_vmlinux.bin := -O binary
+targets += vmlinux.bin vmlinux.gz vmImage
+$(obj)/vmlinux.bin: vmlinux FORCE
+        $(call if_changed,objcopy)
+$(obj)/vmlinux.gz: $(obj)/vmlinux.bin FORCE
+        $(call if_changed,gzip)
+$(obj)/vmImage: $(obj)/vmlinux.gz
+        $(call if_changed,uimage)
+        @$(kecho) 'Kernel: $@ is ready'
+# Rule to build device tree blobs
+DTB_SRC := $(patsubst "%",%,$(CONFIG_NIOS2_DTB_SOURCE))
+# Make sure the generated dtb gets removed during clean
+extra-$(CONFIG_NIOS2_DTB_SOURCE_BOOL) += system.dtb
+$(obj)/system.dtb: $(DTB_SRC) FORCE
+        $(call cmd,dtc)
+# Ensure system.dtb exists
+$(obj)/linked_dtb.o: $(obj)/system.dtb
+obj-$(CONFIG_NIOS2_DTB_SOURCE_BOOL) += linked_dtb.o
+targets += $(dtb-y)
+# Rule to build device tree blobs with make command
+$(obj)/%.dtb: $(src)/dts/%.dts FORCE
+        $(call if_changed_dep,dtc)
+$(obj)/dtbs: $(addprefix $(obj)/, $(dtb-y))
+clean-files := *.dtb
+install:
+        sh $(srctree)/$(src)/install.sh $(KERNELRELEASE) $(BOOTIMAGE) System.map "$(INSTALL_PATH)"
diff --git a/arch/nios2/boot/dts/3c120_devboard.dts b/arch/nios2/boot/dts/3c120_devboard.dts
new file mode 100644
index 000000000000..31c51f9a2f09
--- /dev/null
+++ b/arch/nios2/boot/dts/3c120_devboard.dts
@@ -0,0 +1,164 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * This file is generated by sopc2dts.
+ */
+/dts-v1/;
+/ {
+        model = "altr,qsys_ghrd_3c120";
+        compatible = "altr,qsys_ghrd_3c120";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu: cpu@0x0 {
+                        device_type = "cpu";
+                        compatible = "altr,nios2-1.0";
+                        reg = <0x00000000>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        clock-frequency = <125000000>;
+                        dcache-line-size = <32>;
+                        icache-line-size = <32>;
+                        dcache-size = <32768>;
+                        icache-size = <32768>;
+                        altr,implementation = "fast";
+                        altr,pid-num-bits = <8>;
+                        altr,tlb-num-ways = <16>;
+                        altr,tlb-num-entries = <128>;
+                        altr,tlb-ptr-sz = <7>;
+                        altr,has-div = <1>;
+                        altr,has-mul = <1>;
+                        altr,reset-addr = <0xc2800000>;
+                        altr,fast-tlb-miss-addr = <0xc7fff400>;
+                        altr,exception-addr = <0xd0000020>;
+                        altr,has-initda = <1>;
+                        altr,has-mmu = <1>;
+                };
+        };
+        memory@0 {
+                device_type = "memory";
+                reg = <0x10000000 0x08000000>,
+                        <0x07fff400 0x00000400>;
+        };
+        sopc@0 {
+                device_type = "soc";
+                ranges;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "altr,avalon", "simple-bus";
+                bus-frequency = <125000000>;
+                pb_cpu_to_io: bridge@0x8000000 {
+                        compatible = "simple-bus";
+                        reg = <0x08000000 0x00800000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x00002000 0x08002000 0x00002000>,
+                                <0x00004000 0x08004000 0x00000400>,
+                                <0x00004400 0x08004400 0x00000040>,
+                                <0x00004800 0x08004800 0x00000040>,
+                                <0x00004c80 0x08004c80 0x00000020>,
+                                <0x00004d50 0x08004d50 0x00000008>,
+                                <0x00008000 0x08008000 0x00000020>,
+                                <0x00400000 0x08400000 0x00000020>;
+                        timer_1ms: timer@0x400000 {
+                                compatible = "altr,timer-1.0";
+                                reg = <0x00400000 0x00000020>;
+                                interrupt-parent = <&cpu>;
+                                interrupts = <11>;
+                                clock-frequency = <125000000>;
+                        };
+                        timer_0: timer@0x8000 {
+                                compatible = "altr,timer-1.0";
+                                reg = < 0x00008000 0x00000020 >;
+                                interrupt-parent = < &cpu >;
+                                interrupts = < 5 >;
+                                clock-frequency = < 125000000 >;
+                        };
+                        jtag_uart: serial@0x4d50 {
+                                compatible = "altr,juart-1.0";
+                                reg = <0x00004d50 0x00000008>;
+                                interrupt-parent = <&cpu>;
+                                interrupts = <1>;
+                        };
+                        tse_mac: ethernet@0x4000 {
+                                compatible = "altr,tse-1.0";
+                                reg = <0x00004000 0x00000400>,
+                                        <0x00004400 0x00000040>,
+                                        <0x00004800 0x00000040>,
+                                        <0x00002000 0x00002000>;
+                                reg-names = "control_port", "rx_csr", "tx_csr", "s1";
+                                interrupt-parent = <&cpu>;
+                                interrupts = <2 3>;
+                                interrupt-names = "rx_irq", "tx_irq";
+                                rx-fifo-depth = <8192>;
+                                tx-fifo-depth = <8192>;
+                                max-frame-size = <1518>;
+                                local-mac-address = [ 00 00 00 00 00 00 ];
+                                phy-mode = "rgmii-id";
+                                phy-handle = <&phy0>;
+                                tse_mac_mdio: mdio {
+                                        compatible = "altr,tse-mdio";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        phy0: ethernet-phy@18 {
+                                                reg = <18>;
+                                                device_type = "ethernet-phy";
+                                        };
+                                };
+                        };
+                        uart: serial@0x4c80 {
+                                compatible = "altr,uart-1.0";
+                                reg = <0x00004c80 0x00000020>;
+                                interrupt-parent = <&cpu>;
+                                interrupts = <10>;
+                                current-speed = <115200>;
+                                clock-frequency = <62500000>;
+                        };
+                };
+                cfi_flash_64m: flash@0x0 {
+                        compatible = "cfi-flash";
+                        reg = <0x00000000 0x04000000>;
+                        bank-width = <2>;
+                        device-width = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        partition@800000 {
+                                reg = <0x00800000 0x01e00000>;
+                                label = "JFFS2 Filesystem";
+                        };
+                };
+        };
+        chosen {
+                bootargs = "debug console=ttyJ0,115200";
+        };
+};
diff --git a/arch/nios2/boot/install.sh b/arch/nios2/boot/install.sh
new file mode 100644
index 000000000000..3cb3f468bc51
--- /dev/null
+++ b/arch/nios2/boot/install.sh
@@ -0,0 +1,52 @@
+#!/bin/sh
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.  See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+# Copyright (C) 1995 by Linus Torvalds
+#
+# Adapted from code in arch/i386/boot/Makefile by H. Peter Anvin
+#
+# "make install" script for nios2 architecture
+#
+# Arguments:
+#   $1 - kernel version
+#   $2 - kernel image file
+#   $3 - kernel map file
+#   $4 - default install path (blank if root directory)
+#
+verify () {
+        if [ ! -f "$1" ]; then
+                echo ""                                                   1>&2
+                echo " *** Missing file: $1"                              1>&2
+                echo ' *** You need to run "make" before "make install".' 1>&2
+                echo ""                                                   1>&2
+                exit 1
+        fi
+}
+# Make sure the files actually exist
+verify "$2"
+verify "$3"
+# User may have a custom install script
+if [ -x ~/bin/${INSTALLKERNEL} ]; then exec ~/bin/${INSTALLKERNEL} "$@"; fi
+if [ -x /sbin/${INSTALLKERNEL} ]; then exec /sbin/${INSTALLKERNEL} "$@"; fi
+# Default install - same as make zlilo
+if [ -f $4/vmlinuz ]; then
+        mv $4/vmlinuz $4/vmlinuz.old
+fi
+if [ -f $4/System.map ]; then
+        mv $4/System.map $4/System.old
+fi
+cat $2 > $4/vmlinuz
+cp $3 $4/System.map
+sync
diff --git a/arch/nios2/boot/linked_dtb.S b/arch/nios2/boot/linked_dtb.S
new file mode 100644
index 000000000000..071f922db338
--- /dev/null
+++ b/arch/nios2/boot/linked_dtb.S
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2011 Thomas Chou <thomas@wytron.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+.section .dtb.init.rodata,"a"
+.incbin "arch/nios2/boot/system.dtb"
diff --git a/arch/nios2/configs/3c120_defconfig b/arch/nios2/configs/3c120_defconfig
new file mode 100644
index 000000000000..87541f0a5d6e
--- /dev/null
+++ b/arch/nios2/configs/3c120_defconfig
@@ -0,0 +1,77 @@
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSCTL_SYSCALL=y
+# CONFIG_ELF_CORE is not set
+# CONFIG_EPOLL is not set
+# CONFIG_SIGNALFD is not set
+# CONFIG_TIMERFD is not set
+# CONFIG_EVENTFD is not set
+# CONFIG_SHMEM is not set
+# CONFIG_AIO is not set
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_NIOS2_MEM_BASE=0x10000000
+CONFIG_NIOS2_HW_MUL_SUPPORT=y
+CONFIG_NIOS2_HW_DIV_SUPPORT=y
+CONFIG_CUSTOM_CACHE_SETTINGS=y
+CONFIG_NIOS2_DCACHE_SIZE=0x8000
+CONFIG_NIOS2_ICACHE_SIZE=0x8000
+# CONFIG_NIOS2_CMDLINE_IGNORE_DTB is not set
+CONFIG_NIOS2_PASS_CMDLINE=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_FW_LOADER is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_NETDEVICES=y
+CONFIG_ALTERA_TSE=y
+CONFIG_MARVELL_PHY=y
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_VT is not set
+CONFIG_SERIAL_ALTERA_JTAGUART=y
+CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE=y
+CONFIG_SERIAL_ALTERA_UART=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+CONFIG_JFFS2_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_ROOT_NFS=y
+CONFIG_SUNRPC_DEBUG=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
diff --git a/arch/nios2/include/asm/Kbuild b/arch/nios2/include/asm/Kbuild
new file mode 100644
index 000000000000..01c75f36e8b3
--- /dev/null
+++ b/arch/nios2/include/asm/Kbuild
@@ -0,0 +1,65 @@
+generic-y += atomic.h
+generic-y += auxvec.h
+generic-y += barrier.h
+generic-y += bitops.h
+generic-y += bitsperlong.h
+generic-y += bug.h
+generic-y += bugs.h
+generic-y += clkdev.h
+generic-y += cputime.h
+generic-y += current.h
+generic-y += device.h
+generic-y += div64.h
+generic-y += dma.h
+generic-y += emergency-restart.h
+generic-y += errno.h
+generic-y += exec.h
+generic-y += fb.h
+generic-y += fcntl.h
+generic-y += ftrace.h
+generic-y += futex.h
+generic-y += hardirq.h
+generic-y += hw_irq.h
+generic-y += ioctl.h
+generic-y += ioctls.h
+generic-y += ipcbuf.h
+generic-y += irq_regs.h
+generic-y += irq_work.h
+generic-y += kdebug.h
+generic-y += kmap_types.h
+generic-y += kvm_para.h
+generic-y += local.h
+generic-y += mcs_spinlock.h
+generic-y += mman.h
+generic-y += module.h
+generic-y += msgbuf.h
+generic-y += param.h
+generic-y += pci.h
+generic-y += percpu.h
+generic-y += poll.h
+generic-y += posix_types.h
+generic-y += preempt.h
+generic-y += resource.h
+generic-y += scatterlist.h
+generic-y += sections.h
+generic-y += segment.h
+generic-y += sembuf.h
+generic-y += serial.h
+generic-y += shmbuf.h
+generic-y += shmparam.h
+generic-y += siginfo.h
+generic-y += signal.h
+generic-y += socket.h
+generic-y += sockios.h
+generic-y += spinlock.h
+generic-y += stat.h
+generic-y += statfs.h
+generic-y += termbits.h
+generic-y += termios.h
+generic-y += topology.h
+generic-y += trace_clock.h
+generic-y += types.h
+generic-y += unaligned.h
+generic-y += user.h
+generic-y += vga.h
+generic-y += xor.h
diff --git a/arch/nios2/include/asm/asm-macros.h b/arch/nios2/include/asm/asm-macros.h
new file mode 100644
index 000000000000..29fa2e4d7b00
--- /dev/null
+++ b/arch/nios2/include/asm/asm-macros.h
@@ -0,0 +1,309 @@
+/*
+ * Macro used to simplify coding multi-line assembler.
+ * Some of the bit test macro can simplify down to one line
+ * depending on the mask value.
+ *
+ * Copyright (C) 2004 Microtronix Datacom Ltd.
+ *
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ */
+#ifndef _ASM_NIOS2_ASMMACROS_H
+#define _ASM_NIOS2_ASMMACROS_H
+/*
+ * ANDs reg2 with mask and places the result in reg1.
+ *
+ * You cannnot use the same register for reg1 & reg2.
+ */
+.macro ANDI32   reg1, reg2, mask
+.if \mask & 0xffff
+        .if \mask & 0xffff0000
+                movhi   \reg1, %hi(\mask)
+                movui   \reg1, %lo(\mask)
+                and     \reg1, \reg1, \reg2
+        .else
+                andi    \reg1, \reg2, %lo(\mask)
+        .endif
+.else
+        andhi   \reg1, \reg2, %hi(\mask)
+.endif
+.endm
+/*
+ * ORs reg2 with mask and places the result in reg1.
+ *
+ * It is safe to use the same register for reg1 & reg2.
+ */
+.macro ORI32    reg1, reg2, mask
+.if \mask & 0xffff
+        .if \mask & 0xffff0000
+                orhi    \reg1, \reg2, %hi(\mask)
+                ori     \reg1, \reg2, %lo(\mask)
+        .else
+                ori     \reg1, \reg2, %lo(\mask)
+        .endif
+.else
+        orhi    \reg1, \reg2, %hi(\mask)
+.endif
+.endm
+/*
+ * XORs reg2 with mask and places the result in reg1.
+ *
+ * It is safe to use the same register for reg1 & reg2.
+ */
+.macro XORI32   reg1, reg2, mask
+.if \mask & 0xffff
+        .if \mask & 0xffff0000
+                xorhi   \reg1, \reg2, %hi(\mask)
+                xori    \reg1, \reg1, %lo(\mask)
+        .else
+                xori    \reg1, \reg2, %lo(\mask)
+        .endif
+.else
+        xorhi   \reg1, \reg2, %hi(\mask)
+.endif
+.endm
+/*
+ * This is a support macro for BTBZ & BTBNZ.  It checks
+ * the bit to make sure it is valid 32 value.
+ *
+ * It is safe to use the same register for reg1 & reg2.
+ */
+.macro BT       reg1, reg2, bit
+.if \bit > 31
+        .err
+.else
+        .if \bit < 16
+                andi    \reg1, \reg2, (1 << \bit)
+        .else
+                andhi   \reg1, \reg2, (1 << (\bit - 16))
+        .endif
+.endif
+.endm
+/*
+ * Tests the bit in reg2 and branches to label if the
+ * bit is zero.  The result of the bit test is stored in reg1.
+ *
+ * It is safe to use the same register for reg1 & reg2.
+ */
+.macro BTBZ     reg1, reg2, bit, label
+        BT      \reg1, \reg2, \bit
+        beq     \reg1, r0, \label
+.endm
+/*
+ * Tests the bit in reg2 and branches to label if the
+ * bit is non-zero.  The result of the bit test is stored in reg1.
+ *
+ * It is safe to use the same register for reg1 & reg2.
+ */
+.macro BTBNZ    reg1, reg2, bit, label
+        BT      \reg1, \reg2, \bit
+        bne     \reg1, r0, \label
+.endm
+/*
+ * Tests the bit in reg2 and then compliments the bit in reg2.
+ * The result of the bit test is stored in reg1.
+ *
+ * It is NOT safe to use the same register for reg1 & reg2.
+ */
+.macro BTC      reg1, reg2, bit
+.if \bit > 31
+        .err
+.else
+        .if \bit < 16
+                andi    \reg1, \reg2, (1 << \bit)
+                xori    \reg2, \reg2, (1 << \bit)
+        .else
+                andhi   \reg1, \reg2, (1 << (\bit - 16))
+                xorhi   \reg2, \reg2, (1 << (\bit - 16))
+        .endif
+.endif
+.endm
+/*
+ * Tests the bit in reg2 and then sets the bit in reg2.
+ * The result of the bit test is stored in reg1.
+ *
+ * It is NOT safe to use the same register for reg1 & reg2.
+ */
+.macro BTS      reg1, reg2, bit
+.if \bit > 31
+        .err
+.else
+        .if \bit < 16
+                andi    \reg1, \reg2, (1 << \bit)
+                ori     \reg2, \reg2, (1 << \bit)
+        .else
+                andhi   \reg1, \reg2, (1 << (\bit - 16))
+                orhi    \reg2, \reg2, (1 << (\bit - 16))
+        .endif
+.endif
+.endm
+/*
+ * Tests the bit in reg2 and then resets the bit in reg2.
+ * The result of the bit test is stored in reg1.
+ *
+ * It is NOT safe to use the same register for reg1 & reg2.
+ */
+.macro BTR      reg1, reg2, bit
+.if \bit > 31
+        .err
+.else
+        .if \bit < 16
+                andi    \reg1, \reg2, (1 << \bit)
+                andi    \reg2, \reg2, %lo(~(1 << \bit))
+        .else
+                andhi   \reg1, \reg2, (1 << (\bit - 16))
+                andhi   \reg2, \reg2, %lo(~(1 << (\bit - 16)))
+        .endif
+.endif
+.endm
+/*
+ * Tests the bit in reg2 and then compliments the bit in reg2.
+ * The result of the bit test is stored in reg1.  If the
+ * original bit was zero it branches to label.
+ *
+ * It is NOT safe to use the same register for reg1 & reg2.
+ */
+.macro BTCBZ    reg1, reg2, bit, label
+        BTC     \reg1, \reg2, \bit
+        beq     \reg1, r0, \label
+.endm
+/*
+ * Tests the bit in reg2 and then compliments the bit in reg2.
+ * The result of the bit test is stored in reg1.  If the
+ * original bit was non-zero it branches to label.
+ *
+ * It is NOT safe to use the same register for reg1 & reg2.
+ */
+.macro BTCBNZ   reg1, reg2, bit, label
+        BTC     \reg1, \reg2, \bit
+        bne     \reg1, r0, \label
+.endm
+/*
+ * Tests the bit in reg2 and then sets the bit in reg2.
+ * The result of the bit test is stored in reg1.  If the
+ * original bit was zero it branches to label.
+ *
+ * It is NOT safe to use the same register for reg1 & reg2.
+ */
+.macro BTSBZ    reg1, reg2, bit, label
+        BTS     \reg1, \reg2, \bit
+        beq     \reg1, r0, \label
+.endm
+/*
+ * Tests the bit in reg2 and then sets the bit in reg2.
+ * The result of the bit test is stored in reg1.  If the
+ * original bit was non-zero it branches to label.
+ *
+ * It is NOT safe to use the same register for reg1 & reg2.
+ */
+.macro BTSBNZ   reg1, reg2, bit, label
+        BTS     \reg1, \reg2, \bit
+        bne     \reg1, r0, \label
+.endm
+/*
+ * Tests the bit in reg2 and then resets the bit in reg2.
+ * The result of the bit test is stored in reg1.  If the
+ * original bit was zero it branches to label.
+ *
+ * It is NOT safe to use the same register for reg1 & reg2.
+ */
+.macro BTRBZ    reg1, reg2, bit, label
+        BTR     \reg1, \reg2, \bit
+        bne     \reg1, r0, \label
+.endm
+/*
+ * Tests the bit in reg2 and then resets the bit in reg2.
+ * The result of the bit test is stored in reg1.  If the
+ * original bit was non-zero it branches to label.
+ *
+ * It is NOT safe to use the same register for reg1 & reg2.
+ */
+.macro BTRBNZ   reg1, reg2, bit, label
+        BTR     \reg1, \reg2, \bit
+        bne     \reg1, r0, \label
+.endm
+/*
+ * Tests the bits in mask against reg2 stores the result in reg1.
+ * If the all the bits in the mask are zero it branches to label.
+ *
+ * It is safe to use the same register for reg1 & reg2.
+ */
+.macro TSTBZ    reg1, reg2, mask, label
+        ANDI32  \reg1, \reg2, \mask
+        beq     \reg1, r0, \label
+.endm
+/*
+ * Tests the bits in mask against reg2 stores the result in reg1.
+ * If the any of the bits in the mask are 1 it branches to label.
+ *
+ * It is safe to use the same register for reg1 & reg2.
+ */
+.macro TSTBNZ   reg1, reg2, mask, label
+        ANDI32  \reg1, \reg2, \mask
+        bne     \reg1, r0, \label
+.endm
+/*
+ * Pushes reg onto the stack.
+ */
+.macro PUSH     reg
+        addi    sp, sp, -4
+        stw     \reg, 0(sp)
+.endm
+/*
+ * Pops the top of the stack into reg.
+ */
+.macro POP      reg
+        ldw     \reg, 0(sp)
+        addi    sp, sp, 4
+.endm
+#endif /* _ASM_NIOS2_ASMMACROS_H */
diff --git a/arch/nios2/include/asm/asm-offsets.h b/arch/nios2/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..5b9f5e04a058
--- /dev/null
+++ b/arch/nios2/include/asm/asm-offsets.h
@@ -0,0 +1,20 @@
+/*
+ *  Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
+ *  Copyright (C) 2009 Thomas Chou <thomas@wytron.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#include <generated/asm-offsets.h>
diff --git a/arch/nios2/include/asm/cache.h b/arch/nios2/include/asm/cache.h
new file mode 100644
index 000000000000..2293cf57e307
--- /dev/null
+++ b/arch/nios2/include/asm/cache.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2004 Microtronix Datacom Ltd.
+ *
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ */
+#ifndef _ASM_NIOS2_CACHE_H
+#define _ASM_NIOS2_CACHE_H
+#define NIOS2_DCACHE_SIZE       CONFIG_NIOS2_DCACHE_SIZE
+#define NIOS2_ICACHE_SIZE       CONFIG_NIOS2_ICACHE_SIZE
+#define NIOS2_DCACHE_LINE_SIZE  CONFIG_NIOS2_DCACHE_LINE_SIZE
+#define NIOS2_ICACHE_LINE_SHIFT 5
+#define NIOS2_ICACHE_LINE_SIZE  (1 << NIOS2_ICACHE_LINE_SHIFT)
+/* bytes per L1 cache line */
+#define L1_CACHE_SHIFT          NIOS2_ICACHE_LINE_SHIFT
+#define L1_CACHE_BYTES          NIOS2_ICACHE_LINE_SIZE
+#define ARCH_DMA_MINALIGN       L1_CACHE_BYTES
+#define __cacheline_aligned
+#define ____cacheline_aligned
+#endif
diff --git a/arch/nios2/include/asm/cacheflush.h b/arch/nios2/include/asm/cacheflush.h
new file mode 100644
index 000000000000..52abba973dc2
--- /dev/null
+++ b/arch/nios2/include/asm/cacheflush.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2003 Microtronix Datacom Ltd.
+ * Copyright (C) 2000-2002 Greg Ungerer <gerg@snapgear.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_NIOS2_CACHEFLUSH_H
+#define _ASM_NIOS2_CACHEFLUSH_H
+#include <linux/mm_types.h>
+/*
+ * This flag is used to indicate that the page pointed to by a pte is clean
+ * and does not require cleaning before returning it to the user.
+ */
+#define PG_dcache_clean PG_arch_1
+struct mm_struct;
+extern void flush_cache_all(void);
+extern void flush_cache_mm(struct mm_struct *mm);
+extern void flush_cache_dup_mm(struct mm_struct *mm);
+extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
+        unsigned long end);
+extern void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
+        unsigned long pfn);
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
+extern void flush_dcache_page(struct page *page);
+extern void flush_icache_range(unsigned long start, unsigned long end);
+extern void flush_icache_page(struct vm_area_struct *vma, struct page *page);
+#define flush_cache_vmap(start, end)            flush_dcache_range(start, end)
+#define flush_cache_vunmap(start, end)          flush_dcache_range(start, end)
+extern void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
+                                unsigned long user_vaddr,
+                                void *dst, void *src, int len);
+extern void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
+                                unsigned long user_vaddr,
+                                void *dst, void *src, int len);
+extern void flush_dcache_range(unsigned long start, unsigned long end);
+extern void invalidate_dcache_range(unsigned long start, unsigned long end);
+#define flush_dcache_mmap_lock(mapping)         do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
+#endif /* _ASM_NIOS2_CACHEFLUSH_H */
diff --git a/arch/nios2/include/asm/checksum.h b/arch/nios2/include/asm/checksum.h
new file mode 100644
index 000000000000..6bc1f0d5df7b
--- /dev/null
+++ b/arch/nios2/include/asm/checksum.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2004 Microtronix Datacom Ltd.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_NIOS_CHECKSUM_H
+#define _ASM_NIOS_CHECKSUM_H
+/* Take these from lib/checksum.c */
+extern __wsum csum_partial(const void *buff, int len, __wsum sum);
+extern __wsum csum_partial_copy(const void *src, void *dst, int len,
+                                __wsum sum);
+extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
+                                        int len, __wsum sum, int *csum_err);
+#define csum_partial_copy_nocheck(src, dst, len, sum)   \
+        csum_partial_copy((src), (dst), (len), (sum))
+extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
+extern __sum16 ip_compute_csum(const void *buff, int len);
+/*
+ * Fold a partial checksum
+ */
+static inline __sum16 csum_fold(__wsum sum)
+{
+        __asm__ __volatile__(
+                "add    %0, %1, %0\n"
+                "cmpltu r8, %0, %1\n"
+                "srli   %0, %0, 16\n"
+                "add    %0, %0, r8\n"
+                "nor    %0, %0, %0\n"
+                : "=r" (sum)
+                : "r" (sum << 16), "0" (sum)
+                : "r8");
+        return (__force __sum16) sum;
+}
+/*
+ * computes the checksum of the TCP/UDP pseudo-header
+ * returns a 16-bit checksum, already complemented
+ */
+#define csum_tcpudp_nofold csum_tcpudp_nofold
+static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
+                                        unsigned short len,
+                                        unsigned short proto,
+                                        __wsum sum)
+{
+        __asm__ __volatile__(
+                "add    %0, %1, %0\n"
+                "cmpltu r8, %0, %1\n"
+                "add    %0, %0, r8\n"   /* add carry */
+                "add    %0, %2, %0\n"
+                "cmpltu r8, %0, %2\n"
+                "add    %0, %0, r8\n"   /* add carry */
+                "add    %0, %3, %0\n"
+                "cmpltu r8, %0, %3\n"
+                "add    %0, %0, r8\n"   /* add carry */
+                : "=r" (sum), "=r" (saddr)
+                : "r" (daddr), "r" ((ntohs(len) << 16) + (proto * 256)),
+                  "0" (sum),
+                  "1" (saddr)
+                : "r8");
+        return sum;
+}
+static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
+                                        unsigned short len,
+                                        unsigned short proto, __wsum sum)
+{
+        return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
+}
+#endif /* _ASM_NIOS_CHECKSUM_H */
diff --git a/arch/nios2/include/asm/cmpxchg.h b/arch/nios2/include/asm/cmpxchg.h
new file mode 100644
index 000000000000..85938711542d
--- /dev/null
+++ b/arch/nios2/include/asm/cmpxchg.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2004 Microtronix Datacom Ltd.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_NIOS2_CMPXCHG_H
+#define _ASM_NIOS2_CMPXCHG_H
+#include <linux/irqflags.h>
+#define xchg(ptr, x)    \
+        ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))
+struct __xchg_dummy { unsigned long a[100]; };
+#define __xg(x)         ((volatile struct __xchg_dummy *)(x))
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
+                                        int size)
+{
+        unsigned long tmp, flags;
+        local_irq_save(flags);
+        switch (size) {
+        case 1:
+                __asm__ __volatile__(
+                        "ldb    %0, %2\n"
+                        "stb    %1, %2\n"
+                        : "=&r" (tmp)
+                        : "r" (x), "m" (*__xg(ptr))
+                        : "memory");
+                break;
+        case 2:
+                __asm__ __volatile__(
+                        "ldh    %0, %2\n"
+                        "sth    %1, %2\n"
+                        : "=&r" (tmp)
+                        : "r" (x), "m" (*__xg(ptr))
+                        : "memory");
+                break;
+        case 4:
+                __asm__ __volatile__(
+                        "ldw    %0, %2\n"
+                        "stw    %1, %2\n"
+                        : "=&r" (tmp)
+                        : "r" (x), "m" (*__xg(ptr))
+                        : "memory");
+                break;
+        }
+        local_irq_restore(flags);
+        return tmp;
+}
+#include <asm-generic/cmpxchg.h>
+#include <asm-generic/cmpxchg-local.h>
+#endif /* _ASM_NIOS2_CMPXCHG_H */
diff --git a/arch/nios2/include/asm/cpuinfo.h b/arch/nios2/include/asm/cpuinfo.h
new file mode 100644
index 000000000000..e88fcae464d9
--- /dev/null
+++ b/arch/nios2/include/asm/cpuinfo.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#ifndef _ASM_NIOS2_CPUINFO_H
+#define _ASM_NIOS2_CPUINFO_H
+#include <linux/types.h>
+struct cpuinfo {
+        /* Core CPU configuration */
+        char cpu_impl[12];
+        u32 cpu_clock_freq;
+        u32 mmu;
+        u32 has_div;
+        u32 has_mul;
+        u32 has_mulx;
+        /* CPU caches */
+        u32 icache_line_size;
+        u32 icache_size;
+        u32 dcache_line_size;
+        u32 dcache_size;
+        /* TLB */
+        u32 tlb_pid_num_bits;   /* number of bits used for the PID in TLBMISC */
+        u32 tlb_num_ways;
+        u32 tlb_num_ways_log2;
+        u32 tlb_num_entries;
+        u32 tlb_num_lines;
+        u32 tlb_ptr_sz;
+        /* Addresses */
+        u32 reset_addr;
+        u32 exception_addr;
+        u32 fast_tlb_miss_exc_addr;
+};
+extern struct cpuinfo cpuinfo;
+extern void setup_cpuinfo(void);
+#endif /* _ASM_NIOS2_CPUINFO_H */
diff --git a/arch/nios2/include/asm/delay.h b/arch/nios2/include/asm/delay.h
new file mode 100644
index 000000000000..098e49bf3aa3
--- /dev/null
+++ b/arch/nios2/include/asm/delay.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2014 Altera Corporation
+ * Copyright (C) 2004 Microtronix Datacom Ltd
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_NIOS2_DELAY_H
+#define _ASM_NIOS2_DELAY_H
+#include <asm-generic/delay.h>
+/* Undefined functions to get compile-time errors */
+extern void __bad_udelay(void);
+extern void __bad_ndelay(void);
+extern unsigned long loops_per_jiffy;
+#endif /* _ASM_NIOS2_DELAY_H */
diff --git a/arch/nios2/include/asm/dma-mapping.h b/arch/nios2/include/asm/dma-mapping.h
new file mode 100644
index 000000000000..b5567233f7f1
--- /dev/null
+++ b/arch/nios2/include/asm/dma-mapping.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2009 Wind River Systems Inc
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file COPYING in the main directory of this
+ * archive for more details.
+ */
+#ifndef _ASM_NIOS2_DMA_MAPPING_H
+#define _ASM_NIOS2_DMA_MAPPING_H
+#include <linux/scatterlist.h>
+#include <linux/cache.h>
+#include <asm/cacheflush.h>
+static inline void __dma_sync_for_device(void *vaddr, size_t size,
+                              enum dma_data_direction direction)
+{
+        switch (direction) {
+        case DMA_FROM_DEVICE:
+                invalidate_dcache_range((unsigned long)vaddr,
+                        (unsigned long)(vaddr + size));
+                break;
+        case DMA_TO_DEVICE:
+                /*
+                 * We just need to flush the caches here , but Nios2 flush
+                 * instruction will do both writeback and invalidate.
+                 */
+        case DMA_BIDIRECTIONAL: /* flush and invalidate */
+                flush_dcache_range((unsigned long)vaddr,
+                        (unsigned long)(vaddr + size));
+                break;
+        default:
+                BUG();
+        }
+}
+static inline void __dma_sync_for_cpu(void *vaddr, size_t size,
+                              enum dma_data_direction direction)
+{
+        switch (direction) {
+        case DMA_BIDIRECTIONAL:
+        case DMA_FROM_DEVICE:
+                invalidate_dcache_range((unsigned long)vaddr,
+                        (unsigned long)(vaddr + size));
+                break;
+        case DMA_TO_DEVICE:
+                break;
+        default:
+                BUG();
+        }
+}
+#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
+#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
+void *dma_alloc_coherent(struct device *dev, size_t size,
+                           dma_addr_t *dma_handle, gfp_t flag);
+void dma_free_coherent(struct device *dev, size_t size,
+                         void *vaddr, dma_addr_t dma_handle);
+static inline dma_addr_t dma_map_single(struct device *dev, void *ptr,
+                                        size_t size,
+                                        enum dma_data_direction direction)
+{
+        BUG_ON(!valid_dma_direction(direction));
+        __dma_sync_for_device(ptr, size, direction);
+        return virt_to_phys(ptr);
+}
+static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
+                                size_t size, enum dma_data_direction direction)
+{
+}
+extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
+        enum dma_data_direction direction);
+extern dma_addr_t dma_map_page(struct device *dev, struct page *page,
+        unsigned long offset, size_t size, enum dma_data_direction direction);
+extern void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
+        size_t size, enum dma_data_direction direction);
+extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+        int nhwentries, enum dma_data_direction direction);
+extern void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
+        size_t size, enum dma_data_direction direction);
+extern void dma_sync_single_for_device(struct device *dev,
+        dma_addr_t dma_handle, size_t size, enum dma_data_direction direction);
+extern void dma_sync_single_range_for_cpu(struct device *dev,
+        dma_addr_t dma_handle, unsigned long offset, size_t size,
+        enum dma_data_direction direction);
+extern void dma_sync_single_range_for_device(struct device *dev,
+        dma_addr_t dma_handle, unsigned long offset, size_t size,
+        enum dma_data_direction direction);
+extern void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
+        int nelems, enum dma_data_direction direction);
+extern void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
+        int nelems, enum dma_data_direction direction);
+static inline int dma_supported(struct device *dev, u64 mask)
+{
+        return 1;
+}
+static inline int dma_set_mask(struct device *dev, u64 mask)
+{
+        if (!dev->dma_mask || !dma_supported(dev, mask))
+                return -EIO;
+        *dev->dma_mask = mask;
+        return 0;
+}
+static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
+{
+        return 0;
+}
+/*
+* dma_alloc_noncoherent() returns non-cacheable memory, so there's no need to
+* do any flushing here.
+*/
+static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
+                                  enum dma_data_direction direction)
+{
+}
+/* drivers/base/dma-mapping.c */
+extern int dma_common_mmap(struct device *dev, struct vm_area_struct *vma,
+                void *cpu_addr, dma_addr_t dma_addr, size_t size);
+extern int dma_common_get_sgtable(struct device *dev, struct sg_table *sgt,
+                void *cpu_addr, dma_addr_t dma_addr,
+                size_t size);
+#define dma_mmap_coherent(d, v, c, h, s) dma_common_mmap(d, v, c, h, s)
+#define dma_get_sgtable(d, t, v, h, s) dma_common_get_sgtable(d, t, v, h, s)
+#endif /* _ASM_NIOS2_DMA_MAPPING_H */
diff --git a/arch/nios2/include/asm/elf.h b/arch/nios2/include/asm/elf.h
new file mode 100644
index 000000000000..b7d655dff731
--- /dev/null
+++ b/arch/nios2/include/asm/elf.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#ifndef _ASM_NIOS2_ELF_H
+#define _ASM_NIOS2_ELF_H
+#include <uapi/asm/elf.h>
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x) ((x)->e_machine == EM_ALTERA_NIOS2)
+#define ELF_PLAT_INIT(_r, load_addr)
+#define CORE_DUMP_USE_REGSET
+#define ELF_EXEC_PAGESIZE       4096
+/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
+   use of this is to invoke "./ld.so someprog" to test out a new version of
+   the loader.  We need to make sure that it is out of the way of the program
+   that it will "exec", and that there is sufficient room for the brk.  */
+#define ELF_ET_DYN_BASE         0xD0000000UL
+/* regs is struct pt_regs, pr_reg is elf_gregset_t (which is
+   now struct_user_regs, they are different) */
+#define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1
+struct linux_binprm;
+extern int arch_setup_additional_pages(struct linux_binprm *bprm,
+        int uses_interp);
+#define ELF_CORE_COPY_REGS(pr_reg, regs)                                \
+{ do {                                                                  \
+        /* Bleech. */                                                   \
+        pr_reg[0]  = regs->r8;                                          \
+        pr_reg[1]  = regs->r9;                                          \
+        pr_reg[2]  = regs->r10;                                         \
+        pr_reg[3]  = regs->r11;                                         \
+        pr_reg[4]  = regs->r12;                                         \
+        pr_reg[5]  = regs->r13;                                         \
+        pr_reg[6]  = regs->r14;                                         \
+        pr_reg[7]  = regs->r15;                                         \
+        pr_reg[8]  = regs->r1;                                          \
+        pr_reg[9]  = regs->r2;                                          \
+        pr_reg[10] = regs->r3;                                          \
+        pr_reg[11] = regs->r4;                                          \
+        pr_reg[12] = regs->r5;                                          \
+        pr_reg[13] = regs->r6;                                          \
+        pr_reg[14] = regs->r7;                                          \
+        pr_reg[15] = regs->orig_r2;                                     \
+        pr_reg[16] = regs->ra;                                          \
+        pr_reg[17] = regs->fp;                                          \
+        pr_reg[18] = regs->sp;                                          \
+        pr_reg[19] = regs->gp;                                          \
+        pr_reg[20] = regs->estatus;                                     \
+        pr_reg[21] = regs->ea;                                          \
+        pr_reg[22] = regs->orig_r7;                                     \
+        {                                                               \
+                struct switch_stack *sw = ((struct switch_stack *)regs) - 1; \
+                pr_reg[23] = sw->r16;                                   \
+                pr_reg[24] = sw->r17;                                   \
+                pr_reg[25] = sw->r18;                                   \
+                pr_reg[26] = sw->r19;                                   \
+                pr_reg[27] = sw->r20;                                   \
+                pr_reg[28] = sw->r21;                                   \
+                pr_reg[29] = sw->r22;                                   \
+                pr_reg[30] = sw->r23;                                   \
+                pr_reg[31] = sw->fp;                                    \
+                pr_reg[32] = sw->gp;                                    \
+                pr_reg[33] = sw->ra;                                    \
+        }                                                               \
+} while (0); }
+/* This yields a mask that user programs can use to figure out what
+   instruction set this cpu supports.  */
+#define ELF_HWCAP       (0)
+/* This yields a string that ld.so will use to load implementation
+   specific libraries for optimization.  This is more specific in
+   intent than poking at uname or /proc/cpuinfo.  */
+#define ELF_PLATFORM  (NULL)
+#endif /* _ASM_NIOS2_ELF_H */
diff --git a/arch/nios2/include/asm/entry.h b/arch/nios2/include/asm/entry.h
new file mode 100644
index 000000000000..cf37f55efbc2
--- /dev/null
+++ b/arch/nios2/include/asm/entry.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2004 Microtronix Datacom Ltd.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_NIOS2_ENTRY_H
+#define _ASM_NIOS2_ENTRY_H
+#ifdef __ASSEMBLY__
+#include <asm/processor.h>
+#include <asm/registers.h>
+#include <asm/asm-offsets.h>
+/*
+ * Standard Nios2 interrupt entry and exit macros.
+ * Must be called with interrupts disabled.
+ */
+.macro SAVE_ALL
+        rdctl   r24, estatus
+        andi    r24, r24, ESTATUS_EU
+        beq     r24, r0, 1f /* In supervisor mode, already on kernel stack */
+        movia   r24, _current_thread    /* Switch to current kernel stack */
+        ldw     r24, 0(r24)             /* using the thread_info */
+        addi    r24, r24, THREAD_SIZE-PT_REGS_SIZE
+        stw     sp, PT_SP(r24)          /* Save user stack before changing */
+        mov     sp, r24
+        br      2f
+1 :     mov     r24, sp
+        addi    sp, sp, -PT_REGS_SIZE   /* Backup the kernel stack pointer */
+        stw     r24, PT_SP(sp)
+2 :     stw     r1, PT_R1(sp)
+        stw     r2, PT_R2(sp)
+        stw     r3, PT_R3(sp)
+        stw     r4, PT_R4(sp)
+        stw     r5, PT_R5(sp)
+        stw     r6, PT_R6(sp)
+        stw     r7, PT_R7(sp)
+        stw     r8, PT_R8(sp)
+        stw     r9, PT_R9(sp)
+        stw     r10, PT_R10(sp)
+        stw     r11, PT_R11(sp)
+        stw     r12, PT_R12(sp)
+        stw     r13, PT_R13(sp)
+        stw     r14, PT_R14(sp)
+        stw     r15, PT_R15(sp)
+        stw     r2, PT_ORIG_R2(sp)
+        stw     r7, PT_ORIG_R7(sp)
+        stw     ra, PT_RA(sp)
+        stw     fp, PT_FP(sp)
+        stw     gp, PT_GP(sp)
+        rdctl   r24, estatus
+        stw     r24, PT_ESTATUS(sp)
+        stw     ea, PT_EA(sp)
+.endm
+.macro RESTORE_ALL
+        ldw     r1, PT_R1(sp)           /* Restore registers */
+        ldw     r2, PT_R2(sp)
+        ldw     r3, PT_R3(sp)
+        ldw     r4, PT_R4(sp)
+        ldw     r5, PT_R5(sp)
+        ldw     r6, PT_R6(sp)
+        ldw     r7, PT_R7(sp)
+        ldw     r8, PT_R8(sp)
+        ldw     r9, PT_R9(sp)
+        ldw     r10, PT_R10(sp)
+        ldw     r11, PT_R11(sp)
+        ldw     r12, PT_R12(sp)
+        ldw     r13, PT_R13(sp)
+        ldw     r14, PT_R14(sp)
+        ldw     r15, PT_R15(sp)
+        ldw     ra, PT_RA(sp)
+        ldw     fp, PT_FP(sp)
+        ldw     gp, PT_GP(sp)
+        ldw     r24, PT_ESTATUS(sp)
+        wrctl   estatus, r24
+        ldw     ea, PT_EA(sp)
+        ldw     sp, PT_SP(sp)           /* Restore sp last */
+.endm
+.macro  SAVE_SWITCH_STACK
+        addi    sp, sp, -SWITCH_STACK_SIZE
+        stw     r16, SW_R16(sp)
+        stw     r17, SW_R17(sp)
+        stw     r18, SW_R18(sp)
+        stw     r19, SW_R19(sp)
+        stw     r20, SW_R20(sp)
+        stw     r21, SW_R21(sp)
+        stw     r22, SW_R22(sp)
+        stw     r23, SW_R23(sp)
+        stw     fp, SW_FP(sp)
+        stw     gp, SW_GP(sp)
+        stw     ra, SW_RA(sp)
+.endm
+.macro  RESTORE_SWITCH_STACK
+        ldw     r16, SW_R16(sp)
+        ldw     r17, SW_R17(sp)
+        ldw     r18, SW_R18(sp)
+        ldw     r19, SW_R19(sp)
+        ldw     r20, SW_R20(sp)
+        ldw     r21, SW_R21(sp)
+        ldw     r22, SW_R22(sp)
+        ldw     r23, SW_R23(sp)
+        ldw     fp, SW_FP(sp)
+        ldw     gp, SW_GP(sp)
+        ldw     ra, SW_RA(sp)
+        addi    sp, sp, SWITCH_STACK_SIZE
+.endm
+#endif /* __ASSEMBLY__ */
+#endif /* _ASM_NIOS2_ENTRY_H */
diff --git a/arch/nios2/include/asm/io.h b/arch/nios2/include/asm/io.h
new file mode 100644
index 000000000000..9102bfd3fa1c
--- /dev/null
+++ b/arch/nios2/include/asm/io.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2014 Altera Corporation
+ * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2004 Microtronix Datacom Ltd.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_NIOS2_IO_H
+#define _ASM_NIOS2_IO_H
+#include <linux/types.h>
+#include <asm/pgtable-bits.h>
+/* PCI is not supported in nios2, set this to 0. */
+#define IO_SPACE_LIMIT 0
+#define readb_relaxed(addr)     readb(addr)
+#define readw_relaxed(addr)     readw(addr)
+#define readl_relaxed(addr)     readl(addr)
+#define writeb_relaxed(x, addr) writeb(x, addr)
+#define writew_relaxed(x, addr) writew(x, addr)
+#define writel_relaxed(x, addr) writel(x, addr)
+extern void __iomem *__ioremap(unsigned long physaddr, unsigned long size,
+                        unsigned long cacheflag);
+extern void __iounmap(void __iomem *addr);
+static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
+{
+        return __ioremap(physaddr, size, 0);
+}
+static inline void __iomem *ioremap_nocache(unsigned long physaddr,
+                                                unsigned long size)
+{
+        return __ioremap(physaddr, size, 0);
+}
+static inline void iounmap(void __iomem *addr)
+{
+        __iounmap(addr);
+}
+/* Pages to physical address... */
+#define page_to_phys(page)      virt_to_phys(page_to_virt(page))
+#define page_to_bus(page)       page_to_virt(page)
+/* Macros used for converting between virtual and physical mappings. */
+#define phys_to_virt(vaddr)     \
+        ((void *)((unsigned long)(vaddr) | CONFIG_NIOS2_KERNEL_REGION_BASE))
+/* Clear top 3 bits */
+#define virt_to_phys(vaddr)     \
+        ((unsigned long)((unsigned long)(vaddr) & ~0xE0000000))
+#include <asm-generic/io.h>
+#endif /* _ASM_NIOS2_IO_H */
diff --git a/arch/nios2/include/asm/irq.h b/arch/nios2/include/asm/irq.h
new file mode 100644
index 000000000000..8e40fd94a36c
--- /dev/null
+++ b/arch/nios2/include/asm/irq.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#ifndef _ASM_NIOS2_IRQ_H
+#define _ASM_NIOS2_IRQ_H
+#define NIOS2_CPU_NR_IRQS       32
+#include <asm-generic/irq.h>
+#include <linux/irqdomain.h>
+#endif
diff --git a/arch/nios2/include/asm/irqflags.h b/arch/nios2/include/asm/irqflags.h
new file mode 100644
index 000000000000..75ab92e639f8
--- /dev/null
+++ b/arch/nios2/include/asm/irqflags.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#ifndef _ASM_IRQFLAGS_H
+#define _ASM_IRQFLAGS_H
+#include <asm/registers.h>
+static inline unsigned long arch_local_save_flags(void)
+{
+        return RDCTL(CTL_STATUS);
+}
+/*
+ * This will restore ALL status register flags, not only the interrupt
+ * mask flag.
+ */
+static inline void arch_local_irq_restore(unsigned long flags)
+{
+        WRCTL(CTL_STATUS, flags);
+}
+static inline void arch_local_irq_disable(void)
+{
+        unsigned long flags;
+        flags = arch_local_save_flags();
+        arch_local_irq_restore(flags & ~STATUS_PIE);
+}
+static inline void arch_local_irq_enable(void)
+{
+        unsigned long flags;
+        flags = arch_local_save_flags();
+        arch_local_irq_restore(flags | STATUS_PIE);
+}
+static inline int arch_irqs_disabled_flags(unsigned long flags)
+{
+        return (flags & STATUS_PIE) == 0;
+}
+static inline int arch_irqs_disabled(void)
+{
+        return arch_irqs_disabled_flags(arch_local_save_flags());
+}
+static inline unsigned long arch_local_irq_save(void)
+{
+        unsigned long flags;
+        flags = arch_local_save_flags();
+        arch_local_irq_restore(flags & ~STATUS_PIE);
+        return flags;
+}
+#endif /* _ASM_IRQFLAGS_H */
diff --git a/arch/nios2/include/asm/linkage.h b/arch/nios2/include/asm/linkage.h
new file mode 100644
index 000000000000..e0c6decd7d58
--- /dev/null
+++ b/arch/nios2/include/asm/linkage.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2009 Thomas Chou <thomas@wytron.com.tw>
+ *
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ */
+#ifndef _ASM_NIOS2_LINKAGE_H
+#define _ASM_NIOS2_LINKAGE_H
+/* This file is required by include/linux/linkage.h */
+#define __ALIGN .align 4
+#define __ALIGN_STR ".align 4"
+#endif
diff --git a/arch/nios2/include/asm/mmu.h b/arch/nios2/include/asm/mmu.h
new file mode 100644
index 000000000000..d9c0b1010f26
--- /dev/null
+++ b/arch/nios2/include/asm/mmu.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2004 Microtronix Datacom Ltd.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_NIOS2_MMU_H
+#define _ASM_NIOS2_MMU_H
+/* Default "unsigned long" context */
+typedef unsigned long mm_context_t;
+#endif /* _ASM_NIOS2_MMU_H */
diff --git a/arch/nios2/include/asm/mmu_context.h b/arch/nios2/include/asm/mmu_context.h
new file mode 100644
index 000000000000..294b4b1f81d4
--- /dev/null
+++ b/arch/nios2/include/asm/mmu_context.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ *
+ * based on MIPS asm/mmu_context.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_NIOS2_MMU_CONTEXT_H
+#define _ASM_NIOS2_MMU_CONTEXT_H
+#include <asm-generic/mm_hooks.h>
+extern void mmu_context_init(void);
+extern unsigned long get_pid_from_context(mm_context_t *ctx);
+/*
+ * For the fast tlb miss handlers, we keep a pointer to the current pgd.
+ * processor.
+ */
+extern pgd_t *pgd_current;
+static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
+{
+}
+/*
+ * Initialize the context related info for a new mm_struct instance.
+ *
+ * Set all new contexts to 0, that way the generation will never match
+ * the currently running generation when this context is switched in.
+ */
+static inline int init_new_context(struct task_struct *tsk,
+                                        struct mm_struct *mm)
+{
+        mm->context = 0;
+        return 0;
+}
+/*
+ * Destroy context related info for an mm_struct that is about
+ * to be put to rest.
+ */
+static inline void destroy_context(struct mm_struct *mm)
+{
+}
+void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+                struct task_struct *tsk);
+static inline void deactivate_mm(struct task_struct *tsk,
+                                struct mm_struct *mm)
+{
+}
+/*
+ * After we have set current->mm to a new value, this activates
+ * the context for the new mm so we see the new mappings.
+ */
+void activate_mm(struct mm_struct *prev, struct mm_struct *next);
+#endif /* _ASM_NIOS2_MMU_CONTEXT_H */
diff --git a/arch/nios2/include/asm/mutex.h b/arch/nios2/include/asm/mutex.h
new file mode 100644
index 000000000000..ff6101aa2c71
--- /dev/null
+++ b/arch/nios2/include/asm/mutex.h
@@ -0,0 +1 @@
+#include <asm-generic/mutex-dec.h>
diff --git a/arch/nios2/include/asm/page.h b/arch/nios2/include/asm/page.h
new file mode 100644
index 000000000000..4b32d6fd9d98
--- /dev/null
+++ b/arch/nios2/include/asm/page.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2004 Microtronix Datacom Ltd.
+ *
+ * MMU support based on asm/page.h from mips which is:
+ *
+ * Copyright (C) 1994 - 1999, 2000, 03 Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_NIOS2_PAGE_H
+#define _ASM_NIOS2_PAGE_H
+#include <linux/pfn.h>
+#include <linux/const.h>
+/*
+ * PAGE_SHIFT determines the page size
+ */
+#define PAGE_SHIFT      12
+#define PAGE_SIZE       (_AC(1, UL) << PAGE_SHIFT)
+#define PAGE_MASK       (~(PAGE_SIZE - 1))
+/*
+ * PAGE_OFFSET -- the first address of the first page of memory.
+ */
+#define PAGE_OFFSET     \
+        (CONFIG_NIOS2_MEM_BASE + CONFIG_NIOS2_KERNEL_REGION_BASE)
+#ifndef __ASSEMBLY__
+/*
+ * This gives the physical RAM offset.
+ */
+#define PHYS_OFFSET             CONFIG_NIOS2_MEM_BASE
+/*
+ * It's normally defined only for FLATMEM config but it's
+ * used in our early mem init code for all memory models.
+ * So always define it.
+ */
+#define ARCH_PFN_OFFSET         PFN_UP(PHYS_OFFSET)
+#define clear_page(page)        memset((page), 0, PAGE_SIZE)
+#define copy_page(to, from)     memcpy((to), (from), PAGE_SIZE)
+struct page;
+extern void clear_user_page(void *addr, unsigned long vaddr, struct page *page);
+extern void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
+                                struct page *to);
+/*
+ * These are used to make use of C type-checking.
+ */
+typedef struct page *pgtable_t;
+typedef struct { unsigned long pte; } pte_t;
+typedef struct { unsigned long pgd; } pgd_t;
+typedef struct { unsigned long pgprot; } pgprot_t;
+#define pte_val(x)      ((x).pte)
+#define pgd_val(x)      ((x).pgd)
+#define pgprot_val(x)   ((x).pgprot)
+#define __pte(x)        ((pte_t) { (x) })
+#define __pgd(x)        ((pgd_t) { (x) })
+#define __pgprot(x)     ((pgprot_t) { (x) })
+extern unsigned long memory_start;
+extern unsigned long memory_end;
+extern unsigned long memory_size;
+extern struct page *mem_map;
+#endif /* !__ASSEMBLY__ */
+# define __pa(x)                \
+        ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET)
+# define __va(x)                \
+        ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET))
+#define page_to_virt(page)      \
+        ((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET)
+# define pfn_to_kaddr(pfn)      __va((pfn) << PAGE_SHIFT)
+# define pfn_valid(pfn)         ((pfn) >= ARCH_PFN_OFFSET &&    \
+                                        (pfn) < max_mapnr)
+# define virt_to_page(vaddr)    pfn_to_page(PFN_DOWN(virt_to_phys(vaddr)))
+# define virt_addr_valid(vaddr) pfn_valid(PFN_DOWN(virt_to_phys(vaddr)))
+# define VM_DATA_DEFAULT_FLAGS  (VM_READ | VM_WRITE | \
+                                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+# define UNCAC_ADDR(addr)       \
+        ((void *)((unsigned)(addr) | CONFIG_NIOS2_IO_REGION_BASE))
+# define CAC_ADDR(addr)         \
+        ((void *)(((unsigned)(addr) & ~CONFIG_NIOS2_IO_REGION_BASE) |   \
+                CONFIG_NIOS2_KERNEL_REGION_BASE))
+#include <asm-generic/memory_model.h>
+#include <asm-generic/getorder.h>
+#endif /* _ASM_NIOS2_PAGE_H */
diff --git a/arch/nios2/include/asm/pgalloc.h b/arch/nios2/include/asm/pgalloc.h
new file mode 100644
index 000000000000..6e2985e0a7b9
--- /dev/null
+++ b/arch/nios2/include/asm/pgalloc.h
@@ -0,0 +1,86 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 2001, 2003 by Ralf Baechle
+ * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_NIOS2_PGALLOC_H
+#define _ASM_NIOS2_PGALLOC_H
+#include <linux/mm.h>
+static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
+        pte_t *pte)
+{
+        set_pmd(pmd, __pmd((unsigned long)pte));
+}
+static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
+        pgtable_t pte)
+{
+        set_pmd(pmd, __pmd((unsigned long)page_address(pte)));
+}
+#define pmd_pgtable(pmd) pmd_page(pmd)
+/*
+ * Initialize a new pmd table with invalid pointers.
+ */
+extern void pmd_init(unsigned long page, unsigned long pagetable);
+extern pgd_t *pgd_alloc(struct mm_struct *mm);
+static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
+{
+        free_pages((unsigned long)pgd, PGD_ORDER);
+}
+static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
+        unsigned long address)
+{
+        pte_t *pte;
+        pte = (pte_t *) __get_free_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO,
+                                        PTE_ORDER);
+        return pte;
+}
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
+        unsigned long address)
+{
+        struct page *pte;
+        pte = alloc_pages(GFP_KERNEL | __GFP_REPEAT, PTE_ORDER);
+        if (pte) {
+                if (!pgtable_page_ctor(pte)) {
+                        __free_page(pte);
+                        return NULL;
+                }
+                clear_highpage(pte);
+        }
+        return pte;
+}
+static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
+{
+        free_pages((unsigned long)pte, PTE_ORDER);
+}
+static inline void pte_free(struct mm_struct *mm, struct page *pte)
+{
+        pgtable_page_dtor(pte);
+        __free_pages(pte, PTE_ORDER);
+}
+#define __pte_free_tlb(tlb, pte, addr)                          \
+        do {                                                    \
+                pgtable_page_dtor(pte);                         \
+                tlb_remove_page((tlb), (pte));                  \
+        } while (0)
+#define check_pgt_cache()       do { } while (0)
+#endif /* _ASM_NIOS2_PGALLOC_H */
diff --git a/arch/nios2/include/asm/pgtable-bits.h b/arch/nios2/include/asm/pgtable-bits.h
new file mode 100644
index 000000000000..ce9e7069aa96
--- /dev/null
+++ b/arch/nios2/include/asm/pgtable-bits.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2009 Wind River Systems Inc
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_NIOS2_PGTABLE_BITS_H
+#define _ASM_NIOS2_PGTABLE_BITS_H
+/*
+ * These are actual hardware defined protection bits in the tlbacc register
+ * which looks like this:
+ *
+ * 31 30 ... 26 25 24 23 22 21 20 19 18 ...  1  0
+ * ignored........  C  R  W  X  G PFN............
+ */
+#define _PAGE_GLOBAL    (1<<20)
+#define _PAGE_EXEC      (1<<21)
+#define _PAGE_WRITE     (1<<22)
+#define _PAGE_READ      (1<<23)
+#define _PAGE_CACHED    (1<<24) /* C: data access cacheable */
+/*
+ * Software defined bits. They are ignored by the hardware and always read back
+ * as zero, but can be written as non-zero.
+ */
+#define _PAGE_PRESENT   (1<<25) /* PTE contains a translation */
+#define _PAGE_ACCESSED  (1<<26) /* page referenced */
+#define _PAGE_DIRTY     (1<<27) /* dirty page */
+#define _PAGE_FILE      (1<<28) /* PTE used for file mapping or swap */
+#endif /* _ASM_NIOS2_PGTABLE_BITS_H */
diff --git a/arch/nios2/include/asm/pgtable.h b/arch/nios2/include/asm/pgtable.h
new file mode 100644
index 000000000000..ccbaffd47671
--- /dev/null
+++ b/arch/nios2/include/asm/pgtable.h
@@ -0,0 +1,310 @@
+/*
+ * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2009 Wind River Systems Inc
+ *
+ * Based on asm/pgtable-32.h from mips which is:
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
+ * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_NIOS2_PGTABLE_H
+#define _ASM_NIOS2_PGTABLE_H
+#include <linux/io.h>
+#include <linux/bug.h>
+#include <asm/page.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include <asm/pgtable-bits.h>
+#include <asm-generic/pgtable-nopmd.h>
+#define FIRST_USER_ADDRESS      0
+#define VMALLOC_START           CONFIG_NIOS2_KERNEL_MMU_REGION_BASE
+#define VMALLOC_END             (CONFIG_NIOS2_KERNEL_REGION_BASE - 1)
+struct mm_struct;
+/* Helper macro */
+#define MKP(x, w, r) __pgprot(_PAGE_PRESENT | _PAGE_CACHED |            \
+                                ((x) ? _PAGE_EXEC : 0) |                \
+                                ((r) ? _PAGE_READ : 0) |                \
+                                ((w) ? _PAGE_WRITE : 0))
+/*
+ * These are the macros that generic kernel code needs
+ * (to populate protection_map[])
+ */
+/* Remove W bit on private pages for COW support */
+#define __P000  MKP(0, 0, 0)
+#define __P001  MKP(0, 0, 1)
+#define __P010  MKP(0, 0, 0)    /* COW */
+#define __P011  MKP(0, 0, 1)    /* COW */
+#define __P100  MKP(1, 0, 0)
+#define __P101  MKP(1, 0, 1)
+#define __P110  MKP(1, 0, 0)    /* COW */
+#define __P111  MKP(1, 0, 1)    /* COW */
+/* Shared pages can have exact HW mapping */
+#define __S000  MKP(0, 0, 0)
+#define __S001  MKP(0, 0, 1)
+#define __S010  MKP(0, 1, 0)
+#define __S011  MKP(0, 1, 1)
+#define __S100  MKP(1, 0, 0)
+#define __S101  MKP(1, 0, 1)
+#define __S110  MKP(1, 1, 0)
+#define __S111  MKP(1, 1, 1)
+/* Used all over the kernel */
+#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_CACHED | _PAGE_READ | \
+                             _PAGE_WRITE | _PAGE_EXEC | _PAGE_GLOBAL)
+#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_CACHED | _PAGE_READ | \
+                             _PAGE_WRITE | _PAGE_ACCESSED)
+#define PAGE_COPY MKP(0, 0, 1)
+#define PGD_ORDER       0
+#define PTE_ORDER       0
+#define PTRS_PER_PGD    ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
+#define PTRS_PER_PTE    ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
+#define USER_PTRS_PER_PGD       \
+        (CONFIG_NIOS2_KERNEL_MMU_REGION_BASE / PGDIR_SIZE)
+#define PGDIR_SHIFT     22
+#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK      (~(PGDIR_SIZE-1))
+/*
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
+#define ZERO_PAGE(vaddr)        (virt_to_page(empty_zero_page))
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
+/*
+ * (pmds are folded into puds so this doesn't get actually called,
+ * but the define is needed for a generic inline function.)
+ */
+static inline void set_pmd(pmd_t *pmdptr, pmd_t pmdval)
+{
+        pmdptr->pud.pgd.pgd = pmdval.pud.pgd.pgd;
+}
+/* to find an entry in a page-table-directory */
+#define pgd_index(addr)         (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
+#define pgd_offset(mm, addr)    ((mm)->pgd + pgd_index(addr))
+static inline int pte_write(pte_t pte)          \
+        { return pte_val(pte) & _PAGE_WRITE; }
+static inline int pte_dirty(pte_t pte)          \
+        { return pte_val(pte) & _PAGE_DIRTY; }
+static inline int pte_young(pte_t pte)          \
+        { return pte_val(pte) & _PAGE_ACCESSED; }
+static inline int pte_file(pte_t pte)           \
+        { return pte_val(pte) & _PAGE_FILE; }
+static inline int pte_special(pte_t pte)        { return 0; }
+#define pgprot_noncached pgprot_noncached
+static inline pgprot_t pgprot_noncached(pgprot_t _prot)
+{
+        unsigned long prot = pgprot_val(_prot);
+        prot &= ~_PAGE_CACHED;
+        return __pgprot(prot);
+}
+static inline int pte_none(pte_t pte)
+{
+        return !(pte_val(pte) & ~(_PAGE_GLOBAL|0xf));
+}
+static inline int pte_present(pte_t pte)        \
+        { return pte_val(pte) & _PAGE_PRESENT; }
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not..
+ */
+static inline pte_t pte_wrprotect(pte_t pte)
+{
+        pte_val(pte) &= ~_PAGE_WRITE;
+        return pte;
+}
+static inline pte_t pte_mkclean(pte_t pte)
+{
+        pte_val(pte) &= ~_PAGE_DIRTY;
+        return pte;
+}
+static inline pte_t pte_mkold(pte_t pte)
+{
+        pte_val(pte) &= ~_PAGE_ACCESSED;
+        return pte;
+}
+static inline pte_t pte_mkwrite(pte_t pte)
+{
+        pte_val(pte) |= _PAGE_WRITE;
+        return pte;
+}
+static inline pte_t pte_mkdirty(pte_t pte)
+{
+        pte_val(pte) |= _PAGE_DIRTY;
+        return pte;
+}
+static inline pte_t pte_mkspecial(pte_t pte)    { return pte; }
+static inline pte_t pte_mkyoung(pte_t pte)
+{
+        pte_val(pte) |= _PAGE_ACCESSED;
+        return pte;
+}
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+        const unsigned long mask = _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC;
+        pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
+        return pte;
+}
+static inline int pmd_present(pmd_t pmd)
+{
+        return (pmd_val(pmd) != (unsigned long) invalid_pte_table)
+                        && (pmd_val(pmd) != 0UL);
+}
+static inline void pmd_clear(pmd_t *pmdp)
+{
+        pmd_val(*pmdp) = (unsigned long) invalid_pte_table;
+}
+#define pte_pfn(pte)            (pte_val(pte) & 0xfffff)
+#define pfn_pte(pfn, prot)      (__pte(pfn | pgprot_val(prot)))
+#define pte_page(pte)           (pfn_to_page(pte_pfn(pte)))
+/*
+ * Store a linux PTE into the linux page table.
+ */
+static inline void set_pte(pte_t *ptep, pte_t pteval)
+{
+        *ptep = pteval;
+}
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+                              pte_t *ptep, pte_t pteval)
+{
+        unsigned long paddr = page_to_virt(pte_page(pteval));
+        flush_dcache_range(paddr, paddr + PAGE_SIZE);
+        set_pte(ptep, pteval);
+}
+static inline int pmd_none(pmd_t pmd)
+{
+        return (pmd_val(pmd) ==
+                (unsigned long) invalid_pte_table) || (pmd_val(pmd) == 0UL);
+}
+#define pmd_bad(pmd)    (pmd_val(pmd) & ~PAGE_MASK)
+static inline void pte_clear(struct mm_struct *mm,
+                                unsigned long addr, pte_t *ptep)
+{
+        pte_t null;
+        pte_val(null) = (addr >> PAGE_SHIFT) & 0xf;
+        set_pte_at(mm, addr, ptep, null);
+        flush_tlb_one(addr);
+}
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+#define mk_pte(page, prot)      (pfn_pte(page_to_pfn(page), prot))
+#define pte_unmap(pte)  do { } while (0)
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+#define pmd_phys(pmd)           virt_to_phys((void *)pmd_val(pmd))
+#define pmd_page(pmd)           (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
+#define pmd_page_vaddr(pmd)     pmd_val(pmd)
+#define pte_offset_map(dir, addr)                       \
+        ((pte_t *) page_address(pmd_page(*dir)) +       \
+         (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
+/* to find an entry in a kernel page-table-directory */
+#define pgd_offset_k(addr)      pgd_offset(&init_mm, addr)
+/* Get the address to the PTE for a vaddr in specific directory */
+#define pte_offset_kernel(dir, addr)                    \
+        ((pte_t *) pmd_page_vaddr(*(dir)) +             \
+         (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
+#define pte_ERROR(e) \
+        pr_err("%s:%d: bad pte %08lx.\n", \
+                __FILE__, __LINE__, pte_val(e))
+#define pgd_ERROR(e) \
+        pr_err("%s:%d: bad pgd %08lx.\n", \
+                __FILE__, __LINE__, pgd_val(e))
+/*
+ * Encode and decode a swap entry (must be !pte_none(pte) && !pte_present(pte)
+ * && !pte_file(pte)):
+ *
+ * 31 30 29 28 27 26 25 24 23 22 21 20 19 18 ...  1  0
+ *  0  0  0  0 type.  0  0  0  0  0  0 offset.........
+ *
+ * This gives us up to 2**2 = 4 swap files and 2**20 * 4K = 4G per swap file.
+ *
+ * Note that the offset field is always non-zero, thus !pte_none(pte) is always
+ * true.
+ */
+#define __swp_type(swp)         (((swp).val >> 26) & 0x3)
+#define __swp_offset(swp)       ((swp).val & 0xfffff)
+#define __swp_entry(type, off)  ((swp_entry_t) { (((type) & 0x3) << 26) \
+                                                 | ((off) & 0xfffff) })
+#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
+/* Encode and decode a nonlinear file mapping entry */
+#define PTE_FILE_MAX_BITS       25
+#define pte_to_pgoff(pte)       (pte_val(pte) & 0x1ffffff)
+#define pgoff_to_pte(off)       __pte(((off) & 0x1ffffff) | _PAGE_FILE)
+#define kern_addr_valid(addr)           (1)
+#include <asm-generic/pgtable.h>
+#define pgtable_cache_init()            do { } while (0)
+extern void __init paging_init(void);
+extern void __init mmu_init(void);
+extern void update_mmu_cache(struct vm_area_struct *vma,
+                             unsigned long address, pte_t *pte);
+#endif /* _ASM_NIOS2_PGTABLE_H */
diff --git a/arch/nios2/include/asm/processor.h b/arch/nios2/include/asm/processor.h
new file mode 100644
index 000000000000..3bd349473b06
--- /dev/null
+++ b/arch/nios2/include/asm/processor.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2004 Microtronix Datacom Ltd
+ * Copyright (C) 2001 Ken Hill (khill@microtronix.com)
+ *                    Vic Phillips (vic@microtronix.com)
+ *
+ * based on SPARC asm/processor_32.h which is:
+ *
+ * Copyright (C) 1994 David S. Miller
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_NIOS2_PROCESSOR_H
+#define _ASM_NIOS2_PROCESSOR_H
+#include <asm/ptrace.h>
+#include <asm/registers.h>
+#include <asm/page.h>
+#define NIOS2_FLAG_KTHREAD      0x00000001      /* task is a kernel thread */
+#define NIOS2_OP_NOP            0x1883a
+#define NIOS2_OP_BREAK          0x3da03a
+#ifdef __KERNEL__
+#define STACK_TOP       TASK_SIZE
+#define STACK_TOP_MAX   STACK_TOP
+#endif /* __KERNEL__ */
+/* Kuser helpers is mapped to this user space address */
+#define KUSER_BASE              0x1000
+#define KUSER_SIZE              (PAGE_SIZE)
+#ifndef __ASSEMBLY__
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l; })
+# define TASK_SIZE              0x7FFF0000UL
+# define TASK_UNMAPPED_BASE     (PAGE_ALIGN(TASK_SIZE / 3))
+/* The Nios processor specific thread struct. */
+struct thread_struct {
+        struct pt_regs *kregs;
+        /* Context switch saved kernel state. */
+        unsigned long ksp;
+        unsigned long kpsr;
+};
+#define INIT_MMAP \
+        { &init_mm, (0), (0), __pgprot(0x0), VM_READ | VM_WRITE | VM_EXEC }
+# define INIT_THREAD {                  \
+        .kregs  = NULL,                 \
+        .ksp    = 0,                    \
+        .kpsr   = 0,                    \
+}
+extern void start_thread(struct pt_regs *regs, unsigned long pc,
+                        unsigned long sp);
+struct task_struct;
+/* Free all resources held by a thread. */
+static inline void release_thread(struct task_struct *dead_task)
+{
+}
+/* Free current thread data structures etc.. */
+static inline void exit_thread(void)
+{
+}
+/* Return saved PC of a blocked thread. */
+#define thread_saved_pc(tsk)    ((tsk)->thread.kregs->ea)
+extern unsigned long get_wchan(struct task_struct *p);
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk)    do { } while (0)
+#define task_pt_regs(p) \
+        ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
+/* Used by procfs */
+#define KSTK_EIP(tsk)   ((tsk)->thread.kregs->ea)
+#define KSTK_ESP(tsk)   ((tsk)->thread.kregs->sp)
+#define cpu_relax()     barrier()
+#define cpu_relax_lowlatency()  cpu_relax()
+#endif /* __ASSEMBLY__ */
+#endif /* _ASM_NIOS2_PROCESSOR_H */
diff --git a/arch/nios2/include/asm/ptrace.h b/arch/nios2/include/asm/ptrace.h
new file mode 100644
index 000000000000..20fb1cf2dab6
--- /dev/null
+++ b/arch/nios2/include/asm/ptrace.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2004 Microtronix Datacom Ltd
+ *
+ * based on m68k asm/processor.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_NIOS2_PTRACE_H
+#define _ASM_NIOS2_PTRACE_H
+#include <uapi/asm/ptrace.h>
+#ifndef __ASSEMBLY__
+#define user_mode(regs) (((regs)->estatus & ESTATUS_EU))
+#define instruction_pointer(regs)       ((regs)->ra)
+#define profile_pc(regs)                instruction_pointer(regs)
+#define user_stack_pointer(regs)        ((regs)->sp)
+extern void show_regs(struct pt_regs *);
+#define current_pt_regs() \
+        ((struct pt_regs *)((unsigned long)current_thread_info() + THREAD_SIZE)\
+                - 1)
+int do_syscall_trace_enter(void);
+void do_syscall_trace_exit(void);
+#endif /* __ASSEMBLY__ */
+#endif /* _ASM_NIOS2_PTRACE_H */
diff --git a/arch/nios2/include/asm/registers.h b/arch/nios2/include/asm/registers.h
new file mode 100644
index 000000000000..615bce19b546
--- /dev/null
+++ b/arch/nios2/include/asm/registers.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#ifndef _ASM_NIOS2_REGISTERS_H
+#define _ASM_NIOS2_REGISTERS_H
+#ifndef __ASSEMBLY__
+#include <asm/cpuinfo.h>
+#endif
+/* control register numbers */
+#define CTL_STATUS      0
+#define CTL_ESTATUS     1
+#define CTL_BSTATUS     2
+#define CTL_IENABLE     3
+#define CTL_IPENDING    4
+#define CTL_CPUID       5
+#define CTL_RSV1        6
+#define CTL_EXCEPTION   7
+#define CTL_PTEADDR     8
+#define CTL_TLBACC      9
+#define CTL_TLBMISC     10
+#define CTL_RSV2        11
+#define CTL_BADADDR     12
+#define CTL_CONFIG      13
+#define CTL_MPUBASE     14
+#define CTL_MPUACC      15
+/* access control registers using GCC builtins */
+#define RDCTL(r)        __builtin_rdctl(r)
+#define WRCTL(r, v)     __builtin_wrctl(r, v)
+/* status register bits */
+#define STATUS_PIE      (1 << 0)        /* processor interrupt enable */
+#define STATUS_U        (1 << 1)        /* user mode */
+#define STATUS_EH       (1 << 2)        /* Exception mode */
+/* estatus register bits */
+#define ESTATUS_EPIE    (1 << 0)        /* processor interrupt enable */
+#define ESTATUS_EU      (1 << 1)        /* user mode */
+#define ESTATUS_EH      (1 << 2)        /* Exception mode */
+/* tlbmisc register bits */
+#define TLBMISC_PID_SHIFT       4
+#ifndef __ASSEMBLY__
+#define TLBMISC_PID_MASK        ((1UL << cpuinfo.tlb_pid_num_bits) - 1)
+#endif
+#define TLBMISC_WAY_MASK        0xf
+#define TLBMISC_WAY_SHIFT       20
+#define TLBMISC_PID     (TLBMISC_PID_MASK << TLBMISC_PID_SHIFT) /* TLB PID */
+#define TLBMISC_WE      (1 << 18)       /* TLB write enable */
+#define TLBMISC_RD      (1 << 19)       /* TLB read */
+#define TLBMISC_WAY     (TLBMISC_WAY_MASK << TLBMISC_WAY_SHIFT) /* TLB way */
+#endif /* _ASM_NIOS2_REGISTERS_H */
diff --git a/arch/nios2/include/asm/setup.h b/arch/nios2/include/asm/setup.h
new file mode 100644
index 000000000000..dcbf8cf1a344
--- /dev/null
+++ b/arch/nios2/include/asm/setup.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#ifndef _ASM_NIOS2_SETUP_H
+#define _ASM_NIOS2_SETUP_H
+#include <asm-generic/setup.h>
+#ifndef __ASSEMBLY__
+#ifdef __KERNEL__
+extern char exception_handler_hook[];
+extern char fast_handler[];
+extern char fast_handler_end[];
+extern void pagetable_init(void);
+extern void setup_early_printk(void);
+#endif/* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+#endif /* _ASM_NIOS2_SETUP_H */
diff --git a/arch/nios2/include/asm/signal.h b/arch/nios2/include/asm/signal.h
new file mode 100644
index 000000000000..bbcf11eecb01
--- /dev/null
+++ b/arch/nios2/include/asm/signal.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright Altera Corporation (C) 2013. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#ifndef _NIOS2_SIGNAL_H
+#define _NIOS2_SIGNAL_H
+#include <uapi/asm/signal.h>
+#endif  /* _NIOS2_SIGNAL_H */
diff --git a/arch/nios2/include/asm/string.h b/arch/nios2/include/asm/string.h
new file mode 100644
index 000000000000..14dd570d64f7
--- /dev/null
+++ b/arch/nios2/include/asm/string.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2004 Microtronix Datacom Ltd
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_NIOS2_STRING_H
+#define _ASM_NIOS2_STRING_H
+#ifdef __KERNEL__
+#define __HAVE_ARCH_MEMSET
+#define __HAVE_ARCH_MEMCPY
+#define __HAVE_ARCH_MEMMOVE
+extern void *memset(void *s, int c, size_t count);
+extern void *memcpy(void *d, const void *s, size_t count);
+extern void *memmove(void *d, const void *s, size_t count);
+#endif /* __KERNEL__ */
+#endif /* _ASM_NIOS2_STRING_H */
diff --git a/arch/nios2/include/asm/switch_to.h b/arch/nios2/include/asm/switch_to.h
new file mode 100644
index 000000000000..c47b3f4afbcd
--- /dev/null
+++ b/arch/nios2/include/asm/switch_to.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2004 Microtronix Datacom Ltd.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_NIOS2_SWITCH_TO_H
+#define _ASM_NIOS2_SWITCH_TO_H
+/*
+ * switch_to(n) should switch tasks to task ptr, first checking that
+ * ptr isn't the current task, in which case it does nothing.  This
+ * also clears the TS-flag if the task we switched to has used the
+ * math co-processor latest.
+ */
+#define switch_to(prev, next, last)                     \
+{                                                       \
+        void *_last;                                    \
+        __asm__ __volatile__ (                          \
+                "mov    r4, %1\n"                       \
+                "mov    r5, %2\n"                       \
+                "call   resume\n"                       \
+                "mov    %0,r4\n"                        \
+                : "=r" (_last)                          \
+                : "r" (prev), "r" (next)                \
+                : "r4", "r5", "r7", "r8", "ra");        \
+        (last) = _last;                                 \
+}
+#endif /* _ASM_NIOS2_SWITCH_TO_H */
diff --git a/arch/nios2/include/asm/syscall.h b/arch/nios2/include/asm/syscall.h
new file mode 100644
index 000000000000..9de220854c4a
--- /dev/null
+++ b/arch/nios2/include/asm/syscall.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright Altera Corporation (C) <2014>. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_NIOS2_SYSCALL_H__
+#define __ASM_NIOS2_SYSCALL_H__
+#include <linux/err.h>
+#include <linux/sched.h>
+static inline int syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
+{
+        return regs->r2;
+}
+static inline void syscall_rollback(struct task_struct *task,
+                                struct pt_regs *regs)
+{
+        regs->r2 = regs->orig_r2;
+        regs->r7 = regs->orig_r7;
+}
+static inline long syscall_get_error(struct task_struct *task,
+                                struct pt_regs *regs)
+{
+        return regs->r7 ? regs->r2 : 0;
+}
+static inline long syscall_get_return_value(struct task_struct *task,
+        struct pt_regs *regs)
+{
+        return regs->r2;
+}
+static inline void syscall_set_return_value(struct task_struct *task,
+        struct pt_regs *regs, int error, long val)
+{
+        if (error) {
+                /* error < 0, but nios2 uses > 0 return value */
+                regs->r2 = -error;
+                regs->r7 = 1;
+        } else {
+                regs->r2 = val;
+                regs->r7 = 0;
+        }
+}
+static inline void syscall_get_arguments(struct task_struct *task,
+        struct pt_regs *regs, unsigned int i, unsigned int n,
+        unsigned long *args)
+{
+        BUG_ON(i + n > 6);
+        switch (i) {
+        case 0:
+                if (!n--)
+                        break;
+                *args++ = regs->r4;
+        case 1:
+                if (!n--)
+                        break;
+                *args++ = regs->r5;
+        case 2:
+                if (!n--)
+                        break;
+                *args++ = regs->r6;
+        case 3:
+                if (!n--)
+                        break;
+                *args++ = regs->r7;
+        case 4:
+                if (!n--)
+                        break;
+                *args++ = regs->r8;
+        case 5:
+                if (!n--)
+                        break;
+                *args++ = regs->r9;
+        case 6:
+                if (!n--)
+                        break;
+        default:
+                BUG();
+        }
+}
+static inline void syscall_set_arguments(struct task_struct *task,
+        struct pt_regs *regs, unsigned int i, unsigned int n,
+        const unsigned long *args)
+{
+        BUG_ON(i + n > 6);
+        switch (i) {
+        case 0:
+                if (!n--)
+                        break;
+                regs->r4 = *args++;
+        case 1:
+                if (!n--)
+                        break;
+                regs->r5 = *args++;
+        case 2:
+                if (!n--)
+                        break;
+                regs->r6 = *args++;
+        case 3:
+                if (!n--)
+                        break;
+                regs->r7 = *args++;
+        case 4:
+                if (!n--)
+                        break;
+                regs->r8 = *args++;
+        case 5:
+                if (!n--)
+                        break;
+                regs->r9 = *args++;
+        case 6:
+                if (!n)
+                        break;
+        default:
+                BUG();
+        }
+}
+#endif
diff --git a/arch/nios2/include/asm/syscalls.h b/arch/nios2/include/asm/syscalls.h
new file mode 100644
index 000000000000..0245d780351b
--- /dev/null
+++ b/arch/nios2/include/asm/syscalls.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright Altera Corporation (C) 2013. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#ifndef __ASM_NIOS2_SYSCALLS_H
+#define __ASM_NIOS2_SYSCALLS_H
+int sys_cacheflush(unsigned long addr, unsigned long len,
+                                unsigned int op);
+#include <asm-generic/syscalls.h>
+#endif /* __ASM_NIOS2_SYSCALLS_H */
diff --git a/arch/nios2/include/asm/thread_info.h b/arch/nios2/include/asm/thread_info.h
new file mode 100644
index 000000000000..1f266575beb5
--- /dev/null
+++ b/arch/nios2/include/asm/thread_info.h
@@ -0,0 +1,120 @@
+/*
+ * NiosII low-level thread information
+ *
+ * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2004 Microtronix Datacom Ltd.
+ *
+ * Based on asm/thread_info_no.h from m68k which is:
+ *
+ * Copyright (C) 2002 David Howells <dhowells@redhat.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_NIOS2_THREAD_INFO_H
+#define _ASM_NIOS2_THREAD_INFO_H
+#ifdef __KERNEL__
+/*
+ * Size of the kernel stack for each process.
+ */
+#define THREAD_SIZE_ORDER       1
+#define THREAD_SIZE             8192 /* 2 * PAGE_SIZE */
+#ifndef __ASSEMBLY__
+typedef struct {
+        unsigned long seg;
+} mm_segment_t;
+/*
+ * low level task data that entry.S needs immediate access to
+ * - this struct should fit entirely inside of one cache line
+ * - this struct shares the supervisor stack pages
+ * - if the contents of this structure are changed, the assembly constants
+ *   must also be changed
+ */
+struct thread_info {
+        struct task_struct      *task;          /* main task structure */
+        struct exec_domain      *exec_domain;   /* execution domain */
+        unsigned long           flags;          /* low level flags */
+        __u32                   cpu;            /* current CPU */
+        int                     preempt_count;  /* 0 => preemptable,<0 => BUG */
+        mm_segment_t            addr_limit;     /* thread address space:
+                                                  0-0x7FFFFFFF for user-thead
+                                                  0-0xFFFFFFFF for kernel-thread
+                                                */
+        struct restart_block    restart_block;
+        struct pt_regs          *regs;
+};
+/*
+ * macros/functions for gaining access to the thread information structure
+ *
+ * preempt_count needs to be 1 initially, until the scheduler is functional.
+ */
+#define INIT_THREAD_INFO(tsk)                   \
+{                                               \
+        .task           = &tsk,                 \
+        .exec_domain    = &default_exec_domain, \
+        .flags          = 0,                    \
+        .cpu            = 0,                    \
+        .preempt_count  = INIT_PREEMPT_COUNT,   \
+        .addr_limit     = KERNEL_DS,            \
+        .restart_block  = {                     \
+                .fn = do_no_restart_syscall,    \
+        },                                      \
+}
+#define init_thread_info        (init_thread_union.thread_info)
+#define init_stack              (init_thread_union.stack)
+/* how to get the thread information struct from C */
+static inline struct thread_info *current_thread_info(void)
+{
+        register unsigned long sp asm("sp");
+        return (struct thread_info *)(sp & ~(THREAD_SIZE - 1));
+}
+#endif /* !__ASSEMBLY__ */
+/*
+ * thread information flags
+ * - these are process state flags that various assembly files may need to
+ *   access
+ * - pending work-to-be-done flags are in LSW
+ * - other flags in MSW
+ */
+#define TIF_SYSCALL_TRACE       0       /* syscall trace active */
+#define TIF_NOTIFY_RESUME       1       /* resumption notification requested */
+#define TIF_SIGPENDING          2       /* signal pending */
+#define TIF_NEED_RESCHED        3       /* rescheduling necessary */
+#define TIF_MEMDIE              4       /* is terminating due to OOM killer */
+#define TIF_SECCOMP             5       /* secure computing */
+#define TIF_SYSCALL_AUDIT       6       /* syscall auditing active */
+#define TIF_RESTORE_SIGMASK     9       /* restore signal mask in do_signal() */
+#define TIF_POLLING_NRFLAG      16      /* true if poll_idle() is polling
+                                           TIF_NEED_RESCHED */
+#define _TIF_SYSCALL_TRACE      (1 << TIF_SYSCALL_TRACE)
+#define _TIF_NOTIFY_RESUME      (1 << TIF_NOTIFY_RESUME)
+#define _TIF_SIGPENDING         (1 << TIF_SIGPENDING)
+#define _TIF_NEED_RESCHED       (1 << TIF_NEED_RESCHED)
+#define _TIF_SECCOMP            (1 << TIF_SECCOMP)
+#define _TIF_SYSCALL_AUDIT      (1 << TIF_SYSCALL_AUDIT)
+#define _TIF_RESTORE_SIGMASK    (1 << TIF_RESTORE_SIGMASK)
+#define _TIF_POLLING_NRFLAG     (1 << TIF_POLLING_NRFLAG)
+/* work to do on interrupt/exception return */
+#define _TIF_WORK_MASK          0x0000FFFE
+/* work to do on any return to u-space */
+# define _TIF_ALLWORK_MASK      0x0000FFFF
+#endif /* __KERNEL__ */
+#endif /* _ASM_NIOS2_THREAD_INFO_H */
diff --git a/arch/nios2/include/asm/timex.h b/arch/nios2/include/asm/timex.h
new file mode 100644
index 000000000000..2f2abb28ec2f
--- /dev/null
+++ b/arch/nios2/include/asm/timex.h
@@ -0,0 +1,24 @@
+/* Copyright Altera Corporation (C) 2014. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2,
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#ifndef _ASM_NIOS2_TIMEX_H
+#define _ASM_NIOS2_TIMEX_H
+typedef unsigned long cycles_t;
+extern cycles_t get_cycles(void);
+#endif
diff --git a/arch/nios2/include/asm/tlb.h b/arch/nios2/include/asm/tlb.h
new file mode 100644
index 000000000000..d3bc648e08b5
--- /dev/null
+++ b/arch/nios2/include/asm/tlb.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2009 Wind River Systems Inc
+ * Copyright (C) 2004 Microtronix Datacom Ltd.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_NIOS2_TLB_H
+#define _ASM_NIOS2_TLB_H
+#define tlb_flush(tlb)  flush_tlb_mm((tlb)->mm)
+extern void set_mmu_pid(unsigned long pid);
+/*
+ * NiosII doesn't need any special per-pte or per-vma handling, except
+ * we need to flush cache for the area to be unmapped.
+ */
+#define tlb_start_vma(tlb, vma)                                 \
+        do {                                                    \
+                if (!tlb->fullmm)                               \
+                        flush_cache_range(vma, vma->vm_start, vma->vm_end); \
+        }  while (0)
+#define tlb_end_vma(tlb, vma)   do { } while (0)
+#define __tlb_remove_tlb_entry(tlb, ptep, address)      do { } while (0)
+#include <linux/pagemap.h>
+#include <asm-generic/tlb.h>
+#endif /* _ASM_NIOS2_TLB_H */
diff --git a/arch/nios2/include/asm/tlbflush.h b/arch/nios2/include/asm/tlbflush.h
new file mode 100644
index 000000000000..e19652fca1c6
--- /dev/null
+++ b/arch/nios2/include/asm/tlbflush.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#ifndef _ASM_NIOS2_TLBFLUSH_H
+#define _ASM_NIOS2_TLBFLUSH_H
+struct mm_struct;
+/*
+ * TLB flushing:
+ *
+ *  - flush_tlb_all() flushes all processes TLB entries
+ *  - flush_tlb_mm(mm) flushes the specified mm context TLB entries
+ *  - flush_tlb_page(vma, vmaddr) flushes one page
+ *  - flush_tlb_range(vma, start, end) flushes a range of pages
+ *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
+ */
+extern void flush_tlb_all(void);
+extern void flush_tlb_mm(struct mm_struct *mm);
+extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
+                            unsigned long end);
+extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
+extern void flush_tlb_one(unsigned long vaddr);
+static inline void flush_tlb_page(struct vm_area_struct *vma,
+                                unsigned long addr)
+{
+        flush_tlb_one(addr);
+}
+#endif /* _ASM_NIOS2_TLBFLUSH_H */
diff --git a/arch/nios2/include/asm/traps.h b/arch/nios2/include/asm/traps.h
new file mode 100644
index 000000000000..82a48473280d
--- /dev/null
+++ b/arch/nios2/include/asm/traps.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2004 Microtronix Datacom Ltd.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_NIOS2_TRAPS_H
+#define _ASM_NIOS2_TRAPS_H
+#define TRAP_ID_SYSCALL         0
+#ifndef __ASSEMBLY__
+void _exception(int signo, struct pt_regs *regs, int code, unsigned long addr);
+#endif
+#endif /* _ASM_NIOS2_TRAPS_H */
diff --git a/arch/nios2/include/asm/uaccess.h b/arch/nios2/include/asm/uaccess.h
new file mode 100644
index 000000000000..acedc0a2860e
--- /dev/null
+++ b/arch/nios2/include/asm/uaccess.h
@@ -0,0 +1,231 @@
+/*
+ * User space memory access functions for Nios II
+ *
+ * Copyright (C) 2010-2011, Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2009, Wind River Systems Inc
+ *   Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_NIOS2_UACCESS_H
+#define _ASM_NIOS2_UACCESS_H
+#include <linux/errno.h>
+#include <linux/thread_info.h>
+#include <linux/string.h>
+#include <asm/page.h>
+#define VERIFY_READ     0
+#define VERIFY_WRITE    1
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue.  No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path.  This means when everything is well,
+ * we don't even have to jump over them.  Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+struct exception_table_entry {
+        unsigned long insn;
+        unsigned long fixup;
+};
+extern int fixup_exception(struct pt_regs *regs);
+/*
+ * Segment stuff
+ */
+#define MAKE_MM_SEG(s)          ((mm_segment_t) { (s) })
+#define USER_DS                 MAKE_MM_SEG(0x80000000UL)
+#define KERNEL_DS               MAKE_MM_SEG(0)
+#define get_ds()                (KERNEL_DS)
+#define get_fs()                (current_thread_info()->addr_limit)
+#define set_fs(seg)             (current_thread_info()->addr_limit = (seg))
+#define segment_eq(a, b)        ((a).seg == (b).seg)
+#define __access_ok(addr, len)                  \
+        (((signed long)(((long)get_fs().seg) &  \
+                ((long)(addr) | (((long)(addr)) + (len)) | (len)))) == 0)
+#define access_ok(type, addr, len)              \
+        likely(__access_ok((unsigned long)(addr), (unsigned long)(len)))
+# define __EX_TABLE_SECTION     ".section __ex_table,\"a\"\n"
+/*
+ * Zero Userspace
+ */
+static inline unsigned long __must_check __clear_user(void __user *to,
+                                                      unsigned long n)
+{
+        __asm__ __volatile__ (
+                "1:     stb     zero, 0(%1)\n"
+                "       addi    %0, %0, -1\n"
+                "       addi    %1, %1, 1\n"
+                "       bne     %0, zero, 1b\n"
+                "2:\n"
+                __EX_TABLE_SECTION
+                ".word  1b, 2b\n"
+                ".previous\n"
+                : "=r" (n), "=r" (to)
+                : "0" (n), "1" (to)
+        );
+        return n;
+}
+static inline unsigned long __must_check clear_user(void __user *to,
+                                                    unsigned long n)
+{
+        if (!access_ok(VERIFY_WRITE, to, n))
+                return n;
+        return __clear_user(to, n);
+}
+extern long __copy_from_user(void *to, const void __user *from,
+                                unsigned long n);
+extern long __copy_to_user(void __user *to, const void *from, unsigned long n);
+static inline long copy_from_user(void *to, const void __user *from,
+                                unsigned long n)
+{
+        if (!access_ok(VERIFY_READ, from, n))
+                return n;
+        return __copy_from_user(to, from, n);
+}
+static inline long copy_to_user(void __user *to, const void *from,
+                                unsigned long n)
+{
+        if (!access_ok(VERIFY_WRITE, to, n))
+                return n;
+        return __copy_to_user(to, from, n);
+}
+extern long strncpy_from_user(char *__to, const char __user *__from,
+                                long __len);
+extern long strnlen_user(const char __user *s, long n);
+#define __copy_from_user_inatomic       __copy_from_user
+#define __copy_to_user_inatomic         __copy_to_user
+/* Optimized macros */
+#define __get_user_asm(val, insn, addr, err)                            \
+{                                                                       \
+        __asm__ __volatile__(                                           \
+        "       movi    %0, %3\n"                                       \
+        "1:   " insn " %1, 0(%2)\n"                                     \
+        "       movi     %0, 0\n"                                       \
+        "2:\n"                                                          \
+        "       .section __ex_table,\"a\"\n"                            \
+        "       .word 1b, 2b\n"                                         \
+        "       .previous"                                              \
+        : "=&r" (err), "=r" (val)                                       \
+        : "r" (addr), "i" (-EFAULT));                                   \
+}
+#define __get_user_unknown(val, size, ptr, err) do {                    \
+        err = 0;                                                        \
+        if (copy_from_user(&(val), ptr, size)) {                        \
+                err = -EFAULT;                                          \
+        }                                                               \
+        } while (0)
+#define __get_user_common(val, size, ptr, err)                          \
+do {                                                                    \
+        switch (size) {                                                 \
+        case 1:                                                         \
+                __get_user_asm(val, "ldbu", ptr, err);                  \
+                break;                                                  \
+        case 2:                                                         \
+                __get_user_asm(val, "ldhu", ptr, err);                  \
+                break;                                                  \
+        case 4:                                                         \
+                __get_user_asm(val, "ldw", ptr, err);                   \
+                break;                                                  \
+        default:                                                        \
+                __get_user_unknown(val, size, ptr, err);                \
+                break;                                                  \
+        }                                                               \
+} while (0)
+#define __get_user(x, ptr)                                              \
+        ({                                                              \
+        long __gu_err = -EFAULT;                                        \
+        const __typeof__(*(ptr)) __user *__gu_ptr = (ptr);              \
+        unsigned long __gu_val;                                         \
+        __get_user_common(__gu_val, sizeof(*(ptr)), __gu_ptr, __gu_err);\
+        (x) = (__typeof__(x))__gu_val;                                  \
+        __gu_err;                                                       \
+        })
+#define get_user(x, ptr)                                                \
+({                                                                      \
+        long __gu_err = -EFAULT;                                        \
+        const __typeof__(*(ptr)) __user *__gu_ptr = (ptr);              \
+        unsigned long __gu_val = 0;                                     \
+        if (access_ok(VERIFY_READ,  __gu_ptr, sizeof(*__gu_ptr)))       \
+                __get_user_common(__gu_val, sizeof(*__gu_ptr),          \
+                        __gu_ptr, __gu_err);                            \
+        (x) = (__typeof__(x))__gu_val;                                  \
+        __gu_err;                                                       \
+})
+#define __put_user_asm(val, insn, ptr, err)                             \
+{                                                                       \
+        __asm__ __volatile__(                                           \
+        "       movi    %0, %3\n"                                       \
+        "1:   " insn " %1, 0(%2)\n"                                     \
+        "       movi     %0, 0\n"                                       \
+        "2:\n"                                                          \
+        "       .section __ex_table,\"a\"\n"                            \
+        "       .word 1b, 2b\n"                                         \
+        "       .previous\n"                                            \
+        : "=&r" (err)                                                   \
+        : "r" (val), "r" (ptr), "i" (-EFAULT));                         \
+}
+#define put_user(x, ptr)                                                \
+({                                                                      \
+        long __pu_err = -EFAULT;                                        \
+        __typeof__(*(ptr)) __user *__pu_ptr = (ptr);                    \
+        __typeof__(*(ptr)) __pu_val = (__typeof(*ptr))(x);              \
+        if (access_ok(VERIFY_WRITE, __pu_ptr, sizeof(*__pu_ptr))) {     \
+                switch (sizeof(*__pu_ptr)) {                            \
+                case 1:                                                 \
+                        __put_user_asm(__pu_val, "stb", __pu_ptr, __pu_err); \
+                        break;                                          \
+                case 2:                                                 \
+                        __put_user_asm(__pu_val, "sth", __pu_ptr, __pu_err); \
+                        break;                                          \
+                case 4:                                                 \
+                        __put_user_asm(__pu_val, "stw", __pu_ptr, __pu_err); \
+                        break;                                          \
+                default:                                                \
+                        /* XXX: This looks wrong... */                  \
+                        __pu_err = 0;                                   \
+                        if (copy_to_user(__pu_ptr, &(__pu_val),         \
+                                sizeof(*__pu_ptr)))                     \
+                                __pu_err = -EFAULT;                     \
+                        break;                                          \
+                }                                                       \
+        }                                                               \
+        __pu_err;                                                       \
+})
+#define __put_user(x, ptr) put_user(x, ptr)
+#endif /* _ASM_NIOS2_UACCESS_H */
diff --git a/arch/nios2/include/asm/ucontext.h b/arch/nios2/include/asm/ucontext.h
new file mode 100644
index 000000000000..2c87614b0f6e
--- /dev/null
+++ b/arch/nios2/include/asm/ucontext.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2004 Microtronix Datacom Ltd
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_NIOS2_UCONTEXT_H
+#define _ASM_NIOS2_UCONTEXT_H
+typedef int greg_t;
+#define NGREG 32
+typedef greg_t gregset_t[NGREG];
+struct mcontext {
+        int version;
+        gregset_t gregs;
+};
+#define MCONTEXT_VERSION 2
+struct ucontext {
+        unsigned long     uc_flags;
+        struct ucontext  *uc_link;
+        stack_t           uc_stack;
+        struct mcontext   uc_mcontext;
+        sigset_t          uc_sigmask;   /* mask last for extensibility */
+};
+#endif
diff --git a/arch/nios2/include/uapi/asm/Kbuild b/arch/nios2/include/uapi/asm/Kbuild
new file mode 100644
index 000000000000..4f07ca3f8d10
--- /dev/null
+++ b/arch/nios2/include/uapi/asm/Kbuild
@@ -0,0 +1,4 @@
+include include/uapi/asm-generic/Kbuild.asm
+header-y += elf.h
+header-y += ucontext.h
diff --git a/arch/nios2/include/uapi/asm/byteorder.h b/arch/nios2/include/uapi/asm/byteorder.h
new file mode 100644
index 000000000000..3ab5dc20d757
--- /dev/null
+++ b/arch/nios2/include/uapi/asm/byteorder.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2009   Thomas Chou <thomas@wytron.com.tw>
+ * Copyright (C) 2004   Microtronix Datacom Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef _ASM_NIOS2_BYTEORDER_H
+#define _ASM_NIOS2_BYTEORDER_H
+#include <linux/byteorder/little_endian.h>
+#endif
diff --git a/arch/nios2/include/uapi/asm/elf.h b/arch/nios2/include/uapi/asm/elf.h
new file mode 100644
index 000000000000..a5b91ae5cf56
--- /dev/null
+++ b/arch/nios2/include/uapi/asm/elf.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#ifndef _UAPI_ASM_NIOS2_ELF_H
+#define _UAPI_ASM_NIOS2_ELF_H
+#include <linux/ptrace.h>
+/* Relocation types */
+#define R_NIOS2_NONE            0
+#define R_NIOS2_S16             1
+#define R_NIOS2_U16             2
+#define R_NIOS2_PCREL16         3
+#define R_NIOS2_CALL26          4
+#define R_NIOS2_IMM5            5
+#define R_NIOS2_CACHE_OPX       6
+#define R_NIOS2_IMM6            7
+#define R_NIOS2_IMM8            8
+#define R_NIOS2_HI16            9
+#define R_NIOS2_LO16            10
+#define R_NIOS2_HIADJ16         11
+#define R_NIOS2_BFD_RELOC_32    12
+#define R_NIOS2_BFD_RELOC_16    13
+#define R_NIOS2_BFD_RELOC_8     14
+#define R_NIOS2_GPREL           15
+#define R_NIOS2_GNU_VTINHERIT   16
+#define R_NIOS2_GNU_VTENTRY     17
+#define R_NIOS2_UJMP            18
+#define R_NIOS2_CJMP            19
+#define R_NIOS2_CALLR           20
+#define R_NIOS2_ALIGN           21
+/* Keep this the last entry.  */
+#define R_NIOS2_NUM             22
+typedef unsigned long elf_greg_t;
+#define ELF_NGREG       \
+        ((sizeof(struct pt_regs) + sizeof(struct switch_stack)) /       \
+                sizeof(elf_greg_t))
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+typedef unsigned long elf_fpregset_t;
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_CLASS       ELFCLASS32
+#define ELF_DATA        ELFDATA2LSB
+#define ELF_ARCH        EM_ALTERA_NIOS2
+#endif /* _UAPI_ASM_NIOS2_ELF_H */
diff --git a/arch/nios2/include/uapi/asm/ptrace.h b/arch/nios2/include/uapi/asm/ptrace.h
new file mode 100644
index 000000000000..e83a7c9d1c36
--- /dev/null
+++ b/arch/nios2/include/uapi/asm/ptrace.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2004 Microtronix Datacom Ltd
+ *
+ * based on m68k asm/processor.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _UAPI_ASM_NIOS2_PTRACE_H
+#define _UAPI_ASM_NIOS2_PTRACE_H
+#ifndef __ASSEMBLY__
+/*
+ * Register numbers used by 'ptrace' system call interface.
+ */
+/* GP registers */
+#define PTR_R0          0
+#define PTR_R1          1
+#define PTR_R2          2
+#define PTR_R3          3
+#define PTR_R4          4
+#define PTR_R5          5
+#define PTR_R6          6
+#define PTR_R7          7
+#define PTR_R8          8
+#define PTR_R9          9
+#define PTR_R10         10
+#define PTR_R11         11
+#define PTR_R12         12
+#define PTR_R13         13
+#define PTR_R14         14
+#define PTR_R15         15
+#define PTR_R16         16
+#define PTR_R17         17
+#define PTR_R18         18
+#define PTR_R19         19
+#define PTR_R20         20
+#define PTR_R21         21
+#define PTR_R22         22
+#define PTR_R23         23
+#define PTR_R24         24
+#define PTR_R25         25
+#define PTR_GP          26
+#define PTR_SP          27
+#define PTR_FP          28
+#define PTR_EA          29
+#define PTR_BA          30
+#define PTR_RA          31
+/* Control registers */
+#define PTR_PC          32
+#define PTR_STATUS      33
+#define PTR_ESTATUS     34
+#define PTR_BSTATUS     35
+#define PTR_IENABLE     36
+#define PTR_IPENDING    37
+#define PTR_CPUID       38
+#define PTR_CTL6        39
+#define PTR_CTL7        40
+#define PTR_PTEADDR     41
+#define PTR_TLBACC      42
+#define PTR_TLBMISC     43
+#define NUM_PTRACE_REG (PTR_TLBMISC + 1)
+/* this struct defines the way the registers are stored on the
+   stack during a system call.
+   There is a fake_regs in setup.c that has to match pt_regs.*/
+struct pt_regs {
+        unsigned long  r8;              /* r8-r15 Caller-saved GP registers */
+        unsigned long  r9;
+        unsigned long  r10;
+        unsigned long  r11;
+        unsigned long  r12;
+        unsigned long  r13;
+        unsigned long  r14;
+        unsigned long  r15;
+        unsigned long  r1;              /* Assembler temporary */
+        unsigned long  r2;              /* Retval LS 32bits */
+        unsigned long  r3;              /* Retval MS 32bits */
+        unsigned long  r4;              /* r4-r7 Register arguments */
+        unsigned long  r5;
+        unsigned long  r6;
+        unsigned long  r7;
+        unsigned long  orig_r2;         /* Copy of r2 ?? */
+        unsigned long  ra;              /* Return address */
+        unsigned long  fp;              /* Frame pointer */
+        unsigned long  sp;              /* Stack pointer */
+        unsigned long  gp;              /* Global pointer */
+        unsigned long  estatus;
+        unsigned long  ea;              /* Exception return address (pc) */
+        unsigned long  orig_r7;
+};
+/*
+ * This is the extended stack used by signal handlers and the context
+ * switcher: it's pushed after the normal "struct pt_regs".
+ */
+struct switch_stack {
+        unsigned long  r16;             /* r16-r23 Callee-saved GP registers */
+        unsigned long  r17;
+        unsigned long  r18;
+        unsigned long  r19;
+        unsigned long  r20;
+        unsigned long  r21;
+        unsigned long  r22;
+        unsigned long  r23;
+        unsigned long  fp;
+        unsigned long  gp;
+        unsigned long  ra;
+};
+#endif /* __ASSEMBLY__ */
+#endif /* _UAPI_ASM_NIOS2_PTRACE_H */
diff --git a/arch/nios2/include/uapi/asm/sigcontext.h b/arch/nios2/include/uapi/asm/sigcontext.h
new file mode 100644
index 000000000000..7b8bb41867d4
--- /dev/null
+++ b/arch/nios2/include/uapi/asm/sigcontext.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2004, Microtronix Datacom Ltd.
+ *
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ */
+#ifndef _ASM_NIOS2_SIGCONTEXT_H
+#define _ASM_NIOS2_SIGCONTEXT_H
+#include <asm/ptrace.h>
+struct sigcontext {
+        struct pt_regs regs;
+        unsigned long  sc_mask; /* old sigmask */
+};
+#endif
diff --git a/arch/nios2/include/uapi/asm/signal.h b/arch/nios2/include/uapi/asm/signal.h
new file mode 100644
index 000000000000..f29ee6314481
--- /dev/null
+++ b/arch/nios2/include/uapi/asm/signal.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright Altera Corporation (C) 2013. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#ifndef _ASM_NIOS2_SIGNAL_H
+#define _ASM_NIOS2_SIGNAL_H
+#define SA_RESTORER 0x04000000
+#include <asm-generic/signal.h>
+#endif /* _ASM_NIOS2_SIGNAL_H */
diff --git a/arch/nios2/include/uapi/asm/swab.h b/arch/nios2/include/uapi/asm/swab.h
new file mode 100644
index 000000000000..b4e22ebaeb17
--- /dev/null
+++ b/arch/nios2/include/uapi/asm/swab.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2012 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2011 Pyramid Technical Consultants, Inc.
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file COPYING in the main directory of this
+ * archive for more details.
+ */
+#ifndef _ASM_NIOS2_SWAB_H
+#define _ASM_NIOS2_SWAB_H
+#include <linux/types.h>
+#include <asm-generic/swab.h>
+#ifdef CONFIG_NIOS2_CI_SWAB_SUPPORT
+#ifdef __GNUC__
+#define __nios2_swab(x)         \
+        __builtin_custom_ini(CONFIG_NIOS2_CI_SWAB_NO, (x))
+static inline __attribute__((const)) __u16 __arch_swab16(__u16 x)
+{
+        return (__u16) __nios2_swab(((__u32) x) << 16);
+}
+#define __arch_swab16 __arch_swab16
+static inline __attribute__((const)) __u32 __arch_swab32(__u32 x)
+{
+        return (__u32) __nios2_swab(x);
+}
+#define __arch_swab32 __arch_swab32
+#endif /* __GNUC__ */
+#endif /* CONFIG_NIOS2_CI_SWAB_SUPPORT */
+#endif /* _ASM_NIOS2_SWAB_H */
diff --git a/arch/nios2/include/uapi/asm/unistd.h b/arch/nios2/include/uapi/asm/unistd.h
new file mode 100644
index 000000000000..c4bf79510461
--- /dev/null
+++ b/arch/nios2/include/uapi/asm/unistd.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+ #define sys_mmap2 sys_mmap_pgoff
+/* Use the standard ABI for syscalls */
+#include <asm-generic/unistd.h>
+/* Additional Nios II specific syscalls. */
+#define __NR_cacheflush (__NR_arch_specific_syscall)
+__SYSCALL(__NR_cacheflush, sys_cacheflush)
diff --git a/arch/nios2/kernel/Makefile b/arch/nios2/kernel/Makefile
new file mode 100644
index 000000000000..8ae76823ff93
--- /dev/null
+++ b/arch/nios2/kernel/Makefile
@@ -0,0 +1,24 @@
+#
+# Makefile for the nios2 linux kernel.
+#
+extra-y += head.o
+extra-y += vmlinux.lds
+obj-y   += cpuinfo.o
+obj-y   += entry.o
+obj-y   += insnemu.o
+obj-y   += irq.o
+obj-y   += nios2_ksyms.o
+obj-y   += process.o
+obj-y   += prom.o
+obj-y   += ptrace.o
+obj-y   += setup.o
+obj-y   += signal.o
+obj-y   += sys_nios2.o
+obj-y   += syscall_table.o
+obj-y   += time.o
+obj-y   += traps.o
+obj-$(CONFIG_MODULES)                   += module.o
+obj-$(CONFIG_NIOS2_ALIGNMENT_TRAP)      += misaligned.o
diff --git a/arch/nios2/kernel/asm-offsets.c b/arch/nios2/kernel/asm-offsets.c
new file mode 100644
index 000000000000..c3ee73c18b71
--- /dev/null
+++ b/arch/nios2/kernel/asm-offsets.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#include <linux/stddef.h>
+#include <linux/sched.h>
+#include <linux/kernel_stat.h>
+#include <linux/ptrace.h>
+#include <linux/hardirq.h>
+#include <linux/thread_info.h>
+#include <linux/kbuild.h>
+int main(void)
+{
+        /* struct task_struct */
+        OFFSET(TASK_THREAD, task_struct, thread);
+        BLANK();
+        /* struct thread_struct */
+        OFFSET(THREAD_KSP, thread_struct, ksp);
+        OFFSET(THREAD_KPSR, thread_struct, kpsr);
+        BLANK();
+        /* struct pt_regs */
+        OFFSET(PT_ORIG_R2, pt_regs, orig_r2);
+        OFFSET(PT_ORIG_R7, pt_regs, orig_r7);
+        OFFSET(PT_R1, pt_regs, r1);
+        OFFSET(PT_R2, pt_regs, r2);
+        OFFSET(PT_R3, pt_regs, r3);
+        OFFSET(PT_R4, pt_regs, r4);
+        OFFSET(PT_R5, pt_regs, r5);
+        OFFSET(PT_R6, pt_regs, r6);
+        OFFSET(PT_R7, pt_regs, r7);
+        OFFSET(PT_R8, pt_regs, r8);
+        OFFSET(PT_R9, pt_regs, r9);
+        OFFSET(PT_R10, pt_regs, r10);
+        OFFSET(PT_R11, pt_regs, r11);
+        OFFSET(PT_R12, pt_regs, r12);
+        OFFSET(PT_R13, pt_regs, r13);
+        OFFSET(PT_R14, pt_regs, r14);
+        OFFSET(PT_R15, pt_regs, r15);
+        OFFSET(PT_EA, pt_regs, ea);
+        OFFSET(PT_RA, pt_regs, ra);
+        OFFSET(PT_FP, pt_regs, fp);
+        OFFSET(PT_SP, pt_regs, sp);
+        OFFSET(PT_GP, pt_regs, gp);
+        OFFSET(PT_ESTATUS, pt_regs, estatus);
+        DEFINE(PT_REGS_SIZE, sizeof(struct pt_regs));
+        BLANK();
+        /* struct switch_stack */
+        OFFSET(SW_R16, switch_stack, r16);
+        OFFSET(SW_R17, switch_stack, r17);
+        OFFSET(SW_R18, switch_stack, r18);
+        OFFSET(SW_R19, switch_stack, r19);
+        OFFSET(SW_R20, switch_stack, r20);
+        OFFSET(SW_R21, switch_stack, r21);
+        OFFSET(SW_R22, switch_stack, r22);
+        OFFSET(SW_R23, switch_stack, r23);
+        OFFSET(SW_FP, switch_stack, fp);
+        OFFSET(SW_GP, switch_stack, gp);
+        OFFSET(SW_RA, switch_stack, ra);
+        DEFINE(SWITCH_STACK_SIZE, sizeof(struct switch_stack));
+        BLANK();
+        /* struct thread_info */
+        OFFSET(TI_FLAGS, thread_info, flags);
+        OFFSET(TI_PREEMPT_COUNT, thread_info, preempt_count);
+        BLANK();
+        return 0;
+}
diff --git a/arch/nios2/kernel/cpuinfo.c b/arch/nios2/kernel/cpuinfo.c
new file mode 100644
index 000000000000..51d5bb90d3e5
--- /dev/null
+++ b/arch/nios2/kernel/cpuinfo.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
+ *
+ * Based on cpuinfo.c from microblaze
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/string.h>
+#include <linux/of.h>
+#include <asm/cpuinfo.h>
+struct cpuinfo cpuinfo;
+#define err_cpu(x) \
+        pr_err("ERROR: Nios II " x " different for kernel and DTS\n")
+static inline u32 fcpu(struct device_node *cpu, const char *n)
+{
+        u32 val = 0;
+        of_property_read_u32(cpu, n, &val);
+        return val;
+}
+static inline u32 fcpu_has(struct device_node *cpu, const char *n)
+{
+        return of_get_property(cpu, n, NULL) ? 1 : 0;
+}
+void __init setup_cpuinfo(void)
+{
+        struct device_node *cpu;
+        const char *str;
+        int len;
+        cpu = of_find_node_by_type(NULL, "cpu");
+        if (!cpu)
+                panic("%s: No CPU found in devicetree!\n", __func__);
+        if (!fcpu_has(cpu, "altr,has-initda"))
+                panic("initda instruction is unimplemented. Please update your "
+                        "hardware system to have more than 4-byte line data "
+                        "cache\n");
+        cpuinfo.cpu_clock_freq = fcpu(cpu, "clock-frequency");
+        str = of_get_property(cpu, "altr,implementation", &len);
+        if (str)
+                strlcpy(cpuinfo.cpu_impl, str, sizeof(cpuinfo.cpu_impl));
+        else
+                strcpy(cpuinfo.cpu_impl, "<unknown>");
+        cpuinfo.has_div = fcpu_has(cpu, "altr,has-div");
+        cpuinfo.has_mul = fcpu_has(cpu, "altr,has-mul");
+        cpuinfo.has_mulx = fcpu_has(cpu, "altr,has-mulx");
+        if (IS_ENABLED(CONFIG_NIOS2_HW_DIV_SUPPORT) && !cpuinfo.has_div)
+                err_cpu("DIV");
+        if (IS_ENABLED(CONFIG_NIOS2_HW_MUL_SUPPORT) && !cpuinfo.has_mul)
+                err_cpu("MUL");
+        if (IS_ENABLED(CONFIG_NIOS2_HW_MULX_SUPPORT) && !cpuinfo.has_mulx)
+                err_cpu("MULX");
+        cpuinfo.tlb_num_ways = fcpu(cpu, "altr,tlb-num-ways");
+        if (!cpuinfo.tlb_num_ways)
+                panic("altr,tlb-num-ways can't be 0. Please check your hardware "
+                        "system\n");
+        cpuinfo.icache_line_size = fcpu(cpu, "icache-line-size");
+        cpuinfo.icache_size = fcpu(cpu, "icache-size");
+        if (CONFIG_NIOS2_ICACHE_SIZE != cpuinfo.icache_size)
+                pr_warn("Warning: icache size configuration mismatch "
+                "(0x%x vs 0x%x) of CONFIG_NIOS2_ICACHE_SIZE vs "
+                "device tree icache-size\n",
+                CONFIG_NIOS2_ICACHE_SIZE, cpuinfo.icache_size);
+        cpuinfo.dcache_line_size = fcpu(cpu, "dcache-line-size");
+        if (CONFIG_NIOS2_DCACHE_LINE_SIZE != cpuinfo.dcache_line_size)
+                pr_warn("Warning: dcache line size configuration mismatch "
+                "(0x%x vs 0x%x) of CONFIG_NIOS2_DCACHE_LINE_SIZE vs "
+                "device tree dcache-line-size\n",
+                CONFIG_NIOS2_DCACHE_LINE_SIZE, cpuinfo.dcache_line_size);
+        cpuinfo.dcache_size = fcpu(cpu, "dcache-size");
+        if (CONFIG_NIOS2_DCACHE_SIZE != cpuinfo.dcache_size)
+                pr_warn("Warning: dcache size configuration mismatch "
+                        "(0x%x vs 0x%x) of CONFIG_NIOS2_DCACHE_SIZE vs "
+                        "device tree dcache-size\n",
+                        CONFIG_NIOS2_DCACHE_SIZE, cpuinfo.dcache_size);
+        cpuinfo.tlb_pid_num_bits = fcpu(cpu, "altr,pid-num-bits");
+        cpuinfo.tlb_num_ways_log2 = ilog2(cpuinfo.tlb_num_ways);
+        cpuinfo.tlb_num_entries = fcpu(cpu, "altr,tlb-num-entries");
+        cpuinfo.tlb_num_lines = cpuinfo.tlb_num_entries / cpuinfo.tlb_num_ways;
+        cpuinfo.tlb_ptr_sz = fcpu(cpu, "altr,tlb-ptr-sz");
+        cpuinfo.reset_addr = fcpu(cpu, "altr,reset-addr");
+        cpuinfo.exception_addr = fcpu(cpu, "altr,exception-addr");
+        cpuinfo.fast_tlb_miss_exc_addr = fcpu(cpu, "altr,fast-tlb-miss-addr");
+}
+#ifdef CONFIG_PROC_FS
+/*
+ * Get CPU information for use by the procfs.
+ */
+static int show_cpuinfo(struct seq_file *m, void *v)
+{
+        int count = 0;
+        const u32 clockfreq = cpuinfo.cpu_clock_freq;
+        count = seq_printf(m,
+                        "CPU:\t\tNios II/%s\n"
+                        "MMU:\t\t%s\n"
+                        "FPU:\t\tnone\n"
+                        "Clocking:\t%u.%02u MHz\n"
+                        "BogoMips:\t%lu.%02lu\n"
+                        "Calibration:\t%lu loops\n",
+                        cpuinfo.cpu_impl,
+                        cpuinfo.mmu ? "present" : "none",
+                        clockfreq / 1000000, (clockfreq / 100000) % 10,
+                        (loops_per_jiffy * HZ) / 500000,
+                        ((loops_per_jiffy * HZ) / 5000) % 100,
+                        (loops_per_jiffy * HZ));
+        count += seq_printf(m,
+                        "HW:\n"
+                        " MUL:\t\t%s\n"
+                        " MULX:\t\t%s\n"
+                        " DIV:\t\t%s\n",
+                        cpuinfo.has_mul ? "yes" : "no",
+                        cpuinfo.has_mulx ? "yes" : "no",
+                        cpuinfo.has_div ? "yes" : "no");
+        count += seq_printf(m,
+                        "Icache:\t\t%ukB, line length: %u\n",
+                        cpuinfo.icache_size >> 10,
+                        cpuinfo.icache_line_size);
+        count += seq_printf(m,
+                        "Dcache:\t\t%ukB, line length: %u\n",
+                        cpuinfo.dcache_size >> 10,
+                        cpuinfo.dcache_line_size);
+        count += seq_printf(m,
+                        "TLB:\t\t%u ways, %u entries, %u PID bits\n",
+                        cpuinfo.tlb_num_ways,
+                        cpuinfo.tlb_num_entries,
+                        cpuinfo.tlb_pid_num_bits);
+        return 0;
+}
+static void *cpuinfo_start(struct seq_file *m, loff_t *pos)
+{
+        unsigned long i = *pos;
+        return i < num_possible_cpus() ? (void *) (i + 1) : NULL;
+}
+static void *cpuinfo_next(struct seq_file *m, void *v, loff_t *pos)
+{
+        ++*pos;
+        return cpuinfo_start(m, pos);
+}
+static void cpuinfo_stop(struct seq_file *m, void *v)
+{
+}
+const struct seq_operations cpuinfo_op = {
+        .start  = cpuinfo_start,
+        .next   = cpuinfo_next,
+        .stop   = cpuinfo_stop,
+        .show   = show_cpuinfo
+};
+#endif /* CONFIG_PROC_FS */
diff --git a/arch/nios2/kernel/entry.S b/arch/nios2/kernel/entry.S
new file mode 100644
index 000000000000..83bca17d1008
--- /dev/null
+++ b/arch/nios2/kernel/entry.S
@@ -0,0 +1,555 @@
+/*
+ * linux/arch/nios2/kernel/entry.S
+ *
+ * Copyright (C) 2013-2014  Altera Corporation
+ * Copyright (C) 2009, Wind River Systems Inc
+ *
+ * Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
+ *
+ *  Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
+ *  Copyright (C) 1998  D. Jeff Dionne <jeff@lineo.ca>,
+ *                      Kenneth Albanowski <kjahds@kjahds.com>,
+ *  Copyright (C) 2000  Lineo Inc. (www.lineo.com)
+ *  Copyright (C) 2004  Microtronix Datacom Ltd.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Linux/m68k support by Hamish Macdonald
+ *
+ * 68060 fixes by Jesper Skov
+ * ColdFire support by Greg Ungerer (gerg@snapgear.com)
+ * 5307 fixes by David W. Miller
+ * linux 2.4 support David McCullough <davidm@snapgear.com>
+ */
+#include <linux/sys.h>
+#include <linux/linkage.h>
+#include <asm/asm-offsets.h>
+#include <asm/asm-macros.h>
+#include <asm/thread_info.h>
+#include <asm/errno.h>
+#include <asm/setup.h>
+#include <asm/entry.h>
+#include <asm/unistd.h>
+#include <asm/processor.h>
+.macro GET_THREAD_INFO reg
+.if THREAD_SIZE & 0xffff0000
+        andhi   \reg, sp, %hi(~(THREAD_SIZE-1))
+.else
+        addi    \reg, r0, %lo(~(THREAD_SIZE-1))
+        and     \reg, \reg, sp
+.endif
+.endm
+.macro  kuser_cmpxchg_check
+        /*
+         * Make sure our user space atomic helper is restarted if it was
+         * interrupted in a critical region.
+         * ea-4 = address of interrupted insn (ea must be preserved).
+         * sp = saved regs.
+         * cmpxchg_ldw = first critical insn, cmpxchg_stw = last critical insn.
+         * If ea <= cmpxchg_stw and ea > cmpxchg_ldw then saved EA is set to
+         * cmpxchg_ldw + 4.
+        */
+        /* et = cmpxchg_stw + 4 */
+        movui   et, (KUSER_BASE + 4 + (cmpxchg_stw - __kuser_helper_start))
+        bgtu    ea, et, 1f
+        subi    et, et, (cmpxchg_stw - cmpxchg_ldw) /* et = cmpxchg_ldw + 4 */
+        bltu    ea, et, 1f
+        stw     et, PT_EA(sp)   /* fix up EA */
+        mov     ea, et
+1:
+.endm
+.section .rodata
+.align 4
+exception_table:
+        .word unhandled_exception       /* 0 - Reset */
+        .word unhandled_exception       /* 1 - Processor-only Reset */
+        .word external_interrupt        /* 2 - Interrupt */
+        .word handle_trap               /* 3 - Trap Instruction */
+        .word instruction_trap          /* 4 - Unimplemented instruction */
+        .word handle_illegal            /* 5 - Illegal instruction */
+        .word handle_unaligned          /* 6 - Misaligned data access */
+        .word handle_unaligned          /* 7 - Misaligned destination address */
+        .word handle_diverror           /* 8 - Division error */
+        .word protection_exception_ba   /* 9 - Supervisor-only instr. address */
+        .word protection_exception_instr /* 10 - Supervisor only instruction */
+        .word protection_exception_ba   /* 11 - Supervisor only data address */
+        .word unhandled_exception       /* 12 - Double TLB miss (data) */
+        .word protection_exception_pte  /* 13 - TLB permission violation (x) */
+        .word protection_exception_pte  /* 14 - TLB permission violation (r) */
+        .word protection_exception_pte  /* 15 - TLB permission violation (w) */
+        .word unhandled_exception       /* 16 - MPU region violation */
+trap_table:
+        .word   handle_system_call      /* 0  */
+        .word   instruction_trap        /* 1  */
+        .word   instruction_trap        /* 2  */
+        .word   instruction_trap        /* 3  */
+        .word   instruction_trap        /* 4  */
+        .word   instruction_trap        /* 5  */
+        .word   instruction_trap        /* 6  */
+        .word   instruction_trap        /* 7  */
+        .word   instruction_trap        /* 8  */
+        .word   instruction_trap        /* 9  */
+        .word   instruction_trap        /* 10 */
+        .word   instruction_trap        /* 11 */
+        .word   instruction_trap        /* 12 */
+        .word   instruction_trap        /* 13 */
+        .word   instruction_trap        /* 14 */
+        .word   instruction_trap        /* 15 */
+        .word   instruction_trap        /* 16 */
+        .word   instruction_trap        /* 17 */
+        .word   instruction_trap        /* 18 */
+        .word   instruction_trap        /* 19 */
+        .word   instruction_trap        /* 20 */
+        .word   instruction_trap        /* 21 */
+        .word   instruction_trap        /* 22 */
+        .word   instruction_trap        /* 23 */
+        .word   instruction_trap        /* 24 */
+        .word   instruction_trap        /* 25 */
+        .word   instruction_trap        /* 26 */
+        .word   instruction_trap        /* 27 */
+        .word   instruction_trap        /* 28 */
+        .word   instruction_trap        /* 29 */
+        .word   instruction_trap        /* 30 */
+        .word   handle_breakpoint       /* 31 */
+.text
+.set noat
+.set nobreak
+ENTRY(inthandler)
+        SAVE_ALL
+        kuser_cmpxchg_check
+        /* Clear EH bit before we get a new excpetion in the kernel
+         * and after we have saved it to the exception frame. This is done
+         * whether it's trap, tlb-miss or interrupt. If we don't do this
+         * estatus is not updated the next exception.
+         */
+        rdctl   r24, status
+        movi    r9, %lo(~STATUS_EH)
+        and     r24, r24, r9
+        wrctl   status, r24
+        /* Read cause and vector and branch to the associated handler */
+        mov     r4, sp
+        rdctl   r5, exception
+        movia   r9, exception_table
+        add     r24, r9, r5
+        ldw     r24, 0(r24)
+        jmp     r24
+/***********************************************************************
+ * Handle traps
+ ***********************************************************************
+ */
+ENTRY(handle_trap)
+        ldw     r24, -4(ea)     /* instruction that caused the exception */
+        srli    r24, r24, 4
+        andi    r24, r24, 0x7c
+        movia   r9,trap_table
+        add     r24, r24, r9
+        ldw     r24, 0(r24)
+        jmp     r24
+/***********************************************************************
+ * Handle system calls
+ ***********************************************************************
+ */
+ENTRY(handle_system_call)
+        /* Enable interrupts */
+        rdctl   r10, status
+        ori     r10, r10, STATUS_PIE
+        wrctl   status, r10
+        /* Reload registers destroyed by common code. */
+        ldw     r4, PT_R4(sp)
+        ldw     r5, PT_R5(sp)
+local_restart:
+        /* Check that the requested system call is within limits */
+        movui   r1, __NR_syscalls
+        bgeu    r2, r1, ret_invsyscall
+        slli    r1, r2, 2
+        movhi   r11, %hiadj(sys_call_table)
+        add     r1, r1, r11
+        ldw     r1, %lo(sys_call_table)(r1)
+        beq     r1, r0, ret_invsyscall
+        /* Check if we are being traced */
+        GET_THREAD_INFO r11
+        ldw     r11,TI_FLAGS(r11)
+        BTBNZ   r11,r11,TIF_SYSCALL_TRACE,traced_system_call
+        /* Execute the system call */
+        callr   r1
+        /* If the syscall returns a negative result:
+         *   Set r7 to 1 to indicate error,
+         *   Negate r2 to get a positive error code
+         * If the syscall returns zero or a positive value:
+         *   Set r7 to 0.
+         * The sigreturn system calls will skip the code below by
+         * adding to register ra. To avoid destroying registers
+         */
+translate_rc_and_ret:
+        movi    r1, 0
+        bge     r2, zero, 3f
+        sub     r2, zero, r2
+        movi    r1, 1
+3:
+        stw     r2, PT_R2(sp)
+        stw     r1, PT_R7(sp)
+end_translate_rc_and_ret:
+ret_from_exception:
+        ldw     r1, PT_ESTATUS(sp)
+        /* if so, skip resched, signals */
+        TSTBNZ  r1, r1, ESTATUS_EU, Luser_return
+restore_all:
+        rdctl   r10, status                     /* disable intrs */
+        andi    r10, r10, %lo(~STATUS_PIE)
+        wrctl   status, r10
+        RESTORE_ALL
+        eret
+        /* If the syscall number was invalid return ENOSYS */
+ret_invsyscall:
+        movi    r2, -ENOSYS
+        br      translate_rc_and_ret
+        /* This implements the same as above, except it calls
+         * do_syscall_trace_enter and do_syscall_trace_exit before and after the
+         * syscall in order for utilities like strace and gdb to work.
+         */
+traced_system_call:
+        SAVE_SWITCH_STACK
+        call    do_syscall_trace_enter
+        RESTORE_SWITCH_STACK
+        /* Create system call register arguments. The 5th and 6th
+           arguments on stack are already in place at the beginning
+           of pt_regs. */
+        ldw     r2, PT_R2(sp)
+        ldw     r4, PT_R4(sp)
+        ldw     r5, PT_R5(sp)
+        ldw     r6, PT_R6(sp)
+        ldw     r7, PT_R7(sp)
+        /* Fetch the syscall function, we don't need to check the boundaries
+         * since this is already done.
+         */
+        slli    r1, r2, 2
+        movhi   r11,%hiadj(sys_call_table)
+        add     r1, r1, r11
+        ldw     r1, %lo(sys_call_table)(r1)
+        callr   r1
+        /* If the syscall returns a negative result:
+         *   Set r7 to 1 to indicate error,
+         *   Negate r2 to get a positive error code
+         * If the syscall returns zero or a positive value:
+         *   Set r7 to 0.
+         * The sigreturn system calls will skip the code below by
+         * adding to register ra. To avoid destroying registers
+         */
+translate_rc_and_ret2:
+        movi    r1, 0
+        bge     r2, zero, 4f
+        sub     r2, zero, r2
+        movi    r1, 1
+4:
+        stw     r2, PT_R2(sp)
+        stw     r1, PT_R7(sp)
+end_translate_rc_and_ret2:
+        SAVE_SWITCH_STACK
+        call    do_syscall_trace_exit
+        RESTORE_SWITCH_STACK
+        br      ret_from_exception
+Luser_return:
+        GET_THREAD_INFO r11                     /* get thread_info pointer */
+        ldw     r10, TI_FLAGS(r11)              /* get thread_info->flags */
+        ANDI32  r11, r10, _TIF_WORK_MASK
+        beq     r11, r0, restore_all            /* Nothing to do */
+        BTBZ    r1, r10, TIF_NEED_RESCHED, Lsignal_return
+        /* Reschedule work */
+        call    schedule
+        br      ret_from_exception
+Lsignal_return:
+        ANDI32  r1, r10, _TIF_SIGPENDING | _TIF_NOTIFY_RESUME
+        beq     r1, r0, restore_all
+        mov     r4, sp                  /* pt_regs */
+        SAVE_SWITCH_STACK
+        call    do_notify_resume
+        beq     r2, r0, no_work_pending
+        RESTORE_SWITCH_STACK
+        /* prepare restart syscall here without leaving kernel */
+        ldw     r2, PT_R2(sp)   /* reload syscall number in r2 */
+        ldw     r4, PT_R4(sp)   /* reload syscall arguments r4-r9 */
+        ldw     r5, PT_R5(sp)
+        ldw     r6, PT_R6(sp)
+        ldw     r7, PT_R7(sp)
+        ldw     r8, PT_R8(sp)
+        ldw     r9, PT_R9(sp)
+        br      local_restart   /* restart syscall */
+no_work_pending:
+        RESTORE_SWITCH_STACK
+        br      ret_from_exception
+/***********************************************************************
+ * Handle external interrupts.
+ ***********************************************************************
+ */
+/*
+ * This is the generic interrupt handler (for all hardware interrupt
+ * sources). It figures out the vector number and calls the appropriate
+ * interrupt service routine directly.
+ */
+external_interrupt:
+        rdctl   r12, ipending
+        rdctl   r9, ienable
+        and     r12, r12, r9
+        /* skip if no interrupt is pending */
+        beq     r12, r0, ret_from_interrupt
+        movi    r24, -1
+        stw     r24, PT_ORIG_R2(sp)
+        /*
+         * Process an external hardware interrupt.
+         */
+        addi    ea, ea, -4      /* re-issue the interrupted instruction */
+        stw     ea, PT_EA(sp)
+2:      movi    r4, %lo(-1)     /* Start from bit position 0,
+                                        highest priority */
+                                /* This is the IRQ # for handler call */
+1:      andi    r10, r12, 1     /* Isolate bit we are interested in */
+        srli    r12, r12, 1     /* shift count is costly without hardware
+                                        multiplier */
+        addi    r4, r4, 1
+        beq     r10, r0, 1b
+        mov     r5, sp          /* Setup pt_regs pointer for handler call */
+        call    do_IRQ
+        rdctl   r12, ipending   /* check again if irq still pending */
+        rdctl   r9, ienable     /* Isolate possible interrupts */
+        and     r12, r12, r9
+        bne     r12, r0, 2b
+        /* br   ret_from_interrupt */ /* fall through to ret_from_interrupt */
+ENTRY(ret_from_interrupt)
+        ldw     r1, PT_ESTATUS(sp)      /* check if returning to kernel */
+        TSTBNZ  r1, r1, ESTATUS_EU, Luser_return
+#ifdef CONFIG_PREEMPT
+        GET_THREAD_INFO r1
+        ldw     r4, TI_PREEMPT_COUNT(r1)
+        bne     r4, r0, restore_all
+need_resched:
+        ldw     r4, TI_FLAGS(r1)                /* ? Need resched set */
+        BTBZ    r10, r4, TIF_NEED_RESCHED, restore_all
+        ldw     r4, PT_ESTATUS(sp)      /* ? Interrupts off */
+        andi    r10, r4, ESTATUS_EPIE
+        beq     r10, r0, restore_all
+        movia   r4, PREEMPT_ACTIVE
+        stw     r4, TI_PREEMPT_COUNT(r1)
+        rdctl   r10, status             /* enable intrs again */
+        ori     r10, r10 ,STATUS_PIE
+        wrctl   status, r10
+        PUSH    r1
+        call    schedule
+        POP     r1
+        mov     r4, r0
+        stw     r4, TI_PREEMPT_COUNT(r1)
+        rdctl   r10, status             /* disable intrs */
+        andi    r10, r10, %lo(~STATUS_PIE)
+        wrctl   status, r10
+        br      need_resched
+#else
+        br      restore_all
+#endif
+/***********************************************************************
+ * A few syscall wrappers
+ ***********************************************************************
+ */
+/*
+ * int clone(unsigned long clone_flags, unsigned long newsp,
+ *              int __user * parent_tidptr, int __user * child_tidptr,
+ *              int tls_val)
+ */
+ENTRY(sys_clone)
+        SAVE_SWITCH_STACK
+        addi    sp, sp, -4
+        stw     r7, 0(sp)       /* Pass 5th arg thru stack */
+        mov     r7, r6          /* 4th arg is 3rd of clone() */
+        mov     r6, zero        /* 3rd arg always 0 */
+        call    do_fork
+        addi    sp, sp, 4
+        RESTORE_SWITCH_STACK
+        ret
+ENTRY(sys_rt_sigreturn)
+        SAVE_SWITCH_STACK
+        mov     r4, sp
+        call    do_rt_sigreturn
+        RESTORE_SWITCH_STACK
+        addi    ra, ra, (end_translate_rc_and_ret - translate_rc_and_ret)
+        ret
+/***********************************************************************
+ * A few other wrappers and stubs
+ ***********************************************************************
+ */
+protection_exception_pte:
+        rdctl   r6, pteaddr
+        slli    r6, r6, 10
+        call    do_page_fault
+        br      ret_from_exception
+protection_exception_ba:
+        rdctl   r6, badaddr
+        call    do_page_fault
+        br      ret_from_exception
+protection_exception_instr:
+        call    handle_supervisor_instr
+        br      ret_from_exception
+handle_breakpoint:
+        call    breakpoint_c
+        br      ret_from_exception
+#ifdef CONFIG_NIOS2_ALIGNMENT_TRAP
+handle_unaligned:
+        SAVE_SWITCH_STACK
+        call    handle_unaligned_c
+        RESTORE_SWITCH_STACK
+        br      ret_from_exception
+#else
+handle_unaligned:
+        call    handle_unaligned_c
+        br      ret_from_exception
+#endif
+handle_illegal:
+        call    handle_illegal_c
+        br      ret_from_exception
+handle_diverror:
+        call    handle_diverror_c
+        br      ret_from_exception
+/*
+ * Beware - when entering resume, prev (the current task) is
+ * in r4, next (the new task) is in r5, don't change these
+ * registers.
+ */
+ENTRY(resume)
+        rdctl   r7, status                      /* save thread status reg */
+        stw     r7, TASK_THREAD + THREAD_KPSR(r4)
+        andi    r7, r7, %lo(~STATUS_PIE)        /* disable interrupts */
+        wrctl   status, r7
+        SAVE_SWITCH_STACK
+        stw     sp, TASK_THREAD + THREAD_KSP(r4)/* save kernel stack pointer */
+        ldw     sp, TASK_THREAD + THREAD_KSP(r5)/* restore new thread stack */
+        movia   r24, _current_thread            /* save thread */
+        GET_THREAD_INFO r1
+        stw     r1, 0(r24)
+        RESTORE_SWITCH_STACK
+        ldw     r7, TASK_THREAD + THREAD_KPSR(r5)/* restore thread status reg */
+        wrctl   status, r7
+        ret
+ENTRY(ret_from_fork)
+        call    schedule_tail
+        br      ret_from_exception
+ENTRY(ret_from_kernel_thread)
+        call    schedule_tail
+        mov     r4,r17  /* arg */
+        callr   r16     /* function */
+        br      ret_from_exception
+/*
+ * Kernel user helpers.
+ *
+ * Each segment is 64-byte aligned and will be mapped to the <User space>.
+ * New segments (if ever needed) must be added after the existing ones.
+ * This mechanism should be used only for things that are really small and
+ * justified, and not be abused freely.
+ *
+ */
+ /* Filling pads with undefined instructions. */
+.macro  kuser_pad sym size
+        .if     ((. - \sym) & 3)
+        .rept   (4 - (. - \sym) & 3)
+        .byte   0
+        .endr
+        .endif
+        .rept   ((\size - (. - \sym)) / 4)
+        .word   0xdeadbeef
+        .endr
+.endm
+        .align  6
+        .globl  __kuser_helper_start
+__kuser_helper_start:
+__kuser_helper_version:                         /* @ 0x1000 */
+        .word   ((__kuser_helper_end - __kuser_helper_start) >> 6)
+__kuser_cmpxchg:                                /* @ 0x1004 */
+        /*
+         * r4 pointer to exchange variable
+         * r5 old value
+         * r6 new value
+         */
+cmpxchg_ldw:
+        ldw     r2, 0(r4)                       /* load current value */
+        sub     r2, r2, r5                      /* compare with old value */
+        bne     r2, zero, cmpxchg_ret
+        /* We had a match, store the new value */
+cmpxchg_stw:
+        stw     r6, 0(r4)
+cmpxchg_ret:
+        ret
+        kuser_pad __kuser_cmpxchg, 64
+        .globl  __kuser_sigtramp
+__kuser_sigtramp:
+        movi    r2, __NR_rt_sigreturn
+        trap
+        kuser_pad __kuser_sigtramp, 64
+        .globl  __kuser_helper_end
+__kuser_helper_end:
diff --git a/arch/nios2/kernel/head.S b/arch/nios2/kernel/head.S
new file mode 100644
index 000000000000..372ce4a33018
--- /dev/null
+++ b/arch/nios2/kernel/head.S
@@ -0,0 +1,175 @@
+/*
+ * Copyright (C) 2009 Wind River Systems Inc
+ *   Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
+ * Copyright (C) 2004 Microtronix Datacom Ltd
+ * Copyright (C) 2001 Vic Phillips, Microtronix Datacom Ltd.
+ *
+ * Based on head.S for Altera's Excalibur development board with nios processor
+ *
+ * Based on the following from the Excalibur sdk distribution:
+ *      NA_MemoryMap.s, NR_JumpToStart.s, NR_Setup.s, NR_CWPManager.s
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/linkage.h>
+#include <asm/thread_info.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/page.h>
+#include <asm/asm-offsets.h>
+#include <asm/asm-macros.h>
+/*
+ * ZERO_PAGE is a special page that is used for zero-initialized
+ * data and COW.
+ */
+.data
+.global empty_zero_page
+.align 12
+empty_zero_page:
+        .space  PAGE_SIZE
+/*
+ * This global variable is used as an extension to the nios'
+ * STATUS register to emulate a user/supervisor mode.
+ */
+        .data
+        .align  2
+        .set noat
+        .global _current_thread
+_current_thread:
+        .long   0
+/*
+ * Input(s): passed from u-boot
+ *   r4 - Optional pointer to a board information structure.
+ *   r5 - Optional pointer to the physical starting address of the init RAM
+ *        disk.
+ *   r6 - Optional pointer to the physical ending address of the init RAM
+ *        disk.
+ *   r7 - Optional pointer to the physical starting address of any kernel
+ *        command-line parameters.
+ */
+/*
+ * First executable code - detected and jumped to by the ROM bootstrap
+ * if the code resides in flash (looks for "Nios" at offset 0x0c from
+ * the potential executable image).
+ */
+        __HEAD
+ENTRY(_start)
+        wrctl   status, r0              /* Disable interrupts */
+        /* Initialize all cache lines within the instruction cache */
+        movia   r1, NIOS2_ICACHE_SIZE
+        movui   r2, NIOS2_ICACHE_LINE_SIZE
+icache_init:
+        initi   r1
+        sub     r1, r1, r2
+        bgt     r1, r0, icache_init
+        br      1f
+        /*
+         * This is the default location for the exception handler. Code in jump
+         * to our handler
+         */
+ENTRY(exception_handler_hook)
+        movia   r24, inthandler
+        jmp     r24
+ENTRY(fast_handler)
+        nextpc et
+helper:
+        stw     r3, r3save - helper(et)
+        rdctl   r3 , pteaddr
+        srli    r3, r3, 12
+        slli    r3, r3, 2
+        movia   et, pgd_current
+        ldw     et, 0(et)
+        add     r3, et, r3
+        ldw     et, 0(r3)
+        rdctl   r3, pteaddr
+        andi    r3, r3, 0xfff
+        add     et, r3, et
+        ldw     et, 0(et)
+        wrctl   tlbacc, et
+        nextpc  et
+helper2:
+        ldw     r3, r3save - helper2(et)
+        subi    ea, ea, 4
+        eret
+r3save:
+        .word 0x0
+ENTRY(fast_handler_end)
+1:
+        /*
+         * After the instruction cache is initialized, the data cache must
+         * also be initialized.
+         */
+        movia   r1, NIOS2_DCACHE_SIZE
+        movui   r2, NIOS2_DCACHE_LINE_SIZE
+dcache_init:
+        initd   0(r1)
+        sub     r1, r1, r2
+        bgt     r1, r0, dcache_init
+        nextpc  r1                      /* Find out where we are */
+chkadr:
+        movia   r2, chkadr
+        beq     r1, r2,finish_move      /* We are running in RAM done */
+        addi    r1, r1,(_start - chkadr)        /* Source */
+        movia   r2, _start              /* Destination */
+        movia   r3, __bss_start         /* End of copy */
+loop_move:                              /* r1: src, r2: dest, r3: last dest */
+        ldw     r8, 0(r1)               /* load a word from [r1] */
+        stw     r8, 0(r2)               /* store a word to dest [r2] */
+        flushd  0(r2)                   /* Flush cache for safety */
+        addi    r1, r1, 4               /* inc the src addr */
+        addi    r2, r2, 4               /* inc the dest addr */
+        blt     r2, r3, loop_move
+        movia   r1, finish_move         /* VMA(_start)->l1 */
+        jmp     r1                      /* jmp to _start */
+finish_move:
+        /* Mask off all possible interrupts */
+        wrctl   ienable, r0
+        /* Clear .bss */
+        movia   r2, __bss_start
+        movia   r1, __bss_stop
+1:
+        stb     r0, 0(r2)
+        addi    r2, r2, 1
+        bne     r1, r2, 1b
+        movia   r1, init_thread_union   /* set stack at top of the task union */
+        addi    sp, r1, THREAD_SIZE
+        movia   r2, _current_thread     /* Remember current thread */
+        stw     r1, 0(r2)
+        movia   r1, nios2_boot_init     /* save args r4-r7 passed from u-boot */
+        callr   r1
+        movia   r1, start_kernel        /* call start_kernel as a subroutine */
+        callr   r1
+        /* If we return from start_kernel, break to the oci debugger and
+         * buggered we are.
+         */
+        break
+        /* End of startup code */
+.set at
diff --git a/arch/nios2/kernel/insnemu.S b/arch/nios2/kernel/insnemu.S
new file mode 100644
index 000000000000..1c6b651e770d
--- /dev/null
+++ b/arch/nios2/kernel/insnemu.S
@@ -0,0 +1,592 @@
+/*
+ *  Copyright (C) 2003-2013 Altera Corporation
+ *  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/linkage.h>
+#include <asm/entry.h>
+.set noat
+.set nobreak
+/*
+* Explicitly allow the use of r1 (the assembler temporary register)
+* within this code. This register is normally reserved for the use of
+* the compiler.
+*/
+ENTRY(instruction_trap)
+        ldw     r1, PT_R1(sp)           // Restore registers
+        ldw     r2, PT_R2(sp)
+        ldw     r3, PT_R3(sp)
+        ldw     r4, PT_R4(sp)
+        ldw     r5, PT_R5(sp)
+        ldw     r6, PT_R6(sp)
+        ldw     r7, PT_R7(sp)
+        ldw     r8, PT_R8(sp)
+        ldw     r9, PT_R9(sp)
+        ldw     r10, PT_R10(sp)
+        ldw     r11, PT_R11(sp)
+        ldw     r12, PT_R12(sp)
+        ldw     r13, PT_R13(sp)
+        ldw     r14, PT_R14(sp)
+        ldw     r15, PT_R15(sp)
+        ldw     ra, PT_RA(sp)
+        ldw     fp, PT_FP(sp)
+        ldw     gp, PT_GP(sp)
+        ldw     et, PT_ESTATUS(sp)
+        wrctl   estatus, et
+        ldw     ea, PT_EA(sp)
+        ldw     et, PT_SP(sp)           /* backup sp in et */
+        addi    sp, sp, PT_REGS_SIZE
+        /* INSTRUCTION EMULATION
+        *  ---------------------
+        *
+        * Nios II processors generate exceptions for unimplemented instructions.
+        * The routines below emulate these instructions.  Depending on the
+        * processor core, the only instructions that might need to be emulated
+        * are div, divu, mul, muli, mulxss, mulxsu, and mulxuu.
+        *
+        * The emulations match the instructions, except for the following
+        * limitations:
+        *
+        * 1) The emulation routines do not emulate the use of the exception
+        *    temporary register (et) as a source operand because the exception
+        *    handler already has modified it.
+        *
+        * 2) The routines do not emulate the use of the stack pointer (sp) or
+        *    the exception return address register (ea) as a destination because
+        *    modifying these registers crashes the exception handler or the
+        *    interrupted routine.
+        *
+        * Detailed Design
+        * ---------------
+        *
+        * The emulation routines expect the contents of integer registers r0-r31
+        * to be on the stack at addresses sp, 4(sp), 8(sp), ... 124(sp).  The
+        * routines retrieve source operands from the stack and modify the
+        * destination register's value on the stack prior to the end of the
+        * exception handler.  Then all registers except the destination register
+        * are restored to their previous values.
+        *
+        * The instruction that causes the exception is found at address -4(ea).
+        * The instruction's OP and OPX fields identify the operation to be
+        * performed.
+        *
+        * One instruction, muli, is an I-type instruction that is identified by
+        * an OP field of 0x24.
+        *
+        * muli   AAAAA,BBBBB,IIIIIIIIIIIIIIII,-0x24-
+        *           27    22                6      0    <-- LSB of field
+        *
+        * The remaining emulated instructions are R-type and have an OP field
+        * of 0x3a.  Their OPX fields identify them.
+        *
+        * R-type AAAAA,BBBBB,CCCCC,XXXXXX,NNNNN,-0x3a-
+        *           27    22    17     11     6      0  <-- LSB of field
+        *
+        *
+        * Opcode Encoding.  muli is identified by its OP value.  Then OPX & 0x02
+        * is used to differentiate between the division opcodes and the
+        * remaining multiplication opcodes.
+        *
+        * Instruction   OP      OPX    OPX & 0x02
+        * -----------   ----    ----   ----------
+        * muli          0x24
+        * divu          0x3a    0x24         0
+        * div           0x3a    0x25         0
+        * mul           0x3a    0x27      != 0
+        * mulxuu        0x3a    0x07      != 0
+        * mulxsu        0x3a    0x17      != 0
+        * mulxss        0x3a    0x1f      != 0
+        */
+        /*
+        * Save everything on the stack to make it easy for the emulation
+        * routines to retrieve the source register operands.
+        */
+        addi sp, sp, -128
+        stw zero, 0(sp) /* Save zero on stack to avoid special case for r0. */
+        stw r1, 4(sp)
+        stw r2,  8(sp)
+        stw r3, 12(sp)
+        stw r4, 16(sp)
+        stw r5, 20(sp)
+        stw r6, 24(sp)
+        stw r7, 28(sp)
+        stw r8, 32(sp)
+        stw r9, 36(sp)
+        stw r10, 40(sp)
+        stw r11, 44(sp)
+        stw r12, 48(sp)
+        stw r13, 52(sp)
+        stw r14, 56(sp)
+        stw r15, 60(sp)
+        stw r16, 64(sp)
+        stw r17, 68(sp)
+        stw r18, 72(sp)
+        stw r19, 76(sp)
+        stw r20, 80(sp)
+        stw r21, 84(sp)
+        stw r22, 88(sp)
+        stw r23, 92(sp)
+                /* Don't bother to save et.  It's already been changed. */
+        rdctl r5, estatus
+        stw r5,  100(sp)
+        stw gp, 104(sp)
+        stw et, 108(sp) /* et contains previous sp value. */
+        stw fp, 112(sp)
+        stw ea, 116(sp)
+        stw ra, 120(sp)
+        /*
+        * Split the instruction into its fields.  We need 4*A, 4*B, and 4*C as
+        * offsets to the stack pointer for access to the stored register values.
+        */
+        ldw r2,-4(ea)   /* r2 = AAAAA,BBBBB,IIIIIIIIIIIIIIII,PPPPPP */
+        roli r3, r2, 7  /* r3 = BBB,IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BB */
+        roli r4, r3, 3  /* r4 = IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB */
+        roli r5, r4, 2  /* r5 = IIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB,II */
+        srai r4, r4, 16 /* r4 = (sign-extended) IMM16 */
+        roli r6, r5, 5  /* r6 = XXXX,NNNNN,PPPPPP,AAAAA,BBBBB,CCCCC,XX */
+        andi r2, r2, 0x3f       /* r2 = 00000000000000000000000000,PPPPPP */
+        andi r3, r3, 0x7c       /* r3 = 0000000000000000000000000,AAAAA,00 */
+        andi r5, r5, 0x7c       /* r5 = 0000000000000000000000000,BBBBB,00 */
+        andi r6, r6, 0x7c       /* r6 = 0000000000000000000000000,CCCCC,00 */
+        /* Now
+        * r2 = OP
+        * r3 = 4*A
+        * r4 = IMM16 (sign extended)
+        * r5 = 4*B
+        * r6 = 4*C
+        */
+        /*
+        * Get the operands.
+        *
+        * It is necessary to check for muli because it uses an I-type
+        * instruction format, while the other instructions are have an R-type
+        * format.
+        *
+        *  Prepare for either multiplication or division loop.
+        *  They both loop 32 times.
+        */
+        movi r14, 32
+        add  r3, r3, sp         /* r3 = address of A-operand. */
+        ldw  r3, 0(r3)          /* r3 = A-operand. */
+        movi r7, 0x24           /* muli opcode (I-type instruction format) */
+        beq r2, r7, mul_immed /* muli doesn't use the B register as a source */
+        add  r5, r5, sp         /* r5 = address of B-operand. */
+        ldw  r5, 0(r5)          /* r5 = B-operand. */
+                                /* r4 = SSSSSSSSSSSSSSSS,-----IMM16------ */
+                                /* IMM16 not needed, align OPX portion */
+                                /* r4 = SSSSSSSSSSSSSSSS,CCCCC,-OPX--,00000 */
+        srli r4, r4, 5          /* r4 = 00000,SSSSSSSSSSSSSSSS,CCCCC,-OPX-- */
+        andi r4, r4, 0x3f       /* r4 = 00000000000000000000000000,-OPX-- */
+        /* Now
+        * r2 = OP
+        * r3 = src1
+        * r5 = src2
+        * r4 = OPX (no longer can be muli)
+        * r6 = 4*C
+        */
+        /*
+        *  Multiply or Divide?
+        */
+        andi r7, r4, 0x02       /* For R-type multiply instructions,
+                                   OPX & 0x02 != 0 */
+        bne r7, zero, multiply
+        /* DIVISION
+        *
+        * Divide an unsigned dividend by an unsigned divisor using
+        * a shift-and-subtract algorithm.  The example below shows
+        * 43 div 7 = 6 for 8-bit integers.  This classic algorithm uses a
+        * single register to store both the dividend and the quotient,
+        * allowing both values to be shifted with a single instruction.
+        *
+        *                               remainder dividend:quotient
+        *                               --------- -----------------
+        *   initialize                   00000000     00101011:
+        *   shift                        00000000     0101011:_
+        *   remainder >= divisor? no     00000000     0101011:0
+        *   shift                        00000000     101011:0_
+        *   remainder >= divisor? no     00000000     101011:00
+        *   shift                        00000001     01011:00_
+        *   remainder >= divisor? no     00000001     01011:000
+        *   shift                        00000010     1011:000_
+        *   remainder >= divisor? no     00000010     1011:0000
+        *   shift                        00000101     011:0000_
+        *   remainder >= divisor? no     00000101     011:00000
+        *   shift                        00001010     11:00000_
+        *   remainder >= divisor? yes    00001010     11:000001
+        *       remainder -= divisor   - 00000111
+        *                              ----------
+        *                                00000011     11:000001
+        *   shift                        00000111     1:000001_
+        *   remainder >= divisor? yes    00000111     1:0000011
+        *       remainder -= divisor   - 00000111
+        *                              ----------
+        *                                00000000     1:0000011
+        *   shift                        00000001     :0000011_
+        *   remainder >= divisor? no     00000001     :00000110
+        *
+        * The quotient is 00000110.
+        */
+divide:
+        /*
+        *  Prepare for division by assuming the result
+        *  is unsigned, and storing its "sign" as 0.
+        */
+        movi r17, 0
+        /* Which division opcode? */
+        xori r7, r4, 0x25               /* OPX of div */
+        bne r7, zero, unsigned_division
+        /*
+        *  OPX is div.  Determine and store the sign of the quotient.
+        *  Then take the absolute value of both operands.
+        */
+        xor r17, r3, r5         /* MSB contains sign of quotient */
+        bge r3,zero,dividend_is_nonnegative
+        sub r3, zero, r3        /* -r3 */
+dividend_is_nonnegative:
+        bge r5, zero, divisor_is_nonnegative
+        sub r5, zero, r5        /* -r5 */
+divisor_is_nonnegative:
+unsigned_division:
+        /* Initialize the unsigned-division loop. */
+        movi r13, 0     /* remainder = 0 */
+        /* Now
+        * r3 = dividend : quotient
+        * r4 = 0x25 for div, 0x24 for divu
+        * r5 = divisor
+        * r13 = remainder
+        * r14 = loop counter (already initialized to 32)
+        * r17 = MSB contains sign of quotient
+        */
+        /*
+        *   for (count = 32; count > 0; --count)
+        *   {
+        */
+divide_loop:
+        /*
+        *       Division:
+        *
+        *       (remainder:dividend:quotient) <<= 1;
+        */
+        slli r13, r13, 1
+        cmplt r7, r3, zero      /* r7 = MSB of r3 */
+        or r13, r13, r7
+        slli r3, r3, 1
+        /*
+        *       if (remainder >= divisor)
+        *       {
+        *           set LSB of quotient
+        *           remainder -= divisor;
+        *       }
+        */
+        bltu r13, r5, div_skip
+        ori r3, r3, 1
+        sub r13, r13, r5
+div_skip:
+        /*
+        *   }
+        */
+        subi r14, r14, 1
+        bne r14, zero, divide_loop
+        /* Now
+        * r3 = quotient
+        * r4 = 0x25 for div, 0x24 for divu
+        * r6 = 4*C
+        * r17 = MSB contains sign of quotient
+        */
+        /*
+        *  Conditionally negate signed quotient.  If quotient is unsigned,
+        *  the sign already is initialized to 0.
+        */
+        bge r17, zero, quotient_is_nonnegative
+        sub r3, zero, r3                /* -r3 */
+        quotient_is_nonnegative:
+        /*
+        *  Final quotient is in r3.
+        */
+        add r6, r6, sp
+        stw r3, 0(r6)   /* write quotient to stack */
+        br restore_registers
+        /* MULTIPLICATION
+        *
+        * A "product" is the number that one gets by summing a "multiplicand"
+        * several times.  The "multiplier" specifies the number of copies of the
+        * multiplicand that are summed.
+        *
+        * Actual multiplication algorithms don't use repeated addition, however.
+        * Shift-and-add algorithms get the same answer as repeated addition, and
+        * they are faster.  To compute the lower half of a product (pppp below)
+        * one shifts the product left before adding in each of the partial
+        * products (a * mmmm) through (d * mmmm).
+        *
+        * To compute the upper half of a product (PPPP below), one adds in the
+        * partial products (d * mmmm) through (a * mmmm), each time following
+        * the add by a right shift of the product.
+        *
+        *     mmmm
+        *   * abcd
+        *   ------
+        *     ####  = d * mmmm
+        *    ####   = c * mmmm
+        *   ####    = b * mmmm
+        *  ####     = a * mmmm
+        * --------
+        * PPPPpppp
+        *
+        * The example above shows 4 partial products.  Computing actual Nios II
+        * products requires 32 partials.
+        *
+        * It is possible to compute the result of mulxsu from the result of
+        * mulxuu because the only difference between the results of these two
+        * opcodes is the value of the partial product associated with the sign
+        * bit of rA.
+        *
+        *   mulxsu = mulxuu - (rA < 0) ? rB : 0;
+        *
+        * It is possible to compute the result of mulxss from the result of
+        * mulxsu because the only difference between the results of these two
+        * opcodes is the value of the partial product associated with the sign
+        * bit of rB.
+        *
+        *   mulxss = mulxsu - (rB < 0) ? rA : 0;
+        *
+        */
+mul_immed:
+        /* Opcode is muli.  Change it into mul for remainder of algorithm. */
+        mov r6, r5              /* Field B is dest register, not field C. */
+        mov r5, r4              /* Field IMM16 is src2, not field B. */
+        movi r4, 0x27           /* OPX of mul is 0x27 */
+multiply:
+        /* Initialize the multiplication loop. */
+        movi r9, 0      /* mul_product    = 0 */
+        movi r10, 0     /* mulxuu_product = 0 */
+        mov r11, r5     /* save original multiplier for mulxsu and mulxss */
+        mov r12, r5     /* mulxuu_multiplier (will be shifted) */
+        movi r16, 1     /* used to create "rori B,A,1" from "ror B,A,r16" */
+        /* Now
+        * r3 = multiplicand
+        * r5 = mul_multiplier
+        * r6 = 4 * dest_register (used later as offset to sp)
+        * r7 = temp
+        * r9 = mul_product
+        * r10 = mulxuu_product
+        * r11 = original multiplier
+        * r12 = mulxuu_multiplier
+        * r14 = loop counter (already initialized)
+        * r16 = 1
+        */
+        /*
+        *   for (count = 32; count > 0; --count)
+        *   {
+        */
+multiply_loop:
+        /*
+        *       mul_product <<= 1;
+        *       lsb = multiplier & 1;
+        */
+        slli r9, r9, 1
+        andi r7, r12, 1
+        /*
+        *       if (lsb == 1)
+        *       {
+        *           mulxuu_product += multiplicand;
+        *       }
+        */
+        beq r7, zero, mulx_skip
+        add r10, r10, r3
+        cmpltu r7, r10, r3 /* Save the carry from the MSB of mulxuu_product. */
+        ror r7, r7, r16 /* r7 = 0x80000000 on carry, or else 0x00000000 */
+mulx_skip:
+        /*
+        *       if (MSB of mul_multiplier == 1)
+        *       {
+        *           mul_product += multiplicand;
+        *       }
+        */
+        bge r5, zero, mul_skip
+        add r9, r9, r3
+mul_skip:
+        /*
+        *       mulxuu_product >>= 1;           logical shift
+        *       mul_multiplier <<= 1;           done with MSB
+        *       mulx_multiplier >>= 1;          done with LSB
+        */
+        srli r10, r10, 1
+        or r10, r10, r7         /* OR in the saved carry bit. */
+        slli r5, r5, 1
+        srli r12, r12, 1
+        /*
+        *   }
+        */
+        subi r14, r14, 1
+        bne r14, zero, multiply_loop
+        /*
+        *  Multiply emulation loop done.
+        */
+        /* Now
+        * r3 = multiplicand
+        * r4 = OPX
+        * r6 = 4 * dest_register (used later as offset to sp)
+        * r7 = temp
+        * r9 = mul_product
+        * r10 = mulxuu_product
+        * r11 = original multiplier
+        */
+        /* Calculate address for result from 4 * dest_register */
+        add r6, r6, sp
+        /*
+        * Select/compute the result based on OPX.
+        */
+        /* OPX == mul?  Then store. */
+        xori r7, r4, 0x27
+        beq r7, zero, store_product
+        /* It's one of the mulx.. opcodes.  Move over the result. */
+        mov r9, r10
+        /* OPX == mulxuu?  Then store. */
+        xori r7, r4, 0x07
+        beq r7, zero, store_product
+        /* Compute mulxsu
+         *
+         * mulxsu = mulxuu - (rA < 0) ? rB : 0;
+         */
+        bge r3, zero, mulxsu_skip
+        sub r9, r9, r11
+mulxsu_skip:
+        /* OPX == mulxsu?  Then store. */
+        xori r7, r4, 0x17
+        beq r7, zero, store_product
+        /* Compute mulxss
+         *
+         * mulxss = mulxsu - (rB < 0) ? rA : 0;
+         */
+        bge r11,zero,mulxss_skip
+        sub r9, r9, r3
+mulxss_skip:
+        /* At this point, assume that OPX is mulxss, so store*/
+store_product:
+        stw r9, 0(r6)
+restore_registers:
+                        /* No need to restore r0. */
+        ldw r5, 100(sp)
+        wrctl estatus, r5
+        ldw r1, 4(sp)
+        ldw r2, 8(sp)
+        ldw r3, 12(sp)
+        ldw r4, 16(sp)
+        ldw r5, 20(sp)
+        ldw r6, 24(sp)
+        ldw r7, 28(sp)
+        ldw r8, 32(sp)
+        ldw r9, 36(sp)
+        ldw r10, 40(sp)
+        ldw r11, 44(sp)
+        ldw r12, 48(sp)
+        ldw r13, 52(sp)
+        ldw r14, 56(sp)
+        ldw r15, 60(sp)
+        ldw r16, 64(sp)
+        ldw r17, 68(sp)
+        ldw r18, 72(sp)
+        ldw r19, 76(sp)
+        ldw r20, 80(sp)
+        ldw r21, 84(sp)
+        ldw r22, 88(sp)
+        ldw r23, 92(sp)
+                        /* Does not need to restore et */
+        ldw gp, 104(sp)
+        ldw fp, 112(sp)
+        ldw ea, 116(sp)
+        ldw ra, 120(sp)
+        ldw sp, 108(sp) /* last restore sp */
+        eret
+.set at
+.set break
diff --git a/arch/nios2/kernel/irq.c b/arch/nios2/kernel/irq.c
new file mode 100644
index 000000000000..f5b74ae69b5b
--- /dev/null
+++ b/arch/nios2/kernel/irq.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2008 Thomas Chou <thomas@wytron.com.tw>
+ *
+ * based on irq.c from m68k which is:
+ *
+ * Copyright (C) 2007 Greg Ungerer <gerg@snapgear.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/of.h>
+static u32 ienable;
+asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs)
+{
+        struct pt_regs *oldregs = set_irq_regs(regs);
+        int irq;
+        irq_enter();
+        irq = irq_find_mapping(NULL, hwirq);
+        generic_handle_irq(irq);
+        irq_exit();
+        set_irq_regs(oldregs);
+}
+static void chip_unmask(struct irq_data *d)
+{
+        ienable |= (1 << d->hwirq);
+        WRCTL(CTL_IENABLE, ienable);
+}
+static void chip_mask(struct irq_data *d)
+{
+        ienable &= ~(1 << d->hwirq);
+        WRCTL(CTL_IENABLE, ienable);
+}
+static struct irq_chip m_irq_chip = {
+        .name           = "NIOS2-INTC",
+        .irq_unmask     = chip_unmask,
+        .irq_mask       = chip_mask,
+};
+static int irq_map(struct irq_domain *h, unsigned int virq,
+                                irq_hw_number_t hw_irq_num)
+{
+        irq_set_chip_and_handler(virq, &m_irq_chip, handle_level_irq);
+        return 0;
+}
+static struct irq_domain_ops irq_ops = {
+        .map    = irq_map,
+        .xlate  = irq_domain_xlate_onecell,
+};
+void __init init_IRQ(void)
+{
+        struct irq_domain *domain;
+        struct device_node *node;
+        node = of_find_compatible_node(NULL, NULL, "altr,nios2-1.0");
+        if (!node)
+                node = of_find_compatible_node(NULL, NULL, "altr,nios2-1.1");
+        BUG_ON(!node);
+        domain = irq_domain_add_linear(node, NIOS2_CPU_NR_IRQS, &irq_ops, NULL);
+        BUG_ON(!domain);
+        irq_set_default_host(domain);
+        of_node_put(node);
+        /* Load the initial ienable value */
+        ienable = RDCTL(CTL_IENABLE);
+}
diff --git a/arch/nios2/kernel/misaligned.c b/arch/nios2/kernel/misaligned.c
new file mode 100644
index 000000000000..4e5907a0cabe
--- /dev/null
+++ b/arch/nios2/kernel/misaligned.c
@@ -0,0 +1,256 @@
+/*
+ *  linux/arch/nios2/kernel/misaligned.c
+ *
+ *  basic emulation for mis-aligned accesses on the NIOS II cpu
+ *  modelled after the version for arm in arm/alignment.c
+ *
+ *  Brad Parker <brad@heeltoe.com>
+ *  Copyright (C) 2010 Ambient Corporation
+ *  Copyright (c) 2010 Altera Corporation, San Jose, California, USA.
+ *  Copyright (c) 2010 Arrow Electronics, Inc.
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file COPYING in the main directory of
+ * this archive for more details.
+ */
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/proc_fs.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/uaccess.h>
+#include <linux/seq_file.h>
+#include <asm/traps.h>
+#include <asm/unaligned.h>
+/* instructions we emulate */
+#define INST_LDHU       0x0b
+#define INST_STH        0x0d
+#define INST_LDH        0x0f
+#define INST_STW        0x15
+#define INST_LDW        0x17
+static unsigned long ma_user, ma_kern, ma_skipped, ma_half, ma_word;
+static unsigned int ma_usermode;
+#define UM_WARN         0x01
+#define UM_FIXUP        0x02
+#define UM_SIGNAL       0x04
+#define KM_WARN         0x08
+/* see arch/nios2/include/asm/ptrace.h */
+static u8 sys_stack_frame_reg_offset[] = {
+        /* struct pt_regs */
+        8, 9, 10, 11, 12, 13, 14, 15, 1, 2, 3, 4, 5, 6, 7, 0,
+        /* struct switch_stack */
+        16, 17, 18, 19, 20, 21, 22, 23, 0, 0, 0, 0, 0, 0, 0, 0
+};
+static int reg_offsets[32];
+static inline u32 get_reg_val(struct pt_regs *fp, int reg)
+{
+        u8 *p = ((u8 *)fp) + reg_offsets[reg];
+        return *(u32 *)p;
+}
+static inline void put_reg_val(struct pt_regs *fp, int reg, u32 val)
+{
+        u8 *p = ((u8 *)fp) + reg_offsets[reg];
+        *(u32 *)p = val;
+}
+/*
+ * (mis)alignment handler
+ */
+asmlinkage void handle_unaligned_c(struct pt_regs *fp, int cause)
+{
+        u32 isn, addr, val;
+        int in_kernel;
+        u8 a, b, d0, d1, d2, d3;
+        u16 imm16;
+        unsigned int fault;
+        /* back up one instruction */
+        fp->ea -= 4;
+        if (fixup_exception(fp)) {
+                ma_skipped++;
+                return;
+        }
+        in_kernel = !user_mode(fp);
+        isn = *(unsigned long *)(fp->ea);
+        fault = 0;
+        /* do fixup if in kernel or mode turned on */
+        if (in_kernel || (ma_usermode & UM_FIXUP)) {
+                /* decompose instruction */
+                a = (isn >> 27) & 0x1f;
+                b = (isn >> 22) & 0x1f;
+                imm16 = (isn >> 6) & 0xffff;
+                addr = get_reg_val(fp, a) + imm16;
+                /* do fixup to saved registers */
+                switch (isn & 0x3f) {
+                case INST_LDHU:
+                        fault |= __get_user(d0, (u8 *)(addr+0));
+                        fault |= __get_user(d1, (u8 *)(addr+1));
+                        val = (d1 << 8) | d0;
+                        put_reg_val(fp, b, val);
+                        ma_half++;
+                        break;
+                case INST_STH:
+                        val = get_reg_val(fp, b);
+                        d1 = val >> 8;
+                        d0 = val >> 0;
+                        pr_debug("sth: ra=%d (%08x) rb=%d (%08x), imm16 %04x addr %08x val %08x\n",
+                                a, get_reg_val(fp, a),
+                                b, get_reg_val(fp, b),
+                                imm16, addr, val);
+                        if (in_kernel) {
+                                *(u8 *)(addr+0) = d0;
+                                *(u8 *)(addr+1) = d1;
+                        } else {
+                                fault |= __put_user(d0, (u8 *)(addr+0));
+                                fault |= __put_user(d1, (u8 *)(addr+1));
+                        }
+                        ma_half++;
+                        break;
+                case INST_LDH:
+                        fault |= __get_user(d0, (u8 *)(addr+0));
+                        fault |= __get_user(d1, (u8 *)(addr+1));
+                        val = (short)((d1 << 8) | d0);
+                        put_reg_val(fp, b, val);
+                        ma_half++;
+                        break;
+                case INST_STW:
+                        val = get_reg_val(fp, b);
+                        d3 = val >> 24;
+                        d2 = val >> 16;
+                        d1 = val >> 8;
+                        d0 = val >> 0;
+                        if (in_kernel) {
+                                *(u8 *)(addr+0) = d0;
+                                *(u8 *)(addr+1) = d1;
+                                *(u8 *)(addr+2) = d2;
+                                *(u8 *)(addr+3) = d3;
+                        } else {
+                                fault |= __put_user(d0, (u8 *)(addr+0));
+                                fault |= __put_user(d1, (u8 *)(addr+1));
+                                fault |= __put_user(d2, (u8 *)(addr+2));
+                                fault |= __put_user(d3, (u8 *)(addr+3));
+                        }
+                        ma_word++;
+                        break;
+                case INST_LDW:
+                        fault |= __get_user(d0, (u8 *)(addr+0));
+                        fault |= __get_user(d1, (u8 *)(addr+1));
+                        fault |= __get_user(d2, (u8 *)(addr+2));
+                        fault |= __get_user(d3, (u8 *)(addr+3));
+                        val = (d3 << 24) | (d2 << 16) | (d1 << 8) | d0;
+                        put_reg_val(fp, b, val);
+                        ma_word++;
+                        break;
+                }
+        }
+        addr = RDCTL(CTL_BADADDR);
+        cause >>= 2;
+        if (fault) {
+                if (in_kernel) {
+                        pr_err("fault during kernel misaligned fixup @ %#lx; addr 0x%08x; isn=0x%08x\n",
+                                fp->ea, (unsigned int)addr,
+                                (unsigned int)isn);
+                } else {
+                        pr_err("fault during user misaligned fixup @ %#lx; isn=%08x addr=0x%08x sp=0x%08lx pid=%d\n",
+                                fp->ea,
+                                (unsigned int)isn, addr, fp->sp,
+                                current->pid);
+                        _exception(SIGSEGV, fp, SEGV_MAPERR, fp->ea);
+                        return;
+                }
+        }
+        /*
+         * kernel mode -
+         *  note exception and skip bad instruction (return)
+         */
+        if (in_kernel) {
+                ma_kern++;
+                fp->ea += 4;
+                if (ma_usermode & KM_WARN) {
+                        pr_err("kernel unaligned access @ %#lx; BADADDR 0x%08x; cause=%d, isn=0x%08x\n",
+                                fp->ea,
+                                (unsigned int)addr, cause,
+                                (unsigned int)isn);
+                        /* show_regs(fp); */
+                }
+                return;
+        }
+        ma_user++;
+        /*
+         * user mode -
+         *  possibly warn,
+         *  possibly send SIGBUS signal to process
+         */
+        if (ma_usermode & UM_WARN) {
+                pr_err("user unaligned access @ %#lx; isn=0x%08lx ea=0x%08lx ra=0x%08lx sp=0x%08lx\n",
+                        (unsigned long)addr, (unsigned long)isn,
+                        fp->ea, fp->ra, fp->sp);
+        }
+        if (ma_usermode & UM_SIGNAL)
+                _exception(SIGBUS, fp, BUS_ADRALN, fp->ea);
+        else
+                fp->ea += 4;    /* else advance */
+}
+static void __init misaligned_calc_reg_offsets(void)
+{
+        int i, r, offset;
+        /* pre-calc offsets of registers on sys call stack frame */
+        offset = 0;
+        /* struct pt_regs */
+        for (i = 0; i < 16; i++) {
+                r = sys_stack_frame_reg_offset[i];
+                reg_offsets[r] = offset;
+                offset += 4;
+        }
+        /* struct switch_stack */
+        offset = -sizeof(struct switch_stack);
+        for (i = 16; i < 32; i++) {
+                r = sys_stack_frame_reg_offset[i];
+                reg_offsets[r] = offset;
+                offset += 4;
+        }
+}
+static int __init misaligned_init(void)
+{
+        /* default mode - silent fix */
+        ma_usermode = UM_FIXUP | KM_WARN;
+        misaligned_calc_reg_offsets();
+        return 0;
+}
+fs_initcall(misaligned_init);
diff --git a/arch/nios2/kernel/module.c b/arch/nios2/kernel/module.c
new file mode 100644
index 000000000000..cc924a38f22a
--- /dev/null
+++ b/arch/nios2/kernel/module.c
@@ -0,0 +1,138 @@
+/*
+ * Kernel module support for Nios II.
+ *
+ * Copyright (C) 2004 Microtronix Datacom Ltd.
+ *   Written by Wentao Xu <xuwentao@microtronix.com>
+ * Copyright (C) 2001, 2003 Rusty Russell
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file COPYING in the main directory of this
+ * archive for more details.
+ */
+#include <linux/moduleloader.h>
+#include <linux/elf.h>
+#include <linux/mm.h>
+#include <linux/vmalloc.h>
+#include <linux/slab.h>
+#include <linux/fs.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <asm/pgtable.h>
+#include <asm/cacheflush.h>
+/*
+ * Modules should NOT be allocated with kmalloc for (obvious) reasons.
+ * But we do it for now to avoid relocation issues. CALL26/PCREL26 cannot reach
+ * from 0x80000000 (vmalloc area) to 0xc00000000 (kernel) (kmalloc returns
+ * addresses in 0xc0000000)
+ */
+void *module_alloc(unsigned long size)
+{
+        if (size == 0)
+                return NULL;
+        return kmalloc(size, GFP_KERNEL);
+}
+/* Free memory returned from module_alloc */
+void module_free(struct module *mod, void *module_region)
+{
+        kfree(module_region);
+}
+int apply_relocate_add(Elf32_Shdr *sechdrs, const char *strtab,
+                        unsigned int symindex, unsigned int relsec,
+                        struct module *mod)
+{
+        unsigned int i;
+        Elf32_Rela *rela = (void *)sechdrs[relsec].sh_addr;
+        pr_debug("Applying relocate section %u to %u\n", relsec,
+                 sechdrs[relsec].sh_info);
+        for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rela); i++) {
+                /* This is where to make the change */
+                uint32_t word;
+                uint32_t *loc
+                        = ((void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
+                           + rela[i].r_offset);
+                /* This is the symbol it is referring to.  Note that all
+                   undefined symbols have been resolved.  */
+                Elf32_Sym *sym
+                        = ((Elf32_Sym *)sechdrs[symindex].sh_addr
+                                + ELF32_R_SYM(rela[i].r_info));
+                uint32_t v = sym->st_value + rela[i].r_addend;
+                pr_debug("reltype %d 0x%x name:<%s>\n",
+                        ELF32_R_TYPE(rela[i].r_info),
+                        rela[i].r_offset, strtab + sym->st_name);
+                switch (ELF32_R_TYPE(rela[i].r_info)) {
+                case R_NIOS2_NONE:
+                        break;
+                case R_NIOS2_BFD_RELOC_32:
+                        *loc += v;
+                        break;
+                case R_NIOS2_PCREL16:
+                        v -= (uint32_t)loc + 4;
+                        if ((int32_t)v > 0x7fff ||
+                                (int32_t)v < -(int32_t)0x8000) {
+                                pr_err("module %s: relocation overflow\n",
+                                        mod->name);
+                                return -ENOEXEC;
+                        }
+                        word = *loc;
+                        *loc = ((((word >> 22) << 16) | (v & 0xffff)) << 6) |
+                                (word & 0x3f);
+                        break;
+                case R_NIOS2_CALL26:
+                        if (v & 3) {
+                                pr_err("module %s: dangerous relocation\n",
+                                        mod->name);
+                                return -ENOEXEC;
+                        }
+                        if ((v >> 28) != ((uint32_t)loc >> 28)) {
+                                pr_err("module %s: relocation overflow\n",
+                                        mod->name);
+                                return -ENOEXEC;
+                        }
+                        *loc = (*loc & 0x3f) | ((v >> 2) << 6);
+                        break;
+                case R_NIOS2_HI16:
+                        word = *loc;
+                        *loc = ((((word >> 22) << 16) |
+                                ((v >> 16) & 0xffff)) << 6) | (word & 0x3f);
+                        break;
+                case R_NIOS2_LO16:
+                        word = *loc;
+                        *loc = ((((word >> 22) << 16) | (v & 0xffff)) << 6) |
+                                        (word & 0x3f);
+                        break;
+                case R_NIOS2_HIADJ16:
+                        {
+                                Elf32_Addr word2;
+                                word = *loc;
+                                word2 = ((v >> 16) + ((v >> 15) & 1)) & 0xffff;
+                                *loc = ((((word >> 22) << 16) | word2) << 6) |
+                                                (word & 0x3f);
+                        }
+                        break;
+                default:
+                        pr_err("module %s: Unknown reloc: %u\n",
+                                mod->name, ELF32_R_TYPE(rela[i].r_info));
+                        return -ENOEXEC;
+                }
+        }
+        return 0;
+}
+int module_finalize(const Elf_Ehdr *hdr, const Elf_Shdr *sechdrs,
+                        struct module *me)
+{
+        flush_cache_all();
+        return 0;
+}
diff --git a/arch/nios2/kernel/nios2_ksyms.c b/arch/nios2/kernel/nios2_ksyms.c
new file mode 100644
index 000000000000..bf2f55d10a4d
--- /dev/null
+++ b/arch/nios2/kernel/nios2_ksyms.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2004 Microtronix Datacom Ltd
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file COPYING in the main directory of this
+ * archive for more details.
+ */
+#include <linux/export.h>
+#include <linux/string.h>
+/* string functions */
+EXPORT_SYMBOL(memcpy);
+EXPORT_SYMBOL(memset);
+EXPORT_SYMBOL(memmove);
+/*
+ * libgcc functions - functions that are used internally by the
+ * compiler...  (prototypes are not correct though, but that
+ * doesn't really matter since they're not versioned).
+ */
+#define DECLARE_EXPORT(name)    extern void name(void); EXPORT_SYMBOL(name)
+DECLARE_EXPORT(__gcc_bcmp);
+DECLARE_EXPORT(__divsi3);
+DECLARE_EXPORT(__moddi3);
+DECLARE_EXPORT(__modsi3);
+DECLARE_EXPORT(__udivmoddi4);
+DECLARE_EXPORT(__udivsi3);
+DECLARE_EXPORT(__umoddi3);
+DECLARE_EXPORT(__umodsi3);
+DECLARE_EXPORT(__muldi3);
diff --git a/arch/nios2/kernel/process.c b/arch/nios2/kernel/process.c
new file mode 100644
index 000000000000..0e075b5ad2a5
--- /dev/null
+++ b/arch/nios2/kernel/process.c
@@ -0,0 +1,258 @@
+/*
+ * Architecture-dependent parts of process handling.
+ *
+ * Copyright (C) 2013 Altera Corporation
+ * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2009 Wind River Systems Inc
+ *   Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
+ * Copyright (C) 2004 Microtronix Datacom Ltd
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/export.h>
+#include <linux/sched.h>
+#include <linux/tick.h>
+#include <linux/uaccess.h>
+#include <asm/unistd.h>
+#include <asm/traps.h>
+#include <asm/cpuinfo.h>
+asmlinkage void ret_from_fork(void);
+asmlinkage void ret_from_kernel_thread(void);
+void (*pm_power_off)(void) = NULL;
+EXPORT_SYMBOL(pm_power_off);
+void arch_cpu_idle(void)
+{
+        local_irq_enable();
+}
+/*
+ * The development boards have no way to pull a board reset. Just jump to the
+ * cpu reset address and let the boot loader or the code in head.S take care of
+ * resetting peripherals.
+ */
+void machine_restart(char *__unused)
+{
+        pr_notice("Machine restart (%08x)...\n", cpuinfo.reset_addr);
+        local_irq_disable();
+        __asm__ __volatile__ (
+        "jmp    %0\n\t"
+        :
+        : "r" (cpuinfo.reset_addr)
+        : "r4");
+}
+void machine_halt(void)
+{
+        pr_notice("Machine halt...\n");
+        local_irq_disable();
+        for (;;)
+                ;
+}
+/*
+ * There is no way to power off the development boards. So just spin for now. If
+ * we ever have a way of resetting a board using a GPIO we should add that here.
+ */
+void machine_power_off(void)
+{
+        pr_notice("Machine power off...\n");
+        local_irq_disable();
+        for (;;)
+                ;
+}
+void show_regs(struct pt_regs *regs)
+{
+        pr_notice("\n");
+        show_regs_print_info(KERN_DEFAULT);
+        pr_notice("r1: %08lx r2: %08lx r3: %08lx r4: %08lx\n",
+                regs->r1,  regs->r2,  regs->r3,  regs->r4);
+        pr_notice("r5: %08lx r6: %08lx r7: %08lx r8: %08lx\n",
+                regs->r5,  regs->r6,  regs->r7,  regs->r8);
+        pr_notice("r9: %08lx r10: %08lx r11: %08lx r12: %08lx\n",
+                regs->r9,  regs->r10, regs->r11, regs->r12);
+        pr_notice("r13: %08lx r14: %08lx r15: %08lx\n",
+                regs->r13, regs->r14, regs->r15);
+        pr_notice("ra: %08lx fp:  %08lx sp: %08lx gp: %08lx\n",
+                regs->ra,  regs->fp,  regs->sp,  regs->gp);
+        pr_notice("ea: %08lx estatus: %08lx\n",
+                regs->ea,  regs->estatus);
+}
+void flush_thread(void)
+{
+        set_fs(USER_DS);
+}
+int copy_thread(unsigned long clone_flags,
+                unsigned long usp, unsigned long arg, struct task_struct *p)
+{
+        struct pt_regs *childregs = task_pt_regs(p);
+        struct pt_regs *regs;
+        struct switch_stack *stack;
+        struct switch_stack *childstack =
+                ((struct switch_stack *)childregs) - 1;
+        if (unlikely(p->flags & PF_KTHREAD)) {
+                memset(childstack, 0,
+                        sizeof(struct switch_stack) + sizeof(struct pt_regs));
+                childstack->r16 = usp;          /* fn */
+                childstack->r17 = arg;
+                childstack->ra = (unsigned long) ret_from_kernel_thread;
+                childregs->estatus = STATUS_PIE;
+                childregs->sp = (unsigned long) childstack;
+                p->thread.ksp = (unsigned long) childstack;
+                p->thread.kregs = childregs;
+                return 0;
+        }
+        regs = current_pt_regs();
+        *childregs = *regs;
+        childregs->r2 = 0;      /* Set the return value for the child. */
+        childregs->r7 = 0;
+        stack = ((struct switch_stack *) regs) - 1;
+        *childstack = *stack;
+        childstack->ra = (unsigned long)ret_from_fork;
+        p->thread.kregs = childregs;
+        p->thread.ksp = (unsigned long) childstack;
+        if (usp)
+                childregs->sp = usp;
+        /* Initialize tls register. */
+        if (clone_flags & CLONE_SETTLS)
+                childstack->r23 = regs->r8;
+        return 0;
+}
+/*
+ *      Generic dumping code. Used for panic and debug.
+ */
+void dump(struct pt_regs *fp)
+{
+        unsigned long   *sp;
+        unsigned char   *tp;
+        int             i;
+        pr_emerg("\nCURRENT PROCESS:\n\n");
+        pr_emerg("COMM=%s PID=%d\n", current->comm, current->pid);
+        if (current->mm) {
+                pr_emerg("TEXT=%08x-%08x DATA=%08x-%08x BSS=%08x-%08x\n",
+                        (int) current->mm->start_code,
+                        (int) current->mm->end_code,
+                        (int) current->mm->start_data,
+                        (int) current->mm->end_data,
+                        (int) current->mm->end_data,
+                        (int) current->mm->brk);
+                pr_emerg("USER-STACK=%08x  KERNEL-STACK=%08x\n\n",
+                        (int) current->mm->start_stack,
+                        (int)(((unsigned long) current) + THREAD_SIZE));
+        }
+        pr_emerg("PC: %08lx\n", fp->ea);
+        pr_emerg("SR: %08lx    SP: %08lx\n",
+                (long) fp->estatus, (long) fp);
+        pr_emerg("r1: %08lx    r2: %08lx    r3: %08lx\n",
+                fp->r1, fp->r2, fp->r3);
+        pr_emerg("r4: %08lx    r5: %08lx    r6: %08lx    r7: %08lx\n",
+                fp->r4, fp->r5, fp->r6, fp->r7);
+        pr_emerg("r8: %08lx    r9: %08lx    r10: %08lx    r11: %08lx\n",
+                fp->r8, fp->r9, fp->r10, fp->r11);
+        pr_emerg("r12: %08lx  r13: %08lx    r14: %08lx    r15: %08lx\n",
+                fp->r12, fp->r13, fp->r14, fp->r15);
+        pr_emerg("or2: %08lx   ra: %08lx     fp: %08lx    sp: %08lx\n",
+                fp->orig_r2, fp->ra, fp->fp, fp->sp);
+        pr_emerg("\nUSP: %08x   TRAPFRAME: %08x\n",
+                (unsigned int) fp->sp, (unsigned int) fp);
+        pr_emerg("\nCODE:");
+        tp = ((unsigned char *) fp->ea) - 0x20;
+        for (sp = (unsigned long *) tp, i = 0; (i < 0x40);  i += 4) {
+                if ((i % 0x10) == 0)
+                        pr_emerg("\n%08x: ", (int) (tp + i));
+                pr_emerg("%08x ", (int) *sp++);
+        }
+        pr_emerg("\n");
+        pr_emerg("\nKERNEL STACK:");
+        tp = ((unsigned char *) fp) - 0x40;
+        for (sp = (unsigned long *) tp, i = 0; (i < 0xc0); i += 4) {
+                if ((i % 0x10) == 0)
+                        pr_emerg("\n%08x: ", (int) (tp + i));
+                pr_emerg("%08x ", (int) *sp++);
+        }
+        pr_emerg("\n");
+        pr_emerg("\n");
+        pr_emerg("\nUSER STACK:");
+        tp = (unsigned char *) (fp->sp - 0x10);
+        for (sp = (unsigned long *) tp, i = 0; (i < 0x80); i += 4) {
+                if ((i % 0x10) == 0)
+                        pr_emerg("\n%08x: ", (int) (tp + i));
+                pr_emerg("%08x ", (int) *sp++);
+        }
+        pr_emerg("\n\n");
+}
+unsigned long get_wchan(struct task_struct *p)
+{
+        unsigned long fp, pc;
+        unsigned long stack_page;
+        int count = 0;
+        if (!p || p == current || p->state == TASK_RUNNING)
+                return 0;
+        stack_page = (unsigned long)p;
+        fp = ((struct switch_stack *)p->thread.ksp)->fp;        /* ;dgt2 */
+        do {
+                if (fp < stack_page+sizeof(struct task_struct) ||
+                        fp >= 8184+stack_page)  /* ;dgt2;tmp */
+                        return 0;
+                pc = ((unsigned long *)fp)[1];
+                if (!in_sched_functions(pc))
+                        return pc;
+                fp = *(unsigned long *) fp;
+        } while (count++ < 16);         /* ;dgt2;tmp */
+        return 0;
+}
+/*
+ * Do necessary setup to start up a newly executed thread.
+ * Will startup in user mode (status_extension = 0).
+ */
+void start_thread(struct pt_regs *regs, unsigned long pc, unsigned long sp)
+{
+        memset((void *) regs, 0, sizeof(struct pt_regs));
+        regs->estatus = ESTATUS_EPIE | ESTATUS_EU;
+        regs->ea = pc;
+        regs->sp = sp;
+}
+#include <linux/elfcore.h>
+/* Fill in the FPU structure for a core dump. */
+int dump_fpu(struct pt_regs *regs, elf_fpregset_t *r)
+{
+        return 0; /* Nios2 has no FPU and thus no FPU registers */
+}
diff --git a/arch/nios2/kernel/prom.c b/arch/nios2/kernel/prom.c
new file mode 100644
index 000000000000..0522d3378e3f
--- /dev/null
+++ b/arch/nios2/kernel/prom.c
@@ -0,0 +1,65 @@
+/*
+ * Device tree support
+ *
+ * Copyright (C) 2013 Altera Corporation
+ * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
+ *
+ * Based on MIPS support for CONFIG_OF device tree support
+ *
+ * Copyright (C) 2010 Cisco Systems Inc. <dediao@cisco.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/bootmem.h>
+#include <linux/of.h>
+#include <linux/of_fdt.h>
+#include <linux/io.h>
+#include <asm/sections.h>
+void __init early_init_dt_add_memory_arch(u64 base, u64 size)
+{
+        u64 kernel_start = (u64)virt_to_phys(_text);
+        if (!memory_size &&
+            (kernel_start >= base) && (kernel_start < (base + size)))
+                memory_size = size;
+}
+void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
+{
+        return alloc_bootmem_align(size, align);
+}
+void __init early_init_devtree(void *params)
+{
+        __be32 *dtb = (u32 *)__dtb_start;
+#if defined(CONFIG_NIOS2_DTB_AT_PHYS_ADDR)
+        if (be32_to_cpup((__be32 *)CONFIG_NIOS2_DTB_PHYS_ADDR) ==
+                 OF_DT_HEADER) {
+                params = (void *)CONFIG_NIOS2_DTB_PHYS_ADDR;
+                early_init_dt_scan(params);
+                return;
+        }
+#endif
+        if (be32_to_cpu((__be32) *dtb) == OF_DT_HEADER)
+                params = (void *)__dtb_start;
+        early_init_dt_scan(params);
+}
diff --git a/arch/nios2/kernel/ptrace.c b/arch/nios2/kernel/ptrace.c
new file mode 100644
index 000000000000..681dda92eff1
--- /dev/null
+++ b/arch/nios2/kernel/ptrace.c
@@ -0,0 +1,166 @@
+/*
+ * Copyright (C) 2014 Altera Corporation
+ * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file COPYING in the main directory of this
+ * archive for more details.
+ */
+#include <linux/elf.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/ptrace.h>
+#include <linux/regset.h>
+#include <linux/sched.h>
+#include <linux/tracehook.h>
+#include <linux/uaccess.h>
+#include <linux/user.h>
+static int genregs_get(struct task_struct *target,
+                       const struct user_regset *regset,
+                       unsigned int pos, unsigned int count,
+                       void *kbuf, void __user *ubuf)
+{
+        const struct pt_regs *regs = task_pt_regs(target);
+        const struct switch_stack *sw = (struct switch_stack *)regs - 1;
+        int ret = 0;
+#define REG_O_ZERO_RANGE(START, END)            \
+        if (!ret)                                       \
+                ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, \
+                        START * 4, (END * 4) + 4);
+#define REG_O_ONE(PTR, LOC)     \
+        if (!ret)                       \
+                ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, PTR, \
+                        LOC * 4, (LOC * 4) + 4);
+#define REG_O_RANGE(PTR, START, END)    \
+        if (!ret)                               \
+                ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, PTR, \
+                        START * 4, (END * 4) + 4);
+        REG_O_ZERO_RANGE(PTR_R0, PTR_R0);
+        REG_O_RANGE(&regs->r1, PTR_R1, PTR_R7);
+        REG_O_RANGE(&regs->r8, PTR_R8, PTR_R15);
+        REG_O_RANGE(sw, PTR_R16, PTR_R23);
+        REG_O_ZERO_RANGE(PTR_R24, PTR_R25); /* et and bt */
+        REG_O_ONE(&regs->gp, PTR_GP);
+        REG_O_ONE(&regs->sp, PTR_SP);
+        REG_O_ONE(&regs->fp, PTR_FP);
+        REG_O_ONE(&regs->ea, PTR_EA);
+        REG_O_ZERO_RANGE(PTR_BA, PTR_BA);
+        REG_O_ONE(&regs->ra, PTR_RA);
+        REG_O_ONE(&regs->ea, PTR_PC); /* use ea for PC */
+        if (!ret)
+                ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
+                                         PTR_STATUS * 4, -1);
+        return ret;
+}
+/*
+ * Set the thread state from a regset passed in via ptrace
+ */
+static int genregs_set(struct task_struct *target,
+                       const struct user_regset *regset,
+                       unsigned int pos, unsigned int count,
+                       const void *kbuf, const void __user *ubuf)
+{
+        struct pt_regs *regs = task_pt_regs(target);
+        const struct switch_stack *sw = (struct switch_stack *)regs - 1;
+        int ret = 0;
+#define REG_IGNORE_RANGE(START, END)            \
+        if (!ret)                                       \
+                ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, \
+                        START * 4, (END * 4) + 4);
+#define REG_IN_ONE(PTR, LOC)    \
+        if (!ret)                       \
+                ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, \
+                        (void *)(PTR), LOC * 4, (LOC * 4) + 4);
+#define REG_IN_RANGE(PTR, START, END)   \
+        if (!ret)                               \
+                ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, \
+                        (void *)(PTR), START * 4, (END * 4) + 4);
+        REG_IGNORE_RANGE(PTR_R0, PTR_R0);
+        REG_IN_RANGE(&regs->r1, PTR_R1, PTR_R7);
+        REG_IN_RANGE(&regs->r8, PTR_R8, PTR_R15);
+        REG_IN_RANGE(sw, PTR_R16, PTR_R23);
+        REG_IGNORE_RANGE(PTR_R24, PTR_R25); /* et and bt */
+        REG_IN_ONE(&regs->gp, PTR_GP);
+        REG_IN_ONE(&regs->sp, PTR_SP);
+        REG_IN_ONE(&regs->fp, PTR_FP);
+        REG_IN_ONE(&regs->ea, PTR_EA);
+        REG_IGNORE_RANGE(PTR_BA, PTR_BA);
+        REG_IN_ONE(&regs->ra, PTR_RA);
+        REG_IN_ONE(&regs->ea, PTR_PC); /* use ea for PC */
+        if (!ret)
+                ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
+                                         PTR_STATUS * 4, -1);
+        return ret;
+}
+/*
+ * Define the register sets available on Nios2 under Linux
+ */
+enum nios2_regset {
+        REGSET_GENERAL,
+};
+static const struct user_regset nios2_regsets[] = {
+        [REGSET_GENERAL] = {
+                .core_note_type = NT_PRSTATUS,
+                .n = NUM_PTRACE_REG,
+                .size = sizeof(unsigned long),
+                .align = sizeof(unsigned long),
+                .get = genregs_get,
+                .set = genregs_set,
+        }
+};
+static const struct user_regset_view nios2_user_view = {
+        .name = "nios2",
+        .e_machine = ELF_ARCH,
+        .ei_osabi = ELF_OSABI,
+        .regsets = nios2_regsets,
+        .n = ARRAY_SIZE(nios2_regsets)
+};
+const struct user_regset_view *task_user_regset_view(struct task_struct *task)
+{
+        return &nios2_user_view;
+}
+void ptrace_disable(struct task_struct *child)
+{
+}
+long arch_ptrace(struct task_struct *child, long request, unsigned long addr,
+                 unsigned long data)
+{
+        return ptrace_request(child, request, addr, data);
+}
+asmlinkage int do_syscall_trace_enter(void)
+{
+        int ret = 0;
+        if (test_thread_flag(TIF_SYSCALL_TRACE))
+                ret = tracehook_report_syscall_entry(task_pt_regs(current));
+        return ret;
+}
+asmlinkage void do_syscall_trace_exit(void)
+{
+        if (test_thread_flag(TIF_SYSCALL_TRACE))
+                tracehook_report_syscall_exit(task_pt_regs(current), 0);
+}
diff --git a/arch/nios2/kernel/setup.c b/arch/nios2/kernel/setup.c
new file mode 100644
index 000000000000..cb3121f975d4
--- /dev/null
+++ b/arch/nios2/kernel/setup.c
@@ -0,0 +1,218 @@
+/*
+ * Nios2-specific parts of system setup
+ *
+ * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2004 Microtronix Datacom Ltd.
+ * Copyright (C) 2001 Vic Phillips <vic@microtronix.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/export.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/console.h>
+#include <linux/bootmem.h>
+#include <linux/initrd.h>
+#include <linux/of_fdt.h>
+#include <asm/mmu_context.h>
+#include <asm/sections.h>
+#include <asm/setup.h>
+#include <asm/cpuinfo.h>
+unsigned long memory_start;
+EXPORT_SYMBOL(memory_start);
+unsigned long memory_end;
+EXPORT_SYMBOL(memory_end);
+unsigned long memory_size;
+static struct pt_regs fake_regs = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                                        0, 0, 0, 0, 0, 0,
+                                        0};
+/* Copy a short hook instruction sequence to the exception address */
+static inline void copy_exception_handler(unsigned int addr)
+{
+        unsigned int start = (unsigned int) exception_handler_hook;
+        volatile unsigned int tmp = 0;
+        if (start == addr) {
+                /* The CPU exception address already points to the handler. */
+                return;
+        }
+        __asm__ __volatile__ (
+                "ldw    %2,0(%0)\n"
+                "stw    %2,0(%1)\n"
+                "ldw    %2,4(%0)\n"
+                "stw    %2,4(%1)\n"
+                "ldw    %2,8(%0)\n"
+                "stw    %2,8(%1)\n"
+                "flushd 0(%1)\n"
+                "flushd 4(%1)\n"
+                "flushd 8(%1)\n"
+                "flushi %1\n"
+                "addi   %1,%1,4\n"
+                "flushi %1\n"
+                "addi   %1,%1,4\n"
+                "flushi %1\n"
+                "flushp\n"
+                : /* no output registers */
+                : "r" (start), "r" (addr), "r" (tmp)
+                : "memory"
+        );
+}
+/* Copy the fast TLB miss handler */
+static inline void copy_fast_tlb_miss_handler(unsigned int addr)
+{
+        unsigned int start = (unsigned int) fast_handler;
+        unsigned int end = (unsigned int) fast_handler_end;
+        volatile unsigned int tmp = 0;
+        __asm__ __volatile__ (
+                "1:\n"
+                "       ldw     %3,0(%0)\n"
+                "       stw     %3,0(%1)\n"
+                "       flushd  0(%1)\n"
+                "       flushi  %1\n"
+                "       flushp\n"
+                "       addi    %0,%0,4\n"
+                "       addi    %1,%1,4\n"
+                "       bne     %0,%2,1b\n"
+                : /* no output registers */
+                : "r" (start), "r" (addr), "r" (end), "r" (tmp)
+                : "memory"
+        );
+}
+/*
+ * save args passed from u-boot, called from head.S
+ *
+ * @r4: NIOS magic
+ * @r5: initrd start
+ * @r6: initrd end or fdt
+ * @r7: kernel command line
+ */
+asmlinkage void __init nios2_boot_init(unsigned r4, unsigned r5, unsigned r6,
+                                       unsigned r7)
+{
+        unsigned dtb_passed = 0;
+        char cmdline_passed[COMMAND_LINE_SIZE] = { 0, };
+#if defined(CONFIG_NIOS2_PASS_CMDLINE)
+        if (r4 == 0x534f494e) { /* r4 is magic NIOS */
+#if defined(CONFIG_BLK_DEV_INITRD)
+                if (r5) { /* initramfs */
+                        initrd_start = r5;
+                        initrd_end = r6;
+                }
+#endif /* CONFIG_BLK_DEV_INITRD */
+                dtb_passed = r6;
+                if (r7)
+                        strncpy(cmdline_passed, (char *)r7, COMMAND_LINE_SIZE);
+        }
+#endif
+        early_init_devtree((void *)dtb_passed);
+#ifndef CONFIG_CMDLINE_FORCE
+        if (cmdline_passed[0])
+                strncpy(boot_command_line, cmdline_passed, COMMAND_LINE_SIZE);
+#ifdef CONFIG_NIOS2_CMDLINE_IGNORE_DTB
+        else
+                strncpy(boot_command_line, CONFIG_CMDLINE, COMMAND_LINE_SIZE);
+#endif
+#endif
+}
+void __init setup_arch(char **cmdline_p)
+{
+        int bootmap_size;
+        console_verbose();
+        memory_start = PAGE_ALIGN((unsigned long)__pa(_end));
+        memory_end = (unsigned long) CONFIG_NIOS2_MEM_BASE + memory_size;
+        init_mm.start_code = (unsigned long) _stext;
+        init_mm.end_code = (unsigned long) _etext;
+        init_mm.end_data = (unsigned long) _edata;
+        init_mm.brk = (unsigned long) _end;
+        init_task.thread.kregs = &fake_regs;
+        /* Keep a copy of command line */
+        *cmdline_p = boot_command_line;
+        min_low_pfn = PFN_UP(memory_start);
+        max_low_pfn = PFN_DOWN(memory_end);
+        max_mapnr = max_low_pfn;
+        /*
+         * give all the memory to the bootmap allocator,  tell it to put the
+         * boot mem_map at the start of memory
+         */
+        pr_debug("init_bootmem_node(?,%#lx, %#x, %#lx)\n",
+                min_low_pfn, PFN_DOWN(PHYS_OFFSET), max_low_pfn);
+        bootmap_size = init_bootmem_node(NODE_DATA(0),
+                                        min_low_pfn, PFN_DOWN(PHYS_OFFSET),
+                                        max_low_pfn);
+        /*
+         * free the usable memory,  we have to make sure we do not free
+         * the bootmem bitmap so we then reserve it after freeing it :-)
+         */
+        pr_debug("free_bootmem(%#lx, %#lx)\n",
+                memory_start, memory_end - memory_start);
+        free_bootmem(memory_start, memory_end - memory_start);
+        /*
+         * Reserve the bootmem bitmap itself as well. We do this in two
+         * steps (first step was init_bootmem()) because this catches
+         * the (very unlikely) case of us accidentally initializing the
+         * bootmem allocator with an invalid RAM area.
+         *
+         * Arguments are start, size
+         */
+        pr_debug("reserve_bootmem(%#lx, %#x)\n", memory_start, bootmap_size);
+        reserve_bootmem(memory_start, bootmap_size, BOOTMEM_DEFAULT);
+#ifdef CONFIG_BLK_DEV_INITRD
+        if (initrd_start) {
+                reserve_bootmem(virt_to_phys((void *)initrd_start),
+                                initrd_end - initrd_start, BOOTMEM_DEFAULT);
+        }
+#endif /* CONFIG_BLK_DEV_INITRD */
+        unflatten_and_copy_device_tree();
+        setup_cpuinfo();
+        copy_exception_handler(cpuinfo.exception_addr);
+        mmu_init();
+        copy_fast_tlb_miss_handler(cpuinfo.fast_tlb_miss_exc_addr);
+        /*
+         * Initialize MMU context handling here because data from cpuinfo is
+         * needed for this.
+         */
+        mmu_context_init();
+        /*
+         * get kmalloc into gear
+         */
+        paging_init();
+#if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
+        conswitchp = &dummy_con;
+#endif
+}
diff --git a/arch/nios2/kernel/signal.c b/arch/nios2/kernel/signal.c
new file mode 100644
index 000000000000..f9d27883a714
--- /dev/null
+++ b/arch/nios2/kernel/signal.c
@@ -0,0 +1,323 @@
+/*
+ * Copyright (C) 2013-2014 Altera Corporation
+ * Copyright (C) 2011-2012 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2004 Microtronix Datacom Ltd
+ * Copyright (C) 1991, 1992 Linus Torvalds
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+#include <linux/signal.h>
+#include <linux/errno.h>
+#include <linux/ptrace.h>
+#include <linux/uaccess.h>
+#include <linux/unistd.h>
+#include <linux/personality.h>
+#include <linux/tracehook.h>
+#include <asm/ucontext.h>
+#include <asm/cacheflush.h>
+#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
+/*
+ * Do a signal return; undo the signal stack.
+ *
+ * Keep the return code on the stack quadword aligned!
+ * That makes the cache flush below easier.
+ */
+struct rt_sigframe {
+        struct siginfo info;
+        struct ucontext uc;
+};
+static inline int rt_restore_ucontext(struct pt_regs *regs,
+                                        struct switch_stack *sw,
+                                        struct ucontext *uc, int *pr2)
+{
+        int temp;
+        greg_t *gregs = uc->uc_mcontext.gregs;
+        int err;
+        /* Always make any pending restarted system calls return -EINTR */
+        current_thread_info()->restart_block.fn = do_no_restart_syscall;
+        err = __get_user(temp, &uc->uc_mcontext.version);
+        if (temp != MCONTEXT_VERSION)
+                goto badframe;
+        /* restore passed registers */
+        err |= __get_user(regs->r1, &gregs[0]);
+        err |= __get_user(regs->r2, &gregs[1]);
+        err |= __get_user(regs->r3, &gregs[2]);
+        err |= __get_user(regs->r4, &gregs[3]);
+        err |= __get_user(regs->r5, &gregs[4]);
+        err |= __get_user(regs->r6, &gregs[5]);
+        err |= __get_user(regs->r7, &gregs[6]);
+        err |= __get_user(regs->r8, &gregs[7]);
+        err |= __get_user(regs->r9, &gregs[8]);
+        err |= __get_user(regs->r10, &gregs[9]);
+        err |= __get_user(regs->r11, &gregs[10]);
+        err |= __get_user(regs->r12, &gregs[11]);
+        err |= __get_user(regs->r13, &gregs[12]);
+        err |= __get_user(regs->r14, &gregs[13]);
+        err |= __get_user(regs->r15, &gregs[14]);
+        err |= __get_user(sw->r16, &gregs[15]);
+        err |= __get_user(sw->r17, &gregs[16]);
+        err |= __get_user(sw->r18, &gregs[17]);
+        err |= __get_user(sw->r19, &gregs[18]);
+        err |= __get_user(sw->r20, &gregs[19]);
+        err |= __get_user(sw->r21, &gregs[20]);
+        err |= __get_user(sw->r22, &gregs[21]);
+        err |= __get_user(sw->r23, &gregs[22]);
+        /* gregs[23] is handled below */
+        err |= __get_user(sw->fp, &gregs[24]);  /* Verify, should this be
+                                                        settable */
+        err |= __get_user(sw->gp, &gregs[25]);  /* Verify, should this be
+                                                        settable */
+        err |= __get_user(temp, &gregs[26]);  /* Not really necessary no user
+                                                        settable bits */
+        err |= __get_user(regs->ea, &gregs[27]);
+        err |= __get_user(regs->ra, &gregs[23]);
+        err |= __get_user(regs->sp, &gregs[28]);
+        regs->orig_r2 = -1;             /* disable syscall checks */
+        err |= restore_altstack(&uc->uc_stack);
+        if (err)
+                goto badframe;
+        *pr2 = regs->r2;
+        return err;
+badframe:
+        return 1;
+}
+asmlinkage int do_rt_sigreturn(struct switch_stack *sw)
+{
+        struct pt_regs *regs = (struct pt_regs *)(sw + 1);
+        /* Verify, can we follow the stack back */
+        struct rt_sigframe *frame = (struct rt_sigframe *) regs->sp;
+        sigset_t set;
+        int rval;
+        if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
+                goto badframe;
+        if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
+                goto badframe;
+        set_current_blocked(&set);
+        if (rt_restore_ucontext(regs, sw, &frame->uc, &rval))
+                goto badframe;
+        return rval;
+badframe:
+        force_sig(SIGSEGV, current);
+        return 0;
+}
+static inline int rt_setup_ucontext(struct ucontext *uc, struct pt_regs *regs)
+{
+        struct switch_stack *sw = (struct switch_stack *)regs - 1;
+        greg_t *gregs = uc->uc_mcontext.gregs;
+        int err = 0;
+        err |= __put_user(MCONTEXT_VERSION, &uc->uc_mcontext.version);
+        err |= __put_user(regs->r1, &gregs[0]);
+        err |= __put_user(regs->r2, &gregs[1]);
+        err |= __put_user(regs->r3, &gregs[2]);
+        err |= __put_user(regs->r4, &gregs[3]);
+        err |= __put_user(regs->r5, &gregs[4]);
+        err |= __put_user(regs->r6, &gregs[5]);
+        err |= __put_user(regs->r7, &gregs[6]);
+        err |= __put_user(regs->r8, &gregs[7]);
+        err |= __put_user(regs->r9, &gregs[8]);
+        err |= __put_user(regs->r10, &gregs[9]);
+        err |= __put_user(regs->r11, &gregs[10]);
+        err |= __put_user(regs->r12, &gregs[11]);
+        err |= __put_user(regs->r13, &gregs[12]);
+        err |= __put_user(regs->r14, &gregs[13]);
+        err |= __put_user(regs->r15, &gregs[14]);
+        err |= __put_user(sw->r16, &gregs[15]);
+        err |= __put_user(sw->r17, &gregs[16]);
+        err |= __put_user(sw->r18, &gregs[17]);
+        err |= __put_user(sw->r19, &gregs[18]);
+        err |= __put_user(sw->r20, &gregs[19]);
+        err |= __put_user(sw->r21, &gregs[20]);
+        err |= __put_user(sw->r22, &gregs[21]);
+        err |= __put_user(sw->r23, &gregs[22]);
+        err |= __put_user(regs->ra, &gregs[23]);
+        err |= __put_user(sw->fp, &gregs[24]);
+        err |= __put_user(sw->gp, &gregs[25]);
+        err |= __put_user(regs->ea, &gregs[27]);
+        err |= __put_user(regs->sp, &gregs[28]);
+        return err;
+}
+static inline void *get_sigframe(struct ksignal *ksig, struct pt_regs *regs,
+                                 size_t frame_size)
+{
+        unsigned long usp;
+        /* Default to using normal stack.  */
+        usp = regs->sp;
+        /* This is the X/Open sanctioned signal stack switching.  */
+        usp = sigsp(usp, ksig);
+        /* Verify, is it 32 or 64 bit aligned */
+        return (void *)((usp - frame_size) & -8UL);
+}
+static int setup_rt_frame(struct ksignal *ksig, sigset_t *set,
+                          struct pt_regs *regs)
+{
+        struct rt_sigframe *frame;
+        int err = 0;
+        frame = get_sigframe(ksig, regs, sizeof(*frame));
+        if (ksig->ka.sa.sa_flags & SA_SIGINFO)
+                err |= copy_siginfo_to_user(&frame->info, &ksig->info);
+        /* Create the ucontext.  */
+        err |= __put_user(0, &frame->uc.uc_flags);
+        err |= __put_user(0, &frame->uc.uc_link);
+        err |= __save_altstack(&frame->uc.uc_stack, regs->sp);
+        err |= rt_setup_ucontext(&frame->uc, regs);
+        err |= copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
+        if (err)
+                goto give_sigsegv;
+        /* Set up to return from userspace; jump to fixed address sigreturn
+           trampoline on kuser page.  */
+        regs->ra = (unsigned long) (0x1040);
+        /* Set up registers for signal handler */
+        regs->sp = (unsigned long) frame;
+        regs->r4 = (unsigned long) ksig->sig;
+        regs->r5 = (unsigned long) &frame->info;
+        regs->r6 = (unsigned long) &frame->uc;
+        regs->ea = (unsigned long) ksig->ka.sa.sa_handler;
+        return 0;
+give_sigsegv:
+        force_sigsegv(ksig->sig, current);
+        return -EFAULT;
+}
+/*
+ * OK, we're invoking a handler
+ */
+static void handle_signal(struct ksignal *ksig, struct pt_regs *regs)
+{
+        int ret;
+        sigset_t *oldset = sigmask_to_save();
+        /* set up the stack frame */
+        ret = setup_rt_frame(ksig, oldset, regs);
+        signal_setup_done(ret, ksig, 0);
+}
+static int do_signal(struct pt_regs *regs)
+{
+        unsigned int retval = 0, continue_addr = 0, restart_addr = 0;
+        int restart = 0;
+        struct ksignal ksig;
+        current->thread.kregs = regs;
+        /*
+         * If we were from a system call, check for system call restarting...
+         */
+        if (regs->orig_r2 >= 0) {
+                continue_addr = regs->ea;
+                restart_addr = continue_addr - 4;
+                retval = regs->r2;
+                /*
+                 * Prepare for system call restart. We do this here so that a
+                 * debugger will see the already changed PC.
+                 */
+                switch (retval) {
+                case ERESTART_RESTARTBLOCK:
+                        restart = -2;
+                case ERESTARTNOHAND:
+                case ERESTARTSYS:
+                case ERESTARTNOINTR:
+                        restart++;
+                        regs->r2 = regs->orig_r2;
+                        regs->r7 = regs->orig_r7;
+                        regs->ea = restart_addr;
+                        break;
+                }
+        }
+        if (get_signal(&ksig)) {
+                /* handler */
+                if (unlikely(restart && regs->ea == restart_addr)) {
+                        if (retval == ERESTARTNOHAND ||
+                            retval == ERESTART_RESTARTBLOCK ||
+                             (retval == ERESTARTSYS
+                                && !(ksig.ka.sa.sa_flags & SA_RESTART))) {
+                                regs->r2 = EINTR;
+                                regs->r7 = 1;
+                                regs->ea = continue_addr;
+                        }
+                }
+                handle_signal(&ksig, regs);
+                return 0;
+        }
+        /*
+         * No handler present
+         */
+        if (unlikely(restart) && regs->ea == restart_addr) {
+                regs->ea = continue_addr;
+                regs->r2 = __NR_restart_syscall;
+        }
+        /*
+        * If there's no signal to deliver, we just put the saved sigmask back.
+        */
+        restore_saved_sigmask();
+        return restart;
+}
+asmlinkage int do_notify_resume(struct pt_regs *regs)
+{
+        /*
+         * We want the common case to go fast, which is why we may in certain
+         * cases get here from kernel mode. Just return without doing anything
+         * if so.
+         */
+        if (!user_mode(regs))
+                return 0;
+        if (test_thread_flag(TIF_SIGPENDING)) {
+                int restart = do_signal(regs);
+                if (unlikely(restart)) {
+                        /*
+                         * Restart without handlers.
+                         * Deal with it without leaving
+                         * the kernel space.
+                         */
+                        return restart;
+                }
+        } else if (test_and_clear_thread_flag(TIF_NOTIFY_RESUME))
+                tracehook_notify_resume(regs);
+        return 0;
+}
diff --git a/arch/nios2/kernel/sys_nios2.c b/arch/nios2/kernel/sys_nios2.c
new file mode 100644
index 000000000000..cd390ec4f88b
--- /dev/null
+++ b/arch/nios2/kernel/sys_nios2.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ * Copyright (C) 2011-2012 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2004 Microtronix Datacom Ltd.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/export.h>
+#include <linux/file.h>
+#include <linux/fs.h>
+#include <linux/slab.h>
+#include <linux/syscalls.h>
+#include <asm/cacheflush.h>
+#include <asm/traps.h>
+/* sys_cacheflush -- flush the processor cache. */
+asmlinkage int sys_cacheflush(unsigned long addr, unsigned long len,
+                                unsigned int op)
+{
+        struct vm_area_struct *vma;
+        if (len == 0)
+                return 0;
+        /* We only support op 0 now, return error if op is non-zero.*/
+        if (op)
+                return -EINVAL;
+        /* Check for overflow */
+        if (addr + len < addr)
+                return -EFAULT;
+        /*
+         * Verify that the specified address region actually belongs
+         * to this process.
+         */
+        vma = find_vma(current->mm, addr);
+        if (vma == NULL || addr < vma->vm_start || addr + len > vma->vm_end)
+                return -EFAULT;
+        flush_cache_range(vma, addr, addr + len);
+        return 0;
+}
+asmlinkage int sys_getpagesize(void)
+{
+        return PAGE_SIZE;
+}
diff --git a/arch/nios2/kernel/syscall_table.c b/arch/nios2/kernel/syscall_table.c
new file mode 100644
index 000000000000..06e6ac1835b2
--- /dev/null
+++ b/arch/nios2/kernel/syscall_table.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright Altera Corporation (C) 2013. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#include <linux/syscalls.h>
+#include <linux/signal.h>
+#include <linux/unistd.h>
+#include <asm/syscalls.h>
+#undef __SYSCALL
+#define __SYSCALL(nr, call) [nr] = (call),
+void *sys_call_table[__NR_syscalls] = {
+#include <asm/unistd.h>
+};
diff --git a/arch/nios2/kernel/time.c b/arch/nios2/kernel/time.c
new file mode 100644
index 000000000000..7f4547418ee1
--- /dev/null
+++ b/arch/nios2/kernel/time.c
@@ -0,0 +1,308 @@
+/*
+ * Copyright (C) 2013-2014 Altera Corporation
+ * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2004 Microtronix Datacom Ltd.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/interrupt.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#define ALTERA_TIMER_STATUS_REG         0
+#define ALTERA_TIMER_CONTROL_REG        4
+#define ALTERA_TIMER_PERIODL_REG        8
+#define ALTERA_TIMER_PERIODH_REG        12
+#define ALTERA_TIMER_SNAPL_REG          16
+#define ALTERA_TIMER_SNAPH_REG          20
+#define ALTERA_TIMER_CONTROL_ITO_MSK    (0x1)
+#define ALTERA_TIMER_CONTROL_CONT_MSK   (0x2)
+#define ALTERA_TIMER_CONTROL_START_MSK  (0x4)
+#define ALTERA_TIMER_CONTROL_STOP_MSK   (0x8)
+struct nios2_timer {
+        void __iomem *base;
+        unsigned long freq;
+};
+struct nios2_clockevent_dev {
+        struct nios2_timer timer;
+        struct clock_event_device ced;
+};
+struct nios2_clocksource {
+        struct nios2_timer timer;
+        struct clocksource cs;
+};
+static inline struct nios2_clockevent_dev *
+        to_nios2_clkevent(struct clock_event_device *evt)
+{
+        return container_of(evt, struct nios2_clockevent_dev, ced);
+}
+static inline struct nios2_clocksource *
+        to_nios2_clksource(struct clocksource *cs)
+{
+        return container_of(cs, struct nios2_clocksource, cs);
+}
+static u16 timer_readw(struct nios2_timer *timer, u32 offs)
+{
+        return readw(timer->base + offs);
+}
+static void timer_writew(struct nios2_timer *timer, u16 val, u32 offs)
+{
+        writew(val, timer->base + offs);
+}
+static inline unsigned long read_timersnapshot(struct nios2_timer *timer)
+{
+        unsigned long count;
+        timer_writew(timer, 0, ALTERA_TIMER_SNAPL_REG);
+        count = timer_readw(timer, ALTERA_TIMER_SNAPH_REG) << 16 |
+                timer_readw(timer, ALTERA_TIMER_SNAPL_REG);
+        return count;
+}
+static cycle_t nios2_timer_read(struct clocksource *cs)
+{
+        struct nios2_clocksource *nios2_cs = to_nios2_clksource(cs);
+        unsigned long flags;
+        u32 count;
+        local_irq_save(flags);
+        count = read_timersnapshot(&nios2_cs->timer);
+        local_irq_restore(flags);
+        /* Counter is counting down */
+        return ~count;
+}
+static struct nios2_clocksource nios2_cs = {
+        .cs = {
+                .name   = "nios2-clksrc",
+                .rating = 250,
+                .read   = nios2_timer_read,
+                .mask   = CLOCKSOURCE_MASK(32),
+                .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
+        },
+};
+cycles_t get_cycles(void)
+{
+        return nios2_timer_read(&nios2_cs.cs);
+}
+static void nios2_timer_start(struct nios2_timer *timer)
+{
+        u16 ctrl;
+        ctrl = timer_readw(timer, ALTERA_TIMER_CONTROL_REG);
+        ctrl |= ALTERA_TIMER_CONTROL_START_MSK;
+        timer_writew(timer, ctrl, ALTERA_TIMER_CONTROL_REG);
+}
+static void nios2_timer_stop(struct nios2_timer *timer)
+{
+        u16 ctrl;
+        ctrl = timer_readw(timer, ALTERA_TIMER_CONTROL_REG);
+        ctrl |= ALTERA_TIMER_CONTROL_STOP_MSK;
+        timer_writew(timer, ctrl, ALTERA_TIMER_CONTROL_REG);
+}
+static void nios2_timer_config(struct nios2_timer *timer, unsigned long period,
+        enum clock_event_mode mode)
+{
+        u16 ctrl;
+        /* The timer's actual period is one cycle greater than the value
+         * stored in the period register. */
+         period--;
+        ctrl = timer_readw(timer, ALTERA_TIMER_CONTROL_REG);
+        /* stop counter */
+        timer_writew(timer, ctrl | ALTERA_TIMER_CONTROL_STOP_MSK,
+                ALTERA_TIMER_CONTROL_REG);
+        /* write new count */
+        timer_writew(timer, period, ALTERA_TIMER_PERIODL_REG);
+        timer_writew(timer, period >> 16, ALTERA_TIMER_PERIODH_REG);
+        ctrl |= ALTERA_TIMER_CONTROL_START_MSK | ALTERA_TIMER_CONTROL_ITO_MSK;
+        if (mode == CLOCK_EVT_MODE_PERIODIC)
+                ctrl |= ALTERA_TIMER_CONTROL_CONT_MSK;
+        else
+                ctrl &= ~ALTERA_TIMER_CONTROL_CONT_MSK;
+        timer_writew(timer, ctrl, ALTERA_TIMER_CONTROL_REG);
+}
+static int nios2_timer_set_next_event(unsigned long delta,
+        struct clock_event_device *evt)
+{
+        struct nios2_clockevent_dev *nios2_ced = to_nios2_clkevent(evt);
+        nios2_timer_config(&nios2_ced->timer, delta, evt->mode);
+        return 0;
+}
+static void nios2_timer_set_mode(enum clock_event_mode mode,
+        struct clock_event_device *evt)
+{
+        unsigned long period;
+        struct nios2_clockevent_dev *nios2_ced = to_nios2_clkevent(evt);
+        struct nios2_timer *timer = &nios2_ced->timer;
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                period = DIV_ROUND_UP(timer->freq, HZ);
+                nios2_timer_config(timer, period, CLOCK_EVT_MODE_PERIODIC);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+                nios2_timer_stop(timer);
+                break;
+        case CLOCK_EVT_MODE_RESUME:
+                nios2_timer_start(timer);
+                break;
+        }
+}
+irqreturn_t timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = (struct clock_event_device *) dev_id;
+        struct nios2_clockevent_dev *nios2_ced = to_nios2_clkevent(evt);
+        /* Clear the interrupt condition */
+        timer_writew(&nios2_ced->timer, 0, ALTERA_TIMER_STATUS_REG);
+        evt->event_handler(evt);
+        return IRQ_HANDLED;
+}
+static void __init nios2_timer_get_base_and_freq(struct device_node *np,
+                                void __iomem **base, u32 *freq)
+{
+        *base = of_iomap(np, 0);
+        if (!*base)
+                panic("Unable to map reg for %s\n", np->name);
+        if (of_property_read_u32(np, "clock-frequency", freq))
+                panic("Unable to get %s clock frequency\n", np->name);
+}
+static struct nios2_clockevent_dev nios2_ce = {
+        .ced = {
+                .name = "nios2-clkevent",
+                .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+                .rating = 250,
+                .shift = 32,
+                .set_next_event = nios2_timer_set_next_event,
+                .set_mode = nios2_timer_set_mode,
+        },
+};
+static __init void nios2_clockevent_init(struct device_node *timer)
+{
+        void __iomem *iobase;
+        u32 freq;
+        int irq;
+        nios2_timer_get_base_and_freq(timer, &iobase, &freq);
+        irq = irq_of_parse_and_map(timer, 0);
+        if (!irq)
+                panic("Unable to parse timer irq\n");
+        nios2_ce.timer.base = iobase;
+        nios2_ce.timer.freq = freq;
+        nios2_ce.ced.cpumask = cpumask_of(0);
+        nios2_ce.ced.irq = irq;
+        nios2_timer_stop(&nios2_ce.timer);
+        /* clear pending interrupt */
+        timer_writew(&nios2_ce.timer, 0, ALTERA_TIMER_STATUS_REG);
+        if (request_irq(irq, timer_interrupt, IRQF_TIMER, timer->name,
+                &nios2_ce.ced))
+                panic("Unable to setup timer irq\n");
+        clockevents_config_and_register(&nios2_ce.ced, freq, 1, ULONG_MAX);
+}
+static __init void nios2_clocksource_init(struct device_node *timer)
+{
+        unsigned int ctrl;
+        void __iomem *iobase;
+        u32 freq;
+        nios2_timer_get_base_and_freq(timer, &iobase, &freq);
+        nios2_cs.timer.base = iobase;
+        nios2_cs.timer.freq = freq;
+        clocksource_register_hz(&nios2_cs.cs, freq);
+        timer_writew(&nios2_cs.timer, USHRT_MAX, ALTERA_TIMER_PERIODL_REG);
+        timer_writew(&nios2_cs.timer, USHRT_MAX, ALTERA_TIMER_PERIODH_REG);
+        /* interrupt disable + continuous + start */
+        ctrl = ALTERA_TIMER_CONTROL_CONT_MSK | ALTERA_TIMER_CONTROL_START_MSK;
+        timer_writew(&nios2_cs.timer, ctrl, ALTERA_TIMER_CONTROL_REG);
+        /* Calibrate the delay loop directly */
+        lpj_fine = freq / HZ;
+}
+/*
+ * The first timer instance will use as a clockevent. If there are two or
+ * more instances, the second one gets used as clocksource and all
+ * others are unused.
+*/
+static void __init nios2_time_init(struct device_node *timer)
+{
+        static int num_called;
+        switch (num_called) {
+        case 0:
+                nios2_clockevent_init(timer);
+                break;
+        case 1:
+                nios2_clocksource_init(timer);
+                break;
+        default:
+                break;
+        }
+        num_called++;
+}
+void read_persistent_clock(struct timespec *ts)
+{
+        ts->tv_sec = mktime(2007, 1, 1, 0, 0, 0);
+        ts->tv_nsec = 0;
+}
+void __init time_init(void)
+{
+        clocksource_of_init();
+}
+CLOCKSOURCE_OF_DECLARE(nios2_timer, "altr,timer-1.0", nios2_time_init);
diff --git a/arch/nios2/kernel/traps.c b/arch/nios2/kernel/traps.c
new file mode 100644
index 000000000000..b7b97641a9a6
--- /dev/null
+++ b/arch/nios2/kernel/traps.c
@@ -0,0 +1,185 @@
+/*
+ * Hardware exception handling
+ *
+ * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2004 Microtronix Datacom Ltd.
+ * Copyright (C) 2001 Vic Phillips
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file COPYING in the main directory of this
+ * archive for more details.
+ */
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/signal.h>
+#include <linux/export.h>
+#include <linux/mm.h>
+#include <linux/ptrace.h>
+#include <asm/traps.h>
+#include <asm/sections.h>
+#include <asm/uaccess.h>
+static DEFINE_SPINLOCK(die_lock);
+void die(const char *str, struct pt_regs *regs, long err)
+{
+        console_verbose();
+        spin_lock_irq(&die_lock);
+        pr_warn("Oops: %s, sig: %ld\n", str, err);
+        show_regs(regs);
+        spin_unlock_irq(&die_lock);
+        /*
+         * do_exit() should take care of panic'ing from an interrupt
+         * context so we don't handle it here
+         */
+        do_exit(err);
+}
+void _exception(int signo, struct pt_regs *regs, int code, unsigned long addr)
+{
+        siginfo_t info;
+        if (!user_mode(regs))
+                die("Exception in kernel mode", regs, signo);
+        info.si_signo = signo;
+        info.si_errno = 0;
+        info.si_code = code;
+        info.si_addr = (void __user *) addr;
+        force_sig_info(signo, &info, current);
+}
+/*
+ * The show_stack is an external API which we do not use ourselves.
+ */
+int kstack_depth_to_print = 48;
+void show_stack(struct task_struct *task, unsigned long *stack)
+{
+        unsigned long *endstack, addr;
+        int i;
+        if (!stack) {
+                if (task)
+                        stack = (unsigned long *)task->thread.ksp;
+                else
+                        stack = (unsigned long *)&stack;
+        }
+        addr = (unsigned long) stack;
+        endstack = (unsigned long *) PAGE_ALIGN(addr);
+        pr_emerg("Stack from %08lx:", (unsigned long)stack);
+        for (i = 0; i < kstack_depth_to_print; i++) {
+                if (stack + 1 > endstack)
+                        break;
+                if (i % 8 == 0)
+                        pr_emerg("\n       ");
+                pr_emerg(" %08lx", *stack++);
+        }
+        pr_emerg("\nCall Trace:");
+        i = 0;
+        while (stack + 1 <= endstack) {
+                addr = *stack++;
+                /*
+                 * If the address is either in the text segment of the
+                 * kernel, or in the region which contains vmalloc'ed
+                 * memory, it *may* be the address of a calling
+                 * routine; if so, print it so that someone tracing
+                 * down the cause of the crash will be able to figure
+                 * out the call path that was taken.
+                 */
+                if (((addr >= (unsigned long) _stext) &&
+                     (addr <= (unsigned long) _etext))) {
+                        if (i % 4 == 0)
+                                pr_emerg("\n       ");
+                        pr_emerg(" [<%08lx>]", addr);
+                        i++;
+                }
+        }
+        pr_emerg("\n");
+}
+void __init trap_init(void)
+{
+        /* Nothing to do here */
+}
+/* Breakpoint handler */
+asmlinkage void breakpoint_c(struct pt_regs *fp)
+{
+        /*
+         * The breakpoint entry code has moved the PC on by 4 bytes, so we must
+         * move it back. This could be done on the host but we do it here
+         * because monitor.S of JTAG gdbserver does it too.
+         */
+        fp->ea -= 4;
+        _exception(SIGTRAP, fp, TRAP_BRKPT, fp->ea);
+}
+#ifndef CONFIG_NIOS2_ALIGNMENT_TRAP
+/* Alignment exception handler */
+asmlinkage void handle_unaligned_c(struct pt_regs *fp, int cause)
+{
+        unsigned long addr = RDCTL(CTL_BADADDR);
+        cause >>= 2;
+        fp->ea -= 4;
+        if (fixup_exception(fp))
+                return;
+        if (!user_mode(fp)) {
+                pr_alert("Unaligned access from kernel mode, this might be a hardware\n");
+                pr_alert("problem, dump registers and restart the instruction\n");
+                pr_alert("  BADADDR 0x%08lx\n", addr);
+                pr_alert("  cause   %d\n", cause);
+                pr_alert("  op-code 0x%08lx\n", *(unsigned long *)(fp->ea));
+                show_regs(fp);
+                return;
+        }
+        _exception(SIGBUS, fp, BUS_ADRALN, addr);
+}
+#endif /* CONFIG_NIOS2_ALIGNMENT_TRAP */
+/* Illegal instruction handler */
+asmlinkage void handle_illegal_c(struct pt_regs *fp)
+{
+        fp->ea -= 4;
+        _exception(SIGILL, fp, ILL_ILLOPC, fp->ea);
+}
+/* Supervisor instruction handler */
+asmlinkage void handle_supervisor_instr(struct pt_regs *fp)
+{
+        fp->ea -= 4;
+        _exception(SIGILL, fp, ILL_PRVOPC, fp->ea);
+}
+/* Division error handler */
+asmlinkage void handle_diverror_c(struct pt_regs *fp)
+{
+        fp->ea -= 4;
+        _exception(SIGFPE, fp, FPE_INTDIV, fp->ea);
+}
+/* Unhandled exception handler */
+asmlinkage void unhandled_exception(struct pt_regs *regs, int cause)
+{
+        unsigned long addr = RDCTL(CTL_BADADDR);
+        cause /= 4;
+        pr_emerg("Unhandled exception #%d in %s mode (badaddr=0x%08lx)\n",
+                        cause, user_mode(regs) ? "user" : "kernel", addr);
+        regs->ea -= 4;
+        show_regs(regs);
+        pr_emerg("opcode: 0x%08lx\n", *(unsigned long *)(regs->ea));
+}
diff --git a/arch/nios2/kernel/vmlinux.lds.S b/arch/nios2/kernel/vmlinux.lds.S
new file mode 100644
index 000000000000..326fab40a9de
--- /dev/null
+++ b/arch/nios2/kernel/vmlinux.lds.S
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2009 Thomas Chou <thomas@wytron.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#include <asm/page.h>
+#include <asm-generic/vmlinux.lds.h>
+#include <asm/cache.h>
+#include <asm/thread_info.h>
+OUTPUT_FORMAT("elf32-littlenios2", "elf32-littlenios2", "elf32-littlenios2")
+OUTPUT_ARCH(nios)
+ENTRY(_start)   /* Defined in head.S */
+jiffies = jiffies_64;
+SECTIONS
+{
+        . = CONFIG_NIOS2_MEM_BASE | CONFIG_NIOS2_KERNEL_REGION_BASE;
+        _text = .;
+        _stext = .;
+        HEAD_TEXT_SECTION
+        .text : {
+                TEXT_TEXT
+                SCHED_TEXT
+                LOCK_TEXT
+                IRQENTRY_TEXT
+                KPROBES_TEXT
+        } =0
+        _etext = .;
+        .got : {
+                *(.got.plt)
+                *(.igot.plt)
+                *(.got)
+                *(.igot)
+        }
+        EXCEPTION_TABLE(L1_CACHE_BYTES)
+        . = ALIGN(PAGE_SIZE);
+        __init_begin = .;
+        INIT_TEXT_SECTION(PAGE_SIZE)
+        INIT_DATA_SECTION(PAGE_SIZE)
+        PERCPU_SECTION(L1_CACHE_BYTES)
+        __init_end = .;
+        _sdata = .;
+        RO_DATA_SECTION(PAGE_SIZE)
+        RW_DATA_SECTION(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
+        _edata = .;
+        BSS_SECTION(0, 0, 0)
+        _end = .;
+        STABS_DEBUG
+        DWARF_DEBUG
+        NOTES
+        DISCARDS
+}
diff --git a/arch/nios2/lib/Makefile b/arch/nios2/lib/Makefile
new file mode 100644
index 000000000000..557256628ecd
--- /dev/null
+++ b/arch/nios2/lib/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for Nios2-specific library files.
+#
+lib-y += delay.o
+lib-y += memcpy.o
+lib-y += memmove.o
+lib-y += memset.o
diff --git a/arch/nios2/lib/delay.c b/arch/nios2/lib/delay.c
new file mode 100644
index 000000000000..088119cd0cc5
--- /dev/null
+++ b/arch/nios2/lib/delay.c
@@ -0,0 +1,52 @@
+/* Copyright Altera Corporation (C) 2014. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2,
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#include <linux/module.h>
+#include <asm/delay.h>
+#include <asm/param.h>
+#include <asm/processor.h>
+#include <asm/timex.h>
+void __delay(unsigned long cycles)
+{
+        cycles_t start = get_cycles();
+        while ((get_cycles() - start) < cycles)
+                cpu_relax();
+}
+EXPORT_SYMBOL(__delay);
+void __const_udelay(unsigned long xloops)
+{
+        u64 loops;
+        loops = (u64)xloops * loops_per_jiffy * HZ;
+        __delay(loops >> 32);
+}
+EXPORT_SYMBOL(__const_udelay);
+void __udelay(unsigned long usecs)
+{
+        __const_udelay(usecs * 0x10C7UL); /* 2**32 / 1000000 (rounded up) */
+}
+EXPORT_SYMBOL(__udelay);
+void __ndelay(unsigned long nsecs)
+{
+        __const_udelay(nsecs * 0x5UL); /* 2**32 / 1000000000 (rounded up) */
+}
+EXPORT_SYMBOL(__ndelay);
diff --git a/arch/nios2/lib/memcpy.c b/arch/nios2/lib/memcpy.c
new file mode 100644
index 000000000000..1715f5d28b11
--- /dev/null
+++ b/arch/nios2/lib/memcpy.c
@@ -0,0 +1,202 @@
+/* Extracted from GLIBC memcpy.c and memcopy.h, which is:
+   Copyright (C) 1991, 1992, 1993, 1997, 2004 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Torbjorn Granlund (tege@sics.se).
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+#include <linux/types.h>
+/* Type to use for aligned memory operations.
+   This should normally be the biggest type supported by a single load
+   and store.  */
+#define op_t    unsigned long int
+#define OPSIZ   (sizeof(op_t))
+/* Optimal type for storing bytes in registers.  */
+#define reg_char        char
+#define MERGE(w0, sh_1, w1, sh_2) (((w0) >> (sh_1)) | ((w1) << (sh_2)))
+/* Copy exactly NBYTES bytes from SRC_BP to DST_BP,
+   without any assumptions about alignment of the pointers.  */
+#define BYTE_COPY_FWD(dst_bp, src_bp, nbytes)                           \
+do {                                                                    \
+        size_t __nbytes = (nbytes);                                     \
+        while (__nbytes > 0) {                                          \
+                unsigned char __x = ((unsigned char *) src_bp)[0];      \
+                src_bp += 1;                                            \
+                __nbytes -= 1;                                          \
+                ((unsigned char *) dst_bp)[0] = __x;                    \
+                dst_bp += 1;                                            \
+        }                                                               \
+} while (0)
+/* Copy *up to* NBYTES bytes from SRC_BP to DST_BP, with
+   the assumption that DST_BP is aligned on an OPSIZ multiple.  If
+   not all bytes could be easily copied, store remaining number of bytes
+   in NBYTES_LEFT, otherwise store 0.  */
+/* extern void _wordcopy_fwd_aligned __P ((long int, long int, size_t)); */
+/* extern void _wordcopy_fwd_dest_aligned __P ((long int, long int, size_t)); */
+#define WORD_COPY_FWD(dst_bp, src_bp, nbytes_left, nbytes)              \
+do {                                                                    \
+        if (src_bp % OPSIZ == 0)                                        \
+                _wordcopy_fwd_aligned(dst_bp, src_bp, (nbytes) / OPSIZ);\
+        else                                                            \
+                _wordcopy_fwd_dest_aligned(dst_bp, src_bp, (nbytes) / OPSIZ);\
+        src_bp += (nbytes) & -OPSIZ;                                    \
+        dst_bp += (nbytes) & -OPSIZ;                                    \
+        (nbytes_left) = (nbytes) % OPSIZ;                               \
+} while (0)
+/* Threshold value for when to enter the unrolled loops.  */
+#define OP_T_THRES      16
+/* _wordcopy_fwd_aligned -- Copy block beginning at SRCP to
+   block beginning at DSTP with LEN `op_t' words (not LEN bytes!).
+   Both SRCP and DSTP should be aligned for memory operations on `op_t's.  */
+/* stream-lined (read x8 + write x8) */
+static void _wordcopy_fwd_aligned(long int dstp, long int srcp, size_t len)
+{
+        while (len > 7) {
+                register op_t a0, a1, a2, a3, a4, a5, a6, a7;
+                a0 = ((op_t *) srcp)[0];
+                a1 = ((op_t *) srcp)[1];
+                a2 = ((op_t *) srcp)[2];
+                a3 = ((op_t *) srcp)[3];
+                a4 = ((op_t *) srcp)[4];
+                a5 = ((op_t *) srcp)[5];
+                a6 = ((op_t *) srcp)[6];
+                a7 = ((op_t *) srcp)[7];
+                ((op_t *) dstp)[0] = a0;
+                ((op_t *) dstp)[1] = a1;
+                ((op_t *) dstp)[2] = a2;
+                ((op_t *) dstp)[3] = a3;
+                ((op_t *) dstp)[4] = a4;
+                ((op_t *) dstp)[5] = a5;
+                ((op_t *) dstp)[6] = a6;
+                ((op_t *) dstp)[7] = a7;
+                srcp += 8 * OPSIZ;
+                dstp += 8 * OPSIZ;
+                len -= 8;
+        }
+        while (len > 0) {
+                *(op_t *)dstp = *(op_t *)srcp;
+                srcp += OPSIZ;
+                dstp += OPSIZ;
+                len -= 1;
+        }
+}
+/* _wordcopy_fwd_dest_aligned -- Copy block beginning at SRCP to
+   block beginning at DSTP with LEN `op_t' words (not LEN bytes!).
+   DSTP should be aligned for memory operations on `op_t's, but SRCP must
+   *not* be aligned.  */
+/* stream-lined (read x4 + write x4) */
+static void _wordcopy_fwd_dest_aligned(long int dstp, long int srcp,
+                                        size_t len)
+{
+        op_t ap;
+        int sh_1, sh_2;
+        /* Calculate how to shift a word read at the memory operation
+        aligned srcp to make it aligned for copy. */
+        sh_1 = 8 * (srcp % OPSIZ);
+        sh_2 = 8 * OPSIZ - sh_1;
+        /* Make SRCP aligned by rounding it down to the beginning of the `op_t'
+        it points in the middle of. */
+        srcp &= -OPSIZ;
+        ap = ((op_t *) srcp)[0];
+        srcp += OPSIZ;
+        while (len > 3) {
+                op_t a0, a1, a2, a3;
+                a0 = ((op_t *) srcp)[0];
+                a1 = ((op_t *) srcp)[1];
+                a2 = ((op_t *) srcp)[2];
+                a3 = ((op_t *) srcp)[3];
+                ((op_t *) dstp)[0] = MERGE(ap, sh_1, a0, sh_2);
+                ((op_t *) dstp)[1] = MERGE(a0, sh_1, a1, sh_2);
+                ((op_t *) dstp)[2] = MERGE(a1, sh_1, a2, sh_2);
+                ((op_t *) dstp)[3] = MERGE(a2, sh_1, a3, sh_2);
+                ap = a3;
+                srcp += 4 * OPSIZ;
+                dstp += 4 * OPSIZ;
+                len -= 4;
+        }
+        while (len > 0) {
+                register op_t a0;
+                a0 = ((op_t *) srcp)[0];
+                ((op_t *) dstp)[0] = MERGE(ap, sh_1, a0, sh_2);
+                ap = a0;
+                srcp += OPSIZ;
+                dstp += OPSIZ;
+                len -= 1;
+        }
+}
+void *memcpy(void *dstpp, const void *srcpp, size_t len)
+{
+        unsigned long int dstp = (long int) dstpp;
+        unsigned long int srcp = (long int) srcpp;
+        /* Copy from the beginning to the end.  */
+        /* If there not too few bytes to copy, use word copy.  */
+        if (len >= OP_T_THRES) {
+                /* Copy just a few bytes to make DSTP aligned.  */
+                len -= (-dstp) % OPSIZ;
+                BYTE_COPY_FWD(dstp, srcp, (-dstp) % OPSIZ);
+                /* Copy whole pages from SRCP to DSTP by virtual address
+                   manipulation, as much as possible.  */
+                /* PAGE_COPY_FWD_MAYBE (dstp, srcp, len, len); */
+                /* Copy from SRCP to DSTP taking advantage of the known
+                   alignment of DSTP. Number of bytes remaining is put in the
+                   third argument, i.e. in LEN.  This number may vary from
+                   machine to machine. */
+                WORD_COPY_FWD(dstp, srcp, len, len);
+                /* Fall out and copy the tail. */
+        }
+        /* There are just a few bytes to copy.  Use byte memory operations. */
+        BYTE_COPY_FWD(dstp, srcp, len);
+        return dstpp;
+}
+void *memcpyb(void *dstpp, const void *srcpp, unsigned len)
+{
+        unsigned long int dstp = (long int) dstpp;
+        unsigned long int srcp = (long int) srcpp;
+        BYTE_COPY_FWD(dstp, srcp, len);
+        return dstpp;
+}
diff --git a/arch/nios2/lib/memmove.c b/arch/nios2/lib/memmove.c
new file mode 100644
index 000000000000..c65ef517eb80
--- /dev/null
+++ b/arch/nios2/lib/memmove.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2004 Microtronix Datacom Ltd
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/types.h>
+#include <linux/string.h>
+#ifdef __HAVE_ARCH_MEMMOVE
+void *memmove(void *d, const void *s, size_t count)
+{
+        unsigned long dst, src;
+        if (!count)
+                return d;
+        if (d < s) {
+                dst = (unsigned long) d;
+                src = (unsigned long) s;
+                if ((count < 8) || ((dst ^ src) & 3))
+                        goto restup;
+                if (dst & 1) {
+                        *(char *)dst++ = *(char *)src++;
+                        count--;
+                }
+                if (dst & 2) {
+                        *(short *)dst = *(short *)src;
+                        src += 2;
+                        dst += 2;
+                        count -= 2;
+                }
+                while (count > 3) {
+                        *(long *)dst = *(long *)src;
+                        src += 4;
+                        dst += 4;
+                        count -= 4;
+                }
+restup:
+                while (count--)
+                        *(char *)dst++ = *(char *)src++;
+        } else {
+                dst = (unsigned long) d + count;
+                src = (unsigned long) s + count;
+                if ((count < 8) || ((dst ^ src) & 3))
+                        goto restdown;
+                if (dst & 1) {
+                        src--;
+                        dst--;
+                        count--;
+                        *(char *)dst = *(char *)src;
+                }
+                if (dst & 2) {
+                        src -= 2;
+                        dst -= 2;
+                        count -= 2;
+                        *(short *)dst = *(short *)src;
+                }
+                while (count > 3) {
+                        src -= 4;
+                        dst -= 4;
+                        count -= 4;
+                        *(long *)dst = *(long *)src;
+                }
+restdown:
+                while (count--) {
+                        src--;
+                        dst--;
+                        *(char *)dst = *(char *)src;
+                }
+        }
+        return d;
+}
+#endif /* __HAVE_ARCH_MEMMOVE */
diff --git a/arch/nios2/lib/memset.c b/arch/nios2/lib/memset.c
new file mode 100644
index 000000000000..65e97802f5cc
--- /dev/null
+++ b/arch/nios2/lib/memset.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2004 Microtronix Datacom Ltd
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/types.h>
+#include <linux/string.h>
+#ifdef __HAVE_ARCH_MEMSET
+void *memset(void *s, int c, size_t count)
+{
+        int destptr, charcnt, dwordcnt, fill8reg, wrkrega;
+        if (!count)
+                return s;
+        c &= 0xFF;
+        if (count <= 8) {
+                char *xs = (char *) s;
+                while (count--)
+                        *xs++ = c;
+                return s;
+        }
+        __asm__ __volatile__ (
+                /* fill8 %3, %5 (c & 0xff) */
+                "       slli    %4, %5, 8\n"
+                "       or      %4, %4, %5\n"
+                "       slli    %3, %4, 16\n"
+                "       or      %3, %3, %4\n"
+                /* Word-align %0 (s) if necessary */
+                "       andi    %4, %0, 0x01\n"
+                "       beq     %4, zero, 1f\n"
+                "       addi    %1, %1, -1\n"
+                "       stb     %3, 0(%0)\n"
+                "       addi    %0, %0, 1\n"
+                "1:     mov     %2, %1\n"
+                /* Dword-align %0 (s) if necessary */
+                "       andi    %4, %0, 0x02\n"
+                "       beq     %4, zero, 2f\n"
+                "       addi    %1, %1, -2\n"
+                "       sth     %3, 0(%0)\n"
+                "       addi    %0, %0, 2\n"
+                "       mov     %2, %1\n"
+                /* %1 and %2 are how many more bytes to set */
+                "2:     srli    %2, %2, 2\n"
+                /* %2 is how many dwords to set */
+                "3:     stw     %3, 0(%0)\n"
+                "       addi    %0, %0, 4\n"
+                "       addi    %2, %2, -1\n"
+                "       bne     %2, zero, 3b\n"
+                /* store residual word and/or byte if necessary */
+                "       andi    %4, %1, 0x02\n"
+                "       beq     %4, zero, 4f\n"
+                "       sth     %3, 0(%0)\n"
+                "       addi    %0, %0, 2\n"
+                /* store residual byte if necessary */
+                "4:     andi    %4, %1, 0x01\n"
+                "       beq     %4, zero, 5f\n"
+                "       stb     %3, 0(%0)\n"
+                "5:\n"
+                : "=r" (destptr),       /* %0  Output */
+                  "=r" (charcnt),       /* %1  Output */
+                  "=r" (dwordcnt),      /* %2  Output */
+                  "=r" (fill8reg),      /* %3  Output */
+                  "=r" (wrkrega)        /* %4  Output */
+                : "r" (c),              /* %5  Input */
+                  "0" (s),              /* %0  Input/Output */
+                  "1" (count)           /* %1  Input/Output */
+                : "memory"              /* clobbered */
+        );
+        return s;
+}
+#endif /* __HAVE_ARCH_MEMSET */
diff --git a/arch/nios2/mm/Makefile b/arch/nios2/mm/Makefile
new file mode 100644
index 000000000000..3cbd0840873c
--- /dev/null
+++ b/arch/nios2/mm/Makefile
@@ -0,0 +1,14 @@
+#
+# Makefile for the Nios2-specific parts of the memory manager.
+#
+obj-y   += cacheflush.o
+obj-y   += dma-mapping.o
+obj-y   += extable.o
+obj-y   += fault.o
+obj-y   += init.o
+obj-y   += ioremap.o
+obj-y   += mmu_context.o
+obj-y   += pgtable.o
+obj-y   += tlb.o
+obj-y   += uaccess.o
diff --git a/arch/nios2/mm/cacheflush.c b/arch/nios2/mm/cacheflush.c
new file mode 100644
index 000000000000..2ae482b42669
--- /dev/null
+++ b/arch/nios2/mm/cacheflush.c
@@ -0,0 +1,271 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2009, Wind River Systems Inc
+ * Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
+ */
+#include <linux/export.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/fs.h>
+#include <asm/cacheflush.h>
+#include <asm/cpuinfo.h>
+static void __flush_dcache(unsigned long start, unsigned long end)
+{
+        unsigned long addr;
+        start &= ~(cpuinfo.dcache_line_size - 1);
+        end += (cpuinfo.dcache_line_size - 1);
+        end &= ~(cpuinfo.dcache_line_size - 1);
+        if (end > start + cpuinfo.dcache_size)
+                end = start + cpuinfo.dcache_size;
+        for (addr = start; addr < end; addr += cpuinfo.dcache_line_size) {
+                __asm__ __volatile__ ("   flushda 0(%0)\n"
+                                        : /* Outputs */
+                                        : /* Inputs  */ "r"(addr)
+                                        /* : No clobber */);
+        }
+}
+static void __flush_dcache_all(unsigned long start, unsigned long end)
+{
+        unsigned long addr;
+        start &= ~(cpuinfo.dcache_line_size - 1);
+        end += (cpuinfo.dcache_line_size - 1);
+        end &= ~(cpuinfo.dcache_line_size - 1);
+        if (end > start + cpuinfo.dcache_size)
+                end = start + cpuinfo.dcache_size;
+        for (addr = start; addr < end; addr += cpuinfo.dcache_line_size) {
+                __asm__ __volatile__ ("   flushd 0(%0)\n"
+                                        : /* Outputs */
+                                        : /* Inputs  */ "r"(addr)
+                                        /* : No clobber */);
+        }
+}
+static void __invalidate_dcache(unsigned long start, unsigned long end)
+{
+        unsigned long addr;
+        start &= ~(cpuinfo.dcache_line_size - 1);
+        end += (cpuinfo.dcache_line_size - 1);
+        end &= ~(cpuinfo.dcache_line_size - 1);
+        if (end > start + cpuinfo.dcache_size)
+                end = start + cpuinfo.dcache_size;
+        for (addr = start; addr < end; addr += cpuinfo.dcache_line_size) {
+                __asm__ __volatile__ ("   initda 0(%0)\n"
+                                        : /* Outputs */
+                                        : /* Inputs  */ "r"(addr)
+                                        /* : No clobber */);
+        }
+}
+static void __flush_icache(unsigned long start, unsigned long end)
+{
+        unsigned long addr;
+        start &= ~(cpuinfo.icache_line_size - 1);
+        end += (cpuinfo.icache_line_size - 1);
+        end &= ~(cpuinfo.icache_line_size - 1);
+        if (end > start + cpuinfo.icache_size)
+                end = start + cpuinfo.icache_size;
+        for (addr = start; addr < end; addr += cpuinfo.icache_line_size) {
+                __asm__ __volatile__ ("   flushi %0\n"
+                                        : /* Outputs */
+                                        : /* Inputs  */ "r"(addr)
+                                        /* : No clobber */);
+        }
+        __asm__ __volatile(" flushp\n");
+}
+static void flush_aliases(struct address_space *mapping, struct page *page)
+{
+        struct mm_struct *mm = current->active_mm;
+        struct vm_area_struct *mpnt;
+        pgoff_t pgoff;
+        pgoff = page->index;
+        flush_dcache_mmap_lock(mapping);
+        vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) {
+                unsigned long offset;
+                if (mpnt->vm_mm != mm)
+                        continue;
+                if (!(mpnt->vm_flags & VM_MAYSHARE))
+                        continue;
+                offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
+                flush_cache_page(mpnt, mpnt->vm_start + offset,
+                        page_to_pfn(page));
+        }
+        flush_dcache_mmap_unlock(mapping);
+}
+void flush_cache_all(void)
+{
+        __flush_dcache_all(0, cpuinfo.dcache_size);
+        __flush_icache(0, cpuinfo.icache_size);
+}
+void flush_cache_mm(struct mm_struct *mm)
+{
+        flush_cache_all();
+}
+void flush_cache_dup_mm(struct mm_struct *mm)
+{
+        flush_cache_all();
+}
+void flush_icache_range(unsigned long start, unsigned long end)
+{
+        __flush_icache(start, end);
+}
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+        __flush_dcache(start, end);
+}
+EXPORT_SYMBOL(flush_dcache_range);
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+        __invalidate_dcache(start, end);
+}
+EXPORT_SYMBOL(invalidate_dcache_range);
+void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
+                        unsigned long end)
+{
+        __flush_dcache(start, end);
+        if (vma == NULL || (vma->vm_flags & VM_EXEC))
+                __flush_icache(start, end);
+}
+void flush_icache_page(struct vm_area_struct *vma, struct page *page)
+{
+        unsigned long start = (unsigned long) page_address(page);
+        unsigned long end = start + PAGE_SIZE;
+        __flush_icache(start, end);
+}
+void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
+                        unsigned long pfn)
+{
+        unsigned long start = vmaddr;
+        unsigned long end = start + PAGE_SIZE;
+        __flush_dcache(start, end);
+        if (vma->vm_flags & VM_EXEC)
+                __flush_icache(start, end);
+}
+void flush_dcache_page(struct page *page)
+{
+        struct address_space *mapping;
+        /*
+         * The zero page is never written to, so never has any dirty
+         * cache lines, and therefore never needs to be flushed.
+         */
+        if (page == ZERO_PAGE(0))
+                return;
+        mapping = page_mapping(page);
+        /* Flush this page if there are aliases. */
+        if (mapping && !mapping_mapped(mapping)) {
+                clear_bit(PG_dcache_clean, &page->flags);
+        } else {
+                unsigned long start = (unsigned long)page_address(page);
+                __flush_dcache_all(start, start + PAGE_SIZE);
+                if (mapping)
+                        flush_aliases(mapping,  page);
+                set_bit(PG_dcache_clean, &page->flags);
+        }
+}
+EXPORT_SYMBOL(flush_dcache_page);
+void update_mmu_cache(struct vm_area_struct *vma,
+                      unsigned long address, pte_t *pte)
+{
+        unsigned long pfn = pte_pfn(*pte);
+        struct page *page;
+        if (!pfn_valid(pfn))
+                return;
+        /*
+        * The zero page is never written to, so never has any dirty
+        * cache lines, and therefore never needs to be flushed.
+        */
+        page = pfn_to_page(pfn);
+        if (page == ZERO_PAGE(0))
+                return;
+        if (!PageReserved(page) &&
+             !test_and_set_bit(PG_dcache_clean, &page->flags)) {
+                unsigned long start = page_to_virt(page);
+                struct address_space *mapping;
+                __flush_dcache(start, start + PAGE_SIZE);
+                mapping = page_mapping(page);
+                if (mapping)
+                        flush_aliases(mapping, page);
+        }
+}
+void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
+                    struct page *to)
+{
+        __flush_dcache(vaddr, vaddr + PAGE_SIZE);
+        copy_page(vto, vfrom);
+        __flush_dcache((unsigned long)vto, (unsigned long)vto + PAGE_SIZE);
+}
+void clear_user_page(void *addr, unsigned long vaddr, struct page *page)
+{
+        __flush_dcache(vaddr, vaddr + PAGE_SIZE);
+        clear_page(addr);
+        __flush_dcache((unsigned long)addr, (unsigned long)addr + PAGE_SIZE);
+}
+void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
+                        unsigned long user_vaddr,
+                        void *dst, void *src, int len)
+{
+        flush_cache_page(vma, user_vaddr, page_to_pfn(page));
+        memcpy(dst, src, len);
+        __flush_dcache((unsigned long)src, (unsigned long)src + len);
+        if (vma->vm_flags & VM_EXEC)
+                __flush_icache((unsigned long)src, (unsigned long)src + len);
+}
+void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
+                        unsigned long user_vaddr,
+                        void *dst, void *src, int len)
+{
+        flush_cache_page(vma, user_vaddr, page_to_pfn(page));
+        memcpy(dst, src, len);
+        __flush_dcache((unsigned long)dst, (unsigned long)dst + len);
+        if (vma->vm_flags & VM_EXEC)
+                __flush_icache((unsigned long)dst, (unsigned long)dst + len);
+}
diff --git a/arch/nios2/mm/dma-mapping.c b/arch/nios2/mm/dma-mapping.c
new file mode 100644
index 000000000000..ac5da7594f0b
--- /dev/null
+++ b/arch/nios2/mm/dma-mapping.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2009 Wind River Systems Inc
+ *  Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
+ *
+ * Based on DMA code from MIPS.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/export.h>
+#include <linux/string.h>
+#include <linux/scatterlist.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+#include <linux/cache.h>
+#include <asm/cacheflush.h>
+void *dma_alloc_coherent(struct device *dev, size_t size,
+                            dma_addr_t *dma_handle, gfp_t gfp)
+{
+        void *ret;
+        /* ignore region specifiers */
+        gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
+        /* optimized page clearing */
+        gfp |= __GFP_ZERO;
+        if (dev == NULL || (dev->coherent_dma_mask < 0xffffffff))
+                gfp |= GFP_DMA;
+        ret = (void *) __get_free_pages(gfp, get_order(size));
+        if (ret != NULL) {
+                *dma_handle = virt_to_phys(ret);
+                flush_dcache_range((unsigned long) ret,
+                        (unsigned long) ret + size);
+                ret = UNCAC_ADDR(ret);
+        }
+        return ret;
+}
+EXPORT_SYMBOL(dma_alloc_coherent);
+void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
+                        dma_addr_t dma_handle)
+{
+        unsigned long addr = (unsigned long) CAC_ADDR((unsigned long) vaddr);
+        free_pages(addr, get_order(size));
+}
+EXPORT_SYMBOL(dma_free_coherent);
+int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
+                enum dma_data_direction direction)
+{
+        int i;
+        BUG_ON(!valid_dma_direction(direction));
+        for_each_sg(sg, sg, nents, i) {
+                void *addr;
+                addr = sg_virt(sg);
+                if (addr) {
+                        __dma_sync_for_device(addr, sg->length, direction);
+                        sg->dma_address = sg_phys(sg);
+                }
+        }
+        return nents;
+}
+EXPORT_SYMBOL(dma_map_sg);
+dma_addr_t dma_map_page(struct device *dev, struct page *page,
+                        unsigned long offset, size_t size,
+                        enum dma_data_direction direction)
+{
+        void *addr;
+        BUG_ON(!valid_dma_direction(direction));
+        addr = page_address(page) + offset;
+        __dma_sync_for_device(addr, size, direction);
+        return page_to_phys(page) + offset;
+}
+EXPORT_SYMBOL(dma_map_page);
+void dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
+                    enum dma_data_direction direction)
+{
+        BUG_ON(!valid_dma_direction(direction));
+        __dma_sync_for_cpu(phys_to_virt(dma_address), size, direction);
+}
+EXPORT_SYMBOL(dma_unmap_page);
+void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
+                  enum dma_data_direction direction)
+{
+        void *addr;
+        int i;
+        BUG_ON(!valid_dma_direction(direction));
+        if (direction == DMA_TO_DEVICE)
+                return;
+        for_each_sg(sg, sg, nhwentries, i) {
+                addr = sg_virt(sg);
+                if (addr)
+                        __dma_sync_for_cpu(addr, sg->length, direction);
+        }
+}
+EXPORT_SYMBOL(dma_unmap_sg);
+void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
+                             size_t size, enum dma_data_direction direction)
+{
+        BUG_ON(!valid_dma_direction(direction));
+        __dma_sync_for_cpu(phys_to_virt(dma_handle), size, direction);
+}
+EXPORT_SYMBOL(dma_sync_single_for_cpu);
+void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
+                                size_t size, enum dma_data_direction direction)
+{
+        BUG_ON(!valid_dma_direction(direction));
+        __dma_sync_for_device(phys_to_virt(dma_handle), size, direction);
+}
+EXPORT_SYMBOL(dma_sync_single_for_device);
+void dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
+                                        unsigned long offset, size_t size,
+                                        enum dma_data_direction direction)
+{
+        BUG_ON(!valid_dma_direction(direction));
+        __dma_sync_for_cpu(phys_to_virt(dma_handle), size, direction);
+}
+EXPORT_SYMBOL(dma_sync_single_range_for_cpu);
+void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
+                                        unsigned long offset, size_t size,
+                                        enum dma_data_direction direction)
+{
+        BUG_ON(!valid_dma_direction(direction));
+        __dma_sync_for_device(phys_to_virt(dma_handle), size, direction);
+}
+EXPORT_SYMBOL(dma_sync_single_range_for_device);
+void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
+                         enum dma_data_direction direction)
+{
+        int i;
+        BUG_ON(!valid_dma_direction(direction));
+        /* Make sure that gcc doesn't leave the empty loop body.  */
+        for_each_sg(sg, sg, nelems, i)
+                __dma_sync_for_cpu(sg_virt(sg), sg->length, direction);
+}
+EXPORT_SYMBOL(dma_sync_sg_for_cpu);
+void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
+                                int nelems, enum dma_data_direction direction)
+{
+        int i;
+        BUG_ON(!valid_dma_direction(direction));
+        /* Make sure that gcc doesn't leave the empty loop body.  */
+        for_each_sg(sg, sg, nelems, i)
+                __dma_sync_for_device(sg_virt(sg), sg->length, direction);
+}
+EXPORT_SYMBOL(dma_sync_sg_for_device);
diff --git a/arch/nios2/mm/extable.c b/arch/nios2/mm/extable.c
new file mode 100644
index 000000000000..4d2fc5a589d0
--- /dev/null
+++ b/arch/nios2/mm/extable.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2010, Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2009, Wind River Systems Inc
+ *   Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/module.h>
+#include <linux/uaccess.h>
+int fixup_exception(struct pt_regs *regs)
+{
+        const struct exception_table_entry *fixup;
+        fixup = search_exception_tables(regs->ea);
+        if (fixup) {
+                regs->ea = fixup->fixup;
+                return 1;
+        }
+        return 0;
+}
diff --git a/arch/nios2/mm/fault.c b/arch/nios2/mm/fault.c
new file mode 100644
index 000000000000..15a0bb5fc06d
--- /dev/null
+++ b/arch/nios2/mm/fault.c
@@ -0,0 +1,251 @@
+/*
+ * Copyright (C) 2009 Wind River Systems Inc
+ *   Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
+ *
+ * based on arch/mips/mm/fault.c which is:
+ *
+ * Copyright (C) 1995-2000 Ralf Baechle
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <linux/ptrace.h>
+#include <linux/mman.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/uaccess.h>
+#include <linux/ptrace.h>
+#include <asm/mmu_context.h>
+#include <asm/traps.h>
+#define EXC_SUPERV_INSN_ACCESS  9  /* Supervisor only instruction address */
+#define EXC_SUPERV_DATA_ACCESS  11 /* Supervisor only data address */
+#define EXC_X_PROTECTION_FAULT  13 /* TLB permission violation (x) */
+#define EXC_R_PROTECTION_FAULT  14 /* TLB permission violation (r) */
+#define EXC_W_PROTECTION_FAULT  15 /* TLB permission violation (w) */
+/*
+ * This routine handles page faults.  It determines the address,
+ * and the problem, and then passes it off to one of the appropriate
+ * routines.
+ */
+asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long cause,
+                                unsigned long address)
+{
+        struct vm_area_struct *vma = NULL;
+        struct task_struct *tsk = current;
+        struct mm_struct *mm = tsk->mm;
+        int code = SEGV_MAPERR;
+        int fault;
+        unsigned int flags = 0;
+        cause >>= 2;
+        /* Restart the instruction */
+        regs->ea -= 4;
+        /*
+         * We fault-in kernel-space virtual memory on-demand. The
+         * 'reference' page table is init_mm.pgd.
+         *
+         * NOTE! We MUST NOT take any locks for this case. We may
+         * be in an interrupt or a critical region, and should
+         * only copy the information from the master page table,
+         * nothing more.
+         */
+        if (unlikely(address >= VMALLOC_START && address <= VMALLOC_END)) {
+                if (user_mode(regs))
+                        goto bad_area_nosemaphore;
+                else
+                        goto vmalloc_fault;
+        }
+        if (unlikely(address >= TASK_SIZE))
+                goto bad_area_nosemaphore;
+        /*
+         * If we're in an interrupt or have no user
+         * context, we must not take the fault..
+         */
+        if (in_atomic() || !mm)
+                goto bad_area_nosemaphore;
+        if (user_mode(regs))
+                flags |= FAULT_FLAG_USER;
+        if (!down_read_trylock(&mm->mmap_sem)) {
+                if (!user_mode(regs) && !search_exception_tables(regs->ea))
+                        goto bad_area_nosemaphore;
+                down_read(&mm->mmap_sem);
+        }
+        vma = find_vma(mm, address);
+        if (!vma)
+                goto bad_area;
+        if (vma->vm_start <= address)
+                goto good_area;
+        if (!(vma->vm_flags & VM_GROWSDOWN))
+                goto bad_area;
+        if (expand_stack(vma, address))
+                goto bad_area;
+/*
+ * Ok, we have a good vm_area for this memory access, so
+ * we can handle it..
+ */
+good_area:
+        code = SEGV_ACCERR;
+        switch (cause) {
+        case EXC_SUPERV_INSN_ACCESS:
+                goto bad_area;
+        case EXC_SUPERV_DATA_ACCESS:
+                goto bad_area;
+        case EXC_X_PROTECTION_FAULT:
+                if (!(vma->vm_flags & VM_EXEC))
+                        goto bad_area;
+                break;
+        case EXC_R_PROTECTION_FAULT:
+                if (!(vma->vm_flags & VM_READ))
+                        goto bad_area;
+                break;
+        case EXC_W_PROTECTION_FAULT:
+                if (!(vma->vm_flags & VM_WRITE))
+                        goto bad_area;
+                flags = FAULT_FLAG_WRITE;
+                break;
+        }
+survive:
+        /*
+         * If for any reason at all we couldn't handle the fault,
+         * make sure we exit gracefully rather than endlessly redo
+         * the fault.
+         */
+        fault = handle_mm_fault(mm, vma, address, flags);
+        if (unlikely(fault & VM_FAULT_ERROR)) {
+                if (fault & VM_FAULT_OOM)
+                        goto out_of_memory;
+                else if (fault & VM_FAULT_SIGBUS)
+                        goto do_sigbus;
+                BUG();
+        }
+        if (fault & VM_FAULT_MAJOR)
+                tsk->maj_flt++;
+        else
+                tsk->min_flt++;
+        up_read(&mm->mmap_sem);
+        return;
+/*
+ * Something tried to access memory that isn't in our memory map..
+ * Fix it, but check if it's kernel or user first..
+ */
+bad_area:
+        up_read(&mm->mmap_sem);
+bad_area_nosemaphore:
+        /* User mode accesses just cause a SIGSEGV */
+        if (user_mode(regs)) {
+                pr_alert("%s: unhandled page fault (%d) at 0x%08lx, "
+                        "cause %ld\n", current->comm, SIGSEGV, address, cause);
+                show_regs(regs);
+                _exception(SIGSEGV, regs, code, address);
+                return;
+        }
+no_context:
+        /* Are we prepared to handle this kernel fault? */
+        if (fixup_exception(regs))
+                return;
+        /*
+         * Oops. The kernel tried to access some bad page. We'll have to
+         * terminate things with extreme prejudice.
+         */
+        bust_spinlocks(1);
+        pr_alert("Unable to handle kernel %s at virtual address %08lx",
+                address < PAGE_SIZE ? "NULL pointer dereference" :
+                "paging request", address);
+        pr_alert("ea = %08lx, ra = %08lx, cause = %ld\n", regs->ea, regs->ra,
+                cause);
+        panic("Oops");
+        return;
+/*
+ * We ran out of memory, or some other thing happened to us that made
+ * us unable to handle the page fault gracefully.
+ */
+out_of_memory:
+        up_read(&mm->mmap_sem);
+        if (is_global_init(tsk)) {
+                yield();
+                down_read(&mm->mmap_sem);
+                goto survive;
+        }
+        if (!user_mode(regs))
+                goto no_context;
+        pagefault_out_of_memory();
+        return;
+do_sigbus:
+        up_read(&mm->mmap_sem);
+        /* Kernel mode? Handle exceptions or die */
+        if (!user_mode(regs))
+                goto no_context;
+        _exception(SIGBUS, regs, BUS_ADRERR, address);
+        return;
+vmalloc_fault:
+        {
+                /*
+                 * Synchronize this task's top level page-table
+                 * with the 'reference' page table.
+                 *
+                 * Do _not_ use "tsk" here. We might be inside
+                 * an interrupt in the middle of a task switch..
+                 */
+                int offset = pgd_index(address);
+                pgd_t *pgd, *pgd_k;
+                pud_t *pud, *pud_k;
+                pmd_t *pmd, *pmd_k;
+                pte_t *pte_k;
+                pgd = pgd_current + offset;
+                pgd_k = init_mm.pgd + offset;
+                if (!pgd_present(*pgd_k))
+                        goto no_context;
+                set_pgd(pgd, *pgd_k);
+                pud = pud_offset(pgd, address);
+                pud_k = pud_offset(pgd_k, address);
+                if (!pud_present(*pud_k))
+                        goto no_context;
+                pmd = pmd_offset(pud, address);
+                pmd_k = pmd_offset(pud_k, address);
+                if (!pmd_present(*pmd_k))
+                        goto no_context;
+                set_pmd(pmd, *pmd_k);
+                pte_k = pte_offset_kernel(pmd_k, address);
+                if (!pte_present(*pte_k))
+                        goto no_context;
+                flush_tlb_one(address);
+                return;
+        }
+}
diff --git a/arch/nios2/mm/init.c b/arch/nios2/mm/init.c
new file mode 100644
index 000000000000..e75c75d249d6
--- /dev/null
+++ b/arch/nios2/mm/init.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2009 Wind River Systems Inc
+ *   Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
+ * Copyright (C) 2004 Microtronix Datacom Ltd
+ *
+ * based on arch/m68k/mm/init.c
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <linux/ptrace.h>
+#include <linux/mman.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/pagemap.h>
+#include <linux/bootmem.h>
+#include <linux/slab.h>
+#include <linux/binfmts.h>
+#include <asm/setup.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/sections.h>
+#include <asm/tlb.h>
+#include <asm/mmu_context.h>
+#include <asm/cpuinfo.h>
+#include <asm/processor.h>
+pgd_t *pgd_current;
+/*
+ * paging_init() continues the virtual memory environment setup which
+ * was begun by the code in arch/head.S.
+ * The parameters are pointers to where to stick the starting and ending
+ * addresses of available kernel virtual memory.
+ */
+void __init paging_init(void)
+{
+        unsigned long zones_size[MAX_NR_ZONES];
+        memset(zones_size, 0, sizeof(zones_size));
+        pagetable_init();
+        pgd_current = swapper_pg_dir;
+        zones_size[ZONE_NORMAL] = max_mapnr;
+        /* pass the memory from the bootmem allocator to the main allocator */
+        free_area_init(zones_size);
+        flush_dcache_range((unsigned long)empty_zero_page,
+                        (unsigned long)empty_zero_page + PAGE_SIZE);
+}
+void __init mem_init(void)
+{
+        unsigned long end_mem   = memory_end; /* this must not include
+                                                kernel stack at top */
+        pr_debug("mem_init: start=%lx, end=%lx\n", memory_start, memory_end);
+        end_mem &= PAGE_MASK;
+        high_memory = __va(end_mem);
+        /* this will put all memory onto the freelists */
+        free_all_bootmem();
+        mem_init_print_info(NULL);
+}
+void __init mmu_init(void)
+{
+        flush_tlb_all();
+}
+#ifdef CONFIG_BLK_DEV_INITRD
+void __init free_initrd_mem(unsigned long start, unsigned long end)
+{
+        free_reserved_area((void *)start, (void *)end, -1, "initrd");
+}
+#endif
+void __init_refok free_initmem(void)
+{
+        free_initmem_default(-1);
+}
+#define __page_aligned(order) __aligned(PAGE_SIZE << (order))
+pgd_t swapper_pg_dir[PTRS_PER_PGD] __page_aligned(PGD_ORDER);
+pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned(PTE_ORDER);
+static struct page *kuser_page[1];
+static int alloc_kuser_page(void)
+{
+        extern char __kuser_helper_start[], __kuser_helper_end[];
+        int kuser_sz = __kuser_helper_end - __kuser_helper_start;
+        unsigned long vpage;
+        vpage = get_zeroed_page(GFP_ATOMIC);
+        if (!vpage)
+                return -ENOMEM;
+        /* Copy kuser helpers */
+        memcpy((void *)vpage, __kuser_helper_start, kuser_sz);
+        flush_icache_range(vpage, vpage + KUSER_SIZE);
+        kuser_page[0] = virt_to_page(vpage);
+        return 0;
+}
+arch_initcall(alloc_kuser_page);
+int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
+{
+        struct mm_struct *mm = current->mm;
+        int ret;
+        down_write(&mm->mmap_sem);
+        /* Map kuser helpers to user space address */
+        ret = install_special_mapping(mm, KUSER_BASE, KUSER_SIZE,
+                                      VM_READ | VM_EXEC | VM_MAYREAD |
+                                      VM_MAYEXEC, kuser_page);
+        up_write(&mm->mmap_sem);
+        return ret;
+}
+const char *arch_vma_name(struct vm_area_struct *vma)
+{
+        return (vma->vm_start == KUSER_BASE) ? "[kuser]" : NULL;
+}
diff --git a/arch/nios2/mm/ioremap.c b/arch/nios2/mm/ioremap.c
new file mode 100644
index 000000000000..3a28177a01eb
--- /dev/null
+++ b/arch/nios2/mm/ioremap.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2009 Wind River Systems Inc
+ *   Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
+ * Copyright (C) 2004 Microtronix Datacom Ltd.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/export.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/io.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+static inline void remap_area_pte(pte_t *pte, unsigned long address,
+                                unsigned long size, unsigned long phys_addr,
+                                unsigned long flags)
+{
+        unsigned long end;
+        unsigned long pfn;
+        pgprot_t pgprot = __pgprot(_PAGE_GLOBAL | _PAGE_PRESENT | _PAGE_READ
+                                | _PAGE_WRITE | flags);
+        address &= ~PMD_MASK;
+        end = address + size;
+        if (end > PMD_SIZE)
+                end = PMD_SIZE;
+        if (address >= end)
+                BUG();
+        pfn = PFN_DOWN(phys_addr);
+        do {
+                if (!pte_none(*pte)) {
+                        pr_err("remap_area_pte: page already exists\n");
+                        BUG();
+                }
+                set_pte(pte, pfn_pte(pfn, pgprot));
+                address += PAGE_SIZE;
+                pfn++;
+                pte++;
+        } while (address && (address < end));
+}
+static inline int remap_area_pmd(pmd_t *pmd, unsigned long address,
+                                unsigned long size, unsigned long phys_addr,
+                                unsigned long flags)
+{
+        unsigned long end;
+        address &= ~PGDIR_MASK;
+        end = address + size;
+        if (end > PGDIR_SIZE)
+                end = PGDIR_SIZE;
+        phys_addr -= address;
+        if (address >= end)
+                BUG();
+        do {
+                pte_t *pte = pte_alloc_kernel(pmd, address);
+                if (!pte)
+                        return -ENOMEM;
+                remap_area_pte(pte, address, end - address, address + phys_addr,
+                        flags);
+                address = (address + PMD_SIZE) & PMD_MASK;
+                pmd++;
+        } while (address && (address < end));
+        return 0;
+}
+static int remap_area_pages(unsigned long address, unsigned long phys_addr,
+                                unsigned long size, unsigned long flags)
+{
+        int error;
+        pgd_t *dir;
+        unsigned long end = address + size;
+        phys_addr -= address;
+        dir = pgd_offset(&init_mm, address);
+        flush_cache_all();
+        if (address >= end)
+                BUG();
+        do {
+                pud_t *pud;
+                pmd_t *pmd;
+                error = -ENOMEM;
+                pud = pud_alloc(&init_mm, dir, address);
+                if (!pud)
+                        break;
+                pmd = pmd_alloc(&init_mm, pud, address);
+                if (!pmd)
+                        break;
+                if (remap_area_pmd(pmd, address, end - address,
+                        phys_addr + address, flags))
+                        break;
+                error = 0;
+                address = (address + PGDIR_SIZE) & PGDIR_MASK;
+                dir++;
+        } while (address && (address < end));
+        flush_tlb_all();
+        return error;
+}
+#define IS_MAPPABLE_UNCACHEABLE(addr) (addr < 0x20000000UL)
+/*
+ * Map some physical address range into the kernel address space.
+ */
+void __iomem *__ioremap(unsigned long phys_addr, unsigned long size,
+                        unsigned long cacheflag)
+{
+        struct vm_struct *area;
+        unsigned long offset;
+        unsigned long last_addr;
+        void *addr;
+        /* Don't allow wraparound or zero size */
+        last_addr = phys_addr + size - 1;
+        if (!size || last_addr < phys_addr)
+                return NULL;
+        /* Don't allow anybody to remap normal RAM that we're using */
+        if (phys_addr > PHYS_OFFSET && phys_addr < virt_to_phys(high_memory)) {
+                char *t_addr, *t_end;
+                struct page *page;
+                t_addr = __va(phys_addr);
+                t_end = t_addr + (size - 1);
+                for (page = virt_to_page(t_addr);
+                        page <= virt_to_page(t_end); page++)
+                        if (!PageReserved(page))
+                                return NULL;
+        }
+        /*
+         * Map uncached objects in the low part of address space to
+         * CONFIG_NIOS2_IO_REGION_BASE
+         */
+        if (IS_MAPPABLE_UNCACHEABLE(phys_addr) &&
+            IS_MAPPABLE_UNCACHEABLE(last_addr) &&
+            !(cacheflag & _PAGE_CACHED))
+                return (void __iomem *)(CONFIG_NIOS2_IO_REGION_BASE + phys_addr);
+        /* Mappings have to be page-aligned */
+        offset = phys_addr & ~PAGE_MASK;
+        phys_addr &= PAGE_MASK;
+        size = PAGE_ALIGN(last_addr + 1) - phys_addr;
+        /* Ok, go for it */
+        area = get_vm_area(size, VM_IOREMAP);
+        if (!area)
+                return NULL;
+        addr = area->addr;
+        if (remap_area_pages((unsigned long) addr, phys_addr, size,
+                cacheflag)) {
+                vunmap(addr);
+                return NULL;
+        }
+        return (void __iomem *) (offset + (char *)addr);
+}
+EXPORT_SYMBOL(__ioremap);
+/*
+ * __iounmap unmaps nearly everything, so be careful
+ * it doesn't free currently pointer/page tables anymore but it
+ * wasn't used anyway and might be added later.
+ */
+void __iounmap(void __iomem *addr)
+{
+        struct vm_struct *p;
+        if ((unsigned long) addr > CONFIG_NIOS2_IO_REGION_BASE)
+                return;
+        p = remove_vm_area((void *) (PAGE_MASK & (unsigned long __force) addr));
+        if (!p)
+                pr_err("iounmap: bad address %p\n", addr);
+        kfree(p);
+}
+EXPORT_SYMBOL(__iounmap);
diff --git a/arch/nios2/mm/mmu_context.c b/arch/nios2/mm/mmu_context.c
new file mode 100644
index 000000000000..45d6b9c58d67
--- /dev/null
+++ b/arch/nios2/mm/mmu_context.c
@@ -0,0 +1,116 @@
+/*
+ * MMU context handling.
+ *
+ * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
+ * Copyright (C) 2009 Wind River Systems Inc
+ *   Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/mm.h>
+#include <asm/cpuinfo.h>
+#include <asm/mmu_context.h>
+#include <asm/tlb.h>
+/* The pids position and mask in context */
+#define PID_SHIFT       0
+#define PID_BITS        (cpuinfo.tlb_pid_num_bits)
+#define PID_MASK        ((1UL << PID_BITS) - 1)
+/* The versions position and mask in context */
+#define VERSION_BITS    (32 - PID_BITS)
+#define VERSION_SHIFT   (PID_SHIFT + PID_BITS)
+#define VERSION_MASK    ((1UL << VERSION_BITS) - 1)
+/* Return the version part of a context */
+#define CTX_VERSION(c)  (((c) >> VERSION_SHIFT) & VERSION_MASK)
+/* Return the pid part of a context */
+#define CTX_PID(c)      (((c) >> PID_SHIFT) & PID_MASK)
+/* Value of the first context (version 1, pid 0) */
+#define FIRST_CTX       ((1UL << VERSION_SHIFT) | (0 << PID_SHIFT))
+static mm_context_t next_mmu_context;
+/*
+ * Initialize MMU context management stuff.
+ */
+void __init mmu_context_init(void)
+{
+        /* We need to set this here because the value depends on runtime data
+         * from cpuinfo */
+        next_mmu_context = FIRST_CTX;
+}
+/*
+ * Set new context (pid), keep way
+ */
+static void set_context(mm_context_t context)
+{
+        set_mmu_pid(CTX_PID(context));
+}
+static mm_context_t get_new_context(void)
+{
+        /* Return the next pid */
+        next_mmu_context += (1UL << PID_SHIFT);
+        /* If the pid field wraps around we increase the version and
+         * flush the tlb */
+        if (unlikely(CTX_PID(next_mmu_context) == 0)) {
+                /* Version is incremented since the pid increment above
+                 * overflows info version */
+                flush_cache_all();
+                flush_tlb_all();
+        }
+        /* If the version wraps we start over with the first generation, we do
+         * not need to flush the tlb here since it's always done above */
+        if (unlikely(CTX_VERSION(next_mmu_context) == 0))
+                next_mmu_context = FIRST_CTX;
+        return next_mmu_context;
+}
+void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+               struct task_struct *tsk)
+{
+        unsigned long flags;
+        local_irq_save(flags);
+        /* If the process context we are swapping in has a different context
+         * generation then we have it should get a new generation/pid */
+        if (unlikely(CTX_VERSION(next->context) !=
+                CTX_VERSION(next_mmu_context)))
+                next->context = get_new_context();
+        /* Save the current pgd so the fast tlb handler can find it */
+        pgd_current = next->pgd;
+        /* Set the current context */
+        set_context(next->context);
+        local_irq_restore(flags);
+}
+/*
+ * After we have set current->mm to a new value, this activates
+ * the context for the new mm so we see the new mappings.
+ */
+void activate_mm(struct mm_struct *prev, struct mm_struct *next)
+{
+        next->context = get_new_context();
+        set_context(next->context);
+        pgd_current = next->pgd;
+}
+unsigned long get_pid_from_context(mm_context_t *context)
+{
+        return CTX_PID((*context));
+}
diff --git a/arch/nios2/mm/pgtable.c b/arch/nios2/mm/pgtable.c
new file mode 100644
index 000000000000..61e24a25f71a
--- /dev/null
+++ b/arch/nios2/mm/pgtable.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2009 Wind River Systems Inc
+ *   Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <asm/pgtable.h>
+#include <asm/cpuinfo.h>
+/* pteaddr:
+ *   ptbase | vpn* | zero
+ *   31-22  | 21-2 | 1-0
+ *
+ *   *vpn is preserved on double fault
+ *
+ * tlbacc:
+ *   IG   |*flags| pfn
+ *   31-25|24-20 | 19-0
+ *
+ *   *crwxg
+ *
+ * tlbmisc:
+ *   resv  |way   |rd | we|pid |dbl|bad|perm|d
+ *   31-24 |23-20 |19 | 20|17-4|3  |2  |1   |0
+ *
+ */
+/*
+ * Initialize a new pgd / pmd table with invalid pointers.
+ */
+static void pgd_init(pgd_t *pgd)
+{
+        unsigned long *p = (unsigned long *) pgd;
+        int i;
+        for (i = 0; i < USER_PTRS_PER_PGD; i += 8) {
+                p[i + 0] = (unsigned long) invalid_pte_table;
+                p[i + 1] = (unsigned long) invalid_pte_table;
+                p[i + 2] = (unsigned long) invalid_pte_table;
+                p[i + 3] = (unsigned long) invalid_pte_table;
+                p[i + 4] = (unsigned long) invalid_pte_table;
+                p[i + 5] = (unsigned long) invalid_pte_table;
+                p[i + 6] = (unsigned long) invalid_pte_table;
+                p[i + 7] = (unsigned long) invalid_pte_table;
+        }
+}
+pgd_t *pgd_alloc(struct mm_struct *mm)
+{
+        pgd_t *ret, *init;
+        ret = (pgd_t *) __get_free_pages(GFP_KERNEL, PGD_ORDER);
+        if (ret) {
+                init = pgd_offset(&init_mm, 0UL);
+                pgd_init(ret);
+                memcpy(ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
+                       (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
+        }
+        return ret;
+}
+void __init pagetable_init(void)
+{
+        /* Initialize the entire pgd.  */
+        pgd_init(swapper_pg_dir);
+        pgd_init(swapper_pg_dir + USER_PTRS_PER_PGD);
+}
diff --git a/arch/nios2/mm/tlb.c b/arch/nios2/mm/tlb.c
new file mode 100644
index 000000000000..cf10326aab1c
--- /dev/null
+++ b/arch/nios2/mm/tlb.c
@@ -0,0 +1,275 @@
+/*
+ * Nios2 TLB handling
+ *
+ * Copyright (C) 2009, Wind River Systems Inc
+ *   Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/pagemap.h>
+#include <asm/tlb.h>
+#include <asm/mmu_context.h>
+#include <asm/pgtable.h>
+#include <asm/cpuinfo.h>
+#define TLB_INDEX_MASK          \
+        ((((1UL << (cpuinfo.tlb_ptr_sz - cpuinfo.tlb_num_ways_log2))) - 1) \
+                << PAGE_SHIFT)
+/* Used as illegal PHYS_ADDR for TLB mappings
+ */
+#define MAX_PHYS_ADDR 0
+static void get_misc_and_pid(unsigned long *misc, unsigned long *pid)
+{
+        *misc  = RDCTL(CTL_TLBMISC);
+        *misc &= (TLBMISC_PID | TLBMISC_WAY);
+        *pid  = *misc & TLBMISC_PID;
+}
+/*
+ * All entries common to a mm share an asid.  To effectively flush these
+ * entries, we just bump the asid.
+ */
+void flush_tlb_mm(struct mm_struct *mm)
+{
+        if (current->mm == mm)
+                flush_tlb_all();
+        else
+                memset(&mm->context, 0, sizeof(mm_context_t));
+}
+/*
+ * This one is only used for pages with the global bit set so we don't care
+ * much about the ASID.
+ */
+void flush_tlb_one_pid(unsigned long addr, unsigned long mmu_pid)
+{
+        unsigned int way;
+        unsigned long org_misc, pid_misc;
+        pr_debug("Flush tlb-entry for vaddr=%#lx\n", addr);
+        /* remember pid/way until we return. */
+        get_misc_and_pid(&org_misc, &pid_misc);
+        WRCTL(CTL_PTEADDR, (addr >> PAGE_SHIFT) << 2);
+        for (way = 0; way < cpuinfo.tlb_num_ways; way++) {
+                unsigned long pteaddr;
+                unsigned long tlbmisc;
+                unsigned long pid;
+                tlbmisc = pid_misc | TLBMISC_RD | (way << TLBMISC_WAY_SHIFT);
+                WRCTL(CTL_TLBMISC, tlbmisc);
+                pteaddr = RDCTL(CTL_PTEADDR);
+                tlbmisc = RDCTL(CTL_TLBMISC);
+                pid = (tlbmisc >> TLBMISC_PID_SHIFT) & TLBMISC_PID_MASK;
+                if (((((pteaddr >> 2) & 0xfffff)) == (addr >> PAGE_SHIFT)) &&
+                                pid == mmu_pid) {
+                        unsigned long vaddr = CONFIG_NIOS2_IO_REGION_BASE +
+                                ((PAGE_SIZE * cpuinfo.tlb_num_lines) * way) +
+                                (addr & TLB_INDEX_MASK);
+                        pr_debug("Flush entry by writing %#lx way=%dl pid=%ld\n",
+                                vaddr, way, (pid_misc >> TLBMISC_PID_SHIFT));
+                        WRCTL(CTL_PTEADDR, (vaddr >> 12) << 2);
+                        tlbmisc = pid_misc | TLBMISC_WE |
+                                (way << TLBMISC_WAY_SHIFT);
+                        WRCTL(CTL_TLBMISC, tlbmisc);
+                        WRCTL(CTL_TLBACC, (MAX_PHYS_ADDR >> PAGE_SHIFT));
+                }
+        }
+        WRCTL(CTL_TLBMISC, org_misc);
+}
+void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
+                        unsigned long end)
+{
+        unsigned long mmu_pid = get_pid_from_context(&vma->vm_mm->context);
+        while (start < end) {
+                flush_tlb_one_pid(start, mmu_pid);
+                start += PAGE_SIZE;
+        }
+}
+void flush_tlb_kernel_range(unsigned long start, unsigned long end)
+{
+        while (start < end) {
+                flush_tlb_one(start);
+                start += PAGE_SIZE;
+        }
+}
+/*
+ * This one is only used for pages with the global bit set so we don't care
+ * much about the ASID.
+ */
+void flush_tlb_one(unsigned long addr)
+{
+        unsigned int way;
+        unsigned long org_misc, pid_misc;
+        pr_debug("Flush tlb-entry for vaddr=%#lx\n", addr);
+        /* remember pid/way until we return. */
+        get_misc_and_pid(&org_misc, &pid_misc);
+        WRCTL(CTL_PTEADDR, (addr >> PAGE_SHIFT) << 2);
+        for (way = 0; way < cpuinfo.tlb_num_ways; way++) {
+                unsigned long pteaddr;
+                unsigned long tlbmisc;
+                tlbmisc = pid_misc | TLBMISC_RD | (way << TLBMISC_WAY_SHIFT);
+                WRCTL(CTL_TLBMISC, tlbmisc);
+                pteaddr = RDCTL(CTL_PTEADDR);
+                tlbmisc = RDCTL(CTL_TLBMISC);
+                if ((((pteaddr >> 2) & 0xfffff)) == (addr >> PAGE_SHIFT)) {
+                        unsigned long vaddr = CONFIG_NIOS2_IO_REGION_BASE +
+                                ((PAGE_SIZE * cpuinfo.tlb_num_lines) * way) +
+                                (addr & TLB_INDEX_MASK);
+                        pr_debug("Flush entry by writing %#lx way=%dl pid=%ld\n",
+                                vaddr, way, (pid_misc >> TLBMISC_PID_SHIFT));
+                        tlbmisc = pid_misc | TLBMISC_WE |
+                                (way << TLBMISC_WAY_SHIFT);
+                        WRCTL(CTL_PTEADDR, (vaddr >> 12) << 2);
+                        WRCTL(CTL_TLBMISC, tlbmisc);
+                        WRCTL(CTL_TLBACC, (MAX_PHYS_ADDR >> PAGE_SHIFT));
+                }
+        }
+        WRCTL(CTL_TLBMISC, org_misc);
+}
+void dump_tlb_line(unsigned long line)
+{
+        unsigned int way;
+        unsigned long org_misc;
+        pr_debug("dump tlb-entries for line=%#lx (addr %08lx)\n", line,
+                line << (PAGE_SHIFT + cpuinfo.tlb_num_ways_log2));
+        /* remember pid/way until we return */
+        org_misc = (RDCTL(CTL_TLBMISC) & (TLBMISC_PID | TLBMISC_WAY));
+        WRCTL(CTL_PTEADDR, line << 2);
+        for (way = 0; way < cpuinfo.tlb_num_ways; way++) {
+                unsigned long pteaddr;
+                unsigned long tlbmisc;
+                unsigned long tlbacc;
+                WRCTL(CTL_TLBMISC, TLBMISC_RD | (way << TLBMISC_WAY_SHIFT));
+                pteaddr = RDCTL(CTL_PTEADDR);
+                tlbmisc = RDCTL(CTL_TLBMISC);
+                tlbacc = RDCTL(CTL_TLBACC);
+                if ((tlbacc << PAGE_SHIFT) != (MAX_PHYS_ADDR & PAGE_MASK)) {
+                        pr_debug("-- way:%02x vpn:0x%08lx phys:0x%08lx pid:0x%02lx flags:%c%c%c%c%c\n",
+                                way,
+                                (pteaddr << (PAGE_SHIFT-2)),
+                                (tlbacc << PAGE_SHIFT),
+                                ((tlbmisc >> TLBMISC_PID_SHIFT) &
+                                TLBMISC_PID_MASK),
+                                (tlbacc & _PAGE_READ ? 'r' : '-'),
+                                (tlbacc & _PAGE_WRITE ? 'w' : '-'),
+                                (tlbacc & _PAGE_EXEC ? 'x' : '-'),
+                                (tlbacc & _PAGE_GLOBAL ? 'g' : '-'),
+                                (tlbacc & _PAGE_CACHED ? 'c' : '-'));
+                }
+        }
+        WRCTL(CTL_TLBMISC, org_misc);
+}
+void dump_tlb(void)
+{
+        unsigned int i;
+        for (i = 0; i < cpuinfo.tlb_num_lines; i++)
+                dump_tlb_line(i);
+}
+void flush_tlb_pid(unsigned long pid)
+{
+        unsigned int line;
+        unsigned int way;
+        unsigned long org_misc, pid_misc;
+        /* remember pid/way until we return */
+        get_misc_and_pid(&org_misc, &pid_misc);
+        for (line = 0; line < cpuinfo.tlb_num_lines; line++) {
+                WRCTL(CTL_PTEADDR, line << 2);
+                for (way = 0; way < cpuinfo.tlb_num_ways; way++) {
+                        unsigned long pteaddr;
+                        unsigned long tlbmisc;
+                        unsigned long tlbacc;
+                        tlbmisc = pid_misc | TLBMISC_RD |
+                                (way << TLBMISC_WAY_SHIFT);
+                        WRCTL(CTL_TLBMISC, tlbmisc);
+                        pteaddr = RDCTL(CTL_PTEADDR);
+                        tlbmisc = RDCTL(CTL_TLBMISC);
+                        tlbacc = RDCTL(CTL_TLBACC);
+                        if (((tlbmisc>>TLBMISC_PID_SHIFT) & TLBMISC_PID_MASK)
+                                == pid) {
+                                tlbmisc = pid_misc | TLBMISC_WE |
+                                        (way << TLBMISC_WAY_SHIFT);
+                                WRCTL(CTL_TLBMISC, tlbmisc);
+                                WRCTL(CTL_TLBACC,
+                                        (MAX_PHYS_ADDR >> PAGE_SHIFT));
+                        }
+                }
+                WRCTL(CTL_TLBMISC, org_misc);
+        }
+}
+void flush_tlb_all(void)
+{
+        int i;
+        unsigned long vaddr = CONFIG_NIOS2_IO_REGION_BASE;
+        unsigned int way;
+        unsigned long org_misc, pid_misc, tlbmisc;
+        /* remember pid/way until we return */
+        get_misc_and_pid(&org_misc, &pid_misc);
+        pid_misc |= TLBMISC_WE;
+        /* Map each TLB entry to physcal address 0 with no-access and a
+           bad ptbase */
+        for (way = 0; way < cpuinfo.tlb_num_ways; way++) {
+                tlbmisc = pid_misc | (way << TLBMISC_WAY_SHIFT);
+                for (i = 0; i < cpuinfo.tlb_num_lines; i++) {
+                        WRCTL(CTL_PTEADDR, ((vaddr) >> PAGE_SHIFT) << 2);
+                        WRCTL(CTL_TLBMISC, tlbmisc);
+                        WRCTL(CTL_TLBACC, (MAX_PHYS_ADDR >> PAGE_SHIFT));
+                        vaddr += 1UL << 12;
+                }
+        }
+        /* restore pid/way */
+        WRCTL(CTL_TLBMISC, org_misc);
+}
+void set_mmu_pid(unsigned long pid)
+{
+        WRCTL(CTL_TLBMISC, (RDCTL(CTL_TLBMISC) & TLBMISC_WAY) |
+                ((pid & TLBMISC_PID_MASK) << TLBMISC_PID_SHIFT));
+}
diff --git a/arch/nios2/mm/uaccess.c b/arch/nios2/mm/uaccess.c
new file mode 100644
index 000000000000..7663e156ff4f
--- /dev/null
+++ b/arch/nios2/mm/uaccess.c
@@ -0,0 +1,163 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2009, Wind River Systems Inc
+ * Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
+ */
+#include <linux/export.h>
+#include <linux/uaccess.h>
+asm(".global    __copy_from_user\n"
+        "   .type __copy_from_user, @function\n"
+        "__copy_from_user:\n"
+        "   movi  r2,7\n"
+        "   mov   r3,r4\n"
+        "   bge   r2,r6,1f\n"
+        "   xor   r2,r4,r5\n"
+        "   andi  r2,r2,3\n"
+        "   movi  r7,3\n"
+        "   beq   r2,zero,4f\n"
+        "1: addi  r6,r6,-1\n"
+        "   movi  r2,-1\n"
+        "   beq   r6,r2,3f\n"
+        "   mov   r7,r2\n"
+        "2: ldbu  r2,0(r5)\n"
+        "   addi  r6,r6,-1\n"
+        "   addi  r5,r5,1\n"
+        "   stb   r2,0(r3)\n"
+        "   addi  r3,r3,1\n"
+        "   bne   r6,r7,2b\n"
+        "3:\n"
+        "   addi  r2,r6,1\n"
+        "   ret\n"
+        "13:mov   r2,r6\n"
+        "   ret\n"
+        "4: andi  r2,r4,1\n"
+        "   cmpeq r2,r2,zero\n"
+        "   beq   r2,zero,7f\n"
+        "5: andi  r2,r3,2\n"
+        "   beq   r2,zero,6f\n"
+        "9: ldhu  r2,0(r5)\n"
+        "   addi  r6,r6,-2\n"
+        "   addi  r5,r5,2\n"
+        "   sth   r2,0(r3)\n"
+        "   addi  r3,r3,2\n"
+        "6: bge   r7,r6,1b\n"
+        "10:ldw   r2,0(r5)\n"
+        "   addi  r6,r6,-4\n"
+        "   addi  r5,r5,4\n"
+        "   stw   r2,0(r3)\n"
+        "   addi  r3,r3,4\n"
+        "   br    6b\n"
+        "7: ldbu  r2,0(r5)\n"
+        "   addi  r6,r6,-1\n"
+        "   addi  r5,r5,1\n"
+        "   addi  r3,r4,1\n"
+        "   stb   r2,0(r4)\n"
+        "   br    5b\n"
+        ".section __ex_table,\"a\"\n"
+        ".word 2b,3b\n"
+        ".word 9b,13b\n"
+        ".word 10b,13b\n"
+        ".word 7b,13b\n"
+        ".previous\n"
+        );
+EXPORT_SYMBOL(__copy_from_user);
+asm(
+        "   .global __copy_to_user\n"
+        "   .type __copy_to_user, @function\n"
+        "__copy_to_user:\n"
+        "   movi  r2,7\n"
+        "   mov   r3,r4\n"
+        "   bge   r2,r6,1f\n"
+        "   xor   r2,r4,r5\n"
+        "   andi  r2,r2,3\n"
+        "   movi  r7,3\n"
+        "   beq   r2,zero,4f\n"
+        /* Bail if we try to copy zero bytes  */
+        "1: addi  r6,r6,-1\n"
+        "   movi  r2,-1\n"
+        "   beq   r6,r2,3f\n"
+        /* Copy byte by byte for small copies and if src^dst != 0 */
+        "   mov   r7,r2\n"
+        "2: ldbu  r2,0(r5)\n"
+        "   addi  r5,r5,1\n"
+        "9: stb   r2,0(r3)\n"
+        "   addi  r6,r6,-1\n"
+        "   addi  r3,r3,1\n"
+        "   bne   r6,r7,2b\n"
+        "3: addi  r2,r6,1\n"
+        "   ret\n"
+        "13:mov   r2,r6\n"
+        "   ret\n"
+        /*  If 'to' is an odd address byte copy */
+        "4: andi  r2,r4,1\n"
+        "   cmpeq r2,r2,zero\n"
+        "   beq   r2,zero,7f\n"
+        /* If 'to' is not divideable by four copy halfwords */
+        "5: andi  r2,r3,2\n"
+        "   beq   r2,zero,6f\n"
+        "   ldhu  r2,0(r5)\n"
+        "   addi  r5,r5,2\n"
+        "10:sth   r2,0(r3)\n"
+        "   addi  r6,r6,-2\n"
+        "   addi  r3,r3,2\n"
+        /* Copy words */
+        "6: bge   r7,r6,1b\n"
+        "   ldw   r2,0(r5)\n"
+        "   addi  r5,r5,4\n"
+        "11:stw   r2,0(r3)\n"
+        "   addi  r6,r6,-4\n"
+        "   addi  r3,r3,4\n"
+        "   br    6b\n"
+        /* Copy remaining bytes */
+        "7: ldbu  r2,0(r5)\n"
+        "   addi  r5,r5,1\n"
+        "   addi  r3,r4,1\n"
+        "12: stb  r2,0(r4)\n"
+        "   addi  r6,r6,-1\n"
+        "   br    5b\n"
+        ".section __ex_table,\"a\"\n"
+        ".word 9b,3b\n"
+        ".word 10b,13b\n"
+        ".word 11b,13b\n"
+        ".word 12b,13b\n"
+        ".previous\n");
+EXPORT_SYMBOL(__copy_to_user);
+long strncpy_from_user(char *__to, const char __user *__from, long __len)
+{
+        int l = strnlen_user(__from, __len);
+        int is_zt = 1;
+        if (l > __len) {
+                is_zt = 0;
+                l = __len;
+        }
+        if (l == 0 || copy_from_user(__to, __from, l))
+                return -EFAULT;
+        if (is_zt)
+                l--;
+        return l;
+}
+long strnlen_user(const char __user *s, long n)
+{
+        long i;
+        for (i = 0; i < n; i++) {
+                char c;
+                if (get_user(c, s + i) == -EFAULT)
+                        return 0;
+                if (c == 0)
+                        return i + 1;
+        }
+        return n + 1;
+}
diff --git a/arch/nios2/platform/Kconfig.platform b/arch/nios2/platform/Kconfig.platform
new file mode 100644
index 000000000000..d3e5df9fb36b
--- /dev/null
+++ b/arch/nios2/platform/Kconfig.platform
@@ -0,0 +1,129 @@
+menu "Platform options"
+comment "Memory settings"
+config NIOS2_MEM_BASE
+        hex "Memory base address"
+        default "0x00000000"
+        help
+          This is the physical address of the memory that the kernel will run
+          from. This address is used to link the kernel and setup initial memory
+          management. You should take the raw memory address without any MMU
+          or cache bits set.
+          Please not that this address is used directly so you have to manually
+          do address translation if it's connected to a bridge.
+comment "Device tree"
+config NIOS2_DTB_AT_PHYS_ADDR
+        bool "DTB at physical address"
+        default n
+        help
+          When enabled you can select a physical address to load the dtb from.
+          Normally this address is passed by a bootloader such as u-boot but
+          using this you can use a devicetree without a bootloader.
+          This way you can store a devicetree in NOR flash or an onchip rom.
+          Please note that this address is used directly so you have to manually
+          do address translation if it's connected to a bridge. Also take into
+          account that when using an MMU you'd have to ad 0xC0000000 to your
+          address
+config NIOS2_DTB_PHYS_ADDR
+        hex "DTB Address"
+        depends on NIOS2_DTB_AT_PHYS_ADDR
+        default "0xC0000000"
+        help
+          Physical address of a dtb blob.
+config NIOS2_DTB_SOURCE_BOOL
+        bool "Compile and link device tree into kernel image"
+        default n
+        help
+          This allows you to specify a dts (device tree source) file
+          which will be compiled and linked into the kernel image.
+config NIOS2_DTB_SOURCE
+        string "Device tree source file"
+        depends on NIOS2_DTB_SOURCE_BOOL
+        default ""
+        help
+          Absolute path to the device tree source (dts) file describing your
+          system.
+comment "Nios II instructions"
+config NIOS2_HW_MUL_SUPPORT
+        bool "Enable MUL instruction"
+        default n
+        help
+          Set to true if you configured the Nios II to include the MUL
+          instruction.  This will enable the -mhw-mul compiler flag.
+config NIOS2_HW_MULX_SUPPORT
+        bool "Enable MULX instruction"
+        default n
+        help
+          Set to true if you configured the Nios II to include the MULX
+          instruction.  Enables the -mhw-mulx compiler flag.
+config NIOS2_HW_DIV_SUPPORT
+        bool "Enable DIV instruction"
+        default n
+        help
+          Set to true if you configured the Nios II to include the DIV
+          instruction.  Enables the -mhw-div compiler flag.
+config NIOS2_FPU_SUPPORT
+        bool "Custom floating point instr support"
+        default n
+        help
+          Enables the -mcustom-fpu-cfg=60-1 compiler flag.
+config NIOS2_CI_SWAB_SUPPORT
+        bool "Byteswap custom instruction"
+        default n
+        help
+          Use the byteswap (endian converter) Nios II custom instruction provided
+          by Altera and which can be enabled in QSYS builder. This accelerates
+          endian conversions in the kernel (e.g. ntohs).
+config NIOS2_CI_SWAB_NO
+        int "Byteswap custom instruction number" if NIOS2_CI_SWAB_SUPPORT
+        default 0
+        help
+          Number of the instruction as configured in QSYS Builder.
+comment "Cache settings"
+config CUSTOM_CACHE_SETTINGS
+        bool "Custom cache settings"
+        help
+          This option allows you to tweak the cache settings used during early
+          boot (where the information from device tree is not yet available).
+          There should be no reason to change these values. Linux will work
+          perfectly fine, even if the Nios II is configured with smaller caches.
+          Say N here unless you know what you are doing.
+config NIOS2_DCACHE_SIZE
+        hex "D-Cache size" if CUSTOM_CACHE_SETTINGS
+        range 0x200 0x10000
+        default "0x800"
+        help
+          Maximum possible data cache size.
+config NIOS2_DCACHE_LINE_SIZE
+        hex "D-Cache line size" if CUSTOM_CACHE_SETTINGS
+        range 0x10 0x20
+        default "0x20"
+        help
+          Minimum possible data cache line size.
+config NIOS2_ICACHE_SIZE
+        hex "I-Cache size" if CUSTOM_CACHE_SETTINGS
+        range 0x200 0x10000
+        default "0x1000"
+        help
+          Maximum possible instruction cache size.
+endmenu
diff --git a/arch/nios2/platform/Makefile b/arch/nios2/platform/Makefile
new file mode 100644
index 000000000000..46364f1d9352
--- /dev/null
+++ b/arch/nios2/platform/Makefile
@@ -0,0 +1 @@
+obj-y += platform.o
diff --git a/arch/nios2/platform/platform.c b/arch/nios2/platform/platform.c
new file mode 100644
index 000000000000..d478773f758a
--- /dev/null
+++ b/arch/nios2/platform/platform.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2013 Altera Corporation
+ * Copyright (C) 2011 Thomas Chou
+ * Copyright (C) 2011 Walter Goossens
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file COPYING in the main directory of this
+ * archive for more details.
+ */
+#include <linux/init.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/sys_soc.h>
+#include <linux/io.h>
+static int __init nios2_soc_device_init(void)
+{
+        struct soc_device *soc_dev;
+        struct soc_device_attribute *soc_dev_attr;
+        const char *machine;
+        soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+        if (soc_dev_attr) {
+                machine = of_flat_dt_get_machine_name();
+                if (machine)
+                        soc_dev_attr->machine = kasprintf(GFP_KERNEL, "%s",
+                                                machine);
+                soc_dev_attr->family = "Nios II";
+                soc_dev = soc_device_register(soc_dev_attr);
+                if (IS_ERR(soc_dev)) {
+                        kfree(soc_dev_attr->machine);
+                        kfree(soc_dev_attr);
+                }
+        }
+        return of_platform_populate(NULL, of_default_bus_match_table,
+                NULL, NULL);
+}
+device_initcall(nios2_soc_device_init);
diff --git a/arch/parisc/hpux/fs.c b/arch/parisc/hpux/fs.c
index 2bedafea3d94..97a7bf8df348 100644
--- a/arch/parisc/hpux/fs.c
+++ b/arch/parisc/hpux/fs.c
@@ -56,11 +56,12 @@ struct getdents_callback {
 #define NAME_OFFSET(de) ((int) ((de)->d_name - (char __user *) (de)))
-static int filldir(void * __buf, const char * name, int namlen, loff_t offset,
+static int filldir(struct dir_context *ctx, const char *name, int namlen,
-                u64 ino, unsigned d_type)
+                   loff_t offset, u64 ino, unsigned d_type)
 {
        struct hpux_dirent __user * dirent;
-        struct getdents_callback * buf = (struct getdents_callback *) __buf;
+        struct getdents_callback *buf =
+                container_of(ctx, struct getdents_callback, ctx);
        ino_t d_ino;
        int reclen = ALIGN(NAME_OFFSET(dirent) + namlen + 1, sizeof(long));
diff --git a/arch/parisc/include/asm/io.h b/arch/parisc/include/asm/io.h
index 1f6d2ae7aba5..8cd0abf28ffb 100644
--- a/arch/parisc/include/asm/io.h
+++ b/arch/parisc/include/asm/io.h
@@ -217,10 +217,14 @@ static inline void writeq(unsigned long long q, volatile void __iomem *addr)
 #define writel  writel
 #define writeq  writeq
-#define readb_relaxed(addr) readb(addr)
+#define readb_relaxed(addr)     readb(addr)
-#define readw_relaxed(addr) readw(addr)
+#define readw_relaxed(addr)     readw(addr)
-#define readl_relaxed(addr) readl(addr)
+#define readl_relaxed(addr)     readl(addr)
-#define readq_relaxed(addr) readq(addr)
+#define readq_relaxed(addr)     readq(addr)
+#define writeb_relaxed(b, addr) writeb(b, addr)
+#define writew_relaxed(w, addr) writew(w, addr)
+#define writel_relaxed(l, addr) writel(l, addr)
+#define writeq_relaxed(q, addr) writeq(q, addr)
 #define mmiowb() do { } while (0)
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index 97d3869991ca..9eaf301ac952 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -617,10 +617,14 @@ static inline void name at					\
 /*
 * We don't do relaxed operations yet, at least not with this semantic
 */
-#define readb_relaxed(addr) readb(addr)
+#define readb_relaxed(addr)     readb(addr)
-#define readw_relaxed(addr) readw(addr)
+#define readw_relaxed(addr)     readw(addr)
-#define readl_relaxed(addr) readl(addr)
+#define readl_relaxed(addr)     readl(addr)
-#define readq_relaxed(addr) readq(addr)
+#define readq_relaxed(addr)     readq(addr)
+#define writeb_relaxed(v, addr) writeb(v, addr)
+#define writew_relaxed(v, addr) writew(v, addr)
+#define writel_relaxed(v, addr) writel(v, addr)
+#define writeq_relaxed(v, addr) writeq(v, addr)
 #ifdef CONFIG_PPC32
 #define mmiowb()
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h
index 42632c7a2a4e..9cfa3706a1b8 100644
--- a/arch/powerpc/include/asm/iommu.h
+++ b/arch/powerpc/include/asm/iommu.h
@@ -137,13 +137,16 @@ static inline void set_iommu_table_base_and_group(struct device *dev,
        iommu_add_device(dev);
 }
-extern int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
+extern int ppc_iommu_map_sg(struct device *dev, struct iommu_table *tbl,
-                        struct scatterlist *sglist, int nelems,
+                            struct scatterlist *sglist, int nelems,
-                        unsigned long mask, enum dma_data_direction direction,
+                            unsigned long mask,
-                        struct dma_attrs *attrs);
+                            enum dma_data_direction direction,
-extern void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
+                            struct dma_attrs *attrs);
-                           int nelems, enum dma_data_direction direction,
+extern void ppc_iommu_unmap_sg(struct iommu_table *tbl,
-                           struct dma_attrs *attrs);
+                               struct scatterlist *sglist,
+                               int nelems,
+                               enum dma_data_direction direction,
+                               struct dma_attrs *attrs);
 extern void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
                                  size_t size, dma_addr_t *dma_handle,
diff --git a/arch/powerpc/include/asm/pgalloc.h b/arch/powerpc/include/asm/pgalloc.h
index e9a9f60e596d..fc3ee06eab87 100644
--- a/arch/powerpc/include/asm/pgalloc.h
+++ b/arch/powerpc/include/asm/pgalloc.h
@@ -3,7 +3,6 @@
 #ifdef __KERNEL__
 #include <linux/mm.h>
-#include <asm-generic/tlb.h>
 #ifdef CONFIG_PPC_BOOK3E
 extern void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address);
@@ -14,6 +13,8 @@ static inline void tlb_flush_pgtable(struct mmu_gather *tlb,
 }
 #endif /* !CONFIG_PPC_BOOK3E */
+extern void tlb_remove_table(struct mmu_gather *tlb, void *table);
 #ifdef CONFIG_PPC64
 #include <asm/pgalloc-64.h>
 #else
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index ae153c40ab7c..9b4b1904efae 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -467,6 +467,7 @@ static inline pte_t *pmdp_ptep(pmd_t *pmd)
 }
 #define pmd_pfn(pmd)            pte_pfn(pmd_pte(pmd))
+#define pmd_dirty(pmd)          pte_dirty(pmd_pte(pmd))
 #define pmd_young(pmd)          pte_young(pmd_pte(pmd))
 #define pmd_mkold(pmd)          pte_pmd(pte_mkold(pmd_pte(pmd)))
 #define pmd_wrprotect(pmd)      pte_pmd(pte_wrprotect(pmd_pte(pmd)))
diff --git a/arch/powerpc/include/asm/tlb.h b/arch/powerpc/include/asm/tlb.h
index e2b428b0f7ba..20733fa518ae 100644
--- a/arch/powerpc/include/asm/tlb.h
+++ b/arch/powerpc/include/asm/tlb.h
@@ -27,6 +27,7 @@
 #define tlb_start_vma(tlb, vma) do { } while (0)
 #define tlb_end_vma(tlb, vma)   do { } while (0)
+#define __tlb_remove_tlb_entry  __tlb_remove_tlb_entry
 extern void tlb_flush(struct mmu_gather *tlb);
diff --git a/arch/powerpc/kernel/dma-iommu.c b/arch/powerpc/kernel/dma-iommu.c
index 54d0116256f7..4c68bfe4108a 100644
--- a/arch/powerpc/kernel/dma-iommu.c
+++ b/arch/powerpc/kernel/dma-iommu.c
@@ -60,16 +60,16 @@ static int dma_iommu_map_sg(struct device *dev, struct scatterlist *sglist,
                            int nelems, enum dma_data_direction direction,
                            struct dma_attrs *attrs)
 {
-        return iommu_map_sg(dev, get_iommu_table_base(dev), sglist, nelems,
+        return ppc_iommu_map_sg(dev, get_iommu_table_base(dev), sglist, nelems,
-                            device_to_mask(dev), direction, attrs);
+                                device_to_mask(dev), direction, attrs);
 }
 static void dma_iommu_unmap_sg(struct device *dev, struct scatterlist *sglist,
                int nelems, enum dma_data_direction direction,
                struct dma_attrs *attrs)
 {
-        iommu_unmap_sg(get_iommu_table_base(dev), sglist, nelems, direction,
+        ppc_iommu_unmap_sg(get_iommu_table_base(dev), sglist, nelems,
-                       attrs);
+                           direction, attrs);
 }
 /* We support DMA to/from any memory page via the iommu */
diff --git a/arch/powerpc/kernel/ftrace.c b/arch/powerpc/kernel/ftrace.c
index 390311c0f03d..e66af6d265e8 100644
--- a/arch/powerpc/kernel/ftrace.c
+++ b/arch/powerpc/kernel/ftrace.c
@@ -449,7 +449,7 @@ void ftrace_replace_code(int enable)
                rec = ftrace_rec_iter_record(iter);
                ret = __ftrace_replace_code(rec, enable);
                if (ret) {
-                        ftrace_bug(ret, rec->ip);
+                        ftrace_bug(ret, rec);
                        return;
                }
        }
diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c
index a10642a0d861..a83cf5ef6488 100644
--- a/arch/powerpc/kernel/iommu.c
+++ b/arch/powerpc/kernel/iommu.c
@@ -428,10 +428,10 @@ static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
                ppc_md.tce_flush(tbl);
 }
-int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
+int ppc_iommu_map_sg(struct device *dev, struct iommu_table *tbl,
-                 struct scatterlist *sglist, int nelems,
+                     struct scatterlist *sglist, int nelems,
-                 unsigned long mask, enum dma_data_direction direction,
+                     unsigned long mask, enum dma_data_direction direction,
-                 struct dma_attrs *attrs)
+                     struct dma_attrs *attrs)
 {
        dma_addr_t dma_next = 0, dma_addr;
        struct scatterlist *s, *outs, *segstart;
@@ -539,7 +539,7 @@ int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
        DBG("mapped %d elements:\n", outcount);
-        /* For the sake of iommu_unmap_sg, we clear out the length in the
+        /* For the sake of ppc_iommu_unmap_sg, we clear out the length in the
         * next entry of the sglist if we didn't fill the list completely
         */
        if (outcount < incount) {
@@ -572,9 +572,9 @@ int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
 }
-void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
+void ppc_iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
-                int nelems, enum dma_data_direction direction,
+                        int nelems, enum dma_data_direction direction,
-                struct dma_attrs *attrs)
+                        struct dma_attrs *attrs)
 {
        struct scatterlist *sg;
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 7e70ae968e5f..6a4a5fcb9730 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -517,8 +517,6 @@ static void free_hugepd_range(struct mmu_gather *tlb, hugepd_t *hpdp, int pdshif
        for (i = 0; i < num_hugepd; i++, hpdp++)
                hpdp->pd = 0;
-        tlb->need_flush = 1;
 #ifdef CONFIG_PPC_FSL_BOOK3E
        hugepd_free(tlb, hugepte);
 #else
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index b9d1dfdbe5bb..9fe6002c1d5a 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -1711,12 +1711,11 @@ static void stage_topology_update(int core_id)
 static int dt_update_callback(struct notifier_block *nb,
                                unsigned long action, void *data)
 {
-        struct of_prop_reconfig *update;
+        struct of_reconfig_data *update = data;
        int rc = NOTIFY_DONE;
        switch (action) {
        case OF_RECONFIG_UPDATE_PROPERTY:
-                update = (struct of_prop_reconfig *)data;
                if (!of_prop_cmp(update->dn->type, "cpu") &&
                    !of_prop_cmp(update->prop->name, "ibm,associativity")) {
                        u32 core_id;
diff --git a/arch/powerpc/oprofile/cell/spu_task_sync.c b/arch/powerpc/oprofile/cell/spu_task_sync.c
index 28f1af2db1f5..1c27831df1ac 100644
--- a/arch/powerpc/oprofile/cell/spu_task_sync.c
+++ b/arch/powerpc/oprofile/cell/spu_task_sync.c
@@ -331,8 +331,7 @@ get_exec_dcookie_and_offset(struct spu *spu, unsigned int *offsetp,
        if (mm->exe_file) {
                app_cookie = fast_get_dcookie(&mm->exe_file->f_path);
-                pr_debug("got dcookie for %s\n",
+                pr_debug("got dcookie for %pD\n", mm->exe_file);
-                         mm->exe_file->f_dentry->d_name.name);
        }
        for (vma = mm->mmap; vma; vma = vma->vm_next) {
@@ -342,15 +341,14 @@ get_exec_dcookie_and_offset(struct spu *spu, unsigned int *offsetp,
                if (!vma->vm_file)
                        goto fail_no_image_cookie;
-                pr_debug("Found spu ELF at %X(object-id:%lx) for file %s\n",
+                pr_debug("Found spu ELF at %X(object-id:%lx) for file %pD\n",
-                         my_offset, spu_ref,
+                         my_offset, spu_ref, vma->vm_file);
-                         vma->vm_file->f_dentry->d_name.name);
                *offsetp = my_offset;
                break;
        }
        *spu_bin_dcookie = fast_get_dcookie(&vma->vm_file->f_path);
-        pr_debug("got dcookie for %s\n", vma->vm_file->f_dentry->d_name.name);
+        pr_debug("got dcookie for %pD\n", vma->vm_file);
        up_read(&mm->mmap_sem);
diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c
index 862b32702d29..0883994df384 100644
--- a/arch/powerpc/platforms/cell/axon_msi.c
+++ b/arch/powerpc/platforms/cell/axon_msi.c
@@ -279,7 +279,7 @@ static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
                irq_set_msi_desc(virq, entry);
                msg.data = virq;
-                write_msi_msg(virq, &msg);
+                pci_write_msi_msg(virq, &msg);
        }
        return 0;
@@ -301,9 +301,9 @@ static void axon_msi_teardown_msi_irqs(struct pci_dev *dev)
 }
 static struct irq_chip msic_irq_chip = {
-        .irq_mask       = mask_msi_irq,
+        .irq_mask       = pci_msi_mask_irq,
-        .irq_unmask     = unmask_msi_irq,
+        .irq_unmask     = pci_msi_unmask_irq,
-        .irq_shutdown   = mask_msi_irq,
+        .irq_shutdown   = pci_msi_mask_irq,
        .name           = "AXON-MSI",
 };
diff --git a/arch/powerpc/platforms/cell/iommu.c b/arch/powerpc/platforms/cell/iommu.c
index 2b90ff8a93be..c7c8720aa39f 100644
--- a/arch/powerpc/platforms/cell/iommu.c
+++ b/arch/powerpc/platforms/cell/iommu.c
@@ -621,8 +621,9 @@ static int dma_fixed_map_sg(struct device *dev, struct scatterlist *sg,
        if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))
                return dma_direct_ops.map_sg(dev, sg, nents, direction, attrs);
        else
-                return iommu_map_sg(dev, cell_get_iommu_table(dev), sg, nents,
+                return ppc_iommu_map_sg(dev, cell_get_iommu_table(dev), sg,
-                                    device_to_mask(dev), direction, attrs);
+                                        nents, device_to_mask(dev),
+                                        direction, attrs);
 }
 static void dma_fixed_unmap_sg(struct device *dev, struct scatterlist *sg,
@@ -632,8 +633,8 @@ static void dma_fixed_unmap_sg(struct device *dev, struct scatterlist *sg,
        if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))
                dma_direct_ops.unmap_sg(dev, sg, nents, direction, attrs);
        else
-                iommu_unmap_sg(cell_get_iommu_table(dev), sg, nents, direction,
+                ppc_iommu_unmap_sg(cell_get_iommu_table(dev), sg, nents,
-                               attrs);
+                                   direction, attrs);
 }
 static int dma_fixed_dma_supported(struct device *dev, u64 mask)
diff --git a/arch/powerpc/platforms/cell/spufs/inode.c b/arch/powerpc/platforms/cell/spufs/inode.c
index 87ba7cf99cd7..1a3429e1ccb5 100644
--- a/arch/powerpc/platforms/cell/spufs/inode.c
+++ b/arch/powerpc/platforms/cell/spufs/inode.c
@@ -164,7 +164,7 @@ static void spufs_prune_dir(struct dentry *dir)
        struct dentry *dentry, *tmp;
        mutex_lock(&dir->d_inode->i_mutex);
-        list_for_each_entry_safe(dentry, tmp, &dir->d_subdirs, d_u.d_child) {
+        list_for_each_entry_safe(dentry, tmp, &dir->d_subdirs, d_child) {
                spin_lock(&dentry->d_lock);
                if (!(d_unhashed(dentry)) && dentry->d_inode) {
                        dget_dlock(dentry);
@@ -301,7 +301,7 @@ static int spufs_context_open(struct path *path)
        int ret;
        struct file *filp;
-        ret = get_unused_fd();
+        ret = get_unused_fd_flags(0);
        if (ret < 0)
                return ret;
@@ -518,7 +518,7 @@ static int spufs_gang_open(struct path *path)
        int ret;
        struct file *filp;
-        ret = get_unused_fd();
+        ret = get_unused_fd_flags(0);
        if (ret < 0)
                return ret;
diff --git a/arch/powerpc/platforms/powernv/opal-sensor.c b/arch/powerpc/platforms/powernv/opal-sensor.c
index 10271ad1fac4..4ab67ef7abc9 100644
--- a/arch/powerpc/platforms/powernv/opal-sensor.c
+++ b/arch/powerpc/platforms/powernv/opal-sensor.c
@@ -20,7 +20,9 @@
 #include <linux/delay.h>
 #include <linux/mutex.h>
+#include <linux/of_platform.h>
 #include <asm/opal.h>
+#include <asm/machdep.h>
 static DEFINE_MUTEX(opal_sensor_mutex);
@@ -64,3 +66,21 @@ out:
        return ret;
 }
 EXPORT_SYMBOL_GPL(opal_get_sensor_data);
+static __init int opal_sensor_init(void)
+{
+        struct platform_device *pdev;
+        struct device_node *sensor;
+        sensor = of_find_node_by_path("/ibm,opal/sensors");
+        if (!sensor) {
+                pr_err("Opal node 'sensors' not found\n");
+                return -ENODEV;
+        }
+        pdev = of_platform_device_create(sensor, "opal-sensor", NULL);
+        of_node_put(sensor);
+        return PTR_ERR_OR_ZERO(pdev);
+}
+machine_subsys_initcall(powernv, opal_sensor_init);
diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
index 4b20f2c6b3b2..540fc6dd56b3 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -90,7 +90,7 @@ static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
                        return rc;
                }
                irq_set_msi_desc(virq, entry);
-                write_msi_msg(virq, &msg);
+                pci_write_msi_msg(virq, &msg);
        }
        return 0;
 }
diff --git a/arch/powerpc/platforms/pseries/hotplug-cpu.c b/arch/powerpc/platforms/pseries/hotplug-cpu.c
index 5c375f93c669..f30cf4d136a4 100644
--- a/arch/powerpc/platforms/pseries/hotplug-cpu.c
+++ b/arch/powerpc/platforms/pseries/hotplug-cpu.c
@@ -340,16 +340,17 @@ static void pseries_remove_processor(struct device_node *np)
 }
 static int pseries_smp_notifier(struct notifier_block *nb,
-                                unsigned long action, void *node)
+                                unsigned long action, void *data)
 {
+        struct of_reconfig_data *rd = data;
        int err = 0;
        switch (action) {
        case OF_RECONFIG_ATTACH_NODE:
-                err = pseries_add_processor(node);
+                err = pseries_add_processor(rd->dn);
                break;
        case OF_RECONFIG_DETACH_NODE:
-                pseries_remove_processor(node);
+                pseries_remove_processor(rd->dn);
                break;
        }
        return notifier_from_errno(err);
diff --git a/arch/powerpc/platforms/pseries/hotplug-memory.c b/arch/powerpc/platforms/pseries/hotplug-memory.c
index 3c4c0dcd90d3..1bbb78fab530 100644
--- a/arch/powerpc/platforms/pseries/hotplug-memory.c
+++ b/arch/powerpc/platforms/pseries/hotplug-memory.c
@@ -183,7 +183,7 @@ static int pseries_add_mem_node(struct device_node *np)
        return (ret < 0) ? -EINVAL : 0;
 }
-static int pseries_update_drconf_memory(struct of_prop_reconfig *pr)
+static int pseries_update_drconf_memory(struct of_reconfig_data *pr)
 {
        struct of_drconf_cell *new_drmem, *old_drmem;
        unsigned long memblock_size;
@@ -232,22 +232,21 @@ static int pseries_update_drconf_memory(struct of_prop_reconfig *pr)
 }
 static int pseries_memory_notifier(struct notifier_block *nb,
-                                   unsigned long action, void *node)
+                                   unsigned long action, void *data)
 {
-        struct of_prop_reconfig *pr;
+        struct of_reconfig_data *rd = data;
        int err = 0;
        switch (action) {
        case OF_RECONFIG_ATTACH_NODE:
-                err = pseries_add_mem_node(node);
+                err = pseries_add_mem_node(rd->dn);
                break;
        case OF_RECONFIG_DETACH_NODE:
-                err = pseries_remove_mem_node(node);
+                err = pseries_remove_mem_node(rd->dn);
                break;
        case OF_RECONFIG_UPDATE_PROPERTY:
-                pr = (struct of_prop_reconfig *)node;
+                if (!strcmp(rd->prop->name, "ibm,dynamic-memory"))
-                if (!strcmp(pr->prop->name, "ibm,dynamic-memory"))
+                        err = pseries_update_drconf_memory(rd);
-                        err = pseries_update_drconf_memory(pr);
                break;
        }
        return notifier_from_errno(err);
diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c
index e32e00976a94..3e5bfdafee63 100644
--- a/arch/powerpc/platforms/pseries/iommu.c
+++ b/arch/powerpc/platforms/pseries/iommu.c
@@ -1251,10 +1251,11 @@ static struct notifier_block iommu_mem_nb = {
        .notifier_call = iommu_mem_notifier,
 };
-static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node)
+static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *data)
 {
        int err = NOTIFY_OK;
-        struct device_node *np = node;
+        struct of_reconfig_data *rd = data;
+        struct device_node *np = rd->dn;
        struct pci_dn *pci = PCI_DN(np);
        struct direct_window *window;
diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c
index 8b909e94fd9a..691a154c286d 100644
--- a/arch/powerpc/platforms/pseries/msi.c
+++ b/arch/powerpc/platforms/pseries/msi.c
@@ -476,7 +476,7 @@ again:
                irq_set_msi_desc(virq, entry);
                /* Read config space back so we can restore after reset */
-                __read_msi_msg(entry, &msg);
+                __pci_read_msi_msg(entry, &msg);
                entry->msg = msg;
        }
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index 125c589eeef5..ed8a90022a3d 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -251,9 +251,10 @@ static void __init pseries_discover_pic(void)
               " interrupt-controller\n");
 }
-static int pci_dn_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node)
+static int pci_dn_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *data)
 {
-        struct device_node *np = node;
+        struct of_reconfig_data *rd = data;
+        struct device_node *np = rd->dn;
        struct pci_dn *pci = NULL;
        int err = NOTIFY_OK;
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index da08ed088157..7aed8d0876b7 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -82,8 +82,8 @@ static void fsl_msi_print_chip(struct irq_data *irqd, struct seq_file *p)
 static struct irq_chip fsl_msi_chip = {
-        .irq_mask       = mask_msi_irq,
+        .irq_mask       = pci_msi_mask_irq,
-        .irq_unmask     = unmask_msi_irq,
+        .irq_unmask     = pci_msi_unmask_irq,
        .irq_ack        = fsl_msi_end_irq,
        .irq_print_chip = fsl_msi_print_chip,
 };
@@ -242,7 +242,7 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
                irq_set_msi_desc(virq, entry);
                fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
-                write_msi_msg(virq, &msg);
+                pci_write_msi_msg(virq, &msg);
        }
        return 0;
diff --git a/arch/powerpc/sysdev/mpic_pasemi_msi.c b/arch/powerpc/sysdev/mpic_pasemi_msi.c
index 15dccd35fa11..45c114bc430b 100644
--- a/arch/powerpc/sysdev/mpic_pasemi_msi.c
+++ b/arch/powerpc/sysdev/mpic_pasemi_msi.c
@@ -42,7 +42,7 @@ static struct mpic *msi_mpic;
 static void mpic_pasemi_msi_mask_irq(struct irq_data *data)
 {
        pr_debug("mpic_pasemi_msi_mask_irq %d\n", data->irq);
-        mask_msi_irq(data);
+        pci_msi_mask_irq(data);
        mpic_mask_irq(data);
 }
@@ -50,7 +50,7 @@ static void mpic_pasemi_msi_unmask_irq(struct irq_data *data)
 {
        pr_debug("mpic_pasemi_msi_unmask_irq %d\n", data->irq);
        mpic_unmask_irq(data);
-        unmask_msi_irq(data);
+        pci_msi_unmask_irq(data);
 }
 static struct irq_chip mpic_pasemi_msi_chip = {
@@ -136,7 +136,7 @@ static int pasemi_msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
                 * register to generate MSI [512...1023]
                 */
                msg.data = hwirq-0x200;
-                write_msi_msg(virq, &msg);
+                pci_write_msi_msg(virq, &msg);
        }
        return 0;
diff --git a/arch/powerpc/sysdev/mpic_u3msi.c b/arch/powerpc/sysdev/mpic_u3msi.c
index 623d7fba15b4..0dff1cd44481 100644
--- a/arch/powerpc/sysdev/mpic_u3msi.c
+++ b/arch/powerpc/sysdev/mpic_u3msi.c
@@ -25,14 +25,14 @@ static struct mpic *msi_mpic;
 static void mpic_u3msi_mask_irq(struct irq_data *data)
 {
-        mask_msi_irq(data);
+        pci_msi_mask_irq(data);
        mpic_mask_irq(data);
 }
 static void mpic_u3msi_unmask_irq(struct irq_data *data)
 {
        mpic_unmask_irq(data);
-        unmask_msi_irq(data);
+        pci_msi_unmask_irq(data);
 }
 static struct irq_chip mpic_u3msi_chip = {
@@ -171,7 +171,7 @@ static int u3msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
                printk("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n",
                          virq, hwirq, (unsigned long)addr);
                msg.data = hwirq;
-                write_msi_msg(virq, &msg);
+                pci_write_msi_msg(virq, &msg);
                hwirq++;
        }
diff --git a/arch/powerpc/sysdev/ppc4xx_hsta_msi.c b/arch/powerpc/sysdev/ppc4xx_hsta_msi.c
index a6a4dbda9078..908105f835d1 100644
--- a/arch/powerpc/sysdev/ppc4xx_hsta_msi.c
+++ b/arch/powerpc/sysdev/ppc4xx_hsta_msi.c
@@ -85,7 +85,7 @@ static int hsta_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
                        msi_bitmap_free_hwirqs(&ppc4xx_hsta_msi.bmp, irq, 1);
                        return -EINVAL;
                }
-                write_msi_msg(hwirq, &msg);
+                pci_write_msi_msg(hwirq, &msg);
        }
        return 0;
diff --git a/arch/powerpc/sysdev/ppc4xx_msi.c b/arch/powerpc/sysdev/ppc4xx_msi.c
index 22b5200636e7..518eabbe0bdc 100644
--- a/arch/powerpc/sysdev/ppc4xx_msi.c
+++ b/arch/powerpc/sysdev/ppc4xx_msi.c
@@ -116,7 +116,7 @@ static int ppc4xx_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
                irq_set_msi_desc(virq, entry);
                msg.data = int_no;
-                write_msi_msg(virq, &msg);
+                pci_write_msi_msg(virq, &msg);
        }
        return 0;
 }
diff --git a/arch/powerpc/sysdev/xics/ics-opal.c b/arch/powerpc/sysdev/xics/ics-opal.c
index 3c6ee1b64e5d..4ba554ec8eaf 100644
--- a/arch/powerpc/sysdev/xics/ics-opal.c
+++ b/arch/powerpc/sysdev/xics/ics-opal.c
@@ -73,7 +73,7 @@ static unsigned int ics_opal_startup(struct irq_data *d)
         * at that level, so we do it here by hand.
         */
        if (d->msi_desc)
-                unmask_msi_irq(d);
+                pci_msi_unmask_irq(d);
 #endif
        /* unmask it */
diff --git a/arch/powerpc/sysdev/xics/ics-rtas.c b/arch/powerpc/sysdev/xics/ics-rtas.c
index 936575d99c5c..bc81335b2cbc 100644
--- a/arch/powerpc/sysdev/xics/ics-rtas.c
+++ b/arch/powerpc/sysdev/xics/ics-rtas.c
@@ -76,7 +76,7 @@ static unsigned int ics_rtas_startup(struct irq_data *d)
         * at that level, so we do it here by hand.
         */
        if (d->msi_desc)
-                unmask_msi_irq(d);
+                pci_msi_unmask_irq(d);
 #endif
        /* unmask it */
        ics_rtas_unmask_irq(d);
diff --git a/arch/s390/hypfs/hypfs_dbfs.c b/arch/s390/hypfs/hypfs_dbfs.c
index 2badf2bf9cd7..47fe1055c714 100644
--- a/arch/s390/hypfs/hypfs_dbfs.c
+++ b/arch/s390/hypfs/hypfs_dbfs.c
@@ -83,10 +83,9 @@ static ssize_t dbfs_read(struct file *file, char __user *buf,
 static long dbfs_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
 {
-        struct hypfs_dbfs_file *df;
+        struct hypfs_dbfs_file *df = file_inode(file)->i_private;
        long rc;
-        df = file->f_path.dentry->d_inode->i_private;
        mutex_lock(&df->lock);
        if (df->unlocked_ioctl)
                rc = df->unlocked_ioctl(file, cmd, arg);
diff --git a/arch/s390/include/asm/io.h b/arch/s390/include/asm/io.h
index cd6b9ee7b69c..6ad9013c67e7 100644
--- a/arch/s390/include/asm/io.h
+++ b/arch/s390/include/asm/io.h
@@ -13,9 +13,10 @@
 #include <asm/page.h>
 #include <asm/pci_io.h>
-void *xlate_dev_mem_ptr(unsigned long phys);
 #define xlate_dev_mem_ptr xlate_dev_mem_ptr
-void unxlate_dev_mem_ptr(unsigned long phys, void *addr);
+void *xlate_dev_mem_ptr(phys_addr_t phys);
+#define unxlate_dev_mem_ptr unxlate_dev_mem_ptr
+void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr);
 /*
 * Convert a virtual cached pointer to an uncached pointer
@@ -60,11 +61,6 @@ static inline void iounmap(volatile void __iomem *addr)
 #define __raw_writel    zpci_write_u32
 #define __raw_writeq    zpci_write_u64
-#define readb_relaxed   readb
-#define readw_relaxed   readw
-#define readl_relaxed   readl
-#define readq_relaxed   readq
 #endif /* CONFIG_PCI */
 #include <asm-generic/io.h>
diff --git a/arch/s390/include/asm/mmu_context.h b/arch/s390/include/asm/mmu_context.h
index 3815bfea1b2d..f49b71954654 100644
--- a/arch/s390/include/asm/mmu_context.h
+++ b/arch/s390/include/asm/mmu_context.h
@@ -120,4 +120,15 @@ static inline void arch_exit_mmap(struct mm_struct *mm)
 {
 }
+static inline void arch_unmap(struct mm_struct *mm,
+                        struct vm_area_struct *vma,
+                        unsigned long start, unsigned long end)
+{
+}
+static inline void arch_bprm_mm_init(struct mm_struct *mm,
+                                     struct vm_area_struct *vma)
+{
+}
 #endif /* __S390_MMU_CONTEXT_H */
diff --git a/arch/s390/mm/maccess.c b/arch/s390/mm/maccess.c
index 2a2e35416d2f..2eb34bdfc613 100644
--- a/arch/s390/mm/maccess.c
+++ b/arch/s390/mm/maccess.c
@@ -176,7 +176,7 @@ static int is_swapped(unsigned long addr)
 * For swapped prefix pages a new buffer is returned that contains a copy of
 * the absolute memory. The buffer size is maximum one page large.
 */
-void *xlate_dev_mem_ptr(unsigned long addr)
+void *xlate_dev_mem_ptr(phys_addr_t addr)
 {
        void *bounce = (void *) addr;
        unsigned long size;
@@ -197,7 +197,7 @@ void *xlate_dev_mem_ptr(unsigned long addr)
 /*
 * Free converted buffer for /dev/mem access (if necessary)
 */
-void unxlate_dev_mem_ptr(unsigned long addr, void *buf)
+void unxlate_dev_mem_ptr(phys_addr_t addr, void *buf)
 {
        if ((void *) addr != buf)
                free_page((unsigned long) buf);
diff --git a/arch/s390/pci/pci.c b/arch/s390/pci/pci.c
index 2fa7b14b9c08..d59c82569750 100644
--- a/arch/s390/pci/pci.c
+++ b/arch/s390/pci/pci.c
@@ -50,8 +50,8 @@ static DEFINE_SPINLOCK(zpci_list_lock);
 static struct irq_chip zpci_irq_chip = {
        .name = "zPCI",
-        .irq_unmask = unmask_msi_irq,
+        .irq_unmask = pci_msi_unmask_irq,
-        .irq_mask = mask_msi_irq,
+        .irq_mask = pci_msi_mask_irq,
 };
 static DECLARE_BITMAP(zpci_domain, ZPCI_NR_DEVICES);
@@ -403,7 +403,7 @@ int arch_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
                msg.data = hwirq;
                msg.address_lo = zdev->msi_addr & 0xffffffff;
                msg.address_hi = zdev->msi_addr >> 32;
-                write_msi_msg(irq, &msg);
+                pci_write_msi_msg(irq, &msg);
                airq_iv_set_data(zdev->aibv, hwirq, irq);
                hwirq++;
        }
@@ -448,9 +448,9 @@ void arch_teardown_msi_irqs(struct pci_dev *pdev)
        /* Release MSI interrupts */
        list_for_each_entry(msi, &pdev->msi_list, list) {
                if (msi->msi_attrib.is_msix)
-                        default_msix_mask_irq(msi, 1);
+                        __pci_msix_desc_mask_irq(msi, 1);
                else
-                        default_msi_mask_irq(msi, 1, 1);
+                        __pci_msi_desc_mask_irq(msi, 1, 1);
                irq_set_msi_desc(msi->irq, NULL);
                irq_free_desc(msi->irq);
                msi->msg.address_lo = 0;
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 244fb4c81e25..a1403470f80e 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -222,7 +222,6 @@ config CPU_SHX3
 config ARCH_SHMOBILE
        bool
        select ARCH_SUSPEND_POSSIBLE
-        select PM
        select PM_RUNTIME
 config CPU_HAS_PMU
diff --git a/arch/sh/boards/mach-ap325rxa/setup.c b/arch/sh/boards/mach-ap325rxa/setup.c
index 5620e33c18a0..d4b01d4cc102 100644
--- a/arch/sh/boards/mach-ap325rxa/setup.c
+++ b/arch/sh/boards/mach-ap325rxa/setup.c
@@ -338,7 +338,7 @@ static struct soc_camera_platform_info camera_info = {
        .format_name = "UYVY",
        .format_depth = 16,
        .format = {
-                .code = V4L2_MBUS_FMT_UYVY8_2X8,
+                .code = MEDIA_BUS_FMT_UYVY8_2X8,
                .colorspace = V4L2_COLORSPACE_SMPTE170M,
                .field = V4L2_FIELD_NONE,
                .width = 640,
diff --git a/arch/sh/kernel/cpu/shmobile/cpuidle.c b/arch/sh/kernel/cpu/shmobile/cpuidle.c
index e3abfd4277e2..53b8eeb1db20 100644
--- a/arch/sh/kernel/cpu/shmobile/cpuidle.c
+++ b/arch/sh/kernel/cpu/shmobile/cpuidle.c
@@ -59,7 +59,6 @@ static struct cpuidle_driver cpuidle_driver = {
                        .exit_latency = 1,
                        .target_residency = 1 * 2,
                        .power_usage = 3,
-                        .flags = CPUIDLE_FLAG_TIME_VALID,
                        .enter = cpuidle_sleep_enter,
                        .name = "C1",
                        .desc = "SuperH Sleep Mode",
@@ -68,7 +67,6 @@ static struct cpuidle_driver cpuidle_driver = {
                        .exit_latency = 100,
                        .target_residency = 1 * 2,
                        .power_usage = 1,
-                        .flags = CPUIDLE_FLAG_TIME_VALID,
                        .enter = cpuidle_sleep_enter,
                        .name = "C2",
                        .desc = "SuperH Sleep Mode [SF]",
@@ -78,7 +76,6 @@ static struct cpuidle_driver cpuidle_driver = {
                        .exit_latency = 2300,
                        .target_residency = 1 * 2,
                        .power_usage = 1,
-                        .flags = CPUIDLE_FLAG_TIME_VALID,
                        .enter = cpuidle_sleep_enter,
                        .name = "C3",
                        .desc = "SuperH Mobile Standby Mode [SF]",
diff --git a/arch/sh/mm/numa.c b/arch/sh/mm/numa.c
index 3d85225b9e95..bce52ba66206 100644
--- a/arch/sh/mm/numa.c
+++ b/arch/sh/mm/numa.c
@@ -31,7 +31,7 @@ void __init setup_bootmem_node(int nid, unsigned long start, unsigned long end)
        unsigned long bootmem_paddr;
        /* Don't allow bogus node assignment */
-        BUG_ON(nid > MAX_NUMNODES || nid <= 0);
+        BUG_ON(nid >= MAX_NUMNODES || nid <= 0);
        start_pfn = start >> PAGE_SHIFT;
        end_pfn = end >> PAGE_SHIFT;
diff --git a/arch/sparc/include/asm/io_32.h b/arch/sparc/include/asm/io_32.h
index 9f532902627c..407ac14295f4 100644
--- a/arch/sparc/include/asm/io_32.h
+++ b/arch/sparc/include/asm/io_32.h
@@ -4,10 +4,6 @@
 #include <linux/kernel.h>
 #include <linux/ioport.h>  /* struct resource */
-#define readb_relaxed(__addr)   readb(__addr)
-#define readw_relaxed(__addr)   readw(__addr)
-#define readl_relaxed(__addr)   readl(__addr)
 #define IO_SPACE_LIMIT 0xffffffff
 #define memset_io(d,c,sz)     _memset_io(d,c,sz)
diff --git a/arch/sparc/include/asm/io_64.h b/arch/sparc/include/asm/io_64.h
index 80b54b326d49..9b672be70dda 100644
--- a/arch/sparc/include/asm/io_64.h
+++ b/arch/sparc/include/asm/io_64.h
@@ -101,6 +101,7 @@ static inline void __raw_writeq(u64 q, const volatile void __iomem *addr)
 * the cache by using ASI_PHYS_BYPASS_EC_E_L
 */
 #define readb readb
+#define readb_relaxed readb
 static inline u8 readb(const volatile void __iomem *addr)
 {       u8 ret;
@@ -112,6 +113,7 @@ static inline u8 readb(const volatile void __iomem *addr)
 }
 #define readw readw
+#define readw_relaxed readw
 static inline u16 readw(const volatile void __iomem *addr)
 {       u16 ret;
@@ -124,6 +126,7 @@ static inline u16 readw(const volatile void __iomem *addr)
 }
 #define readl readl
+#define readl_relaxed readl
 static inline u32 readl(const volatile void __iomem *addr)
 {       u32 ret;
@@ -136,6 +139,7 @@ static inline u32 readl(const volatile void __iomem *addr)
 }
 #define readq readq
+#define readq_relaxed readq
 static inline u64 readq(const volatile void __iomem *addr)
 {       u64 ret;
@@ -148,6 +152,7 @@ static inline u64 readq(const volatile void __iomem *addr)
 }
 #define writeb writeb
+#define writeb_relaxed writeb
 static inline void writeb(u8 b, volatile void __iomem *addr)
 {
        __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
@@ -157,6 +162,7 @@ static inline void writeb(u8 b, volatile void __iomem *addr)
 }
 #define writew writew
+#define writew_relaxed writew
 static inline void writew(u16 w, volatile void __iomem *addr)
 {
        __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
@@ -166,6 +172,7 @@ static inline void writew(u16 w, volatile void __iomem *addr)
 }
 #define writel writel
+#define writel_relaxed writel
 static inline void writel(u32 l, volatile void __iomem *addr)
 {
        __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
@@ -175,6 +182,7 @@ static inline void writel(u32 l, volatile void __iomem *addr)
 }
 #define writeq writeq
+#define writeq_relaxed writeq
 static inline void writeq(u64 q, volatile void __iomem *addr)
 {
        __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
@@ -183,7 +191,6 @@ static inline void writeq(u64 q, volatile void __iomem *addr)
                             : "memory");
 }
 #define inb inb
 static inline u8 inb(unsigned long addr)
 {
@@ -264,11 +271,6 @@ static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned l
        outsl((unsigned long __force)port, buf, count);
 }
-#define readb_relaxed(__addr)   readb(__addr)
-#define readw_relaxed(__addr)   readw(__addr)
-#define readl_relaxed(__addr)   readl(__addr)
-#define readq_relaxed(__addr)   readq(__addr)
 /* Valid I/O Space regions are anywhere, because each PCI bus supported
 * can live in an arbitrary area of the physical address range.
 */
diff --git a/arch/sparc/include/asm/pgtable_64.h b/arch/sparc/include/asm/pgtable_64.h
index bfeb626085ac..1ff9e7864168 100644
--- a/arch/sparc/include/asm/pgtable_64.h
+++ b/arch/sparc/include/asm/pgtable_64.h
@@ -667,6 +667,13 @@ static inline unsigned long pmd_pfn(pmd_t pmd)
 }
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
+static inline unsigned long pmd_dirty(pmd_t pmd)
+{
+        pte_t pte = __pte(pmd_val(pmd));
+        return pte_dirty(pte);
+}
 static inline unsigned long pmd_young(pmd_t pmd)
 {
        pte_t pte = __pte(pmd_val(pmd));
diff --git a/arch/sparc/kernel/pci_msi.c b/arch/sparc/kernel/pci_msi.c
index 580651af73f2..84e16d81a6d8 100644
--- a/arch/sparc/kernel/pci_msi.c
+++ b/arch/sparc/kernel/pci_msi.c
@@ -111,10 +111,10 @@ static void free_msi(struct pci_pbm_info *pbm, int msi_num)
 static struct irq_chip msi_irq = {
        .name           = "PCI-MSI",
-        .irq_mask       = mask_msi_irq,
+        .irq_mask       = pci_msi_mask_irq,
-        .irq_unmask     = unmask_msi_irq,
+        .irq_unmask     = pci_msi_unmask_irq,
-        .irq_enable     = unmask_msi_irq,
+        .irq_enable     = pci_msi_unmask_irq,
-        .irq_disable    = mask_msi_irq,
+        .irq_disable    = pci_msi_mask_irq,
        /* XXX affinity XXX */
 };
@@ -161,7 +161,7 @@ static int sparc64_setup_msi_irq(unsigned int *irq_p,
        msg.data = msi;
        irq_set_msi_desc(*irq_p, entry);
-        write_msi_msg(*irq_p, &msg);
+        pci_write_msi_msg(*irq_p, &msg);
        return 0;
diff --git a/arch/tile/include/asm/io.h b/arch/tile/include/asm/io.h
index 9fe434969fab..d372641054d9 100644
--- a/arch/tile/include/asm/io.h
+++ b/arch/tile/include/asm/io.h
@@ -241,6 +241,10 @@ static inline void writeq(u64 val, unsigned long addr)
 #define readw_relaxed readw
 #define readl_relaxed readl
 #define readq_relaxed readq
+#define writeb_relaxed writeb
+#define writew_relaxed writew
+#define writel_relaxed writel
+#define writeq_relaxed writeq
 #define ioread8 readb
 #define ioread16 readw
diff --git a/arch/tile/kernel/early_printk.c b/arch/tile/kernel/early_printk.c
index b608e00e7f6d..aefb2c086726 100644
--- a/arch/tile/kernel/early_printk.c
+++ b/arch/tile/kernel/early_printk.c
@@ -43,13 +43,20 @@ static struct console early_hv_console = {
 void early_panic(const char *fmt, ...)
 {
-        va_list ap;
+        struct va_format vaf;
+        va_list args;
        arch_local_irq_disable_all();
-        va_start(ap, fmt);
-        early_printk("Kernel panic - not syncing: ");
+        va_start(args, fmt);
-        early_vprintk(fmt, ap);
-        early_printk("\n");
+        vaf.fmt = fmt;
-        va_end(ap);
+        vaf.va = &args;
+        early_printk("Kernel panic - not syncing: %pV", &vaf);
+        va_end(args);
        dump_stack();
        hv_halt();
 }
diff --git a/arch/tile/kernel/pci_gx.c b/arch/tile/kernel/pci_gx.c
index e39f9c542807..e717af20dada 100644
--- a/arch/tile/kernel/pci_gx.c
+++ b/arch/tile/kernel/pci_gx.c
@@ -1453,7 +1453,7 @@ static struct pci_ops tile_cfg_ops = {
 static unsigned int tilegx_msi_startup(struct irq_data *d)
 {
        if (d->msi_desc)
-                unmask_msi_irq(d);
+                pci_msi_unmask_irq(d);
        return 0;
 }
@@ -1465,14 +1465,14 @@ static void tilegx_msi_ack(struct irq_data *d)
 static void tilegx_msi_mask(struct irq_data *d)
 {
-        mask_msi_irq(d);
+        pci_msi_mask_irq(d);
        __insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq);
 }
 static void tilegx_msi_unmask(struct irq_data *d)
 {
        __insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq);
-        unmask_msi_irq(d);
+        pci_msi_unmask_irq(d);
 }
 static struct irq_chip tilegx_msi_chip = {
@@ -1590,7 +1590,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
        msg.address_hi = msi_addr >> 32;
        msg.address_lo = msi_addr & 0xffffffff;
-        write_msi_msg(irq, &msg);
+        pci_write_msi_msg(irq, &msg);
        irq_set_chip_and_handler(irq, &tilegx_msi_chip, handle_level_irq);
        irq_set_handler_data(irq, controller);
diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c
index b9736ded06f2..7f079bbfdf4c 100644
--- a/arch/tile/kernel/setup.c
+++ b/arch/tile/kernel/setup.c
@@ -534,11 +534,10 @@ static void __init setup_memory(void)
                        }
                }
                physpages -= dropped_pages;
-                pr_warning("Only using %ldMB memory;"
+                pr_warn("Only using %ldMB memory - ignoring %ldMB\n",
-                       " ignoring %ldMB.\n",
+                        physpages >> (20 - PAGE_SHIFT),
-                       physpages >> (20 - PAGE_SHIFT),
+                        dropped_pages >> (20 - PAGE_SHIFT));
-                       dropped_pages >> (20 - PAGE_SHIFT));
+                pr_warn("Consider using a larger page size\n");
-                pr_warning("Consider using a larger page size.\n");
        }
 #endif
@@ -566,9 +565,8 @@ static void __init setup_memory(void)
 #ifndef __tilegx__
        if (node_end_pfn[0] > MAXMEM_PFN) {
-                pr_warning("Only using %ldMB LOWMEM.\n",
+                pr_warn("Only using %ldMB LOWMEM\n", MAXMEM >> 20);
-                       MAXMEM>>20);
+                pr_warn("Use a HIGHMEM enabled kernel\n");
-                pr_warning("Use a HIGHMEM enabled kernel.\n");
                max_low_pfn = MAXMEM_PFN;
                max_pfn = MAXMEM_PFN;
                node_end_pfn[0] = MAXMEM_PFN;
@@ -1112,8 +1110,8 @@ static void __init load_hv_initrd(void)
        fd = hv_fs_findfile((HV_VirtAddr) initramfs_file);
        if (fd == HV_ENOENT) {
                if (set_initramfs_file) {
-                        pr_warning("No such hvfs initramfs file '%s'\n",
+                        pr_warn("No such hvfs initramfs file '%s'\n",
-                                   initramfs_file);
+                                initramfs_file);
                        return;
                } else {
                        /* Try old backwards-compatible name. */
@@ -1126,8 +1124,8 @@ static void __init load_hv_initrd(void)
        stat = hv_fs_fstat(fd);
        BUG_ON(stat.size < 0);
        if (stat.flags & HV_FS_ISDIR) {
-                pr_warning("Ignoring hvfs file '%s': it's a directory.\n",
+                pr_warn("Ignoring hvfs file '%s': it's a directory\n",
-                           initramfs_file);
+                        initramfs_file);
                return;
        }
        initrd = alloc_bootmem_pages(stat.size);
@@ -1185,9 +1183,8 @@ static void __init validate_hv(void)
        HV_Topology topology = hv_inquire_topology();
        BUG_ON(topology.coord.x != 0 || topology.coord.y != 0);
        if (topology.width != 1 || topology.height != 1) {
-                pr_warning("Warning: booting UP kernel on %dx%d grid;"
+                pr_warn("Warning: booting UP kernel on %dx%d grid; will ignore all but first tile\n",
-                           " will ignore all but first tile.\n",
+                        topology.width, topology.height);
-                           topology.width, topology.height);
        }
 #endif
@@ -1208,9 +1205,8 @@ static void __init validate_hv(void)
         * We use a struct cpumask for this, so it must be big enough.
         */
        if ((smp_height * smp_width) > nr_cpu_ids)
-                early_panic("Hypervisor %d x %d grid too big for Linux"
+                early_panic("Hypervisor %d x %d grid too big for Linux NR_CPUS %d\n",
-                            " NR_CPUS %d\n", smp_height, smp_width,
+                            smp_height, smp_width, nr_cpu_ids);
-                            nr_cpu_ids);
 #endif
        /*
@@ -1265,10 +1261,9 @@ static void __init validate_va(void)
        /* Kernel PCs must have their high bit set; see intvec.S. */
        if ((long)VMALLOC_START >= 0)
-                early_panic(
+                early_panic("Linux VMALLOC region below the 2GB line (%#lx)!\n"
-                        "Linux VMALLOC region below the 2GB line (%#lx)!\n"
+                            "Reconfigure the kernel with smaller VMALLOC_RESERVE\n",
-                        "Reconfigure the kernel with smaller VMALLOC_RESERVE.\n",
+                            VMALLOC_START);
-                        VMALLOC_START);
 #endif
 }
@@ -1395,7 +1390,7 @@ static void __init setup_cpu_maps(void)
 static int __init dataplane(char *str)
 {
-        pr_warning("WARNING: dataplane support disabled in this kernel\n");
+        pr_warn("WARNING: dataplane support disabled in this kernel\n");
        return 0;
 }
@@ -1413,8 +1408,8 @@ void __init setup_arch(char **cmdline_p)
        len = hv_get_command_line((HV_VirtAddr) boot_command_line,
                                  COMMAND_LINE_SIZE);
        if (boot_command_line[0])
-                pr_warning("WARNING: ignoring dynamic command line \"%s\"\n",
+                pr_warn("WARNING: ignoring dynamic command line \"%s\"\n",
-                           boot_command_line);
+                        boot_command_line);
        strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
 #else
        char *hv_cmdline;
diff --git a/arch/um/include/asm/mmu_context.h b/arch/um/include/asm/mmu_context.h
index aa4a743dc4ab..941527e507f7 100644
--- a/arch/um/include/asm/mmu_context.h
+++ b/arch/um/include/asm/mmu_context.h
@@ -10,7 +10,26 @@
 #include <asm/mmu.h>
 extern void uml_setup_stubs(struct mm_struct *mm);
+/*
+ * Needed since we do not use the asm-generic/mm_hooks.h:
+ */
+static inline void arch_dup_mmap(struct mm_struct *oldmm, struct mm_struct *mm)
+{
+        uml_setup_stubs(mm);
+}
 extern void arch_exit_mmap(struct mm_struct *mm);
+static inline void arch_unmap(struct mm_struct *mm,
+                        struct vm_area_struct *vma,
+                        unsigned long start, unsigned long end)
+{
+}
+static inline void arch_bprm_mm_init(struct mm_struct *mm,
+                                     struct vm_area_struct *vma)
+{
+}
+/*
+ * end asm-generic/mm_hooks.h functions
+ */
 #define deactivate_mm(tsk,mm)   do { } while (0)
@@ -41,11 +60,6 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
        }
 }
-static inline void arch_dup_mmap(struct mm_struct *oldmm, struct mm_struct *mm)
-{
-        uml_setup_stubs(mm);
-}
 static inline void enter_lazy_tlb(struct mm_struct *mm, 
                                  struct task_struct *tsk)
 {
diff --git a/arch/unicore32/include/asm/mmu_context.h b/arch/unicore32/include/asm/mmu_context.h
index ef470a7a3d0f..1cb5220afaf9 100644
--- a/arch/unicore32/include/asm/mmu_context.h
+++ b/arch/unicore32/include/asm/mmu_context.h
@@ -86,4 +86,15 @@ static inline void arch_dup_mmap(struct mm_struct *oldmm,
 {
 }
+static inline void arch_unmap(struct mm_struct *mm,
+                        struct vm_area_struct *vma,
+                        unsigned long start, unsigned long end)
+{
+}
+static inline void arch_bprm_mm_init(struct mm_struct *mm,
+                                     struct vm_area_struct *vma)
+{
+}
 #endif
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 41a503c15862..bea3a0159496 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -248,6 +248,10 @@ config HAVE_INTEL_TXT
        def_bool y
        depends on INTEL_IOMMU && ACPI
+config X86_INTEL_MPX
+        def_bool y
+        depends on CPU_SUP_INTEL
 config X86_32_SMP
        def_bool y
        depends on X86_32 && SMP
@@ -988,6 +992,24 @@ config X86_ESPFIX64
        def_bool y
        depends on X86_16BIT && X86_64
+config X86_VSYSCALL_EMULATION
+       bool "Enable vsyscall emulation" if EXPERT
+       default y
+       depends on X86_64
+       ---help---
+         This enables emulation of the legacy vsyscall page.  Disabling
+         it is roughly equivalent to booting with vsyscall=none, except
+         that it will also disable the helpful warning if a program
+         tries to use a vsyscall.  With this option set to N, offending
+         programs will just segfault, citing addresses of the form
+         0xffffffffff600?00.
+         This option is required by many programs built before 2013, and
+         care should be used even with newer programs if set to N.
+         Disabling this option saves about 7K of kernel size and
+         possibly 4K of additional runtime pagetable memory.
 config TOSHIBA
        tristate "Toshiba Laptop support"
        depends on X86_32
diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/Makefile
index be1e07d4b596..d999398928bc 100644
--- a/arch/x86/boot/compressed/Makefile
+++ b/arch/x86/boot/compressed/Makefile
@@ -3,6 +3,18 @@
 #
 # create a compressed vmlinux image from the original vmlinux
 #
+# vmlinuz is:
+#       decompression code (*.o)
+#       asm globals (piggy.S), including:
+#               vmlinux.bin.(gz|bz2|lzma|...)
+#
+# vmlinux.bin is:
+#       vmlinux stripped of debugging and comments
+# vmlinux.bin.all is:
+#       vmlinux.bin + vmlinux.relocs
+# vmlinux.bin.(gz|bz2|lzma|...) is:
+#       (see scripts/Makefile.lib size_append)
+#       compressed vmlinux.bin.all + u32 size of vmlinux.bin.all
 targets := vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma \
        vmlinux.bin.xz vmlinux.bin.lzo vmlinux.bin.lz4
@@ -35,7 +47,8 @@ vmlinux-objs-$(CONFIG_RANDOMIZE_BASE) += $(obj)/aslr.o
 $(obj)/eboot.o: KBUILD_CFLAGS += -fshort-wchar -mno-red-zone
-vmlinux-objs-$(CONFIG_EFI_STUB) += $(obj)/eboot.o $(obj)/efi_stub_$(BITS).o
+vmlinux-objs-$(CONFIG_EFI_STUB) += $(obj)/eboot.o $(obj)/efi_stub_$(BITS).o \
+        $(objtree)/drivers/firmware/efi/libstub/lib.a
 $(obj)/vmlinux: $(vmlinux-objs-y) FORCE
        $(call if_changed,ld)
@@ -76,7 +89,7 @@ suffix-$(CONFIG_KERNEL_XZ)	:= xz
 suffix-$(CONFIG_KERNEL_LZO)     := lzo
 suffix-$(CONFIG_KERNEL_LZ4)     := lz4
-RUN_SIZE = $(shell objdump -h vmlinux | \
+RUN_SIZE = $(shell $(OBJDUMP) -h vmlinux | \
             perl $(srctree)/arch/x86/tools/calc_run_size.pl)
 quiet_cmd_mkpiggy = MKPIGGY $@
      cmd_mkpiggy = $(obj)/mkpiggy $< $(RUN_SIZE) > $@ || ( rm -f $@ ; false )
diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c
index 1acf605a646d..92b9a5f2aed6 100644
--- a/arch/x86/boot/compressed/eboot.c
+++ b/arch/x86/boot/compressed/eboot.c
@@ -21,8 +21,10 @@ static efi_system_table_t *sys_table;
 static struct efi_config *efi_early;
-#define efi_call_early(f, ...)                                          \
+__pure const struct efi_config *__efi_early(void)
-        efi_early->call(efi_early->f, __VA_ARGS__);
+{
+        return efi_early;
+}
 #define BOOT_SERVICES(bits)                                             \
 static void setup_boot_services##bits(struct efi_config *c)             \
@@ -285,8 +287,6 @@ void efi_char16_printk(efi_system_table_t *table, efi_char16_t *str)
        }
 }
-#include "../../../../drivers/firmware/efi/libstub/efi-stub-helper.c"
 static void find_bits(unsigned long mask, u8 *pos, u8 *size)
 {
        u8 first, len;
diff --git a/arch/x86/boot/compressed/eboot.h b/arch/x86/boot/compressed/eboot.h
index c88c31ecad12..d487e727f1ec 100644
--- a/arch/x86/boot/compressed/eboot.h
+++ b/arch/x86/boot/compressed/eboot.h
@@ -103,20 +103,4 @@ struct efi_uga_draw_protocol {
        void *blt;
 };
-struct efi_config {
-        u64 image_handle;
-        u64 table;
-        u64 allocate_pool;
-        u64 allocate_pages;
-        u64 get_memory_map;
-        u64 free_pool;
-        u64 free_pages;
-        u64 locate_handle;
-        u64 handle_protocol;
-        u64 exit_boot_services;
-        u64 text_output;
-        efi_status_t (*call)(unsigned long, ...);
-        bool is64;
-} __packed;
 #endif /* BOOT_COMPRESSED_EBOOT_H */
diff --git a/arch/x86/boot/compressed/misc.c b/arch/x86/boot/compressed/misc.c
index 30dd59a9f0b4..dcc1c536cc21 100644
--- a/arch/x86/boot/compressed/misc.c
+++ b/arch/x86/boot/compressed/misc.c
@@ -260,7 +260,7 @@ static void handle_relocations(void *output, unsigned long output_len)
        /*
         * Process relocations: 32 bit relocations first then 64 bit after.
-         * Two sets of binary relocations are added to the end of the kernel
+         * Three sets of binary relocations are added to the end of the kernel
         * before compression. Each relocation table entry is the kernel
         * address of the location which needs to be updated stored as a
         * 32-bit value which is sign extended to 64 bits.
@@ -270,6 +270,8 @@ static void handle_relocations(void *output, unsigned long output_len)
         * kernel bits...
         * 0 - zero terminator for 64 bit relocations
         * 64 bit relocation repeated
+         * 0 - zero terminator for inverse 32 bit relocations
+         * 32 bit inverse relocation repeated
         * 0 - zero terminator for 32 bit relocations
         * 32 bit relocation repeated
         *
@@ -286,6 +288,16 @@ static void handle_relocations(void *output, unsigned long output_len)
                *(uint32_t *)ptr += delta;
        }
 #ifdef CONFIG_X86_64
+        while (*--reloc) {
+                long extended = *reloc;
+                extended += map;
+                ptr = (unsigned long)extended;
+                if (ptr < min_addr || ptr > max_addr)
+                        error("inverse 32-bit relocation outside of kernel!\n");
+                *(int32_t *)ptr -= delta;
+        }
        for (reloc--; *reloc; reloc--) {
                long extended = *reloc;
                extended += map;
diff --git a/arch/x86/configs/i386_defconfig b/arch/x86/configs/i386_defconfig
index 32d2e7056c87..419819d6dab3 100644
--- a/arch/x86/configs/i386_defconfig
+++ b/arch/x86/configs/i386_defconfig
@@ -8,6 +8,7 @@ CONFIG_TASKSTATS=y
 CONFIG_TASK_DELAY_ACCT=y
 CONFIG_TASK_XACCT=y
 CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_FHANDLE=y
 CONFIG_AUDIT=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/x86/configs/x86_64_defconfig b/arch/x86/configs/x86_64_defconfig
index a481dd4755d5..4c311ddd973b 100644
--- a/arch/x86/configs/x86_64_defconfig
+++ b/arch/x86/configs/x86_64_defconfig
@@ -7,6 +7,7 @@ CONFIG_TASKSTATS=y
 CONFIG_TASK_DELAY_ACCT=y
 CONFIG_TASK_XACCT=y
 CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_FHANDLE=y
 CONFIG_AUDIT=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/x86/ia32/ia32_aout.c b/arch/x86/ia32/ia32_aout.c
index df91466f973d..ae6aad1d24f7 100644
--- a/arch/x86/ia32/ia32_aout.c
+++ b/arch/x86/ia32/ia32_aout.c
@@ -342,8 +342,8 @@ static int load_aout_binary(struct linux_binprm *bprm)
                            time_after(jiffies, error_time + 5*HZ)) {
                        printk(KERN_WARNING
                               "fd_offset is not page aligned. Please convert "
-                               "program: %s\n",
+                               "program: %pD\n",
-                               bprm->file->f_path.dentry->d_name.name);
+                               bprm->file);
                        error_time = jiffies;
                }
 #endif
@@ -429,8 +429,8 @@ static int load_aout_library(struct file *file)
                if (time_after(jiffies, error_time + 5*HZ)) {
                        printk(KERN_WARNING
                               "N_TXTOFF is not page aligned. Please convert "
-                               "library: %s\n",
+                               "library: %pD\n",
-                               file->f_path.dentry->d_name.name);
+                               file);
                        error_time = jiffies;
                }
 #endif
diff --git a/arch/x86/include/asm/cacheflush.h b/arch/x86/include/asm/cacheflush.h
index 9863ee3747da..47c8e32f621a 100644
--- a/arch/x86/include/asm/cacheflush.h
+++ b/arch/x86/include/asm/cacheflush.h
@@ -5,65 +5,6 @@
 #include <asm-generic/cacheflush.h>
 #include <asm/special_insns.h>
-#ifdef CONFIG_X86_PAT
-/*
- * X86 PAT uses page flags WC and Uncached together to keep track of
- * memory type of pages that have backing page struct. X86 PAT supports 3
- * different memory types, _PAGE_CACHE_WB, _PAGE_CACHE_WC and
- * _PAGE_CACHE_UC_MINUS and fourth state where page's memory type has not
- * been changed from its default (value of -1 used to denote this).
- * Note we do not support _PAGE_CACHE_UC here.
- */
-#define _PGMT_DEFAULT           0
-#define _PGMT_WC                (1UL << PG_arch_1)
-#define _PGMT_UC_MINUS          (1UL << PG_uncached)
-#define _PGMT_WB                (1UL << PG_uncached | 1UL << PG_arch_1)
-#define _PGMT_MASK              (1UL << PG_uncached | 1UL << PG_arch_1)
-#define _PGMT_CLEAR_MASK        (~_PGMT_MASK)
-static inline unsigned long get_page_memtype(struct page *pg)
-{
-        unsigned long pg_flags = pg->flags & _PGMT_MASK;
-        if (pg_flags == _PGMT_DEFAULT)
-                return -1;
-        else if (pg_flags == _PGMT_WC)
-                return _PAGE_CACHE_WC;
-        else if (pg_flags == _PGMT_UC_MINUS)
-                return _PAGE_CACHE_UC_MINUS;
-        else
-                return _PAGE_CACHE_WB;
-}
-static inline void set_page_memtype(struct page *pg, unsigned long memtype)
-{
-        unsigned long memtype_flags = _PGMT_DEFAULT;
-        unsigned long old_flags;
-        unsigned long new_flags;
-        switch (memtype) {
-        case _PAGE_CACHE_WC:
-                memtype_flags = _PGMT_WC;
-                break;
-        case _PAGE_CACHE_UC_MINUS:
-                memtype_flags = _PGMT_UC_MINUS;
-                break;
-        case _PAGE_CACHE_WB:
-                memtype_flags = _PGMT_WB;
-                break;
-        }
-        do {
-                old_flags = pg->flags;
-                new_flags = (old_flags & _PGMT_CLEAR_MASK) | memtype_flags;
-        } while (cmpxchg(&pg->flags, old_flags, new_flags) != old_flags);
-}
-#else
-static inline unsigned long get_page_memtype(struct page *pg) { return -1; }
-static inline void set_page_memtype(struct page *pg, unsigned long memtype) { }
-#endif
 /*
 * The set_memory_* API can be used to change various attributes of a virtual
 * address range. The attributes include:
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 0bb1335313b2..aede2c347bde 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -189,6 +189,11 @@
 #define X86_FEATURE_DTHERM      ( 7*32+ 7) /* Digital Thermal Sensor */
 #define X86_FEATURE_HW_PSTATE   ( 7*32+ 8) /* AMD HW-PState */
 #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
+#define X86_FEATURE_HWP         ( 7*32+ 10) /* "hwp" Intel HWP */
+#define X86_FEATURE_HWP_NOITFY  ( 7*32+ 11) /* Intel HWP_NOTIFY */
+#define X86_FEATURE_HWP_ACT_WINDOW ( 7*32+ 12) /* Intel HWP_ACT_WINDOW */
+#define X86_FEATURE_HWP_EPP     ( 7*32+13) /* Intel HWP_EPP */
+#define X86_FEATURE_HWP_PKG_REQ ( 7*32+14) /* Intel HWP_PKG_REQ */
 /* Virtualization flags: Linux defined, word 8 */
 #define X86_FEATURE_TPR_SHADOW  ( 8*32+ 0) /* Intel TPR Shadow */
diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h
index 97534a7d38e3..f226df064660 100644
--- a/arch/x86/include/asm/disabled-features.h
+++ b/arch/x86/include/asm/disabled-features.h
@@ -10,6 +10,12 @@
 * cpu_feature_enabled().
 */
+#ifdef CONFIG_X86_INTEL_MPX
+# define DISABLE_MPX    0
+#else
+# define DISABLE_MPX    (1<<(X86_FEATURE_MPX & 31))
+#endif
 #ifdef CONFIG_X86_64
 # define DISABLE_VME            (1<<(X86_FEATURE_VME & 31))
 # define DISABLE_K6_MTRR        (1<<(X86_FEATURE_K6_MTRR & 31))
@@ -34,6 +40,6 @@
 #define DISABLED_MASK6  0
 #define DISABLED_MASK7  0
 #define DISABLED_MASK8  0
-#define DISABLED_MASK9  0
+#define DISABLED_MASK9  (DISABLE_MPX)
 #endif /* _ASM_X86_DISABLED_FEATURES_H */
diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h
index 9b11757975d0..25bce45c6fc4 100644
--- a/arch/x86/include/asm/efi.h
+++ b/arch/x86/include/asm/efi.h
@@ -158,6 +158,30 @@ static inline efi_status_t efi_thunk_set_virtual_address_map(
 }
 #endif /* CONFIG_EFI_MIXED */
+/* arch specific definitions used by the stub code */
+struct efi_config {
+        u64 image_handle;
+        u64 table;
+        u64 allocate_pool;
+        u64 allocate_pages;
+        u64 get_memory_map;
+        u64 free_pool;
+        u64 free_pages;
+        u64 locate_handle;
+        u64 handle_protocol;
+        u64 exit_boot_services;
+        u64 text_output;
+        efi_status_t (*call)(unsigned long, ...);
+        bool is64;
+} __packed;
+__pure const struct efi_config *__efi_early(void);
+#define efi_call_early(f, ...)                                          \
+        __efi_early()->call(__efi_early()->f, __VA_ARGS__);
 extern bool efi_reboot_required(void);
 #else
diff --git a/arch/x86/include/asm/fb.h b/arch/x86/include/asm/fb.h
index 2519d0679d99..c3dd5e71f439 100644
--- a/arch/x86/include/asm/fb.h
+++ b/arch/x86/include/asm/fb.h
@@ -8,8 +8,12 @@
 static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
                                unsigned long off)
 {
+        unsigned long prot;
+        prot = pgprot_val(vma->vm_page_prot) & ~_PAGE_CACHE_MASK;
        if (boot_cpu_data.x86 > 3)
-                pgprot_val(vma->vm_page_prot) |= _PAGE_PCD;
+                pgprot_val(vma->vm_page_prot) =
+                        prot | cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS);
 }
 extern int fb_is_primary_device(struct fb_info *info);
diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h
index ffb1733ac91f..f80d70009ff8 100644
--- a/arch/x86/include/asm/fixmap.h
+++ b/arch/x86/include/asm/fixmap.h
@@ -69,7 +69,9 @@ enum fixed_addresses {
 #ifdef CONFIG_X86_32
        FIX_HOLE,
 #else
+#ifdef CONFIG_X86_VSYSCALL_EMULATION
        VSYSCALL_PAGE = (FIXADDR_TOP - VSYSCALL_ADDR) >> PAGE_SHIFT,
+#endif
 #ifdef CONFIG_PARAVIRT_CLOCK
        PVCLOCK_FIXMAP_BEGIN,
        PVCLOCK_FIXMAP_END = PVCLOCK_FIXMAP_BEGIN+PVCLOCK_VSYSCALL_NR_PAGES-1,
@@ -136,9 +138,7 @@ enum fixed_addresses {
 extern void reserve_top_address(unsigned long reserve);
 #define FIXADDR_SIZE    (__end_of_permanent_fixed_addresses << PAGE_SHIFT)
-#define FIXADDR_BOOT_SIZE       (__end_of_fixed_addresses << PAGE_SHIFT)
 #define FIXADDR_START           (FIXADDR_TOP - FIXADDR_SIZE)
-#define FIXADDR_BOOT_START      (FIXADDR_TOP - FIXADDR_BOOT_SIZE)
 extern int fixmaps_set;
diff --git a/arch/x86/include/asm/ftrace.h b/arch/x86/include/asm/ftrace.h
index e1f7fecaa7d6..f45acad3c4b6 100644
--- a/arch/x86/include/asm/ftrace.h
+++ b/arch/x86/include/asm/ftrace.h
@@ -1,39 +1,6 @@
 #ifndef _ASM_X86_FTRACE_H
 #define _ASM_X86_FTRACE_H
-#ifdef __ASSEMBLY__
-        /* skip is set if the stack was already partially adjusted */
-        .macro MCOUNT_SAVE_FRAME skip=0
-         /*
-          * We add enough stack to save all regs.
-          */
-        subq $(SS+8-\skip), %rsp
-        movq %rax, RAX(%rsp)
-        movq %rcx, RCX(%rsp)
-        movq %rdx, RDX(%rsp)
-        movq %rsi, RSI(%rsp)
-        movq %rdi, RDI(%rsp)
-        movq %r8, R8(%rsp)
-        movq %r9, R9(%rsp)
-         /* Move RIP to its proper location */
-        movq SS+8(%rsp), %rdx
-        movq %rdx, RIP(%rsp)
-        .endm
-        .macro MCOUNT_RESTORE_FRAME skip=0
-        movq R9(%rsp), %r9
-        movq R8(%rsp), %r8
-        movq RDI(%rsp), %rdi
-        movq RSI(%rsp), %rsi
-        movq RDX(%rsp), %rdx
-        movq RCX(%rsp), %rcx
-        movq RAX(%rsp), %rax
-        addq $(SS+8-\skip), %rsp
-        .endm
-#endif
 #ifdef CONFIG_FUNCTION_TRACER
 #ifdef CC_USING_FENTRY
 # define MCOUNT_ADDR            ((long)(__fentry__))
diff --git a/arch/x86/include/asm/highmem.h b/arch/x86/include/asm/highmem.h
index 302a323b3f67..04e9d023168f 100644
--- a/arch/x86/include/asm/highmem.h
+++ b/arch/x86/include/asm/highmem.h
@@ -38,17 +38,20 @@ extern unsigned long highstart_pfn, highend_pfn;
 /*
 * Ordering is:
 *
- * FIXADDR_TOP
+ * high memory on:                                    high_memory off:
- *                      fixed_addresses
+ *    FIXADDR_TOP                                        FIXADDR_TOP
- * FIXADDR_START
+ *        fixed addresses                                    fixed addresses
- *                      temp fixed addresses
+ *    FIXADDR_START                                      FIXADDR_START
- * FIXADDR_BOOT_START
+ *        temp fixed addresses/persistent kmap area      VMALLOC_END
- *                      Persistent kmap area
+ *    PKMAP_BASE                                             temp fixed addresses/vmalloc area
- * PKMAP_BASE
+ *    VMALLOC_END                                        VMALLOC_START
- * VMALLOC_END
+ *        vmalloc area                                   high_memory
- *                      Vmalloc area
+ *    VMALLOC_START
- * VMALLOC_START
+ *    high_memory
- * high_memory
+ *
+ * The temp fixed area is only used during boot for early_ioremap(), and
+ * it is unused when the ioremap() is functional. vmalloc/pkmap area become
+ * available after early boot so the temp fixed area is available for re-use.
 */
 #define LAST_PKMAP_MASK (LAST_PKMAP-1)
 #define PKMAP_NR(virt)  ((virt-PKMAP_BASE) >> PAGE_SHIFT)
diff --git a/arch/x86/include/asm/insn.h b/arch/x86/include/asm/insn.h
index 48eb30a86062..47f29b1d1846 100644
--- a/arch/x86/include/asm/insn.h
+++ b/arch/x86/include/asm/insn.h
@@ -65,6 +65,7 @@ struct insn {
        unsigned char x86_64;
        const insn_byte_t *kaddr;       /* kernel address of insn to analyze */
+        const insn_byte_t *end_kaddr;   /* kernel address of last insn in buffer */
        const insn_byte_t *next_byte;
 };
@@ -96,7 +97,7 @@ struct insn {
 #define X86_VEX_P(vex)  ((vex) & 0x03)          /* VEX3 Byte2, VEX2 Byte1 */
 #define X86_VEX_M_MAX   0x1f                    /* VEX3.M Maximum value */
-extern void insn_init(struct insn *insn, const void *kaddr, int x86_64);
+extern void insn_init(struct insn *insn, const void *kaddr, int buf_len, int x86_64);
 extern void insn_get_prefixes(struct insn *insn);
 extern void insn_get_opcode(struct insn *insn);
 extern void insn_get_modrm(struct insn *insn);
@@ -115,12 +116,13 @@ static inline void insn_get_attribute(struct insn *insn)
 extern int insn_rip_relative(struct insn *insn);
 /* Init insn for kernel text */
-static inline void kernel_insn_init(struct insn *insn, const void *kaddr)
+static inline void kernel_insn_init(struct insn *insn,
+                                    const void *kaddr, int buf_len)
 {
 #ifdef CONFIG_X86_64
-        insn_init(insn, kaddr, 1);
+        insn_init(insn, kaddr, buf_len, 1);
 #else /* CONFIG_X86_32 */
-        insn_init(insn, kaddr, 0);
+        insn_init(insn, kaddr, buf_len, 0);
 #endif
 }
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index b8237d8a1e0c..34a5b93704d3 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -74,6 +74,9 @@ build_mmio_write(__writel, "l", unsigned int, "r", )
 #define __raw_readw __readw
 #define __raw_readl __readl
+#define writeb_relaxed(v, a) __writeb(v, a)
+#define writew_relaxed(v, a) __writew(v, a)
+#define writel_relaxed(v, a) __writel(v, a)
 #define __raw_writeb __writeb
 #define __raw_writew __writew
 #define __raw_writel __writel
@@ -86,6 +89,7 @@ build_mmio_read(readq, "q", unsigned long, "=r", :"memory")
 build_mmio_write(writeq, "q", unsigned long, "r", :"memory")
 #define readq_relaxed(a)        readq(a)
+#define writeq_relaxed(v, a)    writeq(v, a)
 #define __raw_readq(a)          readq(a)
 #define __raw_writeq(val, addr) writeq(val, addr)
@@ -310,11 +314,11 @@ BUILDIO(b, b, char)
 BUILDIO(w, w, short)
 BUILDIO(l, , int)
-extern void *xlate_dev_mem_ptr(unsigned long phys);
+extern void *xlate_dev_mem_ptr(phys_addr_t phys);
-extern void unxlate_dev_mem_ptr(unsigned long phys, void *addr);
+extern void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr);
 extern int ioremap_change_attr(unsigned long vaddr, unsigned long size,
-                                unsigned long prot_val);
+                                enum page_cache_mode pcm);
 extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size);
 extern bool is_early_ioremap_ptep(pte_t *ptep);
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 958b90f761e5..51b26e895933 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -34,6 +34,10 @@
 #define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
 #define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
+/* AMD-specific bits */
+#define MCI_STATUS_DEFERRED     (1ULL<<44)  /* declare an uncorrected error */
+#define MCI_STATUS_POISON       (1ULL<<43)  /* access poisonous data */
 /*
 * Note that the full MCACOD field of IA32_MCi_STATUS MSR is
 * bits 15:0.  But bit 12 is the 'F' bit, defined for corrected
@@ -78,7 +82,6 @@
 /* Software defined banks */
 #define MCE_EXTENDED_BANK       128
 #define MCE_THERMAL_BANK        (MCE_EXTENDED_BANK + 0)
-#define K8_MCE_THRESHOLD_BASE   (MCE_EXTENDED_BANK + 1)
 #define MCE_LOG_LEN 32
 #define MCE_LOG_SIGNATURE       "MACHINECHECK"
diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
index 64dc362506b7..201b520521ed 100644
--- a/arch/x86/include/asm/microcode.h
+++ b/arch/x86/include/asm/microcode.h
@@ -78,6 +78,7 @@ static inline void __exit exit_amd_microcode(void) {}
 extern void __init load_ucode_bsp(void);
 extern void load_ucode_ap(void);
 extern int __init save_microcode_in_initrd(void);
+void reload_early_microcode(void);
 #else
 static inline void __init load_ucode_bsp(void) {}
 static inline void load_ucode_ap(void) {}
@@ -85,6 +86,7 @@ static inline int __init save_microcode_in_initrd(void)
 {
        return 0;
 }
+static inline void reload_early_microcode(void) {}
 #endif
 #endif /* _ASM_X86_MICROCODE_H */
diff --git a/arch/x86/include/asm/microcode_amd.h b/arch/x86/include/asm/microcode_amd.h
index b7b10b82d3e5..af935397e053 100644
--- a/arch/x86/include/asm/microcode_amd.h
+++ b/arch/x86/include/asm/microcode_amd.h
@@ -59,7 +59,7 @@ static inline u16 find_equiv_id(struct equiv_cpu_entry *equiv_cpu_table,
 extern int __apply_microcode_amd(struct microcode_amd *mc_amd);
 extern int apply_microcode_amd(int cpu);
-extern enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t size);
+extern enum ucode_state load_microcode_amd(int cpu, u8 family, const u8 *data, size_t size);
 #define PATCH_MAX_SIZE PAGE_SIZE
 extern u8 amd_ucode_patch[PATCH_MAX_SIZE];
@@ -68,10 +68,12 @@ extern u8 amd_ucode_patch[PATCH_MAX_SIZE];
 extern void __init load_ucode_amd_bsp(void);
 extern void load_ucode_amd_ap(void);
 extern int __init save_microcode_in_initrd_amd(void);
+void reload_ucode_amd(void);
 #else
 static inline void __init load_ucode_amd_bsp(void) {}
 static inline void load_ucode_amd_ap(void) {}
 static inline int __init save_microcode_in_initrd_amd(void) { return -EINVAL; }
+void reload_ucode_amd(void) {}
 #endif
 #endif /* _ASM_X86_MICROCODE_AMD_H */
diff --git a/arch/x86/include/asm/microcode_intel.h b/arch/x86/include/asm/microcode_intel.h
index bbe296e0bce1..dd4c20043ce7 100644
--- a/arch/x86/include/asm/microcode_intel.h
+++ b/arch/x86/include/asm/microcode_intel.h
@@ -68,11 +68,13 @@ extern void __init load_ucode_intel_bsp(void);
 extern void load_ucode_intel_ap(void);
 extern void show_ucode_info_early(void);
 extern int __init save_microcode_in_initrd_intel(void);
+void reload_ucode_intel(void);
 #else
 static inline __init void load_ucode_intel_bsp(void) {}
 static inline void load_ucode_intel_ap(void) {}
 static inline void show_ucode_info_early(void) {}
 static inline int __init save_microcode_in_initrd_intel(void) { return -EINVAL; }
+static inline void reload_ucode_intel(void) {}
 #endif
 #if defined(CONFIG_MICROCODE_INTEL_EARLY) && defined(CONFIG_HOTPLUG_CPU)
diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h
index 166af2a8e865..40269a2bf6f9 100644
--- a/arch/x86/include/asm/mmu_context.h
+++ b/arch/x86/include/asm/mmu_context.h
@@ -10,9 +10,8 @@
 #include <asm/pgalloc.h>
 #include <asm/tlbflush.h>
 #include <asm/paravirt.h>
+#include <asm/mpx.h>
 #ifndef CONFIG_PARAVIRT
-#include <asm-generic/mm_hooks.h>
 static inline void paravirt_activate_mm(struct mm_struct *prev,
                                        struct mm_struct *next)
 {
@@ -53,7 +52,16 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
                /* Stop flush ipis for the previous mm */
                cpumask_clear_cpu(cpu, mm_cpumask(prev));
-                /* Load the LDT, if the LDT is different: */
+                /*
+                 * Load the LDT, if the LDT is different.
+                 *
+                 * It's possible leave_mm(prev) has been called.  If so,
+                 * then prev->context.ldt could be out of sync with the
+                 * LDT descriptor or the LDT register.  This can only happen
+                 * if prev->context.ldt is non-null, since we never free
+                 * an LDT.  But LDTs can't be shared across mms, so
+                 * prev->context.ldt won't be equal to next->context.ldt.
+                 */
                if (unlikely(prev->context.ldt != next->context.ldt))
                        load_LDT_nolock(&next->context);
        }
@@ -102,4 +110,27 @@ do {						\
 } while (0)
 #endif
+static inline void arch_dup_mmap(struct mm_struct *oldmm,
+                                 struct mm_struct *mm)
+{
+        paravirt_arch_dup_mmap(oldmm, mm);
+}
+static inline void arch_exit_mmap(struct mm_struct *mm)
+{
+        paravirt_arch_exit_mmap(mm);
+}
+static inline void arch_bprm_mm_init(struct mm_struct *mm,
+                struct vm_area_struct *vma)
+{
+        mpx_mm_init(mm);
+}
+static inline void arch_unmap(struct mm_struct *mm, struct vm_area_struct *vma,
+                              unsigned long start, unsigned long end)
+{
+        mpx_notify_unmap(mm, vma, start, end);
+}
 #endif /* _ASM_X86_MMU_CONTEXT_H */
diff --git a/arch/x86/include/asm/mpx.h b/arch/x86/include/asm/mpx.h
new file mode 100644
index 000000000000..a952a13d59a7
--- /dev/null
+++ b/arch/x86/include/asm/mpx.h
@@ -0,0 +1,103 @@
+#ifndef _ASM_X86_MPX_H
+#define _ASM_X86_MPX_H
+#include <linux/types.h>
+#include <asm/ptrace.h>
+#include <asm/insn.h>
+/*
+ * NULL is theoretically a valid place to put the bounds
+ * directory, so point this at an invalid address.
+ */
+#define MPX_INVALID_BOUNDS_DIR  ((void __user *)-1)
+#define MPX_BNDCFG_ENABLE_FLAG  0x1
+#define MPX_BD_ENTRY_VALID_FLAG 0x1
+#ifdef CONFIG_X86_64
+/* upper 28 bits [47:20] of the virtual address in 64-bit used to
+ * index into bounds directory (BD).
+ */
+#define MPX_BD_ENTRY_OFFSET     28
+#define MPX_BD_ENTRY_SHIFT      3
+/* bits [19:3] of the virtual address in 64-bit used to index into
+ * bounds table (BT).
+ */
+#define MPX_BT_ENTRY_OFFSET     17
+#define MPX_BT_ENTRY_SHIFT      5
+#define MPX_IGN_BITS            3
+#define MPX_BD_ENTRY_TAIL       3
+#else
+#define MPX_BD_ENTRY_OFFSET     20
+#define MPX_BD_ENTRY_SHIFT      2
+#define MPX_BT_ENTRY_OFFSET     10
+#define MPX_BT_ENTRY_SHIFT      4
+#define MPX_IGN_BITS            2
+#define MPX_BD_ENTRY_TAIL       2
+#endif
+#define MPX_BD_SIZE_BYTES (1UL<<(MPX_BD_ENTRY_OFFSET+MPX_BD_ENTRY_SHIFT))
+#define MPX_BT_SIZE_BYTES (1UL<<(MPX_BT_ENTRY_OFFSET+MPX_BT_ENTRY_SHIFT))
+#define MPX_BNDSTA_TAIL         2
+#define MPX_BNDCFG_TAIL         12
+#define MPX_BNDSTA_ADDR_MASK    (~((1UL<<MPX_BNDSTA_TAIL)-1))
+#define MPX_BNDCFG_ADDR_MASK    (~((1UL<<MPX_BNDCFG_TAIL)-1))
+#define MPX_BT_ADDR_MASK        (~((1UL<<MPX_BD_ENTRY_TAIL)-1))
+#define MPX_BNDCFG_ADDR_MASK    (~((1UL<<MPX_BNDCFG_TAIL)-1))
+#define MPX_BNDSTA_ERROR_CODE   0x3
+#define MPX_BD_ENTRY_MASK       ((1<<MPX_BD_ENTRY_OFFSET)-1)
+#define MPX_BT_ENTRY_MASK       ((1<<MPX_BT_ENTRY_OFFSET)-1)
+#define MPX_GET_BD_ENTRY_OFFSET(addr)   ((((addr)>>(MPX_BT_ENTRY_OFFSET+ \
+                MPX_IGN_BITS)) & MPX_BD_ENTRY_MASK) << MPX_BD_ENTRY_SHIFT)
+#define MPX_GET_BT_ENTRY_OFFSET(addr)   ((((addr)>>MPX_IGN_BITS) & \
+                MPX_BT_ENTRY_MASK) << MPX_BT_ENTRY_SHIFT)
+#ifdef CONFIG_X86_INTEL_MPX
+siginfo_t *mpx_generate_siginfo(struct pt_regs *regs,
+                                struct xsave_struct *xsave_buf);
+int mpx_handle_bd_fault(struct xsave_struct *xsave_buf);
+static inline int kernel_managing_mpx_tables(struct mm_struct *mm)
+{
+        return (mm->bd_addr != MPX_INVALID_BOUNDS_DIR);
+}
+static inline void mpx_mm_init(struct mm_struct *mm)
+{
+        /*
+         * NULL is theoretically a valid place to put the bounds
+         * directory, so point this at an invalid address.
+         */
+        mm->bd_addr = MPX_INVALID_BOUNDS_DIR;
+}
+void mpx_notify_unmap(struct mm_struct *mm, struct vm_area_struct *vma,
+                      unsigned long start, unsigned long end);
+#else
+static inline siginfo_t *mpx_generate_siginfo(struct pt_regs *regs,
+                                              struct xsave_struct *xsave_buf)
+{
+        return NULL;
+}
+static inline int mpx_handle_bd_fault(struct xsave_struct *xsave_buf)
+{
+        return -EINVAL;
+}
+static inline int kernel_managing_mpx_tables(struct mm_struct *mm)
+{
+        return 0;
+}
+static inline void mpx_mm_init(struct mm_struct *mm)
+{
+}
+static inline void mpx_notify_unmap(struct mm_struct *mm,
+                                    struct vm_area_struct *vma,
+                                    unsigned long start, unsigned long end)
+{
+}
+#endif /* CONFIG_X86_INTEL_MPX */
+#endif /* _ASM_X86_MPX_H */
diff --git a/arch/x86/include/asm/page_64.h b/arch/x86/include/asm/page_64.h
index f408caf73430..b3bebf9e5746 100644
--- a/arch/x86/include/asm/page_64.h
+++ b/arch/x86/include/asm/page_64.h
@@ -39,6 +39,8 @@ void copy_page(void *to, void *from);
 #endif  /* !__ASSEMBLY__ */
-#define __HAVE_ARCH_GATE_AREA 1
+#ifdef CONFIG_X86_VSYSCALL_EMULATION
+# define __HAVE_ARCH_GATE_AREA 1
+#endif
 #endif /* _ASM_X86_PAGE_64_H */
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index cd6e1610e29e..32444ae939ca 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -330,13 +330,13 @@ static inline void paravirt_activate_mm(struct mm_struct *prev,
        PVOP_VCALL2(pv_mmu_ops.activate_mm, prev, next);
 }
-static inline void arch_dup_mmap(struct mm_struct *oldmm,
+static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm,
-                                 struct mm_struct *mm)
+                                          struct mm_struct *mm)
 {
        PVOP_VCALL2(pv_mmu_ops.dup_mmap, oldmm, mm);
 }
-static inline void arch_exit_mmap(struct mm_struct *mm)
+static inline void paravirt_arch_exit_mmap(struct mm_struct *mm)
 {
        PVOP_VCALL1(pv_mmu_ops.exit_mmap, mm);
 }
@@ -986,5 +986,15 @@ extern void default_banner(void);
 #endif /* __ASSEMBLY__ */
 #else  /* CONFIG_PARAVIRT */
 # define default_banner x86_init_noop
+#ifndef __ASSEMBLY__
+static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm,
+                                          struct mm_struct *mm)
+{
+}
+static inline void paravirt_arch_exit_mmap(struct mm_struct *mm)
+{
+}
+#endif /* __ASSEMBLY__ */
 #endif /* !CONFIG_PARAVIRT */
 #endif /* _ASM_X86_PARAVIRT_H */
diff --git a/arch/x86/include/asm/pat.h b/arch/x86/include/asm/pat.h
index e2c1668dde7a..91bc4ba95f91 100644
--- a/arch/x86/include/asm/pat.h
+++ b/arch/x86/include/asm/pat.h
@@ -11,16 +11,17 @@ static const int pat_enabled;
 #endif
 extern void pat_init(void);
+void pat_init_cache_modes(void);
 extern int reserve_memtype(u64 start, u64 end,
-                unsigned long req_type, unsigned long *ret_type);
+                enum page_cache_mode req_pcm, enum page_cache_mode *ret_pcm);
 extern int free_memtype(u64 start, u64 end);
 extern int kernel_map_sync_memtype(u64 base, unsigned long size,
-                unsigned long flag);
+                enum page_cache_mode pcm);
 int io_reserve_memtype(resource_size_t start, resource_size_t end,
-                        unsigned long *type);
+                        enum page_cache_mode *pcm);
 void io_free_memtype(resource_size_t start, resource_size_t end);
diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h
index fd472181a1d0..e0ba66ca68c6 100644
--- a/arch/x86/include/asm/percpu.h
+++ b/arch/x86/include/asm/percpu.h
@@ -64,7 +64,7 @@
 #define __percpu_prefix         ""
 #endif
-#define __percpu_arg(x)         __percpu_prefix "%P" #x
+#define __percpu_arg(x)         __percpu_prefix "%" #x
 /*
 * Initialized pointers to per-cpu variables needed for the boot
@@ -179,29 +179,58 @@ do {									\
        }                                                               \
 } while (0)
-#define percpu_from_op(op, var, constraint)             \
+#define percpu_from_op(op, var)                         \
 ({                                                      \
        typeof(var) pfo_ret__;                          \
        switch (sizeof(var)) {                          \
        case 1:                                         \
                asm(op "b "__percpu_arg(1)",%0"         \
                    : "=q" (pfo_ret__)                  \
-                    : constraint);                      \
+                    : "m" (var));                       \
                break;                                  \
        case 2:                                         \
                asm(op "w "__percpu_arg(1)",%0"         \
                    : "=r" (pfo_ret__)                  \
-                    : constraint);                      \
+                    : "m" (var));                       \
                break;                                  \
        case 4:                                         \
                asm(op "l "__percpu_arg(1)",%0"         \
                    : "=r" (pfo_ret__)                  \
-                    : constraint);                      \
+                    : "m" (var));                       \
                break;                                  \
        case 8:                                         \
                asm(op "q "__percpu_arg(1)",%0"         \
                    : "=r" (pfo_ret__)                  \
-                    : constraint);                      \
+                    : "m" (var));                       \
+                break;                                  \
+        default: __bad_percpu_size();                   \
+        }                                               \
+        pfo_ret__;                                      \
+})
+#define percpu_stable_op(op, var)                       \
+({                                                      \
+        typeof(var) pfo_ret__;                          \
+        switch (sizeof(var)) {                          \
+        case 1:                                         \
+                asm(op "b "__percpu_arg(P1)",%0"        \
+                    : "=q" (pfo_ret__)                  \
+                    : "p" (&(var)));                    \
+                break;                                  \
+        case 2:                                         \
+                asm(op "w "__percpu_arg(P1)",%0"        \
+                    : "=r" (pfo_ret__)                  \
+                    : "p" (&(var)));                    \
+                break;                                  \
+        case 4:                                         \
+                asm(op "l "__percpu_arg(P1)",%0"        \
+                    : "=r" (pfo_ret__)                  \
+                    : "p" (&(var)));                    \
+                break;                                  \
+        case 8:                                         \
+                asm(op "q "__percpu_arg(P1)",%0"        \
+                    : "=r" (pfo_ret__)                  \
+                    : "p" (&(var)));                    \
                break;                                  \
        default: __bad_percpu_size();                   \
        }                                               \
@@ -359,11 +388,11 @@ do {									\
 * per-thread variables implemented as per-cpu variables and thus
 * stable for the duration of the respective task.
 */
-#define this_cpu_read_stable(var)       percpu_from_op("mov", var, "p" (&(var)))
+#define this_cpu_read_stable(var)       percpu_stable_op("mov", var)
-#define raw_cpu_read_1(pcp)             percpu_from_op("mov", (pcp), "m"(pcp))
+#define raw_cpu_read_1(pcp)             percpu_from_op("mov", pcp)
-#define raw_cpu_read_2(pcp)             percpu_from_op("mov", (pcp), "m"(pcp))
+#define raw_cpu_read_2(pcp)             percpu_from_op("mov", pcp)
-#define raw_cpu_read_4(pcp)             percpu_from_op("mov", (pcp), "m"(pcp))
+#define raw_cpu_read_4(pcp)             percpu_from_op("mov", pcp)
 #define raw_cpu_write_1(pcp, val)       percpu_to_op("mov", (pcp), val)
 #define raw_cpu_write_2(pcp, val)       percpu_to_op("mov", (pcp), val)
@@ -381,9 +410,9 @@ do {									\
 #define raw_cpu_xchg_2(pcp, val)        percpu_xchg_op(pcp, val)
 #define raw_cpu_xchg_4(pcp, val)        percpu_xchg_op(pcp, val)
-#define this_cpu_read_1(pcp)            percpu_from_op("mov", (pcp), "m"(pcp))
+#define this_cpu_read_1(pcp)            percpu_from_op("mov", pcp)
-#define this_cpu_read_2(pcp)            percpu_from_op("mov", (pcp), "m"(pcp))
+#define this_cpu_read_2(pcp)            percpu_from_op("mov", pcp)
-#define this_cpu_read_4(pcp)            percpu_from_op("mov", (pcp), "m"(pcp))
+#define this_cpu_read_4(pcp)            percpu_from_op("mov", pcp)
 #define this_cpu_write_1(pcp, val)      percpu_to_op("mov", (pcp), val)
 #define this_cpu_write_2(pcp, val)      percpu_to_op("mov", (pcp), val)
 #define this_cpu_write_4(pcp, val)      percpu_to_op("mov", (pcp), val)
@@ -435,7 +464,7 @@ do {									\
 * 32 bit must fall back to generic operations.
 */
 #ifdef CONFIG_X86_64
-#define raw_cpu_read_8(pcp)                     percpu_from_op("mov", (pcp), "m"(pcp))
+#define raw_cpu_read_8(pcp)                     percpu_from_op("mov", pcp)
 #define raw_cpu_write_8(pcp, val)               percpu_to_op("mov", (pcp), val)
 #define raw_cpu_add_8(pcp, val)                 percpu_add_op((pcp), val)
 #define raw_cpu_and_8(pcp, val)                 percpu_to_op("and", (pcp), val)
@@ -444,7 +473,7 @@ do {									\
 #define raw_cpu_xchg_8(pcp, nval)               percpu_xchg_op(pcp, nval)
 #define raw_cpu_cmpxchg_8(pcp, oval, nval)      percpu_cmpxchg_op(pcp, oval, nval)
-#define this_cpu_read_8(pcp)                    percpu_from_op("mov", (pcp), "m"(pcp))
+#define this_cpu_read_8(pcp)                    percpu_from_op("mov", pcp)
 #define this_cpu_write_8(pcp, val)              percpu_to_op("mov", (pcp), val)
 #define this_cpu_add_8(pcp, val)                percpu_add_op((pcp), val)
 #define this_cpu_and_8(pcp, val)                percpu_to_op("and", (pcp), val)
@@ -522,7 +551,7 @@ static inline int x86_this_cpu_variable_test_bit(int nr,
 #include <asm-generic/percpu.h>
 /* We can use this directly for local CPU (faster). */
-DECLARE_PER_CPU(unsigned long, this_cpu_off);
+DECLARE_PER_CPU_READ_MOSTLY(unsigned long, this_cpu_off);
 #endif /* !__ASSEMBLY__ */
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 8dfc9fd094a3..dc0f6ed35b08 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -177,6 +177,9 @@ struct x86_pmu_capability {
 #define IBS_CAPS_BRNTRGT                (1U<<5)
 #define IBS_CAPS_OPCNTEXT               (1U<<6)
 #define IBS_CAPS_RIPINVALIDCHK          (1U<<7)
+#define IBS_CAPS_OPBRNFUSE              (1U<<8)
+#define IBS_CAPS_FETCHCTLEXTD           (1U<<9)
+#define IBS_CAPS_OPDATA4                (1U<<10)
 #define IBS_CAPS_DEFAULT                (IBS_CAPS_AVAIL         \
                                         | IBS_CAPS_FETCHSAM    \
diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
index aa97a070f09f..e8a5454acc99 100644
--- a/arch/x86/include/asm/pgtable.h
+++ b/arch/x86/include/asm/pgtable.h
@@ -9,9 +9,10 @@
 /*
 * Macro to mark a page protection value as UC-
 */
-#define pgprot_noncached(prot)                                  \
+#define pgprot_noncached(prot)                                          \
-        ((boot_cpu_data.x86 > 3)                                \
+        ((boot_cpu_data.x86 > 3)                                        \
-         ? (__pgprot(pgprot_val(prot) | _PAGE_CACHE_UC_MINUS))  \
+         ? (__pgprot(pgprot_val(prot) |                                 \
+                     cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS)))     \
         : (prot))
 #ifndef __ASSEMBLY__
@@ -99,6 +100,11 @@ static inline int pte_young(pte_t pte)
        return pte_flags(pte) & _PAGE_ACCESSED;
 }
+static inline int pmd_dirty(pmd_t pmd)
+{
+        return pmd_flags(pmd) & _PAGE_DIRTY;
+}
 static inline int pmd_young(pmd_t pmd)
 {
        return pmd_flags(pmd) & _PAGE_ACCESSED;
@@ -404,8 +410,8 @@ static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot)
 #define canon_pgprot(p) __pgprot(massage_pgprot(p))
 static inline int is_new_memtype_allowed(u64 paddr, unsigned long size,
-                                         unsigned long flags,
+                                         enum page_cache_mode pcm,
-                                         unsigned long new_flags)
+                                         enum page_cache_mode new_pcm)
 {
        /*
         * PAT type is always WB for untracked ranges, so no need to check.
@@ -419,10 +425,10 @@ static inline int is_new_memtype_allowed(u64 paddr, unsigned long size,
         * - request is uncached, return cannot be write-back
         * - request is write-combine, return cannot be write-back
         */
-        if ((flags == _PAGE_CACHE_UC_MINUS &&
+        if ((pcm == _PAGE_CACHE_MODE_UC_MINUS &&
-             new_flags == _PAGE_CACHE_WB) ||
+             new_pcm == _PAGE_CACHE_MODE_WB) ||
-            (flags == _PAGE_CACHE_WC &&
+            (pcm == _PAGE_CACHE_MODE_WC &&
-             new_flags == _PAGE_CACHE_WB)) {
+             new_pcm == _PAGE_CACHE_MODE_WB)) {
                return 0;
        }
diff --git a/arch/x86/include/asm/pgtable_32_types.h b/arch/x86/include/asm/pgtable_32_types.h
index ed5903be26fe..9fb2f2bc8245 100644
--- a/arch/x86/include/asm/pgtable_32_types.h
+++ b/arch/x86/include/asm/pgtable_32_types.h
@@ -37,7 +37,7 @@ extern bool __vmalloc_start_set; /* set once high_memory is set */
 #define LAST_PKMAP 1024
 #endif
-#define PKMAP_BASE ((FIXADDR_BOOT_START - PAGE_SIZE * (LAST_PKMAP + 1)) \
+#define PKMAP_BASE ((FIXADDR_START - PAGE_SIZE * (LAST_PKMAP + 1))      \
                    & PMD_MASK)
 #ifdef CONFIG_HIGHMEM
diff --git a/arch/x86/include/asm/pgtable_64_types.h b/arch/x86/include/asm/pgtable_64_types.h
index 7166e25ecb57..602b6028c5b6 100644
--- a/arch/x86/include/asm/pgtable_64_types.h
+++ b/arch/x86/include/asm/pgtable_64_types.h
@@ -63,6 +63,8 @@ typedef struct { pteval_t pte; } pte_t;
 #define MODULES_LEN   (MODULES_END - MODULES_VADDR)
 #define ESPFIX_PGD_ENTRY _AC(-2, UL)
 #define ESPFIX_BASE_ADDR (ESPFIX_PGD_ENTRY << PGDIR_SHIFT)
+#define EFI_VA_START     ( -4 * (_AC(1, UL) << 30))
+#define EFI_VA_END       (-68 * (_AC(1, UL) << 30))
 #define EARLY_DYNAMIC_PAGE_TABLES       64
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index 07789647bf33..af447f95e3be 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -128,11 +128,28 @@
                         _PAGE_SOFT_DIRTY | _PAGE_NUMA)
 #define _HPAGE_CHG_MASK (_PAGE_CHG_MASK | _PAGE_PSE | _PAGE_NUMA)
-#define _PAGE_CACHE_MASK        (_PAGE_PCD | _PAGE_PWT)
+/*
-#define _PAGE_CACHE_WB          (0)
+ * The cache modes defined here are used to translate between pure SW usage
-#define _PAGE_CACHE_WC          (_PAGE_PWT)
+ * and the HW defined cache mode bits and/or PAT entries.
-#define _PAGE_CACHE_UC_MINUS    (_PAGE_PCD)
+ *
-#define _PAGE_CACHE_UC          (_PAGE_PCD | _PAGE_PWT)
+ * The resulting bits for PWT, PCD and PAT should be chosen in a way
+ * to have the WB mode at index 0 (all bits clear). This is the default
+ * right now and likely would break too much if changed.
+ */
+#ifndef __ASSEMBLY__
+enum page_cache_mode {
+        _PAGE_CACHE_MODE_WB = 0,
+        _PAGE_CACHE_MODE_WC = 1,
+        _PAGE_CACHE_MODE_UC_MINUS = 2,
+        _PAGE_CACHE_MODE_UC = 3,
+        _PAGE_CACHE_MODE_WT = 4,
+        _PAGE_CACHE_MODE_WP = 5,
+        _PAGE_CACHE_MODE_NUM = 8
+};
+#endif
+#define _PAGE_CACHE_MASK        (_PAGE_PAT | _PAGE_PCD | _PAGE_PWT)
+#define _PAGE_NOCACHE           (cachemode2protval(_PAGE_CACHE_MODE_UC))
 #define PAGE_NONE       __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
 #define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \
@@ -156,41 +173,27 @@
 #define __PAGE_KERNEL_RO                (__PAGE_KERNEL & ~_PAGE_RW)
 #define __PAGE_KERNEL_RX                (__PAGE_KERNEL_EXEC & ~_PAGE_RW)
-#define __PAGE_KERNEL_EXEC_NOCACHE      (__PAGE_KERNEL_EXEC | _PAGE_PCD | _PAGE_PWT)
+#define __PAGE_KERNEL_NOCACHE           (__PAGE_KERNEL | _PAGE_NOCACHE)
-#define __PAGE_KERNEL_WC                (__PAGE_KERNEL | _PAGE_CACHE_WC)
-#define __PAGE_KERNEL_NOCACHE           (__PAGE_KERNEL | _PAGE_PCD | _PAGE_PWT)
-#define __PAGE_KERNEL_UC_MINUS          (__PAGE_KERNEL | _PAGE_PCD)
 #define __PAGE_KERNEL_VSYSCALL          (__PAGE_KERNEL_RX | _PAGE_USER)
 #define __PAGE_KERNEL_VVAR              (__PAGE_KERNEL_RO | _PAGE_USER)
-#define __PAGE_KERNEL_VVAR_NOCACHE      (__PAGE_KERNEL_VVAR | _PAGE_PCD | _PAGE_PWT)
 #define __PAGE_KERNEL_LARGE             (__PAGE_KERNEL | _PAGE_PSE)
-#define __PAGE_KERNEL_LARGE_NOCACHE     (__PAGE_KERNEL | _PAGE_CACHE_UC | _PAGE_PSE)
 #define __PAGE_KERNEL_LARGE_EXEC        (__PAGE_KERNEL_EXEC | _PAGE_PSE)
 #define __PAGE_KERNEL_IO                (__PAGE_KERNEL)
 #define __PAGE_KERNEL_IO_NOCACHE        (__PAGE_KERNEL_NOCACHE)
-#define __PAGE_KERNEL_IO_UC_MINUS       (__PAGE_KERNEL_UC_MINUS)
-#define __PAGE_KERNEL_IO_WC             (__PAGE_KERNEL_WC)
 #define PAGE_KERNEL                     __pgprot(__PAGE_KERNEL)
 #define PAGE_KERNEL_RO                  __pgprot(__PAGE_KERNEL_RO)
 #define PAGE_KERNEL_EXEC                __pgprot(__PAGE_KERNEL_EXEC)
 #define PAGE_KERNEL_RX                  __pgprot(__PAGE_KERNEL_RX)
-#define PAGE_KERNEL_WC                  __pgprot(__PAGE_KERNEL_WC)
 #define PAGE_KERNEL_NOCACHE             __pgprot(__PAGE_KERNEL_NOCACHE)
-#define PAGE_KERNEL_UC_MINUS            __pgprot(__PAGE_KERNEL_UC_MINUS)
-#define PAGE_KERNEL_EXEC_NOCACHE        __pgprot(__PAGE_KERNEL_EXEC_NOCACHE)
 #define PAGE_KERNEL_LARGE               __pgprot(__PAGE_KERNEL_LARGE)
-#define PAGE_KERNEL_LARGE_NOCACHE       __pgprot(__PAGE_KERNEL_LARGE_NOCACHE)
 #define PAGE_KERNEL_LARGE_EXEC          __pgprot(__PAGE_KERNEL_LARGE_EXEC)
 #define PAGE_KERNEL_VSYSCALL            __pgprot(__PAGE_KERNEL_VSYSCALL)
 #define PAGE_KERNEL_VVAR                __pgprot(__PAGE_KERNEL_VVAR)
-#define PAGE_KERNEL_VVAR_NOCACHE        __pgprot(__PAGE_KERNEL_VVAR_NOCACHE)
 #define PAGE_KERNEL_IO                  __pgprot(__PAGE_KERNEL_IO)
 #define PAGE_KERNEL_IO_NOCACHE          __pgprot(__PAGE_KERNEL_IO_NOCACHE)
-#define PAGE_KERNEL_IO_UC_MINUS         __pgprot(__PAGE_KERNEL_IO_UC_MINUS)
-#define PAGE_KERNEL_IO_WC               __pgprot(__PAGE_KERNEL_IO_WC)
 /*         xwr */
 #define __P000  PAGE_NONE
@@ -341,6 +344,59 @@ static inline pmdval_t pmdnuma_flags(pmd_t pmd)
 #define pgprot_val(x)   ((x).pgprot)
 #define __pgprot(x)     ((pgprot_t) { (x) } )
+extern uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM];
+extern uint8_t __pte2cachemode_tbl[8];
+#define __pte2cm_idx(cb)                                \
+        ((((cb) >> (_PAGE_BIT_PAT - 2)) & 4) |          \
+         (((cb) >> (_PAGE_BIT_PCD - 1)) & 2) |          \
+         (((cb) >> _PAGE_BIT_PWT) & 1))
+#define __cm_idx2pte(i)                                 \
+        ((((i) & 4) << (_PAGE_BIT_PAT - 2)) |           \
+         (((i) & 2) << (_PAGE_BIT_PCD - 1)) |           \
+         (((i) & 1) << _PAGE_BIT_PWT))
+static inline unsigned long cachemode2protval(enum page_cache_mode pcm)
+{
+        if (likely(pcm == 0))
+                return 0;
+        return __cachemode2pte_tbl[pcm];
+}
+static inline pgprot_t cachemode2pgprot(enum page_cache_mode pcm)
+{
+        return __pgprot(cachemode2protval(pcm));
+}
+static inline enum page_cache_mode pgprot2cachemode(pgprot_t pgprot)
+{
+        unsigned long masked;
+        masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK;
+        if (likely(masked == 0))
+                return 0;
+        return __pte2cachemode_tbl[__pte2cm_idx(masked)];
+}
+static inline pgprot_t pgprot_4k_2_large(pgprot_t pgprot)
+{
+        pgprot_t new;
+        unsigned long val;
+        val = pgprot_val(pgprot);
+        pgprot_val(new) = (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
+                ((val & _PAGE_PAT) << (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT));
+        return new;
+}
+static inline pgprot_t pgprot_large_2_4k(pgprot_t pgprot)
+{
+        pgprot_t new;
+        unsigned long val;
+        val = pgprot_val(pgprot);
+        pgprot_val(new) = (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
+                          ((val & _PAGE_PAT_LARGE) >>
+                           (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT));
+        return new;
+}
 typedef struct page *pgtable_t;
diff --git a/arch/x86/include/asm/platform_sst_audio.h b/arch/x86/include/asm/platform_sst_audio.h
index 0a4e140315b6..7249e6d0902d 100644
--- a/arch/x86/include/asm/platform_sst_audio.h
+++ b/arch/x86/include/asm/platform_sst_audio.h
@@ -16,6 +16,9 @@
 #include <linux/sfi.h>
+#define MAX_NUM_STREAMS_MRFLD   25
+#define MAX_NUM_STREAMS MAX_NUM_STREAMS_MRFLD
 enum sst_audio_task_id_mrfld {
        SST_TASK_ID_NONE = 0,
        SST_TASK_ID_SBA = 1,
@@ -73,6 +76,65 @@ struct sst_platform_data {
        unsigned int strm_map_size;
 };
+struct sst_info {
+        u32 iram_start;
+        u32 iram_end;
+        bool iram_use;
+        u32 dram_start;
+        u32 dram_end;
+        bool dram_use;
+        u32 imr_start;
+        u32 imr_end;
+        bool imr_use;
+        u32 mailbox_start;
+        bool use_elf;
+        bool lpe_viewpt_rqd;
+        unsigned int max_streams;
+        u32 dma_max_len;
+        u8 num_probes;
+};
+struct sst_lib_dnld_info {
+        unsigned int mod_base;
+        unsigned int mod_end;
+        unsigned int mod_table_offset;
+        unsigned int mod_table_size;
+        bool mod_ddr_dnld;
+};
+struct sst_res_info {
+        unsigned int shim_offset;
+        unsigned int shim_size;
+        unsigned int shim_phy_addr;
+        unsigned int ssp0_offset;
+        unsigned int ssp0_size;
+        unsigned int dma0_offset;
+        unsigned int dma0_size;
+        unsigned int dma1_offset;
+        unsigned int dma1_size;
+        unsigned int iram_offset;
+        unsigned int iram_size;
+        unsigned int dram_offset;
+        unsigned int dram_size;
+        unsigned int mbox_offset;
+        unsigned int mbox_size;
+        unsigned int acpi_lpe_res_index;
+        unsigned int acpi_ddr_index;
+        unsigned int acpi_ipc_irq_index;
+};
+struct sst_ipc_info {
+        int ipc_offset;
+        unsigned int mbox_recv_off;
+};
+struct sst_platform_info {
+        const struct sst_info *probe_data;
+        const struct sst_ipc_info *ipc_info;
+        const struct sst_res_info *res_info;
+        const struct sst_lib_dnld_info *lib_info;
+        const char *platform;
+};
 int add_sst_platform_device(void);
 #endif
diff --git a/arch/x86/include/asm/preempt.h b/arch/x86/include/asm/preempt.h
index 400873450e33..8f3271842533 100644
--- a/arch/x86/include/asm/preempt.h
+++ b/arch/x86/include/asm/preempt.h
@@ -30,9 +30,6 @@ static __always_inline void preempt_count_set(int pc)
 /*
 * must be macros to avoid header recursion hell
 */
-#define task_preempt_count(p) \
-        (task_thread_info(p)->saved_preempt_count & ~PREEMPT_NEED_RESCHED)
 #define init_task_preempt_count(p) do { \
        task_thread_info(p)->saved_preempt_count = PREEMPT_DISABLED; \
 } while (0)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index eb71ec794732..a092a0cce0b7 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -127,7 +127,7 @@ struct cpuinfo_x86 {
        /* Index into per_cpu list: */
        u16                     cpu_index;
        u32                     microcode;
-} __attribute__((__aligned__(SMP_CACHE_BYTES)));
+};
 #define X86_VENDOR_INTEL        0
 #define X86_VENDOR_CYRIX        1
@@ -151,7 +151,7 @@ extern __u32			cpu_caps_cleared[NCAPINTS];
 extern __u32                    cpu_caps_set[NCAPINTS];
 #ifdef CONFIG_SMP
-DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
+DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
 #else
 #define cpu_info                boot_cpu_data
@@ -374,13 +374,14 @@ struct lwp_struct {
        u8 reserved[128];
 };
-struct bndregs_struct {
+struct bndreg {
-        u64 bndregs[8];
+        u64 lower_bound;
+        u64 upper_bound;
 } __packed;
-struct bndcsr_struct {
+struct bndcsr {
-        u64 cfg_reg_u;
+        u64 bndcfgu;
-        u64 status_reg;
+        u64 bndstatus;
 } __packed;
 struct xsave_hdr_struct {
@@ -394,8 +395,8 @@ struct xsave_struct {
        struct xsave_hdr_struct xsave_hdr;
        struct ymmh_struct ymmh;
        struct lwp_struct lwp;
-        struct bndregs_struct bndregs;
+        struct bndreg bndreg[4];
-        struct bndcsr_struct bndcsr;
+        struct bndcsr bndcsr;
        /* new processor state extensions will go here */
 } __attribute__ ((packed, aligned (64)));
@@ -893,7 +894,13 @@ extern unsigned long thread_saved_pc(struct task_struct *tsk);
 #else
 /*
- * User space process size. 47bits minus one guard page.
+ * User space process size. 47bits minus one guard page.  The guard
+ * page is necessary on Intel CPUs: if a SYSCALL instruction is at
+ * the highest possible canonical userspace address, then that
+ * syscall will enter the kernel with a non-canonical return
+ * address, and SYSRET will explode dangerously.  We avoid this
+ * particular problem by preventing anything from being mapped
+ * at the maximum canonical address.
 */
 #define TASK_SIZE_MAX   ((1UL << 47) - PAGE_SIZE)
@@ -953,6 +960,24 @@ extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
 extern int get_tsc_mode(unsigned long adr);
 extern int set_tsc_mode(unsigned int val);
+/* Register/unregister a process' MPX related resource */
+#define MPX_ENABLE_MANAGEMENT(tsk)      mpx_enable_management((tsk))
+#define MPX_DISABLE_MANAGEMENT(tsk)     mpx_disable_management((tsk))
+#ifdef CONFIG_X86_INTEL_MPX
+extern int mpx_enable_management(struct task_struct *tsk);
+extern int mpx_disable_management(struct task_struct *tsk);
+#else
+static inline int mpx_enable_management(struct task_struct *tsk)
+{
+        return -EINVAL;
+}
+static inline int mpx_disable_management(struct task_struct *tsk)
+{
+        return -EINVAL;
+}
+#endif /* CONFIG_X86_INTEL_MPX */
 extern u16 amd_get_nb_id(int cpu);
 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
diff --git a/arch/x86/include/asm/spinlock.h b/arch/x86/include/asm/spinlock.h
index 9295016485c9..a4efe477ceab 100644
--- a/arch/x86/include/asm/spinlock.h
+++ b/arch/x86/include/asm/spinlock.h
@@ -183,8 +183,20 @@ static __always_inline void arch_spin_lock_flags(arch_spinlock_t *lock,
 static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
 {
-        while (arch_spin_is_locked(lock))
+        __ticket_t head = ACCESS_ONCE(lock->tickets.head);
+        for (;;) {
+                struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets);
+                /*
+                 * We need to check "unlocked" in a loop, tmp.head == head
+                 * can be false positive because of overflow.
+                 */
+                if (tmp.head == (tmp.tail & ~TICKET_SLOWPATH_FLAG) ||
+                    tmp.head != head)
+                        break;
                cpu_relax();
+        }
 }
 /*
diff --git a/arch/x86/include/asm/switch_to.h b/arch/x86/include/asm/switch_to.h
index d7f3b3b78ac3..751bf4b7bf11 100644
--- a/arch/x86/include/asm/switch_to.h
+++ b/arch/x86/include/asm/switch_to.h
@@ -79,12 +79,12 @@ do {									\
 #else /* CONFIG_X86_32 */
 /* frame pointer must be last for get_wchan */
-#define SAVE_CONTEXT    "pushf ; pushq %%rbp ; movq %%rsi,%%rbp\n\t"
+#define SAVE_CONTEXT    "pushq %%rbp ; movq %%rsi,%%rbp\n\t"
-#define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp ; popf\t"
+#define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp\t"
 #define __EXTRA_CLOBBER  \
        , "rcx", "rbx", "rdx", "r8", "r9", "r10", "r11", \
-          "r12", "r13", "r14", "r15"
+          "r12", "r13", "r14", "r15", "flags"
 #ifdef CONFIG_CC_STACKPROTECTOR
 #define __switch_canary                                                   \
@@ -100,7 +100,11 @@ do {									\
 #define __switch_canary_iparam
 #endif  /* CC_STACKPROTECTOR */
-/* Save restore flags to clear handle leaking NT */
+/*
+ * There is no need to save or restore flags, because flags are always
+ * clean in kernel mode, with the possible exception of IOPL.  Kernel IOPL
+ * has no effect.
+ */
 #define switch_to(prev, next, last) \
        asm volatile(SAVE_CONTEXT                                         \
             "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */       \
diff --git a/arch/x86/include/asm/uv/uv_bau.h b/arch/x86/include/asm/uv/uv_bau.h
index 2d60a7813dfe..fc808b83fccb 100644
--- a/arch/x86/include/asm/uv/uv_bau.h
+++ b/arch/x86/include/asm/uv/uv_bau.h
@@ -33,8 +33,8 @@
 * Each of the descriptors is 64 bytes in size (8*64 = 512 bytes in a set).
 */
-#define MAX_CPUS_PER_UVHUB              64
+#define MAX_CPUS_PER_UVHUB              128
-#define MAX_CPUS_PER_SOCKET             32
+#define MAX_CPUS_PER_SOCKET             64
 #define ADP_SZ                          64 /* hardware-provided max. */
 #define UV_CPUS_PER_AS                  32 /* hardware-provided max. */
 #define ITEMS_PER_DESC                  8
diff --git a/arch/x86/include/asm/vgtod.h b/arch/x86/include/asm/vgtod.h
index 3c3366c2e37f..e7e9682a33e9 100644
--- a/arch/x86/include/asm/vgtod.h
+++ b/arch/x86/include/asm/vgtod.h
@@ -70,4 +70,23 @@ static inline void gtod_write_end(struct vsyscall_gtod_data *s)
        ++s->seq;
 }
+#ifdef CONFIG_X86_64
+#define VGETCPU_CPU_MASK 0xfff
+static inline unsigned int __getcpu(void)
+{
+        unsigned int p;
+        /*
+         * Load per CPU data from GDT.  LSL is faster than RDTSCP and
+         * works on all CPUs.
+         */
+        asm("lsl %1,%0" : "=r" (p) : "r" (__PER_CPU_SEG));
+        return p;
+}
+#endif /* CONFIG_X86_64 */
 #endif /* _ASM_X86_VGTOD_H */
diff --git a/arch/x86/include/asm/vsyscall.h b/arch/x86/include/asm/vsyscall.h
index 2a46ca720afc..6ba66ee79710 100644
--- a/arch/x86/include/asm/vsyscall.h
+++ b/arch/x86/include/asm/vsyscall.h
@@ -4,15 +4,7 @@
 #include <linux/seqlock.h>
 #include <uapi/asm/vsyscall.h>
-#define VGETCPU_RDTSCP  1
+#ifdef CONFIG_X86_VSYSCALL_EMULATION
-#define VGETCPU_LSL     2
-/* kernel space (writeable) */
-extern int vgetcpu_mode;
-extern struct timezone sys_tz;
-#include <asm/vvar.h>
 extern void map_vsyscall(void);
 /*
@@ -20,25 +12,12 @@ extern void map_vsyscall(void);
 * Returns true if handled.
 */
 extern bool emulate_vsyscall(struct pt_regs *regs, unsigned long address);
+#else
-#ifdef CONFIG_X86_64
+static inline void map_vsyscall(void) {}
+static inline bool emulate_vsyscall(struct pt_regs *regs, unsigned long address)
-#define VGETCPU_CPU_MASK 0xfff
-static inline unsigned int __getcpu(void)
 {
-        unsigned int p;
+        return false;
-        if (VVAR(vgetcpu_mode) == VGETCPU_RDTSCP) {
-                /* Load per CPU data from RDTSCP */
-                native_read_tscp(&p);
-        } else {
-                /* Load per CPU data from GDT */
-                asm("lsl %1,%0" : "=r" (p) : "r" (__PER_CPU_SEG));
-        }
-        return p;
 }
-#endif /* CONFIG_X86_64 */
+#endif
 #endif /* _ASM_X86_VSYSCALL_H */
diff --git a/arch/x86/include/asm/vvar.h b/arch/x86/include/asm/vvar.h
index 5d2b9ad2c6d2..3f32dfc2ab73 100644
--- a/arch/x86/include/asm/vvar.h
+++ b/arch/x86/include/asm/vvar.h
@@ -44,8 +44,6 @@ extern char __vvar_page;
 /* DECLARE_VVAR(offset, type, name) */
-DECLARE_VVAR(0, volatile unsigned long, jiffies)
-DECLARE_VVAR(16, int, vgetcpu_mode)
 DECLARE_VVAR(128, struct vsyscall_gtod_data, vsyscall_gtod_data)
 #undef DECLARE_VVAR
diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
index e45e4da96bf1..f58a9c7a3c86 100644
--- a/arch/x86/include/asm/x86_init.h
+++ b/arch/x86/include/asm/x86_init.h
@@ -172,7 +172,6 @@ struct x86_platform_ops {
 struct pci_dev;
 struct msi_msg;
-struct msi_desc;
 struct x86_msi_ops {
        int (*setup_msi_irqs)(struct pci_dev *dev, int nvec, int type);
@@ -183,8 +182,6 @@ struct x86_msi_ops {
        void (*teardown_msi_irqs)(struct pci_dev *dev);
        void (*restore_msi_irqs)(struct pci_dev *dev);
        int  (*setup_hpet_msi)(unsigned int irq, unsigned int id);
-        u32 (*msi_mask_irq)(struct msi_desc *desc, u32 mask, u32 flag);
-        u32 (*msix_mask_irq)(struct msi_desc *desc, u32 flag);
 };
 struct IO_APIC_route_entry;
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
index e21331ce368f..c8aa65d56027 100644
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -152,6 +152,45 @@
 #define MSR_CC6_DEMOTION_POLICY_CONFIG  0x00000668
 #define MSR_MC6_DEMOTION_POLICY_CONFIG  0x00000669
+/* Hardware P state interface */
+#define MSR_PPERF                       0x0000064e
+#define MSR_PERF_LIMIT_REASONS          0x0000064f
+#define MSR_PM_ENABLE                   0x00000770
+#define MSR_HWP_CAPABILITIES            0x00000771
+#define MSR_HWP_REQUEST_PKG             0x00000772
+#define MSR_HWP_INTERRUPT               0x00000773
+#define MSR_HWP_REQUEST                 0x00000774
+#define MSR_HWP_STATUS                  0x00000777
+/* CPUID.6.EAX */
+#define HWP_BASE_BIT                    (1<<7)
+#define HWP_NOTIFICATIONS_BIT           (1<<8)
+#define HWP_ACTIVITY_WINDOW_BIT         (1<<9)
+#define HWP_ENERGY_PERF_PREFERENCE_BIT  (1<<10)
+#define HWP_PACKAGE_LEVEL_REQUEST_BIT   (1<<11)
+/* IA32_HWP_CAPABILITIES */
+#define HWP_HIGHEST_PERF(x)             (x & 0xff)
+#define HWP_GUARANTEED_PERF(x)          ((x & (0xff << 8)) >>8)
+#define HWP_MOSTEFFICIENT_PERF(x)       ((x & (0xff << 16)) >>16)
+#define HWP_LOWEST_PERF(x)              ((x & (0xff << 24)) >>24)
+/* IA32_HWP_REQUEST */
+#define HWP_MIN_PERF(x)                 (x & 0xff)
+#define HWP_MAX_PERF(x)                 ((x & 0xff) << 8)
+#define HWP_DESIRED_PERF(x)             ((x & 0xff) << 16)
+#define HWP_ENERGY_PERF_PREFERENCE(x)   ((x & 0xff) << 24)
+#define HWP_ACTIVITY_WINDOW(x)          ((x & 0xff3) << 32)
+#define HWP_PACKAGE_CONTROL(x)          ((x & 0x1) << 42)
+/* IA32_HWP_STATUS */
+#define HWP_GUARANTEED_CHANGE(x)        (x & 0x1)
+#define HWP_EXCURSION_TO_MINIMUM(x)     (x & 0x4)
+/* IA32_HWP_INTERRUPT */
+#define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1)
+#define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2)
 #define MSR_AMD64_MC0_MASK              0xc0010044
 #define MSR_IA32_MCx_CTL(x)             (MSR_IA32_MC0_CTL + 4*(x))
@@ -206,6 +245,7 @@
 #define MSR_AMD64_IBSOP_REG_MASK        ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
 #define MSR_AMD64_IBSCTL                0xc001103a
 #define MSR_AMD64_IBSBRTARGET           0xc001103b
+#define MSR_AMD64_IBSOPDATA4            0xc001103d
 #define MSR_AMD64_IBS_REG_COUNT_MAX     8 /* includes MSR_AMD64_IBSBRTARGET */
 /* Fam 16h MSRs */
@@ -345,6 +385,8 @@
 #define MSR_IA32_TEMPERATURE_TARGET     0x000001a2
+#define MSR_MISC_PWR_MGMT               0x000001aa
 #define MSR_IA32_ENERGY_PERF_BIAS       0x000001b0
 #define ENERGY_PERF_BIAS_PERFORMANCE    0
 #define ENERGY_PERF_BIAS_NORMAL         6
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 8f1e77440b2b..5d4502c8b983 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -28,8 +28,7 @@ obj-$(CONFIG_X86_32)	+= i386_ksyms_32.o
 obj-$(CONFIG_X86_64)    += sys_x86_64.o x8664_ksyms_64.o
 obj-$(CONFIG_X86_64)    += mcount_64.o
 obj-y                   += syscall_$(BITS).o vsyscall_gtod.o
-obj-$(CONFIG_X86_64)    += vsyscall_64.o
+obj-$(CONFIG_X86_VSYSCALL_EMULATION)    += vsyscall_64.o vsyscall_emu_64.o
-obj-$(CONFIG_X86_64)    += vsyscall_emu_64.o
 obj-$(CONFIG_X86_ESPFIX64)      += espfix_64.o
 obj-$(CONFIG_SYSFS)     += ksysfs.o
 obj-y                   += bootflag.o e820.o
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index f04dbb3069b8..5caed1dd7ccf 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -21,6 +21,7 @@ const struct pci_device_id amd_nb_misc_ids[] = {
        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
+        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
        {}
@@ -30,6 +31,7 @@ EXPORT_SYMBOL(amd_nb_misc_ids);
 static const struct pci_device_id amd_nb_link_ids[] = {
        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
+        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
        {}
diff --git a/arch/x86/kernel/apic/apic_numachip.c b/arch/x86/kernel/apic/apic_numachip.c
index 4128b5fcb559..c2fd21fed002 100644
--- a/arch/x86/kernel/apic/apic_numachip.c
+++ b/arch/x86/kernel/apic/apic_numachip.c
@@ -40,7 +40,7 @@ static unsigned int get_apic_id(unsigned long x)
        unsigned int id;
        rdmsrl(MSR_FAM10H_NODE_ID, value);
-        id = ((x >> 24) & 0xffU) | ((value << 2) & 0x3f00U);
+        id = ((x >> 24) & 0xffU) | ((value << 2) & 0xff00U);
        return id;
 }
@@ -145,7 +145,7 @@ static void numachip_send_IPI_all(int vector)
 static void numachip_send_IPI_self(int vector)
 {
-        __default_send_IPI_shortcut(APIC_DEST_SELF, vector, APIC_DEST_PHYSICAL);
+        apic_write(APIC_SELF_IPI, vector);
 }
 static int __init numachip_probe(void)
@@ -153,20 +153,8 @@ static int __init numachip_probe(void)
        return apic == &apic_numachip;
 }
-static void __init map_csrs(void)
-{
-        printk(KERN_INFO "NumaChip: Mapping local CSR space (%016llx - %016llx)\n",
-                NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_BASE + NUMACHIP_LCSR_SIZE - 1);
-        init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE);
-        printk(KERN_INFO "NumaChip: Mapping global CSR space (%016llx - %016llx)\n",
-                NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_BASE + NUMACHIP_GCSR_SIZE - 1);
-        init_extra_mapping_uc(NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_SIZE);
-}
 static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
 {
        if (c->phys_proc_id != node) {
                c->phys_proc_id = node;
                per_cpu(cpu_llc_id, smp_processor_id()) = node;
@@ -175,19 +163,15 @@ static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
 static int __init numachip_system_init(void)
 {
-        unsigned int val;
        if (!numachip_system)
                return 0;
+        init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE);
+        init_extra_mapping_uc(NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_SIZE);
        x86_cpuinit.fixup_cpu_id = fixup_cpu_id;
        x86_init.pci.arch_init = pci_numachip_init;
-        map_csrs();
-        val = read_lcsr(CSR_G0_NODE_IDS);
-        printk(KERN_INFO "NumaChip: Local NodeID = %08x\n", val);
        return 0;
 }
 early_initcall(numachip_system_init);
diff --git a/arch/x86/kernel/apic/hw_nmi.c b/arch/x86/kernel/apic/hw_nmi.c
index 6a1e71bde323..6873ab925d00 100644
--- a/arch/x86/kernel/apic/hw_nmi.c
+++ b/arch/x86/kernel/apic/hw_nmi.c
@@ -18,6 +18,7 @@
 #include <linux/nmi.h>
 #include <linux/module.h>
 #include <linux/delay.h>
+#include <linux/seq_buf.h>
 #ifdef CONFIG_HARDLOCKUP_DETECTOR
 u64 hw_nmi_get_sample_period(int watchdog_thresh)
@@ -29,14 +30,35 @@ u64 hw_nmi_get_sample_period(int watchdog_thresh)
 #ifdef arch_trigger_all_cpu_backtrace
 /* For reliability, we're prepared to waste bits here. */
 static DECLARE_BITMAP(backtrace_mask, NR_CPUS) __read_mostly;
+static cpumask_t printtrace_mask;
+#define NMI_BUF_SIZE            4096
+struct nmi_seq_buf {
+        unsigned char           buffer[NMI_BUF_SIZE];
+        struct seq_buf          seq;
+};
+/* Safe printing in NMI context */
+static DEFINE_PER_CPU(struct nmi_seq_buf, nmi_print_seq);
 /* "in progress" flag of arch_trigger_all_cpu_backtrace */
 static unsigned long backtrace_flag;
+static void print_seq_line(struct nmi_seq_buf *s, int start, int end)
+{
+        const char *buf = s->buffer + start;
+        printk("%.*s", (end - start) + 1, buf);
+}
 void arch_trigger_all_cpu_backtrace(bool include_self)
 {
+        struct nmi_seq_buf *s;
+        int len;
+        int cpu;
        int i;
-        int cpu = get_cpu();
+        int this_cpu = get_cpu();
        if (test_and_set_bit(0, &backtrace_flag)) {
                /*
@@ -49,7 +71,17 @@ void arch_trigger_all_cpu_backtrace(bool include_self)
        cpumask_copy(to_cpumask(backtrace_mask), cpu_online_mask);
        if (!include_self)
-                cpumask_clear_cpu(cpu, to_cpumask(backtrace_mask));
+                cpumask_clear_cpu(this_cpu, to_cpumask(backtrace_mask));
+        cpumask_copy(&printtrace_mask, to_cpumask(backtrace_mask));
+        /*
+         * Set up per_cpu seq_buf buffers that the NMIs running on the other
+         * CPUs will write to.
+         */
+        for_each_cpu(cpu, to_cpumask(backtrace_mask)) {
+                s = &per_cpu(nmi_print_seq, cpu);
+                seq_buf_init(&s->seq, s->buffer, NMI_BUF_SIZE);
+        }
        if (!cpumask_empty(to_cpumask(backtrace_mask))) {
                pr_info("sending NMI to %s CPUs:\n",
@@ -65,11 +97,58 @@ void arch_trigger_all_cpu_backtrace(bool include_self)
                touch_softlockup_watchdog();
        }
+        /*
+         * Now that all the NMIs have triggered, we can dump out their
+         * back traces safely to the console.
+         */
+        for_each_cpu(cpu, &printtrace_mask) {
+                int last_i = 0;
+                s = &per_cpu(nmi_print_seq, cpu);
+                len = seq_buf_used(&s->seq);
+                if (!len)
+                        continue;
+                /* Print line by line. */
+                for (i = 0; i < len; i++) {
+                        if (s->buffer[i] == '\n') {
+                                print_seq_line(s, last_i, i);
+                                last_i = i + 1;
+                        }
+                }
+                /* Check if there was a partial line. */
+                if (last_i < len) {
+                        print_seq_line(s, last_i, len - 1);
+                        pr_cont("\n");
+                }
+        }
        clear_bit(0, &backtrace_flag);
        smp_mb__after_atomic();
        put_cpu();
 }
+/*
+ * It is not safe to call printk() directly from NMI handlers.
+ * It may be fine if the NMI detected a lock up and we have no choice
+ * but to do so, but doing a NMI on all other CPUs to get a back trace
+ * can be done with a sysrq-l. We don't want that to lock up, which
+ * can happen if the NMI interrupts a printk in progress.
+ *
+ * Instead, we redirect the vprintk() to this nmi_vprintk() that writes
+ * the content into a per cpu seq_buf buffer. Then when the NMIs are
+ * all done, we can safely dump the contents of the seq_buf to a printk()
+ * from a non NMI context.
+ */
+static int nmi_vprintk(const char *fmt, va_list args)
+{
+        struct nmi_seq_buf *s = this_cpu_ptr(&nmi_print_seq);
+        unsigned int len = seq_buf_used(&s->seq);
+        seq_buf_vprintf(&s->seq, fmt, args);
+        return seq_buf_used(&s->seq) - len;
+}
 static int
 arch_trigger_all_cpu_backtrace_handler(unsigned int cmd, struct pt_regs *regs)
 {
@@ -78,12 +157,14 @@ arch_trigger_all_cpu_backtrace_handler(unsigned int cmd, struct pt_regs *regs)
        cpu = smp_processor_id();
        if (cpumask_test_cpu(cpu, to_cpumask(backtrace_mask))) {
-                static arch_spinlock_t lock = __ARCH_SPIN_LOCK_UNLOCKED;
+                printk_func_t printk_func_save = this_cpu_read(printk_func);
-                arch_spin_lock(&lock);
+                /* Replace printk to write into the NMI seq */
+                this_cpu_write(printk_func, nmi_vprintk);
                printk(KERN_WARNING "NMI backtrace for cpu %d\n", cpu);
                show_regs(regs);
-                arch_spin_unlock(&lock);
+                this_cpu_write(printk_func, printk_func_save);
                cpumask_clear_cpu(cpu, to_cpumask(backtrace_mask));
                return NMI_HANDLED;
        }
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 1183d545da1e..7ffe0a2b870f 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -3158,7 +3158,7 @@ msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
        msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
        msg.address_lo |= MSI_ADDR_DEST_ID(dest);
-        __write_msi_msg(data->msi_desc, &msg);
+        __pci_write_msi_msg(data->msi_desc, &msg);
        return IRQ_SET_MASK_OK_NOCOPY;
 }
@@ -3169,8 +3169,8 @@ msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
 */
 static struct irq_chip msi_chip = {
        .name                   = "PCI-MSI",
-        .irq_unmask             = unmask_msi_irq,
+        .irq_unmask             = pci_msi_unmask_irq,
-        .irq_mask               = mask_msi_irq,
+        .irq_mask               = pci_msi_mask_irq,
        .irq_ack                = ack_apic_edge,
        .irq_set_affinity       = msi_set_affinity,
        .irq_retrigger          = ioapic_retrigger_irq,
@@ -3196,7 +3196,7 @@ int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc,
         * MSI message denotes a contiguous group of IRQs, written for 0th IRQ.
         */
        if (!irq_offset)
-                write_msi_msg(irq, &msg);
+                pci_write_msi_msg(irq, &msg);
        setup_remapped_irq(irq, irq_cfg(irq), chip);
diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c
index 584874451414..927ec9235947 100644
--- a/arch/x86/kernel/apm_32.c
+++ b/arch/x86/kernel/apm_32.c
@@ -378,7 +378,6 @@ static struct cpuidle_driver apm_idle_driver = {
                { /* entry 1 is for APM idle */
                        .name = "APM",
                        .desc = "APM idle",
-                        .flags = CPUIDLE_FLAG_TIME_VALID,
                        .exit_latency = 250,    /* WAG */
                        .target_residency = 500,        /* WAG */
                        .enter = &apm_cpu_idle
diff --git a/arch/x86/kernel/asm-offsets_64.c b/arch/x86/kernel/asm-offsets_64.c
index e7c798b354fa..4f9359f36bb7 100644
--- a/arch/x86/kernel/asm-offsets_64.c
+++ b/arch/x86/kernel/asm-offsets_64.c
@@ -48,7 +48,6 @@ int main(void)
 #define ENTRY(entry) OFFSET(pt_regs_ ## entry, pt_regs, entry)
        ENTRY(bx);
-        ENTRY(bx);
        ENTRY(cx);
        ENTRY(dx);
        ENTRY(sp);
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 813d29d00a17..15c5df92f74e 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -566,6 +566,17 @@ static void init_amd_k8(struct cpuinfo_x86 *c)
        if (!c->x86_model_id[0])
                strcpy(c->x86_model_id, "Hammer");
+#ifdef CONFIG_SMP
+        /*
+         * Disable TLB flush filter by setting HWCR.FFDIS on K8
+         * bit 6 of msr C001_0015
+         *
+         * Errata 63 for SH-B3 steppings
+         * Errata 122 for all steppings (F+ have it disabled by default)
+         */
+        msr_set_bit(MSR_K7_HWCR, 6);
+#endif
 }
 static void init_amd_gh(struct cpuinfo_x86 *c)
@@ -636,18 +647,6 @@ static void init_amd(struct cpuinfo_x86 *c)
 {
        u32 dummy;
-#ifdef CONFIG_SMP
-        /*
-         * Disable TLB flush filter by setting HWCR.FFDIS on K8
-         * bit 6 of msr C001_0015
-         *
-         * Errata 63 for SH-B3 steppings
-         * Errata 122 for all steppings (F+ have it disabled by default)
-         */
-        if (c->x86 == 0xf)
-                msr_set_bit(MSR_K7_HWCR, 6);
-#endif
        early_init_amd(c);
        /*
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index cfa9b5b2c27a..c6049650c093 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -958,14 +958,6 @@ static void identify_cpu(struct cpuinfo_x86 *c)
 }
 #ifdef CONFIG_X86_64
-static void vgetcpu_set_mode(void)
-{
-        if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
-                vgetcpu_mode = VGETCPU_RDTSCP;
-        else
-                vgetcpu_mode = VGETCPU_LSL;
-}
 #ifdef CONFIG_IA32_EMULATION
 /* May not be __init: called during resume */
 static void syscall32_cpu_init(void)
@@ -1008,8 +1000,6 @@ void __init identify_boot_cpu(void)
 #ifdef CONFIG_X86_32
        sysenter_setup();
        enable_sep_cpu();
-#else
-        vgetcpu_set_mode();
 #endif
        cpu_detect_tlb(&boot_cpu_data);
 }
diff --git a/arch/x86/kernel/cpu/mcheck/mce-internal.h b/arch/x86/kernel/cpu/mcheck/mce-internal.h
index 09edd0b65fef..10b46906767f 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-internal.h
+++ b/arch/x86/kernel/cpu/mcheck/mce-internal.h
@@ -3,6 +3,8 @@
 enum severity_level {
        MCE_NO_SEVERITY,
+        MCE_DEFERRED_SEVERITY,
+        MCE_UCNA_SEVERITY = MCE_DEFERRED_SEVERITY,
        MCE_KEEP_SEVERITY,
        MCE_SOME_SEVERITY,
        MCE_AO_SEVERITY,
@@ -21,7 +23,7 @@ struct mce_bank {
        char                    attrname[ATTR_LEN];     /* attribute name */
 };
-int mce_severity(struct mce *a, int tolerant, char **msg);
+int mce_severity(struct mce *a, int tolerant, char **msg, bool is_excp);
 struct dentry *mce_get_debugfs_dir(void);
 extern struct mce_bank *mce_banks;
diff --git a/arch/x86/kernel/cpu/mcheck/mce-severity.c b/arch/x86/kernel/cpu/mcheck/mce-severity.c
index c370e1c4468b..8bb433043a7f 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-severity.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-severity.c
@@ -31,6 +31,7 @@
 enum context { IN_KERNEL = 1, IN_USER = 2 };
 enum ser { SER_REQUIRED = 1, NO_SER = 2 };
+enum exception { EXCP_CONTEXT = 1, NO_EXCP = 2 };
 static struct severity {
        u64 mask;
@@ -40,6 +41,7 @@ static struct severity {
        unsigned char mcgres;
        unsigned char ser;
        unsigned char context;
+        unsigned char excp;
        unsigned char covered;
        char *msg;
 } severities[] = {
@@ -48,6 +50,8 @@ static struct severity {
 #define  USER           .context = IN_USER
 #define  SER            .ser = SER_REQUIRED
 #define  NOSER          .ser = NO_SER
+#define  EXCP           .excp = EXCP_CONTEXT
+#define  NOEXCP         .excp = NO_EXCP
 #define  BITCLR(x)      .mask = x, .result = 0
 #define  BITSET(x)      .mask = x, .result = x
 #define  MCGMASK(x, y)  .mcgmask = x, .mcgres = y
@@ -62,7 +66,7 @@ static struct severity {
                ),
        MCESEV(
                NO, "Not enabled",
-                BITCLR(MCI_STATUS_EN)
+                EXCP, BITCLR(MCI_STATUS_EN)
                ),
        MCESEV(
                PANIC, "Processor context corrupt",
@@ -71,16 +75,20 @@ static struct severity {
        /* When MCIP is not set something is very confused */
        MCESEV(
                PANIC, "MCIP not set in MCA handler",
-                MCGMASK(MCG_STATUS_MCIP, 0)
+                EXCP, MCGMASK(MCG_STATUS_MCIP, 0)
                ),
        /* Neither return not error IP -- no chance to recover -> PANIC */
        MCESEV(
                PANIC, "Neither restart nor error IP",
-                MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, 0)
+                EXCP, MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, 0)
                ),
        MCESEV(
                PANIC, "In kernel and no restart IP",
-                KERNEL, MCGMASK(MCG_STATUS_RIPV, 0)
+                EXCP, KERNEL, MCGMASK(MCG_STATUS_RIPV, 0)
+                ),
+        MCESEV(
+                DEFERRED, "Deferred error",
+                NOSER, MASK(MCI_STATUS_UC|MCI_STATUS_DEFERRED|MCI_STATUS_POISON, MCI_STATUS_DEFERRED)
                ),
        MCESEV(
                KEEP, "Corrected error",
@@ -89,7 +97,7 @@ static struct severity {
        /* ignore OVER for UCNA */
        MCESEV(
-                KEEP, "Uncorrected no action required",
+                UCNA, "Uncorrected no action required",
                SER, MASK(MCI_UC_SAR, MCI_STATUS_UC)
                ),
        MCESEV(
@@ -178,8 +186,9 @@ static int error_context(struct mce *m)
        return ((m->cs & 3) == 3) ? IN_USER : IN_KERNEL;
 }
-int mce_severity(struct mce *m, int tolerant, char **msg)
+int mce_severity(struct mce *m, int tolerant, char **msg, bool is_excp)
 {
+        enum exception excp = (is_excp ? EXCP_CONTEXT : NO_EXCP);
        enum context ctx = error_context(m);
        struct severity *s;
@@ -194,6 +203,8 @@ int mce_severity(struct mce *m, int tolerant, char **msg)
                        continue;
                if (s->context && ctx != s->context)
                        continue;
+                if (s->excp && excp != s->excp)
+                        continue;
                if (msg)
                        *msg = s->msg;
                s->covered = 1;
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 61a9668cebfd..d2c611699cd9 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -292,10 +292,10 @@ static void print_mce(struct mce *m)
 #define PANIC_TIMEOUT 5 /* 5 seconds */
-static atomic_t mce_paniced;
+static atomic_t mce_panicked;
 static int fake_panic;
-static atomic_t mce_fake_paniced;
+static atomic_t mce_fake_panicked;
 /* Panic in progress. Enable interrupts and wait for final IPI */
 static void wait_for_panic(void)
@@ -319,7 +319,7 @@ static void mce_panic(char *msg, struct mce *final, char *exp)
                /*
                 * Make sure only one CPU runs in machine check panic
                 */
-                if (atomic_inc_return(&mce_paniced) > 1)
+                if (atomic_inc_return(&mce_panicked) > 1)
                        wait_for_panic();
                barrier();
@@ -327,7 +327,7 @@ static void mce_panic(char *msg, struct mce *final, char *exp)
                console_verbose();
        } else {
                /* Don't log too much for fake panic */
-                if (atomic_inc_return(&mce_fake_paniced) > 1)
+                if (atomic_inc_return(&mce_fake_panicked) > 1)
                        return;
        }
        /* First print corrected ones that are still unlogged */
@@ -575,6 +575,37 @@ static void mce_read_aux(struct mce *m, int i)
        }
 }
+static bool memory_error(struct mce *m)
+{
+        struct cpuinfo_x86 *c = &boot_cpu_data;
+        if (c->x86_vendor == X86_VENDOR_AMD) {
+                /*
+                 * coming soon
+                 */
+                return false;
+        } else if (c->x86_vendor == X86_VENDOR_INTEL) {
+                /*
+                 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
+                 *
+                 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
+                 * indicating a memory error. Bit 8 is used for indicating a
+                 * cache hierarchy error. The combination of bit 2 and bit 3
+                 * is used for indicating a `generic' cache hierarchy error
+                 * But we can't just blindly check the above bits, because if
+                 * bit 11 is set, then it is a bus/interconnect error - and
+                 * either way the above bits just gives more detail on what
+                 * bus/interconnect error happened. Note that bit 12 can be
+                 * ignored, as it's the "filter" bit.
+                 */
+                return (m->status & 0xef80) == BIT(7) ||
+                       (m->status & 0xef00) == BIT(8) ||
+                       (m->status & 0xeffc) == 0xc;
+        }
+        return false;
+}
 DEFINE_PER_CPU(unsigned, mce_poll_count);
 /*
@@ -595,6 +626,7 @@ DEFINE_PER_CPU(unsigned, mce_poll_count);
 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
 {
        struct mce m;
+        int severity;
        int i;
        this_cpu_inc(mce_poll_count);
@@ -630,6 +662,20 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
                if (!(flags & MCP_TIMESTAMP))
                        m.tsc = 0;
+                severity = mce_severity(&m, mca_cfg.tolerant, NULL, false);
+                /*
+                 * In the cases where we don't have a valid address after all,
+                 * do not add it into the ring buffer.
+                 */
+                if (severity == MCE_DEFERRED_SEVERITY && memory_error(&m)) {
+                        if (m.status & MCI_STATUS_ADDRV) {
+                                mce_ring_add(m.addr >> PAGE_SHIFT);
+                                mce_schedule_work();
+                        }
+                }
                /*
                 * Don't get the IP here because it's unlikely to
                 * have anything to do with the actual error location.
@@ -668,7 +714,8 @@ static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
                        if (quirk_no_way_out)
                                quirk_no_way_out(i, m, regs);
                }
-                if (mce_severity(m, mca_cfg.tolerant, msg) >= MCE_PANIC_SEVERITY)
+                if (mce_severity(m, mca_cfg.tolerant, msg, true) >=
+                    MCE_PANIC_SEVERITY)
                        ret = 1;
        }
        return ret;
@@ -697,7 +744,7 @@ static int mce_timed_out(u64 *t)
         * might have been modified by someone else.
         */
        rmb();
-        if (atomic_read(&mce_paniced))
+        if (atomic_read(&mce_panicked))
                wait_for_panic();
        if (!mca_cfg.monarch_timeout)
                goto out;
@@ -754,7 +801,7 @@ static void mce_reign(void)
        for_each_possible_cpu(cpu) {
                int severity = mce_severity(&per_cpu(mces_seen, cpu),
                                            mca_cfg.tolerant,
-                                            &nmsg);
+                                            &nmsg, true);
                if (severity > global_worst) {
                        msg = nmsg;
                        global_worst = severity;
@@ -1095,13 +1142,14 @@ void do_machine_check(struct pt_regs *regs, long error_code)
                 */
                add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
-                severity = mce_severity(&m, cfg->tolerant, NULL);
+                severity = mce_severity(&m, cfg->tolerant, NULL, true);
                /*
-                 * When machine check was for corrected handler don't touch,
+                 * When machine check was for corrected/deferred handler don't
-                 * unless we're panicing.
+                 * touch, unless we're panicing.
                 */
-                if (severity == MCE_KEEP_SEVERITY && !no_way_out)
+                if ((severity == MCE_KEEP_SEVERITY ||
+                     severity == MCE_UCNA_SEVERITY) && !no_way_out)
                        continue;
                __set_bit(i, toclear);
                if (severity == MCE_NO_SEVERITY) {
@@ -2520,7 +2568,7 @@ struct dentry *mce_get_debugfs_dir(void)
 static void mce_reset(void)
 {
        cpu_missing = 0;
-        atomic_set(&mce_fake_paniced, 0);
+        atomic_set(&mce_fake_panicked, 0);
        atomic_set(&mce_executing, 0);
        atomic_set(&mce_callin, 0);
        atomic_set(&global_nwo, 0);
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 5d4999f95aec..f1c3769bbd64 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -212,12 +212,12 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
        unsigned int cpu = smp_processor_id();
        u32 low = 0, high = 0, address = 0;
        unsigned int bank, block;
-        int offset = -1;
+        int offset = -1, new;
        for (bank = 0; bank < mca_cfg.banks; ++bank) {
                for (block = 0; block < NR_BLOCKS; ++block) {
                        if (block == 0)
-                                address = MSR_IA32_MC0_MISC + bank * 4;
+                                address = MSR_IA32_MCx_MISC(bank);
                        else if (block == 1) {
                                address = (low & MASK_BLKPTR_LO) >> 21;
                                if (!address)
@@ -247,13 +247,18 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
                        b.address               = address;
                        b.interrupt_capable     = lvt_interrupt_supported(bank, high);
-                        if (b.interrupt_capable) {
+                        if (!b.interrupt_capable)
-                                int new = (high & MASK_LVTOFF_HI) >> 20;
+                                goto init;
-                                offset  = setup_APIC_mce(offset, new);
-                        }
+                        new     = (high & MASK_LVTOFF_HI) >> 20;
+                        offset  = setup_APIC_mce(offset, new);
+                        if ((offset == new) &&
+                            (mce_threshold_vector != amd_threshold_interrupt))
+                                mce_threshold_vector = amd_threshold_interrupt;
+init:
                        mce_threshold_block_init(&b, offset);
-                        mce_threshold_vector = amd_threshold_interrupt;
                }
        }
 }
@@ -270,18 +275,17 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
 static void amd_threshold_interrupt(void)
 {
        u32 low = 0, high = 0, address = 0;
+        int cpu = smp_processor_id();
        unsigned int bank, block;
        struct mce m;
-        mce_setup(&m);
        /* assume first bank caused it */
        for (bank = 0; bank < mca_cfg.banks; ++bank) {
-                if (!(per_cpu(bank_map, m.cpu) & (1 << bank)))
+                if (!(per_cpu(bank_map, cpu) & (1 << bank)))
                        continue;
                for (block = 0; block < NR_BLOCKS; ++block) {
                        if (block == 0) {
-                                address = MSR_IA32_MC0_MISC + bank * 4;
+                                address = MSR_IA32_MCx_MISC(bank);
                        } else if (block == 1) {
                                address = (low & MASK_BLKPTR_LO) >> 21;
                                if (!address)
@@ -309,21 +313,20 @@ static void amd_threshold_interrupt(void)
                         * Log the machine check that caused the threshold
                         * event.
                         */
-                        machine_check_poll(MCP_TIMESTAMP,
+                        if (high & MASK_OVERFLOW_HI)
-                                        this_cpu_ptr(&mce_poll_banks));
+                                goto log;
-                        if (high & MASK_OVERFLOW_HI) {
-                                rdmsrl(address, m.misc);
-                                rdmsrl(MSR_IA32_MC0_STATUS + bank * 4,
-                                       m.status);
-                                m.bank = K8_MCE_THRESHOLD_BASE
-                                       + bank * NR_BLOCKS
-                                       + block;
-                                mce_log(&m);
-                                return;
-                        }
                }
        }
+        return;
+log:
+        mce_setup(&m);
+        rdmsrl(MSR_IA32_MCx_STATUS(bank), m.status);
+        m.misc = ((u64)high << 32) | low;
+        m.bank = bank;
+        mce_log(&m);
+        wrmsrl(MSR_IA32_MCx_STATUS(bank), 0);
 }
 /*
@@ -617,8 +620,7 @@ static int threshold_create_bank(unsigned int cpu, unsigned int bank)
                }
        }
-        err = allocate_threshold_blocks(cpu, bank, 0,
+        err = allocate_threshold_blocks(cpu, bank, 0, MSR_IA32_MCx_MISC(bank));
-                                        MSR_IA32_MC0_MISC + bank * 4);
        if (!err)
                goto out;
diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c
index 8fffd845e22b..bfbbe6195e2d 100644
--- a/arch/x86/kernel/cpu/microcode/amd.c
+++ b/arch/x86/kernel/cpu/microcode/amd.c
@@ -376,7 +376,7 @@ static enum ucode_state __load_microcode_amd(u8 family, const u8 *data,
        return UCODE_OK;
 }
-enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t size)
+enum ucode_state load_microcode_amd(int cpu, u8 family, const u8 *data, size_t size)
 {
        enum ucode_state ret;
@@ -390,8 +390,8 @@ enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t size)
 #if defined(CONFIG_MICROCODE_AMD_EARLY) && defined(CONFIG_X86_32)
        /* save BSP's matching patch for early load */
-        if (cpu_data(smp_processor_id()).cpu_index == boot_cpu_data.cpu_index) {
+        if (cpu_data(cpu).cpu_index == boot_cpu_data.cpu_index) {
-                struct ucode_patch *p = find_patch(smp_processor_id());
+                struct ucode_patch *p = find_patch(cpu);
                if (p) {
                        memset(amd_ucode_patch, 0, PATCH_MAX_SIZE);
                        memcpy(amd_ucode_patch, p->data, min_t(u32, ksize(p->data),
@@ -444,7 +444,7 @@ static enum ucode_state request_microcode_amd(int cpu, struct device *device,
                goto fw_release;
        }
-        ret = load_microcode_amd(c->x86, fw->data, fw->size);
+        ret = load_microcode_amd(cpu, c->x86, fw->data, fw->size);
 fw_release:
        release_firmware(fw);
diff --git a/arch/x86/kernel/cpu/microcode/amd_early.c b/arch/x86/kernel/cpu/microcode/amd_early.c
index 06674473b0e6..737737edbd1e 100644
--- a/arch/x86/kernel/cpu/microcode/amd_early.c
+++ b/arch/x86/kernel/cpu/microcode/amd_early.c
@@ -389,7 +389,7 @@ int __init save_microcode_in_initrd_amd(void)
        eax   = cpuid_eax(0x00000001);
        eax   = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff);
-        ret = load_microcode_amd(eax, container, container_size);
+        ret = load_microcode_amd(smp_processor_id(), eax, container, container_size);
        if (ret != UCODE_OK)
                retval = -EINVAL;
@@ -402,3 +402,21 @@ int __init save_microcode_in_initrd_amd(void)
        return retval;
 }
+void reload_ucode_amd(void)
+{
+        struct microcode_amd *mc;
+        u32 rev, eax;
+        rdmsr(MSR_AMD64_PATCH_LEVEL, rev, eax);
+        mc = (struct microcode_amd *)amd_ucode_patch;
+        if (mc && rev < mc->hdr.patch_id) {
+                if (!__apply_microcode_amd(mc)) {
+                        ucode_new_rev = mc->hdr.patch_id;
+                        pr_info("microcode: reload patch_level=0x%08x\n",
+                                ucode_new_rev);
+                }
+        }
+}
diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c
index 2ce9051174e6..15c29096136b 100644
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -466,13 +466,7 @@ static void mc_bp_resume(void)
        if (uci->valid && uci->mc)
                microcode_ops->apply_microcode(cpu);
        else if (!uci->mc)
-                /*
+                reload_early_microcode();
-                 * We might resume and not have applied late microcode but still
-                 * have a newer patch stashed from the early loader. We don't
-                 * have it in uci->mc so we have to load it the same way we're
-                 * applying patches early on the APs.
-                 */
-                load_ucode_ap();
 }
 static struct syscore_ops mc_syscore_ops = {
@@ -557,7 +551,7 @@ static int __init microcode_init(void)
        struct cpuinfo_x86 *c = &cpu_data(0);
        int error;
-        if (dis_ucode_ldr)
+        if (paravirt_enabled() || dis_ucode_ldr)
                return 0;
        if (c->x86_vendor == X86_VENDOR_INTEL)
diff --git a/arch/x86/kernel/cpu/microcode/core_early.c b/arch/x86/kernel/cpu/microcode/core_early.c
index 2c017f242a78..d45df4bd16ab 100644
--- a/arch/x86/kernel/cpu/microcode/core_early.c
+++ b/arch/x86/kernel/cpu/microcode/core_early.c
@@ -176,3 +176,24 @@ int __init save_microcode_in_initrd(void)
        return 0;
 }
+void reload_early_microcode(void)
+{
+        int vendor, x86;
+        vendor = x86_vendor();
+        x86 = x86_family();
+        switch (vendor) {
+        case X86_VENDOR_INTEL:
+                if (x86 >= 6)
+                        reload_ucode_intel();
+                break;
+        case X86_VENDOR_AMD:
+                if (x86 >= 0x10)
+                        reload_ucode_amd();
+                break;
+        default:
+                break;
+        }
+}
diff --git a/arch/x86/kernel/cpu/microcode/intel_early.c b/arch/x86/kernel/cpu/microcode/intel_early.c
index b88343f7a3b3..ec9df6f9cd47 100644
--- a/arch/x86/kernel/cpu/microcode/intel_early.c
+++ b/arch/x86/kernel/cpu/microcode/intel_early.c
@@ -650,8 +650,7 @@ static inline void print_ucode(struct ucode_cpu_info *uci)
 }
 #endif
-static int apply_microcode_early(struct mc_saved_data *mc_saved_data,
+static int apply_microcode_early(struct ucode_cpu_info *uci, bool early)
-                                 struct ucode_cpu_info *uci)
 {
        struct microcode_intel *mc_intel;
        unsigned int val[2];
@@ -680,7 +679,10 @@ static int apply_microcode_early(struct mc_saved_data *mc_saved_data,
 #endif
        uci->cpu_sig.rev = val[1];
-        print_ucode(uci);
+        if (early)
+                print_ucode(uci);
+        else
+                print_ucode_info(uci, mc_intel->hdr.date);
        return 0;
 }
@@ -715,12 +717,17 @@ _load_ucode_intel_bsp(struct mc_saved_data *mc_saved_data,
                      unsigned long initrd_end_early,
                      struct ucode_cpu_info *uci)
 {
+        enum ucode_state ret;
        collect_cpu_info_early(uci);
        scan_microcode(initrd_start_early, initrd_end_early, mc_saved_data,
                       mc_saved_in_initrd, uci);
-        load_microcode(mc_saved_data, mc_saved_in_initrd,
-                       initrd_start_early, uci);
+        ret = load_microcode(mc_saved_data, mc_saved_in_initrd,
-        apply_microcode_early(mc_saved_data, uci);
+                             initrd_start_early, uci);
+        if (ret == UCODE_OK)
+                apply_microcode_early(uci, true);
 }
 void __init
@@ -749,7 +756,8 @@ load_ucode_intel_bsp(void)
        initrd_end_early = initrd_start_early + ramdisk_size;
        _load_ucode_intel_bsp(&mc_saved_data, mc_saved_in_initrd,
-                              initrd_start_early, initrd_end_early, &uci);
+                              initrd_start_early, initrd_end_early,
+                              &uci);
 #endif
 }
@@ -783,5 +791,23 @@ void load_ucode_intel_ap(void)
        collect_cpu_info_early(&uci);
        load_microcode(mc_saved_data_p, mc_saved_in_initrd_p,
                       initrd_start_addr, &uci);
-        apply_microcode_early(mc_saved_data_p, &uci);
+        apply_microcode_early(&uci, true);
+}
+void reload_ucode_intel(void)
+{
+        struct ucode_cpu_info uci;
+        enum ucode_state ret;
+        if (!mc_saved_data.mc_saved_count)
+                return;
+        collect_cpu_info_early(&uci);
+        ret = generic_load_microcode_early(mc_saved_data.mc_saved,
+                                           mc_saved_data.mc_saved_count, &uci);
+        if (ret != UCODE_OK)
+                return;
+        apply_microcode_early(&uci, false);
 }
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index fc5eb390b368..4e6cdb0ddc70 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -253,6 +253,10 @@ struct cpu_hw_events {
 #define INTEL_UEVENT_CONSTRAINT(c, n)   \
        EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
+/* Like UEVENT_CONSTRAINT, but match flags too */
+#define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n)     \
+        EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
 #define INTEL_PLD_CONSTRAINT(c, n)      \
        __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
                           HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
diff --git a/arch/x86/kernel/cpu/perf_event_amd_ibs.c b/arch/x86/kernel/cpu/perf_event_amd_ibs.c
index cbb1be3ed9e4..a61f5c6911da 100644
--- a/arch/x86/kernel/cpu/perf_event_amd_ibs.c
+++ b/arch/x86/kernel/cpu/perf_event_amd_ibs.c
@@ -565,6 +565,21 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
                                       perf_ibs->offset_max,
                                       offset + 1);
        } while (offset < offset_max);
+        if (event->attr.sample_type & PERF_SAMPLE_RAW) {
+                /*
+                 * Read IbsBrTarget and IbsOpData4 separately
+                 * depending on their availability.
+                 * Can't add to offset_max as they are staggered
+                 */
+                if (ibs_caps & IBS_CAPS_BRNTRGT) {
+                        rdmsrl(MSR_AMD64_IBSBRTARGET, *buf++);
+                        size++;
+                }
+                if (ibs_caps & IBS_CAPS_OPDATA4) {
+                        rdmsrl(MSR_AMD64_IBSOPDATA4, *buf++);
+                        size++;
+                }
+        }
        ibs_data.size = sizeof(u64) * size;
        regs = *iregs;
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index 46211bcc813e..3c895d480cd7 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -552,18 +552,18 @@ int intel_pmu_drain_bts_buffer(void)
 * PEBS
 */
 struct event_constraint intel_core2_pebs_event_constraints[] = {
-        INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
+        INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
-        INTEL_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
+        INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
-        INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
+        INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
-        INTEL_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
+        INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
-        INTEL_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
+        INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
        EVENT_CONSTRAINT_END
 };
 struct event_constraint intel_atom_pebs_event_constraints[] = {
-        INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
+        INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
-        INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
+        INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
-        INTEL_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
+        INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
        EVENT_CONSTRAINT_END
 };
@@ -577,36 +577,36 @@ struct event_constraint intel_slm_pebs_event_constraints[] = {
 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
        INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
-        INTEL_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
+        INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
-        INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
+        INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
-        INTEL_EVENT_CONSTRAINT(0xc0, 0xf),    /* INST_RETIRED.ANY */
+        INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),    /* INST_RETIRED.ANY */
        INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
-        INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
+        INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
-        INTEL_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
+        INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
-        INTEL_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
+        INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
-        INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
+        INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
-        INTEL_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
+        INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
-        INTEL_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
+        INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
        EVENT_CONSTRAINT_END
 };
 struct event_constraint intel_westmere_pebs_event_constraints[] = {
        INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
-        INTEL_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
+        INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
-        INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
+        INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
-        INTEL_EVENT_CONSTRAINT(0xc0, 0xf),    /* INSTR_RETIRED.* */
+        INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),    /* INSTR_RETIRED.* */
        INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
-        INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
+        INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
-        INTEL_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
+        INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
-        INTEL_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
+        INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
-        INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
+        INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
-        INTEL_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
+        INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
-        INTEL_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
+        INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
        EVENT_CONSTRAINT_END
 };
 struct event_constraint intel_snb_pebs_event_constraints[] = {
-        INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
+        INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
        INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
        INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
        /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
@@ -617,7 +617,7 @@ struct event_constraint intel_snb_pebs_event_constraints[] = {
 };
 struct event_constraint intel_ivb_pebs_event_constraints[] = {
-        INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
+        INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
        INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
        INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
        /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
@@ -628,7 +628,7 @@ struct event_constraint intel_ivb_pebs_event_constraints[] = {
 };
 struct event_constraint intel_hsw_pebs_event_constraints[] = {
-        INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
+        INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
        INTEL_PLD_CONSTRAINT(0x01cd, 0xf),    /* MEM_TRANS_RETIRED.* */
        /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
        INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
@@ -724,6 +724,7 @@ static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
        unsigned long ip = regs->ip;
        int is_64bit = 0;
        void *kaddr;
+        int size;
        /*
         * We don't need to fixup if the PEBS assist is fault like
@@ -758,11 +759,12 @@ static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
                return 1;
        }
+        size = ip - to;
        if (!kernel_ip(ip)) {
-                int size, bytes;
+                int bytes;
                u8 *buf = this_cpu_read(insn_buffer);
-                size = ip - to; /* Must fit our buffer, see above */
+                /* 'size' must fit our buffer, see above */
                bytes = copy_from_user_nmi(buf, (void __user *)to, size);
                if (bytes != 0)
                        return 0;
@@ -780,11 +782,20 @@ static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
 #ifdef CONFIG_X86_64
                is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
 #endif
-                insn_init(&insn, kaddr, is_64bit);
+                insn_init(&insn, kaddr, size, is_64bit);
                insn_get_length(&insn);
+                /*
+                 * Make sure there was not a problem decoding the
+                 * instruction and getting the length.  This is
+                 * doubly important because we have an infinite
+                 * loop if insn.length=0.
+                 */
+                if (!insn.length)
+                        break;
                to += insn.length;
                kaddr += insn.length;
+                size -= insn.length;
        } while (to < ip);
        if (to == ip) {
@@ -886,6 +897,29 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
        regs.bp = pebs->bp;
        regs.sp = pebs->sp;
+        if (sample_type & PERF_SAMPLE_REGS_INTR) {
+                regs.ax = pebs->ax;
+                regs.bx = pebs->bx;
+                regs.cx = pebs->cx;
+                regs.dx = pebs->dx;
+                regs.si = pebs->si;
+                regs.di = pebs->di;
+                regs.bp = pebs->bp;
+                regs.sp = pebs->sp;
+                regs.flags = pebs->flags;
+#ifndef CONFIG_X86_32
+                regs.r8 = pebs->r8;
+                regs.r9 = pebs->r9;
+                regs.r10 = pebs->r10;
+                regs.r11 = pebs->r11;
+                regs.r12 = pebs->r12;
+                regs.r13 = pebs->r13;
+                regs.r14 = pebs->r14;
+                regs.r15 = pebs->r15;
+#endif
+        }
        if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
                regs.ip = pebs->real_ip;
                regs.flags |= PERF_EFLAGS_EXACT;
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index 45fa730a5283..58f1a94beaf0 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -465,7 +465,7 @@ static int branch_type(unsigned long from, unsigned long to, int abort)
 {
        struct insn insn;
        void *addr;
-        int bytes, size = MAX_INSN_SIZE;
+        int bytes_read, bytes_left;
        int ret = X86_BR_NONE;
        int ext, to_plm, from_plm;
        u8 buf[MAX_INSN_SIZE];
@@ -493,8 +493,10 @@ static int branch_type(unsigned long from, unsigned long to, int abort)
                        return X86_BR_NONE;
                /* may fail if text not present */
-                bytes = copy_from_user_nmi(buf, (void __user *)from, size);
+                bytes_left = copy_from_user_nmi(buf, (void __user *)from,
-                if (bytes != 0)
+                                                MAX_INSN_SIZE);
+                bytes_read = MAX_INSN_SIZE - bytes_left;
+                if (!bytes_read)
                        return X86_BR_NONE;
                addr = buf;
@@ -505,10 +507,19 @@ static int branch_type(unsigned long from, unsigned long to, int abort)
                 * Ensure we don't blindy read any address by validating it is
                 * a known text address.
                 */
-                if (kernel_text_address(from))
+                if (kernel_text_address(from)) {
                        addr = (void *)from;
-                else
+                        /*
+                         * Assume we can get the maximum possible size
+                         * when grabbing kernel data.  This is not
+                         * _strictly_ true since we could possibly be
+                         * executing up next to a memory hole, but
+                         * it is very unlikely to be a problem.
+                         */
+                        bytes_read = MAX_INSN_SIZE;
+                } else {
                        return X86_BR_NONE;
+                }
        }
        /*
@@ -518,8 +529,10 @@ static int branch_type(unsigned long from, unsigned long to, int abort)
 #ifdef CONFIG_X86_64
        is64 = kernel_ip((unsigned long)addr) || !test_thread_flag(TIF_IA32);
 #endif
-        insn_init(&insn, addr, is64);
+        insn_init(&insn, addr, bytes_read, is64);
        insn_get_opcode(&insn);
+        if (!insn.opcode.got)
+                return X86_BR_ABORT;
        switch (insn.opcode.bytes[0]) {
        case 0xf:
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
index f9ed429d6e4f..745b158e9a65 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
@@ -449,7 +449,11 @@ static struct attribute *snbep_uncore_qpi_formats_attr[] = {
 static struct uncore_event_desc snbep_uncore_imc_events[] = {
        INTEL_UNCORE_EVENT_DESC(clockticks,      "event=0xff,umask=0x00"),
        INTEL_UNCORE_EVENT_DESC(cas_count_read,  "event=0x04,umask=0x03"),
+        INTEL_UNCORE_EVENT_DESC(cas_count_read.scale, "6.103515625e-5"),
+        INTEL_UNCORE_EVENT_DESC(cas_count_read.unit, "MiB"),
        INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x0c"),
+        INTEL_UNCORE_EVENT_DESC(cas_count_write.scale, "6.103515625e-5"),
+        INTEL_UNCORE_EVENT_DESC(cas_count_write.unit, "MiB"),
        { /* end: all zeroes */ },
 };
@@ -2036,7 +2040,11 @@ static struct intel_uncore_type hswep_uncore_ha = {
 static struct uncore_event_desc hswep_uncore_imc_events[] = {
        INTEL_UNCORE_EVENT_DESC(clockticks,      "event=0x00,umask=0x00"),
        INTEL_UNCORE_EVENT_DESC(cas_count_read,  "event=0x04,umask=0x03"),
+        INTEL_UNCORE_EVENT_DESC(cas_count_read.scale, "6.103515625e-5"),
+        INTEL_UNCORE_EVENT_DESC(cas_count_read.unit, "MiB"),
        INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x0c"),
+        INTEL_UNCORE_EVENT_DESC(cas_count_write.scale, "6.103515625e-5"),
+        INTEL_UNCORE_EVENT_DESC(cas_count_write.unit, "MiB"),
        { /* end: all zeroes */ },
 };
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index 5433658e598d..e7d8c7608471 100644
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -72,7 +72,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
        if (c->x86_mask || c->cpuid_level >= 0)
                seq_printf(m, "stepping\t: %d\n", c->x86_mask);
        else
-                seq_printf(m, "stepping\t: unknown\n");
+                seq_puts(m, "stepping\t: unknown\n");
        if (c->microcode)
                seq_printf(m, "microcode\t: 0x%x\n", c->microcode);
@@ -92,12 +92,12 @@ static int show_cpuinfo(struct seq_file *m, void *v)
        show_cpuinfo_core(m, c, cpu);
        show_cpuinfo_misc(m, c);
-        seq_printf(m, "flags\t\t:");
+        seq_puts(m, "flags\t\t:");
        for (i = 0; i < 32*NCAPINTS; i++)
                if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
                        seq_printf(m, " %s", x86_cap_flags[i]);
-        seq_printf(m, "\nbugs\t\t:");
+        seq_puts(m, "\nbugs\t\t:");
        for (i = 0; i < 32*NBUGINTS; i++) {
                unsigned int bug_bit = 32*NCAPINTS + i;
@@ -118,7 +118,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
        seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
                   c->x86_phys_bits, c->x86_virt_bits);
-        seq_printf(m, "power management:");
+        seq_puts(m, "power management:");
        for (i = 0; i < 32; i++) {
                if (c->x86_power & (1 << i)) {
                        if (i < ARRAY_SIZE(x86_power_flags) &&
@@ -131,7 +131,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                }
        }
-        seq_printf(m, "\n\n");
+        seq_puts(m, "\n\n");
        return 0;
 }
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 4a8013d55947..60639093d536 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -36,6 +36,11 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
                { X86_FEATURE_ARAT,             CR_EAX, 2, 0x00000006, 0 },
                { X86_FEATURE_PLN,              CR_EAX, 4, 0x00000006, 0 },
                { X86_FEATURE_PTS,              CR_EAX, 6, 0x00000006, 0 },
+                { X86_FEATURE_HWP,              CR_EAX, 7, 0x00000006, 0 },
+                { X86_FEATURE_HWP_NOITFY,       CR_EAX, 8, 0x00000006, 0 },
+                { X86_FEATURE_HWP_ACT_WINDOW,   CR_EAX, 9, 0x00000006, 0 },
+                { X86_FEATURE_HWP_EPP,          CR_EAX,10, 0x00000006, 0 },
+                { X86_FEATURE_HWP_PKG_REQ,      CR_EAX,11, 0x00000006, 0 },
                { X86_FEATURE_APERFMPERF,       CR_ECX, 0, 0x00000006, 0 },
                { X86_FEATURE_EPB,              CR_ECX, 3, 0x00000006, 0 },
                { X86_FEATURE_HW_PSTATE,        CR_EDX, 7, 0x80000007, 0 },
diff --git a/arch/x86/kernel/cpuid.c b/arch/x86/kernel/cpuid.c
index 3225ae6c5180..83741a71558f 100644
--- a/arch/x86/kernel/cpuid.c
+++ b/arch/x86/kernel/cpuid.c
@@ -143,7 +143,7 @@ static int cpuid_device_create(int cpu)
        dev = device_create(cpuid_class, NULL, MKDEV(CPUID_MAJOR, cpu), NULL,
                            "cpu%d", cpu);
-        return IS_ERR(dev) ? PTR_ERR(dev) : 0;
+        return PTR_ERR_OR_ZERO(dev);
 }
 static void cpuid_device_destroy(int cpu)
diff --git a/arch/x86/kernel/espfix_64.c b/arch/x86/kernel/espfix_64.c
index 94d857fb1033..f5d0730e7b08 100644
--- a/arch/x86/kernel/espfix_64.c
+++ b/arch/x86/kernel/espfix_64.c
@@ -122,9 +122,6 @@ static void init_espfix_random(void)
 void __init init_espfix_bsp(void)
 {
        pgd_t *pgd_p;
-        pteval_t ptemask;
-        ptemask = __supported_pte_mask;
        /* Install the espfix pud into the kernel page directory */
        pgd_p = &init_level4_pgt[pgd_index(ESPFIX_BASE_ADDR)];
diff --git a/arch/x86/kernel/ftrace.c b/arch/x86/kernel/ftrace.c
index 3386dc9aa333..2142376dc8c6 100644
--- a/arch/x86/kernel/ftrace.c
+++ b/arch/x86/kernel/ftrace.c
@@ -17,6 +17,7 @@
 #include <linux/ftrace.h>
 #include <linux/percpu.h>
 #include <linux/sched.h>
+#include <linux/slab.h>
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/module.h>
@@ -47,7 +48,7 @@ int ftrace_arch_code_modify_post_process(void)
 union ftrace_code_union {
        char code[MCOUNT_INSN_SIZE];
        struct {
-                char e8;
+                unsigned char e8;
                int offset;
        } __attribute__((packed));
 };
@@ -582,7 +583,7 @@ void ftrace_replace_code(int enable)
 remove_breakpoints:
        pr_warn("Failed on %s (%d):\n", report, count);
-        ftrace_bug(ret, rec ? rec->ip : 0);
+        ftrace_bug(ret, rec);
        for_ftrace_rec_iter(iter) {
                rec = ftrace_rec_iter_record(iter);
                /*
@@ -644,13 +645,8 @@ int __init ftrace_dyn_arch_init(void)
 {
        return 0;
 }
-#endif
-#ifdef CONFIG_FUNCTION_GRAPH_TRACER
-#ifdef CONFIG_DYNAMIC_FTRACE
-extern void ftrace_graph_call(void);
+#if defined(CONFIG_X86_64) || defined(CONFIG_FUNCTION_GRAPH_TRACER)
 static unsigned char *ftrace_jmp_replace(unsigned long ip, unsigned long addr)
 {
        static union ftrace_code_union calc;
@@ -664,6 +660,280 @@ static unsigned char *ftrace_jmp_replace(unsigned long ip, unsigned long addr)
         */
        return calc.code;
 }
+#endif
+/* Currently only x86_64 supports dynamic trampolines */
+#ifdef CONFIG_X86_64
+#ifdef CONFIG_MODULES
+#include <linux/moduleloader.h>
+/* Module allocation simplifies allocating memory for code */
+static inline void *alloc_tramp(unsigned long size)
+{
+        return module_alloc(size);
+}
+static inline void tramp_free(void *tramp)
+{
+        module_free(NULL, tramp);
+}
+#else
+/* Trampolines can only be created if modules are supported */
+static inline void *alloc_tramp(unsigned long size)
+{
+        return NULL;
+}
+static inline void tramp_free(void *tramp) { }
+#endif
+/* Defined as markers to the end of the ftrace default trampolines */
+extern void ftrace_caller_end(void);
+extern void ftrace_regs_caller_end(void);
+extern void ftrace_return(void);
+extern void ftrace_caller_op_ptr(void);
+extern void ftrace_regs_caller_op_ptr(void);
+/* movq function_trace_op(%rip), %rdx */
+/* 0x48 0x8b 0x15 <offset-to-ftrace_trace_op (4 bytes)> */
+#define OP_REF_SIZE     7
+/*
+ * The ftrace_ops is passed to the function callback. Since the
+ * trampoline only services a single ftrace_ops, we can pass in
+ * that ops directly.
+ *
+ * The ftrace_op_code_union is used to create a pointer to the
+ * ftrace_ops that will be passed to the callback function.
+ */
+union ftrace_op_code_union {
+        char code[OP_REF_SIZE];
+        struct {
+                char op[3];
+                int offset;
+        } __attribute__((packed));
+};
+static unsigned long
+create_trampoline(struct ftrace_ops *ops, unsigned int *tramp_size)
+{
+        unsigned const char *jmp;
+        unsigned long start_offset;
+        unsigned long end_offset;
+        unsigned long op_offset;
+        unsigned long offset;
+        unsigned long size;
+        unsigned long ip;
+        unsigned long *ptr;
+        void *trampoline;
+        /* 48 8b 15 <offset> is movq <offset>(%rip), %rdx */
+        unsigned const char op_ref[] = { 0x48, 0x8b, 0x15 };
+        union ftrace_op_code_union op_ptr;
+        int ret;
+        if (ops->flags & FTRACE_OPS_FL_SAVE_REGS) {
+                start_offset = (unsigned long)ftrace_regs_caller;
+                end_offset = (unsigned long)ftrace_regs_caller_end;
+                op_offset = (unsigned long)ftrace_regs_caller_op_ptr;
+        } else {
+                start_offset = (unsigned long)ftrace_caller;
+                end_offset = (unsigned long)ftrace_caller_end;
+                op_offset = (unsigned long)ftrace_caller_op_ptr;
+        }
+        size = end_offset - start_offset;
+        /*
+         * Allocate enough size to store the ftrace_caller code,
+         * the jmp to ftrace_return, as well as the address of
+         * the ftrace_ops this trampoline is used for.
+         */
+        trampoline = alloc_tramp(size + MCOUNT_INSN_SIZE + sizeof(void *));
+        if (!trampoline)
+                return 0;
+        *tramp_size = size + MCOUNT_INSN_SIZE + sizeof(void *);
+        /* Copy ftrace_caller onto the trampoline memory */
+        ret = probe_kernel_read(trampoline, (void *)start_offset, size);
+        if (WARN_ON(ret < 0)) {
+                tramp_free(trampoline);
+                return 0;
+        }
+        ip = (unsigned long)trampoline + size;
+        /* The trampoline ends with a jmp to ftrace_return */
+        jmp = ftrace_jmp_replace(ip, (unsigned long)ftrace_return);
+        memcpy(trampoline + size, jmp, MCOUNT_INSN_SIZE);
+        /*
+         * The address of the ftrace_ops that is used for this trampoline
+         * is stored at the end of the trampoline. This will be used to
+         * load the third parameter for the callback. Basically, that
+         * location at the end of the trampoline takes the place of
+         * the global function_trace_op variable.
+         */
+        ptr = (unsigned long *)(trampoline + size + MCOUNT_INSN_SIZE);
+        *ptr = (unsigned long)ops;
+        op_offset -= start_offset;
+        memcpy(&op_ptr, trampoline + op_offset, OP_REF_SIZE);
+        /* Are we pointing to the reference? */
+        if (WARN_ON(memcmp(op_ptr.op, op_ref, 3) != 0)) {
+                tramp_free(trampoline);
+                return 0;
+        }
+        /* Load the contents of ptr into the callback parameter */
+        offset = (unsigned long)ptr;
+        offset -= (unsigned long)trampoline + op_offset + OP_REF_SIZE;
+        op_ptr.offset = offset;
+        /* put in the new offset to the ftrace_ops */
+        memcpy(trampoline + op_offset, &op_ptr, OP_REF_SIZE);
+        /* ALLOC_TRAMP flags lets us know we created it */
+        ops->flags |= FTRACE_OPS_FL_ALLOC_TRAMP;
+        return (unsigned long)trampoline;
+}
+static unsigned long calc_trampoline_call_offset(bool save_regs)
+{
+        unsigned long start_offset;
+        unsigned long call_offset;
+        if (save_regs) {
+                start_offset = (unsigned long)ftrace_regs_caller;
+                call_offset = (unsigned long)ftrace_regs_call;
+        } else {
+                start_offset = (unsigned long)ftrace_caller;
+                call_offset = (unsigned long)ftrace_call;
+        }
+        return call_offset - start_offset;
+}
+void arch_ftrace_update_trampoline(struct ftrace_ops *ops)
+{
+        ftrace_func_t func;
+        unsigned char *new;
+        unsigned long offset;
+        unsigned long ip;
+        unsigned int size;
+        int ret;
+        if (ops->trampoline) {
+                /*
+                 * The ftrace_ops caller may set up its own trampoline.
+                 * In such a case, this code must not modify it.
+                 */
+                if (!(ops->flags & FTRACE_OPS_FL_ALLOC_TRAMP))
+                        return;
+        } else {
+                ops->trampoline = create_trampoline(ops, &size);
+                if (!ops->trampoline)
+                        return;
+                ops->trampoline_size = size;
+        }
+        offset = calc_trampoline_call_offset(ops->flags & FTRACE_OPS_FL_SAVE_REGS);
+        ip = ops->trampoline + offset;
+        func = ftrace_ops_get_func(ops);
+        /* Do a safe modify in case the trampoline is executing */
+        new = ftrace_call_replace(ip, (unsigned long)func);
+        ret = update_ftrace_func(ip, new);
+        /* The update should never fail */
+        WARN_ON(ret);
+}
+/* Return the address of the function the trampoline calls */
+static void *addr_from_call(void *ptr)
+{
+        union ftrace_code_union calc;
+        int ret;
+        ret = probe_kernel_read(&calc, ptr, MCOUNT_INSN_SIZE);
+        if (WARN_ON_ONCE(ret < 0))
+                return NULL;
+        /* Make sure this is a call */
+        if (WARN_ON_ONCE(calc.e8 != 0xe8)) {
+                pr_warn("Expected e8, got %x\n", calc.e8);
+                return NULL;
+        }
+        return ptr + MCOUNT_INSN_SIZE + calc.offset;
+}
+void prepare_ftrace_return(unsigned long self_addr, unsigned long *parent,
+                           unsigned long frame_pointer);
+/*
+ * If the ops->trampoline was not allocated, then it probably
+ * has a static trampoline func, or is the ftrace caller itself.
+ */
+static void *static_tramp_func(struct ftrace_ops *ops, struct dyn_ftrace *rec)
+{
+        unsigned long offset;
+        bool save_regs = rec->flags & FTRACE_FL_REGS_EN;
+        void *ptr;
+        if (ops && ops->trampoline) {
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+                /*
+                 * We only know about function graph tracer setting as static
+                 * trampoline.
+                 */
+                if (ops->trampoline == FTRACE_GRAPH_ADDR)
+                        return (void *)prepare_ftrace_return;
+#endif
+                return NULL;
+        }
+        offset = calc_trampoline_call_offset(save_regs);
+        if (save_regs)
+                ptr = (void *)FTRACE_REGS_ADDR + offset;
+        else
+                ptr = (void *)FTRACE_ADDR + offset;
+        return addr_from_call(ptr);
+}
+void *arch_ftrace_trampoline_func(struct ftrace_ops *ops, struct dyn_ftrace *rec)
+{
+        unsigned long offset;
+        /* If we didn't allocate this trampoline, consider it static */
+        if (!ops || !(ops->flags & FTRACE_OPS_FL_ALLOC_TRAMP))
+                return static_tramp_func(ops, rec);
+        offset = calc_trampoline_call_offset(ops->flags & FTRACE_OPS_FL_SAVE_REGS);
+        return addr_from_call((void *)ops->trampoline + offset);
+}
+void arch_ftrace_trampoline_free(struct ftrace_ops *ops)
+{
+        if (!ops || !(ops->flags & FTRACE_OPS_FL_ALLOC_TRAMP))
+                return;
+        tramp_free((void *)ops->trampoline);
+        ops->trampoline = 0;
+}
+#endif /* CONFIG_X86_64 */
+#endif /* CONFIG_DYNAMIC_FTRACE */
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+#ifdef CONFIG_DYNAMIC_FTRACE
+extern void ftrace_graph_call(void);
 static int ftrace_mod_jmp(unsigned long ip, void *func)
 {
@@ -694,7 +964,7 @@ int ftrace_disable_ftrace_graph_caller(void)
 * Hook the return address and push it in the stack of return addrs
 * in current thread info.
 */
-void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr,
+void prepare_ftrace_return(unsigned long self_addr, unsigned long *parent,
                           unsigned long frame_pointer)
 {
        unsigned long old;
diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c
index 922d28581024..6307a0f0cf17 100644
--- a/arch/x86/kernel/irq.c
+++ b/arch/x86/kernel/irq.c
@@ -59,78 +59,78 @@ int arch_show_interrupts(struct seq_file *p, int prec)
        seq_printf(p, "%*s: ", prec, "NMI");
        for_each_online_cpu(j)
                seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
-        seq_printf(p, "  Non-maskable interrupts\n");
+        seq_puts(p, "  Non-maskable interrupts\n");
 #ifdef CONFIG_X86_LOCAL_APIC
        seq_printf(p, "%*s: ", prec, "LOC");
        for_each_online_cpu(j)
                seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
-        seq_printf(p, "  Local timer interrupts\n");
+        seq_puts(p, "  Local timer interrupts\n");
        seq_printf(p, "%*s: ", prec, "SPU");
        for_each_online_cpu(j)
                seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
-        seq_printf(p, "  Spurious interrupts\n");
+        seq_puts(p, "  Spurious interrupts\n");
        seq_printf(p, "%*s: ", prec, "PMI");
        for_each_online_cpu(j)
                seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
-        seq_printf(p, "  Performance monitoring interrupts\n");
+        seq_puts(p, "  Performance monitoring interrupts\n");
        seq_printf(p, "%*s: ", prec, "IWI");
        for_each_online_cpu(j)
                seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
-        seq_printf(p, "  IRQ work interrupts\n");
+        seq_puts(p, "  IRQ work interrupts\n");
        seq_printf(p, "%*s: ", prec, "RTR");
        for_each_online_cpu(j)
                seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
-        seq_printf(p, "  APIC ICR read retries\n");
+        seq_puts(p, "  APIC ICR read retries\n");
 #endif
        if (x86_platform_ipi_callback) {
                seq_printf(p, "%*s: ", prec, "PLT");
                for_each_online_cpu(j)
                        seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
-                seq_printf(p, "  Platform interrupts\n");
+                seq_puts(p, "  Platform interrupts\n");
        }
 #ifdef CONFIG_SMP
        seq_printf(p, "%*s: ", prec, "RES");
        for_each_online_cpu(j)
                seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
-        seq_printf(p, "  Rescheduling interrupts\n");
+        seq_puts(p, "  Rescheduling interrupts\n");
        seq_printf(p, "%*s: ", prec, "CAL");
        for_each_online_cpu(j)
                seq_printf(p, "%10u ", irq_stats(j)->irq_call_count -
                                        irq_stats(j)->irq_tlb_count);
-        seq_printf(p, "  Function call interrupts\n");
+        seq_puts(p, "  Function call interrupts\n");
        seq_printf(p, "%*s: ", prec, "TLB");
        for_each_online_cpu(j)
                seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
-        seq_printf(p, "  TLB shootdowns\n");
+        seq_puts(p, "  TLB shootdowns\n");
 #endif
 #ifdef CONFIG_X86_THERMAL_VECTOR
        seq_printf(p, "%*s: ", prec, "TRM");
        for_each_online_cpu(j)
                seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
-        seq_printf(p, "  Thermal event interrupts\n");
+        seq_puts(p, "  Thermal event interrupts\n");
 #endif
 #ifdef CONFIG_X86_MCE_THRESHOLD
        seq_printf(p, "%*s: ", prec, "THR");
        for_each_online_cpu(j)
                seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
-        seq_printf(p, "  Threshold APIC interrupts\n");
+        seq_puts(p, "  Threshold APIC interrupts\n");
 #endif
 #ifdef CONFIG_X86_MCE
        seq_printf(p, "%*s: ", prec, "MCE");
        for_each_online_cpu(j)
                seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
-        seq_printf(p, "  Machine check exceptions\n");
+        seq_puts(p, "  Machine check exceptions\n");
        seq_printf(p, "%*s: ", prec, "MCP");
        for_each_online_cpu(j)
                seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
-        seq_printf(p, "  Machine check polls\n");
+        seq_puts(p, "  Machine check polls\n");
 #endif
 #if IS_ENABLED(CONFIG_HYPERV) || defined(CONFIG_XEN)
        seq_printf(p, "%*s: ", prec, "THR");
        for_each_online_cpu(j)
                seq_printf(p, "%10u ", irq_stats(j)->irq_hv_callback_count);
-        seq_printf(p, "  Hypervisor callback interrupts\n");
+        seq_puts(p, "  Hypervisor callback interrupts\n");
 #endif
        seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
 #if defined(CONFIG_X86_IO_APIC)
diff --git a/arch/x86/kernel/kprobes/core.c b/arch/x86/kernel/kprobes/core.c
index 67e6d19ef1be..f7e3cd50ece0 100644
--- a/arch/x86/kernel/kprobes/core.c
+++ b/arch/x86/kernel/kprobes/core.c
@@ -285,7 +285,7 @@ static int can_probe(unsigned long paddr)
                 * normally used, we just go through if there is no kprobe.
                 */
                __addr = recover_probed_instruction(buf, addr);
-                kernel_insn_init(&insn, (void *)__addr);
+                kernel_insn_init(&insn, (void *)__addr, MAX_INSN_SIZE);
                insn_get_length(&insn);
                /*
@@ -330,8 +330,10 @@ int __copy_instruction(u8 *dest, u8 *src)
 {
        struct insn insn;
        kprobe_opcode_t buf[MAX_INSN_SIZE];
+        unsigned long recovered_insn =
+                recover_probed_instruction(buf, (unsigned long)src);
-        kernel_insn_init(&insn, (void *)recover_probed_instruction(buf, (unsigned long)src));
+        kernel_insn_init(&insn, (void *)recovered_insn, MAX_INSN_SIZE);
        insn_get_length(&insn);
        /* Another subsystem puts a breakpoint, failed to recover */
        if (insn.opcode.bytes[0] == BREAKPOINT_INSTRUCTION)
@@ -342,7 +344,7 @@ int __copy_instruction(u8 *dest, u8 *src)
        if (insn_rip_relative(&insn)) {
                s64 newdisp;
                u8 *disp;
-                kernel_insn_init(&insn, dest);
+                kernel_insn_init(&insn, dest, insn.length);
                insn_get_displacement(&insn);
                /*
                 * The copied instruction uses the %rip-relative addressing
diff --git a/arch/x86/kernel/kprobes/ftrace.c b/arch/x86/kernel/kprobes/ftrace.c
index 717b02a22e67..5f8f0b3cc674 100644
--- a/arch/x86/kernel/kprobes/ftrace.c
+++ b/arch/x86/kernel/kprobes/ftrace.c
@@ -27,7 +27,7 @@
 static nokprobe_inline
 int __skip_singlestep(struct kprobe *p, struct pt_regs *regs,
-                      struct kprobe_ctlblk *kcb)
+                      struct kprobe_ctlblk *kcb, unsigned long orig_ip)
 {
        /*
         * Emulate singlestep (and also recover regs->ip)
@@ -39,6 +39,8 @@ int __skip_singlestep(struct kprobe *p, struct pt_regs *regs,
                p->post_handler(p, regs, 0);
        }
        __this_cpu_write(current_kprobe, NULL);
+        if (orig_ip)
+                regs->ip = orig_ip;
        return 1;
 }
@@ -46,7 +48,7 @@ int skip_singlestep(struct kprobe *p, struct pt_regs *regs,
                    struct kprobe_ctlblk *kcb)
 {
        if (kprobe_ftrace(p))
-                return __skip_singlestep(p, regs, kcb);
+                return __skip_singlestep(p, regs, kcb, 0);
        else
                return 0;
 }
@@ -71,13 +73,14 @@ void kprobe_ftrace_handler(unsigned long ip, unsigned long parent_ip,
        if (kprobe_running()) {
                kprobes_inc_nmissed_count(p);
        } else {
+                unsigned long orig_ip = regs->ip;
                /* Kprobe handler expects regs->ip = ip + 1 as breakpoint hit */
                regs->ip = ip + sizeof(kprobe_opcode_t);
                __this_cpu_write(current_kprobe, p);
                kcb->kprobe_status = KPROBE_HIT_ACTIVE;
                if (!p->pre_handler || !p->pre_handler(p, regs))
-                        __skip_singlestep(p, regs, kcb);
+                        __skip_singlestep(p, regs, kcb, orig_ip);
                /*
                 * If pre_handler returns !0, it sets regs->ip and
                 * resets current kprobe.
diff --git a/arch/x86/kernel/kprobes/opt.c b/arch/x86/kernel/kprobes/opt.c
index f1314d0bcf0a..7c523bbf3dc8 100644
--- a/arch/x86/kernel/kprobes/opt.c
+++ b/arch/x86/kernel/kprobes/opt.c
@@ -251,13 +251,15 @@ static int can_optimize(unsigned long paddr)
        /* Decode instructions */
        addr = paddr - offset;
        while (addr < paddr - offset + size) { /* Decode until function end */
+                unsigned long recovered_insn;
                if (search_exception_tables(addr))
                        /*
                         * Since some fixup code will jumps into this function,
                         * we can't optimize kprobe in this function.
                         */
                        return 0;
-                kernel_insn_init(&insn, (void *)recover_probed_instruction(buf, addr));
+                recovered_insn = recover_probed_instruction(buf, addr);
+                kernel_insn_init(&insn, (void *)recovered_insn, MAX_INSN_SIZE);
                insn_get_length(&insn);
                /* Another subsystem puts a breakpoint */
                if (insn.opcode.bytes[0] == BREAKPOINT_INSTRUCTION)
diff --git a/arch/x86/kernel/mcount_64.S b/arch/x86/kernel/mcount_64.S
index c73aecf10d34..94ea120fa21f 100644
--- a/arch/x86/kernel/mcount_64.S
+++ b/arch/x86/kernel/mcount_64.S
@@ -21,40 +21,159 @@
 # define function_hook  mcount
 #endif
+/* All cases save the original rbp (8 bytes) */
+#ifdef CONFIG_FRAME_POINTER
+# ifdef CC_USING_FENTRY
+/* Save parent and function stack frames (rip and rbp) */
+#  define MCOUNT_FRAME_SIZE     (8+16*2)
+# else
+/* Save just function stack frame (rip and rbp) */
+#  define MCOUNT_FRAME_SIZE     (8+16)
+# endif
+#else
+/* No need to save a stack frame */
+# define MCOUNT_FRAME_SIZE      8
+#endif /* CONFIG_FRAME_POINTER */
+/* Size of stack used to save mcount regs in save_mcount_regs */
+#define MCOUNT_REG_SIZE         (SS+8 + MCOUNT_FRAME_SIZE)
+/*
+ * gcc -pg option adds a call to 'mcount' in most functions.
+ * When -mfentry is used, the call is to 'fentry' and not 'mcount'
+ * and is done before the function's stack frame is set up.
+ * They both require a set of regs to be saved before calling
+ * any C code and restored before returning back to the function.
+ *
+ * On boot up, all these calls are converted into nops. When tracing
+ * is enabled, the call can jump to either ftrace_caller or
+ * ftrace_regs_caller. Callbacks (tracing functions) that require
+ * ftrace_regs_caller (like kprobes) need to have pt_regs passed to
+ * it. For this reason, the size of the pt_regs structure will be
+ * allocated on the stack and the required mcount registers will
+ * be saved in the locations that pt_regs has them in.
+ */
+/*
+ * @added: the amount of stack added before calling this
+ *
+ * After this is called, the following registers contain:
+ *
+ *  %rdi - holds the address that called the trampoline
+ *  %rsi - holds the parent function (traced function's return address)
+ *  %rdx - holds the original %rbp
+ */
+.macro save_mcount_regs added=0
+        /* Always save the original rbp */
+        pushq %rbp
+#ifdef CONFIG_FRAME_POINTER
+        /*
+         * Stack traces will stop at the ftrace trampoline if the frame pointer
+         * is not set up properly. If fentry is used, we need to save a frame
+         * pointer for the parent as well as the function traced, because the
+         * fentry is called before the stack frame is set up, where as mcount
+         * is called afterward.
+         */
+#ifdef CC_USING_FENTRY
+        /* Save the parent pointer (skip orig rbp and our return address) */
+        pushq \added+8*2(%rsp)
+        pushq %rbp
+        movq %rsp, %rbp
+        /* Save the return address (now skip orig rbp, rbp and parent) */
+        pushq \added+8*3(%rsp)
+#else
+        /* Can't assume that rip is before this (unless added was zero) */
+        pushq \added+8(%rsp)
+#endif
+        pushq %rbp
+        movq %rsp, %rbp
+#endif /* CONFIG_FRAME_POINTER */
+        /*
+         * We add enough stack to save all regs.
+         */
+        subq $(MCOUNT_REG_SIZE - MCOUNT_FRAME_SIZE), %rsp
+        movq %rax, RAX(%rsp)
+        movq %rcx, RCX(%rsp)
+        movq %rdx, RDX(%rsp)
+        movq %rsi, RSI(%rsp)
+        movq %rdi, RDI(%rsp)
+        movq %r8, R8(%rsp)
+        movq %r9, R9(%rsp)
+        /*
+         * Save the original RBP. Even though the mcount ABI does not
+         * require this, it helps out callers.
+         */
+        movq MCOUNT_REG_SIZE-8(%rsp), %rdx
+        movq %rdx, RBP(%rsp)
+        /* Copy the parent address into %rsi (second parameter) */
+#ifdef CC_USING_FENTRY
+        movq MCOUNT_REG_SIZE+8+\added(%rsp), %rsi
+#else
+        /* %rdx contains original %rbp */
+        movq 8(%rdx), %rsi
+#endif
+         /* Move RIP to its proper location */
+        movq MCOUNT_REG_SIZE+\added(%rsp), %rdi
+        movq %rdi, RIP(%rsp)
+        /*
+         * Now %rdi (the first parameter) has the return address of
+         * where ftrace_call returns. But the callbacks expect the
+         * address of the call itself.
+         */
+        subq $MCOUNT_INSN_SIZE, %rdi
+        .endm
+.macro restore_mcount_regs
+        movq R9(%rsp), %r9
+        movq R8(%rsp), %r8
+        movq RDI(%rsp), %rdi
+        movq RSI(%rsp), %rsi
+        movq RDX(%rsp), %rdx
+        movq RCX(%rsp), %rcx
+        movq RAX(%rsp), %rax
+        /* ftrace_regs_caller can modify %rbp */
+        movq RBP(%rsp), %rbp
+        addq $MCOUNT_REG_SIZE, %rsp
+        .endm
 #ifdef CONFIG_DYNAMIC_FTRACE
 ENTRY(function_hook)
        retq
 END(function_hook)
-/* skip is set if stack has been adjusted */
+ENTRY(ftrace_caller)
-.macro ftrace_caller_setup skip=0
+        /* save_mcount_regs fills in first two parameters */
-        MCOUNT_SAVE_FRAME \skip
+        save_mcount_regs
+GLOBAL(ftrace_caller_op_ptr)
        /* Load the ftrace_ops into the 3rd parameter */
        movq function_trace_op(%rip), %rdx
-        /* Load ip into the first parameter */
-        movq RIP(%rsp), %rdi
-        subq $MCOUNT_INSN_SIZE, %rdi
-        /* Load the parent_ip into the second parameter */
-#ifdef CC_USING_FENTRY
-        movq SS+16(%rsp), %rsi
-#else
-        movq 8(%rbp), %rsi
-#endif
-.endm
-ENTRY(ftrace_caller)
-        ftrace_caller_setup
        /* regs go into 4th parameter (but make it NULL) */
        movq $0, %rcx
 GLOBAL(ftrace_call)
        call ftrace_stub
-        MCOUNT_RESTORE_FRAME
+        restore_mcount_regs
-ftrace_return:
+        /*
+         * The copied trampoline must call ftrace_return as it
+         * still may need to call the function graph tracer.
+         */
+GLOBAL(ftrace_caller_end)
+GLOBAL(ftrace_return)
 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
 GLOBAL(ftrace_graph_call)
@@ -66,11 +185,16 @@ GLOBAL(ftrace_stub)
 END(ftrace_caller)
 ENTRY(ftrace_regs_caller)
-        /* Save the current flags before compare (in SS location)*/
+        /* Save the current flags before any operations that can change them */
        pushfq
-        /* skip=8 to skip flags saved in SS */
+        /* added 8 bytes to save flags */
-        ftrace_caller_setup 8
+        save_mcount_regs 8
+        /* save_mcount_regs fills in first two parameters */
+GLOBAL(ftrace_regs_caller_op_ptr)
+        /* Load the ftrace_ops into the 3rd parameter */
+        movq function_trace_op(%rip), %rdx
        /* Save the rest of pt_regs */
        movq %r15, R15(%rsp)
@@ -79,18 +203,17 @@ ENTRY(ftrace_regs_caller)
        movq %r12, R12(%rsp)
        movq %r11, R11(%rsp)
        movq %r10, R10(%rsp)
-        movq %rbp, RBP(%rsp)
        movq %rbx, RBX(%rsp)
        /* Copy saved flags */
-        movq SS(%rsp), %rcx
+        movq MCOUNT_REG_SIZE(%rsp), %rcx
        movq %rcx, EFLAGS(%rsp)
        /* Kernel segments */
        movq $__KERNEL_DS, %rcx
        movq %rcx, SS(%rsp)
        movq $__KERNEL_CS, %rcx
        movq %rcx, CS(%rsp)
-        /* Stack - skipping return address */
+        /* Stack - skipping return address and flags */
-        leaq SS+16(%rsp), %rcx
+        leaq MCOUNT_REG_SIZE+8*2(%rsp), %rcx
        movq %rcx, RSP(%rsp)
        /* regs go into 4th parameter */
@@ -101,11 +224,11 @@ GLOBAL(ftrace_regs_call)
        /* Copy flags back to SS, to restore them */
        movq EFLAGS(%rsp), %rax
-        movq %rax, SS(%rsp)
+        movq %rax, MCOUNT_REG_SIZE(%rsp)
        /* Handlers can change the RIP */
        movq RIP(%rsp), %rax
-        movq %rax, SS+8(%rsp)
+        movq %rax, MCOUNT_REG_SIZE+8(%rsp)
        /* restore the rest of pt_regs */
        movq R15(%rsp), %r15
@@ -113,19 +236,22 @@ GLOBAL(ftrace_regs_call)
        movq R13(%rsp), %r13
        movq R12(%rsp), %r12
        movq R10(%rsp), %r10
-        movq RBP(%rsp), %rbp
        movq RBX(%rsp), %rbx
-        /* skip=8 to skip flags saved in SS */
+        restore_mcount_regs
-        MCOUNT_RESTORE_FRAME 8
        /* Restore flags */
        popfq
-        jmp ftrace_return
+        /*
+         * As this jmp to ftrace_return can be a short jump
+         * it must not be copied into the trampoline.
+         * The trampoline will add the code to jump
+         * to the return.
+         */
+GLOBAL(ftrace_regs_caller_end)
-        popfq
+        jmp ftrace_return
-        jmp  ftrace_stub
 END(ftrace_regs_caller)
@@ -136,6 +262,7 @@ ENTRY(function_hook)
        cmpq $ftrace_stub, ftrace_trace_function
        jnz trace
+fgraph_trace:
 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
        cmpq $ftrace_stub, ftrace_graph_return
        jnz ftrace_graph_caller
@@ -148,42 +275,35 @@ GLOBAL(ftrace_stub)
        retq
 trace:
-        MCOUNT_SAVE_FRAME
+        /* save_mcount_regs fills in first two parameters */
+        save_mcount_regs
-        movq RIP(%rsp), %rdi
-#ifdef CC_USING_FENTRY
-        movq SS+16(%rsp), %rsi
-#else
-        movq 8(%rbp), %rsi
-#endif
-        subq $MCOUNT_INSN_SIZE, %rdi
        call   *ftrace_trace_function
-        MCOUNT_RESTORE_FRAME
+        restore_mcount_regs
-        jmp ftrace_stub
+        jmp fgraph_trace
 END(function_hook)
 #endif /* CONFIG_DYNAMIC_FTRACE */
 #endif /* CONFIG_FUNCTION_TRACER */
 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
 ENTRY(ftrace_graph_caller)
-        MCOUNT_SAVE_FRAME
+        /* Saves rbp into %rdx and fills first parameter  */
+        save_mcount_regs
 #ifdef CC_USING_FENTRY
-        leaq SS+16(%rsp), %rdi
+        leaq MCOUNT_REG_SIZE+8(%rsp), %rsi
        movq $0, %rdx   /* No framepointers needed */
 #else
-        leaq 8(%rbp), %rdi
+        /* Save address of the return address of traced function */
-        movq (%rbp), %rdx
+        leaq 8(%rdx), %rsi
+        /* ftrace does sanity checks against frame pointers */
+        movq (%rdx), %rdx
 #endif
-        movq RIP(%rsp), %rsi
-        subq $MCOUNT_INSN_SIZE, %rsi
        call    prepare_ftrace_return
-        MCOUNT_RESTORE_FRAME
+        restore_mcount_regs
        retq
 END(ftrace_graph_caller)
diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c
index c9603ac80de5..113e70784854 100644
--- a/arch/x86/kernel/msr.c
+++ b/arch/x86/kernel/msr.c
@@ -22,6 +22,8 @@
 * an SMP box will direct the access to CPU %d.
 */
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 #include <linux/module.h>
 #include <linux/types.h>
@@ -50,11 +52,11 @@ static loff_t msr_seek(struct file *file, loff_t offset, int orig)
        mutex_lock(&inode->i_mutex);
        switch (orig) {
-        case 0:
+        case SEEK_SET:
                file->f_pos = offset;
                ret = file->f_pos;
                break;
-        case 1:
+        case SEEK_CUR:
                file->f_pos += offset;
                ret = file->f_pos;
                break;
@@ -206,7 +208,7 @@ static int msr_device_create(int cpu)
        dev = device_create(msr_class, NULL, MKDEV(MSR_MAJOR, cpu), NULL,
                            "msr%d", cpu);
-        return IS_ERR(dev) ? PTR_ERR(dev) : 0;
+        return PTR_ERR_OR_ZERO(dev);
 }
 static void msr_device_destroy(int cpu)
@@ -248,8 +250,7 @@ static int __init msr_init(void)
        i = 0;
        if (__register_chrdev(MSR_MAJOR, 0, NR_CPUS, "cpu/msr", &msr_fops)) {
-                printk(KERN_ERR "msr: unable to get major %d for msr\n",
+                pr_err("unable to get major %d for msr\n", MSR_MAJOR);
-                       MSR_MAJOR);
                err = -EBUSY;
                goto out;
        }
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index ab08aa2276fb..ab4734e5411d 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -960,6 +960,8 @@ void __init setup_arch(char **cmdline_p)
        init_mm.end_data = (unsigned long) _edata;
        init_mm.brk = _brk_end;
+        mpx_mm_init(&init_mm);
        code_resource.start = __pa_symbol(_text);
        code_resource.end = __pa_symbol(_etext)-1;
        data_resource.start = __pa_symbol(_etext);
@@ -1190,9 +1192,7 @@ void __init setup_arch(char **cmdline_p)
        tboot_probe();
-#ifdef CONFIG_X86_64
        map_vsyscall();
-#endif
        generic_apic_probe();
diff --git a/arch/x86/kernel/setup_percpu.c b/arch/x86/kernel/setup_percpu.c
index 5cdff0357746..e4fcb87ba7a6 100644
--- a/arch/x86/kernel/setup_percpu.c
+++ b/arch/x86/kernel/setup_percpu.c
@@ -30,7 +30,7 @@ EXPORT_PER_CPU_SYMBOL(cpu_number);
 #define BOOT_PERCPU_OFFSET 0
 #endif
-DEFINE_PER_CPU(unsigned long, this_cpu_off) = BOOT_PERCPU_OFFSET;
+DEFINE_PER_CPU_READ_MOSTLY(unsigned long, this_cpu_off) = BOOT_PERCPU_OFFSET;
 EXPORT_PER_CPU_SYMBOL(this_cpu_off);
 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly = {
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 668d8f2a8781..7a8f5845e8eb 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -99,7 +99,7 @@ EXPORT_PER_CPU_SYMBOL(cpu_core_map);
 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
 /* Per CPU bogomips and other parameters */
-DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
+DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
 EXPORT_PER_CPU_SYMBOL(cpu_info);
 atomic_t init_deasserted;
diff --git a/arch/x86/kernel/sysfb.c b/arch/x86/kernel/sysfb.c
index 193ec2ce46c7..160386e9fc17 100644
--- a/arch/x86/kernel/sysfb.c
+++ b/arch/x86/kernel/sysfb.c
@@ -67,7 +67,7 @@ static __init int sysfb_init(void)
        pd = platform_device_register_resndata(NULL, name, 0,
                                               NULL, 0, si, sizeof(*si));
-        return IS_ERR(pd) ? PTR_ERR(pd) : 0;
+        return PTR_ERR_OR_ZERO(pd);
 }
 /* must execute after PCI subsystem for EFI quirks */
diff --git a/arch/x86/kernel/sysfb_simplefb.c b/arch/x86/kernel/sysfb_simplefb.c
index 86179d409893..764a29f84de7 100644
--- a/arch/x86/kernel/sysfb_simplefb.c
+++ b/arch/x86/kernel/sysfb_simplefb.c
@@ -88,8 +88,5 @@ __init int create_simplefb(const struct screen_info *si,
        pd = platform_device_register_resndata(NULL, "simple-framebuffer", 0,
                                               &res, 1, mode, sizeof(*mode));
-        if (IS_ERR(pd))
+        return PTR_ERR_OR_ZERO(pd);
-                return PTR_ERR(pd);
-        return 0;
 }
diff --git a/arch/x86/kernel/time.c b/arch/x86/kernel/time.c
index 0fa29609b2c4..25adc0e16eaa 100644
--- a/arch/x86/kernel/time.c
+++ b/arch/x86/kernel/time.c
@@ -23,7 +23,7 @@
 #include <asm/time.h>
 #ifdef CONFIG_X86_64
-__visible DEFINE_VVAR(volatile unsigned long, jiffies) = INITIAL_JIFFIES;
+__visible volatile unsigned long jiffies __cacheline_aligned = INITIAL_JIFFIES;
 #endif
 unsigned long profile_pc(struct pt_regs *regs)
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index de801f22128a..a9ae20579895 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -60,6 +60,7 @@
 #include <asm/fixmap.h>
 #include <asm/mach_traps.h>
 #include <asm/alternative.h>
+#include <asm/mpx.h>
 #ifdef CONFIG_X86_64
 #include <asm/x86_init.h>
@@ -228,7 +229,6 @@ dotraplinkage void do_##name(struct pt_regs *regs, long error_code)	\
 DO_ERROR(X86_TRAP_DE,     SIGFPE,  "divide error",              divide_error)
 DO_ERROR(X86_TRAP_OF,     SIGSEGV, "overflow",                  overflow)
-DO_ERROR(X86_TRAP_BR,     SIGSEGV, "bounds",                    bounds)
 DO_ERROR(X86_TRAP_UD,     SIGILL,  "invalid opcode",            invalid_op)
 DO_ERROR(X86_TRAP_OLD_MF, SIGFPE,  "coprocessor segment overrun",coprocessor_segment_overrun)
 DO_ERROR(X86_TRAP_TS,     SIGSEGV, "invalid TSS",               invalid_TSS)
@@ -286,6 +286,89 @@ dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code)
 }
 #endif
+dotraplinkage void do_bounds(struct pt_regs *regs, long error_code)
+{
+        struct task_struct *tsk = current;
+        struct xsave_struct *xsave_buf;
+        enum ctx_state prev_state;
+        struct bndcsr *bndcsr;
+        siginfo_t *info;
+        prev_state = exception_enter();
+        if (notify_die(DIE_TRAP, "bounds", regs, error_code,
+                        X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP)
+                goto exit;
+        conditional_sti(regs);
+        if (!user_mode(regs))
+                die("bounds", regs, error_code);
+        if (!cpu_feature_enabled(X86_FEATURE_MPX)) {
+                /* The exception is not from Intel MPX */
+                goto exit_trap;
+        }
+        /*
+         * We need to look at BNDSTATUS to resolve this exception.
+         * It is not directly accessible, though, so we need to
+         * do an xsave and then pull it out of the xsave buffer.
+         */
+        fpu_save_init(&tsk->thread.fpu);
+        xsave_buf = &(tsk->thread.fpu.state->xsave);
+        bndcsr = get_xsave_addr(xsave_buf, XSTATE_BNDCSR);
+        if (!bndcsr)
+                goto exit_trap;
+        /*
+         * The error code field of the BNDSTATUS register communicates status
+         * information of a bound range exception #BR or operation involving
+         * bound directory.
+         */
+        switch (bndcsr->bndstatus & MPX_BNDSTA_ERROR_CODE) {
+        case 2: /* Bound directory has invalid entry. */
+                if (mpx_handle_bd_fault(xsave_buf))
+                        goto exit_trap;
+                break; /* Success, it was handled */
+        case 1: /* Bound violation. */
+                info = mpx_generate_siginfo(regs, xsave_buf);
+                if (PTR_ERR(info)) {
+                        /*
+                         * We failed to decode the MPX instruction.  Act as if
+                         * the exception was not caused by MPX.
+                         */
+                        goto exit_trap;
+                }
+                /*
+                 * Success, we decoded the instruction and retrieved
+                 * an 'info' containing the address being accessed
+                 * which caused the exception.  This information
+                 * allows and application to possibly handle the
+                 * #BR exception itself.
+                 */
+                do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, info);
+                kfree(info);
+                break;
+        case 0: /* No exception caused by Intel MPX operations. */
+                goto exit_trap;
+        default:
+                die("bounds", regs, error_code);
+        }
+exit:
+        exception_exit(prev_state);
+        return;
+exit_trap:
+        /*
+         * This path out is for all the cases where we could not
+         * handle the exception in some way (like allocating a
+         * table or telling userspace about it.  We will also end
+         * up here if the kernel has MPX turned off at compile
+         * time..
+         */
+        do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, NULL);
+        exception_exit(prev_state);
+}
 dotraplinkage void
 do_general_protection(struct pt_regs *regs, long error_code)
 {
@@ -387,7 +470,7 @@ NOKPROBE_SYMBOL(do_int3);
 * for scheduling or signal handling. The actual stack switch is done in
 * entry.S
 */
-asmlinkage __visible struct pt_regs *sync_regs(struct pt_regs *eregs)
+asmlinkage __visible notrace struct pt_regs *sync_regs(struct pt_regs *eregs)
 {
        struct pt_regs *regs = eregs;
        /* Did already sync */
@@ -413,7 +496,7 @@ struct bad_iret_stack {
        struct pt_regs regs;
 };
-asmlinkage __visible
+asmlinkage __visible notrace
 struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s)
 {
        /*
@@ -436,6 +519,7 @@ struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s)
        BUG_ON(!user_mode_vm(&new_stack->regs));
        return new_stack;
 }
+NOKPROBE_SYMBOL(fixup_bad_iret);
 #endif
 /*
diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c
index 5d1cbfe4ae58..8b96a947021f 100644
--- a/arch/x86/kernel/uprobes.c
+++ b/arch/x86/kernel/uprobes.c
@@ -219,7 +219,7 @@ static int uprobe_init_insn(struct arch_uprobe *auprobe, struct insn *insn, bool
 {
        u32 volatile *good_insns;
-        insn_init(insn, auprobe->insn, x86_64);
+        insn_init(insn, auprobe->insn, sizeof(auprobe->insn), x86_64);
        /* has the side-effect of processing the entire instruction */
        insn_get_length(insn);
        if (WARN_ON_ONCE(!insn_complete(insn)))
diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S
index 49edf2dd3613..00bf300fd846 100644
--- a/arch/x86/kernel/vmlinux.lds.S
+++ b/arch/x86/kernel/vmlinux.lds.S
@@ -186,6 +186,8 @@ SECTIONS
         * start another segment - init.
         */
        PERCPU_VADDR(INTERNODE_CACHE_BYTES, 0, :percpu)
+        ASSERT(SIZEOF(.data..percpu) < CONFIG_PHYSICAL_START,
+               "per-CPU data too large - increase CONFIG_PHYSICAL_START")
 #endif
        INIT_TEXT_SECTION(PAGE_SIZE)
diff --git a/arch/x86/kernel/vsyscall_64.c b/arch/x86/kernel/vsyscall_64.c
index 957779f4eb40..2dcc6ff6fdcc 100644
--- a/arch/x86/kernel/vsyscall_64.c
+++ b/arch/x86/kernel/vsyscall_64.c
@@ -1,59 +1,43 @@
 /*
+ * Copyright (c) 2012-2014 Andy Lutomirski <luto@amacapital.net>
+ *
+ * Based on the original implementation which is:
 *  Copyright (C) 2001 Andrea Arcangeli <andrea@suse.de> SuSE
 *  Copyright 2003 Andi Kleen, SuSE Labs.
 *
- *  [ NOTE: this mechanism is now deprecated in favor of the vDSO. ]
+ *  Parts of the original code have been moved to arch/x86/vdso/vma.c
+ *
+ * This file implements vsyscall emulation.  vsyscalls are a legacy ABI:
+ * Userspace can request certain kernel services by calling fixed
+ * addresses.  This concept is problematic:
 *
- *  Thanks to hpa@transmeta.com for some useful hint.
+ * - It interferes with ASLR.
- *  Special thanks to Ingo Molnar for his early experience with
+ * - It's awkward to write code that lives in kernel addresses but is
- *  a different vsyscall implementation for Linux/IA32 and for the name.
+ *   callable by userspace at fixed addresses.
+ * - The whole concept is impossible for 32-bit compat userspace.
+ * - UML cannot easily virtualize a vsyscall.
 *
- *  vsyscall 1 is located at -10Mbyte, vsyscall 2 is located
+ * As of mid-2014, I believe that there is no new userspace code that
- *  at virtual address -10Mbyte+1024bytes etc... There are at max 4
+ * will use a vsyscall if the vDSO is present.  I hope that there will
- *  vsyscalls. One vsyscall can reserve more than 1 slot to avoid
+ * soon be no new userspace code that will ever use a vsyscall.
- *  jumping out of line if necessary. We cannot add more with this
- *  mechanism because older kernels won't return -ENOSYS.
 *
- *  Note: the concept clashes with user mode linux.  UML users should
+ * The code in this file emulates vsyscalls when notified of a page
- *  use the vDSO.
+ * fault to a vsyscall address.
 */
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-#include <linux/time.h>
-#include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/timer.h>
-#include <linux/seqlock.h>
-#include <linux/jiffies.h>
-#include <linux/sysctl.h>
-#include <linux/topology.h>
-#include <linux/timekeeper_internal.h>
-#include <linux/getcpu.h>
-#include <linux/cpu.h>
-#include <linux/smp.h>
-#include <linux/notifier.h>
 #include <linux/syscalls.h>
 #include <linux/ratelimit.h>
 #include <asm/vsyscall.h>
-#include <asm/pgtable.h>
-#include <asm/compat.h>
-#include <asm/page.h>
 #include <asm/unistd.h>
 #include <asm/fixmap.h>
-#include <asm/errno.h>
-#include <asm/io.h>
-#include <asm/segment.h>
-#include <asm/desc.h>
-#include <asm/topology.h>
 #include <asm/traps.h>
 #define CREATE_TRACE_POINTS
 #include "vsyscall_trace.h"
-DEFINE_VVAR(int, vgetcpu_mode);
 static enum { EMULATE, NATIVE, NONE } vsyscall_mode = EMULATE;
 static int __init vsyscall_setup(char *str)
@@ -222,6 +206,7 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address)
                                  "seccomp tried to change syscall nr or ip");
                do_exit(SIGSYS);
        }
+        regs->orig_ax = -1;
        if (tmp)
                goto do_ret;  /* skip requested */
@@ -284,46 +269,54 @@ sigsegv:
 }
 /*
- * Assume __initcall executes before all user space. Hopefully kmod
+ * A pseudo VMA to allow ptrace access for the vsyscall page.  This only
- * doesn't violate that. We'll find out if it does.
+ * covers the 64bit vsyscall page now. 32bit has a real VMA now and does
+ * not need special handling anymore:
 */
-static void vsyscall_set_cpu(int cpu)
+static const char *gate_vma_name(struct vm_area_struct *vma)
 {
-        unsigned long d;
+        return "[vsyscall]";
-        unsigned long node = 0;
-#ifdef CONFIG_NUMA
-        node = cpu_to_node(cpu);
-#endif
-        if (cpu_has(&cpu_data(cpu), X86_FEATURE_RDTSCP))
-                write_rdtscp_aux((node << 12) | cpu);
-        /*
-         * Store cpu number in limit so that it can be loaded quickly
-         * in user space in vgetcpu. (12 bits for the CPU and 8 bits for the node)
-         */
-        d = 0x0f40000000000ULL;
-        d |= cpu;
-        d |= (node & 0xf) << 12;
-        d |= (node >> 4) << 48;
-        write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_PER_CPU, &d, DESCTYPE_S);
 }
+static struct vm_operations_struct gate_vma_ops = {
-static void cpu_vsyscall_init(void *arg)
+        .name = gate_vma_name,
+};
+static struct vm_area_struct gate_vma = {
+        .vm_start       = VSYSCALL_ADDR,
+        .vm_end         = VSYSCALL_ADDR + PAGE_SIZE,
+        .vm_page_prot   = PAGE_READONLY_EXEC,
+        .vm_flags       = VM_READ | VM_EXEC,
+        .vm_ops         = &gate_vma_ops,
+};
+struct vm_area_struct *get_gate_vma(struct mm_struct *mm)
 {
-        /* preemption should be already off */
+#ifdef CONFIG_IA32_EMULATION
-        vsyscall_set_cpu(raw_smp_processor_id());
+        if (!mm || mm->context.ia32_compat)
+                return NULL;
+#endif
+        if (vsyscall_mode == NONE)
+                return NULL;
+        return &gate_vma;
 }
-static int
+int in_gate_area(struct mm_struct *mm, unsigned long addr)
-cpu_vsyscall_notifier(struct notifier_block *n, unsigned long action, void *arg)
 {
-        long cpu = (long)arg;
+        struct vm_area_struct *vma = get_gate_vma(mm);
+        if (!vma)
+                return 0;
-        if (action == CPU_ONLINE || action == CPU_ONLINE_FROZEN)
+        return (addr >= vma->vm_start) && (addr < vma->vm_end);
-                smp_call_function_single(cpu, cpu_vsyscall_init, NULL, 1);
+}
-        return NOTIFY_DONE;
+/*
+ * Use this when you have no reliable mm, typically from interrupt
+ * context. It is less reliable than using a task's mm and may give
+ * false positives.
+ */
+int in_gate_area_no_mm(unsigned long addr)
+{
+        return vsyscall_mode != NONE && (addr & PAGE_MASK) == VSYSCALL_ADDR;
 }
 void __init map_vsyscall(void)
@@ -331,24 +324,12 @@ void __init map_vsyscall(void)
        extern char __vsyscall_page;
        unsigned long physaddr_vsyscall = __pa_symbol(&__vsyscall_page);
-        __set_fixmap(VSYSCALL_PAGE, physaddr_vsyscall,
+        if (vsyscall_mode != NONE)
-                     vsyscall_mode == NATIVE
+                __set_fixmap(VSYSCALL_PAGE, physaddr_vsyscall,
-                     ? PAGE_KERNEL_VSYSCALL
+                             vsyscall_mode == NATIVE
-                     : PAGE_KERNEL_VVAR);
+                             ? PAGE_KERNEL_VSYSCALL
+                             : PAGE_KERNEL_VVAR);
        BUILD_BUG_ON((unsigned long)__fix_to_virt(VSYSCALL_PAGE) !=
                     (unsigned long)VSYSCALL_ADDR);
 }
-static int __init vsyscall_init(void)
-{
-        cpu_notifier_register_begin();
-        on_each_cpu(cpu_vsyscall_init, NULL, 1);
-        /* notifier priority > KVM */
-        __hotcpu_notifier(cpu_vsyscall_notifier, 30);
-        cpu_notifier_register_done();
-        return 0;
-}
-__initcall(vsyscall_init);
diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c
index e48b674639cc..234b0722de53 100644
--- a/arch/x86/kernel/x86_init.c
+++ b/arch/x86/kernel/x86_init.c
@@ -116,8 +116,6 @@ struct x86_msi_ops x86_msi = {
        .teardown_msi_irqs      = default_teardown_msi_irqs,
        .restore_msi_irqs       = default_restore_msi_irqs,
        .setup_hpet_msi         = default_setup_hpet_msi,
-        .msi_mask_irq           = default_msi_mask_irq,
-        .msix_mask_irq          = default_msix_mask_irq,
 };
 /* MSI arch specific hooks */
@@ -140,14 +138,6 @@ void arch_restore_msi_irqs(struct pci_dev *dev)
 {
        x86_msi.restore_msi_irqs(dev);
 }
-u32 arch_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
-{
-        return x86_msi.msi_mask_irq(desc, mask, flag);
-}
-u32 arch_msix_mask_irq(struct msi_desc *desc, u32 flag)
-{
-        return x86_msi.msix_mask_irq(desc, flag);
-}
 #endif
 struct x86_io_apic_ops x86_io_apic_ops = {
diff --git a/arch/x86/kvm/mmutrace.h b/arch/x86/kvm/mmutrace.h
index 5aaf35641768..ce463a9cc8fb 100644
--- a/arch/x86/kvm/mmutrace.h
+++ b/arch/x86/kvm/mmutrace.h
@@ -22,7 +22,7 @@
        __entry->unsync = sp->unsync;
 #define KVM_MMU_PAGE_PRINTK() ({                                        \
-        const u32 saved_len = p->len;                                   \
+        const char *saved_ptr = trace_seq_buffer_ptr(p);                \
        static const char *access_str[] = {                             \
                "---", "--x", "w--", "w-x", "-u-", "-ux", "wu-", "wux"  \
        };                                                              \
@@ -41,7 +41,7 @@
                         role.nxe ? "" : "!",                           \
                         __entry->root_count,                           \
                         __entry->unsync ? "unsync" : "sync", 0);       \
-        p->buffer + saved_len;                                          \
+        saved_ptr;                                                      \
                })
 #define kvm_mmu_trace_pferr_flags       \
diff --git a/arch/x86/lib/insn.c b/arch/x86/lib/insn.c
index 54fcffed28ed..2480978b31cc 100644
--- a/arch/x86/lib/insn.c
+++ b/arch/x86/lib/insn.c
@@ -28,7 +28,7 @@
 /* Verify next sizeof(t) bytes can be on the same instruction */
 #define validate_next(t, insn, n)       \
-        ((insn)->next_byte + sizeof(t) + n - (insn)->kaddr <= MAX_INSN_SIZE)
+        ((insn)->next_byte + sizeof(t) + n < (insn)->end_kaddr)
 #define __get_next(t, insn)     \
        ({ t r = *(t*)insn->next_byte; insn->next_byte += sizeof(t); r; })
@@ -50,10 +50,11 @@
 * @kaddr:      address (in kernel memory) of instruction (or copy thereof)
 * @x86_64:     !0 for 64-bit kernel or 64-bit app
 */
-void insn_init(struct insn *insn, const void *kaddr, int x86_64)
+void insn_init(struct insn *insn, const void *kaddr, int buf_len, int x86_64)
 {
        memset(insn, 0, sizeof(*insn));
        insn->kaddr = kaddr;
+        insn->end_kaddr = kaddr + buf_len;
        insn->next_byte = kaddr;
        insn->x86_64 = x86_64 ? 1 : 0;
        insn->opnd_bytes = 4;
diff --git a/arch/x86/mm/Makefile b/arch/x86/mm/Makefile
index 6a19ad9f370d..ecfdc46a024a 100644
--- a/arch/x86/mm/Makefile
+++ b/arch/x86/mm/Makefile
@@ -30,3 +30,5 @@ obj-$(CONFIG_ACPI_NUMA)		+= srat.o
 obj-$(CONFIG_NUMA_EMU)          += numa_emulation.o
 obj-$(CONFIG_MEMTEST)           += memtest.o
+obj-$(CONFIG_X86_INTEL_MPX)     += mpx.o
diff --git a/arch/x86/mm/dump_pagetables.c b/arch/x86/mm/dump_pagetables.c
index 95a427e57887..f0cedf3395af 100644
--- a/arch/x86/mm/dump_pagetables.c
+++ b/arch/x86/mm/dump_pagetables.c
@@ -76,6 +76,9 @@ static struct addr_marker address_markers[] = {
 # ifdef CONFIG_X86_ESPFIX64
        { ESPFIX_BASE_ADDR,     "ESPfix Area", 16 },
 # endif
+# ifdef CONFIG_EFI
+        { EFI_VA_END,           "EFI Runtime Services" },
+# endif
        { __START_KERNEL_map,   "High Kernel Mapping" },
        { MODULES_VADDR,        "Modules" },
        { MODULES_END,          "End Modules" },
@@ -126,7 +129,7 @@ static void printk_prot(struct seq_file *m, pgprot_t prot, int level, bool dmsg)
        if (!pgprot_val(prot)) {
                /* Not present */
-                pt_dump_cont_printf(m, dmsg, "                          ");
+                pt_dump_cont_printf(m, dmsg, "                              ");
        } else {
                if (pr & _PAGE_USER)
                        pt_dump_cont_printf(m, dmsg, "USR ");
@@ -145,18 +148,16 @@ static void printk_prot(struct seq_file *m, pgprot_t prot, int level, bool dmsg)
                else
                        pt_dump_cont_printf(m, dmsg, "    ");
-                /* Bit 9 has a different meaning on level 3 vs 4 */
+                /* Bit 7 has a different meaning on level 3 vs 4 */
-                if (level <= 3) {
+                if (level <= 3 && pr & _PAGE_PSE)
-                        if (pr & _PAGE_PSE)
+                        pt_dump_cont_printf(m, dmsg, "PSE ");
-                                pt_dump_cont_printf(m, dmsg, "PSE ");
+                else
-                        else
+                        pt_dump_cont_printf(m, dmsg, "    ");
-                                pt_dump_cont_printf(m, dmsg, "    ");
+                if ((level == 4 && pr & _PAGE_PAT) ||
-                } else {
+                    ((level == 3 || level == 2) && pr & _PAGE_PAT_LARGE))
-                        if (pr & _PAGE_PAT)
+                        pt_dump_cont_printf(m, dmsg, "pat ");
-                                pt_dump_cont_printf(m, dmsg, "pat ");
+                else
-                        else
+                        pt_dump_cont_printf(m, dmsg, "    ");
-                                pt_dump_cont_printf(m, dmsg, "    ");
-                }
                if (pr & _PAGE_GLOBAL)
                        pt_dump_cont_printf(m, dmsg, "GLB ");
                else
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index 66dba36f2343..82b41d56bb98 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -27,6 +27,35 @@
 #include "mm_internal.h"
+/*
+ * Tables translating between page_cache_type_t and pte encoding.
+ * Minimal supported modes are defined statically, modified if more supported
+ * cache modes are available.
+ * Index into __cachemode2pte_tbl is the cachemode.
+ * Index into __pte2cachemode_tbl are the caching attribute bits of the pte
+ * (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT) at index bit positions 0, 1, 2.
+ */
+uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {
+        [_PAGE_CACHE_MODE_WB]           = 0,
+        [_PAGE_CACHE_MODE_WC]           = _PAGE_PWT,
+        [_PAGE_CACHE_MODE_UC_MINUS]     = _PAGE_PCD,
+        [_PAGE_CACHE_MODE_UC]           = _PAGE_PCD | _PAGE_PWT,
+        [_PAGE_CACHE_MODE_WT]           = _PAGE_PCD,
+        [_PAGE_CACHE_MODE_WP]           = _PAGE_PCD,
+};
+EXPORT_SYMBOL_GPL(__cachemode2pte_tbl);
+uint8_t __pte2cachemode_tbl[8] = {
+        [__pte2cm_idx(0)] = _PAGE_CACHE_MODE_WB,
+        [__pte2cm_idx(_PAGE_PWT)] = _PAGE_CACHE_MODE_WC,
+        [__pte2cm_idx(_PAGE_PCD)] = _PAGE_CACHE_MODE_UC_MINUS,
+        [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD)] = _PAGE_CACHE_MODE_UC,
+        [__pte2cm_idx(_PAGE_PAT)] = _PAGE_CACHE_MODE_WB,
+        [__pte2cm_idx(_PAGE_PWT | _PAGE_PAT)] = _PAGE_CACHE_MODE_WC,
+        [__pte2cm_idx(_PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,
+        [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC,
+};
+EXPORT_SYMBOL_GPL(__pte2cachemode_tbl);
 static unsigned long __initdata pgt_buf_start;
 static unsigned long __initdata pgt_buf_end;
 static unsigned long __initdata pgt_buf_top;
@@ -687,3 +716,11 @@ void __init zone_sizes_init(void)
        free_area_init_nodes(max_zone_pfns);
 }
+void update_cache_mode_entry(unsigned entry, enum page_cache_mode cache)
+{
+        /* entry 0 MUST be WB (hardwired to speed up translations) */
+        BUG_ON(!entry && cache != _PAGE_CACHE_MODE_WB);
+        __cachemode2pte_tbl[cache] = __cm_idx2pte(entry);
+        __pte2cachemode_tbl[entry] = cache;
+}
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index 4e5dfec750fc..30eb05ae7061 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -52,7 +52,6 @@
 #include <asm/numa.h>
 #include <asm/cacheflush.h>
 #include <asm/init.h>
-#include <asm/uv/uv.h>
 #include <asm/setup.h>
 #include "mm_internal.h"
@@ -338,12 +337,15 @@ pte_t * __init populate_extra_pte(unsigned long vaddr)
 * Create large page table mappings for a range of physical addresses.
 */
 static void __init __init_extra_mapping(unsigned long phys, unsigned long size,
-                                                pgprot_t prot)
+                                        enum page_cache_mode cache)
 {
        pgd_t *pgd;
        pud_t *pud;
        pmd_t *pmd;
+        pgprot_t prot;
+        pgprot_val(prot) = pgprot_val(PAGE_KERNEL_LARGE) |
+                pgprot_val(pgprot_4k_2_large(cachemode2pgprot(cache)));
        BUG_ON((phys & ~PMD_MASK) || (size & ~PMD_MASK));
        for (; size; phys += PMD_SIZE, size -= PMD_SIZE) {
                pgd = pgd_offset_k((unsigned long)__va(phys));
@@ -366,12 +368,12 @@ static void __init __init_extra_mapping(unsigned long phys, unsigned long size,
 void __init init_extra_mapping_wb(unsigned long phys, unsigned long size)
 {
-        __init_extra_mapping(phys, size, PAGE_KERNEL_LARGE);
+        __init_extra_mapping(phys, size, _PAGE_CACHE_MODE_WB);
 }
 void __init init_extra_mapping_uc(unsigned long phys, unsigned long size)
 {
-        __init_extra_mapping(phys, size, PAGE_KERNEL_LARGE_NOCACHE);
+        __init_extra_mapping(phys, size, _PAGE_CACHE_MODE_UC);
 }
 /*
@@ -1202,66 +1204,15 @@ int kern_addr_valid(unsigned long addr)
        return pfn_valid(pte_pfn(*pte));
 }
-/*
- * A pseudo VMA to allow ptrace access for the vsyscall page.  This only
- * covers the 64bit vsyscall page now. 32bit has a real VMA now and does
- * not need special handling anymore:
- */
-static const char *gate_vma_name(struct vm_area_struct *vma)
-{
-        return "[vsyscall]";
-}
-static struct vm_operations_struct gate_vma_ops = {
-        .name = gate_vma_name,
-};
-static struct vm_area_struct gate_vma = {
-        .vm_start       = VSYSCALL_ADDR,
-        .vm_end         = VSYSCALL_ADDR + PAGE_SIZE,
-        .vm_page_prot   = PAGE_READONLY_EXEC,
-        .vm_flags       = VM_READ | VM_EXEC,
-        .vm_ops         = &gate_vma_ops,
-};
-struct vm_area_struct *get_gate_vma(struct mm_struct *mm)
-{
-#ifdef CONFIG_IA32_EMULATION
-        if (!mm || mm->context.ia32_compat)
-                return NULL;
-#endif
-        return &gate_vma;
-}
-int in_gate_area(struct mm_struct *mm, unsigned long addr)
-{
-        struct vm_area_struct *vma = get_gate_vma(mm);
-        if (!vma)
-                return 0;
-        return (addr >= vma->vm_start) && (addr < vma->vm_end);
-}
-/*
- * Use this when you have no reliable mm, typically from interrupt
- * context. It is less reliable than using a task's mm and may give
- * false positives.
- */
-int in_gate_area_no_mm(unsigned long addr)
-{
-        return (addr & PAGE_MASK) == VSYSCALL_ADDR;
-}
 static unsigned long probe_memory_block_size(void)
 {
        /* start from 2g */
        unsigned long bz = 1UL<<31;
-#ifdef CONFIG_X86_UV
+        if (totalram_pages >= (64ULL << (30 - PAGE_SHIFT))) {
-        if (is_uv_system()) {
+                pr_info("Using 2GB memory block size for large-memory system\n");
-                printk(KERN_INFO "UV: memory block size 2GB\n");
                return 2UL * 1024 * 1024 * 1024;
        }
-#endif
        /* less than 64g installed */
        if ((max_pfn << PAGE_SHIFT) < (16UL << 32))
diff --git a/arch/x86/mm/iomap_32.c b/arch/x86/mm/iomap_32.c
index 7b179b499fa3..9ca35fc60cfe 100644
--- a/arch/x86/mm/iomap_32.c
+++ b/arch/x86/mm/iomap_32.c
@@ -33,17 +33,17 @@ static int is_io_mapping_possible(resource_size_t base, unsigned long size)
 int iomap_create_wc(resource_size_t base, unsigned long size, pgprot_t *prot)
 {
-        unsigned long flag = _PAGE_CACHE_WC;
+        enum page_cache_mode pcm = _PAGE_CACHE_MODE_WC;
        int ret;
        if (!is_io_mapping_possible(base, size))
                return -EINVAL;
-        ret = io_reserve_memtype(base, base + size, &flag);
+        ret = io_reserve_memtype(base, base + size, &pcm);
        if (ret)
                return ret;
-        *prot = __pgprot(__PAGE_KERNEL | flag);
+        *prot = __pgprot(__PAGE_KERNEL | cachemode2protval(pcm));
        return 0;
 }
 EXPORT_SYMBOL_GPL(iomap_create_wc);
@@ -82,8 +82,10 @@ iomap_atomic_prot_pfn(unsigned long pfn, pgprot_t prot)
         * MTRR is UC or WC.  UC_MINUS gets the real intention, of the
         * user, which is "WC if the MTRR is WC, UC if you can't do that."
         */
-        if (!pat_enabled && pgprot_val(prot) == pgprot_val(PAGE_KERNEL_WC))
+        if (!pat_enabled && pgprot_val(prot) ==
-                prot = PAGE_KERNEL_UC_MINUS;
+            (__PAGE_KERNEL | cachemode2protval(_PAGE_CACHE_MODE_WC)))
+                prot = __pgprot(__PAGE_KERNEL |
+                                cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS));
        return (void __force __iomem *) kmap_atomic_prot_pfn(pfn, prot);
 }
diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c
index af78e50ca6ce..fdf617c00e2f 100644
--- a/arch/x86/mm/ioremap.c
+++ b/arch/x86/mm/ioremap.c
@@ -29,20 +29,20 @@
 * conflicts.
 */
 int ioremap_change_attr(unsigned long vaddr, unsigned long size,
-                               unsigned long prot_val)
+                        enum page_cache_mode pcm)
 {
        unsigned long nrpages = size >> PAGE_SHIFT;
        int err;
-        switch (prot_val) {
+        switch (pcm) {
-        case _PAGE_CACHE_UC:
+        case _PAGE_CACHE_MODE_UC:
        default:
                err = _set_memory_uc(vaddr, nrpages);
                break;
-        case _PAGE_CACHE_WC:
+        case _PAGE_CACHE_MODE_WC:
                err = _set_memory_wc(vaddr, nrpages);
                break;
-        case _PAGE_CACHE_WB:
+        case _PAGE_CACHE_MODE_WB:
                err = _set_memory_wb(vaddr, nrpages);
                break;
        }
@@ -75,14 +75,14 @@ static int __ioremap_check_ram(unsigned long start_pfn, unsigned long nr_pages,
 * caller shouldn't need to know that small detail.
 */
 static void __iomem *__ioremap_caller(resource_size_t phys_addr,
-                unsigned long size, unsigned long prot_val, void *caller)
+                unsigned long size, enum page_cache_mode pcm, void *caller)
 {
        unsigned long offset, vaddr;
        resource_size_t pfn, last_pfn, last_addr;
        const resource_size_t unaligned_phys_addr = phys_addr;
        const unsigned long unaligned_size = size;
        struct vm_struct *area;
-        unsigned long new_prot_val;
+        enum page_cache_mode new_pcm;
        pgprot_t prot;
        int retval;
        void __iomem *ret_addr;
@@ -134,38 +134,40 @@ static void __iomem *__ioremap_caller(resource_size_t phys_addr,
        size = PAGE_ALIGN(last_addr+1) - phys_addr;
        retval = reserve_memtype(phys_addr, (u64)phys_addr + size,
-                                                prot_val, &new_prot_val);
+                                                pcm, &new_pcm);
        if (retval) {
                printk(KERN_ERR "ioremap reserve_memtype failed %d\n", retval);
                return NULL;
        }
-        if (prot_val != new_prot_val) {
+        if (pcm != new_pcm) {
-                if (!is_new_memtype_allowed(phys_addr, size,
+                if (!is_new_memtype_allowed(phys_addr, size, pcm, new_pcm)) {
-                                            prot_val, new_prot_val)) {
                        printk(KERN_ERR
-                "ioremap error for 0x%llx-0x%llx, requested 0x%lx, got 0x%lx\n",
+                "ioremap error for 0x%llx-0x%llx, requested 0x%x, got 0x%x\n",
                                (unsigned long long)phys_addr,
                                (unsigned long long)(phys_addr + size),
-                                prot_val, new_prot_val);
+                                pcm, new_pcm);
                        goto err_free_memtype;
                }
-                prot_val = new_prot_val;
+                pcm = new_pcm;
        }
-        switch (prot_val) {
+        prot = PAGE_KERNEL_IO;
-        case _PAGE_CACHE_UC:
+        switch (pcm) {
+        case _PAGE_CACHE_MODE_UC:
        default:
-                prot = PAGE_KERNEL_IO_NOCACHE;
+                prot = __pgprot(pgprot_val(prot) |
+                                cachemode2protval(_PAGE_CACHE_MODE_UC));
                break;
-        case _PAGE_CACHE_UC_MINUS:
+        case _PAGE_CACHE_MODE_UC_MINUS:
-                prot = PAGE_KERNEL_IO_UC_MINUS;
+                prot = __pgprot(pgprot_val(prot) |
+                                cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS));
                break;
-        case _PAGE_CACHE_WC:
+        case _PAGE_CACHE_MODE_WC:
-                prot = PAGE_KERNEL_IO_WC;
+                prot = __pgprot(pgprot_val(prot) |
+                                cachemode2protval(_PAGE_CACHE_MODE_WC));
                break;
-        case _PAGE_CACHE_WB:
+        case _PAGE_CACHE_MODE_WB:
-                prot = PAGE_KERNEL_IO;
                break;
        }
@@ -178,7 +180,7 @@ static void __iomem *__ioremap_caller(resource_size_t phys_addr,
        area->phys_addr = phys_addr;
        vaddr = (unsigned long) area->addr;
-        if (kernel_map_sync_memtype(phys_addr, size, prot_val))
+        if (kernel_map_sync_memtype(phys_addr, size, pcm))
                goto err_free_area;
        if (ioremap_page_range(vaddr, vaddr + size, phys_addr, prot))
@@ -227,14 +229,14 @@ void __iomem *ioremap_nocache(resource_size_t phys_addr, unsigned long size)
 {
        /*
         * Ideally, this should be:
-         *      pat_enabled ? _PAGE_CACHE_UC : _PAGE_CACHE_UC_MINUS;
+         *      pat_enabled ? _PAGE_CACHE_MODE_UC : _PAGE_CACHE_MODE_UC_MINUS;
         *
         * Till we fix all X drivers to use ioremap_wc(), we will use
         * UC MINUS.
         */
-        unsigned long val = _PAGE_CACHE_UC_MINUS;
+        enum page_cache_mode pcm = _PAGE_CACHE_MODE_UC_MINUS;
-        return __ioremap_caller(phys_addr, size, val,
+        return __ioremap_caller(phys_addr, size, pcm,
                                __builtin_return_address(0));
 }
 EXPORT_SYMBOL(ioremap_nocache);
@@ -252,7 +254,7 @@ EXPORT_SYMBOL(ioremap_nocache);
 void __iomem *ioremap_wc(resource_size_t phys_addr, unsigned long size)
 {
        if (pat_enabled)
-                return __ioremap_caller(phys_addr, size, _PAGE_CACHE_WC,
+                return __ioremap_caller(phys_addr, size, _PAGE_CACHE_MODE_WC,
                                        __builtin_return_address(0));
        else
                return ioremap_nocache(phys_addr, size);
@@ -261,7 +263,7 @@ EXPORT_SYMBOL(ioremap_wc);
 void __iomem *ioremap_cache(resource_size_t phys_addr, unsigned long size)
 {
-        return __ioremap_caller(phys_addr, size, _PAGE_CACHE_WB,
+        return __ioremap_caller(phys_addr, size, _PAGE_CACHE_MODE_WB,
                                __builtin_return_address(0));
 }
 EXPORT_SYMBOL(ioremap_cache);
@@ -269,7 +271,8 @@ EXPORT_SYMBOL(ioremap_cache);
 void __iomem *ioremap_prot(resource_size_t phys_addr, unsigned long size,
                                unsigned long prot_val)
 {
-        return __ioremap_caller(phys_addr, size, (prot_val & _PAGE_CACHE_MASK),
+        return __ioremap_caller(phys_addr, size,
+                                pgprot2cachemode(__pgprot(prot_val)),
                                __builtin_return_address(0));
 }
 EXPORT_SYMBOL(ioremap_prot);
@@ -327,7 +330,7 @@ EXPORT_SYMBOL(iounmap);
 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 * access
 */
-void *xlate_dev_mem_ptr(unsigned long phys)
+void *xlate_dev_mem_ptr(phys_addr_t phys)
 {
        void *addr;
        unsigned long start = phys & PAGE_MASK;
@@ -343,7 +346,7 @@ void *xlate_dev_mem_ptr(unsigned long phys)
        return addr;
 }
-void unxlate_dev_mem_ptr(unsigned long phys, void *addr)
+void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr)
 {
        if (page_is_ram(phys >> PAGE_SHIFT))
                return;
diff --git a/arch/x86/mm/mm_internal.h b/arch/x86/mm/mm_internal.h
index 6b563a118891..62474ba66c8e 100644
--- a/arch/x86/mm/mm_internal.h
+++ b/arch/x86/mm/mm_internal.h
@@ -16,4 +16,6 @@ void zone_sizes_init(void);
 extern int after_bootmem;
+void update_cache_mode_entry(unsigned entry, enum page_cache_mode cache);
 #endif  /* __X86_MM_INTERNAL_H */
diff --git a/arch/x86/mm/mpx.c b/arch/x86/mm/mpx.c
new file mode 100644
index 000000000000..67ebf5751222
--- /dev/null
+++ b/arch/x86/mm/mpx.c
@@ -0,0 +1,928 @@
+/*
+ * mpx.c - Memory Protection eXtensions
+ *
+ * Copyright (c) 2014, Intel Corporation.
+ * Qiaowei Ren <qiaowei.ren@intel.com>
+ * Dave Hansen <dave.hansen@intel.com>
+ */
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/syscalls.h>
+#include <linux/sched/sysctl.h>
+#include <asm/i387.h>
+#include <asm/insn.h>
+#include <asm/mman.h>
+#include <asm/mmu_context.h>
+#include <asm/mpx.h>
+#include <asm/processor.h>
+#include <asm/fpu-internal.h>
+static const char *mpx_mapping_name(struct vm_area_struct *vma)
+{
+        return "[mpx]";
+}
+static struct vm_operations_struct mpx_vma_ops = {
+        .name = mpx_mapping_name,
+};
+static int is_mpx_vma(struct vm_area_struct *vma)
+{
+        return (vma->vm_ops == &mpx_vma_ops);
+}
+/*
+ * This is really a simplified "vm_mmap". it only handles MPX
+ * bounds tables (the bounds directory is user-allocated).
+ *
+ * Later on, we use the vma->vm_ops to uniquely identify these
+ * VMAs.
+ */
+static unsigned long mpx_mmap(unsigned long len)
+{
+        unsigned long ret;
+        unsigned long addr, pgoff;
+        struct mm_struct *mm = current->mm;
+        vm_flags_t vm_flags;
+        struct vm_area_struct *vma;
+        /* Only bounds table and bounds directory can be allocated here */
+        if (len != MPX_BD_SIZE_BYTES && len != MPX_BT_SIZE_BYTES)
+                return -EINVAL;
+        down_write(&mm->mmap_sem);
+        /* Too many mappings? */
+        if (mm->map_count > sysctl_max_map_count) {
+                ret = -ENOMEM;
+                goto out;
+        }
+        /* Obtain the address to map to. we verify (or select) it and ensure
+         * that it represents a valid section of the address space.
+         */
+        addr = get_unmapped_area(NULL, 0, len, 0, MAP_ANONYMOUS | MAP_PRIVATE);
+        if (addr & ~PAGE_MASK) {
+                ret = addr;
+                goto out;
+        }
+        vm_flags = VM_READ | VM_WRITE | VM_MPX |
+                        mm->def_flags | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC;
+        /* Set pgoff according to addr for anon_vma */
+        pgoff = addr >> PAGE_SHIFT;
+        ret = mmap_region(NULL, addr, len, vm_flags, pgoff);
+        if (IS_ERR_VALUE(ret))
+                goto out;
+        vma = find_vma(mm, ret);
+        if (!vma) {
+                ret = -ENOMEM;
+                goto out;
+        }
+        vma->vm_ops = &mpx_vma_ops;
+        if (vm_flags & VM_LOCKED) {
+                up_write(&mm->mmap_sem);
+                mm_populate(ret, len);
+                return ret;
+        }
+out:
+        up_write(&mm->mmap_sem);
+        return ret;
+}
+enum reg_type {
+        REG_TYPE_RM = 0,
+        REG_TYPE_INDEX,
+        REG_TYPE_BASE,
+};
+static int get_reg_offset(struct insn *insn, struct pt_regs *regs,
+                          enum reg_type type)
+{
+        int regno = 0;
+        static const int regoff[] = {
+                offsetof(struct pt_regs, ax),
+                offsetof(struct pt_regs, cx),
+                offsetof(struct pt_regs, dx),
+                offsetof(struct pt_regs, bx),
+                offsetof(struct pt_regs, sp),
+                offsetof(struct pt_regs, bp),
+                offsetof(struct pt_regs, si),
+                offsetof(struct pt_regs, di),
+#ifdef CONFIG_X86_64
+                offsetof(struct pt_regs, r8),
+                offsetof(struct pt_regs, r9),
+                offsetof(struct pt_regs, r10),
+                offsetof(struct pt_regs, r11),
+                offsetof(struct pt_regs, r12),
+                offsetof(struct pt_regs, r13),
+                offsetof(struct pt_regs, r14),
+                offsetof(struct pt_regs, r15),
+#endif
+        };
+        int nr_registers = ARRAY_SIZE(regoff);
+        /*
+         * Don't possibly decode a 32-bit instructions as
+         * reading a 64-bit-only register.
+         */
+        if (IS_ENABLED(CONFIG_X86_64) && !insn->x86_64)
+                nr_registers -= 8;
+        switch (type) {
+        case REG_TYPE_RM:
+                regno = X86_MODRM_RM(insn->modrm.value);
+                if (X86_REX_B(insn->rex_prefix.value) == 1)
+                        regno += 8;
+                break;
+        case REG_TYPE_INDEX:
+                regno = X86_SIB_INDEX(insn->sib.value);
+                if (X86_REX_X(insn->rex_prefix.value) == 1)
+                        regno += 8;
+                break;
+        case REG_TYPE_BASE:
+                regno = X86_SIB_BASE(insn->sib.value);
+                if (X86_REX_B(insn->rex_prefix.value) == 1)
+                        regno += 8;
+                break;
+        default:
+                pr_err("invalid register type");
+                BUG();
+                break;
+        }
+        if (regno > nr_registers) {
+                WARN_ONCE(1, "decoded an instruction with an invalid register");
+                return -EINVAL;
+        }
+        return regoff[regno];
+}
+/*
+ * return the address being referenced be instruction
+ * for rm=3 returning the content of the rm reg
+ * for rm!=3 calculates the address using SIB and Disp
+ */
+static void __user *mpx_get_addr_ref(struct insn *insn, struct pt_regs *regs)
+{
+        unsigned long addr, base, indx;
+        int addr_offset, base_offset, indx_offset;
+        insn_byte_t sib;
+        insn_get_modrm(insn);
+        insn_get_sib(insn);
+        sib = insn->sib.value;
+        if (X86_MODRM_MOD(insn->modrm.value) == 3) {
+                addr_offset = get_reg_offset(insn, regs, REG_TYPE_RM);
+                if (addr_offset < 0)
+                        goto out_err;
+                addr = regs_get_register(regs, addr_offset);
+        } else {
+                if (insn->sib.nbytes) {
+                        base_offset = get_reg_offset(insn, regs, REG_TYPE_BASE);
+                        if (base_offset < 0)
+                                goto out_err;
+                        indx_offset = get_reg_offset(insn, regs, REG_TYPE_INDEX);
+                        if (indx_offset < 0)
+                                goto out_err;
+                        base = regs_get_register(regs, base_offset);
+                        indx = regs_get_register(regs, indx_offset);
+                        addr = base + indx * (1 << X86_SIB_SCALE(sib));
+                } else {
+                        addr_offset = get_reg_offset(insn, regs, REG_TYPE_RM);
+                        if (addr_offset < 0)
+                                goto out_err;
+                        addr = regs_get_register(regs, addr_offset);
+                }
+                addr += insn->displacement.value;
+        }
+        return (void __user *)addr;
+out_err:
+        return (void __user *)-1;
+}
+static int mpx_insn_decode(struct insn *insn,
+                           struct pt_regs *regs)
+{
+        unsigned char buf[MAX_INSN_SIZE];
+        int x86_64 = !test_thread_flag(TIF_IA32);
+        int not_copied;
+        int nr_copied;
+        not_copied = copy_from_user(buf, (void __user *)regs->ip, sizeof(buf));
+        nr_copied = sizeof(buf) - not_copied;
+        /*
+         * The decoder _should_ fail nicely if we pass it a short buffer.
+         * But, let's not depend on that implementation detail.  If we
+         * did not get anything, just error out now.
+         */
+        if (!nr_copied)
+                return -EFAULT;
+        insn_init(insn, buf, nr_copied, x86_64);
+        insn_get_length(insn);
+        /*
+         * copy_from_user() tries to get as many bytes as we could see in
+         * the largest possible instruction.  If the instruction we are
+         * after is shorter than that _and_ we attempt to copy from
+         * something unreadable, we might get a short read.  This is OK
+         * as long as the read did not stop in the middle of the
+         * instruction.  Check to see if we got a partial instruction.
+         */
+        if (nr_copied < insn->length)
+                return -EFAULT;
+        insn_get_opcode(insn);
+        /*
+         * We only _really_ need to decode bndcl/bndcn/bndcu
+         * Error out on anything else.
+         */
+        if (insn->opcode.bytes[0] != 0x0f)
+                goto bad_opcode;
+        if ((insn->opcode.bytes[1] != 0x1a) &&
+            (insn->opcode.bytes[1] != 0x1b))
+                goto bad_opcode;
+        return 0;
+bad_opcode:
+        return -EINVAL;
+}
+/*
+ * If a bounds overflow occurs then a #BR is generated. This
+ * function decodes MPX instructions to get violation address
+ * and set this address into extended struct siginfo.
+ *
+ * Note that this is not a super precise way of doing this.
+ * Userspace could have, by the time we get here, written
+ * anything it wants in to the instructions.  We can not
+ * trust anything about it.  They might not be valid
+ * instructions or might encode invalid registers, etc...
+ *
+ * The caller is expected to kfree() the returned siginfo_t.
+ */
+siginfo_t *mpx_generate_siginfo(struct pt_regs *regs,
+                                struct xsave_struct *xsave_buf)
+{
+        struct bndreg *bndregs, *bndreg;
+        siginfo_t *info = NULL;
+        struct insn insn;
+        uint8_t bndregno;
+        int err;
+        err = mpx_insn_decode(&insn, regs);
+        if (err)
+                goto err_out;
+        /*
+         * We know at this point that we are only dealing with
+         * MPX instructions.
+         */
+        insn_get_modrm(&insn);
+        bndregno = X86_MODRM_REG(insn.modrm.value);
+        if (bndregno > 3) {
+                err = -EINVAL;
+                goto err_out;
+        }
+        /* get the bndregs _area_ of the xsave structure */
+        bndregs = get_xsave_addr(xsave_buf, XSTATE_BNDREGS);
+        if (!bndregs) {
+                err = -EINVAL;
+                goto err_out;
+        }
+        /* now go select the individual register in the set of 4 */
+        bndreg = &bndregs[bndregno];
+        info = kzalloc(sizeof(*info), GFP_KERNEL);
+        if (!info) {
+                err = -ENOMEM;
+                goto err_out;
+        }
+        /*
+         * The registers are always 64-bit, but the upper 32
+         * bits are ignored in 32-bit mode.  Also, note that the
+         * upper bounds are architecturally represented in 1's
+         * complement form.
+         *
+         * The 'unsigned long' cast is because the compiler
+         * complains when casting from integers to different-size
+         * pointers.
+         */
+        info->si_lower = (void __user *)(unsigned long)bndreg->lower_bound;
+        info->si_upper = (void __user *)(unsigned long)~bndreg->upper_bound;
+        info->si_addr_lsb = 0;
+        info->si_signo = SIGSEGV;
+        info->si_errno = 0;
+        info->si_code = SEGV_BNDERR;
+        info->si_addr = mpx_get_addr_ref(&insn, regs);
+        /*
+         * We were not able to extract an address from the instruction,
+         * probably because there was something invalid in it.
+         */
+        if (info->si_addr == (void *)-1) {
+                err = -EINVAL;
+                goto err_out;
+        }
+        return info;
+err_out:
+        /* info might be NULL, but kfree() handles that */
+        kfree(info);
+        return ERR_PTR(err);
+}
+static __user void *task_get_bounds_dir(struct task_struct *tsk)
+{
+        struct bndcsr *bndcsr;
+        if (!cpu_feature_enabled(X86_FEATURE_MPX))
+                return MPX_INVALID_BOUNDS_DIR;
+        /*
+         * The bounds directory pointer is stored in a register
+         * only accessible if we first do an xsave.
+         */
+        fpu_save_init(&tsk->thread.fpu);
+        bndcsr = get_xsave_addr(&tsk->thread.fpu.state->xsave, XSTATE_BNDCSR);
+        if (!bndcsr)
+                return MPX_INVALID_BOUNDS_DIR;
+        /*
+         * Make sure the register looks valid by checking the
+         * enable bit.
+         */
+        if (!(bndcsr->bndcfgu & MPX_BNDCFG_ENABLE_FLAG))
+                return MPX_INVALID_BOUNDS_DIR;
+        /*
+         * Lastly, mask off the low bits used for configuration
+         * flags, and return the address of the bounds table.
+         */
+        return (void __user *)(unsigned long)
+                (bndcsr->bndcfgu & MPX_BNDCFG_ADDR_MASK);
+}
+int mpx_enable_management(struct task_struct *tsk)
+{
+        void __user *bd_base = MPX_INVALID_BOUNDS_DIR;
+        struct mm_struct *mm = tsk->mm;
+        int ret = 0;
+        /*
+         * runtime in the userspace will be responsible for allocation of
+         * the bounds directory. Then, it will save the base of the bounds
+         * directory into XSAVE/XRSTOR Save Area and enable MPX through
+         * XRSTOR instruction.
+         *
+         * fpu_xsave() is expected to be very expensive. Storing the bounds
+         * directory here means that we do not have to do xsave in the unmap
+         * path; we can just use mm->bd_addr instead.
+         */
+        bd_base = task_get_bounds_dir(tsk);
+        down_write(&mm->mmap_sem);
+        mm->bd_addr = bd_base;
+        if (mm->bd_addr == MPX_INVALID_BOUNDS_DIR)
+                ret = -ENXIO;
+        up_write(&mm->mmap_sem);
+        return ret;
+}
+int mpx_disable_management(struct task_struct *tsk)
+{
+        struct mm_struct *mm = current->mm;
+        if (!cpu_feature_enabled(X86_FEATURE_MPX))
+                return -ENXIO;
+        down_write(&mm->mmap_sem);
+        mm->bd_addr = MPX_INVALID_BOUNDS_DIR;
+        up_write(&mm->mmap_sem);
+        return 0;
+}
+/*
+ * With 32-bit mode, MPX_BT_SIZE_BYTES is 4MB, and the size of each
+ * bounds table is 16KB. With 64-bit mode, MPX_BT_SIZE_BYTES is 2GB,
+ * and the size of each bounds table is 4MB.
+ */
+static int allocate_bt(long __user *bd_entry)
+{
+        unsigned long expected_old_val = 0;
+        unsigned long actual_old_val = 0;
+        unsigned long bt_addr;
+        int ret = 0;
+        /*
+         * Carve the virtual space out of userspace for the new
+         * bounds table:
+         */
+        bt_addr = mpx_mmap(MPX_BT_SIZE_BYTES);
+        if (IS_ERR((void *)bt_addr))
+                return PTR_ERR((void *)bt_addr);
+        /*
+         * Set the valid flag (kinda like _PAGE_PRESENT in a pte)
+         */
+        bt_addr = bt_addr | MPX_BD_ENTRY_VALID_FLAG;
+        /*
+         * Go poke the address of the new bounds table in to the
+         * bounds directory entry out in userspace memory.  Note:
+         * we may race with another CPU instantiating the same table.
+         * In that case the cmpxchg will see an unexpected
+         * 'actual_old_val'.
+         *
+         * This can fault, but that's OK because we do not hold
+         * mmap_sem at this point, unlike some of the other part
+         * of the MPX code that have to pagefault_disable().
+         */
+        ret = user_atomic_cmpxchg_inatomic(&actual_old_val, bd_entry,
+                                           expected_old_val, bt_addr);
+        if (ret)
+                goto out_unmap;
+        /*
+         * The user_atomic_cmpxchg_inatomic() will only return nonzero
+         * for faults, *not* if the cmpxchg itself fails.  Now we must
+         * verify that the cmpxchg itself completed successfully.
+         */
+        /*
+         * We expected an empty 'expected_old_val', but instead found
+         * an apparently valid entry.  Assume we raced with another
+         * thread to instantiate this table and desclare succecss.
+         */
+        if (actual_old_val & MPX_BD_ENTRY_VALID_FLAG) {
+                ret = 0;
+                goto out_unmap;
+        }
+        /*
+         * We found a non-empty bd_entry but it did not have the
+         * VALID_FLAG set.  Return an error which will result in
+         * a SEGV since this probably means that somebody scribbled
+         * some invalid data in to a bounds table.
+         */
+        if (expected_old_val != actual_old_val) {
+                ret = -EINVAL;
+                goto out_unmap;
+        }
+        return 0;
+out_unmap:
+        vm_munmap(bt_addr & MPX_BT_ADDR_MASK, MPX_BT_SIZE_BYTES);
+        return ret;
+}
+/*
+ * When a BNDSTX instruction attempts to save bounds to a bounds
+ * table, it will first attempt to look up the table in the
+ * first-level bounds directory.  If it does not find a table in
+ * the directory, a #BR is generated and we get here in order to
+ * allocate a new table.
+ *
+ * With 32-bit mode, the size of BD is 4MB, and the size of each
+ * bound table is 16KB. With 64-bit mode, the size of BD is 2GB,
+ * and the size of each bound table is 4MB.
+ */
+static int do_mpx_bt_fault(struct xsave_struct *xsave_buf)
+{
+        unsigned long bd_entry, bd_base;
+        struct bndcsr *bndcsr;
+        bndcsr = get_xsave_addr(xsave_buf, XSTATE_BNDCSR);
+        if (!bndcsr)
+                return -EINVAL;
+        /*
+         * Mask off the preserve and enable bits
+         */
+        bd_base = bndcsr->bndcfgu & MPX_BNDCFG_ADDR_MASK;
+        /*
+         * The hardware provides the address of the missing or invalid
+         * entry via BNDSTATUS, so we don't have to go look it up.
+         */
+        bd_entry = bndcsr->bndstatus & MPX_BNDSTA_ADDR_MASK;
+        /*
+         * Make sure the directory entry is within where we think
+         * the directory is.
+         */
+        if ((bd_entry < bd_base) ||
+            (bd_entry >= bd_base + MPX_BD_SIZE_BYTES))
+                return -EINVAL;
+        return allocate_bt((long __user *)bd_entry);
+}
+int mpx_handle_bd_fault(struct xsave_struct *xsave_buf)
+{
+        /*
+         * Userspace never asked us to manage the bounds tables,
+         * so refuse to help.
+         */
+        if (!kernel_managing_mpx_tables(current->mm))
+                return -EINVAL;
+        if (do_mpx_bt_fault(xsave_buf)) {
+                force_sig(SIGSEGV, current);
+                /*
+                 * The force_sig() is essentially "handling" this
+                 * exception, so we do not pass up the error
+                 * from do_mpx_bt_fault().
+                 */
+        }
+        return 0;
+}
+/*
+ * A thin wrapper around get_user_pages().  Returns 0 if the
+ * fault was resolved or -errno if not.
+ */
+static int mpx_resolve_fault(long __user *addr, int write)
+{
+        long gup_ret;
+        int nr_pages = 1;
+        int force = 0;
+        gup_ret = get_user_pages(current, current->mm, (unsigned long)addr,
+                                 nr_pages, write, force, NULL, NULL);
+        /*
+         * get_user_pages() returns number of pages gotten.
+         * 0 means we failed to fault in and get anything,
+         * probably because 'addr' is bad.
+         */
+        if (!gup_ret)
+                return -EFAULT;
+        /* Other error, return it */
+        if (gup_ret < 0)
+                return gup_ret;
+        /* must have gup'd a page and gup_ret>0, success */
+        return 0;
+}
+/*
+ * Get the base of bounds tables pointed by specific bounds
+ * directory entry.
+ */
+static int get_bt_addr(struct mm_struct *mm,
+                        long __user *bd_entry, unsigned long *bt_addr)
+{
+        int ret;
+        int valid_bit;
+        if (!access_ok(VERIFY_READ, (bd_entry), sizeof(*bd_entry)))
+                return -EFAULT;
+        while (1) {
+                int need_write = 0;
+                pagefault_disable();
+                ret = get_user(*bt_addr, bd_entry);
+                pagefault_enable();
+                if (!ret)
+                        break;
+                if (ret == -EFAULT)
+                        ret = mpx_resolve_fault(bd_entry, need_write);
+                /*
+                 * If we could not resolve the fault, consider it
+                 * userspace's fault and error out.
+                 */
+                if (ret)
+                        return ret;
+        }
+        valid_bit = *bt_addr & MPX_BD_ENTRY_VALID_FLAG;
+        *bt_addr &= MPX_BT_ADDR_MASK;
+        /*
+         * When the kernel is managing bounds tables, a bounds directory
+         * entry will either have a valid address (plus the valid bit)
+         * *OR* be completely empty. If we see a !valid entry *and* some
+         * data in the address field, we know something is wrong. This
+         * -EINVAL return will cause a SIGSEGV.
+         */
+        if (!valid_bit && *bt_addr)
+                return -EINVAL;
+        /*
+         * Do we have an completely zeroed bt entry?  That is OK.  It
+         * just means there was no bounds table for this memory.  Make
+         * sure to distinguish this from -EINVAL, which will cause
+         * a SEGV.
+         */
+        if (!valid_bit)
+                return -ENOENT;
+        return 0;
+}
+/*
+ * Free the backing physical pages of bounds table 'bt_addr'.
+ * Assume start...end is within that bounds table.
+ */
+static int zap_bt_entries(struct mm_struct *mm,
+                unsigned long bt_addr,
+                unsigned long start, unsigned long end)
+{
+        struct vm_area_struct *vma;
+        unsigned long addr, len;
+        /*
+         * Find the first overlapping vma. If vma->vm_start > start, there
+         * will be a hole in the bounds table. This -EINVAL return will
+         * cause a SIGSEGV.
+         */
+        vma = find_vma(mm, start);
+        if (!vma || vma->vm_start > start)
+                return -EINVAL;
+        /*
+         * A NUMA policy on a VM_MPX VMA could cause this bouds table to
+         * be split. So we need to look across the entire 'start -> end'
+         * range of this bounds table, find all of the VM_MPX VMAs, and
+         * zap only those.
+         */
+        addr = start;
+        while (vma && vma->vm_start < end) {
+                /*
+                 * We followed a bounds directory entry down
+                 * here.  If we find a non-MPX VMA, that's bad,
+                 * so stop immediately and return an error.  This
+                 * probably results in a SIGSEGV.
+                 */
+                if (!is_mpx_vma(vma))
+                        return -EINVAL;
+                len = min(vma->vm_end, end) - addr;
+                zap_page_range(vma, addr, len, NULL);
+                vma = vma->vm_next;
+                addr = vma->vm_start;
+        }
+        return 0;
+}
+static int unmap_single_bt(struct mm_struct *mm,
+                long __user *bd_entry, unsigned long bt_addr)
+{
+        unsigned long expected_old_val = bt_addr | MPX_BD_ENTRY_VALID_FLAG;
+        unsigned long actual_old_val = 0;
+        int ret;
+        while (1) {
+                int need_write = 1;
+                pagefault_disable();
+                ret = user_atomic_cmpxchg_inatomic(&actual_old_val, bd_entry,
+                                                   expected_old_val, 0);
+                pagefault_enable();
+                if (!ret)
+                        break;
+                if (ret == -EFAULT)
+                        ret = mpx_resolve_fault(bd_entry, need_write);
+                /*
+                 * If we could not resolve the fault, consider it
+                 * userspace's fault and error out.
+                 */
+                if (ret)
+                        return ret;
+        }
+        /*
+         * The cmpxchg was performed, check the results.
+         */
+        if (actual_old_val != expected_old_val) {
+                /*
+                 * Someone else raced with us to unmap the table.
+                 * There was no bounds table pointed to by the
+                 * directory, so declare success.  Somebody freed
+                 * it.
+                 */
+                if (!actual_old_val)
+                        return 0;
+                /*
+                 * Something messed with the bounds directory
+                 * entry.  We hold mmap_sem for read or write
+                 * here, so it could not be a _new_ bounds table
+                 * that someone just allocated.  Something is
+                 * wrong, so pass up the error and SIGSEGV.
+                 */
+                return -EINVAL;
+        }
+        /*
+         * Note, we are likely being called under do_munmap() already. To
+         * avoid recursion, do_munmap() will check whether it comes
+         * from one bounds table through VM_MPX flag.
+         */
+        return do_munmap(mm, bt_addr, MPX_BT_SIZE_BYTES);
+}
+/*
+ * If the bounds table pointed by bounds directory 'bd_entry' is
+ * not shared, unmap this whole bounds table. Otherwise, only free
+ * those backing physical pages of bounds table entries covered
+ * in this virtual address region start...end.
+ */
+static int unmap_shared_bt(struct mm_struct *mm,
+                long __user *bd_entry, unsigned long start,
+                unsigned long end, bool prev_shared, bool next_shared)
+{
+        unsigned long bt_addr;
+        int ret;
+        ret = get_bt_addr(mm, bd_entry, &bt_addr);
+        /*
+         * We could see an "error" ret for not-present bounds
+         * tables (not really an error), or actual errors, but
+         * stop unmapping either way.
+         */
+        if (ret)
+                return ret;
+        if (prev_shared && next_shared)
+                ret = zap_bt_entries(mm, bt_addr,
+                                bt_addr+MPX_GET_BT_ENTRY_OFFSET(start),
+                                bt_addr+MPX_GET_BT_ENTRY_OFFSET(end));
+        else if (prev_shared)
+                ret = zap_bt_entries(mm, bt_addr,
+                                bt_addr+MPX_GET_BT_ENTRY_OFFSET(start),
+                                bt_addr+MPX_BT_SIZE_BYTES);
+        else if (next_shared)
+                ret = zap_bt_entries(mm, bt_addr, bt_addr,
+                                bt_addr+MPX_GET_BT_ENTRY_OFFSET(end));
+        else
+                ret = unmap_single_bt(mm, bd_entry, bt_addr);
+        return ret;
+}
+/*
+ * A virtual address region being munmap()ed might share bounds table
+ * with adjacent VMAs. We only need to free the backing physical
+ * memory of these shared bounds tables entries covered in this virtual
+ * address region.
+ */
+static int unmap_edge_bts(struct mm_struct *mm,
+                unsigned long start, unsigned long end)
+{
+        int ret;
+        long __user *bde_start, *bde_end;
+        struct vm_area_struct *prev, *next;
+        bool prev_shared = false, next_shared = false;
+        bde_start = mm->bd_addr + MPX_GET_BD_ENTRY_OFFSET(start);
+        bde_end = mm->bd_addr + MPX_GET_BD_ENTRY_OFFSET(end-1);
+        /*
+         * Check whether bde_start and bde_end are shared with adjacent
+         * VMAs.
+         *
+         * We already unliked the VMAs from the mm's rbtree so 'start'
+         * is guaranteed to be in a hole. This gets us the first VMA
+         * before the hole in to 'prev' and the next VMA after the hole
+         * in to 'next'.
+         */
+        next = find_vma_prev(mm, start, &prev);
+        if (prev && (mm->bd_addr + MPX_GET_BD_ENTRY_OFFSET(prev->vm_end-1))
+                        == bde_start)
+                prev_shared = true;
+        if (next && (mm->bd_addr + MPX_GET_BD_ENTRY_OFFSET(next->vm_start))
+                        == bde_end)
+                next_shared = true;
+        /*
+         * This virtual address region being munmap()ed is only
+         * covered by one bounds table.
+         *
+         * In this case, if this table is also shared with adjacent
+         * VMAs, only part of the backing physical memory of the bounds
+         * table need be freeed. Otherwise the whole bounds table need
+         * be unmapped.
+         */
+        if (bde_start == bde_end) {
+                return unmap_shared_bt(mm, bde_start, start, end,
+                                prev_shared, next_shared);
+        }
+        /*
+         * If more than one bounds tables are covered in this virtual
+         * address region being munmap()ed, we need to separately check
+         * whether bde_start and bde_end are shared with adjacent VMAs.
+         */
+        ret = unmap_shared_bt(mm, bde_start, start, end, prev_shared, false);
+        if (ret)
+                return ret;
+        ret = unmap_shared_bt(mm, bde_end, start, end, false, next_shared);
+        if (ret)
+                return ret;
+        return 0;
+}
+static int mpx_unmap_tables(struct mm_struct *mm,
+                unsigned long start, unsigned long end)
+{
+        int ret;
+        long __user *bd_entry, *bde_start, *bde_end;
+        unsigned long bt_addr;
+        /*
+         * "Edge" bounds tables are those which are being used by the region
+         * (start -> end), but that may be shared with adjacent areas.  If they
+         * turn out to be completely unshared, they will be freed.  If they are
+         * shared, we will free the backing store (like an MADV_DONTNEED) for
+         * areas used by this region.
+         */
+        ret = unmap_edge_bts(mm, start, end);
+        switch (ret) {
+                /* non-present tables are OK */
+                case 0:
+                case -ENOENT:
+                        /* Success, or no tables to unmap */
+                        break;
+                case -EINVAL:
+                case -EFAULT:
+                default:
+                        return ret;
+        }
+        /*
+         * Only unmap the bounds table that are
+         *   1. fully covered
+         *   2. not at the edges of the mapping, even if full aligned
+         */
+        bde_start = mm->bd_addr + MPX_GET_BD_ENTRY_OFFSET(start);
+        bde_end = mm->bd_addr + MPX_GET_BD_ENTRY_OFFSET(end-1);
+        for (bd_entry = bde_start + 1; bd_entry < bde_end; bd_entry++) {
+                ret = get_bt_addr(mm, bd_entry, &bt_addr);
+                switch (ret) {
+                        case 0:
+                                break;
+                        case -ENOENT:
+                                /* No table here, try the next one */
+                                continue;
+                        case -EINVAL:
+                        case -EFAULT:
+                        default:
+                                /*
+                                 * Note: we are being strict here.
+                                 * Any time we run in to an issue
+                                 * unmapping tables, we stop and
+                                 * SIGSEGV.
+                                 */
+                                return ret;
+                }
+                ret = unmap_single_bt(mm, bd_entry, bt_addr);
+                if (ret)
+                        return ret;
+        }
+        return 0;
+}
+/*
+ * Free unused bounds tables covered in a virtual address region being
+ * munmap()ed. Assume end > start.
+ *
+ * This function will be called by do_munmap(), and the VMAs covering
+ * the virtual address region start...end have already been split if
+ * necessary, and the 'vma' is the first vma in this range (start -> end).
+ */
+void mpx_notify_unmap(struct mm_struct *mm, struct vm_area_struct *vma,
+                unsigned long start, unsigned long end)
+{
+        int ret;
+        /*
+         * Refuse to do anything unless userspace has asked
+         * the kernel to help manage the bounds tables,
+         */
+        if (!kernel_managing_mpx_tables(current->mm))
+                return;
+        /*
+         * This will look across the entire 'start -> end' range,
+         * and find all of the non-VM_MPX VMAs.
+         *
+         * To avoid recursion, if a VM_MPX vma is found in the range
+         * (start->end), we will not continue follow-up work. This
+         * recursion represents having bounds tables for bounds tables,
+         * which should not occur normally. Being strict about it here
+         * helps ensure that we do not have an exploitable stack overflow.
+         */
+        do {
+                if (vma->vm_flags & VM_MPX)
+                        return;
+                vma = vma->vm_next;
+        } while (vma && vma->vm_start < end);
+        ret = mpx_unmap_tables(mm, start, end);
+        if (ret)
+                force_sig(SIGSEGV, current);
+}
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index 36de293caf25..a3a5d46605d2 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -485,14 +485,23 @@ try_preserve_large_page(pte_t *kpte, unsigned long address,
        /*
         * We are safe now. Check whether the new pgprot is the same:
+         * Convert protection attributes to 4k-format, as cpa->mask* are set
+         * up accordingly.
         */
        old_pte = *kpte;
-        old_prot = req_prot = pte_pgprot(old_pte);
+        old_prot = req_prot = pgprot_large_2_4k(pte_pgprot(old_pte));
        pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr);
        pgprot_val(req_prot) |= pgprot_val(cpa->mask_set);
        /*
+         * req_prot is in format of 4k pages. It must be converted to large
+         * page format: the caching mode includes the PAT bit located at
+         * different bit positions in the two formats.
+         */
+        req_prot = pgprot_4k_2_large(req_prot);
+        /*
         * Set the PSE and GLOBAL flags only if the PRESENT flag is
         * set otherwise pmd_present/pmd_huge will return true even on
         * a non present pmd. The canon_pgprot will clear _PAGE_GLOBAL
@@ -585,13 +594,10 @@ __split_large_page(struct cpa_data *cpa, pte_t *kpte, unsigned long address,
        paravirt_alloc_pte(&init_mm, page_to_pfn(base));
        ref_prot = pte_pgprot(pte_clrhuge(*kpte));
-        /*
-         * If we ever want to utilize the PAT bit, we need to
+        /* promote PAT bit to correct position */
-         * update this function to make sure it's converted from
+        if (level == PG_LEVEL_2M)
-         * bit 12 to bit 7 when we cross from the 2MB level to
+                ref_prot = pgprot_large_2_4k(ref_prot);
-         * the 4K level:
-         */
-        WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE);
 #ifdef CONFIG_X86_64
        if (level == PG_LEVEL_1G) {
@@ -879,6 +885,7 @@ static int populate_pmd(struct cpa_data *cpa,
 {
        unsigned int cur_pages = 0;
        pmd_t *pmd;
+        pgprot_t pmd_pgprot;
        /*
         * Not on a 2M boundary?
@@ -910,6 +917,8 @@ static int populate_pmd(struct cpa_data *cpa,
        if (num_pages == cur_pages)
                return cur_pages;
+        pmd_pgprot = pgprot_4k_2_large(pgprot);
        while (end - start >= PMD_SIZE) {
                /*
@@ -921,7 +930,8 @@ static int populate_pmd(struct cpa_data *cpa,
                pmd = pmd_offset(pud, start);
-                set_pmd(pmd, __pmd(cpa->pfn | _PAGE_PSE | massage_pgprot(pgprot)));
+                set_pmd(pmd, __pmd(cpa->pfn | _PAGE_PSE |
+                                   massage_pgprot(pmd_pgprot)));
                start     += PMD_SIZE;
                cpa->pfn  += PMD_SIZE;
@@ -949,6 +959,7 @@ static int populate_pud(struct cpa_data *cpa, unsigned long start, pgd_t *pgd,
        pud_t *pud;
        unsigned long end;
        int cur_pages = 0;
+        pgprot_t pud_pgprot;
        end = start + (cpa->numpages << PAGE_SHIFT);
@@ -986,12 +997,14 @@ static int populate_pud(struct cpa_data *cpa, unsigned long start, pgd_t *pgd,
                return cur_pages;
        pud = pud_offset(pgd, start);
+        pud_pgprot = pgprot_4k_2_large(pgprot);
        /*
         * Map everything starting from the Gb boundary, possibly with 1G pages
         */
        while (end - start >= PUD_SIZE) {
-                set_pud(pud, __pud(cpa->pfn | _PAGE_PSE | massage_pgprot(pgprot)));
+                set_pud(pud, __pud(cpa->pfn | _PAGE_PSE |
+                                   massage_pgprot(pud_pgprot)));
                start     += PUD_SIZE;
                cpa->pfn  += PUD_SIZE;
@@ -1304,12 +1317,6 @@ static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
        return 0;
 }
-static inline int cache_attr(pgprot_t attr)
-{
-        return pgprot_val(attr) &
-                (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD);
-}
 static int change_page_attr_set_clr(unsigned long *addr, int numpages,
                                    pgprot_t mask_set, pgprot_t mask_clr,
                                    int force_split, int in_flag,
@@ -1390,7 +1397,7 @@ static int change_page_attr_set_clr(unsigned long *addr, int numpages,
         * No need to flush, when we did not set any of the caching
         * attributes:
         */
-        cache = cache_attr(mask_set);
+        cache = !!pgprot2cachemode(mask_set);
        /*
         * On success we use CLFLUSH, when the CPU supports it to
@@ -1445,7 +1452,8 @@ int _set_memory_uc(unsigned long addr, int numpages)
         * for now UC MINUS. see comments in ioremap_nocache()
         */
        return change_page_attr_set(&addr, numpages,
-                                    __pgprot(_PAGE_CACHE_UC_MINUS), 0);
+                                    cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS),
+                                    0);
 }
 int set_memory_uc(unsigned long addr, int numpages)
@@ -1456,7 +1464,7 @@ int set_memory_uc(unsigned long addr, int numpages)
         * for now UC MINUS. see comments in ioremap_nocache()
         */
        ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
-                            _PAGE_CACHE_UC_MINUS, NULL);
+                              _PAGE_CACHE_MODE_UC_MINUS, NULL);
        if (ret)
                goto out_err;
@@ -1474,7 +1482,7 @@ out_err:
 EXPORT_SYMBOL(set_memory_uc);
 static int _set_memory_array(unsigned long *addr, int addrinarray,
-                unsigned long new_type)
+                enum page_cache_mode new_type)
 {
        int i, j;
        int ret;
@@ -1490,11 +1498,13 @@ static int _set_memory_array(unsigned long *addr, int addrinarray,
        }
        ret = change_page_attr_set(addr, addrinarray,
-                                    __pgprot(_PAGE_CACHE_UC_MINUS), 1);
+                                   cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS),
+                                   1);
-        if (!ret && new_type == _PAGE_CACHE_WC)
+        if (!ret && new_type == _PAGE_CACHE_MODE_WC)
                ret = change_page_attr_set_clr(addr, addrinarray,
-                                               __pgprot(_PAGE_CACHE_WC),
+                                               cachemode2pgprot(
+                                                _PAGE_CACHE_MODE_WC),
                                               __pgprot(_PAGE_CACHE_MASK),
                                               0, CPA_ARRAY, NULL);
        if (ret)
@@ -1511,13 +1521,13 @@ out_free:
 int set_memory_array_uc(unsigned long *addr, int addrinarray)
 {
-        return _set_memory_array(addr, addrinarray, _PAGE_CACHE_UC_MINUS);
+        return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_UC_MINUS);
 }
 EXPORT_SYMBOL(set_memory_array_uc);
 int set_memory_array_wc(unsigned long *addr, int addrinarray)
 {
-        return _set_memory_array(addr, addrinarray, _PAGE_CACHE_WC);
+        return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_WC);
 }
 EXPORT_SYMBOL(set_memory_array_wc);
@@ -1527,10 +1537,12 @@ int _set_memory_wc(unsigned long addr, int numpages)
        unsigned long addr_copy = addr;
        ret = change_page_attr_set(&addr, numpages,
-                                    __pgprot(_PAGE_CACHE_UC_MINUS), 0);
+                                   cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS),
+                                   0);
        if (!ret) {
                ret = change_page_attr_set_clr(&addr_copy, numpages,
-                                               __pgprot(_PAGE_CACHE_WC),
+                                               cachemode2pgprot(
+                                                _PAGE_CACHE_MODE_WC),
                                               __pgprot(_PAGE_CACHE_MASK),
                                               0, 0, NULL);
        }
@@ -1545,7 +1557,7 @@ int set_memory_wc(unsigned long addr, int numpages)
                return set_memory_uc(addr, numpages);
        ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
-                _PAGE_CACHE_WC, NULL);
+                _PAGE_CACHE_MODE_WC, NULL);
        if (ret)
                goto out_err;
@@ -1564,6 +1576,7 @@ EXPORT_SYMBOL(set_memory_wc);
 int _set_memory_wb(unsigned long addr, int numpages)
 {
+        /* WB cache mode is hard wired to all cache attribute bits being 0 */
        return change_page_attr_clear(&addr, numpages,
                                      __pgprot(_PAGE_CACHE_MASK), 0);
 }
@@ -1586,6 +1599,7 @@ int set_memory_array_wb(unsigned long *addr, int addrinarray)
        int i;
        int ret;
+        /* WB cache mode is hard wired to all cache attribute bits being 0 */
        ret = change_page_attr_clear(addr, addrinarray,
                                      __pgprot(_PAGE_CACHE_MASK), 1);
        if (ret)
@@ -1648,7 +1662,7 @@ int set_pages_uc(struct page *page, int numpages)
 EXPORT_SYMBOL(set_pages_uc);
 static int _set_pages_array(struct page **pages, int addrinarray,
-                unsigned long new_type)
+                enum page_cache_mode new_type)
 {
        unsigned long start;
        unsigned long end;
@@ -1666,10 +1680,11 @@ static int _set_pages_array(struct page **pages, int addrinarray,
        }
        ret = cpa_set_pages_array(pages, addrinarray,
-                        __pgprot(_PAGE_CACHE_UC_MINUS));
+                        cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS));
-        if (!ret && new_type == _PAGE_CACHE_WC)
+        if (!ret && new_type == _PAGE_CACHE_MODE_WC)
                ret = change_page_attr_set_clr(NULL, addrinarray,
-                                               __pgprot(_PAGE_CACHE_WC),
+                                               cachemode2pgprot(
+                                                _PAGE_CACHE_MODE_WC),
                                               __pgprot(_PAGE_CACHE_MASK),
                                               0, CPA_PAGES_ARRAY, pages);
        if (ret)
@@ -1689,13 +1704,13 @@ err_out:
 int set_pages_array_uc(struct page **pages, int addrinarray)
 {
-        return _set_pages_array(pages, addrinarray, _PAGE_CACHE_UC_MINUS);
+        return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_UC_MINUS);
 }
 EXPORT_SYMBOL(set_pages_array_uc);
 int set_pages_array_wc(struct page **pages, int addrinarray)
 {
-        return _set_pages_array(pages, addrinarray, _PAGE_CACHE_WC);
+        return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_WC);
 }
 EXPORT_SYMBOL(set_pages_array_wc);
@@ -1714,6 +1729,7 @@ int set_pages_array_wb(struct page **pages, int addrinarray)
        unsigned long end;
        int i;
+        /* WB cache mode is hard wired to all cache attribute bits being 0 */
        retval = cpa_clear_pages_array(pages, addrinarray,
                        __pgprot(_PAGE_CACHE_MASK));
        if (retval)
diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c
index 657438858e83..edf299c8ff6c 100644
--- a/arch/x86/mm/pat.c
+++ b/arch/x86/mm/pat.c
@@ -31,6 +31,7 @@
 #include <asm/io.h>
 #include "pat_internal.h"
+#include "mm_internal.h"
 #ifdef CONFIG_X86_PAT
 int __read_mostly pat_enabled = 1;
@@ -66,6 +67,75 @@ __setup("debugpat", pat_debug_setup);
 static u64 __read_mostly boot_pat_state;
+#ifdef CONFIG_X86_PAT
+/*
+ * X86 PAT uses page flags WC and Uncached together to keep track of
+ * memory type of pages that have backing page struct. X86 PAT supports 3
+ * different memory types, _PAGE_CACHE_MODE_WB, _PAGE_CACHE_MODE_WC and
+ * _PAGE_CACHE_MODE_UC_MINUS and fourth state where page's memory type has not
+ * been changed from its default (value of -1 used to denote this).
+ * Note we do not support _PAGE_CACHE_MODE_UC here.
+ */
+#define _PGMT_DEFAULT           0
+#define _PGMT_WC                (1UL << PG_arch_1)
+#define _PGMT_UC_MINUS          (1UL << PG_uncached)
+#define _PGMT_WB                (1UL << PG_uncached | 1UL << PG_arch_1)
+#define _PGMT_MASK              (1UL << PG_uncached | 1UL << PG_arch_1)
+#define _PGMT_CLEAR_MASK        (~_PGMT_MASK)
+static inline enum page_cache_mode get_page_memtype(struct page *pg)
+{
+        unsigned long pg_flags = pg->flags & _PGMT_MASK;
+        if (pg_flags == _PGMT_DEFAULT)
+                return -1;
+        else if (pg_flags == _PGMT_WC)
+                return _PAGE_CACHE_MODE_WC;
+        else if (pg_flags == _PGMT_UC_MINUS)
+                return _PAGE_CACHE_MODE_UC_MINUS;
+        else
+                return _PAGE_CACHE_MODE_WB;
+}
+static inline void set_page_memtype(struct page *pg,
+                                    enum page_cache_mode memtype)
+{
+        unsigned long memtype_flags;
+        unsigned long old_flags;
+        unsigned long new_flags;
+        switch (memtype) {
+        case _PAGE_CACHE_MODE_WC:
+                memtype_flags = _PGMT_WC;
+                break;
+        case _PAGE_CACHE_MODE_UC_MINUS:
+                memtype_flags = _PGMT_UC_MINUS;
+                break;
+        case _PAGE_CACHE_MODE_WB:
+                memtype_flags = _PGMT_WB;
+                break;
+        default:
+                memtype_flags = _PGMT_DEFAULT;
+                break;
+        }
+        do {
+                old_flags = pg->flags;
+                new_flags = (old_flags & _PGMT_CLEAR_MASK) | memtype_flags;
+        } while (cmpxchg(&pg->flags, old_flags, new_flags) != old_flags);
+}
+#else
+static inline enum page_cache_mode get_page_memtype(struct page *pg)
+{
+        return -1;
+}
+static inline void set_page_memtype(struct page *pg,
+                                    enum page_cache_mode memtype)
+{
+}
+#endif
 enum {
        PAT_UC = 0,             /* uncached */
        PAT_WC = 1,             /* Write combining */
@@ -75,6 +145,52 @@ enum {
        PAT_UC_MINUS = 7,       /* UC, but can be overriden by MTRR */
 };
+#define CM(c) (_PAGE_CACHE_MODE_ ## c)
+static enum page_cache_mode pat_get_cache_mode(unsigned pat_val, char *msg)
+{
+        enum page_cache_mode cache;
+        char *cache_mode;
+        switch (pat_val) {
+        case PAT_UC:       cache = CM(UC);       cache_mode = "UC  "; break;
+        case PAT_WC:       cache = CM(WC);       cache_mode = "WC  "; break;
+        case PAT_WT:       cache = CM(WT);       cache_mode = "WT  "; break;
+        case PAT_WP:       cache = CM(WP);       cache_mode = "WP  "; break;
+        case PAT_WB:       cache = CM(WB);       cache_mode = "WB  "; break;
+        case PAT_UC_MINUS: cache = CM(UC_MINUS); cache_mode = "UC- "; break;
+        default:           cache = CM(WB);       cache_mode = "WB  "; break;
+        }
+        memcpy(msg, cache_mode, 4);
+        return cache;
+}
+#undef CM
+/*
+ * Update the cache mode to pgprot translation tables according to PAT
+ * configuration.
+ * Using lower indices is preferred, so we start with highest index.
+ */
+void pat_init_cache_modes(void)
+{
+        int i;
+        enum page_cache_mode cache;
+        char pat_msg[33];
+        u64 pat;
+        rdmsrl(MSR_IA32_CR_PAT, pat);
+        pat_msg[32] = 0;
+        for (i = 7; i >= 0; i--) {
+                cache = pat_get_cache_mode((pat >> (i * 8)) & 7,
+                                           pat_msg + 4 * i);
+                update_cache_mode_entry(i, cache);
+        }
+        pr_info("PAT configuration [0-7]: %s\n", pat_msg);
+}
 #define PAT(x, y)       ((u64)PAT_ ## y << ((x)*8))
 void pat_init(void)
@@ -124,8 +240,7 @@ void pat_init(void)
        wrmsrl(MSR_IA32_CR_PAT, pat);
        if (boot_cpu)
-                printk(KERN_INFO "x86 PAT enabled: cpu %d, old 0x%Lx, new 0x%Lx\n",
+                pat_init_cache_modes();
-                       smp_processor_id(), boot_pat_state, pat);
 }
 #undef PAT
@@ -139,20 +254,21 @@ static DEFINE_SPINLOCK(memtype_lock);	/* protects memtype accesses */
 * The intersection is based on "Effective Memory Type" tables in IA-32
 * SDM vol 3a
 */
-static unsigned long pat_x_mtrr_type(u64 start, u64 end, unsigned long req_type)
+static unsigned long pat_x_mtrr_type(u64 start, u64 end,
+                                     enum page_cache_mode req_type)
 {
        /*
         * Look for MTRR hint to get the effective type in case where PAT
         * request is for WB.
         */
-        if (req_type == _PAGE_CACHE_WB) {
+        if (req_type == _PAGE_CACHE_MODE_WB) {
                u8 mtrr_type;
                mtrr_type = mtrr_type_lookup(start, end);
                if (mtrr_type != MTRR_TYPE_WRBACK)
-                        return _PAGE_CACHE_UC_MINUS;
+                        return _PAGE_CACHE_MODE_UC_MINUS;
-                return _PAGE_CACHE_WB;
+                return _PAGE_CACHE_MODE_WB;
        }
        return req_type;
@@ -207,25 +323,26 @@ static int pat_pagerange_is_ram(resource_size_t start, resource_size_t end)
 * - Find the memtype of all the pages in the range, look for any conflicts
 * - In case of no conflicts, set the new memtype for pages in the range
 */
-static int reserve_ram_pages_type(u64 start, u64 end, unsigned long req_type,
+static int reserve_ram_pages_type(u64 start, u64 end,
-                                  unsigned long *new_type)
+                                  enum page_cache_mode req_type,
+                                  enum page_cache_mode *new_type)
 {
        struct page *page;
        u64 pfn;
-        if (req_type == _PAGE_CACHE_UC) {
+        if (req_type == _PAGE_CACHE_MODE_UC) {
                /* We do not support strong UC */
                WARN_ON_ONCE(1);
-                req_type = _PAGE_CACHE_UC_MINUS;
+                req_type = _PAGE_CACHE_MODE_UC_MINUS;
        }
        for (pfn = (start >> PAGE_SHIFT); pfn < (end >> PAGE_SHIFT); ++pfn) {
-                unsigned long type;
+                enum page_cache_mode type;
                page = pfn_to_page(pfn);
                type = get_page_memtype(page);
                if (type != -1) {
-                        printk(KERN_INFO "reserve_ram_pages_type failed [mem %#010Lx-%#010Lx], track 0x%lx, req 0x%lx\n",
+                        pr_info("reserve_ram_pages_type failed [mem %#010Lx-%#010Lx], track 0x%x, req 0x%x\n",
                                start, end - 1, type, req_type);
                        if (new_type)
                                *new_type = type;
@@ -258,21 +375,21 @@ static int free_ram_pages_type(u64 start, u64 end)
 /*
 * req_type typically has one of the:
- * - _PAGE_CACHE_WB
+ * - _PAGE_CACHE_MODE_WB
- * - _PAGE_CACHE_WC
+ * - _PAGE_CACHE_MODE_WC
- * - _PAGE_CACHE_UC_MINUS
+ * - _PAGE_CACHE_MODE_UC_MINUS
- * - _PAGE_CACHE_UC
+ * - _PAGE_CACHE_MODE_UC
 *
 * If new_type is NULL, function will return an error if it cannot reserve the
 * region with req_type. If new_type is non-NULL, function will return
 * available type in new_type in case of no error. In case of any error
 * it will return a negative return value.
 */
-int reserve_memtype(u64 start, u64 end, unsigned long req_type,
+int reserve_memtype(u64 start, u64 end, enum page_cache_mode req_type,
-                    unsigned long *new_type)
+                    enum page_cache_mode *new_type)
 {
        struct memtype *new;
-        unsigned long actual_type;
+        enum page_cache_mode actual_type;
        int is_range_ram;
        int err = 0;
@@ -281,10 +398,10 @@ int reserve_memtype(u64 start, u64 end, unsigned long req_type,
        if (!pat_enabled) {
                /* This is identical to page table setting without PAT */
                if (new_type) {
-                        if (req_type == _PAGE_CACHE_WC)
+                        if (req_type == _PAGE_CACHE_MODE_WC)
-                                *new_type = _PAGE_CACHE_UC_MINUS;
+                                *new_type = _PAGE_CACHE_MODE_UC_MINUS;
                        else
-                                *new_type = req_type & _PAGE_CACHE_MASK;
+                                *new_type = req_type;
                }
                return 0;
        }
@@ -292,7 +409,7 @@ int reserve_memtype(u64 start, u64 end, unsigned long req_type,
        /* Low ISA region is always mapped WB in page table. No need to track */
        if (x86_platform.is_untracked_pat_range(start, end)) {
                if (new_type)
-                        *new_type = _PAGE_CACHE_WB;
+                        *new_type = _PAGE_CACHE_MODE_WB;
                return 0;
        }
@@ -302,7 +419,7 @@ int reserve_memtype(u64 start, u64 end, unsigned long req_type,
         * tools and ACPI tools). Use WB request for WB memory and use
         * UC_MINUS otherwise.
         */
-        actual_type = pat_x_mtrr_type(start, end, req_type & _PAGE_CACHE_MASK);
+        actual_type = pat_x_mtrr_type(start, end, req_type);
        if (new_type)
                *new_type = actual_type;
@@ -394,12 +511,12 @@ int free_memtype(u64 start, u64 end)
 *
 * Only to be called when PAT is enabled
 *
- * Returns _PAGE_CACHE_WB, _PAGE_CACHE_WC, _PAGE_CACHE_UC_MINUS or
+ * Returns _PAGE_CACHE_MODE_WB, _PAGE_CACHE_MODE_WC, _PAGE_CACHE_MODE_UC_MINUS
- * _PAGE_CACHE_UC
+ * or _PAGE_CACHE_MODE_UC
 */
-static unsigned long lookup_memtype(u64 paddr)
+static enum page_cache_mode lookup_memtype(u64 paddr)
 {
-        int rettype = _PAGE_CACHE_WB;
+        enum page_cache_mode rettype = _PAGE_CACHE_MODE_WB;
        struct memtype *entry;
        if (x86_platform.is_untracked_pat_range(paddr, paddr + PAGE_SIZE))
@@ -414,7 +531,7 @@ static unsigned long lookup_memtype(u64 paddr)
                 * default state and not reserved, and hence of type WB
                 */
                if (rettype == -1)
-                        rettype = _PAGE_CACHE_WB;
+                        rettype = _PAGE_CACHE_MODE_WB;
                return rettype;
        }
@@ -425,7 +542,7 @@ static unsigned long lookup_memtype(u64 paddr)
        if (entry != NULL)
                rettype = entry->type;
        else
-                rettype = _PAGE_CACHE_UC_MINUS;
+                rettype = _PAGE_CACHE_MODE_UC_MINUS;
        spin_unlock(&memtype_lock);
        return rettype;
@@ -442,11 +559,11 @@ static unsigned long lookup_memtype(u64 paddr)
 * On failure, returns non-zero
 */
 int io_reserve_memtype(resource_size_t start, resource_size_t end,
-                        unsigned long *type)
+                        enum page_cache_mode *type)
 {
        resource_size_t size = end - start;
-        unsigned long req_type = *type;
+        enum page_cache_mode req_type = *type;
-        unsigned long new_type;
+        enum page_cache_mode new_type;
        int ret;
        WARN_ON_ONCE(iomem_map_sanity_check(start, size));
@@ -520,13 +637,13 @@ static inline int range_is_allowed(unsigned long pfn, unsigned long size)
 int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
                                unsigned long size, pgprot_t *vma_prot)
 {
-        unsigned long flags = _PAGE_CACHE_WB;
+        enum page_cache_mode pcm = _PAGE_CACHE_MODE_WB;
        if (!range_is_allowed(pfn, size))
                return 0;
        if (file->f_flags & O_DSYNC)
-                flags = _PAGE_CACHE_UC_MINUS;
+                pcm = _PAGE_CACHE_MODE_UC_MINUS;
 #ifdef CONFIG_X86_32
        /*
@@ -543,12 +660,12 @@ int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
              boot_cpu_has(X86_FEATURE_CYRIX_ARR) ||
              boot_cpu_has(X86_FEATURE_CENTAUR_MCR)) &&
            (pfn << PAGE_SHIFT) >= __pa(high_memory)) {
-                flags = _PAGE_CACHE_UC;
+                pcm = _PAGE_CACHE_MODE_UC;
        }
 #endif
        *vma_prot = __pgprot((pgprot_val(*vma_prot) & ~_PAGE_CACHE_MASK) |
-                             flags);
+                             cachemode2protval(pcm));
        return 1;
 }
@@ -556,7 +673,8 @@ int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
 * Change the memory type for the physial address range in kernel identity
 * mapping space if that range is a part of identity map.
 */
-int kernel_map_sync_memtype(u64 base, unsigned long size, unsigned long flags)
+int kernel_map_sync_memtype(u64 base, unsigned long size,
+                            enum page_cache_mode pcm)
 {
        unsigned long id_sz;
@@ -574,11 +692,11 @@ int kernel_map_sync_memtype(u64 base, unsigned long size, unsigned long flags)
                                __pa(high_memory) - base :
                                size;
-        if (ioremap_change_attr((unsigned long)__va(base), id_sz, flags) < 0) {
+        if (ioremap_change_attr((unsigned long)__va(base), id_sz, pcm) < 0) {
                printk(KERN_INFO "%s:%d ioremap_change_attr failed %s "
                        "for [mem %#010Lx-%#010Lx]\n",
                        current->comm, current->pid,
-                        cattr_name(flags),
+                        cattr_name(pcm),
                        base, (unsigned long long)(base + size-1));
                return -EINVAL;
        }
@@ -595,8 +713,8 @@ static int reserve_pfn_range(u64 paddr, unsigned long size, pgprot_t *vma_prot,
 {
        int is_ram = 0;
        int ret;
-        unsigned long want_flags = (pgprot_val(*vma_prot) & _PAGE_CACHE_MASK);
+        enum page_cache_mode want_pcm = pgprot2cachemode(*vma_prot);
-        unsigned long flags = want_flags;
+        enum page_cache_mode pcm = want_pcm;
        is_ram = pat_pagerange_is_ram(paddr, paddr + size);
@@ -609,36 +727,36 @@ static int reserve_pfn_range(u64 paddr, unsigned long size, pgprot_t *vma_prot,
                if (!pat_enabled)
                        return 0;
-                flags = lookup_memtype(paddr);
+                pcm = lookup_memtype(paddr);
-                if (want_flags != flags) {
+                if (want_pcm != pcm) {
                        printk(KERN_WARNING "%s:%d map pfn RAM range req %s for [mem %#010Lx-%#010Lx], got %s\n",
                                current->comm, current->pid,
-                                cattr_name(want_flags),
+                                cattr_name(want_pcm),
                                (unsigned long long)paddr,
                                (unsigned long long)(paddr + size - 1),
-                                cattr_name(flags));
+                                cattr_name(pcm));
                        *vma_prot = __pgprot((pgprot_val(*vma_prot) &
-                                              (~_PAGE_CACHE_MASK)) |
+                                             (~_PAGE_CACHE_MASK)) |
-                                             flags);
+                                             cachemode2protval(pcm));
                }
                return 0;
        }
-        ret = reserve_memtype(paddr, paddr + size, want_flags, &flags);
+        ret = reserve_memtype(paddr, paddr + size, want_pcm, &pcm);
        if (ret)
                return ret;
-        if (flags != want_flags) {
+        if (pcm != want_pcm) {
                if (strict_prot ||
-                    !is_new_memtype_allowed(paddr, size, want_flags, flags)) {
+                    !is_new_memtype_allowed(paddr, size, want_pcm, pcm)) {
                        free_memtype(paddr, paddr + size);
                        printk(KERN_ERR "%s:%d map pfn expected mapping type %s"
                                " for [mem %#010Lx-%#010Lx], got %s\n",
                                current->comm, current->pid,
-                                cattr_name(want_flags),
+                                cattr_name(want_pcm),
                                (unsigned long long)paddr,
                                (unsigned long long)(paddr + size - 1),
-                                cattr_name(flags));
+                                cattr_name(pcm));
                        return -EINVAL;
                }
                /*
@@ -647,10 +765,10 @@ static int reserve_pfn_range(u64 paddr, unsigned long size, pgprot_t *vma_prot,
                 */
                *vma_prot = __pgprot((pgprot_val(*vma_prot) &
                                      (~_PAGE_CACHE_MASK)) |
-                                     flags);
+                                     cachemode2protval(pcm));
        }
-        if (kernel_map_sync_memtype(paddr, size, flags) < 0) {
+        if (kernel_map_sync_memtype(paddr, size, pcm) < 0) {
                free_memtype(paddr, paddr + size);
                return -EINVAL;
        }
@@ -709,7 +827,7 @@ int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot,
                    unsigned long pfn, unsigned long addr, unsigned long size)
 {
        resource_size_t paddr = (resource_size_t)pfn << PAGE_SHIFT;
-        unsigned long flags;
+        enum page_cache_mode pcm;
        /* reserve the whole chunk starting from paddr */
        if (addr == vma->vm_start && size == (vma->vm_end - vma->vm_start)) {
@@ -728,18 +846,18 @@ int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot,
         * For anything smaller than the vma size we set prot based on the
         * lookup.
         */
-        flags = lookup_memtype(paddr);
+        pcm = lookup_memtype(paddr);
        /* Check memtype for the remaining pages */
        while (size > PAGE_SIZE) {
                size -= PAGE_SIZE;
                paddr += PAGE_SIZE;
-                if (flags != lookup_memtype(paddr))
+                if (pcm != lookup_memtype(paddr))
                        return -EINVAL;
        }
        *prot = __pgprot((pgprot_val(vma->vm_page_prot) & (~_PAGE_CACHE_MASK)) |
-                         flags);
+                         cachemode2protval(pcm));
        return 0;
 }
@@ -747,15 +865,15 @@ int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot,
 int track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot,
                     unsigned long pfn)
 {
-        unsigned long flags;
+        enum page_cache_mode pcm;
        if (!pat_enabled)
                return 0;
        /* Set prot based on lookup */
-        flags = lookup_memtype((resource_size_t)pfn << PAGE_SHIFT);
+        pcm = lookup_memtype((resource_size_t)pfn << PAGE_SHIFT);
        *prot = __pgprot((pgprot_val(vma->vm_page_prot) & (~_PAGE_CACHE_MASK)) |
-                         flags);
+                         cachemode2protval(pcm));
        return 0;
 }
@@ -791,7 +909,8 @@ void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn,
 pgprot_t pgprot_writecombine(pgprot_t prot)
 {
        if (pat_enabled)
-                return __pgprot(pgprot_val(prot) | _PAGE_CACHE_WC);
+                return __pgprot(pgprot_val(prot) |
+                                cachemode2protval(_PAGE_CACHE_MODE_WC));
        else
                return pgprot_noncached(prot);
 }
@@ -824,7 +943,7 @@ static void *memtype_seq_start(struct seq_file *seq, loff_t *pos)
 {
        if (*pos == 0) {
                ++*pos;
-                seq_printf(seq, "PAT memtype list:\n");
+                seq_puts(seq, "PAT memtype list:\n");
        }
        return memtype_get_idx(*pos);
diff --git a/arch/x86/mm/pat_internal.h b/arch/x86/mm/pat_internal.h
index 77e5ba153fac..f6411620305d 100644
--- a/arch/x86/mm/pat_internal.h
+++ b/arch/x86/mm/pat_internal.h
@@ -10,30 +10,32 @@ struct memtype {
        u64                     start;
        u64                     end;
        u64                     subtree_max_end;
-        unsigned long           type;
+        enum page_cache_mode    type;
        struct rb_node          rb;
 };
-static inline char *cattr_name(unsigned long flags)
+static inline char *cattr_name(enum page_cache_mode pcm)
 {
-        switch (flags & _PAGE_CACHE_MASK) {
+        switch (pcm) {
-        case _PAGE_CACHE_UC:            return "uncached";
+        case _PAGE_CACHE_MODE_UC:               return "uncached";
-        case _PAGE_CACHE_UC_MINUS:      return "uncached-minus";
+        case _PAGE_CACHE_MODE_UC_MINUS:         return "uncached-minus";
-        case _PAGE_CACHE_WB:            return "write-back";
+        case _PAGE_CACHE_MODE_WB:               return "write-back";
-        case _PAGE_CACHE_WC:            return "write-combining";
+        case _PAGE_CACHE_MODE_WC:               return "write-combining";
-        default:                        return "broken";
+        case _PAGE_CACHE_MODE_WT:               return "write-through";
+        case _PAGE_CACHE_MODE_WP:               return "write-protected";
+        default:                                return "broken";
        }
 }
 #ifdef CONFIG_X86_PAT
 extern int rbt_memtype_check_insert(struct memtype *new,
-                                        unsigned long *new_type);
+                                        enum page_cache_mode *new_type);
 extern struct memtype *rbt_memtype_erase(u64 start, u64 end);
 extern struct memtype *rbt_memtype_lookup(u64 addr);
 extern int rbt_memtype_copy_nth_element(struct memtype *out, loff_t pos);
 #else
 static inline int rbt_memtype_check_insert(struct memtype *new,
-                                        unsigned long *new_type)
+                                        enum page_cache_mode *new_type)
 { return 0; }
 static inline struct memtype *rbt_memtype_erase(u64 start, u64 end)
 { return NULL; }
diff --git a/arch/x86/mm/pat_rbtree.c b/arch/x86/mm/pat_rbtree.c
index 415f6c4ced36..6582adcc8bd9 100644
--- a/arch/x86/mm/pat_rbtree.c
+++ b/arch/x86/mm/pat_rbtree.c
@@ -122,11 +122,12 @@ static struct memtype *memtype_rb_exact_match(struct rb_root *root,
 static int memtype_rb_check_conflict(struct rb_root *root,
                                u64 start, u64 end,
-                                unsigned long reqtype, unsigned long *newtype)
+                                enum page_cache_mode reqtype,
+                                enum page_cache_mode *newtype)
 {
        struct rb_node *node;
        struct memtype *match;
-        int found_type = reqtype;
+        enum page_cache_mode found_type = reqtype;
        match = memtype_rb_lowest_match(&memtype_rbroot, start, end);
        if (match == NULL)
@@ -187,7 +188,8 @@ static void memtype_rb_insert(struct rb_root *root, struct memtype *newdata)
        rb_insert_augmented(&newdata->rb, root, &memtype_rb_augment_cb);
 }
-int rbt_memtype_check_insert(struct memtype *new, unsigned long *ret_type)
+int rbt_memtype_check_insert(struct memtype *new,
+                             enum page_cache_mode *ret_type)
 {
        int err = 0;
diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c
index 37c1435889ce..9b18ef315a55 100644
--- a/arch/x86/pci/i386.c
+++ b/arch/x86/pci/i386.c
@@ -433,14 +433,14 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
                return -EINVAL;
        if (pat_enabled && write_combine)
-                prot |= _PAGE_CACHE_WC;
+                prot |= cachemode2protval(_PAGE_CACHE_MODE_WC);
        else if (pat_enabled || boot_cpu_data.x86 > 3)
                /*
                 * ioremap() and ioremap_nocache() defaults to UC MINUS for now.
                 * To avoid attribute conflicts, request UC MINUS here
                 * as well.
                 */
-                prot |= _PAGE_CACHE_UC_MINUS;
+                prot |= cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS);
        vma->vm_page_prot = __pgprot(prot);
diff --git a/arch/x86/pci/numachip.c b/arch/x86/pci/numachip.c
index 7307d9d12d15..2e565e65c893 100644
--- a/arch/x86/pci/numachip.c
+++ b/arch/x86/pci/numachip.c
@@ -103,7 +103,7 @@ static int pci_mmcfg_write_numachip(unsigned int seg, unsigned int bus,
        return 0;
 }
-const struct pci_raw_ops pci_mmcfg_numachip = {
+static const struct pci_raw_ops pci_mmcfg_numachip = {
        .read = pci_mmcfg_read_numachip,
        .write = pci_mmcfg_write_numachip,
 };
diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c
index 093f5f4272d3..1819a91bbb9f 100644
--- a/arch/x86/pci/xen.c
+++ b/arch/x86/pci/xen.c
@@ -229,7 +229,7 @@ static int xen_hvm_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
                return 1;
        list_for_each_entry(msidesc, &dev->msi_list, list) {
-                __read_msi_msg(msidesc, &msg);
+                __pci_read_msi_msg(msidesc, &msg);
                pirq = MSI_ADDR_EXT_DEST_ID(msg.address_hi) |
                        ((msg.address_lo >> MSI_ADDR_DEST_ID_SHIFT) & 0xff);
                if (msg.data != XEN_PIRQ_MSI_DATA ||
@@ -240,7 +240,7 @@ static int xen_hvm_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
                                goto error;
                        }
                        xen_msi_compose_msg(dev, pirq, &msg);
-                        __write_msi_msg(msidesc, &msg);
+                        __pci_write_msi_msg(msidesc, &msg);
                        dev_dbg(&dev->dev, "xen: msi bound to pirq=%d\n", pirq);
                } else {
                        dev_dbg(&dev->dev,
@@ -394,14 +394,7 @@ static void xen_teardown_msi_irq(unsigned int irq)
 {
        xen_destroy_irq(irq);
 }
-static u32 xen_nop_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
-{
-        return 0;
-}
-static u32 xen_nop_msix_mask_irq(struct msi_desc *desc, u32 flag)
-{
-        return 0;
-}
 #endif
 int __init pci_xen_init(void)
@@ -425,8 +418,7 @@ int __init pci_xen_init(void)
        x86_msi.setup_msi_irqs = xen_setup_msi_irqs;
        x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
        x86_msi.teardown_msi_irqs = xen_teardown_msi_irqs;
-        x86_msi.msi_mask_irq = xen_nop_msi_mask_irq;
+        pci_msi_ignore_mask = 1;
-        x86_msi.msix_mask_irq = xen_nop_msix_mask_irq;
 #endif
        return 0;
 }
@@ -506,8 +498,7 @@ int __init pci_xen_initial_domain(void)
        x86_msi.setup_msi_irqs = xen_initdom_setup_msi_irqs;
        x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
        x86_msi.restore_msi_irqs = xen_initdom_restore_msi_irqs;
-        x86_msi.msi_mask_irq = xen_nop_msi_mask_irq;
+        pci_msi_ignore_mask = 1;
-        x86_msi.msix_mask_irq = xen_nop_msix_mask_irq;
 #endif
        xen_setup_acpi_sci();
        __acpi_register_gsi = acpi_register_gsi_xen;
diff --git a/arch/x86/platform/efi/efi_64.c b/arch/x86/platform/efi/efi_64.c
index 35aecb6042fb..17e80d829df0 100644
--- a/arch/x86/platform/efi/efi_64.c
+++ b/arch/x86/platform/efi/efi_64.c
@@ -48,8 +48,7 @@ static unsigned long efi_flags __initdata;
 * We allocate runtime services regions bottom-up, starting from -4G, i.e.
 * 0xffff_ffff_0000_0000 and limit EFI VA mapping space to 64G.
 */
-static u64 efi_va       = -4 * (1UL << 30);
+static u64 efi_va = EFI_VA_START;
-#define EFI_VA_END      (-68 * (1UL << 30))
 /*
 * Scratch space used for switching the pagetable in the EFI stub
diff --git a/arch/x86/platform/uv/tlb_uv.c b/arch/x86/platform/uv/tlb_uv.c
index 3968d67d366b..994798548b1a 100644
--- a/arch/x86/platform/uv/tlb_uv.c
+++ b/arch/x86/platform/uv/tlb_uv.c
@@ -1367,23 +1367,25 @@ static int ptc_seq_show(struct seq_file *file, void *data)
        cpu = *(loff_t *)data;
        if (!cpu) {
-                seq_printf(file,
+                seq_puts(file,
-                 "# cpu bauoff sent stime self locals remotes ncpus localhub ");
+                         "# cpu bauoff sent stime self locals remotes ncpus localhub ");
-                seq_printf(file,
+                seq_puts(file, "remotehub numuvhubs numuvhubs16 numuvhubs8 ");
-                        "remotehub numuvhubs numuvhubs16 numuvhubs8 ");
+                seq_puts(file,
-                seq_printf(file,
+                         "numuvhubs4 numuvhubs2 numuvhubs1 dto snacks retries ");
-                        "numuvhubs4 numuvhubs2 numuvhubs1 dto snacks retries ");
+                seq_puts(file,
-                seq_printf(file,
+                         "rok resetp resett giveup sto bz throt disable ");
-                        "rok resetp resett giveup sto bz throt disable ");
+                seq_puts(file,
-                seq_printf(file,
+                         "enable wars warshw warwaits enters ipidis plugged ");
-                        "enable wars warshw warwaits enters ipidis plugged ");
+                seq_puts(file,
-                seq_printf(file,
+                         "ipiover glim cong swack recv rtime all one mult ");
-                        "ipiover glim cong swack recv rtime all one mult ");
+                seq_puts(file, "none retry canc nocan reset rcan\n");
-                seq_printf(file,
-                        "none retry canc nocan reset rcan\n");
        }
        if (cpu < num_possible_cpus() && cpu_online(cpu)) {
                bcp = &per_cpu(bau_control, cpu);
+                if (bcp->nobau) {
+                        seq_printf(file, "cpu %d bau disabled\n", cpu);
+                        return 0;
+                }
                stat = bcp->statp;
                /* source side statistics */
                seq_printf(file,
diff --git a/arch/x86/purgatory/Makefile b/arch/x86/purgatory/Makefile
index f52e033557c9..2c835e356349 100644
--- a/arch/x86/purgatory/Makefile
+++ b/arch/x86/purgatory/Makefile
@@ -24,6 +24,7 @@ quiet_cmd_bin2c = BIN2C   $@
 $(obj)/kexec-purgatory.c: $(obj)/purgatory.ro FORCE
        $(call if_changed,bin2c)
+        @:
 obj-$(CONFIG_KEXEC_FILE)        += kexec-purgatory.o
diff --git a/arch/x86/tools/insn_sanity.c b/arch/x86/tools/insn_sanity.c
index 872eb60e7806..ba70ff232917 100644
--- a/arch/x86/tools/insn_sanity.c
+++ b/arch/x86/tools/insn_sanity.c
@@ -254,7 +254,7 @@ int main(int argc, char **argv)
                        continue;
                /* Decode an instruction */
-                insn_init(&insn, insn_buf, x86_64);
+                insn_init(&insn, insn_buf, sizeof(insn_buf), x86_64);
                insn_get_length(&insn);
                if (insn.next_byte <= insn.kaddr ||
diff --git a/arch/x86/tools/relocs.c b/arch/x86/tools/relocs.c
index a5efb21d5228..0c2fae8d929d 100644
--- a/arch/x86/tools/relocs.c
+++ b/arch/x86/tools/relocs.c
@@ -20,7 +20,10 @@ struct relocs {
 static struct relocs relocs16;
 static struct relocs relocs32;
+#if ELF_BITS == 64
+static struct relocs relocs32neg;
 static struct relocs relocs64;
+#endif
 struct section {
        Elf_Shdr       shdr;
@@ -762,11 +765,16 @@ static int do_reloc64(struct section *sec, Elf_Rel *rel, ElfW(Sym) *sym,
        switch (r_type) {
        case R_X86_64_NONE:
+                /* NONE can be ignored. */
+                break;
        case R_X86_64_PC32:
                /*
-                 * NONE can be ignored and PC relative relocations don't
+                 * PC relative relocations don't need to be adjusted unless
-                 * need to be adjusted.
+                 * referencing a percpu symbol.
                 */
+                if (is_percpu_sym(sym, symname))
+                        add_reloc(&relocs32neg, offset);
                break;
        case R_X86_64_32:
@@ -986,7 +994,10 @@ static void emit_relocs(int as_text, int use_real_mode)
        /* Order the relocations for more efficient processing */
        sort_relocs(&relocs16);
        sort_relocs(&relocs32);
+#if ELF_BITS == 64
+        sort_relocs(&relocs32neg);
        sort_relocs(&relocs64);
+#endif
        /* Print the relocations */
        if (as_text) {
@@ -1007,14 +1018,21 @@ static void emit_relocs(int as_text, int use_real_mode)
                for (i = 0; i < relocs32.count; i++)
                        write_reloc(relocs32.offset[i], stdout);
        } else {
-                if (ELF_BITS == 64) {
+#if ELF_BITS == 64
-                        /* Print a stop */
+                /* Print a stop */
-                        write_reloc(0, stdout);
+                write_reloc(0, stdout);
-                        /* Now print each relocation */
+                /* Now print each relocation */
-                        for (i = 0; i < relocs64.count; i++)
+                for (i = 0; i < relocs64.count; i++)
-                                write_reloc(relocs64.offset[i], stdout);
+                        write_reloc(relocs64.offset[i], stdout);
-                }
+                /* Print a stop */
+                write_reloc(0, stdout);
+                /* Now print each inverse 32-bit relocation */
+                for (i = 0; i < relocs32neg.count; i++)
+                        write_reloc(relocs32neg.offset[i], stdout);
+#endif
                /* Print a stop */
                write_reloc(0, stdout);
diff --git a/arch/x86/tools/test_get_len.c b/arch/x86/tools/test_get_len.c
index 13403fc95a96..56f04db0c9c0 100644
--- a/arch/x86/tools/test_get_len.c
+++ b/arch/x86/tools/test_get_len.c
@@ -149,7 +149,7 @@ int main(int argc, char **argv)
                                break;
                }
                /* Decode an instruction */
-                insn_init(&insn, insn_buf, x86_64);
+                insn_init(&insn, insn_buf, sizeof(insn_buf), x86_64);
                insn_get_length(&insn);
                if (insn.length != nb) {
                        warnings++;
diff --git a/arch/x86/vdso/vgetcpu.c b/arch/x86/vdso/vgetcpu.c
index 2f94b039e55b..8ec3d1f4ce9a 100644
--- a/arch/x86/vdso/vgetcpu.c
+++ b/arch/x86/vdso/vgetcpu.c
@@ -7,9 +7,7 @@
 #include <linux/kernel.h>
 #include <linux/getcpu.h>
-#include <linux/jiffies.h>
 #include <linux/time.h>
-#include <asm/vsyscall.h>
 #include <asm/vgtod.h>
 notrace long
diff --git a/arch/x86/vdso/vma.c b/arch/x86/vdso/vma.c
index 970463b566cf..009495b9ab4b 100644
--- a/arch/x86/vdso/vma.c
+++ b/arch/x86/vdso/vma.c
@@ -1,7 +1,8 @@
 /*
- * Set up the VMAs to tell the VM about the vDSO.
 * Copyright 2007 Andi Kleen, SUSE Labs.
 * Subject to the GPL, v.2
+ *
+ * This contains most of the x86 vDSO kernel-side code.
 */
 #include <linux/mm.h>
 #include <linux/err.h>
@@ -10,17 +11,17 @@
 #include <linux/init.h>
 #include <linux/random.h>
 #include <linux/elf.h>
-#include <asm/vsyscall.h>
+#include <linux/cpu.h>
 #include <asm/vgtod.h>
 #include <asm/proto.h>
 #include <asm/vdso.h>
+#include <asm/vvar.h>
 #include <asm/page.h>
 #include <asm/hpet.h>
+#include <asm/desc.h>
 #if defined(CONFIG_X86_64)
 unsigned int __read_mostly vdso64_enabled = 1;
-extern unsigned short vdso_sync_cpuid;
 #endif
 void __init init_vdso_image(const struct vdso_image *image)
@@ -38,20 +39,6 @@ void __init init_vdso_image(const struct vdso_image *image)
                                                image->alt_len));
 }
-#if defined(CONFIG_X86_64)
-static int __init init_vdso(void)
-{
-        init_vdso_image(&vdso_image_64);
-#ifdef CONFIG_X86_X32_ABI
-        init_vdso_image(&vdso_image_x32);
-#endif
-        return 0;
-}
-subsys_initcall(init_vdso);
-#endif
 struct linux_binprm;
 /* Put the vdso above the (randomized) stack with another randomized offset.
@@ -238,3 +225,63 @@ static __init int vdso_setup(char *s)
 }
 __setup("vdso=", vdso_setup);
 #endif
+#ifdef CONFIG_X86_64
+static void vgetcpu_cpu_init(void *arg)
+{
+        int cpu = smp_processor_id();
+        struct desc_struct d = { };
+        unsigned long node = 0;
+#ifdef CONFIG_NUMA
+        node = cpu_to_node(cpu);
+#endif
+        if (cpu_has(&cpu_data(cpu), X86_FEATURE_RDTSCP))
+                write_rdtscp_aux((node << 12) | cpu);
+        /*
+         * Store cpu number in limit so that it can be loaded
+         * quickly in user space in vgetcpu. (12 bits for the CPU
+         * and 8 bits for the node)
+         */
+        d.limit0 = cpu | ((node & 0xf) << 12);
+        d.limit = node >> 4;
+        d.type = 5;             /* RO data, expand down, accessed */
+        d.dpl = 3;              /* Visible to user code */
+        d.s = 1;                /* Not a system segment */
+        d.p = 1;                /* Present */
+        d.d = 1;                /* 32-bit */
+        write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_PER_CPU, &d, DESCTYPE_S);
+}
+static int
+vgetcpu_cpu_notifier(struct notifier_block *n, unsigned long action, void *arg)
+{
+        long cpu = (long)arg;
+        if (action == CPU_ONLINE || action == CPU_ONLINE_FROZEN)
+                smp_call_function_single(cpu, vgetcpu_cpu_init, NULL, 1);
+        return NOTIFY_DONE;
+}
+static int __init init_vdso(void)
+{
+        init_vdso_image(&vdso_image_64);
+#ifdef CONFIG_X86_X32_ABI
+        init_vdso_image(&vdso_image_x32);
+#endif
+        cpu_notifier_register_begin();
+        on_each_cpu(vgetcpu_cpu_init, NULL, 1);
+        /* notifier priority > KVM */
+        __hotcpu_notifier(vgetcpu_cpu_notifier, 30);
+        cpu_notifier_register_done();
+        return 0;
+}
+subsys_initcall(init_vdso);
+#endif /* CONFIG_X86_64 */
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index fac5e4f9607c..6bf3a13e3e0f 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -1100,12 +1100,6 @@ static int xen_write_msr_safe(unsigned int msr, unsigned low, unsigned high)
                /* Fast syscall setup is all done in hypercalls, so
                   these are all ignored.  Stub them out here to stop
                   Xen console noise. */
-                break;
-        case MSR_IA32_CR_PAT:
-                if (smp_processor_id() == 0)
-                        xen_set_pat(((u64)high << 32) | low);
-                break;
        default:
                ret = native_write_msr_safe(msr, low, high);
@@ -1561,10 +1555,6 @@ asmlinkage __visible void __init xen_start_kernel(void)
        /* Prevent unwanted bits from being set in PTEs. */
        __supported_pte_mask &= ~_PAGE_GLOBAL;
-#if 0
-        if (!xen_initial_domain())
-#endif
-                __supported_pte_mask &= ~(_PAGE_PWT | _PAGE_PCD);
        /*
         * Prevent page tables from being allocated in highmem, even
@@ -1618,14 +1608,6 @@ asmlinkage __visible void __init xen_start_kernel(void)
         */
        acpi_numa = -1;
 #endif
-#ifdef CONFIG_X86_PAT
-        /*
-         * For right now disable the PAT. We should remove this once
-         * git commit 8eaffa67b43e99ae581622c5133e20b0f48bcef1
-         * (xen/pat: Disable PAT support for now) is reverted.
-         */
-        pat_enabled = 0;
-#endif
        /* Don't do the full vcpu_info placement stuff until we have a
           possible map and a non-dummy shared_info. */
        per_cpu(xen_vcpu, 0) = &HYPERVISOR_shared_info->vcpu_info[0];
@@ -1636,6 +1618,13 @@ asmlinkage __visible void __init xen_start_kernel(void)
        xen_raw_console_write("mapping kernel into physical memory\n");
        xen_setup_kernel_pagetable((pgd_t *)xen_start_info->pt_base, xen_start_info->nr_pages);
+        /*
+         * Modify the cache mode translation tables to match Xen's PAT
+         * configuration.
+         */
+        pat_init_cache_modes();
        /* keep using Xen gdt for now; no urgent need to change it */
 #ifdef CONFIG_X86_32
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index a8a1a3d08d4d..8c8298d78185 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -410,13 +410,7 @@ static pteval_t pte_pfn_to_mfn(pteval_t val)
 __visible pteval_t xen_pte_val(pte_t pte)
 {
        pteval_t pteval = pte.pte;
-#if 0
-        /* If this is a WC pte, convert back from Xen WC to Linux WC */
-        if ((pteval & (_PAGE_PAT | _PAGE_PCD | _PAGE_PWT)) == _PAGE_PAT) {
-                WARN_ON(!pat_enabled);
-                pteval = (pteval & ~_PAGE_PAT) | _PAGE_PWT;
-        }
-#endif
        return pte_mfn_to_pfn(pteval);
 }
 PV_CALLEE_SAVE_REGS_THUNK(xen_pte_val);
@@ -427,47 +421,8 @@ __visible pgdval_t xen_pgd_val(pgd_t pgd)
 }
 PV_CALLEE_SAVE_REGS_THUNK(xen_pgd_val);
-/*
- * Xen's PAT setup is part of its ABI, though I assume entries 6 & 7
- * are reserved for now, to correspond to the Intel-reserved PAT
- * types.
- *
- * We expect Linux's PAT set as follows:
- *
- * Idx  PTE flags        Linux    Xen    Default
- * 0                     WB       WB     WB
- * 1            PWT      WC       WT     WT
- * 2        PCD          UC-      UC-    UC-
- * 3        PCD PWT      UC       UC     UC
- * 4    PAT              WB       WC     WB
- * 5    PAT     PWT      WC       WP     WT
- * 6    PAT PCD          UC-      rsv    UC-
- * 7    PAT PCD PWT      UC       rsv    UC
- */
-void xen_set_pat(u64 pat)
-{
-        /* We expect Linux to use a PAT setting of
-         * UC UC- WC WB (ignoring the PAT flag) */
-        WARN_ON(pat != 0x0007010600070106ull);
-}
 __visible pte_t xen_make_pte(pteval_t pte)
 {
-#if 0
-        /* If Linux is trying to set a WC pte, then map to the Xen WC.
-         * If _PAGE_PAT is set, then it probably means it is really
-         * _PAGE_PSE, so avoid fiddling with the PAT mapping and hope
-         * things work out OK...
-         *
-         * (We should never see kernel mappings with _PAGE_PSE set,
-         * but we could see hugetlbfs mappings, I think.).
-         */
-        if (pat_enabled && !WARN_ON(pte & _PAGE_PAT)) {
-                if ((pte & (_PAGE_PCD | _PAGE_PWT)) == _PAGE_PWT)
-                        pte = (pte & ~(_PAGE_PCD | _PAGE_PWT)) | _PAGE_PAT;
-        }
-#endif
        pte = pte_pfn_to_mfn(pte);
        return native_make_pte(pte);
@@ -1457,8 +1412,10 @@ static int xen_pgd_alloc(struct mm_struct *mm)
                page->private = (unsigned long)user_pgd;
                if (user_pgd != NULL) {
+#ifdef CONFIG_X86_VSYSCALL_EMULATION
                        user_pgd[pgd_index(VSYSCALL_ADDR)] =
                                __pgd(__pa(level3_user_vsyscall) | _PAGE_TABLE);
+#endif
                        ret = 0;
                }
@@ -2021,7 +1978,7 @@ static void xen_set_fixmap(unsigned idx, phys_addr_t phys, pgprot_t prot)
 # ifdef CONFIG_HIGHMEM
        case FIX_KMAP_BEGIN ... FIX_KMAP_END:
 # endif
-#else
+#elif defined(CONFIG_X86_VSYSCALL_EMULATION)
        case VSYSCALL_PAGE:
 #endif
        case FIX_TEXT_POKE0:
@@ -2060,7 +2017,7 @@ static void xen_set_fixmap(unsigned idx, phys_addr_t phys, pgprot_t prot)
        __native_set_fixmap(idx, pte);
-#ifdef CONFIG_X86_64
+#ifdef CONFIG_X86_VSYSCALL_EMULATION
        /* Replicate changes to map the vsyscall page into the user
           pagetable vsyscall mapping. */
        if (idx == VSYSCALL_PAGE) {
diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h
index 28c7e0be56e4..4ab9298c5e17 100644
--- a/arch/x86/xen/xen-ops.h
+++ b/arch/x86/xen/xen-ops.h
@@ -33,7 +33,6 @@ extern unsigned long xen_max_p2m_pfn;
 void xen_mm_pin_all(void);
 void xen_mm_unpin_all(void);
-void xen_set_pat(u64);
 char * __init xen_memory_setup(void);
 char * xen_auto_xlated_memory_setup(void);
diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h
index 74944207167e..fe1600a09438 100644
--- a/arch/xtensa/include/asm/io.h
+++ b/arch/xtensa/include/asm/io.h
@@ -74,13 +74,6 @@ static inline void iounmap(volatile void __iomem *addr)
 #endif /* CONFIG_MMU */
-/*
- * Generic I/O
- */
-#define readb_relaxed readb
-#define readw_relaxed readw
-#define readl_relaxed readl
 #endif  /* __KERNEL__ */
 #include <asm-generic/io.h>