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-rw-r--r--arch/sh/cchips/Kconfig33
-rw-r--r--arch/sh/cchips/hd6446x/Makefile1
-rw-r--r--arch/sh/cchips/hd6446x/hd64465/Makefile6
-rw-r--r--arch/sh/cchips/hd6446x/hd64465/gpio.c196
-rw-r--r--arch/sh/cchips/hd6446x/hd64465/io.c211
-rw-r--r--arch/sh/cchips/hd6446x/hd64465/setup.c181
-rw-r--r--arch/sh/include/asm/hd64465/gpio.h46
-rw-r--r--arch/sh/include/asm/hd64465/hd64465.h256
-rw-r--r--arch/sh/include/asm/hd64465/io.h44
-rw-r--r--arch/sh/include/asm/serial.h17
-rw-r--r--arch/sh/tools/mach-types1
11 files changed, 0 insertions, 992 deletions
diff --git a/arch/sh/cchips/Kconfig b/arch/sh/cchips/Kconfig
index 7892361eedc8..f43d18373f22 100644
--- a/arch/sh/cchips/Kconfig
+++ b/arch/sh/cchips/Kconfig
@@ -22,20 +22,6 @@ config HD64461
22 Say Y if you want support for the HD64461. 22 Say Y if you want support for the HD64461.
23 Otherwise, say N. 23 Otherwise, say N.
24 24
25config HD64465
26 bool "Hitachi HD64465 companion chip support"
27 ---help---
28 The Hitachi HD64465 provides an interface for
29 the SH7750 CPU, supporting a LCD controller,
30 CRT color controller, IrDA, USB, PCMCIA,
31 keyboard controller, and a printer interface.
32
33 More information is available at
34 <http://global.hitachi.com/New/cnews/E/1998/981019B.html>.
35
36 Say Y if you want support for the HD64465.
37 Otherwise, say N.
38
39endchoice 25endchoice
40 26
41# These will also be split into the Kconfig's below 27# These will also be split into the Kconfig's below
@@ -61,23 +47,4 @@ config HD64461_ENABLER
61 via the HD64461 companion chip. 47 via the HD64461 companion chip.
62 Otherwise, say N. 48 Otherwise, say N.
63 49
64config HD64465_IOBASE
65 hex "HD64465 start address"
66 depends on HD64465
67 default "0xb0000000"
68 help
69 The default setting of the HD64465 IO base address is 0xb0000000.
70
71 Do not change this unless you know what you are doing.
72
73config HD64465_IRQ
74 int "HD64465 IRQ"
75 depends on HD64465
76 default "5"
77 help
78 The default setting of the HD64465 IRQ is 5.
79
80 Do not change this unless you know what you are doing.
81
82endmenu 50endmenu
83
diff --git a/arch/sh/cchips/hd6446x/Makefile b/arch/sh/cchips/hd6446x/Makefile
index f7de4076e242..9682e3ab668f 100644
--- a/arch/sh/cchips/hd6446x/Makefile
+++ b/arch/sh/cchips/hd6446x/Makefile
@@ -1,4 +1,3 @@
1obj-$(CONFIG_HD64461) += hd64461.o 1obj-$(CONFIG_HD64461) += hd64461.o
2obj-$(CONFIG_HD64465) += hd64465/
3 2
4EXTRA_CFLAGS += -Werror 3EXTRA_CFLAGS += -Werror
diff --git a/arch/sh/cchips/hd6446x/hd64465/Makefile b/arch/sh/cchips/hd6446x/hd64465/Makefile
deleted file mode 100644
index f66edcb52c5b..000000000000
--- a/arch/sh/cchips/hd6446x/hd64465/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
1#
2# Makefile for the HD64465
3#
4
5obj-y := setup.o io.o gpio.o
6
diff --git a/arch/sh/cchips/hd6446x/hd64465/gpio.c b/arch/sh/cchips/hd6446x/hd64465/gpio.c
deleted file mode 100644
index 43431855ec86..000000000000
--- a/arch/sh/cchips/hd6446x/hd64465/gpio.c
+++ /dev/null
@@ -1,196 +0,0 @@
1/*
2 * $Id: gpio.c,v 1.4 2003/05/19 22:24:18 lethal Exp $
3 * by Greg Banks <gbanks@pocketpenguins.com>
4 * (c) 2000 PocketPenguins Inc
5 *
6 * GPIO pin support for HD64465 companion chip.
7 */
8
9#include <linux/kernel.h>
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/sched.h>
13#include <linux/ioport.h>
14#include <asm/io.h>
15#include <asm/hd64465/gpio.h>
16
17#define _PORTOF(portpin) (((portpin)>>3)&0x7)
18#define _PINOF(portpin) ((portpin)&0x7)
19
20/* Register addresses parametrised on port */
21#define GPIO_CR(port) (HD64465_REG_GPACR+((port)<<1))
22#define GPIO_DR(port) (HD64465_REG_GPADR+((port)<<1))
23#define GPIO_ICR(port) (HD64465_REG_GPAICR+((port)<<1))
24#define GPIO_ISR(port) (HD64465_REG_GPAISR+((port)<<1))
25
26#define GPIO_NPORTS 5
27
28#define MODNAME "hd64465_gpio"
29
30EXPORT_SYMBOL(hd64465_gpio_configure);
31EXPORT_SYMBOL(hd64465_gpio_get_pin);
32EXPORT_SYMBOL(hd64465_gpio_get_port);
33EXPORT_SYMBOL(hd64465_gpio_register_irq);
34EXPORT_SYMBOL(hd64465_gpio_set_pin);
35EXPORT_SYMBOL(hd64465_gpio_set_port);
36EXPORT_SYMBOL(hd64465_gpio_unregister_irq);
37
38/* TODO: each port should be protected with a spinlock */
39
40
41void hd64465_gpio_configure(int portpin, int direction)
42{
43 unsigned short cr;
44 unsigned int shift = (_PINOF(portpin)<<1);
45
46 cr = inw(GPIO_CR(_PORTOF(portpin)));
47 cr &= ~(3<<shift);
48 cr |= direction<<shift;
49 outw(cr, GPIO_CR(_PORTOF(portpin)));
50}
51
52void hd64465_gpio_set_pin(int portpin, unsigned int value)
53{
54 unsigned short d;
55 unsigned short mask = 1<<(_PINOF(portpin));
56
57 d = inw(GPIO_DR(_PORTOF(portpin)));
58 if (value)
59 d |= mask;
60 else
61 d &= ~mask;
62 outw(d, GPIO_DR(_PORTOF(portpin)));
63}
64
65unsigned int hd64465_gpio_get_pin(int portpin)
66{
67 return inw(GPIO_DR(_PORTOF(portpin))) & (1<<(_PINOF(portpin)));
68}
69
70/* TODO: for cleaner atomicity semantics, add a mask to this routine */
71
72void hd64465_gpio_set_port(int port, unsigned int value)
73{
74 outw(value, GPIO_DR(port));
75}
76
77unsigned int hd64465_gpio_get_port(int port)
78{
79 return inw(GPIO_DR(port));
80}
81
82
83static struct {
84 void (*func)(int portpin, void *dev);
85 void *dev;
86} handlers[GPIO_NPORTS * 8];
87
88static irqreturn_t hd64465_gpio_interrupt(int irq, void *dev)
89{
90 unsigned short port, pin, isr, mask, portpin;
91
92 for (port=0 ; port<GPIO_NPORTS ; port++) {
93 isr = inw(GPIO_ISR(port));
94
95 for (pin=0 ; pin<8 ; pin++) {
96 mask = 1<<pin;
97 if (isr & mask) {
98 portpin = (port<<3)|pin;
99 if (handlers[portpin].func != 0)
100 handlers[portpin].func(portpin, handlers[portpin].dev);
101 else
102 printk(KERN_NOTICE "unexpected GPIO interrupt, pin %c%d\n",
103 port+'A', (int)pin);
104 }
105 }
106
107 /* Write 1s back to ISR to clear it? That's what the manual says.. */
108 outw(isr, GPIO_ISR(port));
109 }
110
111 return IRQ_HANDLED;
112}
113
114void hd64465_gpio_register_irq(int portpin, int mode,
115 void (*handler)(int portpin, void *dev), void *dev)
116{
117 unsigned long flags;
118 unsigned short icr, mask;
119
120 if (handler == 0)
121 return;
122
123 local_irq_save(flags);
124
125 handlers[portpin].func = handler;
126 handlers[portpin].dev = dev;
127
128 /*
129 * Configure Interrupt Control Register
130 */
131 icr = inw(GPIO_ICR(_PORTOF(portpin)));
132 mask = (1<<_PINOF(portpin));
133
134 /* unmask interrupt */
135 icr &= ~mask;
136
137 /* set TS bit */
138 mask <<= 8;
139 icr &= ~mask;
140 if (mode == HD64465_GPIO_RISING)
141 icr |= mask;
142
143 outw(icr, GPIO_ICR(_PORTOF(portpin)));
144
145 local_irq_restore(flags);
146}
147
148void hd64465_gpio_unregister_irq(int portpin)
149{
150 unsigned long flags;
151 unsigned short icr;
152
153 local_irq_save(flags);
154
155 /*
156 * Configure Interrupt Control Register
157 */
158 icr = inw(GPIO_ICR(_PORTOF(portpin)));
159 icr |= (1<<_PINOF(portpin)); /* mask interrupt */
160 outw(icr, GPIO_ICR(_PORTOF(portpin)));
161
162 handlers[portpin].func = 0;
163 handlers[portpin].dev = 0;
164
165 local_irq_restore(flags);
166}
167
168static int __init hd64465_gpio_init(void)
169{
170 if (!request_region(HD64465_REG_GPACR, 0x1000, MODNAME))
171 return -EBUSY;
172 if (request_irq(HD64465_IRQ_GPIO, hd64465_gpio_interrupt,
173 IRQF_DISABLED, MODNAME, 0))
174 goto out_irqfailed;
175
176 printk("HD64465 GPIO layer on irq %d\n", HD64465_IRQ_GPIO);
177
178 return 0;
179
180out_irqfailed:
181 release_region(HD64465_REG_GPACR, 0x1000);
182
183 return -EINVAL;
184}
185
186static void __exit hd64465_gpio_exit(void)
187{
188 release_region(HD64465_REG_GPACR, 0x1000);
189 free_irq(HD64465_IRQ_GPIO, 0);
190}
191
192module_init(hd64465_gpio_init);
193module_exit(hd64465_gpio_exit);
194
195MODULE_LICENSE("GPL");
196
diff --git a/arch/sh/cchips/hd6446x/hd64465/io.c b/arch/sh/cchips/hd6446x/hd64465/io.c
deleted file mode 100644
index 58704d066ae2..000000000000
--- a/arch/sh/cchips/hd6446x/hd64465/io.c
+++ /dev/null
@@ -1,211 +0,0 @@
1/*
2 * $Id: io.c,v 1.4 2003/08/03 03:05:10 lethal Exp $
3 * by Greg Banks <gbanks@pocketpenguins.com>
4 * (c) 2000 PocketPenguins Inc
5 *
6 * Derived from io_hd64461.c, which bore the message:
7 * Copyright (C) 2000 YAEGASHI Takeshi
8 *
9 * Typical I/O routines for HD64465 system.
10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <asm/io.h>
15#include <asm/hd64465/hd64465.h>
16
17
18#define HD64465_DEBUG 0
19
20#if HD64465_DEBUG
21#define DPRINTK(args...) printk(args)
22#define DIPRINTK(n, args...) if (hd64465_io_debug>(n)) printk(args)
23#else
24#define DPRINTK(args...)
25#define DIPRINTK(n, args...)
26#endif
27
28
29
30/* This is a hack suitable only for debugging IO port problems */
31int hd64465_io_debug;
32EXPORT_SYMBOL(hd64465_io_debug);
33
34/* Low iomap maps port 0-1K to addresses in 8byte chunks */
35#define HD64465_IOMAP_LO_THRESH 0x400
36#define HD64465_IOMAP_LO_SHIFT 3
37#define HD64465_IOMAP_LO_MASK ((1<<HD64465_IOMAP_LO_SHIFT)-1)
38#define HD64465_IOMAP_LO_NMAP (HD64465_IOMAP_LO_THRESH>>HD64465_IOMAP_LO_SHIFT)
39static unsigned long hd64465_iomap_lo[HD64465_IOMAP_LO_NMAP];
40static unsigned char hd64465_iomap_lo_shift[HD64465_IOMAP_LO_NMAP];
41
42/* High iomap maps port 1K-64K to addresses in 1K chunks */
43#define HD64465_IOMAP_HI_THRESH 0x10000
44#define HD64465_IOMAP_HI_SHIFT 10
45#define HD64465_IOMAP_HI_MASK ((1<<HD64465_IOMAP_HI_SHIFT)-1)
46#define HD64465_IOMAP_HI_NMAP (HD64465_IOMAP_HI_THRESH>>HD64465_IOMAP_HI_SHIFT)
47static unsigned long hd64465_iomap_hi[HD64465_IOMAP_HI_NMAP];
48static unsigned char hd64465_iomap_hi_shift[HD64465_IOMAP_HI_NMAP];
49
50#define PORT2ADDR(x) (sh_mv.mv_isa_port2addr(x))
51
52void hd64465_port_map(unsigned short baseport, unsigned int nports,
53 unsigned long addr, unsigned char shift)
54{
55 unsigned int port, endport = baseport + nports;
56
57 DPRINTK("hd64465_port_map(base=0x%04hx, n=0x%04hx, addr=0x%08lx,endport=0x%04x)\n",
58 baseport, nports, addr,endport);
59
60 for (port = baseport ;
61 port < endport && port < HD64465_IOMAP_LO_THRESH ;
62 port += (1<<HD64465_IOMAP_LO_SHIFT)) {
63 DPRINTK(" maplo[0x%x] = 0x%08lx\n", port, addr);
64 hd64465_iomap_lo[port>>HD64465_IOMAP_LO_SHIFT] = addr;
65 hd64465_iomap_lo_shift[port>>HD64465_IOMAP_LO_SHIFT] = shift;
66 addr += (1<<(HD64465_IOMAP_LO_SHIFT));
67 }
68
69 for (port = max_t(unsigned int, baseport, HD64465_IOMAP_LO_THRESH);
70 port < endport && port < HD64465_IOMAP_HI_THRESH ;
71 port += (1<<HD64465_IOMAP_HI_SHIFT)) {
72 DPRINTK(" maphi[0x%x] = 0x%08lx\n", port, addr);
73 hd64465_iomap_hi[port>>HD64465_IOMAP_HI_SHIFT] = addr;
74 hd64465_iomap_hi_shift[port>>HD64465_IOMAP_HI_SHIFT] = shift;
75 addr += (1<<(HD64465_IOMAP_HI_SHIFT));
76 }
77}
78EXPORT_SYMBOL(hd64465_port_map);
79
80void hd64465_port_unmap(unsigned short baseport, unsigned int nports)
81{
82 unsigned int port, endport = baseport + nports;
83
84 DPRINTK("hd64465_port_unmap(base=0x%04hx, n=0x%04hx)\n",
85 baseport, nports);
86
87 for (port = baseport ;
88 port < endport && port < HD64465_IOMAP_LO_THRESH ;
89 port += (1<<HD64465_IOMAP_LO_SHIFT)) {
90 hd64465_iomap_lo[port>>HD64465_IOMAP_LO_SHIFT] = 0;
91 }
92
93 for (port = max_t(unsigned int, baseport, HD64465_IOMAP_LO_THRESH);
94 port < endport && port < HD64465_IOMAP_HI_THRESH ;
95 port += (1<<HD64465_IOMAP_HI_SHIFT)) {
96 hd64465_iomap_hi[port>>HD64465_IOMAP_HI_SHIFT] = 0;
97 }
98}
99EXPORT_SYMBOL(hd64465_port_unmap);
100
101unsigned long hd64465_isa_port2addr(unsigned long port)
102{
103 unsigned long addr = 0;
104 unsigned char shift;
105
106 /* handle remapping of low IO ports */
107 if (port < HD64465_IOMAP_LO_THRESH) {
108 addr = hd64465_iomap_lo[port >> HD64465_IOMAP_LO_SHIFT];
109 shift = hd64465_iomap_lo_shift[port >> HD64465_IOMAP_LO_SHIFT];
110 if (addr != 0)
111 addr += (port & HD64465_IOMAP_LO_MASK) << shift;
112 else
113 printk(KERN_NOTICE "io_hd64465: access to un-mapped port %lx\n", port);
114 } else if (port < HD64465_IOMAP_HI_THRESH) {
115 addr = hd64465_iomap_hi[port >> HD64465_IOMAP_HI_SHIFT];
116 shift = hd64465_iomap_hi_shift[port >> HD64465_IOMAP_HI_SHIFT];
117 if (addr != 0)
118 addr += (port & HD64465_IOMAP_HI_MASK) << shift;
119 else
120 printk(KERN_NOTICE "io_hd64465: access to un-mapped port %lx\n", port);
121 }
122
123 /* HD64465 internal devices (0xb0000000) */
124 else if (port < 0x20000)
125 addr = CONFIG_HD64465_IOBASE + port - 0x10000;
126
127 /* Whole physical address space (0xa0000000) */
128 else
129 addr = P2SEGADDR(port);
130
131 DIPRINTK(2, "PORT2ADDR(0x%08lx) = 0x%08lx\n", port, addr);
132
133 return addr;
134}
135
136static inline void delay(void)
137{
138 ctrl_inw(0xa0000000);
139}
140
141unsigned char hd64465_inb(unsigned long port)
142{
143 unsigned long addr = PORT2ADDR(port);
144 unsigned long b = (addr == 0 ? 0 : *(volatile unsigned char*)addr);
145
146 DIPRINTK(0, "inb(%08lx) = %02x\n", addr, (unsigned)b);
147 return b;
148}
149
150unsigned char hd64465_inb_p(unsigned long port)
151{
152 unsigned long v;
153 unsigned long addr = PORT2ADDR(port);
154
155 v = (addr == 0 ? 0 : *(volatile unsigned char*)addr);
156 delay();
157 DIPRINTK(0, "inb_p(%08lx) = %02x\n", addr, (unsigned)v);
158 return v;
159}
160
161unsigned short hd64465_inw(unsigned long port)
162{
163 unsigned long addr = PORT2ADDR(port);
164 unsigned long b = (addr == 0 ? 0 : *(volatile unsigned short*)addr);
165 DIPRINTK(0, "inw(%08lx) = %04lx\n", addr, b);
166 return b;
167}
168
169unsigned int hd64465_inl(unsigned long port)
170{
171 unsigned long addr = PORT2ADDR(port);
172 unsigned int b = (addr == 0 ? 0 : *(volatile unsigned long*)addr);
173 DIPRINTK(0, "inl(%08lx) = %08x\n", addr, b);
174 return b;
175}
176
177void hd64465_outb(unsigned char b, unsigned long port)
178{
179 unsigned long addr = PORT2ADDR(port);
180
181 DIPRINTK(0, "outb(%02x, %08lx)\n", (unsigned)b, addr);
182 if (addr != 0)
183 *(volatile unsigned char*)addr = b;
184}
185
186void hd64465_outb_p(unsigned char b, unsigned long port)
187{
188 unsigned long addr = PORT2ADDR(port);
189
190 DIPRINTK(0, "outb_p(%02x, %08lx)\n", (unsigned)b, addr);
191 if (addr != 0)
192 *(volatile unsigned char*)addr = b;
193 delay();
194}
195
196void hd64465_outw(unsigned short b, unsigned long port)
197{
198 unsigned long addr = PORT2ADDR(port);
199 DIPRINTK(0, "outw(%04x, %08lx)\n", (unsigned)b, addr);
200 if (addr != 0)
201 *(volatile unsigned short*)addr = b;
202}
203
204void hd64465_outl(unsigned int b, unsigned long port)
205{
206 unsigned long addr = PORT2ADDR(port);
207 DIPRINTK(0, "outl(%08x, %08lx)\n", b, addr);
208 if (addr != 0)
209 *(volatile unsigned long*)addr = b;
210}
211
diff --git a/arch/sh/cchips/hd6446x/hd64465/setup.c b/arch/sh/cchips/hd6446x/hd64465/setup.c
deleted file mode 100644
index 9b8820c36701..000000000000
--- a/arch/sh/cchips/hd6446x/hd64465/setup.c
+++ /dev/null
@@ -1,181 +0,0 @@
1/*
2 * $Id: setup.c,v 1.4 2003/08/03 03:05:10 lethal Exp $
3 *
4 * Setup and IRQ handling code for the HD64465 companion chip.
5 * by Greg Banks <gbanks@pocketpenguins.com>
6 * Copyright (c) 2000 PocketPenguins Inc
7 *
8 * Derived from setup_hd64461.c which bore the message:
9 * Copyright (C) 2000 YAEGASHI Takeshi
10 */
11
12#include <linux/sched.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/param.h>
16#include <linux/ioport.h>
17#include <linux/interrupt.h>
18#include <linux/init.h>
19#include <linux/irq.h>
20#include <asm/io.h>
21#include <asm/irq.h>
22#include <asm/hd64465/hd64465.h>
23
24static void disable_hd64465_irq(unsigned int irq)
25{
26 unsigned short nimr;
27 unsigned short mask = 1 << (irq - HD64465_IRQ_BASE);
28
29 pr_debug("disable_hd64465_irq(%d): mask=%x\n", irq, mask);
30 nimr = inw(HD64465_REG_NIMR);
31 nimr |= mask;
32 outw(nimr, HD64465_REG_NIMR);
33}
34
35static void enable_hd64465_irq(unsigned int irq)
36{
37 unsigned short nimr;
38 unsigned short mask = 1 << (irq - HD64465_IRQ_BASE);
39
40 pr_debug("enable_hd64465_irq(%d): mask=%x\n", irq, mask);
41 nimr = inw(HD64465_REG_NIMR);
42 nimr &= ~mask;
43 outw(nimr, HD64465_REG_NIMR);
44}
45
46static void mask_and_ack_hd64465(unsigned int irq)
47{
48 disable_hd64465_irq(irq);
49}
50
51static void end_hd64465_irq(unsigned int irq)
52{
53 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
54 enable_hd64465_irq(irq);
55}
56
57static unsigned int startup_hd64465_irq(unsigned int irq)
58{
59 enable_hd64465_irq(irq);
60 return 0;
61}
62
63static void shutdown_hd64465_irq(unsigned int irq)
64{
65 disable_hd64465_irq(irq);
66}
67
68static struct hw_interrupt_type hd64465_irq_type = {
69 .typename = "HD64465-IRQ",
70 .startup = startup_hd64465_irq,
71 .shutdown = shutdown_hd64465_irq,
72 .enable = enable_hd64465_irq,
73 .disable = disable_hd64465_irq,
74 .ack = mask_and_ack_hd64465,
75 .end = end_hd64465_irq,
76};
77
78static irqreturn_t hd64465_interrupt(int irq, void *dev_id)
79{
80 printk(KERN_INFO
81 "HD64465: spurious interrupt, nirr: 0x%x nimr: 0x%x\n",
82 inw(HD64465_REG_NIRR), inw(HD64465_REG_NIMR));
83
84 return IRQ_NONE;
85}
86
87/*
88 * Support for a secondary IRQ demux step. This is necessary
89 * because the HD64465 presents a very thin interface to the
90 * PCMCIA bus; a lot of features (such as remapping interrupts)
91 * normally done in hardware by other PCMCIA host bridges is
92 * instead done in software.
93 */
94static struct {
95 int (*func)(int, void *);
96 void *dev;
97} hd64465_demux[HD64465_IRQ_NUM];
98
99void hd64465_register_irq_demux(int irq,
100 int (*demux)(int irq, void *dev), void *dev)
101{
102 hd64465_demux[irq - HD64465_IRQ_BASE].func = demux;
103 hd64465_demux[irq - HD64465_IRQ_BASE].dev = dev;
104}
105EXPORT_SYMBOL(hd64465_register_irq_demux);
106
107void hd64465_unregister_irq_demux(int irq)
108{
109 hd64465_demux[irq - HD64465_IRQ_BASE].func = 0;
110}
111EXPORT_SYMBOL(hd64465_unregister_irq_demux);
112
113int hd64465_irq_demux(int irq)
114{
115 if (irq == CONFIG_HD64465_IRQ) {
116 unsigned short i, bit;
117 unsigned short nirr = inw(HD64465_REG_NIRR);
118 unsigned short nimr = inw(HD64465_REG_NIMR);
119
120 pr_debug("hd64465_irq_demux, nirr=%04x, nimr=%04x\n", nirr, nimr);
121 nirr &= ~nimr;
122 for (bit = 1, i = 0 ; i < HD64465_IRQ_NUM ; bit <<= 1, i++)
123 if (nirr & bit)
124 break;
125
126 if (i < HD64465_IRQ_NUM) {
127 irq = HD64465_IRQ_BASE + i;
128 if (hd64465_demux[i].func != 0)
129 irq = hd64465_demux[i].func(irq, hd64465_demux[i].dev);
130 }
131 }
132 return irq;
133}
134
135static struct irqaction irq0 = {
136 .handler = hd64465_interrupt,
137 .flags = IRQF_DISABLED,
138 .mask = CPU_MASK_NONE,
139 .name = "HD64465",
140};
141
142static int __init setup_hd64465(void)
143{
144 int i;
145 unsigned short rev;
146 unsigned short smscr;
147
148 if (!MACH_HD64465)
149 return 0;
150
151 printk(KERN_INFO "HD64465 configured at 0x%x on irq %d(mapped into %d to %d)\n",
152 CONFIG_HD64465_IOBASE,
153 CONFIG_HD64465_IRQ,
154 HD64465_IRQ_BASE,
155 HD64465_IRQ_BASE+HD64465_IRQ_NUM-1);
156
157 if (inw(HD64465_REG_SDID) != HD64465_SDID) {
158 printk(KERN_ERR "HD64465 device ID not found, check base address\n");
159 }
160
161 rev = inw(HD64465_REG_SRR);
162 printk(KERN_INFO "HD64465 hardware revision %d.%d\n", (rev >> 8) & 0xff, rev & 0xff);
163
164 outw(0xffff, HD64465_REG_NIMR); /* mask all interrupts */
165
166 for (i = 0; i < HD64465_IRQ_NUM ; i++) {
167 irq_desc[HD64465_IRQ_BASE + i].chip = &hd64465_irq_type;
168 }
169
170 setup_irq(CONFIG_HD64465_IRQ, &irq0);
171
172 /* wake up the UART from STANDBY at this point */
173 smscr = inw(HD64465_REG_SMSCR);
174 outw(smscr & (~HD64465_SMSCR_UARTST), HD64465_REG_SMSCR);
175
176 /* remap IO ports for first ISA serial port to HD64465 UART */
177 hd64465_port_map(0x3f8, 8, CONFIG_HD64465_IOBASE + 0x8000, 1);
178
179 return 0;
180}
181module_init(setup_hd64465);
diff --git a/arch/sh/include/asm/hd64465/gpio.h b/arch/sh/include/asm/hd64465/gpio.h
deleted file mode 100644
index a3cdca2713dd..000000000000
--- a/arch/sh/include/asm/hd64465/gpio.h
+++ /dev/null
@@ -1,46 +0,0 @@
1#ifndef _ASM_SH_HD64465_GPIO_
2#define _ASM_SH_HD64465_GPIO_ 1
3/*
4 * $Id: gpio.h,v 1.3 2003/05/04 19:30:14 lethal Exp $
5 *
6 * Hitachi HD64465 companion chip: General Purpose IO pins support.
7 * This layer enables other device drivers to configure GPIO
8 * pins, get and set their values, and register an interrupt
9 * routine for when input pins change in hardware.
10 *
11 * by Greg Banks <gbanks@pocketpenguins.com>
12 * (c) 2000 PocketPenguins Inc.
13 */
14#include <asm/hd64465.h>
15
16/* Macro to construct a portpin number (used in all
17 * subsequent functions) from a port letter and a pin
18 * number, e.g. HD64465_GPIO_PORTPIN('A', 5).
19 */
20#define HD64465_GPIO_PORTPIN(port,pin) (((port)-'A')<<3|(pin))
21
22/* Pin configuration constants for _configure() */
23#define HD64465_GPIO_FUNCTION2 0 /* use the pin's *other* function */
24#define HD64465_GPIO_OUT 1 /* output */
25#define HD64465_GPIO_IN_PULLUP 2 /* input, pull-up MOS on */
26#define HD64465_GPIO_IN 3 /* input */
27
28/* Configure a pin's direction */
29extern void hd64465_gpio_configure(int portpin, int direction);
30
31/* Get, set value */
32extern void hd64465_gpio_set_pin(int portpin, unsigned int value);
33extern unsigned int hd64465_gpio_get_pin(int portpin);
34extern void hd64465_gpio_set_port(int port, unsigned int value);
35extern unsigned int hd64465_gpio_get_port(int port);
36
37/* mode constants for _register_irq() */
38#define HD64465_GPIO_FALLING 0
39#define HD64465_GPIO_RISING 1
40
41/* Interrupt on external value change */
42extern void hd64465_gpio_register_irq(int portpin, int mode,
43 void (*handler)(int portpin, void *dev), void *dev);
44extern void hd64465_gpio_unregister_irq(int portpin);
45
46#endif /* _ASM_SH_HD64465_GPIO_ */
diff --git a/arch/sh/include/asm/hd64465/hd64465.h b/arch/sh/include/asm/hd64465/hd64465.h
deleted file mode 100644
index cfd0e803d2a2..000000000000
--- a/arch/sh/include/asm/hd64465/hd64465.h
+++ /dev/null
@@ -1,256 +0,0 @@
1#ifndef _ASM_SH_HD64465_
2#define _ASM_SH_HD64465_ 1
3/*
4 * $Id: hd64465.h,v 1.3 2003/05/04 19:30:15 lethal Exp $
5 *
6 * Hitachi HD64465 companion chip support
7 *
8 * by Greg Banks <gbanks@pocketpenguins.com>
9 * (c) 2000 PocketPenguins Inc.
10 *
11 * Derived from <asm/hd64461.h> which bore the message:
12 * Copyright (C) 2000 YAEGASHI Takeshi
13 */
14#include <asm/io.h>
15#include <asm/irq.h>
16
17/*
18 * Note that registers are defined here as virtual port numbers,
19 * which have no meaning except to get translated by hd64465_isa_port2addr()
20 * to an address in the range 0xb0000000-0xb3ffffff. Note that
21 * this translation happens to consist of adding the lower 16 bits
22 * of the virtual port number to 0xb0000000. Note also that the manual
23 * shows addresses as absolute physical addresses starting at 0x10000000,
24 * so e.g. the NIRR register is listed as 0x15000 here, 0x10005000 in the
25 * manual, and accessed using address 0xb0005000 - Greg.
26 */
27
28/* System registers */
29#define HD64465_REG_SRR 0x1000c /* System Revision Register */
30#define HD64465_REG_SDID 0x10010 /* System Device ID Reg */
31#define HD64465_SDID 0x8122 /* 64465 device ID */
32
33/* Power Management registers */
34#define HD64465_REG_SMSCR 0x10000 /* System Module Standby Control Reg */
35#define HD64465_SMSCR_PS2ST 0x4000 /* PS/2 Standby */
36#define HD64465_SMSCR_ADCST 0x1000 /* ADC Standby */
37#define HD64465_SMSCR_UARTST 0x0800 /* UART Standby */
38#define HD64465_SMSCR_SCDIST 0x0200 /* Serial Codec Standby */
39#define HD64465_SMSCR_PPST 0x0100 /* Parallel Port Standby */
40#define HD64465_SMSCR_PC0ST 0x0040 /* PCMCIA0 Standby */
41#define HD64465_SMSCR_PC1ST 0x0020 /* PCMCIA1 Standby */
42#define HD64465_SMSCR_AFEST 0x0010 /* AFE Standby */
43#define HD64465_SMSCR_TM0ST 0x0008 /* Timer0 Standby */
44#define HD64465_SMSCR_TM1ST 0x0004 /* Timer1 Standby */
45#define HD64465_SMSCR_IRDAST 0x0002 /* IRDA Standby */
46#define HD64465_SMSCR_KBCST 0x0001 /* Keyboard Controller Standby */
47
48/* Interrupt Controller registers */
49#define HD64465_REG_NIRR 0x15000 /* Interrupt Request Register */
50#define HD64465_REG_NIMR 0x15002 /* Interrupt Mask Register */
51#define HD64465_REG_NITR 0x15004 /* Interrupt Trigger Mode Register */
52
53/* Timer registers */
54#define HD64465_REG_TCVR1 0x16000 /* Timer 1 constant value register */
55#define HD64465_REG_TCVR0 0x16002 /* Timer 0 constant value register */
56#define HD64465_REG_TRVR1 0x16004 /* Timer 1 read value register */
57#define HD64465_REG_TRVR0 0x16006 /* Timer 0 read value register */
58#define HD64465_REG_TCR1 0x16008 /* Timer 1 control register */
59#define HD64465_REG_TCR0 0x1600A /* Timer 0 control register */
60#define HD64465_TCR_EADT 0x10 /* Enable ADTRIG# signal */
61#define HD64465_TCR_ETMO 0x08 /* Enable TMO signal */
62#define HD64465_TCR_PST_MASK 0x06 /* Clock Prescale */
63#define HD64465_TCR_PST_1 0x06 /* 1:1 */
64#define HD64465_TCR_PST_4 0x04 /* 1:4 */
65#define HD64465_TCR_PST_8 0x02 /* 1:8 */
66#define HD64465_TCR_PST_16 0x00 /* 1:16 */
67#define HD64465_TCR_TSTP 0x01 /* Start/Stop timer */
68#define HD64465_REG_TIRR 0x1600C /* Timer interrupt request register */
69#define HD64465_REG_TIDR 0x1600E /* Timer interrupt disable register */
70#define HD64465_REG_PWM1CS 0x16010 /* PWM 1 clock scale register */
71#define HD64465_REG_PWM1LPC 0x16012 /* PWM 1 low pulse width counter register */
72#define HD64465_REG_PWM1HPC 0x16014 /* PWM 1 high pulse width counter register */
73#define HD64465_REG_PWM0CS 0x16018 /* PWM 0 clock scale register */
74#define HD64465_REG_PWM0LPC 0x1601A /* PWM 0 low pulse width counter register */
75#define HD64465_REG_PWM0HPC 0x1601C /* PWM 0 high pulse width counter register */
76
77/* Analog/Digital Converter registers */
78#define HD64465_REG_ADDRA 0x1E000 /* A/D data register A */
79#define HD64465_REG_ADDRB 0x1E002 /* A/D data register B */
80#define HD64465_REG_ADDRC 0x1E004 /* A/D data register C */
81#define HD64465_REG_ADDRD 0x1E006 /* A/D data register D */
82#define HD64465_REG_ADCSR 0x1E008 /* A/D control/status register */
83#define HD64465_ADCSR_ADF 0x80 /* A/D End Flag */
84#define HD64465_ADCSR_ADST 0x40 /* A/D Start Flag */
85#define HD64465_ADCSR_ADIS 0x20 /* A/D Interrupt Status */
86#define HD64465_ADCSR_TRGE 0x10 /* A/D Trigger Enable */
87#define HD64465_ADCSR_ADIE 0x08 /* A/D Interrupt Enable */
88#define HD64465_ADCSR_SCAN 0x04 /* A/D Scan Mode */
89#define HD64465_ADCSR_CH_MASK 0x03 /* A/D Channel */
90#define HD64465_REG_ADCALCR 0x1E00A /* A/D calibration sample control */
91#define HD64465_REG_ADCAL 0x1E00C /* A/D calibration data register */
92
93
94/* General Purpose I/O ports registers */
95#define HD64465_REG_GPACR 0x14000 /* Port A Control Register */
96#define HD64465_REG_GPBCR 0x14002 /* Port B Control Register */
97#define HD64465_REG_GPCCR 0x14004 /* Port C Control Register */
98#define HD64465_REG_GPDCR 0x14006 /* Port D Control Register */
99#define HD64465_REG_GPECR 0x14008 /* Port E Control Register */
100#define HD64465_REG_GPADR 0x14010 /* Port A Data Register */
101#define HD64465_REG_GPBDR 0x14012 /* Port B Data Register */
102#define HD64465_REG_GPCDR 0x14014 /* Port C Data Register */
103#define HD64465_REG_GPDDR 0x14016 /* Port D Data Register */
104#define HD64465_REG_GPEDR 0x14018 /* Port E Data Register */
105#define HD64465_REG_GPAICR 0x14020 /* Port A Interrupt Control Register */
106#define HD64465_REG_GPBICR 0x14022 /* Port B Interrupt Control Register */
107#define HD64465_REG_GPCICR 0x14024 /* Port C Interrupt Control Register */
108#define HD64465_REG_GPDICR 0x14026 /* Port D Interrupt Control Register */
109#define HD64465_REG_GPEICR 0x14028 /* Port E Interrupt Control Register */
110#define HD64465_REG_GPAISR 0x14040 /* Port A Interrupt Status Register */
111#define HD64465_REG_GPBISR 0x14042 /* Port B Interrupt Status Register */
112#define HD64465_REG_GPCISR 0x14044 /* Port C Interrupt Status Register */
113#define HD64465_REG_GPDISR 0x14046 /* Port D Interrupt Status Register */
114#define HD64465_REG_GPEISR 0x14048 /* Port E Interrupt Status Register */
115
116/* PCMCIA bridge interface */
117#define HD64465_REG_PCC0ISR 0x12000 /* socket 0 interface status */
118#define HD64465_PCCISR_PREADY 0x80 /* mem card ready / io card IREQ */
119#define HD64465_PCCISR_PIREQ 0x80
120#define HD64465_PCCISR_PMWP 0x40 /* mem card write-protected */
121#define HD64465_PCCISR_PVS2 0x20 /* voltage select pin 2 */
122#define HD64465_PCCISR_PVS1 0x10 /* voltage select pin 1 */
123#define HD64465_PCCISR_PCD_MASK 0x0c /* card detect */
124#define HD64465_PCCISR_PBVD_MASK 0x03 /* battery voltage */
125#define HD64465_PCCISR_PBVD_BATGOOD 0x03 /* battery good */
126#define HD64465_PCCISR_PBVD_BATWARN 0x01 /* battery low warning */
127#define HD64465_PCCISR_PBVD_BATDEAD1 0x02 /* battery dead */
128#define HD64465_PCCISR_PBVD_BATDEAD2 0x00 /* battery dead */
129#define HD64465_REG_PCC0GCR 0x12002 /* socket 0 general control */
130#define HD64465_PCCGCR_PDRV 0x80 /* output drive */
131#define HD64465_PCCGCR_PCCR 0x40 /* PC card reset */
132#define HD64465_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */
133#define HD64465_PCCGCR_PVCC0 0x10 /* voltage control pin VCC0SEL0 */
134#define HD64465_PCCGCR_PMMOD 0x08 /* memory mode */
135#define HD64465_PCCGCR_PPA25 0x04 /* pin A25 */
136#define HD64465_PCCGCR_PPA24 0x02 /* pin A24 */
137#define HD64465_PCCGCR_PREG 0x01 /* ping PCC0REG# */
138#define HD64465_REG_PCC0CSCR 0x12004 /* socket 0 card status change */
139#define HD64465_PCCCSCR_PSCDI 0x80 /* sw card detect intr */
140#define HD64465_PCCCSCR_PSWSEL 0x40 /* power select */
141#define HD64465_PCCCSCR_PIREQ 0x20 /* IREQ intr req */
142#define HD64465_PCCCSCR_PSC 0x10 /* STSCHG (status change) pin */
143#define HD64465_PCCCSCR_PCDC 0x08 /* CD (card detect) change */
144#define HD64465_PCCCSCR_PRC 0x04 /* ready change */
145#define HD64465_PCCCSCR_PBW 0x02 /* battery warning change */
146#define HD64465_PCCCSCR_PBD 0x01 /* battery dead change */
147#define HD64465_REG_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */
148#define HD64465_PCCCSCIER_PCRE 0x80 /* change reset enable */
149#define HD64465_PCCCSCIER_PIREQE_MASK 0x60 /* IREQ enable */
150#define HD64465_PCCCSCIER_PIREQE_DISABLED 0x00 /* IREQ disabled */
151#define HD64465_PCCCSCIER_PIREQE_LEVEL 0x20 /* IREQ level-triggered */
152#define HD64465_PCCCSCIER_PIREQE_FALLING 0x40 /* IREQ falling-edge-trig */
153#define HD64465_PCCCSCIER_PIREQE_RISING 0x60 /* IREQ rising-edge-trig */
154#define HD64465_PCCCSCIER_PSCE 0x10 /* status change enable */
155#define HD64465_PCCCSCIER_PCDE 0x08 /* card detect change enable */
156#define HD64465_PCCCSCIER_PRE 0x04 /* ready change enable */
157#define HD64465_PCCCSCIER_PBWE 0x02 /* battery warn change enable */
158#define HD64465_PCCCSCIER_PBDE 0x01 /* battery dead change enable*/
159#define HD64465_REG_PCC0SCR 0x12008 /* socket 0 software control */
160#define HD64465_PCCSCR_SHDN 0x10 /* TPS2206 SHutDowN pin */
161#define HD64465_PCCSCR_SWP 0x01 /* write protect */
162#define HD64465_REG_PCCPSR 0x1200A /* serial power switch control */
163#define HD64465_REG_PCC1ISR 0x12010 /* socket 1 interface status */
164#define HD64465_REG_PCC1GCR 0x12012 /* socket 1 general control */
165#define HD64465_REG_PCC1CSCR 0x12014 /* socket 1 card status change */
166#define HD64465_REG_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */
167#define HD64465_REG_PCC1SCR 0x12018 /* socket 1 software control */
168
169
170/* PS/2 Keyboard and mouse controller -- *not* register compatible */
171#define HD64465_REG_KBCSR 0x1dc00 /* Keyboard Control/Status reg */
172#define HD64465_KBCSR_KBCIE 0x8000 /* KBCK Input Enable */
173#define HD64465_KBCSR_KBCOE 0x4000 /* KBCK Output Enable */
174#define HD64465_KBCSR_KBDOE 0x2000 /* KB DATA Output Enable */
175#define HD64465_KBCSR_KBCD 0x1000 /* KBCK Driven */
176#define HD64465_KBCSR_KBDD 0x0800 /* KB DATA Driven */
177#define HD64465_KBCSR_KBCS 0x0400 /* KBCK pin Status */
178#define HD64465_KBCSR_KBDS 0x0200 /* KB DATA pin Status */
179#define HD64465_KBCSR_KBDP 0x0100 /* KB DATA Parity bit */
180#define HD64465_KBCSR_KBD_MASK 0x00ff /* KD DATA shift reg */
181#define HD64465_REG_KBISR 0x1dc04 /* Keyboard Interrupt Status reg */
182#define HD64465_KBISR_KBRDF 0x0001 /* KB Received Data Full */
183#define HD64465_REG_MSCSR 0x1dc10 /* Mouse Control/Status reg */
184#define HD64465_REG_MSISR 0x1dc14 /* Mouse Interrupt Status reg */
185
186
187/*
188 * Logical address at which the HD64465 is mapped. Note that this
189 * should always be in the P2 segment (uncached and untranslated).
190 */
191#ifndef CONFIG_HD64465_IOBASE
192#define CONFIG_HD64465_IOBASE 0xb0000000
193#endif
194/*
195 * The HD64465 multiplexes all its modules' interrupts onto
196 * this single interrupt.
197 */
198#ifndef CONFIG_HD64465_IRQ
199#define CONFIG_HD64465_IRQ 5
200#endif
201
202
203#define _HD64465_IO_MASK 0xf8000000
204#define is_hd64465_addr(addr) \
205 ((addr & _HD64465_IO_MASK) == (CONFIG_HD64465_IOBASE & _HD64465_IO_MASK))
206
207/*
208 * A range of 16 virtual interrupts generated by
209 * demuxing the HD64465 muxed interrupt.
210 */
211#define HD64465_IRQ_BASE OFFCHIP_IRQ_BASE
212#define HD64465_IRQ_NUM 16
213#define HD64465_IRQ_ADC (HD64465_IRQ_BASE+0)
214#define HD64465_IRQ_USB (HD64465_IRQ_BASE+1)
215#define HD64465_IRQ_SCDI (HD64465_IRQ_BASE+2)
216#define HD64465_IRQ_PARALLEL (HD64465_IRQ_BASE+3)
217/* bit 4 is reserved */
218#define HD64465_IRQ_UART (HD64465_IRQ_BASE+5)
219#define HD64465_IRQ_IRDA (HD64465_IRQ_BASE+6)
220#define HD64465_IRQ_PS2MOUSE (HD64465_IRQ_BASE+7)
221#define HD64465_IRQ_KBC (HD64465_IRQ_BASE+8)
222#define HD64465_IRQ_TIMER1 (HD64465_IRQ_BASE+9)
223#define HD64465_IRQ_TIMER0 (HD64465_IRQ_BASE+10)
224#define HD64465_IRQ_GPIO (HD64465_IRQ_BASE+11)
225#define HD64465_IRQ_AFE (HD64465_IRQ_BASE+12)
226#define HD64465_IRQ_PCMCIA1 (HD64465_IRQ_BASE+13)
227#define HD64465_IRQ_PCMCIA0 (HD64465_IRQ_BASE+14)
228#define HD64465_IRQ_PS2KBD (HD64465_IRQ_BASE+15)
229
230/* Constants for PCMCIA mappings */
231#define HD64465_PCC_WINDOW 0x01000000
232
233#define HD64465_PCC0_BASE 0xb8000000 /* area 6 */
234#define HD64465_PCC0_ATTR (HD64465_PCC0_BASE)
235#define HD64465_PCC0_COMM (HD64465_PCC0_BASE+HD64465_PCC_WINDOW)
236#define HD64465_PCC0_IO (HD64465_PCC0_BASE+2*HD64465_PCC_WINDOW)
237
238#define HD64465_PCC1_BASE 0xb4000000 /* area 5 */
239#define HD64465_PCC1_ATTR (HD64465_PCC1_BASE)
240#define HD64465_PCC1_COMM (HD64465_PCC1_BASE+HD64465_PCC_WINDOW)
241#define HD64465_PCC1_IO (HD64465_PCC1_BASE+2*HD64465_PCC_WINDOW)
242
243/*
244 * Base of USB controller interface (as memory)
245 */
246#define HD64465_USB_BASE (CONFIG_HD64465_IOBASE+0xb000)
247#define HD64465_USB_LEN 0x1000
248/*
249 * Base of embedded SRAM, used for USB controller.
250 */
251#define HD64465_SRAM_BASE (CONFIG_HD64465_IOBASE+0x9000)
252#define HD64465_SRAM_LEN 0x1000
253
254
255
256#endif /* _ASM_SH_HD64465_ */
diff --git a/arch/sh/include/asm/hd64465/io.h b/arch/sh/include/asm/hd64465/io.h
deleted file mode 100644
index 139f1472e5bb..000000000000
--- a/arch/sh/include/asm/hd64465/io.h
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * include/asm-sh/hd64465/io.h
3 *
4 * By Greg Banks <gbanks@pocketpenguins.com>
5 * (c) 2000 PocketPenguins Inc.
6 *
7 * Derived from io_hd64461.h, which bore the message:
8 * Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
9 *
10 * May be copied or modified under the terms of the GNU General Public
11 * License. See linux/COPYING for more information.
12 *
13 * IO functions for an HD64465 "Windows CE Intelligent Peripheral Controller".
14 */
15
16#ifndef _ASM_SH_IO_HD64465_H
17#define _ASM_SH_IO_HD64465_H
18
19extern unsigned char hd64465_inb(unsigned long port);
20extern unsigned short hd64465_inw(unsigned long port);
21extern unsigned int hd64465_inl(unsigned long port);
22
23extern void hd64465_outb(unsigned char value, unsigned long port);
24extern void hd64465_outw(unsigned short value, unsigned long port);
25extern void hd64465_outl(unsigned int value, unsigned long port);
26
27extern unsigned char hd64465_inb_p(unsigned long port);
28extern void hd64465_outb_p(unsigned char value, unsigned long port);
29
30extern unsigned long hd64465_isa_port2addr(unsigned long offset);
31extern int hd64465_irq_demux(int irq);
32/* Provision for generic secondary demux step -- used by PCMCIA code */
33extern void hd64465_register_irq_demux(int irq,
34 int (*demux)(int irq, void *dev), void *dev);
35extern void hd64465_unregister_irq_demux(int irq);
36/* Set this variable to 1 to see port traffic */
37extern int hd64465_io_debug;
38/* Map a range of ports to a range of kernel virtual memory.
39 */
40extern void hd64465_port_map(unsigned short baseport, unsigned int nports,
41 unsigned long addr, unsigned char shift);
42extern void hd64465_port_unmap(unsigned short baseport, unsigned int nports);
43
44#endif /* _ASM_SH_IO_HD64465_H */
diff --git a/arch/sh/include/asm/serial.h b/arch/sh/include/asm/serial.h
index e13cc948ee60..11f854dd1363 100644
--- a/arch/sh/include/asm/serial.h
+++ b/arch/sh/include/asm/serial.h
@@ -7,8 +7,6 @@
7#ifndef _ASM_SERIAL_H 7#ifndef _ASM_SERIAL_H
8#define _ASM_SERIAL_H 8#define _ASM_SERIAL_H
9 9
10#include <linux/kernel.h>
11
12/* 10/*
13 * This assumes you have a 1.8432 MHz clock for your UART. 11 * This assumes you have a 1.8432 MHz clock for your UART.
14 * 12 *
@@ -18,19 +16,4 @@
18 */ 16 */
19#define BASE_BAUD ( 1843200 / 16 ) 17#define BASE_BAUD ( 1843200 / 16 )
20 18
21#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
22
23#ifdef CONFIG_HD64465
24#include <asm/hd64465/hd64465.h>
25
26#define SERIAL_PORT_DFNS \
27 /* UART CLK PORT IRQ FLAGS */ \
28 { 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS } /* ttyS0 */
29
30#else
31
32#define SERIAL_PORT_DFNS
33
34#endif
35
36#endif /* _ASM_SERIAL_H */ 19#endif /* _ASM_SERIAL_H */
diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types
index d4fb11f7e2ee..d0c2928d1066 100644
--- a/arch/sh/tools/mach-types
+++ b/arch/sh/tools/mach-types
@@ -13,7 +13,6 @@ RTS7751R2D SH_RTS7751R2D
13# List of companion chips / MFDs. 13# List of companion chips / MFDs.
14# 14#
15HD64461 HD64461 15HD64461 HD64461
16HD64465 HD64465
17 16
18# 17#
19# List of boards. 18# List of boards.
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 06:51:21 -0500