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-rw-r--r--arch/arm/include/asm/cacheflush.h5
-rw-r--r--arch/arm/kernel/signal.c41
-rw-r--r--arch/arm/kernel/signal.h4
-rw-r--r--arch/arm/kernel/traps.c4
-rw-r--r--arch/arm/kernel/unwind.c9
-rw-r--r--arch/arm/mach-at91/include/mach/cpu.h9
-rw-r--r--arch/arm/mach-integrator/include/mach/memory.h1
-rw-r--r--arch/arm/mach-realview/core.h2
-rw-r--r--arch/arm/mach-realview/include/mach/board-pb1176.h5
-rw-r--r--arch/arm/mach-realview/include/mach/board-pb11mp.h12
-rw-r--r--arch/arm/mach-realview/include/mach/platform.h15
-rw-r--r--arch/arm/mach-realview/include/mach/system.h10
-rw-r--r--arch/arm/mach-realview/realview_pb1176.c11
-rw-r--r--arch/arm/mach-realview/realview_pb11mp.c16
-rw-r--r--arch/arm/mach-s3c2410/gpio.c1
-rw-r--r--arch/arm/mach-s3c2410/include/mach/dma.h7
-rw-r--r--arch/arm/mach-s3c2440/Kconfig1
-rw-r--r--arch/arm/mach-s3c2440/mach-mini2440.c4
-rw-r--r--arch/arm/mach-s3c6400/include/mach/dma.h5
-rw-r--r--arch/arm/mm/context.c5
-rw-r--r--arch/arm/mm/dma-mapping.c4
-rw-r--r--arch/arm/mm/flush.c31
-rw-r--r--arch/arm/mm/init.c20
-rw-r--r--arch/arm/mm/mmu.c7
-rw-r--r--arch/arm/mm/proc-v6.S7
-rw-r--r--arch/arm/mm/proc-v7.S7
-rw-r--r--arch/arm/plat-s3c24xx/adc.c2
-rw-r--r--arch/arm/plat-s3c24xx/cpu.c10
-rw-r--r--arch/arm/plat-s3c24xx/dma.c6
-rw-r--r--arch/arm/plat-s3c24xx/gpio.c1
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h9
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/s3c2410.h1
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/regs-clock.h4
-rw-r--r--arch/arm/plat-s3c64xx/s3c6400-clock.c3
-rw-r--r--arch/avr32/mach-at32ap/include/mach/cpu.h3
-rw-r--r--arch/ia64/include/asm/spinlock.h62
-rw-r--r--arch/ia64/include/asm/spinlock_types.h2
-rw-r--r--arch/ia64/kernel/mca.c104
-rw-r--r--arch/ia64/kernel/unaligned.c6
-rw-r--r--arch/ia64/mm/tlb.c24
-rw-r--r--arch/ia64/pci/pci.c9
-rw-r--r--arch/ia64/sn/kernel/io_common.c8
-rw-r--r--arch/ia64/sn/kernel/sn2/sn_hwperf.c7
-rw-r--r--arch/m32r/Kconfig3
-rw-r--r--arch/m32r/boot/compressed/Makefile18
-rw-r--r--arch/m32r/boot/compressed/misc.c143
-rw-r--r--arch/m32r/kernel/smp.c2
-rw-r--r--arch/m32r/kernel/time.c6
-rw-r--r--arch/m32r/kernel/vmlinux.lds.S2
-rw-r--r--arch/m68k/Kconfig6
-rw-r--r--arch/mips/Kconfig4
-rw-r--r--arch/mips/alchemy/common/irq.c34
-rw-r--r--arch/mips/alchemy/mtx-1/board_setup.c3
-rw-r--r--arch/mips/ar7/platform.c9
-rw-r--r--arch/mips/bcm63xx/Makefile2
-rw-r--r--arch/mips/bcm63xx/boards/board_bcm963xx.c3
-rw-r--r--arch/mips/bcm63xx/cpu.c3
-rw-r--r--arch/mips/bcm63xx/dev-uart.c2
-rw-r--r--arch/mips/bcm63xx/dev-wdt.c37
-rw-r--r--arch/mips/bcm63xx/setup.c4
-rw-r--r--arch/mips/cavium-octeon/octeon-irq.c224
-rw-r--r--arch/mips/cavium-octeon/smp.c5
-rw-r--r--arch/mips/include/asm/fixmap.h4
-rw-r--r--arch/mips/include/asm/gcmpregs.h18
-rw-r--r--arch/mips/include/asm/gic.h188
-rw-r--r--arch/mips/include/asm/mach-ar7/ar7.h3
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio-au1000.h2
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h6
-rw-r--r--arch/mips/include/asm/mach-ip27/topology.h4
-rw-r--r--arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h3
-rw-r--r--arch/mips/include/asm/mmu_context.h13
-rw-r--r--arch/mips/include/asm/setup.h2
-rw-r--r--arch/mips/include/asm/smtc_ipi.h1
-rw-r--r--arch/mips/include/asm/spram.h10
-rw-r--r--arch/mips/include/asm/thread_info.h9
-rw-r--r--arch/mips/jazz/irq.c2
-rw-r--r--arch/mips/kernel/cevt-bcm1480.c2
-rw-r--r--arch/mips/kernel/cevt-ds1287.c2
-rw-r--r--arch/mips/kernel/cevt-gt641xx.c2
-rw-r--r--arch/mips/kernel/cevt-r4k.c2
-rw-r--r--arch/mips/kernel/cevt-sb1250.c2
-rw-r--r--arch/mips/kernel/cevt-txx9.c2
-rw-r--r--arch/mips/kernel/cpu-probe.c8
-rw-r--r--arch/mips/kernel/head.S1
-rw-r--r--arch/mips/kernel/i8253.c2
-rw-r--r--arch/mips/kernel/irq-gic.c114
-rw-r--r--arch/mips/kernel/linux32.c6
-rw-r--r--arch/mips/kernel/scall64-o32.S4
-rw-r--r--arch/mips/kernel/smtc.c34
-rw-r--r--arch/mips/kernel/spram.c5
-rw-r--r--arch/mips/kernel/vpe.c2
-rw-r--r--arch/mips/loongson/common/irq.c1
-rw-r--r--arch/mips/math-emu/dp_simple.c13
-rw-r--r--arch/mips/math-emu/sp_simple.c11
-rw-r--r--arch/mips/mm/init.c6
-rw-r--r--arch/mips/mti-malta/malta-amon.c7
-rw-r--r--arch/mips/mti-malta/malta-int.c119
-rw-r--r--arch/mips/mti-malta/malta-pci.c27
-rw-r--r--arch/mips/nxp/pnx8550/common/int.c2
-rw-r--r--arch/mips/nxp/pnx8550/common/time.c4
-rw-r--r--arch/mips/oprofile/op_model_loongson2.c2
-rw-r--r--arch/mips/sgi-ip27/ip27-timer.c2
-rw-r--r--arch/mips/sni/time.c2
-rw-r--r--arch/mips/txx9/generic/setup.c5
-rw-r--r--arch/s390/include/asm/cputime.h6
-rw-r--r--arch/s390/kernel/ipl.c7
-rw-r--r--arch/s390/kernel/smp.c7
-rw-r--r--arch/s390/kernel/swsusp_asm64.S2
-rw-r--r--arch/sh/include/asm/rwsem.h2
-rw-r--r--arch/sh/kernel/dwarf.c2
-rw-r--r--arch/sh/mm/cache-sh4.c5
-rw-r--r--arch/sparc/include/asm/system_64.h4
-rw-r--r--arch/sparc/kernel/prom_common.c4
-rw-r--r--arch/sparc/kernel/visemul.c2
-rw-r--r--arch/x86/Kconfig4
-rw-r--r--arch/x86/Kconfig.cpu2
-rw-r--r--arch/x86/Makefile1
-rw-r--r--arch/x86/ia32/ia32entry.S5
-rw-r--r--arch/x86/include/asm/amd_iommu.h1
-rw-r--r--arch/x86/include/asm/desc.h2
-rw-r--r--arch/x86/include/asm/processor.h2
-rw-r--r--arch/x86/include/asm/topology.h2
-rw-r--r--arch/x86/kernel/amd_iommu.c2
-rw-r--r--arch/x86/kernel/amd_iommu_init.c24
-rw-r--r--arch/x86/kernel/cpu/mtrr/cleanup.c2
-rw-r--r--arch/x86/kernel/crash_dump_32.c19
-rw-r--r--arch/x86/kernel/efi.c2
-rw-r--r--arch/x86/kernel/process_64.c5
-rw-r--r--arch/x86/kernel/reboot.c8
-rw-r--r--arch/x86/kvm/x86.c4
-rw-r--r--arch/x86/xen/enlighten.c11
131 files changed, 1019 insertions, 786 deletions
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index fd03fb63a332..3d0cdd21b882 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -414,9 +414,14 @@ extern void __flush_dcache_page(struct address_space *mapping, struct page *page
414 414
415static inline void __flush_icache_all(void) 415static inline void __flush_icache_all(void)
416{ 416{
417#ifdef CONFIG_ARM_ERRATA_411920
418 extern void v6_icache_inval_all(void);
419 v6_icache_inval_all();
420#else
417 asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n" 421 asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n"
418 : 422 :
419 : "r" (0)); 423 : "r" (0));
424#endif
420} 425}
421 426
422#define ARCH_HAS_FLUSH_ANON_PAGE 427#define ARCH_HAS_FLUSH_ANON_PAGE
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 1423a3419789..2a573d4fea24 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/arch/arm/kernel/signal.c 2 * linux/arch/arm/kernel/signal.c
3 * 3 *
4 * Copyright (C) 1995-2002 Russell King 4 * Copyright (C) 1995-2009 Russell King
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
@@ -29,6 +29,7 @@
29 */ 29 */
30#define SWI_SYS_SIGRETURN (0xef000000|(__NR_sigreturn)|(__NR_OABI_SYSCALL_BASE)) 30#define SWI_SYS_SIGRETURN (0xef000000|(__NR_sigreturn)|(__NR_OABI_SYSCALL_BASE))
31#define SWI_SYS_RT_SIGRETURN (0xef000000|(__NR_rt_sigreturn)|(__NR_OABI_SYSCALL_BASE)) 31#define SWI_SYS_RT_SIGRETURN (0xef000000|(__NR_rt_sigreturn)|(__NR_OABI_SYSCALL_BASE))
32#define SWI_SYS_RESTART (0xef000000|__NR_restart_syscall|__NR_OABI_SYSCALL_BASE)
32 33
33/* 34/*
34 * With EABI, the syscall number has to be loaded into r7. 35 * With EABI, the syscall number has to be loaded into r7.
@@ -49,6 +50,18 @@ const unsigned long sigreturn_codes[7] = {
49}; 50};
50 51
51/* 52/*
53 * Either we support OABI only, or we have EABI with the OABI
54 * compat layer enabled. In the later case we don't know if
55 * user space is EABI or not, and if not we must not clobber r7.
56 * Always using the OABI syscall solves that issue and works for
57 * all those cases.
58 */
59const unsigned long syscall_restart_code[2] = {
60 SWI_SYS_RESTART, /* swi __NR_restart_syscall */
61 0xe49df004, /* ldr pc, [sp], #4 */
62};
63
64/*
52 * atomically swap in the new signal mask, and wait for a signal. 65 * atomically swap in the new signal mask, and wait for a signal.
53 */ 66 */
54asmlinkage int sys_sigsuspend(int restart, unsigned long oldmask, old_sigset_t mask) 67asmlinkage int sys_sigsuspend(int restart, unsigned long oldmask, old_sigset_t mask)
@@ -645,32 +658,12 @@ static void do_signal(struct pt_regs *regs, int syscall)
645 regs->ARM_pc -= 4; 658 regs->ARM_pc -= 4;
646#else 659#else
647 u32 __user *usp; 660 u32 __user *usp;
648 u32 swival = __NR_restart_syscall;
649 661
650 regs->ARM_sp -= 12; 662 regs->ARM_sp -= 4;
651 usp = (u32 __user *)regs->ARM_sp; 663 usp = (u32 __user *)regs->ARM_sp;
652 664
653 /* 665 put_user(regs->ARM_pc, usp);
654 * Either we supports OABI only, or we have 666 regs->ARM_pc = KERN_RESTART_CODE;
655 * EABI with the OABI compat layer enabled.
656 * In the later case we don't know if user
657 * space is EABI or not, and if not we must
658 * not clobber r7. Always using the OABI
659 * syscall solves that issue and works for
660 * all those cases.
661 */
662 swival = swival - __NR_SYSCALL_BASE + __NR_OABI_SYSCALL_BASE;
663
664 put_user(regs->ARM_pc, &usp[0]);
665 /* swi __NR_restart_syscall */
666 put_user(0xef000000 | swival, &usp[1]);
667 /* ldr pc, [sp], #12 */
668 put_user(0xe49df00c, &usp[2]);
669
670 flush_icache_range((unsigned long)usp,
671 (unsigned long)(usp + 3));
672
673 regs->ARM_pc = regs->ARM_sp + 4;
674#endif 667#endif
675 } 668 }
676 } 669 }
diff --git a/arch/arm/kernel/signal.h b/arch/arm/kernel/signal.h
index 27beece15502..6fcfe8398aa4 100644
--- a/arch/arm/kernel/signal.h
+++ b/arch/arm/kernel/signal.h
@@ -1,12 +1,14 @@
1/* 1/*
2 * linux/arch/arm/kernel/signal.h 2 * linux/arch/arm/kernel/signal.h
3 * 3 *
4 * Copyright (C) 2005 Russell King. 4 * Copyright (C) 2005-2009 Russell King.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10#define KERN_SIGRETURN_CODE (CONFIG_VECTORS_BASE + 0x00000500) 10#define KERN_SIGRETURN_CODE (CONFIG_VECTORS_BASE + 0x00000500)
11#define KERN_RESTART_CODE (KERN_SIGRETURN_CODE + sizeof(sigreturn_codes))
11 12
12extern const unsigned long sigreturn_codes[7]; 13extern const unsigned long sigreturn_codes[7];
14extern const unsigned long syscall_restart_code[2];
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index f838f36eb702..95718a6b50a6 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/arch/arm/kernel/traps.c 2 * linux/arch/arm/kernel/traps.c
3 * 3 *
4 * Copyright (C) 1995-2002 Russell King 4 * Copyright (C) 1995-2009 Russell King
5 * Fragments that appear the same as linux/arch/i386/kernel/traps.c (C) Linus Torvalds 5 * Fragments that appear the same as linux/arch/i386/kernel/traps.c (C) Linus Torvalds
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
@@ -751,6 +751,8 @@ void __init early_trap_init(void)
751 */ 751 */
752 memcpy((void *)KERN_SIGRETURN_CODE, sigreturn_codes, 752 memcpy((void *)KERN_SIGRETURN_CODE, sigreturn_codes,
753 sizeof(sigreturn_codes)); 753 sizeof(sigreturn_codes));
754 memcpy((void *)KERN_RESTART_CODE, syscall_restart_code,
755 sizeof(syscall_restart_code));
754 756
755 flush_icache_range(vectors, vectors + PAGE_SIZE); 757 flush_icache_range(vectors, vectors + PAGE_SIZE);
756 modify_domain(DOMAIN_USER, DOMAIN_CLIENT); 758 modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c
index 39baf1128bfa..786ac2b6914a 100644
--- a/arch/arm/kernel/unwind.c
+++ b/arch/arm/kernel/unwind.c
@@ -26,6 +26,15 @@
26 * http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html 26 * http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html
27 */ 27 */
28 28
29#if !defined (__ARM_EABI__)
30#warning Your compiler does not have EABI support.
31#warning ARM unwind is known to compile only with EABI compilers.
32#warning Change compiler or disable ARM_UNWIND option.
33#elif (__GNUC__ == 4 && __GNUC_MINOR__ <= 2)
34#warning Your compiler is too buggy; it is known to not compile ARM unwind support.
35#warning Change compiler or disable ARM_UNWIND option.
36#endif
37
29#include <linux/kernel.h> 38#include <linux/kernel.h>
30#include <linux/init.h> 39#include <linux/init.h>
31#include <linux/module.h> 40#include <linux/module.h>
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index 34a9502c48bc..c22df30ed5e5 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -25,6 +25,8 @@
25#define ARCH_ID_AT91SAM9G20 0x019905a0 25#define ARCH_ID_AT91SAM9G20 0x019905a0
26#define ARCH_ID_AT91SAM9RL64 0x019b03a0 26#define ARCH_ID_AT91SAM9RL64 0x019b03a0
27#define ARCH_ID_AT91SAM9G45 0x819b05a0 27#define ARCH_ID_AT91SAM9G45 0x819b05a0
28#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */
29#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */
28#define ARCH_ID_AT91CAP9 0x039A03A0 30#define ARCH_ID_AT91CAP9 0x039A03A0
29 31
30#define ARCH_ID_AT91SAM9XE128 0x329973a0 32#define ARCH_ID_AT91SAM9XE128 0x329973a0
@@ -41,6 +43,11 @@ static inline unsigned long at91_cpu_identify(void)
41 return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); 43 return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
42} 44}
43 45
46static inline unsigned long at91_cpu_fully_identify(void)
47{
48 return at91_sys_read(AT91_DBGU_CIDR);
49}
50
44#define ARCH_EXID_AT91SAM9M11 0x00000001 51#define ARCH_EXID_AT91SAM9M11 0x00000001
45#define ARCH_EXID_AT91SAM9M10 0x00000002 52#define ARCH_EXID_AT91SAM9M10 0x00000002
46#define ARCH_EXID_AT91SAM9G45 0x00000004 53#define ARCH_EXID_AT91SAM9G45 0x00000004
@@ -118,8 +125,10 @@ static inline unsigned long at91cap9_rev_identify(void)
118 125
119#ifdef CONFIG_ARCH_AT91SAM9G45 126#ifdef CONFIG_ARCH_AT91SAM9G45
120#define cpu_is_at91sam9g45() (at91_cpu_identify() == ARCH_ID_AT91SAM9G45) 127#define cpu_is_at91sam9g45() (at91_cpu_identify() == ARCH_ID_AT91SAM9G45)
128#define cpu_is_at91sam9g45es() (at91_cpu_fully_identify() == ARCH_ID_AT91SAM9G45ES)
121#else 129#else
122#define cpu_is_at91sam9g45() (0) 130#define cpu_is_at91sam9g45() (0)
131#define cpu_is_at91sam9g45es() (0)
123#endif 132#endif
124 133
125#ifdef CONFIG_ARCH_AT91CAP9 134#ifdef CONFIG_ARCH_AT91CAP9
diff --git a/arch/arm/mach-integrator/include/mach/memory.h b/arch/arm/mach-integrator/include/mach/memory.h
index 2b2e7a110724..4891828454f5 100644
--- a/arch/arm/mach-integrator/include/mach/memory.h
+++ b/arch/arm/mach-integrator/include/mach/memory.h
@@ -28,5 +28,6 @@
28#define BUS_OFFSET UL(0x80000000) 28#define BUS_OFFSET UL(0x80000000)
29#define __virt_to_bus(x) ((x) - PAGE_OFFSET + BUS_OFFSET) 29#define __virt_to_bus(x) ((x) - PAGE_OFFSET + BUS_OFFSET)
30#define __bus_to_virt(x) ((x) - BUS_OFFSET + PAGE_OFFSET) 30#define __bus_to_virt(x) ((x) - BUS_OFFSET + PAGE_OFFSET)
31#define __pfn_to_bus(x) (((x) << PAGE_SHIFT) + BUS_OFFSET)
31 32
32#endif 33#endif
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index 46cd6acb4d40..699671fa6e0b 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -61,5 +61,5 @@ extern void realview_timer_init(unsigned int timer_irq);
61extern int realview_flash_register(struct resource *res, u32 num); 61extern int realview_flash_register(struct resource *res, u32 num);
62extern int realview_eth_register(const char *name, struct resource *res); 62extern int realview_eth_register(const char *name, struct resource *res);
63extern int realview_usb_register(struct resource *res); 63extern int realview_usb_register(struct resource *res);
64 64extern void (*realview_reset)(char);
65#endif 65#endif
diff --git a/arch/arm/mach-realview/include/mach/board-pb1176.h b/arch/arm/mach-realview/include/mach/board-pb1176.h
index 98f8e7eeacc2..34b80b7d40b8 100644
--- a/arch/arm/mach-realview/include/mach/board-pb1176.h
+++ b/arch/arm/mach-realview/include/mach/board-pb1176.h
@@ -73,4 +73,9 @@
73#define REALVIEW_PB1176_GIC_DIST_BASE 0x10041000 /* GIC distributor, on FPGA */ 73#define REALVIEW_PB1176_GIC_DIST_BASE 0x10041000 /* GIC distributor, on FPGA */
74#define REALVIEW_PB1176_L220_BASE 0x10110000 /* L220 registers */ 74#define REALVIEW_PB1176_L220_BASE 0x10110000 /* L220 registers */
75 75
76/*
77 * Control register SYS_RESETCTL is set to 1 to force a soft reset
78 */
79#define REALVIEW_PB1176_SYS_LOCKVAL_RSTCTL 0x0100
80
76#endif /* __ASM_ARCH_BOARD_PB1176_H */ 81#endif /* __ASM_ARCH_BOARD_PB1176_H */
diff --git a/arch/arm/mach-realview/include/mach/board-pb11mp.h b/arch/arm/mach-realview/include/mach/board-pb11mp.h
index f0d68e0fea01..7abf918b77e9 100644
--- a/arch/arm/mach-realview/include/mach/board-pb11mp.h
+++ b/arch/arm/mach-realview/include/mach/board-pb11mp.h
@@ -81,4 +81,16 @@
81#define REALVIEW_TC11MP_GIC_DIST_BASE 0x1F001000 /* Test chip interrupt controller distributor */ 81#define REALVIEW_TC11MP_GIC_DIST_BASE 0x1F001000 /* Test chip interrupt controller distributor */
82#define REALVIEW_TC11MP_L220_BASE 0x1F002000 /* L220 registers */ 82#define REALVIEW_TC11MP_L220_BASE 0x1F002000 /* L220 registers */
83 83
84 /*
85 * Values for REALVIEW_SYS_RESET_CTRL
86 */
87#define REALVIEW_PB11MP_SYS_CTRL_RESET_CONFIGCLR 0x01
88#define REALVIEW_PB11MP_SYS_CTRL_RESET_CONFIGINIT 0x02
89#define REALVIEW_PB11MP_SYS_CTRL_RESET_DLLRESET 0x03
90#define REALVIEW_PB11MP_SYS_CTRL_RESET_PLLRESET 0x04
91#define REALVIEW_PB11MP_SYS_CTRL_RESET_POR 0x05
92#define REALVIEW_PB11MP_SYS_CTRL_RESET_DoC 0x06
93
94#define REALVIEW_PB11MP_SYS_CTRL_LED (1 << 0)
95
84#endif /* __ASM_ARCH_BOARD_PB11MP_H */ 96#endif /* __ASM_ARCH_BOARD_PB11MP_H */
diff --git a/arch/arm/mach-realview/include/mach/platform.h b/arch/arm/mach-realview/include/mach/platform.h
index c8f50835fed2..4f46bf71e752 100644
--- a/arch/arm/mach-realview/include/mach/platform.h
+++ b/arch/arm/mach-realview/include/mach/platform.h
@@ -119,19 +119,6 @@
119#define REALVIEW_SYS_TEST_OSC3 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET) 119#define REALVIEW_SYS_TEST_OSC3 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET)
120#define REALVIEW_SYS_TEST_OSC4 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET) 120#define REALVIEW_SYS_TEST_OSC4 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET)
121 121
122/*
123 * Values for REALVIEW_SYS_RESET_CTRL
124 */
125#define REALVIEW_SYS_CTRL_RESET_CONFIGCLR 0x01
126#define REALVIEW_SYS_CTRL_RESET_CONFIGINIT 0x02
127#define REALVIEW_SYS_CTRL_RESET_DLLRESET 0x03
128#define REALVIEW_SYS_CTRL_RESET_PLLRESET 0x04
129#define REALVIEW_SYS_CTRL_RESET_POR 0x05
130#define REALVIEW_SYS_CTRL_RESET_DoC 0x06
131
132#define REALVIEW_SYS_CTRL_LED (1 << 0)
133
134
135/* ------------------------------------------------------------------------ 122/* ------------------------------------------------------------------------
136 * RealView control registers 123 * RealView control registers
137 * ------------------------------------------------------------------------ 124 * ------------------------------------------------------------------------
@@ -153,7 +140,7 @@
153 * SYS_CLD, SYS_BOOTCS 140 * SYS_CLD, SYS_BOOTCS
154 */ 141 */
155#define REALVIEW_SYS_LOCK_LOCKED (1 << 16) 142#define REALVIEW_SYS_LOCK_LOCKED (1 << 16)
156#define REALVIEW_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */ 143#define REALVIEW_SYS_LOCKVAL_MASK 0xA05F /* Enable write access */
157 144
158/* 145/*
159 * REALVIEW_SYS_FLASH 146 * REALVIEW_SYS_FLASH
diff --git a/arch/arm/mach-realview/include/mach/system.h b/arch/arm/mach-realview/include/mach/system.h
index 1a15a441e027..a30f2e3ec178 100644
--- a/arch/arm/mach-realview/include/mach/system.h
+++ b/arch/arm/mach-realview/include/mach/system.h
@@ -25,6 +25,8 @@
25#include <mach/hardware.h> 25#include <mach/hardware.h>
26#include <mach/platform.h> 26#include <mach/platform.h>
27 27
28void (*realview_reset)(char mode);
29
28static inline void arch_idle(void) 30static inline void arch_idle(void)
29{ 31{
30 /* 32 /*
@@ -36,16 +38,12 @@ static inline void arch_idle(void)
36 38
37static inline void arch_reset(char mode, const char *cmd) 39static inline void arch_reset(char mode, const char *cmd)
38{ 40{
39 void __iomem *hdr_ctrl = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_RESETCTL_OFFSET;
40 unsigned int val;
41
42 /* 41 /*
43 * To reset, we hit the on-board reset register 42 * To reset, we hit the on-board reset register
44 * in the system FPGA 43 * in the system FPGA
45 */ 44 */
46 val = __raw_readl(hdr_ctrl); 45 if (realview_reset)
47 val |= REALVIEW_SYS_CTRL_RESET_CONFIGCLR; 46 realview_reset(mode);
48 __raw_writel(val, hdr_ctrl);
49} 47}
50 48
51#endif 49#endif
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index 2817fe099319..a6ba147692c1 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -290,6 +290,16 @@ static struct sys_timer realview_pb1176_timer = {
290 .init = realview_pb1176_timer_init, 290 .init = realview_pb1176_timer_init,
291}; 291};
292 292
293static void realview_pb1176_reset(char mode)
294{
295 void __iomem *hdr_ctrl = __io_address(REALVIEW_SYS_BASE) +
296 REALVIEW_SYS_RESETCTL_OFFSET;
297 void __iomem *rst_hdr_ctrl = __io_address(REALVIEW_SYS_BASE) +
298 REALVIEW_SYS_LOCK_OFFSET;
299 __raw_writel(REALVIEW_SYS_LOCKVAL_MASK, rst_hdr_ctrl);
300 __raw_writel(REALVIEW_PB1176_SYS_LOCKVAL_RSTCTL, hdr_ctrl);
301}
302
293static void __init realview_pb1176_init(void) 303static void __init realview_pb1176_init(void)
294{ 304{
295 int i; 305 int i;
@@ -313,6 +323,7 @@ static void __init realview_pb1176_init(void)
313#ifdef CONFIG_LEDS 323#ifdef CONFIG_LEDS
314 leds_event = realview_leds_event; 324 leds_event = realview_leds_event;
315#endif 325#endif
326 realview_reset = realview_pb1176_reset;
316} 327}
317 328
318MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176") 329MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index 94680fcf726d..070d284ce96e 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -299,6 +299,21 @@ static struct sys_timer realview_pb11mp_timer = {
299 .init = realview_pb11mp_timer_init, 299 .init = realview_pb11mp_timer_init,
300}; 300};
301 301
302static void realview_pb11mp_reset(char mode)
303{
304 void __iomem *hdr_ctrl = __io_address(REALVIEW_SYS_BASE) +
305 REALVIEW_SYS_RESETCTL_OFFSET;
306 unsigned int val;
307
308 /*
309 * To reset, we hit the on-board reset register
310 * in the system FPGA
311 */
312 val = __raw_readl(hdr_ctrl);
313 val |= REALVIEW_PB11MP_SYS_CTRL_RESET_CONFIGCLR;
314 __raw_writel(val, hdr_ctrl);
315}
316
302static void __init realview_pb11mp_init(void) 317static void __init realview_pb11mp_init(void)
303{ 318{
304 int i; 319 int i;
@@ -324,6 +339,7 @@ static void __init realview_pb11mp_init(void)
324#ifdef CONFIG_LEDS 339#ifdef CONFIG_LEDS
325 leds_event = realview_leds_event; 340 leds_event = realview_leds_event;
326#endif 341#endif
342 realview_reset = realview_pb11mp_reset;
327} 343}
328 344
329MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore") 345MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
diff --git a/arch/arm/mach-s3c2410/gpio.c b/arch/arm/mach-s3c2410/gpio.c
index 7974afca297c..9664e011dae2 100644
--- a/arch/arm/mach-s3c2410/gpio.c
+++ b/arch/arm/mach-s3c2410/gpio.c
@@ -28,6 +28,7 @@
28#include <linux/io.h> 28#include <linux/io.h>
29 29
30#include <mach/hardware.h> 30#include <mach/hardware.h>
31#include <mach/gpio-fns.h>
31#include <asm/irq.h> 32#include <asm/irq.h>
32 33
33#include <mach/regs-gpio.h> 34#include <mach/regs-gpio.h>
diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h
index c3a2629e0ded..92e2687009ea 100644
--- a/arch/arm/mach-s3c2410/include/mach/dma.h
+++ b/arch/arm/mach-s3c2410/include/mach/dma.h
@@ -110,6 +110,8 @@ enum s3c2410_dma_loadst {
110 * waiting for reloads */ 110 * waiting for reloads */
111#define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */ 111#define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */
112 112
113#define S3C2410_DMAF_CIRCULAR (1 << 2) /* no circular dma support */
114
113/* dma buffer */ 115/* dma buffer */
114 116
115struct s3c2410_dma_buf; 117struct s3c2410_dma_buf;
@@ -194,4 +196,9 @@ struct s3c2410_dma_chan {
194 196
195typedef unsigned long dma_device_t; 197typedef unsigned long dma_device_t;
196 198
199static inline bool s3c_dma_has_circular(void)
200{
201 return false;
202}
203
197#endif /* __ASM_ARCH_DMA_H */ 204#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index d7bba919a77e..a8b69d77571b 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -103,6 +103,7 @@ config MACH_MINI2440
103 select LEDS_TRIGGER_BACKLIGHT 103 select LEDS_TRIGGER_BACKLIGHT
104 select SND_S3C24XX_SOC_S3C24XX_UDA134X 104 select SND_S3C24XX_SOC_S3C24XX_UDA134X
105 select S3C_DEV_NAND 105 select S3C_DEV_NAND
106 select S3C_DEV_USB_HOST
106 help 107 help
107 Say Y here to select support for the MINI2440. Is a 10cm x 10cm board 108 Say Y here to select support for the MINI2440. Is a 10cm x 10cm board
108 available via various sources. It can come with a 3.5" or 7" touch LCD. 109 available via various sources. It can come with a 3.5" or 7" touch LCD.
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c
index ec71a6965786..1c3382fefdd2 100644
--- a/arch/arm/mach-s3c2440/mach-mini2440.c
+++ b/arch/arm/mach-s3c2440/mach-mini2440.c
@@ -144,7 +144,7 @@ static struct s3c2410_udc_mach_info mini2440_udc_cfg __initdata = {
144 .type = (S3C2410_LCDCON1_TFT16BPP |\ 144 .type = (S3C2410_LCDCON1_TFT16BPP |\
145 S3C2410_LCDCON1_TFT) 145 S3C2410_LCDCON1_TFT)
146 146
147struct s3c2410fb_display mini2440_lcd_cfg[] __initdata = { 147static struct s3c2410fb_display mini2440_lcd_cfg[] __initdata = {
148 [0] = { /* mini2440 + 3.5" TFT + touchscreen */ 148 [0] = { /* mini2440 + 3.5" TFT + touchscreen */
149 _LCD_DECLARE( 149 _LCD_DECLARE(
150 7, /* The 3.5 is quite fast */ 150 7, /* The 3.5 is quite fast */
@@ -191,7 +191,7 @@ struct s3c2410fb_display mini2440_lcd_cfg[] __initdata = {
191#define S3C2410_GPCCON_MASK(x) (3 << ((x) * 2)) 191#define S3C2410_GPCCON_MASK(x) (3 << ((x) * 2))
192#define S3C2410_GPDCON_MASK(x) (3 << ((x) * 2)) 192#define S3C2410_GPDCON_MASK(x) (3 << ((x) * 2))
193 193
194struct s3c2410fb_mach_info mini2440_fb_info __initdata = { 194static struct s3c2410fb_mach_info mini2440_fb_info __initdata = {
195 .displays = &mini2440_lcd_cfg[0], /* not constant! see init */ 195 .displays = &mini2440_lcd_cfg[0], /* not constant! see init */
196 .num_displays = 1, 196 .num_displays = 1,
197 .default_display = 0, 197 .default_display = 0,
diff --git a/arch/arm/mach-s3c6400/include/mach/dma.h b/arch/arm/mach-s3c6400/include/mach/dma.h
index 1067619f0ba0..004edab23954 100644
--- a/arch/arm/mach-s3c6400/include/mach/dma.h
+++ b/arch/arm/mach-s3c6400/include/mach/dma.h
@@ -68,6 +68,11 @@ static __inline__ int s3c_dma_has_circular(void)
68 68
69#define S3C2410_DMAF_CIRCULAR (1 << 0) 69#define S3C2410_DMAF_CIRCULAR (1 << 0)
70 70
71static inline bool s3c_dma_has_circular(void)
72{
73 return false;
74}
75
71#include <plat/dma.h> 76#include <plat/dma.h>
72 77
73#endif /* __ASM_ARCH_IRQ_H */ 78#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 6bda76a43199..a9e22e31eaa1 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -50,10 +50,7 @@ void __new_context(struct mm_struct *mm)
50 isb(); 50 isb();
51 flush_tlb_all(); 51 flush_tlb_all();
52 if (icache_is_vivt_asid_tagged()) { 52 if (icache_is_vivt_asid_tagged()) {
53 asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n" 53 __flush_icache_all();
54 "mcr p15, 0, %0, c7, c5, 6 @ flush BTAC/BTB\n"
55 :
56 : "r" (0));
57 dsb(); 54 dsb();
58 } 55 }
59 } 56 }
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index b30925fcbcdc..b9590a7085ca 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -205,7 +205,7 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
205 205
206 order = get_order(size); 206 order = get_order(size);
207 207
208 if (mask != 0xffffffff) 208 if (mask < 0xffffffffULL)
209 gfp |= GFP_DMA; 209 gfp |= GFP_DMA;
210 210
211 page = alloc_pages(gfp, order); 211 page = alloc_pages(gfp, order);
@@ -289,7 +289,7 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
289 if (!mask) 289 if (!mask)
290 goto error; 290 goto error;
291 291
292 if (mask != 0xffffffff) 292 if (mask < 0xffffffffULL)
293 gfp |= GFP_DMA; 293 gfp |= GFP_DMA;
294 virt = kmalloc(size, gfp); 294 virt = kmalloc(size, gfp);
295 if (!virt) 295 if (!virt)
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index b27942909b23..7f294f307c83 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -18,10 +18,6 @@
18 18
19#include "mm.h" 19#include "mm.h"
20 20
21#ifdef CONFIG_ARM_ERRATA_411920
22extern void v6_icache_inval_all(void);
23#endif
24
25#ifdef CONFIG_CPU_CACHE_VIPT 21#ifdef CONFIG_CPU_CACHE_VIPT
26 22
27#define ALIAS_FLUSH_START 0xffff4000 23#define ALIAS_FLUSH_START 0xffff4000
@@ -35,16 +31,11 @@ static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
35 flush_tlb_kernel_page(to); 31 flush_tlb_kernel_page(to);
36 32
37 asm( "mcrr p15, 0, %1, %0, c14\n" 33 asm( "mcrr p15, 0, %1, %0, c14\n"
38 " mcr p15, 0, %2, c7, c10, 4\n" 34 " mcr p15, 0, %2, c7, c10, 4"
39#ifndef CONFIG_ARM_ERRATA_411920
40 " mcr p15, 0, %2, c7, c5, 0\n"
41#endif
42 : 35 :
43 : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero) 36 : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero)
44 : "cc"); 37 : "cc");
45#ifdef CONFIG_ARM_ERRATA_411920 38 __flush_icache_all();
46 v6_icache_inval_all();
47#endif
48} 39}
49 40
50void flush_cache_mm(struct mm_struct *mm) 41void flush_cache_mm(struct mm_struct *mm)
@@ -57,16 +48,11 @@ void flush_cache_mm(struct mm_struct *mm)
57 48
58 if (cache_is_vipt_aliasing()) { 49 if (cache_is_vipt_aliasing()) {
59 asm( "mcr p15, 0, %0, c7, c14, 0\n" 50 asm( "mcr p15, 0, %0, c7, c14, 0\n"
60 " mcr p15, 0, %0, c7, c10, 4\n" 51 " mcr p15, 0, %0, c7, c10, 4"
61#ifndef CONFIG_ARM_ERRATA_411920
62 " mcr p15, 0, %0, c7, c5, 0\n"
63#endif
64 : 52 :
65 : "r" (0) 53 : "r" (0)
66 : "cc"); 54 : "cc");
67#ifdef CONFIG_ARM_ERRATA_411920 55 __flush_icache_all();
68 v6_icache_inval_all();
69#endif
70 } 56 }
71} 57}
72 58
@@ -81,16 +67,11 @@ void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned
81 67
82 if (cache_is_vipt_aliasing()) { 68 if (cache_is_vipt_aliasing()) {
83 asm( "mcr p15, 0, %0, c7, c14, 0\n" 69 asm( "mcr p15, 0, %0, c7, c14, 0\n"
84 " mcr p15, 0, %0, c7, c10, 4\n" 70 " mcr p15, 0, %0, c7, c10, 4"
85#ifndef CONFIG_ARM_ERRATA_411920
86 " mcr p15, 0, %0, c7, c5, 0\n"
87#endif
88 : 71 :
89 : "r" (0) 72 : "r" (0)
90 : "cc"); 73 : "cc");
91#ifdef CONFIG_ARM_ERRATA_411920 74 __flush_icache_all();
92 v6_icache_inval_all();
93#endif
94 } 75 }
95} 76}
96 77
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 40940d7ce4ff..52c40d155672 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -273,7 +273,6 @@ static void __init bootmem_init_node(int node, struct meminfo *mi,
273 struct membank *bank = &mi->bank[i]; 273 struct membank *bank = &mi->bank[i];
274 if (!bank->highmem) 274 if (!bank->highmem)
275 free_bootmem_node(pgdat, bank_phys_start(bank), bank_phys_size(bank)); 275 free_bootmem_node(pgdat, bank_phys_start(bank), bank_phys_size(bank));
276 memory_present(node, bank_pfn_start(bank), bank_pfn_end(bank));
277 } 276 }
278 277
279 /* 278 /*
@@ -370,6 +369,19 @@ int pfn_valid(unsigned long pfn)
370 return 0; 369 return 0;
371} 370}
372EXPORT_SYMBOL(pfn_valid); 371EXPORT_SYMBOL(pfn_valid);
372
373static void arm_memory_present(struct meminfo *mi, int node)
374{
375}
376#else
377static void arm_memory_present(struct meminfo *mi, int node)
378{
379 int i;
380 for_each_nodebank(i, mi, node) {
381 struct membank *bank = &mi->bank[i];
382 memory_present(node, bank_pfn_start(bank), bank_pfn_end(bank));
383 }
384}
373#endif 385#endif
374 386
375static int __init meminfo_cmp(const void *_a, const void *_b) 387static int __init meminfo_cmp(const void *_a, const void *_b)
@@ -427,6 +439,12 @@ void __init bootmem_init(void)
427 */ 439 */
428 if (node == initrd_node) 440 if (node == initrd_node)
429 bootmem_reserve_initrd(node); 441 bootmem_reserve_initrd(node);
442
443 /*
444 * Sparsemem tries to allocate bootmem in memory_present(),
445 * so must be done after the fixed reservations
446 */
447 arm_memory_present(mi, node);
430 } 448 }
431 449
432 /* 450 /*
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 02243eeccf50..ea67be0223ac 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -117,6 +117,13 @@ static void __init early_cachepolicy(char **p)
117 } 117 }
118 if (i == ARRAY_SIZE(cache_policies)) 118 if (i == ARRAY_SIZE(cache_policies))
119 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); 119 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
120 /*
121 * This restriction is partly to do with the way we boot; it is
122 * unpredictable to have memory mapped using two different sets of
123 * memory attributes (shared, type, and cache attribs). We can not
124 * change these attributes once the initial assembly has setup the
125 * page tables.
126 */
120 if (cpu_architecture() >= CPU_ARCH_ARMv6) { 127 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
121 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n"); 128 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
122 cachepolicy = CPOLICY_WRITEBACK; 129 cachepolicy = CPOLICY_WRITEBACK;
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 194737d60a22..70f75d2e3ead 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -32,8 +32,10 @@
32 32
33#ifndef CONFIG_SMP 33#ifndef CONFIG_SMP
34#define TTB_FLAGS TTB_RGN_WBWA 34#define TTB_FLAGS TTB_RGN_WBWA
35#define PMD_FLAGS PMD_SECT_WB
35#else 36#else
36#define TTB_FLAGS TTB_RGN_WBWA|TTB_S 37#define TTB_FLAGS TTB_RGN_WBWA|TTB_S
38#define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S
37#endif 39#endif
38 40
39ENTRY(cpu_v6_proc_init) 41ENTRY(cpu_v6_proc_init)
@@ -222,10 +224,9 @@ __v6_proc_info:
222 .long 0x0007b000 224 .long 0x0007b000
223 .long 0x0007f000 225 .long 0x0007f000
224 .long PMD_TYPE_SECT | \ 226 .long PMD_TYPE_SECT | \
225 PMD_SECT_BUFFERABLE | \
226 PMD_SECT_CACHEABLE | \
227 PMD_SECT_AP_WRITE | \ 227 PMD_SECT_AP_WRITE | \
228 PMD_SECT_AP_READ 228 PMD_SECT_AP_READ | \
229 PMD_FLAGS
229 .long PMD_TYPE_SECT | \ 230 .long PMD_TYPE_SECT | \
230 PMD_SECT_XN | \ 231 PMD_SECT_XN | \
231 PMD_SECT_AP_WRITE | \ 232 PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 23ebcf6eab9f..eeeed01ee44a 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -33,9 +33,11 @@
33#ifndef CONFIG_SMP 33#ifndef CONFIG_SMP
34/* PTWs cacheable, inner WB not shareable, outer WB not shareable */ 34/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
35#define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB 35#define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB
36#define PMD_FLAGS PMD_SECT_WB
36#else 37#else
37/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ 38/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
38#define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA 39#define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
40#define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S
39#endif 41#endif
40 42
41ENTRY(cpu_v7_proc_init) 43ENTRY(cpu_v7_proc_init)
@@ -326,10 +328,9 @@ __v7_proc_info:
326 .long 0x000f0000 @ Required ID value 328 .long 0x000f0000 @ Required ID value
327 .long 0x000f0000 @ Mask for ID 329 .long 0x000f0000 @ Mask for ID
328 .long PMD_TYPE_SECT | \ 330 .long PMD_TYPE_SECT | \
329 PMD_SECT_BUFFERABLE | \
330 PMD_SECT_CACHEABLE | \
331 PMD_SECT_AP_WRITE | \ 331 PMD_SECT_AP_WRITE | \
332 PMD_SECT_AP_READ 332 PMD_SECT_AP_READ | \
333 PMD_FLAGS
333 .long PMD_TYPE_SECT | \ 334 .long PMD_TYPE_SECT | \
334 PMD_SECT_XN | \ 335 PMD_SECT_XN | \
335 PMD_SECT_AP_WRITE | \ 336 PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/plat-s3c24xx/adc.c b/arch/arm/plat-s3c24xx/adc.c
index 4d36b784fb8b..df47322492d5 100644
--- a/arch/arm/plat-s3c24xx/adc.c
+++ b/arch/arm/plat-s3c24xx/adc.c
@@ -189,7 +189,7 @@ int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch)
189err: 189err:
190 return ret; 190 return ret;
191} 191}
192EXPORT_SYMBOL_GPL(s3c_adc_convert); 192EXPORT_SYMBOL_GPL(s3c_adc_read);
193 193
194static void s3c_adc_default_select(struct s3c_adc_client *client, 194static void s3c_adc_default_select(struct s3c_adc_client *client,
195 unsigned select) 195 unsigned select)
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 5447e60f3936..4af9dd948793 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -61,6 +61,7 @@ static const char name_s3c2410[] = "S3C2410";
61static const char name_s3c2412[] = "S3C2412"; 61static const char name_s3c2412[] = "S3C2412";
62static const char name_s3c2440[] = "S3C2440"; 62static const char name_s3c2440[] = "S3C2440";
63static const char name_s3c2442[] = "S3C2442"; 63static const char name_s3c2442[] = "S3C2442";
64static const char name_s3c2442b[] = "S3C2442B";
64static const char name_s3c2443[] = "S3C2443"; 65static const char name_s3c2443[] = "S3C2443";
65static const char name_s3c2410a[] = "S3C2410A"; 66static const char name_s3c2410a[] = "S3C2410A";
66static const char name_s3c2440a[] = "S3C2440A"; 67static const char name_s3c2440a[] = "S3C2440A";
@@ -112,6 +113,15 @@ static struct cpu_table cpu_ids[] __initdata = {
112 .name = name_s3c2442 113 .name = name_s3c2442
113 }, 114 },
114 { 115 {
116 .idcode = 0x32440aab,
117 .idmask = 0xffffffff,
118 .map_io = s3c244x_map_io,
119 .init_clocks = s3c244x_init_clocks,
120 .init_uarts = s3c244x_init_uarts,
121 .init = s3c2442_init,
122 .name = name_s3c2442b
123 },
124 {
115 .idcode = 0x32412001, 125 .idcode = 0x32412001,
116 .idmask = 0xffffffff, 126 .idmask = 0xffffffff,
117 .map_io = s3c2412_map_io, 127 .map_io = s3c2412_map_io,
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 196b19123653..f046f8c51084 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -208,14 +208,14 @@ s3c2410_dma_loadbuffer(struct s3c2410_dma_chan *chan,
208{ 208{
209 unsigned long reload; 209 unsigned long reload;
210 210
211 pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n",
212 buf, (unsigned long)buf->data, buf->size);
213
214 if (buf == NULL) { 211 if (buf == NULL) {
215 dmawarn("buffer is NULL\n"); 212 dmawarn("buffer is NULL\n");
216 return -EINVAL; 213 return -EINVAL;
217 } 214 }
218 215
216 pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n",
217 buf, (unsigned long)buf->data, buf->size);
218
219 /* check the state of the channel before we do anything */ 219 /* check the state of the channel before we do anything */
220 220
221 if (chan->load_state == S3C2410_DMALOAD_1LOADED) { 221 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c
index 95df059b5a1d..5467470badfd 100644
--- a/arch/arm/plat-s3c24xx/gpio.c
+++ b/arch/arm/plat-s3c24xx/gpio.c
@@ -29,6 +29,7 @@
29#include <linux/io.h> 29#include <linux/io.h>
30 30
31#include <mach/hardware.h> 31#include <mach/hardware.h>
32#include <mach/gpio-fns.h>
32#include <asm/irq.h> 33#include <asm/irq.h>
33 34
34#include <mach/regs-gpio.h> 35#include <mach/regs-gpio.h>
diff --git a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h
index efeb025affc7..c776120b99e6 100644
--- a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h
+++ b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h
@@ -222,7 +222,9 @@ extern struct clk *s3c_cpufreq_clk_get(struct device *, const char *);
222/* S3C2410 and compatible exported functions */ 222/* S3C2410 and compatible exported functions */
223 223
224extern void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg); 224extern void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg);
225extern void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg);
225 226
227#ifdef CONFIG_S3C2410_IOTIMING
226extern int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg, 228extern int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
227 struct s3c_iotimings *iot); 229 struct s3c_iotimings *iot);
228 230
@@ -231,8 +233,11 @@ extern int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
231 233
232extern void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg, 234extern void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
233 struct s3c_iotimings *iot); 235 struct s3c_iotimings *iot);
234 236#else
235extern void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg); 237#define s3c2410_iotiming_calc NULL
238#define s3c2410_iotiming_get NULL
239#define s3c2410_iotiming_set NULL
240#endif /* CONFIG_S3C2410_IOTIMING */
236 241
237/* S3C2412 compatible routines */ 242/* S3C2412 compatible routines */
238 243
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h
index b6deeef8f663..82ab4aad1bbe 100644
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h
@@ -27,6 +27,7 @@ extern void s3c2410_init_clocks(int xtal);
27#define s3c2410_init_uarts NULL 27#define s3c2410_init_uarts NULL
28#define s3c2410_map_io NULL 28#define s3c2410_map_io NULL
29#define s3c2410_init NULL 29#define s3c2410_init NULL
30#define s3c2410a_init NULL
30#endif 31#endif
31 32
32extern int s3c2410_baseclk_add(void); 33extern int s3c2410_baseclk_add(void);
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
index a8777a755dfa..ff46e7fa957a 100644
--- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
@@ -51,8 +51,8 @@
51#define S3C6400_CLKDIV0_HCLK_SHIFT (8) 51#define S3C6400_CLKDIV0_HCLK_SHIFT (8)
52#define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4) 52#define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4)
53#define S3C6400_CLKDIV0_MPLL_SHIFT (4) 53#define S3C6400_CLKDIV0_MPLL_SHIFT (4)
54#define S3C6400_CLKDIV0_ARM_MASK (0x3 << 0) 54#define S3C6400_CLKDIV0_ARM_MASK (0x7 << 0)
55#define S3C6410_CLKDIV0_ARM_MASK (0x7 << 0) 55#define S3C6410_CLKDIV0_ARM_MASK (0xf << 0)
56#define S3C6400_CLKDIV0_ARM_SHIFT (0) 56#define S3C6400_CLKDIV0_ARM_SHIFT (0)
57 57
58/* CLKDIV1 */ 58/* CLKDIV1 */
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index 9745852261e0..6ffa21eb1b91 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -677,6 +677,9 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
677 677
678 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); 678 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
679 679
680 /* For now assume the mux always selects the crystal */
681 clk_ext_xtal_mux.parent = xtal_clk;
682
680 epll = s3c6400_get_epll(xtal); 683 epll = s3c6400_get_epll(xtal);
681 mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON)); 684 mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
682 apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON)); 685 apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
diff --git a/arch/avr32/mach-at32ap/include/mach/cpu.h b/arch/avr32/mach-at32ap/include/mach/cpu.h
index 44d0bfa1f409..9c96a130f3a8 100644
--- a/arch/avr32/mach-at32ap/include/mach/cpu.h
+++ b/arch/avr32/mach-at32ap/include/mach/cpu.h
@@ -31,5 +31,8 @@
31#define cpu_is_at91sam9263() (0) 31#define cpu_is_at91sam9263() (0)
32#define cpu_is_at91sam9rl() (0) 32#define cpu_is_at91sam9rl() (0)
33#define cpu_is_at91cap9() (0) 33#define cpu_is_at91cap9() (0)
34#define cpu_is_at91sam9g10() (0)
35#define cpu_is_at91sam9g45() (0)
36#define cpu_is_at91sam9g45es() (0)
34 37
35#endif /* __ASM_ARCH_CPU_H */ 38#endif /* __ASM_ARCH_CPU_H */
diff --git a/arch/ia64/include/asm/spinlock.h b/arch/ia64/include/asm/spinlock.h
index 30bb930e1111..239ecdc9516d 100644
--- a/arch/ia64/include/asm/spinlock.h
+++ b/arch/ia64/include/asm/spinlock.h
@@ -25,61 +25,82 @@
25 * by atomically noting the tail and incrementing it by one (thus adding 25 * by atomically noting the tail and incrementing it by one (thus adding
26 * ourself to the queue and noting our position), then waiting until the head 26 * ourself to the queue and noting our position), then waiting until the head
27 * becomes equal to the the initial value of the tail. 27 * becomes equal to the the initial value of the tail.
28 * The pad bits in the middle are used to prevent the next_ticket number
29 * overflowing into the now_serving number.
28 * 30 *
29 * 63 32 31 0 31 * 31 17 16 15 14 0
30 * +----------------------------------------------------+ 32 * +----------------------------------------------------+
31 * | next_ticket_number | now_serving | 33 * | now_serving | padding | next_ticket |
32 * +----------------------------------------------------+ 34 * +----------------------------------------------------+
33 */ 35 */
34 36
35#define TICKET_SHIFT 32 37#define TICKET_SHIFT 17
38#define TICKET_BITS 15
39#define TICKET_MASK ((1 << TICKET_BITS) - 1)
36 40
37static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock) 41static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
38{ 42{
39 int *p = (int *)&lock->lock, turn, now_serving; 43 int *p = (int *)&lock->lock, ticket, serve;
40 44
41 now_serving = *p; 45 ticket = ia64_fetchadd(1, p, acq);
42 turn = ia64_fetchadd(1, p+1, acq);
43 46
44 if (turn == now_serving) 47 if (!(((ticket >> TICKET_SHIFT) ^ ticket) & TICKET_MASK))
45 return; 48 return;
46 49
47 do { 50 ia64_invala();
51
52 for (;;) {
53 asm volatile ("ld4.c.nc %0=[%1]" : "=r"(serve) : "r"(p) : "memory");
54
55 if (!(((serve >> TICKET_SHIFT) ^ ticket) & TICKET_MASK))
56 return;
48 cpu_relax(); 57 cpu_relax();
49 } while (ACCESS_ONCE(*p) != turn); 58 }
50} 59}
51 60
52static __always_inline int __ticket_spin_trylock(raw_spinlock_t *lock) 61static __always_inline int __ticket_spin_trylock(raw_spinlock_t *lock)
53{ 62{
54 long tmp = ACCESS_ONCE(lock->lock), try; 63 int tmp = ACCESS_ONCE(lock->lock);
55
56 if (!(((tmp >> TICKET_SHIFT) ^ tmp) & ((1L << TICKET_SHIFT) - 1))) {
57 try = tmp + (1L << TICKET_SHIFT);
58 64
59 return ia64_cmpxchg(acq, &lock->lock, tmp, try, sizeof (tmp)) == tmp; 65 if (!(((tmp >> TICKET_SHIFT) ^ tmp) & TICKET_MASK))
60 } 66 return ia64_cmpxchg(acq, &lock->lock, tmp, tmp + 1, sizeof (tmp)) == tmp;
61 return 0; 67 return 0;
62} 68}
63 69
64static __always_inline void __ticket_spin_unlock(raw_spinlock_t *lock) 70static __always_inline void __ticket_spin_unlock(raw_spinlock_t *lock)
65{ 71{
66 int *p = (int *)&lock->lock; 72 unsigned short *p = (unsigned short *)&lock->lock + 1, tmp;
67 73
68 (void)ia64_fetchadd(1, p, rel); 74 asm volatile ("ld2.bias %0=[%1]" : "=r"(tmp) : "r"(p));
75 ACCESS_ONCE(*p) = (tmp + 2) & ~1;
76}
77
78static __always_inline void __ticket_spin_unlock_wait(raw_spinlock_t *lock)
79{
80 int *p = (int *)&lock->lock, ticket;
81
82 ia64_invala();
83
84 for (;;) {
85 asm volatile ("ld4.c.nc %0=[%1]" : "=r"(ticket) : "r"(p) : "memory");
86 if (!(((ticket >> TICKET_SHIFT) ^ ticket) & TICKET_MASK))
87 return;
88 cpu_relax();
89 }
69} 90}
70 91
71static inline int __ticket_spin_is_locked(raw_spinlock_t *lock) 92static inline int __ticket_spin_is_locked(raw_spinlock_t *lock)
72{ 93{
73 long tmp = ACCESS_ONCE(lock->lock); 94 long tmp = ACCESS_ONCE(lock->lock);
74 95
75 return !!(((tmp >> TICKET_SHIFT) ^ tmp) & ((1L << TICKET_SHIFT) - 1)); 96 return !!(((tmp >> TICKET_SHIFT) ^ tmp) & TICKET_MASK);
76} 97}
77 98
78static inline int __ticket_spin_is_contended(raw_spinlock_t *lock) 99static inline int __ticket_spin_is_contended(raw_spinlock_t *lock)
79{ 100{
80 long tmp = ACCESS_ONCE(lock->lock); 101 long tmp = ACCESS_ONCE(lock->lock);
81 102
82 return (((tmp >> TICKET_SHIFT) - tmp) & ((1L << TICKET_SHIFT) - 1)) > 1; 103 return ((tmp - (tmp >> TICKET_SHIFT)) & TICKET_MASK) > 1;
83} 104}
84 105
85static inline int __raw_spin_is_locked(raw_spinlock_t *lock) 106static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
@@ -116,8 +137,7 @@ static __always_inline void __raw_spin_lock_flags(raw_spinlock_t *lock,
116 137
117static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock) 138static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
118{ 139{
119 while (__raw_spin_is_locked(lock)) 140 __ticket_spin_unlock_wait(lock);
120 cpu_relax();
121} 141}
122 142
123#define __raw_read_can_lock(rw) (*(volatile int *)(rw) >= 0) 143#define __raw_read_can_lock(rw) (*(volatile int *)(rw) >= 0)
diff --git a/arch/ia64/include/asm/spinlock_types.h b/arch/ia64/include/asm/spinlock_types.h
index b61d136d9bc2..474e46f1ab4a 100644
--- a/arch/ia64/include/asm/spinlock_types.h
+++ b/arch/ia64/include/asm/spinlock_types.h
@@ -6,7 +6,7 @@
6#endif 6#endif
7 7
8typedef struct { 8typedef struct {
9 volatile unsigned long lock; 9 volatile unsigned int lock;
10} raw_spinlock_t; 10} raw_spinlock_t;
11 11
12#define __RAW_SPIN_LOCK_UNLOCKED { 0 } 12#define __RAW_SPIN_LOCK_UNLOCKED { 0 }
diff --git a/arch/ia64/kernel/mca.c b/arch/ia64/kernel/mca.c
index d2877a7bfe2e..496ac7a99488 100644
--- a/arch/ia64/kernel/mca.c
+++ b/arch/ia64/kernel/mca.c
@@ -887,6 +887,60 @@ ia64_mca_modify_comm(const struct task_struct *previous_current)
887 memcpy(current->comm, comm, sizeof(current->comm)); 887 memcpy(current->comm, comm, sizeof(current->comm));
888} 888}
889 889
890static void
891finish_pt_regs(struct pt_regs *regs, const pal_min_state_area_t *ms,
892 unsigned long *nat)
893{
894 const u64 *bank;
895
896 /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use
897 * pmsa_{xip,xpsr,xfs}
898 */
899 if (ia64_psr(regs)->ic) {
900 regs->cr_iip = ms->pmsa_iip;
901 regs->cr_ipsr = ms->pmsa_ipsr;
902 regs->cr_ifs = ms->pmsa_ifs;
903 } else {
904 regs->cr_iip = ms->pmsa_xip;
905 regs->cr_ipsr = ms->pmsa_xpsr;
906 regs->cr_ifs = ms->pmsa_xfs;
907 }
908 regs->pr = ms->pmsa_pr;
909 regs->b0 = ms->pmsa_br0;
910 regs->ar_rsc = ms->pmsa_rsc;
911 copy_reg(&ms->pmsa_gr[1-1], ms->pmsa_nat_bits, &regs->r1, nat);
912 copy_reg(&ms->pmsa_gr[2-1], ms->pmsa_nat_bits, &regs->r2, nat);
913 copy_reg(&ms->pmsa_gr[3-1], ms->pmsa_nat_bits, &regs->r3, nat);
914 copy_reg(&ms->pmsa_gr[8-1], ms->pmsa_nat_bits, &regs->r8, nat);
915 copy_reg(&ms->pmsa_gr[9-1], ms->pmsa_nat_bits, &regs->r9, nat);
916 copy_reg(&ms->pmsa_gr[10-1], ms->pmsa_nat_bits, &regs->r10, nat);
917 copy_reg(&ms->pmsa_gr[11-1], ms->pmsa_nat_bits, &regs->r11, nat);
918 copy_reg(&ms->pmsa_gr[12-1], ms->pmsa_nat_bits, &regs->r12, nat);
919 copy_reg(&ms->pmsa_gr[13-1], ms->pmsa_nat_bits, &regs->r13, nat);
920 copy_reg(&ms->pmsa_gr[14-1], ms->pmsa_nat_bits, &regs->r14, nat);
921 copy_reg(&ms->pmsa_gr[15-1], ms->pmsa_nat_bits, &regs->r15, nat);
922 if (ia64_psr(regs)->bn)
923 bank = ms->pmsa_bank1_gr;
924 else
925 bank = ms->pmsa_bank0_gr;
926 copy_reg(&bank[16-16], ms->pmsa_nat_bits, &regs->r16, nat);
927 copy_reg(&bank[17-16], ms->pmsa_nat_bits, &regs->r17, nat);
928 copy_reg(&bank[18-16], ms->pmsa_nat_bits, &regs->r18, nat);
929 copy_reg(&bank[19-16], ms->pmsa_nat_bits, &regs->r19, nat);
930 copy_reg(&bank[20-16], ms->pmsa_nat_bits, &regs->r20, nat);
931 copy_reg(&bank[21-16], ms->pmsa_nat_bits, &regs->r21, nat);
932 copy_reg(&bank[22-16], ms->pmsa_nat_bits, &regs->r22, nat);
933 copy_reg(&bank[23-16], ms->pmsa_nat_bits, &regs->r23, nat);
934 copy_reg(&bank[24-16], ms->pmsa_nat_bits, &regs->r24, nat);
935 copy_reg(&bank[25-16], ms->pmsa_nat_bits, &regs->r25, nat);
936 copy_reg(&bank[26-16], ms->pmsa_nat_bits, &regs->r26, nat);
937 copy_reg(&bank[27-16], ms->pmsa_nat_bits, &regs->r27, nat);
938 copy_reg(&bank[28-16], ms->pmsa_nat_bits, &regs->r28, nat);
939 copy_reg(&bank[29-16], ms->pmsa_nat_bits, &regs->r29, nat);
940 copy_reg(&bank[30-16], ms->pmsa_nat_bits, &regs->r30, nat);
941 copy_reg(&bank[31-16], ms->pmsa_nat_bits, &regs->r31, nat);
942}
943
890/* On entry to this routine, we are running on the per cpu stack, see 944/* On entry to this routine, we are running on the per cpu stack, see
891 * mca_asm.h. The original stack has not been touched by this event. Some of 945 * mca_asm.h. The original stack has not been touched by this event. Some of
892 * the original stack's registers will be in the RBS on this stack. This stack 946 * the original stack's registers will be in the RBS on this stack. This stack
@@ -921,7 +975,6 @@ ia64_mca_modify_original_stack(struct pt_regs *regs,
921 u64 r12 = ms->pmsa_gr[12-1], r13 = ms->pmsa_gr[13-1]; 975 u64 r12 = ms->pmsa_gr[12-1], r13 = ms->pmsa_gr[13-1];
922 u64 ar_bspstore = regs->ar_bspstore; 976 u64 ar_bspstore = regs->ar_bspstore;
923 u64 ar_bsp = regs->ar_bspstore + (loadrs >> 16); 977 u64 ar_bsp = regs->ar_bspstore + (loadrs >> 16);
924 const u64 *bank;
925 const char *msg; 978 const char *msg;
926 int cpu = smp_processor_id(); 979 int cpu = smp_processor_id();
927 980
@@ -1024,54 +1077,9 @@ ia64_mca_modify_original_stack(struct pt_regs *regs,
1024 p = (char *)r12 - sizeof(*regs); 1077 p = (char *)r12 - sizeof(*regs);
1025 old_regs = (struct pt_regs *)p; 1078 old_regs = (struct pt_regs *)p;
1026 memcpy(old_regs, regs, sizeof(*regs)); 1079 memcpy(old_regs, regs, sizeof(*regs));
1027 /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use
1028 * pmsa_{xip,xpsr,xfs}
1029 */
1030 if (ia64_psr(regs)->ic) {
1031 old_regs->cr_iip = ms->pmsa_iip;
1032 old_regs->cr_ipsr = ms->pmsa_ipsr;
1033 old_regs->cr_ifs = ms->pmsa_ifs;
1034 } else {
1035 old_regs->cr_iip = ms->pmsa_xip;
1036 old_regs->cr_ipsr = ms->pmsa_xpsr;
1037 old_regs->cr_ifs = ms->pmsa_xfs;
1038 }
1039 old_regs->pr = ms->pmsa_pr;
1040 old_regs->b0 = ms->pmsa_br0;
1041 old_regs->loadrs = loadrs; 1080 old_regs->loadrs = loadrs;
1042 old_regs->ar_rsc = ms->pmsa_rsc;
1043 old_unat = old_regs->ar_unat; 1081 old_unat = old_regs->ar_unat;
1044 copy_reg(&ms->pmsa_gr[1-1], ms->pmsa_nat_bits, &old_regs->r1, &old_unat); 1082 finish_pt_regs(old_regs, ms, &old_unat);
1045 copy_reg(&ms->pmsa_gr[2-1], ms->pmsa_nat_bits, &old_regs->r2, &old_unat);
1046 copy_reg(&ms->pmsa_gr[3-1], ms->pmsa_nat_bits, &old_regs->r3, &old_unat);
1047 copy_reg(&ms->pmsa_gr[8-1], ms->pmsa_nat_bits, &old_regs->r8, &old_unat);
1048 copy_reg(&ms->pmsa_gr[9-1], ms->pmsa_nat_bits, &old_regs->r9, &old_unat);
1049 copy_reg(&ms->pmsa_gr[10-1], ms->pmsa_nat_bits, &old_regs->r10, &old_unat);
1050 copy_reg(&ms->pmsa_gr[11-1], ms->pmsa_nat_bits, &old_regs->r11, &old_unat);
1051 copy_reg(&ms->pmsa_gr[12-1], ms->pmsa_nat_bits, &old_regs->r12, &old_unat);
1052 copy_reg(&ms->pmsa_gr[13-1], ms->pmsa_nat_bits, &old_regs->r13, &old_unat);
1053 copy_reg(&ms->pmsa_gr[14-1], ms->pmsa_nat_bits, &old_regs->r14, &old_unat);
1054 copy_reg(&ms->pmsa_gr[15-1], ms->pmsa_nat_bits, &old_regs->r15, &old_unat);
1055 if (ia64_psr(old_regs)->bn)
1056 bank = ms->pmsa_bank1_gr;
1057 else
1058 bank = ms->pmsa_bank0_gr;
1059 copy_reg(&bank[16-16], ms->pmsa_nat_bits, &old_regs->r16, &old_unat);
1060 copy_reg(&bank[17-16], ms->pmsa_nat_bits, &old_regs->r17, &old_unat);
1061 copy_reg(&bank[18-16], ms->pmsa_nat_bits, &old_regs->r18, &old_unat);
1062 copy_reg(&bank[19-16], ms->pmsa_nat_bits, &old_regs->r19, &old_unat);
1063 copy_reg(&bank[20-16], ms->pmsa_nat_bits, &old_regs->r20, &old_unat);
1064 copy_reg(&bank[21-16], ms->pmsa_nat_bits, &old_regs->r21, &old_unat);
1065 copy_reg(&bank[22-16], ms->pmsa_nat_bits, &old_regs->r22, &old_unat);
1066 copy_reg(&bank[23-16], ms->pmsa_nat_bits, &old_regs->r23, &old_unat);
1067 copy_reg(&bank[24-16], ms->pmsa_nat_bits, &old_regs->r24, &old_unat);
1068 copy_reg(&bank[25-16], ms->pmsa_nat_bits, &old_regs->r25, &old_unat);
1069 copy_reg(&bank[26-16], ms->pmsa_nat_bits, &old_regs->r26, &old_unat);
1070 copy_reg(&bank[27-16], ms->pmsa_nat_bits, &old_regs->r27, &old_unat);
1071 copy_reg(&bank[28-16], ms->pmsa_nat_bits, &old_regs->r28, &old_unat);
1072 copy_reg(&bank[29-16], ms->pmsa_nat_bits, &old_regs->r29, &old_unat);
1073 copy_reg(&bank[30-16], ms->pmsa_nat_bits, &old_regs->r30, &old_unat);
1074 copy_reg(&bank[31-16], ms->pmsa_nat_bits, &old_regs->r31, &old_unat);
1075 1083
1076 /* Next stack a struct switch_stack. mca_asm.S built a partial 1084 /* Next stack a struct switch_stack. mca_asm.S built a partial
1077 * switch_stack, copy it and fill in the blanks using pt_regs and 1085 * switch_stack, copy it and fill in the blanks using pt_regs and
@@ -1141,6 +1149,8 @@ ia64_mca_modify_original_stack(struct pt_regs *regs,
1141no_mod: 1149no_mod:
1142 mprintk(KERN_INFO "cpu %d, %s %s, original stack not modified\n", 1150 mprintk(KERN_INFO "cpu %d, %s %s, original stack not modified\n",
1143 smp_processor_id(), type, msg); 1151 smp_processor_id(), type, msg);
1152 old_unat = regs->ar_unat;
1153 finish_pt_regs(regs, ms, &old_unat);
1144 return previous_current; 1154 return previous_current;
1145} 1155}
1146 1156
diff --git a/arch/ia64/kernel/unaligned.c b/arch/ia64/kernel/unaligned.c
index 6db08599ebbc..776dd40397e2 100644
--- a/arch/ia64/kernel/unaligned.c
+++ b/arch/ia64/kernel/unaligned.c
@@ -60,7 +60,6 @@ dump (const char *str, void *vp, size_t len)
60 */ 60 */
61int no_unaligned_warning; 61int no_unaligned_warning;
62int unaligned_dump_stack; 62int unaligned_dump_stack;
63static int noprint_warning;
64 63
65/* 64/*
66 * For M-unit: 65 * For M-unit:
@@ -1357,9 +1356,8 @@ ia64_handle_unaligned (unsigned long ifa, struct pt_regs *regs)
1357 /* watch for command names containing %s */ 1356 /* watch for command names containing %s */
1358 printk(KERN_WARNING "%s", buf); 1357 printk(KERN_WARNING "%s", buf);
1359 } else { 1358 } else {
1360 if (no_unaligned_warning && !noprint_warning) { 1359 if (no_unaligned_warning) {
1361 noprint_warning = 1; 1360 printk_once(KERN_WARNING "%s(%d) encountered an "
1362 printk(KERN_WARNING "%s(%d) encountered an "
1363 "unaligned exception which required\n" 1361 "unaligned exception which required\n"
1364 "kernel assistance, which degrades " 1362 "kernel assistance, which degrades "
1365 "the performance of the application.\n" 1363 "the performance of the application.\n"
diff --git a/arch/ia64/mm/tlb.c b/arch/ia64/mm/tlb.c
index f426dc78d959..ee09d261f2e6 100644
--- a/arch/ia64/mm/tlb.c
+++ b/arch/ia64/mm/tlb.c
@@ -100,24 +100,36 @@ wrap_mmu_context (struct mm_struct *mm)
100 * this primitive it can be moved up to a spinaphore.h header. 100 * this primitive it can be moved up to a spinaphore.h header.
101 */ 101 */
102struct spinaphore { 102struct spinaphore {
103 atomic_t cur; 103 unsigned long ticket;
104 unsigned long serve;
104}; 105};
105 106
106static inline void spinaphore_init(struct spinaphore *ss, int val) 107static inline void spinaphore_init(struct spinaphore *ss, int val)
107{ 108{
108 atomic_set(&ss->cur, val); 109 ss->ticket = 0;
110 ss->serve = val;
109} 111}
110 112
111static inline void down_spin(struct spinaphore *ss) 113static inline void down_spin(struct spinaphore *ss)
112{ 114{
113 while (unlikely(!atomic_add_unless(&ss->cur, -1, 0))) 115 unsigned long t = ia64_fetchadd(1, &ss->ticket, acq), serve;
114 while (atomic_read(&ss->cur) == 0) 116
115 cpu_relax(); 117 if (time_before(t, ss->serve))
118 return;
119
120 ia64_invala();
121
122 for (;;) {
123 asm volatile ("ld4.c.nc %0=[%1]" : "=r"(serve) : "r"(&ss->serve) : "memory");
124 if (time_before(t, serve))
125 return;
126 cpu_relax();
127 }
116} 128}
117 129
118static inline void up_spin(struct spinaphore *ss) 130static inline void up_spin(struct spinaphore *ss)
119{ 131{
120 atomic_add(1, &ss->cur); 132 ia64_fetchadd(1, &ss->serve, rel);
121} 133}
122 134
123static struct spinaphore ptcg_sem; 135static struct spinaphore ptcg_sem;
diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index 7de76dd352fe..c0fca2c1c858 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -56,10 +56,13 @@ int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn,
56 if ((seg | reg) <= 255) { 56 if ((seg | reg) <= 255) {
57 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); 57 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
58 mode = 0; 58 mode = 0;
59 } else { 59 } else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
60 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); 60 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
61 mode = 1; 61 mode = 1;
62 } else {
63 return -EINVAL;
62 } 64 }
65
63 result = ia64_sal_pci_config_read(addr, mode, len, &data); 66 result = ia64_sal_pci_config_read(addr, mode, len, &data);
64 if (result != 0) 67 if (result != 0)
65 return -EINVAL; 68 return -EINVAL;
@@ -80,9 +83,11 @@ int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn,
80 if ((seg | reg) <= 255) { 83 if ((seg | reg) <= 255) {
81 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); 84 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
82 mode = 0; 85 mode = 0;
83 } else { 86 } else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
84 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); 87 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
85 mode = 1; 88 mode = 1;
89 } else {
90 return -EINVAL;
86 } 91 }
87 result = ia64_sal_pci_config_write(addr, mode, len, value); 92 result = ia64_sal_pci_config_write(addr, mode, len, value);
88 if (result != 0) 93 if (result != 0)
diff --git a/arch/ia64/sn/kernel/io_common.c b/arch/ia64/sn/kernel/io_common.c
index 25831c47c579..308e6595110e 100644
--- a/arch/ia64/sn/kernel/io_common.c
+++ b/arch/ia64/sn/kernel/io_common.c
@@ -119,7 +119,6 @@ sn_pcidev_info_get(struct pci_dev *dev)
119 * Additionally note that the struct sn_flush_device_war also has to be 119 * Additionally note that the struct sn_flush_device_war also has to be
120 * removed from arch/ia64/sn/include/xtalk/hubdev.h 120 * removed from arch/ia64/sn/include/xtalk/hubdev.h
121 */ 121 */
122static u8 war_implemented = 0;
123 122
124static s64 sn_device_fixup_war(u64 nasid, u64 widget, int device, 123static s64 sn_device_fixup_war(u64 nasid, u64 widget, int device,
125 struct sn_flush_device_common *common) 124 struct sn_flush_device_common *common)
@@ -128,11 +127,8 @@ static s64 sn_device_fixup_war(u64 nasid, u64 widget, int device,
128 struct sn_flush_device_war *dev_entry; 127 struct sn_flush_device_war *dev_entry;
129 struct ia64_sal_retval isrv = {0,0,0,0}; 128 struct ia64_sal_retval isrv = {0,0,0,0};
130 129
131 if (!war_implemented) { 130 printk_once(KERN_WARNING
132 printk(KERN_WARNING "PROM version < 4.50 -- implementing old " 131 "PROM version < 4.50 -- implementing old PROM flush WAR\n");
133 "PROM flush WAR\n");
134 war_implemented = 1;
135 }
136 132
137 war_list = kzalloc(DEV_PER_WIDGET * sizeof(*war_list), GFP_KERNEL); 133 war_list = kzalloc(DEV_PER_WIDGET * sizeof(*war_list), GFP_KERNEL);
138 BUG_ON(!war_list); 134 BUG_ON(!war_list);
diff --git a/arch/ia64/sn/kernel/sn2/sn_hwperf.c b/arch/ia64/sn/kernel/sn2/sn_hwperf.c
index 4c7e74790958..55ac3c4e11d2 100644
--- a/arch/ia64/sn/kernel/sn2/sn_hwperf.c
+++ b/arch/ia64/sn/kernel/sn2/sn_hwperf.c
@@ -786,17 +786,18 @@ sn_hwperf_ioctl(struct inode *in, struct file *fp, u32 op, unsigned long arg)
786 break; 786 break;
787 787
788 case SN_HWPERF_GET_OBJ_NODE: 788 case SN_HWPERF_GET_OBJ_NODE:
789 if (a.sz != sizeof(u64) || a.arg < 0) { 789 i = a.arg;
790 if (a.sz != sizeof(u64) || i < 0) {
790 r = -EINVAL; 791 r = -EINVAL;
791 goto error; 792 goto error;
792 } 793 }
793 if ((r = sn_hwperf_enum_objects(&nobj, &objs)) == 0) { 794 if ((r = sn_hwperf_enum_objects(&nobj, &objs)) == 0) {
794 if (a.arg >= nobj) { 795 if (i >= nobj) {
795 r = -EINVAL; 796 r = -EINVAL;
796 vfree(objs); 797 vfree(objs);
797 goto error; 798 goto error;
798 } 799 }
799 if (objs[(i = a.arg)].id != a.arg) { 800 if (objs[i].id != a.arg) {
800 for (i = 0; i < nobj; i++) { 801 for (i = 0; i < nobj; i++) {
801 if (objs[i].id == a.arg) 802 if (objs[i].id == a.arg)
802 break; 803 break;
diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig
index c41234f1b825..3a9319f93e89 100644
--- a/arch/m32r/Kconfig
+++ b/arch/m32r/Kconfig
@@ -11,6 +11,9 @@ config M32R
11 select HAVE_IDE 11 select HAVE_IDE
12 select HAVE_OPROFILE 12 select HAVE_OPROFILE
13 select INIT_ALL_POSSIBLE 13 select INIT_ALL_POSSIBLE
14 select HAVE_KERNEL_GZIP
15 select HAVE_KERNEL_BZIP2
16 select HAVE_KERNEL_LZMA
14 17
15config SBUS 18config SBUS
16 bool 19 bool
diff --git a/arch/m32r/boot/compressed/Makefile b/arch/m32r/boot/compressed/Makefile
index 560484ae35ec..177716b1d613 100644
--- a/arch/m32r/boot/compressed/Makefile
+++ b/arch/m32r/boot/compressed/Makefile
@@ -1,11 +1,11 @@
1# 1#
2# linux/arch/sh/boot/compressed/Makefile 2# linux/arch/m32r/boot/compressed/Makefile
3# 3#
4# create a compressed vmlinux image from the original vmlinux 4# create a compressed vmlinux image from the original vmlinux
5# 5#
6 6
7targets := vmlinux vmlinux.bin vmlinux.bin.gz head.o misc.o \ 7targets := vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 \
8 piggy.o vmlinux.lds 8 vmlinux.bin.lzma head.o misc.o piggy.o vmlinux.lds
9 9
10OBJECTS = $(obj)/head.o $(obj)/misc.o 10OBJECTS = $(obj)/head.o $(obj)/misc.o
11 11
@@ -27,6 +27,12 @@ $(obj)/vmlinux.bin: vmlinux FORCE
27$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE 27$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
28 $(call if_changed,gzip) 28 $(call if_changed,gzip)
29 29
30$(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE
31 $(call if_changed,bzip2)
32
33$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
34 $(call if_changed,lzma)
35
30CFLAGS_misc.o += -fpic 36CFLAGS_misc.o += -fpic
31 37
32ifdef CONFIG_MMU 38ifdef CONFIG_MMU
@@ -37,5 +43,9 @@ endif
37 43
38OBJCOPYFLAGS += -R .empty_zero_page 44OBJCOPYFLAGS += -R .empty_zero_page
39 45
40$(obj)/piggy.o: $(obj)/vmlinux.scr $(obj)/vmlinux.bin.gz FORCE 46suffix_$(CONFIG_KERNEL_GZIP) = gz
47suffix_$(CONFIG_KERNEL_BZIP2) = bz2
48suffix_$(CONFIG_KERNEL_LZMA) = lzma
49
50$(obj)/piggy.o: $(obj)/vmlinux.scr $(obj)/vmlinux.bin.$(suffix-y) FORCE
41 $(call if_changed,ld) 51 $(call if_changed,ld)
diff --git a/arch/m32r/boot/compressed/misc.c b/arch/m32r/boot/compressed/misc.c
index d394292498c0..370d60881977 100644
--- a/arch/m32r/boot/compressed/misc.c
+++ b/arch/m32r/boot/compressed/misc.c
@@ -9,140 +9,49 @@
9 * Adapted for SH by Stuart Menefy, Aug 1999 9 * Adapted for SH by Stuart Menefy, Aug 1999
10 * 10 *
11 * 2003-02-12: Support M32R by Takeo Takahashi 11 * 2003-02-12: Support M32R by Takeo Takahashi
12 * This is based on arch/sh/boot/compressed/misc.c.
13 */ 12 */
14 13
15#include <linux/string.h>
16
17/* 14/*
18 * gzip declarations 15 * gzip declarations
19 */ 16 */
20
21#define OF(args) args
22#define STATIC static 17#define STATIC static
23 18
24#undef memset 19#undef memset
25#undef memcpy 20#undef memcpy
26#define memzero(s, n) memset ((s), 0, (n)) 21#define memzero(s, n) memset ((s), 0, (n))
27 22
28typedef unsigned char uch;
29typedef unsigned short ush;
30typedef unsigned long ulg;
31
32#define WSIZE 0x8000 /* Window size must be at least 32k, */
33 /* and a power of two */
34
35static uch *inbuf; /* input buffer */
36static uch window[WSIZE]; /* Sliding window buffer */
37
38static unsigned insize = 0; /* valid bytes in inbuf */
39static unsigned inptr = 0; /* index of next byte to be processed in inbuf */
40static unsigned outcnt = 0; /* bytes in output buffer */
41
42/* gzip flag byte */
43#define ASCII_FLAG 0x01 /* bit 0 set: file probably ASCII text */
44#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */
45#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */
46#define ORIG_NAME 0x08 /* bit 3 set: original file name present */
47#define COMMENT 0x10 /* bit 4 set: file comment present */
48#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */
49#define RESERVED 0xC0 /* bit 6,7: reserved */
50
51#define get_byte() (inptr < insize ? inbuf[inptr++] : fill_inbuf())
52
53/* Diagnostic functions */
54#ifdef DEBUG
55# define Assert(cond,msg) {if(!(cond)) error(msg);}
56# define Trace(x) fprintf x
57# define Tracev(x) {if (verbose) fprintf x ;}
58# define Tracevv(x) {if (verbose>1) fprintf x ;}
59# define Tracec(c,x) {if (verbose && (c)) fprintf x ;}
60# define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}
61#else
62# define Assert(cond,msg)
63# define Trace(x)
64# define Tracev(x)
65# define Tracevv(x)
66# define Tracec(c,x)
67# define Tracecv(c,x)
68#endif
69
70static int fill_inbuf(void);
71static void flush_window(void);
72static void error(char *m); 23static void error(char *m);
73 24
74static unsigned char *input_data;
75static int input_len;
76
77static long bytes_out = 0;
78static uch *output_data;
79static unsigned long output_ptr = 0;
80
81#include "m32r_sio.c" 25#include "m32r_sio.c"
82 26
83static unsigned long free_mem_ptr; 27static unsigned long free_mem_ptr;
84static unsigned long free_mem_end_ptr; 28static unsigned long free_mem_end_ptr;
85 29
86#define HEAP_SIZE 0x10000 30#ifdef CONFIG_KERNEL_BZIP2
87 31static void *memset(void *s, int c, size_t n)
88#include "../../../../lib/inflate.c"
89
90void* memset(void* s, int c, size_t n)
91{ 32{
92 int i; 33 char *ss = s;
93 char *ss = (char*)s;
94 34
95 for (i=0;i<n;i++) ss[i] = c; 35 while (n--)
36 *ss++ = c;
96 return s; 37 return s;
97} 38}
39#endif
98 40
99void* memcpy(void* __dest, __const void* __src, 41#ifdef CONFIG_KERNEL_GZIP
100 size_t __n) 42#define BOOT_HEAP_SIZE 0x10000
101{ 43#include "../../../../lib/decompress_inflate.c"
102 int i; 44#endif
103 char *d = (char *)__dest, *s = (char *)__src;
104
105 for (i=0;i<__n;i++) d[i] = s[i];
106 return __dest;
107}
108
109/* ===========================================================================
110 * Fill the input buffer. This is called only when the buffer is empty
111 * and at least one byte is really needed.
112 */
113static int fill_inbuf(void)
114{
115 if (insize != 0) {
116 error("ran out of input data");
117 }
118
119 inbuf = input_data;
120 insize = input_len;
121 inptr = 1;
122 return inbuf[0];
123}
124 45
125/* =========================================================================== 46#ifdef CONFIG_KERNEL_BZIP2
126 * Write the output window window[0..outcnt-1] and update crc and bytes_out. 47#define BOOT_HEAP_SIZE 0x400000
127 * (Used for the decompressed data only.) 48#include "../../../../lib/decompress_bunzip2.c"
128 */ 49#endif
129static void flush_window(void)
130{
131 ulg c = crc; /* temporary variable */
132 unsigned n;
133 uch *in, *out, ch;
134 50
135 in = window; 51#ifdef CONFIG_KERNEL_LZMA
136 out = &output_data[output_ptr]; 52#define BOOT_HEAP_SIZE 0x10000
137 for (n = 0; n < outcnt; n++) { 53#include "../../../../lib/decompress_unlzma.c"
138 ch = *out++ = *in++; 54#endif
139 c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8);
140 }
141 crc = c;
142 bytes_out += (ulg)outcnt;
143 output_ptr += (ulg)outcnt;
144 outcnt = 0;
145}
146 55
147static void error(char *x) 56static void error(char *x)
148{ 57{
@@ -153,20 +62,20 @@ static void error(char *x)
153 while(1); /* Halt */ 62 while(1); /* Halt */
154} 63}
155 64
156/* return decompressed size */
157void 65void
158decompress_kernel(int mmu_on, unsigned char *zimage_data, 66decompress_kernel(int mmu_on, unsigned char *zimage_data,
159 unsigned int zimage_len, unsigned long heap) 67 unsigned int zimage_len, unsigned long heap)
160{ 68{
69 unsigned char *input_data = zimage_data;
70 int input_len = zimage_len;
71 unsigned char *output_data;
72
161 output_data = (unsigned char *)CONFIG_MEMORY_START + 0x2000 73 output_data = (unsigned char *)CONFIG_MEMORY_START + 0x2000
162 + (mmu_on ? 0x80000000 : 0); 74 + (mmu_on ? 0x80000000 : 0);
163 free_mem_ptr = heap; 75 free_mem_ptr = heap;
164 free_mem_end_ptr = free_mem_ptr + HEAP_SIZE; 76 free_mem_end_ptr = free_mem_ptr + BOOT_HEAP_SIZE;
165 input_data = zimage_data;
166 input_len = zimage_len;
167 77
168 makecrc(); 78 puts("\nDecompressing Linux... ");
169 puts("Uncompressing Linux... "); 79 decompress(input_data, input_len, NULL, NULL, output_data, NULL, error);
170 gunzip(); 80 puts("done.\nBooting the kernel.\n");
171 puts("Ok, booting the kernel.\n");
172} 81}
diff --git a/arch/m32r/kernel/smp.c b/arch/m32r/kernel/smp.c
index 8a88f1f0a3e2..31cef20b2996 100644
--- a/arch/m32r/kernel/smp.c
+++ b/arch/m32r/kernel/smp.c
@@ -806,7 +806,7 @@ unsigned long send_IPI_mask_phys(cpumask_t physid_mask, int ipi_num,
806 806
807 if (mask & ~physids_coerce(phys_cpu_present_map)) 807 if (mask & ~physids_coerce(phys_cpu_present_map))
808 BUG(); 808 BUG();
809 if (ipi_num >= NR_IPIS) 809 if (ipi_num >= NR_IPIS || ipi_num < 0)
810 BUG(); 810 BUG();
811 811
812 mask <<= IPI_SHIFT; 812 mask <<= IPI_SHIFT;
diff --git a/arch/m32r/kernel/time.c b/arch/m32r/kernel/time.c
index e7fee0f198d5..9cedcef11575 100644
--- a/arch/m32r/kernel/time.c
+++ b/arch/m32r/kernel/time.c
@@ -75,7 +75,7 @@ u32 arch_gettimeoffset(void)
75 count = 0; 75 count = 0;
76 76
77 count = (latch - count) * TICK_SIZE; 77 count = (latch - count) * TICK_SIZE;
78 elapsed_time = (count + latch / 2) / latch; 78 elapsed_time = DIV_ROUND_CLOSEST(count, latch);
79 /* NOTE: LATCH is equal to the "interval" value (= reload count). */ 79 /* NOTE: LATCH is equal to the "interval" value (= reload count). */
80 80
81#else /* CONFIG_SMP */ 81#else /* CONFIG_SMP */
@@ -93,7 +93,7 @@ u32 arch_gettimeoffset(void)
93 p_count = count; 93 p_count = count;
94 94
95 count = (latch - count) * TICK_SIZE; 95 count = (latch - count) * TICK_SIZE;
96 elapsed_time = (count + latch / 2) / latch; 96 elapsed_time = DIV_ROUND_CLOSEST(count, latch);
97 /* NOTE: LATCH is equal to the "interval" value (= reload count). */ 97 /* NOTE: LATCH is equal to the "interval" value (= reload count). */
98#endif /* CONFIG_SMP */ 98#endif /* CONFIG_SMP */
99#elif defined(CONFIG_CHIP_M32310) 99#elif defined(CONFIG_CHIP_M32310)
@@ -211,7 +211,7 @@ void __init time_init(void)
211 211
212 bus_clock = boot_cpu_data.bus_clock; 212 bus_clock = boot_cpu_data.bus_clock;
213 divide = boot_cpu_data.timer_divide; 213 divide = boot_cpu_data.timer_divide;
214 latch = (bus_clock/divide + HZ / 2) / HZ; 214 latch = DIV_ROUND_CLOSEST(bus_clock/divide, HZ);
215 215
216 printk("Timer start : latch = %ld\n", latch); 216 printk("Timer start : latch = %ld\n", latch);
217 217
diff --git a/arch/m32r/kernel/vmlinux.lds.S b/arch/m32r/kernel/vmlinux.lds.S
index 8ceb6181d805..7da94eaa082b 100644
--- a/arch/m32r/kernel/vmlinux.lds.S
+++ b/arch/m32r/kernel/vmlinux.lds.S
@@ -42,6 +42,8 @@ SECTIONS
42 _etext = .; /* End of text section */ 42 _etext = .; /* End of text section */
43 43
44 EXCEPTION_TABLE(16) 44 EXCEPTION_TABLE(16)
45 NOTES
46
45 RODATA 47 RODATA
46 RW_DATA_SECTION(32, PAGE_SIZE, THREAD_SIZE) 48 RW_DATA_SECTION(32, PAGE_SIZE, THREAD_SIZE)
47 _edata = .; /* End of data section */ 49 _edata = .; /* End of data section */
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 29dd8489ffec..ecdc19a299b2 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -561,7 +561,7 @@ config HPAPCI
561 561
562config MVME147_SCC 562config MVME147_SCC
563 bool "SCC support for MVME147 serial ports" 563 bool "SCC support for MVME147 serial ports"
564 depends on MVME147 564 depends on MVME147 && BROKEN
565 help 565 help
566 This is the driver for the serial ports on the Motorola MVME147 566 This is the driver for the serial ports on the Motorola MVME147
567 boards. Everyone using one of these boards should say Y here. 567 boards. Everyone using one of these boards should say Y here.
@@ -576,14 +576,14 @@ config SERIAL167
576 576
577config MVME162_SCC 577config MVME162_SCC
578 bool "SCC support for MVME162 serial ports" 578 bool "SCC support for MVME162 serial ports"
579 depends on MVME16x 579 depends on MVME16x && BROKEN
580 help 580 help
581 This is the driver for the serial ports on the Motorola MVME162 and 581 This is the driver for the serial ports on the Motorola MVME162 and
582 172 boards. Everyone using one of these boards should say Y here. 582 172 boards. Everyone using one of these boards should say Y here.
583 583
584config BVME6000_SCC 584config BVME6000_SCC
585 bool "SCC support for BVME6000 serial ports" 585 bool "SCC support for BVME6000 serial ports"
586 depends on BVME6000 586 depends on BVME6000 && BROKEN
587 help 587 help
588 This is the driver for the serial ports on the BVME4000 and BVME6000 588 This is the driver for the serial ports on the BVME4000 and BVME6000
589 boards from BVM Ltd. Everyone using one of these boards should say 589 boards from BVM Ltd. Everyone using one of these boards should say
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 705a7a9170f3..03bd56a2fb6e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1012,9 +1012,9 @@ config BOOT_ELF32
1012 1012
1013config MIPS_L1_CACHE_SHIFT 1013config MIPS_L1_CACHE_SHIFT
1014 int 1014 int
1015 default "4" if MACH_DECSTATION || MIKROTIK_RB532 1015 default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL
1016 default "6" if MIPS_CPU_SCACHE
1016 default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON 1017 default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
1017 default "4" if PMC_MSP4200_EVAL
1018 default "5" 1018 default "5"
1019 1019
1020config HAVE_STD_PC_SERIAL_PORT 1020config HAVE_STD_PC_SERIAL_PORT
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index c88c821b4c36..d670928afcfd 100644
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -354,6 +354,28 @@ static void au1x_ic1_ack(unsigned int irq_nr)
354 au_sync(); 354 au_sync();
355} 355}
356 356
357static void au1x_ic0_maskack(unsigned int irq_nr)
358{
359 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
360
361 au_writel(1 << bit, IC0_WAKECLR);
362 au_writel(1 << bit, IC0_MASKCLR);
363 au_writel(1 << bit, IC0_RISINGCLR);
364 au_writel(1 << bit, IC0_FALLINGCLR);
365 au_sync();
366}
367
368static void au1x_ic1_maskack(unsigned int irq_nr)
369{
370 unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
371
372 au_writel(1 << bit, IC1_WAKECLR);
373 au_writel(1 << bit, IC1_MASKCLR);
374 au_writel(1 << bit, IC1_RISINGCLR);
375 au_writel(1 << bit, IC1_FALLINGCLR);
376 au_sync();
377}
378
357static int au1x_ic1_setwake(unsigned int irq, unsigned int on) 379static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
358{ 380{
359 unsigned int bit = irq - AU1000_INTC1_INT_BASE; 381 unsigned int bit = irq - AU1000_INTC1_INT_BASE;
@@ -379,25 +401,21 @@ static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
379/* 401/*
380 * irq_chips for both ICs; this way the mask handlers can be 402 * irq_chips for both ICs; this way the mask handlers can be
381 * as short as possible. 403 * as short as possible.
382 *
383 * NOTE: the ->ack() callback is used by the handle_edge_irq
384 * flowhandler only, the ->mask_ack() one by handle_level_irq,
385 * so no need for an irq_chip for each type of irq (level/edge).
386 */ 404 */
387static struct irq_chip au1x_ic0_chip = { 405static struct irq_chip au1x_ic0_chip = {
388 .name = "Alchemy-IC0", 406 .name = "Alchemy-IC0",
389 .ack = au1x_ic0_ack, /* edge */ 407 .ack = au1x_ic0_ack,
390 .mask = au1x_ic0_mask, 408 .mask = au1x_ic0_mask,
391 .mask_ack = au1x_ic0_mask, /* level */ 409 .mask_ack = au1x_ic0_maskack,
392 .unmask = au1x_ic0_unmask, 410 .unmask = au1x_ic0_unmask,
393 .set_type = au1x_ic_settype, 411 .set_type = au1x_ic_settype,
394}; 412};
395 413
396static struct irq_chip au1x_ic1_chip = { 414static struct irq_chip au1x_ic1_chip = {
397 .name = "Alchemy-IC1", 415 .name = "Alchemy-IC1",
398 .ack = au1x_ic1_ack, /* edge */ 416 .ack = au1x_ic1_ack,
399 .mask = au1x_ic1_mask, 417 .mask = au1x_ic1_mask,
400 .mask_ack = au1x_ic1_mask, /* level */ 418 .mask_ack = au1x_ic1_maskack,
401 .unmask = au1x_ic1_unmask, 419 .unmask = au1x_ic1_unmask,
402 .set_type = au1x_ic_settype, 420 .set_type = au1x_ic_settype,
403 .set_wake = au1x_ic1_setwake, 421 .set_wake = au1x_ic1_setwake,
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index cc32c69a74ad..45b61c9b82b9 100644
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -69,6 +69,7 @@ void __init board_setup(void)
69#else 69#else
70 au_writel(0xf, Au1500_PCI_CFG); 70 au_writel(0xf, Au1500_PCI_CFG);
71#endif 71#endif
72 board_pci_idsel = mtx1_pci_idsel;
72#endif 73#endif
73 74
74 /* Initialize sys_pinfunc */ 75 /* Initialize sys_pinfunc */
@@ -85,8 +86,6 @@ void __init board_setup(void)
85 alchemy_gpio_direction_output(211, 1); /* green on */ 86 alchemy_gpio_direction_output(211, 1); /* green on */
86 alchemy_gpio_direction_output(212, 0); /* red off */ 87 alchemy_gpio_direction_output(212, 0); /* red off */
87 88
88 board_pci_idsel = mtx1_pci_idsel;
89
90 printk(KERN_INFO "4G Systems MTX-1 Board\n"); 89 printk(KERN_INFO "4G Systems MTX-1 Board\n");
91} 90}
92 91
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index e2278c04459d..835f3f0319ca 100644
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -503,6 +503,7 @@ static int __init ar7_register_devices(void)
503{ 503{
504 u16 chip_id; 504 u16 chip_id;
505 int res; 505 int res;
506 u32 *bootcr, val;
506#ifdef CONFIG_SERIAL_8250 507#ifdef CONFIG_SERIAL_8250
507 static struct uart_port uart_port[2]; 508 static struct uart_port uart_port[2];
508 509
@@ -595,7 +596,13 @@ static int __init ar7_register_devices(void)
595 596
596 ar7_wdt_res.end = ar7_wdt_res.start + 0x20; 597 ar7_wdt_res.end = ar7_wdt_res.start + 0x20;
597 598
598 res = platform_device_register(&ar7_wdt); 599 bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
600 val = *bootcr;
601 iounmap(bootcr);
602
603 /* Register watchdog only if enabled in hardware */
604 if (val & AR7_WDT_HW_ENA)
605 res = platform_device_register(&ar7_wdt);
599 606
600 return res; 607 return res;
601} 608}
diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile
index c146d1ededed..00064b660809 100644
--- a/arch/mips/bcm63xx/Makefile
+++ b/arch/mips/bcm63xx/Makefile
@@ -1,5 +1,5 @@
1obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \ 1obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
2 dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o 2 dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o
3obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 3obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
4 4
5obj-y += boards/ 5obj-y += boards/
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index 78e155d21be6..05a35cf5963d 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -24,7 +24,6 @@
24#include <bcm63xx_dev_enet.h> 24#include <bcm63xx_dev_enet.h>
25#include <bcm63xx_dev_dsp.h> 25#include <bcm63xx_dev_dsp.h>
26#include <bcm63xx_dev_pcmcia.h> 26#include <bcm63xx_dev_pcmcia.h>
27#include <bcm63xx_dev_uart.h>
28#include <board_bcm963xx.h> 27#include <board_bcm963xx.h>
29 28
30#define PFX "board_bcm963xx: " 29#define PFX "board_bcm963xx: "
@@ -794,8 +793,6 @@ int __init board_register_devices(void)
794{ 793{
795 u32 val; 794 u32 val;
796 795
797 bcm63xx_uart_register();
798
799 if (board.has_pccard) 796 if (board.has_pccard)
800 bcm63xx_pcmcia_register(); 797 bcm63xx_pcmcia_register();
801 798
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index 6dc43f0483e8..70378bb5e3f9 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -10,6 +10,7 @@
10#include <linux/kernel.h> 10#include <linux/kernel.h>
11#include <linux/module.h> 11#include <linux/module.h>
12#include <linux/cpu.h> 12#include <linux/cpu.h>
13#include <asm/cpu-info.h>
13#include <bcm63xx_cpu.h> 14#include <bcm63xx_cpu.h>
14#include <bcm63xx_regs.h> 15#include <bcm63xx_regs.h>
15#include <bcm63xx_io.h> 16#include <bcm63xx_io.h>
@@ -284,6 +285,7 @@ void __init bcm63xx_cpu_init(void)
284{ 285{
285 unsigned int tmp, expected_cpu_id; 286 unsigned int tmp, expected_cpu_id;
286 struct cpuinfo_mips *c = &current_cpu_data; 287 struct cpuinfo_mips *c = &current_cpu_data;
288 unsigned int cpu = smp_processor_id();
287 289
288 /* soc registers location depends on cpu type */ 290 /* soc registers location depends on cpu type */
289 expected_cpu_id = 0; 291 expected_cpu_id = 0;
@@ -293,6 +295,7 @@ void __init bcm63xx_cpu_init(void)
293 * BCM6338 as the same PrId as BCM3302 see arch/mips/kernel/cpu-probe.c 295 * BCM6338 as the same PrId as BCM3302 see arch/mips/kernel/cpu-probe.c
294 */ 296 */
295 case CPU_BCM3302: 297 case CPU_BCM3302:
298 __cpu_name[cpu] = "Broadcom BCM6338";
296 expected_cpu_id = BCM6338_CPU_ID; 299 expected_cpu_id = BCM6338_CPU_ID;
297 bcm63xx_regs_base = bcm96338_regs_base; 300 bcm63xx_regs_base = bcm96338_regs_base;
298 bcm63xx_irqs = bcm96338_irqs; 301 bcm63xx_irqs = bcm96338_irqs;
diff --git a/arch/mips/bcm63xx/dev-uart.c b/arch/mips/bcm63xx/dev-uart.c
index 5f3d89c4a988..b0519461ad9b 100644
--- a/arch/mips/bcm63xx/dev-uart.c
+++ b/arch/mips/bcm63xx/dev-uart.c
@@ -10,7 +10,6 @@
10#include <linux/kernel.h> 10#include <linux/kernel.h>
11#include <linux/platform_device.h> 11#include <linux/platform_device.h>
12#include <bcm63xx_cpu.h> 12#include <bcm63xx_cpu.h>
13#include <bcm63xx_dev_uart.h>
14 13
15static struct resource uart_resources[] = { 14static struct resource uart_resources[] = {
16 { 15 {
@@ -39,3 +38,4 @@ int __init bcm63xx_uart_register(void)
39 uart_resources[1].start = bcm63xx_get_irq_number(IRQ_UART0); 38 uart_resources[1].start = bcm63xx_get_irq_number(IRQ_UART0);
40 return platform_device_register(&bcm63xx_uart_device); 39 return platform_device_register(&bcm63xx_uart_device);
41} 40}
41arch_initcall(bcm63xx_uart_register);
diff --git a/arch/mips/bcm63xx/dev-wdt.c b/arch/mips/bcm63xx/dev-wdt.c
new file mode 100644
index 000000000000..3e6c716a4c11
--- /dev/null
+++ b/arch/mips/bcm63xx/dev-wdt.c
@@ -0,0 +1,37 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
7 */
8
9#include <linux/init.h>
10#include <linux/kernel.h>
11#include <linux/platform_device.h>
12#include <bcm63xx_cpu.h>
13
14static struct resource wdt_resources[] = {
15 {
16 .start = -1, /* filled at runtime */
17 .end = -1, /* filled at runtime */
18 .flags = IORESOURCE_MEM,
19 },
20};
21
22static struct platform_device bcm63xx_wdt_device = {
23 .name = "bcm63xx-wdt",
24 .id = 0,
25 .num_resources = ARRAY_SIZE(wdt_resources),
26 .resource = wdt_resources,
27};
28
29int __init bcm63xx_wdt_register(void)
30{
31 wdt_resources[0].start = bcm63xx_regset_address(RSET_WDT);
32 wdt_resources[0].end = wdt_resources[0].start;
33 wdt_resources[0].end += RSET_WDT_SIZE - 1;
34
35 return platform_device_register(&bcm63xx_wdt_device);
36}
37arch_initcall(bcm63xx_wdt_register);
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
index b18a0ca926fa..d0056598fbfc 100644
--- a/arch/mips/bcm63xx/setup.c
+++ b/arch/mips/bcm63xx/setup.c
@@ -75,7 +75,9 @@ void bcm63xx_machine_reboot(void)
75 bcm6348_a1_reboot(); 75 bcm6348_a1_reboot();
76 76
77 printk(KERN_INFO "triggering watchdog soft-reset...\n"); 77 printk(KERN_INFO "triggering watchdog soft-reset...\n");
78 bcm_perf_writel(SYS_PLL_SOFT_RESET, PERF_SYS_PLL_CTL_REG); 78 reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
79 reg |= SYS_PLL_SOFT_RESET;
80 bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG);
79 while (1) 81 while (1)
80 ; 82 ;
81} 83}
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index 384f1842bfb1..6f2acf09328d 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -17,6 +17,15 @@ DEFINE_RWLOCK(octeon_irq_ciu0_rwlock);
17DEFINE_RWLOCK(octeon_irq_ciu1_rwlock); 17DEFINE_RWLOCK(octeon_irq_ciu1_rwlock);
18DEFINE_SPINLOCK(octeon_irq_msi_lock); 18DEFINE_SPINLOCK(octeon_irq_msi_lock);
19 19
20static int octeon_coreid_for_cpu(int cpu)
21{
22#ifdef CONFIG_SMP
23 return cpu_logical_map(cpu);
24#else
25 return cvmx_get_core_num();
26#endif
27}
28
20static void octeon_irq_core_ack(unsigned int irq) 29static void octeon_irq_core_ack(unsigned int irq)
21{ 30{
22 unsigned int bit = irq - OCTEON_IRQ_SW0; 31 unsigned int bit = irq - OCTEON_IRQ_SW0;
@@ -152,11 +161,10 @@ static void octeon_irq_ciu0_disable(unsigned int irq)
152 int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ 161 int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
153 unsigned long flags; 162 unsigned long flags;
154 uint64_t en0; 163 uint64_t en0;
155#ifdef CONFIG_SMP
156 int cpu; 164 int cpu;
157 write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags); 165 write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags);
158 for_each_online_cpu(cpu) { 166 for_each_online_cpu(cpu) {
159 int coreid = cpu_logical_map(cpu); 167 int coreid = octeon_coreid_for_cpu(cpu);
160 en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); 168 en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
161 en0 &= ~(1ull << bit); 169 en0 &= ~(1ull << bit);
162 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); 170 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
@@ -167,26 +175,57 @@ static void octeon_irq_ciu0_disable(unsigned int irq)
167 */ 175 */
168 cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); 176 cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
169 write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags); 177 write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags);
170#else 178}
171 int coreid = cvmx_get_core_num(); 179
172 local_irq_save(flags); 180/*
173 en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); 181 * Enable the irq on the current core for chips that have the EN*_W1{S,C}
174 en0 &= ~(1ull << bit); 182 * registers.
175 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); 183 */
176 cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); 184static void octeon_irq_ciu0_enable_v2(unsigned int irq)
177 local_irq_restore(flags); 185{
178#endif 186 int index = cvmx_get_core_num() * 2;
187 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
188
189 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
190}
191
192/*
193 * Disable the irq on the current core for chips that have the EN*_W1{S,C}
194 * registers.
195 */
196static void octeon_irq_ciu0_disable_v2(unsigned int irq)
197{
198 int index = cvmx_get_core_num() * 2;
199 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
200
201 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
202}
203
204/*
205 * Disable the irq on the all cores for chips that have the EN*_W1{S,C}
206 * registers.
207 */
208static void octeon_irq_ciu0_disable_all_v2(unsigned int irq)
209{
210 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
211 int index;
212 int cpu;
213 for_each_online_cpu(cpu) {
214 index = octeon_coreid_for_cpu(cpu) * 2;
215 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
216 }
179} 217}
180 218
181#ifdef CONFIG_SMP 219#ifdef CONFIG_SMP
182static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest) 220static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest)
183{ 221{
184 int cpu; 222 int cpu;
223 unsigned long flags;
185 int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ 224 int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
186 225
187 write_lock(&octeon_irq_ciu0_rwlock); 226 write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags);
188 for_each_online_cpu(cpu) { 227 for_each_online_cpu(cpu) {
189 int coreid = cpu_logical_map(cpu); 228 int coreid = octeon_coreid_for_cpu(cpu);
190 uint64_t en0 = 229 uint64_t en0 =
191 cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); 230 cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
192 if (cpumask_test_cpu(cpu, dest)) 231 if (cpumask_test_cpu(cpu, dest))
@@ -200,11 +239,45 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *
200 * of them are done. 239 * of them are done.
201 */ 240 */
202 cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); 241 cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
203 write_unlock(&octeon_irq_ciu0_rwlock); 242 write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags);
204 243
205 return 0; 244 return 0;
206} 245}
246
247/*
248 * Set affinity for the irq for chips that have the EN*_W1{S,C}
249 * registers.
250 */
251static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq,
252 const struct cpumask *dest)
253{
254 int cpu;
255 int index;
256 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
257 for_each_online_cpu(cpu) {
258 index = octeon_coreid_for_cpu(cpu) * 2;
259 if (cpumask_test_cpu(cpu, dest))
260 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
261 else
262 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
263 }
264 return 0;
265}
266#endif
267
268/*
269 * Newer octeon chips have support for lockless CIU operation.
270 */
271static struct irq_chip octeon_irq_chip_ciu0_v2 = {
272 .name = "CIU0",
273 .enable = octeon_irq_ciu0_enable_v2,
274 .disable = octeon_irq_ciu0_disable_all_v2,
275 .ack = octeon_irq_ciu0_disable_v2,
276 .eoi = octeon_irq_ciu0_enable_v2,
277#ifdef CONFIG_SMP
278 .set_affinity = octeon_irq_ciu0_set_affinity_v2,
207#endif 279#endif
280};
208 281
209static struct irq_chip octeon_irq_chip_ciu0 = { 282static struct irq_chip octeon_irq_chip_ciu0 = {
210 .name = "CIU0", 283 .name = "CIU0",
@@ -269,11 +342,10 @@ static void octeon_irq_ciu1_disable(unsigned int irq)
269 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ 342 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
270 unsigned long flags; 343 unsigned long flags;
271 uint64_t en1; 344 uint64_t en1;
272#ifdef CONFIG_SMP
273 int cpu; 345 int cpu;
274 write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags); 346 write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags);
275 for_each_online_cpu(cpu) { 347 for_each_online_cpu(cpu) {
276 int coreid = cpu_logical_map(cpu); 348 int coreid = octeon_coreid_for_cpu(cpu);
277 en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); 349 en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
278 en1 &= ~(1ull << bit); 350 en1 &= ~(1ull << bit);
279 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); 351 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
@@ -284,26 +356,58 @@ static void octeon_irq_ciu1_disable(unsigned int irq)
284 */ 356 */
285 cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); 357 cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
286 write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags); 358 write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags);
287#else 359}
288 int coreid = cvmx_get_core_num(); 360
289 local_irq_save(flags); 361/*
290 en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); 362 * Enable the irq on the current core for chips that have the EN*_W1{S,C}
291 en1 &= ~(1ull << bit); 363 * registers.
292 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); 364 */
293 cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); 365static void octeon_irq_ciu1_enable_v2(unsigned int irq)
294 local_irq_restore(flags); 366{
295#endif 367 int index = cvmx_get_core_num() * 2 + 1;
368 u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
369
370 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
371}
372
373/*
374 * Disable the irq on the current core for chips that have the EN*_W1{S,C}
375 * registers.
376 */
377static void octeon_irq_ciu1_disable_v2(unsigned int irq)
378{
379 int index = cvmx_get_core_num() * 2 + 1;
380 u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
381
382 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
383}
384
385/*
386 * Disable the irq on the all cores for chips that have the EN*_W1{S,C}
387 * registers.
388 */
389static void octeon_irq_ciu1_disable_all_v2(unsigned int irq)
390{
391 u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
392 int index;
393 int cpu;
394 for_each_online_cpu(cpu) {
395 index = octeon_coreid_for_cpu(cpu) * 2 + 1;
396 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
397 }
296} 398}
297 399
298#ifdef CONFIG_SMP 400#ifdef CONFIG_SMP
299static int octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask *dest) 401static int octeon_irq_ciu1_set_affinity(unsigned int irq,
402 const struct cpumask *dest)
300{ 403{
301 int cpu; 404 int cpu;
405 unsigned long flags;
302 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ 406 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
303 407
304 write_lock(&octeon_irq_ciu1_rwlock); 408 write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags);
305 for_each_online_cpu(cpu) { 409 for_each_online_cpu(cpu) {
306 int coreid = cpu_logical_map(cpu); 410 int coreid = octeon_coreid_for_cpu(cpu);
307 uint64_t en1 = 411 uint64_t en1 =
308 cvmx_read_csr(CVMX_CIU_INTX_EN1 412 cvmx_read_csr(CVMX_CIU_INTX_EN1
309 (coreid * 2 + 1)); 413 (coreid * 2 + 1));
@@ -318,12 +422,46 @@ static int octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask *
318 * of them are done. 422 * of them are done.
319 */ 423 */
320 cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); 424 cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
321 write_unlock(&octeon_irq_ciu1_rwlock); 425 write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags);
426
427 return 0;
428}
322 429
430/*
431 * Set affinity for the irq for chips that have the EN*_W1{S,C}
432 * registers.
433 */
434static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq,
435 const struct cpumask *dest)
436{
437 int cpu;
438 int index;
439 u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
440 for_each_online_cpu(cpu) {
441 index = octeon_coreid_for_cpu(cpu) * 2 + 1;
442 if (cpumask_test_cpu(cpu, dest))
443 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
444 else
445 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
446 }
323 return 0; 447 return 0;
324} 448}
325#endif 449#endif
326 450
451/*
452 * Newer octeon chips have support for lockless CIU operation.
453 */
454static struct irq_chip octeon_irq_chip_ciu1_v2 = {
455 .name = "CIU0",
456 .enable = octeon_irq_ciu1_enable_v2,
457 .disable = octeon_irq_ciu1_disable_all_v2,
458 .ack = octeon_irq_ciu1_disable_v2,
459 .eoi = octeon_irq_ciu1_enable_v2,
460#ifdef CONFIG_SMP
461 .set_affinity = octeon_irq_ciu1_set_affinity_v2,
462#endif
463};
464
327static struct irq_chip octeon_irq_chip_ciu1 = { 465static struct irq_chip octeon_irq_chip_ciu1 = {
328 .name = "CIU1", 466 .name = "CIU1",
329 .enable = octeon_irq_ciu1_enable, 467 .enable = octeon_irq_ciu1_enable,
@@ -420,6 +558,8 @@ static struct irq_chip octeon_irq_chip_msi = {
420void __init arch_init_irq(void) 558void __init arch_init_irq(void)
421{ 559{
422 int irq; 560 int irq;
561 struct irq_chip *chip0;
562 struct irq_chip *chip1;
423 563
424#ifdef CONFIG_SMP 564#ifdef CONFIG_SMP
425 /* Set the default affinity to the boot cpu. */ 565 /* Set the default affinity to the boot cpu. */
@@ -430,6 +570,16 @@ void __init arch_init_irq(void)
430 if (NR_IRQS < OCTEON_IRQ_LAST) 570 if (NR_IRQS < OCTEON_IRQ_LAST)
431 pr_err("octeon_irq_init: NR_IRQS is set too low\n"); 571 pr_err("octeon_irq_init: NR_IRQS is set too low\n");
432 572
573 if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
574 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
575 OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) {
576 chip0 = &octeon_irq_chip_ciu0_v2;
577 chip1 = &octeon_irq_chip_ciu1_v2;
578 } else {
579 chip0 = &octeon_irq_chip_ciu0;
580 chip1 = &octeon_irq_chip_ciu1;
581 }
582
433 /* 0 - 15 reserved for i8259 master and slave controller. */ 583 /* 0 - 15 reserved for i8259 master and slave controller. */
434 584
435 /* 17 - 23 Mips internal */ 585 /* 17 - 23 Mips internal */
@@ -440,14 +590,12 @@ void __init arch_init_irq(void)
440 590
441 /* 24 - 87 CIU_INT_SUM0 */ 591 /* 24 - 87 CIU_INT_SUM0 */
442 for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) { 592 for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
443 set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu0, 593 set_irq_chip_and_handler(irq, chip0, handle_percpu_irq);
444 handle_percpu_irq);
445 } 594 }
446 595
447 /* 88 - 151 CIU_INT_SUM1 */ 596 /* 88 - 151 CIU_INT_SUM1 */
448 for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED151; irq++) { 597 for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED151; irq++) {
449 set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu1, 598 set_irq_chip_and_handler(irq, chip1, handle_percpu_irq);
450 handle_percpu_irq);
451 } 599 }
452 600
453#ifdef CONFIG_PCI_MSI 601#ifdef CONFIG_PCI_MSI
@@ -505,14 +653,10 @@ asmlinkage void plat_irq_dispatch(void)
505#ifdef CONFIG_HOTPLUG_CPU 653#ifdef CONFIG_HOTPLUG_CPU
506static int is_irq_enabled_on_cpu(unsigned int irq, unsigned int cpu) 654static int is_irq_enabled_on_cpu(unsigned int irq, unsigned int cpu)
507{ 655{
508 unsigned int isset; 656 unsigned int isset;
509#ifdef CONFIG_SMP 657 int coreid = octeon_coreid_for_cpu(cpu);
510 int coreid = cpu_logical_map(cpu);
511#else
512 int coreid = cvmx_get_core_num();
513#endif
514 int bit = (irq < OCTEON_IRQ_WDOG0) ? 658 int bit = (irq < OCTEON_IRQ_WDOG0) ?
515 irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0; 659 irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0;
516 if (irq < 64) { 660 if (irq < 64) {
517 isset = (cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)) & 661 isset = (cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)) &
518 (1ull << bit)) >> bit; 662 (1ull << bit)) >> bit;
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index 32d51a31dc48..c198efdf583e 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -65,11 +65,12 @@ void octeon_send_ipi_single(int cpu, unsigned int action)
65 cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action); 65 cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
66} 66}
67 67
68static inline void octeon_send_ipi_mask(cpumask_t mask, unsigned int action) 68static inline void octeon_send_ipi_mask(const struct cpumask *mask,
69 unsigned int action)
69{ 70{
70 unsigned int i; 71 unsigned int i;
71 72
72 for_each_cpu_mask(i, mask) 73 for_each_cpu_mask(i, *mask)
73 octeon_send_ipi_single(i, action); 74 octeon_send_ipi_single(i, action);
74} 75}
75 76
diff --git a/arch/mips/include/asm/fixmap.h b/arch/mips/include/asm/fixmap.h
index efeddc8db8b1..0b89b83e2055 100644
--- a/arch/mips/include/asm/fixmap.h
+++ b/arch/mips/include/asm/fixmap.h
@@ -48,9 +48,9 @@ enum fixed_addresses {
48#define FIX_N_COLOURS 8 48#define FIX_N_COLOURS 8
49 FIX_CMAP_BEGIN, 49 FIX_CMAP_BEGIN,
50#ifdef CONFIG_MIPS_MT_SMTC 50#ifdef CONFIG_MIPS_MT_SMTC
51 FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS), 51 FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS * 2),
52#else 52#else
53 FIX_CMAP_END = FIX_CMAP_BEGIN + FIX_N_COLOURS, 53 FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * 2),
54#endif 54#endif
55#ifdef CONFIG_HIGHMEM 55#ifdef CONFIG_HIGHMEM
56 /* reserved pte's for temporary kernel mappings */ 56 /* reserved pte's for temporary kernel mappings */
diff --git a/arch/mips/include/asm/gcmpregs.h b/arch/mips/include/asm/gcmpregs.h
index 36fd969d64d6..c0cf76a2ca89 100644
--- a/arch/mips/include/asm/gcmpregs.h
+++ b/arch/mips/include/asm/gcmpregs.h
@@ -19,15 +19,20 @@
19#define GCMP_GDB_OFS 0x8000 /* Global Debug Block */ 19#define GCMP_GDB_OFS 0x8000 /* Global Debug Block */
20 20
21/* Offsets to individual GCMP registers from GCMP base */ 21/* Offsets to individual GCMP registers from GCMP base */
22#define GCMPOFS(block, tag, reg) (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS) 22#define GCMPOFS(block, tag, reg) \
23 (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS)
24#define GCMPOFSn(block, tag, reg, n) \
25 (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS(n))
23 26
24#define GCMPGCBOFS(reg) GCMPOFS(GCB, GCB, reg) 27#define GCMPGCBOFS(reg) GCMPOFS(GCB, GCB, reg)
28#define GCMPGCBOFSn(reg, n) GCMPOFSn(GCB, GCB, reg, n)
25#define GCMPCLCBOFS(reg) GCMPOFS(CLCB, CCB, reg) 29#define GCMPCLCBOFS(reg) GCMPOFS(CLCB, CCB, reg)
26#define GCMPCOCBOFS(reg) GCMPOFS(COCB, CCB, reg) 30#define GCMPCOCBOFS(reg) GCMPOFS(COCB, CCB, reg)
27#define GCMPGDBOFS(reg) GCMPOFS(GDB, GDB, reg) 31#define GCMPGDBOFS(reg) GCMPOFS(GDB, GDB, reg)
28 32
29/* GCMP register access */ 33/* GCMP register access */
30#define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg)) 34#define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg))
35#define GCMPGCBn(reg, n) REGP(_gcmp_base, GCMPGCBOFSn(reg, n))
31#define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg)) 36#define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg))
32#define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg)) 37#define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg))
33#define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg)) 38#define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg))
@@ -49,10 +54,10 @@
49#define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17) 54#define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17)
50#define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0 55#define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0
51#define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2) 56#define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2)
52#define GCMP_GCB_GCMPB_CMDEFTGT_MEM 0 57#define GCMP_GCB_GCMPB_CMDEFTGT_DISABLED 0
53#define GCMP_GCB_GCMPB_CMDEFTGT_MEM1 1 58#define GCMP_GCB_GCMPB_CMDEFTGT_MEM 1
54#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2 59#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2
55#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3 60#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3
56#define GCMP_GCB_CCMC_OFS 0x0010 /* Global CM Control */ 61#define GCMP_GCB_CCMC_OFS 0x0010 /* Global CM Control */
57#define GCMP_GCB_GCSRAP_OFS 0x0020 /* Global CSR Access Privilege */ 62#define GCMP_GCB_GCSRAP_OFS 0x0020 /* Global CSR Access Privilege */
58#define GCMP_GCB_GCSRAP_CMACCESS_SHF 0 63#define GCMP_GCB_GCSRAP_CMACCESS_SHF 0
@@ -115,5 +120,6 @@
115#define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */ 120#define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */
116 121
117extern int __init gcmp_probe(unsigned long, unsigned long); 122extern int __init gcmp_probe(unsigned long, unsigned long);
118 123extern int __init gcmp_niocu(void);
124extern void __init gcmp_setregion(int, unsigned long, unsigned long, int);
119#endif /* _ASM_GCMPREGS_H */ 125#endif /* _ASM_GCMPREGS_H */
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
index a8f57341f123..9b9436a4d816 100644
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -12,7 +12,6 @@
12#define _ASM_GICREGS_H 12#define _ASM_GICREGS_H
13 13
14#undef GICISBYTELITTLEENDIAN 14#undef GICISBYTELITTLEENDIAN
15#define GICISWORDLITTLEENDIAN
16 15
17/* Constants */ 16/* Constants */
18#define GIC_POL_POS 1 17#define GIC_POL_POS 1
@@ -20,11 +19,7 @@
20#define GIC_TRIG_EDGE 1 19#define GIC_TRIG_EDGE 1
21#define GIC_TRIG_LEVEL 0 20#define GIC_TRIG_LEVEL 0
22 21
23#ifdef CONFIG_SMP
24#define GIC_NUM_INTRS (24 + NR_CPUS * 2) 22#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
25#else
26#define GIC_NUM_INTRS 32
27#endif
28 23
29#define MSK(n) ((1 << (n)) - 1) 24#define MSK(n) ((1 << (n)) - 1)
30#define REG32(addr) (*(volatile unsigned int *) (addr)) 25#define REG32(addr) (*(volatile unsigned int *) (addr))
@@ -70,13 +65,13 @@
70#define USM_VISIBLE_SECTION_SIZE 0x10000 65#define USM_VISIBLE_SECTION_SIZE 0x10000
71 66
72/* Register Map for Shared Section */ 67/* Register Map for Shared Section */
73#if defined(CONFIG_CPU_LITTLE_ENDIAN) || defined(GICISWORDLITTLEENDIAN)
74 68
75#define GIC_SH_CONFIG_OFS 0x0000 69#define GIC_SH_CONFIG_OFS 0x0000
76 70
77/* Shared Global Counter */ 71/* Shared Global Counter */
78#define GIC_SH_COUNTER_31_00_OFS 0x0010 72#define GIC_SH_COUNTER_31_00_OFS 0x0010
79#define GIC_SH_COUNTER_63_32_OFS 0x0014 73#define GIC_SH_COUNTER_63_32_OFS 0x0014
74#define GIC_SH_REVISIONID_OFS 0x0020
80 75
81/* Interrupt Polarity */ 76/* Interrupt Polarity */
82#define GIC_SH_POL_31_0_OFS 0x0100 77#define GIC_SH_POL_31_0_OFS 0x0100
@@ -164,24 +159,31 @@
164 (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4)) 159 (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
165#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32)) 160#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
166 161
162/* Convert an interrupt number to a byte offset/bit for multi-word registers */
163#define GIC_INTR_OFS(intr) (((intr) / 32)*4)
164#define GIC_INTR_BIT(intr) ((intr) % 32)
165
167/* Polarity : Reset Value is always 0 */ 166/* Polarity : Reset Value is always 0 */
168#define GIC_SH_SET_POLARITY_OFS 0x0100 167#define GIC_SH_SET_POLARITY_OFS 0x0100
169#define GIC_SET_POLARITY(intr, pol) \ 168#define GIC_SET_POLARITY(intr, pol) \
170 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + (((intr) / 32) * 4)), (pol) << ((intr) % 32)) 169 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \
170 GIC_INTR_OFS(intr)), (pol) << GIC_INTR_BIT(intr))
171 171
172/* Triggering : Reset Value is always 0 */ 172/* Triggering : Reset Value is always 0 */
173#define GIC_SH_SET_TRIGGER_OFS 0x0180 173#define GIC_SH_SET_TRIGGER_OFS 0x0180
174#define GIC_SET_TRIGGER(intr, trig) \ 174#define GIC_SET_TRIGGER(intr, trig) \
175 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + (((intr) / 32) * 4)), (trig) << ((intr) % 32)) 175 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \
176 GIC_INTR_OFS(intr)), (trig) << GIC_INTR_BIT(intr))
176 177
177/* Mask manipulation */ 178/* Mask manipulation */
178#define GIC_SH_SMASK_OFS 0x0380 179#define GIC_SH_SMASK_OFS 0x0380
179#define GIC_SET_INTR_MASK(intr, val) \ 180#define GIC_SET_INTR_MASK(intr) \
180 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32))) 181 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + \
181 182 GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
182#define GIC_SH_RMASK_OFS 0x0300 183#define GIC_SH_RMASK_OFS 0x0300
183#define GIC_CLR_INTR_MASK(intr, val) \ 184#define GIC_CLR_INTR_MASK(intr) \
184 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32))) 185 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + \
186 GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
185 187
186/* Register Map for Local Section */ 188/* Register Map for Local Section */
187#define GIC_VPE_CTL_OFS 0x0000 189#define GIC_VPE_CTL_OFS 0x0000
@@ -219,161 +221,6 @@
219#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000 221#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000
220#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004 222#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004
221 223
222#else /* CONFIG_CPU_BIG_ENDIAN */
223
224#define GIC_SH_CONFIG_OFS 0x0000
225
226/* Shared Global Counter */
227#define GIC_SH_COUNTER_31_00_OFS 0x0014
228#define GIC_SH_COUNTER_63_32_OFS 0x0010
229
230/* Interrupt Polarity */
231#define GIC_SH_POL_31_0_OFS 0x0104
232#define GIC_SH_POL_63_32_OFS 0x0100
233#define GIC_SH_POL_95_64_OFS 0x010c
234#define GIC_SH_POL_127_96_OFS 0x0108
235#define GIC_SH_POL_159_128_OFS 0x0114
236#define GIC_SH_POL_191_160_OFS 0x0110
237#define GIC_SH_POL_223_192_OFS 0x011c
238#define GIC_SH_POL_255_224_OFS 0x0118
239
240/* Edge/Level Triggering */
241#define GIC_SH_TRIG_31_0_OFS 0x0184
242#define GIC_SH_TRIG_63_32_OFS 0x0180
243#define GIC_SH_TRIG_95_64_OFS 0x018c
244#define GIC_SH_TRIG_127_96_OFS 0x0188
245#define GIC_SH_TRIG_159_128_OFS 0x0194
246#define GIC_SH_TRIG_191_160_OFS 0x0190
247#define GIC_SH_TRIG_223_192_OFS 0x019c
248#define GIC_SH_TRIG_255_224_OFS 0x0198
249
250/* Dual Edge Triggering */
251#define GIC_SH_DUAL_31_0_OFS 0x0204
252#define GIC_SH_DUAL_63_32_OFS 0x0200
253#define GIC_SH_DUAL_95_64_OFS 0x020c
254#define GIC_SH_DUAL_127_96_OFS 0x0208
255#define GIC_SH_DUAL_159_128_OFS 0x0214
256#define GIC_SH_DUAL_191_160_OFS 0x0210
257#define GIC_SH_DUAL_223_192_OFS 0x021c
258#define GIC_SH_DUAL_255_224_OFS 0x0218
259
260/* Set/Clear corresponding bit in Edge Detect Register */
261#define GIC_SH_WEDGE_OFS 0x0280
262
263/* Reset Mask - Disables Interrupt */
264#define GIC_SH_RMASK_31_0_OFS 0x0304
265#define GIC_SH_RMASK_63_32_OFS 0x0300
266#define GIC_SH_RMASK_95_64_OFS 0x030c
267#define GIC_SH_RMASK_127_96_OFS 0x0308
268#define GIC_SH_RMASK_159_128_OFS 0x0314
269#define GIC_SH_RMASK_191_160_OFS 0x0310
270#define GIC_SH_RMASK_223_192_OFS 0x031c
271#define GIC_SH_RMASK_255_224_OFS 0x0318
272
273/* Set Mask (WO) - Enables Interrupt */
274#define GIC_SH_SMASK_31_0_OFS 0x0384
275#define GIC_SH_SMASK_63_32_OFS 0x0380
276#define GIC_SH_SMASK_95_64_OFS 0x038c
277#define GIC_SH_SMASK_127_96_OFS 0x0388
278#define GIC_SH_SMASK_159_128_OFS 0x0394
279#define GIC_SH_SMASK_191_160_OFS 0x0390
280#define GIC_SH_SMASK_223_192_OFS 0x039c
281#define GIC_SH_SMASK_255_224_OFS 0x0398
282
283/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
284#define GIC_SH_MASK_31_0_OFS 0x0404
285#define GIC_SH_MASK_63_32_OFS 0x0400
286#define GIC_SH_MASK_95_64_OFS 0x040c
287#define GIC_SH_MASK_127_96_OFS 0x0408
288#define GIC_SH_MASK_159_128_OFS 0x0414
289#define GIC_SH_MASK_191_160_OFS 0x0410
290#define GIC_SH_MASK_223_192_OFS 0x041c
291#define GIC_SH_MASK_255_224_OFS 0x0418
292
293/* Pending Global Interrupts (RO) */
294#define GIC_SH_PEND_31_0_OFS 0x0484
295#define GIC_SH_PEND_63_32_OFS 0x0480
296#define GIC_SH_PEND_95_64_OFS 0x048c
297#define GIC_SH_PEND_127_96_OFS 0x0488
298#define GIC_SH_PEND_159_128_OFS 0x0494
299#define GIC_SH_PEND_191_160_OFS 0x0490
300#define GIC_SH_PEND_223_192_OFS 0x049c
301#define GIC_SH_PEND_255_224_OFS 0x0498
302
303#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
304
305/* Maps Interrupt X to a Pin */
306#define GIC_SH_MAP_TO_PIN(intr) \
307 (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
308
309#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2004
310
311/*
312 * Maps Interrupt X to a VPE. This is more complex than the LE case, as
313 * odd and even registers need to be transposed. It does work - trust me!
314 */
315#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
316 (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + \
317 (((((vpe) / 32) ^ 1) - 1) * 4))
318#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
319
320/* Polarity */
321#define GIC_SH_SET_POLARITY_OFS 0x0100
322#define GIC_SET_POLARITY(intr, pol) \
323 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (pol) << ((intr) % 32))
324
325/* Triggering */
326#define GIC_SH_SET_TRIGGER_OFS 0x0180
327#define GIC_SET_TRIGGER(intr, trig) \
328 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (trig) << ((intr) % 32))
329
330/* Mask manipulation */
331#define GIC_SH_SMASK_OFS 0x0380
332#define GIC_SET_INTR_MASK(intr, val) \
333 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))
334
335#define GIC_SH_RMASK_OFS 0x0300
336#define GIC_CLR_INTR_MASK(intr, val) \
337 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))
338
339/* Register Map for Local Section */
340#define GIC_VPE_CTL_OFS 0x0000
341#define GIC_VPE_PEND_OFS 0x0004
342#define GIC_VPE_MASK_OFS 0x0008
343#define GIC_VPE_RMASK_OFS 0x000c
344#define GIC_VPE_SMASK_OFS 0x0010
345#define GIC_VPE_WD_MAP_OFS 0x0040
346#define GIC_VPE_COMPARE_MAP_OFS 0x0044
347#define GIC_VPE_TIMER_MAP_OFS 0x0048
348#define GIC_VPE_PERFCTR_MAP_OFS 0x0050
349#define GIC_VPE_SWINT0_MAP_OFS 0x0054
350#define GIC_VPE_SWINT1_MAP_OFS 0x0058
351#define GIC_VPE_OTHER_ADDR_OFS 0x0080
352#define GIC_VPE_WD_CONFIG0_OFS 0x0090
353#define GIC_VPE_WD_COUNT0_OFS 0x0094
354#define GIC_VPE_WD_INITIAL0_OFS 0x0098
355#define GIC_VPE_COMPARE_LO_OFS 0x00a4
356#define GIC_VPE_COMPARE_HI_OFS 0x00a0
357
358#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100
359#define GIC_VPE_EIC_SS(intr) \
360 (GIC_EIC_SHADOW_SET_BASE + (4 * intr))
361
362#define GIC_VPE_EIC_VEC_BASE 0x0800
363#define GIC_VPE_EIC_VEC(intr) \
364 (GIC_VPE_EIC_VEC_BASE + (4 * intr))
365
366#define GIC_VPE_TENABLE_NMI_OFS 0x1000
367#define GIC_VPE_TENABLE_YQ_OFS 0x1004
368#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080
369#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084
370
371/* User Mode Visible Section Register Map */
372#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0004
373#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0000
374
375#endif /* !LE */
376
377/* Masks */ 224/* Masks */
378#define GIC_SH_CONFIG_COUNTSTOP_SHF 28 225#define GIC_SH_CONFIG_COUNTSTOP_SHF 28
379#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF) 226#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
@@ -473,12 +320,13 @@ struct gic_intrmask_regs {
473 * in building ipi_map. 320 * in building ipi_map.
474 */ 321 */
475struct gic_intr_map { 322struct gic_intr_map {
476 unsigned int intrnum; /* Ext Intr Num */
477 unsigned int cpunum; /* Directed to this CPU */ 323 unsigned int cpunum; /* Directed to this CPU */
478 unsigned int pin; /* Directed to this Pin */ 324 unsigned int pin; /* Directed to this Pin */
479 unsigned int polarity; /* Polarity : +/- */ 325 unsigned int polarity; /* Polarity : +/- */
480 unsigned int trigtype; /* Trigger : Edge/Levl */ 326 unsigned int trigtype; /* Trigger : Edge/Levl */
481 unsigned int ipiflag; /* Is used for IPI ? */ 327 unsigned int flags; /* Misc flags */
328#define GIC_FLAG_IPI 0x01
329#define GIC_FLAG_TRANSPARENT 0x02
482}; 330};
483 331
484extern void gic_init(unsigned long gic_base_addr, 332extern void gic_init(unsigned long gic_base_addr,
diff --git a/arch/mips/include/asm/mach-ar7/ar7.h b/arch/mips/include/asm/mach-ar7/ar7.h
index de71694614de..21cbbc706448 100644
--- a/arch/mips/include/asm/mach-ar7/ar7.h
+++ b/arch/mips/include/asm/mach-ar7/ar7.h
@@ -78,6 +78,9 @@
78#define AR7_REF_CLOCK 25000000 78#define AR7_REF_CLOCK 25000000
79#define AR7_XTAL_CLOCK 24000000 79#define AR7_XTAL_CLOCK 24000000
80 80
81/* DCL */
82#define AR7_WDT_HW_ENA 0x10
83
81struct plat_cpmac_data { 84struct plat_cpmac_data {
82 int reset_bit; 85 int reset_bit;
83 int power_bit; 86 int power_bit;
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
index feea00148b5d..91595fa89034 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
@@ -104,6 +104,8 @@ static inline int au1100_gpio2_to_irq(int gpio)
104 104
105 if ((gpio >= 8) && (gpio <= 15)) 105 if ((gpio >= 8) && (gpio <= 15))
106 return MAKE_IRQ(0, 29); /* shared GPIO208_215 */ 106 return MAKE_IRQ(0, 29); /* shared GPIO208_215 */
107
108 return -ENXIO;
107} 109}
108 110
109#ifdef CONFIG_SOC_AU1100 111#ifdef CONFIG_SOC_AU1100
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h
deleted file mode 100644
index bf348f573bbc..000000000000
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef BCM63XX_DEV_UART_H_
2#define BCM63XX_DEV_UART_H_
3
4int bcm63xx_uart_register(void);
5
6#endif /* BCM63XX_DEV_UART_H_ */
diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h
index f6837422fe65..09a59bcc1b07 100644
--- a/arch/mips/include/asm/mach-ip27/topology.h
+++ b/arch/mips/include/asm/mach-ip27/topology.h
@@ -44,8 +44,8 @@ extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
44 .busy_factor = 32, \ 44 .busy_factor = 32, \
45 .imbalance_pct = 125, \ 45 .imbalance_pct = 125, \
46 .cache_nice_tries = 1, \ 46 .cache_nice_tries = 1, \
47 .flags = SD_LOAD_BALANCE \ 47 .flags = SD_LOAD_BALANCE | \
48 | SD_BALANCE_EXEC \ 48 SD_BALANCE_EXEC, \
49 .last_balance = jiffies, \ 49 .last_balance = jiffies, \
50 .balance_interval = 1, \ 50 .balance_interval = 1, \
51 .nr_balance_failed = 0, \ 51 .nr_balance_failed = 0, \
diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
index ce5b6e270e3f..9947e57c91de 100644
--- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
@@ -29,7 +29,7 @@
29#define cpu_has_cache_cdex_p 0 29#define cpu_has_cache_cdex_p 0
30#define cpu_has_cache_cdex_s 0 30#define cpu_has_cache_cdex_s 0
31#define cpu_has_counter 1 31#define cpu_has_counter 1
32#define cpu_has_dc_aliases 1 32#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000)
33#define cpu_has_divec 0 33#define cpu_has_divec 0
34#define cpu_has_dsp 0 34#define cpu_has_dsp 0
35#define cpu_has_ejtag 0 35#define cpu_has_ejtag 0
@@ -54,6 +54,5 @@
54#define cpu_has_vce 0 54#define cpu_has_vce 0
55#define cpu_has_vtag_icache 0 55#define cpu_has_vtag_icache 0
56#define cpu_has_watch 1 56#define cpu_has_watch 1
57#define cpu_icache_snoops_remote_store 1
58 57
59#endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */ 58#endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index d9743536a621..6083db586500 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -16,6 +16,7 @@
16#include <linux/smp.h> 16#include <linux/smp.h>
17#include <linux/slab.h> 17#include <linux/slab.h>
18#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
19#include <asm/hazards.h>
19#include <asm/tlbflush.h> 20#include <asm/tlbflush.h>
20#ifdef CONFIG_MIPS_MT_SMTC 21#ifdef CONFIG_MIPS_MT_SMTC
21#include <asm/mipsmtregs.h> 22#include <asm/mipsmtregs.h>
@@ -36,11 +37,13 @@ extern unsigned long pgd_current[];
36#ifdef CONFIG_32BIT 37#ifdef CONFIG_32BIT
37#define TLBMISS_HANDLER_SETUP() \ 38#define TLBMISS_HANDLER_SETUP() \
38 write_c0_context((unsigned long) smp_processor_id() << 25); \ 39 write_c0_context((unsigned long) smp_processor_id() << 25); \
40 back_to_back_c0_hazard(); \
39 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 41 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
40#endif 42#endif
41#ifdef CONFIG_64BIT 43#ifdef CONFIG_64BIT
42#define TLBMISS_HANDLER_SETUP() \ 44#define TLBMISS_HANDLER_SETUP() \
43 write_c0_context((unsigned long) smp_processor_id() << 26); \ 45 write_c0_context((unsigned long) smp_processor_id() << 26); \
46 back_to_back_c0_hazard(); \
44 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 47 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
45#endif 48#endif
46 49
@@ -165,12 +168,12 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
165 * having ASID_MASK smaller than the hardware maximum, 168 * having ASID_MASK smaller than the hardware maximum,
166 * make sure no "soft" bits become "hard"... 169 * make sure no "soft" bits become "hard"...
167 */ 170 */
168 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) 171 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
169 | (cpu_context(cpu, next) & ASID_MASK)); 172 cpu_asid(cpu, next));
170 ehb(); /* Make sure it propagates to TCStatus */ 173 ehb(); /* Make sure it propagates to TCStatus */
171 evpe(mtflags); 174 evpe(mtflags);
172#else 175#else
173 write_c0_entryhi(cpu_context(cpu, next)); 176 write_c0_entryhi(cpu_asid(cpu, next));
174#endif /* CONFIG_MIPS_MT_SMTC */ 177#endif /* CONFIG_MIPS_MT_SMTC */
175 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 178 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
176 179
@@ -226,11 +229,11 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next)
226 } 229 }
227 /* See comments for similar code above */ 230 /* See comments for similar code above */
228 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | 231 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
229 (cpu_context(cpu, next) & ASID_MASK)); 232 cpu_asid(cpu, next));
230 ehb(); /* Make sure it propagates to TCStatus */ 233 ehb(); /* Make sure it propagates to TCStatus */
231 evpe(mtflags); 234 evpe(mtflags);
232#else 235#else
233 write_c0_entryhi(cpu_context(cpu, next)); 236 write_c0_entryhi(cpu_asid(cpu, next));
234#endif /* CONFIG_MIPS_MT_SMTC */ 237#endif /* CONFIG_MIPS_MT_SMTC */
235 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 238 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
236 239
diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h
index e600cedda976..50511aac04e9 100644
--- a/arch/mips/include/asm/setup.h
+++ b/arch/mips/include/asm/setup.h
@@ -1,7 +1,7 @@
1#ifndef _MIPS_SETUP_H 1#ifndef _MIPS_SETUP_H
2#define _MIPS_SETUP_H 2#define _MIPS_SETUP_H
3 3
4#define COMMAND_LINE_SIZE 256 4#define COMMAND_LINE_SIZE 4096
5 5
6#ifdef __KERNEL__ 6#ifdef __KERNEL__
7extern void setup_early_printk(void); 7extern void setup_early_printk(void);
diff --git a/arch/mips/include/asm/smtc_ipi.h b/arch/mips/include/asm/smtc_ipi.h
index 8ce517574340..15278dbd7e79 100644
--- a/arch/mips/include/asm/smtc_ipi.h
+++ b/arch/mips/include/asm/smtc_ipi.h
@@ -45,6 +45,7 @@ struct smtc_ipi_q {
45 spinlock_t lock; 45 spinlock_t lock;
46 struct smtc_ipi *tail; 46 struct smtc_ipi *tail;
47 int depth; 47 int depth;
48 int resched_flag; /* reschedule already queued */
48}; 49};
49 50
50static inline void smtc_ipi_nq(struct smtc_ipi_q *q, struct smtc_ipi *p) 51static inline void smtc_ipi_nq(struct smtc_ipi_q *q, struct smtc_ipi *p)
diff --git a/arch/mips/include/asm/spram.h b/arch/mips/include/asm/spram.h
new file mode 100644
index 000000000000..0b89006e4907
--- /dev/null
+++ b/arch/mips/include/asm/spram.h
@@ -0,0 +1,10 @@
1#ifndef _MIPS_SPRAM_H
2#define _MIPS_SPRAM_H
3
4#ifdef CONFIG_CPU_MIPSR2
5extern __init void spram_config(void);
6#else
7static inline void spram_config(void) { };
8#endif /* CONFIG_CPU_MIPSR2 */
9
10#endif /* _MIPS_SPRAM_H */
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 01cc1630b66c..845da2107ed1 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -86,14 +86,7 @@ register struct thread_info *__current_thread_info __asm__("$28");
86#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR 86#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
87 87
88#ifdef CONFIG_DEBUG_STACK_USAGE 88#ifdef CONFIG_DEBUG_STACK_USAGE
89#define alloc_thread_info(tsk) \ 89#define alloc_thread_info(tsk) kzalloc(THREAD_SIZE, GFP_KERNEL)
90({ \
91 struct thread_info *ret; \
92 \
93 ret = kzalloc(THREAD_SIZE, GFP_KERNEL); \
94 \
95 ret; \
96})
97#else 90#else
98#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL) 91#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL)
99#endif 92#endif
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index 7fd170d007e7..7bd32d04c2cc 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -134,7 +134,7 @@ static irqreturn_t r4030_timer_interrupt(int irq, void *dev_id)
134 134
135static struct irqaction r4030_timer_irqaction = { 135static struct irqaction r4030_timer_irqaction = {
136 .handler = r4030_timer_interrupt, 136 .handler = r4030_timer_interrupt,
137 .flags = IRQF_DISABLED, 137 .flags = IRQF_DISABLED | IRQF_TIMER,
138 .name = "R4030 timer", 138 .name = "R4030 timer",
139}; 139};
140 140
diff --git a/arch/mips/kernel/cevt-bcm1480.c b/arch/mips/kernel/cevt-bcm1480.c
index e02f79b1eb51..bfea327c636c 100644
--- a/arch/mips/kernel/cevt-bcm1480.c
+++ b/arch/mips/kernel/cevt-bcm1480.c
@@ -144,7 +144,7 @@ void __cpuinit sb1480_clockevent_init(void)
144 bcm1480_unmask_irq(cpu, irq); 144 bcm1480_unmask_irq(cpu, irq);
145 145
146 action->handler = sibyte_counter_handler; 146 action->handler = sibyte_counter_handler;
147 action->flags = IRQF_DISABLED | IRQF_PERCPU; 147 action->flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER;
148 action->name = name; 148 action->name = name;
149 action->dev_id = cd; 149 action->dev_id = cd;
150 150
diff --git a/arch/mips/kernel/cevt-ds1287.c b/arch/mips/kernel/cevt-ds1287.c
index 6996da4d74a2..00a4da277cbb 100644
--- a/arch/mips/kernel/cevt-ds1287.c
+++ b/arch/mips/kernel/cevt-ds1287.c
@@ -107,7 +107,7 @@ static irqreturn_t ds1287_interrupt(int irq, void *dev_id)
107 107
108static struct irqaction ds1287_irqaction = { 108static struct irqaction ds1287_irqaction = {
109 .handler = ds1287_interrupt, 109 .handler = ds1287_interrupt,
110 .flags = IRQF_DISABLED | IRQF_PERCPU, 110 .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
111 .name = "ds1287", 111 .name = "ds1287",
112}; 112};
113 113
diff --git a/arch/mips/kernel/cevt-gt641xx.c b/arch/mips/kernel/cevt-gt641xx.c
index 92351e00ae0e..f5d265eb6eae 100644
--- a/arch/mips/kernel/cevt-gt641xx.c
+++ b/arch/mips/kernel/cevt-gt641xx.c
@@ -113,7 +113,7 @@ static irqreturn_t gt641xx_timer0_interrupt(int irq, void *dev_id)
113 113
114static struct irqaction gt641xx_timer0_irqaction = { 114static struct irqaction gt641xx_timer0_irqaction = {
115 .handler = gt641xx_timer0_interrupt, 115 .handler = gt641xx_timer0_interrupt,
116 .flags = IRQF_DISABLED | IRQF_PERCPU, 116 .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
117 .name = "gt641xx_timer0", 117 .name = "gt641xx_timer0",
118}; 118};
119 119
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 2652362ce047..b469ad05d520 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -83,7 +83,7 @@ out:
83 83
84struct irqaction c0_compare_irqaction = { 84struct irqaction c0_compare_irqaction = {
85 .handler = c0_compare_interrupt, 85 .handler = c0_compare_interrupt,
86 .flags = IRQF_DISABLED | IRQF_PERCPU, 86 .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
87 .name = "timer", 87 .name = "timer",
88}; 88};
89 89
diff --git a/arch/mips/kernel/cevt-sb1250.c b/arch/mips/kernel/cevt-sb1250.c
index ac5903d1b20e..da78eeaea6e8 100644
--- a/arch/mips/kernel/cevt-sb1250.c
+++ b/arch/mips/kernel/cevt-sb1250.c
@@ -143,7 +143,7 @@ void __cpuinit sb1250_clockevent_init(void)
143 sb1250_unmask_irq(cpu, irq); 143 sb1250_unmask_irq(cpu, irq);
144 144
145 action->handler = sibyte_counter_handler; 145 action->handler = sibyte_counter_handler;
146 action->flags = IRQF_DISABLED | IRQF_PERCPU; 146 action->flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER;
147 action->name = name; 147 action->name = name;
148 action->dev_id = cd; 148 action->dev_id = cd;
149 149
diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c
index 0037f21baf0d..218ee6bda935 100644
--- a/arch/mips/kernel/cevt-txx9.c
+++ b/arch/mips/kernel/cevt-txx9.c
@@ -146,7 +146,7 @@ static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id)
146 146
147static struct irqaction txx9tmr_irq = { 147static struct irqaction txx9tmr_irq = {
148 .handler = txx9tmr_interrupt, 148 .handler = txx9tmr_interrupt,
149 .flags = IRQF_DISABLED | IRQF_PERCPU, 149 .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
150 .name = "txx9tmr", 150 .name = "txx9tmr",
151 .dev_id = &txx9_clock_event_device, 151 .dev_id = &txx9_clock_event_device,
152}; 152};
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index f709657e4dcd..7a51866068a4 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -23,7 +23,7 @@
23#include <asm/mipsregs.h> 23#include <asm/mipsregs.h>
24#include <asm/system.h> 24#include <asm/system.h>
25#include <asm/watch.h> 25#include <asm/watch.h>
26 26#include <asm/spram.h>
27/* 27/*
28 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, 28 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
29 * the implementation of the "wait" feature differs between CPU families. This 29 * the implementation of the "wait" feature differs between CPU families. This
@@ -711,12 +711,6 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c)
711 mips_probe_watch_registers(c); 711 mips_probe_watch_registers(c);
712} 712}
713 713
714#ifdef CONFIG_CPU_MIPSR2
715extern void spram_config(void);
716#else
717static inline void spram_config(void) {}
718#endif
719
720static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 714static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
721{ 715{
722 decode_configs(c); 716 decode_configs(c);
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index 531ce7b16124..ea695d9605e9 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -191,6 +191,7 @@ NESTED(kernel_entry, 16, sp) # kernel entry point
191 /* Set the SP after an empty pt_regs. */ 191 /* Set the SP after an empty pt_regs. */
192 PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE 192 PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE
193 PTR_ADDU sp, $28 193 PTR_ADDU sp, $28
194 back_to_back_c0_hazard
194 set_saved_sp sp, t0, t1 195 set_saved_sp sp, t0, t1
195 PTR_SUBU sp, 4 * SZREG # init stack pointer 196 PTR_SUBU sp, 4 * SZREG # init stack pointer
196 197
diff --git a/arch/mips/kernel/i8253.c b/arch/mips/kernel/i8253.c
index f7d8d5d0ddbf..ed5c441615e4 100644
--- a/arch/mips/kernel/i8253.c
+++ b/arch/mips/kernel/i8253.c
@@ -98,7 +98,7 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id)
98 98
99static struct irqaction irq0 = { 99static struct irqaction irq0 = {
100 .handler = timer_interrupt, 100 .handler = timer_interrupt,
101 .flags = IRQF_DISABLED | IRQF_NOBALANCING, 101 .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER,
102 .name = "timer" 102 .name = "timer"
103}; 103};
104 104
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c
index d2072cd38592..b181f2f0ea8e 100644
--- a/arch/mips/kernel/irq-gic.c
+++ b/arch/mips/kernel/irq-gic.c
@@ -14,38 +14,23 @@
14 14
15 15
16static unsigned long _gic_base; 16static unsigned long _gic_base;
17static unsigned int _irqbase, _mapsize, numvpes, numintrs; 17static unsigned int _irqbase;
18static struct gic_intr_map *_intrmap; 18static unsigned int gic_irq_flags[GIC_NUM_INTRS];
19#define GIC_IRQ_FLAG_EDGE 0x0001
19 20
20static struct gic_pcpu_mask pcpu_masks[NR_CPUS]; 21struct gic_pcpu_mask pcpu_masks[NR_CPUS];
21static struct gic_pending_regs pending_regs[NR_CPUS]; 22static struct gic_pending_regs pending_regs[NR_CPUS];
22static struct gic_intrmask_regs intrmask_regs[NR_CPUS]; 23static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
23 24
24#define gic_wedgeb2bok 0 /*
25 * Can GIC handle b2b writes to wedge register?
26 */
27#if gic_wedgeb2bok == 0
28static DEFINE_SPINLOCK(gic_wedgeb2b_lock);
29#endif
30
31void gic_send_ipi(unsigned int intr) 25void gic_send_ipi(unsigned int intr)
32{ 26{
33#if gic_wedgeb2bok == 0
34 unsigned long flags;
35#endif
36 pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__, 27 pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__,
37 read_c0_status()); 28 read_c0_status());
38 if (!gic_wedgeb2bok)
39 spin_lock_irqsave(&gic_wedgeb2b_lock, flags);
40 GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr); 29 GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
41 if (!gic_wedgeb2bok) {
42 (void) GIC_REG(SHARED, GIC_SH_CONFIG);
43 spin_unlock_irqrestore(&gic_wedgeb2b_lock, flags);
44 }
45} 30}
46 31
47/* This is Malta specific and needs to be exported */ 32/* This is Malta specific and needs to be exported */
48static void vpe_local_setup(unsigned int numvpes) 33static void __init vpe_local_setup(unsigned int numvpes)
49{ 34{
50 int i; 35 int i;
51 unsigned long timer_interrupt = 5, perf_interrupt = 5; 36 unsigned long timer_interrupt = 5, perf_interrupt = 5;
@@ -105,44 +90,34 @@ unsigned int gic_get_int(void)
105 90
106static unsigned int gic_irq_startup(unsigned int irq) 91static unsigned int gic_irq_startup(unsigned int irq)
107{ 92{
108 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
109 irq -= _irqbase; 93 irq -= _irqbase;
110 GIC_SET_INTR_MASK(irq, 1); 94 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
95 GIC_SET_INTR_MASK(irq);
111 return 0; 96 return 0;
112} 97}
113 98
114static void gic_irq_ack(unsigned int irq) 99static void gic_irq_ack(unsigned int irq)
115{ 100{
116#if gic_wedgeb2bok == 0
117 unsigned long flags;
118#endif
119 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
120 irq -= _irqbase; 101 irq -= _irqbase;
121 GIC_CLR_INTR_MASK(irq, 1); 102 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
103 GIC_CLR_INTR_MASK(irq);
122 104
123 if (_intrmap[irq].trigtype == GIC_TRIG_EDGE) { 105 if (gic_irq_flags[irq] & GIC_IRQ_FLAG_EDGE)
124 if (!gic_wedgeb2bok)
125 spin_lock_irqsave(&gic_wedgeb2b_lock, flags);
126 GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq); 106 GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
127 if (!gic_wedgeb2bok) {
128 (void) GIC_REG(SHARED, GIC_SH_CONFIG);
129 spin_unlock_irqrestore(&gic_wedgeb2b_lock, flags);
130 }
131 }
132} 107}
133 108
134static void gic_mask_irq(unsigned int irq) 109static void gic_mask_irq(unsigned int irq)
135{ 110{
136 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
137 irq -= _irqbase; 111 irq -= _irqbase;
138 GIC_CLR_INTR_MASK(irq, 1); 112 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
113 GIC_CLR_INTR_MASK(irq);
139} 114}
140 115
141static void gic_unmask_irq(unsigned int irq) 116static void gic_unmask_irq(unsigned int irq)
142{ 117{
143 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
144 irq -= _irqbase; 118 irq -= _irqbase;
145 GIC_SET_INTR_MASK(irq, 1); 119 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
120 GIC_SET_INTR_MASK(irq);
146} 121}
147 122
148#ifdef CONFIG_SMP 123#ifdef CONFIG_SMP
@@ -155,9 +130,8 @@ static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
155 unsigned long flags; 130 unsigned long flags;
156 int i; 131 int i;
157 132
158 pr_debug(KERN_DEBUG "%s called\n", __func__);
159 irq -= _irqbase; 133 irq -= _irqbase;
160 134 pr_debug(KERN_DEBUG "%s(%d) called\n", __func__, irq);
161 cpumask_and(&tmp, cpumask, cpu_online_mask); 135 cpumask_and(&tmp, cpumask, cpu_online_mask);
162 if (cpus_empty(tmp)) 136 if (cpus_empty(tmp))
163 return -1; 137 return -1;
@@ -168,13 +142,6 @@ static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
168 /* Re-route this IRQ */ 142 /* Re-route this IRQ */
169 GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp)); 143 GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
170 144
171 /*
172 * FIXME: assumption that _intrmap is ordered and has no holes
173 */
174
175 /* Update the intr_map */
176 _intrmap[irq].cpunum = first_cpu(tmp);
177
178 /* Update the pcpu_masks */ 145 /* Update the pcpu_masks */
179 for (i = 0; i < NR_CPUS; i++) 146 for (i = 0; i < NR_CPUS; i++)
180 clear_bit(irq, pcpu_masks[i].pcpu_mask); 147 clear_bit(irq, pcpu_masks[i].pcpu_mask);
@@ -201,8 +168,9 @@ static struct irq_chip gic_irq_controller = {
201#endif 168#endif
202}; 169};
203 170
204static void __init setup_intr(unsigned int intr, unsigned int cpu, 171static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
205 unsigned int pin, unsigned int polarity, unsigned int trigtype) 172 unsigned int pin, unsigned int polarity, unsigned int trigtype,
173 unsigned int flags)
206{ 174{
207 /* Setup Intr to Pin mapping */ 175 /* Setup Intr to Pin mapping */
208 if (pin & GIC_MAP_TO_NMI_MSK) { 176 if (pin & GIC_MAP_TO_NMI_MSK) {
@@ -227,38 +195,43 @@ static void __init setup_intr(unsigned int intr, unsigned int cpu,
227 GIC_SET_TRIGGER(intr, trigtype); 195 GIC_SET_TRIGGER(intr, trigtype);
228 196
229 /* Init Intr Masks */ 197 /* Init Intr Masks */
230 GIC_SET_INTR_MASK(intr, 0); 198 GIC_CLR_INTR_MASK(intr);
199 /* Initialise per-cpu Interrupt software masks */
200 if (flags & GIC_FLAG_IPI)
201 set_bit(intr, pcpu_masks[cpu].pcpu_mask);
202 if (flags & GIC_FLAG_TRANSPARENT)
203 GIC_SET_INTR_MASK(intr);
204 if (trigtype == GIC_TRIG_EDGE)
205 gic_irq_flags[intr] |= GIC_IRQ_FLAG_EDGE;
231} 206}
232 207
233static void __init gic_basic_init(void) 208static void __init gic_basic_init(int numintrs, int numvpes,
209 struct gic_intr_map *intrmap, int mapsize)
234{ 210{
235 unsigned int i, cpu; 211 unsigned int i, cpu;
236 212
237 /* Setup defaults */ 213 /* Setup defaults */
238 for (i = 0; i < GIC_NUM_INTRS; i++) { 214 for (i = 0; i < numintrs; i++) {
239 GIC_SET_POLARITY(i, GIC_POL_POS); 215 GIC_SET_POLARITY(i, GIC_POL_POS);
240 GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL); 216 GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
241 GIC_SET_INTR_MASK(i, 0); 217 GIC_CLR_INTR_MASK(i);
218 if (i < GIC_NUM_INTRS)
219 gic_irq_flags[i] = 0;
242 } 220 }
243 221
244 /* Setup specifics */ 222 /* Setup specifics */
245 for (i = 0; i < _mapsize; i++) { 223 for (i = 0; i < mapsize; i++) {
246 cpu = _intrmap[i].cpunum; 224 cpu = intrmap[i].cpunum;
247 if (cpu == X) 225 if (cpu == X)
248 continue; 226 continue;
249 227 if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
250 if (cpu == 0 && i != 0 && _intrmap[i].intrnum == 0 &&
251 _intrmap[i].ipiflag == 0)
252 continue; 228 continue;
253 229 gic_setup_intr(i,
254 setup_intr(_intrmap[i].intrnum, 230 intrmap[i].cpunum,
255 _intrmap[i].cpunum, 231 intrmap[i].pin,
256 _intrmap[i].pin, 232 intrmap[i].polarity,
257 _intrmap[i].polarity, 233 intrmap[i].trigtype,
258 _intrmap[i].trigtype); 234 intrmap[i].flags);
259 /* Initialise per-cpu Interrupt software masks */
260 if (_intrmap[i].ipiflag)
261 set_bit(_intrmap[i].intrnum, pcpu_masks[cpu].pcpu_mask);
262 } 235 }
263 236
264 vpe_local_setup(numvpes); 237 vpe_local_setup(numvpes);
@@ -273,12 +246,11 @@ void __init gic_init(unsigned long gic_base_addr,
273 unsigned int irqbase) 246 unsigned int irqbase)
274{ 247{
275 unsigned int gicconfig; 248 unsigned int gicconfig;
249 int numvpes, numintrs;
276 250
277 _gic_base = (unsigned long) ioremap_nocache(gic_base_addr, 251 _gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
278 gic_addrspace_size); 252 gic_addrspace_size);
279 _irqbase = irqbase; 253 _irqbase = irqbase;
280 _intrmap = intr_map;
281 _mapsize = intr_map_size;
282 254
283 GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig); 255 GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
284 numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >> 256 numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
@@ -290,5 +262,5 @@ void __init gic_init(unsigned long gic_base_addr,
290 262
291 pr_debug("%s called\n", __func__); 263 pr_debug("%s called\n", __func__);
292 264
293 gic_basic_init(); 265 gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);
294} 266}
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 6242bc68add7..b77fefaff9da 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -428,3 +428,9 @@ _sys32_clone(nabi_no_regargs struct pt_regs regs)
428 return do_fork(clone_flags, newsp, &regs, 0, 428 return do_fork(clone_flags, newsp, &regs, 0,
429 parent_tidptr, child_tidptr); 429 parent_tidptr, child_tidptr);
430} 430}
431
432asmlinkage long sys32_lookup_dcookie(u32 a0, u32 a1, char __user *buf,
433 size_t len)
434{
435 return sys_lookup_dcookie(merge_64(a0, a1), buf, len);
436}
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 9bbf9775e0bd..14dde4ca932e 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -450,7 +450,7 @@ sys_call_table:
450 PTR sys_io_submit 450 PTR sys_io_submit
451 PTR sys_io_cancel /* 4245 */ 451 PTR sys_io_cancel /* 4245 */
452 PTR sys_exit_group 452 PTR sys_exit_group
453 PTR sys_lookup_dcookie 453 PTR sys32_lookup_dcookie
454 PTR sys_epoll_create 454 PTR sys_epoll_create
455 PTR sys_epoll_ctl 455 PTR sys_epoll_ctl
456 PTR sys_epoll_wait /* 4250 */ 456 PTR sys_epoll_wait /* 4250 */
@@ -505,7 +505,7 @@ sys_call_table:
505 PTR sys_fchmodat 505 PTR sys_fchmodat
506 PTR sys_faccessat /* 4300 */ 506 PTR sys_faccessat /* 4300 */
507 PTR compat_sys_pselect6 507 PTR compat_sys_pselect6
508 PTR sys_ppoll 508 PTR compat_sys_ppoll
509 PTR sys_unshare 509 PTR sys_unshare
510 PTR sys_splice 510 PTR sys_splice
511 PTR sys32_sync_file_range /* 4305 */ 511 PTR sys32_sync_file_range /* 4305 */
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 4d181df44a40..24630fd8ef60 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -75,7 +75,6 @@ unsigned long irq_hwmask[NR_IRQS];
75 75
76asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS]; 76asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
77 77
78
79/* 78/*
80 * Number of InterProcessor Interrupt (IPI) message buffers to allocate 79 * Number of InterProcessor Interrupt (IPI) message buffers to allocate
81 */ 80 */
@@ -388,6 +387,7 @@ void smtc_prepare_cpus(int cpus)
388 IPIQ[i].head = IPIQ[i].tail = NULL; 387 IPIQ[i].head = IPIQ[i].tail = NULL;
389 spin_lock_init(&IPIQ[i].lock); 388 spin_lock_init(&IPIQ[i].lock);
390 IPIQ[i].depth = 0; 389 IPIQ[i].depth = 0;
390 IPIQ[i].resched_flag = 0; /* No reschedules queued initially */
391 } 391 }
392 392
393 /* cpu_data index starts at zero */ 393 /* cpu_data index starts at zero */
@@ -741,11 +741,24 @@ void smtc_forward_irq(unsigned int irq)
741static void smtc_ipi_qdump(void) 741static void smtc_ipi_qdump(void)
742{ 742{
743 int i; 743 int i;
744 struct smtc_ipi *temp;
744 745
745 for (i = 0; i < NR_CPUS ;i++) { 746 for (i = 0; i < NR_CPUS ;i++) {
746 printk("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n", 747 pr_info("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n",
747 i, (unsigned)IPIQ[i].head, (unsigned)IPIQ[i].tail, 748 i, (unsigned)IPIQ[i].head, (unsigned)IPIQ[i].tail,
748 IPIQ[i].depth); 749 IPIQ[i].depth);
750 temp = IPIQ[i].head;
751
752 while (temp != IPIQ[i].tail) {
753 pr_debug("%d %d %d: ", temp->type, temp->dest,
754 (int)temp->arg);
755#ifdef SMTC_IPI_DEBUG
756 pr_debug("%u %lu\n", temp->sender, temp->stamp);
757#else
758 pr_debug("\n");
759#endif
760 temp = temp->flink;
761 }
749 } 762 }
750} 763}
751 764
@@ -784,11 +797,16 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
784 int mtflags; 797 int mtflags;
785 unsigned long tcrestart; 798 unsigned long tcrestart;
786 extern void r4k_wait_irqoff(void), __pastwait(void); 799 extern void r4k_wait_irqoff(void), __pastwait(void);
800 int set_resched_flag = (type == LINUX_SMP_IPI &&
801 action == SMP_RESCHEDULE_YOURSELF);
787 802
788 if (cpu == smp_processor_id()) { 803 if (cpu == smp_processor_id()) {
789 printk("Cannot Send IPI to self!\n"); 804 printk("Cannot Send IPI to self!\n");
790 return; 805 return;
791 } 806 }
807 if (set_resched_flag && IPIQ[cpu].resched_flag != 0)
808 return; /* There is a reschedule queued already */
809
792 /* Set up a descriptor, to be delivered either promptly or queued */ 810 /* Set up a descriptor, to be delivered either promptly or queued */
793 pipi = smtc_ipi_dq(&freeIPIq); 811 pipi = smtc_ipi_dq(&freeIPIq);
794 if (pipi == NULL) { 812 if (pipi == NULL) {
@@ -801,6 +819,7 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
801 pipi->dest = cpu; 819 pipi->dest = cpu;
802 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { 820 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
803 /* If not on same VPE, enqueue and send cross-VPE interrupt */ 821 /* If not on same VPE, enqueue and send cross-VPE interrupt */
822 IPIQ[cpu].resched_flag |= set_resched_flag;
804 smtc_ipi_nq(&IPIQ[cpu], pipi); 823 smtc_ipi_nq(&IPIQ[cpu], pipi);
805 LOCK_CORE_PRA(); 824 LOCK_CORE_PRA();
806 settc(cpu_data[cpu].tc_id); 825 settc(cpu_data[cpu].tc_id);
@@ -847,6 +866,7 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
847 */ 866 */
848 write_tc_c0_tchalt(0); 867 write_tc_c0_tchalt(0);
849 UNLOCK_CORE_PRA(); 868 UNLOCK_CORE_PRA();
869 IPIQ[cpu].resched_flag |= set_resched_flag;
850 smtc_ipi_nq(&IPIQ[cpu], pipi); 870 smtc_ipi_nq(&IPIQ[cpu], pipi);
851 } else { 871 } else {
852postdirect: 872postdirect:
@@ -996,12 +1016,15 @@ void deferred_smtc_ipi(void)
996 * already enabled. 1016 * already enabled.
997 */ 1017 */
998 local_irq_save(flags); 1018 local_irq_save(flags);
999
1000 spin_lock(&q->lock); 1019 spin_lock(&q->lock);
1001 pipi = __smtc_ipi_dq(q); 1020 pipi = __smtc_ipi_dq(q);
1002 spin_unlock(&q->lock); 1021 spin_unlock(&q->lock);
1003 if (pipi != NULL) 1022 if (pipi != NULL) {
1023 if (pipi->type == LINUX_SMP_IPI &&
1024 (int)pipi->arg == SMP_RESCHEDULE_YOURSELF)
1025 IPIQ[cpu].resched_flag = 0;
1004 ipi_decode(pipi); 1026 ipi_decode(pipi);
1027 }
1005 /* 1028 /*
1006 * The use of the __raw_local restore isn't 1029 * The use of the __raw_local restore isn't
1007 * as obviously necessary here as in smtc_ipi_replay(), 1030 * as obviously necessary here as in smtc_ipi_replay(),
@@ -1082,6 +1105,9 @@ static irqreturn_t ipi_interrupt(int irq, void *dev_idm)
1082 * with interrupts off 1105 * with interrupts off
1083 */ 1106 */
1084 local_irq_save(flags); 1107 local_irq_save(flags);
1108 if (pipi->type == LINUX_SMP_IPI &&
1109 (int)pipi->arg == SMP_RESCHEDULE_YOURSELF)
1110 IPIQ[cpu].resched_flag = 0;
1085 ipi_decode(pipi); 1111 ipi_decode(pipi);
1086 local_irq_restore(flags); 1112 local_irq_restore(flags);
1087 } 1113 }
diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c
index 6ddb507a87ef..1821d12a6410 100644
--- a/arch/mips/kernel/spram.c
+++ b/arch/mips/kernel/spram.c
@@ -13,7 +13,6 @@
13#include <linux/ptrace.h> 13#include <linux/ptrace.h>
14#include <linux/stddef.h> 14#include <linux/stddef.h>
15 15
16#include <asm/cpu.h>
17#include <asm/fpu.h> 16#include <asm/fpu.h>
18#include <asm/mipsregs.h> 17#include <asm/mipsregs.h>
19#include <asm/system.h> 18#include <asm/system.h>
@@ -198,8 +197,7 @@ static __cpuinit void probe_spram(char *type,
198 offset += 2 * SPRAM_TAG_STRIDE; 197 offset += 2 * SPRAM_TAG_STRIDE;
199 } 198 }
200} 199}
201 200void __cpuinit spram_config(void)
202__cpuinit void spram_config(void)
203{ 201{
204 struct cpuinfo_mips *c = &current_cpu_data; 202 struct cpuinfo_mips *c = &current_cpu_data;
205 unsigned int config0; 203 unsigned int config0;
@@ -208,6 +206,7 @@ __cpuinit void spram_config(void)
208 case CPU_24K: 206 case CPU_24K:
209 case CPU_34K: 207 case CPU_34K:
210 case CPU_74K: 208 case CPU_74K:
209 case CPU_1004K:
211 config0 = read_c0_config(); 210 config0 = read_c0_config();
212 /* FIXME: addresses are Malta specific */ 211 /* FIXME: addresses are Malta specific */
213 if (config0 & (1<<24)) { 212 if (config0 & (1<<24)) {
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index 03092ab2a296..60477529362e 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -1116,8 +1116,6 @@ static int vpe_open(struct inode *inode, struct file *filp)
1116 v->shared_ptr = NULL; 1116 v->shared_ptr = NULL;
1117 v->__start = 0; 1117 v->__start = 0;
1118 1118
1119 unlock_kernel();
1120
1121 return 0; 1119 return 0;
1122} 1120}
1123 1121
diff --git a/arch/mips/loongson/common/irq.c b/arch/mips/loongson/common/irq.c
index f368c735cbd3..b32b4a3e5137 100644
--- a/arch/mips/loongson/common/irq.c
+++ b/arch/mips/loongson/common/irq.c
@@ -55,7 +55,6 @@ void __init arch_init_irq(void)
55 * int-handler is not on bootstrap 55 * int-handler is not on bootstrap
56 */ 56 */
57 clear_c0_status(ST0_IM | ST0_BEV); 57 clear_c0_status(ST0_IM | ST0_BEV);
58 local_irq_disable();
59 58
60 /* setting irq trigger mode */ 59 /* setting irq trigger mode */
61 set_irq_trigger_mode(); 60 set_irq_trigger_mode();
diff --git a/arch/mips/math-emu/dp_simple.c b/arch/mips/math-emu/dp_simple.c
index 1c555e6c6a9f..d9ae1dbabda7 100644
--- a/arch/mips/math-emu/dp_simple.c
+++ b/arch/mips/math-emu/dp_simple.c
@@ -62,8 +62,6 @@ ieee754dp ieee754dp_neg(ieee754dp x)
62 return ieee754dp_nanxcpt(y, "neg"); 62 return ieee754dp_nanxcpt(y, "neg");
63 } 63 }
64 64
65 if (ieee754dp_isnan(x)) /* but not infinity */
66 return ieee754dp_nanxcpt(x, "neg", x);
67 return x; 65 return x;
68} 66}
69 67
@@ -76,15 +74,12 @@ ieee754dp ieee754dp_abs(ieee754dp x)
76 CLEARCX; 74 CLEARCX;
77 FLUSHXDP; 75 FLUSHXDP;
78 76
77 /* Clear sign ALWAYS, irrespective of NaN */
78 DPSIGN(x) = 0;
79
79 if (xc == IEEE754_CLASS_SNAN) { 80 if (xc == IEEE754_CLASS_SNAN) {
80 SETCX(IEEE754_INVALID_OPERATION); 81 return ieee754dp_nanxcpt(ieee754dp_indef(), "abs");
81 return ieee754dp_nanxcpt(ieee754dp_indef(), "neg");
82 } 82 }
83 83
84 if (ieee754dp_isnan(x)) /* but not infinity */
85 return ieee754dp_nanxcpt(x, "abs", x);
86
87 /* quick fix up */
88 DPSIGN(x) = 0;
89 return x; 84 return x;
90} 85}
diff --git a/arch/mips/math-emu/sp_simple.c b/arch/mips/math-emu/sp_simple.c
index 770f0f4677cd..3175477d36f6 100644
--- a/arch/mips/math-emu/sp_simple.c
+++ b/arch/mips/math-emu/sp_simple.c
@@ -62,8 +62,6 @@ ieee754sp ieee754sp_neg(ieee754sp x)
62 return ieee754sp_nanxcpt(y, "neg"); 62 return ieee754sp_nanxcpt(y, "neg");
63 } 63 }
64 64
65 if (ieee754sp_isnan(x)) /* but not infinity */
66 return ieee754sp_nanxcpt(x, "neg", x);
67 return x; 65 return x;
68} 66}
69 67
@@ -76,15 +74,12 @@ ieee754sp ieee754sp_abs(ieee754sp x)
76 CLEARCX; 74 CLEARCX;
77 FLUSHXSP; 75 FLUSHXSP;
78 76
77 /* Clear sign ALWAYS, irrespective of NaN */
78 SPSIGN(x) = 0;
79
79 if (xc == IEEE754_CLASS_SNAN) { 80 if (xc == IEEE754_CLASS_SNAN) {
80 SETCX(IEEE754_INVALID_OPERATION);
81 return ieee754sp_nanxcpt(ieee754sp_indef(), "abs"); 81 return ieee754sp_nanxcpt(ieee754sp_indef(), "abs");
82 } 82 }
83 83
84 if (ieee754sp_isnan(x)) /* but not infinity */
85 return ieee754sp_nanxcpt(x, "abs", x);
86
87 /* quick fix up */
88 SPSIGN(x) = 0;
89 return x; 84 return x;
90} 85}
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 15aa1902a788..8d1f4f363049 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -27,6 +27,7 @@
27#include <linux/swap.h> 27#include <linux/swap.h>
28#include <linux/proc_fs.h> 28#include <linux/proc_fs.h>
29#include <linux/pfn.h> 29#include <linux/pfn.h>
30#include <linux/hardirq.h>
30 31
31#include <asm/asm-offsets.h> 32#include <asm/asm-offsets.h>
32#include <asm/bootinfo.h> 33#include <asm/bootinfo.h>
@@ -132,7 +133,10 @@ void *kmap_coherent(struct page *page, unsigned long addr)
132 inc_preempt_count(); 133 inc_preempt_count();
133 idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1); 134 idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1);
134#ifdef CONFIG_MIPS_MT_SMTC 135#ifdef CONFIG_MIPS_MT_SMTC
135 idx += FIX_N_COLOURS * smp_processor_id(); 136 idx += FIX_N_COLOURS * smp_processor_id() +
137 (in_interrupt() ? (FIX_N_COLOURS * NR_CPUS) : 0);
138#else
139 idx += in_interrupt() ? FIX_N_COLOURS : 0;
136#endif 140#endif
137 vaddr = __fix_to_virt(FIX_CMAP_END - idx); 141 vaddr = __fix_to_virt(FIX_CMAP_END - idx);
138 pte = mk_pte(page, PAGE_KERNEL); 142 pte = mk_pte(page, PAGE_KERNEL);
diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c
index df9e526312a2..469d9b0cee6d 100644
--- a/arch/mips/mti-malta/malta-amon.c
+++ b/arch/mips/mti-malta/malta-amon.c
@@ -70,11 +70,12 @@ void amon_cpu_start(int cpu,
70 launch->sp = sp; 70 launch->sp = sp;
71 launch->a0 = a0; 71 launch->a0 = a0;
72 72
73 /* Make sure target sees parameters before the go bit */ 73 smp_wmb(); /* Target must see parameters before go */
74 smp_mb();
75
76 launch->flags |= LAUNCH_FGO; 74 launch->flags |= LAUNCH_FGO;
75 smp_wmb(); /* Target must see go before we poll */
76
77 while ((launch->flags & LAUNCH_FGONE) == 0) 77 while ((launch->flags & LAUNCH_FGONE) == 0)
78 ; 78 ;
79 smp_rmb(); /* Target will be updating flags soon */
79 pr_debug("launch: cpu%d gone!\n", cpu); 80 pr_debug("launch: cpu%d gone!\n", cpu);
80} 81}
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index 3e0a9b35ba5c..4c3fca18a171 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -87,7 +87,7 @@ static inline int mips_pcibios_iack(void)
87 dummy = BONITO_PCIMAP_CFG; 87 dummy = BONITO_PCIMAP_CFG;
88 iob(); /* sync */ 88 iob(); /* sync */
89 89
90 irq = readl((u32 *)_pcictrl_bonito_pcicfg); 90 irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
91 iob(); /* sync */ 91 iob(); /* sync */
92 irq &= 0xff; 92 irq &= 0xff;
93 BONITO_PCIMAP_CFG = 0; 93 BONITO_PCIMAP_CFG = 0;
@@ -379,38 +379,43 @@ static msc_irqmap_t __initdata msc_eicirqmap[] = {
379 379
380static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); 380static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
381 381
382#if defined(CONFIG_MIPS_MT_SMP)
383/* 382/*
384 * This GIC specific tabular array defines the association between External 383 * This GIC specific tabular array defines the association between External
385 * Interrupts and CPUs/Core Interrupts. The nature of the External 384 * Interrupts and CPUs/Core Interrupts. The nature of the External
386 * Interrupts is also defined here - polarity/trigger. 385 * Interrupts is also defined here - polarity/trigger.
387 */ 386 */
387
388#define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK
388static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { 389static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
389 { GIC_EXT_INTR(0), X, X, X, X, 0 }, 390 { X, X, X, X, 0 },
390 { GIC_EXT_INTR(1), X, X, X, X, 0 }, 391 { X, X, X, X, 0 },
391 { GIC_EXT_INTR(2), X, X, X, X, 0 }, 392 { X, X, X, X, 0 },
392 { GIC_EXT_INTR(3), 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 393 { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
393 { GIC_EXT_INTR(4), 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 394 { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
394 { GIC_EXT_INTR(5), 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 395 { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
395 { GIC_EXT_INTR(6), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 396 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
396 { GIC_EXT_INTR(7), 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 397 { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
397 { GIC_EXT_INTR(8), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 398 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
398 { GIC_EXT_INTR(9), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 399 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
399 { GIC_EXT_INTR(10), X, X, X, X, 0 }, 400 { X, X, X, X, 0 },
400 { GIC_EXT_INTR(11), X, X, X, X, 0 }, 401 { X, X, X, X, 0 },
401 { GIC_EXT_INTR(12), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 402 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
402 { GIC_EXT_INTR(13), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 403 { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
403 { GIC_EXT_INTR(14), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 404 { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
404 { GIC_EXT_INTR(15), X, X, X, X, 0 }, 405 { X, X, X, X, 0 },
405/* This is the end of the general interrupts now we do IPI ones */ 406 /* The remainder of this table is initialised by fill_ipi_map */
406}; 407};
407#endif
408 408
409/* 409/*
410 * GCMP needs to be detected before any SMP initialisation 410 * GCMP needs to be detected before any SMP initialisation
411 */ 411 */
412int __init gcmp_probe(unsigned long addr, unsigned long size) 412int __init gcmp_probe(unsigned long addr, unsigned long size)
413{ 413{
414 if (mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) {
415 gcmp_present = 0;
416 return gcmp_present;
417 }
418
414 if (gcmp_present >= 0) 419 if (gcmp_present >= 0)
415 return gcmp_present; 420 return gcmp_present;
416 421
@@ -419,20 +424,35 @@ int __init gcmp_probe(unsigned long addr, unsigned long size)
419 gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR; 424 gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR;
420 425
421 if (gcmp_present) 426 if (gcmp_present)
422 printk(KERN_DEBUG "GCMP present\n"); 427 pr_debug("GCMP present\n");
423 return gcmp_present; 428 return gcmp_present;
424} 429}
425 430
431/* Return the number of IOCU's present */
432int __init gcmp_niocu(void)
433{
434 return gcmp_present ?
435 (GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> GCMP_GCB_GC_NUMIOCU_SHF :
436 0;
437}
438
439/* Set GCMP region attributes */
440void __init gcmp_setregion(int region, unsigned long base,
441 unsigned long mask, int type)
442{
443 GCMPGCBn(CMxBASE, region) = base;
444 GCMPGCBn(CMxMASK, region) = mask | type;
445}
446
426#if defined(CONFIG_MIPS_MT_SMP) 447#if defined(CONFIG_MIPS_MT_SMP)
427static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin) 448static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin)
428{ 449{
429 int intr = baseintr + cpu; 450 int intr = baseintr + cpu;
430 gic_intr_map[intr].intrnum = GIC_EXT_INTR(intr);
431 gic_intr_map[intr].cpunum = cpu; 451 gic_intr_map[intr].cpunum = cpu;
432 gic_intr_map[intr].pin = cpupin; 452 gic_intr_map[intr].pin = cpupin;
433 gic_intr_map[intr].polarity = GIC_POL_POS; 453 gic_intr_map[intr].polarity = GIC_POL_POS;
434 gic_intr_map[intr].trigtype = GIC_TRIG_EDGE; 454 gic_intr_map[intr].trigtype = GIC_TRIG_EDGE;
435 gic_intr_map[intr].ipiflag = 1; 455 gic_intr_map[intr].flags = GIC_FLAG_IPI;
436 ipi_map[cpu] |= (1 << (cpupin + 2)); 456 ipi_map[cpu] |= (1 << (cpupin + 2));
437} 457}
438 458
@@ -447,6 +467,12 @@ static void __init fill_ipi_map(void)
447} 467}
448#endif 468#endif
449 469
470void __init arch_init_ipiirq(int irq, struct irqaction *action)
471{
472 setup_irq(irq, action);
473 set_irq_handler(irq, handle_percpu_irq);
474}
475
450void __init arch_init_irq(void) 476void __init arch_init_irq(void)
451{ 477{
452 init_i8259_irqs(); 478 init_i8259_irqs();
@@ -458,12 +484,17 @@ void __init arch_init_irq(void)
458 GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK; 484 GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
459 gic_present = 1; 485 gic_present = 1;
460 } else { 486 } else {
461 _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); 487 if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
462 gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & 488 _msc01_biu_base = (unsigned long)
463 MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF; 489 ioremap_nocache(MSC01_BIU_REG_BASE,
490 MSC01_BIU_ADDRSPACE_SZ);
491 gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) &
492 MSC01_SC_CFG_GICPRES_MSK) >>
493 MSC01_SC_CFG_GICPRES_SHF;
494 }
464 } 495 }
465 if (gic_present) 496 if (gic_present)
466 printk(KERN_DEBUG "GIC present\n"); 497 pr_debug("GIC present\n");
467 498
468 switch (mips_revision_sconid) { 499 switch (mips_revision_sconid) {
469 case MIPS_REVISION_SCON_SOCIT: 500 case MIPS_REVISION_SCON_SOCIT:
@@ -526,16 +557,16 @@ void __init arch_init_irq(void)
526 &corehi_irqaction); 557 &corehi_irqaction);
527 } 558 }
528 559
529#if defined(CONFIG_MIPS_MT_SMP)
530 if (gic_present) { 560 if (gic_present) {
531 /* FIXME */ 561 /* FIXME */
532 int i; 562 int i;
533 563#if defined(CONFIG_MIPS_MT_SMP)
534 gic_call_int_base = GIC_NUM_INTRS - NR_CPUS; 564 gic_call_int_base = GIC_NUM_INTRS - NR_CPUS;
535 gic_resched_int_base = gic_call_int_base - NR_CPUS; 565 gic_resched_int_base = gic_call_int_base - NR_CPUS;
536
537 fill_ipi_map(); 566 fill_ipi_map();
538 gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); 567#endif
568 gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
569 ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
539 if (!gcmp_present) { 570 if (!gcmp_present) {
540 /* Enable the GIC */ 571 /* Enable the GIC */
541 i = REG(_msc01_biu_base, MSC01_SC_CFG); 572 i = REG(_msc01_biu_base, MSC01_SC_CFG);
@@ -543,7 +574,7 @@ void __init arch_init_irq(void)
543 (i | (0x1 << MSC01_SC_CFG_GICENA_SHF)); 574 (i | (0x1 << MSC01_SC_CFG_GICENA_SHF));
544 pr_debug("GIC Enabled\n"); 575 pr_debug("GIC Enabled\n");
545 } 576 }
546 577#if defined(CONFIG_MIPS_MT_SMP)
547 /* set up ipi interrupts */ 578 /* set up ipi interrupts */
548 if (cpu_has_vint) { 579 if (cpu_has_vint) {
549 set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch); 580 set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch);
@@ -556,16 +587,14 @@ void __init arch_init_irq(void)
556 write_c0_status(0x1100dc00); 587 write_c0_status(0x1100dc00);
557 printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); 588 printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status());
558 for (i = 0; i < NR_CPUS; i++) { 589 for (i = 0; i < NR_CPUS; i++) {
559 setup_irq(MIPS_GIC_IRQ_BASE + 590 arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
560 GIC_RESCHED_INT(i), &irq_resched); 591 GIC_RESCHED_INT(i), &irq_resched);
561 setup_irq(MIPS_GIC_IRQ_BASE + 592 arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
562 GIC_CALL_INT(i), &irq_call); 593 GIC_CALL_INT(i), &irq_call);
563 set_irq_handler(MIPS_GIC_IRQ_BASE +
564 GIC_RESCHED_INT(i), handle_percpu_irq);
565 set_irq_handler(MIPS_GIC_IRQ_BASE +
566 GIC_CALL_INT(i), handle_percpu_irq);
567 } 594 }
595#endif
568 } else { 596 } else {
597#if defined(CONFIG_MIPS_MT_SMP)
569 /* set up ipi interrupts */ 598 /* set up ipi interrupts */
570 if (cpu_has_veic) { 599 if (cpu_has_veic) {
571 set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch); 600 set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
@@ -580,14 +609,10 @@ void __init arch_init_irq(void)
580 cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; 609 cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
581 cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; 610 cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
582 } 611 }
583 612 arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
584 setup_irq(cpu_ipi_resched_irq, &irq_resched); 613 arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
585 setup_irq(cpu_ipi_call_irq, &irq_call);
586
587 set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq);
588 set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq);
589 }
590#endif 614#endif
615 }
591} 616}
592 617
593void malta_be_init(void) 618void malta_be_init(void)
diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c
index b9743190609a..2fbfa1a8c3a9 100644
--- a/arch/mips/mti-malta/malta-pci.c
+++ b/arch/mips/mti-malta/malta-pci.c
@@ -27,7 +27,7 @@
27#include <linux/init.h> 27#include <linux/init.h>
28 28
29#include <asm/gt64120.h> 29#include <asm/gt64120.h>
30 30#include <asm/gcmpregs.h>
31#include <asm/mips-boards/generic.h> 31#include <asm/mips-boards/generic.h>
32#include <asm/mips-boards/bonito64.h> 32#include <asm/mips-boards/bonito64.h>
33#include <asm/mips-boards/msc01_pci.h> 33#include <asm/mips-boards/msc01_pci.h>
@@ -201,7 +201,11 @@ void __init mips_pcibios_init(void)
201 msc_mem_resource.start = start & mask; 201 msc_mem_resource.start = start & mask;
202 msc_mem_resource.end = (start & mask) | ~mask; 202 msc_mem_resource.end = (start & mask) | ~mask;
203 msc_controller.mem_offset = (start & mask) - (map & mask); 203 msc_controller.mem_offset = (start & mask) - (map & mask);
204 204#ifdef CONFIG_MIPS_CMP
205 if (gcmp_niocu())
206 gcmp_setregion(0, start, mask,
207 GCMP_GCB_GCMPB_CMDEFTGT_IOCU1);
208#endif
205 MSC_READ(MSC01_PCI_SC2PIOBASL, start); 209 MSC_READ(MSC01_PCI_SC2PIOBASL, start);
206 MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); 210 MSC_READ(MSC01_PCI_SC2PIOMSKL, mask);
207 MSC_READ(MSC01_PCI_SC2PIOMAPL, map); 211 MSC_READ(MSC01_PCI_SC2PIOMAPL, map);
@@ -209,7 +213,11 @@ void __init mips_pcibios_init(void)
209 msc_io_resource.end = (map & mask) | ~mask; 213 msc_io_resource.end = (map & mask) | ~mask;
210 msc_controller.io_offset = 0; 214 msc_controller.io_offset = 0;
211 ioport_resource.end = ~mask; 215 ioport_resource.end = ~mask;
212 216#ifdef CONFIG_MIPS_CMP
217 if (gcmp_niocu())
218 gcmp_setregion(1, start, mask,
219 GCMP_GCB_GCMPB_CMDEFTGT_IOCU1);
220#endif
213 /* If ranges overlap I/O takes precedence. */ 221 /* If ranges overlap I/O takes precedence. */
214 start = start & mask; 222 start = start & mask;
215 end = start | ~mask; 223 end = start | ~mask;
@@ -241,3 +249,16 @@ void __init mips_pcibios_init(void)
241 249
242 register_pci_controller(controller); 250 register_pci_controller(controller);
243} 251}
252
253/* Enable PCI 2.1 compatibility in PIIX4 */
254static void __init quirk_dlcsetup(struct pci_dev *dev)
255{
256 u8 odlc, ndlc;
257 (void) pci_read_config_byte(dev, 0x82, &odlc);
258 /* Enable passive releases and delayed transaction */
259 ndlc = odlc | 7;
260 (void) pci_write_config_byte(dev, 0x82, ndlc);
261}
262
263DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
264 quirk_dlcsetup);
diff --git a/arch/mips/nxp/pnx8550/common/int.c b/arch/mips/nxp/pnx8550/common/int.c
index f080f114a1bf..7aca7d5375e5 100644
--- a/arch/mips/nxp/pnx8550/common/int.c
+++ b/arch/mips/nxp/pnx8550/common/int.c
@@ -172,7 +172,7 @@ static struct irqaction gic_action = {
172 172
173static struct irqaction timer_action = { 173static struct irqaction timer_action = {
174 .handler = no_action, 174 .handler = no_action,
175 .flags = IRQF_DISABLED, 175 .flags = IRQF_DISABLED | IRQF_TIMER,
176 .name = "Timer", 176 .name = "Timer",
177}; 177};
178 178
diff --git a/arch/mips/nxp/pnx8550/common/time.c b/arch/mips/nxp/pnx8550/common/time.c
index 18b192784877..8836c6203df0 100644
--- a/arch/mips/nxp/pnx8550/common/time.c
+++ b/arch/mips/nxp/pnx8550/common/time.c
@@ -59,7 +59,7 @@ static irqreturn_t pnx8xxx_timer_interrupt(int irq, void *dev_id)
59 59
60static struct irqaction pnx8xxx_timer_irq = { 60static struct irqaction pnx8xxx_timer_irq = {
61 .handler = pnx8xxx_timer_interrupt, 61 .handler = pnx8xxx_timer_interrupt,
62 .flags = IRQF_DISABLED | IRQF_PERCPU, 62 .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
63 .name = "pnx8xxx_timer", 63 .name = "pnx8xxx_timer",
64}; 64};
65 65
@@ -72,7 +72,7 @@ static irqreturn_t monotonic_interrupt(int irq, void *dev_id)
72 72
73static struct irqaction monotonic_irqaction = { 73static struct irqaction monotonic_irqaction = {
74 .handler = monotonic_interrupt, 74 .handler = monotonic_interrupt,
75 .flags = IRQF_DISABLED, 75 .flags = IRQF_DISABLED | IRQF_TIMER,
76 .name = "Monotonic timer", 76 .name = "Monotonic timer",
77}; 77};
78 78
diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c
index deed1d5d4982..575cd1473475 100644
--- a/arch/mips/oprofile/op_model_loongson2.c
+++ b/arch/mips/oprofile/op_model_loongson2.c
@@ -22,7 +22,7 @@
22 * otherwise, the oprofile tool will not recognize this and complain about 22 * otherwise, the oprofile tool will not recognize this and complain about
23 * "cpu_type 'unset' is not valid". 23 * "cpu_type 'unset' is not valid".
24 */ 24 */
25#define LOONGSON2_CPU_TYPE "mips/godson2" 25#define LOONGSON2_CPU_TYPE "mips/loongson2"
26 26
27#define LOONGSON2_COUNTER1_EVENT(event) ((event & 0x0f) << 5) 27#define LOONGSON2_COUNTER1_EVENT(event) ((event & 0x0f) << 5)
28#define LOONGSON2_COUNTER2_EVENT(event) ((event & 0x0f) << 9) 28#define LOONGSON2_COUNTER2_EVENT(event) ((event & 0x0f) << 9)
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index 6d0e59ffba2e..d6802d6d1f82 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -105,7 +105,7 @@ static irqreturn_t hub_rt_counter_handler(int irq, void *dev_id)
105 105
106struct irqaction hub_rt_irqaction = { 106struct irqaction hub_rt_irqaction = {
107 .handler = hub_rt_counter_handler, 107 .handler = hub_rt_counter_handler,
108 .flags = IRQF_DISABLED | IRQF_PERCPU, 108 .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
109 .name = "hub-rt", 109 .name = "hub-rt",
110}; 110};
111 111
diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c
index 62df6a598e0a..f3b60e671207 100644
--- a/arch/mips/sni/time.c
+++ b/arch/mips/sni/time.c
@@ -67,7 +67,7 @@ static irqreturn_t a20r_interrupt(int irq, void *dev_id)
67 67
68static struct irqaction a20r_irqaction = { 68static struct irqaction a20r_irqaction = {
69 .handler = a20r_interrupt, 69 .handler = a20r_interrupt,
70 .flags = IRQF_DISABLED | IRQF_PERCPU, 70 .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
71 .name = "a20r-timer", 71 .name = "a20r-timer",
72}; 72};
73 73
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index c860810722c0..e10184c1b3e1 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -85,7 +85,7 @@ int txx9_ccfg_toeon __initdata = 1;
85struct clk *clk_get(struct device *dev, const char *id) 85struct clk *clk_get(struct device *dev, const char *id)
86{ 86{
87 if (!strcmp(id, "spi-baseclk")) 87 if (!strcmp(id, "spi-baseclk"))
88 return (struct clk *)((unsigned long)txx9_gbus_clock / 2 / 4); 88 return (struct clk *)((unsigned long)txx9_gbus_clock / 2 / 2);
89 if (!strcmp(id, "imbus_clk")) 89 if (!strcmp(id, "imbus_clk"))
90 return (struct clk *)((unsigned long)txx9_gbus_clock / 2); 90 return (struct clk *)((unsigned long)txx9_gbus_clock / 2);
91 return ERR_PTR(-ENOENT); 91 return ERR_PTR(-ENOENT);
@@ -817,7 +817,8 @@ void __init txx9_iocled_init(unsigned long baseaddr,
817out_pdev: 817out_pdev:
818 platform_device_put(pdev); 818 platform_device_put(pdev);
819out_gpio: 819out_gpio:
820 gpio_remove(&iocled->chip); 820 if (gpiochip_remove(&iocled->chip))
821 return;
821out_unmap: 822out_unmap:
822 iounmap(iocled->mmioaddr); 823 iounmap(iocled->mmioaddr);
823out_free: 824out_free:
diff --git a/arch/s390/include/asm/cputime.h b/arch/s390/include/asm/cputime.h
index 24b1244aadb9..f23961ada7fb 100644
--- a/arch/s390/include/asm/cputime.h
+++ b/arch/s390/include/asm/cputime.h
@@ -78,7 +78,7 @@ cputime64_to_jiffies64(cputime64_t cputime)
78static inline unsigned int 78static inline unsigned int
79cputime_to_msecs(const cputime_t cputime) 79cputime_to_msecs(const cputime_t cputime)
80{ 80{
81 return __div(cputime, 4096000); 81 return cputime_div(cputime, 4096000);
82} 82}
83 83
84static inline cputime_t 84static inline cputime_t
@@ -160,7 +160,7 @@ cputime_to_timeval(const cputime_t cputime, struct timeval *value)
160static inline clock_t 160static inline clock_t
161cputime_to_clock_t(cputime_t cputime) 161cputime_to_clock_t(cputime_t cputime)
162{ 162{
163 return __div(cputime, 4096000000ULL / USER_HZ); 163 return cputime_div(cputime, 4096000000ULL / USER_HZ);
164} 164}
165 165
166static inline cputime_t 166static inline cputime_t
@@ -175,7 +175,7 @@ clock_t_to_cputime(unsigned long x)
175static inline clock_t 175static inline clock_t
176cputime64_to_clock_t(cputime64_t cputime) 176cputime64_to_clock_t(cputime64_t cputime)
177{ 177{
178 return __div(cputime, 4096000000ULL / USER_HZ); 178 return cputime_div(cputime, 4096000000ULL / USER_HZ);
179} 179}
180 180
181struct s390_idle_data { 181struct s390_idle_data {
diff --git a/arch/s390/kernel/ipl.c b/arch/s390/kernel/ipl.c
index ee57a42e6e93..4890ac6d7faa 100644
--- a/arch/s390/kernel/ipl.c
+++ b/arch/s390/kernel/ipl.c
@@ -1595,10 +1595,9 @@ static void stop_run(struct shutdown_trigger *trigger)
1595{ 1595{
1596 if (strcmp(trigger->name, ON_PANIC_STR) == 0) 1596 if (strcmp(trigger->name, ON_PANIC_STR) == 0)
1597 disabled_wait((unsigned long) __builtin_return_address(0)); 1597 disabled_wait((unsigned long) __builtin_return_address(0));
1598 else { 1598 while (signal_processor(smp_processor_id(), sigp_stop) == sigp_busy)
1599 signal_processor(smp_processor_id(), sigp_stop); 1599 cpu_relax();
1600 for (;;); 1600 for (;;);
1601 }
1602} 1601}
1603 1602
1604static struct shutdown_action stop_action = {SHUTDOWN_ACTION_STOP_STR, 1603static struct shutdown_action stop_action = {SHUTDOWN_ACTION_STOP_STR,
diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c
index c932caa5e850..93e52039321b 100644
--- a/arch/s390/kernel/smp.c
+++ b/arch/s390/kernel/smp.c
@@ -76,7 +76,6 @@ static int cpu_stopped(int cpu)
76 __u32 status; 76 __u32 status;
77 77
78 switch (signal_processor_ps(&status, 0, cpu, sigp_sense)) { 78 switch (signal_processor_ps(&status, 0, cpu, sigp_sense)) {
79 case sigp_order_code_accepted:
80 case sigp_status_stored: 79 case sigp_status_stored:
81 /* Check for stopped and check stop state */ 80 /* Check for stopped and check stop state */
82 if (status & 0x50) 81 if (status & 0x50)
@@ -638,6 +637,8 @@ void __cpu_die(unsigned int cpu)
638 /* Wait until target cpu is down */ 637 /* Wait until target cpu is down */
639 while (!cpu_stopped(cpu)) 638 while (!cpu_stopped(cpu))
640 cpu_relax(); 639 cpu_relax();
640 while (signal_processor_p(0, cpu, sigp_set_prefix) == sigp_busy)
641 udelay(10);
641 smp_free_lowcore(cpu); 642 smp_free_lowcore(cpu);
642 pr_info("Processor %d stopped\n", cpu); 643 pr_info("Processor %d stopped\n", cpu);
643} 644}
@@ -645,8 +646,8 @@ void __cpu_die(unsigned int cpu)
645void cpu_die(void) 646void cpu_die(void)
646{ 647{
647 idle_task_exit(); 648 idle_task_exit();
648 signal_processor(smp_processor_id(), sigp_stop); 649 while (signal_processor(smp_processor_id(), sigp_stop) == sigp_busy)
649 BUG(); 650 cpu_relax();
650 for (;;); 651 for (;;);
651} 652}
652 653
diff --git a/arch/s390/kernel/swsusp_asm64.S b/arch/s390/kernel/swsusp_asm64.S
index 7c8653e27db6..0c26cc1898ec 100644
--- a/arch/s390/kernel/swsusp_asm64.S
+++ b/arch/s390/kernel/swsusp_asm64.S
@@ -199,6 +199,7 @@ pgm_check_entry:
199 brc 2,4b /* busy, try again */ 199 brc 2,4b /* busy, try again */
2005: 2005:
201 sigp %r9,%r2,__SIGP_STOP /* stop resume (current) CPU */ 201 sigp %r9,%r2,__SIGP_STOP /* stop resume (current) CPU */
202 brc 2,5b /* busy, try again */
2026: j 6b 2036: j 6b
203 204
204restart_suspend: 205restart_suspend:
@@ -206,6 +207,7 @@ restart_suspend:
206 llgh %r2,0(%r1) 207 llgh %r2,0(%r1)
2077: 2087:
208 sigp %r9,%r2,__SIGP_SENSE /* Wait for resume CPU */ 209 sigp %r9,%r2,__SIGP_SENSE /* Wait for resume CPU */
210 brc 8,7b /* accepted, status 0, still running */
209 brc 2,7b /* busy, try again */ 211 brc 2,7b /* busy, try again */
210 tmll %r9,0x40 /* Test if resume CPU is stopped */ 212 tmll %r9,0x40 /* Test if resume CPU is stopped */
211 jz 7b 213 jz 7b
diff --git a/arch/sh/include/asm/rwsem.h b/arch/sh/include/asm/rwsem.h
index 1987f3ea7f1b..06e2251a5e48 100644
--- a/arch/sh/include/asm/rwsem.h
+++ b/arch/sh/include/asm/rwsem.h
@@ -41,7 +41,7 @@ struct rw_semaphore {
41#endif 41#endif
42 42
43#define __RWSEM_INITIALIZER(name) \ 43#define __RWSEM_INITIALIZER(name) \
44 { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \ 44 { RWSEM_UNLOCKED_VALUE, __SPIN_LOCK_UNLOCKED((name).wait_lock), \
45 LIST_HEAD_INIT((name).wait_list) \ 45 LIST_HEAD_INIT((name).wait_list) \
46 __RWSEM_DEP_MAP_INIT(name) } 46 __RWSEM_DEP_MAP_INIT(name) }
47 47
diff --git a/arch/sh/kernel/dwarf.c b/arch/sh/kernel/dwarf.c
index 2d07084e4882..d76a23170dbb 100644
--- a/arch/sh/kernel/dwarf.c
+++ b/arch/sh/kernel/dwarf.c
@@ -555,7 +555,7 @@ struct dwarf_frame * dwarf_unwind_stack(unsigned long pc,
555 * NOTE: the return address is guaranteed to be setup by the 555 * NOTE: the return address is guaranteed to be setup by the
556 * time this function makes its first function call. 556 * time this function makes its first function call.
557 */ 557 */
558 if (!pc && !prev) 558 if (!pc || !prev)
559 pc = (unsigned long)current_text_addr(); 559 pc = (unsigned long)current_text_addr();
560 560
561#ifdef CONFIG_FUNCTION_GRAPH_TRACER 561#ifdef CONFIG_FUNCTION_GRAPH_TRACER
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index 519e2d16cd06..b7f235c74d66 100644
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -72,6 +72,7 @@ static void __uses_jump_to_uncached sh4_flush_icache_range(void *args)
72 72
73 for (v = start; v < end; v += L1_CACHE_BYTES) { 73 for (v = start; v < end; v += L1_CACHE_BYTES) {
74 unsigned long icacheaddr; 74 unsigned long icacheaddr;
75 int j, n;
75 76
76 __ocbwb(v); 77 __ocbwb(v);
77 78
@@ -79,8 +80,10 @@ static void __uses_jump_to_uncached sh4_flush_icache_range(void *args)
79 cpu_data->icache.entry_mask); 80 cpu_data->icache.entry_mask);
80 81
81 /* Clear i-cache line valid-bit */ 82 /* Clear i-cache line valid-bit */
83 n = boot_cpu_data.icache.n_aliases;
82 for (i = 0; i < cpu_data->icache.ways; i++) { 84 for (i = 0; i < cpu_data->icache.ways; i++) {
83 __raw_writel(0, icacheaddr); 85 for (j = 0; j < n; j++)
86 __raw_writel(0, icacheaddr + (j * PAGE_SIZE));
84 icacheaddr += cpu_data->icache.way_incr; 87 icacheaddr += cpu_data->icache.way_incr;
85 } 88 }
86 } 89 }
diff --git a/arch/sparc/include/asm/system_64.h b/arch/sparc/include/asm/system_64.h
index 25e848f0cad7..d47a98e66972 100644
--- a/arch/sparc/include/asm/system_64.h
+++ b/arch/sparc/include/asm/system_64.h
@@ -63,6 +63,10 @@ do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \
63 : : : "memory"); \ 63 : : : "memory"); \
64} while (0) 64} while (0)
65 65
66/* The kernel always executes in TSO memory model these days,
67 * and furthermore most sparc64 chips implement more stringent
68 * memory ordering than required by the specifications.
69 */
66#define mb() membar_safe("#StoreLoad") 70#define mb() membar_safe("#StoreLoad")
67#define rmb() __asm__ __volatile__("":::"memory") 71#define rmb() __asm__ __volatile__("":::"memory")
68#define wmb() __asm__ __volatile__("":::"memory") 72#define wmb() __asm__ __volatile__("":::"memory")
diff --git a/arch/sparc/kernel/prom_common.c b/arch/sparc/kernel/prom_common.c
index 138910c67206..d80a65d9e893 100644
--- a/arch/sparc/kernel/prom_common.c
+++ b/arch/sparc/kernel/prom_common.c
@@ -79,6 +79,7 @@ int of_set_property(struct device_node *dp, const char *name, void *val, int len
79 79
80 err = -ENODEV; 80 err = -ENODEV;
81 81
82 mutex_lock(&of_set_property_mutex);
82 write_lock(&devtree_lock); 83 write_lock(&devtree_lock);
83 prevp = &dp->properties; 84 prevp = &dp->properties;
84 while (*prevp) { 85 while (*prevp) {
@@ -88,9 +89,7 @@ int of_set_property(struct device_node *dp, const char *name, void *val, int len
88 void *old_val = prop->value; 89 void *old_val = prop->value;
89 int ret; 90 int ret;
90 91
91 mutex_lock(&of_set_property_mutex);
92 ret = prom_setprop(dp->node, name, val, len); 92 ret = prom_setprop(dp->node, name, val, len);
93 mutex_unlock(&of_set_property_mutex);
94 93
95 err = -EINVAL; 94 err = -EINVAL;
96 if (ret >= 0) { 95 if (ret >= 0) {
@@ -109,6 +108,7 @@ int of_set_property(struct device_node *dp, const char *name, void *val, int len
109 prevp = &(*prevp)->next; 108 prevp = &(*prevp)->next;
110 } 109 }
111 write_unlock(&devtree_lock); 110 write_unlock(&devtree_lock);
111 mutex_unlock(&of_set_property_mutex);
112 112
113 /* XXX Upate procfs if necessary... */ 113 /* XXX Upate procfs if necessary... */
114 114
diff --git a/arch/sparc/kernel/visemul.c b/arch/sparc/kernel/visemul.c
index b956fd71c131..d231cbd5c526 100644
--- a/arch/sparc/kernel/visemul.c
+++ b/arch/sparc/kernel/visemul.c
@@ -617,7 +617,7 @@ static void pmul(struct pt_regs *regs, unsigned int insn, unsigned int opf)
617 rs2 = fps_regval(f, RS2(insn)); 617 rs2 = fps_regval(f, RS2(insn));
618 618
619 rd_val = 0; 619 rd_val = 0;
620 src2 = (rs2 >> (opf == FMUL8x16AU_OPF) ? 16 : 0); 620 src2 = rs2 >> (opf == FMUL8x16AU_OPF ? 16 : 0);
621 for (byte = 0; byte < 4; byte++) { 621 for (byte = 0; byte < 4; byte++) {
622 u16 src1 = (rs1 >> (byte * 8)) & 0x00ff; 622 u16 src1 = (rs1 >> (byte * 8)) & 0x00ff;
623 u32 prod = src1 * src2; 623 u32 prod = src1 * src2;
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 07e01149e3bf..72ace9515a07 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1443,12 +1443,8 @@ config SECCOMP
1443 1443
1444 If unsure, say Y. Only embedded should say N here. 1444 If unsure, say Y. Only embedded should say N here.
1445 1445
1446config CC_STACKPROTECTOR_ALL
1447 bool
1448
1449config CC_STACKPROTECTOR 1446config CC_STACKPROTECTOR
1450 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" 1447 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1451 select CC_STACKPROTECTOR_ALL
1452 ---help--- 1448 ---help---
1453 This option turns on the -fstack-protector GCC feature. This 1449 This option turns on the -fstack-protector GCC feature. This
1454 feature puts, at the beginning of functions, a canary value on 1450 feature puts, at the beginning of functions, a canary value on
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index f2824fb8c79c..2649840d888f 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -400,7 +400,7 @@ config X86_TSC
400 400
401config X86_CMPXCHG64 401config X86_CMPXCHG64
402 def_bool y 402 def_bool y
403 depends on X86_PAE || X86_64 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MATOM 403 depends on !M386 && !M486
404 404
405# this should be set for all -march=.. options where the compiler 405# this should be set for all -march=.. options where the compiler
406# generates cmov. 406# generates cmov.
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index a012ee8ef803..d2d24c9ee64d 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -76,7 +76,6 @@ ifdef CONFIG_CC_STACKPROTECTOR
76 cc_has_sp := $(srctree)/scripts/gcc-x86_$(BITS)-has-stack-protector.sh 76 cc_has_sp := $(srctree)/scripts/gcc-x86_$(BITS)-has-stack-protector.sh
77 ifeq ($(shell $(CONFIG_SHELL) $(cc_has_sp) $(CC) $(biarch)),y) 77 ifeq ($(shell $(CONFIG_SHELL) $(cc_has_sp) $(CC) $(biarch)),y)
78 stackp-y := -fstack-protector 78 stackp-y := -fstack-protector
79 stackp-$(CONFIG_CC_STACKPROTECTOR_ALL) += -fstack-protector-all
80 KBUILD_CFLAGS += $(stackp-y) 79 KBUILD_CFLAGS += $(stackp-y)
81 else 80 else
82 $(warning stack protector enabled but no compiler support) 81 $(warning stack protector enabled but no compiler support)
diff --git a/arch/x86/ia32/ia32entry.S b/arch/x86/ia32/ia32entry.S
index 1733f9f65e82..581b0568fe19 100644
--- a/arch/x86/ia32/ia32entry.S
+++ b/arch/x86/ia32/ia32entry.S
@@ -204,7 +204,7 @@ sysexit_from_sys_call:
204 movl RDI-ARGOFFSET(%rsp),%r8d /* reload 5th syscall arg */ 204 movl RDI-ARGOFFSET(%rsp),%r8d /* reload 5th syscall arg */
205 .endm 205 .endm
206 206
207 .macro auditsys_exit exit,ebpsave=RBP 207 .macro auditsys_exit exit
208 testl $(_TIF_ALLWORK_MASK & ~_TIF_SYSCALL_AUDIT),TI_flags(%r10) 208 testl $(_TIF_ALLWORK_MASK & ~_TIF_SYSCALL_AUDIT),TI_flags(%r10)
209 jnz ia32_ret_from_sys_call 209 jnz ia32_ret_from_sys_call
210 TRACE_IRQS_ON 210 TRACE_IRQS_ON
@@ -217,7 +217,6 @@ sysexit_from_sys_call:
217 call audit_syscall_exit 217 call audit_syscall_exit
218 GET_THREAD_INFO(%r10) 218 GET_THREAD_INFO(%r10)
219 movl RAX-ARGOFFSET(%rsp),%eax /* reload syscall return value */ 219 movl RAX-ARGOFFSET(%rsp),%eax /* reload syscall return value */
220 movl \ebpsave-ARGOFFSET(%rsp),%ebp /* reload user register value */
221 movl $(_TIF_ALLWORK_MASK & ~_TIF_SYSCALL_AUDIT),%edi 220 movl $(_TIF_ALLWORK_MASK & ~_TIF_SYSCALL_AUDIT),%edi
222 cli 221 cli
223 TRACE_IRQS_OFF 222 TRACE_IRQS_OFF
@@ -351,7 +350,7 @@ cstar_auditsys:
351 jmp cstar_dispatch 350 jmp cstar_dispatch
352 351
353sysretl_audit: 352sysretl_audit:
354 auditsys_exit sysretl_from_sys_call, RCX /* user %ebp in RCX slot */ 353 auditsys_exit sysretl_from_sys_call
355#endif 354#endif
356 355
357cstar_tracesys: 356cstar_tracesys:
diff --git a/arch/x86/include/asm/amd_iommu.h b/arch/x86/include/asm/amd_iommu.h
index ac95995b7bad..4b180897e6b5 100644
--- a/arch/x86/include/asm/amd_iommu.h
+++ b/arch/x86/include/asm/amd_iommu.h
@@ -31,6 +31,7 @@ extern irqreturn_t amd_iommu_int_handler(int irq, void *data);
31extern void amd_iommu_flush_all_domains(void); 31extern void amd_iommu_flush_all_domains(void);
32extern void amd_iommu_flush_all_devices(void); 32extern void amd_iommu_flush_all_devices(void);
33extern void amd_iommu_shutdown(void); 33extern void amd_iommu_shutdown(void);
34extern void amd_iommu_apply_erratum_63(u16 devid);
34#else 35#else
35static inline int amd_iommu_init(void) { return -ENODEV; } 36static inline int amd_iommu_init(void) { return -ENODEV; }
36static inline void amd_iommu_detect(void) { } 37static inline void amd_iommu_detect(void) { }
diff --git a/arch/x86/include/asm/desc.h b/arch/x86/include/asm/desc.h
index e8de2f6f5ca5..617bd56b3070 100644
--- a/arch/x86/include/asm/desc.h
+++ b/arch/x86/include/asm/desc.h
@@ -288,7 +288,7 @@ static inline void load_LDT(mm_context_t *pc)
288 288
289static inline unsigned long get_desc_base(const struct desc_struct *desc) 289static inline unsigned long get_desc_base(const struct desc_struct *desc)
290{ 290{
291 return desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24); 291 return (unsigned)(desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24));
292} 292}
293 293
294static inline void set_desc_base(struct desc_struct *desc, unsigned long base) 294static inline void set_desc_base(struct desc_struct *desc, unsigned long base)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index c3429e8b2424..c9786480f0fe 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -1000,7 +1000,7 @@ extern unsigned long thread_saved_pc(struct task_struct *tsk);
1000#define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8)) 1000#define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
1001 1001
1002#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) 1002#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
1003#define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */ 1003extern unsigned long KSTK_ESP(struct task_struct *task);
1004#endif /* CONFIG_X86_64 */ 1004#endif /* CONFIG_X86_64 */
1005 1005
1006extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 1006extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h
index d823c245f63b..40e37b10c6c0 100644
--- a/arch/x86/include/asm/topology.h
+++ b/arch/x86/include/asm/topology.h
@@ -143,7 +143,7 @@ extern unsigned long node_remap_size[];
143 | 1*SD_BALANCE_FORK \ 143 | 1*SD_BALANCE_FORK \
144 | 0*SD_BALANCE_WAKE \ 144 | 0*SD_BALANCE_WAKE \
145 | 1*SD_WAKE_AFFINE \ 145 | 1*SD_WAKE_AFFINE \
146 | 1*SD_PREFER_LOCAL \ 146 | 0*SD_PREFER_LOCAL \
147 | 0*SD_SHARE_CPUPOWER \ 147 | 0*SD_SHARE_CPUPOWER \
148 | 0*SD_POWERSAVINGS_BALANCE \ 148 | 0*SD_POWERSAVINGS_BALANCE \
149 | 0*SD_SHARE_PKG_RESOURCES \ 149 | 0*SD_SHARE_PKG_RESOURCES \
diff --git a/arch/x86/kernel/amd_iommu.c b/arch/x86/kernel/amd_iommu.c
index 98f230f6a28d..0285521e0a99 100644
--- a/arch/x86/kernel/amd_iommu.c
+++ b/arch/x86/kernel/amd_iommu.c
@@ -1220,6 +1220,8 @@ static void __detach_device(struct protection_domain *domain, u16 devid)
1220 amd_iommu_dev_table[devid].data[1] = 0; 1220 amd_iommu_dev_table[devid].data[1] = 0;
1221 amd_iommu_dev_table[devid].data[2] = 0; 1221 amd_iommu_dev_table[devid].data[2] = 0;
1222 1222
1223 amd_iommu_apply_erratum_63(devid);
1224
1223 /* decrease reference counter */ 1225 /* decrease reference counter */
1224 domain->dev_cnt -= 1; 1226 domain->dev_cnt -= 1;
1225 1227
diff --git a/arch/x86/kernel/amd_iommu_init.c b/arch/x86/kernel/amd_iommu_init.c
index b4b61d462dcc..c20001e4f556 100644
--- a/arch/x86/kernel/amd_iommu_init.c
+++ b/arch/x86/kernel/amd_iommu_init.c
@@ -240,7 +240,7 @@ static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
240 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 240 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
241} 241}
242 242
243static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit) 243static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
244{ 244{
245 u32 ctrl; 245 u32 ctrl;
246 246
@@ -519,6 +519,26 @@ static void set_dev_entry_bit(u16 devid, u8 bit)
519 amd_iommu_dev_table[devid].data[i] |= (1 << _bit); 519 amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
520} 520}
521 521
522static int get_dev_entry_bit(u16 devid, u8 bit)
523{
524 int i = (bit >> 5) & 0x07;
525 int _bit = bit & 0x1f;
526
527 return (amd_iommu_dev_table[devid].data[i] & (1 << _bit)) >> _bit;
528}
529
530
531void amd_iommu_apply_erratum_63(u16 devid)
532{
533 int sysmgt;
534
535 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
536 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
537
538 if (sysmgt == 0x01)
539 set_dev_entry_bit(devid, DEV_ENTRY_IW);
540}
541
522/* Writes the specific IOMMU for a device into the rlookup table */ 542/* Writes the specific IOMMU for a device into the rlookup table */
523static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) 543static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
524{ 544{
@@ -547,6 +567,8 @@ static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
547 if (flags & ACPI_DEVFLAG_LINT1) 567 if (flags & ACPI_DEVFLAG_LINT1)
548 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); 568 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
549 569
570 amd_iommu_apply_erratum_63(devid);
571
550 set_iommu_for_device(iommu, devid); 572 set_iommu_for_device(iommu, devid);
551} 573}
552 574
diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/cleanup.c
index 315738c74aad..73c86db5acbe 100644
--- a/arch/x86/kernel/cpu/mtrr/cleanup.c
+++ b/arch/x86/kernel/cpu/mtrr/cleanup.c
@@ -846,7 +846,7 @@ int __init mtrr_cleanup(unsigned address_bits)
846 sort(range, nr_range, sizeof(struct res_range), cmp_range, NULL); 846 sort(range, nr_range, sizeof(struct res_range), cmp_range, NULL);
847 847
848 range_sums = sum_ranges(range, nr_range); 848 range_sums = sum_ranges(range, nr_range);
849 printk(KERN_INFO "total RAM coverred: %ldM\n", 849 printk(KERN_INFO "total RAM covered: %ldM\n",
850 range_sums >> (20 - PAGE_SHIFT)); 850 range_sums >> (20 - PAGE_SHIFT));
851 851
852 if (mtrr_chunk_size && mtrr_gran_size) { 852 if (mtrr_chunk_size && mtrr_gran_size) {
diff --git a/arch/x86/kernel/crash_dump_32.c b/arch/x86/kernel/crash_dump_32.c
index f7cdb3b457aa..cd97ce18c29d 100644
--- a/arch/x86/kernel/crash_dump_32.c
+++ b/arch/x86/kernel/crash_dump_32.c
@@ -16,6 +16,22 @@ static void *kdump_buf_page;
16/* Stores the physical address of elf header of crash image. */ 16/* Stores the physical address of elf header of crash image. */
17unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX; 17unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX;
18 18
19static inline bool is_crashed_pfn_valid(unsigned long pfn)
20{
21#ifndef CONFIG_X86_PAE
22 /*
23 * non-PAE kdump kernel executed from a PAE one will crop high pte
24 * bits and poke unwanted space counting again from address 0, we
25 * don't want that. pte must fit into unsigned long. In fact the
26 * test checks high 12 bits for being zero (pfn will be shifted left
27 * by PAGE_SHIFT).
28 */
29 return pte_pfn(pfn_pte(pfn, __pgprot(0))) == pfn;
30#else
31 return true;
32#endif
33}
34
19/** 35/**
20 * copy_oldmem_page - copy one page from "oldmem" 36 * copy_oldmem_page - copy one page from "oldmem"
21 * @pfn: page frame number to be copied 37 * @pfn: page frame number to be copied
@@ -41,6 +57,9 @@ ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
41 if (!csize) 57 if (!csize)
42 return 0; 58 return 0;
43 59
60 if (!is_crashed_pfn_valid(pfn))
61 return -EFAULT;
62
44 vaddr = kmap_atomic_pfn(pfn, KM_PTE0); 63 vaddr = kmap_atomic_pfn(pfn, KM_PTE0);
45 64
46 if (!userbuf) { 65 if (!userbuf) {
diff --git a/arch/x86/kernel/efi.c b/arch/x86/kernel/efi.c
index ad5bd988fb79..cdcfb122f256 100644
--- a/arch/x86/kernel/efi.c
+++ b/arch/x86/kernel/efi.c
@@ -454,8 +454,10 @@ void __init efi_init(void)
454 if (add_efi_memmap) 454 if (add_efi_memmap)
455 do_add_efi_memmap(); 455 do_add_efi_memmap();
456 456
457#ifdef CONFIG_X86_32
457 x86_platform.get_wallclock = efi_get_time; 458 x86_platform.get_wallclock = efi_get_time;
458 x86_platform.set_wallclock = efi_set_rtc_mmss; 459 x86_platform.set_wallclock = efi_set_rtc_mmss;
460#endif
459 461
460 /* Setup for EFI runtime service */ 462 /* Setup for EFI runtime service */
461 reboot_type = BOOT_EFI; 463 reboot_type = BOOT_EFI;
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index ad535b683170..eb62cbcaa490 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -664,3 +664,8 @@ long sys_arch_prctl(int code, unsigned long addr)
664 return do_arch_prctl(current, code, addr); 664 return do_arch_prctl(current, code, addr);
665} 665}
666 666
667unsigned long KSTK_ESP(struct task_struct *task)
668{
669 return (test_tsk_thread_flag(task, TIF_IA32)) ?
670 (task_pt_regs(task)->sp) : ((task)->thread.usersp);
671}
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index a1a3cdda06e1..f93078746e00 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -436,6 +436,14 @@ static struct dmi_system_id __initdata pci_reboot_dmi_table[] = {
436 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro5"), 436 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro5"),
437 }, 437 },
438 }, 438 },
439 { /* Handle problems with rebooting on Apple Macmini3,1 */
440 .callback = set_pci_reboot,
441 .ident = "Apple Macmini3,1",
442 .matches = {
443 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
444 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini3,1"),
445 },
446 },
439 { } 447 { }
440}; 448};
441 449
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 9b9695322f56..ae07d261527c 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1692,7 +1692,7 @@ static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1692 unsigned bank_num = mcg_cap & 0xff, bank; 1692 unsigned bank_num = mcg_cap & 0xff, bank;
1693 1693
1694 r = -EINVAL; 1694 r = -EINVAL;
1695 if (!bank_num) 1695 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
1696 goto out; 1696 goto out;
1697 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) 1697 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1698 goto out; 1698 goto out;
@@ -4051,7 +4051,7 @@ static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4051 return kvm_write_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu); 4051 return kvm_write_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
4052} 4052}
4053 4053
4054static u32 get_tss_base_addr(struct kvm_vcpu *vcpu, 4054static gpa_t get_tss_base_addr(struct kvm_vcpu *vcpu,
4055 struct desc_struct *seg_desc) 4055 struct desc_struct *seg_desc)
4056{ 4056{
4057 u32 base_addr = get_desc_base(seg_desc); 4057 u32 base_addr = get_desc_base(seg_desc);
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index 23a4d80fb39e..dfbf70e65860 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -178,6 +178,7 @@ static __read_mostly unsigned int cpuid_leaf1_ecx_mask = ~0;
178static void xen_cpuid(unsigned int *ax, unsigned int *bx, 178static void xen_cpuid(unsigned int *ax, unsigned int *bx,
179 unsigned int *cx, unsigned int *dx) 179 unsigned int *cx, unsigned int *dx)
180{ 180{
181 unsigned maskebx = ~0;
181 unsigned maskecx = ~0; 182 unsigned maskecx = ~0;
182 unsigned maskedx = ~0; 183 unsigned maskedx = ~0;
183 184
@@ -185,9 +186,16 @@ static void xen_cpuid(unsigned int *ax, unsigned int *bx,
185 * Mask out inconvenient features, to try and disable as many 186 * Mask out inconvenient features, to try and disable as many
186 * unsupported kernel subsystems as possible. 187 * unsupported kernel subsystems as possible.
187 */ 188 */
188 if (*ax == 1) { 189 switch (*ax) {
190 case 1:
189 maskecx = cpuid_leaf1_ecx_mask; 191 maskecx = cpuid_leaf1_ecx_mask;
190 maskedx = cpuid_leaf1_edx_mask; 192 maskedx = cpuid_leaf1_edx_mask;
193 break;
194
195 case 0xb:
196 /* Suppress extended topology stuff */
197 maskebx = 0;
198 break;
191 } 199 }
192 200
193 asm(XEN_EMULATE_PREFIX "cpuid" 201 asm(XEN_EMULATE_PREFIX "cpuid"
@@ -197,6 +205,7 @@ static void xen_cpuid(unsigned int *ax, unsigned int *bx,
197 "=d" (*dx) 205 "=d" (*dx)
198 : "0" (*ax), "2" (*cx)); 206 : "0" (*ax), "2" (*cx));
199 207
208 *bx &= maskebx;
200 *cx &= maskecx; 209 *cx &= maskecx;
201 *dx &= maskedx; 210 *dx &= maskedx;
202} 211}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-27 11:07:36 -0500