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-rw-r--r--arch/arm/mm/proc-v6.S14
1 files changed, 8 insertions, 6 deletions
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 7b1843befb9c..d78c0ae7c2c2 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -30,6 +30,12 @@
30#define TTB_RGN_WT (2 << 3) 30#define TTB_RGN_WT (2 << 3)
31#define TTB_RGN_WB (3 << 3) 31#define TTB_RGN_WB (3 << 3)
32 32
33#ifndef CONFIG_SMP
34#define TTB_FLAGS TTB_RGN_WBWA
35#else
36#define TTB_FLAGS TTB_RGN_WBWA|TTB_S
37#endif
38
33ENTRY(cpu_v6_proc_init) 39ENTRY(cpu_v6_proc_init)
34 mov pc, lr 40 mov pc, lr
35 41
@@ -92,9 +98,7 @@ ENTRY(cpu_v6_switch_mm)
92#ifdef CONFIG_MMU 98#ifdef CONFIG_MMU
93 mov r2, #0 99 mov r2, #0
94 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 100 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
95#ifdef CONFIG_SMP 101 orr r0, r0, #TTB_FLAGS
96 orr r0, r0, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable
97#endif
98 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 102 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
99 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 103 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
100 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 104 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
@@ -204,9 +208,7 @@ __v6_setup:
204#ifdef CONFIG_MMU 208#ifdef CONFIG_MMU
205 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs 209 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
206 mcr p15, 0, r0, c2, c0, 2 @ TTB control register 210 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
207#ifdef CONFIG_SMP 211 orr r4, r4, #TTB_FLAGS
208 orr r4, r4, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable
209#endif
210 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 212 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
211#endif /* CONFIG_MMU */ 213#endif /* CONFIG_MMU */
212 adr r5, v6_crval 214 adr r5, v6_crval