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-rw-r--r--arch/mips/Makefile5
-rw-r--r--arch/mips/alchemy/Kconfig19
-rw-r--r--arch/mips/alchemy/common/Makefile9
-rw-r--r--arch/mips/alchemy/common/gpio.c201
-rw-r--r--arch/mips/alchemy/common/gpiolib-au1000.c130
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio-au1000.h604
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio.h35
7 files changed, 770 insertions, 233 deletions
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 52a350974496..e5ccc3490d6a 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -183,7 +183,6 @@ load-$(CONFIG_MACH_JAZZ) += 0xffffffff80080000
183# Common Alchemy Au1x00 stuff 183# Common Alchemy Au1x00 stuff
184# 184#
185core-$(CONFIG_SOC_AU1X00) += arch/mips/alchemy/common/ 185core-$(CONFIG_SOC_AU1X00) += arch/mips/alchemy/common/
186cflags-$(CONFIG_SOC_AU1X00) += -I$(srctree)/arch/mips/include/asm/mach-au1x00
187 186
188# 187#
189# AMD Alchemy Pb1000 eval board 188# AMD Alchemy Pb1000 eval board
@@ -281,6 +280,10 @@ load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000
281libs-$(CONFIG_MIPS_XXS1500) += arch/mips/alchemy/xxs1500/ 280libs-$(CONFIG_MIPS_XXS1500) += arch/mips/alchemy/xxs1500/
282load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000 281load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000
283 282
283# must be last for Alchemy systems for GPIO to work properly
284cflags-$(CONFIG_SOC_AU1X00) += -I$(srctree)/arch/mips/include/asm/mach-au1x00
285
286
284# 287#
285# Cobalt Server 288# Cobalt Server
286# 289#
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index 8128aebfb155..00b498e97c83 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -1,3 +1,14 @@
1# au1000-style gpio
2config ALCHEMY_GPIO_AU1000
3 bool
4
5# select this in your board config if you don't want to use the gpio
6# namespace as documented in the manuals. In this case however you need
7# to create the necessary gpio_* functions in your board code/headers!
8# see arch/mips/include/asm/mach-au1x00/gpio.h for more information.
9config ALCHEMY_GPIO_INDIRECT
10 def_bool n
11
1choice 12choice
2 prompt "Machine type" 13 prompt "Machine type"
3 depends on MACH_ALCHEMY 14 depends on MACH_ALCHEMY
@@ -108,22 +119,27 @@ endchoice
108config SOC_AU1000 119config SOC_AU1000
109 bool 120 bool
110 select SOC_AU1X00 121 select SOC_AU1X00
122 select ALCHEMY_GPIO_AU1000
111 123
112config SOC_AU1100 124config SOC_AU1100
113 bool 125 bool
114 select SOC_AU1X00 126 select SOC_AU1X00
127 select ALCHEMY_GPIO_AU1000
115 128
116config SOC_AU1500 129config SOC_AU1500
117 bool 130 bool
118 select SOC_AU1X00 131 select SOC_AU1X00
132 select ALCHEMY_GPIO_AU1000
119 133
120config SOC_AU1550 134config SOC_AU1550
121 bool 135 bool
122 select SOC_AU1X00 136 select SOC_AU1X00
137 select ALCHEMY_GPIO_AU1000
123 138
124config SOC_AU1200 139config SOC_AU1200
125 bool 140 bool
126 select SOC_AU1X00 141 select SOC_AU1X00
142 select ALCHEMY_GPIO_AU1000
127 143
128config SOC_AU1X00 144config SOC_AU1X00
129 bool 145 bool
@@ -134,4 +150,5 @@ config SOC_AU1X00
134 select SYS_HAS_CPU_MIPS32_R1 150 select SYS_HAS_CPU_MIPS32_R1
135 select SYS_SUPPORTS_32BIT_KERNEL 151 select SYS_SUPPORTS_32BIT_KERNEL
136 select SYS_SUPPORTS_APM_EMULATION 152 select SYS_SUPPORTS_APM_EMULATION
137 select ARCH_REQUIRE_GPIOLIB 153 select GENERIC_GPIO
154 select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index d50d4764eafe..b67fb512529d 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -7,7 +7,14 @@
7 7
8obj-y += prom.o irq.o puts.o time.o reset.o \ 8obj-y += prom.o irq.o puts.o time.o reset.o \
9 clocks.o platform.o power.o setup.o \ 9 clocks.o platform.o power.o setup.o \
10 sleeper.o dma.o dbdma.o gpio.o 10 sleeper.o dma.o dbdma.o
11
12# optional gpiolib support
13ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
14 ifeq ($(CONFIG_GPIOLIB),y)
15 obj-$(CONFIG_ALCHEMY_GPIO_AU1000) += gpiolib-au1000.o
16 endif
17endif
11 18
12obj-$(CONFIG_PCI) += pci.o 19obj-$(CONFIG_PCI) += pci.o
13 20
diff --git a/arch/mips/alchemy/common/gpio.c b/arch/mips/alchemy/common/gpio.c
deleted file mode 100644
index 91a9c4436c39..000000000000
--- a/arch/mips/alchemy/common/gpio.c
+++ /dev/null
@@ -1,201 +0,0 @@
1/*
2 * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
3 * Architecture specific GPIO support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 * Notes :
26 * au1000 SoC have only one GPIO line : GPIO1
27 * others have a second one : GPIO2
28 */
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/platform_device.h>
34#include <linux/gpio.h>
35
36#include <asm/mach-au1x00/au1000.h>
37#include <asm/gpio.h>
38
39struct au1000_gpio_chip {
40 struct gpio_chip chip;
41 void __iomem *regbase;
42};
43
44#if !defined(CONFIG_SOC_AU1000)
45static int au1000_gpio2_get(struct gpio_chip *chip, unsigned offset)
46{
47 u32 mask = 1 << offset;
48 struct au1000_gpio_chip *gpch;
49
50 gpch = container_of(chip, struct au1000_gpio_chip, chip);
51 return readl(gpch->regbase + AU1000_GPIO2_ST) & mask;
52}
53
54static void au1000_gpio2_set(struct gpio_chip *chip,
55 unsigned offset, int value)
56{
57 u32 mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset));
58 struct au1000_gpio_chip *gpch;
59 unsigned long flags;
60
61 gpch = container_of(chip, struct au1000_gpio_chip, chip);
62
63 local_irq_save(flags);
64 writel(mask, gpch->regbase + AU1000_GPIO2_OUT);
65 local_irq_restore(flags);
66}
67
68static int au1000_gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
69{
70 u32 mask = 1 << offset;
71 u32 tmp;
72 struct au1000_gpio_chip *gpch;
73 unsigned long flags;
74
75 gpch = container_of(chip, struct au1000_gpio_chip, chip);
76
77 local_irq_save(flags);
78 tmp = readl(gpch->regbase + AU1000_GPIO2_DIR);
79 tmp &= ~mask;
80 writel(tmp, gpch->regbase + AU1000_GPIO2_DIR);
81 local_irq_restore(flags);
82
83 return 0;
84}
85
86static int au1000_gpio2_direction_output(struct gpio_chip *chip,
87 unsigned offset, int value)
88{
89 u32 mask = 1 << offset;
90 u32 out_mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset));
91 u32 tmp;
92 struct au1000_gpio_chip *gpch;
93 unsigned long flags;
94
95 gpch = container_of(chip, struct au1000_gpio_chip, chip);
96
97 local_irq_save(flags);
98 tmp = readl(gpch->regbase + AU1000_GPIO2_DIR);
99 tmp |= mask;
100 writel(tmp, gpch->regbase + AU1000_GPIO2_DIR);
101 writel(out_mask, gpch->regbase + AU1000_GPIO2_OUT);
102 local_irq_restore(flags);
103
104 return 0;
105}
106#endif /* !defined(CONFIG_SOC_AU1000) */
107
108static int au1000_gpio1_get(struct gpio_chip *chip, unsigned offset)
109{
110 u32 mask = 1 << offset;
111 struct au1000_gpio_chip *gpch;
112
113 gpch = container_of(chip, struct au1000_gpio_chip, chip);
114 return readl(gpch->regbase + AU1000_GPIO1_ST) & mask;
115}
116
117static void au1000_gpio1_set(struct gpio_chip *chip,
118 unsigned offset, int value)
119{
120 u32 mask = 1 << offset;
121 u32 reg_offset;
122 struct au1000_gpio_chip *gpch;
123 unsigned long flags;
124
125 gpch = container_of(chip, struct au1000_gpio_chip, chip);
126
127 if (value)
128 reg_offset = AU1000_GPIO1_OUT;
129 else
130 reg_offset = AU1000_GPIO1_CLR;
131
132 local_irq_save(flags);
133 writel(mask, gpch->regbase + reg_offset);
134 local_irq_restore(flags);
135}
136
137static int au1000_gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
138{
139 u32 mask = 1 << offset;
140 struct au1000_gpio_chip *gpch;
141
142 gpch = container_of(chip, struct au1000_gpio_chip, chip);
143 writel(mask, gpch->regbase + AU1000_GPIO1_ST);
144
145 return 0;
146}
147
148static int au1000_gpio1_direction_output(struct gpio_chip *chip,
149 unsigned offset, int value)
150{
151 u32 mask = 1 << offset;
152 struct au1000_gpio_chip *gpch;
153
154 gpch = container_of(chip, struct au1000_gpio_chip, chip);
155
156 writel(mask, gpch->regbase + AU1000_GPIO1_TRI_OUT);
157 au1000_gpio1_set(chip, offset, value);
158
159 return 0;
160}
161
162struct au1000_gpio_chip au1000_gpio_chip[] = {
163 [0] = {
164 .regbase = (void __iomem *)SYS_BASE,
165 .chip = {
166 .label = "au1000-gpio1",
167 .direction_input = au1000_gpio1_direction_input,
168 .direction_output = au1000_gpio1_direction_output,
169 .get = au1000_gpio1_get,
170 .set = au1000_gpio1_set,
171 .base = 0,
172 .ngpio = 32,
173 },
174 },
175#if !defined(CONFIG_SOC_AU1000)
176 [1] = {
177 .regbase = (void __iomem *)GPIO2_BASE,
178 .chip = {
179 .label = "au1000-gpio2",
180 .direction_input = au1000_gpio2_direction_input,
181 .direction_output = au1000_gpio2_direction_output,
182 .get = au1000_gpio2_get,
183 .set = au1000_gpio2_set,
184 .base = AU1XXX_GPIO_BASE,
185 .ngpio = 32,
186 },
187 },
188#endif
189};
190
191static int __init au1000_gpio_init(void)
192{
193 gpiochip_add(&au1000_gpio_chip[0].chip);
194#if !defined(CONFIG_SOC_AU1000)
195 gpiochip_add(&au1000_gpio_chip[1].chip);
196#endif
197
198 return 0;
199}
200arch_initcall(au1000_gpio_init);
201
diff --git a/arch/mips/alchemy/common/gpiolib-au1000.c b/arch/mips/alchemy/common/gpiolib-au1000.c
new file mode 100644
index 000000000000..1bfa91f939f4
--- /dev/null
+++ b/arch/mips/alchemy/common/gpiolib-au1000.c
@@ -0,0 +1,130 @@
1/*
2 * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
3 * GPIOLIB support for Au1000, Au1500, Au1100, Au1550 and Au12x0.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 * Notes :
26 * au1000 SoC have only one GPIO block : GPIO1
27 * Au1100, Au15x0, Au12x0 have a second one : GPIO2
28 */
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/platform_device.h>
34#include <linux/gpio.h>
35
36#include <asm/mach-au1x00/au1000.h>
37#include <asm/mach-au1x00/gpio.h>
38
39#if !defined(CONFIG_SOC_AU1000)
40static int gpio2_get(struct gpio_chip *chip, unsigned offset)
41{
42 return alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE);
43}
44
45static void gpio2_set(struct gpio_chip *chip, unsigned offset, int value)
46{
47 alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value);
48}
49
50static int gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
51{
52 return alchemy_gpio2_direction_input(offset + ALCHEMY_GPIO2_BASE);
53}
54
55static int gpio2_direction_output(struct gpio_chip *chip, unsigned offset,
56 int value)
57{
58 return alchemy_gpio2_direction_output(offset + ALCHEMY_GPIO2_BASE,
59 value);
60}
61
62static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset)
63{
64 return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE);
65}
66#endif /* !defined(CONFIG_SOC_AU1000) */
67
68static int gpio1_get(struct gpio_chip *chip, unsigned offset)
69{
70 return alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE);
71}
72
73static void gpio1_set(struct gpio_chip *chip,
74 unsigned offset, int value)
75{
76 alchemy_gpio1_set_value(offset + ALCHEMY_GPIO1_BASE, value);
77}
78
79static int gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
80{
81 return alchemy_gpio1_direction_input(offset + ALCHEMY_GPIO1_BASE);
82}
83
84static int gpio1_direction_output(struct gpio_chip *chip,
85 unsigned offset, int value)
86{
87 return alchemy_gpio1_direction_output(offset + ALCHEMY_GPIO1_BASE,
88 value);
89}
90
91static int gpio1_to_irq(struct gpio_chip *chip, unsigned offset)
92{
93 return alchemy_gpio1_to_irq(offset + ALCHEMY_GPIO1_BASE);
94}
95
96struct gpio_chip alchemy_gpio_chip[] = {
97 [0] = {
98 .label = "alchemy-gpio1",
99 .direction_input = gpio1_direction_input,
100 .direction_output = gpio1_direction_output,
101 .get = gpio1_get,
102 .set = gpio1_set,
103 .to_irq = gpio1_to_irq,
104 .base = ALCHEMY_GPIO1_BASE,
105 .ngpio = ALCHEMY_GPIO1_NUM,
106 },
107#if !defined(CONFIG_SOC_AU1000)
108 [1] = {
109 .label = "alchemy-gpio2",
110 .direction_input = gpio2_direction_input,
111 .direction_output = gpio2_direction_output,
112 .get = gpio2_get,
113 .set = gpio2_set,
114 .to_irq = gpio2_to_irq,
115 .base = ALCHEMY_GPIO2_BASE,
116 .ngpio = ALCHEMY_GPIO2_NUM,
117 },
118#endif
119};
120
121static int __init alchemy_gpiolib_init(void)
122{
123 gpiochip_add(&alchemy_gpio_chip[0]);
124#if !defined(CONFIG_SOC_AU1000)
125 gpiochip_add(&alchemy_gpio_chip[1]);
126#endif
127
128 return 0;
129}
130arch_initcall(alchemy_gpiolib_init);
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
new file mode 100644
index 000000000000..127d4ed9f073
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
@@ -0,0 +1,604 @@
1/*
2 * GPIO functions for Au1000, Au1500, Au1100, Au1550, Au1200
3 *
4 * Copyright (c) 2009 Manuel Lauss.
5 *
6 * Licensed under the terms outlined in the file COPYING.
7 */
8
9#ifndef _ALCHEMY_GPIO_AU1000_H_
10#define _ALCHEMY_GPIO_AU1000_H_
11
12#include <asm/mach-au1x00/au1000.h>
13
14/* The default GPIO numberspace as documented in the Alchemy manuals.
15 * GPIO0-31 from GPIO1 block, GPIO200-215 from GPIO2 block.
16 */
17#define ALCHEMY_GPIO1_BASE 0
18#define ALCHEMY_GPIO2_BASE 200
19
20#define ALCHEMY_GPIO1_NUM 32
21#define ALCHEMY_GPIO2_NUM 16
22#define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
23#define ALCHEMY_GPIO2_MAX (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
24
25#define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off))
26
27
28static inline int au1000_gpio1_to_irq(int gpio)
29{
30 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
31}
32
33static inline int au1000_gpio2_to_irq(int gpio)
34{
35 return -ENXIO;
36}
37
38#ifdef CONFIG_SOC_AU1000
39static inline int au1000_irq_to_gpio(int irq)
40{
41 if ((irq >= AU1000_GPIO_0) && (irq <= AU1000_GPIO_31))
42 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
43
44 return -ENXIO;
45}
46#endif
47
48static inline int au1500_gpio1_to_irq(int gpio)
49{
50 gpio -= ALCHEMY_GPIO1_BASE;
51
52 switch (gpio) {
53 case 0 ... 15:
54 case 20:
55 case 23 ... 28: return MAKE_IRQ(1, gpio);
56 }
57
58 return -ENXIO;
59}
60
61static inline int au1500_gpio2_to_irq(int gpio)
62{
63 gpio -= ALCHEMY_GPIO2_BASE;
64
65 switch (gpio) {
66 case 0 ... 3: return MAKE_IRQ(1, 16 + gpio - 0);
67 case 4 ... 5: return MAKE_IRQ(1, 21 + gpio - 4);
68 case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6);
69 }
70
71 return -ENXIO;
72}
73
74#ifdef CONFIG_SOC_AU1500
75static inline int au1500_irq_to_gpio(int irq)
76{
77 switch (irq) {
78 case AU1000_GPIO_0 ... AU1000_GPIO_15:
79 case AU1500_GPIO_20:
80 case AU1500_GPIO_23 ... AU1500_GPIO_28:
81 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
82 case AU1500_GPIO_200 ... AU1500_GPIO_203:
83 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_200) + 0;
84 case AU1500_GPIO_204 ... AU1500_GPIO_205:
85 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_204) + 4;
86 case AU1500_GPIO_206 ... AU1500_GPIO_207:
87 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6;
88 case AU1500_GPIO_208_215:
89 return ALCHEMY_GPIO2_BASE + 8;
90 }
91
92 return -ENXIO;
93}
94#endif
95
96static inline int au1100_gpio1_to_irq(int gpio)
97{
98 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
99}
100
101static inline int au1100_gpio2_to_irq(int gpio)
102{
103 gpio -= ALCHEMY_GPIO2_BASE;
104
105 if ((gpio >= 8) && (gpio <= 15))
106 return MAKE_IRQ(0, 29); /* shared GPIO208_215 */
107}
108
109#ifdef CONFIG_SOC_AU1100
110static inline int au1100_irq_to_gpio(int irq)
111{
112 switch (irq) {
113 case AU1000_GPIO_0 ... AU1000_GPIO_31:
114 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
115 case AU1100_GPIO_208_215:
116 return ALCHEMY_GPIO2_BASE + 8;
117 }
118
119 return -ENXIO;
120}
121#endif
122
123static inline int au1550_gpio1_to_irq(int gpio)
124{
125 gpio -= ALCHEMY_GPIO1_BASE;
126
127 switch (gpio) {
128 case 0 ... 15:
129 case 20 ... 28: return MAKE_IRQ(1, gpio);
130 case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16);
131 }
132
133 return -ENXIO;
134}
135
136static inline int au1550_gpio2_to_irq(int gpio)
137{
138 gpio -= ALCHEMY_GPIO2_BASE;
139
140 switch (gpio) {
141 case 0: return MAKE_IRQ(1, 16);
142 case 1 ... 5: return MAKE_IRQ(1, 17); /* shared GPIO201_205 */
143 case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6);
144 case 8 ... 15: return MAKE_IRQ(1, 31); /* shared GPIO208_215 */
145 }
146
147 return -ENXIO;
148}
149
150#ifdef CONFIG_SOC_AU1550
151static inline int au1550_irq_to_gpio(int irq)
152{
153 switch (irq) {
154 case AU1000_GPIO_0 ... AU1000_GPIO_15:
155 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
156 case AU1550_GPIO_200:
157 case AU1500_GPIO_201_205:
158 return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO_200) + 0;
159 case AU1500_GPIO_16 ... AU1500_GPIO_28:
160 return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO_16) + 16;
161 case AU1500_GPIO_206 ... AU1500_GPIO_208_218:
162 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6;
163 }
164
165 return -ENXIO;
166}
167#endif
168
169static inline int au1200_gpio1_to_irq(int gpio)
170{
171 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
172}
173
174static inline int au1200_gpio2_to_irq(int gpio)
175{
176 gpio -= ALCHEMY_GPIO2_BASE;
177
178 switch (gpio) {
179 case 0 ... 2: return MAKE_IRQ(0, 5 + gpio - 0);
180 case 3: return MAKE_IRQ(0, 22);
181 case 4 ... 7: return MAKE_IRQ(0, 24 + gpio - 4);
182 case 8 ... 15: return MAKE_IRQ(0, 28); /* shared GPIO208_215 */
183 }
184
185 return -ENXIO;
186}
187
188#ifdef CONFIG_SOC_AU1200
189static inline int au1200_irq_to_gpio(int irq)
190{
191 switch (irq) {
192 case AU1000_GPIO_0 ... AU1000_GPIO_31:
193 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
194 case AU1200_GPIO_200 ... AU1200_GPIO_202:
195 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_200) + 0;
196 case AU1200_GPIO_203:
197 return ALCHEMY_GPIO2_BASE + 3;
198 case AU1200_GPIO_204 ... AU1200_GPIO_208_215:
199 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_204) + 4;
200 }
201
202 return -ENXIO;
203}
204#endif
205
206/*
207 * GPIO1 block macros for common linux gpio functions.
208 */
209static inline void alchemy_gpio1_set_value(int gpio, int v)
210{
211 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
212 unsigned long r = v ? SYS_OUTPUTSET : SYS_OUTPUTCLR;
213 au_writel(mask, r);
214 au_sync();
215}
216
217static inline int alchemy_gpio1_get_value(int gpio)
218{
219 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
220 return au_readl(SYS_PINSTATERD) & mask;
221}
222
223static inline int alchemy_gpio1_direction_input(int gpio)
224{
225 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
226 au_writel(mask, SYS_TRIOUTCLR);
227 au_sync();
228 return 0;
229}
230
231static inline int alchemy_gpio1_direction_output(int gpio, int v)
232{
233 /* hardware switches to "output" mode when one of the two
234 * "set_value" registers is accessed.
235 */
236 alchemy_gpio1_set_value(gpio, v);
237 return 0;
238}
239
240static inline int alchemy_gpio1_is_valid(int gpio)
241{
242 return ((gpio >= ALCHEMY_GPIO1_BASE) && (gpio <= ALCHEMY_GPIO1_MAX));
243}
244
245static inline int alchemy_gpio1_to_irq(int gpio)
246{
247#if defined(CONFIG_SOC_AU1000)
248 return au1000_gpio1_to_irq(gpio);
249#elif defined(CONFIG_SOC_AU1100)
250 return au1100_gpio1_to_irq(gpio);
251#elif defined(CONFIG_SOC_AU1500)
252 return au1500_gpio1_to_irq(gpio);
253#elif defined(CONFIG_SOC_AU1550)
254 return au1550_gpio1_to_irq(gpio);
255#elif defined(CONFIG_SOC_AU1200)
256 return au1200_gpio1_to_irq(gpio);
257#else
258 return -ENXIO;
259#endif
260}
261
262/*
263 * GPIO2 block macros for common linux GPIO functions. The 'gpio'
264 * parameter must be in range of ALCHEMY_GPIO2_BASE..ALCHEMY_GPIO2_MAX.
265 */
266static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out)
267{
268 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE);
269 unsigned long d = au_readl(GPIO2_DIR);
270 if (to_out)
271 d |= mask;
272 else
273 d &= ~mask;
274 au_writel(d, GPIO2_DIR);
275 au_sync();
276}
277
278static inline void alchemy_gpio2_set_value(int gpio, int v)
279{
280 unsigned long mask;
281 mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);
282 au_writel(mask, GPIO2_OUTPUT);
283 au_sync();
284}
285
286static inline int alchemy_gpio2_get_value(int gpio)
287{
288 return au_readl(GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE));
289}
290
291static inline int alchemy_gpio2_direction_input(int gpio)
292{
293 unsigned long flags;
294 local_irq_save(flags);
295 __alchemy_gpio2_mod_dir(gpio, 0);
296 local_irq_restore(flags);
297 return 0;
298}
299
300static inline int alchemy_gpio2_direction_output(int gpio, int v)
301{
302 unsigned long flags;
303 alchemy_gpio2_set_value(gpio, v);
304 local_irq_save(flags);
305 __alchemy_gpio2_mod_dir(gpio, 1);
306 local_irq_restore(flags);
307 return 0;
308}
309
310static inline int alchemy_gpio2_is_valid(int gpio)
311{
312 return ((gpio >= ALCHEMY_GPIO2_BASE) && (gpio <= ALCHEMY_GPIO2_MAX));
313}
314
315static inline int alchemy_gpio2_to_irq(int gpio)
316{
317#if defined(CONFIG_SOC_AU1000)
318 return au1000_gpio2_to_irq(gpio);
319#elif defined(CONFIG_SOC_AU1100)
320 return au1100_gpio2_to_irq(gpio);
321#elif defined(CONFIG_SOC_AU1500)
322 return au1500_gpio2_to_irq(gpio);
323#elif defined(CONFIG_SOC_AU1550)
324 return au1550_gpio2_to_irq(gpio);
325#elif defined(CONFIG_SOC_AU1200)
326 return au1200_gpio2_to_irq(gpio);
327#else
328 return -ENXIO;
329#endif
330}
331
332/**********************************************************************/
333
334/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
335 * SYS_PININPUTEN is written to at least once. On Au1550/Au1200 this
336 * register enables use of GPIOs as wake source.
337 */
338static inline void alchemy_gpio1_input_enable(void)
339{
340 au_writel(0, SYS_PININPUTEN); /* the write op is key */
341 au_sync();
342}
343
344/* GPIO2 shared interrupts and control */
345
346static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
347{
348 unsigned long r = au_readl(GPIO2_INTENABLE);
349 if (en)
350 r |= 1 << gpio2;
351 else
352 r &= ~(1 << gpio2);
353 au_writel(r, GPIO2_INTENABLE);
354 au_sync();
355}
356
357/**
358 * alchemy_gpio2_enable_int - Enable a GPIO2 pins' shared irq contribution.
359 * @gpio2: The GPIO2 pin to activate (200...215).
360 *
361 * GPIO208-215 have one shared interrupt line to the INTC. They are
362 * and'ed with a per-pin enable bit and finally or'ed together to form
363 * a single irq request (useful for active-high sources).
364 * With this function, a pins' individual contribution to the int request
365 * can be enabled. As with all other GPIO-based interrupts, the INTC
366 * must be programmed to accept the GPIO208_215 interrupt as well.
367 *
368 * NOTE: Calling this macro is only necessary for GPIO208-215; all other
369 * GPIO2-based interrupts have their own request to the INTC. Please
370 * consult your Alchemy databook for more information!
371 *
372 * NOTE: On the Au1550, GPIOs 201-205 also have a shared interrupt request
373 * line to the INTC, GPIO201_205. This function can be used for those
374 * as well.
375 *
376 * NOTE: 'gpio2' parameter must be in range of the GPIO2 numberspace
377 * (200-215 by default). No sanity checks are made,
378 */
379static inline void alchemy_gpio2_enable_int(int gpio2)
380{
381 unsigned long flags;
382
383 gpio2 -= ALCHEMY_GPIO2_BASE;
384
385#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
386 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
387 gpio2 -= 8;
388#endif
389 local_irq_save(flags);
390 __alchemy_gpio2_mod_int(gpio2, 1);
391 local_irq_restore(flags);
392}
393
394/**
395 * alchemy_gpio2_disable_int - Disable a GPIO2 pins' shared irq contribution.
396 * @gpio2: The GPIO2 pin to activate (200...215).
397 *
398 * see function alchemy_gpio2_enable_int() for more information.
399 */
400static inline void alchemy_gpio2_disable_int(int gpio2)
401{
402 unsigned long flags;
403
404 gpio2 -= ALCHEMY_GPIO2_BASE;
405
406#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
407 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
408 gpio2 -= 8;
409#endif
410 local_irq_save(flags);
411 __alchemy_gpio2_mod_int(gpio2, 0);
412 local_irq_restore(flags);
413}
414
415/**
416 * alchemy_gpio2_enable - Activate GPIO2 block.
417 *
418 * The GPIO2 block must be enabled excplicitly to work. On systems
419 * where this isn't done by the bootloader, this macro can be used.
420 */
421static inline void alchemy_gpio2_enable(void)
422{
423 au_writel(3, GPIO2_ENABLE); /* reset, clock enabled */
424 au_sync();
425 au_writel(1, GPIO2_ENABLE); /* clock enabled */
426 au_sync();
427}
428
429/**
430 * alchemy_gpio2_disable - disable GPIO2 block.
431 *
432 * Disable and put GPIO2 block in low-power mode.
433 */
434static inline void alchemy_gpio2_disable(void)
435{
436 au_writel(2, GPIO2_ENABLE); /* reset, clock disabled */
437 au_sync();
438}
439
440/**********************************************************************/
441
442/* wrappers for on-chip gpios; can be used before gpio chips have been
443 * registered with gpiolib.
444 */
445static inline int alchemy_gpio_direction_input(int gpio)
446{
447 return (gpio >= ALCHEMY_GPIO2_BASE) ?
448 alchemy_gpio2_direction_input(gpio) :
449 alchemy_gpio1_direction_input(gpio);
450}
451
452static inline int alchemy_gpio_direction_output(int gpio, int v)
453{
454 return (gpio >= ALCHEMY_GPIO2_BASE) ?
455 alchemy_gpio2_direction_output(gpio, v) :
456 alchemy_gpio1_direction_output(gpio, v);
457}
458
459static inline int alchemy_gpio_get_value(int gpio)
460{
461 return (gpio >= ALCHEMY_GPIO2_BASE) ?
462 alchemy_gpio2_get_value(gpio) :
463 alchemy_gpio1_get_value(gpio);
464}
465
466static inline void alchemy_gpio_set_value(int gpio, int v)
467{
468 if (gpio >= ALCHEMY_GPIO2_BASE)
469 alchemy_gpio2_set_value(gpio, v);
470 else
471 alchemy_gpio1_set_value(gpio, v);
472}
473
474static inline int alchemy_gpio_is_valid(int gpio)
475{
476 return (gpio >= ALCHEMY_GPIO2_BASE) ?
477 alchemy_gpio2_is_valid(gpio) :
478 alchemy_gpio1_is_valid(gpio);
479}
480
481static inline int alchemy_gpio_cansleep(int gpio)
482{
483 return 0; /* Alchemy never gets tired */
484}
485
486static inline int alchemy_gpio_to_irq(int gpio)
487{
488 return (gpio >= ALCHEMY_GPIO2_BASE) ?
489 alchemy_gpio2_to_irq(gpio) :
490 alchemy_gpio1_to_irq(gpio);
491}
492
493static inline int alchemy_irq_to_gpio(int irq)
494{
495#if defined(CONFIG_SOC_AU1000)
496 return au1000_irq_to_gpio(irq);
497#elif defined(CONFIG_SOC_AU1100)
498 return au1100_irq_to_gpio(irq);
499#elif defined(CONFIG_SOC_AU1500)
500 return au1500_irq_to_gpio(irq);
501#elif defined(CONFIG_SOC_AU1550)
502 return au1550_irq_to_gpio(irq);
503#elif defined(CONFIG_SOC_AU1200)
504 return au1200_irq_to_gpio(irq);
505#else
506 return -ENXIO;
507#endif
508}
509
510/**********************************************************************/
511
512/* Linux gpio framework integration.
513 *
514 * 4 use cases of Au1000-Au1200 GPIOS:
515 *(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
516 * Board must register gpiochips.
517 *(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
518 * 2 (1 for Au1000) gpio_chips are registered.
519 *
520 *(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
521 * the boards' gpio.h must provide the linux gpio wrapper functions,
522 *
523 *(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
524 * inlinable gpio functions are provided which enable access to the
525 * Au1000 gpios only by using the numbers straight out of the data-
526 * sheets.
527
528 * Cases 1 and 3 are intended for boards which want to provide their own
529 * GPIO namespace and -operations (i.e. for example you have 8 GPIOs
530 * which are in part provided by spare Au1000 GPIO pins and in part by
531 * an external FPGA but you still want them to be accssible in linux
532 * as gpio0-7. The board can of course use the alchemy_gpioX_* functions
533 * as required).
534 */
535
536#ifndef CONFIG_GPIOLIB
537
538
539#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */
540
541static inline int gpio_direction_input(int gpio)
542{
543 return alchemy_gpio_direction_input(gpio);
544}
545
546static inline int gpio_direction_output(int gpio, int v)
547{
548 return alchemy_gpio_direction_output(gpio, v);
549}
550
551static inline int gpio_get_value(int gpio)
552{
553 return alchemy_gpio_get_value(gpio);
554}
555
556static inline void gpio_set_value(int gpio, int v)
557{
558 alchemy_gpio_set_value(gpio, v);
559}
560
561static inline int gpio_is_valid(int gpio)
562{
563 return alchemy_gpio_is_valid(gpio);
564}
565
566static inline int gpio_cansleep(int gpio)
567{
568 return alchemy_gpio_cansleep(gpio);
569}
570
571static inline int gpio_to_irq(int gpio)
572{
573 return alchemy_gpio_to_irq(gpio);
574}
575
576static inline int irq_to_gpio(int irq)
577{
578 return alchemy_irq_to_gpio(irq);
579}
580
581#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
582
583
584#else /* CONFIG GPIOLIB */
585
586
587 /* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */
588#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */
589
590/* get everything through gpiolib */
591#define gpio_to_irq __gpio_to_irq
592#define gpio_get_value __gpio_get_value
593#define gpio_set_value __gpio_set_value
594#define gpio_cansleep __gpio_cansleep
595#define irq_to_gpio alchemy_irq_to_gpio
596
597#include <asm-generic/gpio.h>
598
599#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
600
601
602#endif /* !CONFIG_GPIOLIB */
603
604#endif /* _ALCHEMY_GPIO_AU1000_H_ */
diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h
index 34d9b7279024..f9b7d41c659a 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio.h
@@ -1,33 +1,10 @@
1#ifndef _AU1XXX_GPIO_H_ 1#ifndef _ALCHEMY_GPIO_H_
2#define _AU1XXX_GPIO_H_ 2#define _ALCHEMY_GPIO_H_
3 3
4#include <linux/types.h> 4#if defined(CONFIG_ALCHEMY_GPIO_AU1000)
5 5
6#define AU1XXX_GPIO_BASE 200 6#include <asm/mach-au1x00/gpio-au1000.h>
7 7
8/* GPIO bank 1 offsets */ 8#endif
9#define AU1000_GPIO1_TRI_OUT 0x0100
10#define AU1000_GPIO1_OUT 0x0108
11#define AU1000_GPIO1_ST 0x0110
12#define AU1000_GPIO1_CLR 0x010C
13 9
14/* GPIO bank 2 offsets */ 10#endif /* _ALCHEMY_GPIO_H_ */
15#define AU1000_GPIO2_DIR 0x00
16#define AU1000_GPIO2_RSVD 0x04
17#define AU1000_GPIO2_OUT 0x08
18#define AU1000_GPIO2_ST 0x0C
19#define AU1000_GPIO2_INT 0x10
20#define AU1000_GPIO2_EN 0x14
21
22#define GPIO2_OUT_EN_MASK 0x00010000
23
24#define gpio_to_irq(gpio) NULL
25
26#define gpio_get_value __gpio_get_value
27#define gpio_set_value __gpio_set_value
28
29#define gpio_cansleep __gpio_cansleep
30
31#include <asm-generic/gpio.h>
32
33#endif /* _AU1XXX_GPIO_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 14:15:03 -0500