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-rw-r--r--arch/alpha/include/asm/atomic.h4
-rw-r--r--arch/arm/include/asm/atomic.h2
-rw-r--r--arch/arm/include/asm/cacheflush.h4
-rw-r--r--arch/arm/include/asm/smp_twd.h17
-rw-r--r--arch/arm/include/asm/tlbflush.h29
-rw-r--r--arch/arm/kernel/smp_twd.c17
-rw-r--r--arch/arm/lib/clear_user.S1
-rw-r--r--arch/arm/lib/copy_to_user.S1
-rw-r--r--arch/arm/mach-davinci/da830.c2
-rw-r--r--arch/arm/mm/cache-v6.S17
-rw-r--r--arch/arm/mm/cache-v7.S4
-rw-r--r--arch/arm/mm/nommu.c13
-rw-r--r--arch/arm/mm/tlb-v7.S8
-rw-r--r--arch/avr32/include/asm/atomic.h2
-rw-r--r--arch/cris/include/asm/atomic.h2
-rw-r--r--arch/frv/include/asm/atomic.h2
-rw-r--r--arch/h8300/include/asm/atomic.h2
-rw-r--r--arch/ia64/include/asm/atomic.h4
-rw-r--r--arch/m32r/include/asm/atomic.h2
-rw-r--r--arch/m68k/amiga/Makefile2
-rw-r--r--arch/m68k/amiga/platform.c83
-rw-r--r--arch/m68k/bvme6000/rtc.c29
-rw-r--r--arch/m68k/hp300/time.h4
-rw-r--r--arch/m68k/include/asm/atomic_mm.h2
-rw-r--r--arch/m68k/include/asm/atomic_no.h2
-rw-r--r--arch/m68k/include/asm/bitops_mm.h14
-rw-r--r--arch/m68k/include/asm/param.h16
-rw-r--r--arch/m68k/kernel/traps.c2
-rw-r--r--arch/m68k/mac/config.c10
-rw-r--r--arch/m68k/mm/fault.c14
-rw-r--r--arch/m68k/mvme16x/rtc.c19
-rw-r--r--arch/m68k/q40/config.c2
-rw-r--r--arch/microblaze/include/asm/uaccess.h87
-rw-r--r--arch/microblaze/kernel/cpu/cache.c3
-rw-r--r--arch/microblaze/kernel/entry-nommu.S2
-rw-r--r--arch/microblaze/kernel/microblaze_ksyms.c11
-rw-r--r--arch/microblaze/kernel/module.c2
-rw-r--r--arch/microblaze/mm/init.c1
-rw-r--r--arch/microblaze/mm/pgtable.c1
-rw-r--r--arch/microblaze/pci/pci-common.c2
-rw-r--r--arch/mips/include/asm/atomic.h4
-rw-r--r--arch/mips/include/asm/i8253.h2
-rw-r--r--arch/mips/include/asm/mipsregs.h9
-rw-r--r--arch/mips/kernel/i8253.c14
-rw-r--r--arch/mips/kernel/scall64-n32.S2
-rw-r--r--arch/mips/math-emu/cp1emu.c15
-rw-r--r--arch/mips/oprofile/op_model_loongson2.c2
-rw-r--r--arch/mn10300/include/asm/atomic.h2
-rw-r--r--arch/parisc/include/asm/atomic.h4
-rw-r--r--arch/powerpc/include/asm/hw_irq.h38
-rw-r--r--arch/powerpc/kernel/asm-offsets.c1
-rw-r--r--arch/powerpc/kernel/dma-swiotlb.c5
-rw-r--r--arch/powerpc/kernel/entry_64.S9
-rw-r--r--arch/powerpc/kernel/irq.c6
-rw-r--r--arch/powerpc/kernel/time.c60
-rw-r--r--arch/powerpc/kvm/44x_tlb.c2
-rw-r--r--arch/s390/kernel/head31.S2
-rw-r--r--arch/s390/kernel/head64.S2
-rw-r--r--arch/s390/kernel/ptrace.c5
-rw-r--r--arch/sh/include/asm/atomic.h2
-rw-r--r--arch/sparc/include/asm/atomic_32.h2
-rw-r--r--arch/sparc/include/asm/atomic_64.h4
-rw-r--r--arch/x86/include/asm/amd_iommu_types.h34
-rw-r--r--arch/x86/include/asm/atomic.h2
-rw-r--r--arch/x86/include/asm/atomic64_64.h2
-rw-r--r--arch/x86/include/asm/i8253.h2
-rw-r--r--arch/x86/include/asm/k8.h5
-rw-r--r--arch/x86/kernel/amd_iommu.c197
-rw-r--r--arch/x86/kernel/amd_iommu_init.c6
-rw-r--r--arch/x86/kernel/apm_32.c4
-rw-r--r--arch/x86/kernel/cpu/intel_cacheinfo.c4
-rw-r--r--arch/x86/kernel/i8253.c14
-rw-r--r--arch/x86/kernel/kprobes.c27
-rw-r--r--arch/x86/kernel/process.c12
-rw-r--r--arch/x86/kvm/svm.c8
-rw-r--r--arch/x86/kvm/vmx.c3
-rw-r--r--arch/x86/kvm/x86.c4
-rw-r--r--arch/x86/mm/srat_64.c3
-rw-r--r--arch/x86/pci/mrst.c4
-rw-r--r--arch/xtensa/include/asm/atomic.h2
80 files changed, 625 insertions, 341 deletions
diff --git a/arch/alpha/include/asm/atomic.h b/arch/alpha/include/asm/atomic.h
index 610dff44d94b..e756d04b6cd5 100644
--- a/arch/alpha/include/asm/atomic.h
+++ b/arch/alpha/include/asm/atomic.h
@@ -17,8 +17,8 @@
17#define ATOMIC_INIT(i) ( (atomic_t) { (i) } ) 17#define ATOMIC_INIT(i) ( (atomic_t) { (i) } )
18#define ATOMIC64_INIT(i) ( (atomic64_t) { (i) } ) 18#define ATOMIC64_INIT(i) ( (atomic64_t) { (i) } )
19 19
20#define atomic_read(v) ((v)->counter + 0) 20#define atomic_read(v) (*(volatile int *)&(v)->counter)
21#define atomic64_read(v) ((v)->counter + 0) 21#define atomic64_read(v) (*(volatile long *)&(v)->counter)
22 22
23#define atomic_set(v,i) ((v)->counter = (i)) 23#define atomic_set(v,i) ((v)->counter = (i))
24#define atomic64_set(v,i) ((v)->counter = (i)) 24#define atomic64_set(v,i) ((v)->counter = (i))
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index e8ddec2cb158..a0162fa94564 100644
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -24,7 +24,7 @@
24 * strex/ldrex monitor on some implementations. The reason we can use it for 24 * strex/ldrex monitor on some implementations. The reason we can use it for
25 * atomic_set() is the clrex or dummy strex done on every exception return. 25 * atomic_set() is the clrex or dummy strex done on every exception return.
26 */ 26 */
27#define atomic_read(v) ((v)->counter) 27#define atomic_read(v) (*(volatile int *)&(v)->counter)
28#define atomic_set(v,i) (((v)->counter) = (i)) 28#define atomic_set(v,i) (((v)->counter) = (i))
29 29
30#if __LINUX_ARM_ARCH__ >= 6 30#if __LINUX_ARM_ARCH__ >= 6
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 0d08d4170b64..4656a24058d2 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -371,6 +371,10 @@ static inline void __flush_icache_all(void)
371#ifdef CONFIG_ARM_ERRATA_411920 371#ifdef CONFIG_ARM_ERRATA_411920
372 extern void v6_icache_inval_all(void); 372 extern void v6_icache_inval_all(void);
373 v6_icache_inval_all(); 373 v6_icache_inval_all();
374#elif defined(CONFIG_SMP) && __LINUX_ARM_ARCH__ >= 7
375 asm("mcr p15, 0, %0, c7, c1, 0 @ invalidate I-cache inner shareable\n"
376 :
377 : "r" (0));
374#else 378#else
375 asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n" 379 asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n"
376 : 380 :
diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h
index 7be0978b2625..634f357be6bb 100644
--- a/arch/arm/include/asm/smp_twd.h
+++ b/arch/arm/include/asm/smp_twd.h
@@ -1,6 +1,23 @@
1#ifndef __ASMARM_SMP_TWD_H 1#ifndef __ASMARM_SMP_TWD_H
2#define __ASMARM_SMP_TWD_H 2#define __ASMARM_SMP_TWD_H
3 3
4#define TWD_TIMER_LOAD 0x00
5#define TWD_TIMER_COUNTER 0x04
6#define TWD_TIMER_CONTROL 0x08
7#define TWD_TIMER_INTSTAT 0x0C
8
9#define TWD_WDOG_LOAD 0x20
10#define TWD_WDOG_COUNTER 0x24
11#define TWD_WDOG_CONTROL 0x28
12#define TWD_WDOG_INTSTAT 0x2C
13#define TWD_WDOG_RESETSTAT 0x30
14#define TWD_WDOG_DISABLE 0x34
15
16#define TWD_TIMER_CONTROL_ENABLE (1 << 0)
17#define TWD_TIMER_CONTROL_ONESHOT (0 << 1)
18#define TWD_TIMER_CONTROL_PERIODIC (1 << 1)
19#define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2)
20
4struct clock_event_device; 21struct clock_event_device;
5 22
6extern void __iomem *twd_base; 23extern void __iomem *twd_base;
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index e085e2c545eb..bd863d8608cd 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -46,6 +46,9 @@
46#define TLB_V7_UIS_FULL (1 << 20) 46#define TLB_V7_UIS_FULL (1 << 20)
47#define TLB_V7_UIS_ASID (1 << 21) 47#define TLB_V7_UIS_ASID (1 << 21)
48 48
49/* Inner Shareable BTB operation (ARMv7 MP extensions) */
50#define TLB_V7_IS_BTB (1 << 22)
51
49#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */ 52#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */
50#define TLB_DCLEAN (1 << 30) 53#define TLB_DCLEAN (1 << 30)
51#define TLB_WB (1 << 31) 54#define TLB_WB (1 << 31)
@@ -183,7 +186,7 @@
183#endif 186#endif
184 187
185#ifdef CONFIG_SMP 188#ifdef CONFIG_SMP
186#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \ 189#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
187 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID) 190 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
188#else 191#else
189#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \ 192#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
@@ -339,6 +342,12 @@ static inline void local_flush_tlb_all(void)
339 dsb(); 342 dsb();
340 isb(); 343 isb();
341 } 344 }
345 if (tlb_flag(TLB_V7_IS_BTB)) {
346 /* flush the branch target cache */
347 asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");
348 dsb();
349 isb();
350 }
342} 351}
343 352
344static inline void local_flush_tlb_mm(struct mm_struct *mm) 353static inline void local_flush_tlb_mm(struct mm_struct *mm)
@@ -376,6 +385,12 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
376 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); 385 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
377 dsb(); 386 dsb();
378 } 387 }
388 if (tlb_flag(TLB_V7_IS_BTB)) {
389 /* flush the branch target cache */
390 asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");
391 dsb();
392 isb();
393 }
379} 394}
380 395
381static inline void 396static inline void
@@ -416,6 +431,12 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
416 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); 431 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
417 dsb(); 432 dsb();
418 } 433 }
434 if (tlb_flag(TLB_V7_IS_BTB)) {
435 /* flush the branch target cache */
436 asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");
437 dsb();
438 isb();
439 }
419} 440}
420 441
421static inline void local_flush_tlb_kernel_page(unsigned long kaddr) 442static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
@@ -454,6 +475,12 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
454 dsb(); 475 dsb();
455 isb(); 476 isb();
456 } 477 }
478 if (tlb_flag(TLB_V7_IS_BTB)) {
479 /* flush the branch target cache */
480 asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");
481 dsb();
482 isb();
483 }
457} 484}
458 485
459/* 486/*
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index ea02a7b1c244..7c5f0c024db7 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -21,23 +21,6 @@
21#include <asm/smp_twd.h> 21#include <asm/smp_twd.h>
22#include <asm/hardware/gic.h> 22#include <asm/hardware/gic.h>
23 23
24#define TWD_TIMER_LOAD 0x00
25#define TWD_TIMER_COUNTER 0x04
26#define TWD_TIMER_CONTROL 0x08
27#define TWD_TIMER_INTSTAT 0x0C
28
29#define TWD_WDOG_LOAD 0x20
30#define TWD_WDOG_COUNTER 0x24
31#define TWD_WDOG_CONTROL 0x28
32#define TWD_WDOG_INTSTAT 0x2C
33#define TWD_WDOG_RESETSTAT 0x30
34#define TWD_WDOG_DISABLE 0x34
35
36#define TWD_TIMER_CONTROL_ENABLE (1 << 0)
37#define TWD_TIMER_CONTROL_ONESHOT (0 << 1)
38#define TWD_TIMER_CONTROL_PERIODIC (1 << 1)
39#define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2)
40
41/* set up by the platform code */ 24/* set up by the platform code */
42void __iomem *twd_base; 25void __iomem *twd_base;
43 26
diff --git a/arch/arm/lib/clear_user.S b/arch/arm/lib/clear_user.S
index 5e3f99620c04..14a0d988c82c 100644
--- a/arch/arm/lib/clear_user.S
+++ b/arch/arm/lib/clear_user.S
@@ -45,6 +45,7 @@ USER( strnebt r2, [r0])
45 mov r0, #0 45 mov r0, #0
46 ldmfd sp!, {r1, pc} 46 ldmfd sp!, {r1, pc}
47ENDPROC(__clear_user) 47ENDPROC(__clear_user)
48ENDPROC(__clear_user_std)
48 49
49 .pushsection .fixup,"ax" 50 .pushsection .fixup,"ax"
50 .align 0 51 .align 0
diff --git a/arch/arm/lib/copy_to_user.S b/arch/arm/lib/copy_to_user.S
index 027b69bdbad1..d066df686e17 100644
--- a/arch/arm/lib/copy_to_user.S
+++ b/arch/arm/lib/copy_to_user.S
@@ -93,6 +93,7 @@ WEAK(__copy_to_user)
93#include "copy_template.S" 93#include "copy_template.S"
94 94
95ENDPROC(__copy_to_user) 95ENDPROC(__copy_to_user)
96ENDPROC(__copy_to_user_std)
96 97
97 .pushsection .fixup,"ax" 98 .pushsection .fixup,"ax"
98 .align 0 99 .align 0
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 122e61a9f505..e8cb982f5e8e 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -410,7 +410,7 @@ static struct clk_lookup da830_clks[] = {
410 CLK("davinci-mcasp.0", NULL, &mcasp0_clk), 410 CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
411 CLK("davinci-mcasp.1", NULL, &mcasp1_clk), 411 CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
412 CLK("davinci-mcasp.2", NULL, &mcasp2_clk), 412 CLK("davinci-mcasp.2", NULL, &mcasp2_clk),
413 CLK("musb_hdrc", NULL, &usb20_clk), 413 CLK(NULL, "usb20", &usb20_clk),
414 CLK(NULL, "aemif", &aemif_clk), 414 CLK(NULL, "aemif", &aemif_clk),
415 CLK(NULL, "aintc", &aintc_clk), 415 CLK(NULL, "aintc", &aintc_clk),
416 CLK(NULL, "secu_mgr", &secu_mgr_clk), 416 CLK(NULL, "secu_mgr", &secu_mgr_clk),
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 9d89c67a1cc3..e46ecd847138 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -211,6 +211,9 @@ v6_dma_inv_range:
211 mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line 211 mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line
212#endif 212#endif
2131: 2131:
214#ifdef CONFIG_SMP
215 str r0, [r0] @ write for ownership
216#endif
214#ifdef HARVARD_CACHE 217#ifdef HARVARD_CACHE
215 mcr p15, 0, r0, c7, c6, 1 @ invalidate D line 218 mcr p15, 0, r0, c7, c6, 1 @ invalidate D line
216#else 219#else
@@ -231,6 +234,9 @@ v6_dma_inv_range:
231v6_dma_clean_range: 234v6_dma_clean_range:
232 bic r0, r0, #D_CACHE_LINE_SIZE - 1 235 bic r0, r0, #D_CACHE_LINE_SIZE - 1
2331: 2361:
237#ifdef CONFIG_SMP
238 ldr r2, [r0] @ read for ownership
239#endif
234#ifdef HARVARD_CACHE 240#ifdef HARVARD_CACHE
235 mcr p15, 0, r0, c7, c10, 1 @ clean D line 241 mcr p15, 0, r0, c7, c10, 1 @ clean D line
236#else 242#else
@@ -251,6 +257,10 @@ v6_dma_clean_range:
251ENTRY(v6_dma_flush_range) 257ENTRY(v6_dma_flush_range)
252 bic r0, r0, #D_CACHE_LINE_SIZE - 1 258 bic r0, r0, #D_CACHE_LINE_SIZE - 1
2531: 2591:
260#ifdef CONFIG_SMP
261 ldr r2, [r0] @ read for ownership
262 str r2, [r0] @ write for ownership
263#endif
254#ifdef HARVARD_CACHE 264#ifdef HARVARD_CACHE
255 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line 265 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
256#else 266#else
@@ -273,7 +283,9 @@ ENTRY(v6_dma_map_area)
273 add r1, r1, r0 283 add r1, r1, r0
274 teq r2, #DMA_FROM_DEVICE 284 teq r2, #DMA_FROM_DEVICE
275 beq v6_dma_inv_range 285 beq v6_dma_inv_range
276 b v6_dma_clean_range 286 teq r2, #DMA_TO_DEVICE
287 beq v6_dma_clean_range
288 b v6_dma_flush_range
277ENDPROC(v6_dma_map_area) 289ENDPROC(v6_dma_map_area)
278 290
279/* 291/*
@@ -283,9 +295,6 @@ ENDPROC(v6_dma_map_area)
283 * - dir - DMA direction 295 * - dir - DMA direction
284 */ 296 */
285ENTRY(v6_dma_unmap_area) 297ENTRY(v6_dma_unmap_area)
286 add r1, r1, r0
287 teq r2, #DMA_TO_DEVICE
288 bne v6_dma_inv_range
289 mov pc, lr 298 mov pc, lr
290ENDPROC(v6_dma_unmap_area) 299ENDPROC(v6_dma_unmap_area)
291 300
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index bcd64f265870..06a90dcfc60a 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -167,7 +167,11 @@ ENTRY(v7_coherent_user_range)
167 cmp r0, r1 167 cmp r0, r1
168 blo 1b 168 blo 1b
169 mov r0, #0 169 mov r0, #0
170#ifdef CONFIG_SMP
171 mcr p15, 0, r0, c7, c1, 6 @ invalidate BTB Inner Shareable
172#else
170 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB 173 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
174#endif
171 dsb 175 dsb
172 isb 176 isb
173 mov pc, lr 177 mov pc, lr
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 9bfeb6b9509a..33b327379f07 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -65,6 +65,15 @@ void flush_dcache_page(struct page *page)
65} 65}
66EXPORT_SYMBOL(flush_dcache_page); 66EXPORT_SYMBOL(flush_dcache_page);
67 67
68void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
69 unsigned long uaddr, void *dst, const void *src,
70 unsigned long len)
71{
72 memcpy(dst, src, len);
73 if (vma->vm_flags & VM_EXEC)
74 __cpuc_coherent_user_range(uaddr, uaddr + len);
75}
76
68void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset, 77void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset,
69 size_t size, unsigned int mtype) 78 size_t size, unsigned int mtype)
70{ 79{
@@ -87,8 +96,8 @@ void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size,
87} 96}
88EXPORT_SYMBOL(__arm_ioremap); 97EXPORT_SYMBOL(__arm_ioremap);
89 98
90void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size, 99void __iomem *__arm_ioremap_caller(unsigned long phys_addr, size_t size,
91 unsigned int mtype, void *caller) 100 unsigned int mtype, void *caller)
92{ 101{
93 return __arm_ioremap(phys_addr, size, mtype); 102 return __arm_ioremap(phys_addr, size, mtype);
94} 103}
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index 0cb1848bd876..f3f288a9546d 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -50,7 +50,11 @@ ENTRY(v7wbi_flush_user_tlb_range)
50 cmp r0, r1 50 cmp r0, r1
51 blo 1b 51 blo 1b
52 mov ip, #0 52 mov ip, #0
53#ifdef CONFIG_SMP
54 mcr p15, 0, ip, c7, c1, 6 @ flush BTAC/BTB Inner Shareable
55#else
53 mcr p15, 0, ip, c7, c5, 6 @ flush BTAC/BTB 56 mcr p15, 0, ip, c7, c5, 6 @ flush BTAC/BTB
57#endif
54 dsb 58 dsb
55 mov pc, lr 59 mov pc, lr
56ENDPROC(v7wbi_flush_user_tlb_range) 60ENDPROC(v7wbi_flush_user_tlb_range)
@@ -79,7 +83,11 @@ ENTRY(v7wbi_flush_kern_tlb_range)
79 cmp r0, r1 83 cmp r0, r1
80 blo 1b 84 blo 1b
81 mov r2, #0 85 mov r2, #0
86#ifdef CONFIG_SMP
87 mcr p15, 0, r2, c7, c1, 6 @ flush BTAC/BTB Inner Shareable
88#else
82 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 89 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
90#endif
83 dsb 91 dsb
84 isb 92 isb
85 mov pc, lr 93 mov pc, lr
diff --git a/arch/avr32/include/asm/atomic.h b/arch/avr32/include/asm/atomic.h
index b131c27ddf57..bbce6a1c6bb6 100644
--- a/arch/avr32/include/asm/atomic.h
+++ b/arch/avr32/include/asm/atomic.h
@@ -19,7 +19,7 @@
19 19
20#define ATOMIC_INIT(i) { (i) } 20#define ATOMIC_INIT(i) { (i) }
21 21
22#define atomic_read(v) ((v)->counter) 22#define atomic_read(v) (*(volatile int *)&(v)->counter)
23#define atomic_set(v, i) (((v)->counter) = i) 23#define atomic_set(v, i) (((v)->counter) = i)
24 24
25/* 25/*
diff --git a/arch/cris/include/asm/atomic.h b/arch/cris/include/asm/atomic.h
index a6aca819e9f3..88dc9b9c4ba0 100644
--- a/arch/cris/include/asm/atomic.h
+++ b/arch/cris/include/asm/atomic.h
@@ -15,7 +15,7 @@
15 15
16#define ATOMIC_INIT(i) { (i) } 16#define ATOMIC_INIT(i) { (i) }
17 17
18#define atomic_read(v) ((v)->counter) 18#define atomic_read(v) (*(volatile int *)&(v)->counter)
19#define atomic_set(v,i) (((v)->counter) = (i)) 19#define atomic_set(v,i) (((v)->counter) = (i))
20 20
21/* These should be written in asm but we do it in C for now. */ 21/* These should be written in asm but we do it in C for now. */
diff --git a/arch/frv/include/asm/atomic.h b/arch/frv/include/asm/atomic.h
index 00a57af79afc..fae32c7fdcb6 100644
--- a/arch/frv/include/asm/atomic.h
+++ b/arch/frv/include/asm/atomic.h
@@ -36,7 +36,7 @@
36#define smp_mb__after_atomic_inc() barrier() 36#define smp_mb__after_atomic_inc() barrier()
37 37
38#define ATOMIC_INIT(i) { (i) } 38#define ATOMIC_INIT(i) { (i) }
39#define atomic_read(v) ((v)->counter) 39#define atomic_read(v) (*(volatile int *)&(v)->counter)
40#define atomic_set(v, i) (((v)->counter) = (i)) 40#define atomic_set(v, i) (((v)->counter) = (i))
41 41
42#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS 42#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
diff --git a/arch/h8300/include/asm/atomic.h b/arch/h8300/include/asm/atomic.h
index 33c8c0fa9583..e936804b7508 100644
--- a/arch/h8300/include/asm/atomic.h
+++ b/arch/h8300/include/asm/atomic.h
@@ -10,7 +10,7 @@
10 10
11#define ATOMIC_INIT(i) { (i) } 11#define ATOMIC_INIT(i) { (i) }
12 12
13#define atomic_read(v) ((v)->counter) 13#define atomic_read(v) (*(volatile int *)&(v)->counter)
14#define atomic_set(v, i) (((v)->counter) = i) 14#define atomic_set(v, i) (((v)->counter) = i)
15 15
16#include <asm/system.h> 16#include <asm/system.h>
diff --git a/arch/ia64/include/asm/atomic.h b/arch/ia64/include/asm/atomic.h
index 88405cb0832a..4e1948447a00 100644
--- a/arch/ia64/include/asm/atomic.h
+++ b/arch/ia64/include/asm/atomic.h
@@ -21,8 +21,8 @@
21#define ATOMIC_INIT(i) ((atomic_t) { (i) }) 21#define ATOMIC_INIT(i) ((atomic_t) { (i) })
22#define ATOMIC64_INIT(i) ((atomic64_t) { (i) }) 22#define ATOMIC64_INIT(i) ((atomic64_t) { (i) })
23 23
24#define atomic_read(v) ((v)->counter) 24#define atomic_read(v) (*(volatile int *)&(v)->counter)
25#define atomic64_read(v) ((v)->counter) 25#define atomic64_read(v) (*(volatile long *)&(v)->counter)
26 26
27#define atomic_set(v,i) (((v)->counter) = (i)) 27#define atomic_set(v,i) (((v)->counter) = (i))
28#define atomic64_set(v,i) (((v)->counter) = (i)) 28#define atomic64_set(v,i) (((v)->counter) = (i))
diff --git a/arch/m32r/include/asm/atomic.h b/arch/m32r/include/asm/atomic.h
index 63f0cf0f50dd..d44a51e5271b 100644
--- a/arch/m32r/include/asm/atomic.h
+++ b/arch/m32r/include/asm/atomic.h
@@ -26,7 +26,7 @@
26 * 26 *
27 * Atomically reads the value of @v. 27 * Atomically reads the value of @v.
28 */ 28 */
29#define atomic_read(v) ((v)->counter) 29#define atomic_read(v) (*(volatile int *)&(v)->counter)
30 30
31/** 31/**
32 * atomic_set - set atomic variable 32 * atomic_set - set atomic variable
diff --git a/arch/m68k/amiga/Makefile b/arch/m68k/amiga/Makefile
index 6a0d7650f980..11dd30b16b3b 100644
--- a/arch/m68k/amiga/Makefile
+++ b/arch/m68k/amiga/Makefile
@@ -2,6 +2,6 @@
2# Makefile for Linux arch/m68k/amiga source directory 2# Makefile for Linux arch/m68k/amiga source directory
3# 3#
4 4
5obj-y := config.o amiints.o cia.o chipram.o amisound.o 5obj-y := config.o amiints.o cia.o chipram.o amisound.o platform.o
6 6
7obj-$(CONFIG_AMIGA_PCMCIA) += pcmcia.o 7obj-$(CONFIG_AMIGA_PCMCIA) += pcmcia.o
diff --git a/arch/m68k/amiga/platform.c b/arch/m68k/amiga/platform.c
new file mode 100644
index 000000000000..38f18bf14737
--- /dev/null
+++ b/arch/m68k/amiga/platform.c
@@ -0,0 +1,83 @@
1/*
2 * Copyright (C) 2007-2009 Geert Uytterhoeven
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file COPYING in the main directory of this archive
6 * for more details.
7 */
8
9#include <linux/init.h>
10#include <linux/platform_device.h>
11#include <linux/zorro.h>
12
13#include <asm/amigahw.h>
14
15
16#ifdef CONFIG_ZORRO
17
18static const struct resource zorro_resources[] __initconst = {
19 /* Zorro II regions (on Zorro II/III) */
20 {
21 .name = "Zorro II exp",
22 .start = 0x00e80000,
23 .end = 0x00efffff,
24 .flags = IORESOURCE_MEM,
25 }, {
26 .name = "Zorro II mem",
27 .start = 0x00200000,
28 .end = 0x009fffff,
29 .flags = IORESOURCE_MEM,
30 },
31 /* Zorro III regions (on Zorro III only) */
32 {
33 .name = "Zorro III exp",
34 .start = 0xff000000,
35 .end = 0xffffffff,
36 .flags = IORESOURCE_MEM,
37 }, {
38 .name = "Zorro III cfg",
39 .start = 0x40000000,
40 .end = 0x7fffffff,
41 .flags = IORESOURCE_MEM,
42 }
43};
44
45
46static int __init amiga_init_bus(void)
47{
48 if (!MACH_IS_AMIGA || !AMIGAHW_PRESENT(ZORRO))
49 return -ENODEV;
50
51 platform_device_register_simple("amiga-zorro", -1, zorro_resources,
52 AMIGAHW_PRESENT(ZORRO3) ? 4 : 2);
53 return 0;
54}
55
56subsys_initcall(amiga_init_bus);
57
58#endif /* CONFIG_ZORRO */
59
60
61static int __init amiga_init_devices(void)
62{
63 if (!MACH_IS_AMIGA)
64 return -ENODEV;
65
66 /* video hardware */
67 if (AMIGAHW_PRESENT(AMI_VIDEO))
68 platform_device_register_simple("amiga-video", -1, NULL, 0);
69
70
71 /* sound hardware */
72 if (AMIGAHW_PRESENT(AMI_AUDIO))
73 platform_device_register_simple("amiga-audio", -1, NULL, 0);
74
75
76 /* storage interfaces */
77 if (AMIGAHW_PRESENT(AMI_FLOPPY))
78 platform_device_register_simple("amiga-floppy", -1, NULL, 0);
79
80 return 0;
81}
82
83device_initcall(amiga_init_devices);
diff --git a/arch/m68k/bvme6000/rtc.c b/arch/m68k/bvme6000/rtc.c
index b46ea1714a89..cb8617bb194b 100644
--- a/arch/m68k/bvme6000/rtc.c
+++ b/arch/m68k/bvme6000/rtc.c
@@ -9,7 +9,6 @@
9#include <linux/types.h> 9#include <linux/types.h>
10#include <linux/errno.h> 10#include <linux/errno.h>
11#include <linux/miscdevice.h> 11#include <linux/miscdevice.h>
12#include <linux/smp_lock.h>
13#include <linux/ioport.h> 12#include <linux/ioport.h>
14#include <linux/capability.h> 13#include <linux/capability.h>
15#include <linux/fcntl.h> 14#include <linux/fcntl.h>
@@ -35,10 +34,9 @@
35static unsigned char days_in_mo[] = 34static unsigned char days_in_mo[] =
36{0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; 35{0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31};
37 36
38static char rtc_status; 37static atomic_t rtc_status = ATOMIC_INIT(1);
39 38
40static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, 39static long rtc_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
41 unsigned long arg)
42{ 40{
43 volatile RtcPtr_t rtc = (RtcPtr_t)BVME_RTC_BASE; 41 volatile RtcPtr_t rtc = (RtcPtr_t)BVME_RTC_BASE;
44 unsigned char msr; 42 unsigned char msr;
@@ -132,29 +130,20 @@ static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
132} 130}
133 131
134/* 132/*
135 * We enforce only one user at a time here with the open/close. 133 * We enforce only one user at a time here with the open/close.
136 * Also clear the previous interrupt data on an open, and clean
137 * up things on a close.
138 */ 134 */
139
140static int rtc_open(struct inode *inode, struct file *file) 135static int rtc_open(struct inode *inode, struct file *file)
141{ 136{
142 lock_kernel(); 137 if (!atomic_dec_and_test(&rtc_status)) {
143 if(rtc_status) { 138 atomic_inc(&rtc_status);
144 unlock_kernel();
145 return -EBUSY; 139 return -EBUSY;
146 } 140 }
147
148 rtc_status = 1;
149 unlock_kernel();
150 return 0; 141 return 0;
151} 142}
152 143
153static int rtc_release(struct inode *inode, struct file *file) 144static int rtc_release(struct inode *inode, struct file *file)
154{ 145{
155 lock_kernel(); 146 atomic_inc(&rtc_status);
156 rtc_status = 0;
157 unlock_kernel();
158 return 0; 147 return 0;
159} 148}
160 149
@@ -163,9 +152,9 @@ static int rtc_release(struct inode *inode, struct file *file)
163 */ 152 */
164 153
165static const struct file_operations rtc_fops = { 154static const struct file_operations rtc_fops = {
166 .ioctl = rtc_ioctl, 155 .unlocked_ioctl = rtc_ioctl,
167 .open = rtc_open, 156 .open = rtc_open,
168 .release = rtc_release, 157 .release = rtc_release,
169}; 158};
170 159
171static struct miscdevice rtc_dev = { 160static struct miscdevice rtc_dev = {
diff --git a/arch/m68k/hp300/time.h b/arch/m68k/hp300/time.h
index f5b3d098b0f5..7b98242960de 100644
--- a/arch/m68k/hp300/time.h
+++ b/arch/m68k/hp300/time.h
@@ -1,4 +1,2 @@
1extern void hp300_sched_init(irq_handler_t vector); 1extern void hp300_sched_init(irq_handler_t vector);
2extern unsigned long hp300_gettimeoffset (void); 2extern unsigned long hp300_gettimeoffset(void);
3
4
diff --git a/arch/m68k/include/asm/atomic_mm.h b/arch/m68k/include/asm/atomic_mm.h
index d9d2ed647435..6a223b3f7e74 100644
--- a/arch/m68k/include/asm/atomic_mm.h
+++ b/arch/m68k/include/asm/atomic_mm.h
@@ -15,7 +15,7 @@
15 15
16#define ATOMIC_INIT(i) { (i) } 16#define ATOMIC_INIT(i) { (i) }
17 17
18#define atomic_read(v) ((v)->counter) 18#define atomic_read(v) (*(volatile int *)&(v)->counter)
19#define atomic_set(v, i) (((v)->counter) = i) 19#define atomic_set(v, i) (((v)->counter) = i)
20 20
21static inline void atomic_add(int i, atomic_t *v) 21static inline void atomic_add(int i, atomic_t *v)
diff --git a/arch/m68k/include/asm/atomic_no.h b/arch/m68k/include/asm/atomic_no.h
index 5674cb9449bd..289310c63a8a 100644
--- a/arch/m68k/include/asm/atomic_no.h
+++ b/arch/m68k/include/asm/atomic_no.h
@@ -15,7 +15,7 @@
15 15
16#define ATOMIC_INIT(i) { (i) } 16#define ATOMIC_INIT(i) { (i) }
17 17
18#define atomic_read(v) ((v)->counter) 18#define atomic_read(v) (*(volatile int *)&(v)->counter)
19#define atomic_set(v, i) (((v)->counter) = i) 19#define atomic_set(v, i) (((v)->counter) = i)
20 20
21static __inline__ void atomic_add(int i, atomic_t *v) 21static __inline__ void atomic_add(int i, atomic_t *v)
diff --git a/arch/m68k/include/asm/bitops_mm.h b/arch/m68k/include/asm/bitops_mm.h
index 9bde784e7bad..b4ecdaada520 100644
--- a/arch/m68k/include/asm/bitops_mm.h
+++ b/arch/m68k/include/asm/bitops_mm.h
@@ -365,6 +365,10 @@ static inline int minix_test_bit(int nr, const void *vaddr)
365#define ext2_set_bit_atomic(lock, nr, addr) test_and_set_bit((nr) ^ 24, (unsigned long *)(addr)) 365#define ext2_set_bit_atomic(lock, nr, addr) test_and_set_bit((nr) ^ 24, (unsigned long *)(addr))
366#define ext2_clear_bit(nr, addr) __test_and_clear_bit((nr) ^ 24, (unsigned long *)(addr)) 366#define ext2_clear_bit(nr, addr) __test_and_clear_bit((nr) ^ 24, (unsigned long *)(addr))
367#define ext2_clear_bit_atomic(lock, nr, addr) test_and_clear_bit((nr) ^ 24, (unsigned long *)(addr)) 367#define ext2_clear_bit_atomic(lock, nr, addr) test_and_clear_bit((nr) ^ 24, (unsigned long *)(addr))
368#define ext2_find_next_zero_bit(addr, size, offset) \
369 generic_find_next_zero_le_bit((unsigned long *)addr, size, offset)
370#define ext2_find_next_bit(addr, size, offset) \
371 generic_find_next_le_bit((unsigned long *)addr, size, offset)
368 372
369static inline int ext2_test_bit(int nr, const void *vaddr) 373static inline int ext2_test_bit(int nr, const void *vaddr)
370{ 374{
@@ -394,10 +398,9 @@ static inline int ext2_find_first_zero_bit(const void *vaddr, unsigned size)
394 return (p - addr) * 32 + res; 398 return (p - addr) * 32 + res;
395} 399}
396 400
397static inline int ext2_find_next_zero_bit(const void *vaddr, unsigned size, 401static inline unsigned long generic_find_next_zero_le_bit(const unsigned long *addr,
398 unsigned offset) 402 unsigned long size, unsigned long offset)
399{ 403{
400 const unsigned long *addr = vaddr;
401 const unsigned long *p = addr + (offset >> 5); 404 const unsigned long *p = addr + (offset >> 5);
402 int bit = offset & 31UL, res; 405 int bit = offset & 31UL, res;
403 406
@@ -437,10 +440,9 @@ static inline int ext2_find_first_bit(const void *vaddr, unsigned size)
437 return (p - addr) * 32 + res; 440 return (p - addr) * 32 + res;
438} 441}
439 442
440static inline int ext2_find_next_bit(const void *vaddr, unsigned size, 443static inline unsigned long generic_find_next_le_bit(const unsigned long *addr,
441 unsigned offset) 444 unsigned long size, unsigned long offset)
442{ 445{
443 const unsigned long *addr = vaddr;
444 const unsigned long *p = addr + (offset >> 5); 446 const unsigned long *p = addr + (offset >> 5);
445 int bit = offset & 31UL, res; 447 int bit = offset & 31UL, res;
446 448
diff --git a/arch/m68k/include/asm/param.h b/arch/m68k/include/asm/param.h
index 85c41b75aa78..36265ccf5c7b 100644
--- a/arch/m68k/include/asm/param.h
+++ b/arch/m68k/include/asm/param.h
@@ -1,26 +1,12 @@
1#ifndef _M68K_PARAM_H 1#ifndef _M68K_PARAM_H
2#define _M68K_PARAM_H 2#define _M68K_PARAM_H
3 3
4#ifdef __KERNEL__
5# define HZ CONFIG_HZ /* Internal kernel timer frequency */
6# define USER_HZ 100 /* .. some user interfaces are in "ticks" */
7# define CLOCKS_PER_SEC (USER_HZ) /* like times() */
8#endif
9
10#ifndef HZ
11#define HZ 100
12#endif
13
14#ifdef __uClinux__ 4#ifdef __uClinux__
15#define EXEC_PAGESIZE 4096 5#define EXEC_PAGESIZE 4096
16#else 6#else
17#define EXEC_PAGESIZE 8192 7#define EXEC_PAGESIZE 8192
18#endif 8#endif
19 9
20#ifndef NOGROUP 10#include <asm-generic/param.h>
21#define NOGROUP (-1)
22#endif
23
24#define MAXHOSTNAMELEN 64 /* max length of hostname */
25 11
26#endif /* _M68K_PARAM_H */ 12#endif /* _M68K_PARAM_H */
diff --git a/arch/m68k/kernel/traps.c b/arch/m68k/kernel/traps.c
index aacd6d17b833..ada4f4cca811 100644
--- a/arch/m68k/kernel/traps.c
+++ b/arch/m68k/kernel/traps.c
@@ -455,7 +455,7 @@ static inline void access_error040(struct frame *fp)
455 455
456 if (do_page_fault(&fp->ptregs, addr, errorcode)) { 456 if (do_page_fault(&fp->ptregs, addr, errorcode)) {
457#ifdef DEBUG 457#ifdef DEBUG
458 printk("do_page_fault() !=0 \n"); 458 printk("do_page_fault() !=0\n");
459#endif 459#endif
460 if (user_mode(&fp->ptregs)){ 460 if (user_mode(&fp->ptregs)){
461 /* delay writebacks after signal delivery */ 461 /* delay writebacks after signal delivery */
diff --git a/arch/m68k/mac/config.c b/arch/m68k/mac/config.c
index 0356da9bf763..1c16b1baf8db 100644
--- a/arch/m68k/mac/config.c
+++ b/arch/m68k/mac/config.c
@@ -148,7 +148,7 @@ static void mac_cache_card_flush(int writeback)
148void __init config_mac(void) 148void __init config_mac(void)
149{ 149{
150 if (!MACH_IS_MAC) 150 if (!MACH_IS_MAC)
151 printk(KERN_ERR "ERROR: no Mac, but config_mac() called!! \n"); 151 printk(KERN_ERR "ERROR: no Mac, but config_mac() called!!\n");
152 152
153 mach_sched_init = mac_sched_init; 153 mach_sched_init = mac_sched_init;
154 mach_init_IRQ = mac_init_IRQ; 154 mach_init_IRQ = mac_init_IRQ;
@@ -867,7 +867,7 @@ static void __init mac_identify(void)
867 */ 867 */
868 iop_preinit(); 868 iop_preinit();
869 869
870 printk(KERN_INFO "Detected Macintosh model: %d \n", model); 870 printk(KERN_INFO "Detected Macintosh model: %d\n", model);
871 871
872 /* 872 /*
873 * Report booter data: 873 * Report booter data:
@@ -878,12 +878,12 @@ static void __init mac_identify(void)
878 mac_bi_data.videoaddr, mac_bi_data.videorow, 878 mac_bi_data.videoaddr, mac_bi_data.videorow,
879 mac_bi_data.videodepth, mac_bi_data.dimensions & 0xFFFF, 879 mac_bi_data.videodepth, mac_bi_data.dimensions & 0xFFFF,
880 mac_bi_data.dimensions >> 16); 880 mac_bi_data.dimensions >> 16);
881 printk(KERN_DEBUG " Videological 0x%lx phys. 0x%lx, SCC at 0x%lx \n", 881 printk(KERN_DEBUG " Videological 0x%lx phys. 0x%lx, SCC at 0x%lx\n",
882 mac_bi_data.videological, mac_orig_videoaddr, 882 mac_bi_data.videological, mac_orig_videoaddr,
883 mac_bi_data.sccbase); 883 mac_bi_data.sccbase);
884 printk(KERN_DEBUG " Boottime: 0x%lx GMTBias: 0x%lx \n", 884 printk(KERN_DEBUG " Boottime: 0x%lx GMTBias: 0x%lx\n",
885 mac_bi_data.boottime, mac_bi_data.gmtbias); 885 mac_bi_data.boottime, mac_bi_data.gmtbias);
886 printk(KERN_DEBUG " Machine ID: %ld CPUid: 0x%lx memory size: 0x%lx \n", 886 printk(KERN_DEBUG " Machine ID: %ld CPUid: 0x%lx memory size: 0x%lx\n",
887 mac_bi_data.id, mac_bi_data.cpuid, mac_bi_data.memsize); 887 mac_bi_data.id, mac_bi_data.cpuid, mac_bi_data.memsize);
888 888
889 iop_init(); 889 iop_init();
diff --git a/arch/m68k/mm/fault.c b/arch/m68k/mm/fault.c
index d0e35cf99fc6..a96394a0333d 100644
--- a/arch/m68k/mm/fault.c
+++ b/arch/m68k/mm/fault.c
@@ -154,7 +154,6 @@ good_area:
154 * the fault. 154 * the fault.
155 */ 155 */
156 156
157 survive:
158 fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0); 157 fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0);
159#ifdef DEBUG 158#ifdef DEBUG
160 printk("handle_mm_fault returns %d\n",fault); 159 printk("handle_mm_fault returns %d\n",fault);
@@ -180,15 +179,10 @@ good_area:
180 */ 179 */
181out_of_memory: 180out_of_memory:
182 up_read(&mm->mmap_sem); 181 up_read(&mm->mmap_sem);
183 if (is_global_init(current)) { 182 if (!user_mode(regs))
184 yield(); 183 goto no_context;
185 down_read(&mm->mmap_sem); 184 pagefault_out_of_memory();
186 goto survive; 185 return 0;
187 }
188
189 printk("VM: killing process %s\n", current->comm);
190 if (user_mode(regs))
191 do_group_exit(SIGKILL);
192 186
193no_context: 187no_context:
194 current->thread.signo = SIGBUS; 188 current->thread.signo = SIGBUS;
diff --git a/arch/m68k/mvme16x/rtc.c b/arch/m68k/mvme16x/rtc.c
index 8da9c250d3e1..11ac6f63967a 100644
--- a/arch/m68k/mvme16x/rtc.c
+++ b/arch/m68k/mvme16x/rtc.c
@@ -9,7 +9,6 @@
9#include <linux/types.h> 9#include <linux/types.h>
10#include <linux/errno.h> 10#include <linux/errno.h>
11#include <linux/miscdevice.h> 11#include <linux/miscdevice.h>
12#include <linux/smp_lock.h>
13#include <linux/ioport.h> 12#include <linux/ioport.h>
14#include <linux/capability.h> 13#include <linux/capability.h>
15#include <linux/fcntl.h> 14#include <linux/fcntl.h>
@@ -36,8 +35,7 @@ static const unsigned char days_in_mo[] =
36 35
37static atomic_t rtc_ready = ATOMIC_INIT(1); 36static atomic_t rtc_ready = ATOMIC_INIT(1);
38 37
39static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, 38static long rtc_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
40 unsigned long arg)
41{ 39{
42 volatile MK48T08ptr_t rtc = (MK48T08ptr_t)MVME_RTC_BASE; 40 volatile MK48T08ptr_t rtc = (MK48T08ptr_t)MVME_RTC_BASE;
43 unsigned long flags; 41 unsigned long flags;
@@ -120,22 +118,15 @@ static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
120} 118}
121 119
122/* 120/*
123 * We enforce only one user at a time here with the open/close. 121 * We enforce only one user at a time here with the open/close.
124 * Also clear the previous interrupt data on an open, and clean
125 * up things on a close.
126 */ 122 */
127
128static int rtc_open(struct inode *inode, struct file *file) 123static int rtc_open(struct inode *inode, struct file *file)
129{ 124{
130 lock_kernel();
131 if( !atomic_dec_and_test(&rtc_ready) ) 125 if( !atomic_dec_and_test(&rtc_ready) )
132 { 126 {
133 atomic_inc( &rtc_ready ); 127 atomic_inc( &rtc_ready );
134 unlock_kernel();
135 return -EBUSY; 128 return -EBUSY;
136 } 129 }
137 unlock_kernel();
138
139 return 0; 130 return 0;
140} 131}
141 132
@@ -150,9 +141,9 @@ static int rtc_release(struct inode *inode, struct file *file)
150 */ 141 */
151 142
152static const struct file_operations rtc_fops = { 143static const struct file_operations rtc_fops = {
153 .ioctl = rtc_ioctl, 144 .unlocked_ioctl = rtc_ioctl,
154 .open = rtc_open, 145 .open = rtc_open,
155 .release = rtc_release, 146 .release = rtc_release,
156}; 147};
157 148
158static struct miscdevice rtc_dev= 149static struct miscdevice rtc_dev=
diff --git a/arch/m68k/q40/config.c b/arch/m68k/q40/config.c
index 31ab3f08bbda..ad10fecec2fe 100644
--- a/arch/m68k/q40/config.c
+++ b/arch/m68k/q40/config.c
@@ -126,7 +126,7 @@ static void q40_reset(void)
126{ 126{
127 halted = 1; 127 halted = 1;
128 printk("\n\n*******************************************\n" 128 printk("\n\n*******************************************\n"
129 "Called q40_reset : press the RESET button!! \n" 129 "Called q40_reset : press the RESET button!!\n"
130 "*******************************************\n"); 130 "*******************************************\n");
131 Q40_LED_ON(); 131 Q40_LED_ON();
132 while (1) 132 while (1)
diff --git a/arch/microblaze/include/asm/uaccess.h b/arch/microblaze/include/asm/uaccess.h
index 446bec29b142..26460d15b338 100644
--- a/arch/microblaze/include/asm/uaccess.h
+++ b/arch/microblaze/include/asm/uaccess.h
@@ -182,6 +182,39 @@ extern long __user_bad(void);
182 * Returns zero on success, or -EFAULT on error. 182 * Returns zero on success, or -EFAULT on error.
183 * On error, the variable @x is set to zero. 183 * On error, the variable @x is set to zero.
184 */ 184 */
185#define get_user(x, ptr) \
186 __get_user_check((x), (ptr), sizeof(*(ptr)))
187
188#define __get_user_check(x, ptr, size) \
189({ \
190 unsigned long __gu_val = 0; \
191 const typeof(*(ptr)) __user *__gu_addr = (ptr); \
192 int __gu_err = 0; \
193 \
194 if (access_ok(VERIFY_READ, __gu_addr, size)) { \
195 switch (size) { \
196 case 1: \
197 __get_user_asm("lbu", __gu_addr, __gu_val, \
198 __gu_err); \
199 break; \
200 case 2: \
201 __get_user_asm("lhu", __gu_addr, __gu_val, \
202 __gu_err); \
203 break; \
204 case 4: \
205 __get_user_asm("lw", __gu_addr, __gu_val, \
206 __gu_err); \
207 break; \
208 default: \
209 __gu_err = __user_bad(); \
210 break; \
211 } \
212 } else { \
213 __gu_err = -EFAULT; \
214 } \
215 x = (typeof(*(ptr)))__gu_val; \
216 __gu_err; \
217})
185 218
186#define __get_user(x, ptr) \ 219#define __get_user(x, ptr) \
187({ \ 220({ \
@@ -206,12 +239,6 @@ extern long __user_bad(void);
206}) 239})
207 240
208 241
209#define get_user(x, ptr) \
210({ \
211 access_ok(VERIFY_READ, (ptr), sizeof(*(ptr))) \
212 ? __get_user((x), (ptr)) : -EFAULT; \
213})
214
215#define __put_user_asm(insn, __gu_ptr, __gu_val, __gu_err) \ 242#define __put_user_asm(insn, __gu_ptr, __gu_val, __gu_err) \
216({ \ 243({ \
217 __asm__ __volatile__ ( \ 244 __asm__ __volatile__ ( \
@@ -266,6 +293,42 @@ extern long __user_bad(void);
266 * 293 *
267 * Returns zero on success, or -EFAULT on error. 294 * Returns zero on success, or -EFAULT on error.
268 */ 295 */
296#define put_user(x, ptr) \
297 __put_user_check((x), (ptr), sizeof(*(ptr)))
298
299#define __put_user_check(x, ptr, size) \
300({ \
301 typeof(*(ptr)) __pu_val; \
302 typeof(*(ptr)) __user *__pu_addr = (ptr); \
303 int __pu_err = 0; \
304 \
305 __pu_val = (x); \
306 if (access_ok(VERIFY_WRITE, __pu_addr, size)) { \
307 switch (size) { \
308 case 1: \
309 __put_user_asm("sb", __pu_addr, __pu_val, \
310 __pu_err); \
311 break; \
312 case 2: \
313 __put_user_asm("sh", __pu_addr, __pu_val, \
314 __pu_err); \
315 break; \
316 case 4: \
317 __put_user_asm("sw", __pu_addr, __pu_val, \
318 __pu_err); \
319 break; \
320 case 8: \
321 __put_user_asm_8(__pu_addr, __pu_val, __pu_err);\
322 break; \
323 default: \
324 __pu_err = __user_bad(); \
325 break; \
326 } \
327 } else { \
328 __pu_err = -EFAULT; \
329 } \
330 __pu_err; \
331})
269 332
270#define __put_user(x, ptr) \ 333#define __put_user(x, ptr) \
271({ \ 334({ \
@@ -290,18 +353,6 @@ extern long __user_bad(void);
290 __gu_err; \ 353 __gu_err; \
291}) 354})
292 355
293#ifndef CONFIG_MMU
294
295#define put_user(x, ptr) __put_user((x), (ptr))
296
297#else /* CONFIG_MMU */
298
299#define put_user(x, ptr) \
300({ \
301 access_ok(VERIFY_WRITE, (ptr), sizeof(*(ptr))) \
302 ? __put_user((x), (ptr)) : -EFAULT; \
303})
304#endif /* CONFIG_MMU */
305 356
306/* copy_to_from_user */ 357/* copy_to_from_user */
307#define __copy_from_user(to, from, n) \ 358#define __copy_from_user(to, from, n) \
diff --git a/arch/microblaze/kernel/cpu/cache.c b/arch/microblaze/kernel/cpu/cache.c
index 21c3a92394de..109876e8d643 100644
--- a/arch/microblaze/kernel/cpu/cache.c
+++ b/arch/microblaze/kernel/cpu/cache.c
@@ -137,8 +137,9 @@ do { \
137do { \ 137do { \
138 int step = -line_length; \ 138 int step = -line_length; \
139 int align = ~(line_length - 1); \ 139 int align = ~(line_length - 1); \
140 int count; \
140 end = ((end & align) == end) ? end - line_length : end & align; \ 141 end = ((end & align) == end) ? end - line_length : end & align; \
141 int count = end - start; \ 142 count = end - start; \
142 WARN_ON(count < 0); \ 143 WARN_ON(count < 0); \
143 \ 144 \
144 __asm__ __volatile__ (" 1: " #op " %0, %1; \ 145 __asm__ __volatile__ (" 1: " #op " %0, %1; \
diff --git a/arch/microblaze/kernel/entry-nommu.S b/arch/microblaze/kernel/entry-nommu.S
index 391d6197fc3b..8cc18cd2cce6 100644
--- a/arch/microblaze/kernel/entry-nommu.S
+++ b/arch/microblaze/kernel/entry-nommu.S
@@ -476,6 +476,8 @@ ENTRY(ret_from_fork)
476 nop 476 nop
477 477
478work_pending: 478work_pending:
479 enable_irq
480
479 andi r11, r19, _TIF_NEED_RESCHED 481 andi r11, r19, _TIF_NEED_RESCHED
480 beqi r11, 1f 482 beqi r11, 1f
481 bralid r15, schedule 483 bralid r15, schedule
diff --git a/arch/microblaze/kernel/microblaze_ksyms.c b/arch/microblaze/kernel/microblaze_ksyms.c
index bc4dcb7d3861..ff85f7718035 100644
--- a/arch/microblaze/kernel/microblaze_ksyms.c
+++ b/arch/microblaze/kernel/microblaze_ksyms.c
@@ -52,3 +52,14 @@ EXPORT_SYMBOL_GPL(_ebss);
52extern void _mcount(void); 52extern void _mcount(void);
53EXPORT_SYMBOL(_mcount); 53EXPORT_SYMBOL(_mcount);
54#endif 54#endif
55
56/*
57 * Assembly functions that may be used (directly or indirectly) by modules
58 */
59EXPORT_SYMBOL(__copy_tofrom_user);
60EXPORT_SYMBOL(__strncpy_user);
61
62#ifdef CONFIG_OPT_LIB_ASM
63EXPORT_SYMBOL(memcpy);
64EXPORT_SYMBOL(memmove);
65#endif
diff --git a/arch/microblaze/kernel/module.c b/arch/microblaze/kernel/module.c
index cbecf110dc30..0e73f6606547 100644
--- a/arch/microblaze/kernel/module.c
+++ b/arch/microblaze/kernel/module.c
@@ -16,6 +16,7 @@
16#include <linux/string.h> 16#include <linux/string.h>
17 17
18#include <asm/pgtable.h> 18#include <asm/pgtable.h>
19#include <asm/cacheflush.h>
19 20
20void *module_alloc(unsigned long size) 21void *module_alloc(unsigned long size)
21{ 22{
@@ -151,6 +152,7 @@ int apply_relocate_add(Elf32_Shdr *sechdrs, const char *strtab,
151int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs, 152int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
152 struct module *module) 153 struct module *module)
153{ 154{
155 flush_dcache();
154 return 0; 156 return 0;
155} 157}
156 158
diff --git a/arch/microblaze/mm/init.c b/arch/microblaze/mm/init.c
index f42c2dde8b1c..cca3579d4268 100644
--- a/arch/microblaze/mm/init.c
+++ b/arch/microblaze/mm/init.c
@@ -47,6 +47,7 @@ unsigned long memory_start;
47EXPORT_SYMBOL(memory_start); 47EXPORT_SYMBOL(memory_start);
48unsigned long memory_end; /* due to mm/nommu.c */ 48unsigned long memory_end; /* due to mm/nommu.c */
49unsigned long memory_size; 49unsigned long memory_size;
50EXPORT_SYMBOL(memory_size);
50 51
51/* 52/*
52 * paging_init() sets up the page tables - in fact we've already done this. 53 * paging_init() sets up the page tables - in fact we've already done this.
diff --git a/arch/microblaze/mm/pgtable.c b/arch/microblaze/mm/pgtable.c
index 784557fb28cf..59bf2335a4ce 100644
--- a/arch/microblaze/mm/pgtable.c
+++ b/arch/microblaze/mm/pgtable.c
@@ -42,6 +42,7 @@
42 42
43unsigned long ioremap_base; 43unsigned long ioremap_base;
44unsigned long ioremap_bot; 44unsigned long ioremap_bot;
45EXPORT_SYMBOL(ioremap_bot);
45 46
46/* The maximum lowmem defaults to 768Mb, but this can be configured to 47/* The maximum lowmem defaults to 768Mb, but this can be configured to
47 * another value. 48 * another value.
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index 01c8c97c15b7..9cb782b8e036 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -1507,7 +1507,7 @@ void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1507 pci_bus_add_devices(bus); 1507 pci_bus_add_devices(bus);
1508 1508
1509 /* Fixup EEH */ 1509 /* Fixup EEH */
1510 eeh_add_device_tree_late(bus); 1510 /* eeh_add_device_tree_late(bus); */
1511} 1511}
1512EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); 1512EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1513 1513
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index 519197ede089..59dc0c7ef733 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -29,7 +29,7 @@
29 * 29 *
30 * Atomically reads the value of @v. 30 * Atomically reads the value of @v.
31 */ 31 */
32#define atomic_read(v) ((v)->counter) 32#define atomic_read(v) (*(volatile int *)&(v)->counter)
33 33
34/* 34/*
35 * atomic_set - set atomic variable 35 * atomic_set - set atomic variable
@@ -410,7 +410,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
410 * @v: pointer of type atomic64_t 410 * @v: pointer of type atomic64_t
411 * 411 *
412 */ 412 */
413#define atomic64_read(v) ((v)->counter) 413#define atomic64_read(v) (*(volatile long *)&(v)->counter)
414 414
415/* 415/*
416 * atomic64_set - set atomic variable 416 * atomic64_set - set atomic variable
diff --git a/arch/mips/include/asm/i8253.h b/arch/mips/include/asm/i8253.h
index 032ca73f181b..48bb82372994 100644
--- a/arch/mips/include/asm/i8253.h
+++ b/arch/mips/include/asm/i8253.h
@@ -12,7 +12,7 @@
12#define PIT_CH0 0x40 12#define PIT_CH0 0x40
13#define PIT_CH2 0x42 13#define PIT_CH2 0x42
14 14
15extern spinlock_t i8253_lock; 15extern raw_spinlock_t i8253_lock;
16 16
17extern void setup_pit_timer(void); 17extern void setup_pit_timer(void);
18 18
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 49382d5e891a..c6e3c93ce7c7 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -135,6 +135,12 @@
135#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ 135#define FPU_CSR_COND7 0x80000000 /* $fcc7 */
136 136
137/* 137/*
138 * Bits 18 - 20 of the FPU Status Register will be read as 0,
139 * and should be written as zero.
140 */
141#define FPU_CSR_RSVD 0x001c0000
142
143/*
138 * X the exception cause indicator 144 * X the exception cause indicator
139 * E the exception enable 145 * E the exception enable
140 * S the sticky/flag bit 146 * S the sticky/flag bit
@@ -161,7 +167,8 @@
161#define FPU_CSR_UDF_S 0x00000008 167#define FPU_CSR_UDF_S 0x00000008
162#define FPU_CSR_INE_S 0x00000004 168#define FPU_CSR_INE_S 0x00000004
163 169
164/* rounding mode */ 170/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
171#define FPU_CSR_RM 0x00000003
165#define FPU_CSR_RN 0x0 /* nearest */ 172#define FPU_CSR_RN 0x0 /* nearest */
166#define FPU_CSR_RZ 0x1 /* towards zero */ 173#define FPU_CSR_RZ 0x1 /* towards zero */
167#define FPU_CSR_RU 0x2 /* towards +Infinity */ 174#define FPU_CSR_RU 0x2 /* towards +Infinity */
diff --git a/arch/mips/kernel/i8253.c b/arch/mips/kernel/i8253.c
index ed5c441615e4..94794062a177 100644
--- a/arch/mips/kernel/i8253.c
+++ b/arch/mips/kernel/i8253.c
@@ -15,7 +15,7 @@
15#include <asm/io.h> 15#include <asm/io.h>
16#include <asm/time.h> 16#include <asm/time.h>
17 17
18DEFINE_SPINLOCK(i8253_lock); 18DEFINE_RAW_SPINLOCK(i8253_lock);
19EXPORT_SYMBOL(i8253_lock); 19EXPORT_SYMBOL(i8253_lock);
20 20
21/* 21/*
@@ -26,7 +26,7 @@ EXPORT_SYMBOL(i8253_lock);
26static void init_pit_timer(enum clock_event_mode mode, 26static void init_pit_timer(enum clock_event_mode mode,
27 struct clock_event_device *evt) 27 struct clock_event_device *evt)
28{ 28{
29 spin_lock(&i8253_lock); 29 raw_spin_lock(&i8253_lock);
30 30
31 switch(mode) { 31 switch(mode) {
32 case CLOCK_EVT_MODE_PERIODIC: 32 case CLOCK_EVT_MODE_PERIODIC:
@@ -55,7 +55,7 @@ static void init_pit_timer(enum clock_event_mode mode,
55 /* Nothing to do here */ 55 /* Nothing to do here */
56 break; 56 break;
57 } 57 }
58 spin_unlock(&i8253_lock); 58 raw_spin_unlock(&i8253_lock);
59} 59}
60 60
61/* 61/*
@@ -65,10 +65,10 @@ static void init_pit_timer(enum clock_event_mode mode,
65 */ 65 */
66static int pit_next_event(unsigned long delta, struct clock_event_device *evt) 66static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
67{ 67{
68 spin_lock(&i8253_lock); 68 raw_spin_lock(&i8253_lock);
69 outb_p(delta & 0xff , PIT_CH0); /* LSB */ 69 outb_p(delta & 0xff , PIT_CH0); /* LSB */
70 outb(delta >> 8 , PIT_CH0); /* MSB */ 70 outb(delta >> 8 , PIT_CH0); /* MSB */
71 spin_unlock(&i8253_lock); 71 raw_spin_unlock(&i8253_lock);
72 72
73 return 0; 73 return 0;
74} 74}
@@ -137,7 +137,7 @@ static cycle_t pit_read(struct clocksource *cs)
137 static int old_count; 137 static int old_count;
138 static u32 old_jifs; 138 static u32 old_jifs;
139 139
140 spin_lock_irqsave(&i8253_lock, flags); 140 raw_spin_lock_irqsave(&i8253_lock, flags);
141 /* 141 /*
142 * Although our caller may have the read side of xtime_lock, 142 * Although our caller may have the read side of xtime_lock,
143 * this is now a seqlock, and we are cheating in this routine 143 * this is now a seqlock, and we are cheating in this routine
@@ -183,7 +183,7 @@ static cycle_t pit_read(struct clocksource *cs)
183 old_count = count; 183 old_count = count;
184 old_jifs = jifs; 184 old_jifs = jifs;
185 185
186 spin_unlock_irqrestore(&i8253_lock, flags); 186 raw_spin_unlock_irqrestore(&i8253_lock, flags);
187 187
188 count = (LATCH - 1) - count; 188 count = (LATCH - 1) - count;
189 189
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index 44337ba03717..a5297e2a353a 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -385,7 +385,7 @@ EXPORT(sysn32_call_table)
385 PTR sys_fchmodat 385 PTR sys_fchmodat
386 PTR sys_faccessat 386 PTR sys_faccessat
387 PTR compat_sys_pselect6 387 PTR compat_sys_pselect6
388 PTR sys_ppoll /* 6265 */ 388 PTR compat_sys_ppoll /* 6265 */
389 PTR sys_unshare 389 PTR sys_unshare
390 PTR sys_splice 390 PTR sys_splice
391 PTR sys_sync_file_range 391 PTR sys_sync_file_range
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 8f2f8e9d8b21..f2338d1c0b48 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -78,6 +78,9 @@ DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
78#define FPCREG_RID 0 /* $0 = revision id */ 78#define FPCREG_RID 0 /* $0 = revision id */
79#define FPCREG_CSR 31 /* $31 = csr */ 79#define FPCREG_CSR 31 /* $31 = csr */
80 80
81/* Determine rounding mode from the RM bits of the FCSR */
82#define modeindex(v) ((v) & FPU_CSR_RM)
83
81/* Convert Mips rounding mode (0..3) to IEEE library modes. */ 84/* Convert Mips rounding mode (0..3) to IEEE library modes. */
82static const unsigned char ieee_rm[4] = { 85static const unsigned char ieee_rm[4] = {
83 [FPU_CSR_RN] = IEEE754_RN, 86 [FPU_CSR_RN] = IEEE754_RN,
@@ -384,10 +387,14 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
384 (void *) (xcp->cp0_epc), 387 (void *) (xcp->cp0_epc),
385 MIPSInst_RT(ir), value); 388 MIPSInst_RT(ir), value);
386#endif 389#endif
387 value &= (FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03); 390
388 ctx->fcr31 &= ~(FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03); 391 /*
389 /* convert to ieee library modes */ 392 * Don't write reserved bits,
390 ctx->fcr31 |= (value & ~0x3) | ieee_rm[value & 0x3]; 393 * and convert to ieee library modes
394 */
395 ctx->fcr31 = (value &
396 ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
397 ieee_rm[modeindex(value)];
391 } 398 }
392 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 399 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
393 return SIGFPE; 400 return SIGFPE;
diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c
index 29e2326b6257..fa3bf661ae29 100644
--- a/arch/mips/oprofile/op_model_loongson2.c
+++ b/arch/mips/oprofile/op_model_loongson2.c
@@ -122,7 +122,7 @@ static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
122 */ 122 */
123 123
124 /* Check whether the irq belongs to me */ 124 /* Check whether the irq belongs to me */
125 enabled = read_c0_perfcnt() & LOONGSON2_PERFCNT_INT_EN; 125 enabled = read_c0_perfctrl() & LOONGSON2_PERFCNT_INT_EN;
126 if (!enabled) 126 if (!enabled)
127 return IRQ_NONE; 127 return IRQ_NONE;
128 enabled = reg.cnt1_enabled | reg.cnt2_enabled; 128 enabled = reg.cnt1_enabled | reg.cnt2_enabled;
diff --git a/arch/mn10300/include/asm/atomic.h b/arch/mn10300/include/asm/atomic.h
index 5bf5be9566de..e41222d6c2fd 100644
--- a/arch/mn10300/include/asm/atomic.h
+++ b/arch/mn10300/include/asm/atomic.h
@@ -31,7 +31,7 @@
31 * Atomically reads the value of @v. Note that the guaranteed 31 * Atomically reads the value of @v. Note that the guaranteed
32 * useful range of an atomic_t is only 24 bits. 32 * useful range of an atomic_t is only 24 bits.
33 */ 33 */
34#define atomic_read(v) ((v)->counter) 34#define atomic_read(v) (*(volatile int *)&(v)->counter)
35 35
36/** 36/**
37 * atomic_set - set atomic variable 37 * atomic_set - set atomic variable
diff --git a/arch/parisc/include/asm/atomic.h b/arch/parisc/include/asm/atomic.h
index 716634d1f546..f81955934aeb 100644
--- a/arch/parisc/include/asm/atomic.h
+++ b/arch/parisc/include/asm/atomic.h
@@ -189,7 +189,7 @@ static __inline__ void atomic_set(atomic_t *v, int i)
189 189
190static __inline__ int atomic_read(const atomic_t *v) 190static __inline__ int atomic_read(const atomic_t *v)
191{ 191{
192 return v->counter; 192 return (*(volatile int *)&(v)->counter);
193} 193}
194 194
195/* exported interface */ 195/* exported interface */
@@ -286,7 +286,7 @@ atomic64_set(atomic64_t *v, s64 i)
286static __inline__ s64 286static __inline__ s64
287atomic64_read(const atomic64_t *v) 287atomic64_read(const atomic64_t *v)
288{ 288{
289 return v->counter; 289 return (*(volatile long *)&(v)->counter);
290} 290}
291 291
292#define atomic64_add(i,v) ((void)(__atomic64_add_return( ((s64)(i)),(v)))) 292#define atomic64_add(i,v) ((void)(__atomic64_add_return( ((s64)(i)),(v))))
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index 9f4c9d4f5803..bd100fcf40d0 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -130,43 +130,5 @@ static inline int irqs_disabled_flags(unsigned long flags)
130 */ 130 */
131struct irq_chip; 131struct irq_chip;
132 132
133#ifdef CONFIG_PERF_EVENTS
134
135#ifdef CONFIG_PPC64
136static inline unsigned long test_perf_event_pending(void)
137{
138 unsigned long x;
139
140 asm volatile("lbz %0,%1(13)"
141 : "=r" (x)
142 : "i" (offsetof(struct paca_struct, perf_event_pending)));
143 return x;
144}
145
146static inline void set_perf_event_pending(void)
147{
148 asm volatile("stb %0,%1(13)" : :
149 "r" (1),
150 "i" (offsetof(struct paca_struct, perf_event_pending)));
151}
152
153static inline void clear_perf_event_pending(void)
154{
155 asm volatile("stb %0,%1(13)" : :
156 "r" (0),
157 "i" (offsetof(struct paca_struct, perf_event_pending)));
158}
159#endif /* CONFIG_PPC64 */
160
161#else /* CONFIG_PERF_EVENTS */
162
163static inline unsigned long test_perf_event_pending(void)
164{
165 return 0;
166}
167
168static inline void clear_perf_event_pending(void) {}
169#endif /* CONFIG_PERF_EVENTS */
170
171#endif /* __KERNEL__ */ 133#endif /* __KERNEL__ */
172#endif /* _ASM_POWERPC_HW_IRQ_H */ 134#endif /* _ASM_POWERPC_HW_IRQ_H */
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 957ceb7059c5..c09138d150d4 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -133,7 +133,6 @@ int main(void)
133 DEFINE(PACAKMSR, offsetof(struct paca_struct, kernel_msr)); 133 DEFINE(PACAKMSR, offsetof(struct paca_struct, kernel_msr));
134 DEFINE(PACASOFTIRQEN, offsetof(struct paca_struct, soft_enabled)); 134 DEFINE(PACASOFTIRQEN, offsetof(struct paca_struct, soft_enabled));
135 DEFINE(PACAHARDIRQEN, offsetof(struct paca_struct, hard_enabled)); 135 DEFINE(PACAHARDIRQEN, offsetof(struct paca_struct, hard_enabled));
136 DEFINE(PACAPERFPEND, offsetof(struct paca_struct, perf_event_pending));
137 DEFINE(PACACONTEXTID, offsetof(struct paca_struct, context.id)); 136 DEFINE(PACACONTEXTID, offsetof(struct paca_struct, context.id));
138#ifdef CONFIG_PPC_MM_SLICES 137#ifdef CONFIG_PPC_MM_SLICES
139 DEFINE(PACALOWSLICESPSIZE, offsetof(struct paca_struct, 138 DEFINE(PACALOWSLICESPSIZE, offsetof(struct paca_struct,
diff --git a/arch/powerpc/kernel/dma-swiotlb.c b/arch/powerpc/kernel/dma-swiotlb.c
index 59c928564a03..4ff4da2c238b 100644
--- a/arch/powerpc/kernel/dma-swiotlb.c
+++ b/arch/powerpc/kernel/dma-swiotlb.c
@@ -1,7 +1,8 @@
1/* 1/*
2 * Contains routines needed to support swiotlb for ppc. 2 * Contains routines needed to support swiotlb for ppc.
3 * 3 *
4 * Copyright (C) 2009 Becky Bruce, Freescale Semiconductor 4 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
5 * Author: Becky Bruce
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 8 * under the terms of the GNU General Public License as published by the
@@ -70,7 +71,7 @@ static int ppc_swiotlb_bus_notify(struct notifier_block *nb,
70 sd->max_direct_dma_addr = 0; 71 sd->max_direct_dma_addr = 0;
71 72
72 /* May need to bounce if the device can't address all of DRAM */ 73 /* May need to bounce if the device can't address all of DRAM */
73 if (dma_get_mask(dev) < lmb_end_of_DRAM()) 74 if ((dma_get_mask(dev) + 1) < lmb_end_of_DRAM())
74 set_dma_ops(dev, &swiotlb_dma_ops); 75 set_dma_ops(dev, &swiotlb_dma_ops);
75 76
76 return NOTIFY_DONE; 77 return NOTIFY_DONE;
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 07109d843787..42e9d908914a 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -556,15 +556,6 @@ ALT_FW_FTR_SECTION_END_IFCLR(FW_FEATURE_ISERIES)
5562: 5562:
557 TRACE_AND_RESTORE_IRQ(r5); 557 TRACE_AND_RESTORE_IRQ(r5);
558 558
559#ifdef CONFIG_PERF_EVENTS
560 /* check paca->perf_event_pending if we're enabling ints */
561 lbz r3,PACAPERFPEND(r13)
562 and. r3,r3,r5
563 beq 27f
564 bl .perf_event_do_pending
56527:
566#endif /* CONFIG_PERF_EVENTS */
567
568 /* extract EE bit and use it to restore paca->hard_enabled */ 559 /* extract EE bit and use it to restore paca->hard_enabled */
569 ld r3,_MSR(r1) 560 ld r3,_MSR(r1)
570 rldicl r4,r3,49,63 /* r0 = (r3 >> 15) & 1 */ 561 rldicl r4,r3,49,63 /* r0 = (r3 >> 15) & 1 */
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 64f6f2031c22..066bd31551d5 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -53,7 +53,6 @@
53#include <linux/bootmem.h> 53#include <linux/bootmem.h>
54#include <linux/pci.h> 54#include <linux/pci.h>
55#include <linux/debugfs.h> 55#include <linux/debugfs.h>
56#include <linux/perf_event.h>
57 56
58#include <asm/uaccess.h> 57#include <asm/uaccess.h>
59#include <asm/system.h> 58#include <asm/system.h>
@@ -145,11 +144,6 @@ notrace void raw_local_irq_restore(unsigned long en)
145 } 144 }
146#endif /* CONFIG_PPC_STD_MMU_64 */ 145#endif /* CONFIG_PPC_STD_MMU_64 */
147 146
148 if (test_perf_event_pending()) {
149 clear_perf_event_pending();
150 perf_event_do_pending();
151 }
152
153 /* 147 /*
154 * if (get_paca()->hard_enabled) return; 148 * if (get_paca()->hard_enabled) return;
155 * But again we need to take care that gcc gets hard_enabled directly 149 * But again we need to take care that gcc gets hard_enabled directly
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 1b16b9a3e49a..0441bbdadbd1 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -532,25 +532,60 @@ void __init iSeries_time_init_early(void)
532} 532}
533#endif /* CONFIG_PPC_ISERIES */ 533#endif /* CONFIG_PPC_ISERIES */
534 534
535#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_PPC32) 535#ifdef CONFIG_PERF_EVENTS
536DEFINE_PER_CPU(u8, perf_event_pending);
537 536
538void set_perf_event_pending(void) 537/*
538 * 64-bit uses a byte in the PACA, 32-bit uses a per-cpu variable...
539 */
540#ifdef CONFIG_PPC64
541static inline unsigned long test_perf_event_pending(void)
539{ 542{
540 get_cpu_var(perf_event_pending) = 1; 543 unsigned long x;
541 set_dec(1); 544
542 put_cpu_var(perf_event_pending); 545 asm volatile("lbz %0,%1(13)"
546 : "=r" (x)
547 : "i" (offsetof(struct paca_struct, perf_event_pending)));
548 return x;
543} 549}
544 550
551static inline void set_perf_event_pending_flag(void)
552{
553 asm volatile("stb %0,%1(13)" : :
554 "r" (1),
555 "i" (offsetof(struct paca_struct, perf_event_pending)));
556}
557
558static inline void clear_perf_event_pending(void)
559{
560 asm volatile("stb %0,%1(13)" : :
561 "r" (0),
562 "i" (offsetof(struct paca_struct, perf_event_pending)));
563}
564
565#else /* 32-bit */
566
567DEFINE_PER_CPU(u8, perf_event_pending);
568
569#define set_perf_event_pending_flag() __get_cpu_var(perf_event_pending) = 1
545#define test_perf_event_pending() __get_cpu_var(perf_event_pending) 570#define test_perf_event_pending() __get_cpu_var(perf_event_pending)
546#define clear_perf_event_pending() __get_cpu_var(perf_event_pending) = 0 571#define clear_perf_event_pending() __get_cpu_var(perf_event_pending) = 0
547 572
548#else /* CONFIG_PERF_EVENTS && CONFIG_PPC32 */ 573#endif /* 32 vs 64 bit */
574
575void set_perf_event_pending(void)
576{
577 preempt_disable();
578 set_perf_event_pending_flag();
579 set_dec(1);
580 preempt_enable();
581}
582
583#else /* CONFIG_PERF_EVENTS */
549 584
550#define test_perf_event_pending() 0 585#define test_perf_event_pending() 0
551#define clear_perf_event_pending() 586#define clear_perf_event_pending()
552 587
553#endif /* CONFIG_PERF_EVENTS && CONFIG_PPC32 */ 588#endif /* CONFIG_PERF_EVENTS */
554 589
555/* 590/*
556 * For iSeries shared processors, we have to let the hypervisor 591 * For iSeries shared processors, we have to let the hypervisor
@@ -582,10 +617,6 @@ void timer_interrupt(struct pt_regs * regs)
582 set_dec(DECREMENTER_MAX); 617 set_dec(DECREMENTER_MAX);
583 618
584#ifdef CONFIG_PPC32 619#ifdef CONFIG_PPC32
585 if (test_perf_event_pending()) {
586 clear_perf_event_pending();
587 perf_event_do_pending();
588 }
589 if (atomic_read(&ppc_n_lost_interrupts) != 0) 620 if (atomic_read(&ppc_n_lost_interrupts) != 0)
590 do_IRQ(regs); 621 do_IRQ(regs);
591#endif 622#endif
@@ -604,6 +635,11 @@ void timer_interrupt(struct pt_regs * regs)
604 635
605 calculate_steal_time(); 636 calculate_steal_time();
606 637
638 if (test_perf_event_pending()) {
639 clear_perf_event_pending();
640 perf_event_do_pending();
641 }
642
607#ifdef CONFIG_PPC_ISERIES 643#ifdef CONFIG_PPC_ISERIES
608 if (firmware_has_feature(FW_FEATURE_ISERIES)) 644 if (firmware_has_feature(FW_FEATURE_ISERIES))
609 get_lppaca()->int_dword.fields.decr_int = 0; 645 get_lppaca()->int_dword.fields.decr_int = 0;
diff --git a/arch/powerpc/kvm/44x_tlb.c b/arch/powerpc/kvm/44x_tlb.c
index 2570fcc7665d..812312542e50 100644
--- a/arch/powerpc/kvm/44x_tlb.c
+++ b/arch/powerpc/kvm/44x_tlb.c
@@ -440,7 +440,7 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
440 unsigned int gtlb_index; 440 unsigned int gtlb_index;
441 441
442 gtlb_index = kvmppc_get_gpr(vcpu, ra); 442 gtlb_index = kvmppc_get_gpr(vcpu, ra);
443 if (gtlb_index > KVM44x_GUEST_TLB_SIZE) { 443 if (gtlb_index >= KVM44x_GUEST_TLB_SIZE) {
444 printk("%s: index %d\n", __func__, gtlb_index); 444 printk("%s: index %d\n", __func__, gtlb_index);
445 kvmppc_dump_vcpu(vcpu); 445 kvmppc_dump_vcpu(vcpu);
446 return EMULATE_FAIL; 446 return EMULATE_FAIL;
diff --git a/arch/s390/kernel/head31.S b/arch/s390/kernel/head31.S
index 1bbcc499d455..b8f8dc126102 100644
--- a/arch/s390/kernel/head31.S
+++ b/arch/s390/kernel/head31.S
@@ -82,7 +82,7 @@ startup_continue:
82_ehead: 82_ehead:
83 83
84#ifdef CONFIG_SHARED_KERNEL 84#ifdef CONFIG_SHARED_KERNEL
85 .org 0x100000 85 .org 0x100000 - 0x11000 # head.o ends at 0x11000
86#endif 86#endif
87 87
88# 88#
diff --git a/arch/s390/kernel/head64.S b/arch/s390/kernel/head64.S
index 1f70970de0aa..cdef68717416 100644
--- a/arch/s390/kernel/head64.S
+++ b/arch/s390/kernel/head64.S
@@ -80,7 +80,7 @@ startup_continue:
80_ehead: 80_ehead:
81 81
82#ifdef CONFIG_SHARED_KERNEL 82#ifdef CONFIG_SHARED_KERNEL
83 .org 0x100000 83 .org 0x100000 - 0x11000 # head.o ends at 0x11000
84#endif 84#endif
85 85
86# 86#
diff --git a/arch/s390/kernel/ptrace.c b/arch/s390/kernel/ptrace.c
index 33fdc5a79764..9f654da4cecc 100644
--- a/arch/s390/kernel/ptrace.c
+++ b/arch/s390/kernel/ptrace.c
@@ -640,7 +640,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
640 640
641asmlinkage long do_syscall_trace_enter(struct pt_regs *regs) 641asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
642{ 642{
643 long ret; 643 long ret = 0;
644 644
645 /* Do the secure computing check first. */ 645 /* Do the secure computing check first. */
646 secure_computing(regs->gprs[2]); 646 secure_computing(regs->gprs[2]);
@@ -649,7 +649,6 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
649 * The sysc_tracesys code in entry.S stored the system 649 * The sysc_tracesys code in entry.S stored the system
650 * call number to gprs[2]. 650 * call number to gprs[2].
651 */ 651 */
652 ret = regs->gprs[2];
653 if (test_thread_flag(TIF_SYSCALL_TRACE) && 652 if (test_thread_flag(TIF_SYSCALL_TRACE) &&
654 (tracehook_report_syscall_entry(regs) || 653 (tracehook_report_syscall_entry(regs) ||
655 regs->gprs[2] >= NR_syscalls)) { 654 regs->gprs[2] >= NR_syscalls)) {
@@ -671,7 +670,7 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
671 regs->gprs[2], regs->orig_gpr2, 670 regs->gprs[2], regs->orig_gpr2,
672 regs->gprs[3], regs->gprs[4], 671 regs->gprs[3], regs->gprs[4],
673 regs->gprs[5]); 672 regs->gprs[5]);
674 return ret; 673 return ret ?: regs->gprs[2];
675} 674}
676 675
677asmlinkage void do_syscall_trace_exit(struct pt_regs *regs) 676asmlinkage void do_syscall_trace_exit(struct pt_regs *regs)
diff --git a/arch/sh/include/asm/atomic.h b/arch/sh/include/asm/atomic.h
index 275a448ae8c2..c7983124d99d 100644
--- a/arch/sh/include/asm/atomic.h
+++ b/arch/sh/include/asm/atomic.h
@@ -13,7 +13,7 @@
13 13
14#define ATOMIC_INIT(i) ( (atomic_t) { (i) } ) 14#define ATOMIC_INIT(i) ( (atomic_t) { (i) } )
15 15
16#define atomic_read(v) ((v)->counter) 16#define atomic_read(v) (*(volatile int *)&(v)->counter)
17#define atomic_set(v,i) ((v)->counter = (i)) 17#define atomic_set(v,i) ((v)->counter = (i))
18 18
19#if defined(CONFIG_GUSA_RB) 19#if defined(CONFIG_GUSA_RB)
diff --git a/arch/sparc/include/asm/atomic_32.h b/arch/sparc/include/asm/atomic_32.h
index f0d343c3b956..7ae128b19d3f 100644
--- a/arch/sparc/include/asm/atomic_32.h
+++ b/arch/sparc/include/asm/atomic_32.h
@@ -25,7 +25,7 @@ extern int atomic_cmpxchg(atomic_t *, int, int);
25extern int atomic_add_unless(atomic_t *, int, int); 25extern int atomic_add_unless(atomic_t *, int, int);
26extern void atomic_set(atomic_t *, int); 26extern void atomic_set(atomic_t *, int);
27 27
28#define atomic_read(v) ((v)->counter) 28#define atomic_read(v) (*(volatile int *)&(v)->counter)
29 29
30#define atomic_add(i, v) ((void)__atomic_add_return( (int)(i), (v))) 30#define atomic_add(i, v) ((void)__atomic_add_return( (int)(i), (v)))
31#define atomic_sub(i, v) ((void)__atomic_add_return(-(int)(i), (v))) 31#define atomic_sub(i, v) ((void)__atomic_add_return(-(int)(i), (v)))
diff --git a/arch/sparc/include/asm/atomic_64.h b/arch/sparc/include/asm/atomic_64.h
index f2e48009989e..2050ca02c423 100644
--- a/arch/sparc/include/asm/atomic_64.h
+++ b/arch/sparc/include/asm/atomic_64.h
@@ -13,8 +13,8 @@
13#define ATOMIC_INIT(i) { (i) } 13#define ATOMIC_INIT(i) { (i) }
14#define ATOMIC64_INIT(i) { (i) } 14#define ATOMIC64_INIT(i) { (i) }
15 15
16#define atomic_read(v) ((v)->counter) 16#define atomic_read(v) (*(volatile int *)&(v)->counter)
17#define atomic64_read(v) ((v)->counter) 17#define atomic64_read(v) (*(volatile long *)&(v)->counter)
18 18
19#define atomic_set(v, i) (((v)->counter) = i) 19#define atomic_set(v, i) (((v)->counter) = i)
20#define atomic64_set(v, i) (((v)->counter) = i) 20#define atomic64_set(v, i) (((v)->counter) = i)
diff --git a/arch/x86/include/asm/amd_iommu_types.h b/arch/x86/include/asm/amd_iommu_types.h
index 86a0ff0aeac7..7014e88bc779 100644
--- a/arch/x86/include/asm/amd_iommu_types.h
+++ b/arch/x86/include/asm/amd_iommu_types.h
@@ -174,6 +174,40 @@
174 (~((1ULL << (12 + ((lvl) * 9))) - 1))) 174 (~((1ULL << (12 + ((lvl) * 9))) - 1)))
175#define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr)) 175#define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr))
176 176
177/*
178 * Returns the page table level to use for a given page size
179 * Pagesize is expected to be a power-of-two
180 */
181#define PAGE_SIZE_LEVEL(pagesize) \
182 ((__ffs(pagesize) - 12) / 9)
183/*
184 * Returns the number of ptes to use for a given page size
185 * Pagesize is expected to be a power-of-two
186 */
187#define PAGE_SIZE_PTE_COUNT(pagesize) \
188 (1ULL << ((__ffs(pagesize) - 12) % 9))
189
190/*
191 * Aligns a given io-virtual address to a given page size
192 * Pagesize is expected to be a power-of-two
193 */
194#define PAGE_SIZE_ALIGN(address, pagesize) \
195 ((address) & ~((pagesize) - 1))
196/*
197 * Creates an IOMMU PTE for an address an a given pagesize
198 * The PTE has no permission bits set
199 * Pagesize is expected to be a power-of-two larger than 4096
200 */
201#define PAGE_SIZE_PTE(address, pagesize) \
202 (((address) | ((pagesize) - 1)) & \
203 (~(pagesize >> 1)) & PM_ADDR_MASK)
204
205/*
206 * Takes a PTE value with mode=0x07 and returns the page size it maps
207 */
208#define PTE_PAGE_SIZE(pte) \
209 (1ULL << (1 + ffz(((pte) | 0xfffULL))))
210
177#define IOMMU_PTE_P (1ULL << 0) 211#define IOMMU_PTE_P (1ULL << 0)
178#define IOMMU_PTE_TV (1ULL << 1) 212#define IOMMU_PTE_TV (1ULL << 1)
179#define IOMMU_PTE_U (1ULL << 59) 213#define IOMMU_PTE_U (1ULL << 59)
diff --git a/arch/x86/include/asm/atomic.h b/arch/x86/include/asm/atomic.h
index 8f8217b9bdac..37b39d27abe0 100644
--- a/arch/x86/include/asm/atomic.h
+++ b/arch/x86/include/asm/atomic.h
@@ -22,7 +22,7 @@
22 */ 22 */
23static inline int atomic_read(const atomic_t *v) 23static inline int atomic_read(const atomic_t *v)
24{ 24{
25 return v->counter; 25 return (*(volatile int *)&(v)->counter);
26} 26}
27 27
28/** 28/**
diff --git a/arch/x86/include/asm/atomic64_64.h b/arch/x86/include/asm/atomic64_64.h
index 51c5b4056929..b014e235ea8d 100644
--- a/arch/x86/include/asm/atomic64_64.h
+++ b/arch/x86/include/asm/atomic64_64.h
@@ -18,7 +18,7 @@
18 */ 18 */
19static inline long atomic64_read(const atomic64_t *v) 19static inline long atomic64_read(const atomic64_t *v)
20{ 20{
21 return v->counter; 21 return (*(volatile long *)&(v)->counter);
22} 22}
23 23
24/** 24/**
diff --git a/arch/x86/include/asm/i8253.h b/arch/x86/include/asm/i8253.h
index 1edbf89680fd..fc1f579fb965 100644
--- a/arch/x86/include/asm/i8253.h
+++ b/arch/x86/include/asm/i8253.h
@@ -6,7 +6,7 @@
6#define PIT_CH0 0x40 6#define PIT_CH0 0x40
7#define PIT_CH2 0x42 7#define PIT_CH2 0x42
8 8
9extern spinlock_t i8253_lock; 9extern raw_spinlock_t i8253_lock;
10 10
11extern struct clock_event_device *global_clock_event; 11extern struct clock_event_device *global_clock_event;
12 12
diff --git a/arch/x86/include/asm/k8.h b/arch/x86/include/asm/k8.h
index f70e60071fe8..af00bd1d2089 100644
--- a/arch/x86/include/asm/k8.h
+++ b/arch/x86/include/asm/k8.h
@@ -16,11 +16,16 @@ extern int k8_numa_init(unsigned long start_pfn, unsigned long end_pfn);
16extern int k8_scan_nodes(void); 16extern int k8_scan_nodes(void);
17 17
18#ifdef CONFIG_K8_NB 18#ifdef CONFIG_K8_NB
19extern int num_k8_northbridges;
20
19static inline struct pci_dev *node_to_k8_nb_misc(int node) 21static inline struct pci_dev *node_to_k8_nb_misc(int node)
20{ 22{
21 return (node < num_k8_northbridges) ? k8_northbridges[node] : NULL; 23 return (node < num_k8_northbridges) ? k8_northbridges[node] : NULL;
22} 24}
25
23#else 26#else
27#define num_k8_northbridges 0
28
24static inline struct pci_dev *node_to_k8_nb_misc(int node) 29static inline struct pci_dev *node_to_k8_nb_misc(int node)
25{ 30{
26 return NULL; 31 return NULL;
diff --git a/arch/x86/kernel/amd_iommu.c b/arch/x86/kernel/amd_iommu.c
index f854d89b7edf..fa5a1474cd18 100644
--- a/arch/x86/kernel/amd_iommu.c
+++ b/arch/x86/kernel/amd_iommu.c
@@ -731,18 +731,22 @@ static bool increase_address_space(struct protection_domain *domain,
731 731
732static u64 *alloc_pte(struct protection_domain *domain, 732static u64 *alloc_pte(struct protection_domain *domain,
733 unsigned long address, 733 unsigned long address,
734 int end_lvl, 734 unsigned long page_size,
735 u64 **pte_page, 735 u64 **pte_page,
736 gfp_t gfp) 736 gfp_t gfp)
737{ 737{
738 int level, end_lvl;
738 u64 *pte, *page; 739 u64 *pte, *page;
739 int level; 740
741 BUG_ON(!is_power_of_2(page_size));
740 742
741 while (address > PM_LEVEL_SIZE(domain->mode)) 743 while (address > PM_LEVEL_SIZE(domain->mode))
742 increase_address_space(domain, gfp); 744 increase_address_space(domain, gfp);
743 745
744 level = domain->mode - 1; 746 level = domain->mode - 1;
745 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; 747 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
748 address = PAGE_SIZE_ALIGN(address, page_size);
749 end_lvl = PAGE_SIZE_LEVEL(page_size);
746 750
747 while (level > end_lvl) { 751 while (level > end_lvl) {
748 if (!IOMMU_PTE_PRESENT(*pte)) { 752 if (!IOMMU_PTE_PRESENT(*pte)) {
@@ -752,6 +756,10 @@ static u64 *alloc_pte(struct protection_domain *domain,
752 *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); 756 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
753 } 757 }
754 758
759 /* No level skipping support yet */
760 if (PM_PTE_LEVEL(*pte) != level)
761 return NULL;
762
755 level -= 1; 763 level -= 1;
756 764
757 pte = IOMMU_PTE_PAGE(*pte); 765 pte = IOMMU_PTE_PAGE(*pte);
@@ -769,28 +777,47 @@ static u64 *alloc_pte(struct protection_domain *domain,
769 * This function checks if there is a PTE for a given dma address. If 777 * This function checks if there is a PTE for a given dma address. If
770 * there is one, it returns the pointer to it. 778 * there is one, it returns the pointer to it.
771 */ 779 */
772static u64 *fetch_pte(struct protection_domain *domain, 780static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
773 unsigned long address, int map_size)
774{ 781{
775 int level; 782 int level;
776 u64 *pte; 783 u64 *pte;
777 784
778 level = domain->mode - 1; 785 if (address > PM_LEVEL_SIZE(domain->mode))
779 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; 786 return NULL;
787
788 level = domain->mode - 1;
789 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
780 790
781 while (level > map_size) { 791 while (level > 0) {
792
793 /* Not Present */
782 if (!IOMMU_PTE_PRESENT(*pte)) 794 if (!IOMMU_PTE_PRESENT(*pte))
783 return NULL; 795 return NULL;
784 796
797 /* Large PTE */
798 if (PM_PTE_LEVEL(*pte) == 0x07) {
799 unsigned long pte_mask, __pte;
800
801 /*
802 * If we have a series of large PTEs, make
803 * sure to return a pointer to the first one.
804 */
805 pte_mask = PTE_PAGE_SIZE(*pte);
806 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
807 __pte = ((unsigned long)pte) & pte_mask;
808
809 return (u64 *)__pte;
810 }
811
812 /* No level skipping support yet */
813 if (PM_PTE_LEVEL(*pte) != level)
814 return NULL;
815
785 level -= 1; 816 level -= 1;
786 817
818 /* Walk to the next level */
787 pte = IOMMU_PTE_PAGE(*pte); 819 pte = IOMMU_PTE_PAGE(*pte);
788 pte = &pte[PM_LEVEL_INDEX(level, address)]; 820 pte = &pte[PM_LEVEL_INDEX(level, address)];
789
790 if ((PM_PTE_LEVEL(*pte) == 0) && level != map_size) {
791 pte = NULL;
792 break;
793 }
794 } 821 }
795 822
796 return pte; 823 return pte;
@@ -807,44 +834,84 @@ static int iommu_map_page(struct protection_domain *dom,
807 unsigned long bus_addr, 834 unsigned long bus_addr,
808 unsigned long phys_addr, 835 unsigned long phys_addr,
809 int prot, 836 int prot,
810 int map_size) 837 unsigned long page_size)
811{ 838{
812 u64 __pte, *pte; 839 u64 __pte, *pte;
813 840 int i, count;
814 bus_addr = PAGE_ALIGN(bus_addr);
815 phys_addr = PAGE_ALIGN(phys_addr);
816
817 BUG_ON(!PM_ALIGNED(map_size, bus_addr));
818 BUG_ON(!PM_ALIGNED(map_size, phys_addr));
819 841
820 if (!(prot & IOMMU_PROT_MASK)) 842 if (!(prot & IOMMU_PROT_MASK))
821 return -EINVAL; 843 return -EINVAL;
822 844
823 pte = alloc_pte(dom, bus_addr, map_size, NULL, GFP_KERNEL); 845 bus_addr = PAGE_ALIGN(bus_addr);
846 phys_addr = PAGE_ALIGN(phys_addr);
847 count = PAGE_SIZE_PTE_COUNT(page_size);
848 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
849
850 for (i = 0; i < count; ++i)
851 if (IOMMU_PTE_PRESENT(pte[i]))
852 return -EBUSY;
824 853
825 if (IOMMU_PTE_PRESENT(*pte)) 854 if (page_size > PAGE_SIZE) {
826 return -EBUSY; 855 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
856 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
857 } else
858 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
827 859
828 __pte = phys_addr | IOMMU_PTE_P;
829 if (prot & IOMMU_PROT_IR) 860 if (prot & IOMMU_PROT_IR)
830 __pte |= IOMMU_PTE_IR; 861 __pte |= IOMMU_PTE_IR;
831 if (prot & IOMMU_PROT_IW) 862 if (prot & IOMMU_PROT_IW)
832 __pte |= IOMMU_PTE_IW; 863 __pte |= IOMMU_PTE_IW;
833 864
834 *pte = __pte; 865 for (i = 0; i < count; ++i)
866 pte[i] = __pte;
835 867
836 update_domain(dom); 868 update_domain(dom);
837 869
838 return 0; 870 return 0;
839} 871}
840 872
841static void iommu_unmap_page(struct protection_domain *dom, 873static unsigned long iommu_unmap_page(struct protection_domain *dom,
842 unsigned long bus_addr, int map_size) 874 unsigned long bus_addr,
875 unsigned long page_size)
843{ 876{
844 u64 *pte = fetch_pte(dom, bus_addr, map_size); 877 unsigned long long unmap_size, unmapped;
878 u64 *pte;
879
880 BUG_ON(!is_power_of_2(page_size));
881
882 unmapped = 0;
845 883
846 if (pte) 884 while (unmapped < page_size) {
847 *pte = 0; 885
886 pte = fetch_pte(dom, bus_addr);
887
888 if (!pte) {
889 /*
890 * No PTE for this address
891 * move forward in 4kb steps
892 */
893 unmap_size = PAGE_SIZE;
894 } else if (PM_PTE_LEVEL(*pte) == 0) {
895 /* 4kb PTE found for this address */
896 unmap_size = PAGE_SIZE;
897 *pte = 0ULL;
898 } else {
899 int count, i;
900
901 /* Large PTE found which maps this address */
902 unmap_size = PTE_PAGE_SIZE(*pte);
903 count = PAGE_SIZE_PTE_COUNT(unmap_size);
904 for (i = 0; i < count; i++)
905 pte[i] = 0ULL;
906 }
907
908 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
909 unmapped += unmap_size;
910 }
911
912 BUG_ON(!is_power_of_2(unmapped));
913
914 return unmapped;
848} 915}
849 916
850/* 917/*
@@ -878,7 +945,7 @@ static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
878 for (addr = e->address_start; addr < e->address_end; 945 for (addr = e->address_start; addr < e->address_end;
879 addr += PAGE_SIZE) { 946 addr += PAGE_SIZE) {
880 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, 947 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
881 PM_MAP_4k); 948 PAGE_SIZE);
882 if (ret) 949 if (ret)
883 return ret; 950 return ret;
884 /* 951 /*
@@ -1006,7 +1073,7 @@ static int alloc_new_range(struct dma_ops_domain *dma_dom,
1006 u64 *pte, *pte_page; 1073 u64 *pte, *pte_page;
1007 1074
1008 for (i = 0; i < num_ptes; ++i) { 1075 for (i = 0; i < num_ptes; ++i) {
1009 pte = alloc_pte(&dma_dom->domain, address, PM_MAP_4k, 1076 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1010 &pte_page, gfp); 1077 &pte_page, gfp);
1011 if (!pte) 1078 if (!pte)
1012 goto out_free; 1079 goto out_free;
@@ -1042,7 +1109,7 @@ static int alloc_new_range(struct dma_ops_domain *dma_dom,
1042 for (i = dma_dom->aperture[index]->offset; 1109 for (i = dma_dom->aperture[index]->offset;
1043 i < dma_dom->aperture_size; 1110 i < dma_dom->aperture_size;
1044 i += PAGE_SIZE) { 1111 i += PAGE_SIZE) {
1045 u64 *pte = fetch_pte(&dma_dom->domain, i, PM_MAP_4k); 1112 u64 *pte = fetch_pte(&dma_dom->domain, i);
1046 if (!pte || !IOMMU_PTE_PRESENT(*pte)) 1113 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1047 continue; 1114 continue;
1048 1115
@@ -1712,7 +1779,7 @@ static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1712 1779
1713 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; 1780 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1714 if (!pte) { 1781 if (!pte) {
1715 pte = alloc_pte(&dom->domain, address, PM_MAP_4k, &pte_page, 1782 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
1716 GFP_ATOMIC); 1783 GFP_ATOMIC);
1717 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; 1784 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1718 } else 1785 } else
@@ -2439,12 +2506,11 @@ static int amd_iommu_attach_device(struct iommu_domain *dom,
2439 return ret; 2506 return ret;
2440} 2507}
2441 2508
2442static int amd_iommu_map_range(struct iommu_domain *dom, 2509static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2443 unsigned long iova, phys_addr_t paddr, 2510 phys_addr_t paddr, int gfp_order, int iommu_prot)
2444 size_t size, int iommu_prot)
2445{ 2511{
2512 unsigned long page_size = 0x1000UL << gfp_order;
2446 struct protection_domain *domain = dom->priv; 2513 struct protection_domain *domain = dom->priv;
2447 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
2448 int prot = 0; 2514 int prot = 0;
2449 int ret; 2515 int ret;
2450 2516
@@ -2453,61 +2519,50 @@ static int amd_iommu_map_range(struct iommu_domain *dom,
2453 if (iommu_prot & IOMMU_WRITE) 2519 if (iommu_prot & IOMMU_WRITE)
2454 prot |= IOMMU_PROT_IW; 2520 prot |= IOMMU_PROT_IW;
2455 2521
2456 iova &= PAGE_MASK;
2457 paddr &= PAGE_MASK;
2458
2459 mutex_lock(&domain->api_lock); 2522 mutex_lock(&domain->api_lock);
2460 2523 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
2461 for (i = 0; i < npages; ++i) {
2462 ret = iommu_map_page(domain, iova, paddr, prot, PM_MAP_4k);
2463 if (ret)
2464 return ret;
2465
2466 iova += PAGE_SIZE;
2467 paddr += PAGE_SIZE;
2468 }
2469
2470 mutex_unlock(&domain->api_lock); 2524 mutex_unlock(&domain->api_lock);
2471 2525
2472 return 0; 2526 return ret;
2473} 2527}
2474 2528
2475static void amd_iommu_unmap_range(struct iommu_domain *dom, 2529static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
2476 unsigned long iova, size_t size) 2530 int gfp_order)
2477{ 2531{
2478
2479 struct protection_domain *domain = dom->priv; 2532 struct protection_domain *domain = dom->priv;
2480 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); 2533 unsigned long page_size, unmap_size;
2481 2534
2482 iova &= PAGE_MASK; 2535 page_size = 0x1000UL << gfp_order;
2483 2536
2484 mutex_lock(&domain->api_lock); 2537 mutex_lock(&domain->api_lock);
2485 2538 unmap_size = iommu_unmap_page(domain, iova, page_size);
2486 for (i = 0; i < npages; ++i) { 2539 mutex_unlock(&domain->api_lock);
2487 iommu_unmap_page(domain, iova, PM_MAP_4k);
2488 iova += PAGE_SIZE;
2489 }
2490 2540
2491 iommu_flush_tlb_pde(domain); 2541 iommu_flush_tlb_pde(domain);
2492 2542
2493 mutex_unlock(&domain->api_lock); 2543 return get_order(unmap_size);
2494} 2544}
2495 2545
2496static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, 2546static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2497 unsigned long iova) 2547 unsigned long iova)
2498{ 2548{
2499 struct protection_domain *domain = dom->priv; 2549 struct protection_domain *domain = dom->priv;
2500 unsigned long offset = iova & ~PAGE_MASK; 2550 unsigned long offset_mask;
2501 phys_addr_t paddr; 2551 phys_addr_t paddr;
2502 u64 *pte; 2552 u64 *pte, __pte;
2503 2553
2504 pte = fetch_pte(domain, iova, PM_MAP_4k); 2554 pte = fetch_pte(domain, iova);
2505 2555
2506 if (!pte || !IOMMU_PTE_PRESENT(*pte)) 2556 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2507 return 0; 2557 return 0;
2508 2558
2509 paddr = *pte & IOMMU_PAGE_MASK; 2559 if (PM_PTE_LEVEL(*pte) == 0)
2510 paddr |= offset; 2560 offset_mask = PAGE_SIZE - 1;
2561 else
2562 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
2563
2564 __pte = *pte & PM_ADDR_MASK;
2565 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
2511 2566
2512 return paddr; 2567 return paddr;
2513} 2568}
@@ -2523,8 +2578,8 @@ static struct iommu_ops amd_iommu_ops = {
2523 .domain_destroy = amd_iommu_domain_destroy, 2578 .domain_destroy = amd_iommu_domain_destroy,
2524 .attach_dev = amd_iommu_attach_device, 2579 .attach_dev = amd_iommu_attach_device,
2525 .detach_dev = amd_iommu_detach_device, 2580 .detach_dev = amd_iommu_detach_device,
2526 .map = amd_iommu_map_range, 2581 .map = amd_iommu_map,
2527 .unmap = amd_iommu_unmap_range, 2582 .unmap = amd_iommu_unmap,
2528 .iova_to_phys = amd_iommu_iova_to_phys, 2583 .iova_to_phys = amd_iommu_iova_to_phys,
2529 .domain_has_cap = amd_iommu_domain_has_cap, 2584 .domain_has_cap = amd_iommu_domain_has_cap,
2530}; 2585};
diff --git a/arch/x86/kernel/amd_iommu_init.c b/arch/x86/kernel/amd_iommu_init.c
index 6360abf993d4..3bacb4d0844c 100644
--- a/arch/x86/kernel/amd_iommu_init.c
+++ b/arch/x86/kernel/amd_iommu_init.c
@@ -120,6 +120,7 @@ struct ivmd_header {
120bool amd_iommu_dump; 120bool amd_iommu_dump;
121 121
122static int __initdata amd_iommu_detected; 122static int __initdata amd_iommu_detected;
123static bool __initdata amd_iommu_disabled;
123 124
124u16 amd_iommu_last_bdf; /* largest PCI device id we have 125u16 amd_iommu_last_bdf; /* largest PCI device id we have
125 to handle */ 126 to handle */
@@ -1372,6 +1373,9 @@ void __init amd_iommu_detect(void)
1372 if (no_iommu || (iommu_detected && !gart_iommu_aperture)) 1373 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
1373 return; 1374 return;
1374 1375
1376 if (amd_iommu_disabled)
1377 return;
1378
1375 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) { 1379 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
1376 iommu_detected = 1; 1380 iommu_detected = 1;
1377 amd_iommu_detected = 1; 1381 amd_iommu_detected = 1;
@@ -1401,6 +1405,8 @@ static int __init parse_amd_iommu_options(char *str)
1401 for (; *str; ++str) { 1405 for (; *str; ++str) {
1402 if (strncmp(str, "fullflush", 9) == 0) 1406 if (strncmp(str, "fullflush", 9) == 0)
1403 amd_iommu_unmap_flush = true; 1407 amd_iommu_unmap_flush = true;
1408 if (strncmp(str, "off", 3) == 0)
1409 amd_iommu_disabled = true;
1404 } 1410 }
1405 1411
1406 return 1; 1412 return 1;
diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c
index 031aa887b0eb..c4f9182ca3ac 100644
--- a/arch/x86/kernel/apm_32.c
+++ b/arch/x86/kernel/apm_32.c
@@ -1224,7 +1224,7 @@ static void reinit_timer(void)
1224#ifdef INIT_TIMER_AFTER_SUSPEND 1224#ifdef INIT_TIMER_AFTER_SUSPEND
1225 unsigned long flags; 1225 unsigned long flags;
1226 1226
1227 spin_lock_irqsave(&i8253_lock, flags); 1227 raw_spin_lock_irqsave(&i8253_lock, flags);
1228 /* set the clock to HZ */ 1228 /* set the clock to HZ */
1229 outb_pit(0x34, PIT_MODE); /* binary, mode 2, LSB/MSB, ch 0 */ 1229 outb_pit(0x34, PIT_MODE); /* binary, mode 2, LSB/MSB, ch 0 */
1230 udelay(10); 1230 udelay(10);
@@ -1232,7 +1232,7 @@ static void reinit_timer(void)
1232 udelay(10); 1232 udelay(10);
1233 outb_pit(LATCH >> 8, PIT_CH0); /* MSB */ 1233 outb_pit(LATCH >> 8, PIT_CH0); /* MSB */
1234 udelay(10); 1234 udelay(10);
1235 spin_unlock_irqrestore(&i8253_lock, flags); 1235 raw_spin_unlock_irqrestore(&i8253_lock, flags);
1236#endif 1236#endif
1237} 1237}
1238 1238
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index b3eeb66c0a51..95962a93f99a 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -340,6 +340,10 @@ amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
340 (boot_cpu_data.x86_mask < 0x1))) 340 (boot_cpu_data.x86_mask < 0x1)))
341 return; 341 return;
342 342
343 /* not in virtualized environments */
344 if (num_k8_northbridges == 0)
345 return;
346
343 this_leaf->can_disable = true; 347 this_leaf->can_disable = true;
344 this_leaf->l3_indices = amd_calc_l3_indices(); 348 this_leaf->l3_indices = amd_calc_l3_indices();
345} 349}
diff --git a/arch/x86/kernel/i8253.c b/arch/x86/kernel/i8253.c
index 23c167925a5c..2dfd31597443 100644
--- a/arch/x86/kernel/i8253.c
+++ b/arch/x86/kernel/i8253.c
@@ -16,7 +16,7 @@
16#include <asm/hpet.h> 16#include <asm/hpet.h>
17#include <asm/smp.h> 17#include <asm/smp.h>
18 18
19DEFINE_SPINLOCK(i8253_lock); 19DEFINE_RAW_SPINLOCK(i8253_lock);
20EXPORT_SYMBOL(i8253_lock); 20EXPORT_SYMBOL(i8253_lock);
21 21
22/* 22/*
@@ -33,7 +33,7 @@ struct clock_event_device *global_clock_event;
33static void init_pit_timer(enum clock_event_mode mode, 33static void init_pit_timer(enum clock_event_mode mode,
34 struct clock_event_device *evt) 34 struct clock_event_device *evt)
35{ 35{
36 spin_lock(&i8253_lock); 36 raw_spin_lock(&i8253_lock);
37 37
38 switch (mode) { 38 switch (mode) {
39 case CLOCK_EVT_MODE_PERIODIC: 39 case CLOCK_EVT_MODE_PERIODIC:
@@ -62,7 +62,7 @@ static void init_pit_timer(enum clock_event_mode mode,
62 /* Nothing to do here */ 62 /* Nothing to do here */
63 break; 63 break;
64 } 64 }
65 spin_unlock(&i8253_lock); 65 raw_spin_unlock(&i8253_lock);
66} 66}
67 67
68/* 68/*
@@ -72,10 +72,10 @@ static void init_pit_timer(enum clock_event_mode mode,
72 */ 72 */
73static int pit_next_event(unsigned long delta, struct clock_event_device *evt) 73static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
74{ 74{
75 spin_lock(&i8253_lock); 75 raw_spin_lock(&i8253_lock);
76 outb_pit(delta & 0xff , PIT_CH0); /* LSB */ 76 outb_pit(delta & 0xff , PIT_CH0); /* LSB */
77 outb_pit(delta >> 8 , PIT_CH0); /* MSB */ 77 outb_pit(delta >> 8 , PIT_CH0); /* MSB */
78 spin_unlock(&i8253_lock); 78 raw_spin_unlock(&i8253_lock);
79 79
80 return 0; 80 return 0;
81} 81}
@@ -130,7 +130,7 @@ static cycle_t pit_read(struct clocksource *cs)
130 int count; 130 int count;
131 u32 jifs; 131 u32 jifs;
132 132
133 spin_lock_irqsave(&i8253_lock, flags); 133 raw_spin_lock_irqsave(&i8253_lock, flags);
134 /* 134 /*
135 * Although our caller may have the read side of xtime_lock, 135 * Although our caller may have the read side of xtime_lock,
136 * this is now a seqlock, and we are cheating in this routine 136 * this is now a seqlock, and we are cheating in this routine
@@ -176,7 +176,7 @@ static cycle_t pit_read(struct clocksource *cs)
176 old_count = count; 176 old_count = count;
177 old_jifs = jifs; 177 old_jifs = jifs;
178 178
179 spin_unlock_irqrestore(&i8253_lock, flags); 179 raw_spin_unlock_irqrestore(&i8253_lock, flags);
180 180
181 count = (LATCH - 1) - count; 181 count = (LATCH - 1) - count;
182 182
diff --git a/arch/x86/kernel/kprobes.c b/arch/x86/kernel/kprobes.c
index b43bbaebe2c0..1658efdfb4e5 100644
--- a/arch/x86/kernel/kprobes.c
+++ b/arch/x86/kernel/kprobes.c
@@ -534,20 +534,6 @@ static int __kprobes kprobe_handler(struct pt_regs *regs)
534 struct kprobe_ctlblk *kcb; 534 struct kprobe_ctlblk *kcb;
535 535
536 addr = (kprobe_opcode_t *)(regs->ip - sizeof(kprobe_opcode_t)); 536 addr = (kprobe_opcode_t *)(regs->ip - sizeof(kprobe_opcode_t));
537 if (*addr != BREAKPOINT_INSTRUCTION) {
538 /*
539 * The breakpoint instruction was removed right
540 * after we hit it. Another cpu has removed
541 * either a probepoint or a debugger breakpoint
542 * at this address. In either case, no further
543 * handling of this interrupt is appropriate.
544 * Back up over the (now missing) int3 and run
545 * the original instruction.
546 */
547 regs->ip = (unsigned long)addr;
548 return 1;
549 }
550
551 /* 537 /*
552 * We don't want to be preempted for the entire 538 * We don't want to be preempted for the entire
553 * duration of kprobe processing. We conditionally 539 * duration of kprobe processing. We conditionally
@@ -579,6 +565,19 @@ static int __kprobes kprobe_handler(struct pt_regs *regs)
579 setup_singlestep(p, regs, kcb, 0); 565 setup_singlestep(p, regs, kcb, 0);
580 return 1; 566 return 1;
581 } 567 }
568 } else if (*addr != BREAKPOINT_INSTRUCTION) {
569 /*
570 * The breakpoint instruction was removed right
571 * after we hit it. Another cpu has removed
572 * either a probepoint or a debugger breakpoint
573 * at this address. In either case, no further
574 * handling of this interrupt is appropriate.
575 * Back up over the (now missing) int3 and run
576 * the original instruction.
577 */
578 regs->ip = (unsigned long)addr;
579 preempt_enable_no_resched();
580 return 1;
582 } else if (kprobe_running()) { 581 } else if (kprobe_running()) {
583 p = __get_cpu_var(current_kprobe); 582 p = __get_cpu_var(current_kprobe);
584 if (p->break_handler && p->break_handler(p, regs)) { 583 if (p->break_handler && p->break_handler(p, regs)) {
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 28ad9f4d8b94..0415c3ef91b5 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -546,11 +546,13 @@ static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
546 * check OSVW bit for CPUs that are not affected 546 * check OSVW bit for CPUs that are not affected
547 * by erratum #400 547 * by erratum #400
548 */ 548 */
549 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, val); 549 if (cpu_has(c, X86_FEATURE_OSVW)) {
550 if (val >= 2) { 550 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, val);
551 rdmsrl(MSR_AMD64_OSVW_STATUS, val); 551 if (val >= 2) {
552 if (!(val & BIT(1))) 552 rdmsrl(MSR_AMD64_OSVW_STATUS, val);
553 goto no_c1e_idle; 553 if (!(val & BIT(1)))
554 goto no_c1e_idle;
555 }
554 } 556 }
555 return 1; 557 return 1;
556 } 558 }
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 2ba58206812a..737361fcd503 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -2067,7 +2067,7 @@ static int cpuid_interception(struct vcpu_svm *svm)
2067static int iret_interception(struct vcpu_svm *svm) 2067static int iret_interception(struct vcpu_svm *svm)
2068{ 2068{
2069 ++svm->vcpu.stat.nmi_window_exits; 2069 ++svm->vcpu.stat.nmi_window_exits;
2070 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET); 2070 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2071 svm->vcpu.arch.hflags |= HF_IRET_MASK; 2071 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2072 return 1; 2072 return 1;
2073} 2073}
@@ -2479,7 +2479,7 @@ static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2479 2479
2480 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; 2480 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2481 vcpu->arch.hflags |= HF_NMI_MASK; 2481 vcpu->arch.hflags |= HF_NMI_MASK;
2482 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET); 2482 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
2483 ++vcpu->stat.nmi_injections; 2483 ++vcpu->stat.nmi_injections;
2484} 2484}
2485 2485
@@ -2539,10 +2539,10 @@ static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2539 2539
2540 if (masked) { 2540 if (masked) {
2541 svm->vcpu.arch.hflags |= HF_NMI_MASK; 2541 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2542 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET); 2542 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
2543 } else { 2543 } else {
2544 svm->vcpu.arch.hflags &= ~HF_NMI_MASK; 2544 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2545 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET); 2545 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2546 } 2546 }
2547} 2547}
2548 2548
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index bc933cfb4e66..2f8db0ec8ae4 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -2703,8 +2703,7 @@ static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2703 return 0; 2703 return 0;
2704 2704
2705 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 2705 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2706 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS | 2706 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
2707 GUEST_INTR_STATE_NMI));
2708} 2707}
2709 2708
2710static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) 2709static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 3c4ca98ad27f..c4f35b545c1d 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1712,6 +1712,7 @@ static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1712 if (copy_from_user(cpuid_entries, entries, 1712 if (copy_from_user(cpuid_entries, entries,
1713 cpuid->nent * sizeof(struct kvm_cpuid_entry))) 1713 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1714 goto out_free; 1714 goto out_free;
1715 vcpu_load(vcpu);
1715 for (i = 0; i < cpuid->nent; i++) { 1716 for (i = 0; i < cpuid->nent; i++) {
1716 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function; 1717 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1717 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax; 1718 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
@@ -1729,6 +1730,7 @@ static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1729 r = 0; 1730 r = 0;
1730 kvm_apic_set_version(vcpu); 1731 kvm_apic_set_version(vcpu);
1731 kvm_x86_ops->cpuid_update(vcpu); 1732 kvm_x86_ops->cpuid_update(vcpu);
1733 vcpu_put(vcpu);
1732 1734
1733out_free: 1735out_free:
1734 vfree(cpuid_entries); 1736 vfree(cpuid_entries);
@@ -1749,9 +1751,11 @@ static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
1749 if (copy_from_user(&vcpu->arch.cpuid_entries, entries, 1751 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
1750 cpuid->nent * sizeof(struct kvm_cpuid_entry2))) 1752 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
1751 goto out; 1753 goto out;
1754 vcpu_load(vcpu);
1752 vcpu->arch.cpuid_nent = cpuid->nent; 1755 vcpu->arch.cpuid_nent = cpuid->nent;
1753 kvm_apic_set_version(vcpu); 1756 kvm_apic_set_version(vcpu);
1754 kvm_x86_ops->cpuid_update(vcpu); 1757 kvm_x86_ops->cpuid_update(vcpu);
1758 vcpu_put(vcpu);
1755 return 0; 1759 return 0;
1756 1760
1757out: 1761out:
diff --git a/arch/x86/mm/srat_64.c b/arch/x86/mm/srat_64.c
index 28c68762648f..38512d0c4742 100644
--- a/arch/x86/mm/srat_64.c
+++ b/arch/x86/mm/srat_64.c
@@ -461,7 +461,8 @@ void __init acpi_fake_nodes(const struct bootnode *fake_nodes, int num_nodes)
461 * node, it must now point to the fake node ID. 461 * node, it must now point to the fake node ID.
462 */ 462 */
463 for (j = 0; j < MAX_LOCAL_APIC; j++) 463 for (j = 0; j < MAX_LOCAL_APIC; j++)
464 if (apicid_to_node[j] == nid) 464 if (apicid_to_node[j] == nid &&
465 fake_apicid_to_node[j] == NUMA_NO_NODE)
465 fake_apicid_to_node[j] = i; 466 fake_apicid_to_node[j] = i;
466 } 467 }
467 for (i = 0; i < num_nodes; i++) 468 for (i = 0; i < num_nodes; i++)
diff --git a/arch/x86/pci/mrst.c b/arch/x86/pci/mrst.c
index 8bf2fcb88d04..1cdc02cf8fa4 100644
--- a/arch/x86/pci/mrst.c
+++ b/arch/x86/pci/mrst.c
@@ -247,6 +247,10 @@ static void __devinit pci_fixed_bar_fixup(struct pci_dev *dev)
247 u32 size; 247 u32 size;
248 int i; 248 int i;
249 249
250 /* Must have extended configuration space */
251 if (dev->cfg_size < PCIE_CAP_OFFSET + 4)
252 return;
253
250 /* Fixup the BAR sizes for fixed BAR devices and make them unmoveable */ 254 /* Fixup the BAR sizes for fixed BAR devices and make them unmoveable */
251 offset = fixed_bar_cap(dev->bus, dev->devfn); 255 offset = fixed_bar_cap(dev->bus, dev->devfn);
252 if (!offset || PCI_DEVFN(2, 0) == dev->devfn || 256 if (!offset || PCI_DEVFN(2, 0) == dev->devfn ||
diff --git a/arch/xtensa/include/asm/atomic.h b/arch/xtensa/include/asm/atomic.h
index 22d6dde42619..a96a0619d0b7 100644
--- a/arch/xtensa/include/asm/atomic.h
+++ b/arch/xtensa/include/asm/atomic.h
@@ -46,7 +46,7 @@
46 * 46 *
47 * Atomically reads the value of @v. 47 * Atomically reads the value of @v.
48 */ 48 */
49#define atomic_read(v) ((v)->counter) 49#define atomic_read(v) (*(volatile int *)&(v)->counter)
50 50
51/** 51/**
52 * atomic_set - set atomic variable 52 * atomic_set - set atomic variable
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 13:52:24 -0500