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-rw-r--r--arch/arm/mach-omap1/Makefile4
-rw-r--r--arch/arm/mach-omap1/include/mach/lcd_dma.h78
-rw-r--r--arch/arm/mach-omap1/lcd_dma.c447
-rw-r--r--arch/arm/plat-omap/dma.c410
-rw-r--r--arch/arm/plat-omap/include/plat/dma.h60
5 files changed, 541 insertions, 458 deletions
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 191e0cf6ee95..9ce17f13d3f1 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -52,3 +52,7 @@ led-$(CONFIG_MACH_OMAP_INNOVATOR) += leds-innovator.o
52led-$(CONFIG_MACH_OMAP_PERSEUS2) += leds-h2p2-debug.o 52led-$(CONFIG_MACH_OMAP_PERSEUS2) += leds-h2p2-debug.o
53led-$(CONFIG_MACH_OMAP_OSK) += leds-osk.o 53led-$(CONFIG_MACH_OMAP_OSK) += leds-osk.o
54obj-$(CONFIG_LEDS) += $(led-y) 54obj-$(CONFIG_LEDS) += $(led-y)
55
56ifneq ($(CONFIG_FB_OMAP),)
57obj-y += lcd_dma.o
58endif
diff --git a/arch/arm/mach-omap1/include/mach/lcd_dma.h b/arch/arm/mach-omap1/include/mach/lcd_dma.h
new file mode 100644
index 000000000000..d7a457bbcb7f
--- /dev/null
+++ b/arch/arm/mach-omap1/include/mach/lcd_dma.h
@@ -0,0 +1,78 @@
1/*
2 * arch/arm/mach-omap1/include/mach/lcd_dma.h
3 *
4 * Extracted from arch/arm/plat-omap/include/plat/dma.h
5 * Copyright (C) 2003 Nokia Corporation
6 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22#ifndef __MACH_OMAP1_LCD_DMA_H__
23#define __MACH_OMAP1_LCD_DMA_H__
24
25/* Hardware registers for LCD DMA */
26#define OMAP1510_DMA_LCD_BASE (0xfffedb00)
27#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)
28#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02)
29#define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04)
30#define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06)
31#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08)
32
33#define OMAP1610_DMA_LCD_BASE (0xfffee300)
34#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0)
35#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2)
36#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4)
37#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8)
38#define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca)
39#define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc)
40#define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce)
41#define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0)
42#define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2)
43#define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4)
44#define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6)
45#define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8)
46#define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda)
47#define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0)
48#define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4)
49#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
50#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
51
52/* LCD DMA block numbers */
53enum {
54 OMAP_LCD_DMA_B1_TOP,
55 OMAP_LCD_DMA_B1_BOTTOM,
56 OMAP_LCD_DMA_B2_TOP,
57 OMAP_LCD_DMA_B2_BOTTOM
58};
59
60/* LCD DMA functions */
61extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
62 void *data);
63extern void omap_free_lcd_dma(void);
64extern void omap_setup_lcd_dma(void);
65extern void omap_enable_lcd_dma(void);
66extern void omap_stop_lcd_dma(void);
67extern void omap_set_lcd_dma_ext_controller(int external);
68extern void omap_set_lcd_dma_single_transfer(int single);
69extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
70 int data_type);
71extern void omap_set_lcd_dma_b1_rotation(int rotate);
72extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
73extern void omap_set_lcd_dma_b1_mirror(int mirror);
74extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
75
76extern int omap_lcd_dma_running(void);
77
78#endif /* __MACH_OMAP1_LCD_DMA_H__ */
diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c
new file mode 100644
index 000000000000..48895140695f
--- /dev/null
+++ b/arch/arm/mach-omap1/lcd_dma.c
@@ -0,0 +1,447 @@
1/*
2 * linux/arch/arm/mach-omap1/lcd_dma.c
3 *
4 * Extracted from arch/arm/plat-omap/dma.c
5 * Copyright (C) 2003 - 2008 Nokia Corporation
6 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
7 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
8 * Graphics DMA and LCD DMA graphics tranformations
9 * by Imre Deak <imre.deak@nokia.com>
10 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
11 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
12 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 *
14 * Copyright (C) 2009 Texas Instruments
15 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
16 *
17 * Support functions for the OMAP internal DMA channels.
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
22 *
23 */
24
25#include <linux/module.h>
26#include <linux/spinlock.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29
30#include <mach/hardware.h>
31#include <plat/dma.h>
32
33int omap_lcd_dma_running(void)
34{
35 /*
36 * On OMAP1510, internal LCD controller will start the transfer
37 * when it gets enabled, so assume DMA running if LCD enabled.
38 */
39 if (cpu_is_omap1510())
40 if (omap_readw(0xfffec000 + 0x00) & (1 << 0))
41 return 1;
42
43 /* Check if LCD DMA is running */
44 if (cpu_is_omap16xx())
45 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
46 return 1;
47
48 return 0;
49}
50
51static struct lcd_dma_info {
52 spinlock_t lock;
53 int reserved;
54 void (*callback)(u16 status, void *data);
55 void *cb_data;
56
57 int active;
58 unsigned long addr, size;
59 int rotate, data_type, xres, yres;
60 int vxres;
61 int mirror;
62 int xscale, yscale;
63 int ext_ctrl;
64 int src_port;
65 int single_transfer;
66} lcd_dma;
67
68void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
69 int data_type)
70{
71 lcd_dma.addr = addr;
72 lcd_dma.data_type = data_type;
73 lcd_dma.xres = fb_xres;
74 lcd_dma.yres = fb_yres;
75}
76EXPORT_SYMBOL(omap_set_lcd_dma_b1);
77
78void omap_set_lcd_dma_src_port(int port)
79{
80 lcd_dma.src_port = port;
81}
82
83void omap_set_lcd_dma_ext_controller(int external)
84{
85 lcd_dma.ext_ctrl = external;
86}
87EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
88
89void omap_set_lcd_dma_single_transfer(int single)
90{
91 lcd_dma.single_transfer = single;
92}
93EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
94
95void omap_set_lcd_dma_b1_rotation(int rotate)
96{
97 if (cpu_is_omap1510()) {
98 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
99 BUG();
100 return;
101 }
102 lcd_dma.rotate = rotate;
103}
104EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
105
106void omap_set_lcd_dma_b1_mirror(int mirror)
107{
108 if (cpu_is_omap1510()) {
109 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
110 BUG();
111 }
112 lcd_dma.mirror = mirror;
113}
114EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
115
116void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
117{
118 if (cpu_is_omap1510()) {
119 printk(KERN_ERR "DMA virtual resulotion is not supported "
120 "in 1510 mode\n");
121 BUG();
122 }
123 lcd_dma.vxres = vxres;
124}
125EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
126
127void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
128{
129 if (cpu_is_omap1510()) {
130 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
131 BUG();
132 }
133 lcd_dma.xscale = xscale;
134 lcd_dma.yscale = yscale;
135}
136EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
137
138static void set_b1_regs(void)
139{
140 unsigned long top, bottom;
141 int es;
142 u16 w;
143 unsigned long en, fn;
144 long ei, fi;
145 unsigned long vxres;
146 unsigned int xscale, yscale;
147
148 switch (lcd_dma.data_type) {
149 case OMAP_DMA_DATA_TYPE_S8:
150 es = 1;
151 break;
152 case OMAP_DMA_DATA_TYPE_S16:
153 es = 2;
154 break;
155 case OMAP_DMA_DATA_TYPE_S32:
156 es = 4;
157 break;
158 default:
159 BUG();
160 return;
161 }
162
163 vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
164 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
165 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
166 BUG_ON(vxres < lcd_dma.xres);
167
168#define PIXADDR(x, y) (lcd_dma.addr + \
169 ((y) * vxres * yscale + (x) * xscale) * es)
170#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
171
172 switch (lcd_dma.rotate) {
173 case 0:
174 if (!lcd_dma.mirror) {
175 top = PIXADDR(0, 0);
176 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
177 /* 1510 DMA requires the bottom address to be 2 more
178 * than the actual last memory access location. */
179 if (cpu_is_omap1510() &&
180 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
181 bottom += 2;
182 ei = PIXSTEP(0, 0, 1, 0);
183 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
184 } else {
185 top = PIXADDR(lcd_dma.xres - 1, 0);
186 bottom = PIXADDR(0, lcd_dma.yres - 1);
187 ei = PIXSTEP(1, 0, 0, 0);
188 fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
189 }
190 en = lcd_dma.xres;
191 fn = lcd_dma.yres;
192 break;
193 case 90:
194 if (!lcd_dma.mirror) {
195 top = PIXADDR(0, lcd_dma.yres - 1);
196 bottom = PIXADDR(lcd_dma.xres - 1, 0);
197 ei = PIXSTEP(0, 1, 0, 0);
198 fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
199 } else {
200 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
201 bottom = PIXADDR(0, 0);
202 ei = PIXSTEP(0, 1, 0, 0);
203 fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
204 }
205 en = lcd_dma.yres;
206 fn = lcd_dma.xres;
207 break;
208 case 180:
209 if (!lcd_dma.mirror) {
210 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
211 bottom = PIXADDR(0, 0);
212 ei = PIXSTEP(1, 0, 0, 0);
213 fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
214 } else {
215 top = PIXADDR(0, lcd_dma.yres - 1);
216 bottom = PIXADDR(lcd_dma.xres - 1, 0);
217 ei = PIXSTEP(0, 0, 1, 0);
218 fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
219 }
220 en = lcd_dma.xres;
221 fn = lcd_dma.yres;
222 break;
223 case 270:
224 if (!lcd_dma.mirror) {
225 top = PIXADDR(lcd_dma.xres - 1, 0);
226 bottom = PIXADDR(0, lcd_dma.yres - 1);
227 ei = PIXSTEP(0, 0, 0, 1);
228 fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
229 } else {
230 top = PIXADDR(0, 0);
231 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
232 ei = PIXSTEP(0, 0, 0, 1);
233 fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
234 }
235 en = lcd_dma.yres;
236 fn = lcd_dma.xres;
237 break;
238 default:
239 BUG();
240 return; /* Suppress warning about uninitialized vars */
241 }
242
243 if (cpu_is_omap1510()) {
244 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
245 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
246 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
247 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
248
249 return;
250 }
251
252 /* 1610 regs */
253 omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
254 omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
255 omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
256 omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
257
258 omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
259 omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
260
261 w = omap_readw(OMAP1610_DMA_LCD_CSDP);
262 w &= ~0x03;
263 w |= lcd_dma.data_type;
264 omap_writew(w, OMAP1610_DMA_LCD_CSDP);
265
266 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
267 /* Always set the source port as SDRAM for now*/
268 w &= ~(0x03 << 6);
269 if (lcd_dma.callback != NULL)
270 w |= 1 << 1; /* Block interrupt enable */
271 else
272 w &= ~(1 << 1);
273 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
274
275 if (!(lcd_dma.rotate || lcd_dma.mirror ||
276 lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
277 return;
278
279 w = omap_readw(OMAP1610_DMA_LCD_CCR);
280 /* Set the double-indexed addressing mode */
281 w |= (0x03 << 12);
282 omap_writew(w, OMAP1610_DMA_LCD_CCR);
283
284 omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
285 omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
286 omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
287}
288
289static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
290{
291 u16 w;
292
293 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
294 if (unlikely(!(w & (1 << 3)))) {
295 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
296 return IRQ_NONE;
297 }
298 /* Ack the IRQ */
299 w |= (1 << 3);
300 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
301 lcd_dma.active = 0;
302 if (lcd_dma.callback != NULL)
303 lcd_dma.callback(w, lcd_dma.cb_data);
304
305 return IRQ_HANDLED;
306}
307
308int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
309 void *data)
310{
311 spin_lock_irq(&lcd_dma.lock);
312 if (lcd_dma.reserved) {
313 spin_unlock_irq(&lcd_dma.lock);
314 printk(KERN_ERR "LCD DMA channel already reserved\n");
315 BUG();
316 return -EBUSY;
317 }
318 lcd_dma.reserved = 1;
319 spin_unlock_irq(&lcd_dma.lock);
320 lcd_dma.callback = callback;
321 lcd_dma.cb_data = data;
322 lcd_dma.active = 0;
323 lcd_dma.single_transfer = 0;
324 lcd_dma.rotate = 0;
325 lcd_dma.vxres = 0;
326 lcd_dma.mirror = 0;
327 lcd_dma.xscale = 0;
328 lcd_dma.yscale = 0;
329 lcd_dma.ext_ctrl = 0;
330 lcd_dma.src_port = 0;
331
332 return 0;
333}
334EXPORT_SYMBOL(omap_request_lcd_dma);
335
336void omap_free_lcd_dma(void)
337{
338 spin_lock(&lcd_dma.lock);
339 if (!lcd_dma.reserved) {
340 spin_unlock(&lcd_dma.lock);
341 printk(KERN_ERR "LCD DMA is not reserved\n");
342 BUG();
343 return;
344 }
345 if (!cpu_is_omap1510())
346 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
347 OMAP1610_DMA_LCD_CCR);
348 lcd_dma.reserved = 0;
349 spin_unlock(&lcd_dma.lock);
350}
351EXPORT_SYMBOL(omap_free_lcd_dma);
352
353void omap_enable_lcd_dma(void)
354{
355 u16 w;
356
357 /*
358 * Set the Enable bit only if an external controller is
359 * connected. Otherwise the OMAP internal controller will
360 * start the transfer when it gets enabled.
361 */
362 if (cpu_is_omap1510() || !lcd_dma.ext_ctrl)
363 return;
364
365 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
366 w |= 1 << 8;
367 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
368
369 lcd_dma.active = 1;
370
371 w = omap_readw(OMAP1610_DMA_LCD_CCR);
372 w |= 1 << 7;
373 omap_writew(w, OMAP1610_DMA_LCD_CCR);
374}
375EXPORT_SYMBOL(omap_enable_lcd_dma);
376
377void omap_setup_lcd_dma(void)
378{
379 BUG_ON(lcd_dma.active);
380 if (!cpu_is_omap1510()) {
381 /* Set some reasonable defaults */
382 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
383 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
384 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
385 }
386 set_b1_regs();
387 if (!cpu_is_omap1510()) {
388 u16 w;
389
390 w = omap_readw(OMAP1610_DMA_LCD_CCR);
391 /*
392 * If DMA was already active set the end_prog bit to have
393 * the programmed register set loaded into the active
394 * register set.
395 */
396 w |= 1 << 11; /* End_prog */
397 if (!lcd_dma.single_transfer)
398 w |= (3 << 8); /* Auto_init, repeat */
399 omap_writew(w, OMAP1610_DMA_LCD_CCR);
400 }
401}
402EXPORT_SYMBOL(omap_setup_lcd_dma);
403
404void omap_stop_lcd_dma(void)
405{
406 u16 w;
407
408 lcd_dma.active = 0;
409 if (cpu_is_omap1510() || !lcd_dma.ext_ctrl)
410 return;
411
412 w = omap_readw(OMAP1610_DMA_LCD_CCR);
413 w &= ~(1 << 7);
414 omap_writew(w, OMAP1610_DMA_LCD_CCR);
415
416 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
417 w &= ~(1 << 8);
418 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
419}
420EXPORT_SYMBOL(omap_stop_lcd_dma);
421
422static int __init omap_init_lcd_dma(void)
423{
424 int r;
425
426 if (cpu_is_omap16xx()) {
427 u16 w;
428
429 /* this would prevent OMAP sleep */
430 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
431 w &= ~(1 << 8);
432 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
433 }
434
435 spin_lock_init(&lcd_dma.lock);
436
437 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
438 "LCD DMA", NULL);
439 if (r != 0)
440 printk(KERN_ERR "unable to request IRQ for LCD DMA "
441 "(error %d)\n", r);
442
443 return r;
444}
445
446arch_initcall(omap_init_lcd_dma);
447
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index d17375e06a1e..09d82b3c66ce 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -47,7 +47,6 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
47#endif 47#endif
48 48
49#define OMAP_DMA_ACTIVE 0x01 49#define OMAP_DMA_ACTIVE 0x01
50#define OMAP_DMA_CCR_EN (1 << 7)
51#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe 50#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
52 51
53#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) 52#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
@@ -1120,17 +1119,8 @@ int omap_dma_running(void)
1120{ 1119{
1121 int lch; 1120 int lch;
1122 1121
1123 /* 1122 if (cpu_class_is_omap1())
1124 * On OMAP1510, internal LCD controller will start the transfer 1123 if (omap_lcd_dma_running())
1125 * when it gets enabled, so assume DMA running if LCD enabled.
1126 */
1127 if (cpu_is_omap1510())
1128 if (omap_readw(0xfffec000 + 0x00) & (1 << 0))
1129 return 1;
1130
1131 /* Check if LCD DMA is running */
1132 if (cpu_is_omap16xx())
1133 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1134 return 1; 1124 return 1;
1135 1125
1136 for (lch = 0; lch < dma_chan_count; lch++) 1126 for (lch = 0; lch < dma_chan_count; lch++)
@@ -1990,377 +1980,6 @@ static struct irqaction omap24xx_dma_irq;
1990 1980
1991/*----------------------------------------------------------------------------*/ 1981/*----------------------------------------------------------------------------*/
1992 1982
1993static struct lcd_dma_info {
1994 spinlock_t lock;
1995 int reserved;
1996 void (*callback)(u16 status, void *data);
1997 void *cb_data;
1998
1999 int active;
2000 unsigned long addr, size;
2001 int rotate, data_type, xres, yres;
2002 int vxres;
2003 int mirror;
2004 int xscale, yscale;
2005 int ext_ctrl;
2006 int src_port;
2007 int single_transfer;
2008} lcd_dma;
2009
2010void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
2011 int data_type)
2012{
2013 lcd_dma.addr = addr;
2014 lcd_dma.data_type = data_type;
2015 lcd_dma.xres = fb_xres;
2016 lcd_dma.yres = fb_yres;
2017}
2018EXPORT_SYMBOL(omap_set_lcd_dma_b1);
2019
2020void omap_set_lcd_dma_src_port(int port)
2021{
2022 lcd_dma.src_port = port;
2023}
2024
2025void omap_set_lcd_dma_ext_controller(int external)
2026{
2027 lcd_dma.ext_ctrl = external;
2028}
2029EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
2030
2031void omap_set_lcd_dma_single_transfer(int single)
2032{
2033 lcd_dma.single_transfer = single;
2034}
2035EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
2036
2037void omap_set_lcd_dma_b1_rotation(int rotate)
2038{
2039 if (omap_dma_in_1510_mode()) {
2040 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
2041 BUG();
2042 return;
2043 }
2044 lcd_dma.rotate = rotate;
2045}
2046EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
2047
2048void omap_set_lcd_dma_b1_mirror(int mirror)
2049{
2050 if (omap_dma_in_1510_mode()) {
2051 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
2052 BUG();
2053 }
2054 lcd_dma.mirror = mirror;
2055}
2056EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
2057
2058void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
2059{
2060 if (omap_dma_in_1510_mode()) {
2061 printk(KERN_ERR "DMA virtual resulotion is not supported "
2062 "in 1510 mode\n");
2063 BUG();
2064 }
2065 lcd_dma.vxres = vxres;
2066}
2067EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2068
2069void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
2070{
2071 if (omap_dma_in_1510_mode()) {
2072 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
2073 BUG();
2074 }
2075 lcd_dma.xscale = xscale;
2076 lcd_dma.yscale = yscale;
2077}
2078EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2079
2080static void set_b1_regs(void)
2081{
2082 unsigned long top, bottom;
2083 int es;
2084 u16 w;
2085 unsigned long en, fn;
2086 long ei, fi;
2087 unsigned long vxres;
2088 unsigned int xscale, yscale;
2089
2090 switch (lcd_dma.data_type) {
2091 case OMAP_DMA_DATA_TYPE_S8:
2092 es = 1;
2093 break;
2094 case OMAP_DMA_DATA_TYPE_S16:
2095 es = 2;
2096 break;
2097 case OMAP_DMA_DATA_TYPE_S32:
2098 es = 4;
2099 break;
2100 default:
2101 BUG();
2102 return;
2103 }
2104
2105 vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2106 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2107 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2108 BUG_ON(vxres < lcd_dma.xres);
2109
2110#define PIXADDR(x, y) (lcd_dma.addr + \
2111 ((y) * vxres * yscale + (x) * xscale) * es)
2112#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2113
2114 switch (lcd_dma.rotate) {
2115 case 0:
2116 if (!lcd_dma.mirror) {
2117 top = PIXADDR(0, 0);
2118 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2119 /* 1510 DMA requires the bottom address to be 2 more
2120 * than the actual last memory access location. */
2121 if (omap_dma_in_1510_mode() &&
2122 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2123 bottom += 2;
2124 ei = PIXSTEP(0, 0, 1, 0);
2125 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2126 } else {
2127 top = PIXADDR(lcd_dma.xres - 1, 0);
2128 bottom = PIXADDR(0, lcd_dma.yres - 1);
2129 ei = PIXSTEP(1, 0, 0, 0);
2130 fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2131 }
2132 en = lcd_dma.xres;
2133 fn = lcd_dma.yres;
2134 break;
2135 case 90:
2136 if (!lcd_dma.mirror) {
2137 top = PIXADDR(0, lcd_dma.yres - 1);
2138 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2139 ei = PIXSTEP(0, 1, 0, 0);
2140 fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2141 } else {
2142 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2143 bottom = PIXADDR(0, 0);
2144 ei = PIXSTEP(0, 1, 0, 0);
2145 fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2146 }
2147 en = lcd_dma.yres;
2148 fn = lcd_dma.xres;
2149 break;
2150 case 180:
2151 if (!lcd_dma.mirror) {
2152 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2153 bottom = PIXADDR(0, 0);
2154 ei = PIXSTEP(1, 0, 0, 0);
2155 fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2156 } else {
2157 top = PIXADDR(0, lcd_dma.yres - 1);
2158 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2159 ei = PIXSTEP(0, 0, 1, 0);
2160 fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2161 }
2162 en = lcd_dma.xres;
2163 fn = lcd_dma.yres;
2164 break;
2165 case 270:
2166 if (!lcd_dma.mirror) {
2167 top = PIXADDR(lcd_dma.xres - 1, 0);
2168 bottom = PIXADDR(0, lcd_dma.yres - 1);
2169 ei = PIXSTEP(0, 0, 0, 1);
2170 fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2171 } else {
2172 top = PIXADDR(0, 0);
2173 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2174 ei = PIXSTEP(0, 0, 0, 1);
2175 fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2176 }
2177 en = lcd_dma.yres;
2178 fn = lcd_dma.xres;
2179 break;
2180 default:
2181 BUG();
2182 return; /* Suppress warning about uninitialized vars */
2183 }
2184
2185 if (omap_dma_in_1510_mode()) {
2186 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2187 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2188 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2189 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2190
2191 return;
2192 }
2193
2194 /* 1610 regs */
2195 omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2196 omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2197 omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2198 omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2199
2200 omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2201 omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2202
2203 w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2204 w &= ~0x03;
2205 w |= lcd_dma.data_type;
2206 omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2207
2208 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2209 /* Always set the source port as SDRAM for now*/
2210 w &= ~(0x03 << 6);
2211 if (lcd_dma.callback != NULL)
2212 w |= 1 << 1; /* Block interrupt enable */
2213 else
2214 w &= ~(1 << 1);
2215 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2216
2217 if (!(lcd_dma.rotate || lcd_dma.mirror ||
2218 lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2219 return;
2220
2221 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2222 /* Set the double-indexed addressing mode */
2223 w |= (0x03 << 12);
2224 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2225
2226 omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2227 omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2228 omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2229}
2230
2231static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
2232{
2233 u16 w;
2234
2235 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2236 if (unlikely(!(w & (1 << 3)))) {
2237 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2238 return IRQ_NONE;
2239 }
2240 /* Ack the IRQ */
2241 w |= (1 << 3);
2242 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2243 lcd_dma.active = 0;
2244 if (lcd_dma.callback != NULL)
2245 lcd_dma.callback(w, lcd_dma.cb_data);
2246
2247 return IRQ_HANDLED;
2248}
2249
2250int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
2251 void *data)
2252{
2253 spin_lock_irq(&lcd_dma.lock);
2254 if (lcd_dma.reserved) {
2255 spin_unlock_irq(&lcd_dma.lock);
2256 printk(KERN_ERR "LCD DMA channel already reserved\n");
2257 BUG();
2258 return -EBUSY;
2259 }
2260 lcd_dma.reserved = 1;
2261 spin_unlock_irq(&lcd_dma.lock);
2262 lcd_dma.callback = callback;
2263 lcd_dma.cb_data = data;
2264 lcd_dma.active = 0;
2265 lcd_dma.single_transfer = 0;
2266 lcd_dma.rotate = 0;
2267 lcd_dma.vxres = 0;
2268 lcd_dma.mirror = 0;
2269 lcd_dma.xscale = 0;
2270 lcd_dma.yscale = 0;
2271 lcd_dma.ext_ctrl = 0;
2272 lcd_dma.src_port = 0;
2273
2274 return 0;
2275}
2276EXPORT_SYMBOL(omap_request_lcd_dma);
2277
2278void omap_free_lcd_dma(void)
2279{
2280 spin_lock(&lcd_dma.lock);
2281 if (!lcd_dma.reserved) {
2282 spin_unlock(&lcd_dma.lock);
2283 printk(KERN_ERR "LCD DMA is not reserved\n");
2284 BUG();
2285 return;
2286 }
2287 if (!enable_1510_mode)
2288 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2289 OMAP1610_DMA_LCD_CCR);
2290 lcd_dma.reserved = 0;
2291 spin_unlock(&lcd_dma.lock);
2292}
2293EXPORT_SYMBOL(omap_free_lcd_dma);
2294
2295void omap_enable_lcd_dma(void)
2296{
2297 u16 w;
2298
2299 /*
2300 * Set the Enable bit only if an external controller is
2301 * connected. Otherwise the OMAP internal controller will
2302 * start the transfer when it gets enabled.
2303 */
2304 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2305 return;
2306
2307 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2308 w |= 1 << 8;
2309 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2310
2311 lcd_dma.active = 1;
2312
2313 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2314 w |= 1 << 7;
2315 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2316}
2317EXPORT_SYMBOL(omap_enable_lcd_dma);
2318
2319void omap_setup_lcd_dma(void)
2320{
2321 BUG_ON(lcd_dma.active);
2322 if (!enable_1510_mode) {
2323 /* Set some reasonable defaults */
2324 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2325 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2326 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2327 }
2328 set_b1_regs();
2329 if (!enable_1510_mode) {
2330 u16 w;
2331
2332 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2333 /*
2334 * If DMA was already active set the end_prog bit to have
2335 * the programmed register set loaded into the active
2336 * register set.
2337 */
2338 w |= 1 << 11; /* End_prog */
2339 if (!lcd_dma.single_transfer)
2340 w |= (3 << 8); /* Auto_init, repeat */
2341 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2342 }
2343}
2344EXPORT_SYMBOL(omap_setup_lcd_dma);
2345
2346void omap_stop_lcd_dma(void)
2347{
2348 u16 w;
2349
2350 lcd_dma.active = 0;
2351 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2352 return;
2353
2354 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2355 w &= ~(1 << 7);
2356 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2357
2358 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2359 w &= ~(1 << 8);
2360 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2361}
2362EXPORT_SYMBOL(omap_stop_lcd_dma);
2363
2364void omap_dma_global_context_save(void) 1983void omap_dma_global_context_save(void)
2365{ 1984{
2366 omap_dma_global_context.dma_irqenable_l0 = 1985 omap_dma_global_context.dma_irqenable_l0 =
@@ -2465,14 +2084,6 @@ static int __init omap_init_dma(void)
2465 dma_chan_count = 16; 2084 dma_chan_count = 16;
2466 } else 2085 } else
2467 dma_chan_count = 9; 2086 dma_chan_count = 9;
2468 if (cpu_is_omap16xx()) {
2469 u16 w;
2470
2471 /* this would prevent OMAP sleep */
2472 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2473 w &= ~(1 << 8);
2474 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2475 }
2476 } else if (cpu_class_is_omap2()) { 2087 } else if (cpu_class_is_omap2()) {
2477 u8 revision = dma_read(REVISION) & 0xff; 2088 u8 revision = dma_read(REVISION) & 0xff;
2478 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", 2089 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
@@ -2483,7 +2094,6 @@ static int __init omap_init_dma(void)
2483 return 0; 2094 return 0;
2484 } 2095 }
2485 2096
2486 spin_lock_init(&lcd_dma.lock);
2487 spin_lock_init(&dma_chan_lock); 2097 spin_lock_init(&dma_chan_lock);
2488 2098
2489 for (ch = 0; ch < dma_chan_count; ch++) { 2099 for (ch = 0; ch < dma_chan_count; ch++) {
@@ -2548,22 +2158,6 @@ static int __init omap_init_dma(void)
2548 } 2158 }
2549 } 2159 }
2550 2160
2551
2552 /* FIXME: Update LCD DMA to work on 24xx */
2553 if (cpu_class_is_omap1()) {
2554 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2555 "LCD DMA", NULL);
2556 if (r != 0) {
2557 int i;
2558
2559 printk(KERN_ERR "unable to request IRQ for LCD DMA "
2560 "(error %d)\n", r);
2561 for (i = 0; i < dma_chan_count; i++)
2562 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2563 goto out_free;
2564 }
2565 }
2566
2567 return 0; 2161 return 0;
2568 2162
2569out_free: 2163out_free:
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index 1c017b29b7e9..4ede9e17a0be 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -401,33 +401,6 @@
401 401
402/*----------------------------------------------------------------------------*/ 402/*----------------------------------------------------------------------------*/
403 403
404/* Hardware registers for LCD DMA */
405#define OMAP1510_DMA_LCD_BASE (0xfffedb00)
406#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)
407#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02)
408#define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04)
409#define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06)
410#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08)
411
412#define OMAP1610_DMA_LCD_BASE (0xfffee300)
413#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0)
414#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2)
415#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4)
416#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8)
417#define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca)
418#define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc)
419#define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce)
420#define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0)
421#define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2)
422#define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4)
423#define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6)
424#define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8)
425#define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda)
426#define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0)
427#define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4)
428#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
429#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
430
431#define OMAP1_DMA_TOUT_IRQ (1 << 0) 404#define OMAP1_DMA_TOUT_IRQ (1 << 0)
432#define OMAP_DMA_DROP_IRQ (1 << 1) 405#define OMAP_DMA_DROP_IRQ (1 << 1)
433#define OMAP_DMA_HALF_IRQ (1 << 2) 406#define OMAP_DMA_HALF_IRQ (1 << 2)
@@ -441,6 +414,8 @@
441#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10) 414#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
442#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11) 415#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
443 416
417#define OMAP_DMA_CCR_EN (1 << 7)
418
444#define OMAP_DMA_DATA_TYPE_S8 0x00 419#define OMAP_DMA_DATA_TYPE_S8 0x00
445#define OMAP_DMA_DATA_TYPE_S16 0x01 420#define OMAP_DMA_DATA_TYPE_S16 0x01
446#define OMAP_DMA_DATA_TYPE_S32 0x02 421#define OMAP_DMA_DATA_TYPE_S32 0x02
@@ -503,14 +478,6 @@
503#define DMA_CH_PRIO_HIGH 0x1 478#define DMA_CH_PRIO_HIGH 0x1
504#define DMA_CH_PRIO_LOW 0x0 /* Def */ 479#define DMA_CH_PRIO_LOW 0x0 /* Def */
505 480
506/* LCD DMA block numbers */
507enum {
508 OMAP_LCD_DMA_B1_TOP,
509 OMAP_LCD_DMA_B1_BOTTOM,
510 OMAP_LCD_DMA_B2_TOP,
511 OMAP_LCD_DMA_B2_BOTTOM
512};
513
514enum omap_dma_burst_mode { 481enum omap_dma_burst_mode {
515 OMAP_DMA_DATA_BURST_DIS = 0, 482 OMAP_DMA_DATA_BURST_DIS = 0,
516 OMAP_DMA_DATA_BURST_4, 483 OMAP_DMA_DATA_BURST_4,
@@ -661,20 +628,13 @@ extern int omap_modify_dma_chain_params(int chain_id,
661extern int omap_dma_chain_status(int chain_id); 628extern int omap_dma_chain_status(int chain_id);
662#endif 629#endif
663 630
664/* LCD DMA functions */ 631#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP)
665extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data), 632#include <mach/lcd_dma.h>
666 void *data); 633#else
667extern void omap_free_lcd_dma(void); 634static inline int omap_lcd_dma_running(void)
668extern void omap_setup_lcd_dma(void); 635{
669extern void omap_enable_lcd_dma(void); 636 return 0;
670extern void omap_stop_lcd_dma(void); 637}
671extern void omap_set_lcd_dma_ext_controller(int external); 638#endif
672extern void omap_set_lcd_dma_single_transfer(int single);
673extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
674 int data_type);
675extern void omap_set_lcd_dma_b1_rotation(int rotate);
676extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
677extern void omap_set_lcd_dma_b1_mirror(int mirror);
678extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
679 639
680#endif /* __ASM_ARCH_DMA_H */ 640#endif /* __ASM_ARCH_DMA_H */
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