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-rw-r--r--arch/m68k/include/asm/cacheflush_no.h95
-rw-r--r--arch/m68k/include/asm/coldfire.h2
-rw-r--r--arch/m68k/include/asm/entry_no.h59
-rw-r--r--arch/m68k/include/asm/gpio.h2
-rw-r--r--arch/m68k/include/asm/io_no.h1
-rw-r--r--arch/m68k/include/asm/m5206sim.h14
-rw-r--r--arch/m68k/include/asm/m520xsim.h17
-rw-r--r--arch/m68k/include/asm/m523xsim.h11
-rw-r--r--arch/m68k/include/asm/m5249sim.h10
-rw-r--r--arch/m68k/include/asm/m5272sim.h8
-rw-r--r--arch/m68k/include/asm/m527xsim.h10
-rw-r--r--arch/m68k/include/asm/m528xsim.h11
-rw-r--r--arch/m68k/include/asm/m52xxacr.h94
-rw-r--r--arch/m68k/include/asm/m5307sim.h43
-rw-r--r--arch/m68k/include/asm/m532xsim.h33
-rw-r--r--arch/m68k/include/asm/m53xxacr.h101
-rw-r--r--arch/m68k/include/asm/m5407sim.h42
-rw-r--r--arch/m68k/include/asm/m54xxacr.h97
-rw-r--r--arch/m68k/include/asm/m54xxgpt.h (renamed from arch/m68k/include/asm/m548xgpt.h)10
-rw-r--r--arch/m68k/include/asm/m54xxsim.h (renamed from arch/m68k/include/asm/m548xsim.h)23
-rw-r--r--arch/m68k/include/asm/mcfcache.h150
-rw-r--r--arch/m68k/include/asm/mcfsim.h4
-rw-r--r--arch/m68k/include/asm/mcfuart.h45
-rw-r--r--arch/m68k/include/asm/processor.h13
-rw-r--r--arch/m68knommu/Kconfig98
-rw-r--r--arch/m68knommu/Makefile14
-rw-r--r--arch/m68knommu/kernel/setup.c72
-rw-r--r--arch/m68knommu/mm/Makefile2
-rw-r--r--arch/m68knommu/mm/fault.c57
-rw-r--r--arch/m68knommu/mm/kmap.c9
-rw-r--r--arch/m68knommu/mm/memory.c33
-rw-r--r--arch/m68knommu/platform/54xx/Makefile (renamed from arch/m68knommu/platform/548x/Makefile)0
-rw-r--r--arch/m68knommu/platform/54xx/config.c (renamed from arch/m68knommu/platform/548x/config.c)32
-rw-r--r--arch/m68knommu/platform/68328/ints.c4
-rw-r--r--arch/m68knommu/platform/coldfire/Makefile4
-rw-r--r--arch/m68knommu/platform/coldfire/cache.c48
-rw-r--r--arch/m68knommu/platform/coldfire/entry.S56
-rw-r--r--arch/m68knommu/platform/coldfire/head.S26
38 files changed, 727 insertions, 623 deletions
diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h
index 7085bd51668b..cb88aa96c4f1 100644
--- a/arch/m68k/include/asm/cacheflush_no.h
+++ b/arch/m68k/include/asm/cacheflush_no.h
@@ -2,21 +2,22 @@
2#define _M68KNOMMU_CACHEFLUSH_H 2#define _M68KNOMMU_CACHEFLUSH_H
3 3
4/* 4/*
5 * (C) Copyright 2000-2004, Greg Ungerer <gerg@snapgear.com> 5 * (C) Copyright 2000-2010, Greg Ungerer <gerg@snapgear.com>
6 */ 6 */
7#include <linux/mm.h> 7#include <linux/mm.h>
8#include <asm/mcfsim.h>
8 9
9#define flush_cache_all() __flush_cache_all() 10#define flush_cache_all() __flush_cache_all()
10#define flush_cache_mm(mm) do { } while (0) 11#define flush_cache_mm(mm) do { } while (0)
11#define flush_cache_dup_mm(mm) do { } while (0) 12#define flush_cache_dup_mm(mm) do { } while (0)
12#define flush_cache_range(vma, start, end) __flush_cache_all() 13#define flush_cache_range(vma, start, end) do { } while (0)
13#define flush_cache_page(vma, vmaddr) do { } while (0) 14#define flush_cache_page(vma, vmaddr) do { } while (0)
14#define flush_dcache_range(start,len) __flush_cache_all() 15#define flush_dcache_range(start, len) __flush_dcache_all()
15#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 16#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
16#define flush_dcache_page(page) do { } while (0) 17#define flush_dcache_page(page) do { } while (0)
17#define flush_dcache_mmap_lock(mapping) do { } while (0) 18#define flush_dcache_mmap_lock(mapping) do { } while (0)
18#define flush_dcache_mmap_unlock(mapping) do { } while (0) 19#define flush_dcache_mmap_unlock(mapping) do { } while (0)
19#define flush_icache_range(start,len) __flush_cache_all() 20#define flush_icache_range(start, len) __flush_icache_all()
20#define flush_icache_page(vma,pg) do { } while (0) 21#define flush_icache_page(vma,pg) do { } while (0)
21#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) 22#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
22#define flush_cache_vmap(start, end) do { } while (0) 23#define flush_cache_vmap(start, end) do { } while (0)
@@ -27,66 +28,52 @@
27#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ 28#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
28 memcpy(dst, src, len) 29 memcpy(dst, src, len)
29 30
31void mcf_cache_push(void);
32
30static inline void __flush_cache_all(void) 33static inline void __flush_cache_all(void)
31{ 34{
32#if defined(CONFIG_M5407) || defined(CONFIG_M548x) 35#ifdef CACHE_PUSH
33 /* 36 mcf_cache_push();
34 * Use cpushl to push and invalidate all cache lines. 37#endif
35 * Gas doesn't seem to know how to generate the ColdFire 38#ifdef CACHE_INVALIDATE
36 * cpushl instruction... Oh well, bit stuff it for now.
37 */
38 __asm__ __volatile__ (
39 "nop\n\t"
40 "clrl %%d0\n\t"
41 "1:\n\t"
42 "movel %%d0,%%a0\n\t"
43 "2:\n\t"
44 ".word 0xf468\n\t"
45 "addl #0x10,%%a0\n\t"
46 "cmpl #0x00000800,%%a0\n\t"
47 "blt 2b\n\t"
48 "addql #1,%%d0\n\t"
49 "cmpil #4,%%d0\n\t"
50 "bne 1b\n\t"
51 "movel #0xb6088500,%%d0\n\t"
52 "movec %%d0,%%CACR\n\t"
53 : : : "d0", "a0" );
54#endif /* CONFIG_M5407 */
55#if defined(CONFIG_M523x) || defined(CONFIG_M527x)
56 __asm__ __volatile__ (
57 "movel #0x81400100, %%d0\n\t"
58 "movec %%d0, %%CACR\n\t"
59 "nop\n\t"
60 : : : "d0" );
61#endif /* CONFIG_M523x || CONFIG_M527x */
62#if defined(CONFIG_M528x)
63 __asm__ __volatile__ (
64 "movel #0x81000200, %%d0\n\t"
65 "movec %%d0, %%CACR\n\t"
66 "nop\n\t"
67 : : : "d0" );
68#endif /* CONFIG_M528x */
69#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272)
70 __asm__ __volatile__ ( 39 __asm__ __volatile__ (
71 "movel #0x81000100, %%d0\n\t" 40 "movel %0, %%d0\n\t"
72 "movec %%d0, %%CACR\n\t" 41 "movec %%d0, %%CACR\n\t"
73 "nop\n\t" 42 "nop\n\t"
74 : : : "d0" ); 43 : : "i" (CACHE_INVALIDATE) : "d0" );
75#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */ 44#endif
76#ifdef CONFIG_M5249 45}
46
47/*
48 * Some ColdFire parts implement separate instruction and data caches,
49 * on those we should just flush the appropriate cache. If we don't need
50 * to do any specific flushing then this will be optimized away.
51 */
52static inline void __flush_icache_all(void)
53{
54#ifdef CACHE_INVALIDATEI
77 __asm__ __volatile__ ( 55 __asm__ __volatile__ (
78 "movel #0xa1000200, %%d0\n\t" 56 "movel %0, %%d0\n\t"
79 "movec %%d0, %%CACR\n\t" 57 "movec %%d0, %%CACR\n\t"
80 "nop\n\t" 58 "nop\n\t"
81 : : : "d0" ); 59 : : "i" (CACHE_INVALIDATEI) : "d0" );
82#endif /* CONFIG_M5249 */ 60#endif
83#ifdef CONFIG_M532x 61}
62
63static inline void __flush_dcache_all(void)
64{
65#ifdef CACHE_PUSH
66 mcf_cache_push();
67#endif
68#ifdef CACHE_INVALIDATED
84 __asm__ __volatile__ ( 69 __asm__ __volatile__ (
85 "movel #0x81000200, %%d0\n\t" 70 "movel %0, %%d0\n\t"
86 "movec %%d0, %%CACR\n\t" 71 "movec %%d0, %%CACR\n\t"
87 "nop\n\t" 72 "nop\n\t"
88 : : : "d0" ); 73 : : "i" (CACHE_INVALIDATED) : "d0" );
89#endif /* CONFIG_M532x */ 74#else
75 /* Flush the wrtite buffer */
76 __asm__ __volatile__ ( "nop" );
77#endif
90} 78}
91
92#endif /* _M68KNOMMU_CACHEFLUSH_H */ 79#endif /* _M68KNOMMU_CACHEFLUSH_H */
diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h
index 3b0a34d0fe33..213028cbe110 100644
--- a/arch/m68k/include/asm/coldfire.h
+++ b/arch/m68k/include/asm/coldfire.h
@@ -32,7 +32,7 @@
32 */ 32 */
33#define MCF_MBAR 0x10000000 33#define MCF_MBAR 0x10000000
34#define MCF_MBAR2 0x80000000 34#define MCF_MBAR2 0x80000000
35#if defined(CONFIG_M548x) 35#if defined(CONFIG_M54xx)
36#define MCF_IPSBAR MCF_MBAR 36#define MCF_IPSBAR MCF_MBAR
37#elif defined(CONFIG_M520x) 37#elif defined(CONFIG_M520x)
38#define MCF_IPSBAR 0xFC000000 38#define MCF_IPSBAR 0xFC000000
diff --git a/arch/m68k/include/asm/entry_no.h b/arch/m68k/include/asm/entry_no.h
index 26be277394f9..627d69bacc58 100644
--- a/arch/m68k/include/asm/entry_no.h
+++ b/arch/m68k/include/asm/entry_no.h
@@ -42,12 +42,16 @@
42 */ 42 */
43 43
44#ifdef CONFIG_COLDFIRE 44#ifdef CONFIG_COLDFIRE
45#ifdef CONFIG_COLDFIRE_SW_A7
45/* 46/*
46 * This is made a little more tricky on the ColdFire. There is no 47 * This is made a little more tricky on older ColdFires. There is no
47 * separate kernel and user stack pointers. Need to artificially 48 * separate supervisor and user stack pointers. Need to artificially
48 * construct a usp in software... When doing this we need to disable 49 * construct a usp in software... When doing this we need to disable
49 * interrupts, otherwise bad things could happen. 50 * interrupts, otherwise bad things will happen.
50 */ 51 */
52.globl sw_usp
53.globl sw_ksp
54
51.macro SAVE_ALL 55.macro SAVE_ALL
52 move #0x2700,%sr /* disable intrs */ 56 move #0x2700,%sr /* disable intrs */
53 btst #5,%sp@(2) /* from user? */ 57 btst #5,%sp@(2) /* from user? */
@@ -74,9 +78,7 @@
74 7: 78 7:
75.endm 79.endm
76 80
77.macro RESTORE_ALL 81.macro RESTORE_USER
78 btst #5,%sp@(PT_SR) /* going user? */
79 bnes 8f /* no, skip */
80 move #0x2700,%sr /* disable intrs */ 82 move #0x2700,%sr /* disable intrs */
81 movel sw_usp,%a0 /* get usp */ 83 movel sw_usp,%a0 /* get usp */
82 movel %sp@(PT_OFF_PC),%a0@- /* copy exception program counter */ 84 movel %sp@(PT_OFF_PC),%a0@- /* copy exception program counter */
@@ -91,19 +93,22 @@
91 subql #8,sw_usp /* set exception */ 93 subql #8,sw_usp /* set exception */
92 movel sw_usp,%sp /* restore usp */ 94 movel sw_usp,%sp /* restore usp */
93 rte 95 rte
94 8:
95 moveml %sp@,%d1-%d5/%a0-%a2
96 lea %sp@(32),%sp /* space for 8 regs */
97 movel %sp@+,%d0
98 addql #4,%sp /* orig d0 */
99 addl %sp@+,%sp /* stkadj */
100 rte
101.endm 96.endm
102 97
98.macro RDUSP
99 movel sw_usp,%a2
100.endm
101
102.macro WRUSP
103 movel %a0,sw_usp
104.endm
105
106#else /* !CONFIG_COLDFIRE_SW_A7 */
103/* 107/*
104 * Quick exception save, use current stack only. 108 * Modern ColdFire parts have separate supervisor and user stack
109 * pointers. Simple load and restore macros for this case.
105 */ 110 */
106.macro SAVE_LOCAL 111.macro SAVE_ALL
107 move #0x2700,%sr /* disable intrs */ 112 move #0x2700,%sr /* disable intrs */
108 clrl %sp@- /* stkadj */ 113 clrl %sp@- /* stkadj */
109 movel %d0,%sp@- /* orig d0 */ 114 movel %d0,%sp@- /* orig d0 */
@@ -112,7 +117,7 @@
112 moveml %d1-%d5/%a0-%a2,%sp@ 117 moveml %d1-%d5/%a0-%a2,%sp@
113.endm 118.endm
114 119
115.macro RESTORE_LOCAL 120.macro RESTORE_USER
116 moveml %sp@,%d1-%d5/%a0-%a2 121 moveml %sp@,%d1-%d5/%a0-%a2
117 lea %sp@(32),%sp /* space for 8 regs */ 122 lea %sp@(32),%sp /* space for 8 regs */
118 movel %sp@+,%d0 123 movel %sp@+,%d0
@@ -121,6 +126,18 @@
121 rte 126 rte
122.endm 127.endm
123 128
129.macro RDUSP
130 /*move %usp,%a2*/
131 .word 0x4e6a
132.endm
133
134.macro WRUSP
135 /*move %a0,%usp*/
136 .word 0x4e60
137.endm
138
139#endif /* !CONFIG_COLDFIRE_SW_A7 */
140
124.macro SAVE_SWITCH_STACK 141.macro SAVE_SWITCH_STACK
125 lea %sp@(-24),%sp /* 6 regs */ 142 lea %sp@(-24),%sp /* 6 regs */
126 moveml %a3-%a6/%d6-%d7,%sp@ 143 moveml %a3-%a6/%d6-%d7,%sp@
@@ -131,14 +148,6 @@
131 lea %sp@(24),%sp /* 6 regs */ 148 lea %sp@(24),%sp /* 6 regs */
132.endm 149.endm
133 150
134/*
135 * Software copy of the user and kernel stack pointers... Ugh...
136 * Need these to get around ColdFire not having separate kernel
137 * and user stack pointers.
138 */
139.globl sw_usp
140.globl sw_ksp
141
142#else /* !CONFIG_COLDFIRE */ 151#else /* !CONFIG_COLDFIRE */
143 152
144/* 153/*
@@ -167,6 +176,6 @@
167 moveml %sp@+,%a3-%a6/%d6-%d7 176 moveml %sp@+,%a3-%a6/%d6-%d7
168.endm 177.endm
169 178
170#endif /* !CONFIG_COLDFIRE */ 179#endif /* !COLDFIRE_SW_A7 */
171#endif /* __ASSEMBLY__ */ 180#endif /* __ASSEMBLY__ */
172#endif /* __M68KNOMMU_ENTRY_H */ 181#endif /* __M68KNOMMU_ENTRY_H */
diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h
index 1b57adbafad5..c64c7b74cf86 100644
--- a/arch/m68k/include/asm/gpio.h
+++ b/arch/m68k/include/asm/gpio.h
@@ -37,7 +37,7 @@
37#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ 37#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
38 defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ 38 defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
39 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 39 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
40 defined(CONFIG_M532x) || defined(CONFIG_M548x) 40 defined(CONFIG_M532x) || defined(CONFIG_M54xx)
41 41
42/* These parts have GPIO organized by 8 bit ports */ 42/* These parts have GPIO organized by 8 bit ports */
43 43
diff --git a/arch/m68k/include/asm/io_no.h b/arch/m68k/include/asm/io_no.h
index 6e2413e518cb..cf20f3097af6 100644
--- a/arch/m68k/include/asm/io_no.h
+++ b/arch/m68k/include/asm/io_no.h
@@ -145,7 +145,6 @@ static inline void io_insl(unsigned int addr, void *buf, int len)
145#define IOMAP_WRITETHROUGH 3 145#define IOMAP_WRITETHROUGH 3
146 146
147extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag); 147extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag);
148extern void __iounmap(void *addr, unsigned long size);
149 148
150static inline void *ioremap(unsigned long physaddr, unsigned long size) 149static inline void *ioremap(unsigned long physaddr, unsigned long size)
151{ 150{
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 9c384e294af9..561b03b5ddf8 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -12,6 +12,10 @@
12#define m5206sim_h 12#define m5206sim_h
13/****************************************************************************/ 13/****************************************************************************/
14 14
15#define CPU_NAME "COLDFIRE(m5206)"
16#define CPU_INSTR_PER_JIFFY 3
17
18#include <asm/m52xxacr.h>
15 19
16/* 20/*
17 * Define the 5206 SIM register set addresses. 21 * Define the 5206 SIM register set addresses.
@@ -88,6 +92,14 @@
88#define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */ 92#define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */
89#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */ 93#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */
90 94
95#if defined(CONFIG_NETtel)
96#define MCFUART_BASE1 0x180 /* Base address of UART1 */
97#define MCFUART_BASE2 0x140 /* Base address of UART2 */
98#else
99#define MCFUART_BASE1 0x140 /* Base address of UART1 */
100#define MCFUART_BASE2 0x180 /* Base address of UART2 */
101#endif
102
91/* 103/*
92 * Define system peripheral IRQ usage. 104 * Define system peripheral IRQ usage.
93 */ 105 */
@@ -95,7 +107,7 @@
95#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 107#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
96 108
97/* 109/*
98 * Generic GPIO 110 * Generic GPIO
99 */ 111 */
100#define MCFGPIO_PIN_MAX 8 112#define MCFGPIO_PIN_MAX 8
101#define MCFGPIO_IRQ_VECBASE -1 113#define MCFGPIO_IRQ_VECBASE -1
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index db824a4b136e..88ed8239fe4e 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -11,6 +11,11 @@
11#define m520xsim_h 11#define m520xsim_h
12/****************************************************************************/ 12/****************************************************************************/
13 13
14#define CPU_NAME "COLDFIRE(m520x)"
15#define CPU_INSTR_PER_JIFFY 3
16
17#include <asm/m52xxacr.h>
18
14/* 19/*
15 * Define the 520x SIM register set addresses. 20 * Define the 520x SIM register set addresses.
16 */ 21 */
@@ -54,6 +59,9 @@
54#define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */ 59#define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */
55#define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */ 60#define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */
56 61
62/*
63 * EPORT and GPIO registers.
64 */
57#define MCFEPORT_EPDDR 0xFC088002 65#define MCFEPORT_EPDDR 0xFC088002
58#define MCFEPORT_EPDR 0xFC088004 66#define MCFEPORT_EPDR 0xFC088004
59#define MCFEPORT_EPPDR 0xFC088005 67#define MCFEPORT_EPPDR 0xFC088005
@@ -97,6 +105,7 @@
97#define MCFGPIO_PCLRR_UART 0xFC0A402A 105#define MCFGPIO_PCLRR_UART 0xFC0A402A
98#define MCFGPIO_PCLRR_FECH 0xFC0A402B 106#define MCFGPIO_PCLRR_FECH 0xFC0A402B
99#define MCFGPIO_PCLRR_FECL 0xFC0A402C 107#define MCFGPIO_PCLRR_FECL 0xFC0A402C
108
100/* 109/*
101 * Generic GPIO support 110 * Generic GPIO support
102 */ 111 */
@@ -109,7 +118,6 @@
109#define MCFGPIO_PIN_MAX 80 118#define MCFGPIO_PIN_MAX 80
110#define MCFGPIO_IRQ_MAX 8 119#define MCFGPIO_IRQ_MAX 8
111#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 120#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
112/****************************************************************************/
113 121
114#define MCF_GPIO_PAR_UART (0xA4036) 122#define MCF_GPIO_PAR_UART (0xA4036)
115#define MCF_GPIO_PAR_FECI2C (0xA4033) 123#define MCF_GPIO_PAR_FECI2C (0xA4033)
@@ -126,6 +134,13 @@
126#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) 134#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
127 135
128/* 136/*
137 * UART module.
138 */
139#define MCFUART_BASE1 0x60000 /* Base address of UART1 */
140#define MCFUART_BASE2 0x64000 /* Base address of UART2 */
141#define MCFUART_BASE3 0x68000 /* Base address of UART2 */
142
143/*
129 * Reset Controll Unit. 144 * Reset Controll Unit.
130 */ 145 */
131#define MCF_RCR 0xFC0A0000 146#define MCF_RCR 0xFC0A0000
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index e8d06b24a48e..4ad7a00257a8 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -11,6 +11,10 @@
11#define m523xsim_h 11#define m523xsim_h
12/****************************************************************************/ 12/****************************************************************************/
13 13
14#define CPU_NAME "COLDFIRE(m523x)"
15#define CPU_INSTR_PER_JIFFY 3
16
17#include <asm/m52xxacr.h>
14 18
15/* 19/*
16 * Define the 523x SIM register set addresses. 20 * Define the 523x SIM register set addresses.
@@ -50,6 +54,13 @@
50#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 54#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
51#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 55#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
52 56
57/*
58 * UART module.
59 */
60#define MCFUART_BASE1 0x200 /* Base address of UART1 */
61#define MCFUART_BASE2 0x240 /* Base address of UART2 */
62#define MCFUART_BASE3 0x280 /* Base address of UART3 */
63
53#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) 64#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
54#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) 65#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
55#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) 66#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 79b7b402f3c9..4908b118f2fd 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -11,6 +11,11 @@
11#define m5249sim_h 11#define m5249sim_h
12/****************************************************************************/ 12/****************************************************************************/
13 13
14#define CPU_NAME "COLDFIRE(m5249)"
15#define CPU_INSTR_PER_JIFFY 3
16
17#include <asm/m52xxacr.h>
18
14/* 19/*
15 * Define the 5249 SIM register set addresses. 20 * Define the 5249 SIM register set addresses.
16 */ 21 */
@@ -56,6 +61,11 @@
56#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ 61#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
57#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ 62#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
58 63
64/*
65 * UART module.
66 */
67#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
68#define MCFUART_BASE2 0x200 /* Base address of UART2 */
59 69
60/* 70/*
61 * Some symbol defines for the above... 71 * Some symbol defines for the above...
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index df3332c2317d..b7cc50abc831 100644
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -12,6 +12,11 @@
12#define m5272sim_h 12#define m5272sim_h
13/****************************************************************************/ 13/****************************************************************************/
14 14
15#define CPU_NAME "COLDFIRE(m5272)"
16#define CPU_INSTR_PER_JIFFY 3
17
18#include <asm/m52xxacr.h>
19
15/* 20/*
16 * Define the 5272 SIM register set addresses. 21 * Define the 5272 SIM register set addresses.
17 */ 22 */
@@ -62,6 +67,9 @@
62#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ 67#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
63#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ 68#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
64 69
70#define MCFUART_BASE1 0x100 /* Base address of UART1 */
71#define MCFUART_BASE2 0x140 /* Base address of UART2 */
72
65#define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */ 73#define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */
66#define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */ 74#define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */
67#define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */ 75#define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 1feb46f108ce..e8042e8bc003 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -11,6 +11,10 @@
11#define m527xsim_h 11#define m527xsim_h
12/****************************************************************************/ 12/****************************************************************************/
13 13
14#define CPU_NAME "COLDFIRE(m527x)"
15#define CPU_INSTR_PER_JIFFY 3
16
17#include <asm/m52xxacr.h>
14 18
15/* 19/*
16 * Define the 5270/5271 SIM register set addresses. 20 * Define the 5270/5271 SIM register set addresses.
@@ -55,6 +59,12 @@
55#define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */ 59#define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */
56#endif 60#endif
57 61
62/*
63 * UART module.
64 */
65#define MCFUART_BASE1 0x200 /* Base address of UART1 */
66#define MCFUART_BASE2 0x240 /* Base address of UART2 */
67#define MCFUART_BASE3 0x280 /* Base address of UART3 */
58 68
59#ifdef CONFIG_M5271 69#ifdef CONFIG_M5271
60#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) 70#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index 891cbedad972..a6d2f4d9aaa0 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -11,6 +11,10 @@
11#define m528xsim_h 11#define m528xsim_h
12/****************************************************************************/ 12/****************************************************************************/
13 13
14#define CPU_NAME "COLDFIRE(m528x)"
15#define CPU_INSTR_PER_JIFFY 3
16
17#include <asm/m52xxacr.h>
14 18
15/* 19/*
16 * Define the 5280/5282 SIM register set addresses. 20 * Define the 5280/5282 SIM register set addresses.
@@ -42,6 +46,13 @@
42#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ 46#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
43 47
44/* 48/*
49 * UART module.
50 */
51#define MCFUART_BASE1 0x200 /* Base address of UART1 */
52#define MCFUART_BASE2 0x240 /* Base address of UART2 */
53#define MCFUART_BASE3 0x280 /* Base address of UART3 */
54
55/*
45 * GPIO registers 56 * GPIO registers
46 */ 57 */
47#define MCFGPIO_PORTA (MCF_IPSBAR + 0x00100000) 58#define MCFGPIO_PORTA (MCF_IPSBAR + 0x00100000)
diff --git a/arch/m68k/include/asm/m52xxacr.h b/arch/m68k/include/asm/m52xxacr.h
new file mode 100644
index 000000000000..abc391a9ae8d
--- /dev/null
+++ b/arch/m68k/include/asm/m52xxacr.h
@@ -0,0 +1,94 @@
1/****************************************************************************/
2
3/*
4 * m52xxacr.h -- ColdFire version 2 core cache support
5 *
6 * (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
7 */
8
9/****************************************************************************/
10#ifndef m52xxacr_h
11#define m52xxacr_h
12/****************************************************************************/
13
14/*
15 * All varients of the ColdFire using version 2 cores have a similar
16 * cache setup. Although not absolutely identical the cache register
17 * definitions are compatible for all of them. Mostly they support a
18 * configurable cache memory that can be instruction only, data only,
19 * or split instruction and data. The exception is the very old version 2
20 * core based parts, like the 5206(e), 5249 and 5272, which are instruction
21 * cache only. Cache size varies from 2k up to 16k.
22 */
23
24/*
25 * Define the Cache Control register flags.
26 */
27#define CACR_CENB 0x80000000 /* Enable cache */
28#define CACR_CDPI 0x10000000 /* Disable invalidation by CPUSHL */
29#define CACR_CFRZ 0x08000000 /* Cache freeze mode */
30#define CACR_CINV 0x01000000 /* Invalidate cache */
31#define CACR_DISI 0x00800000 /* Disable instruction cache */
32#define CACR_DISD 0x00400000 /* Disable data cache */
33#define CACR_INVI 0x00200000 /* Invalidate instruction cache */
34#define CACR_INVD 0x00100000 /* Invalidate data cache */
35#define CACR_CEIB 0x00000400 /* Non-cachable instruction burst */
36#define CACR_DCM 0x00000200 /* Default cache mode */
37#define CACR_DBWE 0x00000100 /* Buffered write enable */
38#define CACR_DWP 0x00000020 /* Write protection */
39#define CACR_EUSP 0x00000010 /* Enable separate user a7 */
40
41/*
42 * Define the Access Control register flags.
43 */
44#define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */
45#define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */
46#define ACR_ENABLE 0x00008000 /* Enable this ACR */
47#define ACR_USER 0x00000000 /* Allow only user accesses */
48#define ACR_SUPER 0x00002000 /* Allow supervisor access only */
49#define ACR_ANY 0x00004000 /* Allow any access type */
50#define ACR_CENB 0x00000000 /* Caching of region enabled */
51#define ACR_CDIS 0x00000040 /* Caching of region disabled */
52#define ACR_BWE 0x00000020 /* Write buffer enabled */
53#define ACR_WPROTECT 0x00000004 /* Write protect region */
54
55/*
56 * Set the cache controller settings we will use. On the cores that support
57 * a split cache configuration we allow all the combinations at Kconfig
58 * time. For those cores that only have an instruction cache we just set
59 * that as on.
60 */
61#if defined(CONFIG_CACHE_I)
62#define CACHE_TYPE (CACR_DISD + CACR_EUSP)
63#define CACHE_INVTYPEI 0
64#elif defined(CONFIG_CACHE_D)
65#define CACHE_TYPE (CACR_DISI + CACR_EUSP)
66#define CACHE_INVTYPED 0
67#elif defined(CONFIG_CACHE_BOTH)
68#define CACHE_TYPE CACR_EUSP
69#define CACHE_INVTYPEI CACR_INVI
70#define CACHE_INVTYPED CACR_INVD
71#else
72/* This is the instruction cache only devices (no split cache, no eusp) */
73#define CACHE_TYPE 0
74#define CACHE_INVTYPEI 0
75#endif
76
77#define CACHE_INIT (CACR_CINV + CACHE_TYPE)
78#define CACHE_MODE (CACR_CENB + CACHE_TYPE + CACR_DCM)
79
80#define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV)
81#if defined(CACHE_INVTYPEI)
82#define CACHE_INVALIDATEI (CACHE_MODE + CACR_CINV + CACHE_INVTYPEI)
83#endif
84#if defined(CACHE_INVTYPED)
85#define CACHE_INVALIDATED (CACHE_MODE + CACR_CINV + CACHE_INVTYPED)
86#endif
87
88#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \
89 (0x000f0000) + \
90 (ACR_ENABLE + ACR_ANY + ACR_CENB + ACR_BWE))
91#define ACR1_MODE 0
92
93/****************************************************************************/
94#endif /* m52xxsim_h */
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index c6830e5b54ce..0bf57397e7a9 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -14,6 +14,11 @@
14#define m5307sim_h 14#define m5307sim_h
15/****************************************************************************/ 15/****************************************************************************/
16 16
17#define CPU_NAME "COLDFIRE(m5307)"
18#define CPU_INSTR_PER_JIFFY 3
19
20#include <asm/m53xxacr.h>
21
17/* 22/*
18 * Define the 5307 SIM register set addresses. 23 * Define the 5307 SIM register set addresses.
19 */ 24 */
@@ -94,6 +99,17 @@
94#define MCFSIM_PADAT (MCF_MBAR + 0x248) 99#define MCFSIM_PADAT (MCF_MBAR + 0x248)
95 100
96/* 101/*
102 * UART module.
103 */
104#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
105#define MCFUART_BASE1 0x200 /* Base address of UART1 */
106#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */
107#else
108#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
109#define MCFUART_BASE2 0x200 /* Base address of UART2 */
110#endif
111
112/*
97 * Generic GPIO support 113 * Generic GPIO support
98 */ 114 */
99#define MCFGPIO_PIN_MAX 16 115#define MCFGPIO_PIN_MAX 16
@@ -146,32 +162,5 @@
146#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 162#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
147#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 163#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
148 164
149/*
150 * Define the Cache register flags.
151 */
152#define CACR_EC (1<<31)
153#define CACR_ESB (1<<29)
154#define CACR_DPI (1<<28)
155#define CACR_HLCK (1<<27)
156#define CACR_CINVA (1<<24)
157#define CACR_DNFB (1<<10)
158#define CACR_DCM_WTHRU (0<<8)
159#define CACR_DCM_WBACK (1<<8)
160#define CACR_DCM_OFF_PRE (2<<8)
161#define CACR_DCM_OFF_IMP (3<<8)
162#define CACR_DW (1<<5)
163
164#define ACR_BASE_POS 24
165#define ACR_MASK_POS 16
166#define ACR_ENABLE (1<<15)
167#define ACR_USER (0<<13)
168#define ACR_SUPER (1<<13)
169#define ACR_ANY (2<<13)
170#define ACR_CM_WTHRU (0<<5)
171#define ACR_CM_WBACK (1<<5)
172#define ACR_CM_OFF_PRE (2<<5)
173#define ACR_CM_OFF_IMP (3<<5)
174#define ACR_WPROTECT (1<<2)
175
176/****************************************************************************/ 165/****************************************************************************/
177#endif /* m5307sim_h */ 166#endif /* m5307sim_h */
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index c4bf1c81e3cf..e6470f8ca324 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -9,6 +9,11 @@
9#define m532xsim_h 9#define m532xsim_h
10/****************************************************************************/ 10/****************************************************************************/
11 11
12#define CPU_NAME "COLDFIRE(m532x)"
13#define CPU_INSTR_PER_JIFFY 3
14
15#include <asm/m53xxacr.h>
16
12#define MCF_REG32(x) (*(volatile unsigned long *)(x)) 17#define MCF_REG32(x) (*(volatile unsigned long *)(x))
13#define MCF_REG16(x) (*(volatile unsigned short *)(x)) 18#define MCF_REG16(x) (*(volatile unsigned short *)(x))
14#define MCF_REG08(x) (*(volatile unsigned char *)(x)) 19#define MCF_REG08(x) (*(volatile unsigned char *)(x))
@@ -74,31 +79,11 @@
74#define MCF_IRQ_PROFILER (64 + 33) /* Timer1 */ 79#define MCF_IRQ_PROFILER (64 + 33) /* Timer1 */
75 80
76/* 81/*
77 * Define the Cache register flags. 82 * UART module.
78 */ 83 */
79#define CACR_EC (1<<31) 84#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */
80#define CACR_ESB (1<<29) 85#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */
81#define CACR_DPI (1<<28) 86#define MCFUART_BASE3 0xFC068000 /* Base address of UART3 */
82#define CACR_HLCK (1<<27)
83#define CACR_CINVA (1<<24)
84#define CACR_DNFB (1<<10)
85#define CACR_DCM_WTHRU (0<<8)
86#define CACR_DCM_WBACK (1<<8)
87#define CACR_DCM_OFF_PRE (2<<8)
88#define CACR_DCM_OFF_IMP (3<<8)
89#define CACR_DW (1<<5)
90
91#define ACR_BASE_POS 24
92#define ACR_MASK_POS 16
93#define ACR_ENABLE (1<<15)
94#define ACR_USER (0<<13)
95#define ACR_SUPER (1<<13)
96#define ACR_ANY (2<<13)
97#define ACR_CM_WTHRU (0<<5)
98#define ACR_CM_WBACK (1<<5)
99#define ACR_CM_OFF_PRE (2<<5)
100#define ACR_CM_OFF_IMP (3<<5)
101#define ACR_WPROTECT (1<<2)
102 87
103/********************************************************************* 88/*********************************************************************
104 * 89 *
diff --git a/arch/m68k/include/asm/m53xxacr.h b/arch/m68k/include/asm/m53xxacr.h
new file mode 100644
index 000000000000..cd952b0a8bd3
--- /dev/null
+++ b/arch/m68k/include/asm/m53xxacr.h
@@ -0,0 +1,101 @@
1/****************************************************************************/
2
3/*
4 * m53xxacr.h -- ColdFire version 3 core cache support
5 *
6 * (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
7 */
8
9/****************************************************************************/
10#ifndef m53xxacr_h
11#define m53xxacr_h
12/****************************************************************************/
13
14/*
15 * All varients of the ColdFire using version 3 cores have a similar
16 * cache setup. They have a unified instruction and data cache, with
17 * configurable write-through or copy-back operation.
18 */
19
20/*
21 * Define the Cache Control register flags.
22 */
23#define CACR_EC 0x80000000 /* Enable cache */
24#define CACR_ESB 0x20000000 /* Enable store buffer */
25#define CACR_DPI 0x10000000 /* Disable invalidation by CPUSHL */
26#define CACR_HLCK 0x08000000 /* Half cache lock mode */
27#define CACR_CINVA 0x01000000 /* Invalidate cache */
28#define CACR_DNFB 0x00000400 /* Inhibited fill buffer */
29#define CACR_DCM_WT 0x00000000 /* Cacheable write-through */
30#define CACR_DCM_CB 0x00000100 /* Cacheable copy-back */
31#define CACR_DCM_PRE 0x00000200 /* Cache inhibited, precise */
32#define CACR_DCM_IMPRE 0x00000300 /* Cache inhibited, imprecise */
33#define CACR_WPROTECT 0x00000020 /* Write protect*/
34#define CACR_EUSP 0x00000010 /* Eanble separate user a7 */
35
36/*
37 * Define the Access Control register flags.
38 */
39#define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */
40#define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */
41#define ACR_ENABLE 0x00008000 /* Enable this ACR */
42#define ACR_USER 0x00000000 /* Allow only user accesses */
43#define ACR_SUPER 0x00002000 /* Allow supervisor access only */
44#define ACR_ANY 0x00004000 /* Allow any access type */
45#define ACR_CM_WT 0x00000000 /* Cacheable, write-through */
46#define ACR_CM_CB 0x00000020 /* Cacheable, copy-back */
47#define ACR_CM_PRE 0x00000040 /* Cache inhibited, precise */
48#define ACR_CM_IMPRE 0x00000060 /* Cache inhibited, imprecise */
49#define ACR_WPROTECT 0x00000004 /* Write protect region */
50
51/*
52 * Define the cache type and arrangement (needed for pushes).
53 */
54#if defined(CONFIG_M5307)
55#define CACHE_SIZE 0x2000 /* 8k of unified cache */
56#define ICACHE_SIZE CACHE_SIZE
57#define DCACHE_SIZE CACHE_SIZE
58#elif defined(CONFIG_M532x)
59#define CACHE_SIZE 0x4000 /* 32k of unified cache */
60#define ICACHE_SIZE CACHE_SIZE
61#define DCACHE_SIZE CACHE_SIZE
62#endif
63
64#define CACHE_LINE_SIZE 16 /* 16 byte line size */
65#define CACHE_WAYS 4 /* 4 ways - set associative */
66
67/*
68 * Set the cache controller settings we will use. This default in the
69 * CACR is cache inhibited, we use the ACR register to set cacheing
70 * enabled on the regions we want (eg RAM).
71 */
72#if defined(CONFIG_CACHE_COPYBACK)
73#define CACHE_TYPE ACR_CM_CB
74#define CACHE_PUSH
75#else
76#define CACHE_TYPE ACR_CM_WT
77#endif
78
79#ifdef CONFIG_COLDFIRE_SW_A7
80#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE)
81#else
82#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE + CACR_EUSP)
83#endif
84
85/*
86 * Unified cache means we will never need to flush for coherency of
87 * instruction fetch. We will need to flush to maintain memory/DMA
88 * coherency though in all cases. And for copyback caches we will need
89 * to push cached data as well.
90 */
91#define CACHE_INIT CACR_CINVA
92#define CACHE_INVALIDATE CACR_CINVA
93#define CACHE_INVALIDATED CACR_CINVA
94
95#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \
96 (0x000f0000) + \
97 (ACR_ENABLE + ACR_ANY + CACHE_TYPE))
98#define ACR1_MODE 0
99
100/****************************************************************************/
101#endif /* m53xxsim_h */
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index c399abbf953c..75f5c28a551d 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -14,6 +14,11 @@
14#define m5407sim_h 14#define m5407sim_h
15/****************************************************************************/ 15/****************************************************************************/
16 16
17#define CPU_NAME "COLDFIRE(m5407)"
18#define CPU_INSTR_PER_JIFFY 3
19
20#include <asm/m54xxacr.h>
21
17/* 22/*
18 * Define the 5407 SIM register set addresses. 23 * Define the 5407 SIM register set addresses.
19 */ 24 */
@@ -73,6 +78,9 @@
73#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ 78#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
74#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ 79#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
75 80
81#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
82#define MCFUART_BASE2 0x200 /* Base address of UART2 */
83
76#define MCFSIM_PADDR (MCF_MBAR + 0x244) 84#define MCFSIM_PADDR (MCF_MBAR + 0x244)
77#define MCFSIM_PADAT (MCF_MBAR + 0x248) 85#define MCFSIM_PADAT (MCF_MBAR + 0x248)
78 86
@@ -117,39 +125,5 @@
117#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 125#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
118#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 126#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
119 127
120/*
121 * Define the Cache register flags.
122 */
123#define CACR_DEC 0x80000000 /* Enable data cache */
124#define CACR_DWP 0x40000000 /* Data write protection */
125#define CACR_DESB 0x20000000 /* Enable data store buffer */
126#define CACR_DDPI 0x10000000 /* Disable CPUSHL */
127#define CACR_DHCLK 0x08000000 /* Half data cache lock mode */
128#define CACR_DDCM_WT 0x00000000 /* Write through cache*/
129#define CACR_DDCM_CP 0x02000000 /* Copyback cache */
130#define CACR_DDCM_P 0x04000000 /* No cache, precise */
131#define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */
132#define CACR_DCINVA 0x01000000 /* Invalidate data cache */
133#define CACR_BEC 0x00080000 /* Enable branch cache */
134#define CACR_BCINVA 0x00040000 /* Invalidate branch cache */
135#define CACR_IEC 0x00008000 /* Enable instruction cache */
136#define CACR_DNFB 0x00002000 /* Inhibited fill buffer */
137#define CACR_IDPI 0x00001000 /* Disable CPUSHL */
138#define CACR_IHLCK 0x00000800 /* Intruction cache half lock */
139#define CACR_IDCM 0x00000400 /* Intruction cache inhibit */
140#define CACR_ICINVA 0x00000100 /* Invalidate instr cache */
141
142#define ACR_BASE_POS 24 /* Address Base */
143#define ACR_MASK_POS 16 /* Address Mask */
144#define ACR_ENABLE 0x00008000 /* Enable address */
145#define ACR_USER 0x00000000 /* User mode access only */
146#define ACR_SUPER 0x00002000 /* Supervisor mode only */
147#define ACR_ANY 0x00004000 /* Match any access mode */
148#define ACR_CM_WT 0x00000000 /* Write through mode */
149#define ACR_CM_CP 0x00000020 /* Copyback mode */
150#define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */
151#define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */
152#define ACR_WPROTECT 0x00000004 /* Write protect */
153
154/****************************************************************************/ 128/****************************************************************************/
155#endif /* m5407sim_h */ 129#endif /* m5407sim_h */
diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h
new file mode 100644
index 000000000000..16a1835f9b2a
--- /dev/null
+++ b/arch/m68k/include/asm/m54xxacr.h
@@ -0,0 +1,97 @@
1/*
2 * Bit definitions for the MCF54xx ACR and CACR registers.
3 */
4
5#ifndef m54xxacr_h
6#define m54xxacr_h
7
8/*
9 * Define the Cache register flags.
10 */
11#define CACR_DEC 0x80000000 /* Enable data cache */
12#define CACR_DWP 0x40000000 /* Data write protection */
13#define CACR_DESB 0x20000000 /* Enable data store buffer */
14#define CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */
15#define CACR_DHCLK 0x08000000 /* Half data cache lock mode */
16#define CACR_DDCM_WT 0x00000000 /* Write through cache*/
17#define CACR_DDCM_CP 0x02000000 /* Copyback cache */
18#define CACR_DDCM_P 0x04000000 /* No cache, precise */
19#define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */
20#define CACR_DCINVA 0x01000000 /* Invalidate data cache */
21#define CACR_BEC 0x00080000 /* Enable branch cache */
22#define CACR_BCINVA 0x00040000 /* Invalidate branch cache */
23#define CACR_IEC 0x00008000 /* Enable instruction cache */
24#define CACR_DNFB 0x00002000 /* Inhibited fill buffer */
25#define CACR_IDPI 0x00001000 /* Disable CPUSHL */
26#define CACR_IHLCK 0x00000800 /* Intruction cache half lock */
27#define CACR_IDCM 0x00000400 /* Intruction cache inhibit */
28#define CACR_ICINVA 0x00000100 /* Invalidate instr cache */
29#define CACR_EUSP 0x00000020 /* Enable separate user a7 */
30
31#define ACR_BASE_POS 24 /* Address Base */
32#define ACR_MASK_POS 16 /* Address Mask */
33#define ACR_ENABLE 0x00008000 /* Enable address */
34#define ACR_USER 0x00000000 /* User mode access only */
35#define ACR_SUPER 0x00002000 /* Supervisor mode only */
36#define ACR_ANY 0x00004000 /* Match any access mode */
37#define ACR_CM_WT 0x00000000 /* Write through mode */
38#define ACR_CM_CP 0x00000020 /* Copyback mode */
39#define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */
40#define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */
41#define ACR_CM 0x00000060 /* Cache mode mask */
42#define ACR_WPROTECT 0x00000004 /* Write protect */
43
44#if defined(CONFIG_M5407)
45
46#define ICACHE_SIZE 0x4000 /* instruction - 16k */
47#define DCACHE_SIZE 0x2000 /* data - 8k */
48
49#elif defined(CONFIG_M54xx)
50
51#define ICACHE_SIZE 0x8000 /* instruction - 32k */
52#define DCACHE_SIZE 0x8000 /* data - 32k */
53
54#endif
55
56#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */
57#define CACHE_WAYS 4 /* 4 ways */
58
59/*
60 * Version 4 cores have a true harvard style separate instruction
61 * and data cache. Enable data and instruction caches, also enable write
62 * buffers and branch accelerator.
63 */
64/* attention : enabling CACR_DESB requires a "nop" to flush the store buffer */
65/* use '+' instead of '|' for assembler's sake */
66
67 /* Enable data cache */
68 /* Enable data store buffer */
69 /* outside ACRs : No cache, precise */
70 /* Enable instruction+branch caches */
71#if defined(CONFIG_M5407)
72#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC)
73#else
74#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP)
75#endif
76#if defined(CONFIG_CACHE_COPYBACK)
77#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_CP)
78#else
79#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT)
80#endif
81#define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY)
82
83#define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)
84#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)
85#define CACHE_INVALIDATEI (CACHE_MODE+CACR_BCINVA+CACR_ICINVA)
86#define CACHE_INVALIDATED (CACHE_MODE+CACR_DCINVA)
87#define ACR0_MODE (0x000f0000+DATA_CACHE_MODE)
88#define ACR1_MODE 0
89#define ACR2_MODE (0x000f0000+INSN_CACHE_MODE)
90#define ACR3_MODE 0
91
92#if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP)
93/* Copyback cache mode must push dirty cache lines first */
94#define CACHE_PUSH
95#endif
96
97#endif /* m54xxacr_h */
diff --git a/arch/m68k/include/asm/m548xgpt.h b/arch/m68k/include/asm/m54xxgpt.h
index 33b2eef90f0a..df75dd87ae7a 100644
--- a/arch/m68k/include/asm/m548xgpt.h
+++ b/arch/m68k/include/asm/m54xxgpt.h
@@ -1,13 +1,13 @@
1/* 1/*
2 * File: m548xgpt.h 2 * File: m54xxgpt.h
3 * Purpose: Register and bit definitions for the MCF548X 3 * Purpose: Register and bit definitions for the MCF54XX
4 * 4 *
5 * Notes: 5 * Notes:
6 * 6 *
7 */ 7 */
8 8
9#ifndef m548xgpt_h 9#ifndef m54xxgpt_h
10#define m548xgpt_h 10#define m54xxgpt_h
11 11
12/********************************************************************* 12/*********************************************************************
13* 13*
@@ -87,4 +87,4 @@
87 87
88/********************************************************************/ 88/********************************************************************/
89 89
90#endif /* m548xgpt_h */ 90#endif /* m54xxgpt_h */
diff --git a/arch/m68k/include/asm/m548xsim.h b/arch/m68k/include/asm/m54xxsim.h
index 149135ef30d2..462ae5328441 100644
--- a/arch/m68k/include/asm/m548xsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -1,11 +1,16 @@
1/* 1/*
2 * m548xsim.h -- ColdFire 547x/548x System Integration Unit support. 2 * m54xxsim.h -- ColdFire 547x/548x System Integration Unit support.
3 */ 3 */
4 4
5#ifndef m548xsim_h 5#ifndef m54xxsim_h
6#define m548xsim_h 6#define m54xxsim_h
7 7
8#define MCFINT_VECBASE 64 8#define CPU_NAME "COLDFIRE(m54xx)"
9#define CPU_INSTR_PER_JIFFY 2
10
11#include <asm/m54xxacr.h>
12
13#define MCFINT_VECBASE 64
9 14
10/* 15/*
11 * Interrupt Controller Registers 16 * Interrupt Controller Registers
@@ -22,6 +27,14 @@
22#define MCFINTC_ICR0 0x40 /* Base ICR register */ 27#define MCFINTC_ICR0 0x40 /* Base ICR register */
23 28
24/* 29/*
30 * UART module.
31 */
32#define MCFUART_BASE1 0x8600 /* Base address of UART1 */
33#define MCFUART_BASE2 0x8700 /* Base address of UART2 */
34#define MCFUART_BASE3 0x8800 /* Base address of UART3 */
35#define MCFUART_BASE4 0x8900 /* Base address of UART4 */
36
37/*
25 * Define system peripheral IRQ usage. 38 * Define system peripheral IRQ usage.
26 */ 39 */
27#define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */ 40#define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */
@@ -52,4 +65,4 @@
52#define MCF_PAR_PSC_RTS_RTS (0x30) 65#define MCF_PAR_PSC_RTS_RTS (0x30)
53#define MCF_PAR_PSC_CANRX (0x40) 66#define MCF_PAR_PSC_CANRX (0x40)
54 67
55#endif /* m548xsim_h */ 68#endif /* m54xxsim_h */
diff --git a/arch/m68k/include/asm/mcfcache.h b/arch/m68k/include/asm/mcfcache.h
deleted file mode 100644
index f49dfc09f70a..000000000000
--- a/arch/m68k/include/asm/mcfcache.h
+++ /dev/null
@@ -1,150 +0,0 @@
1/****************************************************************************/
2
3/*
4 * mcfcache.h -- ColdFire CPU cache support code
5 *
6 * (C) Copyright 2004, Greg Ungerer <gerg@snapgear.com>
7 */
8
9/****************************************************************************/
10#ifndef __M68KNOMMU_MCFCACHE_H
11#define __M68KNOMMU_MCFCACHE_H
12/****************************************************************************/
13
14
15/*
16 * The different ColdFire families have different cache arrangments.
17 * Everything from a small instruction only cache, to configurable
18 * data and/or instruction cache, to unified instruction/data, to
19 * harvard style separate instruction and data caches.
20 */
21
22#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272)
23/*
24 * Simple version 2 core cache. These have instruction cache only,
25 * we just need to invalidate it and enable it.
26 */
27.macro CACHE_ENABLE
28 movel #0x01000000,%d0 /* invalidate cache cmd */
29 movec %d0,%CACR /* do invalidate cache */
30 movel #0x80000100,%d0 /* setup cache mask */
31 movec %d0,%CACR /* enable cache */
32.endm
33#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */
34
35#if defined(CONFIG_M523x) || defined(CONFIG_M527x)
36/*
37 * New version 2 cores have a configurable split cache arrangement.
38 * For now I am just enabling instruction cache - but ultimately I
39 * think a split instruction/data cache would be better.
40 */
41.macro CACHE_ENABLE
42 movel #0x01400000,%d0
43 movec %d0,%CACR /* invalidate cache */
44 nop
45 movel #0x0000c000,%d0 /* set SDRAM cached only */
46 movec %d0,%ACR0
47 movel #0x00000000,%d0 /* no other regions cached */
48 movec %d0,%ACR1
49 movel #0x80400100,%d0 /* configure cache */
50 movec %d0,%CACR /* enable cache */
51 nop
52.endm
53#endif /* CONFIG_M523x || CONFIG_M527x */
54
55#if defined(CONFIG_M528x)
56.macro CACHE_ENABLE
57 nop
58 movel #0x01000000, %d0
59 movec %d0, %CACR /* Invalidate cache */
60 nop
61 movel #0x0000c020, %d0 /* Set SDRAM cached only */
62 movec %d0, %ACR0
63 movel #0x00000000, %d0 /* No other regions cached */
64 movec %d0, %ACR1
65 movel #0x80000200, %d0 /* Setup cache mask */
66 movec %d0, %CACR /* Enable cache */
67 nop
68.endm
69#endif /* CONFIG_M528x */
70
71#if defined(CONFIG_M5249) || defined(CONFIG_M5307)
72/*
73 * The version 3 core cache. Oddly enough the version 2 core 5249
74 * has the same SDRAM and cache setup as the version 3 cores.
75 * This is a single unified instruction/data cache.
76 */
77.macro CACHE_ENABLE
78 movel #0x01000000,%d0 /* invalidate whole cache */
79 movec %d0,%CACR
80 nop
81#if defined(DEBUGGER_COMPATIBLE_CACHE) || defined(CONFIG_SECUREEDGEMP3)
82 movel #0x0000c000,%d0 /* set SDRAM cached (write-thru) */
83#else
84 movel #0x0000c020,%d0 /* set SDRAM cached (copyback) */
85#endif
86 movec %d0,%ACR0
87 movel #0x00000000,%d0 /* no other regions cached */
88 movec %d0,%ACR1
89 movel #0xa0000200,%d0 /* enable cache */
90 movec %d0,%CACR
91 nop
92.endm
93#endif /* CONFIG_M5249 || CONFIG_M5307 */
94
95#if defined(CONFIG_M532x)
96.macro CACHE_ENABLE
97 movel #0x01000000,%d0 /* invalidate cache cmd */
98 movec %d0,%CACR /* do invalidate cache */
99 nop
100 movel #0x4001C000,%d0 /* set SDRAM cached (write-thru) */
101 movec %d0,%ACR0
102 movel #0x00000000,%d0 /* no other regions cached */
103 movec %d0,%ACR1
104 movel #0x80000200,%d0 /* setup cache mask */
105 movec %d0,%CACR /* enable cache */
106 nop
107.endm
108#endif /* CONFIG_M532x */
109
110#if defined(CONFIG_M5407) || defined(CONFIG_M548x)
111/*
112 * Version 4 cores have a true harvard style separate instruction
113 * and data cache. Invalidate and enable cache, also enable write
114 * buffers and branch accelerator.
115 */
116.macro CACHE_ENABLE
117 movel #0x01040100,%d0 /* invalidate whole cache */
118 movec %d0,%CACR
119 nop
120 movel #0x000fc000,%d0 /* set SDRAM cached only */
121 movec %d0, %ACR0
122 movel #0x00000000,%d0 /* no other regions cached */
123 movec %d0, %ACR1
124 movel #0x000fc000,%d0 /* set SDRAM cached only */
125 movec %d0, %ACR2
126 movel #0x00000000,%d0 /* no other regions cached */
127 movec %d0, %ACR3
128 movel #0xb6088400,%d0 /* enable caches */
129 movec %d0,%CACR
130 nop
131.endm
132#endif /* CONFIG_M5407 */
133
134#if defined(CONFIG_M520x)
135.macro CACHE_ENABLE
136 move.l #0x01000000,%d0 /* invalidate whole cache */
137 movec %d0,%CACR
138 nop
139 move.l #0x0000c000,%d0 /* set SDRAM cached (write-thru) */
140 movec %d0,%ACR0
141 move.l #0x00000000,%d0 /* no other regions cached */
142 movec %d0,%ACR1
143 move.l #0x80400000,%d0 /* enable 8K instruction cache */
144 movec %d0,%CACR
145 nop
146.endm
147#endif /* CONFIG_M520x */
148
149/****************************************************************************/
150#endif /* __M68KNOMMU_MCFCACHE_H */
diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h
index 6901fd68165b..ebd0304054ad 100644
--- a/arch/m68k/include/asm/mcfsim.h
+++ b/arch/m68k/include/asm/mcfsim.h
@@ -41,8 +41,8 @@
41#elif defined(CONFIG_M5407) 41#elif defined(CONFIG_M5407)
42#include <asm/m5407sim.h> 42#include <asm/m5407sim.h>
43#include <asm/mcfintc.h> 43#include <asm/mcfintc.h>
44#elif defined(CONFIG_M548x) 44#elif defined(CONFIG_M54xx)
45#include <asm/m548xsim.h> 45#include <asm/m54xxsim.h>
46#endif 46#endif
47 47
48/****************************************************************************/ 48/****************************************************************************/
diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h
index db72e2b889ca..2abedff0a694 100644
--- a/arch/m68k/include/asm/mcfuart.h
+++ b/arch/m68k/include/asm/mcfuart.h
@@ -12,49 +12,6 @@
12#define mcfuart_h 12#define mcfuart_h
13/****************************************************************************/ 13/****************************************************************************/
14 14
15/*
16 * Define the base address of the UARTS within the MBAR address
17 * space.
18 */
19#if defined(CONFIG_M5272)
20#define MCFUART_BASE1 0x100 /* Base address of UART1 */
21#define MCFUART_BASE2 0x140 /* Base address of UART2 */
22#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e)
23#if defined(CONFIG_NETtel)
24#define MCFUART_BASE1 0x180 /* Base address of UART1 */
25#define MCFUART_BASE2 0x140 /* Base address of UART2 */
26#else
27#define MCFUART_BASE1 0x140 /* Base address of UART1 */
28#define MCFUART_BASE2 0x180 /* Base address of UART2 */
29#endif
30#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
31#define MCFUART_BASE1 0x200 /* Base address of UART1 */
32#define MCFUART_BASE2 0x240 /* Base address of UART2 */
33#define MCFUART_BASE3 0x280 /* Base address of UART3 */
34#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
35#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
36#define MCFUART_BASE1 0x200 /* Base address of UART1 */
37#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */
38#else
39#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
40#define MCFUART_BASE2 0x200 /* Base address of UART2 */
41#endif
42#elif defined(CONFIG_M520x)
43#define MCFUART_BASE1 0x60000 /* Base address of UART1 */
44#define MCFUART_BASE2 0x64000 /* Base address of UART2 */
45#define MCFUART_BASE3 0x68000 /* Base address of UART2 */
46#elif defined(CONFIG_M532x)
47#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */
48#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */
49#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */
50#elif defined(CONFIG_M548x)
51#define MCFUART_BASE1 0x8600 /* on M548x */
52#define MCFUART_BASE2 0x8700 /* on M548x */
53#define MCFUART_BASE3 0x8800 /* on M548x */
54#define MCFUART_BASE4 0x8900 /* on M548x */
55#endif
56
57
58#include <linux/serial_core.h> 15#include <linux/serial_core.h>
59#include <linux/platform_device.h> 16#include <linux/platform_device.h>
60 17
@@ -217,7 +174,7 @@ struct mcf_platform_uart {
217#define MCFUART_URF_RXS 0xc0 /* Receiver status */ 174#define MCFUART_URF_RXS 0xc0 /* Receiver status */
218#endif 175#endif
219 176
220#if defined(CONFIG_M548x) 177#if defined(CONFIG_M54xx)
221#define MCFUART_TXFIFOSIZE 512 178#define MCFUART_TXFIFOSIZE 512
222#elif defined(CONFIG_M5272) 179#elif defined(CONFIG_M5272)
223#define MCFUART_TXFIFOSIZE 25 180#define MCFUART_TXFIFOSIZE 25
diff --git a/arch/m68k/include/asm/processor.h b/arch/m68k/include/asm/processor.h
index 7a6a7590cc02..278c69bad57a 100644
--- a/arch/m68k/include/asm/processor.h
+++ b/arch/m68k/include/asm/processor.h
@@ -20,23 +20,26 @@
20 20
21static inline unsigned long rdusp(void) 21static inline unsigned long rdusp(void)
22{ 22{
23#ifdef CONFIG_COLDFIRE 23#ifdef CONFIG_COLDFIRE_SW_A7
24 extern unsigned int sw_usp; 24 extern unsigned int sw_usp;
25 return sw_usp; 25 return sw_usp;
26#else 26#else
27 unsigned long usp; 27 register unsigned long usp __asm__("a0");
28 __asm__ __volatile__("move %/usp,%0" : "=a" (usp)); 28 /* move %usp,%a0 */
29 __asm__ __volatile__(".word 0x4e68" : "=a" (usp));
29 return usp; 30 return usp;
30#endif 31#endif
31} 32}
32 33
33static inline void wrusp(unsigned long usp) 34static inline void wrusp(unsigned long usp)
34{ 35{
35#ifdef CONFIG_COLDFIRE 36#ifdef CONFIG_COLDFIRE_SW_A7
36 extern unsigned int sw_usp; 37 extern unsigned int sw_usp;
37 sw_usp = usp; 38 sw_usp = usp;
38#else 39#else
39 __asm__ __volatile__("move %0,%/usp" : : "a" (usp)); 40 register unsigned long a0 __asm__("a0") = usp;
41 /* move %a0,%usp */
42 __asm__ __volatile__(".word 0x4e60" : : "a" (a0) );
40#endif 43#endif
41} 44}
42 45
diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig
index fa9f746cf4ae..704e7b92334c 100644
--- a/arch/m68knommu/Kconfig
+++ b/arch/m68knommu/Kconfig
@@ -75,6 +75,16 @@ config GENERIC_CLOCKEVENTS
75config NO_IOPORT 75config NO_IOPORT
76 def_bool y 76 def_bool y
77 77
78config COLDFIRE_SW_A7
79 bool
80 default n
81
82config HAVE_CACHE_SPLIT
83 bool
84
85config HAVE_CACHE_CB
86 bool
87
78source "init/Kconfig" 88source "init/Kconfig"
79 89
80source "kernel/Kconfig.freezer" 90source "kernel/Kconfig.freezer"
@@ -107,69 +117,90 @@ config M68360
107 117
108config M5206 118config M5206
109 bool "MCF5206" 119 bool "MCF5206"
120 select COLDFIRE_SW_A7
110 help 121 help
111 Motorola ColdFire 5206 processor support. 122 Motorola ColdFire 5206 processor support.
112 123
113config M5206e 124config M5206e
114 bool "MCF5206e" 125 bool "MCF5206e"
126 select COLDFIRE_SW_A7
115 help 127 help
116 Motorola ColdFire 5206e processor support. 128 Motorola ColdFire 5206e processor support.
117 129
118config M520x 130config M520x
119 bool "MCF520x" 131 bool "MCF520x"
120 select GENERIC_CLOCKEVENTS 132 select GENERIC_CLOCKEVENTS
133 select HAVE_CACHE_SPLIT
121 help 134 help
122 Freescale Coldfire 5207/5208 processor support. 135 Freescale Coldfire 5207/5208 processor support.
123 136
124config M523x 137config M523x
125 bool "MCF523x" 138 bool "MCF523x"
126 select GENERIC_CLOCKEVENTS 139 select GENERIC_CLOCKEVENTS
140 select HAVE_CACHE_SPLIT
127 help 141 help
128 Freescale Coldfire 5230/1/2/4/5 processor support 142 Freescale Coldfire 5230/1/2/4/5 processor support
129 143
130config M5249 144config M5249
131 bool "MCF5249" 145 bool "MCF5249"
146 select COLDFIRE_SW_A7
132 help 147 help
133 Motorola ColdFire 5249 processor support. 148 Motorola ColdFire 5249 processor support.
134 149
135config M5271 150config M5271
136 bool "MCF5271" 151 bool "MCF5271"
152 select HAVE_CACHE_SPLIT
137 help 153 help
138 Freescale (Motorola) ColdFire 5270/5271 processor support. 154 Freescale (Motorola) ColdFire 5270/5271 processor support.
139 155
140config M5272 156config M5272
141 bool "MCF5272" 157 bool "MCF5272"
158 select COLDFIRE_SW_A7
142 help 159 help
143 Motorola ColdFire 5272 processor support. 160 Motorola ColdFire 5272 processor support.
144 161
145config M5275 162config M5275
146 bool "MCF5275" 163 bool "MCF5275"
164 select HAVE_CACHE_SPLIT
147 help 165 help
148 Freescale (Motorola) ColdFire 5274/5275 processor support. 166 Freescale (Motorola) ColdFire 5274/5275 processor support.
149 167
150config M528x 168config M528x
151 bool "MCF528x" 169 bool "MCF528x"
152 select GENERIC_CLOCKEVENTS 170 select GENERIC_CLOCKEVENTS
171 select HAVE_CACHE_SPLIT
153 help 172 help
154 Motorola ColdFire 5280/5282 processor support. 173 Motorola ColdFire 5280/5282 processor support.
155 174
156config M5307 175config M5307
157 bool "MCF5307" 176 bool "MCF5307"
177 select COLDFIRE_SW_A7
178 select HAVE_CACHE_CB
158 help 179 help
159 Motorola ColdFire 5307 processor support. 180 Motorola ColdFire 5307 processor support.
160 181
161config M532x 182config M532x
162 bool "MCF532x" 183 bool "MCF532x"
184 select HAVE_CACHE_CB
163 help 185 help
164 Freescale (Motorola) ColdFire 532x processor support. 186 Freescale (Motorola) ColdFire 532x processor support.
165 187
166config M5407 188config M5407
167 bool "MCF5407" 189 bool "MCF5407"
190 select COLDFIRE_SW_A7
191 select HAVE_CACHE_CB
168 help 192 help
169 Motorola ColdFire 5407 processor support. 193 Motorola ColdFire 5407 processor support.
170 194
195config M547x
196 bool "MCF547x"
197 select HAVE_CACHE_CB
198 help
199 Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support.
200
171config M548x 201config M548x
172 bool "MCF548x" 202 bool "MCF548x"
203 select HAVE_CACHE_CB
173 help 204 help
174 Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support. 205 Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
175 206
@@ -181,9 +212,14 @@ config M527x
181 select GENERIC_CLOCKEVENTS 212 select GENERIC_CLOCKEVENTS
182 default y 213 default y
183 214
215config M54xx
216 bool
217 depends on (M548x || M547x)
218 default y
219
184config COLDFIRE 220config COLDFIRE
185 bool 221 bool
186 depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407 || M548x) 222 depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407 || M54xx)
187 select GENERIC_GPIO 223 select GENERIC_GPIO
188 select ARCH_REQUIRE_GPIOLIB 224 select ARCH_REQUIRE_GPIOLIB
189 default y 225 default y
@@ -230,6 +266,46 @@ config OLDMASK
230 Build support for the older revision ColdFire 5307 silicon. 266 Build support for the older revision ColdFire 5307 silicon.
231 Specifically this is the 1H55J mask revision. 267 Specifically this is the 1H55J mask revision.
232 268
269if HAVE_CACHE_SPLIT
270choice
271 prompt "Split Cache Configuration"
272 default CACHE_I
273
274config CACHE_I
275 bool "Instruction"
276 help
277 Use all of the ColdFire CPU cache memory as an instruction cache.
278
279config CACHE_D
280 bool "Data"
281 help
282 Use all of the ColdFire CPU cache memory as a data cache.
283
284config CACHE_BOTH
285 bool "Both"
286 help
287 Split the ColdFire CPU cache, and use half as an instruction cache
288 and half as a data cache.
289endchoice
290endif
291
292if HAVE_CACHE_CB
293choice
294 prompt "Data cache mode"
295 default CACHE_WRITETHRU
296
297config CACHE_WRITETHRU
298 bool "Write-through"
299 help
300 The ColdFire CPU cache is set into Write-through mode.
301
302config CACHE_COPYBACK
303 bool "Copy-back"
304 help
305 The ColdFire CPU cache is set into Copy-back mode.
306endchoice
307endif
308
233comment "Platform" 309comment "Platform"
234 310
235config PILOT3 311config PILOT3
@@ -245,16 +321,16 @@ config XCOPILOT_BUGS
245 Support the bugs of Xcopilot. 321 Support the bugs of Xcopilot.
246 322
247config UC5272 323config UC5272
248 bool 'Arcturus Networks uC5272 dimm board support' 324 bool 'Arcturus Networks uC5272 dimm board support'
249 depends on M5272 325 depends on M5272
250 help 326 help
251 Support for the Arcturus Networks uC5272 dimm board. 327 Support for the Arcturus Networks uC5272 dimm board.
252 328
253config UC5282 329config UC5282
254 bool "Arcturus Networks uC5282 board support" 330 bool "Arcturus Networks uC5282 board support"
255 depends on M528x 331 depends on M528x
256 help 332 help
257 Support for the Arcturus Networks uC5282 dimm board. 333 Support for the Arcturus Networks uC5282 dimm board.
258 334
259config UCSIMM 335config UCSIMM
260 bool "uCsimm module support" 336 bool "uCsimm module support"
@@ -279,7 +355,7 @@ config DIRECT_IO_ACCESS
279 depends on (UCSIMM || UCDIMM || DRAGEN2) 355 depends on (UCSIMM || UCDIMM || DRAGEN2)
280 help 356 help
281 Disable the CPU internal registers protection in user mode, 357 Disable the CPU internal registers protection in user mode,
282 to allow a user application to read/write them. 358 to allow a user application to read/write them.
283 359
284config INIT_LCD 360config INIT_LCD
285 bool "Initialize LCD" 361 bool "Initialize LCD"
@@ -517,7 +593,7 @@ config EMAC_INC
517 depends on (SOM5282EM) 593 depends on (SOM5282EM)
518 594
519config SNEHA 595config SNEHA
520 bool 596 bool
521 default y 597 default y
522 depends on CPU16B 598 depends on CPU16B
523 599
diff --git a/arch/m68knommu/Makefile b/arch/m68knommu/Makefile
index 026ef16fa68e..589613fed31d 100644
--- a/arch/m68knommu/Makefile
+++ b/arch/m68knommu/Makefile
@@ -25,7 +25,7 @@ platform-$(CONFIG_M528x) := 528x
25platform-$(CONFIG_M5307) := 5307 25platform-$(CONFIG_M5307) := 5307
26platform-$(CONFIG_M532x) := 532x 26platform-$(CONFIG_M532x) := 532x
27platform-$(CONFIG_M5407) := 5407 27platform-$(CONFIG_M5407) := 5407
28platform-$(CONFIG_M548x) := 548x 28platform-$(CONFIG_M54xx) := 54xx
29PLATFORM := $(platform-y) 29PLATFORM := $(platform-y)
30 30
31board-$(CONFIG_PILOT) := pilot 31board-$(CONFIG_PILOT) := pilot
@@ -74,7 +74,7 @@ cpuclass-$(CONFIG_M528x) := coldfire
74cpuclass-$(CONFIG_M5307) := coldfire 74cpuclass-$(CONFIG_M5307) := coldfire
75cpuclass-$(CONFIG_M532x) := coldfire 75cpuclass-$(CONFIG_M532x) := coldfire
76cpuclass-$(CONFIG_M5407) := coldfire 76cpuclass-$(CONFIG_M5407) := coldfire
77cpuclass-$(CONFIG_M548x) := coldfire 77cpuclass-$(CONFIG_M54xx) := coldfire
78cpuclass-$(CONFIG_M68328) := 68328 78cpuclass-$(CONFIG_M68328) := 68328
79cpuclass-$(CONFIG_M68EZ328) := 68328 79cpuclass-$(CONFIG_M68EZ328) := 68328
80cpuclass-$(CONFIG_M68VZ328) := 68328 80cpuclass-$(CONFIG_M68VZ328) := 68328
@@ -91,18 +91,18 @@ export PLATFORM BOARD MODEL CPUCLASS
91# Some CFLAG additions based on specific CPU type. 91# Some CFLAG additions based on specific CPU type.
92# 92#
93cflags-$(CONFIG_M5206) := $(call cc-option,-mcpu=5206,-m5200) 93cflags-$(CONFIG_M5206) := $(call cc-option,-mcpu=5206,-m5200)
94cflags-$(CONFIG_M5206e) := $(call cc-option,-m5206e,-m5200) 94cflags-$(CONFIG_M5206e) := $(call cc-option,-mcpu=5206e,-m5200)
95cflags-$(CONFIG_M520x) := $(call cc-option,-mcpu=5208,-m5200) 95cflags-$(CONFIG_M520x) := $(call cc-option,-mcpu=5208,-m5200)
96cflags-$(CONFIG_M523x) := $(call cc-option,-mcpu=523x,-m5307) 96cflags-$(CONFIG_M523x) := $(call cc-option,-mcpu=523x,-m5307)
97cflags-$(CONFIG_M5249) := $(call cc-option,-mcpu=5249,-m5200) 97cflags-$(CONFIG_M5249) := $(call cc-option,-mcpu=5249,-m5200)
98cflags-$(CONFIG_M5271) := $(call cc-option,-mcpu=5271,-m5307) 98cflags-$(CONFIG_M5271) := $(call cc-option,-mcpu=5271,-m5307)
99cflags-$(CONFIG_M5272) := $(call cc-option,-mcpu=5272,-m5307) 99cflags-$(CONFIG_M5272) := $(call cc-option,-mcpu=5272,-m5307)
100cflags-$(CONFIG_M5275) := $(call cc-option,-mcpu=5275,-m5307) 100cflags-$(CONFIG_M5275) := $(call cc-option,-mcpu=5275,-m5307)
101cflags-$(CONFIG_M528x) := $(call cc-option,-m528x,-m5307) 101cflags-$(CONFIG_M528x) := $(call cc-option,-mcpu=528x,-m5307)
102cflags-$(CONFIG_M5307) := $(call cc-option,-m5307,-m5200) 102cflags-$(CONFIG_M5307) := $(call cc-option,-mcpu=5307,-m5200)
103cflags-$(CONFIG_M532x) := $(call cc-option,-mcpu=532x,-m5307) 103cflags-$(CONFIG_M532x) := $(call cc-option,-mcpu=532x,-m5307)
104cflags-$(CONFIG_M5407) := $(call cc-option,-m5407,-m5200) 104cflags-$(CONFIG_M5407) := $(call cc-option,-mcpu=5407,-m5200)
105cflags-$(CONFIG_M548x) := $(call cc-option,-m5407,-m5200) 105cflags-$(CONFIG_M54xx) := $(call cc-option,-mcpu=5475,-m5200)
106cflags-$(CONFIG_M68328) := -m68000 106cflags-$(CONFIG_M68328) := -m68000
107cflags-$(CONFIG_M68EZ328) := -m68000 107cflags-$(CONFIG_M68EZ328) := -m68000
108cflags-$(CONFIG_M68VZ328) := -m68000 108cflags-$(CONFIG_M68VZ328) := -m68000
diff --git a/arch/m68knommu/kernel/setup.c b/arch/m68knommu/kernel/setup.c
index c684adf5dc40..16b2de7f5101 100644
--- a/arch/m68knommu/kernel/setup.c
+++ b/arch/m68knommu/kernel/setup.c
@@ -55,55 +55,29 @@ void (*mach_halt)(void);
55void (*mach_power_off)(void); 55void (*mach_power_off)(void);
56 56
57#ifdef CONFIG_M68328 57#ifdef CONFIG_M68328
58 #define CPU "MC68328" 58#define CPU_NAME "MC68328"
59#endif 59#endif
60#ifdef CONFIG_M68EZ328 60#ifdef CONFIG_M68EZ328
61 #define CPU "MC68EZ328" 61#define CPU_NAME "MC68EZ328"
62#endif 62#endif
63#ifdef CONFIG_M68VZ328 63#ifdef CONFIG_M68VZ328
64 #define CPU "MC68VZ328" 64#define CPU_NAME "MC68VZ328"
65#endif 65#endif
66#ifdef CONFIG_M68360 66#ifdef CONFIG_M68360
67 #define CPU "MC68360" 67#define CPU_NAME "MC68360"
68#endif 68#endif
69#if defined(CONFIG_M5206) 69#ifndef CPU_NAME
70 #define CPU "COLDFIRE(m5206)" 70#define CPU_NAME "UNKNOWN"
71#endif 71#endif
72#if defined(CONFIG_M5206e) 72
73 #define CPU "COLDFIRE(m5206e)" 73/*
74#endif 74 * Different cores have different instruction execution timings.
75#if defined(CONFIG_M520x) 75 * The old/traditional 68000 cores are basically all the same, at 16.
76 #define CPU "COLDFIRE(m520x)" 76 * The ColdFire cores vary a little, their values are defined in their
77#endif 77 * headers. We default to the standard 68000 value here.
78#if defined(CONFIG_M523x) 78 */
79 #define CPU "COLDFIRE(m523x)" 79#ifndef CPU_INSTR_PER_JIFFY
80#endif 80#define CPU_INSTR_PER_JIFFY 16
81#if defined(CONFIG_M5249)
82 #define CPU "COLDFIRE(m5249)"
83#endif
84#if defined(CONFIG_M5271)
85 #define CPU "COLDFIRE(m5270/5271)"
86#endif
87#if defined(CONFIG_M5272)
88 #define CPU "COLDFIRE(m5272)"
89#endif
90#if defined(CONFIG_M5275)
91 #define CPU "COLDFIRE(m5274/5275)"
92#endif
93#if defined(CONFIG_M528x)
94 #define CPU "COLDFIRE(m5280/5282)"
95#endif
96#if defined(CONFIG_M5307)
97 #define CPU "COLDFIRE(m5307)"
98#endif
99#if defined(CONFIG_M532x)
100 #define CPU "COLDFIRE(m532x)"
101#endif
102#if defined(CONFIG_M5407)
103 #define CPU "COLDFIRE(m5407)"
104#endif
105#ifndef CPU
106 #define CPU "UNKNOWN"
107#endif 81#endif
108 82
109extern int _stext, _etext, _sdata, _edata, _sbss, _ebss, _end; 83extern int _stext, _etext, _sdata, _edata, _sbss, _ebss, _end;
@@ -208,7 +182,7 @@ void __init setup_arch(char **cmdline_p)
208 command_line[sizeof(command_line) - 1] = 0; 182 command_line[sizeof(command_line) - 1] = 0;
209#endif /* CONFIG_UBOOT */ 183#endif /* CONFIG_UBOOT */
210 184
211 printk(KERN_INFO "\x0F\r\n\nuClinux/" CPU "\n"); 185 printk(KERN_INFO "\x0F\r\n\nuClinux/" CPU_NAME "\n");
212 186
213#ifdef CONFIG_UCDIMM 187#ifdef CONFIG_UCDIMM
214 printk(KERN_INFO "uCdimm by Lineo, Inc. <www.lineo.com>\n"); 188 printk(KERN_INFO "uCdimm by Lineo, Inc. <www.lineo.com>\n");
@@ -257,11 +231,6 @@ void __init setup_arch(char **cmdline_p)
257 memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); 231 memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
258 boot_command_line[COMMAND_LINE_SIZE-1] = 0; 232 boot_command_line[COMMAND_LINE_SIZE-1] = 0;
259 233
260#ifdef DEBUG
261 if (strlen(*cmdline_p))
262 printk(KERN_DEBUG "Command line: '%s'\n", *cmdline_p);
263#endif
264
265#if defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_DUMMY_CONSOLE) 234#if defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_DUMMY_CONSOLE)
266 conswitchp = &dummy_con; 235 conswitchp = &dummy_con;
267#endif 236#endif
@@ -303,15 +272,10 @@ static int show_cpuinfo(struct seq_file *m, void *v)
303 char *cpu, *mmu, *fpu; 272 char *cpu, *mmu, *fpu;
304 u_long clockfreq; 273 u_long clockfreq;
305 274
306 cpu = CPU; 275 cpu = CPU_NAME;
307 mmu = "none"; 276 mmu = "none";
308 fpu = "none"; 277 fpu = "none";
309 278 clockfreq = (loops_per_jiffy * HZ) * CPU_INSTR_PER_JIFFY;
310#ifdef CONFIG_COLDFIRE
311 clockfreq = (loops_per_jiffy * HZ) * 3;
312#else
313 clockfreq = (loops_per_jiffy * HZ) * 16;
314#endif
315 279
316 seq_printf(m, "CPU:\t\t%s\n" 280 seq_printf(m, "CPU:\t\t%s\n"
317 "MMU:\t\t%s\n" 281 "MMU:\t\t%s\n"
diff --git a/arch/m68knommu/mm/Makefile b/arch/m68knommu/mm/Makefile
index fc91f254f51b..b54ab6b4b523 100644
--- a/arch/m68knommu/mm/Makefile
+++ b/arch/m68knommu/mm/Makefile
@@ -2,4 +2,4 @@
2# Makefile for the linux m68knommu specific parts of the memory manager. 2# Makefile for the linux m68knommu specific parts of the memory manager.
3# 3#
4 4
5obj-y += init.o fault.o memory.o kmap.o 5obj-y += init.o kmap.o
diff --git a/arch/m68knommu/mm/fault.c b/arch/m68knommu/mm/fault.c
deleted file mode 100644
index bc05cf74d9c0..000000000000
--- a/arch/m68knommu/mm/fault.c
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * linux/arch/m68knommu/mm/fault.c
3 *
4 * Copyright (C) 1998 D. Jeff Dionne <jeff@lineo.ca>,
5 * Copyright (C) 2000 Lineo, Inc. (www.lineo.com)
6 *
7 * Based on:
8 *
9 * linux/arch/m68k/mm/fault.c
10 *
11 * Copyright (C) 1995 Hamish Macdonald
12 */
13
14#include <linux/mman.h>
15#include <linux/mm.h>
16#include <linux/kernel.h>
17#include <linux/ptrace.h>
18
19#include <asm/system.h>
20#include <asm/pgtable.h>
21
22extern void die_if_kernel(char *, struct pt_regs *, long);
23
24/*
25 * This routine handles page faults. It determines the problem, and
26 * then passes it off to one of the appropriate routines.
27 *
28 * error_code:
29 * bit 0 == 0 means no page found, 1 means protection fault
30 * bit 1 == 0 means read, 1 means write
31 *
32 * If this routine detects a bad access, it returns 1, otherwise it
33 * returns 0.
34 */
35asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address,
36 unsigned long error_code)
37{
38#ifdef DEBUG
39 printk(KERN_DEBUG "regs->sr=%#x, regs->pc=%#lx, address=%#lx, %ld\n",
40 regs->sr, regs->pc, address, error_code);
41#endif
42
43 /*
44 * Oops. The kernel tried to access some bad page. We'll have to
45 * terminate things with extreme prejudice.
46 */
47 if ((unsigned long) address < PAGE_SIZE)
48 printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference");
49 else
50 printk(KERN_ALERT "Unable to handle kernel access");
51 printk(KERN_ALERT " at virtual address %08lx\n", address);
52 die_if_kernel("Oops", regs, error_code);
53 do_exit(SIGKILL);
54
55 return 1;
56}
57
diff --git a/arch/m68knommu/mm/kmap.c b/arch/m68knommu/mm/kmap.c
index 902c1dfda9e5..ece8d5ad4e6c 100644
--- a/arch/m68knommu/mm/kmap.c
+++ b/arch/m68knommu/mm/kmap.c
@@ -36,15 +36,6 @@ void iounmap(void *addr)
36} 36}
37 37
38/* 38/*
39 * __iounmap unmaps nearly everything, so be careful
40 * it doesn't free currently pointer/page tables anymore but it
41 * wans't used anyway and might be added later.
42 */
43void __iounmap(void *addr, unsigned long size)
44{
45}
46
47/*
48 * Set new cache mode for some kernel address space. 39 * Set new cache mode for some kernel address space.
49 * The caller must push data for that range itself, if such data may already 40 * The caller must push data for that range itself, if such data may already
50 * be in the cache. 41 * be in the cache.
diff --git a/arch/m68knommu/mm/memory.c b/arch/m68knommu/mm/memory.c
deleted file mode 100644
index 8f7949e786d4..000000000000
--- a/arch/m68knommu/mm/memory.c
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * linux/arch/m68knommu/mm/memory.c
3 *
4 * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
5 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
6 *
7 * Based on:
8 *
9 * linux/arch/m68k/mm/memory.c
10 *
11 * Copyright (C) 1995 Hamish Macdonald
12 */
13
14#include <linux/mm.h>
15#include <linux/kernel.h>
16#include <linux/string.h>
17#include <linux/types.h>
18
19#include <asm/segment.h>
20#include <asm/page.h>
21#include <asm/pgtable.h>
22#include <asm/system.h>
23
24/*
25 * Map some physical address range into the kernel address space.
26 */
27
28unsigned long kernel_map(unsigned long paddr, unsigned long size,
29 int nocacheflag, unsigned long *memavailp )
30{
31 return paddr;
32}
33
diff --git a/arch/m68knommu/platform/548x/Makefile b/arch/m68knommu/platform/54xx/Makefile
index e6035e7a2d3f..e6035e7a2d3f 100644
--- a/arch/m68knommu/platform/548x/Makefile
+++ b/arch/m68knommu/platform/54xx/Makefile
diff --git a/arch/m68knommu/platform/548x/config.c b/arch/m68knommu/platform/54xx/config.c
index 9888846bd1cf..78130984db95 100644
--- a/arch/m68knommu/platform/548x/config.c
+++ b/arch/m68knommu/platform/54xx/config.c
@@ -1,7 +1,7 @@
1/***************************************************************************/ 1/***************************************************************************/
2 2
3/* 3/*
4 * linux/arch/m68knommu/platform/548x/config.c 4 * linux/arch/m68knommu/platform/54xx/config.c
5 * 5 *
6 * Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be> 6 * Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be>
7 */ 7 */
@@ -15,13 +15,13 @@
15#include <linux/io.h> 15#include <linux/io.h>
16#include <asm/machdep.h> 16#include <asm/machdep.h>
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/m548xsim.h> 18#include <asm/m54xxsim.h>
19#include <asm/mcfuart.h> 19#include <asm/mcfuart.h>
20#include <asm/m548xgpt.h> 20#include <asm/m54xxgpt.h>
21 21
22/***************************************************************************/ 22/***************************************************************************/
23 23
24static struct mcf_platform_uart m548x_uart_platform[] = { 24static struct mcf_platform_uart m54xx_uart_platform[] = {
25 { 25 {
26 .mapbase = MCF_MBAR + MCFUART_BASE1, 26 .mapbase = MCF_MBAR + MCFUART_BASE1,
27 .irq = 64 + 35, 27 .irq = 64 + 35,
@@ -40,20 +40,20 @@ static struct mcf_platform_uart m548x_uart_platform[] = {
40 }, 40 },
41}; 41};
42 42
43static struct platform_device m548x_uart = { 43static struct platform_device m54xx_uart = {
44 .name = "mcfuart", 44 .name = "mcfuart",
45 .id = 0, 45 .id = 0,
46 .dev.platform_data = m548x_uart_platform, 46 .dev.platform_data = m54xx_uart_platform,
47}; 47};
48 48
49static struct platform_device *m548x_devices[] __initdata = { 49static struct platform_device *m54xx_devices[] __initdata = {
50 &m548x_uart, 50 &m54xx_uart,
51}; 51};
52 52
53 53
54/***************************************************************************/ 54/***************************************************************************/
55 55
56static void __init m548x_uart_init_line(int line, int irq) 56static void __init m54xx_uart_init_line(int line, int irq)
57{ 57{
58 int rts_cts; 58 int rts_cts;
59 59
@@ -72,18 +72,18 @@ static void __init m548x_uart_init_line(int line, int irq)
72 MCF_MBAR + MCF_PAR_PSC(line)); 72 MCF_MBAR + MCF_PAR_PSC(line));
73} 73}
74 74
75static void __init m548x_uarts_init(void) 75static void __init m54xx_uarts_init(void)
76{ 76{
77 const int nrlines = ARRAY_SIZE(m548x_uart_platform); 77 const int nrlines = ARRAY_SIZE(m54xx_uart_platform);
78 int line; 78 int line;
79 79
80 for (line = 0; (line < nrlines); line++) 80 for (line = 0; (line < nrlines); line++)
81 m548x_uart_init_line(line, m548x_uart_platform[line].irq); 81 m54xx_uart_init_line(line, m54xx_uart_platform[line].irq);
82} 82}
83 83
84/***************************************************************************/ 84/***************************************************************************/
85 85
86static void mcf548x_reset(void) 86static void mcf54xx_reset(void)
87{ 87{
88 /* disable interrupts and enable the watchdog */ 88 /* disable interrupts and enable the watchdog */
89 asm("movew #0x2700, %sr\n"); 89 asm("movew #0x2700, %sr\n");
@@ -97,8 +97,8 @@ static void mcf548x_reset(void)
97 97
98void __init config_BSP(char *commandp, int size) 98void __init config_BSP(char *commandp, int size)
99{ 99{
100 mach_reset = mcf548x_reset; 100 mach_reset = mcf54xx_reset;
101 m548x_uarts_init(); 101 m54xx_uarts_init();
102} 102}
103 103
104/***************************************************************************/ 104/***************************************************************************/
@@ -106,7 +106,7 @@ void __init config_BSP(char *commandp, int size)
106static int __init init_BSP(void) 106static int __init init_BSP(void)
107{ 107{
108 108
109 platform_add_devices(m548x_devices, ARRAY_SIZE(m548x_devices)); 109 platform_add_devices(m54xx_devices, ARRAY_SIZE(m54xx_devices));
110 return 0; 110 return 0;
111} 111}
112 112
diff --git a/arch/m68knommu/platform/68328/ints.c b/arch/m68knommu/platform/68328/ints.c
index 865852806a17..2a3af193ccd3 100644
--- a/arch/m68knommu/platform/68328/ints.c
+++ b/arch/m68knommu/platform/68328/ints.c
@@ -179,8 +179,8 @@ void __init init_IRQ(void)
179 IMR = ~0; 179 IMR = ~0;
180 180
181 for (i = 0; (i < NR_IRQS); i++) { 181 for (i = 0; (i < NR_IRQS); i++) {
182 set_irq_chip(irq, &intc_irq_chip); 182 set_irq_chip(i, &intc_irq_chip);
183 set_irq_handler(irq, handle_level_irq); 183 set_irq_handler(i, handle_level_irq);
184 } 184 }
185} 185}
186 186
diff --git a/arch/m68knommu/platform/coldfire/Makefile b/arch/m68knommu/platform/coldfire/Makefile
index 45f501fa4525..a8967baabd72 100644
--- a/arch/m68knommu/platform/coldfire/Makefile
+++ b/arch/m68knommu/platform/coldfire/Makefile
@@ -14,7 +14,7 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-$(CONFIG_COLDFIRE) += clk.o dma.o entry.o vectors.o 17obj-$(CONFIG_COLDFIRE) += cache.o clk.o dma.o entry.o vectors.o
18obj-$(CONFIG_M5206) += timers.o intc.o 18obj-$(CONFIG_M5206) += timers.o intc.o
19obj-$(CONFIG_M5206e) += timers.o intc.o 19obj-$(CONFIG_M5206e) += timers.o intc.o
20obj-$(CONFIG_M520x) += pit.o intc-simr.o 20obj-$(CONFIG_M520x) += pit.o intc-simr.o
@@ -26,7 +26,7 @@ obj-$(CONFIG_M528x) += pit.o intc-2.o
26obj-$(CONFIG_M5307) += timers.o intc.o 26obj-$(CONFIG_M5307) += timers.o intc.o
27obj-$(CONFIG_M532x) += timers.o intc-simr.o 27obj-$(CONFIG_M532x) += timers.o intc-simr.o
28obj-$(CONFIG_M5407) += timers.o intc.o 28obj-$(CONFIG_M5407) += timers.o intc.o
29obj-$(CONFIG_M548x) += sltimers.o intc-2.o 29obj-$(CONFIG_M54xx) += sltimers.o intc-2.o
30 30
31obj-y += pinmux.o gpio.o 31obj-y += pinmux.o gpio.o
32extra-y := head.o 32extra-y := head.o
diff --git a/arch/m68knommu/platform/coldfire/cache.c b/arch/m68knommu/platform/coldfire/cache.c
new file mode 100644
index 000000000000..235d3c4f4f0f
--- /dev/null
+++ b/arch/m68knommu/platform/coldfire/cache.c
@@ -0,0 +1,48 @@
1/***************************************************************************/
2
3/*
4 * cache.c -- general ColdFire Cache maintainence code
5 *
6 * Copyright (C) 2010, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/***************************************************************************/
10
11#include <linux/kernel.h>
12#include <asm/coldfire.h>
13#include <asm/mcfsim.h>
14
15/***************************************************************************/
16#ifdef CACHE_PUSH
17/***************************************************************************/
18
19/*
20 * Use cpushl to push all dirty cache lines back to memory.
21 * Older versions of GAS don't seem to know how to generate the
22 * ColdFire cpushl instruction... Oh well, bit stuff it for now.
23 */
24
25void mcf_cache_push(void)
26{
27 __asm__ __volatile__ (
28 "clrl %%d0\n\t"
29 "1:\n\t"
30 "movel %%d0,%%a0\n\t"
31 "2:\n\t"
32 ".word 0xf468\n\t"
33 "addl %0,%%a0\n\t"
34 "cmpl %1,%%a0\n\t"
35 "blt 2b\n\t"
36 "addql #1,%%d0\n\t"
37 "cmpil %2,%%d0\n\t"
38 "bne 1b\n\t"
39 : /* No output */
40 : "i" (CACHE_LINE_SIZE),
41 "i" (DCACHE_SIZE / CACHE_WAYS),
42 "i" (CACHE_WAYS)
43 : "d0", "a0" );
44}
45
46/***************************************************************************/
47#endif /* CACHE_PUSH */
48/***************************************************************************/
diff --git a/arch/m68knommu/platform/coldfire/entry.S b/arch/m68knommu/platform/coldfire/entry.S
index e1debc8285ef..4ddfc3da70d8 100644
--- a/arch/m68knommu/platform/coldfire/entry.S
+++ b/arch/m68knommu/platform/coldfire/entry.S
@@ -36,13 +36,16 @@
36#include <asm/asm-offsets.h> 36#include <asm/asm-offsets.h>
37#include <asm/entry.h> 37#include <asm/entry.h>
38 38
39#ifdef CONFIG_COLDFIRE_SW_A7
40/*
41 * Define software copies of the supervisor and user stack pointers.
42 */
39.bss 43.bss
40
41sw_ksp: 44sw_ksp:
42.long 0 45.long 0
43
44sw_usp: 46sw_usp:
45.long 0 47.long 0
48#endif /* CONFIG_COLDFIRE_SW_A7 */
46 49
47.text 50.text
48 51
@@ -51,7 +54,6 @@ sw_usp:
51.globl ret_from_exception 54.globl ret_from_exception
52.globl ret_from_signal 55.globl ret_from_signal
53.globl sys_call_table 56.globl sys_call_table
54.globl ret_from_interrupt
55.globl inthandler 57.globl inthandler
56.globl fasthandler 58.globl fasthandler
57 59
@@ -140,20 +142,7 @@ Luser_return:
140 jne Lwork_to_do /* still work to do */ 142 jne Lwork_to_do /* still work to do */
141 143
142Lreturn: 144Lreturn:
143 move #0x2700,%sr /* disable intrs */ 145 RESTORE_USER
144 movel sw_usp,%a0 /* get usp */
145 movel %sp@(PT_OFF_PC),%a0@- /* copy exception program counter */
146 movel %sp@(PT_OFF_FORMATVEC),%a0@- /* copy exception format/vector/sr */
147 moveml %sp@,%d1-%d5/%a0-%a2
148 lea %sp@(32),%sp /* space for 8 regs */
149 movel %sp@+,%d0
150 addql #4,%sp /* orig d0 */
151 addl %sp@+,%sp /* stk adj */
152 addql #8,%sp /* remove exception */
153 movel %sp,sw_ksp /* save ksp */
154 subql #8,sw_usp /* set exception */
155 movel sw_usp,%sp /* restore usp */
156 rte
157 146
158Lwork_to_do: 147Lwork_to_do:
159 movel %a0@(TI_FLAGS),%d1 /* get thread_info->flags */ 148 movel %a0@(TI_FLAGS),%d1 /* get thread_info->flags */
@@ -191,31 +180,7 @@ ENTRY(inthandler)
191 jbsr do_IRQ /* call high level irq handler */ 180 jbsr do_IRQ /* call high level irq handler */
192 lea %sp@(8),%sp /* pop args off stack */ 181 lea %sp@(8),%sp /* pop args off stack */
193 182
194 bra ret_from_interrupt /* this was fallthrough */ 183 bra ret_from_exception
195
196/*
197 * This is the fast interrupt handler (for certain hardware interrupt
198 * sources). Unlike the normal interrupt handler it just uses the
199 * current stack (doesn't care if it is user or kernel). It also
200 * doesn't bother doing the bottom half handlers.
201 */
202ENTRY(fasthandler)
203 SAVE_LOCAL
204
205 movew %sp@(PT_OFF_FORMATVEC),%d0
206 andl #0x03fc,%d0 /* mask out vector only */
207
208 movel %sp,%sp@- /* push regs arg */
209 lsrl #2,%d0 /* calculate real vector # */
210 movel %d0,%sp@- /* push vector number */
211 jbsr do_IRQ /* call high level irq handler */
212 lea %sp@(8),%sp /* pop args off stack */
213
214 RESTORE_LOCAL
215
216ENTRY(ret_from_interrupt)
217 /* the fasthandler is confusing me, haven't seen any user */
218 jmp ret_from_exception
219 184
220/* 185/*
221 * Beware - when entering resume, prev (the current task) is 186 * Beware - when entering resume, prev (the current task) is
@@ -226,9 +191,8 @@ ENTRY(ret_from_interrupt)
226 */ 191 */
227ENTRY(resume) 192ENTRY(resume)
228 movel %a0, %d1 /* get prev thread in d1 */ 193 movel %a0, %d1 /* get prev thread in d1 */
229 194 RDUSP
230 movel sw_usp,%d0 /* save usp */ 195 movel %a2,%a0@(TASK_THREAD+THREAD_USP)
231 movel %d0,%a0@(TASK_THREAD+THREAD_USP)
232 196
233 SAVE_SWITCH_STACK 197 SAVE_SWITCH_STACK
234 movel %sp,%a0@(TASK_THREAD+THREAD_KSP) /* save kernel stack pointer */ 198 movel %sp,%a0@(TASK_THREAD+THREAD_KSP) /* save kernel stack pointer */
@@ -236,5 +200,5 @@ ENTRY(resume)
236 RESTORE_SWITCH_STACK 200 RESTORE_SWITCH_STACK
237 201
238 movel %a1@(TASK_THREAD+THREAD_USP),%a0 /* restore thread user stack */ 202 movel %a1@(TASK_THREAD+THREAD_USP),%a0 /* restore thread user stack */
239 movel %a0, sw_usp 203 WRUSP
240 rts 204 rts
diff --git a/arch/m68knommu/platform/coldfire/head.S b/arch/m68knommu/platform/coldfire/head.S
index 0b2d7c7adf79..d5977909ae5f 100644
--- a/arch/m68knommu/platform/coldfire/head.S
+++ b/arch/m68knommu/platform/coldfire/head.S
@@ -3,7 +3,7 @@
3/* 3/*
4 * head.S -- common startup code for ColdFire CPUs. 4 * head.S -- common startup code for ColdFire CPUs.
5 * 5 *
6 * (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com>. 6 * (C) Copyright 1999-2010, Greg Ungerer <gerg@snapgear.com>.
7 */ 7 */
8 8
9/*****************************************************************************/ 9/*****************************************************************************/
@@ -13,7 +13,6 @@
13#include <linux/init.h> 13#include <linux/init.h>
14#include <asm/asm-offsets.h> 14#include <asm/asm-offsets.h>
15#include <asm/coldfire.h> 15#include <asm/coldfire.h>
16#include <asm/mcfcache.h>
17#include <asm/mcfsim.h> 16#include <asm/mcfsim.h>
18#include <asm/thread_info.h> 17#include <asm/thread_info.h>
19 18
@@ -173,10 +172,27 @@ _start:
173 172
174 /* 173 /*
175 * Now that we know what the memory is, lets enable cache 174 * Now that we know what the memory is, lets enable cache
176 * and get things moving. This is Coldfire CPU specific. 175 * and get things moving. This is Coldfire CPU specific. Not
176 * all version cores have identical cache register setup. But
177 * it is very similar. Define the exact settings in the headers
178 * then the code here is the same for all.
177 */ 179 */
178 CACHE_ENABLE /* enable CPU cache */ 180 movel #CACHE_INIT,%d0 /* invalidate whole cache */
179 181 movec %d0,%CACR
182 nop
183 movel #ACR0_MODE,%d0 /* set RAM region for caching */
184 movec %d0,%ACR0
185 movel #ACR1_MODE,%d0 /* anything else to cache? */
186 movec %d0,%ACR1
187#ifdef ACR2_MODE
188 movel #ACR2_MODE,%d0
189 movec %d0,%ACR2
190 movel #ACR3_MODE,%d0
191 movec %d0,%ACR3
192#endif
193 movel #CACHE_MODE,%d0 /* enable cache */
194 movec %d0,%CACR
195 nop
180 196
181#ifdef CONFIG_ROMFS_FS 197#ifdef CONFIG_ROMFS_FS
182 /* 198 /*
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 08:02:26 -0500