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-rw-r--r--arch/blackfin/Kconfig75
-rw-r--r--arch/blackfin/Kconfig.debug55
-rw-r--r--arch/blackfin/Makefile1
-rw-r--r--arch/blackfin/configs/BF526-EZBRD_defconfig1427
-rw-r--r--arch/blackfin/configs/H8606_defconfig36
-rw-r--r--arch/blackfin/include/asm/bfin-global.h5
-rw-r--r--arch/blackfin/include/asm/bfrom.h85
-rw-r--r--arch/blackfin/include/asm/cacheflush.h2
-rw-r--r--arch/blackfin/include/asm/cplb.h8
-rw-r--r--arch/blackfin/include/asm/cplbinit.h16
-rw-r--r--arch/blackfin/include/asm/cpumask.h6
-rw-r--r--arch/blackfin/include/asm/dma-mapping.h11
-rw-r--r--arch/blackfin/include/asm/kgdb.h21
-rw-r--r--arch/blackfin/include/asm/mmu_context.h79
-rw-r--r--arch/blackfin/include/asm/processor.h6
-rw-r--r--arch/blackfin/include/asm/ptrace.h2
-rw-r--r--arch/blackfin/include/asm/traps.h5
-rw-r--r--arch/blackfin/kernel/asm-offsets.c1
-rw-r--r--arch/blackfin/kernel/bfin_gpio.c9
-rw-r--r--arch/blackfin/kernel/cplb-mpu/cplbinit.c12
-rw-r--r--arch/blackfin/kernel/cplb-mpu/cplbmgr.c14
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbinit.c6
-rw-r--r--arch/blackfin/kernel/early_printk.c12
-rw-r--r--arch/blackfin/kernel/kgdb.c711
-rw-r--r--arch/blackfin/kernel/ptrace.c215
-rw-r--r--arch/blackfin/kernel/reboot.c18
-rw-r--r--arch/blackfin/kernel/setup.c97
-rw-r--r--arch/blackfin/kernel/traps.c367
-rw-r--r--arch/blackfin/mach-bf527/boards/Kconfig5
-rw-r--r--arch/blackfin/mach-bf527/boards/Makefile1
-rw-r--r--arch/blackfin/mach-bf527/boards/cm_bf527.c17
-rw-r--r--arch/blackfin/mach-bf527/boards/ezbrd.c734
-rw-r--r--arch/blackfin/mach-bf527/boards/ezkit.c53
-rw-r--r--arch/blackfin/mach-bf527/head.S3
-rw-r--r--arch/blackfin/mach-bf527/include/mach/anomaly.h160
-rw-r--r--arch/blackfin/mach-bf527/include/mach/bf527.h21
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF52x_base.h27
-rw-r--r--arch/blackfin/mach-bf527/include/mach/portmux.h4
-rw-r--r--arch/blackfin/mach-bf533/boards/H8606.c34
-rw-r--r--arch/blackfin/mach-bf533/head.S3
-rw-r--r--arch/blackfin/mach-bf533/include/mach/anomaly.h49
-rw-r--r--arch/blackfin/mach-bf533/include/mach/bf533.h12
-rw-r--r--arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h2
-rw-r--r--arch/blackfin/mach-bf537/boards/stamp.c85
-rw-r--r--arch/blackfin/mach-bf537/head.S3
-rw-r--r--arch/blackfin/mach-bf537/include/mach/anomaly.h2
-rw-r--r--arch/blackfin/mach-bf537/include/mach/bf537.h12
-rw-r--r--arch/blackfin/mach-bf548/boards/cm_bf548.c22
-rw-r--r--arch/blackfin/mach-bf548/boards/ezkit.c58
-rw-r--r--arch/blackfin/mach-bf548/head.S52
-rw-r--r--arch/blackfin/mach-bf548/include/mach/anomaly.h93
-rw-r--r--arch/blackfin/mach-bf548/include/mach/bf548.h25
-rw-r--r--arch/blackfin/mach-bf548/include/mach/mem_map.h14
-rw-r--r--arch/blackfin/mach-bf561/head.S3
-rw-r--r--arch/blackfin/mach-bf561/include/mach/anomaly.h2
-rw-r--r--arch/blackfin/mach-bf561/include/mach/bf561.h8
-rw-r--r--arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h2
-rw-r--r--arch/blackfin/mach-bf561/include/mach/mem_map.h18
-rw-r--r--arch/blackfin/mach-common/entry.S219
-rw-r--r--arch/blackfin/mach-common/head.S52
-rw-r--r--arch/blackfin/mach-common/interrupt.S11
-rw-r--r--arch/blackfin/mach-common/ints-priority.c25
-rw-r--r--arch/blackfin/mm/Makefile2
-rw-r--r--arch/blackfin/mm/isram-driver.c201
-rw-r--r--arch/blackfin/mm/sram-alloc.c (renamed from arch/blackfin/mm/blackfin_sram.c)31
65 files changed, 4503 insertions, 864 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 4154ff1101fa..8102c79aaa94 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -162,16 +162,28 @@ config BF549
162config BF561 162config BF561
163 bool "BF561" 163 bool "BF561"
164 help 164 help
165 Not Supported Yet - Work in progress - BF561 Processor Support. 165 BF561 Processor Support.
166 166
167endchoice 167endchoice
168 168
169config BF_REV_MIN
170 int
171 default 0 if (BF52x || BF54x)
172 default 2 if (BF537 || BF536 || BF534)
173 default 3 if (BF561 ||BF533 || BF532 || BF531)
174
175config BF_REV_MAX
176 int
177 default 2 if (BF52x || BF54x)
178 default 3 if (BF537 || BF536 || BF534)
179 default 5 if (BF561)
180 default 6 if (BF533 || BF532 || BF531)
181
169choice 182choice
170 prompt "Silicon Rev" 183 prompt "Silicon Rev"
171 default BF_REV_0_1 if BF527 184 default BF_REV_0_1 if (BF52x || BF54x)
172 default BF_REV_0_2 if BF537 185 default BF_REV_0_2 if (BF534 || BF536 || BF537)
173 default BF_REV_0_3 if BF533 186 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
174 default BF_REV_0_0 if BF549
175 187
176config BF_REV_0_0 188config BF_REV_0_0
177 bool "0.0" 189 bool "0.0"
@@ -183,7 +195,7 @@ config BF_REV_0_1
183 195
184config BF_REV_0_2 196config BF_REV_0_2
185 bool "0.2" 197 bool "0.2"
186 depends on (BF537 || BF536 || BF534) 198 depends on (BF52x || BF537 || BF536 || BF534 || BF54x)
187 199
188config BF_REV_0_3 200config BF_REV_0_3
189 bool "0.3" 201 bool "0.3"
@@ -197,6 +209,10 @@ config BF_REV_0_5
197 bool "0.5" 209 bool "0.5"
198 depends on (BF561 || BF533 || BF532 || BF531) 210 depends on (BF561 || BF533 || BF532 || BF531)
199 211
212config BF_REV_0_6
213 bool "0.6"
214 depends on (BF533 || BF532 || BF531)
215
200config BF_REV_ANY 216config BF_REV_ANY
201 bool "any" 217 bool "any"
202 218
@@ -249,7 +265,7 @@ config MEM_MT48LC8M32B2B5_7
249 265
250config MEM_MT48LC32M16A2TG_75 266config MEM_MT48LC32M16A2TG_75
251 bool 267 bool
252 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP) 268 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
253 default y 269 default y
254 270
255source "arch/blackfin/mach-bf527/Kconfig" 271source "arch/blackfin/mach-bf527/Kconfig"
@@ -286,13 +302,20 @@ config BOOT_LOAD
286 memory region is used to capture NULL pointer references as well 302 memory region is used to capture NULL pointer references as well
287 as some core kernel functions. 303 as some core kernel functions.
288 304
305config ROM_BASE
306 hex "Kernel ROM Base"
307 default "0x20040000"
308 range 0x20000000 0x20400000 if !(BF54x || BF561)
309 range 0x20000000 0x30000000 if (BF54x || BF561)
310 help
311
289comment "Clock/PLL Setup" 312comment "Clock/PLL Setup"
290 313
291config CLKIN_HZ 314config CLKIN_HZ
292 int "Frequency of the crystal on the board in Hz" 315 int "Frequency of the crystal on the board in Hz"
293 default "11059200" if BFIN533_STAMP 316 default "11059200" if BFIN533_STAMP
294 default "27000000" if BFIN533_EZKIT 317 default "27000000" if BFIN533_EZKIT
295 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP) 318 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
296 default "30000000" if BFIN561_EZKIT 319 default "30000000" if BFIN561_EZKIT
297 default "24576000" if PNAV10 320 default "24576000" if PNAV10
298 default "10000000" if BFIN532_IP0X 321 default "10000000" if BFIN532_IP0X
@@ -332,7 +355,7 @@ config VCO_MULT
332 default "22" if BFIN533_BLUETECHNIX_CM 355 default "22" if BFIN533_BLUETECHNIX_CM
333 default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) 356 default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
334 default "20" if BFIN561_EZKIT 357 default "20" if BFIN561_EZKIT
335 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP) 358 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
336 help 359 help
337 This controls the frequency of the on-chip PLL. This can be between 1 and 64. 360 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
338 PLL Frequency = (Crystal Frequency) * (this setting) 361 PLL Frequency = (Crystal Frequency) * (this setting)
@@ -368,14 +391,6 @@ config SCLK_DIV
368 This can be between 1 and 15 391 This can be between 1 and 15
369 System Clock = (PLL frequency) / (this setting) 392 System Clock = (PLL frequency) / (this setting)
370 393
371config MAX_MEM_SIZE
372 int "Max SDRAM Memory Size in MBytes"
373 depends on !MPU
374 default 512
375 help
376 This is the max memory size that the kernel will create CPLB
377 tables for. Your system will not be able to handle any more.
378
379choice 394choice
380 prompt "DDR SDRAM Chip Type" 395 prompt "DDR SDRAM Chip Type"
381 depends on BFIN_KERNEL_CLOCK 396 depends on BFIN_KERNEL_CLOCK
@@ -389,6 +404,14 @@ config MEM_MT46V32M16_5B
389 bool "MT46V32M16_5B" 404 bool "MT46V32M16_5B"
390endchoice 405endchoice
391 406
407config MAX_MEM_SIZE
408 int "Max SDRAM Memory Size in MBytes"
409 depends on !MPU
410 default 512
411 help
412 This is the max memory size that the kernel will create CPLB
413 tables for. Your system will not be able to handle any more.
414
392# 415#
393# Max & Min Speeds for various Chips 416# Max & Min Speeds for various Chips
394# 417#
@@ -455,8 +478,6 @@ config CYCLES_CLOCKSOURCE
455 478
456source kernel/time/Kconfig 479source kernel/time/Kconfig
457 480
458comment "Memory Setup"
459
460comment "Misc" 481comment "Misc"
461 482
462choice 483choice
@@ -622,6 +643,15 @@ config CPLB_SWITCH_TAB_L1
622 If enabled, the CPLB Switch Tables are linked 643 If enabled, the CPLB Switch Tables are linked
623 into L1 data memory. (less latency) 644 into L1 data memory. (less latency)
624 645
646config APP_STACK_L1
647 bool "Support locating application stack in L1 Scratch Memory"
648 default y
649 help
650 If enabled the application stack can be located in L1
651 scratch memory (less latency).
652
653 Currently only works with FLAT binaries.
654
625comment "Speed Optimizations" 655comment "Speed Optimizations"
626config BFIN_INS_LOWOVERHEAD 656config BFIN_INS_LOWOVERHEAD
627 bool "ins[bwl] low overhead, higher interrupt latency" 657 bool "ins[bwl] low overhead, higher interrupt latency"
@@ -755,6 +785,13 @@ config BFIN_WT
755 785
756endchoice 786endchoice
757 787
788config BFIN_L2_CACHEABLE
789 bool "Cache L2 SRAM"
790 depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
791 default n
792 help
793 Select to make L2 SRAM cacheable in L1 data and instruction cache.
794
758config MPU 795config MPU
759 bool "Enable the memory protection unit (EXPERIMENTAL)" 796 bool "Enable the memory protection unit (EXPERIMENTAL)"
760 default n 797 default n
diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug
index c468624d55f0..3ad25983ec97 100644
--- a/arch/blackfin/Kconfig.debug
+++ b/arch/blackfin/Kconfig.debug
@@ -2,6 +2,22 @@ menu "Kernel hacking"
2 2
3source "lib/Kconfig.debug" 3source "lib/Kconfig.debug"
4 4
5config HAVE_ARCH_KGDB
6 def_bool y
7
8config DEBUG_VERBOSE
9 bool "Verbose fault messages"
10 default y
11 select PRINTK
12 help
13 When a program crashes due to an exception, or the kernel detects
14 an internal error, the kernel can print a not so brief message
15 explaining what the problem was. This debugging information is
16 useful to developers and kernel hackers when tracking down problems,
17 but mostly meaningless to other people. This is always helpful for
18 debugging but serves no purpose on a production system.
19 Most people should say N here.
20
5config DEBUG_MMRS 21config DEBUG_MMRS
6 bool "Generate Blackfin MMR tree" 22 bool "Generate Blackfin MMR tree"
7 select DEBUG_FS 23 select DEBUG_FS
@@ -22,6 +38,44 @@ config DEBUG_HWERR
22 hardware error interrupts and need to know where they are coming 38 hardware error interrupts and need to know where they are coming
23 from. 39 from.
24 40
41config DEBUG_DOUBLEFAULT
42 bool "Debug Double Faults"
43 default n
44 help
45 If an exception is caused while executing code within the exception
46 handler, the NMI handler, the reset vector, or in emulator mode,
47 a double fault occurs. On the Blackfin, this is a unrecoverable
48 event. You have two options:
49 - RESET exactly when double fault occurs. The excepting
50 instruction address is stored in RETX, where the next kernel
51 boot will print it out.
52 - Print debug message. This is much more error prone, although
53 easier to handle. It is error prone since:
54 - The excepting instruction is not committed.
55 - All writebacks from the instruction are prevented.
56 - The generated exception is not taken.
57 - The EXCAUSE field is updated with an unrecoverable event
58 The only way to check this is to see if EXCAUSE contains the
59 unrecoverable event value at every exception return. By selecting
60 this option, you are skipping over the faulting instruction, and
61 hoping things stay together enough to print out a debug message.
62
63 This does add a little kernel code, but is the only method to debug
64 double faults - if unsure say "Y"
65
66choice
67 prompt "Double Fault Failure Method"
68 default DEBUG_DOUBLEFAULT_PRINT
69 depends on DEBUG_DOUBLEFAULT
70
71config DEBUG_DOUBLEFAULT_PRINT
72 bool "Print"
73
74config DEBUG_DOUBLEFAULT_RESET
75 bool "Reset"
76
77endchoice
78
25config DEBUG_ICACHE_CHECK 79config DEBUG_ICACHE_CHECK
26 bool "Check Instruction cache coherency" 80 bool "Check Instruction cache coherency"
27 depends on DEBUG_KERNEL 81 depends on DEBUG_KERNEL
@@ -143,6 +197,7 @@ config DEBUG_BFIN_NO_KERN_HWTRACE
143config EARLY_PRINTK 197config EARLY_PRINTK
144 bool "Early printk" 198 bool "Early printk"
145 default n 199 default n
200 select SERIAL_CORE_CONSOLE
146 help 201 help
147 This option enables special console drivers which allow the kernel 202 This option enables special console drivers which allow the kernel
148 to print messages very early in the bootup process. 203 to print messages very early in the bootup process.
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index eac0533d6e4f..6bf50977850c 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -67,6 +67,7 @@ rev-$(CONFIG_BF_REV_0_2) := 0.2
67rev-$(CONFIG_BF_REV_0_3) := 0.3 67rev-$(CONFIG_BF_REV_0_3) := 0.3
68rev-$(CONFIG_BF_REV_0_4) := 0.4 68rev-$(CONFIG_BF_REV_0_4) := 0.4
69rev-$(CONFIG_BF_REV_0_5) := 0.5 69rev-$(CONFIG_BF_REV_0_5) := 0.5
70rev-$(CONFIG_BF_REV_0_6) := 0.6
70rev-$(CONFIG_BF_REV_NONE) := none 71rev-$(CONFIG_BF_REV_NONE) := none
71rev-$(CONFIG_BF_REV_ANY) := any 72rev-$(CONFIG_BF_REV_ANY) := any
72 73
diff --git a/arch/blackfin/configs/BF526-EZBRD_defconfig b/arch/blackfin/configs/BF526-EZBRD_defconfig
new file mode 100644
index 000000000000..c33bf6f83813
--- /dev/null
+++ b/arch/blackfin/configs/BF526-EZBRD_defconfig
@@ -0,0 +1,1427 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26.3
4# Thu Aug 28 16:49:53 2008
5#
6# CONFIG_MMU is not set
7# CONFIG_FPU is not set
8CONFIG_RWSEM_GENERIC_SPINLOCK=y
9# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
10CONFIG_BLACKFIN=y
11CONFIG_ZONE_DMA=y
12CONFIG_GENERIC_FIND_NEXT_BIT=y
13CONFIG_GENERIC_HWEIGHT=y
14CONFIG_GENERIC_HARDIRQS=y
15CONFIG_GENERIC_IRQ_PROBE=y
16CONFIG_GENERIC_GPIO=y
17CONFIG_FORCE_MAX_ZONEORDER=14
18CONFIG_GENERIC_CALIBRATE_DELAY=y
19CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
20
21#
22# General setup
23#
24CONFIG_EXPERIMENTAL=y
25CONFIG_BROKEN_ON_SMP=y
26CONFIG_INIT_ENV_ARG_LIMIT=32
27CONFIG_LOCALVERSION=""
28CONFIG_LOCALVERSION_AUTO=y
29CONFIG_SYSVIPC=y
30CONFIG_SYSVIPC_SYSCTL=y
31# CONFIG_POSIX_MQUEUE is not set
32# CONFIG_BSD_PROCESS_ACCT is not set
33# CONFIG_TASKSTATS is not set
34# CONFIG_AUDIT is not set
35CONFIG_IKCONFIG=y
36CONFIG_IKCONFIG_PROC=y
37CONFIG_LOG_BUF_SHIFT=14
38# CONFIG_CGROUPS is not set
39# CONFIG_GROUP_SCHED is not set
40CONFIG_SYSFS_DEPRECATED=y
41CONFIG_SYSFS_DEPRECATED_V2=y
42# CONFIG_RELAY is not set
43# CONFIG_NAMESPACES is not set
44CONFIG_BLK_DEV_INITRD=y
45CONFIG_INITRAMFS_SOURCE=""
46# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
47CONFIG_SYSCTL=y
48CONFIG_EMBEDDED=y
49CONFIG_UID16=y
50CONFIG_SYSCTL_SYSCALL=y
51CONFIG_SYSCTL_SYSCALL_CHECK=y
52CONFIG_KALLSYMS=y
53# CONFIG_KALLSYMS_EXTRA_PASS is not set
54CONFIG_HOTPLUG=y
55CONFIG_PRINTK=y
56CONFIG_BUG=y
57CONFIG_ELF_CORE=y
58CONFIG_COMPAT_BRK=y
59CONFIG_BASE_FULL=y
60CONFIG_FUTEX=y
61CONFIG_ANON_INODES=y
62CONFIG_EPOLL=y
63CONFIG_SIGNALFD=y
64CONFIG_TIMERFD=y
65CONFIG_EVENTFD=y
66CONFIG_VM_EVENT_COUNTERS=y
67CONFIG_SLAB=y
68# CONFIG_SLUB is not set
69# CONFIG_SLOB is not set
70# CONFIG_PROFILING is not set
71# CONFIG_MARKERS is not set
72CONFIG_HAVE_OPROFILE=y
73# CONFIG_HAVE_KPROBES is not set
74# CONFIG_HAVE_KRETPROBES is not set
75# CONFIG_HAVE_DMA_ATTRS is not set
76CONFIG_SLABINFO=y
77CONFIG_RT_MUTEXES=y
78CONFIG_TINY_SHMEM=y
79CONFIG_BASE_SMALL=0
80CONFIG_MODULES=y
81# CONFIG_MODULE_FORCE_LOAD is not set
82CONFIG_MODULE_UNLOAD=y
83# CONFIG_MODULE_FORCE_UNLOAD is not set
84# CONFIG_MODVERSIONS is not set
85# CONFIG_MODULE_SRCVERSION_ALL is not set
86CONFIG_KMOD=y
87CONFIG_BLOCK=y
88# CONFIG_LBD is not set
89# CONFIG_BLK_DEV_IO_TRACE is not set
90# CONFIG_LSF is not set
91# CONFIG_BLK_DEV_BSG is not set
92
93#
94# IO Schedulers
95#
96CONFIG_IOSCHED_NOOP=y
97# CONFIG_IOSCHED_AS is not set
98# CONFIG_IOSCHED_DEADLINE is not set
99# CONFIG_IOSCHED_CFQ is not set
100# CONFIG_DEFAULT_AS is not set
101# CONFIG_DEFAULT_DEADLINE is not set
102# CONFIG_DEFAULT_CFQ is not set
103CONFIG_DEFAULT_NOOP=y
104CONFIG_DEFAULT_IOSCHED="noop"
105CONFIG_CLASSIC_RCU=y
106# CONFIG_PREEMPT_NONE is not set
107CONFIG_PREEMPT_VOLUNTARY=y
108# CONFIG_PREEMPT is not set
109
110#
111# Blackfin Processor Options
112#
113
114#
115# Processor and Board Settings
116#
117# CONFIG_BF522 is not set
118# CONFIG_BF523 is not set
119# CONFIG_BF524 is not set
120# CONFIG_BF525 is not set
121CONFIG_BF526=y
122# CONFIG_BF527 is not set
123# CONFIG_BF531 is not set
124# CONFIG_BF532 is not set
125# CONFIG_BF533 is not set
126# CONFIG_BF534 is not set
127# CONFIG_BF536 is not set
128# CONFIG_BF537 is not set
129# CONFIG_BF542 is not set
130# CONFIG_BF544 is not set
131# CONFIG_BF547 is not set
132# CONFIG_BF548 is not set
133# CONFIG_BF549 is not set
134# CONFIG_BF561 is not set
135CONFIG_BF_REV_0_0=y
136# CONFIG_BF_REV_0_1 is not set
137# CONFIG_BF_REV_0_2 is not set
138# CONFIG_BF_REV_0_3 is not set
139# CONFIG_BF_REV_0_4 is not set
140# CONFIG_BF_REV_0_5 is not set
141# CONFIG_BF_REV_ANY is not set
142# CONFIG_BF_REV_NONE is not set
143CONFIG_BF52x=y
144CONFIG_MEM_MT48LC32M16A2TG_75=y
145# CONFIG_BFIN527_EZKIT is not set
146# CONFIG_BFIN527_BLUETECHNIX_CM is not set
147CONFIG_BFIN526_EZBRD=y
148
149#
150# BF527 Specific Configuration
151#
152
153#
154# Alternative Multiplexing Scheme
155#
156# CONFIG_BF527_SPORT0_PORTF is not set
157CONFIG_BF527_SPORT0_PORTG=y
158CONFIG_BF527_SPORT0_TSCLK_PG10=y
159# CONFIG_BF527_SPORT0_TSCLK_PG14 is not set
160CONFIG_BF527_UART1_PORTF=y
161# CONFIG_BF527_UART1_PORTG is not set
162# CONFIG_BF527_NAND_D_PORTF is not set
163CONFIG_BF527_NAND_D_PORTH=y
164
165#
166# Interrupt Priority Assignment
167#
168
169#
170# Priority
171#
172CONFIG_IRQ_PLL_WAKEUP=7
173CONFIG_IRQ_DMA0_ERROR=7
174CONFIG_IRQ_DMAR0_BLK=7
175CONFIG_IRQ_DMAR1_BLK=7
176CONFIG_IRQ_DMAR0_OVR=7
177CONFIG_IRQ_DMAR1_OVR=7
178CONFIG_IRQ_PPI_ERROR=7
179CONFIG_IRQ_MAC_ERROR=7
180CONFIG_IRQ_SPORT0_ERROR=7
181CONFIG_IRQ_SPORT1_ERROR=7
182CONFIG_IRQ_UART0_ERROR=7
183CONFIG_IRQ_UART1_ERROR=7
184CONFIG_IRQ_RTC=8
185CONFIG_IRQ_PPI=8
186CONFIG_IRQ_SPORT0_RX=9
187CONFIG_IRQ_SPORT0_TX=9
188CONFIG_IRQ_SPORT1_RX=9
189CONFIG_IRQ_SPORT1_TX=9
190CONFIG_IRQ_TWI=10
191CONFIG_IRQ_SPI=10
192CONFIG_IRQ_UART0_RX=10
193CONFIG_IRQ_UART0_TX=10
194CONFIG_IRQ_UART1_RX=10
195CONFIG_IRQ_UART1_TX=10
196CONFIG_IRQ_OPTSEC=11
197CONFIG_IRQ_CNT=11
198CONFIG_IRQ_MAC_RX=11
199CONFIG_IRQ_PORTH_INTA=11
200CONFIG_IRQ_MAC_TX=11
201CONFIG_IRQ_PORTH_INTB=11
202CONFIG_IRQ_TMR0=12
203CONFIG_IRQ_TMR1=12
204CONFIG_IRQ_TMR2=12
205CONFIG_IRQ_TMR3=12
206CONFIG_IRQ_TMR4=12
207CONFIG_IRQ_TMR5=12
208CONFIG_IRQ_TMR6=12
209CONFIG_IRQ_TMR7=12
210CONFIG_IRQ_PORTG_INTA=12
211CONFIG_IRQ_PORTG_INTB=12
212CONFIG_IRQ_MEM_DMA0=13
213CONFIG_IRQ_MEM_DMA1=13
214CONFIG_IRQ_WATCH=13
215CONFIG_IRQ_PORTF_INTA=13
216CONFIG_IRQ_PORTF_INTB=13
217CONFIG_IRQ_SPI_ERROR=7
218CONFIG_IRQ_NFC_ERROR=7
219CONFIG_IRQ_HDMA_ERROR=7
220CONFIG_IRQ_HDMA=7
221CONFIG_IRQ_USB_EINT=10
222CONFIG_IRQ_USB_INT0=11
223CONFIG_IRQ_USB_INT1=11
224CONFIG_IRQ_USB_INT2=11
225CONFIG_IRQ_USB_DMA=11
226
227#
228# Board customizations
229#
230# CONFIG_CMDLINE_BOOL is not set
231CONFIG_BOOT_LOAD=0x1000
232
233#
234# Clock/PLL Setup
235#
236CONFIG_CLKIN_HZ=25000000
237# CONFIG_BFIN_KERNEL_CLOCK is not set
238CONFIG_MAX_MEM_SIZE=512
239CONFIG_MAX_VCO_HZ=400000000
240CONFIG_MIN_VCO_HZ=50000000
241CONFIG_MAX_SCLK_HZ=133333333
242CONFIG_MIN_SCLK_HZ=27000000
243
244#
245# Kernel Timer/Scheduler
246#
247# CONFIG_HZ_100 is not set
248CONFIG_HZ_250=y
249# CONFIG_HZ_300 is not set
250# CONFIG_HZ_1000 is not set
251CONFIG_HZ=250
252# CONFIG_SCHED_HRTICK is not set
253CONFIG_GENERIC_TIME=y
254CONFIG_GENERIC_CLOCKEVENTS=y
255# CONFIG_CYCLES_CLOCKSOURCE is not set
256# CONFIG_TICK_ONESHOT is not set
257# CONFIG_NO_HZ is not set
258# CONFIG_HIGH_RES_TIMERS is not set
259CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
260
261#
262# Memory Setup
263#
264
265#
266# Misc
267#
268CONFIG_BFIN_SCRATCH_REG_RETN=y
269# CONFIG_BFIN_SCRATCH_REG_RETE is not set
270# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
271
272#
273# Blackfin Kernel Optimizations
274#
275
276#
277# Memory Optimizations
278#
279CONFIG_I_ENTRY_L1=y
280CONFIG_EXCPT_IRQ_SYSC_L1=y
281CONFIG_DO_IRQ_L1=y
282CONFIG_CORE_TIMER_IRQ_L1=y
283CONFIG_IDLE_L1=y
284# CONFIG_SCHEDULE_L1 is not set
285CONFIG_ARITHMETIC_OPS_L1=y
286CONFIG_ACCESS_OK_L1=y
287# CONFIG_MEMSET_L1 is not set
288# CONFIG_MEMCPY_L1 is not set
289# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
290# CONFIG_IP_CHECKSUM_L1 is not set
291CONFIG_CACHELINE_ALIGNED_L1=y
292# CONFIG_SYSCALL_TAB_L1 is not set
293# CONFIG_CPLB_SWITCH_TAB_L1 is not set
294
295#
296# Speed Optimizations
297#
298CONFIG_BFIN_INS_LOWOVERHEAD=y
299CONFIG_RAMKERNEL=y
300# CONFIG_ROMKERNEL is not set
301CONFIG_SELECT_MEMORY_MODEL=y
302CONFIG_FLATMEM_MANUAL=y
303# CONFIG_DISCONTIGMEM_MANUAL is not set
304# CONFIG_SPARSEMEM_MANUAL is not set
305CONFIG_FLATMEM=y
306CONFIG_FLAT_NODE_MEM_MAP=y
307# CONFIG_SPARSEMEM_STATIC is not set
308# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
309CONFIG_PAGEFLAGS_EXTENDED=y
310CONFIG_SPLIT_PTLOCK_CPUS=4
311# CONFIG_RESOURCES_64BIT is not set
312CONFIG_ZONE_DMA_FLAG=1
313CONFIG_VIRT_TO_BUS=y
314CONFIG_BFIN_GPTIMERS=y
315CONFIG_BFIN_DMA_5XX=y
316# CONFIG_DMA_UNCACHED_4M is not set
317# CONFIG_DMA_UNCACHED_2M is not set
318CONFIG_DMA_UNCACHED_1M=y
319# CONFIG_DMA_UNCACHED_NONE is not set
320
321#
322# Cache Support
323#
324CONFIG_BFIN_ICACHE=y
325CONFIG_BFIN_DCACHE=y
326# CONFIG_BFIN_DCACHE_BANKA is not set
327# CONFIG_BFIN_ICACHE_LOCK is not set
328CONFIG_BFIN_WB=y
329# CONFIG_BFIN_WT is not set
330# CONFIG_MPU is not set
331
332#
333# Asynchonous Memory Configuration
334#
335
336#
337# EBIU_AMGCTL Global Control
338#
339CONFIG_C_AMCKEN=y
340CONFIG_C_CDPRIO=y
341# CONFIG_C_AMBEN is not set
342# CONFIG_C_AMBEN_B0 is not set
343# CONFIG_C_AMBEN_B0_B1 is not set
344# CONFIG_C_AMBEN_B0_B1_B2 is not set
345CONFIG_C_AMBEN_ALL=y
346
347#
348# EBIU_AMBCTL Control
349#
350CONFIG_BANK_0=0x7BB0
351CONFIG_BANK_1=0x5554
352CONFIG_BANK_2=0x7BB0
353CONFIG_BANK_3=0xFFC0
354
355#
356# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
357#
358# CONFIG_ARCH_SUPPORTS_MSI is not set
359# CONFIG_PCCARD is not set
360
361#
362# Executable file formats
363#
364CONFIG_BINFMT_ELF_FDPIC=y
365CONFIG_BINFMT_FLAT=y
366CONFIG_BINFMT_ZFLAT=y
367# CONFIG_BINFMT_SHARED_FLAT is not set
368# CONFIG_BINFMT_MISC is not set
369
370#
371# Power management options
372#
373# CONFIG_PM is not set
374CONFIG_ARCH_SUSPEND_POSSIBLE=y
375# CONFIG_PM_WAKEUP_BY_GPIO is not set
376
377#
378# CPU Frequency scaling
379#
380# CONFIG_CPU_FREQ is not set
381
382#
383# Networking
384#
385CONFIG_NET=y
386
387#
388# Networking options
389#
390CONFIG_PACKET=y
391# CONFIG_PACKET_MMAP is not set
392CONFIG_UNIX=y
393CONFIG_XFRM=y
394# CONFIG_XFRM_USER is not set
395# CONFIG_XFRM_SUB_POLICY is not set
396# CONFIG_XFRM_MIGRATE is not set
397# CONFIG_XFRM_STATISTICS is not set
398# CONFIG_NET_KEY is not set
399CONFIG_INET=y
400# CONFIG_IP_MULTICAST is not set
401# CONFIG_IP_ADVANCED_ROUTER is not set
402CONFIG_IP_FIB_HASH=y
403CONFIG_IP_PNP=y
404# CONFIG_IP_PNP_DHCP is not set
405# CONFIG_IP_PNP_BOOTP is not set
406# CONFIG_IP_PNP_RARP is not set
407# CONFIG_NET_IPIP is not set
408# CONFIG_NET_IPGRE is not set
409# CONFIG_ARPD is not set
410CONFIG_SYN_COOKIES=y
411# CONFIG_INET_AH is not set
412# CONFIG_INET_ESP is not set
413# CONFIG_INET_IPCOMP is not set
414# CONFIG_INET_XFRM_TUNNEL is not set
415# CONFIG_INET_TUNNEL is not set
416CONFIG_INET_XFRM_MODE_TRANSPORT=y
417CONFIG_INET_XFRM_MODE_TUNNEL=y
418CONFIG_INET_XFRM_MODE_BEET=y
419# CONFIG_INET_LRO is not set
420CONFIG_INET_DIAG=y
421CONFIG_INET_TCP_DIAG=y
422# CONFIG_TCP_CONG_ADVANCED is not set
423CONFIG_TCP_CONG_CUBIC=y
424CONFIG_DEFAULT_TCP_CONG="cubic"
425# CONFIG_TCP_MD5SIG is not set
426# CONFIG_IPV6 is not set
427# CONFIG_NETLABEL is not set
428# CONFIG_NETWORK_SECMARK is not set
429# CONFIG_NETFILTER is not set
430# CONFIG_IP_DCCP is not set
431# CONFIG_IP_SCTP is not set
432# CONFIG_TIPC is not set
433# CONFIG_ATM is not set
434# CONFIG_BRIDGE is not set
435# CONFIG_VLAN_8021Q is not set
436# CONFIG_DECNET is not set
437# CONFIG_LLC2 is not set
438# CONFIG_IPX is not set
439# CONFIG_ATALK is not set
440# CONFIG_X25 is not set
441# CONFIG_LAPB is not set
442# CONFIG_ECONET is not set
443# CONFIG_WAN_ROUTER is not set
444# CONFIG_NET_SCHED is not set
445
446#
447# Network testing
448#
449# CONFIG_NET_PKTGEN is not set
450# CONFIG_HAMRADIO is not set
451# CONFIG_CAN is not set
452# CONFIG_IRDA is not set
453# CONFIG_BT is not set
454# CONFIG_AF_RXRPC is not set
455
456#
457# Wireless
458#
459# CONFIG_CFG80211 is not set
460# CONFIG_WIRELESS_EXT is not set
461# CONFIG_MAC80211 is not set
462# CONFIG_IEEE80211 is not set
463# CONFIG_RFKILL is not set
464# CONFIG_NET_9P is not set
465
466#
467# Device Drivers
468#
469
470#
471# Generic Driver Options
472#
473CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
474CONFIG_STANDALONE=y
475CONFIG_PREVENT_FIRMWARE_BUILD=y
476# CONFIG_FW_LOADER is not set
477# CONFIG_SYS_HYPERVISOR is not set
478# CONFIG_CONNECTOR is not set
479CONFIG_MTD=y
480# CONFIG_MTD_DEBUG is not set
481# CONFIG_MTD_CONCAT is not set
482CONFIG_MTD_PARTITIONS=y
483# CONFIG_MTD_REDBOOT_PARTS is not set
484# CONFIG_MTD_CMDLINE_PARTS is not set
485# CONFIG_MTD_AR7_PARTS is not set
486
487#
488# User Modules And Translation Layers
489#
490CONFIG_MTD_CHAR=m
491CONFIG_MTD_BLKDEVS=y
492CONFIG_MTD_BLOCK=y
493# CONFIG_FTL is not set
494# CONFIG_NFTL is not set
495# CONFIG_INFTL is not set
496# CONFIG_RFD_FTL is not set
497# CONFIG_SSFDC is not set
498# CONFIG_MTD_OOPS is not set
499
500#
501# RAM/ROM/Flash chip drivers
502#
503# CONFIG_MTD_CFI is not set
504CONFIG_MTD_JEDECPROBE=m
505CONFIG_MTD_GEN_PROBE=m
506# CONFIG_MTD_CFI_ADV_OPTIONS is not set
507CONFIG_MTD_MAP_BANK_WIDTH_1=y
508CONFIG_MTD_MAP_BANK_WIDTH_2=y
509CONFIG_MTD_MAP_BANK_WIDTH_4=y
510# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
511# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
512# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
513CONFIG_MTD_CFI_I1=y
514CONFIG_MTD_CFI_I2=y
515# CONFIG_MTD_CFI_I4 is not set
516# CONFIG_MTD_CFI_I8 is not set
517# CONFIG_MTD_CFI_INTELEXT is not set
518# CONFIG_MTD_CFI_AMDSTD is not set
519# CONFIG_MTD_CFI_STAA is not set
520CONFIG_MTD_RAM=y
521CONFIG_MTD_ROM=m
522# CONFIG_MTD_ABSENT is not set
523
524#
525# Mapping drivers for chip access
526#
527CONFIG_MTD_COMPLEX_MAPPINGS=y
528# CONFIG_MTD_PHYSMAP is not set
529# CONFIG_MTD_GPIO_ADDR is not set
530# CONFIG_MTD_UCLINUX is not set
531# CONFIG_MTD_PLATRAM is not set
532
533#
534# Self-contained MTD device drivers
535#
536# CONFIG_MTD_DATAFLASH is not set
537# CONFIG_MTD_M25P80 is not set
538# CONFIG_MTD_SLRAM is not set
539# CONFIG_MTD_PHRAM is not set
540# CONFIG_MTD_MTDRAM is not set
541# CONFIG_MTD_BLOCK2MTD is not set
542
543#
544# Disk-On-Chip Device Drivers
545#
546# CONFIG_MTD_DOC2000 is not set
547# CONFIG_MTD_DOC2001 is not set
548# CONFIG_MTD_DOC2001PLUS is not set
549CONFIG_MTD_NAND=m
550# CONFIG_MTD_NAND_VERIFY_WRITE is not set
551# CONFIG_MTD_NAND_ECC_SMC is not set
552# CONFIG_MTD_NAND_MUSEUM_IDS is not set
553CONFIG_MTD_NAND_BFIN=m
554CONFIG_BFIN_NAND_BASE=0x20212000
555CONFIG_BFIN_NAND_CLE=2
556CONFIG_BFIN_NAND_ALE=1
557CONFIG_BFIN_NAND_READY=3
558CONFIG_MTD_NAND_IDS=m
559# CONFIG_MTD_NAND_BF5XX is not set
560# CONFIG_MTD_NAND_DISKONCHIP is not set
561# CONFIG_MTD_NAND_NANDSIM is not set
562# CONFIG_MTD_NAND_PLATFORM is not set
563# CONFIG_MTD_ALAUDA is not set
564# CONFIG_MTD_ONENAND is not set
565
566#
567# UBI - Unsorted block images
568#
569# CONFIG_MTD_UBI is not set
570# CONFIG_PARPORT is not set
571CONFIG_BLK_DEV=y
572# CONFIG_BLK_DEV_COW_COMMON is not set
573# CONFIG_BLK_DEV_LOOP is not set
574# CONFIG_BLK_DEV_NBD is not set
575# CONFIG_BLK_DEV_UB is not set
576CONFIG_BLK_DEV_RAM=y
577CONFIG_BLK_DEV_RAM_COUNT=16
578CONFIG_BLK_DEV_RAM_SIZE=4096
579# CONFIG_BLK_DEV_XIP is not set
580# CONFIG_CDROM_PKTCDVD is not set
581# CONFIG_ATA_OVER_ETH is not set
582CONFIG_MISC_DEVICES=y
583# CONFIG_EEPROM_93CX6 is not set
584# CONFIG_ENCLOSURE_SERVICES is not set
585CONFIG_HAVE_IDE=y
586# CONFIG_IDE is not set
587
588#
589# SCSI device support
590#
591# CONFIG_RAID_ATTRS is not set
592# CONFIG_SCSI is not set
593# CONFIG_SCSI_DMA is not set
594# CONFIG_SCSI_NETLINK is not set
595# CONFIG_ATA is not set
596# CONFIG_MD is not set
597CONFIG_NETDEVICES=y
598# CONFIG_NETDEVICES_MULTIQUEUE is not set
599# CONFIG_DUMMY is not set
600# CONFIG_BONDING is not set
601# CONFIG_MACVLAN is not set
602# CONFIG_EQUALIZER is not set
603# CONFIG_TUN is not set
604# CONFIG_VETH is not set
605CONFIG_PHYLIB=y
606
607#
608# MII PHY device drivers
609#
610# CONFIG_MARVELL_PHY is not set
611# CONFIG_DAVICOM_PHY is not set
612# CONFIG_QSEMI_PHY is not set
613# CONFIG_LXT_PHY is not set
614# CONFIG_CICADA_PHY is not set
615# CONFIG_VITESSE_PHY is not set
616# CONFIG_SMSC_PHY is not set
617# CONFIG_BROADCOM_PHY is not set
618# CONFIG_ICPLUS_PHY is not set
619# CONFIG_REALTEK_PHY is not set
620# CONFIG_FIXED_PHY is not set
621# CONFIG_MDIO_BITBANG is not set
622CONFIG_NET_ETHERNET=y
623CONFIG_MII=y
624CONFIG_BFIN_MAC=y
625CONFIG_BFIN_TX_DESC_NUM=10
626CONFIG_BFIN_RX_DESC_NUM=20
627CONFIG_BFIN_MAC_RMII=y
628# CONFIG_SMC91X is not set
629# CONFIG_SMSC911X is not set
630# CONFIG_DM9000 is not set
631# CONFIG_ENC28J60 is not set
632# CONFIG_IBM_NEW_EMAC_ZMII is not set
633# CONFIG_IBM_NEW_EMAC_RGMII is not set
634# CONFIG_IBM_NEW_EMAC_TAH is not set
635# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
636# CONFIG_B44 is not set
637CONFIG_NETDEV_1000=y
638# CONFIG_E1000E_ENABLED is not set
639# CONFIG_AX88180 is not set
640CONFIG_NETDEV_10000=y
641
642#
643# Wireless LAN
644#
645# CONFIG_WLAN_PRE80211 is not set
646# CONFIG_WLAN_80211 is not set
647# CONFIG_IWLWIFI_LEDS is not set
648
649#
650# USB Network Adapters
651#
652# CONFIG_USB_CATC is not set
653# CONFIG_USB_KAWETH is not set
654# CONFIG_USB_PEGASUS is not set
655# CONFIG_USB_RTL8150 is not set
656# CONFIG_USB_USBNET is not set
657# CONFIG_WAN is not set
658# CONFIG_PPP is not set
659# CONFIG_SLIP is not set
660# CONFIG_NETCONSOLE is not set
661# CONFIG_NETPOLL is not set
662# CONFIG_NET_POLL_CONTROLLER is not set
663# CONFIG_ISDN is not set
664# CONFIG_PHONE is not set
665
666#
667# Input device support
668#
669CONFIG_INPUT=y
670# CONFIG_INPUT_FF_MEMLESS is not set
671# CONFIG_INPUT_POLLDEV is not set
672
673#
674# Userland interfaces
675#
676# CONFIG_INPUT_MOUSEDEV is not set
677# CONFIG_INPUT_JOYDEV is not set
678# CONFIG_INPUT_EVDEV is not set
679# CONFIG_INPUT_EVBUG is not set
680
681#
682# Input Device Drivers
683#
684# CONFIG_INPUT_KEYBOARD is not set
685# CONFIG_INPUT_MOUSE is not set
686# CONFIG_INPUT_JOYSTICK is not set
687# CONFIG_INPUT_TABLET is not set
688# CONFIG_INPUT_TOUCHSCREEN is not set
689CONFIG_INPUT_MISC=y
690# CONFIG_INPUT_ATI_REMOTE is not set
691# CONFIG_INPUT_ATI_REMOTE2 is not set
692# CONFIG_INPUT_KEYSPAN_REMOTE is not set
693# CONFIG_INPUT_POWERMATE is not set
694# CONFIG_INPUT_YEALINK is not set
695# CONFIG_INPUT_UINPUT is not set
696# CONFIG_TWI_KEYPAD is not set
697
698#
699# Hardware I/O ports
700#
701# CONFIG_SERIO is not set
702# CONFIG_GAMEPORT is not set
703
704#
705# Character devices
706#
707# CONFIG_AD9960 is not set
708# CONFIG_SPI_ADC_BF533 is not set
709# CONFIG_BF5xx_PPIFCD is not set
710# CONFIG_BFIN_SIMPLE_TIMER is not set
711# CONFIG_BF5xx_PPI is not set
712# CONFIG_BFIN_SPORT is not set
713# CONFIG_BFIN_TIMER_LATENCY is not set
714# CONFIG_TWI_LCD is not set
715CONFIG_SIMPLE_GPIO=m
716CONFIG_VT=y
717CONFIG_VT_CONSOLE=y
718CONFIG_HW_CONSOLE=y
719# CONFIG_VT_HW_CONSOLE_BINDING is not set
720CONFIG_DEVKMEM=y
721# CONFIG_SERIAL_NONSTANDARD is not set
722
723#
724# Serial drivers
725#
726# CONFIG_SERIAL_8250 is not set
727
728#
729# Non-8250 serial port support
730#
731CONFIG_SERIAL_BFIN=y
732CONFIG_SERIAL_BFIN_CONSOLE=y
733CONFIG_SERIAL_BFIN_DMA=y
734# CONFIG_SERIAL_BFIN_PIO is not set
735# CONFIG_SERIAL_BFIN_UART0 is not set
736CONFIG_SERIAL_BFIN_UART1=y
737# CONFIG_BFIN_UART1_CTSRTS is not set
738CONFIG_SERIAL_CORE=y
739CONFIG_SERIAL_CORE_CONSOLE=y
740# CONFIG_SERIAL_BFIN_SPORT is not set
741CONFIG_UNIX98_PTYS=y
742# CONFIG_LEGACY_PTYS is not set
743CONFIG_BFIN_OTP=y
744# CONFIG_BFIN_OTP_WRITE_ENABLE is not set
745
746#
747# CAN, the car bus and industrial fieldbus
748#
749# CONFIG_CAN4LINUX is not set
750# CONFIG_IPMI_HANDLER is not set
751CONFIG_HW_RANDOM=y
752# CONFIG_R3964 is not set
753# CONFIG_RAW_DRIVER is not set
754# CONFIG_TCG_TPM is not set
755CONFIG_I2C=y
756CONFIG_I2C_BOARDINFO=y
757CONFIG_I2C_CHARDEV=m
758CONFIG_I2C_HELPER_AUTO=y
759
760#
761# I2C Hardware Bus support
762#
763CONFIG_I2C_BLACKFIN_TWI=y
764CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
765# CONFIG_I2C_GPIO is not set
766# CONFIG_I2C_OCORES is not set
767# CONFIG_I2C_PARPORT_LIGHT is not set
768# CONFIG_I2C_SIMTEC is not set
769# CONFIG_I2C_TAOS_EVM is not set
770# CONFIG_I2C_STUB is not set
771# CONFIG_I2C_TINY_USB is not set
772# CONFIG_I2C_PCA_PLATFORM is not set
773
774#
775# Miscellaneous I2C Chip support
776#
777# CONFIG_DS1682 is not set
778# CONFIG_SENSORS_AD5252 is not set
779# CONFIG_SENSORS_EEPROM is not set
780# CONFIG_SENSORS_PCF8574 is not set
781# CONFIG_PCF8575 is not set
782# CONFIG_SENSORS_PCF8591 is not set
783# CONFIG_SENSORS_MAX6875 is not set
784# CONFIG_SENSORS_TSL2550 is not set
785# CONFIG_I2C_DEBUG_CORE is not set
786# CONFIG_I2C_DEBUG_ALGO is not set
787# CONFIG_I2C_DEBUG_BUS is not set
788# CONFIG_I2C_DEBUG_CHIP is not set
789CONFIG_SPI=y
790CONFIG_SPI_MASTER=y
791
792#
793# SPI Master Controller Drivers
794#
795CONFIG_SPI_BFIN=y
796# CONFIG_SPI_BITBANG is not set
797
798#
799# SPI Protocol Masters
800#
801# CONFIG_SPI_AT25 is not set
802# CONFIG_SPI_SPIDEV is not set
803# CONFIG_SPI_TLE62X0 is not set
804# CONFIG_W1 is not set
805# CONFIG_POWER_SUPPLY is not set
806CONFIG_HWMON=y
807# CONFIG_HWMON_VID is not set
808# CONFIG_SENSORS_AD7418 is not set
809# CONFIG_SENSORS_ADM1021 is not set
810# CONFIG_SENSORS_ADM1025 is not set
811# CONFIG_SENSORS_ADM1026 is not set
812# CONFIG_SENSORS_ADM1029 is not set
813# CONFIG_SENSORS_ADM1031 is not set
814# CONFIG_SENSORS_ADM9240 is not set
815# CONFIG_SENSORS_ADT7470 is not set
816# CONFIG_SENSORS_ADT7473 is not set
817# CONFIG_SENSORS_ATXP1 is not set
818# CONFIG_SENSORS_DS1621 is not set
819# CONFIG_SENSORS_F71805F is not set
820# CONFIG_SENSORS_F71882FG is not set
821# CONFIG_SENSORS_F75375S is not set
822# CONFIG_SENSORS_GL518SM is not set
823# CONFIG_SENSORS_GL520SM is not set
824# CONFIG_SENSORS_IT87 is not set
825# CONFIG_SENSORS_LM63 is not set
826# CONFIG_SENSORS_LM70 is not set
827# CONFIG_SENSORS_LM75 is not set
828# CONFIG_SENSORS_LM77 is not set
829# CONFIG_SENSORS_LM78 is not set
830# CONFIG_SENSORS_LM80 is not set
831# CONFIG_SENSORS_LM83 is not set
832# CONFIG_SENSORS_LM85 is not set
833# CONFIG_SENSORS_LM87 is not set
834# CONFIG_SENSORS_LM90 is not set
835# CONFIG_SENSORS_LM92 is not set
836# CONFIG_SENSORS_LM93 is not set
837# CONFIG_SENSORS_MAX1619 is not set
838# CONFIG_SENSORS_MAX6650 is not set
839# CONFIG_SENSORS_PC87360 is not set
840# CONFIG_SENSORS_PC87427 is not set
841# CONFIG_SENSORS_DME1737 is not set
842# CONFIG_SENSORS_SMSC47M1 is not set
843# CONFIG_SENSORS_SMSC47M192 is not set
844# CONFIG_SENSORS_SMSC47B397 is not set
845# CONFIG_SENSORS_ADS7828 is not set
846# CONFIG_SENSORS_THMC50 is not set
847# CONFIG_SENSORS_VT1211 is not set
848# CONFIG_SENSORS_W83781D is not set
849# CONFIG_SENSORS_W83791D is not set
850# CONFIG_SENSORS_W83792D is not set
851# CONFIG_SENSORS_W83793 is not set
852# CONFIG_SENSORS_W83L785TS is not set
853# CONFIG_SENSORS_W83L786NG is not set
854# CONFIG_SENSORS_W83627HF is not set
855# CONFIG_SENSORS_W83627EHF is not set
856# CONFIG_HWMON_DEBUG_CHIP is not set
857# CONFIG_THERMAL is not set
858# CONFIG_THERMAL_HWMON is not set
859CONFIG_WATCHDOG=y
860# CONFIG_WATCHDOG_NOWAYOUT is not set
861
862#
863# Watchdog Device Drivers
864#
865# CONFIG_SOFT_WATCHDOG is not set
866CONFIG_BFIN_WDT=y
867
868#
869# USB-based Watchdog Cards
870#
871# CONFIG_USBPCWATCHDOG is not set
872
873#
874# Sonics Silicon Backplane
875#
876CONFIG_SSB_POSSIBLE=y
877# CONFIG_SSB is not set
878
879#
880# Multifunction device drivers
881#
882# CONFIG_MFD_SM501 is not set
883# CONFIG_HTC_PASIC3 is not set
884
885#
886# Multimedia devices
887#
888
889#
890# Multimedia core support
891#
892# CONFIG_VIDEO_DEV is not set
893# CONFIG_DVB_CORE is not set
894# CONFIG_VIDEO_MEDIA is not set
895
896#
897# Multimedia drivers
898#
899# CONFIG_DAB is not set
900
901#
902# Graphics support
903#
904# CONFIG_VGASTATE is not set
905# CONFIG_VIDEO_OUTPUT_CONTROL is not set
906# CONFIG_FB is not set
907# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
908
909#
910# Display device support
911#
912# CONFIG_DISPLAY_SUPPORT is not set
913
914#
915# Console display driver support
916#
917CONFIG_DUMMY_CONSOLE=y
918
919#
920# Sound
921#
922CONFIG_SOUND=m
923
924#
925# Advanced Linux Sound Architecture
926#
927CONFIG_SND=m
928CONFIG_SND_TIMER=m
929CONFIG_SND_PCM=m
930# CONFIG_SND_SEQUENCER is not set
931CONFIG_SND_OSSEMUL=y
932CONFIG_SND_MIXER_OSS=m
933CONFIG_SND_PCM_OSS=m
934CONFIG_SND_PCM_OSS_PLUGINS=y
935# CONFIG_SND_DYNAMIC_MINORS is not set
936CONFIG_SND_SUPPORT_OLD_API=y
937CONFIG_SND_VERBOSE_PROCFS=y
938# CONFIG_SND_VERBOSE_PRINTK is not set
939# CONFIG_SND_DEBUG is not set
940
941#
942# Generic devices
943#
944# CONFIG_SND_DUMMY is not set
945# CONFIG_SND_MTPAV is not set
946# CONFIG_SND_SERIAL_U16550 is not set
947# CONFIG_SND_MPU401 is not set
948
949#
950# SPI devices
951#
952
953#
954# ALSA Blackfin devices
955#
956# CONFIG_SND_BLACKFIN_AD1836 is not set
957# CONFIG_SND_BFIN_AD73311 is not set
958# CONFIG_SND_BFIN_AD73322 is not set
959
960#
961# USB devices
962#
963# CONFIG_SND_USB_AUDIO is not set
964# CONFIG_SND_USB_CAIAQ is not set
965
966#
967# System on Chip audio support
968#
969CONFIG_SND_SOC=m
970CONFIG_SND_BF5XX_I2S=m
971CONFIG_SND_BF5XX_SOC_SSM2602=m
972# CONFIG_SND_BF5XX_AC97 is not set
973CONFIG_SND_BF5XX_SOC_SPORT=m
974CONFIG_SND_BF5XX_SOC_I2S=m
975CONFIG_SND_BF5XX_SPORT_NUM=0
976
977#
978# ALSA SoC audio for Freescale SOCs
979#
980
981#
982# SoC Audio for the Texas Instruments OMAP
983#
984CONFIG_SND_SOC_SSM2602=m
985
986#
987# Open Sound System
988#
989# CONFIG_SOUND_PRIME is not set
990CONFIG_HID_SUPPORT=y
991CONFIG_HID=y
992# CONFIG_HID_DEBUG is not set
993# CONFIG_HIDRAW is not set
994
995#
996# USB Input Devices
997#
998CONFIG_USB_HID=y
999# CONFIG_USB_HIDINPUT_POWERBOOK is not set
1000# CONFIG_HID_FF is not set
1001# CONFIG_USB_HIDDEV is not set
1002CONFIG_USB_SUPPORT=y
1003CONFIG_USB_ARCH_HAS_HCD=y
1004# CONFIG_USB_ARCH_HAS_OHCI is not set
1005# CONFIG_USB_ARCH_HAS_EHCI is not set
1006CONFIG_USB=y
1007# CONFIG_USB_DEBUG is not set
1008# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
1009
1010#
1011# Miscellaneous USB options
1012#
1013# CONFIG_USB_DEVICEFS is not set
1014CONFIG_USB_DEVICE_CLASS=y
1015# CONFIG_USB_DYNAMIC_MINORS is not set
1016# CONFIG_USB_OTG is not set
1017# CONFIG_USB_OTG_WHITELIST is not set
1018CONFIG_USB_OTG_BLACKLIST_HUB=y
1019
1020#
1021# USB Host Controller Drivers
1022#
1023# CONFIG_USB_C67X00_HCD is not set
1024# CONFIG_USB_ISP116X_HCD is not set
1025# CONFIG_USB_ISP1760_HCD is not set
1026# CONFIG_USB_ISP1362_HCD is not set
1027# CONFIG_USB_SL811_HCD is not set
1028# CONFIG_USB_R8A66597_HCD is not set
1029CONFIG_USB_MUSB_HDRC=y
1030CONFIG_USB_MUSB_SOC=y
1031
1032#
1033# Blackfin high speed USB support
1034#
1035CONFIG_USB_MUSB_HOST=y
1036# CONFIG_USB_MUSB_PERIPHERAL is not set
1037# CONFIG_USB_MUSB_OTG is not set
1038CONFIG_USB_MUSB_HDRC_HCD=y
1039CONFIG_MUSB_PIO_ONLY=y
1040CONFIG_USB_MUSB_LOGLEVEL=0
1041
1042#
1043# USB Device Class drivers
1044#
1045# CONFIG_USB_ACM is not set
1046# CONFIG_USB_PRINTER is not set
1047# CONFIG_USB_WDM is not set
1048
1049#
1050# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1051#
1052
1053#
1054# may also be needed; see USB_STORAGE Help for more information
1055#
1056# CONFIG_USB_LIBUSUAL is not set
1057
1058#
1059# USB Imaging devices
1060#
1061# CONFIG_USB_MDC800 is not set
1062CONFIG_USB_MON=y
1063
1064#
1065# USB port drivers
1066#
1067# CONFIG_USB_SERIAL is not set
1068
1069#
1070# USB Miscellaneous drivers
1071#
1072# CONFIG_USB_EMI62 is not set
1073# CONFIG_USB_EMI26 is not set
1074# CONFIG_USB_ADUTUX is not set
1075# CONFIG_USB_AUERSWALD is not set
1076# CONFIG_USB_RIO500 is not set
1077# CONFIG_USB_LEGOTOWER is not set
1078# CONFIG_USB_LCD is not set
1079# CONFIG_USB_BERRY_CHARGE is not set
1080# CONFIG_USB_LED is not set
1081# CONFIG_USB_CYPRESS_CY7C63 is not set
1082# CONFIG_USB_CYTHERM is not set
1083# CONFIG_USB_PHIDGET is not set
1084# CONFIG_USB_IDMOUSE is not set
1085# CONFIG_USB_FTDI_ELAN is not set
1086# CONFIG_USB_APPLEDISPLAY is not set
1087# CONFIG_USB_SISUSBVGA is not set
1088# CONFIG_USB_LD is not set
1089# CONFIG_USB_TRANCEVIBRATOR is not set
1090# CONFIG_USB_IOWARRIOR is not set
1091# CONFIG_USB_ISIGHTFW is not set
1092# CONFIG_USB_GADGET is not set
1093# CONFIG_MMC is not set
1094# CONFIG_MEMSTICK is not set
1095# CONFIG_NEW_LEDS is not set
1096# CONFIG_ACCESSIBILITY is not set
1097CONFIG_RTC_LIB=y
1098CONFIG_RTC_CLASS=y
1099CONFIG_RTC_HCTOSYS=y
1100CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1101# CONFIG_RTC_DEBUG is not set
1102
1103#
1104# RTC interfaces
1105#
1106CONFIG_RTC_INTF_SYSFS=y
1107CONFIG_RTC_INTF_PROC=y
1108CONFIG_RTC_INTF_DEV=y
1109# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1110# CONFIG_RTC_DRV_TEST is not set
1111
1112#
1113# I2C RTC drivers
1114#
1115# CONFIG_RTC_DRV_DS1307 is not set
1116# CONFIG_RTC_DRV_DS1374 is not set
1117# CONFIG_RTC_DRV_DS1672 is not set
1118# CONFIG_RTC_DRV_MAX6900 is not set
1119# CONFIG_RTC_DRV_RS5C372 is not set
1120# CONFIG_RTC_DRV_ISL1208 is not set
1121# CONFIG_RTC_DRV_X1205 is not set
1122# CONFIG_RTC_DRV_PCF8563 is not set
1123# CONFIG_RTC_DRV_PCF8583 is not set
1124# CONFIG_RTC_DRV_M41T80 is not set
1125# CONFIG_RTC_DRV_S35390A is not set
1126# CONFIG_RTC_DRV_FM3130 is not set
1127
1128#
1129# SPI RTC drivers
1130#
1131# CONFIG_RTC_DRV_MAX6902 is not set
1132# CONFIG_RTC_DRV_R9701 is not set
1133# CONFIG_RTC_DRV_RS5C348 is not set
1134
1135#
1136# Platform RTC drivers
1137#
1138# CONFIG_RTC_DRV_DS1511 is not set
1139# CONFIG_RTC_DRV_DS1553 is not set
1140# CONFIG_RTC_DRV_DS1742 is not set
1141# CONFIG_RTC_DRV_STK17TA8 is not set
1142# CONFIG_RTC_DRV_M48T86 is not set
1143# CONFIG_RTC_DRV_M48T59 is not set
1144# CONFIG_RTC_DRV_V3020 is not set
1145
1146#
1147# on-CPU RTC drivers
1148#
1149CONFIG_RTC_DRV_BFIN=y
1150# CONFIG_UIO is not set
1151
1152#
1153# File systems
1154#
1155# CONFIG_EXT2_FS is not set
1156# CONFIG_EXT3_FS is not set
1157# CONFIG_EXT4DEV_FS is not set
1158# CONFIG_REISERFS_FS is not set
1159# CONFIG_JFS_FS is not set
1160# CONFIG_FS_POSIX_ACL is not set
1161# CONFIG_XFS_FS is not set
1162# CONFIG_OCFS2_FS is not set
1163# CONFIG_DNOTIFY is not set
1164CONFIG_INOTIFY=y
1165CONFIG_INOTIFY_USER=y
1166# CONFIG_QUOTA is not set
1167# CONFIG_AUTOFS_FS is not set
1168# CONFIG_AUTOFS4_FS is not set
1169# CONFIG_FUSE_FS is not set
1170
1171#
1172# CD-ROM/DVD Filesystems
1173#
1174# CONFIG_ISO9660_FS is not set
1175# CONFIG_UDF_FS is not set
1176
1177#
1178# DOS/FAT/NT Filesystems
1179#
1180# CONFIG_MSDOS_FS is not set
1181# CONFIG_VFAT_FS is not set
1182# CONFIG_NTFS_FS is not set
1183
1184#
1185# Pseudo filesystems
1186#
1187CONFIG_PROC_FS=y
1188CONFIG_PROC_SYSCTL=y
1189CONFIG_SYSFS=y
1190# CONFIG_TMPFS is not set
1191# CONFIG_HUGETLB_PAGE is not set
1192# CONFIG_CONFIGFS_FS is not set
1193
1194#
1195# Miscellaneous filesystems
1196#
1197# CONFIG_ADFS_FS is not set
1198# CONFIG_AFFS_FS is not set
1199# CONFIG_HFS_FS is not set
1200# CONFIG_HFSPLUS_FS is not set
1201# CONFIG_BEFS_FS is not set
1202# CONFIG_BFS_FS is not set
1203# CONFIG_EFS_FS is not set
1204CONFIG_YAFFS_FS=m
1205CONFIG_YAFFS_YAFFS1=y
1206# CONFIG_YAFFS_9BYTE_TAGS is not set
1207# CONFIG_YAFFS_DOES_ECC is not set
1208CONFIG_YAFFS_YAFFS2=y
1209CONFIG_YAFFS_AUTO_YAFFS2=y
1210# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
1211# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
1212# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
1213CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
1214CONFIG_JFFS2_FS=m
1215CONFIG_JFFS2_FS_DEBUG=0
1216CONFIG_JFFS2_FS_WRITEBUFFER=y
1217# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1218# CONFIG_JFFS2_SUMMARY is not set
1219# CONFIG_JFFS2_FS_XATTR is not set
1220# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1221CONFIG_JFFS2_ZLIB=y
1222# CONFIG_JFFS2_LZO is not set
1223CONFIG_JFFS2_RTIME=y
1224# CONFIG_JFFS2_RUBIN is not set
1225# CONFIG_CRAMFS is not set
1226# CONFIG_VXFS_FS is not set
1227# CONFIG_MINIX_FS is not set
1228# CONFIG_HPFS_FS is not set
1229# CONFIG_QNX4FS_FS is not set
1230# CONFIG_ROMFS_FS is not set
1231# CONFIG_SYSV_FS is not set
1232# CONFIG_UFS_FS is not set
1233CONFIG_NETWORK_FILESYSTEMS=y
1234CONFIG_NFS_FS=m
1235CONFIG_NFS_V3=y
1236# CONFIG_NFS_V3_ACL is not set
1237# CONFIG_NFS_V4 is not set
1238# CONFIG_NFSD is not set
1239CONFIG_LOCKD=m
1240CONFIG_LOCKD_V4=y
1241CONFIG_NFS_COMMON=y
1242CONFIG_SUNRPC=m
1243# CONFIG_SUNRPC_BIND34 is not set
1244# CONFIG_RPCSEC_GSS_KRB5 is not set
1245# CONFIG_RPCSEC_GSS_SPKM3 is not set
1246CONFIG_SMB_FS=m
1247# CONFIG_SMB_NLS_DEFAULT is not set
1248# CONFIG_CIFS is not set
1249# CONFIG_NCP_FS is not set
1250# CONFIG_CODA_FS is not set
1251# CONFIG_AFS_FS is not set
1252
1253#
1254# Partition Types
1255#
1256# CONFIG_PARTITION_ADVANCED is not set
1257CONFIG_MSDOS_PARTITION=y
1258CONFIG_NLS=m
1259CONFIG_NLS_DEFAULT="iso8859-1"
1260# CONFIG_NLS_CODEPAGE_437 is not set
1261# CONFIG_NLS_CODEPAGE_737 is not set
1262# CONFIG_NLS_CODEPAGE_775 is not set
1263# CONFIG_NLS_CODEPAGE_850 is not set
1264# CONFIG_NLS_CODEPAGE_852 is not set
1265# CONFIG_NLS_CODEPAGE_855 is not set
1266# CONFIG_NLS_CODEPAGE_857 is not set
1267# CONFIG_NLS_CODEPAGE_860 is not set
1268# CONFIG_NLS_CODEPAGE_861 is not set
1269# CONFIG_NLS_CODEPAGE_862 is not set
1270# CONFIG_NLS_CODEPAGE_863 is not set
1271# CONFIG_NLS_CODEPAGE_864 is not set
1272# CONFIG_NLS_CODEPAGE_865 is not set
1273# CONFIG_NLS_CODEPAGE_866 is not set
1274# CONFIG_NLS_CODEPAGE_869 is not set
1275# CONFIG_NLS_CODEPAGE_936 is not set
1276# CONFIG_NLS_CODEPAGE_950 is not set
1277# CONFIG_NLS_CODEPAGE_932 is not set
1278# CONFIG_NLS_CODEPAGE_949 is not set
1279# CONFIG_NLS_CODEPAGE_874 is not set
1280# CONFIG_NLS_ISO8859_8 is not set
1281# CONFIG_NLS_CODEPAGE_1250 is not set
1282# CONFIG_NLS_CODEPAGE_1251 is not set
1283# CONFIG_NLS_ASCII is not set
1284# CONFIG_NLS_ISO8859_1 is not set
1285# CONFIG_NLS_ISO8859_2 is not set
1286# CONFIG_NLS_ISO8859_3 is not set
1287# CONFIG_NLS_ISO8859_4 is not set
1288# CONFIG_NLS_ISO8859_5 is not set
1289# CONFIG_NLS_ISO8859_6 is not set
1290# CONFIG_NLS_ISO8859_7 is not set
1291# CONFIG_NLS_ISO8859_9 is not set
1292# CONFIG_NLS_ISO8859_13 is not set
1293# CONFIG_NLS_ISO8859_14 is not set
1294# CONFIG_NLS_ISO8859_15 is not set
1295# CONFIG_NLS_KOI8_R is not set
1296# CONFIG_NLS_KOI8_U is not set
1297# CONFIG_NLS_UTF8 is not set
1298# CONFIG_DLM is not set
1299
1300#
1301# Kernel hacking
1302#
1303# CONFIG_PRINTK_TIME is not set
1304CONFIG_ENABLE_WARN_DEPRECATED=y
1305CONFIG_ENABLE_MUST_CHECK=y
1306CONFIG_FRAME_WARN=1024
1307# CONFIG_MAGIC_SYSRQ is not set
1308# CONFIG_UNUSED_SYMBOLS is not set
1309CONFIG_DEBUG_FS=y
1310# CONFIG_HEADERS_CHECK is not set
1311# CONFIG_DEBUG_KERNEL is not set
1312# CONFIG_DEBUG_BUGVERBOSE is not set
1313# CONFIG_SAMPLES is not set
1314CONFIG_DEBUG_MMRS=y
1315CONFIG_DEBUG_HUNT_FOR_ZERO=y
1316CONFIG_DEBUG_BFIN_HWTRACE_ON=y
1317CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
1318# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set
1319# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set
1320CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
1321# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
1322# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
1323CONFIG_EARLY_PRINTK=y
1324CONFIG_CPLB_INFO=y
1325CONFIG_ACCESS_CHECK=y
1326
1327#
1328# Security options
1329#
1330# CONFIG_KEYS is not set
1331CONFIG_SECURITY=y
1332# CONFIG_SECURITY_NETWORK is not set
1333# CONFIG_SECURITY_CAPABILITIES is not set
1334# CONFIG_SECURITY_ROOTPLUG is not set
1335CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
1336CONFIG_CRYPTO=y
1337
1338#
1339# Crypto core or helper
1340#
1341# CONFIG_CRYPTO_MANAGER is not set
1342# CONFIG_CRYPTO_GF128MUL is not set
1343# CONFIG_CRYPTO_NULL is not set
1344# CONFIG_CRYPTO_CRYPTD is not set
1345# CONFIG_CRYPTO_AUTHENC is not set
1346# CONFIG_CRYPTO_TEST is not set
1347
1348#
1349# Authenticated Encryption with Associated Data
1350#
1351# CONFIG_CRYPTO_CCM is not set
1352# CONFIG_CRYPTO_GCM is not set
1353# CONFIG_CRYPTO_SEQIV is not set
1354
1355#
1356# Block modes
1357#
1358# CONFIG_CRYPTO_CBC is not set
1359# CONFIG_CRYPTO_CTR is not set
1360# CONFIG_CRYPTO_CTS is not set
1361# CONFIG_CRYPTO_ECB is not set
1362# CONFIG_CRYPTO_LRW is not set
1363# CONFIG_CRYPTO_PCBC is not set
1364# CONFIG_CRYPTO_XTS is not set
1365
1366#
1367# Hash modes
1368#
1369# CONFIG_CRYPTO_HMAC is not set
1370# CONFIG_CRYPTO_XCBC is not set
1371
1372#
1373# Digest
1374#
1375# CONFIG_CRYPTO_CRC32C is not set
1376# CONFIG_CRYPTO_MD4 is not set
1377# CONFIG_CRYPTO_MD5 is not set
1378# CONFIG_CRYPTO_MICHAEL_MIC is not set
1379# CONFIG_CRYPTO_SHA1 is not set
1380# CONFIG_CRYPTO_SHA256 is not set
1381# CONFIG_CRYPTO_SHA512 is not set
1382# CONFIG_CRYPTO_TGR192 is not set
1383# CONFIG_CRYPTO_WP512 is not set
1384
1385#
1386# Ciphers
1387#
1388# CONFIG_CRYPTO_AES is not set
1389# CONFIG_CRYPTO_ANUBIS is not set
1390# CONFIG_CRYPTO_ARC4 is not set
1391# CONFIG_CRYPTO_BLOWFISH is not set
1392# CONFIG_CRYPTO_CAMELLIA is not set
1393# CONFIG_CRYPTO_CAST5 is not set
1394# CONFIG_CRYPTO_CAST6 is not set
1395# CONFIG_CRYPTO_DES is not set
1396# CONFIG_CRYPTO_FCRYPT is not set
1397# CONFIG_CRYPTO_KHAZAD is not set
1398# CONFIG_CRYPTO_SALSA20 is not set
1399# CONFIG_CRYPTO_SEED is not set
1400# CONFIG_CRYPTO_SERPENT is not set
1401# CONFIG_CRYPTO_TEA is not set
1402# CONFIG_CRYPTO_TWOFISH is not set
1403
1404#
1405# Compression
1406#
1407# CONFIG_CRYPTO_DEFLATE is not set
1408# CONFIG_CRYPTO_LZO is not set
1409CONFIG_CRYPTO_HW=y
1410
1411#
1412# Library routines
1413#
1414CONFIG_BITREVERSE=y
1415# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1416CONFIG_CRC_CCITT=m
1417# CONFIG_CRC16 is not set
1418# CONFIG_CRC_ITU_T is not set
1419CONFIG_CRC32=y
1420# CONFIG_CRC7 is not set
1421# CONFIG_LIBCRC32C is not set
1422CONFIG_ZLIB_INFLATE=y
1423CONFIG_ZLIB_DEFLATE=m
1424CONFIG_PLIST=y
1425CONFIG_HAS_IOMEM=y
1426CONFIG_HAS_IOPORT=y
1427CONFIG_HAS_DMA=y
diff --git a/arch/blackfin/configs/H8606_defconfig b/arch/blackfin/configs/H8606_defconfig
index ba0bee90b7e1..1fc31f1b762b 100644
--- a/arch/blackfin/configs/H8606_defconfig
+++ b/arch/blackfin/configs/H8606_defconfig
@@ -1,6 +1,6 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.22.12 3# Linux kernel version: 2.6.22.14
4# 4#
5# CONFIG_MMU is not set 5# CONFIG_MMU is not set
6# CONFIG_FPU is not set 6# CONFIG_FPU is not set
@@ -192,7 +192,7 @@ CONFIG_CLKIN_HZ=25000000
192# CONFIG_BFIN_KERNEL_CLOCK is not set 192# CONFIG_BFIN_KERNEL_CLOCK is not set
193CONFIG_MAX_VCO_HZ=400000000 193CONFIG_MAX_VCO_HZ=400000000
194CONFIG_MIN_VCO_HZ=50000000 194CONFIG_MIN_VCO_HZ=50000000
195CONFIG_MAX_SCLK_HZ=133000000 195CONFIG_MAX_SCLK_HZ=133333333
196CONFIG_MIN_SCLK_HZ=27000000 196CONFIG_MIN_SCLK_HZ=27000000
197 197
198# 198#
@@ -516,7 +516,7 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
516# 516#
517# CONFIG_MTD_DATAFLASH is not set 517# CONFIG_MTD_DATAFLASH is not set
518CONFIG_MTD_M25P80=y 518CONFIG_MTD_M25P80=y
519CONFIG_M25PXX_USE_FAST_READ=y 519# CONFIG_M25PXX_USE_FAST_READ is not set
520# CONFIG_MTD_SLRAM is not set 520# CONFIG_MTD_SLRAM is not set
521# CONFIG_MTD_PHRAM is not set 521# CONFIG_MTD_PHRAM is not set
522# CONFIG_MTD_MTDRAM is not set 522# CONFIG_MTD_MTDRAM is not set
@@ -635,25 +635,25 @@ CONFIG_INPUT=y
635# CONFIG_INPUT_MOUSEDEV is not set 635# CONFIG_INPUT_MOUSEDEV is not set
636# CONFIG_INPUT_JOYDEV is not set 636# CONFIG_INPUT_JOYDEV is not set
637# CONFIG_INPUT_TSDEV is not set 637# CONFIG_INPUT_TSDEV is not set
638CONFIG_INPUT_EVDEV=m 638CONFIG_INPUT_EVDEV=y
639# CONFIG_INPUT_EVBUG is not set 639# CONFIG_INPUT_EVBUG is not set
640 640
641# 641#
642# Input Device Drivers 642# Input Device Drivers
643# 643#
644# CONFIG_INPUT_KEYBOARD is not set 644CONFIG_INPUT_KEYBOARD=y
645# CONFIG_KEYBOARD_ATKBD is not set
646# CONFIG_KEYBOARD_SUNKBD is not set
647# CONFIG_KEYBOARD_LKKBD is not set
648# CONFIG_KEYBOARD_XTKBD is not set
649# CONFIG_KEYBOARD_NEWTON is not set
650# CONFIG_KEYBOARD_STOWAWAY is not set
651CONFIG_KEYBOARD_GPIO=y
645# CONFIG_INPUT_MOUSE is not set 652# CONFIG_INPUT_MOUSE is not set
646# CONFIG_INPUT_JOYSTICK is not set 653# CONFIG_INPUT_JOYSTICK is not set
647# CONFIG_INPUT_TABLET is not set 654# CONFIG_INPUT_TABLET is not set
648# CONFIG_INPUT_TOUCHSCREEN is not set 655# CONFIG_INPUT_TOUCHSCREEN is not set
649CONFIG_INPUT_MISC=y 656# CONFIG_INPUT_MISC is not set
650# CONFIG_INPUT_ATI_REMOTE is not set
651# CONFIG_INPUT_ATI_REMOTE2 is not set
652# CONFIG_INPUT_KEYSPAN_REMOTE is not set
653# CONFIG_INPUT_POWERMATE is not set
654# CONFIG_INPUT_YEALINK is not set
655# CONFIG_INPUT_UINPUT is not set
656# CONFIG_BF53X_PFBUTTONS is not set
657 657
658# 658#
659# Hardware I/O ports 659# Hardware I/O ports
@@ -681,7 +681,15 @@ CONFIG_BFIN_TIMER_LATENCY=y
681# 681#
682# Serial drivers 682# Serial drivers
683# 683#
684# CONFIG_SERIAL_8250 is not set 684CONFIG_SERIAL_8250=y
685# CONFIG_SERIAL_8250_CONSOLE is not set
686CONFIG_SERIAL_8250_NR_UARTS=4
687CONFIG_SERIAL_8250_RUNTIME_UARTS=4
688CONFIG_SERIAL_8250_EXTENDED=y
689# CONFIG_SERIAL_8250_MANY_PORTS is not set
690CONFIG_SERIAL_8250_SHARE_IRQ=y
691# CONFIG_SERIAL_8250_DETECT_IRQ is not set
692# CONFIG_SERIAL_8250_RSA is not set
685 693
686# 694#
687# Non-8250 serial port support 695# Non-8250 serial port support
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h
index 7ba70de66f2b..56dcb0a2d244 100644
--- a/arch/blackfin/include/asm/bfin-global.h
+++ b/arch/blackfin/include/asm/bfin-global.h
@@ -63,7 +63,6 @@ extern void bfin_dcache_init(void);
63extern void init_exception_vectors(void); 63extern void init_exception_vectors(void);
64extern void program_IAR(void); 64extern void program_IAR(void);
65 65
66extern void bfin_reset(void);
67extern asmlinkage void lower_to_irq14(void); 66extern asmlinkage void lower_to_irq14(void);
68extern asmlinkage void bfin_return_from_exception(void); 67extern asmlinkage void bfin_return_from_exception(void);
69extern asmlinkage void evt14_softirq(void); 68extern asmlinkage void evt14_softirq(void);
@@ -92,6 +91,8 @@ extern int sram_free(const void*);
92extern void *sram_alloc_with_lsl(size_t, unsigned long); 91extern void *sram_alloc_with_lsl(size_t, unsigned long);
93extern int sram_free_with_lsl(const void*); 92extern int sram_free_with_lsl(const void*);
94 93
94extern void *isram_memcpy(void *dest, const void *src, size_t n);
95
95extern const char bfin_board_name[]; 96extern const char bfin_board_name[];
96 97
97extern unsigned long bfin_sic_iwr[]; 98extern unsigned long bfin_sic_iwr[];
@@ -104,7 +105,7 @@ extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[],
104 _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], _sbss_l2[], 105 _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], _sbss_l2[],
105 _ebss_l2[], _l2_lma_start[]; 106 _ebss_l2[], _l2_lma_start[];
106 107
107/* only used when CONFIG_MTD_UCLINUX */ 108/* only used when MTD_UCLINUX */
108extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size; 109extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size;
109 110
110#ifdef CONFIG_BFIN_ICACHE_LOCK 111#ifdef CONFIG_BFIN_ICACHE_LOCK
diff --git a/arch/blackfin/include/asm/bfrom.h b/arch/blackfin/include/asm/bfrom.h
new file mode 100644
index 000000000000..cfe8024c3b2f
--- /dev/null
+++ b/arch/blackfin/include/asm/bfrom.h
@@ -0,0 +1,85 @@
1/* Blackfin on-chip ROM API
2 *
3 * Copyright 2008 Analog Devices Inc.
4 *
5 * Licensed under the GPL-2 or later.
6 */
7
8#ifndef __BFROM_H__
9#define __BFROM_H__
10
11#include <linux/types.h>
12
13/* Possible syscontrol action flags */
14#define SYSCTRL_READ 0x00000000 /* read registers */
15#define SYSCTRL_WRITE 0x00000001 /* write registers */
16#define SYSCTRL_SYSRESET 0x00000002 /* perform system reset */
17#define SYSCTRL_CORERESET 0x00000004 /* perform core reset */
18#define SYSCTRL_SOFTRESET 0x00000006 /* perform core and system reset */
19#define SYSCTRL_VRCTL 0x00000010 /* read/write VR_CTL register */
20#define SYSCTRL_EXTVOLTAGE 0x00000020 /* VDDINT supplied externally */
21#define SYSCTRL_INTVOLTAGE 0x00000000 /* VDDINT generated by on-chip regulator */
22#define SYSCTRL_OTPVOLTAGE 0x00000040 /* For Factory Purposes Only */
23#define SYSCTRL_PLLCTL 0x00000100 /* read/write PLL_CTL register */
24#define SYSCTRL_PLLDIV 0x00000200 /* read/write PLL_DIV register */
25#define SYSCTRL_LOCKCNT 0x00000400 /* read/write PLL_LOCKCNT register */
26#define SYSCTRL_PLLSTAT 0x00000800 /* read/write PLL_STAT register */
27
28typedef struct ADI_SYSCTRL_VALUES {
29 uint16_t uwVrCtl;
30 uint16_t uwPllCtl;
31 uint16_t uwPllDiv;
32 uint16_t uwPllLockCnt;
33 uint16_t uwPllStat;
34} ADI_SYSCTRL_VALUES;
35
36static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)0xEF000038;
37
38/* We need a dedicated function since we need to screw with the stack pointer
39 * when resetting. The on-chip ROM will save/restore registers on the stack
40 * when doing a system reset, so the stack cannot be outside of the chip.
41 */
42__attribute__((__noreturn__))
43static inline void bfrom_SoftReset(void *new_stack)
44{
45 while (1)
46 __asm__ __volatile__(
47 "sp = %[stack];"
48 "jump (%[bfrom_syscontrol]);"
49 : : [bfrom_syscontrol] "p"(bfrom_SysControl),
50 "q0"(SYSCTRL_SOFTRESET),
51 "q1"(0),
52 "q2"(NULL),
53 [stack] "p"(new_stack)
54 );
55}
56
57/* OTP Functions */
58static uint32_t (* const bfrom_OtpCommand)(uint32_t command, uint32_t value) = (void *)0xEF000018;
59static uint32_t (* const bfrom_OtpRead)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001A;
60static uint32_t (* const bfrom_OtpWrite)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001C;
61
62/* otp command: defines for "command" */
63#define OTP_INIT 0x00000001
64#define OTP_CLOSE 0x00000002
65
66/* otp read/write: defines for "flags" */
67#define OTP_LOWER_HALF 0x00000000 /* select upper/lower 64-bit half (bit 0) */
68#define OTP_UPPER_HALF 0x00000001
69#define OTP_NO_ECC 0x00000010 /* do not use ECC */
70#define OTP_LOCK 0x00000020 /* sets page protection bit for page */
71#define OTP_CHECK_FOR_PREV_WRITE 0x00000080
72
73/* Return values for all functions */
74#define OTP_SUCCESS 0x00000000
75#define OTP_MASTER_ERROR 0x001
76#define OTP_WRITE_ERROR 0x003
77#define OTP_READ_ERROR 0x005
78#define OTP_ACC_VIO_ERROR 0x009
79#define OTP_DATA_MULT_ERROR 0x011
80#define OTP_ECC_MULT_ERROR 0x021
81#define OTP_PREV_WR_ERROR 0x041
82#define OTP_DATA_SB_WARN 0x100
83#define OTP_ECC_SB_WARN 0x200
84
85#endif
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
index d81a77545a04..5ef9e35e9c3b 100644
--- a/arch/blackfin/include/asm/cacheflush.h
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -30,8 +30,6 @@
30#ifndef _BLACKFIN_CACHEFLUSH_H 30#ifndef _BLACKFIN_CACHEFLUSH_H
31#define _BLACKFIN_CACHEFLUSH_H 31#define _BLACKFIN_CACHEFLUSH_H
32 32
33#include <asm/cplb.h>
34
35extern void blackfin_icache_dcache_flush_range(unsigned int, unsigned int); 33extern void blackfin_icache_dcache_flush_range(unsigned int, unsigned int);
36extern void blackfin_icache_flush_range(unsigned int, unsigned int); 34extern void blackfin_icache_flush_range(unsigned int, unsigned int);
37extern void blackfin_dcache_flush_range(unsigned int, unsigned int); 35extern void blackfin_dcache_flush_range(unsigned int, unsigned int);
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
index 05d6f05fb748..9e8b4035fcec 100644
--- a/arch/blackfin/include/asm/cplb.h
+++ b/arch/blackfin/include/asm/cplb.h
@@ -55,7 +55,13 @@
55#endif 55#endif
56 56
57#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON) 57#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON)
58#define L2_MEMORY (CPLB_COMMON) 58#ifdef CONFIG_BFIN_L2_CACHEABLE
59#define L2_IMEMORY (SDRAM_IGENERIC)
60#define L2_DMEMORY (SDRAM_DGENERIC)
61#else
62#define L2_IMEMORY (CPLB_COMMON)
63#define L2_DMEMORY (CPLB_COMMON)
64#endif
59#define SDRAM_DNON_CHBL (CPLB_COMMON) 65#define SDRAM_DNON_CHBL (CPLB_COMMON)
60#define SDRAM_EBIU (CPLB_COMMON) 66#define SDRAM_EBIU (CPLB_COMMON)
61#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) 67#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
diff --git a/arch/blackfin/include/asm/cplbinit.h b/arch/blackfin/include/asm/cplbinit.h
index 0eb1c1b685a7..d179b747ff03 100644
--- a/arch/blackfin/include/asm/cplbinit.h
+++ b/arch/blackfin/include/asm/cplbinit.h
@@ -90,6 +90,20 @@ extern u_long dpdt_swapcount_table[];
90extern unsigned long reserved_mem_dcache_on; 90extern unsigned long reserved_mem_dcache_on;
91extern unsigned long reserved_mem_icache_on; 91extern unsigned long reserved_mem_icache_on;
92 92
93extern void generate_cpl_tables(void); 93extern void generate_cplb_tables(void);
94
95static inline int bfin_addr_dcachable(unsigned long addr)
96{
97#ifdef CONFIG_BFIN_DCACHE
98 if (addr < (_ramend - DMA_UNCACHED_REGION))
99 return 1;
100#endif
101
102 if (reserved_mem_dcache_on &&
103 addr >= _ramend && addr < physical_mem_end)
104 return 1;
105
106 return 0;
107}
94 108
95#endif 109#endif
diff --git a/arch/blackfin/include/asm/cpumask.h b/arch/blackfin/include/asm/cpumask.h
deleted file mode 100644
index b20a8e9012cb..000000000000
--- a/arch/blackfin/include/asm/cpumask.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ASM_BLACKFIN_CPUMASK_H
2#define _ASM_BLACKFIN_CPUMASK_H
3
4#include <asm-generic/cpumask.h>
5
6#endif /* _ASM_BLACKFIN_CPUMASK_H */
diff --git a/arch/blackfin/include/asm/dma-mapping.h b/arch/blackfin/include/asm/dma-mapping.h
index 1a13c2fc3667..ede748d67efd 100644
--- a/arch/blackfin/include/asm/dma-mapping.h
+++ b/arch/blackfin/include/asm/dma-mapping.h
@@ -80,4 +80,15 @@ extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
80extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg, 80extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
81 int nhwentries, enum dma_data_direction direction); 81 int nhwentries, enum dma_data_direction direction);
82 82
83static inline void dma_sync_single_for_cpu(struct device *dev,
84 dma_addr_t handle, size_t size,
85 enum dma_data_direction dir)
86{
87}
88
89static inline void dma_sync_single_for_device(struct device *dev,
90 dma_addr_t handle, size_t size,
91 enum dma_data_direction dir)
92{
93}
83#endif /* _BLACKFIN_DMA_MAPPING_H */ 94#endif /* _BLACKFIN_DMA_MAPPING_H */
diff --git a/arch/blackfin/include/asm/kgdb.h b/arch/blackfin/include/asm/kgdb.h
index 0f73847fd6bc..26ebac6646d8 100644
--- a/arch/blackfin/include/asm/kgdb.h
+++ b/arch/blackfin/include/asm/kgdb.h
@@ -124,9 +124,16 @@ enum regnames {
124/* Number of bytes of registers. */ 124/* Number of bytes of registers. */
125#define NUMREGBYTES BFIN_NUM_REGS*4 125#define NUMREGBYTES BFIN_NUM_REGS*4
126 126
127#define BREAKPOINT() asm(" EXCPT 2;"); 127static inline void arch_kgdb_breakpoint(void)
128#define BREAK_INSTR_SIZE 2 128{
129#define HW_BREAKPOINT_NUM 6 129 asm(" EXCPT 2;");
130}
131#define BREAK_INSTR_SIZE 2
132#define CACHE_FLUSH_IS_SAFE 1
133#define HW_INST_WATCHPOINT_NUM 6
134#define HW_WATCHPOINT_NUM 8
135#define TYPE_INST_WATCHPOINT 0
136#define TYPE_DATA_WATCHPOINT 1
130 137
131/* Instruction watchpoint address control register bits mask */ 138/* Instruction watchpoint address control register bits mask */
132#define WPPWR 0x1 139#define WPPWR 0x1
@@ -163,10 +170,11 @@ enum regnames {
163#define WPDAEN1 0x8 170#define WPDAEN1 0x8
164#define WPDCNTEN0 0x10 171#define WPDCNTEN0 0x10
165#define WPDCNTEN1 0x20 172#define WPDCNTEN1 0x20
173
166#define WPDSRC0 0xc0 174#define WPDSRC0 0xc0
167#define WPDACC0 0x300 175#define WPDACC0_OFFSET 8
168#define WPDSRC1 0xc00 176#define WPDSRC1 0xc00
169#define WPDACC1 0x3000 177#define WPDACC1_OFFSET 12
170 178
171/* Watchpoint status register bits mask */ 179/* Watchpoint status register bits mask */
172#define STATIA0 0x1 180#define STATIA0 0x1
@@ -178,7 +186,4 @@ enum regnames {
178#define STATDA0 0x40 186#define STATDA0 0x40
179#define STATDA1 0x80 187#define STATDA1 0x80
180 188
181extern void kgdb_print(const char *fmt, ...);
182extern void init_kgdb_uart(void);
183
184#endif 189#endif
diff --git a/arch/blackfin/include/asm/mmu_context.h b/arch/blackfin/include/asm/mmu_context.h
index 8529552a981f..35593dda2a4d 100644
--- a/arch/blackfin/include/asm/mmu_context.h
+++ b/arch/blackfin/include/asm/mmu_context.h
@@ -45,49 +45,12 @@ extern unsigned long l1_stack_len;
45extern int l1sram_free(const void*); 45extern int l1sram_free(const void*);
46extern void *l1sram_alloc_max(void*); 46extern void *l1sram_alloc_max(void*);
47 47
48static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
49{
50}
51
52/* Called when creating a new context during fork() or execve(). */
53static inline int
54init_new_context(struct task_struct *tsk, struct mm_struct *mm)
55{
56#ifdef CONFIG_MPU
57 unsigned long p = __get_free_pages(GFP_KERNEL, page_mask_order);
58 mm->context.page_rwx_mask = (unsigned long *)p;
59 memset(mm->context.page_rwx_mask, 0,
60 page_mask_nelts * 3 * sizeof(long));
61#endif
62 return 0;
63}
64
65static inline void free_l1stack(void) 48static inline void free_l1stack(void)
66{ 49{
67 nr_l1stack_tasks--; 50 nr_l1stack_tasks--;
68 if (nr_l1stack_tasks == 0) 51 if (nr_l1stack_tasks == 0)
69 l1sram_free(l1_stack_base); 52 l1sram_free(l1_stack_base);
70} 53}
71static inline void destroy_context(struct mm_struct *mm)
72{
73 struct sram_list_struct *tmp;
74
75 if (current_l1_stack_save == mm->context.l1_stack_save)
76 current_l1_stack_save = NULL;
77 if (mm->context.l1_stack_save)
78 free_l1stack();
79
80 while ((tmp = mm->context.sram_list)) {
81 mm->context.sram_list = tmp->next;
82 sram_free(tmp->addr);
83 kfree(tmp);
84 }
85#ifdef CONFIG_MPU
86 if (current_rwx_mask == mm->context.page_rwx_mask)
87 current_rwx_mask = NULL;
88 free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order);
89#endif
90}
91 54
92static inline unsigned long 55static inline unsigned long
93alloc_l1stack(unsigned long length, unsigned long *stack_base) 56alloc_l1stack(unsigned long length, unsigned long *stack_base)
@@ -134,6 +97,7 @@ static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_m
134 } 97 }
135#endif 98#endif
136 99
100#ifdef CONFIG_APP_STACK_L1
137 /* L1 stack switching. */ 101 /* L1 stack switching. */
138 if (!next_mm->context.l1_stack_save) 102 if (!next_mm->context.l1_stack_save)
139 return; 103 return;
@@ -144,6 +108,7 @@ static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_m
144 } 108 }
145 current_l1_stack_save = next_mm->context.l1_stack_save; 109 current_l1_stack_save = next_mm->context.l1_stack_save;
146 memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len); 110 memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
111#endif
147} 112}
148 113
149#ifdef CONFIG_MPU 114#ifdef CONFIG_MPU
@@ -180,4 +145,44 @@ static inline void update_protections(struct mm_struct *mm)
180} 145}
181#endif 146#endif
182 147
148static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
149{
150}
151
152/* Called when creating a new context during fork() or execve(). */
153static inline int
154init_new_context(struct task_struct *tsk, struct mm_struct *mm)
155{
156#ifdef CONFIG_MPU
157 unsigned long p = __get_free_pages(GFP_KERNEL, page_mask_order);
158 mm->context.page_rwx_mask = (unsigned long *)p;
159 memset(mm->context.page_rwx_mask, 0,
160 page_mask_nelts * 3 * sizeof(long));
161#endif
162 return 0;
163}
164
165static inline void destroy_context(struct mm_struct *mm)
166{
167 struct sram_list_struct *tmp;
168
169#ifdef CONFIG_APP_STACK_L1
170 if (current_l1_stack_save == mm->context.l1_stack_save)
171 current_l1_stack_save = 0;
172 if (mm->context.l1_stack_save)
173 free_l1stack();
174#endif
175
176 while ((tmp = mm->context.sram_list)) {
177 mm->context.sram_list = tmp->next;
178 sram_free(tmp->addr);
179 kfree(tmp);
180 }
181#ifdef CONFIG_MPU
182 if (current_rwx_mask == mm->context.page_rwx_mask)
183 current_rwx_mask = NULL;
184 free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order);
185#endif
186}
187
183#endif 188#endif
diff --git a/arch/blackfin/include/asm/processor.h b/arch/blackfin/include/asm/processor.h
index 6f3995b119d8..e3e9b41fa8db 100644
--- a/arch/blackfin/include/asm/processor.h
+++ b/arch/blackfin/include/asm/processor.h
@@ -134,6 +134,12 @@ static inline uint32_t __pure bfin_revid(void)
134 return revid; 134 return revid;
135} 135}
136 136
137static inline uint16_t __pure bfin_cpuid(void)
138{
139 return (bfin_read_CHIPID() & CHIPID_FAMILY) >> 12;
140
141}
142
137static inline uint32_t __pure bfin_compiled_revid(void) 143static inline uint32_t __pure bfin_compiled_revid(void)
138{ 144{
139#if defined(CONFIG_BF_REV_0_0) 145#if defined(CONFIG_BF_REV_0_0)
diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h
index a45a80e54adc..e3f086dc7268 100644
--- a/arch/blackfin/include/asm/ptrace.h
+++ b/arch/blackfin/include/asm/ptrace.h
@@ -158,6 +158,8 @@ extern void show_regs(struct pt_regs *);
158#define PT_SEQSTAT 8 158#define PT_SEQSTAT 8
159#define PT_IPEND 4 159#define PT_IPEND 4
160 160
161#define PT_ORIG_R0 208
162#define PT_ORIG_P0 212
161#define PT_SYSCFG 216 163#define PT_SYSCFG 216
162#define PT_TEXT_ADDR 220 164#define PT_TEXT_ADDR 220
163#define PT_TEXT_END_ADDR 224 165#define PT_TEXT_END_ADDR 224
diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h
index f0e5f940d9ca..34f7295fb070 100644
--- a/arch/blackfin/include/asm/traps.h
+++ b/arch/blackfin/include/asm/traps.h
@@ -59,6 +59,9 @@
59 level " or a 16-bit register is accessed with a 32-bit instruction.\n" 59 level " or a 16-bit register is accessed with a 32-bit instruction.\n"
60#define HWC_x3(level) \ 60#define HWC_x3(level) \
61 "External Memory Addressing Error\n" 61 "External Memory Addressing Error\n"
62#define EXC_0x04(level) \
63 "Unimplmented exception occured\n" \
64 level " - Maybe you forgot to install a custom exception handler?\n"
62#define HWC_x12(level) \ 65#define HWC_x12(level) \
63 "Performance Monitor Overflow\n" 66 "Performance Monitor Overflow\n"
64#define HWC_x18(level) \ 67#define HWC_x18(level) \
@@ -84,7 +87,7 @@
84 level " a particular processor implementation.\n" 87 level " a particular processor implementation.\n"
85#define EXC_0x22(level) \ 88#define EXC_0x22(level) \
86 "Illegal instruction combination\n" \ 89 "Illegal instruction combination\n" \
87 level " - See section for multi-issue rules in the ADSP-BF53x Blackfin\n" \ 90 level " - See section for multi-issue rules in the Blackfin\n" \
88 level " Processor Instruction Set Reference.\n" 91 level " Processor Instruction Set Reference.\n"
89#define EXC_0x23(level) \ 92#define EXC_0x23(level) \
90 "Data access CPLB protection violation\n" \ 93 "Data access CPLB protection violation\n" \
diff --git a/arch/blackfin/kernel/asm-offsets.c b/arch/blackfin/kernel/asm-offsets.c
index 881afe9082c7..9bb85dd5ccb3 100644
--- a/arch/blackfin/kernel/asm-offsets.c
+++ b/arch/blackfin/kernel/asm-offsets.c
@@ -60,6 +60,7 @@ int main(void)
60 DEFINE(KERNEL_STACK_SIZE, THREAD_SIZE); 60 DEFINE(KERNEL_STACK_SIZE, THREAD_SIZE);
61 61
62 /* offsets into the pt_regs */ 62 /* offsets into the pt_regs */
63 DEFINE(PT_ORIG_R0, offsetof(struct pt_regs, orig_r0));
63 DEFINE(PT_ORIG_P0, offsetof(struct pt_regs, orig_p0)); 64 DEFINE(PT_ORIG_P0, offsetof(struct pt_regs, orig_p0));
64 DEFINE(PT_ORIG_PC, offsetof(struct pt_regs, orig_pc)); 65 DEFINE(PT_ORIG_PC, offsetof(struct pt_regs, orig_pc));
65 DEFINE(PT_R0, offsetof(struct pt_regs, r0)); 66 DEFINE(PT_R0, offsetof(struct pt_regs, r0));
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index ecbd141e0ef2..6e08f425bb44 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -231,14 +231,14 @@ inline int check_gpio(unsigned gpio)
231} 231}
232#endif 232#endif
233 233
234void gpio_error(unsigned gpio) 234static void gpio_error(unsigned gpio)
235{ 235{
236 printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio); 236 printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio);
237} 237}
238 238
239static void set_label(unsigned short ident, const char *label) 239static void set_label(unsigned short ident, const char *label)
240{ 240{
241 if (label && str_ident) { 241 if (label) {
242 strncpy(str_ident[ident].name, label, 242 strncpy(str_ident[ident].name, label,
243 RESOURCE_LABEL_SIZE); 243 RESOURCE_LABEL_SIZE);
244 str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0; 244 str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
@@ -247,9 +247,6 @@ static void set_label(unsigned short ident, const char *label)
247 247
248static char *get_label(unsigned short ident) 248static char *get_label(unsigned short ident)
249{ 249{
250 if (!str_ident)
251 return "UNKNOWN";
252
253 return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN"); 250 return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN");
254} 251}
255 252
@@ -260,7 +257,7 @@ static int cmp_label(unsigned short ident, const char *label)
260 printk(KERN_ERR "Please provide none-null label\n"); 257 printk(KERN_ERR "Please provide none-null label\n");
261 } 258 }
262 259
263 if (label && str_ident) 260 if (label)
264 return strncmp(str_ident[ident].name, 261 return strncmp(str_ident[ident].name,
265 label, strlen(label)); 262 label, strlen(label));
266 else 263 else
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
index 48060105346a..55af729f8495 100644
--- a/arch/blackfin/kernel/cplb-mpu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
@@ -36,7 +36,7 @@ struct cplb_entry dcplb_tbl[MAX_CPLBS];
36int first_switched_icplb, first_switched_dcplb; 36int first_switched_icplb, first_switched_dcplb;
37int first_mask_dcplb; 37int first_mask_dcplb;
38 38
39void __init generate_cpl_tables(void) 39void __init generate_cplb_tables(void)
40{ 40{
41 int i_d, i_i; 41 int i_d, i_i;
42 unsigned long addr; 42 unsigned long addr;
@@ -83,8 +83,18 @@ void __init generate_cpl_tables(void)
83 dcplb_tbl[i_d].addr = L1_DATA_A_START; 83 dcplb_tbl[i_d].addr = L1_DATA_A_START;
84 dcplb_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; 84 dcplb_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
85#endif 85#endif
86#if L1_CODE_LENGTH > 0
86 icplb_tbl[i_i].addr = L1_CODE_START; 87 icplb_tbl[i_i].addr = L1_CODE_START;
87 icplb_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; 88 icplb_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
89#endif
90
91 /* Cover L2 memory */
92#if L2_LENGTH > 0
93 dcplb_tbl[i_d].addr = L2_START;
94 dcplb_tbl[i_d++].data = L2_DMEMORY | PAGE_SIZE_1MB;
95 icplb_tbl[i_i].addr = L2_START;
96 icplb_tbl[i_i++].data = L2_IMEMORY | PAGE_SIZE_1MB;
97#endif
88 98
89 first_mask_dcplb = i_d; 99 first_mask_dcplb = i_d;
90 first_switched_dcplb = i_d + (1 << page_mask_order); 100 first_switched_dcplb = i_d + (1 << page_mask_order);
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
index 99f2831e2964..5094677fd09e 100644
--- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
@@ -322,9 +322,11 @@ int cplb_hdr(int seqstat, struct pt_regs *regs)
322void flush_switched_cplbs(void) 322void flush_switched_cplbs(void)
323{ 323{
324 int i; 324 int i;
325 unsigned long flags;
325 326
326 nr_cplb_flush++; 327 nr_cplb_flush++;
327 328
329 local_irq_save(flags);
328 disable_icplb(); 330 disable_icplb();
329 for (i = first_switched_icplb; i < MAX_CPLBS; i++) { 331 for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
330 icplb_tbl[i].data = 0; 332 icplb_tbl[i].data = 0;
@@ -338,6 +340,8 @@ void flush_switched_cplbs(void)
338 bfin_write32(DCPLB_DATA0 + i * 4, 0); 340 bfin_write32(DCPLB_DATA0 + i * 4, 0);
339 } 341 }
340 enable_dcplb(); 342 enable_dcplb();
343 local_irq_restore(flags);
344
341} 345}
342 346
343void set_mask_dcplbs(unsigned long *masks) 347void set_mask_dcplbs(unsigned long *masks)
@@ -345,10 +349,15 @@ void set_mask_dcplbs(unsigned long *masks)
345 int i; 349 int i;
346 unsigned long addr = (unsigned long)masks; 350 unsigned long addr = (unsigned long)masks;
347 unsigned long d_data; 351 unsigned long d_data;
348 current_rwx_mask = masks; 352 unsigned long flags;
349 353
350 if (!masks) 354 if (!masks) {
355 current_rwx_mask = masks;
351 return; 356 return;
357 }
358
359 local_irq_save(flags);
360 current_rwx_mask = masks;
352 361
353 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; 362 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
354#ifdef CONFIG_BFIN_DCACHE 363#ifdef CONFIG_BFIN_DCACHE
@@ -367,4 +376,5 @@ void set_mask_dcplbs(unsigned long *masks)
367 addr += PAGE_SIZE; 376 addr += PAGE_SIZE;
368 } 377 }
369 enable_dcplb(); 378 enable_dcplb();
379 local_irq_restore(flags);
370} 380}
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index 728f708d3981..301252e84441 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -168,8 +168,8 @@ static struct cplb_desc cplb_data[] = {
168 .end = L2_START + L2_LENGTH, 168 .end = L2_START + L2_LENGTH,
169 .psize = SIZE_1M, 169 .psize = SIZE_1M,
170 .attr = SWITCH_T | I_CPLB | D_CPLB, 170 .attr = SWITCH_T | I_CPLB | D_CPLB,
171 .i_conf = L2_MEMORY, 171 .i_conf = L2_IMEMORY,
172 .d_conf = L2_MEMORY, 172 .d_conf = L2_DMEMORY,
173 .valid = (L2_LENGTH > 0), 173 .valid = (L2_LENGTH > 0),
174 .name = "L2 Memory", 174 .name = "L2 Memory",
175 }, 175 },
@@ -308,7 +308,7 @@ __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
308 } 308 }
309} 309}
310 310
311void __init generate_cpl_tables(void) 311void __init generate_cplb_tables(void)
312{ 312{
313 313
314 u16 i, j, process; 314 u16 i, j, process;
diff --git a/arch/blackfin/kernel/early_printk.c b/arch/blackfin/kernel/early_printk.c
index 60f67f90fe35..1f4e3d2e0901 100644
--- a/arch/blackfin/kernel/early_printk.c
+++ b/arch/blackfin/kernel/early_printk.c
@@ -35,6 +35,9 @@
35extern struct console *bfin_earlyserial_init(unsigned int port, 35extern struct console *bfin_earlyserial_init(unsigned int port,
36 unsigned int cflag); 36 unsigned int cflag);
37#endif 37#endif
38#ifdef CONFIG_BFIN_JTAG_COMM
39extern struct console *bfin_jc_early_init(void);
40#endif
38 41
39static struct console *early_console; 42static struct console *early_console;
40 43
@@ -142,6 +145,15 @@ int __init setup_early_printk(char *buf)
142 early_console = earlyserial_init(buf); 145 early_console = earlyserial_init(buf);
143 } 146 }
144#endif 147#endif
148
149#ifdef CONFIG_BFIN_JTAG_COMM
150 /* Check for Blackfin JTAG */
151 if (!strncmp(buf, "jtag", 4)) {
152 buf += 4;
153 early_console = bfin_jc_early_init();
154 }
155#endif
156
145#ifdef CONFIG_FB 157#ifdef CONFIG_FB
146 /* TODO: add framebuffer console support */ 158 /* TODO: add framebuffer console support */
147#endif 159#endif
diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c
index a1f9641a6425..b795a207742c 100644
--- a/arch/blackfin/kernel/kgdb.c
+++ b/arch/blackfin/kernel/kgdb.c
@@ -1,32 +1,9 @@
1/* 1/*
2 * File: arch/blackfin/kernel/kgdb.c 2 * arch/blackfin/kernel/kgdb.c - Blackfin kgdb pieces
3 * Based on:
4 * Author: Sonic Zhang
5 * 3 *
6 * Created: 4 * Copyright 2005-2008 Analog Devices Inc.
7 * Description:
8 * 5 *
9 * Rev: $Id: kgdb_bfin_linux-2.6.x.patch 4934 2007-02-13 09:32:11Z sonicz $ 6 * Licensed under the GPL-2 or later.
10 *
11 * Modified:
12 * Copyright 2005-2006 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, see the file COPYING, or write
28 * to the Free Software Foundation, Inc.,
29 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 */ 7 */
31 8
32#include <linux/string.h> 9#include <linux/string.h>
@@ -39,24 +16,29 @@
39#include <linux/kgdb.h> 16#include <linux/kgdb.h>
40#include <linux/console.h> 17#include <linux/console.h>
41#include <linux/init.h> 18#include <linux/init.h>
42#include <linux/debugger.h>
43#include <linux/errno.h> 19#include <linux/errno.h>
44#include <linux/irq.h> 20#include <linux/irq.h>
21#include <linux/uaccess.h>
45#include <asm/system.h> 22#include <asm/system.h>
46#include <asm/traps.h> 23#include <asm/traps.h>
47#include <asm/blackfin.h> 24#include <asm/blackfin.h>
25#include <asm/dma.h>
48 26
49/* Put the error code here just in case the user cares. */ 27/* Put the error code here just in case the user cares. */
50int gdb_bf533errcode; 28int gdb_bfin_errcode;
51/* Likewise, the vector number here (since GDB only gets the signal 29/* Likewise, the vector number here (since GDB only gets the signal
52 number through the usual means, and that's not very specific). */ 30 number through the usual means, and that's not very specific). */
53int gdb_bf533vector = -1; 31int gdb_bfin_vector = -1;
54 32
55#if KGDB_MAX_NO_CPUS != 8 33#if KGDB_MAX_NO_CPUS != 8
56#error change the definition of slavecpulocks 34#error change the definition of slavecpulocks
57#endif 35#endif
58 36
59void regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) 37#ifdef CONFIG_BFIN_WDT
38# error "Please unselect blackfin watchdog driver before build KGDB."
39#endif
40
41void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
60{ 42{
61 gdb_regs[BFIN_R0] = regs->r0; 43 gdb_regs[BFIN_R0] = regs->r0;
62 gdb_regs[BFIN_R1] = regs->r1; 44 gdb_regs[BFIN_R1] = regs->r1;
@@ -133,7 +115,7 @@ void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
133 gdb_regs[BFIN_SEQSTAT] = p->thread.seqstat; 115 gdb_regs[BFIN_SEQSTAT] = p->thread.seqstat;
134} 116}
135 117
136void gdb_regs_to_regs(unsigned long *gdb_regs, struct pt_regs *regs) 118void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
137{ 119{
138 regs->r0 = gdb_regs[BFIN_R0]; 120 regs->r0 = gdb_regs[BFIN_R0];
139 regs->r1 = gdb_regs[BFIN_R1]; 121 regs->r1 = gdb_regs[BFIN_R1];
@@ -199,171 +181,208 @@ struct hw_breakpoint {
199 unsigned int dataacc:2; 181 unsigned int dataacc:2;
200 unsigned short count; 182 unsigned short count;
201 unsigned int addr; 183 unsigned int addr;
202} breakinfo[HW_BREAKPOINT_NUM]; 184} breakinfo[HW_WATCHPOINT_NUM];
203 185
204int kgdb_arch_init(void) 186int bfin_set_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
205{
206 debugger_step = 0;
207
208 kgdb_remove_all_hw_break();
209 return 0;
210}
211
212int kgdb_set_hw_break(unsigned long addr)
213{ 187{
214 int breakno; 188 int breakno;
215 for (breakno = 0; breakno < HW_BREAKPOINT_NUM; breakno++) 189 int bfin_type;
216 if (!breakinfo[breakno].occupied) { 190 int dataacc = 0;
191
192 switch (type) {
193 case BP_HARDWARE_BREAKPOINT:
194 bfin_type = TYPE_INST_WATCHPOINT;
195 break;
196 case BP_WRITE_WATCHPOINT:
197 dataacc = 1;
198 bfin_type = TYPE_DATA_WATCHPOINT;
199 break;
200 case BP_READ_WATCHPOINT:
201 dataacc = 2;
202 bfin_type = TYPE_DATA_WATCHPOINT;
203 break;
204 case BP_ACCESS_WATCHPOINT:
205 dataacc = 3;
206 bfin_type = TYPE_DATA_WATCHPOINT;
207 break;
208 default:
209 return -ENOSPC;
210 }
211
212 /* Becasue hardware data watchpoint impelemented in current
213 * Blackfin can not trigger an exception event as the hardware
214 * instrction watchpoint does, we ignaore all data watch point here.
215 * They can be turned on easily after future blackfin design
216 * supports this feature.
217 */
218 for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
219 if (bfin_type == breakinfo[breakno].type
220 && !breakinfo[breakno].occupied) {
217 breakinfo[breakno].occupied = 1; 221 breakinfo[breakno].occupied = 1;
218 breakinfo[breakno].enabled = 1; 222 breakinfo[breakno].enabled = 1;
219 breakinfo[breakno].type = 1;
220 breakinfo[breakno].addr = addr; 223 breakinfo[breakno].addr = addr;
224 breakinfo[breakno].dataacc = dataacc;
225 breakinfo[breakno].count = 0;
221 return 0; 226 return 0;
222 } 227 }
223 228
224 return -ENOSPC; 229 return -ENOSPC;
225} 230}
226 231
227int kgdb_remove_hw_break(unsigned long addr) 232int bfin_remove_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
228{ 233{
229 int breakno; 234 int breakno;
230 for (breakno = 0; breakno < HW_BREAKPOINT_NUM; breakno++) 235 int bfin_type;
231 if (breakinfo[breakno].addr == addr) 236
232 memset(&(breakinfo[breakno]), 0, sizeof(struct hw_breakpoint)); 237 switch (type) {
238 case BP_HARDWARE_BREAKPOINT:
239 bfin_type = TYPE_INST_WATCHPOINT;
240 break;
241 case BP_WRITE_WATCHPOINT:
242 case BP_READ_WATCHPOINT:
243 case BP_ACCESS_WATCHPOINT:
244 bfin_type = TYPE_DATA_WATCHPOINT;
245 break;
246 default:
247 return 0;
248 }
249 for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
250 if (bfin_type == breakinfo[breakno].type
251 && breakinfo[breakno].occupied
252 && breakinfo[breakno].addr == addr) {
253 breakinfo[breakno].occupied = 0;
254 breakinfo[breakno].enabled = 0;
255 }
233 256
234 return 0; 257 return 0;
235} 258}
236 259
237void kgdb_remove_all_hw_break(void) 260void bfin_remove_all_hw_break(void)
238{ 261{
239 memset(breakinfo, 0, sizeof(struct hw_breakpoint)*8); 262 int breakno;
240}
241 263
242/* 264 memset(breakinfo, 0, sizeof(struct hw_breakpoint)*HW_WATCHPOINT_NUM);
243void kgdb_show_info(void) 265
244{ 266 for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
245 printk(KERN_DEBUG "hwd: wpia0=0x%x, wpiacnt0=%d, wpiactl=0x%x, wpstat=0x%x\n", 267 breakinfo[breakno].type = TYPE_INST_WATCHPOINT;
246 bfin_read_WPIA0(), bfin_read_WPIACNT0(), 268 for (; breakno < HW_WATCHPOINT_NUM; breakno++)
247 bfin_read_WPIACTL(), bfin_read_WPSTAT()); 269 breakinfo[breakno].type = TYPE_DATA_WATCHPOINT;
248} 270}
249*/
250 271
251void kgdb_correct_hw_break(void) 272void bfin_correct_hw_break(void)
252{ 273{
253 int breakno; 274 int breakno;
254 int correctit; 275 unsigned int wpiactl = 0;
255 uint32_t wpdactl = bfin_read_WPDACTL(); 276 unsigned int wpdactl = 0;
277 int enable_wp = 0;
278
279 for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
280 if (breakinfo[breakno].enabled) {
281 enable_wp = 1;
256 282
257 correctit = 0;
258 for (breakno = 0; breakno < HW_BREAKPOINT_NUM; breakno++) {
259 if (breakinfo[breakno].type == 1) {
260 switch (breakno) { 283 switch (breakno) {
261 case 0: 284 case 0:
262 if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN0)) { 285 wpiactl |= WPIAEN0|WPICNTEN0;
263 correctit = 1; 286 bfin_write_WPIA0(breakinfo[breakno].addr);
264 wpdactl &= ~(WPIREN01|EMUSW0); 287 bfin_write_WPIACNT0(breakinfo[breakno].count
265 wpdactl |= WPIAEN0|WPICNTEN0; 288 + breakinfo->skip);
266 bfin_write_WPIA0(breakinfo[breakno].addr);
267 bfin_write_WPIACNT0(breakinfo[breakno].skip);
268 } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN0)) {
269 correctit = 1;
270 wpdactl &= ~WPIAEN0;
271 }
272 break; 289 break;
273
274 case 1: 290 case 1:
275 if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN1)) { 291 wpiactl |= WPIAEN1|WPICNTEN1;
276 correctit = 1; 292 bfin_write_WPIA1(breakinfo[breakno].addr);
277 wpdactl &= ~(WPIREN01|EMUSW1); 293 bfin_write_WPIACNT1(breakinfo[breakno].count
278 wpdactl |= WPIAEN1|WPICNTEN1; 294 + breakinfo->skip);
279 bfin_write_WPIA1(breakinfo[breakno].addr);
280 bfin_write_WPIACNT1(breakinfo[breakno].skip);
281 } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN1)) {
282 correctit = 1;
283 wpdactl &= ~WPIAEN1;
284 }
285 break; 295 break;
286
287 case 2: 296 case 2:
288 if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN2)) { 297 wpiactl |= WPIAEN2|WPICNTEN2;
289 correctit = 1; 298 bfin_write_WPIA2(breakinfo[breakno].addr);
290 wpdactl &= ~(WPIREN23|EMUSW2); 299 bfin_write_WPIACNT2(breakinfo[breakno].count
291 wpdactl |= WPIAEN2|WPICNTEN2; 300 + breakinfo->skip);
292 bfin_write_WPIA2(breakinfo[breakno].addr);
293 bfin_write_WPIACNT2(breakinfo[breakno].skip);
294 } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN2)) {
295 correctit = 1;
296 wpdactl &= ~WPIAEN2;
297 }
298 break; 301 break;
299
300 case 3: 302 case 3:
301 if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN3)) { 303 wpiactl |= WPIAEN3|WPICNTEN3;
302 correctit = 1; 304 bfin_write_WPIA3(breakinfo[breakno].addr);
303 wpdactl &= ~(WPIREN23|EMUSW3); 305 bfin_write_WPIACNT3(breakinfo[breakno].count
304 wpdactl |= WPIAEN3|WPICNTEN3; 306 + breakinfo->skip);
305 bfin_write_WPIA3(breakinfo[breakno].addr);
306 bfin_write_WPIACNT3(breakinfo[breakno].skip);
307 } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN3)) {
308 correctit = 1;
309 wpdactl &= ~WPIAEN3;
310 }
311 break; 307 break;
312 case 4: 308 case 4:
313 if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN4)) { 309 wpiactl |= WPIAEN4|WPICNTEN4;
314 correctit = 1; 310 bfin_write_WPIA4(breakinfo[breakno].addr);
315 wpdactl &= ~(WPIREN45|EMUSW4); 311 bfin_write_WPIACNT4(breakinfo[breakno].count
316 wpdactl |= WPIAEN4|WPICNTEN4; 312 + breakinfo->skip);
317 bfin_write_WPIA4(breakinfo[breakno].addr);
318 bfin_write_WPIACNT4(breakinfo[breakno].skip);
319 } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN4)) {
320 correctit = 1;
321 wpdactl &= ~WPIAEN4;
322 }
323 break; 313 break;
324 case 5: 314 case 5:
325 if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN5)) { 315 wpiactl |= WPIAEN5|WPICNTEN5;
326 correctit = 1; 316 bfin_write_WPIA5(breakinfo[breakno].addr);
327 wpdactl &= ~(WPIREN45|EMUSW5); 317 bfin_write_WPIACNT5(breakinfo[breakno].count
328 wpdactl |= WPIAEN5|WPICNTEN5; 318 + breakinfo->skip);
329 bfin_write_WPIA5(breakinfo[breakno].addr); 319 break;
330 bfin_write_WPIACNT5(breakinfo[breakno].skip); 320 case 6:
331 } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN5)) { 321 wpdactl |= WPDAEN0|WPDCNTEN0|WPDSRC0;
332 correctit = 1; 322 wpdactl |= breakinfo[breakno].dataacc
333 wpdactl &= ~WPIAEN5; 323 << WPDACC0_OFFSET;
334 } 324 bfin_write_WPDA0(breakinfo[breakno].addr);
325 bfin_write_WPDACNT0(breakinfo[breakno].count
326 + breakinfo->skip);
327 break;
328 case 7:
329 wpdactl |= WPDAEN1|WPDCNTEN1|WPDSRC1;
330 wpdactl |= breakinfo[breakno].dataacc
331 << WPDACC1_OFFSET;
332 bfin_write_WPDA1(breakinfo[breakno].addr);
333 bfin_write_WPDACNT1(breakinfo[breakno].count
334 + breakinfo->skip);
335 break; 335 break;
336 } 336 }
337 } 337 }
338 } 338
339 if (correctit) { 339 /* Should enable WPPWR bit first before set any other
340 wpdactl &= ~WPAND; 340 * WPIACTL and WPDACTL bits */
341 wpdactl |= WPPWR; 341 if (enable_wp) {
342 /*printk("correct_hw_break: wpdactl=0x%x\n", wpdactl);*/ 342 bfin_write_WPIACTL(WPPWR);
343 CSYNC();
344 bfin_write_WPIACTL(wpiactl|WPPWR);
343 bfin_write_WPDACTL(wpdactl); 345 bfin_write_WPDACTL(wpdactl);
344 CSYNC(); 346 CSYNC();
345 /*kgdb_show_info();*/
346 } 347 }
347} 348}
348 349
349void kgdb_disable_hw_debug(struct pt_regs *regs) 350void kgdb_disable_hw_debug(struct pt_regs *regs)
350{ 351{
351 /* Disable hardware debugging while we are in kgdb */ 352 /* Disable hardware debugging while we are in kgdb */
352 bfin_write_WPIACTL(bfin_read_WPIACTL() & ~0x1); 353 bfin_write_WPIACTL(0);
354 bfin_write_WPDACTL(0);
353 CSYNC(); 355 CSYNC();
354} 356}
355 357
356void kgdb_post_master_code(struct pt_regs *regs, int eVector, int err_code) 358#ifdef CONFIG_SMP
359void kgdb_passive_cpu_callback(void *info)
360{
361 kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs());
362}
363
364void kgdb_roundup_cpus(unsigned long flags)
365{
366 smp_call_function(kgdb_passive_cpu_callback, NULL, 0, 0);
367}
368
369void kgdb_roundup_cpu(int cpu, unsigned long flags)
370{
371 smp_call_function_single(cpu, kgdb_passive_cpu_callback, NULL, 0, 0);
372}
373#endif
374
375void kgdb_post_primary_code(struct pt_regs *regs, int eVector, int err_code)
357{ 376{
358 /* Master processor is completely in the debugger */ 377 /* Master processor is completely in the debugger */
359 gdb_bf533vector = eVector; 378 gdb_bfin_vector = eVector;
360 gdb_bf533errcode = err_code; 379 gdb_bfin_errcode = err_code;
361} 380}
362 381
363int kgdb_arch_handle_exception(int exceptionVector, int signo, 382int kgdb_arch_handle_exception(int vector, int signo,
364 int err_code, char *remcom_in_buffer, 383 int err_code, char *remcom_in_buffer,
365 char *remcom_out_buffer, 384 char *remcom_out_buffer,
366 struct pt_regs *linux_regs) 385 struct pt_regs *regs)
367{ 386{
368 long addr; 387 long addr;
369 long breakno; 388 long breakno;
@@ -385,44 +404,40 @@ int kgdb_arch_handle_exception(int exceptionVector, int signo,
385 /* try to read optional parameter, pc unchanged if no parm */ 404 /* try to read optional parameter, pc unchanged if no parm */
386 ptr = &remcom_in_buffer[1]; 405 ptr = &remcom_in_buffer[1];
387 if (kgdb_hex2long(&ptr, &addr)) { 406 if (kgdb_hex2long(&ptr, &addr)) {
388 linux_regs->retx = addr; 407 regs->retx = addr;
389 } 408 }
390 newPC = linux_regs->retx; 409 newPC = regs->retx;
391 410
392 /* clear the trace bit */ 411 /* clear the trace bit */
393 linux_regs->syscfg &= 0xfffffffe; 412 regs->syscfg &= 0xfffffffe;
394 413
395 /* set the trace bit if we're stepping */ 414 /* set the trace bit if we're stepping */
396 if (remcom_in_buffer[0] == 's') { 415 if (remcom_in_buffer[0] == 's') {
397 linux_regs->syscfg |= 0x1; 416 regs->syscfg |= 0x1;
398 debugger_step = linux_regs->ipend; 417 kgdb_single_step = regs->ipend;
399 debugger_step >>= 6; 418 kgdb_single_step >>= 6;
400 for (i = 10; i > 0; i--, debugger_step >>= 1) 419 for (i = 10; i > 0; i--, kgdb_single_step >>= 1)
401 if (debugger_step & 1) 420 if (kgdb_single_step & 1)
402 break; 421 break;
403 /* i indicate event priority of current stopped instruction 422 /* i indicate event priority of current stopped instruction
404 * user space instruction is 0, IVG15 is 1, IVTMR is 10. 423 * user space instruction is 0, IVG15 is 1, IVTMR is 10.
405 * debugger_step > 0 means in single step mode 424 * kgdb_single_step > 0 means in single step mode
406 */ 425 */
407 debugger_step = i + 1; 426 kgdb_single_step = i + 1;
408 } else {
409 debugger_step = 0;
410 } 427 }
411 428
412 wp_status = bfin_read_WPSTAT(); 429 if (vector == VEC_WATCH) {
413 CSYNC(); 430 wp_status = bfin_read_WPSTAT();
414 431 for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++) {
415 if (exceptionVector == VEC_WATCH) {
416 for (breakno = 0; breakno < 6; ++breakno) {
417 if (wp_status & (1 << breakno)) { 432 if (wp_status & (1 << breakno)) {
418 breakinfo->skip = 1; 433 breakinfo->skip = 1;
419 break; 434 break;
420 } 435 }
421 } 436 }
437 bfin_write_WPSTAT(0);
422 } 438 }
423 kgdb_correct_hw_break();
424 439
425 bfin_write_WPSTAT(0); 440 bfin_correct_hw_break();
426 441
427 return 0; 442 return 0;
428 } /* switch */ 443 } /* switch */
@@ -431,5 +446,385 @@ int kgdb_arch_handle_exception(int exceptionVector, int signo,
431 446
432struct kgdb_arch arch_kgdb_ops = { 447struct kgdb_arch arch_kgdb_ops = {
433 .gdb_bpt_instr = {0xa1}, 448 .gdb_bpt_instr = {0xa1},
449#ifdef CONFIG_SMP
450 .flags = KGDB_HW_BREAKPOINT|KGDB_THR_PROC_SWAP,
451#else
434 .flags = KGDB_HW_BREAKPOINT, 452 .flags = KGDB_HW_BREAKPOINT,
453#endif
454 .set_hw_breakpoint = bfin_set_hw_break,
455 .remove_hw_breakpoint = bfin_remove_hw_break,
456 .remove_all_hw_break = bfin_remove_all_hw_break,
457 .correct_hw_break = bfin_correct_hw_break,
435}; 458};
459
460static int hex(char ch)
461{
462 if ((ch >= 'a') && (ch <= 'f'))
463 return ch - 'a' + 10;
464 if ((ch >= '0') && (ch <= '9'))
465 return ch - '0';
466 if ((ch >= 'A') && (ch <= 'F'))
467 return ch - 'A' + 10;
468 return -1;
469}
470
471static int validate_memory_access_address(unsigned long addr, int size)
472{
473 int cpu = raw_smp_processor_id();
474
475 if (size < 0)
476 return EFAULT;
477 if (addr >= 0x1000 && (addr + size) <= physical_mem_end)
478 return 0;
479 if (addr >= SYSMMR_BASE)
480 return 0;
481 if (addr >= ASYNC_BANK0_BASE
482 && addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
483 return 0;
484 if (cpu == 0) {
485 if (addr >= L1_SCRATCH_START
486 && (addr + size <= L1_SCRATCH_START + L1_SCRATCH_LENGTH))
487 return 0;
488#if L1_CODE_LENGTH != 0
489 if (addr >= L1_CODE_START
490 && (addr + size <= L1_CODE_START + L1_CODE_LENGTH))
491 return 0;
492#endif
493#if L1_DATA_A_LENGTH != 0
494 if (addr >= L1_DATA_A_START
495 && (addr + size <= L1_DATA_A_START + L1_DATA_A_LENGTH))
496 return 0;
497#endif
498#if L1_DATA_B_LENGTH != 0
499 if (addr >= L1_DATA_B_START
500 && (addr + size <= L1_DATA_B_START + L1_DATA_B_LENGTH))
501 return 0;
502#endif
503#ifdef CONFIG_SMP
504 } else if (cpu == 1) {
505 if (addr >= COREB_L1_SCRATCH_START
506 && (addr + size <= COREB_L1_SCRATCH_START
507 + L1_SCRATCH_LENGTH))
508 return 0;
509# if L1_CODE_LENGTH != 0
510 if (addr >= COREB_L1_CODE_START
511 && (addr + size <= COREB_L1_CODE_START + L1_CODE_LENGTH))
512 return 0;
513# endif
514# if L1_DATA_A_LENGTH != 0
515 if (addr >= COREB_L1_DATA_A_START
516 && (addr + size <= COREB_L1_DATA_A_START + L1_DATA_A_LENGTH))
517 return 0;
518# endif
519# if L1_DATA_B_LENGTH != 0
520 if (addr >= COREB_L1_DATA_B_START
521 && (addr + size <= COREB_L1_DATA_B_START + L1_DATA_B_LENGTH))
522 return 0;
523# endif
524#endif
525 }
526
527#if L2_LENGTH != 0
528 if (addr >= L2_START
529 && addr + size <= L2_START + L2_LENGTH)
530 return 0;
531#endif
532
533 return EFAULT;
534}
535
536/*
537 * Convert the memory pointed to by mem into hex, placing result in buf.
538 * Return a pointer to the last char put in buf (null). May return an error.
539 */
540int kgdb_mem2hex(char *mem, char *buf, int count)
541{
542 char *tmp;
543 int err = 0;
544 unsigned char *pch;
545 unsigned short mmr16;
546 unsigned long mmr32;
547 int cpu = raw_smp_processor_id();
548
549 if (validate_memory_access_address((unsigned long)mem, count))
550 return EFAULT;
551
552 /*
553 * We use the upper half of buf as an intermediate buffer for the
554 * raw memory copy. Hex conversion will work against this one.
555 */
556 tmp = buf + count;
557
558 if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/
559 switch (count) {
560 case 2:
561 if ((unsigned int)mem % 2 == 0) {
562 mmr16 = *(unsigned short *)mem;
563 pch = (unsigned char *)&mmr16;
564 *tmp++ = *pch++;
565 *tmp++ = *pch++;
566 tmp -= 2;
567 } else
568 err = EFAULT;
569 break;
570 case 4:
571 if ((unsigned int)mem % 4 == 0) {
572 mmr32 = *(unsigned long *)mem;
573 pch = (unsigned char *)&mmr32;
574 *tmp++ = *pch++;
575 *tmp++ = *pch++;
576 *tmp++ = *pch++;
577 *tmp++ = *pch++;
578 tmp -= 4;
579 } else
580 err = EFAULT;
581 break;
582 default:
583 err = EFAULT;
584 }
585 } else if (cpu == 0 && (unsigned int)mem >= L1_CODE_START &&
586 (unsigned int)(mem + count) <= L1_CODE_START + L1_CODE_LENGTH
587#ifdef CONFIG_SMP
588 || cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START &&
589 (unsigned int)(mem + count) <=
590 COREB_L1_CODE_START + L1_CODE_LENGTH
591#endif
592 ) {
593 /* access L1 instruction SRAM*/
594 if (dma_memcpy(tmp, mem, count) == NULL)
595 err = EFAULT;
596 } else
597 err = probe_kernel_read(tmp, mem, count);
598
599 if (!err) {
600 while (count > 0) {
601 buf = pack_hex_byte(buf, *tmp);
602 tmp++;
603 count--;
604 }
605
606 *buf = 0;
607 }
608
609 return err;
610}
611
612/*
613 * Copy the binary array pointed to by buf into mem. Fix $, #, and
614 * 0x7d escaped with 0x7d. Return a pointer to the character after
615 * the last byte written.
616 */
617int kgdb_ebin2mem(char *buf, char *mem, int count)
618{
619 char *tmp_old;
620 char *tmp_new;
621 unsigned short *mmr16;
622 unsigned long *mmr32;
623 int err = 0;
624 int size = 0;
625 int cpu = raw_smp_processor_id();
626
627 tmp_old = tmp_new = buf;
628
629 while (count-- > 0) {
630 if (*tmp_old == 0x7d)
631 *tmp_new = *(++tmp_old) ^ 0x20;
632 else
633 *tmp_new = *tmp_old;
634 tmp_new++;
635 tmp_old++;
636 size++;
637 }
638
639 if (validate_memory_access_address((unsigned long)mem, size))
640 return EFAULT;
641
642 if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/
643 switch (size) {
644 case 2:
645 if ((unsigned int)mem % 2 == 0) {
646 mmr16 = (unsigned short *)buf;
647 *(unsigned short *)mem = *mmr16;
648 } else
649 return EFAULT;
650 break;
651 case 4:
652 if ((unsigned int)mem % 4 == 0) {
653 mmr32 = (unsigned long *)buf;
654 *(unsigned long *)mem = *mmr32;
655 } else
656 return EFAULT;
657 break;
658 default:
659 return EFAULT;
660 }
661 } else if (cpu == 0 && (unsigned int)mem >= L1_CODE_START &&
662 (unsigned int)(mem + count) < L1_CODE_START + L1_CODE_LENGTH
663#ifdef CONFIG_SMP
664 || cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START &&
665 (unsigned int)(mem + count) <=
666 COREB_L1_CODE_START + L1_CODE_LENGTH
667#endif
668 ) {
669 /* access L1 instruction SRAM */
670 if (dma_memcpy(mem, buf, size) == NULL)
671 err = EFAULT;
672 } else
673 err = probe_kernel_write(mem, buf, size);
674
675 return err;
676}
677
678/*
679 * Convert the hex array pointed to by buf into binary to be placed in mem.
680 * Return a pointer to the character AFTER the last byte written.
681 * May return an error.
682 */
683int kgdb_hex2mem(char *buf, char *mem, int count)
684{
685 char *tmp_raw;
686 char *tmp_hex;
687 unsigned short *mmr16;
688 unsigned long *mmr32;
689 int cpu = raw_smp_processor_id();
690
691 if (validate_memory_access_address((unsigned long)mem, count))
692 return EFAULT;
693
694 /*
695 * We use the upper half of buf as an intermediate buffer for the
696 * raw memory that is converted from hex.
697 */
698 tmp_raw = buf + count * 2;
699
700 tmp_hex = tmp_raw - 1;
701 while (tmp_hex >= buf) {
702 tmp_raw--;
703 *tmp_raw = hex(*tmp_hex--);
704 *tmp_raw |= hex(*tmp_hex--) << 4;
705 }
706
707 if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/
708 switch (count) {
709 case 2:
710 if ((unsigned int)mem % 2 == 0) {
711 mmr16 = (unsigned short *)tmp_raw;
712 *(unsigned short *)mem = *mmr16;
713 } else
714 return EFAULT;
715 break;
716 case 4:
717 if ((unsigned int)mem % 4 == 0) {
718 mmr32 = (unsigned long *)tmp_raw;
719 *(unsigned long *)mem = *mmr32;
720 } else
721 return EFAULT;
722 break;
723 default:
724 return EFAULT;
725 }
726 } else if (cpu == 0 && (unsigned int)mem >= L1_CODE_START &&
727 (unsigned int)(mem + count) <= L1_CODE_START + L1_CODE_LENGTH
728#ifdef CONFIG_SMP
729 || cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START &&
730 (unsigned int)(mem + count) <=
731 COREB_L1_CODE_START + L1_CODE_LENGTH
732#endif
733 ) {
734 /* access L1 instruction SRAM */
735 if (dma_memcpy(mem, tmp_raw, count) == NULL)
736 return EFAULT;
737 } else
738 return probe_kernel_write(mem, tmp_raw, count);
739 return 0;
740}
741
742int kgdb_validate_break_address(unsigned long addr)
743{
744 int cpu = raw_smp_processor_id();
745
746 if (addr >= 0x1000 && (addr + BREAK_INSTR_SIZE) <= physical_mem_end)
747 return 0;
748 if (addr >= ASYNC_BANK0_BASE
749 && addr + BREAK_INSTR_SIZE <= ASYNC_BANK3_BASE + ASYNC_BANK3_BASE)
750 return 0;
751#if L1_CODE_LENGTH != 0
752 if (cpu == 0 && addr >= L1_CODE_START
753 && addr + BREAK_INSTR_SIZE <= L1_CODE_START + L1_CODE_LENGTH)
754 return 0;
755# ifdef CONFIG_SMP
756 else if (cpu == 1 && addr >= COREB_L1_CODE_START
757 && addr + BREAK_INSTR_SIZE <= COREB_L1_CODE_START + L1_CODE_LENGTH)
758 return 0;
759# endif
760#endif
761#if L2_LENGTH != 0
762 if (addr >= L2_START
763 && addr + BREAK_INSTR_SIZE <= L2_START + L2_LENGTH)
764 return 0;
765#endif
766
767 return EFAULT;
768}
769
770int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr)
771{
772 int err;
773 int cpu = raw_smp_processor_id();
774
775 if ((cpu == 0 && (unsigned int)addr >= L1_CODE_START
776 && (unsigned int)(addr + BREAK_INSTR_SIZE)
777 < L1_CODE_START + L1_CODE_LENGTH)
778#ifdef CONFIG_SMP
779 || (cpu == 1 && (unsigned int)addr >= COREB_L1_CODE_START
780 && (unsigned int)(addr + BREAK_INSTR_SIZE)
781 < COREB_L1_CODE_START + L1_CODE_LENGTH)
782#endif
783 ) {
784 /* access L1 instruction SRAM */
785 if (dma_memcpy(saved_instr, (void *)addr, BREAK_INSTR_SIZE)
786 == NULL)
787 return -EFAULT;
788
789 if (dma_memcpy((void *)addr, arch_kgdb_ops.gdb_bpt_instr,
790 BREAK_INSTR_SIZE) == NULL)
791 return -EFAULT;
792
793 return 0;
794 } else {
795 err = probe_kernel_read(saved_instr, (char *)addr,
796 BREAK_INSTR_SIZE);
797 if (err)
798 return err;
799
800 return probe_kernel_write((char *)addr,
801 arch_kgdb_ops.gdb_bpt_instr, BREAK_INSTR_SIZE);
802 }
803}
804
805int kgdb_arch_remove_breakpoint(unsigned long addr, char *bundle)
806{
807 if ((unsigned int)addr >= L1_CODE_START &&
808 (unsigned int)(addr + BREAK_INSTR_SIZE) <
809 L1_CODE_START + L1_CODE_LENGTH) {
810 /* access L1 instruction SRAM */
811 if (dma_memcpy((void *)addr, bundle, BREAK_INSTR_SIZE) == NULL)
812 return -EFAULT;
813
814 return 0;
815 } else
816 return probe_kernel_write((char *)addr,
817 (char *)bundle, BREAK_INSTR_SIZE);
818}
819
820int kgdb_arch_init(void)
821{
822 kgdb_single_step = 0;
823
824 bfin_remove_all_hw_break();
825 return 0;
826}
827
828void kgdb_arch_exit(void)
829{
830}
diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c
index bf1a51d8e608..140bf00e9974 100644
--- a/arch/blackfin/kernel/ptrace.c
+++ b/arch/blackfin/kernel/ptrace.c
@@ -46,7 +46,6 @@
46#include <asm/dma.h> 46#include <asm/dma.h>
47#include <asm/fixed_code.h> 47#include <asm/fixed_code.h>
48 48
49#define MAX_SHARED_LIBS 3
50#define TEXT_OFFSET 0 49#define TEXT_OFFSET 0
51/* 50/*
52 * does not yet catch signals sent when the child dies. 51 * does not yet catch signals sent when the child dies.
@@ -161,21 +160,32 @@ static inline int is_user_addr_valid(struct task_struct *child,
161 struct vm_list_struct *vml; 160 struct vm_list_struct *vml;
162 struct sram_list_struct *sraml; 161 struct sram_list_struct *sraml;
163 162
163 /* overflow */
164 if (start + len < start)
165 return -EIO;
166
164 for (vml = child->mm->context.vmlist; vml; vml = vml->next) 167 for (vml = child->mm->context.vmlist; vml; vml = vml->next)
165 if (start >= vml->vma->vm_start && start + len <= vml->vma->vm_end) 168 if (start >= vml->vma->vm_start && start + len < vml->vma->vm_end)
166 return 0; 169 return 0;
167 170
168 for (sraml = child->mm->context.sram_list; sraml; sraml = sraml->next) 171 for (sraml = child->mm->context.sram_list; sraml; sraml = sraml->next)
169 if (start >= (unsigned long)sraml->addr 172 if (start >= (unsigned long)sraml->addr
170 && start + len <= (unsigned long)sraml->addr + sraml->length) 173 && start + len < (unsigned long)sraml->addr + sraml->length)
171 return 0; 174 return 0;
172 175
173 if (start >= FIXED_CODE_START && start + len <= FIXED_CODE_END) 176 if (start >= FIXED_CODE_START && start + len < FIXED_CODE_END)
174 return 0; 177 return 0;
175 178
176 return -EIO; 179 return -EIO;
177} 180}
178 181
182void ptrace_enable(struct task_struct *child)
183{
184 unsigned long tmp;
185 tmp = get_reg(child, PT_SYSCFG) | (TRACE_BITS);
186 put_reg(child, PT_SYSCFG, tmp);
187}
188
179/* 189/*
180 * Called by kernel/ptrace.c when detaching.. 190 * Called by kernel/ptrace.c when detaching..
181 * 191 *
@@ -192,14 +202,12 @@ void ptrace_disable(struct task_struct *child)
192long arch_ptrace(struct task_struct *child, long request, long addr, long data) 202long arch_ptrace(struct task_struct *child, long request, long addr, long data)
193{ 203{
194 int ret; 204 int ret;
195 int add = 0;
196 unsigned long __user *datap = (unsigned long __user *)data; 205 unsigned long __user *datap = (unsigned long __user *)data;
197 206
198 switch (request) { 207 switch (request) {
199 /* when I and D space are separate, these will need to be fixed. */ 208 /* when I and D space are separate, these will need to be fixed. */
200 case PTRACE_PEEKDATA: 209 case PTRACE_PEEKDATA:
201 pr_debug("ptrace: PEEKDATA\n"); 210 pr_debug("ptrace: PEEKDATA\n");
202 add = MAX_SHARED_LIBS * 4; /* space between text and data */
203 /* fall through */ 211 /* fall through */
204 case PTRACE_PEEKTEXT: /* read word at location addr. */ 212 case PTRACE_PEEKTEXT: /* read word at location addr. */
205 { 213 {
@@ -207,40 +215,35 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
207 int copied; 215 int copied;
208 216
209 ret = -EIO; 217 ret = -EIO;
210 pr_debug("ptrace: PEEKTEXT at addr 0x%08lx + add %d %ld\n", addr, add, 218 pr_debug("ptrace: PEEKTEXT at addr 0x%08lx + %ld\n", addr, sizeof(data));
211 sizeof(data)); 219 if (is_user_addr_valid(child, addr, sizeof(tmp)) < 0)
212 if (is_user_addr_valid(child, addr + add, sizeof(tmp)) < 0)
213 break; 220 break;
214 pr_debug("ptrace: user address is valid\n"); 221 pr_debug("ptrace: user address is valid\n");
215 222
216#if L1_CODE_LENGTH != 0 223 if (L1_CODE_LENGTH != 0 && addr >= L1_CODE_START
217 if (addr + add >= L1_CODE_START 224 && addr + sizeof(tmp) <= L1_CODE_START + L1_CODE_LENGTH) {
218 && addr + add + sizeof(tmp) <= L1_CODE_START + L1_CODE_LENGTH) { 225 safe_dma_memcpy (&tmp, (const void *)(addr), sizeof(tmp));
219 safe_dma_memcpy (&tmp, (const void *)(addr + add), sizeof(tmp));
220 copied = sizeof(tmp); 226 copied = sizeof(tmp);
221 } else 227
222#endif 228 } else if (L1_DATA_A_LENGTH != 0 && addr >= L1_DATA_A_START
223#if L1_DATA_A_LENGTH != 0 229 && addr + sizeof(tmp) <= L1_DATA_A_START + L1_DATA_A_LENGTH) {
224 if (addr + add >= L1_DATA_A_START 230 memcpy(&tmp, (const void *)(addr), sizeof(tmp));
225 && addr + add + sizeof(tmp) <= L1_DATA_A_START + L1_DATA_A_LENGTH) {
226 memcpy(&tmp, (const void *)(addr + add), sizeof(tmp));
227 copied = sizeof(tmp); 231 copied = sizeof(tmp);
228 } else 232
229#endif 233 } else if (L1_DATA_B_LENGTH != 0 && addr >= L1_DATA_B_START
230#if L1_DATA_B_LENGTH != 0 234 && addr + sizeof(tmp) <= L1_DATA_B_START + L1_DATA_B_LENGTH) {
231 if (addr + add >= L1_DATA_B_START 235 memcpy(&tmp, (const void *)(addr), sizeof(tmp));
232 && addr + add + sizeof(tmp) <= L1_DATA_B_START + L1_DATA_B_LENGTH) {
233 memcpy(&tmp, (const void *)(addr + add), sizeof(tmp));
234 copied = sizeof(tmp); 236 copied = sizeof(tmp);
235 } else 237
236#endif 238 } else if (addr >= FIXED_CODE_START
237 if (addr + add >= FIXED_CODE_START 239 && addr + sizeof(tmp) <= FIXED_CODE_END) {
238 && addr + add + sizeof(tmp) <= FIXED_CODE_END) { 240 memcpy(&tmp, (const void *)(addr), sizeof(tmp));
239 memcpy(&tmp, (const void *)(addr + add), sizeof(tmp));
240 copied = sizeof(tmp); 241 copied = sizeof(tmp);
242
241 } else 243 } else
242 copied = access_process_vm(child, addr + add, &tmp, 244 copied = access_process_vm(child, addr, &tmp,
243 sizeof(tmp), 0); 245 sizeof(tmp), 0);
246
244 pr_debug("ptrace: copied size %d [0x%08lx]\n", copied, tmp); 247 pr_debug("ptrace: copied size %d [0x%08lx]\n", copied, tmp);
245 if (copied != sizeof(tmp)) 248 if (copied != sizeof(tmp))
246 break; 249 break;
@@ -284,47 +287,43 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
284 287
285 /* when I and D space are separate, this will have to be fixed. */ 288 /* when I and D space are separate, this will have to be fixed. */
286 case PTRACE_POKEDATA: 289 case PTRACE_POKEDATA:
287 printk(KERN_NOTICE "ptrace: PTRACE_PEEKDATA\n"); 290 pr_debug("ptrace: PTRACE_PEEKDATA\n");
288 /* fall through */ 291 /* fall through */
289 case PTRACE_POKETEXT: /* write the word at location addr. */ 292 case PTRACE_POKETEXT: /* write the word at location addr. */
290 { 293 {
291 int copied; 294 int copied;
292 295
293 ret = -EIO; 296 ret = -EIO;
294 pr_debug("ptrace: POKETEXT at addr 0x%08lx + add %d %ld bytes %lx\n", 297 pr_debug("ptrace: POKETEXT at addr 0x%08lx + %ld bytes %lx\n",
295 addr, add, sizeof(data), data); 298 addr, sizeof(data), data);
296 if (is_user_addr_valid(child, addr + add, sizeof(data)) < 0) 299 if (is_user_addr_valid(child, addr, sizeof(data)) < 0)
297 break; 300 break;
298 pr_debug("ptrace: user address is valid\n"); 301 pr_debug("ptrace: user address is valid\n");
299 302
300#if L1_CODE_LENGTH != 0 303 if (L1_CODE_LENGTH != 0 && addr >= L1_CODE_START
301 if (addr + add >= L1_CODE_START 304 && addr + sizeof(data) <= L1_CODE_START + L1_CODE_LENGTH) {
302 && addr + add + sizeof(data) <= L1_CODE_START + L1_CODE_LENGTH) { 305 safe_dma_memcpy ((void *)(addr), &data, sizeof(data));
303 safe_dma_memcpy ((void *)(addr + add), &data, sizeof(data));
304 copied = sizeof(data); 306 copied = sizeof(data);
305 } else 307
306#endif 308 } else if (L1_DATA_A_LENGTH != 0 && addr >= L1_DATA_A_START
307#if L1_DATA_A_LENGTH != 0 309 && addr + sizeof(data) <= L1_DATA_A_START + L1_DATA_A_LENGTH) {
308 if (addr + add >= L1_DATA_A_START 310 memcpy((void *)(addr), &data, sizeof(data));
309 && addr + add + sizeof(data) <= L1_DATA_A_START + L1_DATA_A_LENGTH) {
310 memcpy((void *)(addr + add), &data, sizeof(data));
311 copied = sizeof(data); 311 copied = sizeof(data);
312 } else 312
313#endif 313 } else if (L1_DATA_B_LENGTH != 0 && addr >= L1_DATA_B_START
314#if L1_DATA_B_LENGTH != 0 314 && addr + sizeof(data) <= L1_DATA_B_START + L1_DATA_B_LENGTH) {
315 if (addr + add >= L1_DATA_B_START 315 memcpy((void *)(addr), &data, sizeof(data));
316 && addr + add + sizeof(data) <= L1_DATA_B_START + L1_DATA_B_LENGTH) {
317 memcpy((void *)(addr + add), &data, sizeof(data));
318 copied = sizeof(data); 316 copied = sizeof(data);
319 } else 317
320#endif 318 } else if (addr >= FIXED_CODE_START
321 if (addr + add >= FIXED_CODE_START 319 && addr + sizeof(data) <= FIXED_CODE_END) {
322 && addr + add + sizeof(data) <= FIXED_CODE_END) { 320 memcpy((void *)(addr), &data, sizeof(data));
323 memcpy((void *)(addr + add), &data, sizeof(data));
324 copied = sizeof(data); 321 copied = sizeof(data);
322
325 } else 323 } else
326 copied = access_process_vm(child, addr + add, &data, 324 copied = access_process_vm(child, addr, &data,
327 sizeof(data), 1); 325 sizeof(data), 1);
326
328 pr_debug("ptrace: copied size %d\n", copied); 327 pr_debug("ptrace: copied size %d\n", copied);
329 if (copied != sizeof(data)) 328 if (copied != sizeof(data))
330 break; 329 break;
@@ -351,29 +350,22 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
351 break; 350 break;
352 351
353 case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */ 352 case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */
354 case PTRACE_CONT: 353 case PTRACE_CONT: /* restart after signal. */
355 { /* restart after signal. */ 354 pr_debug("ptrace: syscall/cont\n");
356 long tmp;
357 355
358 pr_debug("ptrace_cont\n"); 356 ret = -EIO;
359 357 if (!valid_signal(data))
360 ret = -EIO;
361 if (!valid_signal(data))
362 break;
363 if (request == PTRACE_SYSCALL)
364 set_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
365 else
366 clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
367
368 child->exit_code = data;
369 /* make sure the single step bit is not set. */
370 tmp = get_reg(child, PT_SYSCFG) & ~(TRACE_BITS);
371 put_reg(child, PT_SYSCFG, tmp);
372 pr_debug("before wake_up_process\n");
373 wake_up_process(child);
374 ret = 0;
375 break; 358 break;
376 } 359 if (request == PTRACE_SYSCALL)
360 set_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
361 else
362 clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
363 child->exit_code = data;
364 ptrace_disable(child);
365 pr_debug("ptrace: before wake_up_process\n");
366 wake_up_process(child);
367 ret = 0;
368 break;
377 369
378 /* 370 /*
379 * make the child exit. Best I can do is send it a sigkill. 371 * make the child exit. Best I can do is send it a sigkill.
@@ -381,55 +373,37 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
381 * exit. 373 * exit.
382 */ 374 */
383 case PTRACE_KILL: 375 case PTRACE_KILL:
384 { 376 ret = 0;
385 long tmp; 377 if (child->exit_state == EXIT_ZOMBIE) /* already dead */
386 ret = 0;
387 if (child->exit_state == EXIT_ZOMBIE) /* already dead */
388 break;
389 child->exit_code = SIGKILL;
390 /* make sure the single step bit is not set. */
391 tmp = get_reg(child, PT_SYSCFG) & ~(TRACE_BITS);
392 put_reg(child, PT_SYSCFG, tmp);
393 wake_up_process(child);
394 break; 378 break;
395 } 379 child->exit_code = SIGKILL;
396 380 ptrace_disable(child);
397 case PTRACE_SINGLESTEP: 381 wake_up_process(child);
398 { /* set the trap flag. */ 382 break;
399 long tmp;
400
401 pr_debug("single step\n");
402 ret = -EIO;
403 if (!valid_signal(data))
404 break;
405 clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
406
407 tmp = get_reg(child, PT_SYSCFG) | (TRACE_BITS);
408 put_reg(child, PT_SYSCFG, tmp);
409 383
410 child->exit_code = data; 384 case PTRACE_SINGLESTEP: /* set the trap flag. */
411 /* give it a chance to run. */ 385 pr_debug("ptrace: single step\n");
412 wake_up_process(child); 386 ret = -EIO;
413 ret = 0; 387 if (!valid_signal(data))
414 break; 388 break;
415 } 389 clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
390 ptrace_enable(child);
391 child->exit_code = data;
392 wake_up_process(child);
393 ret = 0;
394 break;
416 395
417 case PTRACE_GETREGS: 396 case PTRACE_GETREGS:
418 { 397 /* Get all gp regs from the child. */
419 398 ret = ptrace_getregs(child, datap);
420 /* Get all gp regs from the child. */ 399 break;
421 ret = ptrace_getregs(child, datap);
422 break;
423 }
424 400
425 case PTRACE_SETREGS: 401 case PTRACE_SETREGS:
426 { 402 printk(KERN_WARNING "ptrace: SETREGS: **** NOT IMPLEMENTED ***\n");
427 printk(KERN_NOTICE 403 /* Set all gp regs in the child. */
428 "ptrace: SETREGS: **** NOT IMPLEMENTED ***\n"); 404 ret = 0;
429 /* Set all gp regs in the child. */ 405 break;
430 ret = 0; 406
431 break;
432 }
433 default: 407 default:
434 ret = ptrace_request(child, request, addr, data); 408 ret = ptrace_request(child, request, addr, data);
435 break; 409 break;
@@ -440,7 +414,6 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
440 414
441asmlinkage void syscall_trace(void) 415asmlinkage void syscall_trace(void)
442{ 416{
443
444 if (!test_thread_flag(TIF_SYSCALL_TRACE)) 417 if (!test_thread_flag(TIF_SYSCALL_TRACE))
445 return; 418 return;
446 419
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
index 367e2dc09881..ae97ca407b0d 100644
--- a/arch/blackfin/kernel/reboot.c
+++ b/arch/blackfin/kernel/reboot.c
@@ -10,6 +10,7 @@
10#include <asm/bfin-global.h> 10#include <asm/bfin-global.h>
11#include <asm/reboot.h> 11#include <asm/reboot.h>
12#include <asm/system.h> 12#include <asm/system.h>
13#include <asm/bfrom.h>
13 14
14/* A system soft reset makes external memory unusable so force 15/* A system soft reset makes external memory unusable so force
15 * this function into L1. We use the compiler ssync here rather 16 * this function into L1. We use the compiler ssync here rather
@@ -20,7 +21,7 @@
20 * the core reset. 21 * the core reset.
21 */ 22 */
22__attribute__((l1_text)) 23__attribute__((l1_text))
23void bfin_reset(void) 24static void bfin_reset(void)
24{ 25{
25 /* Wait for completion of "system" events such as cache line 26 /* Wait for completion of "system" events such as cache line
26 * line fills so that we avoid infinite stalls later on as 27 * line fills so that we avoid infinite stalls later on as
@@ -34,15 +35,15 @@ void bfin_reset(void)
34 bfin_write_SWRST(0x7); 35 bfin_write_SWRST(0x7);
35 36
36 /* Due to the way reset is handled in the hardware, we need 37 /* Due to the way reset is handled in the hardware, we need
37 * to delay for 7 SCLKS. The only reliable way to do this is 38 * to delay for 10 SCLKS. The only reliable way to do this is
38 * to calculate the CCLK/SCLK ratio and multiply 7. For now, 39 * to calculate the CCLK/SCLK ratio and multiply 10. For now,
39 * we'll assume worse case which is a 1:15 ratio. 40 * we'll assume worse case which is a 1:15 ratio.
40 */ 41 */
41 asm( 42 asm(
42 "LSETUP (1f, 1f) LC0 = %0\n" 43 "LSETUP (1f, 1f) LC0 = %0\n"
43 "1: nop;" 44 "1: nop;"
44 : 45 :
45 : "a" (15 * 7) 46 : "a" (15 * 10)
46 : "LC0", "LB0", "LT0" 47 : "LC0", "LB0", "LT0"
47 ); 48 );
48 49
@@ -74,7 +75,14 @@ void machine_restart(char *cmd)
74{ 75{
75 native_machine_restart(cmd); 76 native_machine_restart(cmd);
76 local_irq_disable(); 77 local_irq_disable();
77 bfin_reset(); 78 if (ANOMALY_05000353 || ANOMALY_05000386)
79 bfin_reset();
80 else
81 /* the bootrom checks to see how it was reset and will
82 * automatically perform a software reset for us when
83 * it starts executing boot
84 */
85 asm("raise 1;");
78} 86}
79 87
80__attribute__((weak)) 88__attribute__((weak))
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 7a82d10b4ebf..7f35d1046cd8 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -42,6 +42,7 @@ EXPORT_SYMBOL(memory_start);
42EXPORT_SYMBOL(memory_end); 42EXPORT_SYMBOL(memory_end);
43EXPORT_SYMBOL(physical_mem_end); 43EXPORT_SYMBOL(physical_mem_end);
44EXPORT_SYMBOL(_ramend); 44EXPORT_SYMBOL(_ramend);
45EXPORT_SYMBOL(reserved_mem_dcache_on);
45 46
46#ifdef CONFIG_MTD_UCLINUX 47#ifdef CONFIG_MTD_UCLINUX
47unsigned long memory_mtd_end, memory_mtd_start, mtd_size; 48unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
@@ -52,7 +53,8 @@ EXPORT_SYMBOL(mtd_size);
52#endif 53#endif
53 54
54char __initdata command_line[COMMAND_LINE_SIZE]; 55char __initdata command_line[COMMAND_LINE_SIZE];
55unsigned int __initdata *__retx; 56void __initdata *init_retx, *init_saved_retx, *init_saved_seqstat,
57 *init_saved_icplb_fault_addr, *init_saved_dcplb_fault_addr;
56 58
57/* boot memmap, for parsing "memmap=" */ 59/* boot memmap, for parsing "memmap=" */
58#define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */ 60#define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */
@@ -77,10 +79,10 @@ static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata;
77static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata; 79static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata;
78static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata; 80static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata;
79 81
80void __init bf53x_cache_init(void) 82void __init bfin_cache_init(void)
81{ 83{
82#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) 84#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
83 generate_cpl_tables(); 85 generate_cplb_tables();
84#endif 86#endif
85 87
86#ifdef CONFIG_BFIN_ICACHE 88#ifdef CONFIG_BFIN_ICACHE
@@ -100,7 +102,7 @@ void __init bf53x_cache_init(void)
100#endif 102#endif
101} 103}
102 104
103void __init bf53x_relocate_l1_mem(void) 105void __init bfin_relocate_l1_mem(void)
104{ 106{
105 unsigned long l1_code_length; 107 unsigned long l1_code_length;
106 unsigned long l1_data_a_length; 108 unsigned long l1_data_a_length;
@@ -410,7 +412,7 @@ static __init void parse_cmdline_early(char *cmdline_p)
410 * [_rambase, _ramstart]: kernel image 412 * [_rambase, _ramstart]: kernel image
411 * [memory_start, memory_end]: dynamic memory managed by kernel 413 * [memory_start, memory_end]: dynamic memory managed by kernel
412 * [memory_end, _ramend]: reserved memory 414 * [memory_end, _ramend]: reserved memory
413 * [meory_mtd_start(memory_end), 415 * [memory_mtd_start(memory_end),
414 * memory_mtd_start + mtd_size]: rootfs (if any) 416 * memory_mtd_start + mtd_size]: rootfs (if any)
415 * [_ramend - DMA_UNCACHED_REGION, 417 * [_ramend - DMA_UNCACHED_REGION,
416 * _ramend]: uncached DMA region 418 * _ramend]: uncached DMA region
@@ -782,16 +784,25 @@ void __init setup_arch(char **cmdline_p)
782 784
783 _bfin_swrst = bfin_read_SWRST(); 785 _bfin_swrst = bfin_read_SWRST();
784 786
785 /* If we double fault, reset the system - otherwise we hang forever */ 787#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
786 bfin_write_SWRST(DOUBLE_FAULT); 788 bfin_write_SWRST(_bfin_swrst & ~DOUBLE_FAULT);
789#endif
790#ifdef CONFIG_DEBUG_DOUBLEFAULT_RESET
791 bfin_write_SWRST(_bfin_swrst | DOUBLE_FAULT);
792#endif
787 793
788 if (_bfin_swrst & RESET_DOUBLE) 794 if (_bfin_swrst & RESET_DOUBLE) {
789 /* 795 printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n");
790 * don't decode the address, since you don't know if this 796#ifdef CONFIG_DEBUG_DOUBLEFAULT
791 * kernel's symbol map is the same as the crashing kernel 797 /* We assume the crashing kernel, and the current symbol table match */
792 */ 798 printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
793 printk(KERN_INFO "Recovering from Double Fault event at %pF\n", __retx); 799 (int)init_saved_seqstat & SEQSTAT_EXCAUSE, init_saved_retx);
794 else if (_bfin_swrst & RESET_WDOG) 800 printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr);
801 printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr);
802#endif
803 printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
804 init_retx);
805 } else if (_bfin_swrst & RESET_WDOG)
795 printk(KERN_INFO "Recovering from Watchdog event\n"); 806 printk(KERN_INFO "Recovering from Watchdog event\n");
796 else if (_bfin_swrst & RESET_SOFTWARE) 807 else if (_bfin_swrst & RESET_SOFTWARE)
797 printk(KERN_NOTICE "Reset caused by Software reset\n"); 808 printk(KERN_NOTICE "Reset caused by Software reset\n");
@@ -803,17 +814,24 @@ void __init setup_arch(char **cmdline_p)
803 printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU); 814 printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU);
804 else 815 else
805 printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid()); 816 printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
806 if (bfin_revid() != bfin_compiled_revid()) { 817
807 if (bfin_compiled_revid() == -1) 818 if (unlikely(CPUID != bfin_cpuid()))
808 printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n", 819 printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
809 bfin_revid()); 820 CPU, bfin_cpuid(), bfin_revid());
810 else if (bfin_compiled_revid() != 0xffff) 821 else {
811 printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n", 822 if (bfin_revid() != bfin_compiled_revid()) {
812 bfin_compiled_revid(), bfin_revid()); 823 if (bfin_compiled_revid() == -1)
824 printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n",
825 bfin_revid());
826 else if (bfin_compiled_revid() != 0xffff)
827 printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
828 bfin_compiled_revid(), bfin_revid());
829 }
830 if (bfin_revid() <= CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX)
831 printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
832 CPU, bfin_revid());
813 } 833 }
814 if (bfin_revid() < SUPPORTED_REVID) 834
815 printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
816 CPU, bfin_revid());
817 printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n"); 835 printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
818 836
819 printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n", 837 printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
@@ -850,7 +868,7 @@ void __init setup_arch(char **cmdline_p)
850 != SAFE_USER_INSTRUCTION - FIXED_CODE_START); 868 != SAFE_USER_INSTRUCTION - FIXED_CODE_START);
851 869
852 init_exception_vectors(); 870 init_exception_vectors();
853 bf53x_cache_init(); 871 bfin_cache_init();
854} 872}
855 873
856static int __init topology_init(void) 874static int __init topology_init(void)
@@ -986,13 +1004,18 @@ static int show_cpuinfo(struct seq_file *m, void *v)
986 } 1004 }
987 1005
988 seq_printf(m, "processor\t: %d\n" 1006 seq_printf(m, "processor\t: %d\n"
989 "vendor_id\t: %s\n" 1007 "vendor_id\t: %s\n",
990 "cpu family\t: 0x%x\n" 1008 *(unsigned int *)v,
991 "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n" 1009 vendor);
1010
1011 if (CPUID == bfin_cpuid())
1012 seq_printf(m, "cpu family\t: 0x%04x\n", CPUID);
1013 else
1014 seq_printf(m, "cpu family\t: Compiled for:0x%04x, running on:0x%04x\n",
1015 CPUID, bfin_cpuid());
1016
1017 seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n"
992 "stepping\t: %d\n", 1018 "stepping\t: %d\n",
993 0,
994 vendor,
995 (bfin_read_CHIPID() & CHIPID_FAMILY),
996 cpu, cclk/1000000, sclk/1000000, 1019 cpu, cclk/1000000, sclk/1000000,
997#ifdef CONFIG_MPU 1020#ifdef CONFIG_MPU
998 "mpu on", 1021 "mpu on",
@@ -1038,7 +1061,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
1038 if ((bfin_read_DMEM_CONTROL() & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE)) 1061 if ((bfin_read_DMEM_CONTROL() & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE))
1039 dcache_size = 0; 1062 dcache_size = 0;
1040 1063
1041 if ((bfin_read_IMEM_CONTROL() & (IMC | ENICPLB)) == (IMC | ENICPLB)) 1064 if ((bfin_read_IMEM_CONTROL() & (IMC | ENICPLB)) != (IMC | ENICPLB))
1042 icache_size = 0; 1065 icache_size = 0;
1043 1066
1044 seq_printf(m, "cache size\t: %d KB(L1 icache) " 1067 seq_printf(m, "cache size\t: %d KB(L1 icache) "
@@ -1127,12 +1150,18 @@ static int show_cpuinfo(struct seq_file *m, void *v)
1127 1150
1128static void *c_start(struct seq_file *m, loff_t *pos) 1151static void *c_start(struct seq_file *m, loff_t *pos)
1129{ 1152{
1130 return *pos < NR_CPUS ? ((void *)0x12345678) : NULL; 1153 if (*pos == 0)
1154 *pos = first_cpu(cpu_online_map);
1155 if (*pos >= num_online_cpus())
1156 return NULL;
1157
1158 return pos;
1131} 1159}
1132 1160
1133static void *c_next(struct seq_file *m, void *v, loff_t *pos) 1161static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1134{ 1162{
1135 ++*pos; 1163 *pos = next_cpu(*pos, cpu_online_map);
1164
1136 return c_start(m, pos); 1165 return c_start(m, pos);
1137} 1166}
1138 1167
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
index 9a9d5083acfd..1aa2c788e228 100644
--- a/arch/blackfin/kernel/traps.c
+++ b/arch/blackfin/kernel/traps.c
@@ -34,20 +34,19 @@
34#include <linux/fs.h> 34#include <linux/fs.h>
35#include <asm/traps.h> 35#include <asm/traps.h>
36#include <asm/cacheflush.h> 36#include <asm/cacheflush.h>
37#include <asm/cplb.h>
37#include <asm/blackfin.h> 38#include <asm/blackfin.h>
38#include <asm/irq_handler.h> 39#include <asm/irq_handler.h>
39#include <linux/irq.h> 40#include <linux/irq.h>
40#include <asm/trace.h> 41#include <asm/trace.h>
41#include <asm/fixed_code.h> 42#include <asm/fixed_code.h>
42#include <asm/dma.h>
43 43
44#ifdef CONFIG_KGDB 44#ifdef CONFIG_KGDB
45# include <linux/debugger.h>
46# include <linux/kgdb.h> 45# include <linux/kgdb.h>
47 46
48# define CHK_DEBUGGER_TRAP() \ 47# define CHK_DEBUGGER_TRAP() \
49 do { \ 48 do { \
50 CHK_DEBUGGER(trapnr, sig, info.si_code, fp, ); \ 49 kgdb_handle_exception(trapnr, sig, info.si_code, fp); \
51 } while (0) 50 } while (0)
52# define CHK_DEBUGGER_TRAP_MAYBE() \ 51# define CHK_DEBUGGER_TRAP_MAYBE() \
53 do { \ 52 do { \
@@ -59,6 +58,15 @@
59# define CHK_DEBUGGER_TRAP_MAYBE() do { } while (0) 58# define CHK_DEBUGGER_TRAP_MAYBE() do { } while (0)
60#endif 59#endif
61 60
61
62#ifdef CONFIG_VERBOSE_DEBUG
63#define verbose_printk(fmt, arg...) \
64 printk(fmt, ##arg)
65#else
66#define verbose_printk(fmt, arg...) \
67 ({ if (0) printk(fmt, ##arg); 0; })
68#endif
69
62/* Initiate the event table handler */ 70/* Initiate the event table handler */
63void __init trap_init(void) 71void __init trap_init(void)
64{ 72{
@@ -67,10 +75,19 @@ void __init trap_init(void)
67 CSYNC(); 75 CSYNC();
68} 76}
69 77
70unsigned long saved_icplb_fault_addr, saved_dcplb_fault_addr; 78/*
79 * Used to save the RETX, SEQSTAT, I/D CPLB FAULT ADDR
80 * values across the transition from exception to IRQ5.
81 * We put these in L1, so they are going to be in a valid
82 * location during exception context
83 */
84__attribute__((l1_data))
85unsigned long saved_retx, saved_seqstat,
86 saved_icplb_fault_addr, saved_dcplb_fault_addr;
71 87
72static void decode_address(char *buf, unsigned long address) 88static void decode_address(char *buf, unsigned long address)
73{ 89{
90#ifdef CONFIG_DEBUG_VERBOSE
74 struct vm_list_struct *vml; 91 struct vm_list_struct *vml;
75 struct task_struct *p; 92 struct task_struct *p;
76 struct mm_struct *mm; 93 struct mm_struct *mm;
@@ -178,16 +195,39 @@ static void decode_address(char *buf, unsigned long address)
178 195
179done: 196done:
180 write_unlock_irqrestore(&tasklist_lock, flags); 197 write_unlock_irqrestore(&tasklist_lock, flags);
198#else
199 sprintf(buf, " ");
200#endif
181} 201}
182 202
183asmlinkage void double_fault_c(struct pt_regs *fp) 203asmlinkage void double_fault_c(struct pt_regs *fp)
184{ 204{
185 console_verbose(); 205 console_verbose();
186 oops_in_progress = 1; 206 oops_in_progress = 1;
207#ifdef CONFIG_DEBUG_VERBOSE
187 printk(KERN_EMERG "\n" KERN_EMERG "Double Fault\n"); 208 printk(KERN_EMERG "\n" KERN_EMERG "Double Fault\n");
188 dump_bfin_process(fp); 209#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
189 dump_bfin_mem(fp); 210 if (((long)fp->seqstat & SEQSTAT_EXCAUSE) == VEC_UNCOV) {
190 show_regs(fp); 211 char buf[150];
212 decode_address(buf, saved_retx);
213 printk(KERN_EMERG "While handling exception (EXCAUSE = 0x%x) at %s:\n",
214 (int)saved_seqstat & SEQSTAT_EXCAUSE, buf);
215 decode_address(buf, saved_dcplb_fault_addr);
216 printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %s\n", buf);
217 decode_address(buf, saved_icplb_fault_addr);
218 printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %s\n", buf);
219
220 decode_address(buf, fp->retx);
221 printk(KERN_NOTICE "The instruction at %s caused a double exception\n",
222 buf);
223 } else
224#endif
225 {
226 dump_bfin_process(fp);
227 dump_bfin_mem(fp);
228 show_regs(fp);
229 }
230#endif
191 panic("Double Fault - unrecoverable event\n"); 231 panic("Double Fault - unrecoverable event\n");
192 232
193} 233}
@@ -259,34 +299,42 @@ asmlinkage void trap_c(struct pt_regs *fp)
259 return; 299 return;
260 else 300 else
261 break; 301 break;
302 /* 0x03 - User Defined, userspace stack overflow */
303 case VEC_EXCPT03:
304 info.si_code = SEGV_STACKFLOW;
305 sig = SIGSEGV;
306 verbose_printk(KERN_NOTICE EXC_0x03(KERN_NOTICE));
307 CHK_DEBUGGER_TRAP_MAYBE();
308 break;
309 /* 0x02 - KGDB initial connection and break signal trap */
310 case VEC_EXCPT02:
262#ifdef CONFIG_KGDB 311#ifdef CONFIG_KGDB
263 case VEC_EXCPT02 : /* gdb connection */
264 info.si_code = TRAP_ILLTRAP; 312 info.si_code = TRAP_ILLTRAP;
265 sig = SIGTRAP; 313 sig = SIGTRAP;
266 CHK_DEBUGGER_TRAP(); 314 CHK_DEBUGGER_TRAP();
267 return; 315 return;
268#else
269 /* 0x02 - User Defined, Caught by default */
270#endif 316#endif
271 /* 0x03 - User Defined, userspace stack overflow */ 317 /* 0x04 - User Defined */
272 case VEC_EXCPT03: 318 /* 0x05 - User Defined */
273 info.si_code = SEGV_STACKFLOW; 319 /* 0x06 - User Defined */
274 sig = SIGSEGV; 320 /* 0x07 - User Defined */
275 printk(KERN_NOTICE EXC_0x03(KERN_NOTICE)); 321 /* 0x08 - User Defined */
276 CHK_DEBUGGER_TRAP(); 322 /* 0x09 - User Defined */
323 /* 0x0A - User Defined */
324 /* 0x0B - User Defined */
325 /* 0x0C - User Defined */
326 /* 0x0D - User Defined */
327 /* 0x0E - User Defined */
328 /* 0x0F - User Defined */
329 /* If we got here, it is most likely that someone was trying to use a
330 * custom exception handler, and it is not actually installed properly
331 */
332 case VEC_EXCPT04 ... VEC_EXCPT15:
333 info.si_code = ILL_ILLPARAOP;
334 sig = SIGILL;
335 verbose_printk(KERN_NOTICE EXC_0x04(KERN_NOTICE));
336 CHK_DEBUGGER_TRAP_MAYBE();
277 break; 337 break;
278 /* 0x04 - User Defined, Caught by default */
279 /* 0x05 - User Defined, Caught by default */
280 /* 0x06 - User Defined, Caught by default */
281 /* 0x07 - User Defined, Caught by default */
282 /* 0x08 - User Defined, Caught by default */
283 /* 0x09 - User Defined, Caught by default */
284 /* 0x0A - User Defined, Caught by default */
285 /* 0x0B - User Defined, Caught by default */
286 /* 0x0C - User Defined, Caught by default */
287 /* 0x0D - User Defined, Caught by default */
288 /* 0x0E - User Defined, Caught by default */
289 /* 0x0F - User Defined, Caught by default */
290 /* 0x10 HW Single step, handled here */ 338 /* 0x10 HW Single step, handled here */
291 case VEC_STEP: 339 case VEC_STEP:
292 info.si_code = TRAP_STEP; 340 info.si_code = TRAP_STEP;
@@ -301,8 +349,8 @@ asmlinkage void trap_c(struct pt_regs *fp)
301 case VEC_OVFLOW: 349 case VEC_OVFLOW:
302 info.si_code = TRAP_TRACEFLOW; 350 info.si_code = TRAP_TRACEFLOW;
303 sig = SIGTRAP; 351 sig = SIGTRAP;
304 printk(KERN_NOTICE EXC_0x11(KERN_NOTICE)); 352 verbose_printk(KERN_NOTICE EXC_0x11(KERN_NOTICE));
305 CHK_DEBUGGER_TRAP(); 353 CHK_DEBUGGER_TRAP_MAYBE();
306 break; 354 break;
307 /* 0x12 - Reserved, Caught by default */ 355 /* 0x12 - Reserved, Caught by default */
308 /* 0x13 - Reserved, Caught by default */ 356 /* 0x13 - Reserved, Caught by default */
@@ -323,44 +371,43 @@ asmlinkage void trap_c(struct pt_regs *fp)
323 case VEC_UNDEF_I: 371 case VEC_UNDEF_I:
324 info.si_code = ILL_ILLOPC; 372 info.si_code = ILL_ILLOPC;
325 sig = SIGILL; 373 sig = SIGILL;
326 printk(KERN_NOTICE EXC_0x21(KERN_NOTICE)); 374 verbose_printk(KERN_NOTICE EXC_0x21(KERN_NOTICE));
327 CHK_DEBUGGER_TRAP(); 375 CHK_DEBUGGER_TRAP_MAYBE();
328 break; 376 break;
329 /* 0x22 - Illegal Instruction Combination, handled here */ 377 /* 0x22 - Illegal Instruction Combination, handled here */
330 case VEC_ILGAL_I: 378 case VEC_ILGAL_I:
331 info.si_code = ILL_ILLPARAOP; 379 info.si_code = ILL_ILLPARAOP;
332 sig = SIGILL; 380 sig = SIGILL;
333 printk(KERN_NOTICE EXC_0x22(KERN_NOTICE)); 381 verbose_printk(KERN_NOTICE EXC_0x22(KERN_NOTICE));
334 CHK_DEBUGGER_TRAP(); 382 CHK_DEBUGGER_TRAP_MAYBE();
335 break; 383 break;
336 /* 0x23 - Data CPLB protection violation, handled here */ 384 /* 0x23 - Data CPLB protection violation, handled here */
337 case VEC_CPLB_VL: 385 case VEC_CPLB_VL:
338 info.si_code = ILL_CPLB_VI; 386 info.si_code = ILL_CPLB_VI;
339 sig = SIGBUS; 387 sig = SIGBUS;
340 printk(KERN_NOTICE EXC_0x23(KERN_NOTICE)); 388 verbose_printk(KERN_NOTICE EXC_0x23(KERN_NOTICE));
341 CHK_DEBUGGER_TRAP(); 389 CHK_DEBUGGER_TRAP_MAYBE();
342 break; 390 break;
343 /* 0x24 - Data access misaligned, handled here */ 391 /* 0x24 - Data access misaligned, handled here */
344 case VEC_MISALI_D: 392 case VEC_MISALI_D:
345 info.si_code = BUS_ADRALN; 393 info.si_code = BUS_ADRALN;
346 sig = SIGBUS; 394 sig = SIGBUS;
347 printk(KERN_NOTICE EXC_0x24(KERN_NOTICE)); 395 verbose_printk(KERN_NOTICE EXC_0x24(KERN_NOTICE));
348 CHK_DEBUGGER_TRAP(); 396 CHK_DEBUGGER_TRAP_MAYBE();
349 break; 397 break;
350 /* 0x25 - Unrecoverable Event, handled here */ 398 /* 0x25 - Unrecoverable Event, handled here */
351 case VEC_UNCOV: 399 case VEC_UNCOV:
352 info.si_code = ILL_ILLEXCPT; 400 info.si_code = ILL_ILLEXCPT;
353 sig = SIGILL; 401 sig = SIGILL;
354 printk(KERN_NOTICE EXC_0x25(KERN_NOTICE)); 402 verbose_printk(KERN_NOTICE EXC_0x25(KERN_NOTICE));
355 CHK_DEBUGGER_TRAP(); 403 CHK_DEBUGGER_TRAP_MAYBE();
356 break; 404 break;
357 /* 0x26 - Data CPLB Miss, normal case is handled in _cplb_hdr, 405 /* 0x26 - Data CPLB Miss, normal case is handled in _cplb_hdr,
358 error case is handled here */ 406 error case is handled here */
359 case VEC_CPLB_M: 407 case VEC_CPLB_M:
360 info.si_code = BUS_ADRALN; 408 info.si_code = BUS_ADRALN;
361 sig = SIGBUS; 409 sig = SIGBUS;
362 printk(KERN_NOTICE EXC_0x26(KERN_NOTICE)); 410 verbose_printk(KERN_NOTICE EXC_0x26(KERN_NOTICE));
363 CHK_DEBUGGER_TRAP();
364 break; 411 break;
365 /* 0x27 - Data CPLB Multiple Hits - Linux Trap Zero, handled here */ 412 /* 0x27 - Data CPLB Multiple Hits - Linux Trap Zero, handled here */
366 case VEC_CPLB_MHIT: 413 case VEC_CPLB_MHIT:
@@ -368,11 +415,11 @@ asmlinkage void trap_c(struct pt_regs *fp)
368 sig = SIGSEGV; 415 sig = SIGSEGV;
369#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO 416#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
370 if (saved_dcplb_fault_addr < FIXED_CODE_START) 417 if (saved_dcplb_fault_addr < FIXED_CODE_START)
371 printk(KERN_NOTICE "NULL pointer access\n"); 418 verbose_printk(KERN_NOTICE "NULL pointer access\n");
372 else 419 else
373#endif 420#endif
374 printk(KERN_NOTICE EXC_0x27(KERN_NOTICE)); 421 verbose_printk(KERN_NOTICE EXC_0x27(KERN_NOTICE));
375 CHK_DEBUGGER_TRAP(); 422 CHK_DEBUGGER_TRAP_MAYBE();
376 break; 423 break;
377 /* 0x28 - Emulation Watchpoint, handled here */ 424 /* 0x28 - Emulation Watchpoint, handled here */
378 case VEC_WATCH: 425 case VEC_WATCH:
@@ -390,8 +437,8 @@ asmlinkage void trap_c(struct pt_regs *fp)
390 case VEC_ISTRU_VL: /* ADSP-BF535 only (MH) */ 437 case VEC_ISTRU_VL: /* ADSP-BF535 only (MH) */
391 info.si_code = BUS_OPFETCH; 438 info.si_code = BUS_OPFETCH;
392 sig = SIGBUS; 439 sig = SIGBUS;
393 printk(KERN_NOTICE "BF535: VEC_ISTRU_VL\n"); 440 verbose_printk(KERN_NOTICE "BF535: VEC_ISTRU_VL\n");
394 CHK_DEBUGGER_TRAP(); 441 CHK_DEBUGGER_TRAP_MAYBE();
395 break; 442 break;
396#else 443#else
397 /* 0x29 - Reserved, Caught by default */ 444 /* 0x29 - Reserved, Caught by default */
@@ -400,22 +447,21 @@ asmlinkage void trap_c(struct pt_regs *fp)
400 case VEC_MISALI_I: 447 case VEC_MISALI_I:
401 info.si_code = BUS_ADRALN; 448 info.si_code = BUS_ADRALN;
402 sig = SIGBUS; 449 sig = SIGBUS;
403 printk(KERN_NOTICE EXC_0x2A(KERN_NOTICE)); 450 verbose_printk(KERN_NOTICE EXC_0x2A(KERN_NOTICE));
404 CHK_DEBUGGER_TRAP(); 451 CHK_DEBUGGER_TRAP_MAYBE();
405 break; 452 break;
406 /* 0x2B - Instruction CPLB protection violation, handled here */ 453 /* 0x2B - Instruction CPLB protection violation, handled here */
407 case VEC_CPLB_I_VL: 454 case VEC_CPLB_I_VL:
408 info.si_code = ILL_CPLB_VI; 455 info.si_code = ILL_CPLB_VI;
409 sig = SIGBUS; 456 sig = SIGBUS;
410 printk(KERN_NOTICE EXC_0x2B(KERN_NOTICE)); 457 verbose_printk(KERN_NOTICE EXC_0x2B(KERN_NOTICE));
411 CHK_DEBUGGER_TRAP(); 458 CHK_DEBUGGER_TRAP_MAYBE();
412 break; 459 break;
413 /* 0x2C - Instruction CPLB miss, handled in _cplb_hdr */ 460 /* 0x2C - Instruction CPLB miss, handled in _cplb_hdr */
414 case VEC_CPLB_I_M: 461 case VEC_CPLB_I_M:
415 info.si_code = ILL_CPLB_MISS; 462 info.si_code = ILL_CPLB_MISS;
416 sig = SIGBUS; 463 sig = SIGBUS;
417 printk(KERN_NOTICE EXC_0x2C(KERN_NOTICE)); 464 verbose_printk(KERN_NOTICE EXC_0x2C(KERN_NOTICE));
418 CHK_DEBUGGER_TRAP();
419 break; 465 break;
420 /* 0x2D - Instruction CPLB Multiple Hits, handled here */ 466 /* 0x2D - Instruction CPLB Multiple Hits, handled here */
421 case VEC_CPLB_I_MHIT: 467 case VEC_CPLB_I_MHIT:
@@ -423,18 +469,18 @@ asmlinkage void trap_c(struct pt_regs *fp)
423 sig = SIGSEGV; 469 sig = SIGSEGV;
424#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO 470#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
425 if (saved_icplb_fault_addr < FIXED_CODE_START) 471 if (saved_icplb_fault_addr < FIXED_CODE_START)
426 printk(KERN_NOTICE "Jump to NULL address\n"); 472 verbose_printk(KERN_NOTICE "Jump to NULL address\n");
427 else 473 else
428#endif 474#endif
429 printk(KERN_NOTICE EXC_0x2D(KERN_NOTICE)); 475 verbose_printk(KERN_NOTICE EXC_0x2D(KERN_NOTICE));
430 CHK_DEBUGGER_TRAP(); 476 CHK_DEBUGGER_TRAP_MAYBE();
431 break; 477 break;
432 /* 0x2E - Illegal use of Supervisor Resource, handled here */ 478 /* 0x2E - Illegal use of Supervisor Resource, handled here */
433 case VEC_ILL_RES: 479 case VEC_ILL_RES:
434 info.si_code = ILL_PRVOPC; 480 info.si_code = ILL_PRVOPC;
435 sig = SIGILL; 481 sig = SIGILL;
436 printk(KERN_NOTICE EXC_0x2E(KERN_NOTICE)); 482 verbose_printk(KERN_NOTICE EXC_0x2E(KERN_NOTICE));
437 CHK_DEBUGGER_TRAP(); 483 CHK_DEBUGGER_TRAP_MAYBE();
438 break; 484 break;
439 /* 0x2F - Reserved, Caught by default */ 485 /* 0x2F - Reserved, Caught by default */
440 /* 0x30 - Reserved, Caught by default */ 486 /* 0x30 - Reserved, Caught by default */
@@ -461,17 +507,17 @@ asmlinkage void trap_c(struct pt_regs *fp)
461 case (SEQSTAT_HWERRCAUSE_SYSTEM_MMR): 507 case (SEQSTAT_HWERRCAUSE_SYSTEM_MMR):
462 info.si_code = BUS_ADRALN; 508 info.si_code = BUS_ADRALN;
463 sig = SIGBUS; 509 sig = SIGBUS;
464 printk(KERN_NOTICE HWC_x2(KERN_NOTICE)); 510 verbose_printk(KERN_NOTICE HWC_x2(KERN_NOTICE));
465 break; 511 break;
466 /* External Memory Addressing Error */ 512 /* External Memory Addressing Error */
467 case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR): 513 case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR):
468 info.si_code = BUS_ADRERR; 514 info.si_code = BUS_ADRERR;
469 sig = SIGBUS; 515 sig = SIGBUS;
470 printk(KERN_NOTICE HWC_x3(KERN_NOTICE)); 516 verbose_printk(KERN_NOTICE HWC_x3(KERN_NOTICE));
471 break; 517 break;
472 /* Performance Monitor Overflow */ 518 /* Performance Monitor Overflow */
473 case (SEQSTAT_HWERRCAUSE_PERF_FLOW): 519 case (SEQSTAT_HWERRCAUSE_PERF_FLOW):
474 printk(KERN_NOTICE HWC_x12(KERN_NOTICE)); 520 verbose_printk(KERN_NOTICE HWC_x12(KERN_NOTICE));
475 break; 521 break;
476 /* RAISE 5 instruction */ 522 /* RAISE 5 instruction */
477 case (SEQSTAT_HWERRCAUSE_RAISE_5): 523 case (SEQSTAT_HWERRCAUSE_RAISE_5):
@@ -481,21 +527,25 @@ asmlinkage void trap_c(struct pt_regs *fp)
481 printk(KERN_NOTICE HWC_default(KERN_NOTICE)); 527 printk(KERN_NOTICE HWC_default(KERN_NOTICE));
482 break; 528 break;
483 } 529 }
484 CHK_DEBUGGER_TRAP(); 530 CHK_DEBUGGER_TRAP_MAYBE();
485 break; 531 break;
532 /*
533 * We should be handling all known exception types above,
534 * if we get here we hit a reserved one, so panic
535 */
486 default: 536 default:
487 info.si_code = TRAP_ILLTRAP; 537 oops_in_progress = 1;
488 sig = SIGTRAP; 538 info.si_code = ILL_ILLPARAOP;
489 printk(KERN_EMERG "Caught Unhandled Exception, code = %08lx\n", 539 sig = SIGILL;
540 verbose_printk(KERN_EMERG "Caught Unhandled Exception, code = %08lx\n",
490 (fp->seqstat & SEQSTAT_EXCAUSE)); 541 (fp->seqstat & SEQSTAT_EXCAUSE));
491 CHK_DEBUGGER_TRAP(); 542 CHK_DEBUGGER_TRAP_MAYBE();
492 break; 543 break;
493 } 544 }
494 545
495 BUG_ON(sig == 0); 546 BUG_ON(sig == 0);
496 547
497 if (sig != SIGTRAP) { 548 if (sig != SIGTRAP) {
498 unsigned long *stack;
499 dump_bfin_process(fp); 549 dump_bfin_process(fp);
500 dump_bfin_mem(fp); 550 dump_bfin_mem(fp);
501 show_regs(fp); 551 show_regs(fp);
@@ -503,7 +553,7 @@ asmlinkage void trap_c(struct pt_regs *fp)
503 /* Print out the trace buffer if it makes sense */ 553 /* Print out the trace buffer if it makes sense */
504#ifndef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE 554#ifndef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
505 if (trapnr == VEC_CPLB_I_M || trapnr == VEC_CPLB_M) 555 if (trapnr == VEC_CPLB_I_M || trapnr == VEC_CPLB_M)
506 printk(KERN_NOTICE "No trace since you do not have " 556 verbose_printk(KERN_NOTICE "No trace since you do not have "
507 "CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE enabled\n" 557 "CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE enabled\n"
508 KERN_NOTICE "\n"); 558 KERN_NOTICE "\n");
509 else 559 else
@@ -512,20 +562,22 @@ asmlinkage void trap_c(struct pt_regs *fp)
512 562
513 if (oops_in_progress) { 563 if (oops_in_progress) {
514 /* Dump the current kernel stack */ 564 /* Dump the current kernel stack */
515 printk(KERN_NOTICE "\n" KERN_NOTICE "Kernel Stack\n"); 565 verbose_printk(KERN_NOTICE "\n" KERN_NOTICE "Kernel Stack\n");
516 show_stack(current, NULL); 566 show_stack(current, NULL);
517
518 print_modules(); 567 print_modules();
519#ifndef CONFIG_ACCESS_CHECK 568#ifndef CONFIG_ACCESS_CHECK
520 printk(KERN_EMERG "Please turn on " 569 verbose_printk(KERN_EMERG "Please turn on "
521 "CONFIG_ACCESS_CHECK\n"); 570 "CONFIG_ACCESS_CHECK\n");
522#endif 571#endif
523 panic("Kernel exception"); 572 panic("Kernel exception");
524 } else { 573 } else {
574#ifdef CONFIG_VERBOSE_DEBUG
575 unsigned long *stack;
525 /* Dump the user space stack */ 576 /* Dump the user space stack */
526 stack = (unsigned long *)rdusp(); 577 stack = (unsigned long *)rdusp();
527 printk(KERN_NOTICE "Userspace Stack\n"); 578 verbose_printk(KERN_NOTICE "Userspace Stack\n");
528 show_stack(NULL, stack); 579 show_stack(NULL, stack);
580#endif
529 } 581 }
530 } 582 }
531 583
@@ -546,7 +598,7 @@ asmlinkage void trap_c(struct pt_regs *fp)
546 * Similar to get_user, do some address checking, then dereference 598 * Similar to get_user, do some address checking, then dereference
547 * Return true on sucess, false on bad address 599 * Return true on sucess, false on bad address
548 */ 600 */
549bool get_instruction(unsigned short *val, unsigned short *address) 601static bool get_instruction(unsigned short *val, unsigned short *address)
550{ 602{
551 603
552 unsigned long addr; 604 unsigned long addr;
@@ -592,7 +644,7 @@ bool get_instruction(unsigned short *val, unsigned short *address)
592 644
593#if L1_CODE_LENGTH != 0 645#if L1_CODE_LENGTH != 0
594 if (addr >= L1_CODE_START && (addr + 2) <= (L1_CODE_START + L1_CODE_LENGTH)) { 646 if (addr >= L1_CODE_START && (addr + 2) <= (L1_CODE_START + L1_CODE_LENGTH)) {
595 dma_memcpy(val, address, 2); 647 isram_memcpy(val, address, 2);
596 return true; 648 return true;
597 } 649 }
598#endif 650#endif
@@ -607,45 +659,48 @@ bool get_instruction(unsigned short *val, unsigned short *address)
607 * These are the normal instructions which cause change of flow, which 659 * These are the normal instructions which cause change of flow, which
608 * would be at the source of the trace buffer 660 * would be at the source of the trace buffer
609 */ 661 */
610void decode_instruction(unsigned short *address) 662#ifdef CONFIG_DEBUG_VERBOSE
663static void decode_instruction(unsigned short *address)
611{ 664{
612 unsigned short opcode; 665 unsigned short opcode;
613 666
614 if (get_instruction(&opcode, address)) { 667 if (get_instruction(&opcode, address)) {
615 if (opcode == 0x0010) 668 if (opcode == 0x0010)
616 printk("RTS"); 669 verbose_printk("RTS");
617 else if (opcode == 0x0011) 670 else if (opcode == 0x0011)
618 printk("RTI"); 671 verbose_printk("RTI");
619 else if (opcode == 0x0012) 672 else if (opcode == 0x0012)
620 printk("RTX"); 673 verbose_printk("RTX");
621 else if (opcode >= 0x0050 && opcode <= 0x0057) 674 else if (opcode >= 0x0050 && opcode <= 0x0057)
622 printk("JUMP (P%i)", opcode & 7); 675 verbose_printk("JUMP (P%i)", opcode & 7);
623 else if (opcode >= 0x0060 && opcode <= 0x0067) 676 else if (opcode >= 0x0060 && opcode <= 0x0067)
624 printk("CALL (P%i)", opcode & 7); 677 verbose_printk("CALL (P%i)", opcode & 7);
625 else if (opcode >= 0x0070 && opcode <= 0x0077) 678 else if (opcode >= 0x0070 && opcode <= 0x0077)
626 printk("CALL (PC+P%i)", opcode & 7); 679 verbose_printk("CALL (PC+P%i)", opcode & 7);
627 else if (opcode >= 0x0080 && opcode <= 0x0087) 680 else if (opcode >= 0x0080 && opcode <= 0x0087)
628 printk("JUMP (PC+P%i)", opcode & 7); 681 verbose_printk("JUMP (PC+P%i)", opcode & 7);
629 else if ((opcode >= 0x1000 && opcode <= 0x13FF) || (opcode >= 0x1800 && opcode <= 0x1BFF)) 682 else if ((opcode >= 0x1000 && opcode <= 0x13FF) || (opcode >= 0x1800 && opcode <= 0x1BFF))
630 printk("IF !CC JUMP"); 683 verbose_printk("IF !CC JUMP");
631 else if ((opcode >= 0x1400 && opcode <= 0x17ff) || (opcode >= 0x1c00 && opcode <= 0x1fff)) 684 else if ((opcode >= 0x1400 && opcode <= 0x17ff) || (opcode >= 0x1c00 && opcode <= 0x1fff))
632 printk("IF CC JUMP"); 685 verbose_printk("IF CC JUMP");
633 else if (opcode >= 0x2000 && opcode <= 0x2fff) 686 else if (opcode >= 0x2000 && opcode <= 0x2fff)
634 printk("JUMP.S"); 687 verbose_printk("JUMP.S");
635 else if (opcode >= 0xe080 && opcode <= 0xe0ff) 688 else if (opcode >= 0xe080 && opcode <= 0xe0ff)
636 printk("LSETUP"); 689 verbose_printk("LSETUP");
637 else if (opcode >= 0xe200 && opcode <= 0xe2ff) 690 else if (opcode >= 0xe200 && opcode <= 0xe2ff)
638 printk("JUMP.L"); 691 verbose_printk("JUMP.L");
639 else if (opcode >= 0xe300 && opcode <= 0xe3ff) 692 else if (opcode >= 0xe300 && opcode <= 0xe3ff)
640 printk("CALL pcrel"); 693 verbose_printk("CALL pcrel");
641 else 694 else
642 printk("0x%04x", opcode); 695 verbose_printk("0x%04x", opcode);
643 } 696 }
644 697
645} 698}
699#endif
646 700
647void dump_bfin_trace_buffer(void) 701void dump_bfin_trace_buffer(void)
648{ 702{
703#ifdef CONFIG_DEBUG_VERBOSE
649#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON 704#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
650 int tflags, i = 0; 705 int tflags, i = 0;
651 char buf[150]; 706 char buf[150];
@@ -701,6 +756,7 @@ void dump_bfin_trace_buffer(void)
701 756
702 trace_buffer_restore(tflags); 757 trace_buffer_restore(tflags);
703#endif 758#endif
759#endif
704} 760}
705EXPORT_SYMBOL(dump_bfin_trace_buffer); 761EXPORT_SYMBOL(dump_bfin_trace_buffer);
706 762
@@ -708,7 +764,7 @@ EXPORT_SYMBOL(dump_bfin_trace_buffer);
708 * Checks to see if the address pointed to is either a 764 * Checks to see if the address pointed to is either a
709 * 16-bit CALL instruction, or a 32-bit CALL instruction 765 * 16-bit CALL instruction, or a 32-bit CALL instruction
710 */ 766 */
711bool is_bfin_call(unsigned short *addr) 767static bool is_bfin_call(unsigned short *addr)
712{ 768{
713 unsigned short opcode = 0, *ins_addr; 769 unsigned short opcode = 0, *ins_addr;
714 ins_addr = (unsigned short *)addr; 770 ins_addr = (unsigned short *)addr;
@@ -730,8 +786,10 @@ bool is_bfin_call(unsigned short *addr)
730 return false; 786 return false;
731 787
732} 788}
789
733void show_stack(struct task_struct *task, unsigned long *stack) 790void show_stack(struct task_struct *task, unsigned long *stack)
734{ 791{
792#ifdef CONFIG_PRINTK
735 unsigned int *addr, *endstack, *fp = 0, *frame; 793 unsigned int *addr, *endstack, *fp = 0, *frame;
736 unsigned short *ins_addr; 794 unsigned short *ins_addr;
737 char buf[150]; 795 char buf[150];
@@ -756,8 +814,10 @@ void show_stack(struct task_struct *task, unsigned long *stack)
756 } else 814 } else
757 endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack); 815 endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack);
758 816
817 printk(KERN_NOTICE "Stack info:\n");
759 decode_address(buf, (unsigned int)stack); 818 decode_address(buf, (unsigned int)stack);
760 printk(KERN_NOTICE "Stack info:\n" KERN_NOTICE " SP: [0x%p] %s\n", stack, buf); 819 printk(KERN_NOTICE " SP: [0x%p] %s\n", stack, buf);
820
761 addr = (unsigned int *)((unsigned int)stack & ~0x3F); 821 addr = (unsigned int *)((unsigned int)stack & ~0x3F);
762 822
763 /* First thing is to look for a frame pointer */ 823 /* First thing is to look for a frame pointer */
@@ -848,7 +908,7 @@ void show_stack(struct task_struct *task, unsigned long *stack)
848 if (!j) 908 if (!j)
849 printk("\n"); 909 printk("\n");
850 } 910 }
851 911#endif
852} 912}
853 913
854void dump_stack(void) 914void dump_stack(void)
@@ -866,38 +926,39 @@ EXPORT_SYMBOL(dump_stack);
866 926
867void dump_bfin_process(struct pt_regs *fp) 927void dump_bfin_process(struct pt_regs *fp)
868{ 928{
929#ifdef CONFIG_DEBUG_VERBOSE
869 /* We should be able to look at fp->ipend, but we don't push it on the 930 /* We should be able to look at fp->ipend, but we don't push it on the
870 * stack all the time, so do this until we fix that */ 931 * stack all the time, so do this until we fix that */
871 unsigned int context = bfin_read_IPEND(); 932 unsigned int context = bfin_read_IPEND();
872 933
873 if (oops_in_progress) 934 if (oops_in_progress)
874 printk(KERN_EMERG "Kernel OOPS in progress\n"); 935 verbose_printk(KERN_EMERG "Kernel OOPS in progress\n");
875 936
876 if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) 937 if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR)
877 printk(KERN_NOTICE "HW Error context\n"); 938 verbose_printk(KERN_NOTICE "HW Error context\n");
878 else if (context & 0x0020) 939 else if (context & 0x0020)
879 printk(KERN_NOTICE "Deferred Exception context\n"); 940 verbose_printk(KERN_NOTICE "Deferred Exception context\n");
880 else if (context & 0x3FC0) 941 else if (context & 0x3FC0)
881 printk(KERN_NOTICE "Interrupt context\n"); 942 verbose_printk(KERN_NOTICE "Interrupt context\n");
882 else if (context & 0x4000) 943 else if (context & 0x4000)
883 printk(KERN_NOTICE "Deferred Interrupt context\n"); 944 verbose_printk(KERN_NOTICE "Deferred Interrupt context\n");
884 else if (context & 0x8000) 945 else if (context & 0x8000)
885 printk(KERN_NOTICE "Kernel process context\n"); 946 verbose_printk(KERN_NOTICE "Kernel process context\n");
886 947
887 /* Because we are crashing, and pointers could be bad, we check things 948 /* Because we are crashing, and pointers could be bad, we check things
888 * pretty closely before we use them 949 * pretty closely before we use them
889 */ 950 */
890 if ((unsigned long)current >= FIXED_CODE_START && 951 if ((unsigned long)current >= FIXED_CODE_START &&
891 !((unsigned long)current & 0x3) && current->pid) { 952 !((unsigned long)current & 0x3) && current->pid) {
892 printk(KERN_NOTICE "CURRENT PROCESS:\n"); 953 verbose_printk(KERN_NOTICE "CURRENT PROCESS:\n");
893 if (current->comm >= (char *)FIXED_CODE_START) 954 if (current->comm >= (char *)FIXED_CODE_START)
894 printk(KERN_NOTICE "COMM=%s PID=%d\n", 955 verbose_printk(KERN_NOTICE "COMM=%s PID=%d\n",
895 current->comm, current->pid); 956 current->comm, current->pid);
896 else 957 else
897 printk(KERN_NOTICE "COMM= invalid\n"); 958 verbose_printk(KERN_NOTICE "COMM= invalid\n");
898 959
899 if (!((unsigned long)current->mm & 0x3) && (unsigned long)current->mm >= FIXED_CODE_START) 960 if (!((unsigned long)current->mm & 0x3) && (unsigned long)current->mm >= FIXED_CODE_START)
900 printk(KERN_NOTICE "TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n" 961 verbose_printk(KERN_NOTICE "TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n"
901 KERN_NOTICE " BSS = 0x%p-0x%p USER-STACK = 0x%p\n" 962 KERN_NOTICE " BSS = 0x%p-0x%p USER-STACK = 0x%p\n"
902 KERN_NOTICE "\n", 963 KERN_NOTICE "\n",
903 (void *)current->mm->start_code, 964 (void *)current->mm->start_code,
@@ -908,38 +969,40 @@ void dump_bfin_process(struct pt_regs *fp)
908 (void *)current->mm->brk, 969 (void *)current->mm->brk,
909 (void *)current->mm->start_stack); 970 (void *)current->mm->start_stack);
910 else 971 else
911 printk(KERN_NOTICE "invalid mm\n"); 972 verbose_printk(KERN_NOTICE "invalid mm\n");
912 } else 973 } else
913 printk(KERN_NOTICE "\n" KERN_NOTICE 974 verbose_printk(KERN_NOTICE "\n" KERN_NOTICE
914 "No Valid process in current context\n"); 975 "No Valid process in current context\n");
976#endif
915} 977}
916 978
917void dump_bfin_mem(struct pt_regs *fp) 979void dump_bfin_mem(struct pt_regs *fp)
918{ 980{
981#ifdef CONFIG_DEBUG_VERBOSE
919 unsigned short *addr, *erraddr, val = 0, err = 0; 982 unsigned short *addr, *erraddr, val = 0, err = 0;
920 char sti = 0, buf[6]; 983 char sti = 0, buf[6];
921 984
922 erraddr = (void *)fp->pc; 985 erraddr = (void *)fp->pc;
923 986
924 printk(KERN_NOTICE "return address: [0x%p]; contents of:", erraddr); 987 verbose_printk(KERN_NOTICE "return address: [0x%p]; contents of:", erraddr);
925 988
926 for (addr = (unsigned short *)((unsigned long)erraddr & ~0xF) - 0x10; 989 for (addr = (unsigned short *)((unsigned long)erraddr & ~0xF) - 0x10;
927 addr < (unsigned short *)((unsigned long)erraddr & ~0xF) + 0x10; 990 addr < (unsigned short *)((unsigned long)erraddr & ~0xF) + 0x10;
928 addr++) { 991 addr++) {
929 if (!((unsigned long)addr & 0xF)) 992 if (!((unsigned long)addr & 0xF))
930 printk("\n" KERN_NOTICE "0x%p: ", addr); 993 verbose_printk("\n" KERN_NOTICE "0x%p: ", addr);
931 994
932 if (get_instruction(&val, addr)) { 995 if (!get_instruction(&val, addr)) {
933 val = 0; 996 val = 0;
934 sprintf(buf, "????"); 997 sprintf(buf, "????");
935 } else 998 } else
936 sprintf(buf, "%04x", val); 999 sprintf(buf, "%04x", val);
937 1000
938 if (addr == erraddr) { 1001 if (addr == erraddr) {
939 printk("[%s]", buf); 1002 verbose_printk("[%s]", buf);
940 err = val; 1003 err = val;
941 } else 1004 } else
942 printk(" %s ", buf); 1005 verbose_printk(" %s ", buf);
943 1006
944 /* Do any previous instructions turn on interrupts? */ 1007 /* Do any previous instructions turn on interrupts? */
945 if (addr <= erraddr && /* in the past */ 1008 if (addr <= erraddr && /* in the past */
@@ -948,14 +1011,14 @@ void dump_bfin_mem(struct pt_regs *fp)
948 sti = 1; 1011 sti = 1;
949 } 1012 }
950 1013
951 printk("\n"); 1014 verbose_printk("\n");
952 1015
953 /* Hardware error interrupts can be deferred */ 1016 /* Hardware error interrupts can be deferred */
954 if (unlikely(sti && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR && 1017 if (unlikely(sti && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR &&
955 oops_in_progress)){ 1018 oops_in_progress)){
956 printk(KERN_NOTICE "Looks like this was a deferred error - sorry\n"); 1019 verbose_printk(KERN_NOTICE "Looks like this was a deferred error - sorry\n");
957#ifndef CONFIG_DEBUG_HWERR 1020#ifndef CONFIG_DEBUG_HWERR
958 printk(KERN_NOTICE "The remaining message may be meaningless\n" 1021 verbose_printk(KERN_NOTICE "The remaining message may be meaningless\n"
959 KERN_NOTICE "You should enable CONFIG_DEBUG_HWERR to get a" 1022 KERN_NOTICE "You should enable CONFIG_DEBUG_HWERR to get a"
960 " better idea where it came from\n"); 1023 " better idea where it came from\n");
961#else 1024#else
@@ -969,34 +1032,47 @@ void dump_bfin_mem(struct pt_regs *fp)
969 /* And the last RETI points to the current userspace context */ 1032 /* And the last RETI points to the current userspace context */
970 if ((fp + 1)->pc >= current->mm->start_code && 1033 if ((fp + 1)->pc >= current->mm->start_code &&
971 (fp + 1)->pc <= current->mm->end_code) { 1034 (fp + 1)->pc <= current->mm->end_code) {
972 printk(KERN_NOTICE "It might be better to look around here : \n"); 1035 verbose_printk(KERN_NOTICE "It might be better to look around here : \n");
973 printk(KERN_NOTICE "-------------------------------------------\n"); 1036 verbose_printk(KERN_NOTICE "-------------------------------------------\n");
974 show_regs(fp + 1); 1037 show_regs(fp + 1);
975 printk(KERN_NOTICE "-------------------------------------------\n"); 1038 verbose_printk(KERN_NOTICE "-------------------------------------------\n");
976 } 1039 }
977 } 1040 }
978#endif 1041#endif
979 } 1042 }
1043#endif
980} 1044}
981 1045
982void show_regs(struct pt_regs *fp) 1046void show_regs(struct pt_regs *fp)
983{ 1047{
1048#ifdef CONFIG_DEBUG_VERBOSE
984 char buf [150]; 1049 char buf [150];
985 struct irqaction *action; 1050 struct irqaction *action;
986 unsigned int i; 1051 unsigned int i;
987 unsigned long flags; 1052 unsigned long flags;
988 1053
989 printk(KERN_NOTICE "\n" KERN_NOTICE "SEQUENCER STATUS:\t\t%s\n", print_tainted()); 1054 verbose_printk(KERN_NOTICE "\n" KERN_NOTICE "SEQUENCER STATUS:\t\t%s\n", print_tainted());
990 printk(KERN_NOTICE " SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n", 1055 verbose_printk(KERN_NOTICE " SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n",
991 (long)fp->seqstat, fp->ipend, fp->syscfg); 1056 (long)fp->seqstat, fp->ipend, fp->syscfg);
992 printk(KERN_NOTICE " HWERRCAUSE: 0x%lx\n", 1057 if ((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) {
993 (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14); 1058 verbose_printk(KERN_NOTICE " HWERRCAUSE: 0x%lx\n",
994 printk(KERN_NOTICE " EXCAUSE : 0x%lx\n", 1059 (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14);
1060#ifdef EBIU_ERRMST
1061 /* If the error was from the EBIU, print it out */
1062 if (bfin_read_EBIU_ERRMST() & CORE_ERROR) {
1063 verbose_printk(KERN_NOTICE " EBIU Error Reason : 0x%04x\n",
1064 bfin_read_EBIU_ERRMST());
1065 verbose_printk(KERN_NOTICE " EBIU Error Address : 0x%08x\n",
1066 bfin_read_EBIU_ERRADD());
1067 }
1068#endif
1069 }
1070 verbose_printk(KERN_NOTICE " EXCAUSE : 0x%lx\n",
995 fp->seqstat & SEQSTAT_EXCAUSE); 1071 fp->seqstat & SEQSTAT_EXCAUSE);
996 for (i = 6; i <= 15 ; i++) { 1072 for (i = 6; i <= 15 ; i++) {
997 if (fp->ipend & (1 << i)) { 1073 if (fp->ipend & (1 << i)) {
998 decode_address(buf, bfin_read32(EVT0 + 4*i)); 1074 decode_address(buf, bfin_read32(EVT0 + 4*i));
999 printk(KERN_NOTICE " physical IVG%i asserted : %s\n", i, buf); 1075 verbose_printk(KERN_NOTICE " physical IVG%i asserted : %s\n", i, buf);
1000 } 1076 }
1001 } 1077 }
1002 1078
@@ -1009,64 +1085,65 @@ void show_regs(struct pt_regs *fp)
1009 goto unlock; 1085 goto unlock;
1010 1086
1011 decode_address(buf, (unsigned int)action->handler); 1087 decode_address(buf, (unsigned int)action->handler);
1012 printk(KERN_NOTICE " logical irq %3d mapped : %s", i, buf); 1088 verbose_printk(KERN_NOTICE " logical irq %3d mapped : %s", i, buf);
1013 for (action = action->next; action; action = action->next) { 1089 for (action = action->next; action; action = action->next) {
1014 decode_address(buf, (unsigned int)action->handler); 1090 decode_address(buf, (unsigned int)action->handler);
1015 printk(", %s", buf); 1091 verbose_printk(", %s", buf);
1016 } 1092 }
1017 printk("\n"); 1093 verbose_printk("\n");
1018unlock: 1094unlock:
1019 spin_unlock_irqrestore(&irq_desc[i].lock, flags); 1095 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
1020 } 1096 }
1021 } 1097 }
1022 1098
1023 decode_address(buf, fp->rete); 1099 decode_address(buf, fp->rete);
1024 printk(KERN_NOTICE " RETE: %s\n", buf); 1100 verbose_printk(KERN_NOTICE " RETE: %s\n", buf);
1025 decode_address(buf, fp->retn); 1101 decode_address(buf, fp->retn);
1026 printk(KERN_NOTICE " RETN: %s\n", buf); 1102 verbose_printk(KERN_NOTICE " RETN: %s\n", buf);
1027 decode_address(buf, fp->retx); 1103 decode_address(buf, fp->retx);
1028 printk(KERN_NOTICE " RETX: %s\n", buf); 1104 verbose_printk(KERN_NOTICE " RETX: %s\n", buf);
1029 decode_address(buf, fp->rets); 1105 decode_address(buf, fp->rets);
1030 printk(KERN_NOTICE " RETS: %s\n", buf); 1106 verbose_printk(KERN_NOTICE " RETS: %s\n", buf);
1031 decode_address(buf, fp->pc); 1107 decode_address(buf, fp->pc);
1032 printk(KERN_NOTICE " PC : %s\n", buf); 1108 verbose_printk(KERN_NOTICE " PC : %s\n", buf);
1033 1109
1034 if (((long)fp->seqstat & SEQSTAT_EXCAUSE) && 1110 if (((long)fp->seqstat & SEQSTAT_EXCAUSE) &&
1035 (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) { 1111 (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) {
1036 decode_address(buf, saved_dcplb_fault_addr); 1112 decode_address(buf, saved_dcplb_fault_addr);
1037 printk(KERN_NOTICE "DCPLB_FAULT_ADDR: %s\n", buf); 1113 verbose_printk(KERN_NOTICE "DCPLB_FAULT_ADDR: %s\n", buf);
1038 decode_address(buf, saved_icplb_fault_addr); 1114 decode_address(buf, saved_icplb_fault_addr);
1039 printk(KERN_NOTICE "ICPLB_FAULT_ADDR: %s\n", buf); 1115 verbose_printk(KERN_NOTICE "ICPLB_FAULT_ADDR: %s\n", buf);
1040 } 1116 }
1041 1117
1042 printk(KERN_NOTICE "\n" KERN_NOTICE "PROCESSOR STATE:\n"); 1118 verbose_printk(KERN_NOTICE "\n" KERN_NOTICE "PROCESSOR STATE:\n");
1043 printk(KERN_NOTICE " R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n", 1119 verbose_printk(KERN_NOTICE " R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
1044 fp->r0, fp->r1, fp->r2, fp->r3); 1120 fp->r0, fp->r1, fp->r2, fp->r3);
1045 printk(KERN_NOTICE " R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n", 1121 verbose_printk(KERN_NOTICE " R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n",
1046 fp->r4, fp->r5, fp->r6, fp->r7); 1122 fp->r4, fp->r5, fp->r6, fp->r7);
1047 printk(KERN_NOTICE " P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n", 1123 verbose_printk(KERN_NOTICE " P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n",
1048 fp->p0, fp->p1, fp->p2, fp->p3); 1124 fp->p0, fp->p1, fp->p2, fp->p3);
1049 printk(KERN_NOTICE " P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n", 1125 verbose_printk(KERN_NOTICE " P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n",
1050 fp->p4, fp->p5, fp->fp, (long)fp); 1126 fp->p4, fp->p5, fp->fp, (long)fp);
1051 printk(KERN_NOTICE " LB0: %08lx LT0: %08lx LC0: %08lx\n", 1127 verbose_printk(KERN_NOTICE " LB0: %08lx LT0: %08lx LC0: %08lx\n",
1052 fp->lb0, fp->lt0, fp->lc0); 1128 fp->lb0, fp->lt0, fp->lc0);
1053 printk(KERN_NOTICE " LB1: %08lx LT1: %08lx LC1: %08lx\n", 1129 verbose_printk(KERN_NOTICE " LB1: %08lx LT1: %08lx LC1: %08lx\n",
1054 fp->lb1, fp->lt1, fp->lc1); 1130 fp->lb1, fp->lt1, fp->lc1);
1055 printk(KERN_NOTICE " B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n", 1131 verbose_printk(KERN_NOTICE " B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n",
1056 fp->b0, fp->l0, fp->m0, fp->i0); 1132 fp->b0, fp->l0, fp->m0, fp->i0);
1057 printk(KERN_NOTICE " B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n", 1133 verbose_printk(KERN_NOTICE " B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n",
1058 fp->b1, fp->l1, fp->m1, fp->i1); 1134 fp->b1, fp->l1, fp->m1, fp->i1);
1059 printk(KERN_NOTICE " B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n", 1135 verbose_printk(KERN_NOTICE " B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n",
1060 fp->b2, fp->l2, fp->m2, fp->i2); 1136 fp->b2, fp->l2, fp->m2, fp->i2);
1061 printk(KERN_NOTICE " B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n", 1137 verbose_printk(KERN_NOTICE " B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n",
1062 fp->b3, fp->l3, fp->m3, fp->i3); 1138 fp->b3, fp->l3, fp->m3, fp->i3);
1063 printk(KERN_NOTICE "A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n", 1139 verbose_printk(KERN_NOTICE "A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
1064 fp->a0w, fp->a0x, fp->a1w, fp->a1x); 1140 fp->a0w, fp->a0x, fp->a1w, fp->a1x);
1065 1141
1066 printk(KERN_NOTICE "USP : %08lx ASTAT: %08lx\n", 1142 verbose_printk(KERN_NOTICE "USP : %08lx ASTAT: %08lx\n",
1067 rdusp(), fp->astat); 1143 rdusp(), fp->astat);
1068 1144
1069 printk(KERN_NOTICE "\n"); 1145 verbose_printk(KERN_NOTICE "\n");
1146#endif
1070} 1147}
1071 1148
1072#ifdef CONFIG_SYS_BFIN_SPINLOCK_L1 1149#ifdef CONFIG_SYS_BFIN_SPINLOCK_L1
diff --git a/arch/blackfin/mach-bf527/boards/Kconfig b/arch/blackfin/mach-bf527/boards/Kconfig
index 8bf9e58f0148..df224d04e167 100644
--- a/arch/blackfin/mach-bf527/boards/Kconfig
+++ b/arch/blackfin/mach-bf527/boards/Kconfig
@@ -14,4 +14,9 @@ config BFIN527_BLUETECHNIX_CM
14 help 14 help
15 CM-BF527 support for EVAL- and DEV-Board. 15 CM-BF527 support for EVAL- and DEV-Board.
16 16
17config BFIN526_EZBRD
18 bool "BF526-EZBRD"
19 help
20 BF526-EZBRD/EZKIT Lite board support.
21
17endchoice 22endchoice
diff --git a/arch/blackfin/mach-bf527/boards/Makefile b/arch/blackfin/mach-bf527/boards/Makefile
index 7ba7d256bbb8..eb6ed3362f9f 100644
--- a/arch/blackfin/mach-bf527/boards/Makefile
+++ b/arch/blackfin/mach-bf527/boards/Makefile
@@ -4,3 +4,4 @@
4 4
5obj-$(CONFIG_BFIN527_EZKIT) += ezkit.o 5obj-$(CONFIG_BFIN527_EZKIT) += ezkit.o
6obj-$(CONFIG_BFIN527_BLUETECHNIX_CM) += cm_bf527.o 6obj-$(CONFIG_BFIN527_BLUETECHNIX_CM) += cm_bf527.o
7obj-$(CONFIG_BFIN526_EZBRD) += ezbrd.o
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index d22bc7773717..9ea440bbb13d 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -43,10 +43,7 @@
43#include <linux/irq.h> 43#include <linux/irq.h>
44#include <linux/interrupt.h> 44#include <linux/interrupt.h>
45#include <linux/usb/sl811.h> 45#include <linux/usb/sl811.h>
46#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
47#include <linux/usb/musb.h> 46#include <linux/usb/musb.h>
48#endif
49#include <asm/cplb.h>
50#include <asm/dma.h> 47#include <asm/dma.h>
51#include <asm/bfin5xx_spi.h> 48#include <asm/bfin5xx_spi.h>
52#include <asm/reboot.h> 49#include <asm/reboot.h>
@@ -130,6 +127,16 @@ static struct resource musb_resources[] = {
130 }, 127 },
131}; 128};
132 129
130static struct musb_hdrc_config musb_config = {
131 .multipoint = 0,
132 .dyn_fifo = 0,
133 .soft_con = 1,
134 .dma = 1,
135 .num_eps = 7,
136 .dma_channels = 7,
137 .gpio_vrsel = GPIO_PF11,
138};
139
133static struct musb_hdrc_platform_data musb_plat = { 140static struct musb_hdrc_platform_data musb_plat = {
134#if defined(CONFIG_USB_MUSB_OTG) 141#if defined(CONFIG_USB_MUSB_OTG)
135 .mode = MUSB_OTG, 142 .mode = MUSB_OTG,
@@ -138,7 +145,7 @@ static struct musb_hdrc_platform_data musb_plat = {
138#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) 145#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
139 .mode = MUSB_PERIPHERAL, 146 .mode = MUSB_PERIPHERAL,
140#endif 147#endif
141 .multipoint = 0, 148 .config = &musb_config,
142}; 149};
143 150
144static u64 musb_dmamask = ~(u32)0; 151static u64 musb_dmamask = ~(u32)0;
@@ -201,7 +208,7 @@ static struct mtd_partition partition_info[] = {
201 { 208 {
202 .name = "linux kernel(nand)", 209 .name = "linux kernel(nand)",
203 .offset = 0, 210 .offset = 0,
204 .size = 4 * SIZE_1M, 211 .size = 4 * 1024 * 1024,
205 }, 212 },
206 { 213 {
207 .name = "file system(nand)", 214 .name = "file system(nand)",
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
new file mode 100644
index 000000000000..36c87b6fbdec
--- /dev/null
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -0,0 +1,734 @@
1/*
2 * File: arch/blackfin/mach-bf527/boards/ezbrd.c
3 * Based on: arch/blackfin/mach-bf537/boards/stamp.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2008 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h>
35#include <linux/mtd/physmap.h>
36#include <linux/spi/spi.h>
37#include <linux/spi/flash.h>
38
39#include <linux/i2c.h>
40#include <linux/irq.h>
41#include <linux/interrupt.h>
42#include <linux/usb/musb.h>
43#include <asm/dma.h>
44#include <asm/bfin5xx_spi.h>
45#include <asm/reboot.h>
46#include <asm/nand.h>
47#include <asm/portmux.h>
48#include <asm/dpmc.h>
49#include <linux/spi/ad7877.h>
50
51/*
52 * Name the Board for the /proc/cpuinfo
53 */
54const char bfin_board_name[] = "BF526-EZBRD";
55
56/*
57 * Driver needs to know address, irq and flag pin.
58 */
59
60#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
61static struct resource musb_resources[] = {
62 [0] = {
63 .start = 0xffc03800,
64 .end = 0xffc03cff,
65 .flags = IORESOURCE_MEM,
66 },
67 [1] = { /* general IRQ */
68 .start = IRQ_USB_INT0,
69 .end = IRQ_USB_INT0,
70 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
71 },
72 [2] = { /* DMA IRQ */
73 .start = IRQ_USB_DMA,
74 .end = IRQ_USB_DMA,
75 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
76 },
77};
78
79static struct musb_hdrc_config musb_config = {
80 .multipoint = 0,
81 .dyn_fifo = 0,
82 .soft_con = 1,
83 .dma = 1,
84 .num_eps = 7,
85 .dma_channels = 7,
86 .gpio_vrsel = GPIO_PG13,
87};
88
89static struct musb_hdrc_platform_data musb_plat = {
90#if defined(CONFIG_USB_MUSB_OTG)
91 .mode = MUSB_OTG,
92#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
93 .mode = MUSB_HOST,
94#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
95 .mode = MUSB_PERIPHERAL,
96#endif
97 .config = &musb_config,
98};
99
100static u64 musb_dmamask = ~(u32)0;
101
102static struct platform_device musb_device = {
103 .name = "musb_hdrc",
104 .id = 0,
105 .dev = {
106 .dma_mask = &musb_dmamask,
107 .coherent_dma_mask = 0xffffffff,
108 .platform_data = &musb_plat,
109 },
110 .num_resources = ARRAY_SIZE(musb_resources),
111 .resource = musb_resources,
112};
113#endif
114
115#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
116static struct mtd_partition ezbrd_partitions[] = {
117 {
118 .name = "bootloader(nor)",
119 .size = 0x40000,
120 .offset = 0,
121 }, {
122 .name = "linux kernel(nor)",
123 .size = 0x1C0000,
124 .offset = MTDPART_OFS_APPEND,
125 }, {
126 .name = "file system(nor)",
127 .size = MTDPART_SIZ_FULL,
128 .offset = MTDPART_OFS_APPEND,
129 }
130};
131
132static struct physmap_flash_data ezbrd_flash_data = {
133 .width = 2,
134 .parts = ezbrd_partitions,
135 .nr_parts = ARRAY_SIZE(ezbrd_partitions),
136};
137
138static struct resource ezbrd_flash_resource = {
139 .start = 0x20000000,
140 .end = 0x203fffff,
141 .flags = IORESOURCE_MEM,
142};
143
144static struct platform_device ezbrd_flash_device = {
145 .name = "physmap-flash",
146 .id = 0,
147 .dev = {
148 .platform_data = &ezbrd_flash_data,
149 },
150 .num_resources = 1,
151 .resource = &ezbrd_flash_resource,
152};
153#endif
154
155#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
156static struct mtd_partition partition_info[] = {
157 {
158 .name = "linux kernel(nand)",
159 .offset = 0,
160 .size = 4 * 1024 * 1024,
161 },
162 {
163 .name = "file system(nand)",
164 .offset = MTDPART_OFS_APPEND,
165 .size = MTDPART_SIZ_FULL,
166 },
167};
168
169static struct bf5xx_nand_platform bf5xx_nand_platform = {
170 .page_size = NFC_PG_SIZE_256,
171 .data_width = NFC_NWIDTH_8,
172 .partitions = partition_info,
173 .nr_partitions = ARRAY_SIZE(partition_info),
174 .rd_dly = 3,
175 .wr_dly = 3,
176};
177
178static struct resource bf5xx_nand_resources[] = {
179 {
180 .start = NFC_CTL,
181 .end = NFC_DATA_RD + 2,
182 .flags = IORESOURCE_MEM,
183 },
184 {
185 .start = CH_NFC,
186 .end = CH_NFC,
187 .flags = IORESOURCE_IRQ,
188 },
189};
190
191static struct platform_device bf5xx_nand_device = {
192 .name = "bf5xx-nand",
193 .id = 0,
194 .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
195 .resource = bf5xx_nand_resources,
196 .dev = {
197 .platform_data = &bf5xx_nand_platform,
198 },
199};
200#endif
201
202#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
203static struct platform_device rtc_device = {
204 .name = "rtc-bfin",
205 .id = -1,
206};
207#endif
208
209
210#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
211static struct platform_device bfin_mac_device = {
212 .name = "bfin_mac",
213};
214#endif
215
216#if defined(CONFIG_MTD_M25P80) \
217 || defined(CONFIG_MTD_M25P80_MODULE)
218static struct mtd_partition bfin_spi_flash_partitions[] = {
219 {
220 .name = "bootloader(spi)",
221 .size = 0x00040000,
222 .offset = 0,
223 .mask_flags = MTD_CAP_ROM
224 }, {
225 .name = "linux kernel(spi)",
226 .size = MTDPART_SIZ_FULL,
227 .offset = MTDPART_OFS_APPEND,
228 }
229};
230
231static struct flash_platform_data bfin_spi_flash_data = {
232 .name = "m25p80",
233 .parts = bfin_spi_flash_partitions,
234 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
235 .type = "m25p16",
236};
237
238/* SPI flash chip (m25p64) */
239static struct bfin5xx_spi_chip spi_flash_chip_info = {
240 .enable_dma = 0, /* use dma transfer with this chip*/
241 .bits_per_word = 8,
242};
243#endif
244
245#if defined(CONFIG_SPI_ADC_BF533) \
246 || defined(CONFIG_SPI_ADC_BF533_MODULE)
247/* SPI ADC chip */
248static struct bfin5xx_spi_chip spi_adc_chip_info = {
249 .enable_dma = 1, /* use dma transfer with this chip*/
250 .bits_per_word = 16,
251};
252#endif
253
254#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
255static struct bfin5xx_spi_chip spi_mmc_chip_info = {
256 .enable_dma = 1,
257 .bits_per_word = 8,
258};
259#endif
260
261#if defined(CONFIG_PBX)
262static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
263 .ctl_reg = 0x4, /* send zero */
264 .enable_dma = 0,
265 .bits_per_word = 8,
266 .cs_change_per_word = 1,
267};
268#endif
269
270#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
271static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
272 .enable_dma = 0,
273 .bits_per_word = 16,
274};
275
276static const struct ad7877_platform_data bfin_ad7877_ts_info = {
277 .model = 7877,
278 .vref_delay_usecs = 50, /* internal, no capacitor */
279 .x_plate_ohms = 419,
280 .y_plate_ohms = 486,
281 .pressure_max = 1000,
282 .pressure_min = 0,
283 .stopacq_polarity = 1,
284 .first_conversion_delay = 3,
285 .acquisition_time = 1,
286 .averaging = 1,
287 .pen_down_acc_interval = 1,
288};
289#endif
290
291#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
292 && defined(CONFIG_SND_SOC_WM8731_SPI)
293static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
294 .enable_dma = 0,
295 .bits_per_word = 16,
296};
297#endif
298
299#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
300static struct bfin5xx_spi_chip spidev_chip_info = {
301 .enable_dma = 0,
302 .bits_per_word = 8,
303};
304#endif
305
306#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
307static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
308 .enable_dma = 0,
309 .bits_per_word = 8,
310};
311#endif
312
313static struct spi_board_info bfin_spi_board_info[] __initdata = {
314#if defined(CONFIG_MTD_M25P80) \
315 || defined(CONFIG_MTD_M25P80_MODULE)
316 {
317 /* the modalias must be the same as spi device driver name */
318 .modalias = "m25p80", /* Name of spi_driver for this device */
319 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
320 .bus_num = 0, /* Framework bus number */
321 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
322 .platform_data = &bfin_spi_flash_data,
323 .controller_data = &spi_flash_chip_info,
324 .mode = SPI_MODE_3,
325 },
326#endif
327
328#if defined(CONFIG_SPI_ADC_BF533) \
329 || defined(CONFIG_SPI_ADC_BF533_MODULE)
330 {
331 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
332 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
333 .bus_num = 0, /* Framework bus number */
334 .chip_select = 1, /* Framework chip select. */
335 .platform_data = NULL, /* No spi_driver specific config */
336 .controller_data = &spi_adc_chip_info,
337 },
338#endif
339
340#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
341 {
342 .modalias = "spi_mmc_dummy",
343 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
344 .bus_num = 0,
345 .chip_select = 0,
346 .platform_data = NULL,
347 .controller_data = &spi_mmc_chip_info,
348 .mode = SPI_MODE_3,
349 },
350 {
351 .modalias = "spi_mmc",
352 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
353 .bus_num = 0,
354 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
355 .platform_data = NULL,
356 .controller_data = &spi_mmc_chip_info,
357 .mode = SPI_MODE_3,
358 },
359#endif
360#if defined(CONFIG_PBX)
361 {
362 .modalias = "fxs-spi",
363 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
364 .bus_num = 0,
365 .chip_select = 8 - CONFIG_J11_JUMPER,
366 .controller_data = &spi_si3xxx_chip_info,
367 .mode = SPI_MODE_3,
368 },
369 {
370 .modalias = "fxo-spi",
371 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
372 .bus_num = 0,
373 .chip_select = 8 - CONFIG_J19_JUMPER,
374 .controller_data = &spi_si3xxx_chip_info,
375 .mode = SPI_MODE_3,
376 },
377#endif
378#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
379 {
380 .modalias = "ad7877",
381 .platform_data = &bfin_ad7877_ts_info,
382 .irq = IRQ_PF8,
383 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
384 .bus_num = 0,
385 .chip_select = 2,
386 .controller_data = &spi_ad7877_chip_info,
387 },
388#endif
389#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
390 && defined(CONFIG_SND_SOC_WM8731_SPI)
391 {
392 .modalias = "wm8731",
393 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
394 .bus_num = 0,
395 .chip_select = 5,
396 .controller_data = &spi_wm8731_chip_info,
397 .mode = SPI_MODE_0,
398 },
399#endif
400#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
401 {
402 .modalias = "spidev",
403 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
404 .bus_num = 0,
405 .chip_select = 1,
406 .controller_data = &spidev_chip_info,
407 },
408#endif
409#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
410 {
411 .modalias = "bfin-lq035q1-spi",
412 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
413 .bus_num = 0,
414 .chip_select = 1,
415 .controller_data = &lq035q1_spi_chip_info,
416 .mode = SPI_CPHA | SPI_CPOL,
417 },
418#endif
419};
420
421#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
422/* SPI controller data */
423static struct bfin5xx_spi_master bfin_spi0_info = {
424 .num_chipselect = 8,
425 .enable_dma = 1, /* master has the ability to do dma transfer */
426 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
427};
428
429/* SPI (0) */
430static struct resource bfin_spi0_resource[] = {
431 [0] = {
432 .start = SPI0_REGBASE,
433 .end = SPI0_REGBASE + 0xFF,
434 .flags = IORESOURCE_MEM,
435 },
436 [1] = {
437 .start = CH_SPI,
438 .end = CH_SPI,
439 .flags = IORESOURCE_IRQ,
440 },
441};
442
443static struct platform_device bfin_spi0_device = {
444 .name = "bfin-spi",
445 .id = 0, /* Bus number */
446 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
447 .resource = bfin_spi0_resource,
448 .dev = {
449 .platform_data = &bfin_spi0_info, /* Passed to driver */
450 },
451};
452#endif /* spi master and devices */
453
454#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
455static struct resource bfin_uart_resources[] = {
456#ifdef CONFIG_SERIAL_BFIN_UART0
457 {
458 .start = 0xFFC00400,
459 .end = 0xFFC004FF,
460 .flags = IORESOURCE_MEM,
461 },
462#endif
463#ifdef CONFIG_SERIAL_BFIN_UART1
464 {
465 .start = 0xFFC02000,
466 .end = 0xFFC020FF,
467 .flags = IORESOURCE_MEM,
468 },
469#endif
470};
471
472static struct platform_device bfin_uart_device = {
473 .name = "bfin-uart",
474 .id = 1,
475 .num_resources = ARRAY_SIZE(bfin_uart_resources),
476 .resource = bfin_uart_resources,
477};
478#endif
479
480#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
481static struct resource bfin_sir_resources[] = {
482#ifdef CONFIG_BFIN_SIR0
483 {
484 .start = 0xFFC00400,
485 .end = 0xFFC004FF,
486 .flags = IORESOURCE_MEM,
487 },
488#endif
489#ifdef CONFIG_BFIN_SIR1
490 {
491 .start = 0xFFC02000,
492 .end = 0xFFC020FF,
493 .flags = IORESOURCE_MEM,
494 },
495#endif
496};
497
498static struct platform_device bfin_sir_device = {
499 .name = "bfin_sir",
500 .id = 0,
501 .num_resources = ARRAY_SIZE(bfin_sir_resources),
502 .resource = bfin_sir_resources,
503};
504#endif
505
506#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
507static struct resource bfin_twi0_resource[] = {
508 [0] = {
509 .start = TWI0_REGBASE,
510 .end = TWI0_REGBASE,
511 .flags = IORESOURCE_MEM,
512 },
513 [1] = {
514 .start = IRQ_TWI,
515 .end = IRQ_TWI,
516 .flags = IORESOURCE_IRQ,
517 },
518};
519
520static struct platform_device i2c_bfin_twi_device = {
521 .name = "i2c-bfin-twi",
522 .id = 0,
523 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
524 .resource = bfin_twi0_resource,
525};
526#endif
527
528#ifdef CONFIG_I2C_BOARDINFO
529static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
530#if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
531 {
532 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
533 },
534#endif
535#if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE)
536 {
537 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
538 .irq = IRQ_PF8,
539 },
540#endif
541};
542#endif
543
544#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
545static struct platform_device bfin_sport0_uart_device = {
546 .name = "bfin-sport-uart",
547 .id = 0,
548};
549
550static struct platform_device bfin_sport1_uart_device = {
551 .name = "bfin-sport-uart",
552 .id = 1,
553};
554#endif
555
556#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
557#include <linux/input.h>
558#include <linux/gpio_keys.h>
559
560static struct gpio_keys_button bfin_gpio_keys_table[] = {
561 {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
562 {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
563};
564
565static struct gpio_keys_platform_data bfin_gpio_keys_data = {
566 .buttons = bfin_gpio_keys_table,
567 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
568};
569
570static struct platform_device bfin_device_gpiokeys = {
571 .name = "gpio-keys",
572 .dev = {
573 .platform_data = &bfin_gpio_keys_data,
574 },
575};
576#endif
577
578static struct resource bfin_gpios_resources = {
579 .start = 0,
580 .end = MAX_BLACKFIN_GPIOS - 1,
581 .flags = IORESOURCE_IRQ,
582};
583
584static struct platform_device bfin_gpios_device = {
585 .name = "simple-gpio",
586 .id = -1,
587 .num_resources = 1,
588 .resource = &bfin_gpios_resources,
589};
590
591static const unsigned int cclk_vlev_datasheet[] =
592{
593 VRPAIR(VLEV_100, 400000000),
594 VRPAIR(VLEV_105, 426000000),
595 VRPAIR(VLEV_110, 500000000),
596 VRPAIR(VLEV_115, 533000000),
597 VRPAIR(VLEV_120, 600000000),
598};
599
600static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
601 .tuple_tab = cclk_vlev_datasheet,
602 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
603 .vr_settling_time = 25 /* us */,
604};
605
606static struct platform_device bfin_dpmc = {
607 .name = "bfin dpmc",
608 .dev = {
609 .platform_data = &bfin_dmpc_vreg_data,
610 },
611};
612
613#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
614#include <asm/bfin-lq035q1.h>
615
616static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
617 .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
618 .use_bl = 1,
619 .gpio_bl = GPIO_PG12,
620};
621
622static struct resource bfin_lq035q1_resources[] = {
623 {
624 .start = IRQ_PPI_ERROR,
625 .end = IRQ_PPI_ERROR,
626 .flags = IORESOURCE_IRQ,
627 },
628};
629
630static struct platform_device bfin_lq035q1_device = {
631 .name = "bfin-lq035q1",
632 .id = -1,
633 .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
634 .resource = bfin_lq035q1_resources,
635 .dev = {
636 .platform_data = &bfin_lq035q1_data,
637 },
638};
639#endif
640
641static struct platform_device *stamp_devices[] __initdata = {
642
643 &bfin_dpmc,
644
645#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
646 &bf5xx_nand_device,
647#endif
648
649#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
650 &rtc_device,
651#endif
652
653#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
654 &musb_device,
655#endif
656
657#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
658 &bfin_mac_device,
659#endif
660
661#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
662 &bfin_spi0_device,
663#endif
664
665#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
666 &bfin_uart_device,
667#endif
668
669#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
670 &bfin_lq035q1_device,
671#endif
672
673#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
674 &bfin_sir_device,
675#endif
676
677#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
678 &i2c_bfin_twi_device,
679#endif
680
681#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
682 &bfin_sport0_uart_device,
683 &bfin_sport1_uart_device,
684#endif
685
686#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
687 &bfin_device_gpiokeys,
688#endif
689
690#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
691 &ezbrd_flash_device,
692#endif
693
694 &bfin_gpios_device,
695};
696
697static int __init stamp_init(void)
698{
699 printk(KERN_INFO "%s(): registering device resources\n", __func__);
700
701#ifdef CONFIG_I2C_BOARDINFO
702 i2c_register_board_info(0, bfin_i2c_board_info,
703 ARRAY_SIZE(bfin_i2c_board_info));
704#endif
705
706 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
707 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
708 return 0;
709}
710
711arch_initcall(stamp_init);
712
713void native_machine_restart(char *cmd)
714{
715 /* workaround reboot hang when booting from SPI */
716 if ((bfin_read_SYSCR() & 0x7) == 0x3)
717 bfin_gpio_reset_spi0_ssel1();
718}
719
720void bfin_get_ether_addr(char *addr)
721{
722 /* the MAC is stored in OTP memory page 0xDF */
723 u32 ret;
724 u64 otp_mac;
725 u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
726
727 ret = otp_read(0xDF, 0x00, &otp_mac);
728 if (!(ret & 0x1)) {
729 char *otp_mac_p = (char *)&otp_mac;
730 for (ret = 0; ret < 6; ++ret)
731 addr[ret] = otp_mac_p[5 - ret];
732 }
733}
734EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index 762f754c06cc..8ee2b744e234 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -42,10 +42,7 @@
42#include <linux/irq.h> 42#include <linux/irq.h>
43#include <linux/interrupt.h> 43#include <linux/interrupt.h>
44#include <linux/usb/sl811.h> 44#include <linux/usb/sl811.h>
45#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
46#include <linux/usb/musb.h> 45#include <linux/usb/musb.h>
47#endif
48#include <asm/cplb.h>
49#include <asm/dma.h> 46#include <asm/dma.h>
50#include <asm/bfin5xx_spi.h> 47#include <asm/bfin5xx_spi.h>
51#include <asm/reboot.h> 48#include <asm/reboot.h>
@@ -129,6 +126,16 @@ static struct resource musb_resources[] = {
129 }, 126 },
130}; 127};
131 128
129static struct musb_hdrc_config musb_config = {
130 .multipoint = 0,
131 .dyn_fifo = 0,
132 .soft_con = 1,
133 .dma = 1,
134 .num_eps = 7,
135 .dma_channels = 7,
136 .gpio_vrsel = GPIO_PG13,
137};
138
132static struct musb_hdrc_platform_data musb_plat = { 139static struct musb_hdrc_platform_data musb_plat = {
133#if defined(CONFIG_USB_MUSB_OTG) 140#if defined(CONFIG_USB_MUSB_OTG)
134 .mode = MUSB_OTG, 141 .mode = MUSB_OTG,
@@ -137,7 +144,7 @@ static struct musb_hdrc_platform_data musb_plat = {
137#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) 144#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
138 .mode = MUSB_PERIPHERAL, 145 .mode = MUSB_PERIPHERAL,
139#endif 146#endif
140 .multipoint = 0, 147 .config = &musb_config,
141}; 148};
142 149
143static u64 musb_dmamask = ~(u32)0; 150static u64 musb_dmamask = ~(u32)0;
@@ -218,7 +225,7 @@ static struct mtd_partition partition_info[] = {
218 { 225 {
219 .name = "linux kernel(nand)", 226 .name = "linux kernel(nand)",
220 .offset = 0, 227 .offset = 0,
221 .size = 4 * SIZE_1M, 228 .size = 4 * 1024 * 1024,
222 }, 229 },
223 { 230 {
224 .name = "file system(nand)", 231 .name = "file system(nand)",
@@ -846,6 +853,38 @@ static struct platform_device bfin_device_gpiokeys = {
846}; 853};
847#endif 854#endif
848 855
856#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE)
857#include <linux/input.h>
858#include <asm/bfin_rotary.h>
859
860static struct bfin_rotary_platform_data bfin_rotary_data = {
861 /*.rotary_up_key = KEY_UP,*/
862 /*.rotary_down_key = KEY_DOWN,*/
863 .rotary_rel_code = REL_WHEEL,
864 .rotary_button_key = KEY_ENTER,
865 .debounce = 10, /* 0..17 */
866 .mode = ROT_QUAD_ENC | ROT_DEBE,
867};
868
869static struct resource bfin_rotary_resources[] = {
870 {
871 .start = IRQ_CNT,
872 .end = IRQ_CNT,
873 .flags = IORESOURCE_IRQ,
874 },
875};
876
877static struct platform_device bfin_rotary_device = {
878 .name = "bfin-rotary",
879 .id = -1,
880 .num_resources = ARRAY_SIZE(bfin_rotary_resources),
881 .resource = bfin_rotary_resources,
882 .dev = {
883 .platform_data = &bfin_rotary_data,
884 },
885};
886#endif
887
849static struct resource bfin_gpios_resources = { 888static struct resource bfin_gpios_resources = {
850 .start = 0, 889 .start = 0,
851 .end = MAX_BLACKFIN_GPIOS - 1, 890 .end = MAX_BLACKFIN_GPIOS - 1,
@@ -962,6 +1001,10 @@ static struct platform_device *stamp_devices[] __initdata = {
962 &bfin_device_gpiokeys, 1001 &bfin_device_gpiokeys,
963#endif 1002#endif
964 1003
1004#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE)
1005 &bfin_rotary_device,
1006#endif
1007
965#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) 1008#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
966 &ezkit_flash_device, 1009 &ezkit_flash_device,
967#endif 1010#endif
diff --git a/arch/blackfin/mach-bf527/head.S b/arch/blackfin/mach-bf527/head.S
index 28c486191209..6588170e3845 100644
--- a/arch/blackfin/mach-bf527/head.S
+++ b/arch/blackfin/mach-bf527/head.S
@@ -87,6 +87,9 @@ ENTRY(_start_dma_code)
87 r1 = PLL_BYPASS; /* Bypass the PLL? */ 87 r1 = PLL_BYPASS; /* Bypass the PLL? */
88 r1 = r1 << 8; /* Shift it over */ 88 r1 = r1 << 8; /* Shift it over */
89 r0 = r1 | r0; /* add them all together */ 89 r0 = r1 | r0; /* add them all together */
90#ifdef ANOMALY_05000265
91 r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
92#endif
90 93
91 p0.h = hi(PLL_CTL); 94 p0.h = hi(PLL_CTL);
92 p0.l = lo(PLL_CTL); /* Load the address */ 95 p0.l = lo(PLL_CTL); /* Load the address */
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index b7b166f4f064..62373e61c585 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -7,12 +7,24 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List 10 * - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List
11 * - Revision E, 08/18/2008; ADSP-BF527 Blackfin Processor Anomaly List
11 */ 12 */
12 13
13#ifndef _MACH_ANOMALY_H_ 14#ifndef _MACH_ANOMALY_H_
14#define _MACH_ANOMALY_H_ 15#define _MACH_ANOMALY_H_
15 16
17#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
18# define ANOMALY_BF526 1
19#else
20# define ANOMALY_BF526 0
21#endif
22#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
23# define ANOMALY_BF527 1
24#else
25# define ANOMALY_BF527 0
26#endif
27
16/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ 28/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
17#define ANOMALY_05000074 (1) 29#define ANOMALY_05000074 (1)
18/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ 30/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
@@ -23,68 +35,124 @@
23#define ANOMALY_05000245 (1) 35#define ANOMALY_05000245 (1)
24/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ 36/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
25#define ANOMALY_05000265 (1) 37#define ANOMALY_05000265 (1)
26/* New Feature: EMAC TX DMA Word Alignment */ 38/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
27#define ANOMALY_05000285 (1) 39#define ANOMALY_05000310 (1)
28/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ 40/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
29#define ANOMALY_05000312 (1) 41#define ANOMALY_05000312 (ANOMALY_BF527)
42/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
43#define ANOMALY_05000313 (__SILICON_REVISION__ < 2)
30/* Incorrect Access of OTP_STATUS During otp_write() Function */ 44/* Incorrect Access of OTP_STATUS During otp_write() Function */
31#define ANOMALY_05000328 (1) 45#define ANOMALY_05000328 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
32/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ 46/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
33#define ANOMALY_05000337 (1) 47#define ANOMALY_05000337 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
34/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ 48/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
35#define ANOMALY_05000341 (1) 49#define ANOMALY_05000341 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
36/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */ 50/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
37#define ANOMALY_05000342 (1) 51#define ANOMALY_05000342 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
38/* USB Calibration Value Is Not Initialized */ 52/* USB Calibration Value Is Not Initialized */
39#define ANOMALY_05000346 (1) 53#define ANOMALY_05000346 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
54/* USB Calibration Value to use */
55#define ANOMALY_05000346_value 0xE510
40/* Preboot Routine Incorrectly Alters Reset Value of USB Register */ 56/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
41#define ANOMALY_05000347 (1) 57#define ANOMALY_05000347 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
42/* Security Features Are Not Functional */ 58/* Security Features Are Not Functional */
43#define ANOMALY_05000348 (__SILICON_REVISION__ < 1) 59#define ANOMALY_05000348 (ANOMALY_BF527 && __SILICON_REVISION__ < 1)
60/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
61#define ANOMALY_05000353 (ANOMALY_BF526)
44/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ 62/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
45#define ANOMALY_05000355 (1) 63#define ANOMALY_05000355 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
46/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ 64/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
47#define ANOMALY_05000357 (1) 65#define ANOMALY_05000357 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
48/* Incorrect Revision Number in DSPID Register */ 66/* Incorrect Revision Number in DSPID Register */
49#define ANOMALY_05000364 (__SILICON_REVISION__ > 0) 67#define ANOMALY_05000364 (ANOMALY_BF527 && __SILICON_REVISION__ == 1)
50/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ 68/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
51#define ANOMALY_05000366 (1) 69#define ANOMALY_05000366 (1)
52/* New Feature: Higher Default CCLK Rate */ 70/* Incorrect Default CSEL Value in PLL_DIV */
53#define ANOMALY_05000368 (1) 71#define ANOMALY_05000368 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
54/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ 72/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
55#define ANOMALY_05000371 (1) 73#define ANOMALY_05000371 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
56/* Authentication Fails To Initiate */ 74/* Authentication Fails To Initiate */
57#define ANOMALY_05000376 (__SILICON_REVISION__ > 0) 75#define ANOMALY_05000376 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
58/* Data Read From L3 Memory by USB DMA May be Corrupted */ 76/* Data Read From L3 Memory by USB DMA May be Corrupted */
59#define ANOMALY_05000380 (1) 77#define ANOMALY_05000380 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
60/* USB Full-speed Mode not Fully Tested */ 78/* 8-Bit NAND Flash Boot Mode Not Functional */
61#define ANOMALY_05000381 (1) 79#define ANOMALY_05000382 (__SILICON_REVISION__ < 2)
62/* New Feature: Boot from OTP Memory */ 80/* Host Must Not Read Back During Host DMA Boot */
63#define ANOMALY_05000385 (1) 81#define ANOMALY_05000384 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
64/* New Feature: bfrom_SysControl() Routine */ 82/* Boot from OTP Memory Not Functional */
65#define ANOMALY_05000386 (1) 83#define ANOMALY_05000385 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
66/* New Feature: Programmable Preboot Settings */ 84/* bfrom_SysControl() Firmware Routine Not Functional */
67#define ANOMALY_05000387 (1) 85#define ANOMALY_05000386 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
86/* Programmable Preboot Settings Not Functional */
87#define ANOMALY_05000387 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
88/* CRC32 Checksum Support Not Functional */
89#define ANOMALY_05000388 (__SILICON_REVISION__ < 2)
68/* Reset Vector Must Not Be in SDRAM Memory Space */ 90/* Reset Vector Must Not Be in SDRAM Memory Space */
69#define ANOMALY_05000389 (1) 91#define ANOMALY_05000389 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
70/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */ 92/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
71#define ANOMALY_05000392 (1) 93#define ANOMALY_05000392 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
72/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */ 94/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
73#define ANOMALY_05000393 (1) 95#define ANOMALY_05000393 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
74/* New Feature: Log Buffer Functionality */ 96/* Log Buffer Not Functional */
75#define ANOMALY_05000394 (1) 97#define ANOMALY_05000394 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
76/* New Feature: Hook Routine Functionality */ 98/* Hook Routine Not Functional */
77#define ANOMALY_05000395 (1) 99#define ANOMALY_05000395 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
78/* New Feature: Header Indirect Bit */ 100/* Header Indirect Bit Not Functional */
79#define ANOMALY_05000396 (1) 101#define ANOMALY_05000396 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
80/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */ 102/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
81#define ANOMALY_05000397 (1) 103#define ANOMALY_05000397 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
82/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */ 104/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
83#define ANOMALY_05000398 (1) 105#define ANOMALY_05000398 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
84/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */ 106/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
85#define ANOMALY_05000399 (1) 107#define ANOMALY_05000399 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
86/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */ 108/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
87#define ANOMALY_05000401 (1) 109#define ANOMALY_05000401 (__SILICON_REVISION__ < 2)
110/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
111#define ANOMALY_05000403 (__SILICON_REVISION__ < 2)
112/* Lockbox SESR Disallows Certain User Interrupts */
113#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
114/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
115#define ANOMALY_05000405 (1)
116/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
117#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
118/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
119#define ANOMALY_05000408 (1)
120/* Lockbox firmware leaves MDMA0 channel enabled */
121#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
122/* Incorrect Default Internal Voltage Regulator Setting */
123#define ANOMALY_05000410 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
124/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
125#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
126/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
127#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
128/* DEB2_URGENT Bit Not Functional */
129#define ANOMALY_05000415 (__SILICON_REVISION__ < 2)
130/* Speculative Fetches Can Cause Undesired External FIFO Operations */
131#define ANOMALY_05000416 (1)
132/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
133#define ANOMALY_05000417 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
134/* tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
135#define ANOMALY_05000418 (__SILICON_REVISION__ < 2)
136/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
137#define ANOMALY_05000420 (__SILICON_REVISION__ < 2)
138/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
139#define ANOMALY_05000421 (1)
140/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
141#define ANOMALY_05000422 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
142/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
143#define ANOMALY_05000423 (__SILICON_REVISION__ < 2)
144/* Internal Voltage Regulator Not Trimmed */
145#define ANOMALY_05000424 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
146/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
147#define ANOMALY_05000425 (__SILICON_REVISION__ < 2)
148/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */
149#define ANOMALY_05000426 (1)
150/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
151#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
152/* Software System Reset Corrupts PLL_LOCKCNT Register */
153#define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
154/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
155#define ANOMALY_05000432 (ANOMALY_BF526)
88 156
89/* Anomalies that don't exist on this proc */ 157/* Anomalies that don't exist on this proc */
90#define ANOMALY_05000125 (0) 158#define ANOMALY_05000125 (0)
@@ -97,6 +165,8 @@
97#define ANOMALY_05000263 (0) 165#define ANOMALY_05000263 (0)
98#define ANOMALY_05000266 (0) 166#define ANOMALY_05000266 (0)
99#define ANOMALY_05000273 (0) 167#define ANOMALY_05000273 (0)
168#define ANOMALY_05000285 (0)
169#define ANOMALY_05000307 (0)
100#define ANOMALY_05000311 (0) 170#define ANOMALY_05000311 (0)
101#define ANOMALY_05000323 (0) 171#define ANOMALY_05000323 (0)
102#define ANOMALY_05000363 (0) 172#define ANOMALY_05000363 (0)
diff --git a/arch/blackfin/mach-bf527/include/mach/bf527.h b/arch/blackfin/mach-bf527/include/mach/bf527.h
index 056eb4b9cd25..144f08d3f8ea 100644
--- a/arch/blackfin/mach-bf527/include/mach/bf527.h
+++ b/arch/blackfin/mach-bf527/include/mach/bf527.h
@@ -30,8 +30,6 @@
30#ifndef __MACH_BF527_H__ 30#ifndef __MACH_BF527_H__
31#define __MACH_BF527_H__ 31#define __MACH_BF527_H__
32 32
33#define SUPPORTED_REVID 2
34
35#define OFFSET_(x) ((x) & 0x0000FFFF) 33#define OFFSET_(x) ((x) & 0x0000FFFF)
36 34
37/*some misc defines*/ 35/*some misc defines*/
@@ -112,16 +110,31 @@
112 110
113#ifdef CONFIG_BF527 111#ifdef CONFIG_BF527
114#define CPU "BF527" 112#define CPU "BF527"
113#define CPUID 0x27e4
114#endif
115#ifdef CONFIG_BF526
116#define CPU "BF526"
117#define CPUID 0x27e4
115#endif 118#endif
116#ifdef CONFIG_BF525 119#ifdef CONFIG_BF525
117#define CPU "BF525" 120#define CPU "BF525"
121#define CPUID 0x27e4
122#endif
123#ifdef CONFIG_BF524
124#define CPU "BF524"
125#define CPUID 0x27e4
126#endif
127#ifdef CONFIG_BF523
128#define CPU "BF523"
129#define CPUID 0x27e4
118#endif 130#endif
119#ifdef CONFIG_BF522 131#ifdef CONFIG_BF522
120#define CPU "BF522" 132#define CPU "BF522"
133#define CPUID 0x27e4
121#endif 134#endif
135
122#ifndef CPU 136#ifndef CPU
123#define CPU "UNKNOWN" 137#error Unknown CPU type - This kernel doesn't seem to be configured properly
124#define CPUID 0x0
125#endif 138#endif
126 139
127#endif /* __MACH_BF527_H__ */ 140#endif /* __MACH_BF527_H__ */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
index 6ac2ed7026eb..68b55d03fedf 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
@@ -1840,6 +1840,33 @@
1840 1840
1841#define DPRESCALE 0xf /* Load Counter Register */ 1841#define DPRESCALE 0xf /* Load Counter Register */
1842 1842
1843/* CNT_COMMAND bit field options */
1844
1845#define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */
1846#define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */
1847#define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */
1848
1849#define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */
1850#define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */
1851#define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */
1852
1853#define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */
1854#define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */
1855#define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */
1856
1857/* CNT_CONFIG bit field options */
1858
1859#define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */
1860#define CNTMODE_BINENC 0x0100 /* binary encoder mode */
1861#define CNTMODE_UDCNT 0x0200 /* up/down counter mode */
1862#define CNTMODE_DIRCNT 0x0400 /* direction counter mode */
1863#define CNTMODE_DIRTMR 0x0500 /* direction timer mode */
1864
1865#define BNDMODE_COMP 0x0000 /* boundary compare mode */
1866#define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */
1867#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
1868#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
1869
1843/* Bit masks for OTP_CONTROL */ 1870/* Bit masks for OTP_CONTROL */
1844 1871
1845#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ 1872#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
diff --git a/arch/blackfin/mach-bf527/include/mach/portmux.h b/arch/blackfin/mach-bf527/include/mach/portmux.h
index ae4d205bfcf5..7f6da2c386bb 100644
--- a/arch/blackfin/mach-bf527/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf527/include/mach/portmux.h
@@ -67,6 +67,10 @@
67#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1)) 67#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
68#endif 68#endif
69 69
70#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(3))
71#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(3))
72#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(3))
73
70#define P_HWAIT (P_DONTCARE) 74#define P_HWAIT (P_DONTCARE)
71 75
72#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) 76#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c
index c66a68f30239..72ac3ac8ef76 100644
--- a/arch/blackfin/mach-bf533/boards/H8606.c
+++ b/arch/blackfin/mach-bf533/boards/H8606.c
@@ -9,7 +9,7 @@
9 * Modified: 9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA) 10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2006 Analog Devices Inc 11 * Copyright 2004-2006 Analog Devices Inc
12 * Copyright 2007 HV Sistemas S.L. 12 * Copyright 2007,2008 HV Sistemas S.L.
13 * 13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 * 15 *
@@ -64,18 +64,18 @@ static struct platform_device rtc_device = {
64static struct resource dm9000_resources[] = { 64static struct resource dm9000_resources[] = {
65 [0] = { 65 [0] = {
66 .start = 0x20300000, 66 .start = 0x20300000,
67 .end = 0x20300000 + 1, 67 .end = 0x20300002,
68 .flags = IORESOURCE_MEM, 68 .flags = IORESOURCE_MEM,
69 }, 69 },
70 [1] = { 70 [1] = {
71 .start = 0x20300000 + 4, 71 .start = 0x20300004,
72 .end = 0x20300000 + 5, 72 .end = 0x20300006,
73 .flags = IORESOURCE_MEM, 73 .flags = IORESOURCE_MEM,
74 }, 74 },
75 [2] = { 75 [2] = {
76 .start = IRQ_PF10, 76 .start = IRQ_PF10,
77 .end = IRQ_PF10, 77 .end = IRQ_PF10,
78 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE), 78 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | IRQF_SHARED | IRQF_TRIGGER_HIGH),
79 }, 79 },
80}; 80};
81 81
@@ -140,18 +140,22 @@ static struct platform_device net2272_bfin_device = {
140#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) 140#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
141static struct mtd_partition bfin_spi_flash_partitions[] = { 141static struct mtd_partition bfin_spi_flash_partitions[] = {
142 { 142 {
143 .name = "bootloader(spi)", 143 .name = "bootloader (spi)",
144 .size = 0x00060000, 144 .size = 0x40000,
145 .offset = 0, 145 .offset = 0,
146 .mask_flags = MTD_CAP_ROM 146 .mask_flags = MTD_CAP_ROM
147 }, { 147 }, {
148 .name = "linux kernel(spi)", 148 .name = "fpga (spi)",
149 .size = 0x100000, 149 .size = 0x30000,
150 .offset = 0x60000 150 .offset = 0x40000
151 }, { 151 }, {
152 .name = "file system(spi)", 152 .name = "linux kernel (spi)",
153 .size = 0x6a0000, 153 .size = 0x150000,
154 .offset = 0x00160000, 154 .offset = 0x70000
155 }, {
156 .name = "jffs2 root file system (spi)",
157 .size = 0x640000,
158 .offset = 0x1c0000,
155 } 159 }
156}; 160};
157 161
@@ -340,7 +344,7 @@ static struct platform_device bfin_sir_device = {
340 344
341static struct plat_serial8250_port serial8250_platform_data [] = { 345static struct plat_serial8250_port serial8250_platform_data [] = {
342 { 346 {
343 .membase = 0x20200000, 347 .membase = (void *)0x20200000,
344 .mapbase = 0x20200000, 348 .mapbase = 0x20200000,
345 .irq = IRQ_PF8, 349 .irq = IRQ_PF8,
346 .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE, 350 .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,
@@ -348,7 +352,7 @@ static struct plat_serial8250_port serial8250_platform_data [] = {
348 .regshift = 1, 352 .regshift = 1,
349 .uartclk = 66666667, 353 .uartclk = 66666667,
350 }, { 354 }, {
351 .membase = 0x20200010, 355 .membase = (void *)0x20200010,
352 .mapbase = 0x20200010, 356 .mapbase = 0x20200010,
353 .irq = IRQ_PF8, 357 .irq = IRQ_PF8,
354 .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE, 358 .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
index 01b2b7ead5ab..619685b94d90 100644
--- a/arch/blackfin/mach-bf533/head.S
+++ b/arch/blackfin/mach-bf533/head.S
@@ -78,6 +78,9 @@ ENTRY(_start_dma_code)
78 r1 = PLL_BYPASS; /* Bypass the PLL? */ 78 r1 = PLL_BYPASS; /* Bypass the PLL? */
79 r1 = r1 << 8; /* Shift it over */ 79 r1 = r1 << 8; /* Shift it over */
80 r0 = r1 | r0; /* add them all together */ 80 r0 = r1 | r0; /* add them all together */
81#ifdef ANOMALY_05000265
82 r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
83#endif
81 84
82 p0.h = hi(PLL_CTL); 85 p0.h = hi(PLL_CTL);
83 p0.l = lo(PLL_CTL); /* Load the address */ 86 p0.l = lo(PLL_CTL); /* Load the address */
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
index 8f7ea112fd3a..f544fc56959a 100644
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List 10 * - Revision D, 06/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -97,11 +97,11 @@
97/* UART STB Bit Incorrectly Affects Receiver Setting */ 97/* UART STB Bit Incorrectly Affects Receiver Setting */
98#define ANOMALY_05000231 (__SILICON_REVISION__ < 5) 98#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
99/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ 99/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
100#define ANOMALY_05000233 (__SILICON_REVISION__ < 4) 100#define ANOMALY_05000233 (__SILICON_REVISION__ < 6)
101/* Incorrect Revision Number in DSPID Register */ 101/* Incorrect Revision Number in DSPID Register */
102#define ANOMALY_05000234 (__SILICON_REVISION__ == 4) 102#define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
103/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ 103/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
104#define ANOMALY_05000242 (__SILICON_REVISION__ < 4) 104#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
105/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ 105/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
106#define ANOMALY_05000244 (__SILICON_REVISION__ < 5) 106#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
107/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ 107/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
@@ -131,7 +131,7 @@
131/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ 131/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
132#define ANOMALY_05000264 (__SILICON_REVISION__ < 5) 132#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
133/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ 133/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
134#define ANOMALY_05000265 (__SILICON_REVISION__ < 5) 134#define ANOMALY_05000265 (1)
135/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ 135/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
136#define ANOMALY_05000269 (__SILICON_REVISION__ < 5) 136#define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
137/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ 137/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
@@ -141,56 +141,59 @@
141/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ 141/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
142#define ANOMALY_05000272 (1) 142#define ANOMALY_05000272 (1)
143/* Writes to Synchronous SDRAM Memory May Be Lost */ 143/* Writes to Synchronous SDRAM Memory May Be Lost */
144#define ANOMALY_05000273 (1) 144#define ANOMALY_05000273 (__SILICON_REVISION__ < 6)
145/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ 145/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
146#define ANOMALY_05000276 (1) 146#define ANOMALY_05000276 (1)
147/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ 147/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
148#define ANOMALY_05000277 (1) 148#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
149/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ 149/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
150#define ANOMALY_05000278 (1) 150#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
151/* False Hardware Error Exception When ISR Context Is Not Restored */ 151/* False Hardware Error Exception When ISR Context Is Not Restored */
152#define ANOMALY_05000281 (1) 152#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
153/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ 153/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
154#define ANOMALY_05000282 (1) 154#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
155/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ 155/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
156#define ANOMALY_05000283 (1) 156#define ANOMALY_05000283 (__SILICON_REVISION__ < 6)
157/* SPORTs May Receive Bad Data If FIFOs Fill Up */ 157/* SPORTs May Receive Bad Data If FIFOs Fill Up */
158#define ANOMALY_05000288 (1) 158#define ANOMALY_05000288 (__SILICON_REVISION__ < 6)
159/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ 159/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
160#define ANOMALY_05000301 (1) 160#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
161/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ 161/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
162#define ANOMALY_05000302 (__SILICON_REVISION__ < 5) 162#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
163/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ 163/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
164#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) 164#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
165/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ 165/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
166#define ANOMALY_05000306 (__SILICON_REVISION__ < 5) 166#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
167/* SCKELOW Bit Does Not Maintain State Through Hibernate */
168#define ANOMALY_05000307 (1)
167/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 169/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
168#define ANOMALY_05000310 (1) 170#define ANOMALY_05000310 (1)
169/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ 171/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
170#define ANOMALY_05000311 (1) 172#define ANOMALY_05000311 (__SILICON_REVISION__ < 6)
171/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ 173/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
172#define ANOMALY_05000312 (1) 174#define ANOMALY_05000312 (__SILICON_REVISION__ < 6)
173/* PPI Is Level-Sensitive on First Transfer */ 175/* PPI Is Level-Sensitive on First Transfer */
174#define ANOMALY_05000313 (1) 176#define ANOMALY_05000313 (__SILICON_REVISION__ < 6)
175/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ 177/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
176#define ANOMALY_05000315 (1) 178#define ANOMALY_05000315 (__SILICON_REVISION__ < 6)
177/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ 179/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
178#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532) 180#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6)
179/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ 181/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
180#define ANOMALY_05000357 (1) 182#define ANOMALY_05000357 (__SILICON_REVISION__ < 6)
181/* UART Break Signal Issues */ 183/* UART Break Signal Issues */
182#define ANOMALY_05000363 (__SILICON_REVISION__ < 5) 184#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
183/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ 185/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
184#define ANOMALY_05000366 (1) 186#define ANOMALY_05000366 (1)
185/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ 187/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
186#define ANOMALY_05000371 (1) 188#define ANOMALY_05000371 (__SILICON_REVISION__ < 6)
187/* PPI Does Not Start Properly In Specific Mode */ 189/* PPI Does Not Start Properly In Specific Mode */
188#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5) 190#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
189/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ 191/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
190#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) 192#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
191/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ 193/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
192#define ANOMALY_05000403 (1) 194#define ANOMALY_05000403 (1)
193 195/* Speculative Fetches Can Cause Undesired External FIFO Operations */
196#define ANOMALY_05000416 (1)
194 197
195/* These anomalies have been "phased" out of analog.com anomaly sheets and are 198/* These anomalies have been "phased" out of analog.com anomaly sheets and are
196 * here to show running on older silicon just isn't feasible. 199 * here to show running on older silicon just isn't feasible.
@@ -268,5 +271,7 @@
268/* Anomalies that don't exist on this proc */ 271/* Anomalies that don't exist on this proc */
269#define ANOMALY_05000266 (0) 272#define ANOMALY_05000266 (0)
270#define ANOMALY_05000323 (0) 273#define ANOMALY_05000323 (0)
274#define ANOMALY_05000353 (1)
275#define ANOMALY_05000386 (1)
271 276
272#endif 277#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/bf533.h b/arch/blackfin/mach-bf533/include/mach/bf533.h
index 12a416931991..dfc8c1ad2d7a 100644
--- a/arch/blackfin/mach-bf533/include/mach/bf533.h
+++ b/arch/blackfin/mach-bf533/include/mach/bf533.h
@@ -30,8 +30,6 @@
30#ifndef __MACH_BF533_H__ 30#ifndef __MACH_BF533_H__
31#define __MACH_BF533_H__ 31#define __MACH_BF533_H__
32 32
33#define SUPPORTED_REVID 2
34
35#define OFFSET_(x) ((x) & 0x0000FFFF) 33#define OFFSET_(x) ((x) & 0x0000FFFF)
36 34
37/*some misc defines*/ 35/*some misc defines*/
@@ -143,19 +141,19 @@
143 141
144#ifdef CONFIG_BF533 142#ifdef CONFIG_BF533
145#define CPU "BF533" 143#define CPU "BF533"
146#define CPUID 0x027a5000 144#define CPUID 0x27a5
147#endif 145#endif
148#ifdef CONFIG_BF532 146#ifdef CONFIG_BF532
149#define CPU "BF532" 147#define CPU "BF532"
150#define CPUID 0x0275A000 148#define CPUID 0x275A
151#endif 149#endif
152#ifdef CONFIG_BF531 150#ifdef CONFIG_BF531
153#define CPU "BF531" 151#define CPU "BF531"
154#define CPUID 0x027a5000 152#define CPUID 0x27a5
155#endif 153#endif
154
156#ifndef CPU 155#ifndef CPU
157#define CPU "UNKNOWN" 156#error Unknown CPU type - This kernel doesn't seem to be configured properly
158#define CPUID 0x0
159#endif 157#endif
160 158
161#endif /* __MACH_BF533_H__ */ 159#endif /* __MACH_BF533_H__ */
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
index 815bfe5dd1a9..34ab0e4e4242 100644
--- a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
@@ -85,7 +85,7 @@ struct bfin_serial_port {
85 unsigned int rx_dma_channel; 85 unsigned int rx_dma_channel;
86 struct work_struct tx_dma_workqueue; 86 struct work_struct tx_dma_workqueue;
87#else 87#else
88# if ANOMALY_05000230 88# if ANOMALY_05000363
89 unsigned int anomaly_threshold; 89 unsigned int anomaly_threshold;
90# endif 90# endif
91#endif 91#endif
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 8482d22321f3..dc5a30849c15 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -51,7 +51,6 @@
51#include <asm/reboot.h> 51#include <asm/reboot.h>
52#include <asm/portmux.h> 52#include <asm/portmux.h>
53#include <asm/dpmc.h> 53#include <asm/dpmc.h>
54#include <linux/spi/ad7877.h>
55 54
56/* 55/*
57 * Name the Board for the /proc/cpuinfo 56 * Name the Board for the /proc/cpuinfo
@@ -555,6 +554,7 @@ static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
555#endif 554#endif
556 555
557#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 556#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
557#include <linux/spi/ad7877.h>
558static struct bfin5xx_spi_chip spi_ad7877_chip_info = { 558static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
559 .enable_dma = 0, 559 .enable_dma = 0,
560 .bits_per_word = 16, 560 .bits_per_word = 16,
@@ -575,6 +575,28 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
575}; 575};
576#endif 576#endif
577 577
578#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
579#include <linux/spi/ad7879.h>
580static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
581 .enable_dma = 0,
582 .bits_per_word = 16,
583};
584
585static const struct ad7879_platform_data bfin_ad7879_ts_info = {
586 .model = 7879, /* Model = AD7879 */
587 .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
588 .pressure_max = 10000,
589 .pressure_min = 0,
590 .first_conversion_delay = 3, /* wait 512us before do a first conversion */
591 .acquisition_time = 1, /* 4us acquisition time per sample */
592 .median = 2, /* do 8 measurements */
593 .averaging = 1, /* take the average of 4 middle samples */
594 .pen_down_acc_interval = 255, /* 9.4 ms */
595 .gpio_output = 1, /* configure AUX/VBAT/GPIO as GPIO output */
596 .gpio_default = 1, /* During initialization set GPIO = HIGH */
597};
598#endif
599
578#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) 600#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
579static struct bfin5xx_spi_chip spidev_chip_info = { 601static struct bfin5xx_spi_chip spidev_chip_info = {
580 .enable_dma = 0, 602 .enable_dma = 0,
@@ -582,6 +604,13 @@ static struct bfin5xx_spi_chip spidev_chip_info = {
582}; 604};
583#endif 605#endif
584 606
607#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
608static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
609 .enable_dma = 0,
610 .bits_per_word = 8,
611};
612#endif
613
585#if defined(CONFIG_MTD_DATAFLASH) \ 614#if defined(CONFIG_MTD_DATAFLASH) \
586 || defined(CONFIG_MTD_DATAFLASH_MODULE) 615 || defined(CONFIG_MTD_DATAFLASH_MODULE)
587 616
@@ -721,6 +750,18 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
721 .controller_data = &spi_ad7877_chip_info, 750 .controller_data = &spi_ad7877_chip_info,
722 }, 751 },
723#endif 752#endif
753#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
754 {
755 .modalias = "ad7879",
756 .platform_data = &bfin_ad7879_ts_info,
757 .irq = IRQ_PF7,
758 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
759 .bus_num = 0,
760 .chip_select = 1,
761 .controller_data = &spi_ad7879_chip_info,
762 .mode = SPI_CPHA | SPI_CPOL,
763 },
764#endif
724#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) 765#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
725 { 766 {
726 .modalias = "spidev", 767 .modalias = "spidev",
@@ -730,6 +771,16 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
730 .controller_data = &spidev_chip_info, 771 .controller_data = &spidev_chip_info,
731 }, 772 },
732#endif 773#endif
774#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
775 {
776 .modalias = "bfin-lq035q1-spi",
777 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
778 .bus_num = 0,
779 .chip_select = 2,
780 .controller_data = &lq035q1_spi_chip_info,
781 .mode = SPI_CPHA | SPI_CPOL,
782 },
783#endif
733}; 784};
734 785
735#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 786#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
@@ -777,6 +828,34 @@ static struct platform_device bfin_fb_adv7393_device = {
777}; 828};
778#endif 829#endif
779 830
831#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
832#include <asm/bfin-lq035q1.h>
833
834static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
835 .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
836 .use_bl = 0, /* let something else control the LCD Blacklight */
837 .gpio_bl = GPIO_PF7,
838};
839
840static struct resource bfin_lq035q1_resources[] = {
841 {
842 .start = IRQ_PPI_ERROR,
843 .end = IRQ_PPI_ERROR,
844 .flags = IORESOURCE_IRQ,
845 },
846};
847
848static struct platform_device bfin_lq035q1_device = {
849 .name = "bfin-lq035q1",
850 .id = -1,
851 .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
852 .resource = bfin_lq035q1_resources,
853 .dev = {
854 .platform_data = &bfin_lq035q1_data,
855 },
856};
857#endif
858
780#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) 859#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
781static struct resource bfin_uart_resources[] = { 860static struct resource bfin_uart_resources[] = {
782#ifdef CONFIG_SERIAL_BFIN_UART0 861#ifdef CONFIG_SERIAL_BFIN_UART0
@@ -997,6 +1076,10 @@ static struct platform_device *stamp_devices[] __initdata = {
997 &bfin_fb_device, 1076 &bfin_fb_device,
998#endif 1077#endif
999 1078
1079#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
1080 &bfin_lq035q1_device,
1081#endif
1082
1000#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE) 1083#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
1001 &bfin_fb_adv7393_device, 1084 &bfin_fb_adv7393_device,
1002#endif 1085#endif
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S
index 12eb5cc571d0..559a7eef7a38 100644
--- a/arch/blackfin/mach-bf537/head.S
+++ b/arch/blackfin/mach-bf537/head.S
@@ -87,6 +87,9 @@ ENTRY(_start_dma_code)
87 r1 = PLL_BYPASS; /* Bypass the PLL? */ 87 r1 = PLL_BYPASS; /* Bypass the PLL? */
88 r1 = r1 << 8; /* Shift it over */ 88 r1 = r1 << 8; /* Shift it over */
89 r0 = r1 | r0; /* add them all together */ 89 r0 = r1 | r0; /* add them all together */
90#ifdef ANOMALY_05000265
91 r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
92#endif
90 93
91 p0.h = hi(PLL_CTL); 94 p0.h = hi(PLL_CTL);
92 p0.l = lo(PLL_CTL); /* Load the address */ 95 p0.l = lo(PLL_CTL); /* Load the address */
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
index 8460ab9c324f..c68992494f9e 100644
--- a/arch/blackfin/mach-bf537/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h
@@ -158,6 +158,8 @@
158#define ANOMALY_05000266 (0) 158#define ANOMALY_05000266 (0)
159#define ANOMALY_05000311 (0) 159#define ANOMALY_05000311 (0)
160#define ANOMALY_05000323 (0) 160#define ANOMALY_05000323 (0)
161#define ANOMALY_05000353 (1)
161#define ANOMALY_05000363 (0) 162#define ANOMALY_05000363 (0)
163#define ANOMALY_05000386 (1)
162 164
163#endif 165#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/bf537.h b/arch/blackfin/mach-bf537/include/mach/bf537.h
index cfe2a221112e..24d5c9d42323 100644
--- a/arch/blackfin/mach-bf537/include/mach/bf537.h
+++ b/arch/blackfin/mach-bf537/include/mach/bf537.h
@@ -30,8 +30,6 @@
30#ifndef __MACH_BF537_H__ 30#ifndef __MACH_BF537_H__
31#define __MACH_BF537_H__ 31#define __MACH_BF537_H__
32 32
33#define SUPPORTED_REVID 2
34
35/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */ 33/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */
36 34
37#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */ 35#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */
@@ -123,19 +121,19 @@
123 121
124#ifdef CONFIG_BF537 122#ifdef CONFIG_BF537
125#define CPU "BF537" 123#define CPU "BF537"
126#define CPUID 0x027c8000 124#define CPUID 0x27c8
127#endif 125#endif
128#ifdef CONFIG_BF536 126#ifdef CONFIG_BF536
129#define CPU "BF536" 127#define CPU "BF536"
130#define CPUID 0x027c8000 128#define CPUID 0x27c8
131#endif 129#endif
132#ifdef CONFIG_BF534 130#ifdef CONFIG_BF534
133#define CPU "BF534" 131#define CPU "BF534"
134#define CPUID 0x027c6000 132#define CPUID 0x27c6
135#endif 133#endif
134
136#ifndef CPU 135#ifndef CPU
137#define CPU "UNKNOWN" 136#error Unknown CPU type - This kernel doesn't seem to be configured properly
138#define CPUID 0x0
139#endif 137#endif
140 138
141#endif /* __MACH_BF537_H__ */ 139#endif /* __MACH_BF537_H__ */
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c
index ce934ee174e0..24192aaa9275 100644
--- a/arch/blackfin/mach-bf548/boards/cm_bf548.c
+++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c
@@ -36,11 +36,8 @@
36#include <linux/spi/flash.h> 36#include <linux/spi/flash.h>
37#include <linux/irq.h> 37#include <linux/irq.h>
38#include <linux/interrupt.h> 38#include <linux/interrupt.h>
39#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
40#include <linux/usb/musb.h> 39#include <linux/usb/musb.h>
41#endif
42#include <asm/bfin5xx_spi.h> 40#include <asm/bfin5xx_spi.h>
43#include <asm/cplb.h>
44#include <asm/dma.h> 41#include <asm/dma.h>
45#include <asm/gpio.h> 42#include <asm/gpio.h>
46#include <asm/nand.h> 43#include <asm/nand.h>
@@ -175,6 +172,7 @@ static struct resource bfin_uart_resources[] = {
175 { 172 {
176 .start = 0xFFC03100, 173 .start = 0xFFC03100,
177 .end = 0xFFC031FF, 174 .end = 0xFFC031FF,
175 .flags = IORESOURCE_MEM,
178 }, 176 },
179#endif 177#endif
180}; 178};
@@ -268,6 +266,16 @@ static struct resource musb_resources[] = {
268 }, 266 },
269}; 267};
270 268
269static struct musb_hdrc_config musb_config = {
270 .multipoint = 0,
271 .dyn_fifo = 0,
272 .soft_con = 1,
273 .dma = 1,
274 .num_eps = 7,
275 .dma_channels = 7,
276 .gpio_vrsel = GPIO_PH6,
277};
278
271static struct musb_hdrc_platform_data musb_plat = { 279static struct musb_hdrc_platform_data musb_plat = {
272#if defined(CONFIG_USB_MUSB_OTG) 280#if defined(CONFIG_USB_MUSB_OTG)
273 .mode = MUSB_OTG, 281 .mode = MUSB_OTG,
@@ -276,7 +284,7 @@ static struct musb_hdrc_platform_data musb_plat = {
276#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) 284#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
277 .mode = MUSB_PERIPHERAL, 285 .mode = MUSB_PERIPHERAL,
278#endif 286#endif
279 .multipoint = 0, 287 .config = &musb_config,
280}; 288};
281 289
282static u64 musb_dmamask = ~(u32)0; 290static u64 musb_dmamask = ~(u32)0;
@@ -321,12 +329,12 @@ static struct mtd_partition partition_info[] = {
321 { 329 {
322 .name = "linux kernel(nand)", 330 .name = "linux kernel(nand)",
323 .offset = 0, 331 .offset = 0,
324 .size = 4 * SIZE_1M, 332 .size = 4 * 1024 * 1024,
325 }, 333 },
326 { 334 {
327 .name = "file system(nand)", 335 .name = "file system(nand)",
328 .offset = 4 * SIZE_1M, 336 .offset = 4 * 1024 * 1024,
329 .size = (256 - 4) * SIZE_1M, 337 .size = (256 - 4) * 1024 * 1024,
330 }, 338 },
331}; 339};
332 340
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 39357693046d..5288187a3ace 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -38,11 +38,8 @@
38#include <linux/irq.h> 38#include <linux/irq.h>
39#include <linux/i2c.h> 39#include <linux/i2c.h>
40#include <linux/interrupt.h> 40#include <linux/interrupt.h>
41#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
42#include <linux/usb/musb.h> 41#include <linux/usb/musb.h>
43#endif
44#include <asm/bfin5xx_spi.h> 42#include <asm/bfin5xx_spi.h>
45#include <asm/cplb.h>
46#include <asm/dma.h> 43#include <asm/dma.h>
47#include <asm/gpio.h> 44#include <asm/gpio.h>
48#include <asm/nand.h> 45#include <asm/nand.h>
@@ -186,6 +183,37 @@ static struct platform_device bf54x_kpad_device = {
186}; 183};
187#endif 184#endif
188 185
186#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE)
187#include <asm/bfin_rotary.h>
188
189static struct bfin_rotary_platform_data bfin_rotary_data = {
190 /*.rotary_up_key = KEY_UP,*/
191 /*.rotary_down_key = KEY_DOWN,*/
192 .rotary_rel_code = REL_WHEEL,
193 .rotary_button_key = KEY_ENTER,
194 .debounce = 10, /* 0..17 */
195 .mode = ROT_QUAD_ENC | ROT_DEBE,
196};
197
198static struct resource bfin_rotary_resources[] = {
199 {
200 .start = IRQ_CNT,
201 .end = IRQ_CNT,
202 .flags = IORESOURCE_IRQ,
203 },
204};
205
206static struct platform_device bfin_rotary_device = {
207 .name = "bfin-rotary",
208 .id = -1,
209 .num_resources = ARRAY_SIZE(bfin_rotary_resources),
210 .resource = bfin_rotary_resources,
211 .dev = {
212 .platform_data = &bfin_rotary_data,
213 },
214};
215#endif
216
189#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) 217#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
190static struct platform_device rtc_device = { 218static struct platform_device rtc_device = {
191 .name = "rtc-bfin", 219 .name = "rtc-bfin",
@@ -314,6 +342,16 @@ static struct resource musb_resources[] = {
314 }, 342 },
315}; 343};
316 344
345static struct musb_hdrc_config musb_config = {
346 .multipoint = 0,
347 .dyn_fifo = 0,
348 .soft_con = 1,
349 .dma = 1,
350 .num_eps = 7,
351 .dma_channels = 7,
352 .gpio_vrsel = GPIO_PE7,
353};
354
317static struct musb_hdrc_platform_data musb_plat = { 355static struct musb_hdrc_platform_data musb_plat = {
318#if defined(CONFIG_USB_MUSB_OTG) 356#if defined(CONFIG_USB_MUSB_OTG)
319 .mode = MUSB_OTG, 357 .mode = MUSB_OTG,
@@ -322,7 +360,7 @@ static struct musb_hdrc_platform_data musb_plat = {
322#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) 360#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
323 .mode = MUSB_PERIPHERAL, 361 .mode = MUSB_PERIPHERAL,
324#endif 362#endif
325 .multipoint = 0, 363 .config = &musb_config,
326}; 364};
327 365
328static u64 musb_dmamask = ~(u32)0; 366static u64 musb_dmamask = ~(u32)0;
@@ -367,7 +405,7 @@ static struct mtd_partition partition_info[] = {
367 { 405 {
368 .name = "linux kernel(nand)", 406 .name = "linux kernel(nand)",
369 .offset = 0, 407 .offset = 0,
370 .size = 4 * SIZE_1M, 408 .size = 4 * 1024 * 1024,
371 }, 409 },
372 { 410 {
373 .name = "file system(nand)", 411 .name = "file system(nand)",
@@ -424,7 +462,7 @@ static struct mtd_partition ezkit_partitions[] = {
424 .offset = 0, 462 .offset = 0,
425 }, { 463 }, {
426 .name = "linux kernel(nor)", 464 .name = "linux kernel(nor)",
427 .size = 0x1C0000, 465 .size = 0x400000,
428 .offset = MTDPART_OFS_APPEND, 466 .offset = MTDPART_OFS_APPEND,
429 }, { 467 }, {
430 .name = "file system(nor)", 468 .name = "file system(nor)",
@@ -441,7 +479,7 @@ static struct physmap_flash_data ezkit_flash_data = {
441 479
442static struct resource ezkit_flash_resource = { 480static struct resource ezkit_flash_resource = {
443 .start = 0x20000000, 481 .start = 0x20000000,
444 .end = 0x20ffffff, 482 .end = 0x21ffffff,
445 .flags = IORESOURCE_MEM, 483 .flags = IORESOURCE_MEM,
446}; 484};
447 485
@@ -551,7 +589,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
551{ 589{
552 .modalias = "ad7877", 590 .modalias = "ad7877",
553 .platform_data = &bfin_ad7877_ts_info, 591 .platform_data = &bfin_ad7877_ts_info,
554 .irq = IRQ_PJ11, 592 .irq = IRQ_PJ11, /* newer boards (Rev 1.4+) use IRQ_PB4 */
555 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 593 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
556 .bus_num = 0, 594 .bus_num = 0,
557 .chip_select = 2, 595 .chip_select = 2,
@@ -810,6 +848,10 @@ static struct platform_device *ezkit_devices[] __initdata = {
810 &bf54x_kpad_device, 848 &bf54x_kpad_device,
811#endif 849#endif
812 850
851#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE)
852 &bfin_rotary_device,
853#endif
854
813#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) 855#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
814 &i2c_bfin_twi0_device, 856 &i2c_bfin_twi0_device,
815#if !defined(CONFIG_BF542) 857#if !defined(CONFIG_BF542)
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S
index 4d5cfeacb123..051b05c88027 100644
--- a/arch/blackfin/mach-bf548/head.S
+++ b/arch/blackfin/mach-bf548/head.S
@@ -73,25 +73,19 @@ ENTRY(_start_dma_code)
73 w[p0] = r0.l; 73 w[p0] = r0.l;
74 ssync; 74 ssync;
75 75
76#if defined(CONFIG_BF54x) 76 /* enable self refresh via SRREQ */
77 P2.H = hi(EBIU_RSTCTL); 77 P2.H = hi(EBIU_RSTCTL);
78 P2.L = lo(EBIU_RSTCTL); 78 P2.L = lo(EBIU_RSTCTL);
79 R0 = [P2]; 79 R0 = [P2];
80 BITSET (R0, 3); 80 BITSET (R0, 3);
81#else
82 P2.H = hi(EBIU_SDGCTL);
83 P2.L = lo(EBIU_SDGCTL);
84 R0 = [P2];
85 BITSET (R0, 24);
86#endif
87 [P2] = R0; 81 [P2] = R0;
88 SSYNC; 82 SSYNC;
89#if defined(CONFIG_BF54x) 83
84 /* wait for SRACK bit to be set */
90.LSRR_MODE: 85.LSRR_MODE:
91 R0 = [P2]; 86 R0 = [P2];
92 CC = BITTST(R0, 4); 87 CC = BITTST(R0, 4);
93 if !CC JUMP .LSRR_MODE; 88 if !CC JUMP .LSRR_MODE;
94#endif
95 89
96 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ 90 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
97 r0 = r0 << 9; /* Shift it over, */ 91 r0 = r0 << 9; /* Shift it over, */
@@ -100,6 +94,9 @@ ENTRY(_start_dma_code)
100 r1 = PLL_BYPASS; /* Bypass the PLL? */ 94 r1 = PLL_BYPASS; /* Bypass the PLL? */
101 r1 = r1 << 8; /* Shift it over */ 95 r1 = r1 << 8; /* Shift it over */
102 r0 = r1 | r0; /* add them all together */ 96 r0 = r1 | r0; /* add them all together */
97#ifdef ANOMALY_05000265
98 r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
99#endif
103 100
104 p0.h = hi(PLL_CTL); 101 p0.h = hi(PLL_CTL);
105 p0.l = lo(PLL_CTL); /* Load the address */ 102 p0.l = lo(PLL_CTL); /* Load the address */
@@ -123,7 +120,7 @@ ENTRY(_start_dma_code)
123 w[p0] = r0.l; 120 w[p0] = r0.l;
124 ssync; 121 ssync;
125 122
126#if defined(CONFIG_BF54x) 123 /* disable self refresh by clearing SRREQ */
127 P2.H = hi(EBIU_RSTCTL); 124 P2.H = hi(EBIU_RSTCTL);
128 P2.L = lo(EBIU_RSTCTL); 125 P2.L = lo(EBIU_RSTCTL);
129 R0 = [P2]; 126 R0 = [P2];
@@ -155,41 +152,6 @@ ENTRY(_start_dma_code)
155 r0.h = hi(mem_DDRCTL2); 152 r0.h = hi(mem_DDRCTL2);
156 [p0] = r0; 153 [p0] = r0;
157 ssync; 154 ssync;
158#else
159 p0.l = lo(EBIU_SDRRC);
160 p0.h = hi(EBIU_SDRRC);
161 r0 = mem_SDRRC;
162 w[p0] = r0.l;
163 ssync;
164
165 p0.l = LO(EBIU_SDBCTL);
166 p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
167 r0 = mem_SDBCTL;
168 w[p0] = r0.l;
169 ssync;
170
171 P2.H = hi(EBIU_SDGCTL);
172 P2.L = lo(EBIU_SDGCTL);
173 R0 = [P2];
174 BITCLR (R0, 24);
175 p0.h = hi(EBIU_SDSTAT);
176 p0.l = lo(EBIU_SDSTAT);
177 r2.l = w[p0];
178 cc = bittst(r2,3);
179 if !cc jump .Lskip;
180 NOP;
181 BITSET (R0, 23);
182.Lskip:
183 [P2] = R0;
184 SSYNC;
185
186 R0.L = lo(mem_SDGCTL);
187 R0.H = hi(mem_SDGCTL);
188 R1 = [p2];
189 R1 = R1 | R0;
190 [P2] = R1;
191 SSYNC;
192#endif
193 155
194 RTS; 156 RTS;
195ENDPROC(_start_dma_code) 157ENDPROC(_start_dma_code)
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index 3ad59655881a..816b09278f62 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -2,18 +2,18 @@
2 * File: include/asm-blackfin/mach-bf548/anomaly.h 2 * File: include/asm-blackfin/mach-bf548/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2007 Analog Devices Inc. 5 * Copyright (C) 2004-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List 10 * - Revision G, 08/07/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
14#define _MACH_ANOMALY_H_ 14#define _MACH_ANOMALY_H_
15 15
16/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ 16/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
17#define ANOMALY_05000074 (1) 17#define ANOMALY_05000074 (1)
18/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ 18/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
19#define ANOMALY_05000119 (1) 19#define ANOMALY_05000119 (1)
@@ -36,14 +36,14 @@
36/* TWI Slave Boot Mode Is Not Functional */ 36/* TWI Slave Boot Mode Is Not Functional */
37#define ANOMALY_05000324 (__SILICON_REVISION__ < 1) 37#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
38/* External FIFO Boot Mode Is Not Functional */ 38/* External FIFO Boot Mode Is Not Functional */
39#define ANOMALY_05000325 (__SILICON_REVISION__ < 1) 39#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
40/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ 40/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
41#define ANOMALY_05000327 (__SILICON_REVISION__ < 1) 41#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
42/* Incorrect Access of OTP_STATUS During otp_write() Function */ 42/* Incorrect Access of OTP_STATUS During otp_write() Function */
43#define ANOMALY_05000328 (__SILICON_REVISION__ < 1) 43#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
44/* Synchronous Burst Flash Boot Mode Is Not Functional */ 44/* Synchronous Burst Flash Boot Mode Is Not Functional */
45#define ANOMALY_05000329 (__SILICON_REVISION__ < 1) 45#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
46/* Host DMA Boot Mode Is Not Functional */ 46/* Host DMA Boot Modes Are Not Functional */
47#define ANOMALY_05000330 (__SILICON_REVISION__ < 1) 47#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
48/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ 48/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
49#define ANOMALY_05000334 (__SILICON_REVISION__ < 1) 49#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
@@ -61,26 +61,102 @@
61#define ANOMALY_05000344 (__SILICON_REVISION__ < 1) 61#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
62/* USB Calibration Value Is Not Intialized */ 62/* USB Calibration Value Is Not Intialized */
63#define ANOMALY_05000346 (__SILICON_REVISION__ < 1) 63#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
64/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ 64/* USB Calibration Value to use */
65#define ANOMALY_05000346_value 0x5411
66/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
65#define ANOMALY_05000347 (__SILICON_REVISION__ < 1) 67#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
66/* Data Lost when Core Reads SDH Data FIFO */ 68/* Data Lost when Core Reads SDH Data FIFO */
67#define ANOMALY_05000349 (__SILICON_REVISION__ < 1) 69#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
68/* PLL Status Register Is Inaccurate */ 70/* PLL Status Register Is Inaccurate */
69#define ANOMALY_05000351 (__SILICON_REVISION__ < 1) 71#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
72/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
73#define ANOMALY_05000353 (__SILICON_REVISION__ < 2)
74/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
75#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
76/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
77#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
70/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ 78/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
71#define ANOMALY_05000357 (1) 79#define ANOMALY_05000357 (1)
72/* External Memory Read Access Hangs Core With PLL Bypass */ 80/* External Memory Read Access Hangs Core With PLL Bypass */
73#define ANOMALY_05000360 (1) 81#define ANOMALY_05000360 (1)
74/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ 82/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
75#define ANOMALY_05000365 (1) 83#define ANOMALY_05000365 (1)
84/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
85#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
76/* Addressing Conflict between Boot ROM and Asynchronous Memory */ 86/* Addressing Conflict between Boot ROM and Asynchronous Memory */
77#define ANOMALY_05000369 (1) 87#define ANOMALY_05000369 (1)
88/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
89#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
78/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ 90/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
79#define ANOMALY_05000371 (1) 91#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
92/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
93#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
80/* Mobile DDR Operation Not Functional */ 94/* Mobile DDR Operation Not Functional */
81#define ANOMALY_05000377 (1) 95#define ANOMALY_05000377 (1)
82/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ 96/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
83#define ANOMALY_05000378 (1) 97#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
98/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
99#define ANOMALY_05000379 (1)
100/* 8-Bit NAND Flash Boot Mode Not Functional */
101#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
102/* Some ATAPI Modes Are Not Functional */
103#define ANOMALY_05000383 (1)
104/* Boot from OTP Memory Not Functional */
105#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
106/* bfrom_SysControl() Firmware Routine Not Functional */
107#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
108/* Programmable Preboot Settings Not Functional */
109#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
110/* CRC32 Checksum Support Not Functional */
111#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
112/* Reset Vector Must Not Be in SDRAM Memory Space */
113#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
114/* Changed Meaning of BCODE Field in SYSCR Register */
115#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
116/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
117#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
118/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
119#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
120/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
121#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
122/* Log Buffer Not Functional */
123#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
124/* Hook Routine Not Functional */
125#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
126/* Header Indirect Bit Not Functional */
127#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
128/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
129#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
130/* Lockbox SESR Disallows Certain User Interrupts */
131#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
132/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
133#define ANOMALY_05000405 (1)
134/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
135#define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
136/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
137#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
138/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
139#define ANOMALY_05000408 (1)
140/* Lockbox firmware leaves MDMA0 channel enabled */
141#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
142/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
143#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
144/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
145#define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
146/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
147#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
148/* Speculative Fetches Can Cause Undesired External FIFO Operations */
149#define ANOMALY_05000416 (1)
150/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
151#define ANOMALY_05000425 (1)
152/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */
153#define ANOMALY_05000426 (1)
154/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
155#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
156/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Behaves as a Buffer Status Bit Instead of an IRQ Status Bit */
157#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
158/* Software System Reset Corrupts PLL_LOCKCNT Register */
159#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
84 160
85/* Anomalies that don't exist on this proc */ 161/* Anomalies that don't exist on this proc */
86#define ANOMALY_05000125 (0) 162#define ANOMALY_05000125 (0)
@@ -93,6 +169,7 @@
93#define ANOMALY_05000263 (0) 169#define ANOMALY_05000263 (0)
94#define ANOMALY_05000266 (0) 170#define ANOMALY_05000266 (0)
95#define ANOMALY_05000273 (0) 171#define ANOMALY_05000273 (0)
172#define ANOMALY_05000307 (0)
96#define ANOMALY_05000311 (0) 173#define ANOMALY_05000311 (0)
97#define ANOMALY_05000323 (0) 174#define ANOMALY_05000323 (0)
98#define ANOMALY_05000363 (0) 175#define ANOMALY_05000363 (0)
diff --git a/arch/blackfin/mach-bf548/include/mach/bf548.h b/arch/blackfin/mach-bf548/include/mach/bf548.h
index e748588e8930..49f9b403d458 100644
--- a/arch/blackfin/mach-bf548/include/mach/bf548.h
+++ b/arch/blackfin/mach-bf548/include/mach/bf548.h
@@ -30,8 +30,6 @@
30#ifndef __MACH_BF548_H__ 30#ifndef __MACH_BF548_H__
31#define __MACH_BF548_H__ 31#define __MACH_BF548_H__
32 32
33#define SUPPORTED_REVID 0
34
35#define OFFSET_(x) ((x) & 0x0000FFFF) 33#define OFFSET_(x) ((x) & 0x0000FFFF)
36 34
37/*some misc defines*/ 35/*some misc defines*/
@@ -108,20 +106,23 @@
108 106
109#if defined(CONFIG_BF542) 107#if defined(CONFIG_BF542)
110# define CPU "BF542" 108# define CPU "BF542"
111# define CPUID 0x027c8000 109# define CPUID 0x27de
112#elif defined(CONFIG_BF544) 110#elif defined(CONFIG_BF544)
113# define CPU "BF544" 111# define CPU "BF544"
114# define CPUID 0x027c8000 112# define CPUID 0x27de
115#elif defined(CONFIG_BF547) 113#elif defined(CONFIG_BF547)
116# define CPU "BF547" 114# define CPU "BF547"
115# define CPUID 0x27de
117#elif defined(CONFIG_BF548) 116#elif defined(CONFIG_BF548)
118# define CPU "BF548" 117# define CPU "BF548"
119# define CPUID 0x027c6000 118# define CPUID 0x27de
120#elif defined(CONFIG_BF549) 119#elif defined(CONFIG_BF549)
121# define CPU "BF549" 120# define CPU "BF549"
122#else 121# define CPUID 0x27de
123# define CPU "UNKNOWN" 122#endif
124# define CPUID 0x0 123
124#ifndef CPU
125#error Unknown CPU type - This kernel doesn't seem to be configured properly
125#endif 126#endif
126 127
127#endif /* __MACH_BF48_H__ */ 128#endif /* __MACH_BF48_H__ */
diff --git a/arch/blackfin/mach-bf548/include/mach/mem_map.h b/arch/blackfin/mach-bf548/include/mach/mem_map.h
index f99f47bc3a07..a2228428dc06 100644
--- a/arch/blackfin/mach-bf548/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf548/include/mach/mem_map.h
@@ -94,13 +94,13 @@
94#endif /*CONFIG_BFIN_DCACHE*/ 94#endif /*CONFIG_BFIN_DCACHE*/
95 95
96/* Level 2 Memory */ 96/* Level 2 Memory */
97#if !defined(CONFIG_BF542) 97#define L2_START 0xFEB00000
98# define L2_START 0xFEB00000 98#if defined(CONFIG_BF542)
99# if defined(CONFIG_BF544) 99# define L2_LENGTH 0
100# define L2_LENGTH 0x10000 100#elif defined(CONFIG_BF544)
101# else 101# define L2_LENGTH 0x10000
102# define L2_LENGTH 0x20000 102#else
103# endif 103# define L2_LENGTH 0x20000
104#endif 104#endif
105 105
106/* Scratch Pad Memory */ 106/* Scratch Pad Memory */
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
index 75ea6a905829..0b28137b3dea 100644
--- a/arch/blackfin/mach-bf561/head.S
+++ b/arch/blackfin/mach-bf561/head.S
@@ -77,6 +77,9 @@ ENTRY(_start_dma_code)
77 r1 = PLL_BYPASS; /* Bypass the PLL? */ 77 r1 = PLL_BYPASS; /* Bypass the PLL? */
78 r1 = r1 << 8; /* Shift it over */ 78 r1 = r1 << 8; /* Shift it over */
79 r0 = r1 | r0; /* add them all together */ 79 r0 = r1 | r0; /* add them all together */
80#ifdef ANOMALY_05000265
81 r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
82#endif
80 83
81 p0.h = hi(PLL_CTL); 84 p0.h = hi(PLL_CTL);
82 p0.l = lo(PLL_CTL); /* Load the address */ 85 p0.l = lo(PLL_CTL); /* Load the address */
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 5c5d7d7d695f..22990df04ae1 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -270,5 +270,7 @@
270#define ANOMALY_05000183 (0) 270#define ANOMALY_05000183 (0)
271#define ANOMALY_05000273 (0) 271#define ANOMALY_05000273 (0)
272#define ANOMALY_05000311 (0) 272#define ANOMALY_05000311 (0)
273#define ANOMALY_05000353 (1)
274#define ANOMALY_05000386 (1)
273 275
274#endif 276#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/bf561.h b/arch/blackfin/mach-bf561/include/mach/bf561.h
index 3ef9e5f36136..18b1b3a223ab 100644
--- a/arch/blackfin/mach-bf561/include/mach/bf561.h
+++ b/arch/blackfin/mach-bf561/include/mach/bf561.h
@@ -30,8 +30,6 @@
30#ifndef __MACH_BF561_H__ 30#ifndef __MACH_BF561_H__
31#define __MACH_BF561_H__ 31#define __MACH_BF561_H__
32 32
33#define SUPPORTED_REVID 0x3
34
35#define OFFSET_(x) ((x) & 0x0000FFFF) 33#define OFFSET_(x) ((x) & 0x0000FFFF)
36 34
37/*some misc defines*/ 35/*some misc defines*/
@@ -213,11 +211,11 @@
213 211
214#ifdef CONFIG_BF561 212#ifdef CONFIG_BF561
215#define CPU "BF561" 213#define CPU "BF561"
216#define CPUID 0x027bb000 214#define CPUID 0x27bb
217#endif 215#endif
216
218#ifndef CPU 217#ifndef CPU
219#define CPU "UNKNOWN" 218#error Unknown CPU type - This kernel doesn't seem to be configured properly
220#define CPUID 0x0
221#endif 219#endif
222 220
223#endif /* __MACH_BF561_H__ */ 221#endif /* __MACH_BF561_H__ */
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
index e0ce0c1843d4..f5327264357c 100644
--- a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
@@ -85,7 +85,7 @@ struct bfin_serial_port {
85 unsigned int rx_dma_channel; 85 unsigned int rx_dma_channel;
86 struct work_struct tx_dma_workqueue; 86 struct work_struct tx_dma_workqueue;
87#else 87#else
88# if ANOMALY_05000230 88# if ANOMALY_05000363
89 unsigned int anomaly_threshold; 89 unsigned int anomaly_threshold;
90# endif 90# endif
91#endif 91#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h
index c26d8486cc4b..f1d4c0637bd2 100644
--- a/arch/blackfin/mach-bf561/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf561/include/mach/mem_map.h
@@ -35,9 +35,16 @@
35/* Memory Map for ADSP-BF561 processors */ 35/* Memory Map for ADSP-BF561 processors */
36 36
37#ifdef CONFIG_BF561 37#ifdef CONFIG_BF561
38#define L1_CODE_START 0xFFA00000 38#define COREA_L1_CODE_START 0xFFA00000
39#define L1_DATA_A_START 0xFF800000 39#define COREA_L1_DATA_A_START 0xFF800000
40#define L1_DATA_B_START 0xFF900000 40#define COREA_L1_DATA_B_START 0xFF900000
41#define COREB_L1_CODE_START 0xFF600000
42#define COREB_L1_DATA_A_START 0xFF400000
43#define COREB_L1_DATA_B_START 0xFF500000
44
45#define L1_CODE_START COREA_L1_CODE_START
46#define L1_DATA_A_START COREA_L1_DATA_A_START
47#define L1_DATA_B_START COREA_L1_DATA_B_START
41 48
42#define L1_CODE_LENGTH 0x4000 49#define L1_CODE_LENGTH 0x4000
43 50
@@ -72,7 +79,10 @@
72 79
73/* Scratch Pad Memory */ 80/* Scratch Pad Memory */
74 81
75#define L1_SCRATCH_START 0xFFB00000 82#define COREA_L1_SCRATCH_START 0xFFB00000
83#define COREB_L1_SCRATCH_START 0xFF700000
84
85#define L1_SCRATCH_START COREA_L1_SCRATCH_START
76#define L1_SCRATCH_LENGTH 0x1000 86#define L1_SCRATCH_LENGTH 0x1000
77 87
78#endif /* _MEM_MAP_533_H_ */ 88#endif /* _MEM_MAP_533_H_ */
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 847c172a99eb..c13fa8da28c7 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -129,6 +129,18 @@ ENTRY(_ex_icplb_miss)
129#else 129#else
130 call __cplb_hdr; 130 call __cplb_hdr;
131#endif 131#endif
132
133#ifdef CONFIG_DEBUG_DOUBLEFAULT
134 /* While we were processing this, did we double fault? */
135 r7 = SEQSTAT; /* reason code is in bit 5:0 */
136 r6.l = lo(SEQSTAT_EXCAUSE);
137 r6.h = hi(SEQSTAT_EXCAUSE);
138 r7 = r7 & r6;
139 r6 = 0x25;
140 CC = R7 == R6;
141 if CC JUMP _double_fault;
142#endif
143
132 DEBUG_HWTRACE_RESTORE(p5, r7) 144 DEBUG_HWTRACE_RESTORE(p5, r7)
133 RESTORE_ALL_SYS 145 RESTORE_ALL_SYS
134 SP = EX_SCRATCH_REG; 146 SP = EX_SCRATCH_REG;
@@ -136,11 +148,8 @@ ENTRY(_ex_icplb_miss)
136ENDPROC(_ex_icplb_miss) 148ENDPROC(_ex_icplb_miss)
137 149
138ENTRY(_ex_syscall) 150ENTRY(_ex_syscall)
139 (R7:6,P5:4) = [sp++];
140 ASTAT = [sp++];
141 raise 15; /* invoked by TRAP #0, for sys call */ 151 raise 15; /* invoked by TRAP #0, for sys call */
142 sp = EX_SCRATCH_REG; 152 jump.s _bfin_return_from_exception;
143 rtx
144ENDPROC(_ex_syscall) 153ENDPROC(_ex_syscall)
145 154
146ENTRY(_ex_soft_bp) 155ENTRY(_ex_soft_bp)
@@ -181,8 +190,8 @@ ENTRY(_ex_single_step)
181 if cc jump .Lfind_priority_done; 190 if cc jump .Lfind_priority_done;
182 jump.s .Lfind_priority_start; 191 jump.s .Lfind_priority_start;
183.Lfind_priority_done: 192.Lfind_priority_done:
184 p4.l = _debugger_step; 193 p4.l = _kgdb_single_step;
185 p4.h = _debugger_step; 194 p4.h = _kgdb_single_step;
186 r6 = [p4]; 195 r6 = [p4];
187 cc = r6 == 0; 196 cc = r6 == 0;
188 if cc jump .Ldo_single_step; 197 if cc jump .Ldo_single_step;
@@ -250,6 +259,29 @@ ENTRY(_bfin_return_from_exception)
250 R7=LC1; 259 R7=LC1;
251 LC1=R7; 260 LC1=R7;
252#endif 261#endif
262
263#ifdef CONFIG_DEBUG_DOUBLEFAULT
264 /* While we were processing the current exception,
265 * did we cause another, and double fault?
266 */
267 r7 = SEQSTAT; /* reason code is in bit 5:0 */
268 r6.l = lo(SEQSTAT_EXCAUSE);
269 r6.h = hi(SEQSTAT_EXCAUSE);
270 r7 = r7 & r6;
271 r6 = 0x25;
272 CC = R7 == R6;
273 if CC JUMP _double_fault;
274
275 /* Did we cause a HW error? */
276 p5.l = lo(ILAT);
277 p5.h = hi(ILAT);
278 r6 = [p5];
279 r7 = 0x20; /* Did I just cause anther HW error? */
280 r7 = r7 & r1;
281 CC = R7 == R6;
282 if CC JUMP _double_fault;
283#endif
284
253 (R7:6,P5:4) = [sp++]; 285 (R7:6,P5:4) = [sp++];
254 ASTAT = [sp++]; 286 ASTAT = [sp++];
255 sp = EX_SCRATCH_REG; 287 sp = EX_SCRATCH_REG;
@@ -292,6 +324,14 @@ ENTRY(_ex_trap_c)
292 [p4] = p5; 324 [p4] = p5;
293 csync; 325 csync;
294 326
327#ifndef CONFIG_DEBUG_DOUBLEFAULT
328 /*
329 * Save these registers, as they are only valid in exception context
330 * (where we are now - as soon as we defer to IRQ5, they can change)
331 * DCPLB_STATUS and ICPLB_STATUS are also only valid in EVT3,
332 * but they are not very interesting, so don't save them
333 */
334
295 p4.l = lo(DCPLB_FAULT_ADDR); 335 p4.l = lo(DCPLB_FAULT_ADDR);
296 p4.h = hi(DCPLB_FAULT_ADDR); 336 p4.h = hi(DCPLB_FAULT_ADDR);
297 r7 = [p4]; 337 r7 = [p4];
@@ -304,12 +344,11 @@ ENTRY(_ex_trap_c)
304 p5.l = _saved_icplb_fault_addr; 344 p5.l = _saved_icplb_fault_addr;
305 [p5] = r7; 345 [p5] = r7;
306 346
307 p4.l = _excpt_saved_stuff;
308 p4.h = _excpt_saved_stuff;
309
310 r6 = retx; 347 r6 = retx;
348 p4.l = _saved_retx;
349 p4.h = _saved_retx;
311 [p4] = r6; 350 [p4] = r6;
312 351#endif
313 r6 = SYSCFG; 352 r6 = SYSCFG;
314 [p4 + 4] = r6; 353 [p4 + 4] = r6;
315 BITCLR(r6, 0); 354 BITCLR(r6, 0);
@@ -327,59 +366,56 @@ ENTRY(_ex_trap_c)
327 r6 = 0x3f; 366 r6 = 0x3f;
328 sti r6; 367 sti r6;
329 368
330 (R7:6,P5:4) = [sp++];
331 ASTAT = [sp++];
332 SP = EX_SCRATCH_REG;
333 raise 5; 369 raise 5;
334 rtx; 370 jump.s _bfin_return_from_exception;
335ENDPROC(_ex_trap_c) 371ENDPROC(_ex_trap_c)
336 372
337/* We just realized we got an exception, while we were processing a different 373/* We just realized we got an exception, while we were processing a different
338 * exception. This is a unrecoverable event, so crash 374 * exception. This is a unrecoverable event, so crash
339 */ 375 */
340ENTRY(_double_fault) 376ENTRY(_double_fault)
341 /* Turn caches & protection off, to ensure we don't get any more 377 /* Turn caches & protection off, to ensure we don't get any more
342 * double exceptions 378 * double exceptions
343 */ 379 */
344 380
345 P4.L = LO(IMEM_CONTROL); 381 P4.L = LO(IMEM_CONTROL);
346 P4.H = HI(IMEM_CONTROL); 382 P4.H = HI(IMEM_CONTROL);
347 383
348 R5 = [P4]; /* Control Register*/ 384 R5 = [P4]; /* Control Register*/
349 BITCLR(R5,ENICPLB_P); 385 BITCLR(R5,ENICPLB_P);
350 SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ 386 SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
351 .align 8; 387 .align 8;
352 [P4] = R5; 388 [P4] = R5;
353 SSYNC; 389 SSYNC;
354 390
355 P4.L = LO(DMEM_CONTROL); 391 P4.L = LO(DMEM_CONTROL);
356 P4.H = HI(DMEM_CONTROL); 392 P4.H = HI(DMEM_CONTROL);
357 R5 = [P4]; 393 R5 = [P4];
358 BITCLR(R5,ENDCPLB_P); 394 BITCLR(R5,ENDCPLB_P);
359 SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ 395 SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
360 .align 8; 396 .align 8;
361 [P4] = R5; 397 [P4] = R5;
362 SSYNC; 398 SSYNC;
363 399
364 /* Fix up the stack */ 400 /* Fix up the stack */
365 (R7:6,P5:4) = [sp++]; 401 (R7:6,P5:4) = [sp++];
366 ASTAT = [sp++]; 402 ASTAT = [sp++];
367 SP = EX_SCRATCH_REG; 403 SP = EX_SCRATCH_REG;
368 404
369 /* We should be out of the exception stack, and back down into 405 /* We should be out of the exception stack, and back down into
370 * kernel or user space stack 406 * kernel or user space stack
371 */ 407 */
372 SAVE_ALL_SYS 408 SAVE_ALL_SYS
373 409
374 /* The dumping functions expect the return address in the RETI 410 /* The dumping functions expect the return address in the RETI
375 * slot. */ 411 * slot. */
376 r6 = retx; 412 r6 = retx;
377 [sp + PT_PC] = r6; 413 [sp + PT_PC] = r6;
378 414
379 r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ 415 r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
380 SP += -12; 416 SP += -12;
381 call _double_fault_c; 417 call _double_fault_c;
382 SP += 12; 418 SP += 12;
383.L_double_fault_panic: 419.L_double_fault_panic:
384 JUMP .L_double_fault_panic 420 JUMP .L_double_fault_panic
385 421
@@ -388,8 +424,8 @@ ENDPROC(_double_fault)
388ENTRY(_exception_to_level5) 424ENTRY(_exception_to_level5)
389 SAVE_ALL_SYS 425 SAVE_ALL_SYS
390 426
391 p4.l = _excpt_saved_stuff; 427 p4.l = _saved_retx;
392 p4.h = _excpt_saved_stuff; 428 p4.h = _saved_retx;
393 r6 = [p4]; 429 r6 = [p4];
394 [sp + PT_PC] = r6; 430 [sp + PT_PC] = r6;
395 431
@@ -420,6 +456,17 @@ ENTRY(_exception_to_level5)
420 call _trap_c; 456 call _trap_c;
421 SP += 12; 457 SP += 12;
422 458
459#ifdef CONFIG_DEBUG_DOUBLEFAULT
460 /* Grab ILAT */
461 p2.l = lo(ILAT);
462 p2.h = hi(ILAT);
463 r0 = [p2];
464 r1 = 0x20; /* Did I just cause anther HW error? */
465 r0 = r0 & r1;
466 CC = R0 == R1;
467 if CC JUMP _double_fault;
468#endif
469
423 call _ret_from_exception; 470 call _ret_from_exception;
424 RESTORE_ALL_SYS 471 RESTORE_ALL_SYS
425 rti; 472 rti;
@@ -436,7 +483,48 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/
436 /* Try to deal with syscalls quickly. */ 483 /* Try to deal with syscalls quickly. */
437 [--sp] = ASTAT; 484 [--sp] = ASTAT;
438 [--sp] = (R7:6,P5:4); 485 [--sp] = (R7:6,P5:4);
486
487#if ANOMALY_05000283 || ANOMALY_05000315
488 cc = r7 == r7;
489 p5.h = HI(CHIPID);
490 p5.l = LO(CHIPID);
491 if cc jump 1f;
492 r7.l = W[p5];
4931:
494#endif
495
496#ifdef CONFIG_DEBUG_DOUBLEFAULT
497 /*
498 * Save these registers, as they are only valid in exception context
499 * (where we are now - as soon as we defer to IRQ5, they can change)
500 * DCPLB_STATUS and ICPLB_STATUS are also only valid in EVT3,
501 * but they are not very interesting, so don't save them
502 */
503
504 p4.l = lo(DCPLB_FAULT_ADDR);
505 p4.h = hi(DCPLB_FAULT_ADDR);
506 r7 = [p4];
507 p5.h = _saved_dcplb_fault_addr;
508 p5.l = _saved_dcplb_fault_addr;
509 [p5] = r7;
510
511 r7 = [p4 + (ICPLB_FAULT_ADDR - DCPLB_FAULT_ADDR)];
512 p5.h = _saved_icplb_fault_addr;
513 p5.l = _saved_icplb_fault_addr;
514 [p5] = r7;
515
516 p4.l = _saved_retx;
517 p4.h = _saved_retx;
518 r6 = retx;
519 [p4] = r6;
520
439 r7 = SEQSTAT; /* reason code is in bit 5:0 */ 521 r7 = SEQSTAT; /* reason code is in bit 5:0 */
522 p4.l = _saved_seqstat;
523 p4.h = _saved_seqstat;
524 [p4] = r7;
525#else
526 r7 = SEQSTAT; /* reason code is in bit 5:0 */
527#endif
440 r6.l = lo(SEQSTAT_EXCAUSE); 528 r6.l = lo(SEQSTAT_EXCAUSE);
441 r6.h = hi(SEQSTAT_EXCAUSE); 529 r6.h = hi(SEQSTAT_EXCAUSE);
442 r7 = r7 & r6; 530 r7 = r7 & r6;
@@ -616,6 +704,9 @@ ENTRY(_system_call)
616 rts; 704 rts;
617ENDPROC(_system_call) 705ENDPROC(_system_call)
618 706
707/* Do not mark as ENTRY() to avoid error in assembler ...
708 * this symbol need not be global anyways, so ...
709 */
619_sys_trace: 710_sys_trace:
620 call _syscall_trace; 711 call _syscall_trace;
621 712
@@ -941,6 +1032,15 @@ ENTRY(_early_trap)
941 SAVE_ALL_SYS 1032 SAVE_ALL_SYS
942 trace_buffer_stop(p0,r0); 1033 trace_buffer_stop(p0,r0);
943 1034
1035#if ANOMALY_05000283 || ANOMALY_05000315
1036 cc = r5 == r5;
1037 p4.h = HI(CHIPID);
1038 p4.l = LO(CHIPID);
1039 if cc jump 1f;
1040 r5.l = W[p4];
10411:
1042#endif
1043
944 /* Turn caches off, to ensure we don't get double exceptions */ 1044 /* Turn caches off, to ensure we don't get double exceptions */
945 1045
946 P4.L = LO(IMEM_CONTROL); 1046 P4.L = LO(IMEM_CONTROL);
@@ -992,7 +1092,12 @@ ENTRY(_ex_table)
992 */ 1092 */
993 .long _ex_syscall /* 0x00 - User Defined - Linux Syscall */ 1093 .long _ex_syscall /* 0x00 - User Defined - Linux Syscall */
994 .long _ex_soft_bp /* 0x01 - User Defined - Software breakpoint */ 1094 .long _ex_soft_bp /* 0x01 - User Defined - Software breakpoint */
1095#ifdef CONFIG_KGDB
1096 .long _ex_trap_c /* 0x02 - User Defined - KGDB initial connection
1097 and break signal trap */
1098#else
995 .long _ex_replaceable /* 0x02 - User Defined */ 1099 .long _ex_replaceable /* 0x02 - User Defined */
1100#endif
996 .long _ex_trap_c /* 0x03 - User Defined - userspace stack overflow */ 1101 .long _ex_trap_c /* 0x03 - User Defined - userspace stack overflow */
997 .long _ex_trap_c /* 0x04 - User Defined - dump trace buffer */ 1102 .long _ex_trap_c /* 0x04 - User Defined - dump trace buffer */
998 .long _ex_replaceable /* 0x05 - User Defined */ 1103 .long _ex_replaceable /* 0x05 - User Defined */
@@ -1432,15 +1537,7 @@ ENTRY(_sys_call_table)
1432 .rept NR_syscalls-(.-_sys_call_table)/4 1537 .rept NR_syscalls-(.-_sys_call_table)/4
1433 .long _sys_ni_syscall 1538 .long _sys_ni_syscall
1434 .endr 1539 .endr
1435 1540END(_sys_call_table)
1436 /*
1437 * Used to save the real RETX, IMASK and SYSCFG when temporarily
1438 * storing safe values across the transition from exception to IRQ5.
1439 */
1440_excpt_saved_stuff:
1441 .long 0;
1442 .long 0;
1443 .long 0;
1444 1541
1445_exception_stack: 1542_exception_stack:
1446 .rept 1024 1543 .rept 1024
diff --git a/arch/blackfin/mach-common/head.S b/arch/blackfin/mach-common/head.S
index 191b4e974c4b..3069df580729 100644
--- a/arch/blackfin/mach-common/head.S
+++ b/arch/blackfin/mach-common/head.S
@@ -68,6 +68,16 @@ ENTRY(__start)
68 M2 = r0; 68 M2 = r0;
69 M3 = r0; 69 M3 = r0;
70 70
71 /*
72 * Clear ITEST_COMMAND and DTEST_COMMAND registers,
73 * Leaving these as non-zero can confuse the emulator
74 */
75 p0.L = LO(DTEST_COMMAND);
76 p0.H = HI(DTEST_COMMAND);
77 [p0] = R0;
78 [p0 + (ITEST_COMMAND - DTEST_COMMAND)] = R0;
79 CSYNC;
80
71 trace_buffer_init(p0,r0); 81 trace_buffer_init(p0,r0);
72 P0 = R1; 82 P0 = R1;
73 R0 = R1; 83 R0 = R1;
@@ -90,12 +100,46 @@ ENTRY(__start)
90 [p0] = R0; 100 [p0] = R0;
91 SSYNC; 101 SSYNC;
92 102
93 /* Save RETX, in case of doublefault */ 103 /* in case of double faults, save a few things */
94 p0.l = ___retx; 104 p0.l = _init_retx;
95 p0.h = ___retx; 105 p0.h = _init_retx;
96 R0 = RETX; 106 R0 = RETX;
97 [P0] = R0; 107 [P0] = R0;
98 108
109#ifdef CONFIG_DEBUG_DOUBLEFAULT
110 /* Only save these if we are storing them,
111 * This happens here, since L1 gets clobbered
112 * below
113 */
114 p0.l = _saved_retx;
115 p0.h = _saved_retx;
116 p1.l = _init_saved_retx;
117 p1.h = _init_saved_retx;
118 r0 = [p0];
119 [p1] = r0;
120
121 p0.l = _saved_dcplb_fault_addr;
122 p0.h = _saved_dcplb_fault_addr;
123 p1.l = _init_saved_dcplb_fault_addr;
124 p1.h = _init_saved_dcplb_fault_addr;
125 r0 = [p0];
126 [p1] = r0;
127
128 p0.l = _saved_icplb_fault_addr;
129 p0.h = _saved_icplb_fault_addr;
130 p1.l = _init_saved_icplb_fault_addr;
131 p1.h = _init_saved_icplb_fault_addr;
132 r0 = [p0];
133 [p1] = r0;
134
135 p0.l = _saved_seqstat;
136 p0.h = _saved_seqstat;
137 p1.l = _init_saved_seqstat;
138 p1.h = _init_saved_seqstat;
139 r0 = [p0];
140 [p1] = r0;
141#endif
142
99 /* Initialize stack pointer */ 143 /* Initialize stack pointer */
100 sp.l = lo(INITIAL_STACK); 144 sp.l = lo(INITIAL_STACK);
101 sp.h = hi(INITIAL_STACK); 145 sp.h = hi(INITIAL_STACK);
@@ -107,7 +151,7 @@ ENTRY(__start)
107#endif 151#endif
108 152
109 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */ 153 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
110 call _bf53x_relocate_l1_mem; 154 call _bfin_relocate_l1_mem;
111#ifdef CONFIG_BFIN_KERNEL_CLOCK 155#ifdef CONFIG_BFIN_KERNEL_CLOCK
112 call _start_dma_code; 156 call _start_dma_code;
113#endif 157#endif
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S
index b27e59d32401..4a2ec7a9675a 100644
--- a/arch/blackfin/mach-common/interrupt.S
+++ b/arch/blackfin/mach-common/interrupt.S
@@ -143,7 +143,7 @@ ENTRY(_evt_ivhw)
143 fp = 0; 143 fp = 0;
144#endif 144#endif
145 145
146#if ANOMALY_05000283 146#if ANOMALY_05000283 || ANOMALY_05000315
147 cc = r7 == r7; 147 cc = r7 == r7;
148 p5.h = HI(CHIPID); 148 p5.h = HI(CHIPID);
149 p5.l = LO(CHIPID); 149 p5.l = LO(CHIPID);
@@ -179,7 +179,16 @@ ENTRY(_evt_ivhw)
179 call _trap_c; 179 call _trap_c;
180 SP += 12; 180 SP += 12;
181 181
182#ifdef EBIU_ERRMST
183 /* make sure EBIU_ERRMST is clear */
184 p0.l = LO(EBIU_ERRMST);
185 p0.h = HI(EBIU_ERRMST);
186 r0.l = (CORE_ERROR | CORE_MERROR);
187 w[p0] = r0.l;
188#endif
189
182 call _ret_from_exception; 190 call _ret_from_exception;
191
183.Lcommon_restore_all_sys: 192.Lcommon_restore_all_sys:
184 RESTORE_ALL_SYS 193 RESTORE_ALL_SYS
185 rti; 194 rti;
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 5fa536727c61..34e8a726ffda 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -243,12 +243,14 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state)
243#endif 243#endif
244 244
245static struct irq_chip bfin_core_irqchip = { 245static struct irq_chip bfin_core_irqchip = {
246 .name = "CORE",
246 .ack = bfin_ack_noop, 247 .ack = bfin_ack_noop,
247 .mask = bfin_core_mask_irq, 248 .mask = bfin_core_mask_irq,
248 .unmask = bfin_core_unmask_irq, 249 .unmask = bfin_core_unmask_irq,
249}; 250};
250 251
251static struct irq_chip bfin_internal_irqchip = { 252static struct irq_chip bfin_internal_irqchip = {
253 .name = "INTN",
252 .ack = bfin_ack_noop, 254 .ack = bfin_ack_noop,
253 .mask = bfin_internal_mask_irq, 255 .mask = bfin_internal_mask_irq,
254 .unmask = bfin_internal_unmask_irq, 256 .unmask = bfin_internal_unmask_irq,
@@ -278,6 +280,7 @@ static void bfin_generic_error_unmask_irq(unsigned int irq)
278} 280}
279 281
280static struct irq_chip bfin_generic_error_irqchip = { 282static struct irq_chip bfin_generic_error_irqchip = {
283 .name = "ERROR",
281 .ack = bfin_ack_noop, 284 .ack = bfin_ack_noop,
282 .mask_ack = bfin_generic_error_mask_irq, 285 .mask_ack = bfin_generic_error_mask_irq,
283 .mask = bfin_generic_error_mask_irq, 286 .mask = bfin_generic_error_mask_irq,
@@ -361,6 +364,14 @@ static void bfin_demux_error_irq(unsigned int int_err_irq,
361} 364}
362#endif /* BF537_GENERIC_ERROR_INT_DEMUX */ 365#endif /* BF537_GENERIC_ERROR_INT_DEMUX */
363 366
367static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
368{
369 struct irq_desc *desc = irq_desc + irq;
370 /* May not call generic set_irq_handler() due to spinlock
371 recursion. */
372 desc->handle_irq = handle;
373}
374
364#if !defined(CONFIG_BF54x) 375#if !defined(CONFIG_BF54x)
365 376
366static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; 377static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
@@ -473,9 +484,9 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
473 SSYNC(); 484 SSYNC();
474 485
475 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) 486 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
476 set_irq_handler(irq, handle_edge_irq); 487 bfin_set_irq_handler(irq, handle_edge_irq);
477 else 488 else
478 set_irq_handler(irq, handle_level_irq); 489 bfin_set_irq_handler(irq, handle_level_irq);
479 490
480 return 0; 491 return 0;
481} 492}
@@ -495,6 +506,7 @@ int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
495#endif 506#endif
496 507
497static struct irq_chip bfin_gpio_irqchip = { 508static struct irq_chip bfin_gpio_irqchip = {
509 .name = "GPIO",
498 .ack = bfin_gpio_ack_irq, 510 .ack = bfin_gpio_ack_irq,
499 .mask = bfin_gpio_mask_irq, 511 .mask = bfin_gpio_mask_irq,
500 .mask_ack = bfin_gpio_mask_ack_irq, 512 .mask_ack = bfin_gpio_mask_ack_irq,
@@ -804,10 +816,10 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
804 816
805 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { 817 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
806 pint[bank]->edge_set = pintbit; 818 pint[bank]->edge_set = pintbit;
807 set_irq_handler(irq, handle_edge_irq); 819 bfin_set_irq_handler(irq, handle_edge_irq);
808 } else { 820 } else {
809 pint[bank]->edge_clear = pintbit; 821 pint[bank]->edge_clear = pintbit;
810 set_irq_handler(irq, handle_level_irq); 822 bfin_set_irq_handler(irq, handle_level_irq);
811 } 823 }
812 824
813 SSYNC(); 825 SSYNC();
@@ -884,6 +896,7 @@ void bfin_pm_restore(void)
884#endif 896#endif
885 897
886static struct irq_chip bfin_gpio_irqchip = { 898static struct irq_chip bfin_gpio_irqchip = {
899 .name = "GPIO",
887 .ack = bfin_gpio_ack_irq, 900 .ack = bfin_gpio_ack_irq,
888 .mask = bfin_gpio_mask_irq, 901 .mask = bfin_gpio_mask_irq,
889 .mask_ack = bfin_gpio_mask_ack_irq, 902 .mask_ack = bfin_gpio_mask_ack_irq,
@@ -1136,8 +1149,4 @@ void do_irq(int vec, struct pt_regs *fp)
1136 vec = ivg->irqno; 1149 vec = ivg->irqno;
1137 } 1150 }
1138 asm_do_IRQ(vec, fp); 1151 asm_do_IRQ(vec, fp);
1139
1140#ifdef CONFIG_KGDB
1141 kgdb_process_breakpoint();
1142#endif
1143} 1152}
diff --git a/arch/blackfin/mm/Makefile b/arch/blackfin/mm/Makefile
index 2a7202ce01fd..d489f894f4b1 100644
--- a/arch/blackfin/mm/Makefile
+++ b/arch/blackfin/mm/Makefile
@@ -2,4 +2,4 @@
2# arch/blackfin/mm/Makefile 2# arch/blackfin/mm/Makefile
3# 3#
4 4
5obj-y := blackfin_sram.o init.o 5obj-y := sram-alloc.o isram-driver.o init.o
diff --git a/arch/blackfin/mm/isram-driver.c b/arch/blackfin/mm/isram-driver.c
new file mode 100644
index 000000000000..22913e7a1818
--- /dev/null
+++ b/arch/blackfin/mm/isram-driver.c
@@ -0,0 +1,201 @@
1/*
2 * Description: Instruction SRAM accessor functions for the Blackfin
3 *
4 * Copyright 2008 Analog Devices Inc.
5 *
6 * Bugs: Enter bugs at http://blackfin.uclinux.org/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, see the file COPYING, or write
15 * to the Free Software Foundation, Inc.,
16 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/types.h>
22#include <linux/spinlock.h>
23#include <linux/sched.h>
24
25#include <asm/blackfin.h>
26
27/*
28 * IMPORTANT WARNING ABOUT THESE FUNCTIONS
29 *
30 * The emulator will not function correctly if a write command is left in
31 * ITEST_COMMAND or DTEST_COMMAND AND access to cache memory is needed by
32 * the emulator. To avoid such problems, ensure that both ITEST_COMMAND
33 * and DTEST_COMMAND are zero when exiting these functions.
34 */
35
36
37/*
38 * On the Blackfin, L1 instruction sram (which operates at core speeds) can not
39 * be accessed by a normal core load, so we need to go through a few hoops to
40 * read/write it.
41 * To try to make it easier - we export a memcpy interface, where either src or
42 * dest can be in this special L1 memory area.
43 * The low level read/write functions should not be exposed to the rest of the
44 * kernel, since they operate on 64-bit data, and need specific address alignment
45 */
46
47static DEFINE_SPINLOCK(dtest_lock);
48
49/* Takes a void pointer */
50#define IADDR2DTEST(x) \
51 ({ unsigned long __addr = (unsigned long)(x); \
52 (__addr & 0x47F8) | /* address bits 14 & 10:3 */ \
53 (__addr & 0x0800) << 15 | /* address bit 11 */ \
54 (__addr & 0x3000) << 4 | /* address bits 13:12 */ \
55 (__addr & 0x8000) << 8 | /* address bit 15 */ \
56 (0x1000004); /* isram access */ \
57 })
58
59/* Takes a pointer, and returns the offset (in bits) which things should be shifted */
60#define ADDR2OFFSET(x) ((((unsigned long)(x)) & 0x7) * 8)
61
62/* Takes a pointer, determines if it is the last byte in the isram 64-bit data type */
63#define ADDR2LAST(x) ((((unsigned long)x) & 0x7) == 0x7)
64
65static void isram_write(const void *addr, uint64_t data)
66{
67 uint32_t cmd;
68 unsigned long flags;
69
70 if (addr >= (void *)(L1_CODE_START + L1_CODE_LENGTH))
71 return;
72
73 cmd = IADDR2DTEST(addr) | 1; /* write */
74
75 /*
76 * Writes to DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
77 * While in exception context - atomicity is guaranteed or double fault
78 */
79 spin_lock_irqsave(&dtest_lock, flags);
80
81 bfin_write_DTEST_DATA0(data & 0xFFFFFFFF);
82 bfin_write_DTEST_DATA1(data >> 32);
83
84 /* use the builtin, since interrupts are already turned off */
85 __builtin_bfin_csync();
86 bfin_write_DTEST_COMMAND(cmd);
87 __builtin_bfin_csync();
88
89 bfin_write_DTEST_COMMAND(0);
90 __builtin_bfin_csync();
91
92 spin_unlock_irqrestore(&dtest_lock, flags);
93}
94
95static uint64_t isram_read(const void *addr)
96{
97 uint32_t cmd;
98 unsigned long flags;
99 uint64_t ret;
100
101 if (addr > (void *)(L1_CODE_START + L1_CODE_LENGTH))
102 return 0;
103
104 cmd = IADDR2DTEST(addr) | 0; /* read */
105
106 /*
107 * Reads of DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
108 * While in exception context - atomicity is guaranteed or double fault
109 */
110 spin_lock_irqsave(&dtest_lock, flags);
111 /* use the builtin, since interrupts are already turned off */
112 __builtin_bfin_csync();
113 bfin_write_DTEST_COMMAND(cmd);
114 __builtin_bfin_csync();
115 ret = bfin_read_DTEST_DATA0() | ((uint64_t)bfin_read_DTEST_DATA1() << 32);
116
117 bfin_write_DTEST_COMMAND(0);
118 __builtin_bfin_csync();
119 spin_unlock_irqrestore(&dtest_lock, flags);
120
121 return ret;
122}
123
124static bool isram_check_addr(const void *addr, size_t n)
125{
126 if ((addr >= (void *)L1_CODE_START) &&
127 (addr < (void *)(L1_CODE_START + L1_CODE_LENGTH))) {
128 if ((addr + n) >= (void *)(L1_CODE_START + L1_CODE_LENGTH)) {
129 show_stack(NULL, NULL);
130 printk(KERN_ERR "isram_memcpy: copy involving %p length "
131 "(%zu) too long\n", addr, n);
132 }
133 return true;
134 }
135 return false;
136}
137
138/*
139 * The isram_memcpy() function copies n bytes from memory area src to memory area dest.
140 * The isram_memcpy() function returns a pointer to dest.
141 * Either dest or src can be in L1 instruction sram.
142 */
143void *isram_memcpy(void *dest, const void *src, size_t n)
144{
145 uint64_t data_in = 0, data_out = 0;
146 size_t count;
147 bool dest_in_l1, src_in_l1, need_data, put_data;
148 unsigned char byte, *src_byte, *dest_byte;
149
150 src_byte = (unsigned char *)src;
151 dest_byte = (unsigned char *)dest;
152
153 dest_in_l1 = isram_check_addr(dest, n);
154 src_in_l1 = isram_check_addr(src, n);
155
156 need_data = true;
157 put_data = true;
158 for (count = 0; count < n; count++) {
159 if (src_in_l1) {
160 if (need_data) {
161 data_in = isram_read(src + count);
162 need_data = false;
163 }
164
165 if (ADDR2LAST(src + count))
166 need_data = true;
167
168 byte = (unsigned char)((data_in >> ADDR2OFFSET(src + count)) & 0xff);
169
170 } else {
171 /* src is in L2 or L3 - so just dereference*/
172 byte = src_byte[count];
173 }
174
175 if (dest_in_l1) {
176 if (put_data) {
177 data_out = isram_read(dest + count);
178 put_data = false;
179 }
180
181 data_out &= ~((uint64_t)0xff << ADDR2OFFSET(dest + count));
182 data_out |= ((uint64_t)byte << ADDR2OFFSET(dest + count));
183
184 if (ADDR2LAST(dest + count)) {
185 put_data = true;
186 isram_write(dest + count, data_out);
187 }
188 } else {
189 /* dest in L2 or L3 - so just dereference */
190 dest_byte[count] = byte;
191 }
192 }
193
194 /* make sure we dump the last byte if necessary */
195 if (dest_in_l1 && !put_data)
196 isram_write(dest + count, data_out);
197
198 return dest;
199}
200EXPORT_SYMBOL(isram_memcpy);
201
diff --git a/arch/blackfin/mm/blackfin_sram.c b/arch/blackfin/mm/sram-alloc.c
index 4f5e887a0d96..0f1ca6930c16 100644
--- a/arch/blackfin/mm/blackfin_sram.c
+++ b/arch/blackfin/mm/sram-alloc.c
@@ -1,13 +1,13 @@
1/* 1/*
2 * File: arch/blackfin/mm/blackfin_sram.c 2 * File: arch/blackfin/mm/sram-alloc.c
3 * Based on: 3 * Based on:
4 * Author: 4 * Author:
5 * 5 *
6 * Created: 6 * Created:
7 * Description: SRAM driver for Blackfin ADSP-BF5xx 7 * Description: SRAM allocator for Blackfin L1 and L2 memory
8 * 8 *
9 * Modified: 9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc. 10 * Copyright 2004-2008 Analog Devices Inc.
11 * 11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 * 13 *
@@ -78,7 +78,7 @@ static void __init l1sram_init(void)
78 free_l1_ssram_head.next = 78 free_l1_ssram_head.next =
79 kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); 79 kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
80 if (!free_l1_ssram_head.next) { 80 if (!free_l1_ssram_head.next) {
81 printk(KERN_INFO"Fail to initialize Scratchpad data SRAM.\n"); 81 printk(KERN_INFO "Failed to initialize Scratchpad data SRAM\n");
82 return; 82 return;
83 } 83 }
84 84
@@ -102,7 +102,7 @@ static void __init l1_data_sram_init(void)
102 free_l1_data_A_sram_head.next = 102 free_l1_data_A_sram_head.next =
103 kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); 103 kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
104 if (!free_l1_data_A_sram_head.next) { 104 if (!free_l1_data_A_sram_head.next) {
105 printk(KERN_INFO"Fail to initialize L1 Data A SRAM.\n"); 105 printk(KERN_INFO "Failed to initialize L1 Data A SRAM\n");
106 return; 106 return;
107 } 107 }
108 108
@@ -123,7 +123,7 @@ static void __init l1_data_sram_init(void)
123 free_l1_data_B_sram_head.next = 123 free_l1_data_B_sram_head.next =
124 kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); 124 kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
125 if (!free_l1_data_B_sram_head.next) { 125 if (!free_l1_data_B_sram_head.next) {
126 printk(KERN_INFO"Fail to initialize L1 Data B SRAM.\n"); 126 printk(KERN_INFO "Failed to initialize L1 Data B SRAM\n");
127 return; 127 return;
128 } 128 }
129 129
@@ -151,7 +151,7 @@ static void __init l1_inst_sram_init(void)
151 free_l1_inst_sram_head.next = 151 free_l1_inst_sram_head.next =
152 kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); 152 kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
153 if (!free_l1_inst_sram_head.next) { 153 if (!free_l1_inst_sram_head.next) {
154 printk(KERN_INFO"Fail to initialize L1 Instruction SRAM.\n"); 154 printk(KERN_INFO "Failed to initialize L1 Instruction SRAM\n");
155 return; 155 return;
156 } 156 }
157 157
@@ -179,7 +179,7 @@ static void __init l2_sram_init(void)
179 free_l2_sram_head.next = 179 free_l2_sram_head.next =
180 kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); 180 kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
181 if (!free_l2_sram_head.next) { 181 if (!free_l2_sram_head.next) {
182 printk(KERN_INFO"Fail to initialize L2 SRAM.\n"); 182 printk(KERN_INFO "Failed to initialize L2 SRAM\n");
183 return; 183 return;
184 } 184 }
185 185
@@ -351,28 +351,31 @@ static int _sram_free(const void *addr,
351 351
352int sram_free(const void *addr) 352int sram_free(const void *addr)
353{ 353{
354 if (0) {} 354
355#if L1_CODE_LENGTH != 0 355#if L1_CODE_LENGTH != 0
356 else if (addr >= (void *)L1_CODE_START 356 if (addr >= (void *)L1_CODE_START
357 && addr < (void *)(L1_CODE_START + L1_CODE_LENGTH)) 357 && addr < (void *)(L1_CODE_START + L1_CODE_LENGTH))
358 return l1_inst_sram_free(addr); 358 return l1_inst_sram_free(addr);
359 else
359#endif 360#endif
360#if L1_DATA_A_LENGTH != 0 361#if L1_DATA_A_LENGTH != 0
361 else if (addr >= (void *)L1_DATA_A_START 362 if (addr >= (void *)L1_DATA_A_START
362 && addr < (void *)(L1_DATA_A_START + L1_DATA_A_LENGTH)) 363 && addr < (void *)(L1_DATA_A_START + L1_DATA_A_LENGTH))
363 return l1_data_A_sram_free(addr); 364 return l1_data_A_sram_free(addr);
365 else
364#endif 366#endif
365#if L1_DATA_B_LENGTH != 0 367#if L1_DATA_B_LENGTH != 0
366 else if (addr >= (void *)L1_DATA_B_START 368 if (addr >= (void *)L1_DATA_B_START
367 && addr < (void *)(L1_DATA_B_START + L1_DATA_B_LENGTH)) 369 && addr < (void *)(L1_DATA_B_START + L1_DATA_B_LENGTH))
368 return l1_data_B_sram_free(addr); 370 return l1_data_B_sram_free(addr);
371 else
369#endif 372#endif
370#if L2_LENGTH != 0 373#if L2_LENGTH != 0
371 else if (addr >= (void *)L2_START 374 if (addr >= (void *)L2_START
372 && addr < (void *)(L2_START + L2_LENGTH)) 375 && addr < (void *)(L2_START + L2_LENGTH))
373 return l2_sram_free(addr); 376 return l2_sram_free(addr);
374#endif
375 else 377 else
378#endif
376 return -1; 379 return -1;
377} 380}
378EXPORT_SYMBOL(sram_free); 381EXPORT_SYMBOL(sram_free);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 09:41:34 -0500