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-rw-r--r--arch/arm/kernel/entry-armv.S12
-rw-r--r--arch/arm/kernel/time.c13
-rw-r--r--arch/arm/kernel/traps.c1
-rw-r--r--arch/arm/mm/flush.c39
4 files changed, 61 insertions, 4 deletions
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 2db42b18f53f..8517c3c3eb33 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -436,7 +436,7 @@ __und_usr:
436 usr_entry 436 usr_entry
437 437
438 tst r3, #PSR_T_BIT @ Thumb mode? 438 tst r3, #PSR_T_BIT @ Thumb mode?
439 bne fpundefinstr @ ignore FP 439 bne __und_usr_unknown @ ignore FP
440 sub r4, r2, #4 440 sub r4, r2, #4
441 441
442 @ 442 @
@@ -448,7 +448,7 @@ __und_usr:
448 @ 448 @
4491: ldrt r0, [r4] 4491: ldrt r0, [r4]
450 adr r9, ret_from_exception 450 adr r9, ret_from_exception
451 adr lr, fpundefinstr 451 adr lr, __und_usr_unknown
452 @ 452 @
453 @ fallthrough to call_fpe 453 @ fallthrough to call_fpe
454 @ 454 @
@@ -476,7 +476,9 @@ __und_usr:
476 * Emulators may wish to make use of the following registers: 476 * Emulators may wish to make use of the following registers:
477 * r0 = instruction opcode. 477 * r0 = instruction opcode.
478 * r2 = PC+4 478 * r2 = PC+4
479 * r9 = normal "successful" return address
479 * r10 = this threads thread_info structure. 480 * r10 = this threads thread_info structure.
481 * lr = unrecognised instruction return address
480 */ 482 */
481call_fpe: 483call_fpe:
482 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 484 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
@@ -545,10 +547,12 @@ do_fpe:
545 547
546 .data 548 .data
547ENTRY(fp_enter) 549ENTRY(fp_enter)
548 .word fpundefinstr 550 .word no_fp
549 .text 551 .text
550 552
551fpundefinstr: 553no_fp: mov pc, lr
554
555__und_usr_unknown:
552 mov r0, sp 556 mov r0, sp
553 adr lr, ret_from_exception 557 adr lr, ret_from_exception
554 b do_undefinstr 558 b do_undefinstr
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index 6ff5e3ff6cb5..3c8cdcfe8d4a 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -29,6 +29,8 @@
29#include <linux/timer.h> 29#include <linux/timer.h>
30#include <linux/irq.h> 30#include <linux/irq.h>
31 31
32#include <linux/mc146818rtc.h>
33
32#include <asm/leds.h> 34#include <asm/leds.h>
33#include <asm/thread_info.h> 35#include <asm/thread_info.h>
34#include <asm/mach/time.h> 36#include <asm/mach/time.h>
@@ -85,6 +87,17 @@ unsigned long long __attribute__((weak)) sched_clock(void)
85 return (unsigned long long)jiffies * (1000000000 / HZ); 87 return (unsigned long long)jiffies * (1000000000 / HZ);
86} 88}
87 89
90/*
91 * An implementation of printk_clock() independent from
92 * sched_clock(). This avoids non-bootable kernels when
93 * printk_clock is enabled.
94 */
95unsigned long long printk_clock(void)
96{
97 return (unsigned long long)(jiffies - INITIAL_JIFFIES) *
98 (1000000000 / HZ);
99}
100
88static unsigned long next_rtc_update; 101static unsigned long next_rtc_update;
89 102
90/* 103/*
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 042a12982e98..908915675edc 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -27,6 +27,7 @@
27#include <asm/uaccess.h> 27#include <asm/uaccess.h>
28#include <asm/unistd.h> 28#include <asm/unistd.h>
29#include <asm/traps.h> 29#include <asm/traps.h>
30#include <asm/io.h>
30 31
31#include "ptrace.h" 32#include "ptrace.h"
32#include "signal.h" 33#include "signal.h"
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 628348c9f6c5..9df507d36e0b 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -202,3 +202,42 @@ void flush_dcache_page(struct page *page)
202 } 202 }
203} 203}
204EXPORT_SYMBOL(flush_dcache_page); 204EXPORT_SYMBOL(flush_dcache_page);
205
206/*
207 * Flush an anonymous page so that users of get_user_pages()
208 * can safely access the data. The expected sequence is:
209 *
210 * get_user_pages()
211 * -> flush_anon_page
212 * memcpy() to/from page
213 * if written to page, flush_dcache_page()
214 */
215void __flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr)
216{
217 unsigned long pfn;
218
219 /* VIPT non-aliasing caches need do nothing */
220 if (cache_is_vipt_nonaliasing())
221 return;
222
223 /*
224 * Write back and invalidate userspace mapping.
225 */
226 pfn = page_to_pfn(page);
227 if (cache_is_vivt()) {
228 flush_cache_page(vma, vmaddr, pfn);
229 } else {
230 /*
231 * For aliasing VIPT, we can flush an alias of the
232 * userspace address only.
233 */
234 flush_pfn_alias(pfn, vmaddr);
235 }
236
237 /*
238 * Invalidate kernel mapping. No data should be contained
239 * in this mapping of the page. FIXME: this is overkill
240 * since we actually ask for a write-back and invalidate.
241 */
242 __cpuc_flush_dcache_page(page_address(page));
243}