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-rw-r--r--arch/arm/configs/ams_delta_defconfig1
-rw-r--r--arch/arm/configs/omap3_defconfig34
-rw-r--r--arch/arm/mach-omap1/Kconfig10
-rw-r--r--arch/arm/mach-omap1/Makefile1
-rw-r--r--arch/arm/mach-omap1/ams-delta-fiq-handler.S278
-rw-r--r--arch/arm/mach-omap1/ams-delta-fiq.c155
-rw-r--r--arch/arm/mach-omap1/board-ams-delta.c18
-rw-r--r--arch/arm/mach-omap1/include/mach/ams-delta-fiq.h79
-rw-r--r--arch/arm/mach-omap1/include/mach/debug-macro.S21
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c1
-rw-r--r--arch/arm/mach-omap2/board-zoom-debugboard.c2
-rw-r--r--arch/arm/mach-omap2/board-zoom2.c4
-rw-r--r--arch/arm/mach-omap2/board-zoom3.c4
-rw-r--r--arch/arm/mach-omap2/include/mach/debug-macro.S15
-rw-r--r--arch/arm/mach-omap2/io.c9
-rw-r--r--arch/arm/mach-omap2/mux34xx.c86
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h4
-rw-r--r--arch/arm/plat-omap/include/plat/multi.h16
-rw-r--r--arch/arm/plat-omap/include/plat/serial.h16
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h44
-rw-r--r--arch/arm/plat-omap/sram.c16
21 files changed, 647 insertions, 167 deletions
diff --git a/arch/arm/configs/ams_delta_defconfig b/arch/arm/configs/ams_delta_defconfig
index 1d0e8926a2f0..6d8a0c891f80 100644
--- a/arch/arm/configs/ams_delta_defconfig
+++ b/arch/arm/configs/ams_delta_defconfig
@@ -699,6 +699,7 @@ CONFIG_SERIO=y
699CONFIG_SERIO_SERPORT=y 699CONFIG_SERIO_SERPORT=y
700CONFIG_SERIO_LIBPS2=y 700CONFIG_SERIO_LIBPS2=y
701# CONFIG_SERIO_RAW is not set 701# CONFIG_SERIO_RAW is not set
702CONFIG_SERIO_AMS_DELTA=y
702# CONFIG_GAMEPORT is not set 703# CONFIG_GAMEPORT is not set
703 704
704# 705#
diff --git a/arch/arm/configs/omap3_defconfig b/arch/arm/configs/omap3_defconfig
index d6ad92177324..1efb833147c2 100644
--- a/arch/arm/configs/omap3_defconfig
+++ b/arch/arm/configs/omap3_defconfig
@@ -264,7 +264,7 @@ CONFIG_MACH_OMAP_GENERIC=y
264# OMAP Core Type 264# OMAP Core Type
265# 265#
266CONFIG_ARCH_OMAP2420=y 266CONFIG_ARCH_OMAP2420=y
267# CONFIG_ARCH_OMAP2430 is not set 267CONFIG_ARCH_OMAP2430=y
268CONFIG_ARCH_OMAP3430=y 268CONFIG_ARCH_OMAP3430=y
269CONFIG_OMAP_PACKAGE_CBB=y 269CONFIG_OMAP_PACKAGE_CBB=y
270CONFIG_OMAP_PACKAGE_CUS=y 270CONFIG_OMAP_PACKAGE_CUS=y
@@ -276,8 +276,9 @@ CONFIG_OMAP_PACKAGE_CBP=y
276CONFIG_MACH_OMAP2_TUSB6010=y 276CONFIG_MACH_OMAP2_TUSB6010=y
277CONFIG_MACH_OMAP_H4=y 277CONFIG_MACH_OMAP_H4=y
278CONFIG_MACH_OMAP_APOLLON=y 278CONFIG_MACH_OMAP_APOLLON=y
279# CONFIG_MACH_OMAP_2430SDP is not set 279CONFIG_MACH_OMAP_2430SDP=y
280CONFIG_MACH_OMAP3_BEAGLE=y 280CONFIG_MACH_OMAP3_BEAGLE=y
281CONFIG_MACH_DEVKIT8000=y
281CONFIG_MACH_OMAP_LDP=y 282CONFIG_MACH_OMAP_LDP=y
282CONFIG_MACH_OVERO=y 283CONFIG_MACH_OVERO=y
283CONFIG_MACH_OMAP3EVM=y 284CONFIG_MACH_OMAP3EVM=y
@@ -390,7 +391,7 @@ CONFIG_ALIGNMENT_TRAP=y
390# 391#
391CONFIG_ZBOOT_ROM_TEXT=0x0 392CONFIG_ZBOOT_ROM_TEXT=0x0
392CONFIG_ZBOOT_ROM_BSS=0x0 393CONFIG_ZBOOT_ROM_BSS=0x0
393CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" 394CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyS2,115200"
394# CONFIG_XIP_KERNEL is not set 395# CONFIG_XIP_KERNEL is not set
395CONFIG_KEXEC=y 396CONFIG_KEXEC=y
396CONFIG_ATAGS_PROC=y 397CONFIG_ATAGS_PROC=y
@@ -443,7 +444,7 @@ CONFIG_BINFMT_MISC=y
443# 444#
444CONFIG_PM=y 445CONFIG_PM=y
445CONFIG_PM_DEBUG=y 446CONFIG_PM_DEBUG=y
446CONFIG_PM_VERBOSE=y 447# CONFIG_PM_VERBOSE is not set
447CONFIG_CAN_PM_TRACE=y 448CONFIG_CAN_PM_TRACE=y
448CONFIG_PM_SLEEP=y 449CONFIG_PM_SLEEP=y
449CONFIG_SUSPEND=y 450CONFIG_SUSPEND=y
@@ -1262,7 +1263,7 @@ CONFIG_HWMON=y
1262# CONFIG_SENSORS_LIS3_I2C is not set 1263# CONFIG_SENSORS_LIS3_I2C is not set
1263# CONFIG_THERMAL is not set 1264# CONFIG_THERMAL is not set
1264CONFIG_WATCHDOG=y 1265CONFIG_WATCHDOG=y
1265CONFIG_WATCHDOG_NOWAYOUT=y 1266# CONFIG_WATCHDOG_NOWAYOUT is not set
1266 1267
1267# 1268#
1268# Watchdog Device Drivers 1269# Watchdog Device Drivers
@@ -1291,9 +1292,9 @@ CONFIG_MFD_CORE=y
1291# CONFIG_HTC_EGPIO is not set 1292# CONFIG_HTC_EGPIO is not set
1292# CONFIG_HTC_PASIC3 is not set 1293# CONFIG_HTC_PASIC3 is not set
1293# CONFIG_TPS65010 is not set 1294# CONFIG_TPS65010 is not set
1294# CONFIG_MENELAUS is not set 1295CONFIG_MENELAUS=y
1295CONFIG_TWL4030_CORE=y 1296CONFIG_TWL4030_CORE=y
1296# CONFIG_TWL4030_POWER is not set 1297CONFIG_TWL4030_POWER=y
1297CONFIG_TWL4030_CODEC=y 1298CONFIG_TWL4030_CODEC=y
1298# CONFIG_MFD_TMIO is not set 1299# CONFIG_MFD_TMIO is not set
1299# CONFIG_MFD_T7L66XB is not set 1300# CONFIG_MFD_T7L66XB is not set
@@ -1312,7 +1313,7 @@ CONFIG_TWL4030_CODEC=y
1312# CONFIG_AB4500_CORE is not set 1313# CONFIG_AB4500_CORE is not set
1313CONFIG_REGULATOR=y 1314CONFIG_REGULATOR=y
1314# CONFIG_REGULATOR_DEBUG is not set 1315# CONFIG_REGULATOR_DEBUG is not set
1315CONFIG_REGULATOR_FIXED_VOLTAGE=y 1316# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
1316# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set 1317# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
1317# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set 1318# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
1318# CONFIG_REGULATOR_BQ24022 is not set 1319# CONFIG_REGULATOR_BQ24022 is not set
@@ -1320,8 +1321,8 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
1320# CONFIG_REGULATOR_MAX8660 is not set 1321# CONFIG_REGULATOR_MAX8660 is not set
1321CONFIG_REGULATOR_TWL4030=y 1322CONFIG_REGULATOR_TWL4030=y
1322# CONFIG_REGULATOR_LP3971 is not set 1323# CONFIG_REGULATOR_LP3971 is not set
1323# CONFIG_REGULATOR_TPS65023 is not set 1324CONFIG_REGULATOR_TPS65023=y
1324# CONFIG_REGULATOR_TPS6507X is not set 1325CONFIG_REGULATOR_TPS6507X=y
1325# CONFIG_MEDIA_SUPPORT is not set 1326# CONFIG_MEDIA_SUPPORT is not set
1326 1327
1327# 1328#
@@ -1358,16 +1359,8 @@ CONFIG_FB_TILEBLITTING=y
1358# CONFIG_FB_METRONOME is not set 1359# CONFIG_FB_METRONOME is not set
1359# CONFIG_FB_MB862XX is not set 1360# CONFIG_FB_MB862XX is not set
1360# CONFIG_FB_BROADSHEET is not set 1361# CONFIG_FB_BROADSHEET is not set
1361CONFIG_FB_OMAP=y 1362# CONFIG_FB_OMAP is not set
1362CONFIG_FB_OMAP_LCD_VGA=y 1363CONFIG_FB_OMAP_LCD_VGA=y
1363# CONFIG_FB_OMAP_031M3R is not set
1364# CONFIG_FB_OMAP_048M3R is not set
1365CONFIG_FB_OMAP_079M3R=y
1366# CONFIG_FB_OMAP_092M9R is not set
1367# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
1368# CONFIG_FB_OMAP_LCD_MIPID is not set
1369# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
1370CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
1371# CONFIG_OMAP2_DSS is not set 1364# CONFIG_OMAP2_DSS is not set
1372CONFIG_BACKLIGHT_LCD_SUPPORT=y 1365CONFIG_BACKLIGHT_LCD_SUPPORT=y
1373CONFIG_LCD_CLASS_DEVICE=y 1366CONFIG_LCD_CLASS_DEVICE=y
@@ -1686,7 +1679,7 @@ CONFIG_SDIO_UART=y
1686# MMC/SD/SDIO Host Controller Drivers 1679# MMC/SD/SDIO Host Controller Drivers
1687# 1680#
1688# CONFIG_MMC_SDHCI is not set 1681# CONFIG_MMC_SDHCI is not set
1689# CONFIG_MMC_OMAP is not set 1682CONFIG_MMC_OMAP=y
1690CONFIG_MMC_OMAP_HS=y 1683CONFIG_MMC_OMAP_HS=y
1691# CONFIG_MMC_AT91 is not set 1684# CONFIG_MMC_AT91 is not set
1692# CONFIG_MMC_ATMELMCI is not set 1685# CONFIG_MMC_ATMELMCI is not set
@@ -1751,6 +1744,7 @@ CONFIG_RTC_INTF_DEV=y
1751# CONFIG_RTC_DRV_PCF8583 is not set 1744# CONFIG_RTC_DRV_PCF8583 is not set
1752# CONFIG_RTC_DRV_M41T80 is not set 1745# CONFIG_RTC_DRV_M41T80 is not set
1753# CONFIG_RTC_DRV_BQ32K is not set 1746# CONFIG_RTC_DRV_BQ32K is not set
1747CONFIG_RTC_DRV_TWL92330=y
1754CONFIG_RTC_DRV_TWL4030=y 1748CONFIG_RTC_DRV_TWL4030=y
1755# CONFIG_RTC_DRV_S35390A is not set 1749# CONFIG_RTC_DRV_S35390A is not set
1756# CONFIG_RTC_DRV_FM3130 is not set 1750# CONFIG_RTC_DRV_FM3130 is not set
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 27f489747bbd..b18d7c28ab7a 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -152,6 +152,16 @@ config MACH_AMS_DELTA
152 Support for the Amstrad E3 (codename Delta) videophone. Say Y here 152 Support for the Amstrad E3 (codename Delta) videophone. Say Y here
153 if you have such a device. 153 if you have such a device.
154 154
155config AMS_DELTA_FIQ
156 bool "Fast Interrupt Request (FIQ) support for the E3"
157 depends on MACH_AMS_DELTA
158 select FIQ
159 help
160 Provide a FIQ handler for the E3.
161 This allows for fast handling of interrupts generated
162 by the clock line of the E3 mailboard (or a PS/2 keyboard)
163 connected to the GPIO based external keyboard port.
164
155config MACH_OMAP_GENERIC 165config MACH_OMAP_GENERIC
156 bool "Generic OMAP board" 166 bool "Generic OMAP board"
157 depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX) 167 depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX)
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index b6a537c875b8..ea231c7a550a 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o
37obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o 37obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o
38obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o 38obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o
39obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o 39obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o
40obj-$(CONFIG_AMS_DELTA_FIQ) += ams-delta-fiq.o ams-delta-fiq-handler.o
40obj-$(CONFIG_MACH_SX1) += board-sx1.o board-sx1-mmc.o 41obj-$(CONFIG_MACH_SX1) += board-sx1.o board-sx1-mmc.o
41obj-$(CONFIG_MACH_HERALD) += board-htcherald.o 42obj-$(CONFIG_MACH_HERALD) += board-htcherald.o
42 43
diff --git a/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
new file mode 100644
index 000000000000..927d5a181760
--- /dev/null
+++ b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
@@ -0,0 +1,278 @@
1/*
2 * linux/arch/arm/mach-omap1/ams-delta-fiq-handler.S
3 *
4 * Based on linux/arch/arm/lib/floppydma.S
5 * Renamed and modified to work with 2.6 kernel by Matt Callow
6 * Copyright (C) 1995, 1996 Russell King
7 * Copyright (C) 2004 Pete Trapps
8 * Copyright (C) 2006 Matt Callow
9 * Copyright (C) 2010 Janusz Krzysztofik
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2
13 * as published by the Free Software Foundation.
14 */
15
16#include <linux/linkage.h>
17
18#include <plat/io.h>
19#include <plat/board-ams-delta.h>
20
21#include <mach/ams-delta-fiq.h>
22
23/*
24 * GPIO related definitions, copied from arch/arm/plat-omap/gpio.c.
25 * Unfortunately, those were not placed in a separate header file.
26 */
27#define OMAP1510_GPIO_BASE 0xFFFCE000
28#define OMAP1510_GPIO_DATA_INPUT 0x00
29#define OMAP1510_GPIO_DATA_OUTPUT 0x04
30#define OMAP1510_GPIO_DIR_CONTROL 0x08
31#define OMAP1510_GPIO_INT_CONTROL 0x0c
32#define OMAP1510_GPIO_INT_MASK 0x10
33#define OMAP1510_GPIO_INT_STATUS 0x14
34#define OMAP1510_GPIO_PIN_CONTROL 0x18
35
36/* GPIO register bitmasks */
37#define KEYBRD_DATA_MASK (0x1 << AMS_DELTA_GPIO_PIN_KEYBRD_DATA)
38#define KEYBRD_CLK_MASK (0x1 << AMS_DELTA_GPIO_PIN_KEYBRD_CLK)
39#define MODEM_IRQ_MASK (0x1 << AMS_DELTA_GPIO_PIN_MODEM_IRQ)
40#define HOOK_SWITCH_MASK (0x1 << AMS_DELTA_GPIO_PIN_HOOK_SWITCH)
41#define OTHERS_MASK (MODEM_IRQ_MASK | HOOK_SWITCH_MASK)
42
43/* IRQ handler register bitmasks */
44#define DEFERRED_FIQ_MASK (0x1 << (INT_DEFERRED_FIQ % IH2_BASE))
45#define GPIO_BANK1_MASK (0x1 << INT_GPIO_BANK1)
46
47/* Driver buffer byte offsets */
48#define BUF_MASK (FIQ_MASK * 4)
49#define BUF_STATE (FIQ_STATE * 4)
50#define BUF_KEYS_CNT (FIQ_KEYS_CNT * 4)
51#define BUF_TAIL_OFFSET (FIQ_TAIL_OFFSET * 4)
52#define BUF_HEAD_OFFSET (FIQ_HEAD_OFFSET * 4)
53#define BUF_BUF_LEN (FIQ_BUF_LEN * 4)
54#define BUF_KEY (FIQ_KEY * 4)
55#define BUF_MISSED_KEYS (FIQ_MISSED_KEYS * 4)
56#define BUF_BUFFER_START (FIQ_BUFFER_START * 4)
57#define BUF_GPIO_INT_MASK (FIQ_GPIO_INT_MASK * 4)
58#define BUF_KEYS_HICNT (FIQ_KEYS_HICNT * 4)
59#define BUF_IRQ_PEND (FIQ_IRQ_PEND * 4)
60#define BUF_SIR_CODE_L1 (FIQ_SIR_CODE_L1 * 4)
61#define BUF_SIR_CODE_L2 (IRQ_SIR_CODE_L2 * 4)
62#define BUF_CNT_INT_00 (FIQ_CNT_INT_00 * 4)
63#define BUF_CNT_INT_KEY (FIQ_CNT_INT_KEY * 4)
64#define BUF_CNT_INT_MDM (FIQ_CNT_INT_MDM * 4)
65#define BUF_CNT_INT_03 (FIQ_CNT_INT_03 * 4)
66#define BUF_CNT_INT_HSW (FIQ_CNT_INT_HSW * 4)
67#define BUF_CNT_INT_05 (FIQ_CNT_INT_05 * 4)
68#define BUF_CNT_INT_06 (FIQ_CNT_INT_06 * 4)
69#define BUF_CNT_INT_07 (FIQ_CNT_INT_07 * 4)
70#define BUF_CNT_INT_08 (FIQ_CNT_INT_08 * 4)
71#define BUF_CNT_INT_09 (FIQ_CNT_INT_09 * 4)
72#define BUF_CNT_INT_10 (FIQ_CNT_INT_10 * 4)
73#define BUF_CNT_INT_11 (FIQ_CNT_INT_11 * 4)
74#define BUF_CNT_INT_12 (FIQ_CNT_INT_12 * 4)
75#define BUF_CNT_INT_13 (FIQ_CNT_INT_13 * 4)
76#define BUF_CNT_INT_14 (FIQ_CNT_INT_14 * 4)
77#define BUF_CNT_INT_15 (FIQ_CNT_INT_15 * 4)
78#define BUF_CIRC_BUFF (FIQ_CIRC_BUFF * 4)
79
80
81/*
82 * Register useage
83 * r8 - temporary
84 * r9 - the driver buffer
85 * r10 - temporary
86 * r11 - interrupts mask
87 * r12 - base pointers
88 * r13 - interrupts status
89 */
90
91 .text
92
93 .global qwerty_fiqin_end
94
95ENTRY(qwerty_fiqin_start)
96 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
97 @ FIQ intrrupt handler
98 ldr r12, omap_ih1_base @ set pointer to level1 handler
99
100 ldr r11, [r12, #IRQ_MIR_REG_OFFSET] @ fetch interrupts mask
101
102 ldr r13, [r12, #IRQ_ITR_REG_OFFSET] @ fetch interrupts status
103 bics r13, r13, r11 @ clear masked - any left?
104 beq exit @ none - spurious FIQ? exit
105
106 ldr r10, [r12, #IRQ_SIR_FIQ_REG_OFFSET] @ get requested interrupt number
107
108 mov r8, #2 @ reset FIQ agreement
109 str r8, [r12, #IRQ_CONTROL_REG_OFFSET]
110
111 cmp r10, #INT_GPIO_BANK1 @ is it GPIO bank interrupt?
112 beq gpio @ yes - process it
113
114 mov r8, #1
115 orr r8, r11, r8, lsl r10 @ mask spurious interrupt
116 str r8, [r12, #IRQ_MIR_REG_OFFSET]
117exit:
118 subs pc, lr, #4 @ return from FIQ
119 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
120
121
122 @@@@@@@@@@@@@@@@@@@@@@@@@@@
123gpio: @ GPIO bank interrupt handler
124 ldr r12, omap1510_gpio_base @ set base pointer to GPIO bank
125
126 ldr r11, [r12, #OMAP1510_GPIO_INT_MASK] @ fetch GPIO interrupts mask
127restart:
128 ldr r13, [r12, #OMAP1510_GPIO_INT_STATUS] @ fetch status bits
129 bics r13, r13, r11 @ clear masked - any left?
130 beq exit @ no - spurious interrupt? exit
131
132 orr r11, r11, r13 @ mask all requested interrupts
133 str r11, [r12, #OMAP1510_GPIO_INT_MASK]
134
135 ands r10, r13, #KEYBRD_CLK_MASK @ extract keyboard status - set?
136 beq hksw @ no - try next source
137
138
139 @@@@@@@@@@@@@@@@@@@@@@
140 @ Keyboard clock FIQ mode interrupt handler
141 @ r10 now contains KEYBRD_CLK_MASK, use it
142 str r10, [r12, #OMAP1510_GPIO_INT_STATUS] @ ack the interrupt
143 bic r11, r11, r10 @ unmask it
144 str r11, [r12, #OMAP1510_GPIO_INT_MASK]
145
146 @ Process keyboard data
147 ldr r8, [r12, #OMAP1510_GPIO_DATA_INPUT] @ fetch GPIO input
148
149 ldr r10, [r9, #BUF_STATE] @ fetch kbd interface state
150 cmp r10, #0 @ are we expecting start bit?
151 bne data @ no - go to data processing
152
153 ands r8, r8, #KEYBRD_DATA_MASK @ check start bit - detected?
154 beq hksw @ no - try next source
155
156 @ r8 contains KEYBRD_DATA_MASK, use it
157 str r8, [r9, #BUF_STATE] @ enter data processing state
158 @ r10 already contains 0, reuse it
159 str r10, [r9, #BUF_KEY] @ clear keycode
160 mov r10, #2 @ reset input bit mask
161 str r10, [r9, #BUF_MASK]
162
163 @ Mask other GPIO line interrupts till key done
164 str r11, [r9, #BUF_GPIO_INT_MASK] @ save mask for later restore
165 mvn r11, #KEYBRD_CLK_MASK @ prepare all except kbd mask
166 str r11, [r12, #OMAP1510_GPIO_INT_MASK] @ store into the mask register
167
168 b restart @ restart
169
170data: ldr r10, [r9, #BUF_MASK] @ fetch current input bit mask
171
172 @ r8 still contains GPIO input bits
173 ands r8, r8, #KEYBRD_DATA_MASK @ is keyboard data line low?
174 ldreq r8, [r9, #BUF_KEY] @ yes - fetch collected so far,
175 orreq r8, r8, r10 @ set 1 at current mask position
176 streq r8, [r9, #BUF_KEY] @ and save back
177
178 mov r10, r10, lsl #1 @ shift mask left
179 bics r10, r10, #0x800 @ have we got all the bits?
180 strne r10, [r9, #BUF_MASK] @ not yet - store the mask
181 bne restart @ and restart
182
183 @ r10 already contains 0, reuse it
184 str r10, [r9, #BUF_STATE] @ reset state to start
185
186 @ Key done - restore interrupt mask
187 ldr r10, [r9, #BUF_GPIO_INT_MASK] @ fetch saved mask
188 and r11, r11, r10 @ unmask all saved as unmasked
189 str r11, [r12, #OMAP1510_GPIO_INT_MASK] @ restore into the mask register
190
191 @ Try appending the keycode to the circular buffer
192 ldr r10, [r9, #BUF_KEYS_CNT] @ get saved keystrokes count
193 ldr r8, [r9, #BUF_BUF_LEN] @ get buffer size
194 cmp r10, r8 @ is buffer full?
195 beq hksw @ yes - key lost, next source
196
197 add r10, r10, #1 @ incremet keystrokes counter
198 str r10, [r9, #BUF_KEYS_CNT]
199
200 ldr r10, [r9, #BUF_TAIL_OFFSET] @ get buffer tail offset
201 @ r8 already contains buffer size
202 cmp r10, r8 @ end of buffer?
203 moveq r10, #0 @ yes - rewind to buffer start
204
205 ldr r12, [r9, #BUF_BUFFER_START] @ get buffer start address
206 add r12, r12, r10, LSL #2 @ calculate buffer tail address
207 ldr r8, [r9, #BUF_KEY] @ get last keycode
208 str r8, [r12] @ append it to the buffer tail
209
210 add r10, r10, #1 @ increment buffer tail offset
211 str r10, [r9, #BUF_TAIL_OFFSET]
212
213 ldr r10, [r9, #BUF_CNT_INT_KEY] @ increment interrupts counter
214 add r10, r10, #1
215 str r10, [r9, #BUF_CNT_INT_KEY]
216 @@@@@@@@@@@@@@@@@@@@@@@@
217
218
219hksw: @Is hook switch interrupt requested?
220 tst r13, #HOOK_SWITCH_MASK @ is hook switch status bit set?
221 beq mdm @ no - try next source
222
223
224 @@@@@@@@@@@@@@@@@@@@@@@@
225 @ Hook switch interrupt FIQ mode simple handler
226
227 @ Don't toggle active edge, the switch always bounces
228
229 @ Increment hook switch interrupt counter
230 ldr r10, [r9, #BUF_CNT_INT_HSW]
231 add r10, r10, #1
232 str r10, [r9, #BUF_CNT_INT_HSW]
233 @@@@@@@@@@@@@@@@@@@@@@@@
234
235
236mdm: @Is it a modem interrupt?
237 tst r13, #MODEM_IRQ_MASK @ is modem status bit set?
238 beq irq @ no - check for next interrupt
239
240
241 @@@@@@@@@@@@@@@@@@@@@@@@
242 @ Modem FIQ mode interrupt handler stub
243
244 @ Increment modem interrupt counter
245 ldr r10, [r9, #BUF_CNT_INT_MDM]
246 add r10, r10, #1
247 str r10, [r9, #BUF_CNT_INT_MDM]
248 @@@@@@@@@@@@@@@@@@@@@@@@
249
250
251irq: @ Place deferred_fiq interrupt request
252 ldr r12, deferred_fiq_ih_base @ set pointer to IRQ handler
253 mov r10, #DEFERRED_FIQ_MASK @ set deferred_fiq bit
254 str r10, [r12, #IRQ_ISR_REG_OFFSET] @ place it in the ISR register
255
256 ldr r12, omap1510_gpio_base @ set pointer back to GPIO bank
257 b restart @ check for next GPIO interrupt
258 @@@@@@@@@@@@@@@@@@@@@@@@@@@
259
260
261/*
262 * Virtual addresses for IO
263 */
264omap_ih1_base:
265 .word OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
266deferred_fiq_ih_base:
267 .word OMAP1_IO_ADDRESS(DEFERRED_FIQ_IH_BASE)
268omap1510_gpio_base:
269 .word OMAP1_IO_ADDRESS(OMAP1510_GPIO_BASE)
270qwerty_fiqin_end:
271
272/*
273 * Check the size of the FIQ,
274 * it cannot go beyond 0xffff0200, and is copied to 0xffff001c
275 */
276.if (qwerty_fiqin_end - qwerty_fiqin_start) > (0x200 - 0x1c)
277 .err
278.endif
diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c
new file mode 100644
index 000000000000..6c994e2d8879
--- /dev/null
+++ b/arch/arm/mach-omap1/ams-delta-fiq.c
@@ -0,0 +1,155 @@
1/*
2 * Amstrad E3 FIQ handling
3 *
4 * Copyright (C) 2009 Janusz Krzysztofik
5 * Copyright (c) 2006 Matt Callow
6 * Copyright (c) 2004 Amstrad Plc
7 * Copyright (C) 2001 RidgeRun, Inc.
8 *
9 * Parts of this code are taken from linux/arch/arm/mach-omap/irq.c
10 * in the MontaVista 2.4 kernel (and the Amstrad changes therein)
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License version 2 as published by
14 * the Free Software Foundation.
15 */
16#include <linux/gpio.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/module.h>
20#include <linux/io.h>
21
22#include <plat/board-ams-delta.h>
23
24#include <asm/fiq.h>
25#include <mach/ams-delta-fiq.h>
26
27static struct fiq_handler fh = {
28 .name = "ams-delta-fiq"
29};
30
31/*
32 * This buffer is shared between FIQ and IRQ contexts.
33 * The FIQ and IRQ isrs can both read and write it.
34 * It is structured as a header section several 32bit slots,
35 * followed by the circular buffer where the FIQ isr stores
36 * keystrokes received from the qwerty keyboard.
37 * See ams-delta-fiq.h for details of offsets.
38 */
39unsigned int fiq_buffer[1024];
40EXPORT_SYMBOL(fiq_buffer);
41
42static unsigned int irq_counter[16];
43
44static irqreturn_t deferred_fiq(int irq, void *dev_id)
45{
46 struct irq_desc *irq_desc;
47 struct irq_chip *irq_chip = NULL;
48 int gpio, irq_num, fiq_count;
49
50 irq_desc = irq_to_desc(IH_GPIO_BASE);
51 if (irq_desc)
52 irq_chip = irq_desc->chip;
53
54 /*
55 * For each handled GPIO interrupt, keep calling its interrupt handler
56 * until the IRQ counter catches the FIQ incremented interrupt counter.
57 */
58 for (gpio = AMS_DELTA_GPIO_PIN_KEYBRD_CLK;
59 gpio <= AMS_DELTA_GPIO_PIN_HOOK_SWITCH; gpio++) {
60 irq_num = gpio_to_irq(gpio);
61 fiq_count = fiq_buffer[FIQ_CNT_INT_00 + gpio];
62
63 while (irq_counter[gpio] < fiq_count) {
64 if (gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) {
65 /*
66 * It looks like handle_edge_irq() that
67 * OMAP GPIO edge interrupts default to,
68 * expects interrupt already unmasked.
69 */
70 if (irq_chip && irq_chip->unmask)
71 irq_chip->unmask(irq_num);
72 }
73 generic_handle_irq(irq_num);
74
75 irq_counter[gpio]++;
76 }
77 }
78 return IRQ_HANDLED;
79}
80
81void __init ams_delta_init_fiq(void)
82{
83 void *fiqhandler_start;
84 unsigned int fiqhandler_length;
85 struct pt_regs FIQ_regs;
86 unsigned long val, offset;
87 int i, retval;
88
89 fiqhandler_start = &qwerty_fiqin_start;
90 fiqhandler_length = &qwerty_fiqin_end - &qwerty_fiqin_start;
91 pr_info("Installing fiq handler from %p, length 0x%x\n",
92 fiqhandler_start, fiqhandler_length);
93
94 retval = claim_fiq(&fh);
95 if (retval) {
96 pr_err("ams_delta_init_fiq(): couldn't claim FIQ, ret=%d\n",
97 retval);
98 return;
99 }
100
101 retval = request_irq(INT_DEFERRED_FIQ, deferred_fiq,
102 IRQ_TYPE_EDGE_RISING, "deferred_fiq", 0);
103 if (retval < 0) {
104 pr_err("Failed to get deferred_fiq IRQ, ret=%d\n", retval);
105 release_fiq(&fh);
106 return;
107 }
108 /*
109 * Since no set_type() method is provided by OMAP irq chip,
110 * switch to edge triggered interrupt type manually.
111 */
112 offset = IRQ_ILR0_REG_OFFSET + INT_DEFERRED_FIQ * 0x4;
113 val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1);
114 omap_writel(val, DEFERRED_FIQ_IH_BASE + offset);
115
116 set_fiq_handler(fiqhandler_start, fiqhandler_length);
117
118 /*
119 * Initialise the buffer which is shared
120 * between FIQ mode and IRQ mode
121 */
122 fiq_buffer[FIQ_GPIO_INT_MASK] = 0;
123 fiq_buffer[FIQ_MASK] = 0;
124 fiq_buffer[FIQ_STATE] = 0;
125 fiq_buffer[FIQ_KEY] = 0;
126 fiq_buffer[FIQ_KEYS_CNT] = 0;
127 fiq_buffer[FIQ_KEYS_HICNT] = 0;
128 fiq_buffer[FIQ_TAIL_OFFSET] = 0;
129 fiq_buffer[FIQ_HEAD_OFFSET] = 0;
130 fiq_buffer[FIQ_BUF_LEN] = 256;
131 fiq_buffer[FIQ_MISSED_KEYS] = 0;
132 fiq_buffer[FIQ_BUFFER_START] =
133 (unsigned int) &fiq_buffer[FIQ_CIRC_BUFF];
134
135 for (i = FIQ_CNT_INT_00; i <= FIQ_CNT_INT_15; i++)
136 fiq_buffer[i] = 0;
137
138 /*
139 * FIQ mode r9 always points to the fiq_buffer, becauses the FIQ isr
140 * will run in an unpredictable context. The fiq_buffer is the FIQ isr's
141 * only means of communication with the IRQ level and other kernel
142 * context code.
143 */
144 FIQ_regs.ARM_r9 = (unsigned int)fiq_buffer;
145 set_fiq_regs(&FIQ_regs);
146
147 pr_info("request_fiq(): fiq_buffer = %p\n", fiq_buffer);
148
149 /*
150 * Redirect GPIO interrupts to FIQ
151 */
152 offset = IRQ_ILR0_REG_OFFSET + INT_GPIO_BANK1 * 0x4;
153 val = omap_readl(OMAP_IH1_BASE + offset) | 1;
154 omap_writel(val, OMAP_IH1_BASE + offset);
155}
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 7fc11c34b696..fdd1dd53fa9c 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -33,6 +33,8 @@
33#include <plat/board.h> 33#include <plat/board.h>
34#include <plat/common.h> 34#include <plat/common.h>
35 35
36#include <mach/ams-delta-fiq.h>
37
36static u8 ams_delta_latch1_reg; 38static u8 ams_delta_latch1_reg;
37static u16 ams_delta_latch2_reg; 39static u16 ams_delta_latch2_reg;
38 40
@@ -236,6 +238,10 @@ static void __init ams_delta_init(void)
236 omap_usb_init(&ams_delta_usb_config); 238 omap_usb_init(&ams_delta_usb_config);
237 platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices)); 239 platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices));
238 240
241#ifdef CONFIG_AMS_DELTA_FIQ
242 ams_delta_init_fiq();
243#endif
244
239 omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1); 245 omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1);
240} 246}
241 247
@@ -263,8 +269,18 @@ static struct platform_device ams_delta_modem_device = {
263 269
264static int __init ams_delta_modem_init(void) 270static int __init ams_delta_modem_init(void)
265{ 271{
272 int err;
273
266 omap_cfg_reg(M14_1510_GPIO2); 274 omap_cfg_reg(M14_1510_GPIO2);
267 ams_delta_modem_ports[0].irq = gpio_to_irq(2); 275 ams_delta_modem_ports[0].irq =
276 gpio_to_irq(AMS_DELTA_GPIO_PIN_MODEM_IRQ);
277
278 err = gpio_request(AMS_DELTA_GPIO_PIN_MODEM_IRQ, "modem");
279 if (err) {
280 pr_err("Couldn't request gpio pin for modem\n");
281 return err;
282 }
283 gpio_direction_input(AMS_DELTA_GPIO_PIN_MODEM_IRQ);
268 284
269 ams_delta_latch2_write( 285 ams_delta_latch2_write(
270 AMS_DELTA_LATCH2_MODEM_NRESET | AMS_DELTA_LATCH2_MODEM_CODEC, 286 AMS_DELTA_LATCH2_MODEM_NRESET | AMS_DELTA_LATCH2_MODEM_CODEC,
diff --git a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h
new file mode 100644
index 000000000000..7a2df29400ca
--- /dev/null
+++ b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h
@@ -0,0 +1,79 @@
1/*
2 * arch/arm/mach-omap1/include/ams-delta-fiq.h
3 *
4 * Taken from the original Amstrad modifications to fiq.h
5 *
6 * Copyright (c) 2004 Amstrad Plc
7 * Copyright (c) 2006 Matt Callow
8 * Copyright (c) 2010 Janusz Krzysztofik
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#ifndef __AMS_DELTA_FIQ_H
15#define __AMS_DELTA_FIQ_H
16
17#include <plat/irqs.h>
18
19/*
20 * Interrupt number used for passing control from FIQ to IRQ.
21 * IRQ12, described as reserved, has been selected.
22 */
23#define INT_DEFERRED_FIQ INT_1510_RES12
24/*
25 * Base address of an interrupt handler that the INT_DEFERRED_FIQ belongs to.
26 */
27#if (INT_DEFERRED_FIQ < IH2_BASE)
28#define DEFERRED_FIQ_IH_BASE OMAP_IH1_BASE
29#else
30#define DEFERRED_FIQ_IH_BASE OMAP_IH2_BASE
31#endif
32
33/*
34 * These are the offsets from the begining of the fiq_buffer. They are put here
35 * since the buffer and header need to be accessed by drivers servicing devices
36 * which generate GPIO interrupts - e.g. keyboard, modem, hook switch.
37 */
38#define FIQ_MASK 0
39#define FIQ_STATE 1
40#define FIQ_KEYS_CNT 2
41#define FIQ_TAIL_OFFSET 3
42#define FIQ_HEAD_OFFSET 4
43#define FIQ_BUF_LEN 5
44#define FIQ_KEY 6
45#define FIQ_MISSED_KEYS 7
46#define FIQ_BUFFER_START 8
47#define FIQ_GPIO_INT_MASK 9
48#define FIQ_KEYS_HICNT 10
49#define FIQ_IRQ_PEND 11
50#define FIQ_SIR_CODE_L1 12
51#define IRQ_SIR_CODE_L2 13
52
53#define FIQ_CNT_INT_00 14
54#define FIQ_CNT_INT_KEY 15
55#define FIQ_CNT_INT_MDM 16
56#define FIQ_CNT_INT_03 17
57#define FIQ_CNT_INT_HSW 18
58#define FIQ_CNT_INT_05 19
59#define FIQ_CNT_INT_06 20
60#define FIQ_CNT_INT_07 21
61#define FIQ_CNT_INT_08 22
62#define FIQ_CNT_INT_09 23
63#define FIQ_CNT_INT_10 24
64#define FIQ_CNT_INT_11 25
65#define FIQ_CNT_INT_12 26
66#define FIQ_CNT_INT_13 27
67#define FIQ_CNT_INT_14 28
68#define FIQ_CNT_INT_15 29
69
70#define FIQ_CIRC_BUFF 30 /*Start of circular buffer */
71
72#ifndef __ASSEMBLER__
73extern unsigned int fiq_buffer[];
74extern unsigned char qwerty_fiqin_start, qwerty_fiqin_end;
75
76extern void __init ams_delta_init_fiq(void);
77#endif
78
79#endif
diff --git a/arch/arm/mach-omap1/include/mach/debug-macro.S b/arch/arm/mach-omap1/include/mach/debug-macro.S
index b6d9584544b4..e8a8cf36b7f0 100644
--- a/arch/arm/mach-omap1/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap1/include/mach/debug-macro.S
@@ -13,6 +13,8 @@
13 13
14#include <linux/serial_reg.h> 14#include <linux/serial_reg.h>
15 15
16#include <asm/memory.h>
17
16#include <plat/serial.h> 18#include <plat/serial.h>
17 19
18 .pushsection .data 20 .pushsection .data
@@ -37,23 +39,12 @@ omap_uart_virt: .word 0x0
37 cmp \rx, #0 @ is port configured? 39 cmp \rx, #0 @ is port configured?
38 bne 99f @ already configured 40 bne 99f @ already configured
39 41
40 /* Check 7XX UART1 scratchpad register for uart to use */ 42 /* Check the debug UART configuration set in uncompress.h */
41 mrc p15, 0, \rx, c1, c0 43 mrc p15, 0, \rx, c1, c0
42 tst \rx, #1 @ MMU enabled? 44 tst \rx, #1 @ MMU enabled?
43 moveq \rx, #0xff000000 @ physical base address 45 ldreq \rx, =OMAP_UART_INFO
44 movne \rx, #0xfe000000 @ virtual base 46 ldrne \rx, =__phys_to_virt(OMAP_UART_INFO)
45 orr \rx, \rx, #0x00fb0000 @ OMAP1UART1 47 ldr \rx, [\rx, #0]
46 ldrb \rx, [\rx, #(UART_SCR << OMAP7XX_PORT_SHIFT)]
47 cmp \rx, #0 @ anything in 7XX scratchpad?
48 bne 10f @ found 7XX uart
49
50 /* Check 15xx/16xx UART1 scratchpad register for uart to use */
51 mrc p15, 0, \rx, c1, c0
52 tst \rx, #1 @ MMU enabled?
53 moveq \rx, #0xff000000 @ physical base address
54 movne \rx, #0xfe000000 @ virtual base
55 orr \rx, \rx, #0x00fb0000 @ OMAP1UART1
56 ldrb \rx, [\rx, #(UART_SCR << OMAP_PORT_SHIFT)]
57 48
58 /* Select the UART to use based on the UART1 scratchpad value */ 49 /* Select the UART to use based on the UART1 scratchpad value */
5910: cmp \rx, #0 @ no port configured? 5010: cmp \rx, #0 @ no port configured?
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 2de4f79f03a0..e679a2cc86c3 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -45,6 +45,7 @@
45#include <plat/gpmc.h> 45#include <plat/gpmc.h>
46#include <plat/usb.h> 46#include <plat/usb.h>
47#include <plat/display.h> 47#include <plat/display.h>
48#include <plat/mcspi.h>
48 49
49#include <mach/hardware.h> 50#include <mach/hardware.h>
50 51
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index e15d2e87cfc1..1d7f827b0408 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -82,7 +82,7 @@ static inline void __init zoom_init_smsc911x(void)
82 82
83static struct plat_serial8250_port serial_platform_data[] = { 83static struct plat_serial8250_port serial_platform_data[] = {
84 { 84 {
85 .mapbase = 0x10000000, 85 .mapbase = ZOOM_UART_BASE,
86 .irq = OMAP_GPIO_IRQ(102), 86 .irq = OMAP_GPIO_IRQ(102),
87 .flags = UPF_BOOT_AUTOCONF|UPF_IOREMAP|UPF_SHARE_IRQ, 87 .flags = UPF_BOOT_AUTOCONF|UPF_IOREMAP|UPF_SHARE_IRQ,
88 .irqflags = IRQF_SHARED | IRQF_TRIGGER_RISING, 88 .irqflags = IRQF_SHARED | IRQF_TRIGGER_RISING,
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c
index 9a26f84b1141..803ef14cbf2d 100644
--- a/arch/arm/mach-omap2/board-zoom2.c
+++ b/arch/arm/mach-omap2/board-zoom2.c
@@ -91,8 +91,8 @@ static void __init omap_zoom2_map_io(void)
91} 91}
92 92
93MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") 93MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
94 .phys_io = 0x48000000, 94 .phys_io = ZOOM_UART_BASE,
95 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, 95 .io_pg_offst = (ZOOM_UART_VIRT >> 18) & 0xfffc,
96 .boot_params = 0x80000100, 96 .boot_params = 0x80000100,
97 .map_io = omap_zoom2_map_io, 97 .map_io = omap_zoom2_map_io,
98 .init_irq = omap_zoom2_init_irq, 98 .init_irq = omap_zoom2_init_irq,
diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c
index cd3e40cf3ac1..33147042485f 100644
--- a/arch/arm/mach-omap2/board-zoom3.c
+++ b/arch/arm/mach-omap2/board-zoom3.c
@@ -73,8 +73,8 @@ static void __init omap_zoom_init(void)
73} 73}
74 74
75MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") 75MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
76 .phys_io = 0x48000000, 76 .phys_io = ZOOM_UART_BASE,
77 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, 77 .io_pg_offst = (ZOOM_UART_VIRT >> 18) & 0xfffc,
78 .boot_params = 0x80000100, 78 .boot_params = 0x80000100,
79 .map_io = omap_zoom_map_io, 79 .map_io = omap_zoom_map_io,
80 .init_irq = omap_zoom_init_irq, 80 .init_irq = omap_zoom_init_irq,
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index 4a63a2ea484d..35b24409a0c8 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -13,6 +13,8 @@
13 13
14#include <linux/serial_reg.h> 14#include <linux/serial_reg.h>
15 15
16#include <asm/memory.h>
17
16#include <plat/serial.h> 18#include <plat/serial.h>
17 19
18#define UART_OFFSET(addr) ((addr) & 0x00ffffff) 20#define UART_OFFSET(addr) ((addr) & 0x00ffffff)
@@ -40,13 +42,12 @@ omap_uart_lsr: .word 0
40 cmp \rx, #0 @ is port configured? 42 cmp \rx, #0 @ is port configured?
41 bne 99f @ already configured 43 bne 99f @ already configured
42 44
43 /* Check UART1 scratchpad register for uart to use */ 45 /* Check the debug UART configuration set in uncompress.h */
44 mrc p15, 0, \rx, c1, c0 46 mrc p15, 0, \rx, c1, c0
45 tst \rx, #1 @ MMU enabled? 47 tst \rx, #1 @ MMU enabled?
46 moveq \rx, #0x48000000 @ physical base address 48 ldreq \rx, =OMAP_UART_INFO
47 movne \rx, #0xfa000000 @ virtual base 49 ldrne \rx, =__phys_to_virt(OMAP_UART_INFO)
48 orr \rx, \rx, #0x0006a000 @ uart1 on omap2/3/4 50 ldr \rx, [\rx, #0]
49 ldrb \rx, [\rx, #(UART_SCR << OMAP_PORT_SHIFT)] @ scratchpad
50 51
51 /* Select the UART to use based on the UART1 scratchpad value */ 52 /* Select the UART to use based on the UART1 scratchpad value */
52 cmp \rx, #0 @ no port configured? 53 cmp \rx, #0 @ no port configured?
@@ -87,10 +88,10 @@ omap_uart_lsr: .word 0
87 b 98f 88 b 98f
8844: mov \rx, #UART_OFFSET(OMAP4_UART4_BASE) 8944: mov \rx, #UART_OFFSET(OMAP4_UART4_BASE)
89 b 98f 90 b 98f
9095: mov \rx, #ZOOM_UART_BASE 9195: ldr \rx, =ZOOM_UART_BASE
91 ldr \tmp, =omap_uart_phys 92 ldr \tmp, =omap_uart_phys
92 str \rx, [\tmp, #0] 93 str \rx, [\tmp, #0]
93 mov \rx, #ZOOM_UART_VIRT 94 ldr \rx, =ZOOM_UART_VIRT
94 ldr \tmp, =omap_uart_virt 95 ldr \tmp, =omap_uart_virt
95 str \rx, [\tmp, #0] 96 str \rx, [\tmp, #0]
96 mov \rx, #(UART_LSR << ZOOM_PORT_SHIFT) 97 mov \rx, #(UART_LSR << ZOOM_PORT_SHIFT)
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 87f676acf61d..3cfb425ea67e 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -166,6 +166,15 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
166 .length = L4_EMU_34XX_SIZE, 166 .length = L4_EMU_34XX_SIZE,
167 .type = MT_DEVICE 167 .type = MT_DEVICE
168 }, 168 },
169#if defined(CONFIG_DEBUG_LL) && \
170 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
171 {
172 .virtual = ZOOM_UART_VIRT,
173 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
174 .length = SZ_1M,
175 .type = MT_DEVICE
176 },
177#endif
169}; 178};
170#endif 179#endif
171#ifdef CONFIG_ARCH_OMAP4 180#ifdef CONFIG_ARCH_OMAP4
diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c
index 07aa7b3c95f7..2ff4dce95ee8 100644
--- a/arch/arm/mach-omap2/mux34xx.c
+++ b/arch/arm/mach-omap2/mux34xx.c
@@ -1901,26 +1901,15 @@ struct omap_ball __initdata omap36xx_cbp_ball[] = {
1901 _OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"), 1901 _OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"),
1902 _OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"), 1902 _OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"),
1903 _OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"), 1903 _OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"),
1904 _OMAP3_BALLENTRY(GPMC_D0, "k1", "m2"),
1905 _OMAP3_BALLENTRY(GPMC_D1, "l1", "m1"),
1906 _OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"), 1904 _OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"),
1907 _OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"), 1905 _OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"),
1908 _OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"), 1906 _OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"),
1909 _OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"), 1907 _OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"),
1910 _OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"), 1908 _OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"),
1911 _OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"), 1909 _OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"),
1912 _OMAP3_BALLENTRY(GPMC_D2, "l2", "n2"),
1913 _OMAP3_BALLENTRY(GPMC_D3, "p2", "n1"),
1914 _OMAP3_BALLENTRY(GPMC_D4, "t1", "r2"),
1915 _OMAP3_BALLENTRY(GPMC_D5, "v1", "r1"),
1916 _OMAP3_BALLENTRY(GPMC_D6, "v2", "t2"),
1917 _OMAP3_BALLENTRY(GPMC_D7, "w2", "t1"),
1918 _OMAP3_BALLENTRY(GPMC_D8, "h2", "ab3"),
1919 _OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"), 1910 _OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"),
1920 _OMAP3_BALLENTRY(GPMC_NADV_ALE, "f3", "w1"),
1921 _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"), 1911 _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"),
1922 _OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL), 1912 _OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL),
1923 _OMAP3_BALLENTRY(GPMC_NCS0, "g4", "y2"),
1924 _OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"), 1913 _OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"),
1925 _OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL), 1914 _OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL),
1926 _OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL), 1915 _OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL),
@@ -1928,10 +1917,7 @@ struct omap_ball __initdata omap36xx_cbp_ball[] = {
1928 _OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL), 1917 _OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL),
1929 _OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL), 1918 _OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL),
1930 _OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL), 1919 _OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL),
1931 _OMAP3_BALLENTRY(GPMC_NOE, "g2", "v2"),
1932 _OMAP3_BALLENTRY(GPMC_NWE, "f4", "v1"),
1933 _OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"), 1920 _OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"),
1934 _OMAP3_BALLENTRY(GPMC_WAIT0, "m8", "ab12"),
1935 _OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"), 1921 _OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"),
1936 _OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL), 1922 _OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL),
1937 _OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL), 1923 _OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL),
@@ -1948,8 +1934,6 @@ struct omap_ball __initdata omap36xx_cbp_ball[] = {
1948 _OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL), 1934 _OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL),
1949 _OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL), 1935 _OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL),
1950 _OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL), 1936 _OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL),
1951 _OMAP3_BALLENTRY(I2C1_SCL, "k21", NULL),
1952 _OMAP3_BALLENTRY(I2C1_SDA, "j21", NULL),
1953 _OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL), 1937 _OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL),
1954 _OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL), 1938 _OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL),
1955 _OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL), 1939 _OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL),
@@ -1958,11 +1942,6 @@ struct omap_ball __initdata omap36xx_cbp_ball[] = {
1958 _OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL), 1942 _OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL),
1959 _OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL), 1943 _OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL),
1960 _OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL), 1944 _OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL),
1961 _OMAP3_BALLENTRY(JTAG_RTCK, "aa12", NULL),
1962 _OMAP3_BALLENTRY(JTAG_TCK, "aa13", NULL),
1963 _OMAP3_BALLENTRY(JTAG_TDI, "aa20", NULL),
1964 _OMAP3_BALLENTRY(JTAG_TDO, "aa19", NULL),
1965 _OMAP3_BALLENTRY(JTAG_TMS_TMSC, "aa18", NULL),
1966 _OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL), 1945 _OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL),
1967 _OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL), 1946 _OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL),
1968 _OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL), 1947 _OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL),
@@ -2010,77 +1989,12 @@ struct omap_ball __initdata omap36xx_cbp_ball[] = {
2010 _OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL), 1989 _OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL),
2011 _OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL), 1990 _OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL),
2012 _OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL), 1991 _OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL),
2013 _OMAP3_BALLENTRY(SDRC_A0, NULL, "n22"),
2014 _OMAP3_BALLENTRY(SDRC_A1, NULL, "n23"),
2015 _OMAP3_BALLENTRY(SDRC_A10, NULL, "v22"),
2016 _OMAP3_BALLENTRY(SDRC_A11, NULL, "v23"),
2017 _OMAP3_BALLENTRY(SDRC_A12, NULL, "w22"),
2018 _OMAP3_BALLENTRY(SDRC_A13, NULL, "w23"),
2019 _OMAP3_BALLENTRY(SDRC_A14, NULL, "y22"),
2020 _OMAP3_BALLENTRY(SDRC_A2, NULL, "p22"),
2021 _OMAP3_BALLENTRY(SDRC_A3, NULL, "p23"),
2022 _OMAP3_BALLENTRY(SDRC_A4, NULL, "r22"),
2023 _OMAP3_BALLENTRY(SDRC_A5, NULL, "r23"),
2024 _OMAP3_BALLENTRY(SDRC_A6, NULL, "t22"),
2025 _OMAP3_BALLENTRY(SDRC_A7, NULL, "t23"),
2026 _OMAP3_BALLENTRY(SDRC_A8, NULL, "u22"),
2027 _OMAP3_BALLENTRY(SDRC_A9, NULL, "u23"),
2028 _OMAP3_BALLENTRY(SDRC_BA0, "h9", "ab21"),
2029 _OMAP3_BALLENTRY(SDRC_BA1, "h10", "ac21"),
2030 _OMAP3_BALLENTRY(SDRC_CKE0, "h16", "j22"), 1992 _OMAP3_BALLENTRY(SDRC_CKE0, "h16", "j22"),
2031 _OMAP3_BALLENTRY(SDRC_CKE1, "h17", "j23"), 1993 _OMAP3_BALLENTRY(SDRC_CKE1, "h17", "j23"),
2032 _OMAP3_BALLENTRY(SDRC_CLK, "a13", "a11"),
2033 _OMAP3_BALLENTRY(SDRC_D0, NULL, "j2"),
2034 _OMAP3_BALLENTRY(SDRC_D1, NULL, "j1"),
2035 _OMAP3_BALLENTRY(SDRC_D10, "c15", "b14"),
2036 _OMAP3_BALLENTRY(SDRC_D11, "b16", "a14"),
2037 _OMAP3_BALLENTRY(SDRC_D12, "d17", "b16"),
2038 _OMAP3_BALLENTRY(SDRC_D13, "c17", "a16"),
2039 _OMAP3_BALLENTRY(SDRC_D14, "b17", "b19"),
2040 _OMAP3_BALLENTRY(SDRC_D15, "d18", "a19"),
2041 _OMAP3_BALLENTRY(SDRC_D16, NULL, "b3"),
2042 _OMAP3_BALLENTRY(SDRC_D17, NULL, "a3"),
2043 _OMAP3_BALLENTRY(SDRC_D18, NULL, "b5"),
2044 _OMAP3_BALLENTRY(SDRC_D19, NULL, "a5"),
2045 _OMAP3_BALLENTRY(SDRC_D2, NULL, "g2"),
2046 _OMAP3_BALLENTRY(SDRC_D20, NULL, "b8"),
2047 _OMAP3_BALLENTRY(SDRC_D21, NULL, "a8"),
2048 _OMAP3_BALLENTRY(SDRC_D22, NULL, "b9"),
2049 _OMAP3_BALLENTRY(SDRC_D23, NULL, "a9"),
2050 _OMAP3_BALLENTRY(SDRC_D24, NULL, "b21"),
2051 _OMAP3_BALLENTRY(SDRC_D25, NULL, "a21"),
2052 _OMAP3_BALLENTRY(SDRC_D26, NULL, "d22"),
2053 _OMAP3_BALLENTRY(SDRC_D27, NULL, "d23"),
2054 _OMAP3_BALLENTRY(SDRC_D28, NULL, "e22"),
2055 _OMAP3_BALLENTRY(SDRC_D29, NULL, "e23"),
2056 _OMAP3_BALLENTRY(SDRC_D3, NULL, "g1"),
2057 _OMAP3_BALLENTRY(SDRC_D30, NULL, "g22"),
2058 _OMAP3_BALLENTRY(SDRC_D31, NULL, "g23"),
2059 _OMAP3_BALLENTRY(SDRC_D4, NULL, "f2"),
2060 _OMAP3_BALLENTRY(SDRC_D5, NULL, "f1"),
2061 _OMAP3_BALLENTRY(SDRC_D6, NULL, "d2"),
2062 _OMAP3_BALLENTRY(SDRC_D7, NULL, "d1"),
2063 _OMAP3_BALLENTRY(SDRC_D8, "c14", "b13"),
2064 _OMAP3_BALLENTRY(SDRC_D9, "b14", "a13"),
2065 _OMAP3_BALLENTRY(SDRC_DM0, NULL, "c1"),
2066 _OMAP3_BALLENTRY(SDRC_DM1, "a16", "a17"),
2067 _OMAP3_BALLENTRY(SDRC_DM2, NULL, "a6"),
2068 _OMAP3_BALLENTRY(SDRC_DM3, NULL, "a20"),
2069 _OMAP3_BALLENTRY(SDRC_DQS0, NULL, "c2"),
2070 _OMAP3_BALLENTRY(SDRC_DQS1, "a17", "b17"),
2071 _OMAP3_BALLENTRY(SDRC_DQS2, NULL, "b6"),
2072 _OMAP3_BALLENTRY(SDRC_DQS3, NULL, "b20"),
2073 _OMAP3_BALLENTRY(SDRC_NCAS, "h13", "l22"),
2074 _OMAP3_BALLENTRY(SDRC_NCLK, "a14", "b11"),
2075 _OMAP3_BALLENTRY(SDRC_NCS0, "h11", "m22"),
2076 _OMAP3_BALLENTRY(SDRC_NCS1, "h12", "m23"),
2077 _OMAP3_BALLENTRY(SDRC_NRAS, "h14", "l23"),
2078 _OMAP3_BALLENTRY(SDRC_NWE, "h15", "k23"),
2079 _OMAP3_BALLENTRY(SIM_CLK, "p26", NULL), 1994 _OMAP3_BALLENTRY(SIM_CLK, "p26", NULL),
2080 _OMAP3_BALLENTRY(SIM_IO, "p27", NULL), 1995 _OMAP3_BALLENTRY(SIM_IO, "p27", NULL),
2081 _OMAP3_BALLENTRY(SIM_PWRCTRL, "r27", NULL), 1996 _OMAP3_BALLENTRY(SIM_PWRCTRL, "r27", NULL),
2082 _OMAP3_BALLENTRY(SIM_RST, "r25", NULL), 1997 _OMAP3_BALLENTRY(SIM_RST, "r25", NULL),
2083 _OMAP3_BALLENTRY(SYS_32K, "ae25", NULL),
2084 _OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL), 1998 _OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL),
2085 _OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL), 1999 _OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL),
2086 _OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL), 2000 _OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL),
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 401701977dbb..c01d9f08a198 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -428,4 +428,8 @@ void omap3_intc_resume_idle(void);
428 428
429#include <mach/hardware.h> 429#include <mach/hardware.h>
430 430
431#ifdef CONFIG_FIQ
432#define FIQ_START 1024
433#endif
434
431#endif 435#endif
diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
index f235d32cd942..ffd909fa5287 100644
--- a/arch/arm/plat-omap/include/plat/multi.h
+++ b/arch/arm/plat-omap/include/plat/multi.h
@@ -61,9 +61,9 @@
61# define OMAP_NAME omap16xx 61# define OMAP_NAME omap16xx
62# endif 62# endif
63#endif 63#endif
64#if (defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)) 64#ifdef CONFIG_ARCH_OMAP2PLUS
65# if (defined(OMAP_NAME) || defined(MULTI_OMAP1)) 65# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
66# error "OMAP1 and OMAP2 can't be selected at the same time" 66# error "OMAP1 and OMAP2PLUS can't be selected at the same time"
67# endif 67# endif
68#endif 68#endif
69#ifdef CONFIG_ARCH_OMAP2420 69#ifdef CONFIG_ARCH_OMAP2420
@@ -82,12 +82,20 @@
82# define OMAP_NAME omap2430 82# define OMAP_NAME omap2430
83# endif 83# endif
84#endif 84#endif
85#ifdef CONFIG_ARCH_OMAP3430 85#ifdef CONFIG_ARCH_OMAP3
86# ifdef OMAP_NAME 86# ifdef OMAP_NAME
87# undef MULTI_OMAP2 87# undef MULTI_OMAP2
88# define MULTI_OMAP2 88# define MULTI_OMAP2
89# else 89# else
90# define OMAP_NAME omap3430 90# define OMAP_NAME omap3
91# endif
92#endif
93#ifdef CONFIG_ARCH_OMAP4
94# ifdef OMAP_NAME
95# undef MULTI_OMAP2
96# define MULTI_OMAP2
97# else
98# define OMAP_NAME omap4
91# endif 99# endif
92#endif 100#endif
93 101
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index 83dce4c4f7e6..19145f5c32ba 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -15,6 +15,20 @@
15 15
16#include <linux/init.h> 16#include <linux/init.h>
17 17
18/*
19 * Memory entry used for the DEBUG_LL UART configuration. See also
20 * uncompress.h and debug-macro.S.
21 *
22 * Note that using a memory location for storing the UART configuration
23 * has at least two limitations:
24 *
25 * 1. Kernel uncompress code cannot overlap OMAP_UART_INFO as the
26 * uncompress code could then partially overwrite itself
27 * 2. We assume printascii is called at least once before paging_init,
28 * and addruart has a chance to read OMAP_UART_INFO
29 */
30#define OMAP_UART_INFO (PHYS_OFFSET + 0x3ffc)
31
18/* OMAP1 serial ports */ 32/* OMAP1 serial ports */
19#define OMAP1_UART1_BASE 0xfffb0000 33#define OMAP1_UART1_BASE 0xfffb0000
20#define OMAP1_UART2_BASE 0xfffb0800 34#define OMAP1_UART2_BASE 0xfffb0800
@@ -39,7 +53,7 @@
39 53
40/* External port on Zoom2/3 */ 54/* External port on Zoom2/3 */
41#define ZOOM_UART_BASE 0x10000000 55#define ZOOM_UART_BASE 0x10000000
42#define ZOOM_UART_VIRT 0xfb000000 56#define ZOOM_UART_VIRT 0xfa400000
43 57
44#define OMAP_PORT_SHIFT 2 58#define OMAP_PORT_SHIFT 2
45#define OMAP7XX_PORT_SHIFT 0 59#define OMAP7XX_PORT_SHIFT 0
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 81d9ec540fcf..bbedd71943f6 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -20,27 +20,21 @@
20#include <linux/types.h> 20#include <linux/types.h>
21#include <linux/serial_reg.h> 21#include <linux/serial_reg.h>
22 22
23#include <asm/memory.h>
23#include <asm/mach-types.h> 24#include <asm/mach-types.h>
24 25
25#include <plat/serial.h> 26#include <plat/serial.h>
26 27
27static volatile u8 *uart1_base;
28static int uart1_shift;
29
30static volatile u8 *uart_base; 28static volatile u8 *uart_base;
31static int uart_shift; 29static int uart_shift;
32 30
33/* 31/*
34 * Store the DEBUG_LL uart number into UART1 scratchpad register. 32 * Store the DEBUG_LL uart number into memory.
35 * See also debug-macro.S, and serial.c for related code. 33 * See also debug-macro.S, and serial.c for related code.
36 *
37 * Please note that we currently assume that:
38 * - UART1 clocks are enabled for register access
39 * - UART1 scratchpad register can be used
40 */ 34 */
41static void set_uart1_scratchpad(unsigned char port) 35static void set_omap_uart_info(unsigned char port)
42{ 36{
43 uart1_base[UART_SCR << uart1_shift] = port; 37 *(volatile u32 *)OMAP_UART_INFO = port;
44} 38}
45 39
46static void putc(int c) 40static void putc(int c)
@@ -60,42 +54,38 @@ static inline void flush(void)
60/* 54/*
61 * Macros to configure UART1 and debug UART 55 * Macros to configure UART1 and debug UART
62 */ 56 */
63#define _DEBUG_LL_ENTRY(mach, uart1_phys, uart1_shft, \ 57#define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id) \
64 dbg_uart, dbg_shft, dbg_id) \
65 if (machine_is_##mach()) { \ 58 if (machine_is_##mach()) { \
66 uart1_base = (volatile u8 *)(uart1_phys); \
67 uart1_shift = (uart1_shft); \
68 uart_base = (volatile u8 *)(dbg_uart); \ 59 uart_base = (volatile u8 *)(dbg_uart); \
69 uart_shift = (dbg_shft); \ 60 uart_shift = (dbg_shft); \
70 port = (dbg_id); \ 61 port = (dbg_id); \
71 set_uart1_scratchpad(port); \ 62 set_omap_uart_info(port); \
72 break; \ 63 break; \
73 } 64 }
74 65
75#define DEBUG_LL_OMAP7XX(p, mach) \ 66#define DEBUG_LL_OMAP7XX(p, mach) \
76 _DEBUG_LL_ENTRY(mach, OMAP1_UART1_BASE, OMAP7XX_PORT_SHIFT, \ 67 _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, \
77 OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, OMAP1UART##p) 68 OMAP1UART##p)
78 69
79#define DEBUG_LL_OMAP1(p, mach) \ 70#define DEBUG_LL_OMAP1(p, mach) \
80 _DEBUG_LL_ENTRY(mach, OMAP1_UART1_BASE, OMAP_PORT_SHIFT, \ 71 _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT, \
81 OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP1UART##p) 72 OMAP1UART##p)
82 73
83#define DEBUG_LL_OMAP2(p, mach) \ 74#define DEBUG_LL_OMAP2(p, mach) \
84 _DEBUG_LL_ENTRY(mach, OMAP2_UART1_BASE, OMAP_PORT_SHIFT, \ 75 _DEBUG_LL_ENTRY(mach, OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT, \
85 OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP2UART##p) 76 OMAP2UART##p)
86 77
87#define DEBUG_LL_OMAP3(p, mach) \ 78#define DEBUG_LL_OMAP3(p, mach) \
88 _DEBUG_LL_ENTRY(mach, OMAP3_UART1_BASE, OMAP_PORT_SHIFT, \ 79 _DEBUG_LL_ENTRY(mach, OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT, \
89 OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP3UART##p) 80 OMAP3UART##p)
90 81
91#define DEBUG_LL_OMAP4(p, mach) \ 82#define DEBUG_LL_OMAP4(p, mach) \
92 _DEBUG_LL_ENTRY(mach, OMAP4_UART1_BASE, OMAP_PORT_SHIFT, \ 83 _DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, \
93 OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP4UART##p) 84 OMAP4UART##p)
94 85
95/* Zoom2/3 shift is different for UART1 and external port */ 86/* Zoom2/3 shift is different for UART1 and external port */
96#define DEBUG_LL_ZOOM(mach) \ 87#define DEBUG_LL_ZOOM(mach) \
97 _DEBUG_LL_ENTRY(mach, OMAP2_UART1_BASE, OMAP_PORT_SHIFT, \ 88 _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
98 ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
99 89
100static inline void __arch_decomp_setup(unsigned long arch_id) 90static inline void __arch_decomp_setup(unsigned long arch_id)
101{ 91{
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 51f4dfb82e2b..226b2e858d6c 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -437,6 +437,20 @@ static inline int omap34xx_sram_init(void)
437} 437}
438#endif 438#endif
439 439
440#ifdef CONFIG_ARCH_OMAP4
441int __init omap44xx_sram_init(void)
442{
443 printk(KERN_ERR "FIXME: %s not implemented\n", __func__);
444
445 return -ENODEV;
446}
447#else
448static inline int omap44xx_sram_init(void)
449{
450 return 0;
451}
452#endif
453
440int __init omap_sram_init(void) 454int __init omap_sram_init(void)
441{ 455{
442 omap_detect_sram(); 456 omap_detect_sram();
@@ -451,7 +465,7 @@ int __init omap_sram_init(void)
451 else if (cpu_is_omap34xx()) 465 else if (cpu_is_omap34xx())
452 omap34xx_sram_init(); 466 omap34xx_sram_init();
453 else if (cpu_is_omap44xx()) 467 else if (cpu_is_omap44xx())
454 omap34xx_sram_init(); /* FIXME: */ 468 omap44xx_sram_init();
455 469
456 return 0; 470 return 0;
457} 471}
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-20 20:39:00 -0400