8 files changed, 108 insertions, 87 deletions

diff --git a/arch/arm/mach-at91rm9200/at91rm9200.c b/arch/arm/mach-at91rm9200/at91rm9200.c
index 7e1d072bdd80..0985b1c42c7c 100644
--- a/arch/arm/mach-at91rm9200/at91rm9200.c
+++ b/arch/arm/mach-at91rm9200/at91rm9200.c
@@ -107,3 +107,48 @@ void __init at91rm9200_map_io(void)
         iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
 }
 
+/*
+ * The default interrupt priority levels (0 = lowest, 7 = highest).
+ */
+static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
+        7,      /* Advanced Interrupt Controller (FIQ) */
+        7,      /* System Peripherals */
+        0,      /* Parallel IO Controller A */
+        0,      /* Parallel IO Controller B */
+        0,      /* Parallel IO Controller C */
+        0,      /* Parallel IO Controller D */
+        6,      /* USART 0 */
+        6,      /* USART 1 */
+        6,      /* USART 2 */
+        6,      /* USART 3 */
+        0,      /* Multimedia Card Interface */
+        4,      /* USB Device Port */
+        0,      /* Two-Wire Interface */
+        6,      /* Serial Peripheral Interface */
+        5,      /* Serial Synchronous Controller 0 */
+        5,      /* Serial Synchronous Controller 1 */
+        5,      /* Serial Synchronous Controller 2 */
+        0,      /* Timer Counter 0 */
+        0,      /* Timer Counter 1 */
+        0,      /* Timer Counter 2 */
+        0,      /* Timer Counter 3 */
+        0,      /* Timer Counter 4 */
+        0,      /* Timer Counter 5 */
+        3,      /* USB Host port */
+        3,      /* Ethernet MAC */
+        0,      /* Advanced Interrupt Controller (IRQ0) */
+        0,      /* Advanced Interrupt Controller (IRQ1) */
+        0,      /* Advanced Interrupt Controller (IRQ2) */
+        0,      /* Advanced Interrupt Controller (IRQ3) */
+        0,      /* Advanced Interrupt Controller (IRQ4) */
+        0,      /* Advanced Interrupt Controller (IRQ5) */
+        0       /* Advanced Interrupt Controller (IRQ6) */
+};
+
+void __init at91rm9200_init_irq(unsigned int priority[NR_AIC_IRQS])
+{
+        if (!priority)
+                priority = at91rm9200_default_irq_priority;
+
+        at91_aic_init(priority);
+}
diff --git a/arch/arm/mach-at91rm9200/generic.h b/arch/arm/mach-at91rm9200/generic.h
index f0d969d7d874..7979d8ab7e07 100644
--- a/arch/arm/mach-at91rm9200/generic.h
+++ b/arch/arm/mach-at91rm9200/generic.h
@@ -8,13 +8,19 @@
  * published by the Free Software Foundation.
  */
 
-void at91_gpio_irq_setup(unsigned banks);
+ /* Interrupts */
+extern void __init at91rm9200_init_irq(unsigned int priority[]);
+extern void __init at91_aic_init(unsigned int priority[]);
+extern void __init at91_gpio_irq_setup(unsigned banks);
 
+ /* Timer */
 struct sys_timer;
 extern struct sys_timer at91rm9200_timer;
 
+ /* Memory Map */
 extern void __init at91rm9200_map_io(void);
 
+ /* Clocks */
 extern int __init at91_clock_init(unsigned long main_clock);
 struct device;
 extern void __init at91_clock_associate(const char *id, struct device *dev, const char *func);
diff --git a/arch/arm/mach-at91rm9200/irq.c b/arch/arm/mach-at91rm9200/irq.c
index dcd560dbcfb7..9b0911320417 100644
--- a/arch/arm/mach-at91rm9200/irq.c
+++ b/arch/arm/mach-at91rm9200/irq.c
@@ -36,58 +36,20 @@
 
 #include "generic.h"
 
-/*
- * The default interrupt priority levels (0 = lowest, 7 = highest).
- */
-static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
-        7,      /* Advanced Interrupt Controller */
-        7,      /* System Peripheral */
-        0,      /* Parallel IO Controller A */
-        0,      /* Parallel IO Controller B */
-        0,      /* Parallel IO Controller C */
-        0,      /* Parallel IO Controller D */
-        6,      /* USART 0 */
-        6,      /* USART 1 */
-        6,      /* USART 2 */
-        6,      /* USART 3 */
-        0,      /* Multimedia Card Interface */
-        4,      /* USB Device Port */
-        0,      /* Two-Wire Interface */
-        6,      /* Serial Peripheral Interface */
-        5,      /* Serial Synchronous Controller */
-        5,      /* Serial Synchronous Controller */
-        5,      /* Serial Synchronous Controller */
-        0,      /* Timer Counter 0 */
-        0,      /* Timer Counter 1 */
-        0,      /* Timer Counter 2 */
-        0,      /* Timer Counter 3 */
-        0,      /* Timer Counter 4 */
-        0,      /* Timer Counter 5 */
-        3,      /* USB Host port */
-        3,      /* Ethernet MAC */
-        0,      /* Advanced Interrupt Controller */
-        0,      /* Advanced Interrupt Controller */
-        0,      /* Advanced Interrupt Controller */
-        0,      /* Advanced Interrupt Controller */
-        0,      /* Advanced Interrupt Controller */
-        0,      /* Advanced Interrupt Controller */
-        0       /* Advanced Interrupt Controller */
-};
 
-
-static void at91rm9200_mask_irq(unsigned int irq)
+static void at91_aic_mask_irq(unsigned int irq)
 {
         /* Disable interrupt on AIC */
         at91_sys_write(AT91_AIC_IDCR, 1 << irq);
 }
 
-static void at91rm9200_unmask_irq(unsigned int irq)
+static void at91_aic_unmask_irq(unsigned int irq)
 {
         /* Enable interrupt on AIC */
         at91_sys_write(AT91_AIC_IECR, 1 << irq);
 }
 
-static int at91rm9200_irq_type(unsigned irq, unsigned type)
+static int at91_aic_set_type(unsigned irq, unsigned type)
 {
         unsigned int smr, srctype;
 
@@ -122,7 +84,7 @@ static int at91rm9200_irq_type(unsigned irq, unsigned type)
 static u32 wakeups;
 static u32 backups;
 
-static int at91rm9200_irq_set_wake(unsigned irq, unsigned value)
+static int at91_aic_set_wake(unsigned irq, unsigned value)
 {
         if (unlikely(irq >= 32))
                 return -EINVAL;
@@ -149,28 +111,24 @@ void at91_irq_resume(void)
 }
 
 #else
-#define at91rm9200_irq_set_wake NULL
+#define at91_aic_set_wake       NULL
 #endif
 
-static struct irqchip at91rm9200_irq_chip = {
-        .ack            = at91rm9200_mask_irq,
-        .mask           = at91rm9200_mask_irq,
-        .unmask         = at91rm9200_unmask_irq,
-        .set_type       = at91rm9200_irq_type,
-        .set_wake       = at91rm9200_irq_set_wake,
+static struct irqchip at91_aic_chip = {
+        .ack            = at91_aic_mask_irq,
+        .mask           = at91_aic_mask_irq,
+        .unmask         = at91_aic_unmask_irq,
+        .set_type       = at91_aic_set_type,
+        .set_wake       = at91_aic_set_wake,
 };
 
 /*
  * Initialize the AIC interrupt controller.
  */
-void __init at91rm9200_init_irq(unsigned int priority[NR_AIC_IRQS])
+void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
 {
         unsigned int i;
 
-        /* No priority list specified for this board -> use defaults */
-        if (priority == NULL)
-                priority = at91rm9200_default_irq_priority;
-
         /*
          * The IVR is used by macro get_irqnr_and_base to read and verify.
          * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
@@ -178,10 +136,10 @@ void __init at91rm9200_init_irq(unsigned int priority[NR_AIC_IRQS])
         for (i = 0; i < NR_AIC_IRQS; i++) {
                 /* Put irq number in Source Vector Register: */
                 at91_sys_write(AT91_AIC_SVR(i), i);
-                /* Store the Source Mode Register as defined in table above */
+                /* Active Low interrupt, with the specified priority */
                 at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
 
-                set_irq_chip(i, &at91rm9200_irq_chip);
+                set_irq_chip(i, &at91_aic_chip);
                 set_irq_handler(i, do_level_IRQ);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 
diff --git a/arch/arm/mach-pnx4008/core.c b/arch/arm/mach-pnx4008/core.c
index ba91daad64fb..3d73c1e93752 100644
--- a/arch/arm/mach-pnx4008/core.c
+++ b/arch/arm/mach-pnx4008/core.c
@@ -27,7 +27,6 @@
 #include <linux/spi/spi.h>
 
 #include <asm/hardware.h>
-#include <asm/irq.h>
 #include <asm/io.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -36,7 +35,6 @@
 #include <asm/system.h>
 
 #include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 
diff --git a/arch/arm/mach-pnx4008/dma.c b/arch/arm/mach-pnx4008/dma.c
index 981aa9dcdede..ec01574f88ac 100644
--- a/arch/arm/mach-pnx4008/dma.c
+++ b/arch/arm/mach-pnx4008/dma.c
@@ -23,7 +23,6 @@
 #include <linux/clk.h>
 
 #include <asm/system.h>
-#include <asm/irq.h>
 #include <asm/hardware.h>
 #include <asm/dma.h>
 #include <asm/dma-mapping.h>
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c
index 9b0a8e084e99..3a4bcf3d91fa 100644
--- a/arch/arm/mach-pnx4008/irq.c
+++ b/arch/arm/mach-pnx4008/irq.c
@@ -22,8 +22,8 @@
 #include <linux/init.h>
 #include <linux/ioport.h>
 #include <linux/device.h>
+#include <linux/irq.h>
 #include <asm/hardware.h>
-#include <asm/irq.h>
 #include <asm/io.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -96,26 +96,24 @@ void __init pnx4008_init_irq(void)
 {
         unsigned int i;
 
-        /* configure and enable IRQ 0,1,30,31 (cascade interrupts) mask all others */
+        /* configure IRQ's */
+        for (i = 0; i < NR_IRQS; i++) {
+                set_irq_flags(i, IRQF_VALID);
+                set_irq_chip(i, &pnx4008_irq_chip);
+                pnx4008_set_irq_type(i, pnx4008_irq_type[i]);
+        }
+
+        /* configure and enable IRQ 0,1,30,31 (cascade interrupts) */
         pnx4008_set_irq_type(SUB1_IRQ_N, pnx4008_irq_type[SUB1_IRQ_N]);
         pnx4008_set_irq_type(SUB2_IRQ_N, pnx4008_irq_type[SUB2_IRQ_N]);
         pnx4008_set_irq_type(SUB1_FIQ_N, pnx4008_irq_type[SUB1_FIQ_N]);
         pnx4008_set_irq_type(SUB2_FIQ_N, pnx4008_irq_type[SUB2_FIQ_N]);
 
+        /* mask all others */
         __raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) |
                         (1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N),
                 INTC_ER(MAIN_BASE_INT));
         __raw_writel(0, INTC_ER(SIC1_BASE_INT));
         __raw_writel(0, INTC_ER(SIC2_BASE_INT));
-
-        /* configure all other IRQ's */
-        for (i = 0; i < NR_IRQS; i++) {
-                if (i == SUB2_FIQ_N || i == SUB1_FIQ_N ||
-                        i == SUB2_IRQ_N || i == SUB1_IRQ_N)
-                        continue;
-                set_irq_flags(i, IRQF_VALID);
-                set_irq_chip(i, &pnx4008_irq_chip);
-                pnx4008_set_irq_type(i, pnx4008_irq_type[i]);
-        }
 }
 
diff --git a/arch/arm/mach-pnx4008/time.c b/arch/arm/mach-pnx4008/time.c
index 888bf6cfba8a..756228ddd035 100644
--- a/arch/arm/mach-pnx4008/time.c
+++ b/arch/arm/mach-pnx4008/time.c
@@ -20,17 +20,15 @@
 #include <linux/spinlock.h>
 #include <linux/module.h>
 #include <linux/kallsyms.h>
+#include <linux/time.h>
+#include <linux/timex.h>
+#include <linux/irq.h>
 
 #include <asm/system.h>
 #include <asm/hardware.h>
 #include <asm/io.h>
 #include <asm/leds.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
 #include <asm/mach/time.h>
-
-#include <linux/time.h>
-#include <linux/timex.h>
 #include <asm/errno.h>
 
 /*! Note: all timers are UPCOUNTING */
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 7d31d7cc392d..9cecebaa0360 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -405,20 +405,22 @@ static void mpic_unmask_irq(unsigned int irq)
         unsigned int loops = 100000;
         struct mpic *mpic = mpic_from_irq(irq);
         unsigned int src = mpic_irq_to_hw(irq);
+        unsigned long flags;
 
         DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
 
+        spin_lock_irqsave(&mpic_lock, flags);
         mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
                        mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) &
                        ~MPIC_VECPRI_MASK);
-
         /* make sure mask gets to controller before we return to user */
         do {
                 if (!loops--) {
                         printk(KERN_ERR "mpic_enable_irq timeout\n");
                         break;
                 }
-        } while(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK);    
+        } while(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK);
+        spin_unlock_irqrestore(&mpic_lock, flags);
 }
 
 static void mpic_mask_irq(unsigned int irq)
@@ -426,9 +428,11 @@ static void mpic_mask_irq(unsigned int irq)
         unsigned int loops = 100000;
         struct mpic *mpic = mpic_from_irq(irq);
         unsigned int src = mpic_irq_to_hw(irq);
+        unsigned long flags;
 
         DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
 
+        spin_lock_irqsave(&mpic_lock, flags);
         mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
                        mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) |
                        MPIC_VECPRI_MASK);
@@ -440,6 +444,7 @@ static void mpic_mask_irq(unsigned int irq)
                         break;
                 }
         } while(!(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK));
+        spin_unlock_irqrestore(&mpic_lock, flags);
 }
 
 static void mpic_end_irq(unsigned int irq)
@@ -624,9 +629,10 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq,
         struct irq_desc *desc = get_irq_desc(virq);
         struct irq_chip *chip;
         struct mpic *mpic = h->host_data;
-        unsigned int vecpri = MPIC_VECPRI_SENSE_LEVEL |
+        u32 v, vecpri = MPIC_VECPRI_SENSE_LEVEL |
                 MPIC_VECPRI_POLARITY_NEGATIVE;
         int level;
+        unsigned long iflags;
 
         pr_debug("mpic: map virq %d, hwirq 0x%lx, flags: 0x%x\n",
                  virq, hw, flags);
@@ -668,11 +674,21 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq,
         }
 #endif
 
-        /* Reconfigure irq */
-        vecpri |= MPIC_VECPRI_MASK | hw | (8 << MPIC_VECPRI_PRIORITY_SHIFT);
-        mpic_irq_write(hw, MPIC_IRQ_VECTOR_PRI, vecpri);
-
-        pr_debug("mpic: mapping as IRQ\n");
+        /* Reconfigure irq. We must preserve the mask bit as we can be called
+         * while the interrupt is still active (This may change in the future
+         * but for now, it is the case).
+         */
+        spin_lock_irqsave(&mpic_lock, iflags);
+        v = mpic_irq_read(hw, MPIC_IRQ_VECTOR_PRI);
+        vecpri = (v &
+                ~(MPIC_VECPRI_POLARITY_MASK | MPIC_VECPRI_SENSE_MASK)) |
+                vecpri;
+        if (vecpri != v)
+                mpic_irq_write(hw, MPIC_IRQ_VECTOR_PRI, vecpri);
+        spin_unlock_irqrestore(&mpic_lock, iflags);
+
+        pr_debug("mpic: mapping as IRQ, vecpri = 0x%08x (was 0x%08x)\n",
+                 vecpri, v);
 
         set_irq_chip_data(virq, mpic);
         set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);
@@ -904,8 +920,8 @@ void __init mpic_init(struct mpic *mpic)
                 
                 /* do senses munging */
                 if (mpic->senses && i < mpic->senses_count)
-                        vecpri = mpic_flags_to_vecpri(mpic->senses[i],
-                                                      &level);
+                        vecpri |= mpic_flags_to_vecpri(mpic->senses[i],
+                                                       &level);
                 else
                         vecpri |= MPIC_VECPRI_SENSE_LEVEL;
 
@@ -955,14 +971,17 @@ void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
 
 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
 {
+        unsigned long flags;
         u32 v;
 
+        spin_lock_irqsave(&mpic_lock, flags);
         v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
         if (enable)
                 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
         else
                 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
         mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
+        spin_unlock_irqrestore(&mpic_lock, flags);
 }
 
 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)