aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap1/clock.c6
-rw-r--r--arch/arm/mach-omap2/clock34xx_data.c4
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c62
-rw-r--r--arch/arm/mach-omap2/cpuidle34xx.c2
-rw-r--r--arch/arm/mach-omap2/gpmc.c2
-rw-r--r--arch/arm/mach-omap2/id.c41
-rw-r--r--arch/arm/mach-omap2/irq.c18
-rw-r--r--arch/arm/mach-omap2/mux.c27
-rw-r--r--arch/arm/mach-omap2/mux.h24
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c3
-rw-r--r--arch/arm/mach-omap2/pm-debug.c12
-rw-r--r--arch/arm/mach-omap2/pm.h8
-rw-r--r--arch/arm/mach-omap2/pm34xx.c47
-rw-r--r--arch/arm/mach-omap2/prcm.c11
-rw-r--r--arch/arm/mach-omap2/prm.h2
-rw-r--r--arch/arm/mach-omap2/prm44xx.h32
-rw-r--r--arch/arm/mach-omap2/sleep34xx.S13
-rw-r--r--arch/arm/plat-omap/common.c26
-rw-r--r--arch/arm/plat-omap/dma.c2
-rw-r--r--arch/arm/plat-omap/dmtimer.c13
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h1
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h3
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h1
-rw-r--r--arch/sparc/Kconfig5
-rw-r--r--arch/sparc/configs/sparc32_defconfig87
-rw-r--r--arch/sparc/configs/sparc64_defconfig131
-rw-r--r--arch/sparc/include/asm/io_32.h2
-rw-r--r--arch/sparc/include/asm/page_32.h2
-rw-r--r--arch/sparc/include/asm/param.h19
-rw-r--r--arch/sparc/include/asm/timex_32.h1
-rw-r--r--arch/sparc/include/asm/topology_64.h4
-rw-r--r--arch/sparc/include/asm/uaccess_32.h2
-rw-r--r--arch/sparc/include/asm/uaccess_64.h2
-rw-r--r--arch/sparc/kernel/central.c4
-rw-r--r--arch/sparc/kernel/irq_64.c37
-rw-r--r--arch/sparc/kernel/pcic.c103
-rw-r--r--arch/sparc/kernel/perf_event.c627
-rw-r--r--arch/sparc/kernel/sys_sparc_64.c6
-rw-r--r--arch/sparc/kernel/time_32.c116
-rw-r--r--arch/sparc/mm/fault_32.c12
-rw-r--r--arch/sparc/mm/fault_64.c13
41 files changed, 978 insertions, 555 deletions
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 2ba9ab953731..04f1d29cba2c 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -214,8 +214,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate)
214 struct mpu_rate * ptr; 214 struct mpu_rate * ptr;
215 unsigned long dpll1_rate, ref_rate; 215 unsigned long dpll1_rate, ref_rate;
216 216
217 dpll1_rate = clk_get_rate(ck_dpll1_p); 217 dpll1_rate = ck_dpll1_p->rate;
218 ref_rate = clk_get_rate(ck_ref_p); 218 ref_rate = ck_ref_p->rate;
219 219
220 for (ptr = omap1_rate_table; ptr->rate; ptr++) { 220 for (ptr = omap1_rate_table; ptr->rate; ptr++) {
221 if (ptr->xtal != ref_rate) 221 if (ptr->xtal != ref_rate)
@@ -306,7 +306,7 @@ long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
306 long highest_rate; 306 long highest_rate;
307 unsigned long ref_rate; 307 unsigned long ref_rate;
308 308
309 ref_rate = clk_get_rate(ck_ref_p); 309 ref_rate = ck_ref_p->rate;
310 310
311 highest_rate = -EINVAL; 311 highest_rate = -EINVAL;
312 312
diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c
index c6031d74d6f6..74930e3158e3 100644
--- a/arch/arm/mach-omap2/clock34xx_data.c
+++ b/arch/arm/mach-omap2/clock34xx_data.c
@@ -671,7 +671,6 @@ static struct clk dpll4_m3x2_ck = {
671 .name = "dpll4_m3x2_ck", 671 .name = "dpll4_m3x2_ck",
672 .ops = &clkops_omap2_dflt_wait, 672 .ops = &clkops_omap2_dflt_wait,
673 .parent = &dpll4_m3_ck, 673 .parent = &dpll4_m3_ck,
674 .init = &omap2_init_clksel_parent,
675 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 674 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
676 .enable_bit = OMAP3430_PWRDN_TV_SHIFT, 675 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
677 .flags = INVERT_ENABLE, 676 .flags = INVERT_ENABLE,
@@ -811,7 +810,6 @@ static struct clk dpll4_m6x2_ck = {
811 .name = "dpll4_m6x2_ck", 810 .name = "dpll4_m6x2_ck",
812 .ops = &clkops_omap2_dflt_wait, 811 .ops = &clkops_omap2_dflt_wait,
813 .parent = &dpll4_m6_ck, 812 .parent = &dpll4_m6_ck,
814 .init = &omap2_init_clksel_parent,
815 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 813 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
816 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, 814 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
817 .flags = INVERT_ENABLE, 815 .flags = INVERT_ENABLE,
@@ -1047,7 +1045,6 @@ static struct clk iva2_ck = {
1047 .name = "iva2_ck", 1045 .name = "iva2_ck",
1048 .ops = &clkops_omap2_dflt_wait, 1046 .ops = &clkops_omap2_dflt_wait,
1049 .parent = &dpll2_m2_ck, 1047 .parent = &dpll2_m2_ck,
1050 .init = &omap2_init_clksel_parent,
1051 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), 1048 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1052 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, 1049 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1053 .clkdm_name = "iva2_clkdm", 1050 .clkdm_name = "iva2_clkdm",
@@ -1121,7 +1118,6 @@ static struct clk gfx_l3_ck = {
1121 .name = "gfx_l3_ck", 1118 .name = "gfx_l3_ck",
1122 .ops = &clkops_omap2_dflt_wait, 1119 .ops = &clkops_omap2_dflt_wait,
1123 .parent = &l3_ick, 1120 .parent = &l3_ick,
1124 .init = &omap2_init_clksel_parent,
1125 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), 1121 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1126 .enable_bit = OMAP_EN_GFX_SHIFT, 1122 .enable_bit = OMAP_EN_GFX_SHIFT,
1127 .recalc = &followparent_recalc, 1123 .recalc = &followparent_recalc,
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 2210e227d78a..9d882bcb56e3 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -346,37 +346,37 @@ static struct clk aess_fclk = {
346}; 346};
347 347
348static const struct clksel_rate div31_1to31_rates[] = { 348static const struct clksel_rate div31_1to31_rates[] = {
349 { .div = 1, .val = 0, .flags = RATE_IN_4430 }, 349 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
350 { .div = 2, .val = 1, .flags = RATE_IN_4430 }, 350 { .div = 2, .val = 2, .flags = RATE_IN_4430 },
351 { .div = 3, .val = 2, .flags = RATE_IN_4430 }, 351 { .div = 3, .val = 3, .flags = RATE_IN_4430 },
352 { .div = 4, .val = 3, .flags = RATE_IN_4430 }, 352 { .div = 4, .val = 4, .flags = RATE_IN_4430 },
353 { .div = 5, .val = 4, .flags = RATE_IN_4430 }, 353 { .div = 5, .val = 5, .flags = RATE_IN_4430 },
354 { .div = 6, .val = 5, .flags = RATE_IN_4430 }, 354 { .div = 6, .val = 6, .flags = RATE_IN_4430 },
355 { .div = 7, .val = 6, .flags = RATE_IN_4430 }, 355 { .div = 7, .val = 7, .flags = RATE_IN_4430 },
356 { .div = 8, .val = 7, .flags = RATE_IN_4430 }, 356 { .div = 8, .val = 8, .flags = RATE_IN_4430 },
357 { .div = 9, .val = 8, .flags = RATE_IN_4430 }, 357 { .div = 9, .val = 9, .flags = RATE_IN_4430 },
358 { .div = 10, .val = 9, .flags = RATE_IN_4430 }, 358 { .div = 10, .val = 10, .flags = RATE_IN_4430 },
359 { .div = 11, .val = 10, .flags = RATE_IN_4430 }, 359 { .div = 11, .val = 11, .flags = RATE_IN_4430 },
360 { .div = 12, .val = 11, .flags = RATE_IN_4430 }, 360 { .div = 12, .val = 12, .flags = RATE_IN_4430 },
361 { .div = 13, .val = 12, .flags = RATE_IN_4430 }, 361 { .div = 13, .val = 13, .flags = RATE_IN_4430 },
362 { .div = 14, .val = 13, .flags = RATE_IN_4430 }, 362 { .div = 14, .val = 14, .flags = RATE_IN_4430 },
363 { .div = 15, .val = 14, .flags = RATE_IN_4430 }, 363 { .div = 15, .val = 15, .flags = RATE_IN_4430 },
364 { .div = 16, .val = 15, .flags = RATE_IN_4430 }, 364 { .div = 16, .val = 16, .flags = RATE_IN_4430 },
365 { .div = 17, .val = 16, .flags = RATE_IN_4430 }, 365 { .div = 17, .val = 17, .flags = RATE_IN_4430 },
366 { .div = 18, .val = 17, .flags = RATE_IN_4430 }, 366 { .div = 18, .val = 18, .flags = RATE_IN_4430 },
367 { .div = 19, .val = 18, .flags = RATE_IN_4430 }, 367 { .div = 19, .val = 19, .flags = RATE_IN_4430 },
368 { .div = 20, .val = 19, .flags = RATE_IN_4430 }, 368 { .div = 20, .val = 20, .flags = RATE_IN_4430 },
369 { .div = 21, .val = 20, .flags = RATE_IN_4430 }, 369 { .div = 21, .val = 21, .flags = RATE_IN_4430 },
370 { .div = 22, .val = 21, .flags = RATE_IN_4430 }, 370 { .div = 22, .val = 22, .flags = RATE_IN_4430 },
371 { .div = 23, .val = 22, .flags = RATE_IN_4430 }, 371 { .div = 23, .val = 23, .flags = RATE_IN_4430 },
372 { .div = 24, .val = 23, .flags = RATE_IN_4430 }, 372 { .div = 24, .val = 24, .flags = RATE_IN_4430 },
373 { .div = 25, .val = 24, .flags = RATE_IN_4430 }, 373 { .div = 25, .val = 25, .flags = RATE_IN_4430 },
374 { .div = 26, .val = 25, .flags = RATE_IN_4430 }, 374 { .div = 26, .val = 26, .flags = RATE_IN_4430 },
375 { .div = 27, .val = 26, .flags = RATE_IN_4430 }, 375 { .div = 27, .val = 27, .flags = RATE_IN_4430 },
376 { .div = 28, .val = 27, .flags = RATE_IN_4430 }, 376 { .div = 28, .val = 28, .flags = RATE_IN_4430 },
377 { .div = 29, .val = 28, .flags = RATE_IN_4430 }, 377 { .div = 29, .val = 29, .flags = RATE_IN_4430 },
378 { .div = 30, .val = 29, .flags = RATE_IN_4430 }, 378 { .div = 30, .val = 30, .flags = RATE_IN_4430 },
379 { .div = 31, .val = 30, .flags = RATE_IN_4430 }, 379 { .div = 31, .val = 31, .flags = RATE_IN_4430 },
380 { .div = 0 }, 380 { .div = 0 },
381}; 381};
382 382
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index a26d6a08ae3f..12f0cbfc2894 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -137,7 +137,7 @@ return_sleep_time:
137 local_irq_enable(); 137 local_irq_enable();
138 local_fiq_enable(); 138 local_fiq_enable();
139 139
140 return (u32)timespec_to_ns(&ts_idle)/1000; 140 return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;
141} 141}
142 142
143/** 143/**
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index bd8cb5974726..3f1334f62e7a 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -534,6 +534,8 @@ void __init gpmc_init(void)
534 BUG(); 534 BUG();
535 } 535 }
536 536
537 clk_enable(gpmc_l3_clk);
538
537 l = gpmc_read_reg(GPMC_REVISION); 539 l = gpmc_read_reg(GPMC_REVISION);
538 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); 540 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
539 /* Set smart idle mode and automatic L3 clock gating */ 541 /* Set smart idle mode and automatic L3 clock gating */
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index a091b53657b9..3d65c50bd017 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -188,6 +188,8 @@ void __init omap3_check_revision(void)
188 u16 hawkeye; 188 u16 hawkeye;
189 u8 rev; 189 u8 rev;
190 190
191 omap_chip.oc = CHIP_IS_OMAP3430;
192
191 /* 193 /*
192 * We cannot access revision registers on ES1.0. 194 * We cannot access revision registers on ES1.0.
193 * If the processor type is Cortex-A8 and the revision is 0x0 195 * If the processor type is Cortex-A8 and the revision is 0x0
@@ -196,6 +198,7 @@ void __init omap3_check_revision(void)
196 cpuid = read_cpuid(CPUID_ID); 198 cpuid = read_cpuid(CPUID_ID);
197 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { 199 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
198 omap_revision = OMAP3430_REV_ES1_0; 200 omap_revision = OMAP3430_REV_ES1_0;
201 omap_chip.oc |= CHIP_IS_OMAP3430ES1;
199 return; 202 return;
200 } 203 }
201 204
@@ -216,18 +219,28 @@ void __init omap3_check_revision(void)
216 case 0: /* Take care of early samples */ 219 case 0: /* Take care of early samples */
217 case 1: 220 case 1:
218 omap_revision = OMAP3430_REV_ES2_0; 221 omap_revision = OMAP3430_REV_ES2_0;
222 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
219 break; 223 break;
220 case 2: 224 case 2:
221 omap_revision = OMAP3430_REV_ES2_1; 225 omap_revision = OMAP3430_REV_ES2_1;
226 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
222 break; 227 break;
223 case 3: 228 case 3:
224 omap_revision = OMAP3430_REV_ES3_0; 229 omap_revision = OMAP3430_REV_ES3_0;
230 omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
225 break; 231 break;
226 case 4: 232 case 4:
233 omap_revision = OMAP3430_REV_ES3_1;
234 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
235 break;
236 case 7:
227 /* FALLTHROUGH */ 237 /* FALLTHROUGH */
228 default: 238 default:
229 /* Use the latest known revision as default */ 239 /* Use the latest known revision as default */
230 omap_revision = OMAP3430_REV_ES3_1; 240 omap_revision = OMAP3430_REV_ES3_1_2;
241
242 /* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
243 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
231 } 244 }
232 break; 245 break;
233 case 0xb868: 246 case 0xb868:
@@ -235,14 +248,18 @@ void __init omap3_check_revision(void)
235 * 248 *
236 * Set the device to be OMAP3505 here. Actual device 249 * Set the device to be OMAP3505 here. Actual device
237 * is identified later based on the features. 250 * is identified later based on the features.
251 *
252 * REVISIT: AM3505/AM3517 should have their own CHIP_IS
238 */ 253 */
239 omap_revision = OMAP3505_REV(rev); 254 omap_revision = OMAP3505_REV(rev);
255 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
240 break; 256 break;
241 case 0xb891: 257 case 0xb891:
242 /* FALLTHROUGH */ 258 /* FALLTHROUGH */
243 default: 259 default:
244 /* Unknown default to latest silicon rev as default*/ 260 /* Unknown default to latest silicon rev as default*/
245 omap_revision = OMAP3630_REV_ES1_0; 261 omap_revision = OMAP3630_REV_ES1_0;
262 omap_chip.oc |= CHIP_IS_OMAP3630ES1;
246 } 263 }
247} 264}
248 265
@@ -360,6 +377,7 @@ void __init omap2_check_revision(void)
360 omap3_check_revision(); 377 omap3_check_revision();
361 omap3_check_features(); 378 omap3_check_features();
362 omap3_cpuinfo(); 379 omap3_cpuinfo();
380 return;
363 } else if (cpu_is_omap44xx()) { 381 } else if (cpu_is_omap44xx()) {
364 omap4_check_revision(); 382 omap4_check_revision();
365 return; 383 return;
@@ -374,27 +392,14 @@ void __init omap2_check_revision(void)
374 if (cpu_is_omap243x()) { 392 if (cpu_is_omap243x()) {
375 /* Currently only supports 2430ES2.1 and 2430-all */ 393 /* Currently only supports 2430ES2.1 and 2430-all */
376 omap_chip.oc |= CHIP_IS_OMAP2430; 394 omap_chip.oc |= CHIP_IS_OMAP2430;
395 return;
377 } else if (cpu_is_omap242x()) { 396 } else if (cpu_is_omap242x()) {
378 /* Currently only supports 2420ES2.1.1 and 2420-all */ 397 /* Currently only supports 2420ES2.1.1 and 2420-all */
379 omap_chip.oc |= CHIP_IS_OMAP2420; 398 omap_chip.oc |= CHIP_IS_OMAP2420;
380 } else if (cpu_is_omap3505() || cpu_is_omap3517()) { 399 return;
381 omap_chip.oc = CHIP_IS_OMAP3430 | CHIP_IS_OMAP3430ES3_1;
382 } else if (cpu_is_omap343x()) {
383 omap_chip.oc = CHIP_IS_OMAP3430;
384 if (omap_rev() == OMAP3430_REV_ES1_0)
385 omap_chip.oc |= CHIP_IS_OMAP3430ES1;
386 else if (omap_rev() >= OMAP3430_REV_ES2_0 &&
387 omap_rev() <= OMAP3430_REV_ES2_1)
388 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
389 else if (omap_rev() == OMAP3430_REV_ES3_0)
390 omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
391 else if (omap_rev() == OMAP3430_REV_ES3_1)
392 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
393 else if (omap_rev() == OMAP3630_REV_ES1_0)
394 omap_chip.oc |= CHIP_IS_OMAP3630ES1;
395 } else {
396 pr_err("Uninitialized omap_chip, please fix!\n");
397 } 400 }
401
402 pr_err("Uninitialized omap_chip, please fix!\n");
398} 403}
399 404
400/* 405/*
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index e9bc782fa414..27054025da2b 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -274,4 +274,22 @@ void omap_intc_restore_context(void)
274 } 274 }
275 /* MIRs are saved and restore with other PRCM registers */ 275 /* MIRs are saved and restore with other PRCM registers */
276} 276}
277
278void omap3_intc_suspend(void)
279{
280 /* A pending interrupt would prevent OMAP from entering suspend */
281 omap_ack_irq(0);
282}
283
284void omap3_intc_prepare_idle(void)
285{
286 /* Disable autoidle as it can stall interrupt controller */
287 intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
288}
289
290void omap3_intc_resume_idle(void)
291{
292 /* Re-enable autoidle */
293 intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
294}
277#endif /* CONFIG_ARCH_OMAP3 */ 295#endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 459ef23ab8a8..3f59bd12cbbf 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -51,7 +51,7 @@ struct omap_mux_entry {
51static unsigned long mux_phys; 51static unsigned long mux_phys;
52static void __iomem *mux_base; 52static void __iomem *mux_base;
53 53
54static inline u16 omap_mux_read(u16 reg) 54u16 omap_mux_read(u16 reg)
55{ 55{
56 if (cpu_is_omap24xx()) 56 if (cpu_is_omap24xx())
57 return __raw_readb(mux_base + reg); 57 return __raw_readb(mux_base + reg);
@@ -59,7 +59,7 @@ static inline u16 omap_mux_read(u16 reg)
59 return __raw_readw(mux_base + reg); 59 return __raw_readw(mux_base + reg);
60} 60}
61 61
62static inline void omap_mux_write(u16 val, u16 reg) 62void omap_mux_write(u16 val, u16 reg)
63{ 63{
64 if (cpu_is_omap24xx()) 64 if (cpu_is_omap24xx())
65 __raw_writeb(val, mux_base + reg); 65 __raw_writeb(val, mux_base + reg);
@@ -67,6 +67,14 @@ static inline void omap_mux_write(u16 val, u16 reg)
67 __raw_writew(val, mux_base + reg); 67 __raw_writew(val, mux_base + reg);
68} 68}
69 69
70void omap_mux_write_array(struct omap_board_mux *board_mux)
71{
72 while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
73 omap_mux_write(board_mux->value, board_mux->reg_offset);
74 board_mux++;
75 }
76}
77
70#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_OMAP_MUX) 78#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_OMAP_MUX)
71 79
72static struct omap_mux_cfg arch_mux_cfg; 80static struct omap_mux_cfg arch_mux_cfg;
@@ -833,14 +841,6 @@ static void __init omap_mux_set_cmdline_signals(void)
833 kfree(options); 841 kfree(options);
834} 842}
835 843
836static void __init omap_mux_set_board_signals(struct omap_board_mux *board_mux)
837{
838 while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
839 omap_mux_write(board_mux->value, board_mux->reg_offset);
840 board_mux++;
841 }
842}
843
844static int __init omap_mux_copy_names(struct omap_mux *src, 844static int __init omap_mux_copy_names(struct omap_mux *src,
845 struct omap_mux *dst) 845 struct omap_mux *dst)
846{ 846{
@@ -998,12 +998,15 @@ int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
998 omap_mux_package_fixup(package_subset, superset); 998 omap_mux_package_fixup(package_subset, superset);
999 if (package_balls) 999 if (package_balls)
1000 omap_mux_package_init_balls(package_balls, superset); 1000 omap_mux_package_init_balls(package_balls, superset);
1001 omap_mux_set_cmdline_signals();
1002 omap_mux_set_board_signals(board_mux);
1003#endif 1001#endif
1004 1002
1005 omap_mux_init_list(superset); 1003 omap_mux_init_list(superset);
1006 1004
1005#ifdef CONFIG_OMAP_MUX
1006 omap_mux_set_cmdline_signals();
1007 omap_mux_write_array(board_mux);
1008#endif
1009
1007 return 0; 1010 return 0;
1008} 1011}
1009 1012
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index d8b4d5ad2278..f8c2e7a8f063 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -147,6 +147,30 @@ u16 omap_mux_get_gpio(int gpio);
147void omap_mux_set_gpio(u16 val, int gpio); 147void omap_mux_set_gpio(u16 val, int gpio);
148 148
149/** 149/**
150 * omap_mux_read() - read mux register
151 * @mux_offset: Offset of the mux register
152 *
153 */
154u16 omap_mux_read(u16 mux_offset);
155
156/**
157 * omap_mux_write() - write mux register
158 * @val: New mux register value
159 * @mux_offset: Offset of the mux register
160 *
161 * This should be only needed for dynamic remuxing of non-gpio signals.
162 */
163void omap_mux_write(u16 val, u16 mux_offset);
164
165/**
166 * omap_mux_write_array() - write an array of mux registers
167 * @board_mux: Array of mux registers terminated by MAP_MUX_TERMINATOR
168 *
169 * This should be only needed for dynamic remuxing of non-gpio signals.
170 */
171void omap_mux_write_array(struct omap_board_mux *board_mux);
172
173/**
150 * omap3_mux_init() - initialize mux system with board specific set 174 * omap3_mux_init() - initialize mux system with board specific set
151 * @board_mux: Board specific mux table 175 * @board_mux: Board specific mux table
152 * @flags: OMAP package type used for the board 176 * @flags: OMAP package type used for the board
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index d8c8545875b1..478ae585ca39 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -94,7 +94,8 @@ static int _update_sysc_cache(struct omap_hwmod *oh)
94 94
95 oh->_sysc_cache = omap_hwmod_readl(oh, oh->sysconfig->sysc_offs); 95 oh->_sysc_cache = omap_hwmod_readl(oh, oh->sysconfig->sysc_offs);
96 96
97 oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; 97 if (!(oh->sysconfig->sysc_flags & SYSC_NO_CACHE))
98 oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;
98 99
99 return 0; 100 return 0;
100} 101}
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 860b755d2220..a0866268aa41 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -54,8 +54,6 @@ int omap2_pm_debug;
54 regs[reg_count++].val = \ 54 regs[reg_count++].val = \
55 __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off))) 55 __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off)))
56 56
57static int __init pm_dbg_init(void);
58
59void omap2_pm_dump(int mode, int resume, unsigned int us) 57void omap2_pm_dump(int mode, int resume, unsigned int us)
60{ 58{
61 struct reg { 59 struct reg {
@@ -167,6 +165,8 @@ struct dentry *pm_dbg_dir;
167 165
168static int pm_dbg_init_done; 166static int pm_dbg_init_done;
169 167
168static int __init pm_dbg_init(void);
169
170enum { 170enum {
171 DEBUG_FILE_COUNTERS = 0, 171 DEBUG_FILE_COUNTERS = 0,
172 DEBUG_FILE_TIMERS, 172 DEBUG_FILE_TIMERS,
@@ -488,9 +488,11 @@ int pm_dbg_regset_init(int reg_set)
488 488
489static int pwrdm_suspend_get(void *data, u64 *val) 489static int pwrdm_suspend_get(void *data, u64 *val)
490{ 490{
491 *val = omap3_pm_get_suspend_state((struct powerdomain *)data); 491 int ret;
492 ret = omap3_pm_get_suspend_state((struct powerdomain *)data);
493 *val = ret;
492 494
493 if (*val >= 0) 495 if (ret >= 0)
494 return 0; 496 return 0;
495 return *val; 497 return *val;
496} 498}
@@ -604,6 +606,4 @@ static int __init pm_dbg_init(void)
604} 606}
605arch_initcall(pm_dbg_init); 607arch_initcall(pm_dbg_init);
606 608
607#else
608void pm_dbg_update_time(struct powerdomain *pwrdm, int prev) {}
609#endif 609#endif
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 0bf345db7147..7a9c2d004511 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -32,12 +32,16 @@ extern struct omap_dm_timer *gptimer_wakeup;
32#ifdef CONFIG_PM_DEBUG 32#ifdef CONFIG_PM_DEBUG
33extern void omap2_pm_dump(int mode, int resume, unsigned int us); 33extern void omap2_pm_dump(int mode, int resume, unsigned int us);
34extern int omap2_pm_debug; 34extern int omap2_pm_debug;
35#else
36#define omap2_pm_dump(mode, resume, us) do {} while (0);
37#define omap2_pm_debug 0
38#endif
39
40#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
35extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev); 41extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
36extern int pm_dbg_regset_save(int reg_set); 42extern int pm_dbg_regset_save(int reg_set);
37extern int pm_dbg_regset_init(int reg_set); 43extern int pm_dbg_regset_init(int reg_set);
38#else 44#else
39#define omap2_pm_dump(mode, resume, us) do {} while (0);
40#define omap2_pm_debug 0
41#define pm_dbg_update_time(pwrdm, prev) do {} while (0); 45#define pm_dbg_update_time(pwrdm, prev) do {} while (0);
42#define pm_dbg_regset_save(reg_set) do {} while (0); 46#define pm_dbg_regset_save(reg_set) do {} while (0);
43#define pm_dbg_regset_init(reg_set) do {} while (0); 47#define pm_dbg_regset_init(reg_set) do {} while (0);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index c6cc809afb79..910a7acf542d 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -26,6 +26,7 @@
26#include <linux/err.h> 26#include <linux/err.h>
27#include <linux/gpio.h> 27#include <linux/gpio.h>
28#include <linux/clk.h> 28#include <linux/clk.h>
29#include <linux/delay.h>
29 30
30#include <plat/sram.h> 31#include <plat/sram.h>
31#include <plat/clockdomain.h> 32#include <plat/clockdomain.h>
@@ -126,7 +127,15 @@ static void omap3_core_save_context(void)
126 /* wait for the save to complete */ 127 /* wait for the save to complete */
127 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) 128 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
128 & PADCONF_SAVE_DONE)) 129 & PADCONF_SAVE_DONE))
129 ; 130 udelay(1);
131
132 /*
133 * Force write last pad into memory, as this can fail in some
134 * cases according to erratas 1.157, 1.185
135 */
136 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
137 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
138
130 /* Save the Interrupt controller context */ 139 /* Save the Interrupt controller context */
131 omap_intc_save_context(); 140 omap_intc_save_context();
132 /* Save the GPMC context */ 141 /* Save the GPMC context */
@@ -392,6 +401,7 @@ void omap_sram_idle(void)
392 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); 401 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
393 omap3_enable_io_chain(); 402 omap3_enable_io_chain();
394 } 403 }
404 omap3_intc_prepare_idle();
395 405
396 /* 406 /*
397 * On EMU/HS devices ROM code restores a SRDC value 407 * On EMU/HS devices ROM code restores a SRDC value
@@ -438,6 +448,7 @@ void omap_sram_idle(void)
438 OMAP3430_GR_MOD, 448 OMAP3430_GR_MOD,
439 OMAP3_PRM_VOLTCTRL_OFFSET); 449 OMAP3_PRM_VOLTCTRL_OFFSET);
440 } 450 }
451 omap3_intc_resume_idle();
441 452
442 /* PER */ 453 /* PER */
443 if (per_next_state < PWRDM_POWER_ON) { 454 if (per_next_state < PWRDM_POWER_ON) {
@@ -578,6 +589,8 @@ static int omap3_pm_suspend(void)
578 } 589 }
579 590
580 omap_uart_prepare_suspend(); 591 omap_uart_prepare_suspend();
592 omap3_intc_suspend();
593
581 omap_sram_idle(); 594 omap_sram_idle();
582 595
583restore: 596restore:
@@ -835,6 +848,8 @@ static void __init prcm_setup_regs(void)
835 CM_AUTOIDLE); 848 CM_AUTOIDLE);
836 } 849 }
837 850
851 omap_ctrl_writel(OMAP3430_AUTOIDLE, OMAP2_CONTROL_SYSCONFIG);
852
838 /* 853 /*
839 * Set all plls to autoidle. This is needed until autoidle is 854 * Set all plls to autoidle. This is needed until autoidle is
840 * enabled by clockfw 855 * enabled by clockfw
@@ -875,15 +890,23 @@ static void __init prcm_setup_regs(void)
875 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN, 890 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
876 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 891 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
877 892
893 /* Enable PM_WKEN to support DSS LPR */
894 prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS,
895 OMAP3430_DSS_MOD, PM_WKEN);
896
878 /* Enable wakeups in PER */ 897 /* Enable wakeups in PER */
879 prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 | 898 prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |
880 OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 | 899 OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 |
881 OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3, 900 OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3 |
901 OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 |
902 OMAP3430_EN_MCBSP4,
882 OMAP3430_PER_MOD, PM_WKEN); 903 OMAP3430_PER_MOD, PM_WKEN);
883 /* and allow them to wake up MPU */ 904 /* and allow them to wake up MPU */
884 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 | 905 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 |
885 OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 | 906 OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 |
886 OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3, 907 OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3 |
908 OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 |
909 OMAP3430_EN_MCBSP4,
887 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 910 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
888 911
889 /* Don't attach IVA interrupts */ 912 /* Don't attach IVA interrupts */
@@ -904,24 +927,6 @@ static void __init prcm_setup_regs(void)
904 /* Clear any pending PRCM interrupts */ 927 /* Clear any pending PRCM interrupts */
905 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 928 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
906 929
907 /* Don't attach IVA interrupts */
908 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
909 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
910 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
911 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
912
913 /* Clear any pending 'reset' flags */
914 prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
915 prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
916 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
917 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
918 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
919 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
920 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
921
922 /* Clear any pending PRCM interrupts */
923 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
924
925 omap3_iva_idle(); 930 omap3_iva_idle();
926 omap3_d2d_idle(); 931 omap3_d2d_idle();
927} 932}
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 3ea8177ffb25..cf466ea1dffc 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -44,7 +44,6 @@ struct omap3_prcm_regs {
44 u32 iva2_cm_clksel2; 44 u32 iva2_cm_clksel2;
45 u32 cm_sysconfig; 45 u32 cm_sysconfig;
46 u32 sgx_cm_clksel; 46 u32 sgx_cm_clksel;
47 u32 wkup_cm_clksel;
48 u32 dss_cm_clksel; 47 u32 dss_cm_clksel;
49 u32 cam_cm_clksel; 48 u32 cam_cm_clksel;
50 u32 per_cm_clksel; 49 u32 per_cm_clksel;
@@ -53,7 +52,6 @@ struct omap3_prcm_regs {
53 u32 pll_cm_autoidle2; 52 u32 pll_cm_autoidle2;
54 u32 pll_cm_clksel4; 53 u32 pll_cm_clksel4;
55 u32 pll_cm_clksel5; 54 u32 pll_cm_clksel5;
56 u32 pll_cm_clken;
57 u32 pll_cm_clken2; 55 u32 pll_cm_clken2;
58 u32 cm_polctrl; 56 u32 cm_polctrl;
59 u32 iva2_cm_fclken; 57 u32 iva2_cm_fclken;
@@ -77,7 +75,6 @@ struct omap3_prcm_regs {
77 u32 usbhost_cm_iclken; 75 u32 usbhost_cm_iclken;
78 u32 iva2_cm_autiidle2; 76 u32 iva2_cm_autiidle2;
79 u32 mpu_cm_autoidle2; 77 u32 mpu_cm_autoidle2;
80 u32 pll_cm_autoidle;
81 u32 iva2_cm_clkstctrl; 78 u32 iva2_cm_clkstctrl;
82 u32 mpu_cm_clkstctrl; 79 u32 mpu_cm_clkstctrl;
83 u32 core_cm_clkstctrl; 80 u32 core_cm_clkstctrl;
@@ -274,7 +271,6 @@ void omap3_prcm_save_context(void)
274 prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG); 271 prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
275 prcm_context.sgx_cm_clksel = 272 prcm_context.sgx_cm_clksel =
276 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL); 273 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
277 prcm_context.wkup_cm_clksel = cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
278 prcm_context.dss_cm_clksel = 274 prcm_context.dss_cm_clksel =
279 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL); 275 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
280 prcm_context.cam_cm_clksel = 276 prcm_context.cam_cm_clksel =
@@ -291,8 +287,6 @@ void omap3_prcm_save_context(void)
291 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4); 287 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
292 prcm_context.pll_cm_clksel5 = 288 prcm_context.pll_cm_clksel5 =
293 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); 289 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
294 prcm_context.pll_cm_clken =
295 cm_read_mod_reg(PLL_MOD, CM_CLKEN);
296 prcm_context.pll_cm_clken2 = 290 prcm_context.pll_cm_clken2 =
297 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); 291 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
298 prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL); 292 prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
@@ -338,8 +332,6 @@ void omap3_prcm_save_context(void)
338 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2); 332 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
339 prcm_context.mpu_cm_autoidle2 = 333 prcm_context.mpu_cm_autoidle2 =
340 cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); 334 cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
341 prcm_context.pll_cm_autoidle =
342 cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
343 prcm_context.iva2_cm_clkstctrl = 335 prcm_context.iva2_cm_clkstctrl =
344 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL); 336 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL);
345 prcm_context.mpu_cm_clkstctrl = 337 prcm_context.mpu_cm_clkstctrl =
@@ -431,7 +423,6 @@ void omap3_prcm_restore_context(void)
431 __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG); 423 __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
432 cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD, 424 cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
433 CM_CLKSEL); 425 CM_CLKSEL);
434 cm_write_mod_reg(prcm_context.wkup_cm_clksel, WKUP_MOD, CM_CLKSEL);
435 cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD, 426 cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
436 CM_CLKSEL); 427 CM_CLKSEL);
437 cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD, 428 cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
@@ -448,7 +439,6 @@ void omap3_prcm_restore_context(void)
448 OMAP3430ES2_CM_CLKSEL4); 439 OMAP3430ES2_CM_CLKSEL4);
449 cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD, 440 cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
450 OMAP3430ES2_CM_CLKSEL5); 441 OMAP3430ES2_CM_CLKSEL5);
451 cm_write_mod_reg(prcm_context.pll_cm_clken, PLL_MOD, CM_CLKEN);
452 cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD, 442 cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
453 OMAP3430ES2_CM_CLKEN2); 443 OMAP3430ES2_CM_CLKEN2);
454 __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL); 444 __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
@@ -487,7 +477,6 @@ void omap3_prcm_restore_context(void)
487 cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD, 477 cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
488 CM_AUTOIDLE2); 478 CM_AUTOIDLE2);
489 cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2); 479 cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
490 cm_write_mod_reg(prcm_context.pll_cm_autoidle, PLL_MOD, CM_AUTOIDLE);
491 cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, 480 cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
492 CM_CLKSTCTRL); 481 CM_CLKSTCTRL);
493 cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL); 482 cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL);
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index ea050ce188a7..40f006285163 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -24,6 +24,8 @@
24 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) 24 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
25#define OMAP44XX_PRM_REGADDR(module, reg) \ 25#define OMAP44XX_PRM_REGADDR(module, reg) \
26 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg)) 26 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
27#define OMAP44XX_CHIRONSS_REGADDR(module, reg) \
28 OMAP2_L4_IO_ADDRESS(OMAP4430_CHIRONSS_BASE + (module) + (reg))
27 29
28#include "prm44xx.h" 30#include "prm44xx.h"
29 31
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 89be97f0589d..adb2558bb121 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -386,26 +386,26 @@
386 386
387 387
388/* CHIRON_PRCM.CHIRONSS_OCP_SOCKET_PRCM register offsets */ 388/* CHIRON_PRCM.CHIRONSS_OCP_SOCKET_PRCM register offsets */
389#define OMAP4430_REVISION_PRCM OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000) 389#define OMAP4430_REVISION_PRCM OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000)
390 390
391/* CHIRON_PRCM.CHIRONSS_DEVICE_PRM register offsets */ 391/* CHIRON_PRCM.CHIRONSS_DEVICE_PRM register offsets */
392#define OMAP4430_CHIRON_PRCM_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000) 392#define OMAP4430_CHIRON_PRCM_PRM_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000)
393 393
394/* CHIRON_PRCM.CHIRONSS_CPU0 register offsets */ 394/* CHIRON_PRCM.CHIRONSS_CPU0 register offsets */
395#define OMAP4430_PM_PDA_CPU0_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000) 395#define OMAP4430_PM_PDA_CPU0_PWRSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000)
396#define OMAP4430_PM_PDA_CPU0_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004) 396#define OMAP4430_PM_PDA_CPU0_PWRSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004)
397#define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008) 397#define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008)
398#define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c) 398#define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c)
399#define OMAP4430_RM_PDA_CPU0_CPU0_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010) 399#define OMAP4430_RM_PDA_CPU0_CPU0_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010)
400#define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014) 400#define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014)
401#define OMAP4430_CM_PDA_CPU0_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018) 401#define OMAP4430_CM_PDA_CPU0_CLKSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018)
402 402
403/* CHIRON_PRCM.CHIRONSS_CPU1 register offsets */ 403/* CHIRON_PRCM.CHIRONSS_CPU1 register offsets */
404#define OMAP4430_PM_PDA_CPU1_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000) 404#define OMAP4430_PM_PDA_CPU1_PWRSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000)
405#define OMAP4430_PM_PDA_CPU1_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004) 405#define OMAP4430_PM_PDA_CPU1_PWRSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004)
406#define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008) 406#define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008)
407#define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c) 407#define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c)
408#define OMAP4430_RM_PDA_CPU1_CPU1_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010) 408#define OMAP4430_RM_PDA_CPU1_CPU1_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010)
409#define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014) 409#define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014)
410#define OMAP4430_CM_PDA_CPU1_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018) 410#define OMAP4430_CM_PDA_CPU1_CLKSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018)
411#endif 411#endif
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 15268f8b61de..c3626ea48143 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -245,7 +245,8 @@ restore:
245 mov r1, #0 @ set task id for ROM code in r1 245 mov r1, #0 @ set task id for ROM code in r1
246 mov r2, #4 @ set some flags in r2, r6 246 mov r2, #4 @ set some flags in r2, r6
247 mov r6, #0xff 247 mov r6, #0xff
248 adr r3, write_aux_control_params @ r3 points to parameters 248 ldr r4, scratchpad_base
249 ldr r3, [r4, #0xBC] @ r3 points to parameters
249 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 250 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
250 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 251 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
251 .word 0xE1600071 @ call SMI monitor (smi #1) 252 .word 0xE1600071 @ call SMI monitor (smi #1)
@@ -253,14 +254,14 @@ restore:
253 b logic_l1_restore 254 b logic_l1_restore
254l2_inv_api_params: 255l2_inv_api_params:
255 .word 0x1, 0x00 256 .word 0x1, 0x00
256write_aux_control_params:
257 .word 0x1, 0x72
258l2_inv_gp: 257l2_inv_gp:
259 /* Execute smi to invalidate L2 cache */ 258 /* Execute smi to invalidate L2 cache */
260 mov r12, #0x1 @ set up to invalide L2 259 mov r12, #0x1 @ set up to invalide L2
261smi: .word 0xE1600070 @ Call SMI monitor (smieq) 260smi: .word 0xE1600070 @ Call SMI monitor (smieq)
262 /* Write to Aux control register to set some bits */ 261 /* Write to Aux control register to set some bits */
263 mov r0, #0x72 262 ldr r4, scratchpad_base
263 ldr r3, [r4,#0xBC]
264 ldr r0, [r3,#4]
264 mov r12, #0x3 265 mov r12, #0x3
265 .word 0xE1600070 @ Call SMI monitor (smieq) 266 .word 0xE1600070 @ Call SMI monitor (smieq)
266logic_l1_restore: 267logic_l1_restore:
@@ -271,6 +272,7 @@ logic_l1_restore:
271 272
272 ldr r4, scratchpad_base 273 ldr r4, scratchpad_base
273 ldr r3, [r4,#0xBC] 274 ldr r3, [r4,#0xBC]
275 adds r3, r3, #8
274 ldmia r3!, {r4-r6} 276 ldmia r3!, {r4-r6}
275 mov sp, r4 277 mov sp, r4
276 msr spsr_cxsf, r5 278 msr spsr_cxsf, r5
@@ -387,6 +389,9 @@ usettbr0:
387save_context_wfi: 389save_context_wfi:
388 /*b save_context_wfi*/ @ enable to debug save code 390 /*b save_context_wfi*/ @ enable to debug save code
389 mov r8, r0 /* Store SDRAM address in r8 */ 391 mov r8, r0 /* Store SDRAM address in r8 */
392 mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
393 mov r4, #0x1 @ Number of parameters for restore call
394 stmia r8!, {r4-r5}
390 /* Check what that target sleep state is:stored in r1*/ 395 /* Check what that target sleep state is:stored in r1*/
391 /* 1 - Only L1 and logic lost */ 396 /* 1 - Only L1 and logic lost */
392 /* 2 - Only L2 lost */ 397 /* 2 - Only L2 lost */
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index bf1eaf3a27d4..dddc0273bc8b 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -172,6 +172,32 @@ unsigned long long sched_clock(void)
172 clocksource_32k.mult, clocksource_32k.shift); 172 clocksource_32k.mult, clocksource_32k.shift);
173} 173}
174 174
175/**
176 * read_persistent_clock - Return time from a persistent clock.
177 *
178 * Reads the time from a source which isn't disabled during PM, the
179 * 32k sync timer. Convert the cycles elapsed since last read into
180 * nsecs and adds to a monotonically increasing timespec.
181 */
182static struct timespec persistent_ts;
183static cycles_t cycles, last_cycles;
184void read_persistent_clock(struct timespec *ts)
185{
186 unsigned long long nsecs;
187 cycles_t delta;
188 struct timespec *tsp = &persistent_ts;
189
190 last_cycles = cycles;
191 cycles = clocksource_32k.read(&clocksource_32k);
192 delta = cycles - last_cycles;
193
194 nsecs = clocksource_cyc2ns(delta,
195 clocksource_32k.mult, clocksource_32k.shift);
196
197 timespec_add_ns(tsp, nsecs);
198 *ts = *tsp;
199}
200
175static int __init omap_init_clocksource_32k(void) 201static int __init omap_init_clocksource_32k(void)
176{ 202{
177 static char err[] __initdata = KERN_ERR 203 static char err[] __initdata = KERN_ERR
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 09d82b3c66ce..728c64204184 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1183,7 +1183,7 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue)
1183 } 1183 }
1184 1184
1185 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) || 1185 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1186 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) { 1186 (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1187 printk(KERN_ERR "omap_dma: You need to stop the DMA channels " 1187 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1188 "before unlinking\n"); 1188 "before unlinking\n");
1189 dump_stack(); 1189 dump_stack();
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 64f407ee0f4e..08ccf8922520 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -551,6 +551,19 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer)
551 if (l & OMAP_TIMER_CTRL_ST) { 551 if (l & OMAP_TIMER_CTRL_ST) {
552 l &= ~0x1; 552 l &= ~0x1;
553 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 553 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
554#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
555 defined(CONFIG_ARCH_OMAP4)
556 /* Readback to make sure write has completed */
557 omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
558 /*
559 * Wait for functional clock period x 3.5 to make sure that
560 * timer is stopped
561 */
562 udelay(3500000 / clk_get_rate(timer->fclk) + 1);
563 /* Ack possibly pending interrupt */
564 omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
565 OMAP_TIMER_INT_OVERFLOW);
566#endif
554 } 567 }
555} 568}
556EXPORT_SYMBOL_GPL(omap_dm_timer_stop); 569EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 9a028bdebb06..a162f585b1e3 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -434,6 +434,7 @@ IS_OMAP_TYPE(3517, 0x3517)
434#define OMAP3430_REV_ES2_1 0x34302034 434#define OMAP3430_REV_ES2_1 0x34302034
435#define OMAP3430_REV_ES3_0 0x34303034 435#define OMAP3430_REV_ES3_0 0x34303034
436#define OMAP3430_REV_ES3_1 0x34304034 436#define OMAP3430_REV_ES3_1 0x34304034
437#define OMAP3430_REV_ES3_1_2 0x34305034
437 438
438#define OMAP3630_REV_ES1_0 0x36300034 439#define OMAP3630_REV_ES1_0 0x36300034
439 440
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 97d6c50c3dcb..c0ab7c80f72e 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -499,6 +499,9 @@ extern void omap_init_irq(void);
499extern int omap_irq_pending(void); 499extern int omap_irq_pending(void);
500void omap_intc_save_context(void); 500void omap_intc_save_context(void);
501void omap_intc_restore_context(void); 501void omap_intc_restore_context(void);
502void omap3_intc_suspend(void);
503void omap3_intc_prepare_idle(void);
504void omap3_intc_resume_idle(void);
502#endif 505#endif
503 506
504#include <mach/hardware.h> 507#include <mach/hardware.h>
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 007935a921ea..33933256a226 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -227,6 +227,7 @@ struct omap_hwmod_ocp_if {
227#define SYSC_HAS_SIDLEMODE (1 << 5) 227#define SYSC_HAS_SIDLEMODE (1 << 5)
228#define SYSC_HAS_MIDLEMODE (1 << 6) 228#define SYSC_HAS_MIDLEMODE (1 << 6)
229#define SYSS_MISSING (1 << 7) 229#define SYSS_MISSING (1 << 7)
230#define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */
230 231
231/* omap_hwmod_sysconfig.clockact flags */ 232/* omap_hwmod_sysconfig.clockact flags */
232#define CLOCKACT_TEST_BOTH 0x0 233#define CLOCKACT_TEST_BOTH 0x0
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 108197ac0d56..4097f6a10860 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -64,8 +64,11 @@ config BITS
64 default 64 if SPARC64 64 default 64 if SPARC64
65 65
66config GENERIC_TIME 66config GENERIC_TIME
67 def_bool y
68
69config ARCH_USES_GETTIMEOFFSET
67 bool 70 bool
68 default y if SPARC64 71 default y if SPARC32
69 72
70config GENERIC_CMOS_UPDATE 73config GENERIC_CMOS_UPDATE
71 bool 74 bool
diff --git a/arch/sparc/configs/sparc32_defconfig b/arch/sparc/configs/sparc32_defconfig
index 983d59824a28..99a1f191497b 100644
--- a/arch/sparc/configs/sparc32_defconfig
+++ b/arch/sparc/configs/sparc32_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.31 3# Linux kernel version: 2.6.33-rc2
4# Wed Sep 16 00:03:43 2009 4# Mon Jan 11 23:20:31 2010
5# 5#
6# CONFIG_64BIT is not set 6# CONFIG_64BIT is not set
7CONFIG_SPARC=y 7CONFIG_SPARC=y
@@ -41,6 +41,7 @@ CONFIG_POSIX_MQUEUE_SYSCTL=y
41# 41#
42CONFIG_TREE_RCU=y 42CONFIG_TREE_RCU=y
43# CONFIG_TREE_PREEMPT_RCU is not set 43# CONFIG_TREE_PREEMPT_RCU is not set
44# CONFIG_TINY_RCU is not set
44# CONFIG_RCU_TRACE is not set 45# CONFIG_RCU_TRACE is not set
45CONFIG_RCU_FANOUT=32 46CONFIG_RCU_FANOUT=32
46# CONFIG_RCU_FANOUT_EXACT is not set 47# CONFIG_RCU_FANOUT_EXACT is not set
@@ -88,21 +89,21 @@ CONFIG_TIMERFD=y
88CONFIG_EVENTFD=y 89CONFIG_EVENTFD=y
89CONFIG_SHMEM=y 90CONFIG_SHMEM=y
90CONFIG_AIO=y 91CONFIG_AIO=y
91CONFIG_HAVE_PERF_COUNTERS=y 92CONFIG_HAVE_PERF_EVENTS=y
93CONFIG_PERF_USE_VMALLOC=y
92 94
93# 95#
94# Performance Counters 96# Kernel Performance Events And Counters
95# 97#
98# CONFIG_PERF_EVENTS is not set
96# CONFIG_PERF_COUNTERS is not set 99# CONFIG_PERF_COUNTERS is not set
97CONFIG_VM_EVENT_COUNTERS=y 100CONFIG_VM_EVENT_COUNTERS=y
98CONFIG_PCI_QUIRKS=y 101CONFIG_PCI_QUIRKS=y
99# CONFIG_STRIP_ASM_SYMS is not set
100CONFIG_COMPAT_BRK=y 102CONFIG_COMPAT_BRK=y
101CONFIG_SLAB=y 103CONFIG_SLAB=y
102# CONFIG_SLUB is not set 104# CONFIG_SLUB is not set
103# CONFIG_SLOB is not set 105# CONFIG_SLOB is not set
104# CONFIG_PROFILING is not set 106# CONFIG_PROFILING is not set
105# CONFIG_MARKERS is not set
106CONFIG_HAVE_OPROFILE=y 107CONFIG_HAVE_OPROFILE=y
107CONFIG_HAVE_ARCH_TRACEHOOK=y 108CONFIG_HAVE_ARCH_TRACEHOOK=y
108CONFIG_HAVE_DMA_ATTRS=y 109CONFIG_HAVE_DMA_ATTRS=y
@@ -131,14 +132,41 @@ CONFIG_LBDAF=y
131# IO Schedulers 132# IO Schedulers
132# 133#
133CONFIG_IOSCHED_NOOP=y 134CONFIG_IOSCHED_NOOP=y
134CONFIG_IOSCHED_AS=y
135CONFIG_IOSCHED_DEADLINE=y 135CONFIG_IOSCHED_DEADLINE=y
136CONFIG_IOSCHED_CFQ=y 136CONFIG_IOSCHED_CFQ=y
137# CONFIG_DEFAULT_AS is not set
138# CONFIG_DEFAULT_DEADLINE is not set 137# CONFIG_DEFAULT_DEADLINE is not set
139CONFIG_DEFAULT_CFQ=y 138CONFIG_DEFAULT_CFQ=y
140# CONFIG_DEFAULT_NOOP is not set 139# CONFIG_DEFAULT_NOOP is not set
141CONFIG_DEFAULT_IOSCHED="cfq" 140CONFIG_DEFAULT_IOSCHED="cfq"
141# CONFIG_INLINE_SPIN_TRYLOCK is not set
142# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
143# CONFIG_INLINE_SPIN_LOCK is not set
144# CONFIG_INLINE_SPIN_LOCK_BH is not set
145# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
146# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
147CONFIG_INLINE_SPIN_UNLOCK=y
148# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
149CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
150# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
151# CONFIG_INLINE_READ_TRYLOCK is not set
152# CONFIG_INLINE_READ_LOCK is not set
153# CONFIG_INLINE_READ_LOCK_BH is not set
154# CONFIG_INLINE_READ_LOCK_IRQ is not set
155# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
156CONFIG_INLINE_READ_UNLOCK=y
157# CONFIG_INLINE_READ_UNLOCK_BH is not set
158CONFIG_INLINE_READ_UNLOCK_IRQ=y
159# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
160# CONFIG_INLINE_WRITE_TRYLOCK is not set
161# CONFIG_INLINE_WRITE_LOCK is not set
162# CONFIG_INLINE_WRITE_LOCK_BH is not set
163# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
164# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
165CONFIG_INLINE_WRITE_UNLOCK=y
166# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
167CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
168# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
169# CONFIG_MUTEX_SPIN_ON_OWNER is not set
142# CONFIG_FREEZER is not set 170# CONFIG_FREEZER is not set
143 171
144# 172#
@@ -168,8 +196,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
168# CONFIG_PHYS_ADDR_T_64BIT is not set 196# CONFIG_PHYS_ADDR_T_64BIT is not set
169CONFIG_ZONE_DMA_FLAG=1 197CONFIG_ZONE_DMA_FLAG=1
170CONFIG_BOUNCE=y 198CONFIG_BOUNCE=y
171CONFIG_HAVE_MLOCK=y 199# CONFIG_KSM is not set
172CONFIG_HAVE_MLOCKED_PAGE_BIT=y
173CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 200CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
174CONFIG_SUN_PM=y 201CONFIG_SUN_PM=y
175# CONFIG_SPARC_LED is not set 202# CONFIG_SPARC_LED is not set
@@ -257,6 +284,7 @@ CONFIG_INET6_XFRM_MODE_TUNNEL=m
257CONFIG_INET6_XFRM_MODE_BEET=m 284CONFIG_INET6_XFRM_MODE_BEET=m
258# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set 285# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
259CONFIG_IPV6_SIT=m 286CONFIG_IPV6_SIT=m
287# CONFIG_IPV6_SIT_6RD is not set
260CONFIG_IPV6_NDISC_NODETYPE=y 288CONFIG_IPV6_NDISC_NODETYPE=y
261CONFIG_IPV6_TUNNEL=m 289CONFIG_IPV6_TUNNEL=m
262# CONFIG_IPV6_MULTIPLE_TABLES is not set 290# CONFIG_IPV6_MULTIPLE_TABLES is not set
@@ -295,9 +323,6 @@ CONFIG_NET_PKTGEN=m
295# CONFIG_AF_RXRPC is not set 323# CONFIG_AF_RXRPC is not set
296CONFIG_WIRELESS=y 324CONFIG_WIRELESS=y
297# CONFIG_CFG80211 is not set 325# CONFIG_CFG80211 is not set
298CONFIG_CFG80211_DEFAULT_PS_VALUE=0
299CONFIG_WIRELESS_OLD_REGULATORY=y
300# CONFIG_WIRELESS_EXT is not set
301# CONFIG_LIB80211 is not set 326# CONFIG_LIB80211 is not set
302 327
303# 328#
@@ -335,6 +360,10 @@ CONFIG_BLK_DEV=y
335# CONFIG_BLK_DEV_COW_COMMON is not set 360# CONFIG_BLK_DEV_COW_COMMON is not set
336CONFIG_BLK_DEV_LOOP=m 361CONFIG_BLK_DEV_LOOP=m
337CONFIG_BLK_DEV_CRYPTOLOOP=m 362CONFIG_BLK_DEV_CRYPTOLOOP=m
363
364#
365# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
366#
338# CONFIG_BLK_DEV_NBD is not set 367# CONFIG_BLK_DEV_NBD is not set
339# CONFIG_BLK_DEV_SX8 is not set 368# CONFIG_BLK_DEV_SX8 is not set
340CONFIG_BLK_DEV_RAM=y 369CONFIG_BLK_DEV_RAM=y
@@ -398,8 +427,11 @@ CONFIG_SCSI_LOWLEVEL=y
398# CONFIG_ISCSI_TCP is not set 427# CONFIG_ISCSI_TCP is not set
399# CONFIG_SCSI_CXGB3_ISCSI is not set 428# CONFIG_SCSI_CXGB3_ISCSI is not set
400# CONFIG_SCSI_BNX2_ISCSI is not set 429# CONFIG_SCSI_BNX2_ISCSI is not set
430# CONFIG_BE2ISCSI is not set
401# CONFIG_BLK_DEV_3W_XXXX_RAID is not set 431# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
432# CONFIG_SCSI_HPSA is not set
402# CONFIG_SCSI_3W_9XXX is not set 433# CONFIG_SCSI_3W_9XXX is not set
434# CONFIG_SCSI_3W_SAS is not set
403# CONFIG_SCSI_ACARD is not set 435# CONFIG_SCSI_ACARD is not set
404# CONFIG_SCSI_AACRAID is not set 436# CONFIG_SCSI_AACRAID is not set
405# CONFIG_SCSI_AIC7XXX is not set 437# CONFIG_SCSI_AIC7XXX is not set
@@ -434,7 +466,9 @@ CONFIG_SCSI_QLOGICPTI=m
434# CONFIG_SCSI_DEBUG is not set 466# CONFIG_SCSI_DEBUG is not set
435CONFIG_SCSI_SUNESP=y 467CONFIG_SCSI_SUNESP=y
436# CONFIG_SCSI_PMCRAID is not set 468# CONFIG_SCSI_PMCRAID is not set
469# CONFIG_SCSI_PM8001 is not set
437# CONFIG_SCSI_SRP is not set 470# CONFIG_SCSI_SRP is not set
471# CONFIG_SCSI_BFA_FC is not set
438# CONFIG_SCSI_DH is not set 472# CONFIG_SCSI_DH is not set
439# CONFIG_SCSI_OSD_INITIATOR is not set 473# CONFIG_SCSI_OSD_INITIATOR is not set
440# CONFIG_ATA is not set 474# CONFIG_ATA is not set
@@ -450,7 +484,7 @@ CONFIG_SCSI_SUNESP=y
450# 484#
451 485
452# 486#
453# See the help texts for more information. 487# The newer stack is recommended.
454# 488#
455# CONFIG_FIREWIRE is not set 489# CONFIG_FIREWIRE is not set
456# CONFIG_IEEE1394 is not set 490# CONFIG_IEEE1394 is not set
@@ -487,6 +521,7 @@ CONFIG_SUNQE=m
487# CONFIG_NET_PCI is not set 521# CONFIG_NET_PCI is not set
488# CONFIG_B44 is not set 522# CONFIG_B44 is not set
489# CONFIG_KS8842 is not set 523# CONFIG_KS8842 is not set
524# CONFIG_KS8851_MLL is not set
490# CONFIG_ATL2 is not set 525# CONFIG_ATL2 is not set
491CONFIG_NETDEV_1000=y 526CONFIG_NETDEV_1000=y
492# CONFIG_ACENIC is not set 527# CONFIG_ACENIC is not set
@@ -546,6 +581,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
546# CONFIG_NETCONSOLE is not set 581# CONFIG_NETCONSOLE is not set
547# CONFIG_NETPOLL is not set 582# CONFIG_NETPOLL is not set
548# CONFIG_NET_POLL_CONTROLLER is not set 583# CONFIG_NET_POLL_CONTROLLER is not set
584# CONFIG_VMXNET3 is not set
549# CONFIG_ISDN is not set 585# CONFIG_ISDN is not set
550# CONFIG_PHONE is not set 586# CONFIG_PHONE is not set
551 587
@@ -555,6 +591,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
555CONFIG_INPUT=y 591CONFIG_INPUT=y
556# CONFIG_INPUT_FF_MEMLESS is not set 592# CONFIG_INPUT_FF_MEMLESS is not set
557# CONFIG_INPUT_POLLDEV is not set 593# CONFIG_INPUT_POLLDEV is not set
594# CONFIG_INPUT_SPARSEKMAP is not set
558 595
559# 596#
560# Userland interfaces 597# Userland interfaces
@@ -574,6 +611,7 @@ CONFIG_INPUT_KEYBOARD=y
574CONFIG_KEYBOARD_ATKBD=m 611CONFIG_KEYBOARD_ATKBD=m
575# CONFIG_KEYBOARD_LKKBD is not set 612# CONFIG_KEYBOARD_LKKBD is not set
576# CONFIG_KEYBOARD_NEWTON is not set 613# CONFIG_KEYBOARD_NEWTON is not set
614# CONFIG_KEYBOARD_OPENCORES is not set
577# CONFIG_KEYBOARD_STOWAWAY is not set 615# CONFIG_KEYBOARD_STOWAWAY is not set
578CONFIG_KEYBOARD_SUNKBD=m 616CONFIG_KEYBOARD_SUNKBD=m
579# CONFIG_KEYBOARD_XTKBD is not set 617# CONFIG_KEYBOARD_XTKBD is not set
@@ -604,6 +642,7 @@ CONFIG_SERIO_SERPORT=m
604# CONFIG_SERIO_PCIPS2 is not set 642# CONFIG_SERIO_PCIPS2 is not set
605CONFIG_SERIO_LIBPS2=m 643CONFIG_SERIO_LIBPS2=m
606# CONFIG_SERIO_RAW is not set 644# CONFIG_SERIO_RAW is not set
645# CONFIG_SERIO_ALTERA_PS2 is not set
607# CONFIG_GAMEPORT is not set 646# CONFIG_GAMEPORT is not set
608 647
609# 648#
@@ -636,6 +675,7 @@ CONFIG_SERIAL_CORE=y
636CONFIG_SERIAL_CORE_CONSOLE=y 675CONFIG_SERIAL_CORE_CONSOLE=y
637CONFIG_CONSOLE_POLL=y 676CONFIG_CONSOLE_POLL=y
638# CONFIG_SERIAL_JSM is not set 677# CONFIG_SERIAL_JSM is not set
678# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set
639CONFIG_UNIX98_PTYS=y 679CONFIG_UNIX98_PTYS=y
640# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 680# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
641CONFIG_LEGACY_PTYS=y 681CONFIG_LEGACY_PTYS=y
@@ -661,6 +701,11 @@ CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
661# CONFIG_POWER_SUPPLY is not set 701# CONFIG_POWER_SUPPLY is not set
662CONFIG_HWMON=y 702CONFIG_HWMON=y
663# CONFIG_HWMON_VID is not set 703# CONFIG_HWMON_VID is not set
704# CONFIG_HWMON_DEBUG_CHIP is not set
705
706#
707# Native drivers
708#
664# CONFIG_SENSORS_I5K_AMB is not set 709# CONFIG_SENSORS_I5K_AMB is not set
665# CONFIG_SENSORS_F71805F is not set 710# CONFIG_SENSORS_F71805F is not set
666# CONFIG_SENSORS_F71882FG is not set 711# CONFIG_SENSORS_F71882FG is not set
@@ -675,9 +720,7 @@ CONFIG_HWMON=y
675# CONFIG_SENSORS_VT8231 is not set 720# CONFIG_SENSORS_VT8231 is not set
676# CONFIG_SENSORS_W83627HF is not set 721# CONFIG_SENSORS_W83627HF is not set
677# CONFIG_SENSORS_W83627EHF is not set 722# CONFIG_SENSORS_W83627EHF is not set
678# CONFIG_HWMON_DEBUG_CHIP is not set
679# CONFIG_THERMAL is not set 723# CONFIG_THERMAL is not set
680# CONFIG_THERMAL_HWMON is not set
681# CONFIG_WATCHDOG is not set 724# CONFIG_WATCHDOG is not set
682CONFIG_SSB_POSSIBLE=y 725CONFIG_SSB_POSSIBLE=y
683 726
@@ -699,6 +742,7 @@ CONFIG_SSB_POSSIBLE=y
699# 742#
700# Graphics support 743# Graphics support
701# 744#
745CONFIG_VGA_ARB=y
702# CONFIG_VGASTATE is not set 746# CONFIG_VGASTATE is not set
703# CONFIG_VIDEO_OUTPUT_CONTROL is not set 747# CONFIG_VIDEO_OUTPUT_CONTROL is not set
704# CONFIG_FB is not set 748# CONFIG_FB is not set
@@ -776,7 +820,9 @@ CONFIG_RTC_INTF_DEV=y
776# CONFIG_RTC_DRV_M48T86 is not set 820# CONFIG_RTC_DRV_M48T86 is not set
777# CONFIG_RTC_DRV_M48T35 is not set 821# CONFIG_RTC_DRV_M48T35 is not set
778CONFIG_RTC_DRV_M48T59=y 822CONFIG_RTC_DRV_M48T59=y
823# CONFIG_RTC_DRV_MSM6242 is not set
779# CONFIG_RTC_DRV_BQ4802 is not set 824# CONFIG_RTC_DRV_BQ4802 is not set
825# CONFIG_RTC_DRV_RP5C01 is not set
780# CONFIG_RTC_DRV_V3020 is not set 826# CONFIG_RTC_DRV_V3020 is not set
781 827
782# 828#
@@ -955,6 +1001,7 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
955CONFIG_ENABLE_MUST_CHECK=y 1001CONFIG_ENABLE_MUST_CHECK=y
956CONFIG_FRAME_WARN=1024 1002CONFIG_FRAME_WARN=1024
957CONFIG_MAGIC_SYSRQ=y 1003CONFIG_MAGIC_SYSRQ=y
1004# CONFIG_STRIP_ASM_SYMS is not set
958# CONFIG_UNUSED_SYMBOLS is not set 1005# CONFIG_UNUSED_SYMBOLS is not set
959# CONFIG_DEBUG_FS is not set 1006# CONFIG_DEBUG_FS is not set
960# CONFIG_HEADERS_CHECK is not set 1007# CONFIG_HEADERS_CHECK is not set
@@ -1003,9 +1050,9 @@ CONFIG_KGDB=y
1003CONFIG_KGDB_SERIAL_CONSOLE=y 1050CONFIG_KGDB_SERIAL_CONSOLE=y
1004CONFIG_KGDB_TESTS=y 1051CONFIG_KGDB_TESTS=y
1005# CONFIG_KGDB_TESTS_ON_BOOT is not set 1052# CONFIG_KGDB_TESTS_ON_BOOT is not set
1006# CONFIG_KMEMCHECK is not set
1007# CONFIG_DEBUG_STACK_USAGE is not set 1053# CONFIG_DEBUG_STACK_USAGE is not set
1008# CONFIG_STACK_DEBUG is not set 1054# CONFIG_STACK_DEBUG is not set
1055# CONFIG_DEBUG_STRICT_USER_COPY_CHECKS is not set
1009 1056
1010# 1057#
1011# Security options 1058# Security options
@@ -1013,7 +1060,11 @@ CONFIG_KGDB_TESTS=y
1013# CONFIG_KEYS is not set 1060# CONFIG_KEYS is not set
1014# CONFIG_SECURITY is not set 1061# CONFIG_SECURITY is not set
1015# CONFIG_SECURITYFS is not set 1062# CONFIG_SECURITYFS is not set
1016# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1063# CONFIG_DEFAULT_SECURITY_SELINUX is not set
1064# CONFIG_DEFAULT_SECURITY_SMACK is not set
1065# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
1066CONFIG_DEFAULT_SECURITY_DAC=y
1067CONFIG_DEFAULT_SECURITY=""
1017CONFIG_CRYPTO=y 1068CONFIG_CRYPTO=y
1018 1069
1019# 1070#
diff --git a/arch/sparc/configs/sparc64_defconfig b/arch/sparc/configs/sparc64_defconfig
index f80b881dfea7..41c5a56aa6f2 100644
--- a/arch/sparc/configs/sparc64_defconfig
+++ b/arch/sparc/configs/sparc64_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.31 3# Linux kernel version: 2.6.33-rc2
4# Tue Sep 15 17:06:03 2009 4# Wed Jan 20 16:31:47 2010
5# 5#
6CONFIG_64BIT=y 6CONFIG_64BIT=y
7CONFIG_SPARC=y 7CONFIG_SPARC=y
@@ -20,6 +20,7 @@ CONFIG_HAVE_LATENCYTOP_SUPPORT=y
20CONFIG_AUDIT_ARCH=y 20CONFIG_AUDIT_ARCH=y
21CONFIG_HAVE_SETUP_PER_CPU_AREA=y 21CONFIG_HAVE_SETUP_PER_CPU_AREA=y
22CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y 22CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
23CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
23CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y 24CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
24CONFIG_MMU=y 25CONFIG_MMU=y
25CONFIG_ARCH_NO_VIRT_TO_BUS=y 26CONFIG_ARCH_NO_VIRT_TO_BUS=y
@@ -50,6 +51,7 @@ CONFIG_POSIX_MQUEUE_SYSCTL=y
50# 51#
51CONFIG_TREE_RCU=y 52CONFIG_TREE_RCU=y
52# CONFIG_TREE_PREEMPT_RCU is not set 53# CONFIG_TREE_PREEMPT_RCU is not set
54# CONFIG_TINY_RCU is not set
53# CONFIG_RCU_TRACE is not set 55# CONFIG_RCU_TRACE is not set
54CONFIG_RCU_FANOUT=64 56CONFIG_RCU_FANOUT=64
55# CONFIG_RCU_FANOUT_EXACT is not set 57# CONFIG_RCU_FANOUT_EXACT is not set
@@ -62,8 +64,7 @@ CONFIG_RT_GROUP_SCHED=y
62CONFIG_USER_SCHED=y 64CONFIG_USER_SCHED=y
63# CONFIG_CGROUP_SCHED is not set 65# CONFIG_CGROUP_SCHED is not set
64# CONFIG_CGROUPS is not set 66# CONFIG_CGROUPS is not set
65CONFIG_SYSFS_DEPRECATED=y 67# CONFIG_SYSFS_DEPRECATED_V2 is not set
66CONFIG_SYSFS_DEPRECATED_V2=y
67CONFIG_RELAY=y 68CONFIG_RELAY=y
68CONFIG_NAMESPACES=y 69CONFIG_NAMESPACES=y
69# CONFIG_UTS_NS is not set 70# CONFIG_UTS_NS is not set
@@ -97,24 +98,25 @@ CONFIG_TIMERFD=y
97CONFIG_EVENTFD=y 98CONFIG_EVENTFD=y
98CONFIG_SHMEM=y 99CONFIG_SHMEM=y
99CONFIG_AIO=y 100CONFIG_AIO=y
100CONFIG_HAVE_PERF_COUNTERS=y 101CONFIG_HAVE_PERF_EVENTS=y
102CONFIG_PERF_USE_VMALLOC=y
101 103
102# 104#
103# Performance Counters 105# Kernel Performance Events And Counters
104# 106#
105CONFIG_PERF_COUNTERS=y 107CONFIG_PERF_EVENTS=y
106CONFIG_EVENT_PROFILE=y 108CONFIG_EVENT_PROFILE=y
109CONFIG_PERF_COUNTERS=y
110# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
107CONFIG_VM_EVENT_COUNTERS=y 111CONFIG_VM_EVENT_COUNTERS=y
108CONFIG_PCI_QUIRKS=y 112CONFIG_PCI_QUIRKS=y
109CONFIG_SLUB_DEBUG=y 113CONFIG_SLUB_DEBUG=y
110# CONFIG_STRIP_ASM_SYMS is not set
111# CONFIG_COMPAT_BRK is not set 114# CONFIG_COMPAT_BRK is not set
112# CONFIG_SLAB is not set 115# CONFIG_SLAB is not set
113CONFIG_SLUB=y 116CONFIG_SLUB=y
114# CONFIG_SLOB is not set 117# CONFIG_SLOB is not set
115CONFIG_PROFILING=y 118CONFIG_PROFILING=y
116CONFIG_TRACEPOINTS=y 119CONFIG_TRACEPOINTS=y
117CONFIG_MARKERS=y
118CONFIG_OPROFILE=m 120CONFIG_OPROFILE=m
119CONFIG_HAVE_OPROFILE=y 121CONFIG_HAVE_OPROFILE=y
120CONFIG_KPROBES=y 122CONFIG_KPROBES=y
@@ -152,14 +154,41 @@ CONFIG_BLOCK_COMPAT=y
152# IO Schedulers 154# IO Schedulers
153# 155#
154CONFIG_IOSCHED_NOOP=y 156CONFIG_IOSCHED_NOOP=y
155CONFIG_IOSCHED_AS=y
156CONFIG_IOSCHED_DEADLINE=y 157CONFIG_IOSCHED_DEADLINE=y
157CONFIG_IOSCHED_CFQ=y 158CONFIG_IOSCHED_CFQ=y
158CONFIG_DEFAULT_AS=y
159# CONFIG_DEFAULT_DEADLINE is not set 159# CONFIG_DEFAULT_DEADLINE is not set
160# CONFIG_DEFAULT_CFQ is not set 160CONFIG_DEFAULT_CFQ=y
161# CONFIG_DEFAULT_NOOP is not set 161# CONFIG_DEFAULT_NOOP is not set
162CONFIG_DEFAULT_IOSCHED="anticipatory" 162CONFIG_DEFAULT_IOSCHED="cfq"
163# CONFIG_INLINE_SPIN_TRYLOCK is not set
164# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
165# CONFIG_INLINE_SPIN_LOCK is not set
166# CONFIG_INLINE_SPIN_LOCK_BH is not set
167# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
168# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
169CONFIG_INLINE_SPIN_UNLOCK=y
170# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
171CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
172# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
173# CONFIG_INLINE_READ_TRYLOCK is not set
174# CONFIG_INLINE_READ_LOCK is not set
175# CONFIG_INLINE_READ_LOCK_BH is not set
176# CONFIG_INLINE_READ_LOCK_IRQ is not set
177# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
178CONFIG_INLINE_READ_UNLOCK=y
179# CONFIG_INLINE_READ_UNLOCK_BH is not set
180CONFIG_INLINE_READ_UNLOCK_IRQ=y
181# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
182# CONFIG_INLINE_WRITE_TRYLOCK is not set
183# CONFIG_INLINE_WRITE_LOCK is not set
184# CONFIG_INLINE_WRITE_LOCK_BH is not set
185# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
186# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
187CONFIG_INLINE_WRITE_UNLOCK=y
188# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
189CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
190# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
191CONFIG_MUTEX_SPIN_ON_OWNER=y
163# CONFIG_FREEZER is not set 192# CONFIG_FREEZER is not set
164 193
165# 194#
@@ -179,6 +208,7 @@ CONFIG_GENERIC_HWEIGHT=y
179CONFIG_GENERIC_CALIBRATE_DELAY=y 208CONFIG_GENERIC_CALIBRATE_DELAY=y
180CONFIG_ARCH_MAY_HAVE_PC_FDC=y 209CONFIG_ARCH_MAY_HAVE_PC_FDC=y
181CONFIG_SPARC64_SMP=y 210CONFIG_SPARC64_SMP=y
211CONFIG_EARLYFB=y
182CONFIG_SPARC64_PAGE_SIZE_8KB=y 212CONFIG_SPARC64_PAGE_SIZE_8KB=y
183# CONFIG_SPARC64_PAGE_SIZE_64KB is not set 213# CONFIG_SPARC64_PAGE_SIZE_64KB is not set
184CONFIG_SECCOMP=y 214CONFIG_SECCOMP=y
@@ -216,8 +246,7 @@ CONFIG_MIGRATION=y
216CONFIG_PHYS_ADDR_T_64BIT=y 246CONFIG_PHYS_ADDR_T_64BIT=y
217CONFIG_ZONE_DMA_FLAG=0 247CONFIG_ZONE_DMA_FLAG=0
218CONFIG_NR_QUICK=1 248CONFIG_NR_QUICK=1
219CONFIG_HAVE_MLOCK=y 249# CONFIG_KSM is not set
220CONFIG_HAVE_MLOCKED_PAGE_BIT=y
221CONFIG_DEFAULT_MMAP_MIN_ADDR=8192 250CONFIG_DEFAULT_MMAP_MIN_ADDR=8192
222CONFIG_SCHED_SMT=y 251CONFIG_SCHED_SMT=y
223CONFIG_SCHED_MC=y 252CONFIG_SCHED_MC=y
@@ -315,6 +344,7 @@ CONFIG_INET6_XFRM_MODE_TUNNEL=m
315CONFIG_INET6_XFRM_MODE_BEET=m 344CONFIG_INET6_XFRM_MODE_BEET=m
316# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set 345# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
317CONFIG_IPV6_SIT=m 346CONFIG_IPV6_SIT=m
347# CONFIG_IPV6_SIT_6RD is not set
318CONFIG_IPV6_NDISC_NODETYPE=y 348CONFIG_IPV6_NDISC_NODETYPE=y
319CONFIG_IPV6_TUNNEL=m 349CONFIG_IPV6_TUNNEL=m
320# CONFIG_IPV6_MULTIPLE_TABLES is not set 350# CONFIG_IPV6_MULTIPLE_TABLES is not set
@@ -356,9 +386,6 @@ CONFIG_NET_TCPPROBE=m
356# CONFIG_AF_RXRPC is not set 386# CONFIG_AF_RXRPC is not set
357CONFIG_WIRELESS=y 387CONFIG_WIRELESS=y
358# CONFIG_CFG80211 is not set 388# CONFIG_CFG80211 is not set
359CONFIG_CFG80211_DEFAULT_PS_VALUE=0
360CONFIG_WIRELESS_OLD_REGULATORY=y
361# CONFIG_WIRELESS_EXT is not set
362# CONFIG_LIB80211 is not set 389# CONFIG_LIB80211 is not set
363 390
364# 391#
@@ -376,6 +403,7 @@ CONFIG_WIRELESS_OLD_REGULATORY=y
376# Generic Driver Options 403# Generic Driver Options
377# 404#
378CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 405CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
406# CONFIG_DEVTMPFS is not set
379CONFIG_STANDALONE=y 407CONFIG_STANDALONE=y
380# CONFIG_PREVENT_FIRMWARE_BUILD is not set 408# CONFIG_PREVENT_FIRMWARE_BUILD is not set
381CONFIG_FW_LOADER=y 409CONFIG_FW_LOADER=y
@@ -397,6 +425,11 @@ CONFIG_BLK_DEV=y
397# CONFIG_BLK_DEV_COW_COMMON is not set 425# CONFIG_BLK_DEV_COW_COMMON is not set
398CONFIG_BLK_DEV_LOOP=m 426CONFIG_BLK_DEV_LOOP=m
399CONFIG_BLK_DEV_CRYPTOLOOP=m 427CONFIG_BLK_DEV_CRYPTOLOOP=m
428
429#
430# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
431#
432# CONFIG_BLK_DEV_DRBD is not set
400CONFIG_BLK_DEV_NBD=m 433CONFIG_BLK_DEV_NBD=m
401# CONFIG_BLK_DEV_SX8 is not set 434# CONFIG_BLK_DEV_SX8 is not set
402# CONFIG_BLK_DEV_UB is not set 435# CONFIG_BLK_DEV_UB is not set
@@ -408,6 +441,7 @@ CONFIG_ATA_OVER_ETH=m
408CONFIG_SUNVDC=m 441CONFIG_SUNVDC=m
409# CONFIG_BLK_DEV_HD is not set 442# CONFIG_BLK_DEV_HD is not set
410CONFIG_MISC_DEVICES=y 443CONFIG_MISC_DEVICES=y
444# CONFIG_AD525X_DPOT is not set
411# CONFIG_PHANTOM is not set 445# CONFIG_PHANTOM is not set
412# CONFIG_SGI_IOC4 is not set 446# CONFIG_SGI_IOC4 is not set
413# CONFIG_TIFM_CORE is not set 447# CONFIG_TIFM_CORE is not set
@@ -415,6 +449,7 @@ CONFIG_MISC_DEVICES=y
415# CONFIG_ENCLOSURE_SERVICES is not set 449# CONFIG_ENCLOSURE_SERVICES is not set
416# CONFIG_HP_ILO is not set 450# CONFIG_HP_ILO is not set
417# CONFIG_ISL29003 is not set 451# CONFIG_ISL29003 is not set
452# CONFIG_DS1682 is not set
418# CONFIG_C2PORT is not set 453# CONFIG_C2PORT is not set
419 454
420# 455#
@@ -522,8 +557,11 @@ CONFIG_SCSI_LOWLEVEL=y
522# CONFIG_ISCSI_TCP is not set 557# CONFIG_ISCSI_TCP is not set
523# CONFIG_SCSI_CXGB3_ISCSI is not set 558# CONFIG_SCSI_CXGB3_ISCSI is not set
524# CONFIG_SCSI_BNX2_ISCSI is not set 559# CONFIG_SCSI_BNX2_ISCSI is not set
560# CONFIG_BE2ISCSI is not set
525# CONFIG_BLK_DEV_3W_XXXX_RAID is not set 561# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
562# CONFIG_SCSI_HPSA is not set
526# CONFIG_SCSI_3W_9XXX is not set 563# CONFIG_SCSI_3W_9XXX is not set
564# CONFIG_SCSI_3W_SAS is not set
527# CONFIG_SCSI_ACARD is not set 565# CONFIG_SCSI_ACARD is not set
528# CONFIG_SCSI_AACRAID is not set 566# CONFIG_SCSI_AACRAID is not set
529# CONFIG_SCSI_AIC7XXX is not set 567# CONFIG_SCSI_AIC7XXX is not set
@@ -557,7 +595,9 @@ CONFIG_SCSI_LOWLEVEL=y
557# CONFIG_SCSI_DEBUG is not set 595# CONFIG_SCSI_DEBUG is not set
558# CONFIG_SCSI_SUNESP is not set 596# CONFIG_SCSI_SUNESP is not set
559# CONFIG_SCSI_PMCRAID is not set 597# CONFIG_SCSI_PMCRAID is not set
598# CONFIG_SCSI_PM8001 is not set
560# CONFIG_SCSI_SRP is not set 599# CONFIG_SCSI_SRP is not set
600# CONFIG_SCSI_BFA_FC is not set
561# CONFIG_SCSI_DH is not set 601# CONFIG_SCSI_DH is not set
562# CONFIG_SCSI_OSD_INITIATOR is not set 602# CONFIG_SCSI_OSD_INITIATOR is not set
563# CONFIG_ATA is not set 603# CONFIG_ATA is not set
@@ -568,7 +608,9 @@ CONFIG_MD_RAID0=m
568CONFIG_MD_RAID1=m 608CONFIG_MD_RAID1=m
569CONFIG_MD_RAID10=m 609CONFIG_MD_RAID10=m
570CONFIG_MD_RAID456=m 610CONFIG_MD_RAID456=m
611# CONFIG_MULTICORE_RAID456 is not set
571CONFIG_MD_RAID6_PQ=m 612CONFIG_MD_RAID6_PQ=m
613# CONFIG_ASYNC_RAID6_TEST is not set
572CONFIG_MD_MULTIPATH=m 614CONFIG_MD_MULTIPATH=m
573# CONFIG_MD_FAULTY is not set 615# CONFIG_MD_FAULTY is not set
574CONFIG_BLK_DEV_DM=m 616CONFIG_BLK_DEV_DM=m
@@ -592,7 +634,7 @@ CONFIG_DM_ZERO=m
592# 634#
593 635
594# 636#
595# See the help texts for more information. 637# The newer stack is recommended.
596# 638#
597# CONFIG_FIREWIRE is not set 639# CONFIG_FIREWIRE is not set
598# CONFIG_IEEE1394 is not set 640# CONFIG_IEEE1394 is not set
@@ -664,6 +706,7 @@ CONFIG_NET_PCI=y
664# CONFIG_SUNDANCE is not set 706# CONFIG_SUNDANCE is not set
665# CONFIG_TLAN is not set 707# CONFIG_TLAN is not set
666# CONFIG_KS8842 is not set 708# CONFIG_KS8842 is not set
709# CONFIG_KS8851_MLL is not set
667# CONFIG_VIA_RHINE is not set 710# CONFIG_VIA_RHINE is not set
668# CONFIG_SC92031 is not set 711# CONFIG_SC92031 is not set
669# CONFIG_ATL2 is not set 712# CONFIG_ATL2 is not set
@@ -745,6 +788,7 @@ CONFIG_SLHC=m
745# CONFIG_NETCONSOLE is not set 788# CONFIG_NETCONSOLE is not set
746# CONFIG_NETPOLL is not set 789# CONFIG_NETPOLL is not set
747# CONFIG_NET_POLL_CONTROLLER is not set 790# CONFIG_NET_POLL_CONTROLLER is not set
791# CONFIG_VMXNET3 is not set
748# CONFIG_ISDN is not set 792# CONFIG_ISDN is not set
749# CONFIG_PHONE is not set 793# CONFIG_PHONE is not set
750 794
@@ -754,6 +798,7 @@ CONFIG_SLHC=m
754CONFIG_INPUT=y 798CONFIG_INPUT=y
755# CONFIG_INPUT_FF_MEMLESS is not set 799# CONFIG_INPUT_FF_MEMLESS is not set
756# CONFIG_INPUT_POLLDEV is not set 800# CONFIG_INPUT_POLLDEV is not set
801# CONFIG_INPUT_SPARSEKMAP is not set
757 802
758# 803#
759# Userland interfaces 804# Userland interfaces
@@ -770,9 +815,13 @@ CONFIG_INPUT_EVDEV=y
770# Input Device Drivers 815# Input Device Drivers
771# 816#
772CONFIG_INPUT_KEYBOARD=y 817CONFIG_INPUT_KEYBOARD=y
818# CONFIG_KEYBOARD_ADP5588 is not set
773CONFIG_KEYBOARD_ATKBD=y 819CONFIG_KEYBOARD_ATKBD=y
820# CONFIG_QT2160 is not set
774CONFIG_KEYBOARD_LKKBD=m 821CONFIG_KEYBOARD_LKKBD=m
822# CONFIG_KEYBOARD_MAX7359 is not set
775# CONFIG_KEYBOARD_NEWTON is not set 823# CONFIG_KEYBOARD_NEWTON is not set
824# CONFIG_KEYBOARD_OPENCORES is not set
776# CONFIG_KEYBOARD_STOWAWAY is not set 825# CONFIG_KEYBOARD_STOWAWAY is not set
777CONFIG_KEYBOARD_SUNKBD=y 826CONFIG_KEYBOARD_SUNKBD=y
778# CONFIG_KEYBOARD_XTKBD is not set 827# CONFIG_KEYBOARD_XTKBD is not set
@@ -812,6 +861,7 @@ CONFIG_SERIO_I8042=y
812CONFIG_SERIO_PCIPS2=m 861CONFIG_SERIO_PCIPS2=m
813CONFIG_SERIO_LIBPS2=y 862CONFIG_SERIO_LIBPS2=y
814CONFIG_SERIO_RAW=m 863CONFIG_SERIO_RAW=m
864# CONFIG_SERIO_ALTERA_PS2 is not set
815# CONFIG_GAMEPORT is not set 865# CONFIG_GAMEPORT is not set
816 866
817# 867#
@@ -844,6 +894,7 @@ CONFIG_SERIAL_SUNHV=y
844CONFIG_SERIAL_CORE=y 894CONFIG_SERIAL_CORE=y
845CONFIG_SERIAL_CORE_CONSOLE=y 895CONFIG_SERIAL_CORE_CONSOLE=y
846# CONFIG_SERIAL_JSM is not set 896# CONFIG_SERIAL_JSM is not set
897# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set
847CONFIG_UNIX98_PTYS=y 898CONFIG_UNIX98_PTYS=y
848# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 899# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
849# CONFIG_LEGACY_PTYS is not set 900# CONFIG_LEGACY_PTYS is not set
@@ -858,6 +909,7 @@ CONFIG_HW_RANDOM_N2RNG=m
858CONFIG_DEVPORT=y 909CONFIG_DEVPORT=y
859CONFIG_I2C=y 910CONFIG_I2C=y
860CONFIG_I2C_BOARDINFO=y 911CONFIG_I2C_BOARDINFO=y
912CONFIG_I2C_COMPAT=y
861# CONFIG_I2C_CHARDEV is not set 913# CONFIG_I2C_CHARDEV is not set
862CONFIG_I2C_HELPER_AUTO=y 914CONFIG_I2C_HELPER_AUTO=y
863CONFIG_I2C_ALGOBIT=y 915CONFIG_I2C_ALGOBIT=y
@@ -898,11 +950,6 @@ CONFIG_I2C_ALGOBIT=y
898# CONFIG_I2C_TINY_USB is not set 950# CONFIG_I2C_TINY_USB is not set
899 951
900# 952#
901# Graphics adapter I2C/DDC channel drivers
902#
903# CONFIG_I2C_VOODOO3 is not set
904
905#
906# Other I2C/SMBus bus drivers 953# Other I2C/SMBus bus drivers
907# 954#
908# CONFIG_I2C_PCA_PLATFORM is not set 955# CONFIG_I2C_PCA_PLATFORM is not set
@@ -911,10 +958,6 @@ CONFIG_I2C_ALGOBIT=y
911# 958#
912# Miscellaneous I2C Chip support 959# Miscellaneous I2C Chip support
913# 960#
914# CONFIG_DS1682 is not set
915# CONFIG_SENSORS_PCF8574 is not set
916# CONFIG_PCF8575 is not set
917# CONFIG_SENSORS_PCA9539 is not set
918# CONFIG_SENSORS_TSL2550 is not set 961# CONFIG_SENSORS_TSL2550 is not set
919# CONFIG_I2C_DEBUG_CORE is not set 962# CONFIG_I2C_DEBUG_CORE is not set
920# CONFIG_I2C_DEBUG_ALGO is not set 963# CONFIG_I2C_DEBUG_ALGO is not set
@@ -932,6 +975,11 @@ CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
932# CONFIG_POWER_SUPPLY is not set 975# CONFIG_POWER_SUPPLY is not set
933CONFIG_HWMON=y 976CONFIG_HWMON=y
934# CONFIG_HWMON_VID is not set 977# CONFIG_HWMON_VID is not set
978# CONFIG_HWMON_DEBUG_CHIP is not set
979
980#
981# Native drivers
982#
935# CONFIG_SENSORS_AD7414 is not set 983# CONFIG_SENSORS_AD7414 is not set
936# CONFIG_SENSORS_AD7418 is not set 984# CONFIG_SENSORS_AD7418 is not set
937# CONFIG_SENSORS_ADM1021 is not set 985# CONFIG_SENSORS_ADM1021 is not set
@@ -955,6 +1003,7 @@ CONFIG_HWMON=y
955# CONFIG_SENSORS_GL520SM is not set 1003# CONFIG_SENSORS_GL520SM is not set
956# CONFIG_SENSORS_IT87 is not set 1004# CONFIG_SENSORS_IT87 is not set
957# CONFIG_SENSORS_LM63 is not set 1005# CONFIG_SENSORS_LM63 is not set
1006# CONFIG_SENSORS_LM73 is not set
958# CONFIG_SENSORS_LM75 is not set 1007# CONFIG_SENSORS_LM75 is not set
959# CONFIG_SENSORS_LM77 is not set 1008# CONFIG_SENSORS_LM77 is not set
960# CONFIG_SENSORS_LM78 is not set 1009# CONFIG_SENSORS_LM78 is not set
@@ -981,6 +1030,7 @@ CONFIG_HWMON=y
981# CONFIG_SENSORS_ADS7828 is not set 1030# CONFIG_SENSORS_ADS7828 is not set
982# CONFIG_SENSORS_THMC50 is not set 1031# CONFIG_SENSORS_THMC50 is not set
983# CONFIG_SENSORS_TMP401 is not set 1032# CONFIG_SENSORS_TMP401 is not set
1033# CONFIG_SENSORS_TMP421 is not set
984# CONFIG_SENSORS_VIA686A is not set 1034# CONFIG_SENSORS_VIA686A is not set
985# CONFIG_SENSORS_VT1211 is not set 1035# CONFIG_SENSORS_VT1211 is not set
986# CONFIG_SENSORS_VT8231 is not set 1036# CONFIG_SENSORS_VT8231 is not set
@@ -993,9 +1043,8 @@ CONFIG_HWMON=y
993# CONFIG_SENSORS_W83627HF is not set 1043# CONFIG_SENSORS_W83627HF is not set
994# CONFIG_SENSORS_W83627EHF is not set 1044# CONFIG_SENSORS_W83627EHF is not set
995# CONFIG_SENSORS_ULTRA45 is not set 1045# CONFIG_SENSORS_ULTRA45 is not set
996# CONFIG_HWMON_DEBUG_CHIP is not set 1046# CONFIG_SENSORS_LIS3_I2C is not set
997# CONFIG_THERMAL is not set 1047# CONFIG_THERMAL is not set
998# CONFIG_THERMAL_HWMON is not set
999# CONFIG_WATCHDOG is not set 1048# CONFIG_WATCHDOG is not set
1000CONFIG_SSB_POSSIBLE=y 1049CONFIG_SSB_POSSIBLE=y
1001 1050
@@ -1013,16 +1062,20 @@ CONFIG_SSB_POSSIBLE=y
1013# CONFIG_TWL4030_CORE is not set 1062# CONFIG_TWL4030_CORE is not set
1014# CONFIG_MFD_TMIO is not set 1063# CONFIG_MFD_TMIO is not set
1015# CONFIG_PMIC_DA903X is not set 1064# CONFIG_PMIC_DA903X is not set
1065# CONFIG_PMIC_ADP5520 is not set
1016# CONFIG_MFD_WM8400 is not set 1066# CONFIG_MFD_WM8400 is not set
1067# CONFIG_MFD_WM831X is not set
1017# CONFIG_MFD_WM8350_I2C is not set 1068# CONFIG_MFD_WM8350_I2C is not set
1018# CONFIG_MFD_PCF50633 is not set 1069# CONFIG_MFD_PCF50633 is not set
1019# CONFIG_AB3100_CORE is not set 1070# CONFIG_AB3100_CORE is not set
1071# CONFIG_MFD_88PM8607 is not set
1020# CONFIG_REGULATOR is not set 1072# CONFIG_REGULATOR is not set
1021# CONFIG_MEDIA_SUPPORT is not set 1073# CONFIG_MEDIA_SUPPORT is not set
1022 1074
1023# 1075#
1024# Graphics support 1076# Graphics support
1025# 1077#
1078CONFIG_VGA_ARB=y
1026# CONFIG_DRM is not set 1079# CONFIG_DRM is not set
1027# CONFIG_VGASTATE is not set 1080# CONFIG_VGASTATE is not set
1028# CONFIG_VIDEO_OUTPUT_CONTROL is not set 1081# CONFIG_VIDEO_OUTPUT_CONTROL is not set
@@ -1176,6 +1229,7 @@ CONFIG_SND_ALI5451=m
1176# CONFIG_SND_OXYGEN is not set 1229# CONFIG_SND_OXYGEN is not set
1177# CONFIG_SND_CS4281 is not set 1230# CONFIG_SND_CS4281 is not set
1178# CONFIG_SND_CS46XX is not set 1231# CONFIG_SND_CS46XX is not set
1232# CONFIG_SND_CS5535AUDIO is not set
1179# CONFIG_SND_CTXFI is not set 1233# CONFIG_SND_CTXFI is not set
1180# CONFIG_SND_DARLA20 is not set 1234# CONFIG_SND_DARLA20 is not set
1181# CONFIG_SND_GINA20 is not set 1235# CONFIG_SND_GINA20 is not set
@@ -1311,6 +1365,7 @@ CONFIG_USB_EHCI_HCD=m
1311# CONFIG_USB_OXU210HP_HCD is not set 1365# CONFIG_USB_OXU210HP_HCD is not set
1312# CONFIG_USB_ISP116X_HCD is not set 1366# CONFIG_USB_ISP116X_HCD is not set
1313# CONFIG_USB_ISP1760_HCD is not set 1367# CONFIG_USB_ISP1760_HCD is not set
1368# CONFIG_USB_ISP1362_HCD is not set
1314CONFIG_USB_OHCI_HCD=y 1369CONFIG_USB_OHCI_HCD=y
1315# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set 1370# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
1316# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set 1371# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
@@ -1426,6 +1481,7 @@ CONFIG_RTC_INTF_DEV=y
1426# CONFIG_RTC_DRV_PCF8563 is not set 1481# CONFIG_RTC_DRV_PCF8563 is not set
1427# CONFIG_RTC_DRV_PCF8583 is not set 1482# CONFIG_RTC_DRV_PCF8583 is not set
1428# CONFIG_RTC_DRV_M41T80 is not set 1483# CONFIG_RTC_DRV_M41T80 is not set
1484# CONFIG_RTC_DRV_BQ32K is not set
1429# CONFIG_RTC_DRV_S35390A is not set 1485# CONFIG_RTC_DRV_S35390A is not set
1430# CONFIG_RTC_DRV_FM3130 is not set 1486# CONFIG_RTC_DRV_FM3130 is not set
1431# CONFIG_RTC_DRV_RX8581 is not set 1487# CONFIG_RTC_DRV_RX8581 is not set
@@ -1447,7 +1503,9 @@ CONFIG_RTC_DRV_CMOS=y
1447# CONFIG_RTC_DRV_M48T86 is not set 1503# CONFIG_RTC_DRV_M48T86 is not set
1448# CONFIG_RTC_DRV_M48T35 is not set 1504# CONFIG_RTC_DRV_M48T35 is not set
1449CONFIG_RTC_DRV_M48T59=y 1505CONFIG_RTC_DRV_M48T59=y
1506# CONFIG_RTC_DRV_MSM6242 is not set
1450CONFIG_RTC_DRV_BQ4802=y 1507CONFIG_RTC_DRV_BQ4802=y
1508# CONFIG_RTC_DRV_RP5C01 is not set
1451# CONFIG_RTC_DRV_V3020 is not set 1509# CONFIG_RTC_DRV_V3020 is not set
1452 1510
1453# 1511#
@@ -1625,6 +1683,7 @@ CONFIG_PRINTK_TIME=y
1625CONFIG_ENABLE_MUST_CHECK=y 1683CONFIG_ENABLE_MUST_CHECK=y
1626CONFIG_FRAME_WARN=2048 1684CONFIG_FRAME_WARN=2048
1627CONFIG_MAGIC_SYSRQ=y 1685CONFIG_MAGIC_SYSRQ=y
1686# CONFIG_STRIP_ASM_SYMS is not set
1628# CONFIG_UNUSED_SYMBOLS is not set 1687# CONFIG_UNUSED_SYMBOLS is not set
1629CONFIG_DEBUG_FS=y 1688CONFIG_DEBUG_FS=y
1630# CONFIG_HEADERS_CHECK is not set 1689# CONFIG_HEADERS_CHECK is not set
@@ -1678,9 +1737,11 @@ CONFIG_NOP_TRACER=y
1678CONFIG_HAVE_FUNCTION_TRACER=y 1737CONFIG_HAVE_FUNCTION_TRACER=y
1679CONFIG_HAVE_DYNAMIC_FTRACE=y 1738CONFIG_HAVE_DYNAMIC_FTRACE=y
1680CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1739CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1740CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
1681CONFIG_RING_BUFFER=y 1741CONFIG_RING_BUFFER=y
1682CONFIG_EVENT_TRACING=y 1742CONFIG_EVENT_TRACING=y
1683CONFIG_CONTEXT_SWITCH_TRACER=y 1743CONFIG_CONTEXT_SWITCH_TRACER=y
1744CONFIG_RING_BUFFER_ALLOW_SWAP=y
1684CONFIG_TRACING=y 1745CONFIG_TRACING=y
1685CONFIG_GENERIC_TRACER=y 1746CONFIG_GENERIC_TRACER=y
1686CONFIG_TRACING_SUPPORT=y 1747CONFIG_TRACING_SUPPORT=y
@@ -1688,6 +1749,7 @@ CONFIG_FTRACE=y
1688# CONFIG_FUNCTION_TRACER is not set 1749# CONFIG_FUNCTION_TRACER is not set
1689# CONFIG_IRQSOFF_TRACER is not set 1750# CONFIG_IRQSOFF_TRACER is not set
1690# CONFIG_SCHED_TRACER is not set 1751# CONFIG_SCHED_TRACER is not set
1752# CONFIG_FTRACE_SYSCALLS is not set
1691# CONFIG_BOOT_TRACER is not set 1753# CONFIG_BOOT_TRACER is not set
1692CONFIG_BRANCH_PROFILE_NONE=y 1754CONFIG_BRANCH_PROFILE_NONE=y
1693# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set 1755# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
@@ -1706,6 +1768,7 @@ CONFIG_HAVE_ARCH_KGDB=y
1706# CONFIG_DEBUG_STACK_USAGE is not set 1768# CONFIG_DEBUG_STACK_USAGE is not set
1707# CONFIG_DEBUG_DCFLUSH is not set 1769# CONFIG_DEBUG_DCFLUSH is not set
1708# CONFIG_STACK_DEBUG is not set 1770# CONFIG_STACK_DEBUG is not set
1771# CONFIG_DEBUG_STRICT_USER_COPY_CHECKS is not set
1709 1772
1710# 1773#
1711# Security options 1774# Security options
@@ -1714,11 +1777,17 @@ CONFIG_KEYS=y
1714# CONFIG_KEYS_DEBUG_PROC_KEYS is not set 1777# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
1715# CONFIG_SECURITY is not set 1778# CONFIG_SECURITY is not set
1716# CONFIG_SECURITYFS is not set 1779# CONFIG_SECURITYFS is not set
1717# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1780# CONFIG_DEFAULT_SECURITY_SELINUX is not set
1781# CONFIG_DEFAULT_SECURITY_SMACK is not set
1782# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
1783CONFIG_DEFAULT_SECURITY_DAC=y
1784CONFIG_DEFAULT_SECURITY=""
1718CONFIG_XOR_BLOCKS=m 1785CONFIG_XOR_BLOCKS=m
1719CONFIG_ASYNC_CORE=m 1786CONFIG_ASYNC_CORE=m
1720CONFIG_ASYNC_MEMCPY=m 1787CONFIG_ASYNC_MEMCPY=m
1721CONFIG_ASYNC_XOR=m 1788CONFIG_ASYNC_XOR=m
1789CONFIG_ASYNC_PQ=m
1790CONFIG_ASYNC_RAID6_RECOV=m
1722CONFIG_CRYPTO=y 1791CONFIG_CRYPTO=y
1723 1792
1724# 1793#
diff --git a/arch/sparc/include/asm/io_32.h b/arch/sparc/include/asm/io_32.h
index 93fe21e02c86..679c7504625a 100644
--- a/arch/sparc/include/asm/io_32.h
+++ b/arch/sparc/include/asm/io_32.h
@@ -8,7 +8,7 @@
8#include <asm/page.h> /* IO address mapping routines need this */ 8#include <asm/page.h> /* IO address mapping routines need this */
9#include <asm/system.h> 9#include <asm/system.h>
10 10
11#define page_to_phys(page) (((page) - mem_map) << PAGE_SHIFT) 11#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
12 12
13static inline u32 flip_dword (u32 l) 13static inline u32 flip_dword (u32 l)
14{ 14{
diff --git a/arch/sparc/include/asm/page_32.h b/arch/sparc/include/asm/page_32.h
index f72080bdda94..156707b0f18d 100644
--- a/arch/sparc/include/asm/page_32.h
+++ b/arch/sparc/include/asm/page_32.h
@@ -143,7 +143,7 @@ extern unsigned long pfn_base;
143#define phys_to_virt __va 143#define phys_to_virt __va
144 144
145#define ARCH_PFN_OFFSET (pfn_base) 145#define ARCH_PFN_OFFSET (pfn_base)
146#define virt_to_page(kaddr) (mem_map + ((((unsigned long)(kaddr)-PAGE_OFFSET)>>PAGE_SHIFT))) 146#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
147 147
148#define pfn_valid(pfn) (((pfn) >= (pfn_base)) && (((pfn)-(pfn_base)) < max_mapnr)) 148#define pfn_valid(pfn) (((pfn) >= (pfn_base)) && (((pfn)-(pfn_base)) < max_mapnr))
149#define virt_addr_valid(kaddr) ((((unsigned long)(kaddr)-PAGE_OFFSET)>>PAGE_SHIFT) < max_mapnr) 149#define virt_addr_valid(kaddr) ((((unsigned long)(kaddr)-PAGE_OFFSET)>>PAGE_SHIFT) < max_mapnr)
diff --git a/arch/sparc/include/asm/param.h b/arch/sparc/include/asm/param.h
index 9836d9a3cb9a..0bc356bf8c50 100644
--- a/arch/sparc/include/asm/param.h
+++ b/arch/sparc/include/asm/param.h
@@ -1,22 +1,7 @@
1#ifndef _ASMSPARC_PARAM_H 1#ifndef _ASMSPARC_PARAM_H
2#define _ASMSPARC_PARAM_H 2#define _ASMSPARC_PARAM_H
3 3
4#ifdef __KERNEL__
5# define HZ CONFIG_HZ /* Internal kernel timer frequency */
6# define USER_HZ 100 /* .. some user interfaces are in "ticks" */
7# define CLOCKS_PER_SEC (USER_HZ)
8#endif
9
10#ifndef HZ
11#define HZ 100
12#endif
13
14#define EXEC_PAGESIZE 8192 /* Thanks for sun4's we carry baggage... */ 4#define EXEC_PAGESIZE 8192 /* Thanks for sun4's we carry baggage... */
5#include <asm-generic/param.h>
15 6
16#ifndef NOGROUP 7#endif /* _ASMSPARC_PARAM_H */
17#define NOGROUP (-1)
18#endif
19
20#define MAXHOSTNAMELEN 64 /* max length of hostname */
21
22#endif
diff --git a/arch/sparc/include/asm/timex_32.h b/arch/sparc/include/asm/timex_32.h
index b6ccdb0d6f7d..a254750e4c03 100644
--- a/arch/sparc/include/asm/timex_32.h
+++ b/arch/sparc/include/asm/timex_32.h
@@ -12,4 +12,5 @@
12typedef unsigned long cycles_t; 12typedef unsigned long cycles_t;
13#define get_cycles() (0) 13#define get_cycles() (0)
14 14
15extern u32 (*do_arch_gettimeoffset)(void);
15#endif 16#endif
diff --git a/arch/sparc/include/asm/topology_64.h b/arch/sparc/include/asm/topology_64.h
index 600a79035fa1..1c79f32734a0 100644
--- a/arch/sparc/include/asm/topology_64.h
+++ b/arch/sparc/include/asm/topology_64.h
@@ -12,7 +12,9 @@ static inline int cpu_to_node(int cpu)
12 12
13#define parent_node(node) (node) 13#define parent_node(node) (node)
14 14
15#define cpumask_of_node(node) (&numa_cpumask_lookup_table[node]) 15#define cpumask_of_node(node) ((node) == -1 ? \
16 cpu_all_mask : \
17 &numa_cpumask_lookup_table[node])
16 18
17struct pci_bus; 19struct pci_bus;
18#ifdef CONFIG_PCI 20#ifdef CONFIG_PCI
diff --git a/arch/sparc/include/asm/uaccess_32.h b/arch/sparc/include/asm/uaccess_32.h
index 489d2ba92bcb..25f1d10155e8 100644
--- a/arch/sparc/include/asm/uaccess_32.h
+++ b/arch/sparc/include/asm/uaccess_32.h
@@ -274,7 +274,7 @@ static inline unsigned long copy_from_user(void *to, const void __user *from, un
274 274
275 if (unlikely(sz != -1 && sz < n)) { 275 if (unlikely(sz != -1 && sz < n)) {
276 copy_from_user_overflow(); 276 copy_from_user_overflow();
277 return -EFAULT; 277 return n;
278 } 278 }
279 279
280 if (n && __access_ok((unsigned long) from, n)) 280 if (n && __access_ok((unsigned long) from, n))
diff --git a/arch/sparc/include/asm/uaccess_64.h b/arch/sparc/include/asm/uaccess_64.h
index dbc141660994..2406788bfe5f 100644
--- a/arch/sparc/include/asm/uaccess_64.h
+++ b/arch/sparc/include/asm/uaccess_64.h
@@ -221,8 +221,8 @@ extern unsigned long copy_from_user_fixup(void *to, const void __user *from,
221static inline unsigned long __must_check 221static inline unsigned long __must_check
222copy_from_user(void *to, const void __user *from, unsigned long size) 222copy_from_user(void *to, const void __user *from, unsigned long size)
223{ 223{
224 unsigned long ret = (unsigned long) -EFAULT;
225 int sz = __compiletime_object_size(to); 224 int sz = __compiletime_object_size(to);
225 unsigned long ret = size;
226 226
227 if (likely(sz == -1 || sz >= size)) { 227 if (likely(sz == -1 || sz >= size)) {
228 ret = ___copy_from_user(to, from, size); 228 ret = ___copy_from_user(to, from, size);
diff --git a/arch/sparc/kernel/central.c b/arch/sparc/kernel/central.c
index f3b5466c389c..4589ca33220f 100644
--- a/arch/sparc/kernel/central.c
+++ b/arch/sparc/kernel/central.c
@@ -99,7 +99,7 @@ static int __devinit clock_board_probe(struct of_device *op,
99 99
100 p->leds_resource.start = (unsigned long) 100 p->leds_resource.start = (unsigned long)
101 (p->clock_regs + CLOCK_CTRL); 101 (p->clock_regs + CLOCK_CTRL);
102 p->leds_resource.end = p->leds_resource.end; 102 p->leds_resource.end = p->leds_resource.start;
103 p->leds_resource.name = "leds"; 103 p->leds_resource.name = "leds";
104 104
105 p->leds_pdev.name = "sunfire-clockboard-leds"; 105 p->leds_pdev.name = "sunfire-clockboard-leds";
@@ -194,7 +194,7 @@ static int __devinit fhc_probe(struct of_device *op,
194 if (!p->central) { 194 if (!p->central) {
195 p->leds_resource.start = (unsigned long) 195 p->leds_resource.start = (unsigned long)
196 (p->pregs + FHC_PREGS_CTRL); 196 (p->pregs + FHC_PREGS_CTRL);
197 p->leds_resource.end = p->leds_resource.end; 197 p->leds_resource.end = p->leds_resource.start;
198 p->leds_resource.name = "leds"; 198 p->leds_resource.name = "leds";
199 199
200 p->leds_pdev.name = "sunfire-fhc-leds"; 200 p->leds_pdev.name = "sunfire-fhc-leds";
diff --git a/arch/sparc/kernel/irq_64.c b/arch/sparc/kernel/irq_64.c
index 8d6882bb480a..f2179cce1e4d 100644
--- a/arch/sparc/kernel/irq_64.c
+++ b/arch/sparc/kernel/irq_64.c
@@ -250,12 +250,12 @@ struct irq_handler_data {
250}; 250};
251 251
252#ifdef CONFIG_SMP 252#ifdef CONFIG_SMP
253static int irq_choose_cpu(unsigned int virt_irq) 253static int irq_choose_cpu(unsigned int virt_irq, const struct cpumask *affinity)
254{ 254{
255 cpumask_t mask; 255 cpumask_t mask;
256 int cpuid; 256 int cpuid;
257 257
258 cpumask_copy(&mask, irq_desc[virt_irq].affinity); 258 cpumask_copy(&mask, affinity);
259 if (cpus_equal(mask, cpu_online_map)) { 259 if (cpus_equal(mask, cpu_online_map)) {
260 cpuid = map_to_cpu(virt_irq); 260 cpuid = map_to_cpu(virt_irq);
261 } else { 261 } else {
@@ -268,7 +268,7 @@ static int irq_choose_cpu(unsigned int virt_irq)
268 return cpuid; 268 return cpuid;
269} 269}
270#else 270#else
271static int irq_choose_cpu(unsigned int virt_irq) 271static int irq_choose_cpu(unsigned int virt_irq, const struct cpumask *affinity)
272{ 272{
273 return real_hard_smp_processor_id(); 273 return real_hard_smp_processor_id();
274} 274}
@@ -282,7 +282,8 @@ static void sun4u_irq_enable(unsigned int virt_irq)
282 unsigned long cpuid, imap, val; 282 unsigned long cpuid, imap, val;
283 unsigned int tid; 283 unsigned int tid;
284 284
285 cpuid = irq_choose_cpu(virt_irq); 285 cpuid = irq_choose_cpu(virt_irq,
286 irq_desc[virt_irq].affinity);
286 imap = data->imap; 287 imap = data->imap;
287 288
288 tid = sun4u_compute_tid(imap, cpuid); 289 tid = sun4u_compute_tid(imap, cpuid);
@@ -299,7 +300,24 @@ static void sun4u_irq_enable(unsigned int virt_irq)
299static int sun4u_set_affinity(unsigned int virt_irq, 300static int sun4u_set_affinity(unsigned int virt_irq,
300 const struct cpumask *mask) 301 const struct cpumask *mask)
301{ 302{
302 sun4u_irq_enable(virt_irq); 303 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
304
305 if (likely(data)) {
306 unsigned long cpuid, imap, val;
307 unsigned int tid;
308
309 cpuid = irq_choose_cpu(virt_irq, mask);
310 imap = data->imap;
311
312 tid = sun4u_compute_tid(imap, cpuid);
313
314 val = upa_readq(imap);
315 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
316 IMAP_AID_SAFARI | IMAP_NID_SAFARI);
317 val |= tid | IMAP_VALID;
318 upa_writeq(val, imap);
319 upa_writeq(ICLR_IDLE, data->iclr);
320 }
303 321
304 return 0; 322 return 0;
305} 323}
@@ -340,7 +358,8 @@ static void sun4u_irq_eoi(unsigned int virt_irq)
340static void sun4v_irq_enable(unsigned int virt_irq) 358static void sun4v_irq_enable(unsigned int virt_irq)
341{ 359{
342 unsigned int ino = virt_irq_table[virt_irq].dev_ino; 360 unsigned int ino = virt_irq_table[virt_irq].dev_ino;
343 unsigned long cpuid = irq_choose_cpu(virt_irq); 361 unsigned long cpuid = irq_choose_cpu(virt_irq,
362 irq_desc[virt_irq].affinity);
344 int err; 363 int err;
345 364
346 err = sun4v_intr_settarget(ino, cpuid); 365 err = sun4v_intr_settarget(ino, cpuid);
@@ -361,7 +380,7 @@ static int sun4v_set_affinity(unsigned int virt_irq,
361 const struct cpumask *mask) 380 const struct cpumask *mask)
362{ 381{
363 unsigned int ino = virt_irq_table[virt_irq].dev_ino; 382 unsigned int ino = virt_irq_table[virt_irq].dev_ino;
364 unsigned long cpuid = irq_choose_cpu(virt_irq); 383 unsigned long cpuid = irq_choose_cpu(virt_irq, mask);
365 int err; 384 int err;
366 385
367 err = sun4v_intr_settarget(ino, cpuid); 386 err = sun4v_intr_settarget(ino, cpuid);
@@ -403,7 +422,7 @@ static void sun4v_virq_enable(unsigned int virt_irq)
403 unsigned long cpuid, dev_handle, dev_ino; 422 unsigned long cpuid, dev_handle, dev_ino;
404 int err; 423 int err;
405 424
406 cpuid = irq_choose_cpu(virt_irq); 425 cpuid = irq_choose_cpu(virt_irq, irq_desc[virt_irq].affinity);
407 426
408 dev_handle = virt_irq_table[virt_irq].dev_handle; 427 dev_handle = virt_irq_table[virt_irq].dev_handle;
409 dev_ino = virt_irq_table[virt_irq].dev_ino; 428 dev_ino = virt_irq_table[virt_irq].dev_ino;
@@ -433,7 +452,7 @@ static int sun4v_virt_set_affinity(unsigned int virt_irq,
433 unsigned long cpuid, dev_handle, dev_ino; 452 unsigned long cpuid, dev_handle, dev_ino;
434 int err; 453 int err;
435 454
436 cpuid = irq_choose_cpu(virt_irq); 455 cpuid = irq_choose_cpu(virt_irq, mask);
437 456
438 dev_handle = virt_irq_table[virt_irq].dev_handle; 457 dev_handle = virt_irq_table[virt_irq].dev_handle;
439 dev_ino = virt_irq_table[virt_irq].dev_ino; 458 dev_ino = virt_irq_table[virt_irq].dev_ino;
diff --git a/arch/sparc/kernel/pcic.c b/arch/sparc/kernel/pcic.c
index 85e7037429b9..4e2724ec2bb6 100644
--- a/arch/sparc/kernel/pcic.c
+++ b/arch/sparc/kernel/pcic.c
@@ -30,6 +30,7 @@
30#include <asm/oplib.h> 30#include <asm/oplib.h>
31#include <asm/prom.h> 31#include <asm/prom.h>
32#include <asm/pcic.h> 32#include <asm/pcic.h>
33#include <asm/timex.h>
33#include <asm/timer.h> 34#include <asm/timer.h>
34#include <asm/uaccess.h> 35#include <asm/uaccess.h>
35#include <asm/irq_regs.h> 36#include <asm/irq_regs.h>
@@ -163,8 +164,6 @@ void __iomem *pcic_regs;
163volatile int pcic_speculative; 164volatile int pcic_speculative;
164volatile int pcic_trapped; 165volatile int pcic_trapped;
165 166
166static void pci_do_gettimeofday(struct timeval *tv);
167static int pci_do_settimeofday(struct timespec *tv);
168 167
169#define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (((unsigned int)bus) << 16) | (((unsigned int)device_fn) << 8) | (where & ~3)) 168#define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (((unsigned int)bus) << 16) | (((unsigned int)device_fn) << 8) | (where & ~3))
170 169
@@ -716,19 +715,27 @@ static irqreturn_t pcic_timer_handler (int irq, void *h)
716#define USECS_PER_JIFFY 10000 /* We have 100HZ "standard" timer for sparc */ 715#define USECS_PER_JIFFY 10000 /* We have 100HZ "standard" timer for sparc */
717#define TICK_TIMER_LIMIT ((100*1000000/4)/100) 716#define TICK_TIMER_LIMIT ((100*1000000/4)/100)
718 717
718u32 pci_gettimeoffset(void)
719{
720 /*
721 * We divide all by 100
722 * to have microsecond resolution and to avoid overflow
723 */
724 unsigned long count =
725 readl(pcic0.pcic_regs+PCI_SYS_COUNTER) & ~PCI_SYS_COUNTER_OVERFLOW;
726 count = ((count/100)*USECS_PER_JIFFY) / (TICK_TIMER_LIMIT/100);
727 return count * 1000;
728}
729
730
719void __init pci_time_init(void) 731void __init pci_time_init(void)
720{ 732{
721 struct linux_pcic *pcic = &pcic0; 733 struct linux_pcic *pcic = &pcic0;
722 unsigned long v; 734 unsigned long v;
723 int timer_irq, irq; 735 int timer_irq, irq;
724 736
725 /* A hack until do_gettimeofday prototype is moved to arch specific headers 737 do_arch_gettimeoffset = pci_gettimeoffset;
726 and btfixupped. Patch do_gettimeofday with ba pci_do_gettimeofday; nop */ 738
727 ((unsigned int *)do_gettimeofday)[0] =
728 0x10800000 | ((((unsigned long)pci_do_gettimeofday -
729 (unsigned long)do_gettimeofday) >> 2) & 0x003fffff);
730 ((unsigned int *)do_gettimeofday)[1] = 0x01000000;
731 BTFIXUPSET_CALL(bus_do_settimeofday, pci_do_settimeofday, BTFIXUPCALL_NORM);
732 btfixup(); 739 btfixup();
733 740
734 writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT); 741 writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT);
@@ -746,84 +753,6 @@ void __init pci_time_init(void)
746 local_irq_enable(); 753 local_irq_enable();
747} 754}
748 755
749static inline unsigned long do_gettimeoffset(void)
750{
751 /*
752 * We divide all by 100
753 * to have microsecond resolution and to avoid overflow
754 */
755 unsigned long count =
756 readl(pcic0.pcic_regs+PCI_SYS_COUNTER) & ~PCI_SYS_COUNTER_OVERFLOW;
757 count = ((count/100)*USECS_PER_JIFFY) / (TICK_TIMER_LIMIT/100);
758 return count;
759}
760
761static void pci_do_gettimeofday(struct timeval *tv)
762{
763 unsigned long flags;
764 unsigned long seq;
765 unsigned long usec, sec;
766 unsigned long max_ntp_tick = tick_usec - tickadj;
767
768 do {
769 seq = read_seqbegin_irqsave(&xtime_lock, flags);
770 usec = do_gettimeoffset();
771
772 /*
773 * If time_adjust is negative then NTP is slowing the clock
774 * so make sure not to go into next possible interval.
775 * Better to lose some accuracy than have time go backwards..
776 */
777 if (unlikely(time_adjust < 0))
778 usec = min(usec, max_ntp_tick);
779
780 sec = xtime.tv_sec;
781 usec += (xtime.tv_nsec / 1000);
782 } while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
783
784 while (usec >= 1000000) {
785 usec -= 1000000;
786 sec++;
787 }
788
789 tv->tv_sec = sec;
790 tv->tv_usec = usec;
791}
792
793static int pci_do_settimeofday(struct timespec *tv)
794{
795 if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC)
796 return -EINVAL;
797
798 /*
799 * This is revolting. We need to set "xtime" correctly. However, the
800 * value in this location is the value at the most recent update of
801 * wall time. Discover what correction gettimeofday() would have
802 * made, and then undo it!
803 */
804 tv->tv_nsec -= 1000 * do_gettimeoffset();
805 while (tv->tv_nsec < 0) {
806 tv->tv_nsec += NSEC_PER_SEC;
807 tv->tv_sec--;
808 }
809
810 wall_to_monotonic.tv_sec += xtime.tv_sec - tv->tv_sec;
811 wall_to_monotonic.tv_nsec += xtime.tv_nsec - tv->tv_nsec;
812
813 if (wall_to_monotonic.tv_nsec > NSEC_PER_SEC) {
814 wall_to_monotonic.tv_nsec -= NSEC_PER_SEC;
815 wall_to_monotonic.tv_sec++;
816 }
817 if (wall_to_monotonic.tv_nsec < 0) {
818 wall_to_monotonic.tv_nsec += NSEC_PER_SEC;
819 wall_to_monotonic.tv_sec--;
820 }
821
822 xtime.tv_sec = tv->tv_sec;
823 xtime.tv_nsec = tv->tv_nsec;
824 ntp_clear();
825 return 0;
826}
827 756
828#if 0 757#if 0
829static void watchdog_reset() { 758static void watchdog_reset() {
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index 198fb4e79ba2..e856456ec02f 100644
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -1,6 +1,6 @@
1/* Performance event support for sparc64. 1/* Performance event support for sparc64.
2 * 2 *
3 * Copyright (C) 2009 David S. Miller <davem@davemloft.net> 3 * Copyright (C) 2009, 2010 David S. Miller <davem@davemloft.net>
4 * 4 *
5 * This code is based almost entirely upon the x86 perf event 5 * This code is based almost entirely upon the x86 perf event
6 * code, which is: 6 * code, which is:
@@ -18,11 +18,15 @@
18#include <linux/kdebug.h> 18#include <linux/kdebug.h>
19#include <linux/mutex.h> 19#include <linux/mutex.h>
20 20
21#include <asm/stacktrace.h>
21#include <asm/cpudata.h> 22#include <asm/cpudata.h>
23#include <asm/uaccess.h>
22#include <asm/atomic.h> 24#include <asm/atomic.h>
23#include <asm/nmi.h> 25#include <asm/nmi.h>
24#include <asm/pcr.h> 26#include <asm/pcr.h>
25 27
28#include "kstack.h"
29
26/* Sparc64 chips have two performance counters, 32-bits each, with 30/* Sparc64 chips have two performance counters, 32-bits each, with
27 * overflow interrupts generated on transition from 0xffffffff to 0. 31 * overflow interrupts generated on transition from 0xffffffff to 0.
28 * The counters are accessed in one go using a 64-bit register. 32 * The counters are accessed in one go using a 64-bit register.
@@ -51,16 +55,49 @@
51 55
52#define PIC_UPPER_INDEX 0 56#define PIC_UPPER_INDEX 0
53#define PIC_LOWER_INDEX 1 57#define PIC_LOWER_INDEX 1
58#define PIC_NO_INDEX -1
54 59
55struct cpu_hw_events { 60struct cpu_hw_events {
56 struct perf_event *events[MAX_HWEVENTS]; 61 /* Number of events currently scheduled onto this cpu.
57 unsigned long used_mask[BITS_TO_LONGS(MAX_HWEVENTS)]; 62 * This tells how many entries in the arrays below
58 unsigned long active_mask[BITS_TO_LONGS(MAX_HWEVENTS)]; 63 * are valid.
64 */
65 int n_events;
66
67 /* Number of new events added since the last hw_perf_disable().
68 * This works because the perf event layer always adds new
69 * events inside of a perf_{disable,enable}() sequence.
70 */
71 int n_added;
72
73 /* Array of events current scheduled on this cpu. */
74 struct perf_event *event[MAX_HWEVENTS];
75
76 /* Array of encoded longs, specifying the %pcr register
77 * encoding and the mask of PIC counters this even can
78 * be scheduled on. See perf_event_encode() et al.
79 */
80 unsigned long events[MAX_HWEVENTS];
81
82 /* The current counter index assigned to an event. When the
83 * event hasn't been programmed into the cpu yet, this will
84 * hold PIC_NO_INDEX. The event->hw.idx value tells us where
85 * we ought to schedule the event.
86 */
87 int current_idx[MAX_HWEVENTS];
88
89 /* Software copy of %pcr register on this cpu. */
59 u64 pcr; 90 u64 pcr;
91
92 /* Enabled/disable state. */
60 int enabled; 93 int enabled;
61}; 94};
62DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, }; 95DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, };
63 96
97/* An event map describes the characteristics of a performance
98 * counter event. In particular it gives the encoding as well as
99 * a mask telling which counters the event can be measured on.
100 */
64struct perf_event_map { 101struct perf_event_map {
65 u16 encoding; 102 u16 encoding;
66 u8 pic_mask; 103 u8 pic_mask;
@@ -69,15 +106,20 @@ struct perf_event_map {
69#define PIC_LOWER 0x02 106#define PIC_LOWER 0x02
70}; 107};
71 108
109/* Encode a perf_event_map entry into a long. */
72static unsigned long perf_event_encode(const struct perf_event_map *pmap) 110static unsigned long perf_event_encode(const struct perf_event_map *pmap)
73{ 111{
74 return ((unsigned long) pmap->encoding << 16) | pmap->pic_mask; 112 return ((unsigned long) pmap->encoding << 16) | pmap->pic_mask;
75} 113}
76 114
77static void perf_event_decode(unsigned long val, u16 *enc, u8 *msk) 115static u8 perf_event_get_msk(unsigned long val)
78{ 116{
79 *msk = val & 0xff; 117 return val & 0xff;
80 *enc = val >> 16; 118}
119
120static u64 perf_event_get_enc(unsigned long val)
121{
122 return val >> 16;
81} 123}
82 124
83#define C(x) PERF_COUNT_HW_CACHE_##x 125#define C(x) PERF_COUNT_HW_CACHE_##x
@@ -491,53 +533,6 @@ static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw
491 pcr_ops->write(cpuc->pcr); 533 pcr_ops->write(cpuc->pcr);
492} 534}
493 535
494void hw_perf_enable(void)
495{
496 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
497 u64 val;
498 int i;
499
500 if (cpuc->enabled)
501 return;
502
503 cpuc->enabled = 1;
504 barrier();
505
506 val = cpuc->pcr;
507
508 for (i = 0; i < MAX_HWEVENTS; i++) {
509 struct perf_event *cp = cpuc->events[i];
510 struct hw_perf_event *hwc;
511
512 if (!cp)
513 continue;
514 hwc = &cp->hw;
515 val |= hwc->config_base;
516 }
517
518 cpuc->pcr = val;
519
520 pcr_ops->write(cpuc->pcr);
521}
522
523void hw_perf_disable(void)
524{
525 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
526 u64 val;
527
528 if (!cpuc->enabled)
529 return;
530
531 cpuc->enabled = 0;
532
533 val = cpuc->pcr;
534 val &= ~(PCR_UTRACE | PCR_STRACE |
535 sparc_pmu->hv_bit | sparc_pmu->irq_bit);
536 cpuc->pcr = val;
537
538 pcr_ops->write(cpuc->pcr);
539}
540
541static u32 read_pmc(int idx) 536static u32 read_pmc(int idx)
542{ 537{
543 u64 val; 538 u64 val;
@@ -566,6 +561,30 @@ static void write_pmc(int idx, u64 val)
566 write_pic(pic); 561 write_pic(pic);
567} 562}
568 563
564static u64 sparc_perf_event_update(struct perf_event *event,
565 struct hw_perf_event *hwc, int idx)
566{
567 int shift = 64 - 32;
568 u64 prev_raw_count, new_raw_count;
569 s64 delta;
570
571again:
572 prev_raw_count = atomic64_read(&hwc->prev_count);
573 new_raw_count = read_pmc(idx);
574
575 if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
576 new_raw_count) != prev_raw_count)
577 goto again;
578
579 delta = (new_raw_count << shift) - (prev_raw_count << shift);
580 delta >>= shift;
581
582 atomic64_add(delta, &event->count);
583 atomic64_sub(delta, &hwc->period_left);
584
585 return new_raw_count;
586}
587
569static int sparc_perf_event_set_period(struct perf_event *event, 588static int sparc_perf_event_set_period(struct perf_event *event,
570 struct hw_perf_event *hwc, int idx) 589 struct hw_perf_event *hwc, int idx)
571{ 590{
@@ -598,81 +617,166 @@ static int sparc_perf_event_set_period(struct perf_event *event,
598 return ret; 617 return ret;
599} 618}
600 619
601static int sparc_pmu_enable(struct perf_event *event) 620/* If performance event entries have been added, move existing
621 * events around (if necessary) and then assign new entries to
622 * counters.
623 */
624static u64 maybe_change_configuration(struct cpu_hw_events *cpuc, u64 pcr)
602{ 625{
603 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 626 int i;
604 struct hw_perf_event *hwc = &event->hw;
605 int idx = hwc->idx;
606 627
607 if (test_and_set_bit(idx, cpuc->used_mask)) 628 if (!cpuc->n_added)
608 return -EAGAIN; 629 goto out;
609 630
610 sparc_pmu_disable_event(cpuc, hwc, idx); 631 /* Read in the counters which are moving. */
632 for (i = 0; i < cpuc->n_events; i++) {
633 struct perf_event *cp = cpuc->event[i];
611 634
612 cpuc->events[idx] = event; 635 if (cpuc->current_idx[i] != PIC_NO_INDEX &&
613 set_bit(idx, cpuc->active_mask); 636 cpuc->current_idx[i] != cp->hw.idx) {
637 sparc_perf_event_update(cp, &cp->hw,
638 cpuc->current_idx[i]);
639 cpuc->current_idx[i] = PIC_NO_INDEX;
640 }
641 }
614 642
615 sparc_perf_event_set_period(event, hwc, idx); 643 /* Assign to counters all unassigned events. */
616 sparc_pmu_enable_event(cpuc, hwc, idx); 644 for (i = 0; i < cpuc->n_events; i++) {
617 perf_event_update_userpage(event); 645 struct perf_event *cp = cpuc->event[i];
618 return 0; 646 struct hw_perf_event *hwc = &cp->hw;
647 int idx = hwc->idx;
648 u64 enc;
649
650 if (cpuc->current_idx[i] != PIC_NO_INDEX)
651 continue;
652
653 sparc_perf_event_set_period(cp, hwc, idx);
654 cpuc->current_idx[i] = idx;
655
656 enc = perf_event_get_enc(cpuc->events[i]);
657 pcr |= event_encoding(enc, idx);
658 }
659out:
660 return pcr;
619} 661}
620 662
621static u64 sparc_perf_event_update(struct perf_event *event, 663void hw_perf_enable(void)
622 struct hw_perf_event *hwc, int idx)
623{ 664{
624 int shift = 64 - 32; 665 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
625 u64 prev_raw_count, new_raw_count; 666 u64 pcr;
626 s64 delta;
627 667
628again: 668 if (cpuc->enabled)
629 prev_raw_count = atomic64_read(&hwc->prev_count); 669 return;
630 new_raw_count = read_pmc(idx);
631 670
632 if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, 671 cpuc->enabled = 1;
633 new_raw_count) != prev_raw_count) 672 barrier();
634 goto again;
635 673
636 delta = (new_raw_count << shift) - (prev_raw_count << shift); 674 pcr = cpuc->pcr;
637 delta >>= shift; 675 if (!cpuc->n_events) {
676 pcr = 0;
677 } else {
678 pcr = maybe_change_configuration(cpuc, pcr);
638 679
639 atomic64_add(delta, &event->count); 680 /* We require that all of the events have the same
640 atomic64_sub(delta, &hwc->period_left); 681 * configuration, so just fetch the settings from the
682 * first entry.
683 */
684 cpuc->pcr = pcr | cpuc->event[0]->hw.config_base;
685 }
641 686
642 return new_raw_count; 687 pcr_ops->write(cpuc->pcr);
688}
689
690void hw_perf_disable(void)
691{
692 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
693 u64 val;
694
695 if (!cpuc->enabled)
696 return;
697
698 cpuc->enabled = 0;
699 cpuc->n_added = 0;
700
701 val = cpuc->pcr;
702 val &= ~(PCR_UTRACE | PCR_STRACE |
703 sparc_pmu->hv_bit | sparc_pmu->irq_bit);
704 cpuc->pcr = val;
705
706 pcr_ops->write(cpuc->pcr);
643} 707}
644 708
645static void sparc_pmu_disable(struct perf_event *event) 709static void sparc_pmu_disable(struct perf_event *event)
646{ 710{
647 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 711 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
648 struct hw_perf_event *hwc = &event->hw; 712 struct hw_perf_event *hwc = &event->hw;
649 int idx = hwc->idx; 713 unsigned long flags;
714 int i;
650 715
651 clear_bit(idx, cpuc->active_mask); 716 local_irq_save(flags);
652 sparc_pmu_disable_event(cpuc, hwc, idx); 717 perf_disable();
718
719 for (i = 0; i < cpuc->n_events; i++) {
720 if (event == cpuc->event[i]) {
721 int idx = cpuc->current_idx[i];
722
723 /* Shift remaining entries down into
724 * the existing slot.
725 */
726 while (++i < cpuc->n_events) {
727 cpuc->event[i - 1] = cpuc->event[i];
728 cpuc->events[i - 1] = cpuc->events[i];
729 cpuc->current_idx[i - 1] =
730 cpuc->current_idx[i];
731 }
732
733 /* Absorb the final count and turn off the
734 * event.
735 */
736 sparc_pmu_disable_event(cpuc, hwc, idx);
737 barrier();
738 sparc_perf_event_update(event, hwc, idx);
653 739
654 barrier(); 740 perf_event_update_userpage(event);
655 741
656 sparc_perf_event_update(event, hwc, idx); 742 cpuc->n_events--;
657 cpuc->events[idx] = NULL; 743 break;
658 clear_bit(idx, cpuc->used_mask); 744 }
745 }
659 746
660 perf_event_update_userpage(event); 747 perf_enable();
748 local_irq_restore(flags);
749}
750
751static int active_event_index(struct cpu_hw_events *cpuc,
752 struct perf_event *event)
753{
754 int i;
755
756 for (i = 0; i < cpuc->n_events; i++) {
757 if (cpuc->event[i] == event)
758 break;
759 }
760 BUG_ON(i == cpuc->n_events);
761 return cpuc->current_idx[i];
661} 762}
662 763
663static void sparc_pmu_read(struct perf_event *event) 764static void sparc_pmu_read(struct perf_event *event)
664{ 765{
766 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
767 int idx = active_event_index(cpuc, event);
665 struct hw_perf_event *hwc = &event->hw; 768 struct hw_perf_event *hwc = &event->hw;
666 769
667 sparc_perf_event_update(event, hwc, hwc->idx); 770 sparc_perf_event_update(event, hwc, idx);
668} 771}
669 772
670static void sparc_pmu_unthrottle(struct perf_event *event) 773static void sparc_pmu_unthrottle(struct perf_event *event)
671{ 774{
672 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 775 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
776 int idx = active_event_index(cpuc, event);
673 struct hw_perf_event *hwc = &event->hw; 777 struct hw_perf_event *hwc = &event->hw;
674 778
675 sparc_pmu_enable_event(cpuc, hwc, hwc->idx); 779 sparc_pmu_enable_event(cpuc, hwc, idx);
676} 780}
677 781
678static atomic_t active_events = ATOMIC_INIT(0); 782static atomic_t active_events = ATOMIC_INIT(0);
@@ -750,43 +854,75 @@ static void hw_perf_event_destroy(struct perf_event *event)
750/* Make sure all events can be scheduled into the hardware at 854/* Make sure all events can be scheduled into the hardware at
751 * the same time. This is simplified by the fact that we only 855 * the same time. This is simplified by the fact that we only
752 * need to support 2 simultaneous HW events. 856 * need to support 2 simultaneous HW events.
857 *
858 * As a side effect, the evts[]->hw.idx values will be assigned
859 * on success. These are pending indexes. When the events are
860 * actually programmed into the chip, these values will propagate
861 * to the per-cpu cpuc->current_idx[] slots, see the code in
862 * maybe_change_configuration() for details.
753 */ 863 */
754static int sparc_check_constraints(unsigned long *events, int n_ev) 864static int sparc_check_constraints(struct perf_event **evts,
865 unsigned long *events, int n_ev)
755{ 866{
756 if (n_ev <= perf_max_events) { 867 u8 msk0 = 0, msk1 = 0;
757 u8 msk1, msk2; 868 int idx0 = 0;
758 u16 dummy; 869
759 870 /* This case is possible when we are invoked from
760 if (n_ev == 1) 871 * hw_perf_group_sched_in().
761 return 0; 872 */
762 BUG_ON(n_ev != 2); 873 if (!n_ev)
763 perf_event_decode(events[0], &dummy, &msk1); 874 return 0;
764 perf_event_decode(events[1], &dummy, &msk2); 875
765 876 if (n_ev > perf_max_events)
766 /* If both events can go on any counter, OK. */ 877 return -1;
767 if (msk1 == (PIC_UPPER | PIC_LOWER) && 878
768 msk2 == (PIC_UPPER | PIC_LOWER)) 879 msk0 = perf_event_get_msk(events[0]);
769 return 0; 880 if (n_ev == 1) {
770 881 if (msk0 & PIC_LOWER)
771 /* If one event is limited to a specific counter, 882 idx0 = 1;
772 * and the other can go on both, OK. 883 goto success;
773 */
774 if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) &&
775 msk2 == (PIC_UPPER | PIC_LOWER))
776 return 0;
777 if ((msk2 == PIC_UPPER || msk2 == PIC_LOWER) &&
778 msk1 == (PIC_UPPER | PIC_LOWER))
779 return 0;
780
781 /* If the events are fixed to different counters, OK. */
782 if ((msk1 == PIC_UPPER && msk2 == PIC_LOWER) ||
783 (msk1 == PIC_LOWER && msk2 == PIC_UPPER))
784 return 0;
785
786 /* Otherwise, there is a conflict. */
787 } 884 }
885 BUG_ON(n_ev != 2);
886 msk1 = perf_event_get_msk(events[1]);
887
888 /* If both events can go on any counter, OK. */
889 if (msk0 == (PIC_UPPER | PIC_LOWER) &&
890 msk1 == (PIC_UPPER | PIC_LOWER))
891 goto success;
788 892
893 /* If one event is limited to a specific counter,
894 * and the other can go on both, OK.
895 */
896 if ((msk0 == PIC_UPPER || msk0 == PIC_LOWER) &&
897 msk1 == (PIC_UPPER | PIC_LOWER)) {
898 if (msk0 & PIC_LOWER)
899 idx0 = 1;
900 goto success;
901 }
902
903 if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) &&
904 msk0 == (PIC_UPPER | PIC_LOWER)) {
905 if (msk1 & PIC_UPPER)
906 idx0 = 1;
907 goto success;
908 }
909
910 /* If the events are fixed to different counters, OK. */
911 if ((msk0 == PIC_UPPER && msk1 == PIC_LOWER) ||
912 (msk0 == PIC_LOWER && msk1 == PIC_UPPER)) {
913 if (msk0 & PIC_LOWER)
914 idx0 = 1;
915 goto success;
916 }
917
918 /* Otherwise, there is a conflict. */
789 return -1; 919 return -1;
920
921success:
922 evts[0]->hw.idx = idx0;
923 if (n_ev == 2)
924 evts[1]->hw.idx = idx0 ^ 1;
925 return 0;
790} 926}
791 927
792static int check_excludes(struct perf_event **evts, int n_prev, int n_new) 928static int check_excludes(struct perf_event **evts, int n_prev, int n_new)
@@ -818,7 +954,8 @@ static int check_excludes(struct perf_event **evts, int n_prev, int n_new)
818} 954}
819 955
820static int collect_events(struct perf_event *group, int max_count, 956static int collect_events(struct perf_event *group, int max_count,
821 struct perf_event *evts[], unsigned long *events) 957 struct perf_event *evts[], unsigned long *events,
958 int *current_idx)
822{ 959{
823 struct perf_event *event; 960 struct perf_event *event;
824 int n = 0; 961 int n = 0;
@@ -827,7 +964,8 @@ static int collect_events(struct perf_event *group, int max_count,
827 if (n >= max_count) 964 if (n >= max_count)
828 return -1; 965 return -1;
829 evts[n] = group; 966 evts[n] = group;
830 events[n++] = group->hw.event_base; 967 events[n] = group->hw.event_base;
968 current_idx[n++] = PIC_NO_INDEX;
831 } 969 }
832 list_for_each_entry(event, &group->sibling_list, group_entry) { 970 list_for_each_entry(event, &group->sibling_list, group_entry) {
833 if (!is_software_event(event) && 971 if (!is_software_event(event) &&
@@ -835,20 +973,100 @@ static int collect_events(struct perf_event *group, int max_count,
835 if (n >= max_count) 973 if (n >= max_count)
836 return -1; 974 return -1;
837 evts[n] = event; 975 evts[n] = event;
838 events[n++] = event->hw.event_base; 976 events[n] = event->hw.event_base;
977 current_idx[n++] = PIC_NO_INDEX;
839 } 978 }
840 } 979 }
841 return n; 980 return n;
842} 981}
843 982
983static void event_sched_in(struct perf_event *event, int cpu)
984{
985 event->state = PERF_EVENT_STATE_ACTIVE;
986 event->oncpu = cpu;
987 event->tstamp_running += event->ctx->time - event->tstamp_stopped;
988 if (is_software_event(event))
989 event->pmu->enable(event);
990}
991
992int hw_perf_group_sched_in(struct perf_event *group_leader,
993 struct perf_cpu_context *cpuctx,
994 struct perf_event_context *ctx, int cpu)
995{
996 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
997 struct perf_event *sub;
998 int n0, n;
999
1000 if (!sparc_pmu)
1001 return 0;
1002
1003 n0 = cpuc->n_events;
1004 n = collect_events(group_leader, perf_max_events - n0,
1005 &cpuc->event[n0], &cpuc->events[n0],
1006 &cpuc->current_idx[n0]);
1007 if (n < 0)
1008 return -EAGAIN;
1009 if (check_excludes(cpuc->event, n0, n))
1010 return -EINVAL;
1011 if (sparc_check_constraints(cpuc->event, cpuc->events, n + n0))
1012 return -EAGAIN;
1013 cpuc->n_events = n0 + n;
1014 cpuc->n_added += n;
1015
1016 cpuctx->active_oncpu += n;
1017 n = 1;
1018 event_sched_in(group_leader, cpu);
1019 list_for_each_entry(sub, &group_leader->sibling_list, group_entry) {
1020 if (sub->state != PERF_EVENT_STATE_OFF) {
1021 event_sched_in(sub, cpu);
1022 n++;
1023 }
1024 }
1025 ctx->nr_active += n;
1026
1027 return 1;
1028}
1029
1030static int sparc_pmu_enable(struct perf_event *event)
1031{
1032 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1033 int n0, ret = -EAGAIN;
1034 unsigned long flags;
1035
1036 local_irq_save(flags);
1037 perf_disable();
1038
1039 n0 = cpuc->n_events;
1040 if (n0 >= perf_max_events)
1041 goto out;
1042
1043 cpuc->event[n0] = event;
1044 cpuc->events[n0] = event->hw.event_base;
1045 cpuc->current_idx[n0] = PIC_NO_INDEX;
1046
1047 if (check_excludes(cpuc->event, n0, 1))
1048 goto out;
1049 if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1))
1050 goto out;
1051
1052 cpuc->n_events++;
1053 cpuc->n_added++;
1054
1055 ret = 0;
1056out:
1057 perf_enable();
1058 local_irq_restore(flags);
1059 return ret;
1060}
1061
844static int __hw_perf_event_init(struct perf_event *event) 1062static int __hw_perf_event_init(struct perf_event *event)
845{ 1063{
846 struct perf_event_attr *attr = &event->attr; 1064 struct perf_event_attr *attr = &event->attr;
847 struct perf_event *evts[MAX_HWEVENTS]; 1065 struct perf_event *evts[MAX_HWEVENTS];
848 struct hw_perf_event *hwc = &event->hw; 1066 struct hw_perf_event *hwc = &event->hw;
849 unsigned long events[MAX_HWEVENTS]; 1067 unsigned long events[MAX_HWEVENTS];
1068 int current_idx_dmy[MAX_HWEVENTS];
850 const struct perf_event_map *pmap; 1069 const struct perf_event_map *pmap;
851 u64 enc;
852 int n; 1070 int n;
853 1071
854 if (atomic_read(&nmi_active) < 0) 1072 if (atomic_read(&nmi_active) < 0)
@@ -865,10 +1083,7 @@ static int __hw_perf_event_init(struct perf_event *event)
865 } else 1083 } else
866 return -EOPNOTSUPP; 1084 return -EOPNOTSUPP;
867 1085
868 /* We save the enable bits in the config_base. So to 1086 /* We save the enable bits in the config_base. */
869 * turn off sampling just write 'config', and to enable
870 * things write 'config | config_base'.
871 */
872 hwc->config_base = sparc_pmu->irq_bit; 1087 hwc->config_base = sparc_pmu->irq_bit;
873 if (!attr->exclude_user) 1088 if (!attr->exclude_user)
874 hwc->config_base |= PCR_UTRACE; 1089 hwc->config_base |= PCR_UTRACE;
@@ -879,13 +1094,11 @@ static int __hw_perf_event_init(struct perf_event *event)
879 1094
880 hwc->event_base = perf_event_encode(pmap); 1095 hwc->event_base = perf_event_encode(pmap);
881 1096
882 enc = pmap->encoding;
883
884 n = 0; 1097 n = 0;
885 if (event->group_leader != event) { 1098 if (event->group_leader != event) {
886 n = collect_events(event->group_leader, 1099 n = collect_events(event->group_leader,
887 perf_max_events - 1, 1100 perf_max_events - 1,
888 evts, events); 1101 evts, events, current_idx_dmy);
889 if (n < 0) 1102 if (n < 0)
890 return -EINVAL; 1103 return -EINVAL;
891 } 1104 }
@@ -895,9 +1108,11 @@ static int __hw_perf_event_init(struct perf_event *event)
895 if (check_excludes(evts, n, 1)) 1108 if (check_excludes(evts, n, 1))
896 return -EINVAL; 1109 return -EINVAL;
897 1110
898 if (sparc_check_constraints(events, n + 1)) 1111 if (sparc_check_constraints(evts, events, n + 1))
899 return -EINVAL; 1112 return -EINVAL;
900 1113
1114 hwc->idx = PIC_NO_INDEX;
1115
901 /* Try to do all error checking before this point, as unwinding 1116 /* Try to do all error checking before this point, as unwinding
902 * state after grabbing the PMC is difficult. 1117 * state after grabbing the PMC is difficult.
903 */ 1118 */
@@ -910,15 +1125,6 @@ static int __hw_perf_event_init(struct perf_event *event)
910 atomic64_set(&hwc->period_left, hwc->sample_period); 1125 atomic64_set(&hwc->period_left, hwc->sample_period);
911 } 1126 }
912 1127
913 if (pmap->pic_mask & PIC_UPPER) {
914 hwc->idx = PIC_UPPER_INDEX;
915 enc <<= sparc_pmu->upper_shift;
916 } else {
917 hwc->idx = PIC_LOWER_INDEX;
918 enc <<= sparc_pmu->lower_shift;
919 }
920
921 hwc->config |= enc;
922 return 0; 1128 return 0;
923} 1129}
924 1130
@@ -968,7 +1174,7 @@ static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
968 struct perf_sample_data data; 1174 struct perf_sample_data data;
969 struct cpu_hw_events *cpuc; 1175 struct cpu_hw_events *cpuc;
970 struct pt_regs *regs; 1176 struct pt_regs *regs;
971 int idx; 1177 int i;
972 1178
973 if (!atomic_read(&active_events)) 1179 if (!atomic_read(&active_events))
974 return NOTIFY_DONE; 1180 return NOTIFY_DONE;
@@ -997,13 +1203,12 @@ static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
997 if (sparc_pmu->irq_bit) 1203 if (sparc_pmu->irq_bit)
998 pcr_ops->write(cpuc->pcr); 1204 pcr_ops->write(cpuc->pcr);
999 1205
1000 for (idx = 0; idx < MAX_HWEVENTS; idx++) { 1206 for (i = 0; i < cpuc->n_events; i++) {
1001 struct perf_event *event = cpuc->events[idx]; 1207 struct perf_event *event = cpuc->event[i];
1208 int idx = cpuc->current_idx[i];
1002 struct hw_perf_event *hwc; 1209 struct hw_perf_event *hwc;
1003 u64 val; 1210 u64 val;
1004 1211
1005 if (!test_bit(idx, cpuc->active_mask))
1006 continue;
1007 hwc = &event->hw; 1212 hwc = &event->hw;
1008 val = sparc_perf_event_update(event, hwc, idx); 1213 val = sparc_perf_event_update(event, hwc, idx);
1009 if (val & (1ULL << 31)) 1214 if (val & (1ULL << 31))
@@ -1055,10 +1260,122 @@ void __init init_hw_perf_events(void)
1055 1260
1056 pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type); 1261 pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type);
1057 1262
1058 /* All sparc64 PMUs currently have 2 events. But this simple 1263 /* All sparc64 PMUs currently have 2 events. */
1059 * driver only supports one active event at a time. 1264 perf_max_events = 2;
1060 */
1061 perf_max_events = 1;
1062 1265
1063 register_die_notifier(&perf_event_nmi_notifier); 1266 register_die_notifier(&perf_event_nmi_notifier);
1064} 1267}
1268
1269static inline void callchain_store(struct perf_callchain_entry *entry, u64 ip)
1270{
1271 if (entry->nr < PERF_MAX_STACK_DEPTH)
1272 entry->ip[entry->nr++] = ip;
1273}
1274
1275static void perf_callchain_kernel(struct pt_regs *regs,
1276 struct perf_callchain_entry *entry)
1277{
1278 unsigned long ksp, fp;
1279
1280 callchain_store(entry, PERF_CONTEXT_KERNEL);
1281 callchain_store(entry, regs->tpc);
1282
1283 ksp = regs->u_regs[UREG_I6];
1284 fp = ksp + STACK_BIAS;
1285 do {
1286 struct sparc_stackf *sf;
1287 struct pt_regs *regs;
1288 unsigned long pc;
1289
1290 if (!kstack_valid(current_thread_info(), fp))
1291 break;
1292
1293 sf = (struct sparc_stackf *) fp;
1294 regs = (struct pt_regs *) (sf + 1);
1295
1296 if (kstack_is_trap_frame(current_thread_info(), regs)) {
1297 if (user_mode(regs))
1298 break;
1299 pc = regs->tpc;
1300 fp = regs->u_regs[UREG_I6] + STACK_BIAS;
1301 } else {
1302 pc = sf->callers_pc;
1303 fp = (unsigned long)sf->fp + STACK_BIAS;
1304 }
1305 callchain_store(entry, pc);
1306 } while (entry->nr < PERF_MAX_STACK_DEPTH);
1307}
1308
1309static void perf_callchain_user_64(struct pt_regs *regs,
1310 struct perf_callchain_entry *entry)
1311{
1312 unsigned long ufp;
1313
1314 callchain_store(entry, PERF_CONTEXT_USER);
1315 callchain_store(entry, regs->tpc);
1316
1317 ufp = regs->u_regs[UREG_I6] + STACK_BIAS;
1318 do {
1319 struct sparc_stackf *usf, sf;
1320 unsigned long pc;
1321
1322 usf = (struct sparc_stackf *) ufp;
1323 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1324 break;
1325
1326 pc = sf.callers_pc;
1327 ufp = (unsigned long)sf.fp + STACK_BIAS;
1328 callchain_store(entry, pc);
1329 } while (entry->nr < PERF_MAX_STACK_DEPTH);
1330}
1331
1332static void perf_callchain_user_32(struct pt_regs *regs,
1333 struct perf_callchain_entry *entry)
1334{
1335 unsigned long ufp;
1336
1337 callchain_store(entry, PERF_CONTEXT_USER);
1338 callchain_store(entry, regs->tpc);
1339
1340 ufp = regs->u_regs[UREG_I6];
1341 do {
1342 struct sparc_stackf32 *usf, sf;
1343 unsigned long pc;
1344
1345 usf = (struct sparc_stackf32 *) ufp;
1346 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1347 break;
1348
1349 pc = sf.callers_pc;
1350 ufp = (unsigned long)sf.fp;
1351 callchain_store(entry, pc);
1352 } while (entry->nr < PERF_MAX_STACK_DEPTH);
1353}
1354
1355/* Like powerpc we can't get PMU interrupts within the PMU handler,
1356 * so no need for seperate NMI and IRQ chains as on x86.
1357 */
1358static DEFINE_PER_CPU(struct perf_callchain_entry, callchain);
1359
1360struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1361{
1362 struct perf_callchain_entry *entry = &__get_cpu_var(callchain);
1363
1364 entry->nr = 0;
1365 if (!user_mode(regs)) {
1366 stack_trace_flush();
1367 perf_callchain_kernel(regs, entry);
1368 if (current->mm)
1369 regs = task_pt_regs(current);
1370 else
1371 regs = NULL;
1372 }
1373 if (regs) {
1374 flushw_user();
1375 if (test_thread_flag(TIF_32BIT))
1376 perf_callchain_user_32(regs, entry);
1377 else
1378 perf_callchain_user_64(regs, entry);
1379 }
1380 return entry;
1381}
diff --git a/arch/sparc/kernel/sys_sparc_64.c b/arch/sparc/kernel/sys_sparc_64.c
index cfa0e19abe3b..d77f54316948 100644
--- a/arch/sparc/kernel/sys_sparc_64.c
+++ b/arch/sparc/kernel/sys_sparc_64.c
@@ -365,6 +365,7 @@ EXPORT_SYMBOL(get_fb_unmapped_area);
365void arch_pick_mmap_layout(struct mm_struct *mm) 365void arch_pick_mmap_layout(struct mm_struct *mm)
366{ 366{
367 unsigned long random_factor = 0UL; 367 unsigned long random_factor = 0UL;
368 unsigned long gap;
368 369
369 if (current->flags & PF_RANDOMIZE) { 370 if (current->flags & PF_RANDOMIZE) {
370 random_factor = get_random_int(); 371 random_factor = get_random_int();
@@ -379,9 +380,10 @@ void arch_pick_mmap_layout(struct mm_struct *mm)
379 * Fall back to the standard layout if the personality 380 * Fall back to the standard layout if the personality
380 * bit is set, or if the expected stack growth is unlimited: 381 * bit is set, or if the expected stack growth is unlimited:
381 */ 382 */
383 gap = rlimit(RLIMIT_STACK);
382 if (!test_thread_flag(TIF_32BIT) || 384 if (!test_thread_flag(TIF_32BIT) ||
383 (current->personality & ADDR_COMPAT_LAYOUT) || 385 (current->personality & ADDR_COMPAT_LAYOUT) ||
384 current->signal->rlim[RLIMIT_STACK].rlim_cur == RLIM_INFINITY || 386 gap == RLIM_INFINITY ||
385 sysctl_legacy_va_layout) { 387 sysctl_legacy_va_layout) {
386 mm->mmap_base = TASK_UNMAPPED_BASE + random_factor; 388 mm->mmap_base = TASK_UNMAPPED_BASE + random_factor;
387 mm->get_unmapped_area = arch_get_unmapped_area; 389 mm->get_unmapped_area = arch_get_unmapped_area;
@@ -389,9 +391,7 @@ void arch_pick_mmap_layout(struct mm_struct *mm)
389 } else { 391 } else {
390 /* We know it's 32-bit */ 392 /* We know it's 32-bit */
391 unsigned long task_size = STACK_TOP32; 393 unsigned long task_size = STACK_TOP32;
392 unsigned long gap;
393 394
394 gap = current->signal->rlim[RLIMIT_STACK].rlim_cur;
395 if (gap < 128 * 1024 * 1024) 395 if (gap < 128 * 1024 * 1024)
396 gap = 128 * 1024 * 1024; 396 gap = 128 * 1024 * 1024;
397 if (gap > (task_size / 6 * 5)) 397 if (gap > (task_size / 6 * 5))
diff --git a/arch/sparc/kernel/time_32.c b/arch/sparc/kernel/time_32.c
index 5b2f595fe65b..0d4c09b15efc 100644
--- a/arch/sparc/kernel/time_32.c
+++ b/arch/sparc/kernel/time_32.c
@@ -35,6 +35,7 @@
35#include <linux/platform_device.h> 35#include <linux/platform_device.h>
36 36
37#include <asm/oplib.h> 37#include <asm/oplib.h>
38#include <asm/timex.h>
38#include <asm/timer.h> 39#include <asm/timer.h>
39#include <asm/system.h> 40#include <asm/system.h>
40#include <asm/irq.h> 41#include <asm/irq.h>
@@ -51,7 +52,6 @@ DEFINE_SPINLOCK(rtc_lock);
51EXPORT_SYMBOL(rtc_lock); 52EXPORT_SYMBOL(rtc_lock);
52 53
53static int set_rtc_mmss(unsigned long); 54static int set_rtc_mmss(unsigned long);
54static int sbus_do_settimeofday(struct timespec *tv);
55 55
56unsigned long profile_pc(struct pt_regs *regs) 56unsigned long profile_pc(struct pt_regs *regs)
57{ 57{
@@ -76,6 +76,8 @@ EXPORT_SYMBOL(profile_pc);
76 76
77__volatile__ unsigned int *master_l10_counter; 77__volatile__ unsigned int *master_l10_counter;
78 78
79u32 (*do_arch_gettimeoffset)(void);
80
79/* 81/*
80 * timer_interrupt() needs to keep up the real-time clock, 82 * timer_interrupt() needs to keep up the real-time clock,
81 * as well as call the "do_timer()" routine every clocktick 83 * as well as call the "do_timer()" routine every clocktick
@@ -196,35 +198,14 @@ static int __init clock_init(void)
196{ 198{
197 return of_register_driver(&clock_driver, &of_platform_bus_type); 199 return of_register_driver(&clock_driver, &of_platform_bus_type);
198} 200}
199
200/* Must be after subsys_initcall() so that busses are probed. Must 201/* Must be after subsys_initcall() so that busses are probed. Must
201 * be before device_initcall() because things like the RTC driver 202 * be before device_initcall() because things like the RTC driver
202 * need to see the clock registers. 203 * need to see the clock registers.
203 */ 204 */
204fs_initcall(clock_init); 205fs_initcall(clock_init);
205 206
206static void __init sbus_time_init(void)
207{
208
209 BTFIXUPSET_CALL(bus_do_settimeofday, sbus_do_settimeofday, BTFIXUPCALL_NORM);
210 btfixup();
211
212 sparc_init_timers(timer_interrupt);
213}
214
215void __init time_init(void)
216{
217#ifdef CONFIG_PCI
218 extern void pci_time_init(void);
219 if (pcic_present()) {
220 pci_time_init();
221 return;
222 }
223#endif
224 sbus_time_init();
225}
226 207
227static inline unsigned long do_gettimeoffset(void) 208u32 sbus_do_gettimeoffset(void)
228{ 209{
229 unsigned long val = *master_l10_counter; 210 unsigned long val = *master_l10_counter;
230 unsigned long usec = (val >> 10) & 0x1fffff; 211 unsigned long usec = (val >> 10) & 0x1fffff;
@@ -233,86 +214,39 @@ static inline unsigned long do_gettimeoffset(void)
233 if (val & 0x80000000) 214 if (val & 0x80000000)
234 usec += 1000000 / HZ; 215 usec += 1000000 / HZ;
235 216
236 return usec; 217 return usec * 1000;
237} 218}
238 219
239/* Ok, my cute asm atomicity trick doesn't work anymore.
240 * There are just too many variables that need to be protected
241 * now (both members of xtime, et al.)
242 */
243void do_gettimeofday(struct timeval *tv)
244{
245 unsigned long flags;
246 unsigned long seq;
247 unsigned long usec, sec;
248 unsigned long max_ntp_tick = tick_usec - tickadj;
249
250 do {
251 seq = read_seqbegin_irqsave(&xtime_lock, flags);
252 usec = do_gettimeoffset();
253
254 /*
255 * If time_adjust is negative then NTP is slowing the clock
256 * so make sure not to go into next possible interval.
257 * Better to lose some accuracy than have time go backwards..
258 */
259 if (unlikely(time_adjust < 0))
260 usec = min(usec, max_ntp_tick);
261
262 sec = xtime.tv_sec;
263 usec += (xtime.tv_nsec / 1000);
264 } while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
265
266 while (usec >= 1000000) {
267 usec -= 1000000;
268 sec++;
269 }
270 220
271 tv->tv_sec = sec; 221u32 arch_gettimeoffset(void)
272 tv->tv_usec = usec;
273}
274
275EXPORT_SYMBOL(do_gettimeofday);
276
277int do_settimeofday(struct timespec *tv)
278{ 222{
279 int ret; 223 if (unlikely(!do_arch_gettimeoffset))
280 224 return 0;
281 write_seqlock_irq(&xtime_lock); 225 return do_arch_gettimeoffset();
282 ret = bus_do_settimeofday(tv);
283 write_sequnlock_irq(&xtime_lock);
284 clock_was_set();
285 return ret;
286} 226}
287 227
288EXPORT_SYMBOL(do_settimeofday); 228static void __init sbus_time_init(void)
289
290static int sbus_do_settimeofday(struct timespec *tv)
291{ 229{
292 time_t wtm_sec, sec = tv->tv_sec; 230 do_arch_gettimeoffset = sbus_do_gettimeoffset;
293 long wtm_nsec, nsec = tv->tv_nsec;
294 231
295 if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC) 232 btfixup();
296 return -EINVAL;
297
298 /*
299 * This is revolting. We need to set "xtime" correctly. However, the
300 * value in this location is the value at the most recent update of
301 * wall time. Discover what correction gettimeofday() would have
302 * made, and then undo it!
303 */
304 nsec -= 1000 * do_gettimeoffset();
305
306 wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec);
307 wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec);
308 233
309 set_normalized_timespec(&xtime, sec, nsec); 234 sparc_init_timers(timer_interrupt);
310 set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); 235}
311 236
312 ntp_clear(); 237void __init time_init(void)
313 return 0; 238{
239#ifdef CONFIG_PCI
240 extern void pci_time_init(void);
241 if (pcic_present()) {
242 pci_time_init();
243 return;
244 }
245#endif
246 sbus_time_init();
314} 247}
315 248
249
316static int set_rtc_mmss(unsigned long secs) 250static int set_rtc_mmss(unsigned long secs)
317{ 251{
318 struct rtc_device *rtc = rtc_class_open("rtc0"); 252 struct rtc_device *rtc = rtc_class_open("rtc0");
diff --git a/arch/sparc/mm/fault_32.c b/arch/sparc/mm/fault_32.c
index b99f81c4906f..a3413acb8f12 100644
--- a/arch/sparc/mm/fault_32.c
+++ b/arch/sparc/mm/fault_32.c
@@ -18,6 +18,7 @@
18#include <linux/signal.h> 18#include <linux/signal.h>
19#include <linux/mm.h> 19#include <linux/mm.h>
20#include <linux/smp.h> 20#include <linux/smp.h>
21#include <linux/perf_event.h>
21#include <linux/interrupt.h> 22#include <linux/interrupt.h>
22#include <linux/module.h> 23#include <linux/module.h>
23#include <linux/kdebug.h> 24#include <linux/kdebug.h>
@@ -203,6 +204,8 @@ asmlinkage void do_sparc_fault(struct pt_regs *regs, int text_fault, int write,
203 if (in_atomic() || !mm) 204 if (in_atomic() || !mm)
204 goto no_context; 205 goto no_context;
205 206
207 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
208
206 down_read(&mm->mmap_sem); 209 down_read(&mm->mmap_sem);
207 210
208 /* 211 /*
@@ -249,10 +252,15 @@ good_area:
249 goto do_sigbus; 252 goto do_sigbus;
250 BUG(); 253 BUG();
251 } 254 }
252 if (fault & VM_FAULT_MAJOR) 255 if (fault & VM_FAULT_MAJOR) {
253 current->maj_flt++; 256 current->maj_flt++;
254 else 257 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0,
258 regs, address);
259 } else {
255 current->min_flt++; 260 current->min_flt++;
261 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0,
262 regs, address);
263 }
256 up_read(&mm->mmap_sem); 264 up_read(&mm->mmap_sem);
257 return; 265 return;
258 266
diff --git a/arch/sparc/mm/fault_64.c b/arch/sparc/mm/fault_64.c
index 6081936bf03b..b9d4ff02b8fc 100644
--- a/arch/sparc/mm/fault_64.c
+++ b/arch/sparc/mm/fault_64.c
@@ -16,6 +16,7 @@
16#include <linux/mm.h> 16#include <linux/mm.h>
17#include <linux/module.h> 17#include <linux/module.h>
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/perf_event.h>
19#include <linux/interrupt.h> 20#include <linux/interrupt.h>
20#include <linux/kprobes.h> 21#include <linux/kprobes.h>
21#include <linux/kdebug.h> 22#include <linux/kdebug.h>
@@ -296,6 +297,8 @@ asmlinkage void __kprobes do_sparc64_fault(struct pt_regs *regs)
296 if (in_atomic() || !mm) 297 if (in_atomic() || !mm)
297 goto intr_or_no_mm; 298 goto intr_or_no_mm;
298 299
300 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
301
299 if (!down_read_trylock(&mm->mmap_sem)) { 302 if (!down_read_trylock(&mm->mmap_sem)) {
300 if ((regs->tstate & TSTATE_PRIV) && 303 if ((regs->tstate & TSTATE_PRIV) &&
301 !search_exception_tables(regs->tpc)) { 304 !search_exception_tables(regs->tpc)) {
@@ -400,11 +403,15 @@ good_area:
400 goto do_sigbus; 403 goto do_sigbus;
401 BUG(); 404 BUG();
402 } 405 }
403 if (fault & VM_FAULT_MAJOR) 406 if (fault & VM_FAULT_MAJOR) {
404 current->maj_flt++; 407 current->maj_flt++;
405 else 408 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0,
409 regs, address);
410 } else {
406 current->min_flt++; 411 current->min_flt++;
407 412 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0,
413 regs, address);
414 }
408 up_read(&mm->mmap_sem); 415 up_read(&mm->mmap_sem);
409 416
410 mm_rss = get_mm_rss(mm); 417 mm_rss = get_mm_rss(mm);
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-03 08:20:05 -0500