diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/powerpc/kernel/Makefile | 3 | ||||
-rw-r--r-- | arch/powerpc/kernel/pci_32.c | 1897 | ||||
-rw-r--r-- | arch/ppc/kernel/Makefile | 1 |
3 files changed, 1899 insertions, 2 deletions
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile index a94699d8dc52..c287980b7e65 100644 --- a/arch/powerpc/kernel/Makefile +++ b/arch/powerpc/kernel/Makefile | |||
@@ -60,7 +60,8 @@ obj-$(CONFIG_MODULES) += $(module-y) | |||
60 | 60 | ||
61 | pci64-$(CONFIG_PPC64) += pci_64.o pci_dn.o pci_iommu.o \ | 61 | pci64-$(CONFIG_PPC64) += pci_64.o pci_dn.o pci_iommu.o \ |
62 | pci_direct_iommu.o iomap.o | 62 | pci_direct_iommu.o iomap.o |
63 | obj-$(CONFIG_PCI) += $(pci64-y) | 63 | pci32-$(CONFIG_PPC32) := pci_32.o |
64 | obj-$(CONFIG_PCI) += $(pci64-y) $(pci32-y) | ||
64 | kexec-$(CONFIG_PPC64) := machine_kexec_64.o crash.o | 65 | kexec-$(CONFIG_PPC64) := machine_kexec_64.o crash.o |
65 | kexec-$(CONFIG_PPC32) := machine_kexec_32.o | 66 | kexec-$(CONFIG_PPC32) := machine_kexec_32.o |
66 | obj-$(CONFIG_KEXEC) += machine_kexec.o $(kexec-y) | 67 | obj-$(CONFIG_KEXEC) += machine_kexec.o $(kexec-y) |
diff --git a/arch/powerpc/kernel/pci_32.c b/arch/powerpc/kernel/pci_32.c new file mode 100644 index 000000000000..704c846b2b0f --- /dev/null +++ b/arch/powerpc/kernel/pci_32.c | |||
@@ -0,0 +1,1897 @@ | |||
1 | /* | ||
2 | * Common pmac/prep/chrp pci routines. -- Cort | ||
3 | */ | ||
4 | |||
5 | #include <linux/config.h> | ||
6 | #include <linux/kernel.h> | ||
7 | #include <linux/pci.h> | ||
8 | #include <linux/delay.h> | ||
9 | #include <linux/string.h> | ||
10 | #include <linux/init.h> | ||
11 | #include <linux/capability.h> | ||
12 | #include <linux/sched.h> | ||
13 | #include <linux/errno.h> | ||
14 | #include <linux/bootmem.h> | ||
15 | |||
16 | #include <asm/processor.h> | ||
17 | #include <asm/io.h> | ||
18 | #include <asm/prom.h> | ||
19 | #include <asm/sections.h> | ||
20 | #include <asm/pci-bridge.h> | ||
21 | #include <asm/byteorder.h> | ||
22 | #include <asm/irq.h> | ||
23 | #include <asm/uaccess.h> | ||
24 | #include <asm/machdep.h> | ||
25 | |||
26 | #undef DEBUG | ||
27 | |||
28 | #ifdef DEBUG | ||
29 | #define DBG(x...) printk(x) | ||
30 | #else | ||
31 | #define DBG(x...) | ||
32 | #endif | ||
33 | |||
34 | unsigned long isa_io_base = 0; | ||
35 | unsigned long isa_mem_base = 0; | ||
36 | unsigned long pci_dram_offset = 0; | ||
37 | int pcibios_assign_bus_offset = 1; | ||
38 | |||
39 | void pcibios_make_OF_bus_map(void); | ||
40 | |||
41 | static int pci_relocate_bridge_resource(struct pci_bus *bus, int i); | ||
42 | static int probe_resource(struct pci_bus *parent, struct resource *pr, | ||
43 | struct resource *res, struct resource **conflict); | ||
44 | static void update_bridge_base(struct pci_bus *bus, int i); | ||
45 | static void pcibios_fixup_resources(struct pci_dev* dev); | ||
46 | static void fixup_broken_pcnet32(struct pci_dev* dev); | ||
47 | static int reparent_resources(struct resource *parent, struct resource *res); | ||
48 | static void fixup_cpc710_pci64(struct pci_dev* dev); | ||
49 | #ifdef CONFIG_PPC_OF | ||
50 | static u8* pci_to_OF_bus_map; | ||
51 | #endif | ||
52 | |||
53 | /* By default, we don't re-assign bus numbers. We do this only on | ||
54 | * some pmacs | ||
55 | */ | ||
56 | int pci_assign_all_buses; | ||
57 | |||
58 | struct pci_controller* hose_head; | ||
59 | struct pci_controller** hose_tail = &hose_head; | ||
60 | |||
61 | static int pci_bus_count; | ||
62 | |||
63 | static void | ||
64 | fixup_broken_pcnet32(struct pci_dev* dev) | ||
65 | { | ||
66 | if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) { | ||
67 | dev->vendor = PCI_VENDOR_ID_AMD; | ||
68 | pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD); | ||
69 | } | ||
70 | } | ||
71 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32); | ||
72 | |||
73 | static void | ||
74 | fixup_cpc710_pci64(struct pci_dev* dev) | ||
75 | { | ||
76 | /* Hide the PCI64 BARs from the kernel as their content doesn't | ||
77 | * fit well in the resource management | ||
78 | */ | ||
79 | dev->resource[0].start = dev->resource[0].end = 0; | ||
80 | dev->resource[0].flags = 0; | ||
81 | dev->resource[1].start = dev->resource[1].end = 0; | ||
82 | dev->resource[1].flags = 0; | ||
83 | } | ||
84 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64); | ||
85 | |||
86 | static void | ||
87 | pcibios_fixup_resources(struct pci_dev *dev) | ||
88 | { | ||
89 | struct pci_controller* hose = (struct pci_controller *)dev->sysdata; | ||
90 | int i; | ||
91 | unsigned long offset; | ||
92 | |||
93 | if (!hose) { | ||
94 | printk(KERN_ERR "No hose for PCI dev %s!\n", pci_name(dev)); | ||
95 | return; | ||
96 | } | ||
97 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | ||
98 | struct resource *res = dev->resource + i; | ||
99 | if (!res->flags) | ||
100 | continue; | ||
101 | if (res->end == 0xffffffff) { | ||
102 | DBG("PCI:%s Resource %d [%08lx-%08lx] is unassigned\n", | ||
103 | pci_name(dev), i, res->start, res->end); | ||
104 | res->end -= res->start; | ||
105 | res->start = 0; | ||
106 | res->flags |= IORESOURCE_UNSET; | ||
107 | continue; | ||
108 | } | ||
109 | offset = 0; | ||
110 | if (res->flags & IORESOURCE_MEM) { | ||
111 | offset = hose->pci_mem_offset; | ||
112 | } else if (res->flags & IORESOURCE_IO) { | ||
113 | offset = (unsigned long) hose->io_base_virt | ||
114 | - isa_io_base; | ||
115 | } | ||
116 | if (offset != 0) { | ||
117 | res->start += offset; | ||
118 | res->end += offset; | ||
119 | #ifdef DEBUG | ||
120 | printk("Fixup res %d (%lx) of dev %s: %lx -> %lx\n", | ||
121 | i, res->flags, pci_name(dev), | ||
122 | res->start - offset, res->start); | ||
123 | #endif | ||
124 | } | ||
125 | } | ||
126 | |||
127 | /* Call machine specific resource fixup */ | ||
128 | if (ppc_md.pcibios_fixup_resources) | ||
129 | ppc_md.pcibios_fixup_resources(dev); | ||
130 | } | ||
131 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); | ||
132 | |||
133 | void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, | ||
134 | struct resource *res) | ||
135 | { | ||
136 | unsigned long offset = 0; | ||
137 | struct pci_controller *hose = dev->sysdata; | ||
138 | |||
139 | if (hose && res->flags & IORESOURCE_IO) | ||
140 | offset = (unsigned long)hose->io_base_virt - isa_io_base; | ||
141 | else if (hose && res->flags & IORESOURCE_MEM) | ||
142 | offset = hose->pci_mem_offset; | ||
143 | region->start = res->start - offset; | ||
144 | region->end = res->end - offset; | ||
145 | } | ||
146 | EXPORT_SYMBOL(pcibios_resource_to_bus); | ||
147 | |||
148 | void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, | ||
149 | struct pci_bus_region *region) | ||
150 | { | ||
151 | unsigned long offset = 0; | ||
152 | struct pci_controller *hose = dev->sysdata; | ||
153 | |||
154 | if (hose && res->flags & IORESOURCE_IO) | ||
155 | offset = (unsigned long)hose->io_base_virt - isa_io_base; | ||
156 | else if (hose && res->flags & IORESOURCE_MEM) | ||
157 | offset = hose->pci_mem_offset; | ||
158 | res->start = region->start + offset; | ||
159 | res->end = region->end + offset; | ||
160 | } | ||
161 | EXPORT_SYMBOL(pcibios_bus_to_resource); | ||
162 | |||
163 | /* | ||
164 | * We need to avoid collisions with `mirrored' VGA ports | ||
165 | * and other strange ISA hardware, so we always want the | ||
166 | * addresses to be allocated in the 0x000-0x0ff region | ||
167 | * modulo 0x400. | ||
168 | * | ||
169 | * Why? Because some silly external IO cards only decode | ||
170 | * the low 10 bits of the IO address. The 0x00-0xff region | ||
171 | * is reserved for motherboard devices that decode all 16 | ||
172 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | ||
173 | * but we want to try to avoid allocating at 0x2900-0x2bff | ||
174 | * which might have be mirrored at 0x0100-0x03ff.. | ||
175 | */ | ||
176 | void pcibios_align_resource(void *data, struct resource *res, unsigned long size, | ||
177 | unsigned long align) | ||
178 | { | ||
179 | struct pci_dev *dev = data; | ||
180 | |||
181 | if (res->flags & IORESOURCE_IO) { | ||
182 | unsigned long start = res->start; | ||
183 | |||
184 | if (size > 0x100) { | ||
185 | printk(KERN_ERR "PCI: I/O Region %s/%d too large" | ||
186 | " (%ld bytes)\n", pci_name(dev), | ||
187 | dev->resource - res, size); | ||
188 | } | ||
189 | |||
190 | if (start & 0x300) { | ||
191 | start = (start + 0x3ff) & ~0x3ff; | ||
192 | res->start = start; | ||
193 | } | ||
194 | } | ||
195 | } | ||
196 | EXPORT_SYMBOL(pcibios_align_resource); | ||
197 | |||
198 | /* | ||
199 | * Handle resources of PCI devices. If the world were perfect, we could | ||
200 | * just allocate all the resource regions and do nothing more. It isn't. | ||
201 | * On the other hand, we cannot just re-allocate all devices, as it would | ||
202 | * require us to know lots of host bridge internals. So we attempt to | ||
203 | * keep as much of the original configuration as possible, but tweak it | ||
204 | * when it's found to be wrong. | ||
205 | * | ||
206 | * Known BIOS problems we have to work around: | ||
207 | * - I/O or memory regions not configured | ||
208 | * - regions configured, but not enabled in the command register | ||
209 | * - bogus I/O addresses above 64K used | ||
210 | * - expansion ROMs left enabled (this may sound harmless, but given | ||
211 | * the fact the PCI specs explicitly allow address decoders to be | ||
212 | * shared between expansion ROMs and other resource regions, it's | ||
213 | * at least dangerous) | ||
214 | * | ||
215 | * Our solution: | ||
216 | * (1) Allocate resources for all buses behind PCI-to-PCI bridges. | ||
217 | * This gives us fixed barriers on where we can allocate. | ||
218 | * (2) Allocate resources for all enabled devices. If there is | ||
219 | * a collision, just mark the resource as unallocated. Also | ||
220 | * disable expansion ROMs during this step. | ||
221 | * (3) Try to allocate resources for disabled devices. If the | ||
222 | * resources were assigned correctly, everything goes well, | ||
223 | * if they weren't, they won't disturb allocation of other | ||
224 | * resources. | ||
225 | * (4) Assign new addresses to resources which were either | ||
226 | * not configured at all or misconfigured. If explicitly | ||
227 | * requested by the user, configure expansion ROM address | ||
228 | * as well. | ||
229 | */ | ||
230 | |||
231 | static void __init | ||
232 | pcibios_allocate_bus_resources(struct list_head *bus_list) | ||
233 | { | ||
234 | struct pci_bus *bus; | ||
235 | int i; | ||
236 | struct resource *res, *pr; | ||
237 | |||
238 | /* Depth-First Search on bus tree */ | ||
239 | list_for_each_entry(bus, bus_list, node) { | ||
240 | for (i = 0; i < 4; ++i) { | ||
241 | if ((res = bus->resource[i]) == NULL || !res->flags | ||
242 | || res->start > res->end) | ||
243 | continue; | ||
244 | if (bus->parent == NULL) | ||
245 | pr = (res->flags & IORESOURCE_IO)? | ||
246 | &ioport_resource: &iomem_resource; | ||
247 | else { | ||
248 | pr = pci_find_parent_resource(bus->self, res); | ||
249 | if (pr == res) { | ||
250 | /* this happens when the generic PCI | ||
251 | * code (wrongly) decides that this | ||
252 | * bridge is transparent -- paulus | ||
253 | */ | ||
254 | continue; | ||
255 | } | ||
256 | } | ||
257 | |||
258 | DBG("PCI: bridge rsrc %lx..%lx (%lx), parent %p\n", | ||
259 | res->start, res->end, res->flags, pr); | ||
260 | if (pr) { | ||
261 | if (request_resource(pr, res) == 0) | ||
262 | continue; | ||
263 | /* | ||
264 | * Must be a conflict with an existing entry. | ||
265 | * Move that entry (or entries) under the | ||
266 | * bridge resource and try again. | ||
267 | */ | ||
268 | if (reparent_resources(pr, res) == 0) | ||
269 | continue; | ||
270 | } | ||
271 | printk(KERN_ERR "PCI: Cannot allocate resource region " | ||
272 | "%d of PCI bridge %d\n", i, bus->number); | ||
273 | if (pci_relocate_bridge_resource(bus, i)) | ||
274 | bus->resource[i] = NULL; | ||
275 | } | ||
276 | pcibios_allocate_bus_resources(&bus->children); | ||
277 | } | ||
278 | } | ||
279 | |||
280 | /* | ||
281 | * Reparent resource children of pr that conflict with res | ||
282 | * under res, and make res replace those children. | ||
283 | */ | ||
284 | static int __init | ||
285 | reparent_resources(struct resource *parent, struct resource *res) | ||
286 | { | ||
287 | struct resource *p, **pp; | ||
288 | struct resource **firstpp = NULL; | ||
289 | |||
290 | for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { | ||
291 | if (p->end < res->start) | ||
292 | continue; | ||
293 | if (res->end < p->start) | ||
294 | break; | ||
295 | if (p->start < res->start || p->end > res->end) | ||
296 | return -1; /* not completely contained */ | ||
297 | if (firstpp == NULL) | ||
298 | firstpp = pp; | ||
299 | } | ||
300 | if (firstpp == NULL) | ||
301 | return -1; /* didn't find any conflicting entries? */ | ||
302 | res->parent = parent; | ||
303 | res->child = *firstpp; | ||
304 | res->sibling = *pp; | ||
305 | *firstpp = res; | ||
306 | *pp = NULL; | ||
307 | for (p = res->child; p != NULL; p = p->sibling) { | ||
308 | p->parent = res; | ||
309 | DBG(KERN_INFO "PCI: reparented %s [%lx..%lx] under %s\n", | ||
310 | p->name, p->start, p->end, res->name); | ||
311 | } | ||
312 | return 0; | ||
313 | } | ||
314 | |||
315 | /* | ||
316 | * A bridge has been allocated a range which is outside the range | ||
317 | * of its parent bridge, so it needs to be moved. | ||
318 | */ | ||
319 | static int __init | ||
320 | pci_relocate_bridge_resource(struct pci_bus *bus, int i) | ||
321 | { | ||
322 | struct resource *res, *pr, *conflict; | ||
323 | unsigned long try, size; | ||
324 | int j; | ||
325 | struct pci_bus *parent = bus->parent; | ||
326 | |||
327 | if (parent == NULL) { | ||
328 | /* shouldn't ever happen */ | ||
329 | printk(KERN_ERR "PCI: can't move host bridge resource\n"); | ||
330 | return -1; | ||
331 | } | ||
332 | res = bus->resource[i]; | ||
333 | if (res == NULL) | ||
334 | return -1; | ||
335 | pr = NULL; | ||
336 | for (j = 0; j < 4; j++) { | ||
337 | struct resource *r = parent->resource[j]; | ||
338 | if (!r) | ||
339 | continue; | ||
340 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) | ||
341 | continue; | ||
342 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) { | ||
343 | pr = r; | ||
344 | break; | ||
345 | } | ||
346 | if (res->flags & IORESOURCE_PREFETCH) | ||
347 | pr = r; | ||
348 | } | ||
349 | if (pr == NULL) | ||
350 | return -1; | ||
351 | size = res->end - res->start; | ||
352 | if (pr->start > pr->end || size > pr->end - pr->start) | ||
353 | return -1; | ||
354 | try = pr->end; | ||
355 | for (;;) { | ||
356 | res->start = try - size; | ||
357 | res->end = try; | ||
358 | if (probe_resource(bus->parent, pr, res, &conflict) == 0) | ||
359 | break; | ||
360 | if (conflict->start <= pr->start + size) | ||
361 | return -1; | ||
362 | try = conflict->start - 1; | ||
363 | } | ||
364 | if (request_resource(pr, res)) { | ||
365 | DBG(KERN_ERR "PCI: huh? couldn't move to %lx..%lx\n", | ||
366 | res->start, res->end); | ||
367 | return -1; /* "can't happen" */ | ||
368 | } | ||
369 | update_bridge_base(bus, i); | ||
370 | printk(KERN_INFO "PCI: bridge %d resource %d moved to %lx..%lx\n", | ||
371 | bus->number, i, res->start, res->end); | ||
372 | return 0; | ||
373 | } | ||
374 | |||
375 | static int __init | ||
376 | probe_resource(struct pci_bus *parent, struct resource *pr, | ||
377 | struct resource *res, struct resource **conflict) | ||
378 | { | ||
379 | struct pci_bus *bus; | ||
380 | struct pci_dev *dev; | ||
381 | struct resource *r; | ||
382 | int i; | ||
383 | |||
384 | for (r = pr->child; r != NULL; r = r->sibling) { | ||
385 | if (r->end >= res->start && res->end >= r->start) { | ||
386 | *conflict = r; | ||
387 | return 1; | ||
388 | } | ||
389 | } | ||
390 | list_for_each_entry(bus, &parent->children, node) { | ||
391 | for (i = 0; i < 4; ++i) { | ||
392 | if ((r = bus->resource[i]) == NULL) | ||
393 | continue; | ||
394 | if (!r->flags || r->start > r->end || r == res) | ||
395 | continue; | ||
396 | if (pci_find_parent_resource(bus->self, r) != pr) | ||
397 | continue; | ||
398 | if (r->end >= res->start && res->end >= r->start) { | ||
399 | *conflict = r; | ||
400 | return 1; | ||
401 | } | ||
402 | } | ||
403 | } | ||
404 | list_for_each_entry(dev, &parent->devices, bus_list) { | ||
405 | for (i = 0; i < 6; ++i) { | ||
406 | r = &dev->resource[i]; | ||
407 | if (!r->flags || (r->flags & IORESOURCE_UNSET)) | ||
408 | continue; | ||
409 | if (pci_find_parent_resource(dev, r) != pr) | ||
410 | continue; | ||
411 | if (r->end >= res->start && res->end >= r->start) { | ||
412 | *conflict = r; | ||
413 | return 1; | ||
414 | } | ||
415 | } | ||
416 | } | ||
417 | return 0; | ||
418 | } | ||
419 | |||
420 | static void __init | ||
421 | update_bridge_base(struct pci_bus *bus, int i) | ||
422 | { | ||
423 | struct resource *res = bus->resource[i]; | ||
424 | u8 io_base_lo, io_limit_lo; | ||
425 | u16 mem_base, mem_limit; | ||
426 | u16 cmd; | ||
427 | unsigned long start, end, off; | ||
428 | struct pci_dev *dev = bus->self; | ||
429 | struct pci_controller *hose = dev->sysdata; | ||
430 | |||
431 | if (!hose) { | ||
432 | printk("update_bridge_base: no hose?\n"); | ||
433 | return; | ||
434 | } | ||
435 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | ||
436 | pci_write_config_word(dev, PCI_COMMAND, | ||
437 | cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)); | ||
438 | if (res->flags & IORESOURCE_IO) { | ||
439 | off = (unsigned long) hose->io_base_virt - isa_io_base; | ||
440 | start = res->start - off; | ||
441 | end = res->end - off; | ||
442 | io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK; | ||
443 | io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK; | ||
444 | if (end > 0xffff) { | ||
445 | pci_write_config_word(dev, PCI_IO_BASE_UPPER16, | ||
446 | start >> 16); | ||
447 | pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16, | ||
448 | end >> 16); | ||
449 | io_base_lo |= PCI_IO_RANGE_TYPE_32; | ||
450 | } else | ||
451 | io_base_lo |= PCI_IO_RANGE_TYPE_16; | ||
452 | pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo); | ||
453 | pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo); | ||
454 | |||
455 | } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH)) | ||
456 | == IORESOURCE_MEM) { | ||
457 | off = hose->pci_mem_offset; | ||
458 | mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK; | ||
459 | mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK; | ||
460 | pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base); | ||
461 | pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit); | ||
462 | |||
463 | } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH)) | ||
464 | == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) { | ||
465 | off = hose->pci_mem_offset; | ||
466 | mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK; | ||
467 | mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK; | ||
468 | pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base); | ||
469 | pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit); | ||
470 | |||
471 | } else { | ||
472 | DBG(KERN_ERR "PCI: ugh, bridge %s res %d has flags=%lx\n", | ||
473 | pci_name(dev), i, res->flags); | ||
474 | } | ||
475 | pci_write_config_word(dev, PCI_COMMAND, cmd); | ||
476 | } | ||
477 | |||
478 | static inline void alloc_resource(struct pci_dev *dev, int idx) | ||
479 | { | ||
480 | struct resource *pr, *r = &dev->resource[idx]; | ||
481 | |||
482 | DBG("PCI:%s: Resource %d: %08lx-%08lx (f=%lx)\n", | ||
483 | pci_name(dev), idx, r->start, r->end, r->flags); | ||
484 | pr = pci_find_parent_resource(dev, r); | ||
485 | if (!pr || request_resource(pr, r) < 0) { | ||
486 | printk(KERN_ERR "PCI: Cannot allocate resource region %d" | ||
487 | " of device %s\n", idx, pci_name(dev)); | ||
488 | if (pr) | ||
489 | DBG("PCI: parent is %p: %08lx-%08lx (f=%lx)\n", | ||
490 | pr, pr->start, pr->end, pr->flags); | ||
491 | /* We'll assign a new address later */ | ||
492 | r->flags |= IORESOURCE_UNSET; | ||
493 | r->end -= r->start; | ||
494 | r->start = 0; | ||
495 | } | ||
496 | } | ||
497 | |||
498 | static void __init | ||
499 | pcibios_allocate_resources(int pass) | ||
500 | { | ||
501 | struct pci_dev *dev = NULL; | ||
502 | int idx, disabled; | ||
503 | u16 command; | ||
504 | struct resource *r; | ||
505 | |||
506 | for_each_pci_dev(dev) { | ||
507 | pci_read_config_word(dev, PCI_COMMAND, &command); | ||
508 | for (idx = 0; idx < 6; idx++) { | ||
509 | r = &dev->resource[idx]; | ||
510 | if (r->parent) /* Already allocated */ | ||
511 | continue; | ||
512 | if (!r->flags || (r->flags & IORESOURCE_UNSET)) | ||
513 | continue; /* Not assigned at all */ | ||
514 | if (r->flags & IORESOURCE_IO) | ||
515 | disabled = !(command & PCI_COMMAND_IO); | ||
516 | else | ||
517 | disabled = !(command & PCI_COMMAND_MEMORY); | ||
518 | if (pass == disabled) | ||
519 | alloc_resource(dev, idx); | ||
520 | } | ||
521 | if (pass) | ||
522 | continue; | ||
523 | r = &dev->resource[PCI_ROM_RESOURCE]; | ||
524 | if (r->flags & IORESOURCE_ROM_ENABLE) { | ||
525 | /* Turn the ROM off, leave the resource region, but keep it unregistered. */ | ||
526 | u32 reg; | ||
527 | DBG("PCI: Switching off ROM of %s\n", pci_name(dev)); | ||
528 | r->flags &= ~IORESOURCE_ROM_ENABLE; | ||
529 | pci_read_config_dword(dev, dev->rom_base_reg, ®); | ||
530 | pci_write_config_dword(dev, dev->rom_base_reg, | ||
531 | reg & ~PCI_ROM_ADDRESS_ENABLE); | ||
532 | } | ||
533 | } | ||
534 | } | ||
535 | |||
536 | static void __init | ||
537 | pcibios_assign_resources(void) | ||
538 | { | ||
539 | struct pci_dev *dev = NULL; | ||
540 | int idx; | ||
541 | struct resource *r; | ||
542 | |||
543 | for_each_pci_dev(dev) { | ||
544 | int class = dev->class >> 8; | ||
545 | |||
546 | /* Don't touch classless devices and host bridges */ | ||
547 | if (!class || class == PCI_CLASS_BRIDGE_HOST) | ||
548 | continue; | ||
549 | |||
550 | for (idx = 0; idx < 6; idx++) { | ||
551 | r = &dev->resource[idx]; | ||
552 | |||
553 | /* | ||
554 | * We shall assign a new address to this resource, | ||
555 | * either because the BIOS (sic) forgot to do so | ||
556 | * or because we have decided the old address was | ||
557 | * unusable for some reason. | ||
558 | */ | ||
559 | if ((r->flags & IORESOURCE_UNSET) && r->end && | ||
560 | (!ppc_md.pcibios_enable_device_hook || | ||
561 | !ppc_md.pcibios_enable_device_hook(dev, 1))) { | ||
562 | r->flags &= ~IORESOURCE_UNSET; | ||
563 | pci_assign_resource(dev, idx); | ||
564 | } | ||
565 | } | ||
566 | |||
567 | #if 0 /* don't assign ROMs */ | ||
568 | r = &dev->resource[PCI_ROM_RESOURCE]; | ||
569 | r->end -= r->start; | ||
570 | r->start = 0; | ||
571 | if (r->end) | ||
572 | pci_assign_resource(dev, PCI_ROM_RESOURCE); | ||
573 | #endif | ||
574 | } | ||
575 | } | ||
576 | |||
577 | |||
578 | int | ||
579 | pcibios_enable_resources(struct pci_dev *dev, int mask) | ||
580 | { | ||
581 | u16 cmd, old_cmd; | ||
582 | int idx; | ||
583 | struct resource *r; | ||
584 | |||
585 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | ||
586 | old_cmd = cmd; | ||
587 | for (idx=0; idx<6; idx++) { | ||
588 | /* Only set up the requested stuff */ | ||
589 | if (!(mask & (1<<idx))) | ||
590 | continue; | ||
591 | |||
592 | r = &dev->resource[idx]; | ||
593 | if (r->flags & IORESOURCE_UNSET) { | ||
594 | printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev)); | ||
595 | return -EINVAL; | ||
596 | } | ||
597 | if (r->flags & IORESOURCE_IO) | ||
598 | cmd |= PCI_COMMAND_IO; | ||
599 | if (r->flags & IORESOURCE_MEM) | ||
600 | cmd |= PCI_COMMAND_MEMORY; | ||
601 | } | ||
602 | if (dev->resource[PCI_ROM_RESOURCE].start) | ||
603 | cmd |= PCI_COMMAND_MEMORY; | ||
604 | if (cmd != old_cmd) { | ||
605 | printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd); | ||
606 | pci_write_config_word(dev, PCI_COMMAND, cmd); | ||
607 | } | ||
608 | return 0; | ||
609 | } | ||
610 | |||
611 | static int next_controller_index; | ||
612 | |||
613 | struct pci_controller * __init | ||
614 | pcibios_alloc_controller(void) | ||
615 | { | ||
616 | struct pci_controller *hose; | ||
617 | |||
618 | hose = (struct pci_controller *)alloc_bootmem(sizeof(*hose)); | ||
619 | memset(hose, 0, sizeof(struct pci_controller)); | ||
620 | |||
621 | *hose_tail = hose; | ||
622 | hose_tail = &hose->next; | ||
623 | |||
624 | hose->index = next_controller_index++; | ||
625 | |||
626 | return hose; | ||
627 | } | ||
628 | |||
629 | #ifdef CONFIG_PPC_OF | ||
630 | /* | ||
631 | * Functions below are used on OpenFirmware machines. | ||
632 | */ | ||
633 | static void | ||
634 | make_one_node_map(struct device_node* node, u8 pci_bus) | ||
635 | { | ||
636 | int *bus_range; | ||
637 | int len; | ||
638 | |||
639 | if (pci_bus >= pci_bus_count) | ||
640 | return; | ||
641 | bus_range = (int *) get_property(node, "bus-range", &len); | ||
642 | if (bus_range == NULL || len < 2 * sizeof(int)) { | ||
643 | printk(KERN_WARNING "Can't get bus-range for %s, " | ||
644 | "assuming it starts at 0\n", node->full_name); | ||
645 | pci_to_OF_bus_map[pci_bus] = 0; | ||
646 | } else | ||
647 | pci_to_OF_bus_map[pci_bus] = bus_range[0]; | ||
648 | |||
649 | for (node=node->child; node != 0;node = node->sibling) { | ||
650 | struct pci_dev* dev; | ||
651 | unsigned int *class_code, *reg; | ||
652 | |||
653 | class_code = (unsigned int *) get_property(node, "class-code", NULL); | ||
654 | if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && | ||
655 | (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) | ||
656 | continue; | ||
657 | reg = (unsigned int *)get_property(node, "reg", NULL); | ||
658 | if (!reg) | ||
659 | continue; | ||
660 | dev = pci_find_slot(pci_bus, ((reg[0] >> 8) & 0xff)); | ||
661 | if (!dev || !dev->subordinate) | ||
662 | continue; | ||
663 | make_one_node_map(node, dev->subordinate->number); | ||
664 | } | ||
665 | } | ||
666 | |||
667 | void | ||
668 | pcibios_make_OF_bus_map(void) | ||
669 | { | ||
670 | int i; | ||
671 | struct pci_controller* hose; | ||
672 | u8* of_prop_map; | ||
673 | |||
674 | pci_to_OF_bus_map = (u8*)kmalloc(pci_bus_count, GFP_KERNEL); | ||
675 | if (!pci_to_OF_bus_map) { | ||
676 | printk(KERN_ERR "Can't allocate OF bus map !\n"); | ||
677 | return; | ||
678 | } | ||
679 | |||
680 | /* We fill the bus map with invalid values, that helps | ||
681 | * debugging. | ||
682 | */ | ||
683 | for (i=0; i<pci_bus_count; i++) | ||
684 | pci_to_OF_bus_map[i] = 0xff; | ||
685 | |||
686 | /* For each hose, we begin searching bridges */ | ||
687 | for(hose=hose_head; hose; hose=hose->next) { | ||
688 | struct device_node* node; | ||
689 | node = (struct device_node *)hose->arch_data; | ||
690 | if (!node) | ||
691 | continue; | ||
692 | make_one_node_map(node, hose->first_busno); | ||
693 | } | ||
694 | of_prop_map = get_property(find_path_device("/"), "pci-OF-bus-map", NULL); | ||
695 | if (of_prop_map) | ||
696 | memcpy(of_prop_map, pci_to_OF_bus_map, pci_bus_count); | ||
697 | #ifdef DEBUG | ||
698 | printk("PCI->OF bus map:\n"); | ||
699 | for (i=0; i<pci_bus_count; i++) { | ||
700 | if (pci_to_OF_bus_map[i] == 0xff) | ||
701 | continue; | ||
702 | printk("%d -> %d\n", i, pci_to_OF_bus_map[i]); | ||
703 | } | ||
704 | #endif | ||
705 | } | ||
706 | |||
707 | typedef int (*pci_OF_scan_iterator)(struct device_node* node, void* data); | ||
708 | |||
709 | static struct device_node* | ||
710 | scan_OF_pci_childs(struct device_node* node, pci_OF_scan_iterator filter, void* data) | ||
711 | { | ||
712 | struct device_node* sub_node; | ||
713 | |||
714 | for (; node != 0;node = node->sibling) { | ||
715 | unsigned int *class_code; | ||
716 | |||
717 | if (filter(node, data)) | ||
718 | return node; | ||
719 | |||
720 | /* For PCI<->PCI bridges or CardBus bridges, we go down | ||
721 | * Note: some OFs create a parent node "multifunc-device" as | ||
722 | * a fake root for all functions of a multi-function device, | ||
723 | * we go down them as well. | ||
724 | */ | ||
725 | class_code = (unsigned int *) get_property(node, "class-code", NULL); | ||
726 | if ((!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && | ||
727 | (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) && | ||
728 | strcmp(node->name, "multifunc-device")) | ||
729 | continue; | ||
730 | sub_node = scan_OF_pci_childs(node->child, filter, data); | ||
731 | if (sub_node) | ||
732 | return sub_node; | ||
733 | } | ||
734 | return NULL; | ||
735 | } | ||
736 | |||
737 | static int | ||
738 | scan_OF_pci_childs_iterator(struct device_node* node, void* data) | ||
739 | { | ||
740 | unsigned int *reg; | ||
741 | u8* fdata = (u8*)data; | ||
742 | |||
743 | reg = (unsigned int *) get_property(node, "reg", NULL); | ||
744 | if (reg && ((reg[0] >> 8) & 0xff) == fdata[1] | ||
745 | && ((reg[0] >> 16) & 0xff) == fdata[0]) | ||
746 | return 1; | ||
747 | return 0; | ||
748 | } | ||
749 | |||
750 | static struct device_node* | ||
751 | scan_OF_childs_for_device(struct device_node* node, u8 bus, u8 dev_fn) | ||
752 | { | ||
753 | u8 filter_data[2] = {bus, dev_fn}; | ||
754 | |||
755 | return scan_OF_pci_childs(node, scan_OF_pci_childs_iterator, filter_data); | ||
756 | } | ||
757 | |||
758 | /* | ||
759 | * Scans the OF tree for a device node matching a PCI device | ||
760 | */ | ||
761 | struct device_node * | ||
762 | pci_busdev_to_OF_node(struct pci_bus *bus, int devfn) | ||
763 | { | ||
764 | struct pci_controller *hose; | ||
765 | struct device_node *node; | ||
766 | int busnr; | ||
767 | |||
768 | if (!have_of) | ||
769 | return NULL; | ||
770 | |||
771 | /* Lookup the hose */ | ||
772 | busnr = bus->number; | ||
773 | hose = pci_bus_to_hose(busnr); | ||
774 | if (!hose) | ||
775 | return NULL; | ||
776 | |||
777 | /* Check it has an OF node associated */ | ||
778 | node = (struct device_node *) hose->arch_data; | ||
779 | if (!node) | ||
780 | return NULL; | ||
781 | |||
782 | /* Fixup bus number according to what OF think it is. */ | ||
783 | #ifdef CONFIG_PPC_PMAC | ||
784 | /* The G5 need a special case here. Basically, we don't remap all | ||
785 | * busses on it so we don't create the pci-OF-map. However, we do | ||
786 | * remap the AGP bus and so have to deal with it. A future better | ||
787 | * fix has to be done by making the remapping per-host and always | ||
788 | * filling the pci_to_OF map. --BenH | ||
789 | */ | ||
790 | if (_machine == _MACH_Pmac && busnr >= 0xf0) | ||
791 | busnr -= 0xf0; | ||
792 | else | ||
793 | #endif | ||
794 | if (pci_to_OF_bus_map) | ||
795 | busnr = pci_to_OF_bus_map[busnr]; | ||
796 | if (busnr == 0xff) | ||
797 | return NULL; | ||
798 | |||
799 | /* Now, lookup childs of the hose */ | ||
800 | return scan_OF_childs_for_device(node->child, busnr, devfn); | ||
801 | } | ||
802 | EXPORT_SYMBOL(pci_busdev_to_OF_node); | ||
803 | |||
804 | struct device_node* | ||
805 | pci_device_to_OF_node(struct pci_dev *dev) | ||
806 | { | ||
807 | return pci_busdev_to_OF_node(dev->bus, dev->devfn); | ||
808 | } | ||
809 | EXPORT_SYMBOL(pci_device_to_OF_node); | ||
810 | |||
811 | /* This routine is meant to be used early during boot, when the | ||
812 | * PCI bus numbers have not yet been assigned, and you need to | ||
813 | * issue PCI config cycles to an OF device. | ||
814 | * It could also be used to "fix" RTAS config cycles if you want | ||
815 | * to set pci_assign_all_buses to 1 and still use RTAS for PCI | ||
816 | * config cycles. | ||
817 | */ | ||
818 | struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) | ||
819 | { | ||
820 | if (!have_of) | ||
821 | return NULL; | ||
822 | while(node) { | ||
823 | struct pci_controller* hose; | ||
824 | for (hose=hose_head;hose;hose=hose->next) | ||
825 | if (hose->arch_data == node) | ||
826 | return hose; | ||
827 | node=node->parent; | ||
828 | } | ||
829 | return NULL; | ||
830 | } | ||
831 | |||
832 | static int | ||
833 | find_OF_pci_device_filter(struct device_node* node, void* data) | ||
834 | { | ||
835 | return ((void *)node == data); | ||
836 | } | ||
837 | |||
838 | /* | ||
839 | * Returns the PCI device matching a given OF node | ||
840 | */ | ||
841 | int | ||
842 | pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn) | ||
843 | { | ||
844 | unsigned int *reg; | ||
845 | struct pci_controller* hose; | ||
846 | struct pci_dev* dev = NULL; | ||
847 | |||
848 | if (!have_of) | ||
849 | return -ENODEV; | ||
850 | /* Make sure it's really a PCI device */ | ||
851 | hose = pci_find_hose_for_OF_device(node); | ||
852 | if (!hose || !hose->arch_data) | ||
853 | return -ENODEV; | ||
854 | if (!scan_OF_pci_childs(((struct device_node*)hose->arch_data)->child, | ||
855 | find_OF_pci_device_filter, (void *)node)) | ||
856 | return -ENODEV; | ||
857 | reg = (unsigned int *) get_property(node, "reg", NULL); | ||
858 | if (!reg) | ||
859 | return -ENODEV; | ||
860 | *bus = (reg[0] >> 16) & 0xff; | ||
861 | *devfn = ((reg[0] >> 8) & 0xff); | ||
862 | |||
863 | /* Ok, here we need some tweak. If we have already renumbered | ||
864 | * all busses, we can't rely on the OF bus number any more. | ||
865 | * the pci_to_OF_bus_map is not enough as several PCI busses | ||
866 | * may match the same OF bus number. | ||
867 | */ | ||
868 | if (!pci_to_OF_bus_map) | ||
869 | return 0; | ||
870 | |||
871 | for_each_pci_dev(dev) | ||
872 | if (pci_to_OF_bus_map[dev->bus->number] == *bus && | ||
873 | dev->devfn == *devfn) { | ||
874 | *bus = dev->bus->number; | ||
875 | pci_dev_put(dev); | ||
876 | return 0; | ||
877 | } | ||
878 | |||
879 | return -ENODEV; | ||
880 | } | ||
881 | EXPORT_SYMBOL(pci_device_from_OF_node); | ||
882 | |||
883 | void __init | ||
884 | pci_process_bridge_OF_ranges(struct pci_controller *hose, | ||
885 | struct device_node *dev, int primary) | ||
886 | { | ||
887 | static unsigned int static_lc_ranges[256] __initdata; | ||
888 | unsigned int *dt_ranges, *lc_ranges, *ranges, *prev; | ||
889 | unsigned int size; | ||
890 | int rlen = 0, orig_rlen; | ||
891 | int memno = 0; | ||
892 | struct resource *res; | ||
893 | int np, na = prom_n_addr_cells(dev); | ||
894 | np = na + 5; | ||
895 | |||
896 | /* First we try to merge ranges to fix a problem with some pmacs | ||
897 | * that can have more than 3 ranges, fortunately using contiguous | ||
898 | * addresses -- BenH | ||
899 | */ | ||
900 | dt_ranges = (unsigned int *) get_property(dev, "ranges", &rlen); | ||
901 | if (!dt_ranges) | ||
902 | return; | ||
903 | /* Sanity check, though hopefully that never happens */ | ||
904 | if (rlen > sizeof(static_lc_ranges)) { | ||
905 | printk(KERN_WARNING "OF ranges property too large !\n"); | ||
906 | rlen = sizeof(static_lc_ranges); | ||
907 | } | ||
908 | lc_ranges = static_lc_ranges; | ||
909 | memcpy(lc_ranges, dt_ranges, rlen); | ||
910 | orig_rlen = rlen; | ||
911 | |||
912 | /* Let's work on a copy of the "ranges" property instead of damaging | ||
913 | * the device-tree image in memory | ||
914 | */ | ||
915 | ranges = lc_ranges; | ||
916 | prev = NULL; | ||
917 | while ((rlen -= np * sizeof(unsigned int)) >= 0) { | ||
918 | if (prev) { | ||
919 | if (prev[0] == ranges[0] && prev[1] == ranges[1] && | ||
920 | (prev[2] + prev[na+4]) == ranges[2] && | ||
921 | (prev[na+2] + prev[na+4]) == ranges[na+2]) { | ||
922 | prev[na+4] += ranges[na+4]; | ||
923 | ranges[0] = 0; | ||
924 | ranges += np; | ||
925 | continue; | ||
926 | } | ||
927 | } | ||
928 | prev = ranges; | ||
929 | ranges += np; | ||
930 | } | ||
931 | |||
932 | /* | ||
933 | * The ranges property is laid out as an array of elements, | ||
934 | * each of which comprises: | ||
935 | * cells 0 - 2: a PCI address | ||
936 | * cells 3 or 3+4: a CPU physical address | ||
937 | * (size depending on dev->n_addr_cells) | ||
938 | * cells 4+5 or 5+6: the size of the range | ||
939 | */ | ||
940 | ranges = lc_ranges; | ||
941 | rlen = orig_rlen; | ||
942 | while (ranges && (rlen -= np * sizeof(unsigned int)) >= 0) { | ||
943 | res = NULL; | ||
944 | size = ranges[na+4]; | ||
945 | switch ((ranges[0] >> 24) & 0x3) { | ||
946 | case 1: /* I/O space */ | ||
947 | if (ranges[2] != 0) | ||
948 | break; | ||
949 | hose->io_base_phys = ranges[na+2]; | ||
950 | /* limit I/O space to 16MB */ | ||
951 | if (size > 0x01000000) | ||
952 | size = 0x01000000; | ||
953 | hose->io_base_virt = ioremap(ranges[na+2], size); | ||
954 | if (primary) | ||
955 | isa_io_base = (unsigned long) hose->io_base_virt; | ||
956 | res = &hose->io_resource; | ||
957 | res->flags = IORESOURCE_IO; | ||
958 | res->start = ranges[2]; | ||
959 | DBG("PCI: IO 0x%lx -> 0x%lx\n", | ||
960 | res->start, res->start + size - 1); | ||
961 | break; | ||
962 | case 2: /* memory space */ | ||
963 | memno = 0; | ||
964 | if (ranges[1] == 0 && ranges[2] == 0 | ||
965 | && ranges[na+4] <= (16 << 20)) { | ||
966 | /* 1st 16MB, i.e. ISA memory area */ | ||
967 | if (primary) | ||
968 | isa_mem_base = ranges[na+2]; | ||
969 | memno = 1; | ||
970 | } | ||
971 | while (memno < 3 && hose->mem_resources[memno].flags) | ||
972 | ++memno; | ||
973 | if (memno == 0) | ||
974 | hose->pci_mem_offset = ranges[na+2] - ranges[2]; | ||
975 | if (memno < 3) { | ||
976 | res = &hose->mem_resources[memno]; | ||
977 | res->flags = IORESOURCE_MEM; | ||
978 | if(ranges[0] & 0x40000000) | ||
979 | res->flags |= IORESOURCE_PREFETCH; | ||
980 | res->start = ranges[na+2]; | ||
981 | DBG("PCI: MEM[%d] 0x%lx -> 0x%lx\n", memno, | ||
982 | res->start, res->start + size - 1); | ||
983 | } | ||
984 | break; | ||
985 | } | ||
986 | if (res != NULL) { | ||
987 | res->name = dev->full_name; | ||
988 | res->end = res->start + size - 1; | ||
989 | res->parent = NULL; | ||
990 | res->sibling = NULL; | ||
991 | res->child = NULL; | ||
992 | } | ||
993 | ranges += np; | ||
994 | } | ||
995 | } | ||
996 | |||
997 | /* We create the "pci-OF-bus-map" property now so it appears in the | ||
998 | * /proc device tree | ||
999 | */ | ||
1000 | void __init | ||
1001 | pci_create_OF_bus_map(void) | ||
1002 | { | ||
1003 | struct property* of_prop; | ||
1004 | |||
1005 | of_prop = (struct property*) alloc_bootmem(sizeof(struct property) + 256); | ||
1006 | if (of_prop && find_path_device("/")) { | ||
1007 | memset(of_prop, -1, sizeof(struct property) + 256); | ||
1008 | of_prop->name = "pci-OF-bus-map"; | ||
1009 | of_prop->length = 256; | ||
1010 | of_prop->value = (unsigned char *)&of_prop[1]; | ||
1011 | prom_add_property(find_path_device("/"), of_prop); | ||
1012 | } | ||
1013 | } | ||
1014 | |||
1015 | static ssize_t pci_show_devspec(struct device *dev, struct device_attribute *attr, char *buf) | ||
1016 | { | ||
1017 | struct pci_dev *pdev; | ||
1018 | struct device_node *np; | ||
1019 | |||
1020 | pdev = to_pci_dev (dev); | ||
1021 | np = pci_device_to_OF_node(pdev); | ||
1022 | if (np == NULL || np->full_name == NULL) | ||
1023 | return 0; | ||
1024 | return sprintf(buf, "%s", np->full_name); | ||
1025 | } | ||
1026 | static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); | ||
1027 | |||
1028 | #else /* CONFIG_PPC_OF */ | ||
1029 | void pcibios_make_OF_bus_map(void) | ||
1030 | { | ||
1031 | } | ||
1032 | #endif /* CONFIG_PPC_OF */ | ||
1033 | |||
1034 | /* Add sysfs properties */ | ||
1035 | void pcibios_add_platform_entries(struct pci_dev *pdev) | ||
1036 | { | ||
1037 | #ifdef CONFIG_PPC_OF | ||
1038 | device_create_file(&pdev->dev, &dev_attr_devspec); | ||
1039 | #endif /* CONFIG_PPC_OF */ | ||
1040 | } | ||
1041 | |||
1042 | |||
1043 | #ifdef CONFIG_PPC_PMAC | ||
1044 | /* | ||
1045 | * This set of routines checks for PCI<->PCI bridges that have closed | ||
1046 | * IO resources and have child devices. It tries to re-open an IO | ||
1047 | * window on them. | ||
1048 | * | ||
1049 | * This is a _temporary_ fix to workaround a problem with Apple's OF | ||
1050 | * closing IO windows on P2P bridges when the OF drivers of cards | ||
1051 | * below this bridge don't claim any IO range (typically ATI or | ||
1052 | * Adaptec). | ||
1053 | * | ||
1054 | * A more complete fix would be to use drivers/pci/setup-bus.c, which | ||
1055 | * involves a working pcibios_fixup_pbus_ranges(), some more care about | ||
1056 | * ordering when creating the host bus resources, and maybe a few more | ||
1057 | * minor tweaks | ||
1058 | */ | ||
1059 | |||
1060 | /* Initialize bridges with base/limit values we have collected */ | ||
1061 | static void __init | ||
1062 | do_update_p2p_io_resource(struct pci_bus *bus, int enable_vga) | ||
1063 | { | ||
1064 | struct pci_dev *bridge = bus->self; | ||
1065 | struct pci_controller* hose = (struct pci_controller *)bridge->sysdata; | ||
1066 | u32 l; | ||
1067 | u16 w; | ||
1068 | struct resource res; | ||
1069 | |||
1070 | if (bus->resource[0] == NULL) | ||
1071 | return; | ||
1072 | res = *(bus->resource[0]); | ||
1073 | |||
1074 | DBG("Remapping Bus %d, bridge: %s\n", bus->number, pci_name(bridge)); | ||
1075 | res.start -= ((unsigned long) hose->io_base_virt - isa_io_base); | ||
1076 | res.end -= ((unsigned long) hose->io_base_virt - isa_io_base); | ||
1077 | DBG(" IO window: %08lx-%08lx\n", res.start, res.end); | ||
1078 | |||
1079 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ | ||
1080 | pci_read_config_dword(bridge, PCI_IO_BASE, &l); | ||
1081 | l &= 0xffff000f; | ||
1082 | l |= (res.start >> 8) & 0x00f0; | ||
1083 | l |= res.end & 0xf000; | ||
1084 | pci_write_config_dword(bridge, PCI_IO_BASE, l); | ||
1085 | |||
1086 | if ((l & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { | ||
1087 | l = (res.start >> 16) | (res.end & 0xffff0000); | ||
1088 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, l); | ||
1089 | } | ||
1090 | |||
1091 | pci_read_config_word(bridge, PCI_COMMAND, &w); | ||
1092 | w |= PCI_COMMAND_IO; | ||
1093 | pci_write_config_word(bridge, PCI_COMMAND, w); | ||
1094 | |||
1095 | #if 0 /* Enabling this causes XFree 4.2.0 to hang during PCI probe */ | ||
1096 | if (enable_vga) { | ||
1097 | pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, &w); | ||
1098 | w |= PCI_BRIDGE_CTL_VGA; | ||
1099 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, w); | ||
1100 | } | ||
1101 | #endif | ||
1102 | } | ||
1103 | |||
1104 | /* This function is pretty basic and actually quite broken for the | ||
1105 | * general case, it's enough for us right now though. It's supposed | ||
1106 | * to tell us if we need to open an IO range at all or not and what | ||
1107 | * size. | ||
1108 | */ | ||
1109 | static int __init | ||
1110 | check_for_io_childs(struct pci_bus *bus, struct resource* res, int *found_vga) | ||
1111 | { | ||
1112 | struct pci_dev *dev; | ||
1113 | int i; | ||
1114 | int rc = 0; | ||
1115 | |||
1116 | #define push_end(res, size) do { unsigned long __sz = (size) ; \ | ||
1117 | res->end = ((res->end + __sz) / (__sz + 1)) * (__sz + 1) + __sz; \ | ||
1118 | } while (0) | ||
1119 | |||
1120 | list_for_each_entry(dev, &bus->devices, bus_list) { | ||
1121 | u16 class = dev->class >> 8; | ||
1122 | |||
1123 | if (class == PCI_CLASS_DISPLAY_VGA || | ||
1124 | class == PCI_CLASS_NOT_DEFINED_VGA) | ||
1125 | *found_vga = 1; | ||
1126 | if (class >> 8 == PCI_BASE_CLASS_BRIDGE && dev->subordinate) | ||
1127 | rc |= check_for_io_childs(dev->subordinate, res, found_vga); | ||
1128 | if (class == PCI_CLASS_BRIDGE_CARDBUS) | ||
1129 | push_end(res, 0xfff); | ||
1130 | |||
1131 | for (i=0; i<PCI_NUM_RESOURCES; i++) { | ||
1132 | struct resource *r; | ||
1133 | unsigned long r_size; | ||
1134 | |||
1135 | if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI | ||
1136 | && i >= PCI_BRIDGE_RESOURCES) | ||
1137 | continue; | ||
1138 | r = &dev->resource[i]; | ||
1139 | r_size = r->end - r->start; | ||
1140 | if (r_size < 0xfff) | ||
1141 | r_size = 0xfff; | ||
1142 | if (r->flags & IORESOURCE_IO && (r_size) != 0) { | ||
1143 | rc = 1; | ||
1144 | push_end(res, r_size); | ||
1145 | } | ||
1146 | } | ||
1147 | } | ||
1148 | |||
1149 | return rc; | ||
1150 | } | ||
1151 | |||
1152 | /* Here we scan all P2P bridges of a given level that have a closed | ||
1153 | * IO window. Note that the test for the presence of a VGA card should | ||
1154 | * be improved to take into account already configured P2P bridges, | ||
1155 | * currently, we don't see them and might end up configuring 2 bridges | ||
1156 | * with VGA pass through enabled | ||
1157 | */ | ||
1158 | static void __init | ||
1159 | do_fixup_p2p_level(struct pci_bus *bus) | ||
1160 | { | ||
1161 | struct pci_bus *b; | ||
1162 | int i, parent_io; | ||
1163 | int has_vga = 0; | ||
1164 | |||
1165 | for (parent_io=0; parent_io<4; parent_io++) | ||
1166 | if (bus->resource[parent_io] | ||
1167 | && bus->resource[parent_io]->flags & IORESOURCE_IO) | ||
1168 | break; | ||
1169 | if (parent_io >= 4) | ||
1170 | return; | ||
1171 | |||
1172 | list_for_each_entry(b, &bus->children, node) { | ||
1173 | struct pci_dev *d = b->self; | ||
1174 | struct pci_controller* hose = (struct pci_controller *)d->sysdata; | ||
1175 | struct resource *res = b->resource[0]; | ||
1176 | struct resource tmp_res; | ||
1177 | unsigned long max; | ||
1178 | int found_vga = 0; | ||
1179 | |||
1180 | memset(&tmp_res, 0, sizeof(tmp_res)); | ||
1181 | tmp_res.start = bus->resource[parent_io]->start; | ||
1182 | |||
1183 | /* We don't let low addresses go through that closed P2P bridge, well, | ||
1184 | * that may not be necessary but I feel safer that way | ||
1185 | */ | ||
1186 | if (tmp_res.start == 0) | ||
1187 | tmp_res.start = 0x1000; | ||
1188 | |||
1189 | if (!list_empty(&b->devices) && res && res->flags == 0 && | ||
1190 | res != bus->resource[parent_io] && | ||
1191 | (d->class >> 8) == PCI_CLASS_BRIDGE_PCI && | ||
1192 | check_for_io_childs(b, &tmp_res, &found_vga)) { | ||
1193 | u8 io_base_lo; | ||
1194 | |||
1195 | printk(KERN_INFO "Fixing up IO bus %s\n", b->name); | ||
1196 | |||
1197 | if (found_vga) { | ||
1198 | if (has_vga) { | ||
1199 | printk(KERN_WARNING "Skipping VGA, already active" | ||
1200 | " on bus segment\n"); | ||
1201 | found_vga = 0; | ||
1202 | } else | ||
1203 | has_vga = 1; | ||
1204 | } | ||
1205 | pci_read_config_byte(d, PCI_IO_BASE, &io_base_lo); | ||
1206 | |||
1207 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) | ||
1208 | max = ((unsigned long) hose->io_base_virt | ||
1209 | - isa_io_base) + 0xffffffff; | ||
1210 | else | ||
1211 | max = ((unsigned long) hose->io_base_virt | ||
1212 | - isa_io_base) + 0xffff; | ||
1213 | |||
1214 | *res = tmp_res; | ||
1215 | res->flags = IORESOURCE_IO; | ||
1216 | res->name = b->name; | ||
1217 | |||
1218 | /* Find a resource in the parent where we can allocate */ | ||
1219 | for (i = 0 ; i < 4; i++) { | ||
1220 | struct resource *r = bus->resource[i]; | ||
1221 | if (!r) | ||
1222 | continue; | ||
1223 | if ((r->flags & IORESOURCE_IO) == 0) | ||
1224 | continue; | ||
1225 | DBG("Trying to allocate from %08lx, size %08lx from parent" | ||
1226 | " res %d: %08lx -> %08lx\n", | ||
1227 | res->start, res->end, i, r->start, r->end); | ||
1228 | |||
1229 | if (allocate_resource(r, res, res->end + 1, res->start, max, | ||
1230 | res->end + 1, NULL, NULL) < 0) { | ||
1231 | DBG("Failed !\n"); | ||
1232 | continue; | ||
1233 | } | ||
1234 | do_update_p2p_io_resource(b, found_vga); | ||
1235 | break; | ||
1236 | } | ||
1237 | } | ||
1238 | do_fixup_p2p_level(b); | ||
1239 | } | ||
1240 | } | ||
1241 | |||
1242 | static void | ||
1243 | pcibios_fixup_p2p_bridges(void) | ||
1244 | { | ||
1245 | struct pci_bus *b; | ||
1246 | |||
1247 | list_for_each_entry(b, &pci_root_buses, node) | ||
1248 | do_fixup_p2p_level(b); | ||
1249 | } | ||
1250 | |||
1251 | #endif /* CONFIG_PPC_PMAC */ | ||
1252 | |||
1253 | static int __init | ||
1254 | pcibios_init(void) | ||
1255 | { | ||
1256 | struct pci_controller *hose; | ||
1257 | struct pci_bus *bus; | ||
1258 | int next_busno; | ||
1259 | |||
1260 | printk(KERN_INFO "PCI: Probing PCI hardware\n"); | ||
1261 | |||
1262 | /* Scan all of the recorded PCI controllers. */ | ||
1263 | for (next_busno = 0, hose = hose_head; hose; hose = hose->next) { | ||
1264 | if (pci_assign_all_buses) | ||
1265 | hose->first_busno = next_busno; | ||
1266 | hose->last_busno = 0xff; | ||
1267 | bus = pci_scan_bus(hose->first_busno, hose->ops, hose); | ||
1268 | hose->last_busno = bus->subordinate; | ||
1269 | if (pci_assign_all_buses || next_busno <= hose->last_busno) | ||
1270 | next_busno = hose->last_busno + pcibios_assign_bus_offset; | ||
1271 | } | ||
1272 | pci_bus_count = next_busno; | ||
1273 | |||
1274 | /* OpenFirmware based machines need a map of OF bus | ||
1275 | * numbers vs. kernel bus numbers since we may have to | ||
1276 | * remap them. | ||
1277 | */ | ||
1278 | if (pci_assign_all_buses && have_of) | ||
1279 | pcibios_make_OF_bus_map(); | ||
1280 | |||
1281 | /* Do machine dependent PCI interrupt routing */ | ||
1282 | if (ppc_md.pci_swizzle && ppc_md.pci_map_irq) | ||
1283 | pci_fixup_irqs(ppc_md.pci_swizzle, ppc_md.pci_map_irq); | ||
1284 | |||
1285 | /* Call machine dependent fixup */ | ||
1286 | if (ppc_md.pcibios_fixup) | ||
1287 | ppc_md.pcibios_fixup(); | ||
1288 | |||
1289 | /* Allocate and assign resources */ | ||
1290 | pcibios_allocate_bus_resources(&pci_root_buses); | ||
1291 | pcibios_allocate_resources(0); | ||
1292 | pcibios_allocate_resources(1); | ||
1293 | #ifdef CONFIG_PPC_PMAC | ||
1294 | pcibios_fixup_p2p_bridges(); | ||
1295 | #endif /* CONFIG_PPC_PMAC */ | ||
1296 | pcibios_assign_resources(); | ||
1297 | |||
1298 | /* Call machine dependent post-init code */ | ||
1299 | if (ppc_md.pcibios_after_init) | ||
1300 | ppc_md.pcibios_after_init(); | ||
1301 | |||
1302 | return 0; | ||
1303 | } | ||
1304 | |||
1305 | subsys_initcall(pcibios_init); | ||
1306 | |||
1307 | unsigned char __init | ||
1308 | common_swizzle(struct pci_dev *dev, unsigned char *pinp) | ||
1309 | { | ||
1310 | struct pci_controller *hose = dev->sysdata; | ||
1311 | |||
1312 | if (dev->bus->number != hose->first_busno) { | ||
1313 | u8 pin = *pinp; | ||
1314 | do { | ||
1315 | pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)); | ||
1316 | /* Move up the chain of bridges. */ | ||
1317 | dev = dev->bus->self; | ||
1318 | } while (dev->bus->self); | ||
1319 | *pinp = pin; | ||
1320 | |||
1321 | /* The slot is the idsel of the last bridge. */ | ||
1322 | } | ||
1323 | return PCI_SLOT(dev->devfn); | ||
1324 | } | ||
1325 | |||
1326 | unsigned long resource_fixup(struct pci_dev * dev, struct resource * res, | ||
1327 | unsigned long start, unsigned long size) | ||
1328 | { | ||
1329 | return start; | ||
1330 | } | ||
1331 | |||
1332 | void __init pcibios_fixup_bus(struct pci_bus *bus) | ||
1333 | { | ||
1334 | struct pci_controller *hose = (struct pci_controller *) bus->sysdata; | ||
1335 | unsigned long io_offset; | ||
1336 | struct resource *res; | ||
1337 | int i; | ||
1338 | |||
1339 | io_offset = (unsigned long)hose->io_base_virt - isa_io_base; | ||
1340 | if (bus->parent == NULL) { | ||
1341 | /* This is a host bridge - fill in its resources */ | ||
1342 | hose->bus = bus; | ||
1343 | |||
1344 | bus->resource[0] = res = &hose->io_resource; | ||
1345 | if (!res->flags) { | ||
1346 | if (io_offset) | ||
1347 | printk(KERN_ERR "I/O resource not set for host" | ||
1348 | " bridge %d\n", hose->index); | ||
1349 | res->start = 0; | ||
1350 | res->end = IO_SPACE_LIMIT; | ||
1351 | res->flags = IORESOURCE_IO; | ||
1352 | } | ||
1353 | res->start += io_offset; | ||
1354 | res->end += io_offset; | ||
1355 | |||
1356 | for (i = 0; i < 3; ++i) { | ||
1357 | res = &hose->mem_resources[i]; | ||
1358 | if (!res->flags) { | ||
1359 | if (i > 0) | ||
1360 | continue; | ||
1361 | printk(KERN_ERR "Memory resource not set for " | ||
1362 | "host bridge %d\n", hose->index); | ||
1363 | res->start = hose->pci_mem_offset; | ||
1364 | res->end = ~0U; | ||
1365 | res->flags = IORESOURCE_MEM; | ||
1366 | } | ||
1367 | bus->resource[i+1] = res; | ||
1368 | } | ||
1369 | } else { | ||
1370 | /* This is a subordinate bridge */ | ||
1371 | pci_read_bridge_bases(bus); | ||
1372 | |||
1373 | for (i = 0; i < 4; ++i) { | ||
1374 | if ((res = bus->resource[i]) == NULL) | ||
1375 | continue; | ||
1376 | if (!res->flags) | ||
1377 | continue; | ||
1378 | if (io_offset && (res->flags & IORESOURCE_IO)) { | ||
1379 | res->start += io_offset; | ||
1380 | res->end += io_offset; | ||
1381 | } else if (hose->pci_mem_offset | ||
1382 | && (res->flags & IORESOURCE_MEM)) { | ||
1383 | res->start += hose->pci_mem_offset; | ||
1384 | res->end += hose->pci_mem_offset; | ||
1385 | } | ||
1386 | } | ||
1387 | } | ||
1388 | |||
1389 | if (ppc_md.pcibios_fixup_bus) | ||
1390 | ppc_md.pcibios_fixup_bus(bus); | ||
1391 | } | ||
1392 | |||
1393 | char __init *pcibios_setup(char *str) | ||
1394 | { | ||
1395 | return str; | ||
1396 | } | ||
1397 | |||
1398 | /* the next one is stolen from the alpha port... */ | ||
1399 | void __init | ||
1400 | pcibios_update_irq(struct pci_dev *dev, int irq) | ||
1401 | { | ||
1402 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); | ||
1403 | /* XXX FIXME - update OF device tree node interrupt property */ | ||
1404 | } | ||
1405 | |||
1406 | int pcibios_enable_device(struct pci_dev *dev, int mask) | ||
1407 | { | ||
1408 | u16 cmd, old_cmd; | ||
1409 | int idx; | ||
1410 | struct resource *r; | ||
1411 | |||
1412 | if (ppc_md.pcibios_enable_device_hook) | ||
1413 | if (ppc_md.pcibios_enable_device_hook(dev, 0)) | ||
1414 | return -EINVAL; | ||
1415 | |||
1416 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | ||
1417 | old_cmd = cmd; | ||
1418 | for (idx=0; idx<6; idx++) { | ||
1419 | r = &dev->resource[idx]; | ||
1420 | if (r->flags & IORESOURCE_UNSET) { | ||
1421 | printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev)); | ||
1422 | return -EINVAL; | ||
1423 | } | ||
1424 | if (r->flags & IORESOURCE_IO) | ||
1425 | cmd |= PCI_COMMAND_IO; | ||
1426 | if (r->flags & IORESOURCE_MEM) | ||
1427 | cmd |= PCI_COMMAND_MEMORY; | ||
1428 | } | ||
1429 | if (cmd != old_cmd) { | ||
1430 | printk("PCI: Enabling device %s (%04x -> %04x)\n", | ||
1431 | pci_name(dev), old_cmd, cmd); | ||
1432 | pci_write_config_word(dev, PCI_COMMAND, cmd); | ||
1433 | } | ||
1434 | return 0; | ||
1435 | } | ||
1436 | |||
1437 | struct pci_controller* | ||
1438 | pci_bus_to_hose(int bus) | ||
1439 | { | ||
1440 | struct pci_controller* hose = hose_head; | ||
1441 | |||
1442 | for (; hose; hose = hose->next) | ||
1443 | if (bus >= hose->first_busno && bus <= hose->last_busno) | ||
1444 | return hose; | ||
1445 | return NULL; | ||
1446 | } | ||
1447 | |||
1448 | void __iomem * | ||
1449 | pci_bus_io_base(unsigned int bus) | ||
1450 | { | ||
1451 | struct pci_controller *hose; | ||
1452 | |||
1453 | hose = pci_bus_to_hose(bus); | ||
1454 | if (!hose) | ||
1455 | return NULL; | ||
1456 | return hose->io_base_virt; | ||
1457 | } | ||
1458 | |||
1459 | unsigned long | ||
1460 | pci_bus_io_base_phys(unsigned int bus) | ||
1461 | { | ||
1462 | struct pci_controller *hose; | ||
1463 | |||
1464 | hose = pci_bus_to_hose(bus); | ||
1465 | if (!hose) | ||
1466 | return 0; | ||
1467 | return hose->io_base_phys; | ||
1468 | } | ||
1469 | |||
1470 | unsigned long | ||
1471 | pci_bus_mem_base_phys(unsigned int bus) | ||
1472 | { | ||
1473 | struct pci_controller *hose; | ||
1474 | |||
1475 | hose = pci_bus_to_hose(bus); | ||
1476 | if (!hose) | ||
1477 | return 0; | ||
1478 | return hose->pci_mem_offset; | ||
1479 | } | ||
1480 | |||
1481 | unsigned long | ||
1482 | pci_resource_to_bus(struct pci_dev *pdev, struct resource *res) | ||
1483 | { | ||
1484 | /* Hack alert again ! See comments in chrp_pci.c | ||
1485 | */ | ||
1486 | struct pci_controller* hose = | ||
1487 | (struct pci_controller *)pdev->sysdata; | ||
1488 | if (hose && res->flags & IORESOURCE_MEM) | ||
1489 | return res->start - hose->pci_mem_offset; | ||
1490 | /* We may want to do something with IOs here... */ | ||
1491 | return res->start; | ||
1492 | } | ||
1493 | |||
1494 | |||
1495 | static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, | ||
1496 | unsigned long *offset, | ||
1497 | enum pci_mmap_state mmap_state) | ||
1498 | { | ||
1499 | struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); | ||
1500 | unsigned long io_offset = 0; | ||
1501 | int i, res_bit; | ||
1502 | |||
1503 | if (hose == 0) | ||
1504 | return NULL; /* should never happen */ | ||
1505 | |||
1506 | /* If memory, add on the PCI bridge address offset */ | ||
1507 | if (mmap_state == pci_mmap_mem) { | ||
1508 | *offset += hose->pci_mem_offset; | ||
1509 | res_bit = IORESOURCE_MEM; | ||
1510 | } else { | ||
1511 | io_offset = hose->io_base_virt - ___IO_BASE; | ||
1512 | *offset += io_offset; | ||
1513 | res_bit = IORESOURCE_IO; | ||
1514 | } | ||
1515 | |||
1516 | /* | ||
1517 | * Check that the offset requested corresponds to one of the | ||
1518 | * resources of the device. | ||
1519 | */ | ||
1520 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | ||
1521 | struct resource *rp = &dev->resource[i]; | ||
1522 | int flags = rp->flags; | ||
1523 | |||
1524 | /* treat ROM as memory (should be already) */ | ||
1525 | if (i == PCI_ROM_RESOURCE) | ||
1526 | flags |= IORESOURCE_MEM; | ||
1527 | |||
1528 | /* Active and same type? */ | ||
1529 | if ((flags & res_bit) == 0) | ||
1530 | continue; | ||
1531 | |||
1532 | /* In the range of this resource? */ | ||
1533 | if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) | ||
1534 | continue; | ||
1535 | |||
1536 | /* found it! construct the final physical address */ | ||
1537 | if (mmap_state == pci_mmap_io) | ||
1538 | *offset += hose->io_base_phys - io_offset; | ||
1539 | return rp; | ||
1540 | } | ||
1541 | |||
1542 | return NULL; | ||
1543 | } | ||
1544 | |||
1545 | /* | ||
1546 | * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci | ||
1547 | * device mapping. | ||
1548 | */ | ||
1549 | static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, | ||
1550 | pgprot_t protection, | ||
1551 | enum pci_mmap_state mmap_state, | ||
1552 | int write_combine) | ||
1553 | { | ||
1554 | unsigned long prot = pgprot_val(protection); | ||
1555 | |||
1556 | /* Write combine is always 0 on non-memory space mappings. On | ||
1557 | * memory space, if the user didn't pass 1, we check for a | ||
1558 | * "prefetchable" resource. This is a bit hackish, but we use | ||
1559 | * this to workaround the inability of /sysfs to provide a write | ||
1560 | * combine bit | ||
1561 | */ | ||
1562 | if (mmap_state != pci_mmap_mem) | ||
1563 | write_combine = 0; | ||
1564 | else if (write_combine == 0) { | ||
1565 | if (rp->flags & IORESOURCE_PREFETCH) | ||
1566 | write_combine = 1; | ||
1567 | } | ||
1568 | |||
1569 | /* XXX would be nice to have a way to ask for write-through */ | ||
1570 | prot |= _PAGE_NO_CACHE; | ||
1571 | if (write_combine) | ||
1572 | prot &= ~_PAGE_GUARDED; | ||
1573 | else | ||
1574 | prot |= _PAGE_GUARDED; | ||
1575 | |||
1576 | printk("PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start, | ||
1577 | prot); | ||
1578 | |||
1579 | return __pgprot(prot); | ||
1580 | } | ||
1581 | |||
1582 | /* | ||
1583 | * This one is used by /dev/mem and fbdev who have no clue about the | ||
1584 | * PCI device, it tries to find the PCI device first and calls the | ||
1585 | * above routine | ||
1586 | */ | ||
1587 | pgprot_t pci_phys_mem_access_prot(struct file *file, | ||
1588 | unsigned long pfn, | ||
1589 | unsigned long size, | ||
1590 | pgprot_t protection) | ||
1591 | { | ||
1592 | struct pci_dev *pdev = NULL; | ||
1593 | struct resource *found = NULL; | ||
1594 | unsigned long prot = pgprot_val(protection); | ||
1595 | unsigned long offset = pfn << PAGE_SHIFT; | ||
1596 | int i; | ||
1597 | |||
1598 | if (page_is_ram(pfn)) | ||
1599 | return prot; | ||
1600 | |||
1601 | prot |= _PAGE_NO_CACHE | _PAGE_GUARDED; | ||
1602 | |||
1603 | for_each_pci_dev(pdev) { | ||
1604 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | ||
1605 | struct resource *rp = &pdev->resource[i]; | ||
1606 | int flags = rp->flags; | ||
1607 | |||
1608 | /* Active and same type? */ | ||
1609 | if ((flags & IORESOURCE_MEM) == 0) | ||
1610 | continue; | ||
1611 | /* In the range of this resource? */ | ||
1612 | if (offset < (rp->start & PAGE_MASK) || | ||
1613 | offset > rp->end) | ||
1614 | continue; | ||
1615 | found = rp; | ||
1616 | break; | ||
1617 | } | ||
1618 | if (found) | ||
1619 | break; | ||
1620 | } | ||
1621 | if (found) { | ||
1622 | if (found->flags & IORESOURCE_PREFETCH) | ||
1623 | prot &= ~_PAGE_GUARDED; | ||
1624 | pci_dev_put(pdev); | ||
1625 | } | ||
1626 | |||
1627 | DBG("non-PCI map for %lx, prot: %lx\n", offset, prot); | ||
1628 | |||
1629 | return __pgprot(prot); | ||
1630 | } | ||
1631 | |||
1632 | |||
1633 | /* | ||
1634 | * Perform the actual remap of the pages for a PCI device mapping, as | ||
1635 | * appropriate for this architecture. The region in the process to map | ||
1636 | * is described by vm_start and vm_end members of VMA, the base physical | ||
1637 | * address is found in vm_pgoff. | ||
1638 | * The pci device structure is provided so that architectures may make mapping | ||
1639 | * decisions on a per-device or per-bus basis. | ||
1640 | * | ||
1641 | * Returns a negative error code on failure, zero on success. | ||
1642 | */ | ||
1643 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | ||
1644 | enum pci_mmap_state mmap_state, | ||
1645 | int write_combine) | ||
1646 | { | ||
1647 | unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; | ||
1648 | struct resource *rp; | ||
1649 | int ret; | ||
1650 | |||
1651 | rp = __pci_mmap_make_offset(dev, &offset, mmap_state); | ||
1652 | if (rp == NULL) | ||
1653 | return -EINVAL; | ||
1654 | |||
1655 | vma->vm_pgoff = offset >> PAGE_SHIFT; | ||
1656 | vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO; | ||
1657 | vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, | ||
1658 | vma->vm_page_prot, | ||
1659 | mmap_state, write_combine); | ||
1660 | |||
1661 | ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | ||
1662 | vma->vm_end - vma->vm_start, vma->vm_page_prot); | ||
1663 | |||
1664 | return ret; | ||
1665 | } | ||
1666 | |||
1667 | /* Obsolete functions. Should be removed once the symbios driver | ||
1668 | * is fixed | ||
1669 | */ | ||
1670 | unsigned long | ||
1671 | phys_to_bus(unsigned long pa) | ||
1672 | { | ||
1673 | struct pci_controller *hose; | ||
1674 | int i; | ||
1675 | |||
1676 | for (hose = hose_head; hose; hose = hose->next) { | ||
1677 | for (i = 0; i < 3; ++i) { | ||
1678 | if (pa >= hose->mem_resources[i].start | ||
1679 | && pa <= hose->mem_resources[i].end) { | ||
1680 | /* | ||
1681 | * XXX the hose->pci_mem_offset really | ||
1682 | * only applies to mem_resources[0]. | ||
1683 | * We need a way to store an offset for | ||
1684 | * the others. -- paulus | ||
1685 | */ | ||
1686 | if (i == 0) | ||
1687 | pa -= hose->pci_mem_offset; | ||
1688 | return pa; | ||
1689 | } | ||
1690 | } | ||
1691 | } | ||
1692 | /* hmmm, didn't find it */ | ||
1693 | return 0; | ||
1694 | } | ||
1695 | |||
1696 | unsigned long | ||
1697 | pci_phys_to_bus(unsigned long pa, int busnr) | ||
1698 | { | ||
1699 | struct pci_controller* hose = pci_bus_to_hose(busnr); | ||
1700 | if (!hose) | ||
1701 | return pa; | ||
1702 | return pa - hose->pci_mem_offset; | ||
1703 | } | ||
1704 | |||
1705 | unsigned long | ||
1706 | pci_bus_to_phys(unsigned int ba, int busnr) | ||
1707 | { | ||
1708 | struct pci_controller* hose = pci_bus_to_hose(busnr); | ||
1709 | if (!hose) | ||
1710 | return ba; | ||
1711 | return ba + hose->pci_mem_offset; | ||
1712 | } | ||
1713 | |||
1714 | /* Provide information on locations of various I/O regions in physical | ||
1715 | * memory. Do this on a per-card basis so that we choose the right | ||
1716 | * root bridge. | ||
1717 | * Note that the returned IO or memory base is a physical address | ||
1718 | */ | ||
1719 | |||
1720 | long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn) | ||
1721 | { | ||
1722 | struct pci_controller* hose; | ||
1723 | long result = -EOPNOTSUPP; | ||
1724 | |||
1725 | /* Argh ! Please forgive me for that hack, but that's the | ||
1726 | * simplest way to get existing XFree to not lockup on some | ||
1727 | * G5 machines... So when something asks for bus 0 io base | ||
1728 | * (bus 0 is HT root), we return the AGP one instead. | ||
1729 | */ | ||
1730 | #ifdef CONFIG_PPC_PMAC | ||
1731 | if (_machine == _MACH_Pmac && machine_is_compatible("MacRISC4")) | ||
1732 | if (bus == 0) | ||
1733 | bus = 0xf0; | ||
1734 | #endif /* CONFIG_PPC_PMAC */ | ||
1735 | |||
1736 | hose = pci_bus_to_hose(bus); | ||
1737 | if (!hose) | ||
1738 | return -ENODEV; | ||
1739 | |||
1740 | switch (which) { | ||
1741 | case IOBASE_BRIDGE_NUMBER: | ||
1742 | return (long)hose->first_busno; | ||
1743 | case IOBASE_MEMORY: | ||
1744 | return (long)hose->pci_mem_offset; | ||
1745 | case IOBASE_IO: | ||
1746 | return (long)hose->io_base_phys; | ||
1747 | case IOBASE_ISA_IO: | ||
1748 | return (long)isa_io_base; | ||
1749 | case IOBASE_ISA_MEM: | ||
1750 | return (long)isa_mem_base; | ||
1751 | } | ||
1752 | |||
1753 | return result; | ||
1754 | } | ||
1755 | |||
1756 | void pci_resource_to_user(const struct pci_dev *dev, int bar, | ||
1757 | const struct resource *rsrc, | ||
1758 | u64 *start, u64 *end) | ||
1759 | { | ||
1760 | struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); | ||
1761 | unsigned long offset = 0; | ||
1762 | |||
1763 | if (hose == NULL) | ||
1764 | return; | ||
1765 | |||
1766 | if (rsrc->flags & IORESOURCE_IO) | ||
1767 | offset = ___IO_BASE - hose->io_base_virt + hose->io_base_phys; | ||
1768 | |||
1769 | *start = rsrc->start + offset; | ||
1770 | *end = rsrc->end + offset; | ||
1771 | } | ||
1772 | |||
1773 | void __init | ||
1774 | pci_init_resource(struct resource *res, unsigned long start, unsigned long end, | ||
1775 | int flags, char *name) | ||
1776 | { | ||
1777 | res->start = start; | ||
1778 | res->end = end; | ||
1779 | res->flags = flags; | ||
1780 | res->name = name; | ||
1781 | res->parent = NULL; | ||
1782 | res->sibling = NULL; | ||
1783 | res->child = NULL; | ||
1784 | } | ||
1785 | |||
1786 | void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max) | ||
1787 | { | ||
1788 | unsigned long start = pci_resource_start(dev, bar); | ||
1789 | unsigned long len = pci_resource_len(dev, bar); | ||
1790 | unsigned long flags = pci_resource_flags(dev, bar); | ||
1791 | |||
1792 | if (!len) | ||
1793 | return NULL; | ||
1794 | if (max && len > max) | ||
1795 | len = max; | ||
1796 | if (flags & IORESOURCE_IO) | ||
1797 | return ioport_map(start, len); | ||
1798 | if (flags & IORESOURCE_MEM) | ||
1799 | /* Not checking IORESOURCE_CACHEABLE because PPC does | ||
1800 | * not currently distinguish between ioremap and | ||
1801 | * ioremap_nocache. | ||
1802 | */ | ||
1803 | return ioremap(start, len); | ||
1804 | /* What? */ | ||
1805 | return NULL; | ||
1806 | } | ||
1807 | |||
1808 | void pci_iounmap(struct pci_dev *dev, void __iomem *addr) | ||
1809 | { | ||
1810 | /* Nothing to do */ | ||
1811 | } | ||
1812 | EXPORT_SYMBOL(pci_iomap); | ||
1813 | EXPORT_SYMBOL(pci_iounmap); | ||
1814 | |||
1815 | unsigned long pci_address_to_pio(phys_addr_t address) | ||
1816 | { | ||
1817 | struct pci_controller* hose = hose_head; | ||
1818 | |||
1819 | for (; hose; hose = hose->next) { | ||
1820 | unsigned int size = hose->io_resource.end - | ||
1821 | hose->io_resource.start + 1; | ||
1822 | if (address >= hose->io_base_phys && | ||
1823 | address < (hose->io_base_phys + size)) { | ||
1824 | unsigned long base = | ||
1825 | (unsigned long)hose->io_base_virt - _IO_BASE; | ||
1826 | return base + (address - hose->io_base_phys); | ||
1827 | } | ||
1828 | } | ||
1829 | return (unsigned int)-1; | ||
1830 | } | ||
1831 | EXPORT_SYMBOL(pci_address_to_pio); | ||
1832 | |||
1833 | /* | ||
1834 | * Null PCI config access functions, for the case when we can't | ||
1835 | * find a hose. | ||
1836 | */ | ||
1837 | #define NULL_PCI_OP(rw, size, type) \ | ||
1838 | static int \ | ||
1839 | null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ | ||
1840 | { \ | ||
1841 | return PCIBIOS_DEVICE_NOT_FOUND; \ | ||
1842 | } | ||
1843 | |||
1844 | static int | ||
1845 | null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | ||
1846 | int len, u32 *val) | ||
1847 | { | ||
1848 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
1849 | } | ||
1850 | |||
1851 | static int | ||
1852 | null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, | ||
1853 | int len, u32 val) | ||
1854 | { | ||
1855 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
1856 | } | ||
1857 | |||
1858 | static struct pci_ops null_pci_ops = | ||
1859 | { | ||
1860 | null_read_config, | ||
1861 | null_write_config | ||
1862 | }; | ||
1863 | |||
1864 | /* | ||
1865 | * These functions are used early on before PCI scanning is done | ||
1866 | * and all of the pci_dev and pci_bus structures have been created. | ||
1867 | */ | ||
1868 | static struct pci_bus * | ||
1869 | fake_pci_bus(struct pci_controller *hose, int busnr) | ||
1870 | { | ||
1871 | static struct pci_bus bus; | ||
1872 | |||
1873 | if (hose == 0) { | ||
1874 | hose = pci_bus_to_hose(busnr); | ||
1875 | if (hose == 0) | ||
1876 | printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); | ||
1877 | } | ||
1878 | bus.number = busnr; | ||
1879 | bus.sysdata = hose; | ||
1880 | bus.ops = hose? hose->ops: &null_pci_ops; | ||
1881 | return &bus; | ||
1882 | } | ||
1883 | |||
1884 | #define EARLY_PCI_OP(rw, size, type) \ | ||
1885 | int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ | ||
1886 | int devfn, int offset, type value) \ | ||
1887 | { \ | ||
1888 | return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ | ||
1889 | devfn, offset, value); \ | ||
1890 | } | ||
1891 | |||
1892 | EARLY_PCI_OP(read, byte, u8 *) | ||
1893 | EARLY_PCI_OP(read, word, u16 *) | ||
1894 | EARLY_PCI_OP(read, dword, u32 *) | ||
1895 | EARLY_PCI_OP(write, byte, u8) | ||
1896 | EARLY_PCI_OP(write, word, u16) | ||
1897 | EARLY_PCI_OP(write, dword, u32) | ||
diff --git a/arch/ppc/kernel/Makefile b/arch/ppc/kernel/Makefile index 647da4c1d219..e399bbb969a4 100644 --- a/arch/ppc/kernel/Makefile +++ b/arch/ppc/kernel/Makefile | |||
@@ -40,7 +40,6 @@ obj-$(CONFIG_6xx) += l2cr.o cpu_setup_6xx.o | |||
40 | obj-$(CONFIG_SOFTWARE_SUSPEND) += swsusp.o | 40 | obj-$(CONFIG_SOFTWARE_SUSPEND) += swsusp.o |
41 | obj-$(CONFIG_MODULES) += module.o | 41 | obj-$(CONFIG_MODULES) += module.o |
42 | obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-mapping.o | 42 | obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-mapping.o |
43 | obj-$(CONFIG_PCI) += pci.o | ||
44 | obj-$(CONFIG_KGDB) += ppc-stub.o | 43 | obj-$(CONFIG_KGDB) += ppc-stub.o |
45 | obj-$(CONFIG_TAU) += temp.o | 44 | obj-$(CONFIG_TAU) += temp.o |
46 | ifndef CONFIG_E200 | 45 | ifndef CONFIG_E200 |