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-rw-r--r--arch/x86/kernel/Makefile2
-rw-r--r--arch/x86/kernel/mpparse.c (renamed from arch/x86/kernel/mpparse_32.c)20
-rw-r--r--arch/x86/kernel/mpparse_64.c991
3 files changed, 11 insertions, 1002 deletions
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 0bf2fb55aa74..fdd8395e0ed3 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -51,7 +51,7 @@ obj-$(CONFIG_X86_SMP) += smpboot.o tsc_sync.o ipi.o tlb_$(BITS).o
51obj-$(CONFIG_X86_32_SMP) += smpcommon.o 51obj-$(CONFIG_X86_32_SMP) += smpcommon.o
52obj-$(CONFIG_X86_64_SMP) += tsc_sync.o smpcommon.o 52obj-$(CONFIG_X86_64_SMP) += tsc_sync.o smpcommon.o
53obj-$(CONFIG_X86_TRAMPOLINE) += trampoline_$(BITS).o 53obj-$(CONFIG_X86_TRAMPOLINE) += trampoline_$(BITS).o
54obj-$(CONFIG_X86_MPPARSE) += mpparse_$(BITS).o 54obj-$(CONFIG_X86_MPPARSE) += mpparse.o
55obj-$(CONFIG_X86_LOCAL_APIC) += apic_$(BITS).o nmi_$(BITS).o 55obj-$(CONFIG_X86_LOCAL_APIC) += apic_$(BITS).o nmi_$(BITS).o
56obj-$(CONFIG_X86_IO_APIC) += io_apic_$(BITS).o 56obj-$(CONFIG_X86_IO_APIC) += io_apic_$(BITS).o
57obj-$(CONFIG_X86_REBOOTFIXUPS) += reboot_fixups_32.o 57obj-$(CONFIG_X86_REBOOTFIXUPS) += reboot_fixups_32.o
diff --git a/arch/x86/kernel/mpparse_32.c b/arch/x86/kernel/mpparse.c
index 6376791cffe5..6e5e4547981c 100644
--- a/arch/x86/kernel/mpparse_32.c
+++ b/arch/x86/kernel/mpparse.c
@@ -4,34 +4,33 @@
4 * 4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> 5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> 6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * 7 * (c) 2008 Alexey Starikovskiy <astarikovskiy@suse.de>
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */ 8 */
15 9
16#include <linux/mm.h> 10#include <linux/mm.h>
17#include <linux/init.h> 11#include <linux/init.h>
18#include <linux/acpi.h>
19#include <linux/delay.h> 12#include <linux/delay.h>
20#include <linux/bootmem.h> 13#include <linux/bootmem.h>
21#include <linux/kernel_stat.h> 14#include <linux/kernel_stat.h>
22#include <linux/mc146818rtc.h> 15#include <linux/mc146818rtc.h>
23#include <linux/bitops.h> 16#include <linux/bitops.h>
17#include <linux/acpi.h>
18#include <linux/module.h>
24 19
25#include <asm/smp.h> 20#include <asm/smp.h>
26#include <asm/acpi.h>
27#include <asm/mtrr.h> 21#include <asm/mtrr.h>
28#include <asm/mpspec.h> 22#include <asm/mpspec.h>
23#include <asm/pgalloc.h>
29#include <asm/io_apic.h> 24#include <asm/io_apic.h>
25#include <asm/proto.h>
26#include <asm/acpi.h>
30#include <asm/bios_ebda.h> 27#include <asm/bios_ebda.h>
31 28
32#include <mach_apic.h> 29#include <mach_apic.h>
30#ifdef CONFIG_X86_32
33#include <mach_apicdef.h> 31#include <mach_apicdef.h>
34#include <mach_mpparse.h> 32#include <mach_mpparse.h>
33#endif
35 34
36/* Have we found an MP table */ 35/* Have we found an MP table */
37int smp_found_config; 36int smp_found_config;
@@ -43,8 +42,10 @@ int smp_found_config;
43#if defined (CONFIG_MCA) || defined (CONFIG_EISA) 42#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
44int mp_bus_id_to_type[MAX_MP_BUSSES]; 43int mp_bus_id_to_type[MAX_MP_BUSSES];
45#endif 44#endif
45
46DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); 46DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
47int mp_bus_id_to_pci_bus[MAX_MP_BUSSES] = {[0 ... MAX_MP_BUSSES - 1] = -1 }; 47int mp_bus_id_to_pci_bus[MAX_MP_BUSSES] = {[0 ... MAX_MP_BUSSES - 1] = -1 };
48
48static int mp_current_pci_id; 49static int mp_current_pci_id;
49 50
50int pic_mode; 51int pic_mode;
@@ -582,7 +583,6 @@ static void __init __get_smp_config(unsigned early)
582 583
583 if (acpi_lapic && early) 584 if (acpi_lapic && early)
584 return; 585 return;
585
586 /* 586 /*
587 * ACPI supports both logical (e.g. Hyper-Threading) and physical 587 * ACPI supports both logical (e.g. Hyper-Threading) and physical
588 * processors, where MPS only supports physical. 588 * processors, where MPS only supports physical.
diff --git a/arch/x86/kernel/mpparse_64.c b/arch/x86/kernel/mpparse_64.c
deleted file mode 100644
index 7d742577d68a..000000000000
--- a/arch/x86/kernel/mpparse_64.c
+++ /dev/null
@@ -1,991 +0,0 @@
1/*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16#include <linux/mm.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/bootmem.h>
20#include <linux/kernel_stat.h>
21#include <linux/mc146818rtc.h>
22#include <linux/acpi.h>
23#include <linux/module.h>
24
25#include <asm/smp.h>
26#include <asm/mtrr.h>
27#include <asm/mpspec.h>
28#include <asm/pgalloc.h>
29#include <asm/io_apic.h>
30#include <asm/proto.h>
31#include <asm/acpi.h>
32#include <asm/bios_ebda.h>
33
34#include <mach_apic.h>
35
36/* Have we found an MP table */
37int smp_found_config;
38
39/*
40 * Various Linux-internal data structures created from the
41 * MP-table.
42 */
43DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
44int mp_bus_id_to_pci_bus[MAX_MP_BUSSES] = {[0 ... MAX_MP_BUSSES - 1] = -1 };
45
46static int mp_current_pci_id = 0;
47
48/*
49 * Intel MP BIOS table parsing routines:
50 */
51
52/*
53 * Checksum an MP configuration block.
54 */
55
56static int __init mpf_checksum(unsigned char *mp, int len)
57{
58 int sum = 0;
59
60 while (len--)
61 sum += *mp++;
62
63 return sum & 0xFF;
64}
65
66static void __cpuinit MP_processor_info(struct mpc_config_processor *m)
67{
68 int apicid;
69 char *bootup_cpu = "";
70
71 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
72 disabled_cpus++;
73 return;
74 }
75#ifdef CONFIG_X86_NUMAQ
76 apicid = mpc_apic_id(m, translation_table[mpc_record]);
77#else
78 apicid = m->mpc_apicid;
79#endif
80 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
81 bootup_cpu = " (Bootup-CPU)";
82 boot_cpu_physical_apicid = m->mpc_apicid;
83 }
84
85 printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu);
86 generic_processor_info(apicid, m->mpc_apicver);
87}
88
89static void __init MP_bus_info(struct mpc_config_bus *m)
90{
91 char str[7];
92
93 memcpy(str, m->mpc_bustype, 6);
94 str[6] = 0;
95
96#ifdef CONFIG_X86_NUMAQ
97 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
98#else
99 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
100#endif
101
102#if MAX_MP_BUSSES < 256
103 if (m->mpc_busid >= MAX_MP_BUSSES) {
104 printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
105 " is too large, max. supported is %d\n",
106 m->mpc_busid, str, MAX_MP_BUSSES - 1);
107 return;
108 }
109#endif
110
111 if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA) - 1) == 0) {
112 set_bit(m->mpc_busid, mp_bus_not_pci);
113#if defined(CONFIG_EISA) || defined (CONFIG_MCA)
114 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
115#endif
116 } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI) - 1) == 0) {
117#ifdef CONFIG_X86_NUMAQ
118 mpc_oem_pci_bus(m, translation_table[mpc_record]);
119#endif
120 clear_bit(m->mpc_busid, mp_bus_not_pci);
121 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
122 mp_current_pci_id++;
123#if defined(CONFIG_EISA) || defined (CONFIG_MCA)
124 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
125 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA) - 1) == 0) {
126 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
127 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA) - 1) == 0) {
128 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
129#endif
130 } else
131 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
132}
133
134static int bad_ioapic(unsigned long address)
135{
136 if (nr_ioapics >= MAX_IO_APICS) {
137 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
138 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
139 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
140 }
141 if (!address) {
142 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
143 " found in table, skipping!\n");
144 return 1;
145 }
146 return 0;
147}
148
149static void __init MP_ioapic_info(struct mpc_config_ioapic *m)
150{
151 if (!(m->mpc_flags & MPC_APIC_USABLE))
152 return;
153
154 printk(KERN_INFO "I/O APIC #%d at 0x%X.\n", m->mpc_apicid,
155 m->mpc_apicaddr);
156
157 if (bad_ioapic(m->mpc_apicaddr))
158 return;
159
160 mp_ioapics[nr_ioapics] = *m;
161 nr_ioapics++;
162}
163
164static void __init MP_intsrc_info(struct mpc_config_intsrc *m)
165{
166 mp_irqs[mp_irq_entries] = *m;
167 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
168 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
169 m->mpc_irqtype, m->mpc_irqflag & 3,
170 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
171 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
172 if (++mp_irq_entries >= MAX_IRQ_SOURCES)
173 panic("Max # of irq sources exceeded!!\n");
174}
175
176static void __init MP_lintsrc_info(struct mpc_config_lintsrc *m)
177{
178 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
179 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
180 m->mpc_irqtype, m->mpc_irqflag & 3,
181 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbusid,
182 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
183}
184
185/*
186 * Read/parse the MPC
187 */
188static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early)
189{
190 char str[16];
191 char oem[10];
192 int count = sizeof(*mpc);
193 unsigned char *mpt = ((unsigned char *)mpc) + count;
194
195 if (memcmp(mpc->mpc_signature, MPC_SIGNATURE, 4)) {
196 printk(KERN_ERR "MPTABLE: bad signature [%c%c%c%c]!\n",
197 mpc->mpc_signature[0], mpc->mpc_signature[1],
198 mpc->mpc_signature[2], mpc->mpc_signature[3]);
199 return 0;
200 }
201 if (mpf_checksum((unsigned char *)mpc, mpc->mpc_length)) {
202 printk(KERN_ERR "MPTABLE: checksum error!\n");
203 return 0;
204 }
205 if (mpc->mpc_spec != 0x01 && mpc->mpc_spec != 0x04) {
206 printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n",
207 mpc->mpc_spec);
208 return 0;
209 }
210 if (!mpc->mpc_lapic) {
211 printk(KERN_ERR "MPTABLE: null local APIC address!\n");
212 return 0;
213 }
214 memcpy(oem, mpc->mpc_oem, 8);
215 oem[8] = 0;
216 printk(KERN_INFO "MPTABLE: OEM ID: %s ", oem);
217
218 memcpy(str, mpc->mpc_productid, 12);
219 str[12] = 0;
220 printk("Product ID: %s ", str);
221
222#ifdef CONFIG_X86_32
223 mps_oem_check(mpc, oem, str);
224#endif
225 printk(KERN_INFO "MPTABLE: Product ID: %s ", str);
226
227 printk(KERN_INFO "MPTABLE: APIC at: 0x%X\n", mpc->mpc_lapic);
228
229 /* save the local APIC address, it might be non-default */
230 if (!acpi_lapic)
231 mp_lapic_addr = mpc->mpc_lapic;
232
233 if (early)
234 return 1;
235
236 /*
237 * Now process the configuration blocks.
238 */
239#ifdef CONFIG_X86_NUMAQ
240 mpc_record = 0;
241#endif
242 while (count < mpc->mpc_length) {
243 switch (*mpt) {
244 case MP_PROCESSOR:
245 {
246 struct mpc_config_processor *m =
247 (struct mpc_config_processor *)mpt;
248 /* ACPI may have already provided this data */
249 if (!acpi_lapic)
250 MP_processor_info(m);
251 mpt += sizeof(*m);
252 count += sizeof(*m);
253 break;
254 }
255 case MP_BUS:
256 {
257 struct mpc_config_bus *m =
258 (struct mpc_config_bus *)mpt;
259 MP_bus_info(m);
260 mpt += sizeof(*m);
261 count += sizeof(*m);
262 break;
263 }
264 case MP_IOAPIC:
265 {
266 struct mpc_config_ioapic *m =
267 (struct mpc_config_ioapic *)mpt;
268 MP_ioapic_info(m);
269 mpt += sizeof(*m);
270 count += sizeof(*m);
271 break;
272 }
273 case MP_INTSRC:
274 {
275 struct mpc_config_intsrc *m =
276 (struct mpc_config_intsrc *)mpt;
277
278 MP_intsrc_info(m);
279 mpt += sizeof(*m);
280 count += sizeof(*m);
281 break;
282 }
283 case MP_LINTSRC:
284 {
285 struct mpc_config_lintsrc *m =
286 (struct mpc_config_lintsrc *)mpt;
287 MP_lintsrc_info(m);
288 mpt += sizeof(*m);
289 count += sizeof(*m);
290 break;
291 }
292 default:
293 {
294 count = mpc->mpc_length;
295 break;
296 }
297 }
298#ifdef CONFIG_X86_NUMAQ
299 ++mpc_record;
300#endif
301 }
302 setup_apic_routing();
303 if (!num_processors)
304 printk(KERN_ERR "MPTABLE: no processors registered!\n");
305 return num_processors;
306}
307
308static int __init ELCR_trigger(unsigned int irq)
309{
310 unsigned int port;
311
312 port = 0x4d0 + (irq >> 3);
313 return (inb(port) >> (irq & 7)) & 1;
314}
315
316static void __init construct_default_ioirq_mptable(int mpc_default_type)
317{
318 struct mpc_config_intsrc intsrc;
319 int i;
320 int ELCR_fallback = 0;
321
322 intsrc.mpc_type = MP_INTSRC;
323 intsrc.mpc_irqflag = 0; /* conforming */
324 intsrc.mpc_srcbus = 0;
325 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
326
327 intsrc.mpc_irqtype = mp_INT;
328
329 /*
330 * If true, we have an ISA/PCI system with no IRQ entries
331 * in the MP table. To prevent the PCI interrupts from being set up
332 * incorrectly, we try to use the ELCR. The sanity check to see if
333 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
334 * never be level sensitive, so we simply see if the ELCR agrees.
335 * If it does, we assume it's valid.
336 */
337 if (mpc_default_type == 5) {
338 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... "
339 "falling back to ELCR\n");
340
341 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) ||
342 ELCR_trigger(13))
343 printk(KERN_ERR "ELCR contains invalid data... "
344 "not using ELCR\n");
345 else {
346 printk(KERN_INFO
347 "Using ELCR to identify PCI interrupts\n");
348 ELCR_fallback = 1;
349 }
350 }
351
352 for (i = 0; i < 16; i++) {
353 switch (mpc_default_type) {
354 case 2:
355 if (i == 0 || i == 13)
356 continue; /* IRQ0 & IRQ13 not connected */
357 /* fall through */
358 default:
359 if (i == 2)
360 continue; /* IRQ2 is never connected */
361 }
362
363 if (ELCR_fallback) {
364 /*
365 * If the ELCR indicates a level-sensitive interrupt, we
366 * copy that information over to the MP table in the
367 * irqflag field (level sensitive, active high polarity).
368 */
369 if (ELCR_trigger(i))
370 intsrc.mpc_irqflag = 13;
371 else
372 intsrc.mpc_irqflag = 0;
373 }
374
375 intsrc.mpc_srcbusirq = i;
376 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
377 MP_intsrc_info(&intsrc);
378 }
379
380 intsrc.mpc_irqtype = mp_ExtINT;
381 intsrc.mpc_srcbusirq = 0;
382 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
383 MP_intsrc_info(&intsrc);
384}
385
386static inline void __init construct_default_ISA_mptable(int mpc_default_type)
387{
388 struct mpc_config_processor processor;
389 struct mpc_config_bus bus;
390 struct mpc_config_ioapic ioapic;
391 struct mpc_config_lintsrc lintsrc;
392 int linttypes[2] = { mp_ExtINT, mp_NMI };
393 int i;
394
395 /*
396 * local APIC has default address
397 */
398 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
399
400 /*
401 * 2 CPUs, numbered 0 & 1.
402 */
403 processor.mpc_type = MP_PROCESSOR;
404 /* Either an integrated APIC or a discrete 82489DX. */
405 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
406 processor.mpc_cpuflag = CPU_ENABLED;
407 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
408 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
409 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
410 processor.mpc_reserved[0] = 0;
411 processor.mpc_reserved[1] = 0;
412 for (i = 0; i < 2; i++) {
413 processor.mpc_apicid = i;
414 MP_processor_info(&processor);
415 }
416
417 bus.mpc_type = MP_BUS;
418 bus.mpc_busid = 0;
419 switch (mpc_default_type) {
420 default:
421 printk(KERN_ERR "???\nUnknown standard configuration %d\n",
422 mpc_default_type);
423 /* fall through */
424 case 1:
425 case 5:
426 memcpy(bus.mpc_bustype, "ISA ", 6);
427 break;
428 case 2:
429 case 6:
430 case 3:
431 memcpy(bus.mpc_bustype, "EISA ", 6);
432 break;
433 case 4:
434 case 7:
435 memcpy(bus.mpc_bustype, "MCA ", 6);
436 }
437 MP_bus_info(&bus);
438 if (mpc_default_type > 4) {
439 bus.mpc_busid = 1;
440 memcpy(bus.mpc_bustype, "PCI ", 6);
441 MP_bus_info(&bus);
442 }
443
444 ioapic.mpc_type = MP_IOAPIC;
445 ioapic.mpc_apicid = 2;
446 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
447 ioapic.mpc_flags = MPC_APIC_USABLE;
448 ioapic.mpc_apicaddr = 0xFEC00000;
449 MP_ioapic_info(&ioapic);
450
451 /*
452 * We set up most of the low 16 IO-APIC pins according to MPS rules.
453 */
454 construct_default_ioirq_mptable(mpc_default_type);
455
456 lintsrc.mpc_type = MP_LINTSRC;
457 lintsrc.mpc_irqflag = 0; /* conforming */
458 lintsrc.mpc_srcbusid = 0;
459 lintsrc.mpc_srcbusirq = 0;
460 lintsrc.mpc_destapic = MP_APIC_ALL;
461 for (i = 0; i < 2; i++) {
462 lintsrc.mpc_irqtype = linttypes[i];
463 lintsrc.mpc_destapiclint = i;
464 MP_lintsrc_info(&lintsrc);
465 }
466}
467
468static struct intel_mp_floating *mpf_found;
469
470/*
471 * Scan the memory blocks for an SMP configuration block.
472 */
473static void __init __get_smp_config(unsigned early)
474{
475 struct intel_mp_floating *mpf = mpf_found;
476
477 if (acpi_lapic && early)
478 return;
479 /*
480 * ACPI supports both logical (e.g. Hyper-Threading) and physical
481 * processors, where MPS only supports physical.
482 */
483 if (acpi_lapic && acpi_ioapic) {
484 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration "
485 "information\n");
486 return;
487 } else if (acpi_lapic)
488 printk(KERN_INFO "Using ACPI for processor (LAPIC) "
489 "configuration information\n");
490
491 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n",
492 mpf->mpf_specification);
493#ifdef CONFIG_X86_32
494 if (mpf->mpf_feature2 & (1 << 7)) {
495 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
496 pic_mode = 1;
497 } else {
498 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
499 pic_mode = 0;
500 }
501#endif
502 /*
503 * Now see if we need to read further.
504 */
505 if (mpf->mpf_feature1 != 0) {
506 if (early) {
507 /*
508 * local APIC has default address
509 */
510 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
511 return;
512 }
513
514 printk(KERN_INFO "Default MP configuration #%d\n",
515 mpf->mpf_feature1);
516 construct_default_ISA_mptable(mpf->mpf_feature1);
517
518 } else if (mpf->mpf_physptr) {
519
520 /*
521 * Read the physical hardware table. Anything here will
522 * override the defaults.
523 */
524 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr), early)) {
525 smp_found_config = 0;
526 printk(KERN_ERR
527 "BIOS bug, MP table errors detected!...\n");
528 printk(KERN_ERR "... disabling SMP support. "
529 "(tell your hw vendor)\n");
530 return;
531 }
532
533 if (early)
534 return;
535 /*
536 * If there are no explicit MP IRQ entries, then we are
537 * broken. We set up most of the low 16 IO-APIC pins to
538 * ISA defaults and hope it will work.
539 */
540 if (!mp_irq_entries) {
541 struct mpc_config_bus bus;
542
543 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, "
544 "using default mptable. "
545 "(tell your hw vendor)\n");
546
547 bus.mpc_type = MP_BUS;
548 bus.mpc_busid = 0;
549 memcpy(bus.mpc_bustype, "ISA ", 6);
550 MP_bus_info(&bus);
551
552 construct_default_ioirq_mptable(0);
553 }
554
555 } else
556 BUG();
557
558 if (!early)
559 printk(KERN_INFO "Processors: %d\n", num_processors);
560 /*
561 * Only use the first configuration found.
562 */
563}
564
565void __init early_get_smp_config(void)
566{
567 __get_smp_config(1);
568}
569
570void __init get_smp_config(void)
571{
572 __get_smp_config(0);
573}
574
575static int __init smp_scan_config(unsigned long base, unsigned long length,
576 unsigned reserve)
577{
578 extern void __bad_mpf_size(void);
579 unsigned int *bp = phys_to_virt(base);
580 struct intel_mp_floating *mpf;
581
582 Dprintk("Scan SMP from %p for %ld bytes.\n", bp, length);
583 if (sizeof(*mpf) != 16)
584 __bad_mpf_size();
585
586 while (length > 0) {
587 mpf = (struct intel_mp_floating *)bp;
588 if ((*bp == SMP_MAGIC_IDENT) &&
589 (mpf->mpf_length == 1) &&
590 !mpf_checksum((unsigned char *)bp, 16) &&
591 ((mpf->mpf_specification == 1)
592 || (mpf->mpf_specification == 4))) {
593
594 smp_found_config = 1;
595 mpf_found = mpf;
596#ifdef CONFIG_X86_32
597 printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n",
598 mpf, virt_to_phys(mpf));
599 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE,
600 BOOTMEM_DEFAULT);
601 if (mpf->mpf_physptr) {
602 /*
603 * We cannot access to MPC table to compute
604 * table size yet, as only few megabytes from
605 * the bottom is mapped now.
606 * PC-9800's MPC table places on the very last
607 * of physical memory; so that simply reserving
608 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
609 * in reserve_bootmem.
610 */
611 unsigned long size = PAGE_SIZE;
612 unsigned long end = max_low_pfn * PAGE_SIZE;
613 if (mpf->mpf_physptr + size > end)
614 size = end - mpf->mpf_physptr;
615 reserve_bootmem(mpf->mpf_physptr, size,
616 BOOTMEM_DEFAULT);
617 }
618
619#else
620 if (!reserve)
621 return 1;
622
623 reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
624 if (mpf->mpf_physptr)
625 reserve_bootmem_generic(mpf->mpf_physptr,
626 PAGE_SIZE);
627#endif
628 return 1;
629 }
630 bp += 4;
631 length -= 16;
632 }
633 return 0;
634}
635
636static void __init __find_smp_config(unsigned reserve)
637{
638 unsigned int address;
639
640 /*
641 * FIXME: Linux assumes you have 640K of base ram..
642 * this continues the error...
643 *
644 * 1) Scan the bottom 1K for a signature
645 * 2) Scan the top 1K of base RAM
646 * 3) Scan the 64K of bios
647 */
648 if (smp_scan_config(0x0, 0x400, reserve) ||
649 smp_scan_config(639 * 0x400, 0x400, reserve) ||
650 smp_scan_config(0xF0000, 0x10000, reserve))
651 return;
652 /*
653 * If it is an SMP machine we should know now.
654 *
655 * there is a real-mode segmented pointer pointing to the
656 * 4K EBDA area at 0x40E, calculate and scan it here.
657 *
658 * NOTE! There are Linux loaders that will corrupt the EBDA
659 * area, and as such this kind of SMP config may be less
660 * trustworthy, simply because the SMP table may have been
661 * stomped on during early boot. These loaders are buggy and
662 * should be fixed.
663 *
664 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
665 */
666
667 address = get_bios_ebda();
668 if (address)
669 smp_scan_config(address, 0x400, reserve);
670}
671
672void __init early_find_smp_config(void)
673{
674 __find_smp_config(0);
675}
676
677void __init find_smp_config(void)
678{
679 __find_smp_config(1);
680}
681
682/* --------------------------------------------------------------------------
683 ACPI-based MP Configuration
684 -------------------------------------------------------------------------- */
685
686#ifdef CONFIG_ACPI
687
688#ifdef CONFIG_X86_IO_APIC
689
690#define MP_ISA_BUS 0
691#define MP_MAX_IOAPIC_PIN 127
692
693extern struct mp_ioapic_routing mp_ioapic_routing[MAX_IO_APICS];
694
695static int mp_find_ioapic(int gsi)
696{
697 int i = 0;
698
699 /* Find the IOAPIC that manages this GSI. */
700 for (i = 0; i < nr_ioapics; i++) {
701 if ((gsi >= mp_ioapic_routing[i].gsi_base)
702 && (gsi <= mp_ioapic_routing[i].gsi_end))
703 return i;
704 }
705
706 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
707 return -1;
708}
709
710static u8 uniq_ioapic_id(u8 id)
711{
712#ifdef CONFIG_X86_32
713 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
714 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
715 return io_apic_get_unique_id(nr_ioapics, id);
716 else
717 return id;
718#else
719 int i;
720 DECLARE_BITMAP(used, 256);
721 bitmap_zero(used, 256);
722 for (i = 0; i < nr_ioapics; i++) {
723 struct mpc_config_ioapic *ia = &mp_ioapics[i];
724 __set_bit(ia->mpc_apicid, used);
725 }
726 if (!test_bit(id, used))
727 return id;
728 return find_first_zero_bit(used, 256);
729#endif
730}
731
732void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
733{
734 int idx = 0;
735
736 if (bad_ioapic(address))
737 return;
738
739 idx = nr_ioapics;
740
741 mp_ioapics[idx].mpc_type = MP_IOAPIC;
742 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
743 mp_ioapics[idx].mpc_apicaddr = address;
744
745 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
746 mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id);
747#ifdef CONFIG_X86_32
748 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
749#else
750 mp_ioapics[idx].mpc_apicver = 0;
751#endif
752 /*
753 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
754 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
755 */
756 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
757 mp_ioapic_routing[idx].gsi_base = gsi_base;
758 mp_ioapic_routing[idx].gsi_end = gsi_base +
759 io_apic_get_redir_entries(idx);
760
761 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, address 0x%x, "
762 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
763 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
764 mp_ioapic_routing[idx].gsi_base, mp_ioapic_routing[idx].gsi_end);
765
766 nr_ioapics++;
767}
768
769void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
770{
771 struct mpc_config_intsrc intsrc;
772 int ioapic = -1;
773 int pin = -1;
774
775 /*
776 * Convert 'gsi' to 'ioapic.pin'.
777 */
778 ioapic = mp_find_ioapic(gsi);
779 if (ioapic < 0)
780 return;
781 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
782
783 /*
784 * TBD: This check is for faulty timer entries, where the override
785 * erroneously sets the trigger to level, resulting in a HUGE
786 * increase of timer interrupts!
787 */
788 if ((bus_irq == 0) && (trigger == 3))
789 trigger = 1;
790
791 intsrc.mpc_type = MP_INTSRC;
792 intsrc.mpc_irqtype = mp_INT;
793 intsrc.mpc_irqflag = (trigger << 2) | polarity;
794 intsrc.mpc_srcbus = MP_ISA_BUS;
795 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
796 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
797 intsrc.mpc_dstirq = pin; /* INTIN# */
798
799 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
800 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
801 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
802 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
803
804 mp_irqs[mp_irq_entries] = intsrc;
805 if (++mp_irq_entries == MAX_IRQ_SOURCES)
806 panic("Max # of irq sources exceeded!\n");
807}
808
809int es7000_plat;
810
811void __init mp_config_acpi_legacy_irqs(void)
812{
813 struct mpc_config_intsrc intsrc;
814 int i = 0;
815 int ioapic = -1;
816
817#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
818 /*
819 * Fabricate the legacy ISA bus (bus #31).
820 */
821 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
822#endif
823 set_bit(MP_ISA_BUS, mp_bus_not_pci);
824 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
825
826 /*
827 * Older generations of ES7000 have no legacy identity mappings
828 */
829 if (es7000_plat == 1)
830 return;
831
832 /*
833 * Locate the IOAPIC that manages the ISA IRQs (0-15).
834 */
835 ioapic = mp_find_ioapic(0);
836 if (ioapic < 0)
837 return;
838
839 intsrc.mpc_type = MP_INTSRC;
840 intsrc.mpc_irqflag = 0; /* Conforming */
841 intsrc.mpc_srcbus = MP_ISA_BUS;
842 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
843
844 /*
845 * Use the default configuration for the IRQs 0-15. Unless
846 * overridden by (MADT) interrupt source override entries.
847 */
848 for (i = 0; i < 16; i++) {
849 int idx;
850
851 for (idx = 0; idx < mp_irq_entries; idx++) {
852 struct mpc_config_intsrc *irq = mp_irqs + idx;
853
854 /* Do we already have a mapping for this ISA IRQ? */
855 if (irq->mpc_srcbus == MP_ISA_BUS
856 && irq->mpc_srcbusirq == i)
857 break;
858
859 /* Do we already have a mapping for this IOAPIC pin */
860 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
861 (irq->mpc_dstirq == i))
862 break;
863 }
864
865 if (idx != mp_irq_entries) {
866 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
867 continue; /* IRQ already used */
868 }
869
870 intsrc.mpc_irqtype = mp_INT;
871 intsrc.mpc_srcbusirq = i; /* Identity mapped */
872 intsrc.mpc_dstirq = i;
873
874 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
875 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
876 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
877 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
878 intsrc.mpc_dstirq);
879
880 mp_irqs[mp_irq_entries] = intsrc;
881 if (++mp_irq_entries == MAX_IRQ_SOURCES)
882 panic("Max # of irq sources exceeded!\n");
883 }
884}
885
886int mp_register_gsi(u32 gsi, int triggering, int polarity)
887{
888 int ioapic = -1;
889 int ioapic_pin = 0;
890 int idx, bit = 0;
891#ifdef CONFIG_X86_32
892#define MAX_GSI_NUM 4096
893#define IRQ_COMPRESSION_START 64
894
895 static int pci_irq = IRQ_COMPRESSION_START;
896 /*
897 * Mapping between Global System Interrupts, which
898 * represent all possible interrupts, and IRQs
899 * assigned to actual devices.
900 */
901 static int gsi_to_irq[MAX_GSI_NUM];
902#else
903
904 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
905 return gsi;
906#endif
907
908 /* Don't set up the ACPI SCI because it's already set up */
909 if (acpi_gbl_FADT.sci_interrupt == gsi)
910 return gsi;
911
912 ioapic = mp_find_ioapic(gsi);
913 if (ioapic < 0) {
914 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
915 return gsi;
916 }
917
918 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
919
920#ifdef CONFIG_X86_32
921 if (ioapic_renumber_irq)
922 gsi = ioapic_renumber_irq(ioapic, gsi);
923#endif
924
925 /*
926 * Avoid pin reprogramming. PRTs typically include entries
927 * with redundant pin->gsi mappings (but unique PCI devices);
928 * we only program the IOAPIC on the first.
929 */
930 bit = ioapic_pin % 32;
931 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
932 if (idx > 3) {
933 printk(KERN_ERR "Invalid reference to IOAPIC pin "
934 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
935 ioapic_pin);
936 return gsi;
937 }
938 if ((1 << bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
939 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
940 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
941#ifdef CONFIG_X86_32
942 return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
943#else
944 return gsi;
945#endif
946 }
947
948 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1 << bit);
949#ifdef CONFIG_X86_32
950 /*
951 * For GSI >= 64, use IRQ compression
952 */
953 if ((gsi >= IRQ_COMPRESSION_START)
954 && (triggering == ACPI_LEVEL_SENSITIVE)) {
955 /*
956 * For PCI devices assign IRQs in order, avoiding gaps
957 * due to unused I/O APIC pins.
958 */
959 int irq = gsi;
960 if (gsi < MAX_GSI_NUM) {
961 /*
962 * Retain the VIA chipset work-around (gsi > 15), but
963 * avoid a problem where the 8254 timer (IRQ0) is setup
964 * via an override (so it's not on pin 0 of the ioapic),
965 * and at the same time, the pin 0 interrupt is a PCI
966 * type. The gsi > 15 test could cause these two pins
967 * to be shared as IRQ0, and they are not shareable.
968 * So test for this condition, and if necessary, avoid
969 * the pin collision.
970 */
971 gsi = pci_irq++;
972 /*
973 * Don't assign IRQ used by ACPI SCI
974 */
975 if (gsi == acpi_gbl_FADT.sci_interrupt)
976 gsi = pci_irq++;
977 gsi_to_irq[irq] = gsi;
978 } else {
979 printk(KERN_ERR "GSI %u is too high\n", gsi);
980 return gsi;
981 }
982 }
983#endif
984 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
985 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
986 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
987 return gsi;
988}
989
990#endif /* CONFIG_X86_IO_APIC */
991#endif /* CONFIG_ACPI */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 01:58:47 -0500