641 files changed, 41056 insertions, 12333 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index dbfdf87f993f..e02b893fb909 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -241,6 +241,7 @@ config ARCH_VERSATILE
 config ARCH_AT91
         bool "Atmel AT91"
         select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
         select HAVE_CLK
         help
           This enables support for systems based on the Atmel AT91RM9200,
@@ -275,6 +276,14 @@ config ARCH_EP93XX
         help
           This enables support for the Cirrus EP93xx series of CPUs.
 
+config ARCH_GEMINI
+        bool "Cortina Systems Gemini"
+        select CPU_FA526
+        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
+        help
+          Support for the Cortina Systems Gemini family SoCs
+
 config ARCH_FOOTBRIDGE
         bool "FootBridge"
         select CPU_SA110
@@ -477,12 +486,29 @@ config ARCH_PXA
         select HAVE_CLK
         select COMMON_CLKDEV
         select ARCH_REQUIRE_GPIOLIB
+        select HAVE_CLK
+        select COMMON_CLKDEV
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
         select TICK_ONESHOT
+        select PLAT_PXA
         help
           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 
+config ARCH_MMP
+        bool "Marvell PXA168/910"
+        depends on MMU
+        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
+        select HAVE_CLK
+        select COMMON_CLKDEV
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select TICK_ONESHOT
+        select PLAT_PXA
+        help
+          Support for Marvell's PXA168/910 processor line.
+
 config ARCH_RPC
         bool "RiscPC"
         select ARCH_ACORN
@@ -598,6 +624,8 @@ source "arch/arm/mach-ep93xx/Kconfig"
 
 source "arch/arm/mach-footbridge/Kconfig"
 
+source "arch/arm/mach-gemini/Kconfig"
+
 source "arch/arm/mach-integrator/Kconfig"
 
 source "arch/arm/mach-iop32x/Kconfig"
@@ -617,6 +645,9 @@ source "arch/arm/mach-loki/Kconfig"
 source "arch/arm/mach-mv78xx0/Kconfig"
 
 source "arch/arm/mach-pxa/Kconfig"
+source "arch/arm/plat-pxa/Kconfig"
+
+source "arch/arm/mach-mmp/Kconfig"
 
 source "arch/arm/mach-sa1100/Kconfig"
 
@@ -686,12 +717,15 @@ config PLAT_IOP
 config PLAT_ORION
         bool
 
+config PLAT_PXA
+        bool
+
 source arch/arm/mm/Kconfig
 
 config IWMMXT
         bool "Enable iWMMXt support"
-        depends on CPU_XSCALE || CPU_XSC3
-        default y if PXA27x || PXA3xx
+        depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK
+        default y if PXA27x || PXA3xx || ARCH_MMP
         help
           Enable support for iWMMXt context switching at run time if
           running on a CPU that supports it.
@@ -915,6 +949,23 @@ config NODES_SHIFT
         default "2"
         depends on NEED_MULTIPLE_NODES
 
+config HIGHMEM
+        bool "High Memory Support (EXPERIMENTAL)"
+        depends on MMU && EXPERIMENTAL
+        help
+          The address space of ARM processors is only 4 Gigabytes large
+          and it has to accommodate user address space, kernel address
+          space as well as some memory mapped IO. That means that, if you
+          have a large amount of physical memory and/or IO, not all of the
+          memory can be "permanently mapped" by the kernel. The physical
+          memory that is not permanently mapped is called "high memory".
+
+          Depending on the selected kernel/user memory split, minimum
+          vmalloc space and actual amount of RAM, you may not need this
+          option which should result in a slightly faster kernel.
+
+          If unsure, say n.
+
 source "mm/Kconfig"
 
 config LEDS
@@ -1092,7 +1143,7 @@ source "drivers/cpufreq/Kconfig"
 
 config CPU_FREQ_SA1100
         bool
-        depends on CPU_FREQ && (SA1100_H3100 || SA1100_H3600 || SA1100_H3800 || SA1100_LART || SA1100_PLEB || SA1100_BADGE4 || SA1100_HACKKIT)
+        depends on CPU_FREQ && (SA1100_H3100 || SA1100_H3600 || SA1100_LART || SA1100_PLEB || SA1100_BADGE4 || SA1100_HACKKIT)
         default y
 
 config CPU_FREQ_SA1110
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 192ee01a9ba2..a71fd941ade7 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -2,18 +2,29 @@ menu "Kernel hacking"
 
 source "lib/Kconfig.debug"
 
-# RMK wants arm kernels compiled with frame pointers so hardwire this to y.
+# RMK wants arm kernels compiled with frame pointers or stack unwinding.
 # If you know what you are doing and are willing to live without stack
 # traces, you can get a slightly smaller kernel by setting this option to
 # n, but then RMK will have to kill you ;).
 config FRAME_POINTER
         bool
-        default y
+        default y if !ARM_UNWIND
         help
           If you say N here, the resulting kernel will be slightly smaller and
-          faster. However, when a problem occurs with the kernel, the
-          information that is reported is severely limited. Most people
-          should say Y here.
+          faster. However, if neither FRAME_POINTER nor ARM_UNWIND are enabled,
+          when a problem occurs with the kernel, the information that is
+          reported is severely limited.
+
+config ARM_UNWIND
+        bool "Enable stack unwinding support"
+        depends on AEABI && EXPERIMENTAL
+        default y
+        help
+          This option enables stack unwinding support in the kernel
+          using the information automatically generated by the
+          compiler. The resulting kernel image is slightly bigger but
+          the performance is not affected. Currently, this feature
+          only works with EABI compilers. If unsure say Y.
 
 config DEBUG_USER
         bool "Verbose user fault messages"
@@ -66,7 +77,7 @@ config DEBUG_ICEDCC
           Say Y here if you want the debug print routines to direct their
           output to the EmbeddedICE macrocell's DCC channel using
           co-processor 14. This is known to work on the ARM9 style ICE
-          channel.
+          channel and on the XScale with the PEEDI.
 
           It does include a timeout to ensure that the system does not
           totally freeze when there is nothing connected to read.
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 24e0f0187697..e84729bf13d4 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -72,6 +72,7 @@ tune-$(CONFIG_CPU_ARM920T)	:=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_ARM922T)      :=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_ARM925T)      :=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_ARM926T)      :=-mtune=arm9tdmi
+tune-$(CONFIG_CPU_FA526)        :=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_SA110)        :=-mtune=strongarm110
 tune-$(CONFIG_CPU_SA1100)       :=-mtune=strongarm1100
 tune-$(CONFIG_CPU_XSCALE)       :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
@@ -85,6 +86,10 @@ else
 CFLAGS_ABI      :=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) $(call cc-option,-mno-thumb-interwork,)
 endif
 
+ifeq ($(CONFIG_ARM_UNWIND),y)
+CFLAGS_ABI      +=-funwind-tables
+endif
+
 # Need -Uarm for gcc < 3.x
 KBUILD_CFLAGS   +=$(CFLAGS_ABI) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm
 KBUILD_AFLAGS   +=$(CFLAGS_ABI) $(arch-y) $(tune-y) -msoft-float
@@ -105,8 +110,11 @@ ifeq ($(CONFIG_ARCH_SA1100),y)
  textofs-$(CONFIG_SA1111)          := 0x00208000
 endif
  machine-$(CONFIG_ARCH_PXA)        := pxa
+ machine-$(CONFIG_ARCH_MMP)        := mmp
+    plat-$(CONFIG_PLAT_PXA)        := pxa
  machine-$(CONFIG_ARCH_L7200)      := l7200
  machine-$(CONFIG_ARCH_INTEGRATOR) := integrator
+ machine-$(CONFIG_ARCH_GEMINI)     := gemini
  textofs-$(CONFIG_ARCH_CLPS711X)   := 0x00028000
  machine-$(CONFIG_ARCH_CLPS711X)   := clps711x
  machine-$(CONFIG_ARCH_IOP32X)     := iop32x
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 77d614232d81..b371fba1b954 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -27,6 +27,12 @@
                 .macro  writeb, ch, rb
                 mcr     p14, 0, \ch, c0, c5, 0
                 .endm
+#elif defined(CONFIG_CPU_XSCALE)
+                .macro  loadsp, rb
+                .endm
+                .macro  writeb, ch, rb
+                mcr     p14, 0, \ch, c8, c0, 0
+                .endm
 #else
                 .macro  loadsp, rb
                 .endm
@@ -459,6 +465,20 @@ __armv7_mmu_cache_on:
                 mcr     p15, 0, r0, c7, c5, 4   @ ISB
                 mov     pc, r12
 
+__fa526_cache_on:
+                mov     r12, lr
+                bl      __setup_mmu
+                mov     r0, #0
+                mcr     p15, 0, r0, c7, c7, 0   @ Invalidate whole cache
+                mcr     p15, 0, r0, c7, c10, 4  @ drain write buffer
+                mcr     p15, 0, r0, c8, c7, 0   @ flush UTLB
+                mrc     p15, 0, r0, c1, c0, 0   @ read control reg
+                orr     r0, r0, #0x1000         @ I-cache enable
+                bl      __common_mmu_cache_on
+                mov     r0, #0
+                mcr     p15, 0, r0, c8, c7, 0   @ flush UTLB
+                mov     pc, r12
+
 __arm6_mmu_cache_on:
                 mov     r12, lr
                 bl      __setup_mmu
@@ -630,12 +650,30 @@ proc_types:
                 b       __armv4_mmu_cache_off
                 b       __armv4_mmu_cache_flush
 
+                .word   0x56158000              @ PXA168
+                .word   0xfffff000
+                b __armv4_mmu_cache_on
+                b __armv4_mmu_cache_off
+                b __armv5tej_mmu_cache_flush
+
+                .word   0x56056930
+                .word   0xff0ffff0              @ PXA935
+                b       __armv4_mmu_cache_on
+                b       __armv4_mmu_cache_off
+                b       __armv4_mmu_cache_flush
+
                 .word   0x56050000              @ Feroceon
                 .word   0xff0f0000
                 b       __armv4_mmu_cache_on
                 b       __armv4_mmu_cache_off
                 b       __armv5tej_mmu_cache_flush
 
+                .word   0x66015261              @ FA526
+                .word   0xff01fff1
+                b       __fa526_cache_on
+                b       __armv4_mmu_cache_off
+                b       __fa526_cache_flush
+
                 @ These match on the architecture ID
 
                 .word   0x00020000              @ ARMv4T
@@ -775,6 +813,12 @@ __armv4_mpu_cache_flush:
                 mcr     p15, 0, ip, c7, c10, 4  @ drain WB
                 mov     pc, lr
                 
+__fa526_cache_flush:
+                mov     r1, #0
+                mcr     p15, 0, r1, c7, c14, 0  @ clean and invalidate D cache
+                mcr     p15, 0, r1, c7, c5, 0   @ flush I cache
+                mcr     p15, 0, r1, c7, c10, 4  @ drain WB
+                mov     pc, lr
 
 __armv6_mmu_cache_flush:
                 mov     r1, #0
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 3fc08413fff0..393c81641314 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -46,6 +46,21 @@ static void icedcc_putc(int ch)
 
         asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch));
 }
+#elif defined(CONFIG_CPU_XSCALE)
+
+static void icedcc_putc(int ch)
+{
+        int status, i = 0x4000000;
+
+        do {
+                if (--i < 0)
+                        return;
+
+                asm volatile ("mrc p14, 0, %0, c14, c0, 0" : "=r" (status));
+        } while (status & (1 << 28));
+
+        asm("mcr p14, 0, %0, c8, c0, 0" : : "r" (ch));
+}
 
 #else
 
diff --git a/arch/arm/boot/compressed/vmlinux.lds.in b/arch/arm/boot/compressed/vmlinux.lds.in
index 153a07e7222b..a5924b9b88bd 100644
--- a/arch/arm/boot/compressed/vmlinux.lds.in
+++ b/arch/arm/boot/compressed/vmlinux.lds.in
@@ -11,6 +11,11 @@ OUTPUT_ARCH(arm)
 ENTRY(_start)
 SECTIONS
 {
+  /DISCARD/ : {
+    *(.ARM.exidx*)
+    *(.ARM.extab*)
+  }
+
   . = TEXT_START;
   _text = .;
 
diff --git a/arch/arm/common/clkdev.c b/arch/arm/common/clkdev.c
index 1037bba18329..5589444ff437 100644
--- a/arch/arm/common/clkdev.c
+++ b/arch/arm/common/clkdev.c
@@ -62,9 +62,8 @@ static struct clk *clk_find(const char *dev_id, const char *con_id)
         return clk;
 }
 
-struct clk *clk_get(struct device *dev, const char *con_id)
+struct clk *clk_get_sys(const char *dev_id, const char *con_id)
 {
-        const char *dev_id = dev ? dev_name(dev) : NULL;
         struct clk *clk;
 
         mutex_lock(&clocks_mutex);
@@ -75,6 +74,14 @@ struct clk *clk_get(struct device *dev, const char *con_id)
 
         return clk ? clk : ERR_PTR(-ENOENT);
 }
+EXPORT_SYMBOL(clk_get_sys);
+
+struct clk *clk_get(struct device *dev, const char *con_id)
+{
+        const char *dev_id = dev ? dev_name(dev) : NULL;
+
+        return clk_get_sys(dev_id, con_id);
+}
 EXPORT_SYMBOL(clk_get);
 
 void clk_put(struct clk *clk)
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
index f030f0775be7..734ac9135998 100644
--- a/arch/arm/common/dmabounce.c
+++ b/arch/arm/common/dmabounce.c
@@ -25,6 +25,7 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/slab.h>
+#include <linux/page-flags.h>
 #include <linux/device.h>
 #include <linux/dma-mapping.h>
 #include <linux/dmapool.h>
@@ -349,6 +350,12 @@ dma_addr_t dma_map_page(struct device *dev, struct page *page,
 
         BUG_ON(!valid_dma_direction(dir));
 
+        if (PageHighMem(page)) {
+                dev_err(dev, "DMA buffer bouncing of HIGHMEM pages "
+                             "is not supported\n");
+                return ~0;
+        }
+
         return map_single(dev, page_address(page) + offset, size, dir);
 }
 EXPORT_SYMBOL(dma_map_page);
diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c
index 697c64913990..7713a08bb10c 100644
--- a/arch/arm/common/scoop.c
+++ b/arch/arm/common/scoop.c
@@ -124,37 +124,6 @@ static int scoop_gpio_direction_output(struct gpio_chip *chip,
         return 0;
 }
 
-unsigned short set_scoop_gpio(struct device *dev, unsigned short bit)
-{
-        unsigned short gpio_bit;
-        unsigned long flag;
-        struct scoop_dev *sdev = dev_get_drvdata(dev);
-
-        spin_lock_irqsave(&sdev->scoop_lock, flag);
-        gpio_bit = ioread16(sdev->base + SCOOP_GPWR) | bit;
-        iowrite16(gpio_bit, sdev->base + SCOOP_GPWR);
-        spin_unlock_irqrestore(&sdev->scoop_lock, flag);
-
-        return gpio_bit;
-}
-
-unsigned short reset_scoop_gpio(struct device *dev, unsigned short bit)
-{
-        unsigned short gpio_bit;
-        unsigned long flag;
-        struct scoop_dev *sdev = dev_get_drvdata(dev);
-
-        spin_lock_irqsave(&sdev->scoop_lock, flag);
-        gpio_bit = ioread16(sdev->base + SCOOP_GPWR) & ~bit;
-        iowrite16(gpio_bit, sdev->base + SCOOP_GPWR);
-        spin_unlock_irqrestore(&sdev->scoop_lock, flag);
-
-        return gpio_bit;
-}
-
-EXPORT_SYMBOL(set_scoop_gpio);
-EXPORT_SYMBOL(reset_scoop_gpio);
-
 unsigned short read_scoop_reg(struct device *dev, unsigned short reg)
 {
         struct scoop_dev *sdev = dev_get_drvdata(dev);
diff --git a/arch/arm/common/sharpsl_pm.c b/arch/arm/common/sharpsl_pm.c
index 780bbf7cb26f..140f1d721d50 100644
--- a/arch/arm/common/sharpsl_pm.c
+++ b/arch/arm/common/sharpsl_pm.c
@@ -29,8 +29,8 @@
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <mach/pm.h>
-#include <mach/pxa-regs.h>
 #include <mach/pxa2xx-regs.h>
+#include <mach/regs-rtc.h>
 #include <mach/sharpsl.h>
 #include <asm/hardware/sharpsl_pm.h>
 
diff --git a/arch/arm/configs/acs5k_defconfig b/arch/arm/configs/acs5k_defconfig
new file mode 100644
index 000000000000..1cab4e79d368
--- /dev/null
+++ b/arch/arm/configs/acs5k_defconfig
@@ -0,0 +1,1233 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27-simtec-micrel1
+# Tue Dec 16 13:31:34 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+CONFIG_ARCH_KS8695=y
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Kendin/Micrel KS8695 Implementations
+#
+CONFIG_MACH_KS8695=y
+CONFIG_MACH_DSM320=y
+CONFIG_MACH_ACS5K=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM922T=y
+CONFIG_CPU_32v4T=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+CONFIG_PCI=y
+CONFIG_PCI_SYSCALL=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+CONFIG_PCI_DEBUG=y
+CONFIG_PCCARD=y
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=y
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+CONFIG_CARDBUS=y
+
+#
+# PC-card bridges
+#
+CONFIG_YENTA=y
+CONFIG_YENTA_O2=y
+CONFIG_YENTA_RICOH=y
+CONFIG_YENTA_TI=y
+CONFIG_YENTA_ENE_TUNE=y
+CONFIG_YENTA_TOSHIBA=y
+# CONFIG_PD6729 is not set
+# CONFIG_I82092 is not set
+CONFIG_PCCARD_NONSTATIC=y
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev/ram0 rw"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_GEOMETRY is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x8000000
+CONFIG_MTD_PHYSMAP_LEN=0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=4
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=8192
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_ARM_KS8695_ETHER=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+CONFIG_PRISM54=m
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_NET_PCMCIA is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_KS8695=y
+CONFIG_SERIAL_KS8695_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=m
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_ACS5KCAN=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Graphics adapter I2C/DDC channel drivers
+#
+# CONFIG_I2C_VOODOO3 is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+CONFIG_GPIO_PCA953X=y
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+# CONFIG_GPIO_BT8XX is not set
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_KS8695_WATCHDOG=y
+# CONFIG_ALIM7101_WDT is not set
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_USB is not set
+
+#
+# Enable Host or Gadget support to see Inventra options
+#
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+CONFIG_RTC_DRV_PCF8563=y
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+
+#
+# Voltage and Current regulators
+#
+# CONFIG_REGULATOR is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+# CONFIG_FTRACE is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/acs5k_tiny_defconfig b/arch/arm/configs/acs5k_tiny_defconfig
new file mode 100644
index 000000000000..8e3d084afd78
--- /dev/null
+++ b/arch/arm/configs/acs5k_tiny_defconfig
@@ -0,0 +1,941 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27-simtec-micrel1
+# Tue Jan  6 13:23:07 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+CONFIG_ARCH_KS8695=y
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Kendin/Micrel KS8695 Implementations
+#
+# CONFIG_MACH_KS8695 is not set
+# CONFIG_MACH_DSM320 is not set
+CONFIG_MACH_ACS5K=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM922T=y
+CONFIG_CPU_32v4T=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI is not set
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttyAM0,115200 init=/bin/sh"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_GEOMETRY is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x8000000
+CONFIG_MTD_PHYSMAP_LEN=0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=4
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+# CONFIG_BLK_DEV is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_ARM_KS8695_ETHER=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_LIBERTAS is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_KS8695=y
+CONFIG_SERIAL_KS8695_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_ACS5KCAN=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+CONFIG_GPIO_PCA953X=y
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_KS8695_WATCHDOG=y
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+CONFIG_RTC_DRV_PCF8563=y
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+
+#
+# Voltage and Current regulators
+#
+# CONFIG_REGULATOR is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_CRAMFS is not set
+CONFIG_SQUASHFS=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+# CONFIG_FTRACE is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/assabet_defconfig b/arch/arm/configs/assabet_defconfig
index b1cd331aaecf..c66dd399e426 100644
--- a/arch/arm/configs/assabet_defconfig
+++ b/arch/arm/configs/assabet_defconfig
@@ -89,7 +89,6 @@ CONFIG_SA1100_ASSABET=y
 # CONFIG_SA1100_COLLIE is not set
 # CONFIG_SA1100_H3100 is not set
 # CONFIG_SA1100_H3600 is not set
-# CONFIG_SA1100_H3800 is not set
 # CONFIG_SA1100_BADGE4 is not set
 # CONFIG_SA1100_JORNADA720 is not set
 # CONFIG_SA1100_HACKKIT is not set
diff --git a/arch/arm/configs/badge4_defconfig b/arch/arm/configs/badge4_defconfig
index 80222feb7dad..f264846218a2 100644
--- a/arch/arm/configs/badge4_defconfig
+++ b/arch/arm/configs/badge4_defconfig
@@ -91,7 +91,6 @@ CONFIG_ARCH_SA1100=y
 # CONFIG_SA1100_COLLIE is not set
 # CONFIG_SA1100_H3100 is not set
 # CONFIG_SA1100_H3600 is not set
-# CONFIG_SA1100_H3800 is not set
 CONFIG_SA1100_BADGE4=y
 # CONFIG_SA1100_JORNADA720 is not set
 # CONFIG_SA1100_HACKKIT is not set
diff --git a/arch/arm/configs/cerfcube_defconfig b/arch/arm/configs/cerfcube_defconfig
index ee130b528bd4..2b4c0668b1b4 100644
--- a/arch/arm/configs/cerfcube_defconfig
+++ b/arch/arm/configs/cerfcube_defconfig
@@ -93,7 +93,6 @@ CONFIG_SA1100_CERF_FLASH_16MB=y
 # CONFIG_SA1100_COLLIE is not set
 # CONFIG_SA1100_H3100 is not set
 # CONFIG_SA1100_H3600 is not set
-# CONFIG_SA1100_H3800 is not set
 # CONFIG_SA1100_BADGE4 is not set
 # CONFIG_SA1100_JORNADA720 is not set
 # CONFIG_SA1100_HACKKIT is not set
diff --git a/arch/arm/configs/xm_x2xx_defconfig b/arch/arm/configs/cm_x2xx_defconfig
index 1039f366bf8d..797b790cba78 100644
--- a/arch/arm/configs/xm_x2xx_defconfig
+++ b/arch/arm/configs/cm_x2xx_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.27-rc8
-# Sun Oct  5 11:05:36 2008
+# Linux kernel version: 2.6.29-rc2
+# Sun Feb  1 16:31:36 2009
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -22,7 +22,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_SUPPORTS_AOUT=y
 CONFIG_ZONE_DMA=y
 CONFIG_ARCH_MTD_XIP=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
@@ -47,12 +46,12 @@ CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
 CONFIG_GROUP_SCHED=y
 CONFIG_FAIR_GROUP_SCHED=y
 # CONFIG_RT_GROUP_SCHED is not set
 CONFIG_USER_SCHED=y
 # CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
@@ -80,27 +79,21 @@ CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
+CONFIG_AIO=y
 # CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_PCI_QUIRKS=y
 # CONFIG_SLUB_DEBUG is not set
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
-# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
-# CONFIG_HAVE_IOREMAP_PROT is not set
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
-# CONFIG_HAVE_ARCH_TRACEHOOK is not set
-# CONFIG_HAVE_DMA_ATTRS is not set
-# CONFIG_USE_GENERIC_SMP_HELPERS is not set
 CONFIG_HAVE_CLK=y
-# CONFIG_PROC_PAGE_MONITOR is not set
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
 # CONFIG_MODULE_FORCE_LOAD is not set
@@ -108,11 +101,9 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -129,6 +120,11 @@ CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="cfq"
 CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+CONFIG_FREEZER=y
 
 #
 # System Type
@@ -138,7 +134,6 @@ CONFIG_CLASSIC_RCU=y
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS7500 is not set
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_EBSA110 is not set
 # CONFIG_ARCH_EP93XX is not set
@@ -165,17 +160,19 @@ CONFIG_ARCH_PXA=y
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM7X00A is not set
-CONFIG_DMABOUNCE=y
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
 
 #
 # Intel PXA2xx/PXA3xx Implementations
 #
 # CONFIG_ARCH_GUMSTIX is not set
+# CONFIG_MACH_INTELMOTE2 is not set
 # CONFIG_ARCH_LUBBOCK is not set
 # CONFIG_MACH_LOGICPD_PXA270 is not set
 # CONFIG_MACH_MAINSTONE is not set
@@ -185,7 +182,9 @@ CONFIG_DMABOUNCE=y
 # CONFIG_ARCH_VIPER is not set
 # CONFIG_ARCH_PXA_ESERIES is not set
 # CONFIG_TRIZEPS_PXA is not set
-CONFIG_MACH_EM_X270=y
+# CONFIG_MACH_H5000 is not set
+# CONFIG_MACH_EM_X270 is not set
+# CONFIG_MACH_EXEDA is not set
 # CONFIG_MACH_COLIBRI is not set
 # CONFIG_MACH_ZYLONITE is not set
 # CONFIG_MACH_LITTLETON is not set
@@ -204,14 +203,6 @@ CONFIG_PXA_SSP=y
 # CONFIG_PXA_PWM is not set
 
 #
-# Boot options
-#
-
-#
-# Power management
-#
-
-#
 # Processor Type
 #
 CONFIG_CPU_32=y
@@ -232,6 +223,8 @@ CONFIG_ARM_THUMB=y
 # CONFIG_OUTER_CACHE is not set
 CONFIG_IWMMXT=y
 CONFIG_XSCALE_PMU=y
+CONFIG_DMABOUNCE=y
+CONFIG_COMMON_CLKDEV=y
 
 #
 # Bus support
@@ -242,6 +235,7 @@ CONFIG_PCI_HOST_ITE8152=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
 CONFIG_PCI_LEGACY=y
 # CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_STUB is not set
 CONFIG_PCCARD=m
 # CONFIG_PCMCIA_DEBUG is not set
 CONFIG_PCMCIA=m
@@ -287,14 +281,13 @@ CONFIG_FLATMEM_MANUAL=y
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
 CONFIG_ALIGNMENT_TRAP=y
 
 #
@@ -327,6 +320,8 @@ CONFIG_FPE_NWFPE=y
 # Userspace binary formats
 #
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
 # CONFIG_BINFMT_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 
@@ -345,6 +340,7 @@ CONFIG_NET=y
 #
 # Networking options
 #
+CONFIG_COMPAT_NET_DEV_OPS=y
 CONFIG_PACKET=y
 CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
@@ -389,6 +385,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -399,6 +396,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
 # CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
 
 #
 # Network testing
@@ -420,8 +418,6 @@ CONFIG_BT_HIDP=m
 #
 # Bluetooth device drivers
 #
-CONFIG_BT_HCIUSB=m
-CONFIG_BT_HCIUSB_SCO=y
 # CONFIG_BT_HCIBTUSB is not set
 # CONFIG_BT_HCIBTSDIO is not set
 # CONFIG_BT_HCIUART is not set
@@ -434,15 +430,15 @@ CONFIG_BT_HCIUSB_SCO=y
 # CONFIG_BT_HCIBTUART is not set
 # CONFIG_BT_HCIVHCI is not set
 # CONFIG_AF_RXRPC is not set
-
-#
-# Wireless
-#
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
 # CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
 CONFIG_WIRELESS_EXT=y
 CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=m
 # CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
+# CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
 
@@ -467,6 +463,7 @@ CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_REDBOOT_PARTS is not set
 CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AFS_PARTS is not set
@@ -521,9 +518,7 @@ CONFIG_MTD_CFI_UTIL=y
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
 CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0x0
-CONFIG_MTD_PHYSMAP_LEN=0x400000
-CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
 CONFIG_MTD_PXA2XX=y
 # CONFIG_MTD_ARM_INTEGRATOR is not set
 # CONFIG_MTD_IMPA7 is not set
@@ -535,6 +530,8 @@ CONFIG_MTD_PXA2XX=y
 # Self-contained MTD device drivers
 #
 # CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -563,6 +560,12 @@ CONFIG_MTD_NAND_PLATFORM=y
 # CONFIG_MTD_ONENAND is not set
 
 #
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+# CONFIG_MTD_QINFO_PROBE is not set
+
+#
 # UBI - Unsorted block images
 #
 # CONFIG_MTD_UBI is not set
@@ -642,6 +645,8 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_MEGARAID_LEGACY is not set
 # CONFIG_MEGARAID_SAS is not set
 # CONFIG_SCSI_HPTIOP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_FCOE is not set
 # CONFIG_SCSI_DMX3191D is not set
 # CONFIG_SCSI_FUTURE_DOMAIN is not set
 # CONFIG_SCSI_IPS is not set
@@ -756,26 +761,30 @@ CONFIG_MII=y
 CONFIG_DM9000=y
 CONFIG_DM9000_DEBUGLEVEL=1
 # CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set
+# CONFIG_ENC28J60 is not set
 # CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
 # CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 CONFIG_NET_PCI=y
 # CONFIG_PCNET32 is not set
 # CONFIG_AMD8111_ETH is not set
 # CONFIG_ADAPTEC_STARFIRE is not set
 # CONFIG_B44 is not set
 # CONFIG_FORCEDETH is not set
-# CONFIG_EEPRO100 is not set
 # CONFIG_E100 is not set
 # CONFIG_FEALNX is not set
 # CONFIG_NATSEMI is not set
 # CONFIG_NE2K_PCI is not set
 # CONFIG_8139CP is not set
-CONFIG_8139TOO=y
+CONFIG_8139TOO=m
 # CONFIG_8139TOO_PIO is not set
 # CONFIG_8139TOO_TUNE_TWISTER is not set
 # CONFIG_8139TOO_8129 is not set
@@ -783,10 +792,12 @@ CONFIG_8139TOO=y
 # CONFIG_R6040 is not set
 # CONFIG_SIS900 is not set
 # CONFIG_EPIC100 is not set
+# CONFIG_SMSC9420 is not set
 # CONFIG_SUNDANCE is not set
 # CONFIG_TLAN is not set
 # CONFIG_VIA_RHINE is not set
 # CONFIG_SC92031 is not set
+# CONFIG_ATL2 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 # CONFIG_TR is not set
@@ -797,8 +808,6 @@ CONFIG_8139TOO=y
 # CONFIG_WLAN_PRE80211 is not set
 CONFIG_WLAN_80211=y
 # CONFIG_PCMCIA_RAYCS is not set
-# CONFIG_IPW2100 is not set
-# CONFIG_IPW2200 is not set
 CONFIG_LIBERTAS=m
 # CONFIG_LIBERTAS_USB is not set
 # CONFIG_LIBERTAS_CS is not set
@@ -811,10 +820,16 @@ CONFIG_LIBERTAS_SDIO=m
 # CONFIG_PRISM54 is not set
 # CONFIG_USB_ZD1201 is not set
 # CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
 # CONFIG_IWLWIFI_LEDS is not set
 # CONFIG_HOSTAP is not set
 
 #
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
 # USB Network Adapters
 #
 # CONFIG_USB_CATC is not set
@@ -879,22 +894,22 @@ CONFIG_KEYBOARD_PXA27x=m
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
 CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
 # CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
 # CONFIG_TOUCHSCREEN_INEXIO is not set
 # CONFIG_TOUCHSCREEN_MK712 is not set
 # CONFIG_TOUCHSCREEN_PENMOUNT is not set
 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-CONFIG_TOUCHSCREEN_WM97XX=m
-# CONFIG_TOUCHSCREEN_WM9705 is not set
-CONFIG_TOUCHSCREEN_WM9712=y
-# CONFIG_TOUCHSCREEN_WM9713 is not set
-# CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set
+CONFIG_TOUCHSCREEN_UCB1400=m
+# CONFIG_TOUCHSCREEN_WM97XX is not set
 # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
 # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
 # CONFIG_INPUT_MISC is not set
 
 #
@@ -933,6 +948,7 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_JSM is not set
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_IPMI_HANDLER is not set
@@ -1009,26 +1025,45 @@ CONFIG_I2C_PXA=y
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
-# CONFIG_EEPROM_AT24 is not set
-# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_AT24 is not set
+# CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_TPS65010 is not set
 # CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
-# CONFIG_SPI is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_PXA2XX=m
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
 CONFIG_ARCH_REQUIRE_GPIOLIB=y
 CONFIG_GPIOLIB=y
 # CONFIG_DEBUG_GPIO is not set
 # CONFIG_GPIO_SYSFS is not set
 
 #
+# Memory mapped GPIO expanders:
+#
+
+#
 # I2C GPIO expanders:
 #
 # CONFIG_GPIO_MAX732X is not set
@@ -1043,17 +1078,19 @@ CONFIG_GPIOLIB=y
 #
 # SPI GPIO expanders:
 #
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
 # CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
 
 #
 # Sonics Silicon Backplane
 #
-CONFIG_SSB_POSSIBLE=y
 # CONFIG_SSB is not set
 
 #
@@ -1064,11 +1101,17 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_ASIC3 is not set
 # CONFIG_HTC_EGPIO is not set
 # CONFIG_HTC_PASIC3 is not set
-# CONFIG_UCB1400_CORE is not set
+CONFIG_UCB1400_CORE=m
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
 # CONFIG_MFD_TMIO is not set
 # CONFIG_MFD_T7L66XB is not set
 # CONFIG_MFD_TC6387XB is not set
 # CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
 
 #
 # Multimedia devices
@@ -1077,13 +1120,117 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Multimedia core support
 #
-# CONFIG_VIDEO_DEV is not set
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+# CONFIG_VIDEO_ALLOW_V4L1 is not set
+CONFIG_VIDEO_V4L1_COMPAT=y
 # CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
+CONFIG_VIDEO_MEDIA=m
 
 #
 # Multimedia drivers
 #
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=m
+CONFIG_MEDIA_TUNER_CUSTOMIZE=y
+# CONFIG_MEDIA_TUNER_SIMPLE is not set
+# CONFIG_MEDIA_TUNER_TDA8290 is not set
+# CONFIG_MEDIA_TUNER_TDA827X is not set
+# CONFIG_MEDIA_TUNER_TDA18271 is not set
+# CONFIG_MEDIA_TUNER_TDA9887 is not set
+# CONFIG_MEDIA_TUNER_TEA5761 is not set
+# CONFIG_MEDIA_TUNER_TEA5767 is not set
+# CONFIG_MEDIA_TUNER_MT20XX is not set
+# CONFIG_MEDIA_TUNER_MT2060 is not set
+# CONFIG_MEDIA_TUNER_MT2266 is not set
+# CONFIG_MEDIA_TUNER_MT2131 is not set
+# CONFIG_MEDIA_TUNER_QT1010 is not set
+# CONFIG_MEDIA_TUNER_XC2028 is not set
+# CONFIG_MEDIA_TUNER_XC5000 is not set
+# CONFIG_MEDIA_TUNER_MXL5005S is not set
+# CONFIG_MEDIA_TUNER_MXL5007T is not set
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEOBUF_GEN=m
+CONFIG_VIDEOBUF_DMA_SG=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+
+#
+# Encoders/decoders and other helper chips
+#
+
+#
+# Audio decoders
+#
+# CONFIG_VIDEO_TVAUDIO is not set
+# CONFIG_VIDEO_TDA7432 is not set
+# CONFIG_VIDEO_TDA9840 is not set
+# CONFIG_VIDEO_TDA9875 is not set
+# CONFIG_VIDEO_TEA6415C is not set
+# CONFIG_VIDEO_TEA6420 is not set
+# CONFIG_VIDEO_MSP3400 is not set
+# CONFIG_VIDEO_CS5345 is not set
+# CONFIG_VIDEO_CS53L32A is not set
+# CONFIG_VIDEO_M52790 is not set
+# CONFIG_VIDEO_TLV320AIC23B is not set
+# CONFIG_VIDEO_WM8775 is not set
+# CONFIG_VIDEO_WM8739 is not set
+# CONFIG_VIDEO_VP27SMPX is not set
+
+#
+# Video decoders
+#
+# CONFIG_VIDEO_OV7670 is not set
+# CONFIG_VIDEO_TCM825X is not set
+# CONFIG_VIDEO_SAA711X is not set
+# CONFIG_VIDEO_SAA717X is not set
+# CONFIG_VIDEO_TVP514X is not set
+# CONFIG_VIDEO_TVP5150 is not set
+
+#
+# Video and audio decoders
+#
+# CONFIG_VIDEO_CX25840 is not set
+
+#
+# MPEG video encoders
+#
+# CONFIG_VIDEO_CX2341X is not set
+
+#
+# Video encoders
+#
+# CONFIG_VIDEO_SAA7127 is not set
+
+#
+# Video improvement chips
+#
+# CONFIG_VIDEO_UPD64031A is not set
+# CONFIG_VIDEO_UPD64083 is not set
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_BT848 is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_VIDEO_SAA7134 is not set
+# CONFIG_VIDEO_HEXIUM_ORION is not set
+# CONFIG_VIDEO_HEXIUM_GEMINI is not set
+# CONFIG_VIDEO_CX88 is not set
+# CONFIG_VIDEO_IVTV is not set
+# CONFIG_VIDEO_CAFE_CCIC is not set
+CONFIG_SOC_CAMERA=m
+# CONFIG_SOC_CAMERA_MT9M001 is not set
+CONFIG_SOC_CAMERA_MT9M111=m
+# CONFIG_SOC_CAMERA_MT9T031 is not set
+# CONFIG_SOC_CAMERA_MT9V022 is not set
+# CONFIG_SOC_CAMERA_TW9910 is not set
+# CONFIG_SOC_CAMERA_PLATFORM is not set
+# CONFIG_SOC_CAMERA_OV772X is not set
+CONFIG_VIDEO_PXA27x=m
+# CONFIG_VIDEO_SH_MOBILE_CEU is not set
+# CONFIG_V4L_USB_DRIVERS is not set
+# CONFIG_RADIO_ADAPTERS is not set
 # CONFIG_DAB is not set
 
 #
@@ -1095,6 +1242,7 @@ CONFIG_SSB_POSSIBLE=y
 CONFIG_FB=y
 # CONFIG_FIRMWARE_EDID is not set
 # CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
@@ -1128,6 +1276,7 @@ CONFIG_FB_CFB_IMAGEBLIT=y
 # CONFIG_FB_S3 is not set
 # CONFIG_FB_SAVAGE is not set
 # CONFIG_FB_SIS is not set
+# CONFIG_FB_VIA is not set
 # CONFIG_FB_NEOMAGIC is not set
 # CONFIG_FB_KYRO is not set
 # CONFIG_FB_3DFX is not set
@@ -1138,13 +1287,17 @@ CONFIG_FB_CFB_IMAGEBLIT=y
 # CONFIG_FB_PM3 is not set
 # CONFIG_FB_CARMINE is not set
 CONFIG_FB_PXA=y
+# CONFIG_FB_PXA_OVERLAY is not set
 # CONFIG_FB_PXA_SMARTPANEL is not set
 CONFIG_FB_PXA_PARAMETERS=y
 CONFIG_FB_MBX=m
 # CONFIG_FB_W100 is not set
 # CONFIG_FB_VIRTUAL is not set
 # CONFIG_FB_METRONOME is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_FB_MB862XX is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
 
 #
 # Display device support
@@ -1167,6 +1320,7 @@ CONFIG_LOGO_LINUX_MONO=y
 CONFIG_LOGO_LINUX_VGA16=y
 CONFIG_LOGO_LINUX_CLUT224=y
 CONFIG_SOUND=m
+CONFIG_SOUND_OSS_CORE=y
 CONFIG_SND=m
 CONFIG_SND_TIMER=m
 CONFIG_SND_PCM=m
@@ -1182,81 +1336,16 @@ CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_DEBUG is not set
 CONFIG_SND_VMASTER=y
 CONFIG_SND_AC97_CODEC=m
-CONFIG_SND_DRIVERS=y
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
-# CONFIG_SND_AC97_POWER_SAVE is not set
-CONFIG_SND_PCI=y
-# CONFIG_SND_AD1889 is not set
-# CONFIG_SND_ALS300 is not set
-# CONFIG_SND_ALI5451 is not set
-# CONFIG_SND_ATIIXP is not set
-# CONFIG_SND_ATIIXP_MODEM is not set
-# CONFIG_SND_AU8810 is not set
-# CONFIG_SND_AU8820 is not set
-# CONFIG_SND_AU8830 is not set
-# CONFIG_SND_AW2 is not set
-# CONFIG_SND_AZT3328 is not set
-# CONFIG_SND_BT87X is not set
-# CONFIG_SND_CA0106 is not set
-# CONFIG_SND_CMIPCI is not set
-# CONFIG_SND_OXYGEN is not set
-# CONFIG_SND_CS4281 is not set
-# CONFIG_SND_CS46XX is not set
-# CONFIG_SND_DARLA20 is not set
-# CONFIG_SND_GINA20 is not set
-# CONFIG_SND_LAYLA20 is not set
-# CONFIG_SND_DARLA24 is not set
-# CONFIG_SND_GINA24 is not set
-# CONFIG_SND_LAYLA24 is not set
-# CONFIG_SND_MONA is not set
-# CONFIG_SND_MIA is not set
-# CONFIG_SND_ECHO3G is not set
-# CONFIG_SND_INDIGO is not set
-# CONFIG_SND_INDIGOIO is not set
-# CONFIG_SND_INDIGODJ is not set
-# CONFIG_SND_EMU10K1 is not set
-# CONFIG_SND_EMU10K1X is not set
-# CONFIG_SND_ENS1370 is not set
-# CONFIG_SND_ENS1371 is not set
-# CONFIG_SND_ES1938 is not set
-# CONFIG_SND_ES1968 is not set
-# CONFIG_SND_FM801 is not set
-# CONFIG_SND_HDA_INTEL is not set
-# CONFIG_SND_HDSP is not set
-# CONFIG_SND_HDSPM is not set
-# CONFIG_SND_HIFIER is not set
-# CONFIG_SND_ICE1712 is not set
-# CONFIG_SND_ICE1724 is not set
-# CONFIG_SND_INTEL8X0 is not set
-# CONFIG_SND_INTEL8X0M is not set
-# CONFIG_SND_KORG1212 is not set
-# CONFIG_SND_MAESTRO3 is not set
-# CONFIG_SND_MIXART is not set
-# CONFIG_SND_NM256 is not set
-# CONFIG_SND_PCXHR is not set
-# CONFIG_SND_RIPTIDE is not set
-# CONFIG_SND_RME32 is not set
-# CONFIG_SND_RME96 is not set
-# CONFIG_SND_RME9652 is not set
-# CONFIG_SND_SONICVIBES is not set
-# CONFIG_SND_TRIDENT is not set
-# CONFIG_SND_VIA82XX is not set
-# CONFIG_SND_VIA82XX_MODEM is not set
-# CONFIG_SND_VIRTUOSO is not set
-# CONFIG_SND_VX222 is not set
-# CONFIG_SND_YMFPCI is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_PCI is not set
 CONFIG_SND_ARM=y
 CONFIG_SND_PXA2XX_PCM=m
+CONFIG_SND_PXA2XX_LIB=m
+CONFIG_SND_PXA2XX_LIB_AC97=y
 CONFIG_SND_PXA2XX_AC97=m
-CONFIG_SND_USB=y
-# CONFIG_SND_USB_AUDIO is not set
-# CONFIG_SND_USB_CAIAQ is not set
-CONFIG_SND_PCMCIA=y
-# CONFIG_SND_VXPOCKET is not set
-# CONFIG_SND_PDAUDIOCF is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+# CONFIG_SND_PCMCIA is not set
 # CONFIG_SND_SOC is not set
 # CONFIG_SOUND_PRIME is not set
 CONFIG_AC97_BUS=m
@@ -1269,9 +1358,37 @@ CONFIG_HID_DEBUG=y
 # USB Input Devices
 #
 CONFIG_USB_HID=y
-# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-# CONFIG_HID_FF is not set
+# CONFIG_HID_PID is not set
 # CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_LOGITECH=y
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+# CONFIG_HID_NTRIG is not set
+CONFIG_HID_PANTHERLORD=y
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+# CONFIG_GREENASIA_FF is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
@@ -1291,12 +1408,15 @@ CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_OTG_WHITELIST is not set
 # CONFIG_USB_OTG_BLACKLIST_HUB is not set
 CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
 
 #
 # USB Host Controller Drivers
 #
 # CONFIG_USB_C67X00_HCD is not set
 # CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
 # CONFIG_USB_ISP1760_HCD is not set
 CONFIG_USB_OHCI_HCD=y
@@ -1306,6 +1426,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_UHCI_HCD is not set
 # CONFIG_USB_SL811_HCD is not set
 # CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_WHCI_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
 # CONFIG_USB_MUSB_HDRC is not set
 
 #
@@ -1314,20 +1436,20 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_ACM is not set
 # CONFIG_USB_PRINTER is not set
 # CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
 
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
 #
 
 #
-# may also be needed; see USB_STORAGE Help for more information
+# see USB_STORAGE Help for more information
 #
 CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
 # CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_DPCM is not set
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
 # CONFIG_USB_STORAGE_SDDR55 is not set
@@ -1355,6 +1477,7 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_EMI62 is not set
 # CONFIG_USB_EMI26 is not set
 # CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
@@ -1371,13 +1494,20 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
 # CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
 # CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_UWB is not set
 CONFIG_MMC=m
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
 
 #
-# MMC/SD Card Drivers
+# MMC/SD/SDIO Card Drivers
 #
 CONFIG_MMC_BLOCK=m
 CONFIG_MMC_BLOCK_BOUNCE=y
@@ -1385,11 +1515,12 @@ CONFIG_MMC_BLOCK_BOUNCE=y
 # CONFIG_MMC_TEST is not set
 
 #
-# MMC/SD Host Controller Drivers
+# MMC/SD/SDIO Host Controller Drivers
 #
 CONFIG_MMC_PXA=m
 # CONFIG_MMC_SDHCI is not set
 # CONFIG_MMC_TIFM_SD is not set
+# CONFIG_MMC_SPI is not set
 # CONFIG_MMC_SDRICOH_CS is not set
 # CONFIG_MEMSTICK is not set
 # CONFIG_ACCESSIBILITY is not set
@@ -1400,8 +1531,7 @@ CONFIG_LEDS_CLASS=y
 # LED drivers
 #
 # CONFIG_LEDS_PCA9532 is not set
-# CONFIG_LEDS_GPIO is not set
-CONFIG_LEDS_CM_X270=y
+CONFIG_LEDS_GPIO=m
 # CONFIG_LEDS_PCA955X is not set
 
 #
@@ -1410,6 +1540,7 @@ CONFIG_LEDS_CM_X270=y
 CONFIG_LEDS_TRIGGERS=y
 # CONFIG_LEDS_TRIGGER_TIMER is not set
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
 # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
@@ -1441,37 +1572,43 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_M41T80 is not set
 # CONFIG_RTC_DRV_S35390A is not set
 # CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
 
 #
 # SPI RTC drivers
 #
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
 
 #
 # Platform RTC drivers
 #
 # CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
 # CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
 # CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
 CONFIG_RTC_DRV_V3020=y
 
 #
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_SA1100=y
+# CONFIG_RTC_DRV_PXA is not set
 # CONFIG_DMADEVICES is not set
-
-#
-# Voltage and Current regulators
-#
 # CONFIG_REGULATOR is not set
-# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_BQ24022 is not set
 # CONFIG_UIO is not set
+# CONFIG_STAGING is not set
 
 #
 # File systems
@@ -1483,14 +1620,16 @@ CONFIG_EXT3_FS=y
 CONFIG_EXT3_FS_XATTR=y
 # CONFIG_EXT3_FS_POSIX_ACL is not set
 # CONFIG_EXT3_FS_SECURITY is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 CONFIG_JBD=y
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
 # CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -1520,15 +1659,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -1548,6 +1685,7 @@ CONFIG_JFFS2_ZLIB=y
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_OMFS_FS is not set
@@ -1567,6 +1705,7 @@ CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -1678,19 +1817,29 @@ CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
 CONFIG_FRAME_POINTER=y
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_LATENCYTOP is not set
 CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_HAVE_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-# CONFIG_FTRACE is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
 # CONFIG_IRQSOFF_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
 # CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
@@ -1705,13 +1854,16 @@ CONFIG_DEBUG_LL=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
 
 #
 # Crypto core or helper
 #
+# CONFIG_CRYPTO_FIPS is not set
 # CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
 # CONFIG_CRYPTO_GF128MUL is not set
 # CONFIG_CRYPTO_NULL is not set
 # CONFIG_CRYPTO_CRYPTD is not set
@@ -1783,14 +1935,18 @@ CONFIG_CRYPTO=y
 #
 # CONFIG_CRYPTO_DEFLATE is not set
 # CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
 # CONFIG_CRYPTO_HW is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
-# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
 # CONFIG_CRC_T10DIF is not set
diff --git a/arch/arm/configs/colibri_defconfig b/arch/arm/configs/colibri_pxa270_defconfig
index 744086fff414..4cf3bde1c522 100644
--- a/arch/arm/configs/colibri_defconfig
+++ b/arch/arm/configs/colibri_pxa270_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.24-rc3
-# Mon Dec  3 13:36:09 2007
+# Linux kernel version: 2.6.29-rc8
+# Fri Mar 13 16:18:17 2009
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -12,6 +12,7 @@ CONFIG_MMU=y
 # CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
@@ -21,8 +22,8 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ZONE_DMA=y
 CONFIG_ARCH_MTD_XIP=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
@@ -42,22 +43,30 @@ CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BSD_PROCESS_ACCT_V3=y
 # CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
 # CONFIG_CGROUPS is not set
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_FAIR_USER_SCHED=y
-# CONFIG_FAIR_CGROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
@@ -70,29 +79,38 @@ CONFIG_BUG=y
 CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
+CONFIG_AIO=y
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_KMOD=y
 CONFIG_BLOCK=y
 CONFIG_LBD=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
-CONFIG_LSF=y
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -106,6 +124,7 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_FREEZER=y
 
 #
 # System Type
@@ -115,9 +134,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS7500 is not set
 # CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
 # CONFIG_ARCH_EP93XX is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
@@ -131,41 +148,58 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_IXP2000 is not set
 # CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
 # CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
 # CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
 # CONFIG_ARCH_PNX4008 is not set
 CONFIG_ARCH_PXA=y
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
 
 #
 # Intel PXA2xx/PXA3xx Implementations
 #
+# CONFIG_ARCH_GUMSTIX is not set
+# CONFIG_MACH_INTELMOTE2 is not set
 # CONFIG_ARCH_LUBBOCK is not set
 # CONFIG_MACH_LOGICPD_PXA270 is not set
 # CONFIG_MACH_MAINSTONE is not set
+# CONFIG_MACH_MP900C is not set
 # CONFIG_ARCH_PXA_IDP is not set
 # CONFIG_PXA_SHARPSL is not set
-# CONFIG_MACH_TRIZEPS4 is not set
+# CONFIG_ARCH_VIPER is not set
+# CONFIG_ARCH_PXA_ESERIES is not set
+# CONFIG_TRIZEPS_PXA is not set
+# CONFIG_MACH_H5000 is not set
 # CONFIG_MACH_EM_X270 is not set
 CONFIG_MACH_COLIBRI=y
+# CONFIG_MACH_COLIBRI300 is not set
 # CONFIG_MACH_ZYLONITE is not set
+# CONFIG_MACH_LITTLETON is not set
+# CONFIG_MACH_RAUMFELD_PROTO is not set
+# CONFIG_MACH_TAVOREVB is not set
+# CONFIG_MACH_SAAR is not set
 # CONFIG_MACH_ARMCORE is not set
+# CONFIG_MACH_CM_X300 is not set
+# CONFIG_MACH_MAGICIAN is not set
+# CONFIG_MACH_MIOA701 is not set
+# CONFIG_MACH_PCM027 is not set
+# CONFIG_ARCH_PXA_PALM is not set
+# CONFIG_PXA_EZX is not set
 CONFIG_PXA27x=y
-
-#
-# Boot options
-#
-
-#
-# Power management
-#
+# CONFIG_PXA_PWM is not set
 
 #
 # Processor Type
@@ -174,6 +208,7 @@ CONFIG_CPU_32=y
 CONFIG_CPU_XSCALE=y
 CONFIG_CPU_32v5=y
 CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_NOIFAR=y
 CONFIG_CPU_CACHE_VIVT=y
 CONFIG_CPU_TLB_V4WBI=y
 CONFIG_CPU_CP15=y
@@ -187,6 +222,7 @@ CONFIG_ARM_THUMB=y
 # CONFIG_OUTER_CACHE is not set
 CONFIG_IWMMXT=y
 CONFIG_XSCALE_PMU=y
+CONFIG_COMMON_CLKDEV=y
 
 #
 # Bus support
@@ -198,28 +234,33 @@ CONFIG_XSCALE_PMU=y
 #
 # Kernel Features
 #
-# CONFIG_TICK_ONESHOT is not set
+CONFIG_TICK_ONESHOT=y
 # CONFIG_NO_HZ is not set
 # CONFIG_HIGH_RES_TIMERS is not set
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
 CONFIG_PREEMPT=y
 CONFIG_HZ=100
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y
-# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_RESOURCES_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_BOUNCE=y
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
 CONFIG_ALIGNMENT_TRAP=y
 
 #
@@ -232,6 +273,12 @@ CONFIG_CMDLINE=""
 # CONFIG_KEXEC is not set
 
 #
+# CPU Power Management
+#
+# CONFIG_CPU_FREQ is not set
+# CONFIG_CPU_IDLE is not set
+
+#
 # Floating point emulation
 #
 
@@ -246,6 +293,8 @@ CONFIG_FPE_NWFPE=y
 # Userspace binary formats
 #
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
 # CONFIG_BINFMT_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 
@@ -253,21 +302,18 @@ CONFIG_BINFMT_ELF=y
 # Power management options
 #
 CONFIG_PM=y
-# CONFIG_PM_LEGACY is not set
 # CONFIG_PM_DEBUG is not set
 CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND_UP_POSSIBLE=y
 CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
 # CONFIG_APM_EMULATION is not set
-
-#
-# Networking
-#
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_NET=y
 
 #
 # Networking options
 #
+CONFIG_COMPAT_NET_DEV_OPS=y
 CONFIG_PACKET=y
 CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
@@ -275,6 +321,7 @@ CONFIG_XFRM=y
 CONFIG_XFRM_USER=m
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 CONFIG_NET_KEY=y
 # CONFIG_NET_KEY_MIGRATE is not set
 CONFIG_INET=y
@@ -304,26 +351,26 @@ CONFIG_INET_TCP_DIAG=y
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
-# CONFIG_IP_VS is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETLABEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 CONFIG_NETFILTER=y
 # CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
 
 #
 # Core Netfilter Configuration
 #
-# CONFIG_NETFILTER_NETLINK is not set
-# CONFIG_NF_CONNTRACK_ENABLED is not set
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
 # CONFIG_NF_CONNTRACK is not set
 # CONFIG_NETFILTER_XTABLES is not set
+# CONFIG_IP_VS is not set
 
 #
 # IP: Netfilter Configuration
 #
+# CONFIG_NF_DEFRAG_IPV4 is not set
 CONFIG_IP_NF_QUEUE=m
 # CONFIG_IP_NF_IPTABLES is not set
 # CONFIG_IP_NF_ARPTABLES is not set
@@ -332,7 +379,9 @@ CONFIG_IP_NF_QUEUE=m
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 CONFIG_VLAN_8021Q=m
+# CONFIG_VLAN_8021Q_GVRP is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
 # CONFIG_IPX is not set
@@ -342,12 +391,14 @@ CONFIG_VLAN_8021Q=m
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
 # CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 CONFIG_IRDA=m
 
 #
@@ -382,15 +433,6 @@ CONFIG_IRTTY_SIR=m
 # CONFIG_KS959_DONGLE is not set
 
 #
-# Old SIR device drivers
-#
-# CONFIG_IRPORT_SIR is not set
-
-#
-# Old Serial dongle support
-#
-
-#
 # FIR device drivers
 #
 # CONFIG_USB_IRDA is not set
@@ -410,7 +452,6 @@ CONFIG_BT_HIDP=m
 #
 # Bluetooth device drivers
 #
-# CONFIG_BT_HCIUSB is not set
 # CONFIG_BT_HCIBTUSB is not set
 # CONFIG_BT_HCIBTSDIO is not set
 # CONFIG_BT_HCIUART is not set
@@ -419,21 +460,20 @@ CONFIG_BT_HIDP=m
 # CONFIG_BT_HCIBFUSB is not set
 # CONFIG_BT_HCIVHCI is not set
 # CONFIG_AF_RXRPC is not set
-
-#
-# Wireless
-#
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
 CONFIG_CFG80211=y
+# CONFIG_CFG80211_REG_DEBUG is not set
 CONFIG_NL80211=y
+CONFIG_WIRELESS_OLD_REGULATORY=y
 CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=y
+CONFIG_LIB80211_CRYPT_WEP=y
+CONFIG_LIB80211_CRYPT_CCMP=y
+CONFIG_LIB80211_CRYPT_TKIP=y
 # CONFIG_MAC80211 is not set
-CONFIG_IEEE80211=y
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=y
-CONFIG_IEEE80211_CRYPT_CCMP=m
-CONFIG_IEEE80211_CRYPT_TKIP=m
-CONFIG_IEEE80211_SOFTMAC=m
-# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
+# CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
 
@@ -448,6 +488,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_DEBUG_DRIVER is not set
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
@@ -457,9 +499,11 @@ CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 CONFIG_MTD_CONCAT=y
 CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_REDBOOT_PARTS is not set
 # CONFIG_MTD_CMDLINE_PARTS is not set
 # CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -510,9 +554,7 @@ CONFIG_MTD_CFI_UTIL=y
 #
 CONFIG_MTD_COMPLEX_MAPPINGS=y
 CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0x0
-CONFIG_MTD_PHYSMAP_LEN=0x0
-CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
 CONFIG_MTD_PXA2XX=y
 # CONFIG_MTD_ARM_INTEGRATOR is not set
 # CONFIG_MTD_IMPA7 is not set
@@ -538,6 +580,7 @@ CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_ECC_SMC is not set
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
 # CONFIG_MTD_NAND_H1900 is not set
+# CONFIG_MTD_NAND_GPIO is not set
 CONFIG_MTD_NAND_IDS=y
 CONFIG_MTD_NAND_DISKONCHIP=y
 CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
@@ -556,6 +599,11 @@ CONFIG_MTD_ONENAND=y
 # CONFIG_MTD_ONENAND_SIM is not set
 
 #
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
 # UBI - Unsorted block images
 #
 # CONFIG_MTD_UBI is not set
@@ -569,36 +617,41 @@ CONFIG_BLK_DEV_NBD=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=8
 CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
 CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_LEGACY is not set
 # CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
 CONFIG_IDE=y
-CONFIG_IDE_MAX_HWIFS=4
-CONFIG_BLK_DEV_IDE=y
 
 #
-# Please see Documentation/ide.txt for help/info on IDE drives
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
 # CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
-CONFIG_IDEDISK_MULTI_MODE=y
+CONFIG_IDE_GD=y
+CONFIG_IDE_GD_ATA=y
+# CONFIG_IDE_GD_ATAPI is not set
 # CONFIG_BLK_DEV_IDECD is not set
 # CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
 # CONFIG_IDE_TASK_IOCTL is not set
 CONFIG_IDE_PROC_FS=y
 
 #
 # IDE chipset support/bugfixes
 #
-CONFIG_IDE_GENERIC=y
 # CONFIG_BLK_DEV_PLATFORM is not set
-# CONFIG_IDE_ARM is not set
 # CONFIG_BLK_DEV_IDEDMA is not set
-CONFIG_IDE_ARCH_OBSOLETE_INIT=y
-# CONFIG_BLK_DEV_HD is not set
 
 #
 # SCSI device support
@@ -610,7 +663,6 @@ CONFIG_IDE_ARCH_OBSOLETE_INIT=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -631,6 +683,10 @@ CONFIG_PHYLIB=y
 # CONFIG_SMSC_PHY is not set
 # CONFIG_BROADCOM_PHY is not set
 # CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
 # CONFIG_FIXED_PHY is not set
 # CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
@@ -638,11 +694,17 @@ CONFIG_MII=y
 # CONFIG_AX88796 is not set
 # CONFIG_SMC91X is not set
 CONFIG_DM9000=y
+CONFIG_DM9000_DEBUGLEVEL=4
+# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set
 # CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
 # CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_B44 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
@@ -654,10 +716,15 @@ CONFIG_DM9000=y
 CONFIG_WLAN_80211=y
 # CONFIG_LIBERTAS is not set
 # CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_IWLWIFI_LEDS is not set
 CONFIG_HOSTAP=y
 CONFIG_HOSTAP_FIRMWARE=y
 CONFIG_HOSTAP_FIRMWARE_NVRAM=y
-# CONFIG_ZD1211RW is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
 
 #
 # USB Network Adapters
@@ -670,7 +737,6 @@ CONFIG_HOSTAP_FIRMWARE_NVRAM=y
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
@@ -710,6 +776,7 @@ CONFIG_INPUT_MOUSE=y
 # CONFIG_MOUSE_PS2 is not set
 CONFIG_MOUSE_SERIAL=m
 # CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
 # CONFIG_MOUSE_VSXXXAA is not set
 # CONFIG_MOUSE_GPIO is not set
 # CONFIG_INPUT_JOYSTICK is not set
@@ -718,20 +785,25 @@ CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
 # CONFIG_TOUCHSCREEN_MK712 is not set
 # CONFIG_TOUCHSCREEN_PENMOUNT is not set
 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-CONFIG_TOUCHSCREEN_UCB1400=y
 # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
 CONFIG_INPUT_MISC=y
 # CONFIG_INPUT_ATI_REMOTE is not set
 # CONFIG_INPUT_ATI_REMOTE2 is not set
 # CONFIG_INPUT_KEYSPAN_REMOTE is not set
 # CONFIG_INPUT_POWERMATE is not set
 # CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
 CONFIG_INPUT_UINPUT=m
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
 
 #
 # Hardware I/O ports
@@ -746,9 +818,11 @@ CONFIG_SERIO_LIBPS2=y
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 # CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -764,45 +838,50 @@ CONFIG_SERIAL_PXA_CONSOLE=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_IPMI_HANDLER is not set
 CONFIG_HW_RANDOM=y
-# CONFIG_NVRAM is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 CONFIG_I2C=y
 CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
 
 #
-# I2C Algorithms
+# I2C Hardware Bus support
 #
-# CONFIG_I2C_ALGOBIT is not set
-# CONFIG_I2C_ALGOPCF is not set
-# CONFIG_I2C_ALGOPCA is not set
 
 #
-# I2C Hardware Bus support
+# I2C system bus drivers (mostly embedded / system-on-chip)
 #
 # CONFIG_I2C_GPIO is not set
-# CONFIG_I2C_PXA is not set
 # CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PXA is not set
 # CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_STUB is not set
 # CONFIG_I2C_TINY_USB is not set
 
 #
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
 # Miscellaneous I2C Chip support
 #
-# CONFIG_SENSORS_DS1337 is not set
-# CONFIG_SENSORS_DS1374 is not set
 # CONFIG_DS1682 is not set
-# CONFIG_EEPROM_LEGACY is not set
 # CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_MAX6875 is not set
@@ -811,16 +890,35 @@ CONFIG_I2C_CHARDEV=y
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
 
 #
-# SPI support
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
 #
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
 # CONFIG_SENSORS_AD7418 is not set
 # CONFIG_SENSORS_ADM1021 is not set
 # CONFIG_SENSORS_ADM1025 is not set
@@ -828,7 +926,10 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_ADM1029 is not set
 # CONFIG_SENSORS_ADM1031 is not set
 # CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
 # CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
 # CONFIG_SENSORS_ATXP1 is not set
 # CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_F71805F is not set
@@ -848,6 +949,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_LM90 is not set
 # CONFIG_SENSORS_LM92 is not set
 # CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4245 is not set
 # CONFIG_SENSORS_MAX1619 is not set
 # CONFIG_SENSORS_MAX6650 is not set
 # CONFIG_SENSORS_PC87360 is not set
@@ -856,6 +958,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_SMSC47M192 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
 # CONFIG_SENSORS_THMC50 is not set
 # CONFIG_SENSORS_VT1211 is not set
 # CONFIG_SENSORS_W83781D is not set
@@ -863,9 +966,12 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_W83792D is not set
 # CONFIG_SENSORS_W83793 is not set
 # CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 CONFIG_WATCHDOG=y
 # CONFIG_WATCHDOG_NOWAYOUT is not set
 
@@ -879,23 +985,46 @@ CONFIG_WATCHDOG=y
 # USB-based Watchdog Cards
 #
 # CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
 
 #
 # Sonics Silicon Backplane
 #
-CONFIG_SSB_POSSIBLE=y
 # CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
 CONFIG_DAB=y
 # CONFIG_USB_DABUSB is not set
 
@@ -907,6 +1036,7 @@ CONFIG_DAB=y
 CONFIG_FB=y
 CONFIG_FIRMWARE_EDID=y
 # CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
@@ -914,8 +1044,8 @@ CONFIG_FB_CFB_IMAGEBLIT=y
 # CONFIG_FB_SYS_FILLRECT is not set
 # CONFIG_FB_SYS_COPYAREA is not set
 # CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
 # CONFIG_FB_SYS_FOPS is not set
-CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -928,13 +1058,20 @@ CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_UVESA is not set
 # CONFIG_FB_S1D13XXX is not set
 CONFIG_FB_PXA=y
+# CONFIG_FB_PXA_OVERLAY is not set
+# CONFIG_FB_PXA_SMARTPANEL is not set
 # CONFIG_FB_PXA_PARAMETERS is not set
 # CONFIG_FB_MBX is not set
+# CONFIG_FB_W100 is not set
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_PLATFORM is not set
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_CORGI is not set
+CONFIG_BACKLIGHT_GENERIC=y
 
 #
 # Display device support
@@ -964,12 +1101,7 @@ CONFIG_LOGO=y
 CONFIG_LOGO_LINUX_MONO=y
 CONFIG_LOGO_LINUX_VGA16=y
 CONFIG_LOGO_LINUX_CLUT224=y
-
-#
-# Sound
-#
 # CONFIG_SOUND is not set
-CONFIG_AC97_BUS=y
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
 # CONFIG_HID_DEBUG is not set
@@ -979,18 +1111,26 @@ CONFIG_HID=y
 # USB Input Devices
 #
 # CONFIG_USB_HID is not set
+# CONFIG_HID_PID is not set
 
 #
 # USB HID Boot Protocol drivers
 #
 # CONFIG_USB_KBD is not set
 # CONFIG_USB_MOUSE is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+# CONFIG_HID_APPLE is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 # CONFIG_USB_ARCH_HAS_EHCI is not set
 CONFIG_USB=y
 # CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
 
 #
 # Miscellaneous USB options
@@ -999,29 +1139,40 @@ CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_DEVICE_CLASS is not set
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_PERSIST is not set
 # CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
 
 #
 # USB Host Controller Drivers
 #
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
 # CONFIG_USB_OHCI_HCD is not set
 # CONFIG_USB_SL811_HCD is not set
 # CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
 
 #
 # USB Device Class drivers
 #
 # CONFIG_USB_ACM is not set
 # CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
 
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
 #
 
 #
-# may also be needed; see USB_STORAGE Help for more information
+# see USB_STORAGE Help for more information
 #
 # CONFIG_USB_LIBUSUAL is not set
 
@@ -1029,19 +1180,14 @@ CONFIG_USB_DEVICEFS=y
 # USB Imaging devices
 #
 # CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MON is not set
 
 #
 # USB port drivers
 #
-
-#
-# USB Serial Converter support
-#
 CONFIG_USB_SERIAL=m
+# CONFIG_USB_EZUSB is not set
 # CONFIG_USB_SERIAL_GENERIC is not set
 # CONFIG_USB_SERIAL_AIRCABLE is not set
-# CONFIG_USB_SERIAL_AIRPRIME is not set
 # CONFIG_USB_SERIAL_ARK3116 is not set
 # CONFIG_USB_SERIAL_BELKIN is not set
 # CONFIG_USB_SERIAL_CH341 is not set
@@ -1059,6 +1205,7 @@ CONFIG_USB_SERIAL=m
 # CONFIG_USB_SERIAL_EDGEPORT_TI is not set
 # CONFIG_USB_SERIAL_GARMIN is not set
 # CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
 # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
 # CONFIG_USB_SERIAL_KEYSPAN is not set
 # CONFIG_USB_SERIAL_KLSI is not set
@@ -1066,17 +1213,21 @@ CONFIG_USB_SERIAL=m
 # CONFIG_USB_SERIAL_MCT_U232 is not set
 # CONFIG_USB_SERIAL_MOS7720 is not set
 # CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
 # CONFIG_USB_SERIAL_NAVMAN is not set
 # CONFIG_USB_SERIAL_PL2303 is not set
 # CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
 # CONFIG_USB_SERIAL_HP4X is not set
 # CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
 # CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
 # CONFIG_USB_SERIAL_TI is not set
 # CONFIG_USB_SERIAL_CYBERJACK is not set
 # CONFIG_USB_SERIAL_XIRCOM is not set
 # CONFIG_USB_SERIAL_OPTION is not set
 # CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
 # CONFIG_USB_SERIAL_DEBUG is not set
 
 #
@@ -1085,7 +1236,7 @@ CONFIG_USB_SERIAL=m
 # CONFIG_USB_EMI62 is not set
 # CONFIG_USB_EMI26 is not set
 # CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_SEVSEG is not set
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
@@ -1101,30 +1252,29 @@ CONFIG_USB_SERIAL=m
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
 CONFIG_USB_GADGET=m
 # CONFIG_USB_GADGET_DEBUG is not set
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
 # CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
 CONFIG_USB_GADGET_SELECTED=y
-# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_AT91 is not set
 # CONFIG_USB_GADGET_ATMEL_USBA is not set
 # CONFIG_USB_GADGET_FSL_USB2 is not set
-# CONFIG_USB_GADGET_NET2280 is not set
-# CONFIG_USB_GADGET_PXA2XX is not set
-# CONFIG_USB_GADGET_M66592 is not set
-# CONFIG_USB_GADGET_GOKU is not set
 # CONFIG_USB_GADGET_LH7A40X is not set
 # CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
 # CONFIG_USB_GADGET_S3C2410 is not set
-# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
 CONFIG_USB_GADGET_DUMMY_HCD=y
 CONFIG_USB_DUMMY_HCD=m
 CONFIG_USB_GADGET_DUALSPEED=y
@@ -1134,21 +1284,32 @@ CONFIG_USB_GADGET_DUALSPEED=y
 # CONFIG_USB_FILE_STORAGE is not set
 # CONFIG_USB_G_SERIAL is not set
 # CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
 
 #
-# MMC/SD Card Drivers
+# MMC/SD/SDIO Card Drivers
 #
 CONFIG_MMC_BLOCK=y
 CONFIG_MMC_BLOCK_BOUNCE=y
 # CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
 
 #
-# MMC/SD Host Controller Drivers
+# MMC/SD/SDIO Host Controller Drivers
 #
 # CONFIG_MMC_PXA is not set
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
 CONFIG_NEW_LEDS=y
 # CONFIG_LEDS_CLASS is not set
 
@@ -1163,6 +1324,8 @@ CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 # CONFIG_LEDS_TRIGGER_IDE_DISK is not set
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 # CONFIG_RTC_HCTOSYS is not set
@@ -1190,6 +1353,9 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_PCF8563 is not set
 CONFIG_RTC_DRV_PCF8583=m
 # CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
 
 #
 # SPI RTC drivers
@@ -1199,36 +1365,45 @@ CONFIG_RTC_DRV_PCF8583=m
 # Platform RTC drivers
 #
 # CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
 #
 # on-CPU RTC drivers
 #
 # CONFIG_RTC_DRV_SA1100 is not set
+# CONFIG_RTC_DRV_PXA is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
 
 #
 # File systems
 #
 # CONFIG_EXT2_FS is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
 CONFIG_AUTOFS4_FS=y
 # CONFIG_FUSE_FS is not set
@@ -1254,15 +1429,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-15"
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
 CONFIG_CONFIGFS_FS=y
-
-#
-# Miscellaneous filesystems
-#
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_ECRYPT_FS is not set
@@ -1283,9 +1456,13 @@ CONFIG_JFFS2_ZLIB=y
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
@@ -1293,20 +1470,18 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
-# CONFIG_NFS_DIRECTIO is not set
+CONFIG_ROOT_NFS=y
 CONFIG_NFSD=y
 CONFIG_NFSD_V3=y
 # CONFIG_NFSD_V3_ACL is not set
 CONFIG_NFSD_V4=y
-CONFIG_NFSD_TCP=y
-CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
-# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_SUNRPC_REGISTER_V4 is not set
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -1361,9 +1536,6 @@ CONFIG_NLS_ISO8859_15=m
 # CONFIG_NLS_KOI8_U is not set
 CONFIG_NLS_UTF8=m
 # CONFIG_DLM is not set
-CONFIG_INSTRUMENTATION=y
-# CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
 
 #
 # Kernel hacking
@@ -1371,6 +1543,7 @@ CONFIG_INSTRUMENTATION=y
 CONFIG_PRINTK_TIME=y
 CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
@@ -1378,9 +1551,12 @@ CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
 CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_DEBUG_SLAB is not set
 CONFIG_DEBUG_PREEMPT=y
 # CONFIG_DEBUG_RT_MUTEXES is not set
@@ -1396,16 +1572,40 @@ CONFIG_DEBUG_PREEMPT=y
 CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
 CONFIG_FRAME_POINTER=y
-CONFIG_FORCED_INLINING=y
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
 # CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
 # CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
 
@@ -1415,58 +1615,114 @@ CONFIG_DEBUG_LL=y
 CONFIG_KEYS=y
 CONFIG_KEYS_DEBUG_PROC_KEYS=y
 CONFIG_SECURITY=y
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_NETWORK is not set
-CONFIG_SECURITY_CAPABILITIES=y
+# CONFIG_SECURITY_PATH is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
 # CONFIG_SECURITY_ROOTPLUG is not set
+CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
 CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
 CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
 CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
 CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
 # CONFIG_CRYPTO_HMAC is not set
 # CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
 CONFIG_CRYPTO_SHA1=m
 CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
-# CONFIG_CRYPTO_WP512 is not set
 # CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_XTS is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-CONFIG_CRYPTO_DES=y
-# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
 # CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
-CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_CAST5 is not set
 # CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SALSA20 is not set
 # CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
 CONFIG_CRYPTO_DEFLATE=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_CRC32C=y
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
-# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_HW=y
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=y
 CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/arm/configs/colibri_pxa300_defconfig b/arch/arm/configs/colibri_pxa300_defconfig
new file mode 100644
index 000000000000..4774a36fa740
--- /dev/null
+++ b/arch/arm/configs/colibri_pxa300_defconfig
@@ -0,0 +1,1156 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.29-rc8
+# Fri Mar 13 16:13:20 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+# CONFIG_SYSVIPC is not set
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+CONFIG_ARCH_PXA=y
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
+
+#
+# Intel PXA2xx/PXA3xx Implementations
+#
+
+#
+# Supported PXA3xx Processor Variants
+#
+CONFIG_CPU_PXA300=y
+# CONFIG_CPU_PXA310 is not set
+# CONFIG_CPU_PXA320 is not set
+# CONFIG_CPU_PXA930 is not set
+# CONFIG_CPU_PXA935 is not set
+# CONFIG_ARCH_GUMSTIX is not set
+# CONFIG_MACH_INTELMOTE2 is not set
+# CONFIG_ARCH_LUBBOCK is not set
+# CONFIG_MACH_LOGICPD_PXA270 is not set
+# CONFIG_MACH_MAINSTONE is not set
+# CONFIG_MACH_MP900C is not set
+# CONFIG_ARCH_PXA_IDP is not set
+# CONFIG_PXA_SHARPSL is not set
+# CONFIG_ARCH_VIPER is not set
+# CONFIG_ARCH_PXA_ESERIES is not set
+# CONFIG_TRIZEPS_PXA is not set
+# CONFIG_MACH_H5000 is not set
+# CONFIG_MACH_EM_X270 is not set
+# CONFIG_MACH_COLIBRI is not set
+CONFIG_MACH_COLIBRI300=y
+# CONFIG_MACH_ZYLONITE is not set
+# CONFIG_MACH_LITTLETON is not set
+# CONFIG_MACH_RAUMFELD_PROTO is not set
+# CONFIG_MACH_TAVOREVB is not set
+# CONFIG_MACH_SAAR is not set
+# CONFIG_MACH_ARMCORE is not set
+# CONFIG_MACH_CM_X300 is not set
+# CONFIG_MACH_MAGICIAN is not set
+# CONFIG_MACH_MIOA701 is not set
+# CONFIG_MACH_PCM027 is not set
+# CONFIG_ARCH_PXA_PALM is not set
+# CONFIG_PXA_EZX is not set
+CONFIG_PXA3xx=y
+# CONFIG_PXA_PWM is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSC3=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_IO_36=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_OUTER_CACHE=y
+CONFIG_CACHE_XSC3L2=y
+CONFIG_IWMMXT=y
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="console=ttyS0,115200 rw"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_FREQ is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_COMPAT_NET_DEV_OPS=y
+# CONFIG_PACKET is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_BEET=y
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=y
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_AX88796=y
+# CONFIG_AX88796_93CX6 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+# CONFIG_INPUT_UINPUT is not set
+CONFIG_INPUT_GPIO_ROTARY_ENCODER=y
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_PXA=y
+CONFIG_SERIAL_PXA_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_DEBUG_GPIO=y
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_PXA=y
+# CONFIG_FB_PXA_OVERLAY is not set
+# CONFIG_FB_PXA_SMARTPANEL is not set
+# CONFIG_FB_PXA_PARAMETERS is not set
+# CONFIG_FB_MBX is not set
+# CONFIG_FB_W100 is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+#
+
+#
+# see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_PXA=y
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/collie_defconfig b/arch/arm/configs/collie_defconfig
index f7622e658163..1aa62249031b 100644
--- a/arch/arm/configs/collie_defconfig
+++ b/arch/arm/configs/collie_defconfig
@@ -113,7 +113,6 @@ CONFIG_ARCH_SA1100=y
 CONFIG_SA1100_COLLIE=y
 # CONFIG_SA1100_H3100 is not set
 # CONFIG_SA1100_H3600 is not set
-# CONFIG_SA1100_H3800 is not set
 # CONFIG_SA1100_BADGE4 is not set
 # CONFIG_SA1100_JORNADA720 is not set
 # CONFIG_SA1100_HACKKIT is not set
diff --git a/arch/arm/configs/em_x270_defconfig b/arch/arm/configs/em_x270_defconfig
new file mode 100644
index 000000000000..e9955b786c80
--- /dev/null
+++ b/arch/arm/configs/em_x270_defconfig
@@ -0,0 +1,1741 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.29-rc2
+# Sun Feb  1 16:43:31 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+CONFIG_ARCH_PXA=y
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
+
+#
+# Intel PXA2xx/PXA3xx Implementations
+#
+# CONFIG_ARCH_GUMSTIX is not set
+# CONFIG_MACH_INTELMOTE2 is not set
+# CONFIG_ARCH_LUBBOCK is not set
+# CONFIG_MACH_LOGICPD_PXA270 is not set
+# CONFIG_MACH_MAINSTONE is not set
+# CONFIG_MACH_MP900C is not set
+# CONFIG_ARCH_PXA_IDP is not set
+# CONFIG_PXA_SHARPSL is not set
+# CONFIG_ARCH_VIPER is not set
+# CONFIG_ARCH_PXA_ESERIES is not set
+# CONFIG_TRIZEPS_PXA is not set
+# CONFIG_MACH_H5000 is not set
+CONFIG_MACH_EM_X270=y
+CONFIG_MACH_EXEDA=y
+# CONFIG_MACH_COLIBRI is not set
+# CONFIG_MACH_ZYLONITE is not set
+# CONFIG_MACH_LITTLETON is not set
+# CONFIG_MACH_TAVOREVB is not set
+# CONFIG_MACH_SAAR is not set
+# CONFIG_MACH_ARMCORE is not set
+# CONFIG_MACH_CM_X300 is not set
+# CONFIG_MACH_MAGICIAN is not set
+# CONFIG_MACH_MIOA701 is not set
+# CONFIG_MACH_PCM027 is not set
+# CONFIG_ARCH_PXA_PALM is not set
+# CONFIG_PXA_EZX is not set
+CONFIG_PXA27x=y
+CONFIG_PXA_SSP=y
+# CONFIG_PXA_PWM is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+CONFIG_IWMMXT=y
+CONFIG_XSCALE_PMU=y
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="root=1f03 mem=32M"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_USERSPACE=m
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_APM_EMULATION=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_COMPAT_NET_DEV_OPS=y
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+# CONFIG_BT_RFCOMM_TTY is not set
+CONFIG_BT_BNEP=m
+# CONFIG_BT_BNEP_MC_FILTER is not set
+# CONFIG_BT_BNEP_PROTO_FILTER is not set
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=m
+# CONFIG_BT_HCIBTSDIO is not set
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=m
+# CONFIG_MAC80211 is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=m
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_GEOMETRY is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+CONFIG_MTD_PXA2XX=y
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
+# CONFIG_MTD_SHARP_SL is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_H1900 is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_SHARPSL is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+# CONFIG_MTD_QINFO_PROBE is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+CONFIG_DM9000=y
+CONFIG_DM9000_DEBUGLEVEL=1
+# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+CONFIG_LIBERTAS=m
+# CONFIG_LIBERTAS_USB is not set
+CONFIG_LIBERTAS_SDIO=m
+# CONFIG_LIBERTAS_DEBUG is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_HOSTAP is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+CONFIG_INPUT_APMPOWER=y
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_PXA27x=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_DA9034 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+CONFIG_TOUCHSCREEN_WM97XX=m
+# CONFIG_TOUCHSCREEN_WM9705 is not set
+CONFIG_TOUCHSCREEN_WM9712=y
+# CONFIG_TOUCHSCREEN_WM9713 is not set
+# CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_PXA=y
+CONFIG_SERIAL_PXA_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_PXA=y
+# CONFIG_I2C_PXA_SLAVE is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_PXA2XX=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_APM_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+CONFIG_BATTERY_DA9030=y
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_UCB1400_CORE is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+CONFIG_PMIC_DA903X=y
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+# CONFIG_VIDEO_ALLOW_V4L1 is not set
+CONFIG_VIDEO_V4L1_COMPAT=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=m
+CONFIG_MEDIA_TUNER_CUSTOMIZE=y
+# CONFIG_MEDIA_TUNER_SIMPLE is not set
+# CONFIG_MEDIA_TUNER_TDA8290 is not set
+# CONFIG_MEDIA_TUNER_TDA827X is not set
+# CONFIG_MEDIA_TUNER_TDA18271 is not set
+# CONFIG_MEDIA_TUNER_TDA9887 is not set
+# CONFIG_MEDIA_TUNER_TEA5761 is not set
+# CONFIG_MEDIA_TUNER_TEA5767 is not set
+# CONFIG_MEDIA_TUNER_MT20XX is not set
+# CONFIG_MEDIA_TUNER_MT2060 is not set
+# CONFIG_MEDIA_TUNER_MT2266 is not set
+# CONFIG_MEDIA_TUNER_MT2131 is not set
+# CONFIG_MEDIA_TUNER_QT1010 is not set
+# CONFIG_MEDIA_TUNER_XC2028 is not set
+# CONFIG_MEDIA_TUNER_XC5000 is not set
+# CONFIG_MEDIA_TUNER_MXL5005S is not set
+# CONFIG_MEDIA_TUNER_MXL5007T is not set
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEOBUF_GEN=m
+CONFIG_VIDEOBUF_DMA_SG=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+
+#
+# Encoders/decoders and other helper chips
+#
+
+#
+# Audio decoders
+#
+# CONFIG_VIDEO_TVAUDIO is not set
+# CONFIG_VIDEO_TDA7432 is not set
+# CONFIG_VIDEO_TDA9840 is not set
+# CONFIG_VIDEO_TDA9875 is not set
+# CONFIG_VIDEO_TEA6415C is not set
+# CONFIG_VIDEO_TEA6420 is not set
+# CONFIG_VIDEO_MSP3400 is not set
+# CONFIG_VIDEO_CS5345 is not set
+# CONFIG_VIDEO_CS53L32A is not set
+# CONFIG_VIDEO_M52790 is not set
+# CONFIG_VIDEO_TLV320AIC23B is not set
+# CONFIG_VIDEO_WM8775 is not set
+# CONFIG_VIDEO_WM8739 is not set
+# CONFIG_VIDEO_VP27SMPX is not set
+
+#
+# Video decoders
+#
+# CONFIG_VIDEO_OV7670 is not set
+# CONFIG_VIDEO_TCM825X is not set
+# CONFIG_VIDEO_SAA711X is not set
+# CONFIG_VIDEO_SAA717X is not set
+# CONFIG_VIDEO_TVP514X is not set
+# CONFIG_VIDEO_TVP5150 is not set
+
+#
+# Video and audio decoders
+#
+# CONFIG_VIDEO_CX25840 is not set
+
+#
+# MPEG video encoders
+#
+# CONFIG_VIDEO_CX2341X is not set
+
+#
+# Video encoders
+#
+# CONFIG_VIDEO_SAA7127 is not set
+
+#
+# Video improvement chips
+#
+# CONFIG_VIDEO_UPD64031A is not set
+# CONFIG_VIDEO_UPD64083 is not set
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+CONFIG_SOC_CAMERA=m
+# CONFIG_SOC_CAMERA_MT9M001 is not set
+CONFIG_SOC_CAMERA_MT9M111=m
+# CONFIG_SOC_CAMERA_MT9T031 is not set
+# CONFIG_SOC_CAMERA_MT9V022 is not set
+# CONFIG_SOC_CAMERA_TW9910 is not set
+# CONFIG_SOC_CAMERA_PLATFORM is not set
+# CONFIG_SOC_CAMERA_OV772X is not set
+CONFIG_VIDEO_PXA27x=m
+# CONFIG_VIDEO_SH_MOBILE_CEU is not set
+# CONFIG_V4L_USB_DRIVERS is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_PXA=y
+# CONFIG_FB_PXA_OVERLAY is not set
+# CONFIG_FB_PXA_SMARTPANEL is not set
+CONFIG_FB_PXA_PARAMETERS=y
+CONFIG_FB_MBX=m
+# CONFIG_FB_MBX_DEBUG is not set
+# CONFIG_FB_W100 is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_ILI9320 is not set
+CONFIG_LCD_TDO24M=y
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LCD_PLATFORM is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=m
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_DA903X=m
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=m
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+CONFIG_SND_AC97_CODEC=m
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_PXA2XX_LIB=m
+CONFIG_SND_PXA2XX_LIB_AC97=y
+# CONFIG_SND_PXA2XX_AC97 is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=m
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_PXA2XX_SOC=m
+CONFIG_SND_PXA2XX_SOC_AC97=m
+CONFIG_SND_PXA2XX_SOC_EM_X270=m
+CONFIG_SND_SOC_I2C_AND_SPI=m
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_WM9712=m
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=m
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_LOGITECH=y
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+# CONFIG_HID_NTRIG is not set
+CONFIG_HID_PANTHERLORD=y
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+# CONFIG_GREENASIA_FF is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+#
+
+#
+# see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+CONFIG_MMC=m
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=m
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_PXA=m
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_SPI is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_GPIO is not set
+# CONFIG_LEDS_PCA955X is not set
+CONFIG_LEDS_DA903X=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+CONFIG_RTC_DRV_V3020=y
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_SA1100=y
+# CONFIG_RTC_DRV_PXA is not set
+# CONFIG_DMADEVICES is not set
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+CONFIG_REGULATOR_DA903X=y
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=m
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=m
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=0
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_ALGAPI2=m
+CONFIG_CRYPTO_AEAD2=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_BLKCIPHER2=m
+CONFIG_CRYPTO_HASH=m
+CONFIG_CRYPTO_HASH2=m
+CONFIG_CRYPTO_RNG2=m
+CONFIG_CRYPTO_MANAGER=m
+CONFIG_CRYPTO_MANAGER2=m
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+CONFIG_CRYPTO_MICHAEL_MIC=m
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=m
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/h3600_defconfig b/arch/arm/configs/h3600_defconfig
index 8f986e9f1c62..1502957db2c3 100644
--- a/arch/arm/configs/h3600_defconfig
+++ b/arch/arm/configs/h3600_defconfig
@@ -90,7 +90,6 @@ CONFIG_ARCH_SA1100=y
 # CONFIG_SA1100_COLLIE is not set
 # CONFIG_SA1100_H3100 is not set
 CONFIG_SA1100_H3600=y
-# CONFIG_SA1100_H3800 is not set
 CONFIG_SA1100_H3XXX=y
 # CONFIG_SA1100_BADGE4 is not set
 # CONFIG_SA1100_JORNADA720 is not set
@@ -100,7 +99,6 @@ CONFIG_SA1100_H3XXX=y
 # CONFIG_SA1100_SHANNON is not set
 # CONFIG_SA1100_SIMPAD is not set
 # CONFIG_SA1100_SSP is not set
-# CONFIG_H3600_SLEEVE is not set
 
 #
 # Processor Type
diff --git a/arch/arm/configs/hackkit_defconfig b/arch/arm/configs/hackkit_defconfig
index 1c8fb89a6730..db0708d5cbea 100644
--- a/arch/arm/configs/hackkit_defconfig
+++ b/arch/arm/configs/hackkit_defconfig
@@ -91,7 +91,6 @@ CONFIG_ARCH_SA1100=y
 # CONFIG_SA1100_COLLIE is not set
 # CONFIG_SA1100_H3100 is not set
 # CONFIG_SA1100_H3600 is not set
-# CONFIG_SA1100_H3800 is not set
 # CONFIG_SA1100_BADGE4 is not set
 # CONFIG_SA1100_JORNADA720 is not set
 CONFIG_SA1100_HACKKIT=y
diff --git a/arch/arm/configs/jornada720_defconfig b/arch/arm/configs/jornada720_defconfig
index 81fadafae02d..f3074e49f2fa 100644
--- a/arch/arm/configs/jornada720_defconfig
+++ b/arch/arm/configs/jornada720_defconfig
@@ -178,7 +178,6 @@ CONFIG_DMABOUNCE=y
 # CONFIG_SA1100_COLLIE is not set
 # CONFIG_SA1100_H3100 is not set
 # CONFIG_SA1100_H3600 is not set
-# CONFIG_SA1100_H3800 is not set
 # CONFIG_SA1100_BADGE4 is not set
 CONFIG_SA1100_JORNADA720=y
 CONFIG_SA1100_JORNADA720_SSP=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index 4bc38078d580..c367ae44012e 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -1,11 +1,11 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.28-rc7
-# Thu Dec  4 15:27:39 2008
+# Linux kernel version: 2.6.29-rc5
+# Tue Mar  3 21:45:57 2009
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-# CONFIG_GENERIC_GPIO is not set
+CONFIG_GENERIC_GPIO=y
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_MMU=y
@@ -42,10 +42,19 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
+CONFIG_LOG_BUF_SHIFT=19
 # CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
 # CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
 CONFIG_NAMESPACES=y
@@ -53,6 +62,7 @@ CONFIG_NAMESPACES=y
 # CONFIG_IPC_NS is not set
 # CONFIG_USER_NS is not set
 # CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
 # CONFIG_BLK_DEV_INITRD is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
@@ -83,6 +93,7 @@ CONFIG_SLUB_DEBUG=y
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 CONFIG_PROFILING=y
+CONFIG_TRACEPOINTS=y
 # CONFIG_MARKERS is not set
 CONFIG_OPROFILE=y
 CONFIG_HAVE_OPROFILE=y
@@ -93,7 +104,6 @@ CONFIG_HAVE_KRETPROBES=y
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
 # CONFIG_MODULE_FORCE_LOAD is not set
@@ -101,11 +111,9 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -121,7 +129,6 @@ CONFIG_IOSCHED_CFQ=y
 CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_CLASSIC_RCU=y
 # CONFIG_FREEZER is not set
 
 #
@@ -132,7 +139,6 @@ CONFIG_CLASSIC_RCU=y
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS7500 is not set
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_EBSA110 is not set
 # CONFIG_ARCH_EP93XX is not set
@@ -159,11 +165,13 @@ CONFIG_ARCH_KIRKWOOD=y
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
 # CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
 
 #
 # Marvell Kirkwood Implementations
@@ -171,14 +179,8 @@ CONFIG_ARCH_KIRKWOOD=y
 CONFIG_MACH_DB88F6281_BP=y
 CONFIG_MACH_RD88F6192_NAS=y
 CONFIG_MACH_RD88F6281=y
-
-#
-# Boot options
-#
-
-#
-# Power management
-#
+CONFIG_MACH_SHEEVAPLUG=y
+CONFIG_MACH_TS219=y
 CONFIG_PLAT_ORION=y
 
 #
@@ -214,6 +216,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
 CONFIG_PCI_LEGACY=y
 # CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_STUB is not set
 # CONFIG_PCCARD is not set
 
 #
@@ -242,7 +245,6 @@ CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_RESOURCES_64BIT is not set
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
@@ -291,6 +293,7 @@ CONFIG_NET=y
 #
 # Networking options
 #
+CONFIG_COMPAT_NET_DEV_OPS=y
 CONFIG_PACKET=y
 CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
@@ -355,6 +358,7 @@ CONFIG_NET_DSA_MV88E6123_61_65=y
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
 # CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
 
 #
 # Network testing
@@ -368,12 +372,27 @@ CONFIG_NET_PKTGEN=m
 # CONFIG_AF_RXRPC is not set
 # CONFIG_PHONET is not set
 CONFIG_WIRELESS=y
-# CONFIG_CFG80211 is not set
+CONFIG_CFG80211=y
+# CONFIG_CFG80211_REG_DEBUG is not set
+# CONFIG_NL80211 is not set
 CONFIG_WIRELESS_OLD_REGULATORY=y
 CONFIG_WIRELESS_EXT=y
 CONFIG_WIRELESS_EXT_SYSFS=y
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
+CONFIG_LIB80211=y
+CONFIG_MAC80211=y
+
+#
+# Rate control algorithm selection
+#
+CONFIG_MAC80211_RC_MINSTREL=y
+# CONFIG_MAC80211_RC_DEFAULT_PID is not set
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel"
+# CONFIG_MAC80211_MESH is not set
+# CONFIG_MAC80211_LEDS is not set
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
 
@@ -398,6 +417,7 @@ CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_REDBOOT_PARTS is not set
 CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AFS_PARTS is not set
@@ -451,9 +471,7 @@ CONFIG_MTD_CFI_UTIL=y
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
 CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0x0
-CONFIG_MTD_PHYSMAP_LEN=0x0
-CONFIG_MTD_PHYSMAP_BANKWIDTH=0
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
 # CONFIG_MTD_ARM_INTEGRATOR is not set
 # CONFIG_MTD_IMPA7 is not set
 # CONFIG_MTD_INTEL_VR_NOR is not set
@@ -481,6 +499,7 @@ CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
 # CONFIG_MTD_NAND_ECC_SMC is not set
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_CAFE is not set
@@ -491,6 +510,12 @@ CONFIG_MTD_NAND_ORION=y
 # CONFIG_MTD_ONENAND is not set
 
 #
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+# CONFIG_MTD_QINFO_PROBE is not set
+
+#
 # UBI - Unsorted block images
 #
 # CONFIG_MTD_UBI is not set
@@ -568,6 +593,8 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_MEGARAID_LEGACY is not set
 # CONFIG_MEGARAID_SAS is not set
 # CONFIG_SCSI_HPTIOP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_FCOE is not set
 # CONFIG_SCSI_DMX3191D is not set
 # CONFIG_SCSI_FUTURE_DOMAIN is not set
 # CONFIG_SCSI_IPS is not set
@@ -682,6 +709,9 @@ CONFIG_MARVELL_PHY=y
 # CONFIG_BROADCOM_PHY is not set
 # CONFIG_ICPLUS_PHY is not set
 # CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
 # CONFIG_FIXED_PHY is not set
 # CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
@@ -695,6 +725,7 @@ CONFIG_MII=y
 # CONFIG_DM9000 is not set
 # CONFIG_ENC28J60 is not set
 # CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
@@ -710,7 +741,6 @@ CONFIG_NET_PCI=y
 # CONFIG_ADAPTEC_STARFIRE is not set
 # CONFIG_B44 is not set
 # CONFIG_FORCEDETH is not set
-# CONFIG_EEPRO100 is not set
 # CONFIG_E100 is not set
 # CONFIG_FEALNX is not set
 # CONFIG_NATSEMI is not set
@@ -720,6 +750,7 @@ CONFIG_NET_PCI=y
 # CONFIG_R6040 is not set
 # CONFIG_SIS900 is not set
 # CONFIG_EPIC100 is not set
+# CONFIG_SMSC9420 is not set
 # CONFIG_SUNDANCE is not set
 # CONFIG_TLAN is not set
 # CONFIG_VIA_RHINE is not set
@@ -754,8 +785,39 @@ CONFIG_MV643XX_ETH=y
 # Wireless LAN
 #
 # CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
+CONFIG_WLAN_80211=y
+CONFIG_LIBERTAS=y
+# CONFIG_LIBERTAS_USB is not set
+CONFIG_LIBERTAS_SDIO=y
+# CONFIG_LIBERTAS_DEBUG is not set
+# CONFIG_LIBERTAS_THINFIRM is not set
+# CONFIG_HERMES is not set
+# CONFIG_ATMEL is not set
+# CONFIG_PRISM54 is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8180 is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_ADM8211 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_P54_COMMON is not set
+# CONFIG_ATH5K is not set
+# CONFIG_ATH9K is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_IWLCORE is not set
 # CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_IWLAGN is not set
+# CONFIG_IWL3945 is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_ZD1211RW is not set
+# CONFIG_RT2X00 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
 
 #
 # USB Network Adapters
@@ -791,13 +853,20 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_EVDEV is not set
+CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
 #
 # Input Device Drivers
 #
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
@@ -807,7 +876,11 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 #
 # Hardware I/O ports
 #
-# CONFIG_SERIO is not set
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
 
 #
@@ -839,11 +912,11 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_JSM is not set
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_NVRAM is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
 # CONFIG_RAW_DRIVER is not set
@@ -879,6 +952,7 @@ CONFIG_I2C_HELPER_AUTO=y
 #
 # I2C system bus drivers (mostly embedded / system-on-chip)
 #
+# CONFIG_I2C_GPIO is not set
 CONFIG_I2C_MV64XXX=y
 # CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_SIMTEC is not set
@@ -905,8 +979,6 @@ CONFIG_I2C_MV64XXX=y
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
-# CONFIG_EEPROM_AT24 is not set
-# CONFIG_EEPROM_LEGACY is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
@@ -925,12 +997,12 @@ CONFIG_SPI_MASTER=y
 # SPI Master Controller Drivers
 #
 # CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
 CONFIG_SPI_ORION=y
 
 #
 # SPI Protocol Masters
 #
-# CONFIG_EEPROM_AT25 is not set
 # CONFIG_SPI_SPIDEV is not set
 # CONFIG_SPI_TLE62X0 is not set
 # CONFIG_W1 is not set
@@ -952,10 +1024,12 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
 # CONFIG_MFD_TMIO is not set
 # CONFIG_PMIC_DA903X is not set
 # CONFIG_MFD_WM8400 is not set
 # CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
 
 #
 # Multimedia devices
@@ -1012,11 +1086,9 @@ CONFIG_HID_COMPAT=y
 CONFIG_HID_A4TECH=y
 CONFIG_HID_APPLE=y
 CONFIG_HID_BELKIN=y
-CONFIG_HID_BRIGHT=y
 CONFIG_HID_CHERRY=y
 CONFIG_HID_CHICONY=y
 CONFIG_HID_CYPRESS=y
-CONFIG_HID_DELL=y
 CONFIG_HID_EZKEY=y
 CONFIG_HID_GYRATION=y
 CONFIG_HID_LOGITECH=y
@@ -1024,12 +1096,15 @@ CONFIG_HID_LOGITECH=y
 # CONFIG_LOGIRUMBLEPAD2_FF is not set
 CONFIG_HID_MICROSOFT=y
 CONFIG_HID_MONTEREY=y
+CONFIG_HID_NTRIG=y
 CONFIG_HID_PANTHERLORD=y
 # CONFIG_PANTHERLORD_FF is not set
 CONFIG_HID_PETALYNX=y
 CONFIG_HID_SAMSUNG=y
 CONFIG_HID_SONY=y
 CONFIG_HID_SUNPLUS=y
+# CONFIG_GREENASIA_FF is not set
+CONFIG_HID_TOPSEED=y
 # CONFIG_THRUSTMASTER_FF is not set
 # CONFIG_ZEROPLUS_FF is not set
 CONFIG_USB_SUPPORT=y
@@ -1058,6 +1133,7 @@ CONFIG_USB_DEVICE_CLASS=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 CONFIG_USB_EHCI_TT_NEWSCHED=y
+# CONFIG_USB_OXU210HP_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
 # CONFIG_USB_ISP1760_HCD is not set
 # CONFIG_USB_OHCI_HCD is not set
@@ -1087,7 +1163,6 @@ CONFIG_USB_STORAGE=y
 CONFIG_USB_STORAGE_DATAFAB=y
 CONFIG_USB_STORAGE_FREECOM=y
 # CONFIG_USB_STORAGE_ISD200 is not set
-CONFIG_USB_STORAGE_DPCM=y
 # CONFIG_USB_STORAGE_USBAT is not set
 CONFIG_USB_STORAGE_SDDR09=y
 CONFIG_USB_STORAGE_SDDR55=y
@@ -1135,21 +1210,51 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
 # CONFIG_USB_ISIGHTFW is not set
 # CONFIG_USB_VST is not set
 # CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
 # CONFIG_UWB is not set
-# CONFIG_MMC is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MMC_MVSDIO=y
+# CONFIG_MMC_SPI is not set
 # CONFIG_MEMSTICK is not set
 # CONFIG_ACCESSIBILITY is not set
 CONFIG_NEW_LEDS=y
-# CONFIG_LEDS_CLASS is not set
+CONFIG_LEDS_CLASS=y
 
 #
 # LED drivers
 #
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_PCA955X is not set
 
 #
 # LED Triggers
 #
-# CONFIG_LEDS_TRIGGERS is not set
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -1178,7 +1283,7 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_PCF8563 is not set
 # CONFIG_RTC_DRV_PCF8583 is not set
 # CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_S35390A is not set
+CONFIG_RTC_DRV_S35390A=y
 # CONFIG_RTC_DRV_FM3130 is not set
 # CONFIG_RTC_DRV_RX8581 is not set
 
@@ -1227,6 +1332,7 @@ CONFIG_DMA_ENGINE=y
 # CONFIG_DMATEST is not set
 # CONFIG_REGULATOR is not set
 # CONFIG_UIO is not set
+# CONFIG_STAGING is not set
 
 #
 # File systems
@@ -1238,16 +1344,14 @@ CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
 # CONFIG_EXT4_FS is not set
 CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 CONFIG_FILE_LOCKING=y
-CONFIG_XFS_FS=y
-# CONFIG_XFS_QUOTA is not set
-# CONFIG_XFS_POSIX_ACL is not set
-# CONFIG_XFS_RT is not set
-# CONFIG_XFS_DEBUG is not set
+# CONFIG_XFS_FS is not set
 # CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -1268,9 +1372,9 @@ CONFIG_UDF_NLS=y
 #
 # DOS/FAT/NT Filesystems
 #
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
 CONFIG_FAT_DEFAULT_CODEPAGE=437
 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 # CONFIG_NTFS_FS is not set
@@ -1286,10 +1390,7 @@ CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -1309,6 +1410,7 @@ CONFIG_JFFS2_ZLIB=y
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_OMFS_FS is not set
@@ -1393,7 +1495,7 @@ CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
 # CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
+CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
@@ -1416,6 +1518,7 @@ CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
 # CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_INFO=y
@@ -1424,7 +1527,7 @@ CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_MEMORY_INIT=y
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
-CONFIG_FRAME_POINTER=y
+# CONFIG_DEBUG_NOTIFIERS is not set
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
@@ -1435,7 +1538,10 @@ CONFIG_FRAME_POINTER=y
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_LATENCYTOP is not set
 CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_NOP_TRACER=y
 CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_RING_BUFFER=y
+CONFIG_TRACING=y
 
 #
 # Tracers
@@ -1446,11 +1552,14 @@ CONFIG_HAVE_FUNCTION_TRACER=y
 # CONFIG_SCHED_TRACER is not set
 # CONFIG_CONTEXT_SWITCH_TRACER is not set
 # CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
 # CONFIG_STACK_TRACER is not set
+# CONFIG_FTRACE_STARTUP_TEST is not set
 # CONFIG_DYNAMIC_PRINTK_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_ERRORS=y
 # CONFIG_DEBUG_STACK_USAGE is not set
@@ -1464,19 +1573,22 @@ CONFIG_DEBUG_LL=y
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_ASYNC_CORE=y
 CONFIG_CRYPTO=y
 
 #
 # Crypto core or helper
 #
 # CONFIG_CRYPTO_FIPS is not set
-CONFIG_CRYPTO_ALGAPI=m
-CONFIG_CRYPTO_AEAD=m
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_HASH=m
-CONFIG_CRYPTO_RNG=m
-CONFIG_CRYPTO_MANAGER=m
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
 # CONFIG_CRYPTO_GF128MUL is not set
 # CONFIG_CRYPTO_NULL is not set
 # CONFIG_CRYPTO_CRYPTD is not set
@@ -1496,7 +1608,7 @@ CONFIG_CRYPTO_MANAGER=m
 CONFIG_CRYPTO_CBC=m
 # CONFIG_CRYPTO_CTR is not set
 # CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_ECB=y
 # CONFIG_CRYPTO_LRW is not set
 CONFIG_CRYPTO_PCBC=m
 # CONFIG_CRYPTO_XTS is not set
@@ -1510,7 +1622,7 @@ CONFIG_CRYPTO_PCBC=m
 #
 # Digest
 #
-# CONFIG_CRYPTO_CRC32C is not set
+CONFIG_CRYPTO_CRC32C=y
 # CONFIG_CRYPTO_MD4 is not set
 # CONFIG_CRYPTO_MD5 is not set
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
@@ -1527,9 +1639,9 @@ CONFIG_CRYPTO_PCBC=m
 #
 # Ciphers
 #
-# CONFIG_CRYPTO_AES is not set
+CONFIG_CRYPTO_AES=y
 # CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_ARC4 is not set
+CONFIG_CRYPTO_ARC4=y
 # CONFIG_CRYPTO_BLOWFISH is not set
 # CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_CAST5 is not set
@@ -1560,6 +1672,7 @@ CONFIG_CRYPTO_HW=y
 # Library routines
 #
 CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=y
 CONFIG_CRC16=y
 # CONFIG_CRC_T10DIF is not set
diff --git a/arch/arm/configs/lart_defconfig b/arch/arm/configs/lart_defconfig
index a1cc34f25602..56ae56899d2e 100644
--- a/arch/arm/configs/lart_defconfig
+++ b/arch/arm/configs/lart_defconfig
@@ -87,7 +87,6 @@ CONFIG_ARCH_SA1100=y
 # CONFIG_SA1100_COLLIE is not set
 # CONFIG_SA1100_H3100 is not set
 # CONFIG_SA1100_H3600 is not set
-# CONFIG_SA1100_H3800 is not set
 # CONFIG_SA1100_BADGE4 is not set
 # CONFIG_SA1100_JORNADA720 is not set
 # CONFIG_SA1100_HACKKIT is not set
diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig
index 73ba62b71063..82428c2f234c 100644
--- a/arch/arm/configs/magician_defconfig
+++ b/arch/arm/configs/magician_defconfig
@@ -1,9 +1,10 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.24-rc6
-# Sun Dec 30 13:02:54 2007
+# Linux kernel version: 2.6.29-rc3
+# Fri Jan 30 12:42:03 2009
 #
 CONFIG_ARM=y
+CONFIG_HAVE_PWM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_GENERIC_TIME=y
@@ -12,6 +13,7 @@ CONFIG_MMU=y
 # CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
@@ -21,8 +23,8 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ZONE_DMA=y
 CONFIG_ARCH_MTD_XIP=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
@@ -41,16 +43,24 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_GROUP_SCHED is not set
 # CONFIG_CGROUPS is not set
-# CONFIG_FAIR_GROUP_SCHED is not set
-# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
@@ -65,31 +75,41 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
+CONFIG_AIO=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -103,8 +123,7 @@ CONFIG_IOSCHED_NOOP=y
 # CONFIG_DEFAULT_CFQ is not set
 CONFIG_DEFAULT_NOOP=y
 CONFIG_DEFAULT_IOSCHED="noop"
-CONFIG_CLASSIC_RCU=y
-# CONFIG_PREEMPT_RCU is not set
+CONFIG_FREEZER=y
 
 #
 # System Type
@@ -114,9 +133,7 @@ CONFIG_CLASSIC_RCU=y
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS7500 is not set
 # CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
 # CONFIG_ARCH_EP93XX is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
@@ -130,41 +147,58 @@ CONFIG_CLASSIC_RCU=y
 # CONFIG_ARCH_IXP2000 is not set
 # CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
 # CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
 # CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
 # CONFIG_ARCH_PNX4008 is not set
 CONFIG_ARCH_PXA=y
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
 
 #
 # Intel PXA2xx/PXA3xx Implementations
 #
+# CONFIG_ARCH_GUMSTIX is not set
+# CONFIG_MACH_INTELMOTE2 is not set
 # CONFIG_ARCH_LUBBOCK is not set
 # CONFIG_MACH_LOGICPD_PXA270 is not set
 # CONFIG_MACH_MAINSTONE is not set
+# CONFIG_MACH_MP900C is not set
 # CONFIG_ARCH_PXA_IDP is not set
 # CONFIG_PXA_SHARPSL is not set
-# CONFIG_MACH_TRIZEPS4 is not set
+# CONFIG_ARCH_VIPER is not set
+# CONFIG_ARCH_PXA_ESERIES is not set
+# CONFIG_TRIZEPS_PXA is not set
+# CONFIG_MACH_H5000 is not set
 # CONFIG_MACH_EM_X270 is not set
+# CONFIG_MACH_COLIBRI is not set
 # CONFIG_MACH_ZYLONITE is not set
+# CONFIG_MACH_LITTLETON is not set
+# CONFIG_MACH_TAVOREVB is not set
+# CONFIG_MACH_SAAR is not set
 # CONFIG_MACH_ARMCORE is not set
+# CONFIG_MACH_CM_X300 is not set
 CONFIG_MACH_MAGICIAN=y
+# CONFIG_MACH_MIOA701 is not set
+# CONFIG_MACH_PCM027 is not set
+# CONFIG_ARCH_PXA_PALM is not set
+# CONFIG_PXA_EZX is not set
 CONFIG_PXA27x=y
-
-#
-# Boot options
-#
-
-#
-# Power management
-#
+CONFIG_PXA_SSP=y
+CONFIG_PXA_PWM=y
+CONFIG_PXA_HAVE_BOARD_IRQS=y
 
 #
 # Processor Type
@@ -173,6 +207,7 @@ CONFIG_CPU_32=y
 CONFIG_CPU_XSCALE=y
 CONFIG_CPU_32v5=y
 CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_NOIFAR=y
 CONFIG_CPU_CACHE_VIVT=y
 CONFIG_CPU_TLB_V4WBI=y
 CONFIG_CPU_CP15=y
@@ -186,6 +221,7 @@ CONFIG_ARM_THUMB=y
 # CONFIG_OUTER_CACHE is not set
 CONFIG_IWMMXT=y
 CONFIG_XSCALE_PMU=y
+CONFIG_COMMON_CLKDEV=y
 
 #
 # Bus support
@@ -197,28 +233,33 @@ CONFIG_XSCALE_PMU=y
 #
 # Kernel Features
 #
-# CONFIG_TICK_ONESHOT is not set
-# CONFIG_NO_HZ is not set
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
 # CONFIG_HIGH_RES_TIMERS is not set
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
 CONFIG_PREEMPT=y
 CONFIG_HZ=100
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y
-# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_RESOURCES_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_BOUNCE=y
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
 CONFIG_ALIGNMENT_TRAP=y
 
 #
@@ -229,9 +270,10 @@ CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="keepinitrd"
 # CONFIG_XIP_KERNEL is not set
 CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
 
 #
-# CPU Frequency scaling
+# CPU Power Management
 #
 CONFIG_CPU_FREQ=y
 CONFIG_CPU_FREQ_TABLE=y
@@ -239,6 +281,7 @@ CONFIG_CPU_FREQ_TABLE=y
 CONFIG_CPU_FREQ_STAT=y
 # CONFIG_CPU_FREQ_STAT_DETAILS is not set
 CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
 # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
 # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
 # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
@@ -247,6 +290,7 @@ CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
 # CONFIG_CPU_FREQ_GOV_USERSPACE is not set
 CONFIG_CPU_FREQ_GOV_ONDEMAND=y
 # CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_IDLE is not set
 
 #
 # Floating point emulation
@@ -263,6 +307,8 @@ CONFIG_FPE_NWFPE=y
 # Userspace binary formats
 #
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
 # CONFIG_BINFMT_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 
@@ -270,21 +316,18 @@ CONFIG_BINFMT_ELF=y
 # Power management options
 #
 CONFIG_PM=y
-# CONFIG_PM_LEGACY is not set
 # CONFIG_PM_DEBUG is not set
 CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND_UP_POSSIBLE=y
 CONFIG_SUSPEND=y
-CONFIG_APM_EMULATION=y
-
-#
-# Networking
-#
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_NET=y
 
 #
 # Networking options
 #
+CONFIG_COMPAT_NET_DEV_OPS=y
 CONFIG_PACKET=y
 CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
@@ -316,33 +359,15 @@ CONFIG_IP_PNP=y
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
-# CONFIG_IP_VS is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-
-#
-# Core Netfilter Configuration
-#
-# CONFIG_NETFILTER_NETLINK is not set
-# CONFIG_NF_CONNTRACK_ENABLED is not set
-# CONFIG_NF_CONNTRACK is not set
-# CONFIG_NETFILTER_XTABLES is not set
-
-#
-# IP: Netfilter Configuration
-#
-# CONFIG_IP_NF_QUEUE is not set
-# CONFIG_IP_NF_IPTABLES is not set
-# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -353,6 +378,7 @@ CONFIG_NETFILTER=y
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
 # CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
 
 #
 # Network testing
@@ -390,20 +416,17 @@ CONFIG_IRTTY_SIR=m
 # Dongle support
 #
 # CONFIG_DONGLE is not set
-
-#
-# Old SIR device drivers
-#
-# CONFIG_IRPORT_SIR is not set
-
-#
-# Old Serial dongle support
-#
+# CONFIG_KINGSUN_DONGLE is not set
+# CONFIG_KSDAZZLE_DONGLE is not set
+# CONFIG_KS959_DONGLE is not set
 
 #
 # FIR device drivers
 #
+# CONFIG_USB_IRDA is not set
+# CONFIG_SIGMATEL_FIR is not set
 CONFIG_PXA_FICP=m
+# CONFIG_MCS_FIR is not set
 CONFIG_BT=m
 CONFIG_BT_L2CAP=m
 CONFIG_BT_SCO=m
@@ -417,17 +440,17 @@ CONFIG_BT_HIDP=m
 #
 # Bluetooth device drivers
 #
+CONFIG_BT_HCIBTUSB=m
+# CONFIG_BT_HCIBTSDIO is not set
 # CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
 # CONFIG_BT_HCIVHCI is not set
 # CONFIG_AF_RXRPC is not set
-
-#
-# Wireless
-#
-# CONFIG_CFG80211 is not set
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
+# CONFIG_PHONET is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
 
@@ -442,25 +465,28 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_DEBUG_DRIVER is not set
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
-CONFIG_MTD_DEBUG=y
-CONFIG_MTD_DEBUG_VERBOSE=0
+# CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_REDBOOT_PARTS is not set
 CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
 #
-CONFIG_MTD_CHAR=m
-CONFIG_MTD_BLKDEVS=m
-CONFIG_MTD_BLOCK=m
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
 # CONFIG_FTL is not set
 # CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
@@ -473,6 +499,7 @@ CONFIG_MTD_BLOCK=m
 #
 CONFIG_MTD_CFI=y
 # CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
 # CONFIG_MTD_CFI_ADV_OPTIONS is not set
 CONFIG_MTD_MAP_BANK_WIDTH_1=y
 CONFIG_MTD_MAP_BANK_WIDTH_2=y
@@ -487,6 +514,7 @@ CONFIG_MTD_CFI_I2=y
 CONFIG_MTD_CFI_INTELEXT=y
 # CONFIG_MTD_CFI_AMDSTD is not set
 # CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
@@ -497,9 +525,7 @@ CONFIG_MTD_CFI_INTELEXT=y
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
 CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0x00000000
-CONFIG_MTD_PHYSMAP_LEN=0x04000000
-CONFIG_MTD_PHYSMAP_BANKWIDTH=4
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
 # CONFIG_MTD_PXA2XX is not set
 # CONFIG_MTD_ARM_INTEGRATOR is not set
 # CONFIG_MTD_SHARP_SL is not set
@@ -523,6 +549,12 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=4
 # CONFIG_MTD_ONENAND is not set
 
 #
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+# CONFIG_MTD_QINFO_PROBE is not set
+
+#
 # UBI - Unsorted block images
 #
 # CONFIG_MTD_UBI is not set
@@ -531,10 +563,12 @@ CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
 # CONFIG_BLK_DEV_RAM is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
 # CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
@@ -547,7 +581,6 @@ CONFIG_BLK_DEV=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -563,6 +596,20 @@ CONFIG_NETDEVICES=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
 # CONFIG_WAN is not set
 CONFIG_PPP=m
 # CONFIG_PPP_MULTILINK is not set
@@ -612,7 +659,26 @@ CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
 CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
 CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
 CONFIG_INPUT_UINPUT=m
 
 #
@@ -625,9 +691,11 @@ CONFIG_INPUT_UINPUT=m
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 # CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_DEVKMEM is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -642,6 +710,7 @@ CONFIG_SERIAL_PXA=y
 # CONFIG_SERIAL_PXA_CONSOLE is not set
 CONFIG_SERIAL_CORE=y
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
@@ -649,37 +718,45 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
-CONFIG_I2C=m
+CONFIG_I2C=y
 CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
 
 #
-# I2C Algorithms
+# I2C Hardware Bus support
 #
-# CONFIG_I2C_ALGOBIT is not set
-# CONFIG_I2C_ALGOPCF is not set
-# CONFIG_I2C_ALGOPCA is not set
 
 #
-# I2C Hardware Bus support
+# I2C system bus drivers (mostly embedded / system-on-chip)
 #
 # CONFIG_I2C_GPIO is not set
-CONFIG_I2C_PXA=m
-# CONFIG_I2C_PXA_SLAVE is not set
 # CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
+CONFIG_I2C_PXA=y
+# CONFIG_I2C_PXA_SLAVE is not set
 # CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
 # CONFIG_I2C_STUB is not set
 
 #
 # Miscellaneous I2C Chip support
 #
-# CONFIG_SENSORS_DS1337 is not set
-# CONFIG_SENSORS_DS1374 is not set
 # CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
 # CONFIG_EEPROM_LEGACY is not set
 # CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_MAX6875 is not set
@@ -688,19 +765,39 @@ CONFIG_I2C_PXA=m
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
 
 #
-# SPI support
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
 #
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
 CONFIG_W1=y
 
 #
 # 1-wire Bus Masters
 #
+# CONFIG_W1_MASTER_DS2490 is not set
 # CONFIG_W1_MASTER_DS2482 is not set
 CONFIG_W1_MASTER_DS1WM=y
+# CONFIG_W1_MASTER_GPIO is not set
 
 #
 # 1-wire Slaves
@@ -709,32 +806,56 @@ CONFIG_W1_MASTER_DS1WM=y
 # CONFIG_W1_SLAVE_SMEM is not set
 # CONFIG_W1_SLAVE_DS2433 is not set
 CONFIG_W1_SLAVE_DS2760=y
+# CONFIG_W1_SLAVE_BQ27000 is not set
 CONFIG_POWER_SUPPLY=y
 # CONFIG_POWER_SUPPLY_DEBUG is not set
 CONFIG_PDA_POWER=y
-# CONFIG_APM_POWER is not set
 CONFIG_BATTERY_DS2760=y
+# CONFIG_BATTERY_BQ27x00 is not set
 # CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
 
 #
 # Sonics Silicon Backplane
 #
-CONFIG_SSB_POSSIBLE=y
 # CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
 CONFIG_HTC_EGPIO=y
 CONFIG_HTC_PASIC3=y
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
 # CONFIG_DAB is not set
 
 #
@@ -745,6 +866,7 @@ CONFIG_HTC_PASIC3=y
 CONFIG_FB=y
 # CONFIG_FIRMWARE_EDID is not set
 # CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
@@ -752,8 +874,8 @@ CONFIG_FB_CFB_IMAGEBLIT=y
 # CONFIG_FB_SYS_FILLRECT is not set
 # CONFIG_FB_SYS_COPYAREA is not set
 # CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
 # CONFIG_FB_SYS_FOPS is not set
-CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -765,13 +887,21 @@ CONFIG_FB_DEFERRED_IO=y
 #
 # CONFIG_FB_S1D13XXX is not set
 CONFIG_FB_PXA=y
+CONFIG_FB_PXA_OVERLAY=y
+# CONFIG_FB_PXA_SMARTPANEL is not set
 # CONFIG_FB_PXA_PARAMETERS is not set
 # CONFIG_FB_MBX is not set
+# CONFIG_FB_W100 is not set
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_PLATFORM is not set
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_CORGI=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
 
 #
 # Display device support
@@ -802,15 +932,8 @@ CONFIG_FONT_MINI_4x6=y
 # CONFIG_FONT_SUN12x22 is not set
 # CONFIG_FONT_10x18 is not set
 # CONFIG_LOGO is not set
-
-#
-# Sound
-#
 CONFIG_SOUND=y
-
-#
-# Advanced Linux Sound Architecture
-#
+CONFIG_SOUND_OSS_CORE=y
 CONFIG_SND=m
 CONFIG_SND_TIMER=m
 CONFIG_SND_PCM=m
@@ -824,53 +947,185 @@ CONFIG_SND_SUPPORT_OLD_API=y
 CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
+CONFIG_SND_DRIVERS=y
 # CONFIG_SND_DUMMY is not set
 # CONFIG_SND_MTPAV is not set
 # CONFIG_SND_SERIAL_U16550 is not set
 # CONFIG_SND_MPU401 is not set
-
-#
-# ALSA ARM devices
-#
-# CONFIG_SND_PXA2XX_AC97 is not set
-
-#
-# System on Chip audio support
-#
+# CONFIG_SND_ARM is not set
+CONFIG_SND_PXA2XX_LIB=m
+# CONFIG_SND_USB is not set
 CONFIG_SND_SOC=m
 CONFIG_SND_PXA2XX_SOC=m
-
-#
-# SoC Audio support for SuperH
-#
-
-#
-# Open Sound System
-#
+CONFIG_SND_SOC_I2C_AND_SPI=m
+# CONFIG_SND_SOC_ALL_CODECS is not set
 # CONFIG_SOUND_PRIME is not set
 # CONFIG_HID_SUPPORT is not set
 CONFIG_HID=m
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=m
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+#
+
+#
+# see USB_STORAGE Help for more information
+#
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=500
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+CONFIG_USB_GADGET_PXA27X=y
+CONFIG_USB_PXA27X=y
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=m
+# CONFIG_USB_ETH_RNDIS is not set
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+CONFIG_USB_CDC_COMPOSITE=m
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+CONFIG_USB_GPIO_VBUS=y
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
 
 #
-# MMC/SD Card Drivers
+# MMC/SD/SDIO Card Drivers
 #
 CONFIG_MMC_BLOCK=y
 CONFIG_MMC_BLOCK_BOUNCE=y
 CONFIG_SDIO_UART=m
+# CONFIG_MMC_TEST is not set
 
 #
-# MMC/SD Host Controller Drivers
+# MMC/SD/SDIO Host Controller Drivers
 #
 CONFIG_MMC_PXA=y
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
 CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_PCA955X is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -899,6 +1154,9 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_PCF8563 is not set
 # CONFIG_RTC_DRV_PCF8583 is not set
 # CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
 
 #
 # SPI RTC drivers
@@ -908,17 +1166,26 @@ CONFIG_RTC_INTF_DEV=y
 # Platform RTC drivers
 #
 # CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
 #
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_SA1100=y
+# CONFIG_RTC_DRV_PXA is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
 
 #
 # File systems
@@ -927,19 +1194,18 @@ CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -965,15 +1231,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -997,9 +1261,13 @@ CONFIG_JFFS2_CMODE_PRIORITY=y
 # CONFIG_JFFS2_CMODE_SIZE is not set
 # CONFIG_JFFS2_CMODE_FAVOURLZO is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
@@ -1007,14 +1275,13 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-# CONFIG_NFSD is not set
 CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -1076,6 +1343,7 @@ CONFIG_NLS_UTF8=y
 CONFIG_PRINTK_TIME=y
 CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
@@ -1083,15 +1351,18 @@ CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
 CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_SCHEDSTATS is not set
 CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_DEBUG_SLAB is not set
-CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_PREEMPT is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
-CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_MUTEXES is not set
 # CONFIG_DEBUG_LOCK_ALLOC is not set
 # CONFIG_PROVE_LOCKING is not set
 # CONFIG_LOCK_STAT is not set
@@ -1100,17 +1371,41 @@ CONFIG_DEBUG_MUTEXES=y
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
-CONFIG_DEBUG_VM=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
 CONFIG_FRAME_POINTER=y
-CONFIG_FORCED_INLINING=y
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
 # CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
 # CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
 
@@ -1119,55 +1414,110 @@ CONFIG_DEBUG_LL=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
 CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_ALGAPI2=m
+CONFIG_CRYPTO_AEAD2=m
 CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_BLKCIPHER2=m
+CONFIG_CRYPTO_HASH=m
+CONFIG_CRYPTO_HASH2=m
+CONFIG_CRYPTO_RNG2=m
 CONFIG_CRYPTO_MANAGER=m
+CONFIG_CRYPTO_MANAGER2=m
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
 # CONFIG_CRYPTO_HMAC is not set
 # CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
 # CONFIG_CRYPTO_MD4 is not set
 # CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
 CONFIG_CRYPTO_SHA1=m
 # CONFIG_CRYPTO_SHA256 is not set
 # CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
 # CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-CONFIG_CRYPTO_ECB=m
-# CONFIG_CRYPTO_CBC is not set
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_XTS is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
 # CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_CAST5 is not set
 # CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SALSA20 is not set
 # CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
 # CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
-# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
 # CONFIG_CRYPTO_HW is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=y
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig
index 83c817f31bcc..b0698722e0cb 100644
--- a/arch/arm/configs/mv78xx0_defconfig
+++ b/arch/arm/configs/mv78xx0_defconfig
@@ -165,6 +165,7 @@ CONFIG_ARCH_MV78XX0=y
 # Marvell MV78xx0 Implementations
 #
 CONFIG_MACH_DB78X00_BP=y
+CONFIG_MACH_RD78X00_MASA=y
 
 #
 # Boot options
diff --git a/arch/arm/configs/neponset_defconfig b/arch/arm/configs/neponset_defconfig
index d81ea219c934..36cd62edd05c 100644
--- a/arch/arm/configs/neponset_defconfig
+++ b/arch/arm/configs/neponset_defconfig
@@ -91,7 +91,6 @@ CONFIG_ASSABET_NEPONSET=y
 # CONFIG_SA1100_COLLIE is not set
 # CONFIG_SA1100_H3100 is not set
 # CONFIG_SA1100_H3600 is not set
-# CONFIG_SA1100_H3800 is not set
 # CONFIG_SA1100_BADGE4 is not set
 # CONFIG_SA1100_JORNADA720 is not set
 # CONFIG_SA1100_HACKKIT is not set
diff --git a/arch/arm/configs/omap_3430sdp_defconfig b/arch/arm/configs/omap_3430sdp_defconfig
new file mode 100644
index 000000000000..8fb918d9ba65
--- /dev/null
+++ b/arch/arm/configs/omap_3430sdp_defconfig
@@ -0,0 +1,2061 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.29-rc8
+# Fri Mar 13 14:17:01 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_OPROFILE_ARMV7=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_TRACEPOINTS=y
+# CONFIG_MARKERS is not set
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
+
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+# CONFIG_ARCH_OMAP1 is not set
+# CONFIG_ARCH_OMAP2 is not set
+CONFIG_ARCH_OMAP3=y
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
+# CONFIG_OMAP_RESET_CLOCKS is not set
+CONFIG_OMAP_MUX=y
+CONFIG_OMAP_MUX_DEBUG=y
+CONFIG_OMAP_MUX_WARNINGS=y
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_DM_TIMER=y
+# CONFIG_OMAP_LL_DEBUG_UART1 is not set
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+CONFIG_OMAP_LL_DEBUG_UART3=y
+CONFIG_OMAP_SERIAL_WAKE=y
+CONFIG_ARCH_OMAP34XX=y
+CONFIG_ARCH_OMAP3430=y
+
+#
+# OMAP Board Type
+#
+CONFIG_MACH_OMAP3_BEAGLE=y
+CONFIG_MACH_OMAP_LDP=y
+CONFIG_MACH_OVERO=y
+CONFIG_MACH_OMAP3_PANDORA=y
+CONFIG_MACH_OMAP_3430SDP=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_IFAR=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=128
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_LEDS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttyS2,115200 root=/dev/mmcblk0p3 rootwait debug"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_HAVE_AOUT=y
+CONFIG_BINFMT_AOUT=m
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_COMPAT_NET_DEV_OPS=y
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+# CONFIG_BT_HCIBTUSB is not set
+# CONFIG_BT_HCIBTSDIO is not set
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_BCSP=y
+# CONFIG_BT_HCIUART_LL is not set
+CONFIG_BT_HCIBCM203X=y
+CONFIG_BT_HCIBPA10X=y
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
+CONFIG_CFG80211=y
+# CONFIG_CFG80211_REG_DEBUG is not set
+CONFIG_NL80211=y
+CONFIG_WIRELESS_OLD_REGULATORY=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=y
+CONFIG_LIB80211_CRYPT_WEP=m
+CONFIG_LIB80211_CRYPT_CCMP=m
+CONFIG_LIB80211_CRYPT_TKIP=m
+CONFIG_MAC80211=y
+
+#
+# Rate control algorithm selection
+#
+CONFIG_MAC80211_RC_PID=y
+# CONFIG_MAC80211_RC_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT="pid"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+CONFIG_EEPROM_93CX6=m
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID456=m
+CONFIG_MD_RAID5_RESHAPE=y
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_FAULTY=m
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_DELAY=m
+# CONFIG_DM_UEVENT is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=m
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+CONFIG_SMSC_PHY=y
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+CONFIG_SMC911X=m
+CONFIG_SMSC911X=m
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+CONFIG_LIBERTAS=y
+CONFIG_LIBERTAS_USB=y
+CONFIG_LIBERTAS_SDIO=y
+CONFIG_LIBERTAS_DEBUG=y
+# CONFIG_LIBERTAS_THINFIRM is not set
+CONFIG_USB_ZD1201=m
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+CONFIG_RTL8187=m
+# CONFIG_MAC80211_HWSIM is not set
+CONFIG_P54_COMMON=m
+CONFIG_P54_USB=m
+# CONFIG_IWLWIFI_LEDS is not set
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_ZD1211RW is not set
+# CONFIG_RT2X00 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_AX8817X=y
+CONFIG_USB_NET_CDCETHER=y
+CONFIG_USB_NET_DM9601=m
+# CONFIG_USB_NET_SMSC95XX is not set
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_GPIO is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_OMAP24XX=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+CONFIG_GPIO_TWL4030=y
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=m
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_OMAP_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+CONFIG_TWL4030_CORE=y
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+CONFIG_DVB_CORE=m
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+CONFIG_MEDIA_ATTACH=y
+CONFIG_MEDIA_TUNER=m
+# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L1=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_WM8775=m
+CONFIG_VIDEO_SAA711X=m
+CONFIG_VIDEO_CX25840=m
+CONFIG_VIDEO_CX2341X=m
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_VIDEO_AU0828 is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+# CONFIG_USB_GSPCA is not set
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+CONFIG_VIDEO_PVRUSB2_DVB=y
+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
+# CONFIG_VIDEO_EM28XX is not set
+CONFIG_VIDEO_USBVISION=m
+CONFIG_VIDEO_USBVIDEO=m
+CONFIG_USB_VICAM=m
+CONFIG_USB_IBMCAM=m
+CONFIG_USB_KONICAWC=m
+CONFIG_USB_QUICKCAM_MESSENGER=m
+# CONFIG_USB_ET61X251 is not set
+CONFIG_VIDEO_OVCAMCHIP=m
+CONFIG_USB_W9968CF=m
+CONFIG_USB_OV511=m
+CONFIG_USB_SE401=m
+CONFIG_USB_SN9C102=m
+CONFIG_USB_STV680=m
+# CONFIG_USB_ZC0301 is not set
+CONFIG_USB_PWC=m
+# CONFIG_USB_PWC_DEBUG is not set
+CONFIG_USB_ZR364XX=m
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_USB_DSBR is not set
+# CONFIG_USB_SI470X is not set
+# CONFIG_USB_MR800 is not set
+# CONFIG_RADIO_TEA5764 is not set
+# CONFIG_DVB_DYNAMIC_MINORS is not set
+CONFIG_DVB_CAPTURE_DRIVERS=y
+# CONFIG_TTPCI_EEPROM is not set
+
+#
+# Supported USB Adapters
+#
+CONFIG_DVB_USB=m
+# CONFIG_DVB_USB_DEBUG is not set
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_DIBUSB_MB=m
+# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_CXUSB=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+# CONFIG_DVB_USB_DW2102 is not set
+# CONFIG_DVB_USB_CINERGY_T2 is not set
+# CONFIG_DVB_USB_ANYSEE is not set
+# CONFIG_DVB_USB_DTV5100 is not set
+# CONFIG_DVB_USB_AF9015 is not set
+# CONFIG_DVB_SIANO_SMS1XXX is not set
+
+#
+# Supported FlexCopII (B2C2) Adapters
+#
+# CONFIG_DVB_B2C2_FLEXCOP is not set
+
+#
+# Supported DVB Frontends
+#
+
+#
+# Customise DVB Frontends
+#
+# CONFIG_DVB_FE_CUSTOMISE is not set
+
+#
+# Multistandard (satellite) frontends
+#
+# CONFIG_DVB_STB0899 is not set
+# CONFIG_DVB_STB6100 is not set
+
+#
+# DVB-S (satellite) frontends
+#
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_S5H1420=m
+# CONFIG_DVB_STV0288 is not set
+# CONFIG_DVB_STB6000 is not set
+CONFIG_DVB_STV0299=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA10086=m
+# CONFIG_DVB_TDA8261 is not set
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_TUNER_ITD1000=m
+# CONFIG_DVB_TUNER_CX24113 is not set
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TUA6100=m
+# CONFIG_DVB_CX24116 is not set
+# CONFIG_DVB_SI21XX is not set
+
+#
+# DVB-T (terrestrial) frontends
+#
+CONFIG_DVB_SP8870=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+# CONFIG_DVB_DRX397XD is not set
+CONFIG_DVB_L64781=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_TDA10048=m
+
+#
+# DVB-C (cable) frontends
+#
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_STV0297=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+CONFIG_DVB_NXT200X=m
+# CONFIG_DVB_OR51211 is not set
+# CONFIG_DVB_OR51132 is not set
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LGDT330X=m
+# CONFIG_DVB_LGDT3304 is not set
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_S5H1411=m
+
+#
+# ISDB-T (terrestrial) frontends
+#
+# CONFIG_DVB_S921 is not set
+
+#
+# Digital terrestrial only tuners/PLL
+#
+CONFIG_DVB_PLL=m
+CONFIG_DVB_TUNER_DIB0070=m
+
+#
+# SEC control devices for DVB-S
+#
+CONFIG_DVB_LNBP21=m
+# CONFIG_DVB_ISL6405 is not set
+CONFIG_DVB_ISL6421=m
+# CONFIG_DVB_LGS8GL5 is not set
+
+#
+# Tools to develop new frontends
+#
+# CONFIG_DVB_DUMMY_FE is not set
+# CONFIG_DVB_AF9013 is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=y
+CONFIG_SND_RAWMIDI=y
+CONFIG_SND_SEQUENCER=m
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_DEBUG=y
+# CONFIG_SND_DEBUG_VERBOSE is not set
+# CONFIG_SND_PCM_XRUN_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
+CONFIG_SND_SOC=y
+CONFIG_SND_OMAP_SOC=y
+CONFIG_SND_OMAP_SOC_MCBSP=y
+# CONFIG_SND_OMAP_SOC_OVERO is not set
+CONFIG_SND_OMAP_SOC_SDP3430=y
+CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_TWL4030=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_LOGITECH=y
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+# CONFIG_HID_NTRIG is not set
+CONFIG_HID_PANTHERLORD=y
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+# CONFIG_GREENASIA_FF is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_OTG=y
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SOC=y
+
+#
+# OMAP 343x high speed USB support
+#
+# CONFIG_USB_MUSB_HOST is not set
+# CONFIG_USB_MUSB_PERIPHERAL is not set
+CONFIG_USB_MUSB_OTG=y
+CONFIG_USB_GADGET_MUSB_HDRC=y
+CONFIG_USB_MUSB_HDRC_HCD=y
+CONFIG_MUSB_PIO_ONLY=y
+# CONFIG_USB_MUSB_DEBUG is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+CONFIG_USB_PRINTER=y
+CONFIG_USB_WDM=y
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+#
+
+#
+# see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_ISP1301_OMAP is not set
+CONFIG_TWL4030_USB=y
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_OMAP is not set
+CONFIG_MMC_OMAP_HS=y
+# CONFIG_MMC_SPI is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_PCA955X is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+CONFIG_RTC_DRV_TWL4030=y
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+CONFIG_XFS_FS=m
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+CONFIG_QUOTA_TREE=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_NOP_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_RING_BUFFER=y
+CONFIG_TRACING=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_CRYPTD=m
+# CONFIG_CRYPTO_AUTHENC is not set
+CONFIG_CRYPTO_TEST=m
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_XCBC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=m
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig
index a8ee6984a09e..020e6a8a9e5c 100644
--- a/arch/arm/configs/orion5x_defconfig
+++ b/arch/arm/configs/orion5x_defconfig
@@ -481,7 +481,7 @@ CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_CAFE is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
-# CONFIG_MTD_NAND_PLATFORM is not set
+CONFIG_MTD_NAND_PLATFORM=y
 # CONFIG_MTD_ALAUDA is not set
 CONFIG_MTD_NAND_ORION=y
 # CONFIG_MTD_ONENAND is not set
@@ -1177,7 +1177,7 @@ CONFIG_RTC_DRV_S35390A=y
 # CONFIG_RTC_DRV_DS1553 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
 # CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
+CONFIG_RTC_DRV_M48T86=y
 # CONFIG_RTC_DRV_M48T59 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
diff --git a/arch/arm/configs/pleb_defconfig b/arch/arm/configs/pleb_defconfig
index a6b47ea8e465..f2d2dda25949 100644
--- a/arch/arm/configs/pleb_defconfig
+++ b/arch/arm/configs/pleb_defconfig
@@ -88,7 +88,6 @@ CONFIG_ARCH_SA1100=y
 # CONFIG_SA1100_COLLIE is not set
 # CONFIG_SA1100_H3100 is not set
 # CONFIG_SA1100_H3600 is not set
-# CONFIG_SA1100_H3800 is not set
 # CONFIG_SA1100_BADGE4 is not set
 # CONFIG_SA1100_JORNADA720 is not set
 # CONFIG_SA1100_HACKKIT is not set
diff --git a/arch/arm/configs/pxa168_defconfig b/arch/arm/configs/pxa168_defconfig
new file mode 100644
index 000000000000..db5faeaec96c
--- /dev/null
+++ b/arch/arm/configs/pxa168_defconfig
@@ -0,0 +1,891 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.29-rc3
+# Fri Mar 20 13:43:13 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+CONFIG_ARCH_MMP=y
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_MACH_TAVOREVB is not set
+
+#
+# Marvell PXA168/910 Implmentations
+#
+CONFIG_MACH_ASPENITE=y
+CONFIG_MACH_ZYLONITE2=y
+# CONFIG_MACH_TTC_DKB is not set
+CONFIG_CPU_PXA168=y
+CONFIG_PLAT_PXA=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_MOHAWK=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+CONFIG_IWMMXT=y
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.2.100:/nfsroot/ ip=192.168.2.101:192.168.2.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=128M"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_COMPAT_NET_DEV_OPS=y
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_LIB80211 is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+# CONFIG_BLK_DEV is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_PXA=y
+CONFIG_SERIAL_PXA_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+CONFIG_GENERIC_ACL=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/pxa910_defconfig b/arch/arm/configs/pxa910_defconfig
new file mode 100644
index 000000000000..8c7e299f1d66
--- /dev/null
+++ b/arch/arm/configs/pxa910_defconfig
@@ -0,0 +1,891 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.29-rc3
+# Fri Mar 20 13:45:12 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+CONFIG_ARCH_MMP=y
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
+CONFIG_MACH_TAVOREVB=y
+
+#
+# Marvell PXA168/910 Implmentations
+#
+# CONFIG_MACH_ASPENITE is not set
+# CONFIG_MACH_ZYLONITE2 is not set
+CONFIG_MACH_TTC_DKB=y
+CONFIG_CPU_PXA910=y
+CONFIG_PLAT_PXA=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_MOHAWK=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+CONFIG_IWMMXT=y
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.2.100:/nfsroot/ ip=192.168.2.101:192.168.2.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=128M"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_COMPAT_NET_DEV_OPS=y
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_LIB80211 is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+# CONFIG_BLK_DEV is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_PXA=y
+CONFIG_SERIAL_PXA_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+CONFIG_GENERIC_ACL=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/rx51_defconfig b/arch/arm/configs/rx51_defconfig
new file mode 100644
index 000000000000..593102da8cd7
--- /dev/null
+++ b/arch/arm/configs/rx51_defconfig
@@ -0,0 +1,1821 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.29-rc8
+# Fri Mar 13 15:28:56 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_KRETPROBES=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
+
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+# CONFIG_ARCH_OMAP1 is not set
+# CONFIG_ARCH_OMAP2 is not set
+CONFIG_ARCH_OMAP3=y
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
+CONFIG_OMAP_RESET_CLOCKS=y
+CONFIG_OMAP_MUX=y
+CONFIG_OMAP_MUX_DEBUG=y
+CONFIG_OMAP_MUX_WARNINGS=y
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_DM_TIMER=y
+# CONFIG_OMAP_LL_DEBUG_UART1 is not set
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+CONFIG_OMAP_LL_DEBUG_UART3=y
+CONFIG_OMAP_SERIAL_WAKE=y
+CONFIG_ARCH_OMAP34XX=y
+CONFIG_ARCH_OMAP3430=y
+
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_OMAP3_BEAGLE is not set
+# CONFIG_MACH_OMAP_LDP is not set
+# CONFIG_MACH_OVERO is not set
+# CONFIG_MACH_OMAP3_PANDORA is not set
+# CONFIG_MACH_OMAP_3430SDP is not set
+CONFIG_MACH_NOKIA_RX51=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_IFAR=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=128
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs rw console=ttyMTD5"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_FREQ is not set
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+CONFIG_PM=y
+CONFIG_PM_DEBUG=y
+# CONFIG_PM_VERBOSE is not set
+CONFIG_CAN_PM_TRACE=y
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_COMPAT_NET_DEV_OPS=y
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETLABEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+CONFIG_NETFILTER_XTABLES=m
+# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
+# CONFIG_NETFILTER_XT_TARGET_MARK is not set
+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
+# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
+# CONFIG_NETFILTER_XT_MATCH_ESP is not set
+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
+# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_MAC is not set
+# CONFIG_NETFILTER_XT_MATCH_MARK is not set
+# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+# CONFIG_NETFILTER_XT_MATCH_REALM is not set
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
+# CONFIG_NETFILTER_XT_MATCH_STRING is not set
+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+CONFIG_IP_NF_IPTABLES=m
+# CONFIG_IP_NF_MATCH_ADDRTYPE is not set
+# CONFIG_IP_NF_MATCH_AH is not set
+# CONFIG_IP_NF_MATCH_ECN is not set
+# CONFIG_IP_NF_MATCH_TTL is not set
+CONFIG_IP_NF_FILTER=m
+# CONFIG_IP_NF_TARGET_REJECT is not set
+# CONFIG_IP_NF_TARGET_LOG is not set
+# CONFIG_IP_NF_TARGET_ULOG is not set
+# CONFIG_IP_NF_MANGLE is not set
+# CONFIG_IP_NF_RAW is not set
+# CONFIG_IP_NF_SECURITY is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_TCPPROBE is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+# CONFIG_BT_HCIBTUSB is not set
+# CONFIG_BT_HCIBTSDIO is not set
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
+CONFIG_CFG80211=y
+# CONFIG_CFG80211_REG_DEBUG is not set
+CONFIG_NL80211=y
+CONFIG_WIRELESS_OLD_REGULATORY=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_LIB80211 is not set
+CONFIG_MAC80211=m
+
+#
+# Rate control algorithm selection
+#
+CONFIG_MAC80211_RC_PID=y
+# CONFIG_MAC80211_RC_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT="pid"
+# CONFIG_MAC80211_MESH is not set
+# CONFIG_MAC80211_LEDS is not set
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+CONFIG_MTD_OOPS=y
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_OMAP_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+CONFIG_MTD_ONENAND=y
+# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
+# CONFIG_MTD_ONENAND_GENERIC is not set
+CONFIG_MTD_ONENAND_OMAP2=y
+# CONFIG_MTD_ONENAND_OTP is not set
+# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
+# CONFIG_MTD_ONENAND_SIM is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=m
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=m
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_LIBERTAS is not set
+# CONFIG_LIBERTAS_THINFIRM is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_P54_COMMON is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_ZD1211RW is not set
+# CONFIG_RT2X00 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=m
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_OMAP24XX=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+CONFIG_GPIO_TWL4030=y
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_OMAP_WATCHDOG=m
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+CONFIG_TWL4030_CORE=y
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=m
+# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L1=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+# CONFIG_USB_VIDEO_CLASS is not set
+# CONFIG_USB_GSPCA is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_VICAM is not set
+# CONFIG_USB_IBMCAM is not set
+# CONFIG_USB_KONICAWC is not set
+# CONFIG_USB_QUICKCAM_MESSENGER is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_VIDEO_OVCAMCHIP is not set
+# CONFIG_USB_OV511 is not set
+# CONFIG_USB_SE401 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_STV680 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_USB_DSBR is not set
+# CONFIG_USB_SI470X is not set
+# CONFIG_USB_MR800 is not set
+# CONFIG_RADIO_TEA5764 is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_SPI=y
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_OMAP_SOC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=m
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=m
+CONFIG_HID_APPLE=m
+CONFIG_HID_BELKIN=m
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+CONFIG_HID_CYPRESS=m
+CONFIG_HID_EZKEY=m
+CONFIG_HID_GYRATION=m
+CONFIG_HID_LOGITECH=m
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=m
+CONFIG_HID_MONTEREY=m
+# CONFIG_HID_NTRIG is not set
+CONFIG_HID_PANTHERLORD=m
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=m
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SONY=m
+CONFIG_HID_SUNPLUS=m
+# CONFIG_GREENASIA_FF is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_OTG=y
+CONFIG_USB_OTG_WHITELIST=y
+CONFIG_USB_OTG_BLACKLIST_HUB=y
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SOC=y
+
+#
+# OMAP 343x high speed USB support
+#
+# CONFIG_USB_MUSB_HOST is not set
+# CONFIG_USB_MUSB_PERIPHERAL is not set
+CONFIG_USB_MUSB_OTG=y
+CONFIG_USB_GADGET_MUSB_HDRC=y
+CONFIG_USB_MUSB_HDRC_HCD=y
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_USB_INVENTRA_DMA=y
+# CONFIG_USB_TI_CPPI_DMA is not set
+# CONFIG_USB_MUSB_DEBUG is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+#
+
+#
+# see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+CONFIG_USB_TEST=m
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=m
+CONFIG_USB_GADGET_DEBUG=y
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_DEBUG_FS=y
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_ZERO=m
+# CONFIG_USB_ZERO_HNPTEST is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_ISP1301_OMAP is not set
+CONFIG_TWL4030_USB=y
+CONFIG_MMC=m
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=m
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_OMAP is not set
+CONFIG_MMC_OMAP_HS=m
+# CONFIG_MMC_SPI is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=m
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_GPIO is not set
+# CONFIG_LEDS_PCA955X is not set
+
+#
+# LED Triggers
+#
+# CONFIG_LEDS_TRIGGERS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=m
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+CONFIG_RTC_DRV_TWL4030=m
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=m
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=m
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=m
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+CONFIG_QUOTA_TREE=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_XATTR is not set
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=m
+CONFIG_SUNRPC_GSS=m
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+CONFIG_RPCSEC_GSS_KRB5=m
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_DEBUG_LOCK_ALLOC=y
+CONFIG_PROVE_LOCKING=y
+CONFIG_LOCKDEP=y
+CONFIG_LOCK_STAT=y
+# CONFIG_DEBUG_LOCKDEP is not set
+CONFIG_TRACE_IRQFLAGS=y
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_KPROBES_SANITY_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+CONFIG_SECURITY=y
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_NETWORK is not set
+# CONFIG_SECURITY_PATH is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_SECURITY_ROOTPLUG is not set
+CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/shannon_defconfig b/arch/arm/configs/shannon_defconfig
index d052c8f80515..984f7096a533 100644
--- a/arch/arm/configs/shannon_defconfig
+++ b/arch/arm/configs/shannon_defconfig
@@ -87,7 +87,6 @@ CONFIG_ARCH_SA1100=y
 # CONFIG_SA1100_COLLIE is not set
 # CONFIG_SA1100_H3100 is not set
 # CONFIG_SA1100_H3600 is not set
-# CONFIG_SA1100_H3800 is not set
 # CONFIG_SA1100_BADGE4 is not set
 # CONFIG_SA1100_JORNADA720 is not set
 # CONFIG_SA1100_HACKKIT is not set
diff --git a/arch/arm/configs/shark_defconfig b/arch/arm/configs/shark_defconfig
index 9b6561d119af..90235bf7a1de 100644
--- a/arch/arm/configs/shark_defconfig
+++ b/arch/arm/configs/shark_defconfig
@@ -1,88 +1,174 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-git3
-# Sat Jul 16 15:21:47 2005
+# Linux kernel version: 2.6.28-git6
+# Thu Jan  8 17:14:47 2009
 #
 CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+# CONFIG_GENERIC_GPIO is not set
+# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
 CONFIG_MMU=y
-CONFIG_UID16=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
+# CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
-# CONFIG_HOTPLUG is not set
-CONFIG_KOBJECT_UEVENT=y
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_FREEZER is not set
 
 #
 # System Type
 #
-# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
 # CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_IOP3XX is not set
-# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
 # CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
 CONFIG_ARCH_SHARK=y
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
 
 #
 # Processor Type
@@ -91,14 +177,20 @@ CONFIG_CPU_32=y
 CONFIG_CPU_SA110=y
 CONFIG_CPU_32v4=y
 CONFIG_CPU_ABRT_EV4=y
+CONFIG_CPU_PABRT_NOIFAR=y
 CONFIG_CPU_CACHE_V4WB=y
 CONFIG_CPU_CACHE_VIVT=y
 CONFIG_CPU_COPY_V4WB=y
 CONFIG_CPU_TLB_V4WB=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
 
 #
 # Processor Features
 #
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
 
 #
 # Bus support
@@ -107,22 +199,40 @@ CONFIG_ISA=y
 CONFIG_ISA_DMA=y
 CONFIG_ISA_DMA_API=y
 CONFIG_PCI=y
+CONFIG_PCI_SYSCALL=y
 CONFIG_PCI_HOST_VIA82C505=y
-CONFIG_PCI_LEGACY_PROC=y
-# CONFIG_PCI_NAMES is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
 # CONFIG_PCI_DEBUG is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
 # CONFIG_PCCARD is not set
 
 #
 # Kernel Features
 #
-# CONFIG_SMP is not set
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
 # CONFIG_PREEMPT is not set
-# CONFIG_DISCONTIGMEM is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
 CONFIG_LEDS=y
 CONFIG_LEDS_TIMER=y
 # CONFIG_LEDS_CPU is not set
@@ -135,6 +245,12 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE=""
 # CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
 
 #
 # Floating point emulation
@@ -143,13 +259,16 @@ CONFIG_CMDLINE=""
 #
 # At least one emulation must be selected
 #
-# CONFIG_FPE_NWFPE is not set
-CONFIG_FPE_FASTFPE=y
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
 
 #
 # Userspace binary formats
 #
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
 # CONFIG_BINFMT_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 # CONFIG_ARTHUR is not set
@@ -158,44 +277,104 @@ CONFIG_BINFMT_ELF=y
 # Power management options
 #
 # CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
 
 #
-# Device Drivers
+# Networking options
 #
+# CONFIG_NET_NS is not set
+CONFIG_COMPAT_NET_DEV_OPS=y
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
 
 #
-# Generic Driver Options
+# Network testing
 #
-# CONFIG_STANDALONE is not set
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
-# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
-# Memory Technology Devices (MTD)
+# Device Drivers
 #
-# CONFIG_MTD is not set
 
 #
-# Parallel port support
+# Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_STANDALONE is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
 CONFIG_PARPORT=m
 CONFIG_PARPORT_PC=m
 # CONFIG_PARPORT_SERIAL is not set
 # CONFIG_PARPORT_PC_FIFO is not set
 # CONFIG_PARPORT_PC_SUPERIO is not set
-# CONFIG_PARPORT_ARC is not set
 # CONFIG_PARPORT_GSC is not set
+# CONFIG_PARPORT_AX88796 is not set
 # CONFIG_PARPORT_1284 is not set
-
-#
-# Plug and Play support
-#
 # CONFIG_PNP is not set
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_XD is not set
 # CONFIG_PARIDE is not set
 # CONFIG_BLK_CPQ_DA is not set
@@ -210,52 +389,78 @@ CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
 # CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_C2PORT is not set
+CONFIG_HAVE_IDE=y
 CONFIG_IDE=y
-CONFIG_BLK_DEV_IDE=y
 
 #
-# Please see Documentation/ide.txt for help/info on IDE drives
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
+CONFIG_IDE_ATAPI=y
 # CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
-# CONFIG_IDEDISK_MULTI_MODE is not set
+CONFIG_IDE_GD=y
+CONFIG_IDE_GD_ATA=y
+# CONFIG_IDE_GD_ATAPI is not set
 CONFIG_BLK_DEV_IDECD=m
+CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
 # CONFIG_BLK_DEV_IDETAPE is not set
-CONFIG_BLK_DEV_IDEFLOPPY=y
-# CONFIG_BLK_DEV_IDESCSI is not set
 # CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
 
 #
 # IDE chipset support/bugfixes
 #
-CONFIG_IDE_GENERIC=y
-# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+
+#
+# PCI IDE chipsets support
+#
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_JMICRON is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT8213 is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SL82C105 is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
 CONFIG_IDE_ARM=y
-# CONFIG_IDE_CHIPSETS is not set
 # CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_IDEDMA_AUTO is not set
-# CONFIG_BLK_DEV_HD is not set
 
 #
 # SCSI device support
 #
+# CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
 CONFIG_SCSI_PROC_FS=y
 
 #
@@ -275,17 +480,20 @@ CONFIG_CHR_DEV_SG=m
 # CONFIG_SCSI_MULTI_LUN is not set
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 
 #
-# SCSI Transport Attributes
+# SCSI Transports
 #
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_CXGB3_ISCSI is not set
 # CONFIG_BLK_DEV_3W_XXXX_RAID is not set
 # CONFIG_SCSI_3W_9XXX is not set
 # CONFIG_SCSI_7000FASST is not set
@@ -296,12 +504,18 @@ CONFIG_CHR_DEV_SG=m
 # CONFIG_SCSI_AIC7XXX is not set
 # CONFIG_SCSI_AIC7XXX_OLD is not set
 # CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
 # CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
 # CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_ARCMSR is not set
 # CONFIG_MEGARAID_NEWGEN is not set
 # CONFIG_MEGARAID_LEGACY is not set
-# CONFIG_SCSI_SATA is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
 # CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_LIBFC is not set
+# CONFIG_FCOE is not set
 # CONFIG_SCSI_DMX3191D is not set
 # CONFIG_SCSI_DTC3280 is not set
 # CONFIG_SCSI_EATA is not set
@@ -314,20 +528,15 @@ CONFIG_CHR_DEV_SG=m
 # CONFIG_SCSI_INIA100 is not set
 # CONFIG_SCSI_PPA is not set
 # CONFIG_SCSI_IMM is not set
+# CONFIG_SCSI_MVSAS is not set
 # CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_STEX is not set
 # CONFIG_SCSI_SYM53C8XX_2 is not set
-# CONFIG_SCSI_IPR is not set
 # CONFIG_SCSI_PAS16 is not set
-# CONFIG_SCSI_PSI240I is not set
 # CONFIG_SCSI_QLOGIC_FAS is not set
-# CONFIG_SCSI_QLOGIC_FC is not set
 # CONFIG_SCSI_QLOGIC_1280 is not set
-CONFIG_SCSI_QLA2XXX=m
-# CONFIG_SCSI_QLA21XX is not set
-# CONFIG_SCSI_QLA22XX is not set
-# CONFIG_SCSI_QLA2300 is not set
-# CONFIG_SCSI_QLA2322 is not set
-# CONFIG_SCSI_QLA6312 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
 # CONFIG_SCSI_LPFC is not set
 # CONFIG_SCSI_SYM53C416 is not set
 # CONFIG_SCSI_DC395x is not set
@@ -336,123 +545,57 @@ CONFIG_SCSI_QLA2XXX=m
 # CONFIG_SCSI_U14_34F is not set
 # CONFIG_SCSI_NSP32 is not set
 # CONFIG_SCSI_DEBUG is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
+# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
 # CONFIG_FUSION is not set
-# CONFIG_FUSION_SPI is not set
-# CONFIG_FUSION_FC is not set
 
 #
 # IEEE 1394 (FireWire) support
 #
-# CONFIG_IEEE1394 is not set
 
 #
-# I2O device support
+# Enable only one of the two stacks, unless you know what you are doing
 #
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
 # CONFIG_I2O is not set
-
-#
-# Networking support
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_IP_TCPDIAG=y
-# CONFIG_IP_TCPDIAG_IPV6 is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETFILTER is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-# CONFIG_NET_CLS_ROUTE is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
 CONFIG_NETDEVICES=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# ARCnet devices
-#
+# CONFIG_VETH is not set
 # CONFIG_ARCNET is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
+# CONFIG_PHYLIB is not set
 CONFIG_NET_ETHERNET=y
 # CONFIG_MII is not set
+# CONFIG_AX88796 is not set
 # CONFIG_HAPPYMEAL is not set
 # CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_LANCE is not set
 # CONFIG_NET_VENDOR_SMC is not set
 # CONFIG_SMC91X is not set
 # CONFIG_DM9000 is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
 # CONFIG_NET_VENDOR_RACAL is not set
-
-#
-# Tulip family network device support
-#
 # CONFIG_NET_TULIP is not set
 # CONFIG_AT1700 is not set
 # CONFIG_DEPCA is not set
 # CONFIG_HP100 is not set
 # CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 CONFIG_NET_PCI=y
 # CONFIG_PCNET32 is not set
 # CONFIG_AMD8111_ETH is not set
@@ -462,56 +605,69 @@ CONFIG_NET_PCI=y
 # CONFIG_B44 is not set
 # CONFIG_FORCEDETH is not set
 CONFIG_CS89x0=y
-# CONFIG_DGRS is not set
-# CONFIG_EEPRO100 is not set
+CONFIG_CS89x0_NOEEPROM=y
 # CONFIG_E100 is not set
 # CONFIG_FEALNX is not set
 # CONFIG_NATSEMI is not set
 # CONFIG_NE2K_PCI is not set
 # CONFIG_8139CP is not set
 # CONFIG_8139TOO is not set
+# CONFIG_R6040 is not set
 # CONFIG_SIS900 is not set
 # CONFIG_EPIC100 is not set
+# CONFIG_SMSC9420 is not set
 # CONFIG_SUNDANCE is not set
 # CONFIG_TLAN is not set
 # CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
 # CONFIG_NET_POCKET is not set
-
-#
-# Ethernet (1000 Mbit)
-#
+# CONFIG_ATL2 is not set
+CONFIG_NETDEV_1000=y
 # CONFIG_ACENIC is not set
 # CONFIG_DL2K is not set
 # CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
 # CONFIG_NS83820 is not set
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
 # CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
 # CONFIG_SKGE is not set
-# CONFIG_SK98LIN is not set
+# CONFIG_SKY2 is not set
 # CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set
 # CONFIG_BNX2 is not set
-
-#
-# Ethernet (10000 Mbit)
-#
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_JME is not set
+CONFIG_NETDEV_10000=y
+# CONFIG_CHELSIO_T1 is not set
+CONFIG_CHELSIO_T3_DEPENDS=y
+# CONFIG_CHELSIO_T3 is not set
+# CONFIG_ENIC is not set
+# CONFIG_IXGBE is not set
 # CONFIG_IXGB is not set
 # CONFIG_S2IO is not set
-
-#
-# Token Ring devices
-#
+# CONFIG_MYRI10GE is not set
+# CONFIG_NETXEN_NIC is not set
+# CONFIG_NIU is not set
+# CONFIG_MLX4_EN is not set
+# CONFIG_MLX4_CORE is not set
+# CONFIG_TEHUTI is not set
+# CONFIG_BNX2X is not set
+# CONFIG_QLGE is not set
+# CONFIG_SFC is not set
 # CONFIG_TR is not set
 
 #
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
+# Wireless LAN
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 # CONFIG_WAN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
@@ -519,18 +675,17 @@ CONFIG_CS89x0=y
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
 # CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
-
-#
-# ISDN subsystem
-#
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
 # CONFIG_ISDN is not set
 
 #
 # Input device support
 #
 CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -540,7 +695,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -553,14 +707,25 @@ CONFIG_KEYBOARD_ATKBD=y
 # CONFIG_KEYBOARD_LKKBD is not set
 # CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
 CONFIG_INPUT_MOUSE=y
 CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
 # CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
 # CONFIG_MOUSE_INPORT is not set
 # CONFIG_MOUSE_LOGIBM is not set
 # CONFIG_MOUSE_PC110PAD is not set
 # CONFIG_MOUSE_VSXXXAA is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
@@ -580,16 +745,22 @@ CONFIG_SERIO_LIBPS2=y
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
 
 #
 # Serial drivers
 #
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_PCI=y
 CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
 # CONFIG_SERIAL_8250_EXTENDED is not set
 
 #
@@ -599,90 +770,122 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_JSM is not set
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
 CONFIG_PRINTER=m
 # CONFIG_LP_CONSOLE is not set
 # CONFIG_PPDEV is not set
-# CONFIG_TIPAR is not set
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
+CONFIG_HW_RANDOM=m
 # CONFIG_NVRAM is not set
-CONFIG_RTC=y
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_DRM is not set
 # CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
 
 #
-# TPM devices
+# Sonics Silicon Backplane
 #
-# CONFIG_TCG_TPM is not set
+# CONFIG_SSB is not set
 
 #
-# I2C support
+# Multifunction device drivers
 #
-# CONFIG_I2C is not set
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
 
 #
-# Misc devices
+# Multimedia devices
 #
 
 #
-# Multimedia devices
+# Multimedia core support
 #
 # CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multimedia drivers
 #
-# CONFIG_DVB is not set
+# CONFIG_DAB is not set
 
 #
 # Graphics support
 #
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_SOFT_CURSOR=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
 # CONFIG_FB_MODE_HELPERS is not set
 # CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
 # CONFIG_FB_CIRRUS is not set
 # CONFIG_FB_PM2 is not set
 CONFIG_FB_CYBER2000=y
 # CONFIG_FB_ASILIANT is not set
 # CONFIG_FB_IMSTT is not set
+# CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_NVIDIA is not set
 # CONFIG_FB_RIVA is not set
 # CONFIG_FB_MATROX is not set
-# CONFIG_FB_RADEON_OLD is not set
 # CONFIG_FB_RADEON is not set
 # CONFIG_FB_ATY128 is not set
 # CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
 # CONFIG_FB_SAVAGE is not set
 # CONFIG_FB_SIS is not set
+# CONFIG_FB_VIA is not set
 # CONFIG_FB_NEOMAGIC is not set
 # CONFIG_FB_KYRO is not set
 # CONFIG_FB_3DFX is not set
 # CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
 # CONFIG_FB_TRIDENT is not set
-# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
@@ -691,126 +894,132 @@ CONFIG_FB_CYBER2000=y
 # CONFIG_MDA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
 # CONFIG_FONTS is not set
 CONFIG_FONT_8x8=y
 CONFIG_FONT_8x16=y
-
-#
-# Logo configuration
-#
 CONFIG_LOGO=y
 # CONFIG_LOGO_LINUX_MONO is not set
 # CONFIG_LOGO_LINUX_VGA16 is not set
 CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Sound
-#
 CONFIG_SOUND=m
-
-#
-# Advanced Linux Sound Architecture
-#
+CONFIG_SOUND_OSS_CORE=y
 # CONFIG_SND is not set
-
-#
-# Open Sound System
-#
 CONFIG_SOUND_PRIME=m
-# CONFIG_SOUND_BT878 is not set
-# CONFIG_SOUND_CMPCI is not set
-# CONFIG_SOUND_EMU10K1 is not set
-# CONFIG_SOUND_FUSION is not set
-# CONFIG_SOUND_CS4281 is not set
-# CONFIG_SOUND_ES1370 is not set
-# CONFIG_SOUND_ES1371 is not set
-# CONFIG_SOUND_ESSSOLO1 is not set
-# CONFIG_SOUND_MAESTRO is not set
-# CONFIG_SOUND_MAESTRO3 is not set
-# CONFIG_SOUND_ICH is not set
-# CONFIG_SOUND_SONICVIBES is not set
-# CONFIG_SOUND_TRIDENT is not set
 # CONFIG_SOUND_MSNDCLAS is not set
 # CONFIG_SOUND_MSNDPIN is not set
-# CONFIG_SOUND_VIA82CXXX is not set
 CONFIG_SOUND_OSS=m
 # CONFIG_SOUND_TRACEINIT is not set
 # CONFIG_SOUND_DMAP is not set
-# CONFIG_SOUND_AD1816 is not set
-# CONFIG_SOUND_AD1889 is not set
-# CONFIG_SOUND_SGALAXY is not set
-CONFIG_SOUND_ADLIB=m
-# CONFIG_SOUND_ACI_MIXER is not set
-# CONFIG_SOUND_CS4232 is not set
 # CONFIG_SOUND_SSCAPE is not set
-# CONFIG_SOUND_GUS is not set
 # CONFIG_SOUND_VMIDI is not set
 # CONFIG_SOUND_TRIX is not set
 # CONFIG_SOUND_MSS is not set
 # CONFIG_SOUND_MPU401 is not set
-# CONFIG_SOUND_NM256 is not set
-# CONFIG_SOUND_MAD16 is not set
 # CONFIG_SOUND_PAS is not set
 # CONFIG_SOUND_PSS is not set
 CONFIG_SOUND_SB=m
-# CONFIG_SOUND_AWE32_SYNTH is not set
-# CONFIG_SOUND_WAVEFRONT is not set
-# CONFIG_SOUND_MAUI is not set
 # CONFIG_SOUND_YM3812 is not set
-# CONFIG_SOUND_OPL3SA1 is not set
-# CONFIG_SOUND_OPL3SA2 is not set
-# CONFIG_SOUND_YMFPCI is not set
 # CONFIG_SOUND_UART6850 is not set
 # CONFIG_SOUND_AEDSP16 is not set
 # CONFIG_SOUND_KAHLUA is not set
-# CONFIG_SOUND_ALI5455 is not set
-# CONFIG_SOUND_FORTE is not set
-# CONFIG_SOUND_RME96XX is not set
-# CONFIG_SOUND_AD1980 is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
 
 #
-# USB support
+# Special HID drivers
 #
+CONFIG_HID_COMPAT=y
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
 # CONFIG_USB is not set
 
 #
-# USB Gadget Support
+# Enable Host or Gadget support to see Inventra options
 #
-# CONFIG_USB_GADGET is not set
 
 #
-# MMC/SD Card support
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
 #
+# CONFIG_USB_GADGET is not set
+# CONFIG_UWB is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+CONFIG_RTC_DRV_CMOS=y
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
 
 #
 # File systems
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT3_FS_XATTR=y
 # CONFIG_EXT3_FS_POSIX_ACL is not set
 # CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4_FS is not set
 CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
-
-#
-# XFS support
-#
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_QUOTA is not set
+# CONFIG_OCFS2_FS is not set
 CONFIG_DNOTIFY=y
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
 
 #
 # CD-ROM/DVD Filesystems
@@ -834,14 +1043,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 # Pseudo filesystems
 #
 CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SYSFS=y
-CONFIG_DEVFS_FS=y
-CONFIG_DEVFS_MOUNT=y
-# CONFIG_DEVFS_DEBUG is not set
-# CONFIG_DEVPTS_FS_XATTR is not set
 # CONFIG_TMPFS is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
 
 #
 # Miscellaneous filesystems
@@ -855,22 +1062,27 @@ CONFIG_RAMFS=y
 # CONFIG_EFS_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-CONFIG_NFS_FS=m
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-# CONFIG_NFSD is not set
-CONFIG_LOCKD=m
+CONFIG_NFSD=m
+# CONFIG_NFSD_V3 is not set
+# CONFIG_NFSD_V4 is not set
+CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
-CONFIG_SUNRPC=m
+CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -897,11 +1109,9 @@ CONFIG_MSDOS_PARTITION=y
 # CONFIG_SGI_PARTITION is not set
 # CONFIG_ULTRIX_PARTITION is not set
 # CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
 # CONFIG_EFI_PARTITION is not set
-
-#
-# Native Language Support
-#
+# CONFIG_SYSV68_PARTITION is not set
 CONFIG_NLS=m
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=m
@@ -942,30 +1152,74 @@ CONFIG_NLS_ISO8859_1=m
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
+# CONFIG_DLM is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
-CONFIG_DEBUG_KERNEL=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
-CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+# CONFIG_SCHED_DEBUG is not set
 # CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_FS is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
 CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_DEBUG_LL is not set
 
 #
@@ -973,19 +1227,23 @@ CONFIG_DEBUG_USER=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
 # CONFIG_CRYPTO is not set
 
 #
-# Hardware crypto devices
-#
-
-#
 # Library routines
 #
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
 # CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/simpad_defconfig b/arch/arm/configs/simpad_defconfig
index 03f783e696b3..685d2b513206 100644
--- a/arch/arm/configs/simpad_defconfig
+++ b/arch/arm/configs/simpad_defconfig
@@ -89,7 +89,6 @@ CONFIG_ARCH_SA1100=y
 # CONFIG_SA1100_COLLIE is not set
 # CONFIG_SA1100_H3100 is not set
 # CONFIG_SA1100_H3600 is not set
-# CONFIG_SA1100_H3800 is not set
 # CONFIG_SA1100_BADGE4 is not set
 # CONFIG_SA1100_JORNADA720 is not set
 # CONFIG_SA1100_HACKKIT is not set
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 6cbd8fdc9f1f..bb7d695f3900 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -46,6 +46,14 @@
 # define MULTI_CACHE 1
 #endif
 
+#if defined(CONFIG_CPU_FA526)
+# ifdef _CACHE
+#  define MULTI_CACHE 1
+# else
+#  define _CACHE fa
+# endif
+#endif
+
 #if defined(CONFIG_CPU_ARM926T)
 # ifdef _CACHE
 #  define MULTI_CACHE 1
@@ -94,6 +102,14 @@
 # endif
 #endif
 
+#if defined(CONFIG_CPU_MOHAWK)
+# ifdef _CACHE
+#  define MULTI_CACHE 1
+# else
+#  define _CACHE mohawk
+# endif
+#endif
+
 #if defined(CONFIG_CPU_FEROCEON)
 # define MULTI_CACHE 1
 #endif
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 22cb14ec3438..ff46dfa68a97 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -15,10 +15,20 @@
  * must not be used by drivers.
  */
 #ifndef __arch_page_to_dma
+
+#if !defined(CONFIG_HIGHMEM)
 static inline dma_addr_t page_to_dma(struct device *dev, struct page *page)
 {
         return (dma_addr_t)__virt_to_bus((unsigned long)page_address(page));
 }
+#elif defined(__pfn_to_bus)
+static inline dma_addr_t page_to_dma(struct device *dev, struct page *page)
+{
+        return (dma_addr_t)__pfn_to_bus(page_to_pfn(page));
+}
+#else
+#error "this machine class needs to define __arch_page_to_dma to use HIGHMEM"
+#endif
 
 static inline void *dma_to_virt(struct device *dev, dma_addr_t addr)
 {
@@ -57,6 +67,8 @@ static inline dma_addr_t virt_to_dma(struct device *dev, void *addr)
  * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
  */
 extern void dma_cache_maint(const void *kaddr, size_t size, int rw);
+extern void dma_cache_maint_page(struct page *page, unsigned long offset,
+                                 size_t size, int rw);
 
 /*
  * Return whether the given device DMA address mask can be supported
@@ -316,7 +328,7 @@ static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
         BUG_ON(!valid_dma_direction(dir));
 
         if (!arch_is_coherent())
-                dma_cache_maint(page_address(page) + offset, size, dir);
+                dma_cache_maint_page(page, offset, size, dir);
 
         return page_to_dma(dev, page) + offset;
 }
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index df5638f3643a..7edf3536df24 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -19,21 +19,17 @@
 #include <asm/system.h>
 #include <asm/scatterlist.h>
 
-typedef unsigned int dmach_t;
-
 #include <mach/isa-dma.h>
 
 /*
- * DMA modes
+ * The DMA modes reflect the settings for the ISA DMA controller
  */
-typedef unsigned int dmamode_t;
-
-#define DMA_MODE_MASK   3
+#define DMA_MODE_MASK    0xcc
 
-#define DMA_MODE_READ    0
-#define DMA_MODE_WRITE   1
-#define DMA_MODE_CASCADE 2
-#define DMA_AUTOINIT     4
+#define DMA_MODE_READ    0x44
+#define DMA_MODE_WRITE   0x48
+#define DMA_MODE_CASCADE 0xc0
+#define DMA_AUTOINIT     0x10
 
 extern spinlock_t  dma_spin_lock;
 
@@ -52,44 +48,44 @@ static inline void release_dma_lock(unsigned long flags)
 /* Clear the 'DMA Pointer Flip Flop'.
  * Write 0 for LSB/MSB, 1 for MSB/LSB access.
  */
-#define clear_dma_ff(channel)
+#define clear_dma_ff(chan)
 
 /* Set only the page register bits of the transfer address.
  *
  * NOTE: This is an architecture specific function, and should
  *       be hidden from the drivers
  */
-extern void set_dma_page(dmach_t channel, char pagenr);
+extern void set_dma_page(unsigned int chan, char pagenr);
 
 /* Request a DMA channel
  *
  * Some architectures may need to do allocate an interrupt
  */
-extern int  request_dma(dmach_t channel, const char * device_id);
+extern int  request_dma(unsigned int chan, const char * device_id);
 
 /* Free a DMA channel
  *
  * Some architectures may need to do free an interrupt
  */
-extern void free_dma(dmach_t channel);
+extern void free_dma(unsigned int chan);
 
 /* Enable DMA for this channel
  *
  * On some architectures, this may have other side effects like
  * enabling an interrupt and setting the DMA registers.
  */
-extern void enable_dma(dmach_t channel);
+extern void enable_dma(unsigned int chan);
 
 /* Disable DMA for this channel
  *
  * On some architectures, this may have other side effects like
  * disabling an interrupt or whatever.
  */
-extern void disable_dma(dmach_t channel);
+extern void disable_dma(unsigned int chan);
 
 /* Test whether the specified channel has an active DMA transfer
  */
-extern int dma_channel_active(dmach_t channel);
+extern int dma_channel_active(unsigned int chan);
 
 /* Set the DMA scatter gather list for this channel
  *
@@ -97,7 +93,7 @@ extern int dma_channel_active(dmach_t channel);
  * especially since some DMA architectures don't update the
  * DMA address immediately, but defer it to the enable_dma().
  */
-extern void set_dma_sg(dmach_t channel, struct scatterlist *sg, int nr_sg);
+extern void set_dma_sg(unsigned int chan, struct scatterlist *sg, int nr_sg);
 
 /* Set the DMA address for this channel
  *
@@ -105,9 +101,9 @@ extern void set_dma_sg(dmach_t channel, struct scatterlist *sg, int nr_sg);
  * especially since some DMA architectures don't update the
  * DMA address immediately, but defer it to the enable_dma().
  */
-extern void __set_dma_addr(dmach_t channel, void *addr);
-#define set_dma_addr(channel, addr)                             \
-        __set_dma_addr(channel, bus_to_virt(addr))
+extern void __set_dma_addr(unsigned int chan, void *addr);
+#define set_dma_addr(chan, addr)                                \
+        __set_dma_addr(chan, bus_to_virt(addr))
 
 /* Set the DMA byte count for this channel
  *
@@ -115,7 +111,7 @@ extern void __set_dma_addr(dmach_t channel, void *addr);
  * especially since some DMA architectures don't update the
  * DMA count immediately, but defer it to the enable_dma().
  */
-extern void set_dma_count(dmach_t channel, unsigned long count);
+extern void set_dma_count(unsigned int chan, unsigned long count);
 
 /* Set the transfer direction for this channel
  *
@@ -124,11 +120,11 @@ extern void set_dma_count(dmach_t channel, unsigned long count);
  * DMA transfer direction immediately, but defer it to the
  * enable_dma().
  */
-extern void set_dma_mode(dmach_t channel, dmamode_t mode);
+extern void set_dma_mode(unsigned int chan, unsigned int mode);
 
 /* Set the transfer speed for this channel
  */
-extern void set_dma_speed(dmach_t channel, int cycle_ns);
+extern void set_dma_speed(unsigned int chan, int cycle_ns);
 
 /* Get DMA residue count. After a DMA transfer, this
  * should return zero. Reading this while a DMA transfer is
@@ -136,7 +132,7 @@ extern void set_dma_speed(dmach_t channel, int cycle_ns);
  * If called before the channel has been used, it may return 1.
  * Otherwise, it returns the number of _bytes_ left to transfer.
  */
-extern int  get_dma_residue(dmach_t channel);
+extern int  get_dma_residue(unsigned int chan);
 
 #ifndef NO_DMA
 #define NO_DMA  255
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index a58378c343b9..d7da19bcf928 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -50,6 +50,8 @@ typedef struct user_fp elf_fpregset_t;
 #define R_ARM_ABS32     2
 #define R_ARM_CALL      28
 #define R_ARM_JUMP24    29
+#define R_ARM_V4BX      40
+#define R_ARM_PREL31    42
 
 /*
  * These are used to set parameters in the core dumps.
diff --git a/arch/arm/include/asm/fixmap.h b/arch/arm/include/asm/fixmap.h
new file mode 100644
index 000000000000..bbae919bceb4
--- /dev/null
+++ b/arch/arm/include/asm/fixmap.h
@@ -0,0 +1,41 @@
+#ifndef _ASM_FIXMAP_H
+#define _ASM_FIXMAP_H
+
+/*
+ * Nothing too fancy for now.
+ *
+ * On ARM we already have well known fixed virtual addresses imposed by
+ * the architecture such as the vector page which is located at 0xffff0000,
+ * therefore a second level page table is already allocated covering
+ * 0xfff00000 upwards.
+ *
+ * The cache flushing code in proc-xscale.S uses the virtual area between
+ * 0xfffe0000 and 0xfffeffff.
+ */
+
+#define FIXADDR_START           0xfff00000UL
+#define FIXADDR_TOP             0xfffe0000UL
+#define FIXADDR_SIZE            (FIXADDR_TOP - FIXADDR_START)
+
+#define FIX_KMAP_BEGIN          0
+#define FIX_KMAP_END            (FIXADDR_SIZE >> PAGE_SHIFT)
+
+#define __fix_to_virt(x)        (FIXADDR_START + ((x) << PAGE_SHIFT))
+#define __virt_to_fix(x)        (((x) - FIXADDR_START) >> PAGE_SHIFT)
+
+extern void __this_fixmap_does_not_exist(void);
+
+static inline unsigned long fix_to_virt(const unsigned int idx)
+{
+        if (idx >= FIX_KMAP_END)
+                __this_fixmap_does_not_exist();
+        return __fix_to_virt(idx);
+}
+
+static inline unsigned int virt_to_fix(const unsigned long vaddr)
+{
+        BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
+        return __virt_to_fix(vaddr);
+}
+
+#endif
diff --git a/arch/arm/include/asm/hardware/scoop.h b/arch/arm/include/asm/hardware/scoop.h
index dfb8330599f9..46492a63a7c4 100644
--- a/arch/arm/include/asm/hardware/scoop.h
+++ b/arch/arm/include/asm/hardware/scoop.h
@@ -63,7 +63,5 @@ struct scoop_pcmcia_config {
 extern struct scoop_pcmcia_config *platform_scoop_config;
 
 void reset_scoop(struct device *dev);
-unsigned short __deprecated set_scoop_gpio(struct device *dev, unsigned short bit);
-unsigned short __deprecated reset_scoop_gpio(struct device *dev, unsigned short bit);
 unsigned short read_scoop_reg(struct device *dev, unsigned short reg);
 void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data);
diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h
new file mode 100644
index 000000000000..7f36d00600b4
--- /dev/null
+++ b/arch/arm/include/asm/highmem.h
@@ -0,0 +1,31 @@
+#ifndef _ASM_HIGHMEM_H
+#define _ASM_HIGHMEM_H
+
+#include <asm/kmap_types.h>
+
+#define PKMAP_BASE              (PAGE_OFFSET - PMD_SIZE)
+#define LAST_PKMAP              PTRS_PER_PTE
+#define LAST_PKMAP_MASK         (LAST_PKMAP - 1)
+#define PKMAP_NR(virt)          (((virt) - PKMAP_BASE) >> PAGE_SHIFT)
+#define PKMAP_ADDR(nr)          (PKMAP_BASE + ((nr) << PAGE_SHIFT))
+
+#define kmap_prot               PAGE_KERNEL
+
+#define flush_cache_kmaps()     flush_cache_all()
+
+extern pte_t *pkmap_page_table;
+
+#define ARCH_NEEDS_KMAP_HIGH_GET
+
+extern void *kmap_high(struct page *page);
+extern void *kmap_high_get(struct page *page);
+extern void kunmap_high(struct page *page);
+
+extern void *kmap(struct page *page);
+extern void kunmap(struct page *page);
+extern void *kmap_atomic(struct page *page, enum km_type type);
+extern void kunmap_atomic(void *kvaddr, enum km_type type);
+extern void *kmap_atomic_pfn(unsigned long pfn, enum km_type type);
+extern struct page *kmap_atomic_to_page(const void *ptr);
+
+#endif
diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h
index bda489f9f017..f7bd52b1c365 100644
--- a/arch/arm/include/asm/hwcap.h
+++ b/arch/arm/include/asm/hwcap.h
@@ -17,6 +17,8 @@
 #define HWCAP_CRUNCH    1024
 #define HWCAP_THUMBEE   2048
 #define HWCAP_NEON      4096
+#define HWCAP_VFPv3     8192
+#define HWCAP_VFPv3D16  16384
 
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 /*
diff --git a/arch/arm/include/asm/kmap_types.h b/arch/arm/include/asm/kmap_types.h
index 45def13ee17a..d16ec97ec9a9 100644
--- a/arch/arm/include/asm/kmap_types.h
+++ b/arch/arm/include/asm/kmap_types.h
@@ -18,6 +18,7 @@ enum km_type {
         KM_IRQ1,
         KM_SOFTIRQ0,
         KM_SOFTIRQ1,
+        KM_L2_CACHE,
         KM_TYPE_NR
 };
 
diff --git a/arch/arm/include/asm/mach/dma.h b/arch/arm/include/asm/mach/dma.h
index fc7278ea7146..9e614a18e680 100644
--- a/arch/arm/include/asm/mach/dma.h
+++ b/arch/arm/include/asm/mach/dma.h
@@ -15,13 +15,13 @@ struct dma_struct;
 typedef struct dma_struct dma_t;
 
 struct dma_ops {
-        int     (*request)(dmach_t, dma_t *);           /* optional */
-        void    (*free)(dmach_t, dma_t *);              /* optional */
-        void    (*enable)(dmach_t, dma_t *);            /* mandatory */
-        void    (*disable)(dmach_t, dma_t *);           /* mandatory */
-        int     (*residue)(dmach_t, dma_t *);           /* optional */
-        int     (*setspeed)(dmach_t, dma_t *, int);     /* optional */
-        char    *type;
+        int     (*request)(unsigned int, dma_t *);              /* optional */
+        void    (*free)(unsigned int, dma_t *);                 /* optional */
+        void    (*enable)(unsigned int, dma_t *);               /* mandatory */
+        void    (*disable)(unsigned int, dma_t *);              /* mandatory */
+        int     (*residue)(unsigned int, dma_t *);              /* optional */
+        int     (*setspeed)(unsigned int, dma_t *, int);        /* optional */
+        const char *type;
 };
 
 struct dma_struct {
@@ -34,24 +34,21 @@ struct dma_struct {
         unsigned int    active:1;       /* Transfer active              */
         unsigned int    invalid:1;      /* Address/Count changed        */
 
-        dmamode_t       dma_mode;       /* DMA mode                     */
+        unsigned int    dma_mode;       /* DMA mode                     */
         int             speed;          /* DMA speed                    */
 
         unsigned int    lock;           /* Device is allocated          */
         const char      *device_id;     /* Device name                  */
 
-        unsigned int    dma_base;       /* Controller base address      */
-        int             dma_irq;        /* Controller IRQ               */
-        struct scatterlist cur_sg;      /* Current controller buffer    */
-        unsigned int    state;
-
-        struct dma_ops  *d_ops;
+        const struct dma_ops *d_ops;
 };
 
-/* Prototype: void arch_dma_init(dma)
- * Purpose  : Initialise architecture specific DMA
- * Params   : dma - pointer to array of DMA structures
+/*
+ * isa_dma_add - add an ISA-style DMA channel
  */
-extern void arch_dma_init(dma_t *dma);
+extern int isa_dma_add(unsigned int, dma_t *dma);
 
-extern void isa_init_dma(dma_t *dma);
+/*
+ * Add the ISA DMA controller.  Always takes channels 0-7.
+ */
+extern void isa_init_dma(void);
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index 39d949b63e80..58cf91f38e6f 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -26,6 +26,7 @@ struct map_desc {
 #define MT_HIGH_VECTORS         8
 #define MT_MEMORY               9
 #define MT_ROM                  10
+#define MT_MEMORY_NONCACHED     11
 
 #ifdef CONFIG_MMU
 extern void iotable_init(struct map_desc *, int);
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 0202a7c20e62..85763db87449 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -44,14 +44,21 @@
  * The module space lives between the addresses given by TASK_SIZE
  * and PAGE_OFFSET - it must be within 32MB of the kernel text.
  */
-#define MODULES_END             (PAGE_OFFSET)
-#define MODULES_VADDR           (MODULES_END - 16*1048576)
-
+#define MODULES_VADDR           (PAGE_OFFSET - 16*1024*1024)
 #if TASK_SIZE > MODULES_VADDR
 #error Top of user space clashes with start of module space
 #endif
 
 /*
+ * The highmem pkmap virtual space shares the end of the module area.
+ */
+#ifdef CONFIG_HIGHMEM
+#define MODULES_END             (PAGE_OFFSET - PMD_SIZE)
+#else
+#define MODULES_END             (PAGE_OFFSET)
+#endif
+
+/*
  * The XIP kernel gets mapped at the bottom of the module vm area.
  * Since we use sections to map it, this macro replaces the physical address
  * with its virtual address while keeping offset from the base section.
@@ -181,6 +188,7 @@ static inline void *phys_to_virt(unsigned long x)
 #ifndef __virt_to_bus
 #define __virt_to_bus   __virt_to_phys
 #define __bus_to_virt   __phys_to_virt
+#define __pfn_to_bus(x) ((x) << PAGE_SHIFT)
 #endif
 
 static inline __deprecated unsigned long virt_to_bus(void *x)
diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h
index 24b168dc31a3..e4dfa69abb68 100644
--- a/arch/arm/include/asm/module.h
+++ b/arch/arm/include/asm/module.h
@@ -1,15 +1,27 @@
 #ifndef _ASM_ARM_MODULE_H
 #define _ASM_ARM_MODULE_H
 
-struct mod_arch_specific
-{
-        int foo;
-};
-
 #define Elf_Shdr        Elf32_Shdr
 #define Elf_Sym         Elf32_Sym
 #define Elf_Ehdr        Elf32_Ehdr
 
+struct unwind_table;
+
+struct mod_arch_specific
+{
+#ifdef CONFIG_ARM_UNWIND
+        Elf_Shdr *unw_sec_init;
+        Elf_Shdr *unw_sec_devinit;
+        Elf_Shdr *unw_sec_core;
+        Elf_Shdr *sec_init_text;
+        Elf_Shdr *sec_devinit_text;
+        Elf_Shdr *sec_core_text;
+        struct unwind_table *unwind_init;
+        struct unwind_table *unwind_devinit;
+        struct unwind_table *unwind_core;
+#endif
+};
+
 /*
  * Include the ARM architecture version.
  */
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index f341c9dbd662..e6eb8a67b807 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -76,6 +76,14 @@
 # endif
 #endif
 
+#ifdef CONFIG_CPU_COPY_FA
+# ifdef _USER
+#  define MULTI_USER 1
+# else
+#  define _USER fa
+# endif
+#endif
+
 #ifdef CONFIG_CPU_SA1100
 # ifdef _USER
 #  define MULTI_USER 1
diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
index db80203b68e0..3976412685f8 100644
--- a/arch/arm/include/asm/proc-fns.h
+++ b/arch/arm/include/asm/proc-fns.h
@@ -89,6 +89,14 @@
 #   define CPU_NAME cpu_arm922
 #  endif
 # endif
+# ifdef CONFIG_CPU_FA526
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_fa526
+#  endif
+# endif
 # ifdef CONFIG_CPU_ARM925T
 #  ifdef CPU_NAME
 #   undef  MULTI_CPU
@@ -185,6 +193,14 @@
 #   define CPU_NAME cpu_xsc3
 #  endif
 # endif
+# ifdef CONFIG_CPU_MOHAWK
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_mohawk
+#  endif
+# endif
 # ifdef CONFIG_CPU_FEROCEON
 #  ifdef CPU_NAME
 #   undef  MULTI_CPU
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 73192618f1c2..236a06b9b7ce 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -27,6 +27,8 @@
 /* PTRACE_SYSCALL is 24 */
 #define PTRACE_GETCRUNCHREGS    25
 #define PTRACE_SETCRUNCHREGS    26
+#define PTRACE_GETVFPREGS       27
+#define PTRACE_SETVFPREGS       28
 
 /*
  * PSR bits
diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h
index 503843db1565..c10d1aa4b487 100644
--- a/arch/arm/include/asm/sizes.h
+++ b/arch/arm/include/asm/sizes.h
@@ -43,6 +43,7 @@
 #define SZ_8M                           0x00800000
 #define SZ_16M                          0x01000000
 #define SZ_32M                          0x02000000
+#define SZ_48M                          0x03000000
 #define SZ_64M                          0x04000000
 #define SZ_128M                         0x08000000
 #define SZ_256M                         0x10000000
diff --git a/arch/arm/include/asm/stacktrace.h b/arch/arm/include/asm/stacktrace.h
new file mode 100644
index 000000000000..4d0a16441b29
--- /dev/null
+++ b/arch/arm/include/asm/stacktrace.h
@@ -0,0 +1,15 @@
+#ifndef __ASM_STACKTRACE_H
+#define __ASM_STACKTRACE_H
+
+struct stackframe {
+        unsigned long fp;
+        unsigned long sp;
+        unsigned long lr;
+        unsigned long pc;
+};
+
+extern int unwind_frame(struct stackframe *frame);
+extern void walk_stackframe(struct stackframe *frame,
+                            int (*fn)(struct stackframe *, void *), void *data);
+
+#endif  /* __ASM_STACKTRACE_H */
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 811be55f338e..bd4dc8ed53d5 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -97,8 +97,8 @@ extern void __show_regs(struct pt_regs *);
 extern int cpu_architecture(void);
 extern void cpu_init(void);
 
-void arm_machine_restart(char mode);
-extern void (*arm_pm_restart)(char str);
+void arm_machine_restart(char mode, const char *cmd);
+extern void (*arm_pm_restart)(char str, const char *cmd);
 
 #define UDBG_UNDEFINED  (1 << 0)
 #define UDBG_SYSCALL    (1 << 1)
@@ -125,6 +125,12 @@ extern unsigned int user_debug;
                                     : : "r" (0) : "memory")
 #define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
                                     : : "r" (0) : "memory")
+#elif defined(CONFIG_CPU_FA526)
+#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
+                                    : : "r" (0) : "memory")
+#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
+                                    : : "r" (0) : "memory")
+#define dmb() __asm__ __volatile__ ("" : : : "memory")
 #else
 #define isb() __asm__ __volatile__ ("" : : : "memory")
 #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index 68b9ec82a37f..4f8848260ee2 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -99,6 +99,8 @@ static inline struct thread_info *current_thread_info(void)
 
 #define thread_saved_pc(tsk)    \
         ((unsigned long)(task_thread_info(tsk)->cpu_context.pc))
+#define thread_saved_sp(tsk)    \
+        ((unsigned long)(task_thread_info(tsk)->cpu_context.sp))
 #define thread_saved_fp(tsk)    \
         ((unsigned long)(task_thread_info(tsk)->cpu_context.fp))
 
@@ -113,6 +115,8 @@ extern void iwmmxt_task_restore(struct thread_info *, void *);
 extern void iwmmxt_task_release(struct thread_info *);
 extern void iwmmxt_task_switch(struct thread_info *);
 
+extern void vfp_sync_state(struct thread_info *thread);
+
 #endif
 
 /*
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index b543a054a17e..a62218013c78 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -39,6 +39,7 @@
 #define TLB_V6_D_ASID   (1 << 17)
 #define TLB_V6_I_ASID   (1 << 18)
 
+#define TLB_BTB         (1 << 28)
 #define TLB_L2CLEAN_FR  (1 << 29)               /* Feroceon */
 #define TLB_DCLEAN      (1 << 30)
 #define TLB_WB          (1 << 31)
@@ -53,6 +54,7 @@
  *        v4wb  - ARMv4 with write buffer without I TLB flush entry instruction
  *        v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
  *        fr    - Feroceon (v4wbi with non-outer-cacheable page table walks)
+ *        fa    - Faraday (v4 with write buffer with UTLB and branch target buffer (BTB))
  *        v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
  *        v7wbi - identical to v6wbi
  */
@@ -89,6 +91,22 @@
 # define v4_always_flags        (-1UL)
 #endif
 
+#define fa_tlb_flags    (TLB_WB | TLB_BTB | TLB_DCLEAN | \
+                         TLB_V4_U_FULL | TLB_V4_U_PAGE)
+
+#ifdef CONFIG_CPU_TLB_FA
+# define fa_possible_flags      fa_tlb_flags
+# define fa_always_flags        fa_tlb_flags
+# ifdef _TLB
+#  define MULTI_TLB 1
+# else
+#  define _TLB fa
+# endif
+#else
+# define fa_possible_flags      0
+# define fa_always_flags        (-1UL)
+#endif
+
 #define v4wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \
                          TLB_V4_I_FULL | TLB_V4_D_FULL | \
                          TLB_V4_I_PAGE | TLB_V4_D_PAGE)
@@ -140,7 +158,7 @@
 # define v4wb_always_flags      (-1UL)
 #endif
 
-#define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \
+#define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
                          TLB_V6_I_FULL | TLB_V6_D_FULL | \
                          TLB_V6_I_PAGE | TLB_V6_D_PAGE | \
                          TLB_V6_I_ASID | TLB_V6_D_ASID)
@@ -267,6 +285,7 @@ extern struct cpu_tlb_fns cpu_tlb;
                                  v4wbi_possible_flags | \
                                  fr_possible_flags | \
                                  v4wb_possible_flags | \
+                                 fa_possible_flags | \
                                  v6wbi_possible_flags | \
                                  v7wbi_possible_flags)
 
@@ -275,6 +294,7 @@ extern struct cpu_tlb_fns cpu_tlb;
                                  v4wbi_always_flags & \
                                  fr_always_flags & \
                                  v4wb_always_flags & \
+                                 fa_always_flags & \
                                  v6wbi_always_flags & \
                                  v7wbi_always_flags)
 
@@ -297,9 +317,7 @@ static inline void local_flush_tlb_all(void)
         if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
                 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
 
-        if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
-                     TLB_V6_I_PAGE | TLB_V6_D_PAGE |
-                     TLB_V6_I_ASID | TLB_V6_D_ASID)) {
+        if (tlb_flag(TLB_BTB)) {
                 /* flush the branch target cache */
                 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
                 dsb();
@@ -334,9 +352,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
         if (tlb_flag(TLB_V6_I_ASID))
                 asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
 
-        if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
-                     TLB_V6_I_PAGE | TLB_V6_D_PAGE |
-                     TLB_V6_I_ASID | TLB_V6_D_ASID)) {
+        if (tlb_flag(TLB_BTB)) {
                 /* flush the branch target cache */
                 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
                 dsb();
@@ -374,9 +390,7 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
         if (tlb_flag(TLB_V6_I_PAGE))
                 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
 
-        if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
-                     TLB_V6_I_PAGE | TLB_V6_D_PAGE |
-                     TLB_V6_I_ASID | TLB_V6_D_ASID)) {
+        if (tlb_flag(TLB_BTB)) {
                 /* flush the branch target cache */
                 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
                 dsb();
@@ -411,9 +425,7 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
         if (tlb_flag(TLB_V6_I_PAGE))
                 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
 
-        if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
-                     TLB_V6_I_PAGE | TLB_V6_D_PAGE |
-                     TLB_V6_I_ASID | TLB_V6_D_ASID)) {
+        if (tlb_flag(TLB_BTB)) {
                 /* flush the branch target cache */
                 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
                 dsb();
diff --git a/arch/arm/include/asm/traps.h b/arch/arm/include/asm/traps.h
index aa399aec568e..491960bf4260 100644
--- a/arch/arm/include/asm/traps.h
+++ b/arch/arm/include/asm/traps.h
@@ -25,5 +25,6 @@ static inline int in_exception_text(unsigned long ptr)
 }
 
 extern void __init early_trap_init(void);
+extern void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame);
 
 #endif
diff --git a/arch/arm/include/asm/unwind.h b/arch/arm/include/asm/unwind.h
new file mode 100644
index 000000000000..a5edf421005c
--- /dev/null
+++ b/arch/arm/include/asm/unwind.h
@@ -0,0 +1,69 @@
+/*
+ * arch/arm/include/asm/unwind.h
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_UNWIND_H
+#define __ASM_UNWIND_H
+
+#ifndef __ASSEMBLY__
+
+/* Unwind reason code according the the ARM EABI documents */
+enum unwind_reason_code {
+        URC_OK = 0,                     /* operation completed successfully */
+        URC_CONTINUE_UNWIND = 8,
+        URC_FAILURE = 9                 /* unspecified failure of some kind */
+};
+
+struct unwind_idx {
+        unsigned long addr;
+        unsigned long insn;
+};
+
+struct unwind_table {
+        struct list_head list;
+        struct unwind_idx *start;
+        struct unwind_idx *stop;
+        unsigned long begin_addr;
+        unsigned long end_addr;
+};
+
+extern struct unwind_table *unwind_table_add(unsigned long start,
+                                             unsigned long size,
+                                             unsigned long text_addr,
+                                             unsigned long text_size);
+extern void unwind_table_del(struct unwind_table *tab);
+extern void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk);
+
+#ifdef CONFIG_ARM_UNWIND
+extern int __init unwind_init(void);
+#else
+static inline int __init unwind_init(void)
+{
+        return 0;
+}
+#endif
+
+#endif  /* !__ASSEMBLY__ */
+
+#ifdef CONFIG_ARM_UNWIND
+#define UNWIND(code...)         code
+#else
+#define UNWIND(code...)
+#endif
+
+#endif  /* __ASM_UNWIND_H */
diff --git a/arch/arm/include/asm/user.h b/arch/arm/include/asm/user.h
index 825c1e7c582d..df95e050f9dd 100644
--- a/arch/arm/include/asm/user.h
+++ b/arch/arm/include/asm/user.h
@@ -81,4 +81,13 @@ struct user{
 #define HOST_TEXT_START_ADDR (u.start_code)
 #define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
 
+/*
+ * User specific VFP registers. If only VFPv2 is present, registers 16 to 31
+ * are ignored by the ptrace system call.
+ */
+struct user_vfp {
+        unsigned long long fpregs[32];
+        unsigned long fpscr;
+};
+
 #endif /* _ARM_USER_H */
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 4305345987d3..11a5197a221f 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -29,12 +29,14 @@ obj-$(CONFIG_ATAGS_PROC)	+= atags.o
 obj-$(CONFIG_OABI_COMPAT)       += sys_oabi-compat.o
 obj-$(CONFIG_ARM_THUMBEE)       += thumbee.o
 obj-$(CONFIG_KGDB)              += kgdb.o
+obj-$(CONFIG_ARM_UNWIND)        += unwind.o
 
 obj-$(CONFIG_CRUNCH)            += crunch.o crunch-bits.o
 AFLAGS_crunch-bits.o            := -Wa,-mcpu=ep9312
 
 obj-$(CONFIG_CPU_XSCALE)        += xscale-cp0.o
 obj-$(CONFIG_CPU_XSC3)          += xscale-cp0.o
+obj-$(CONFIG_CPU_MOHAWK)        += xscale-cp0.o
 obj-$(CONFIG_IWMMXT)            += iwmmxt.o
 AFLAGS_iwmmxt.o                 := -Wa,-mcpu=iwmmxt
 
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index f53c58290543..b121b6053cce 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -49,6 +49,33 @@
 1002:
                 .endm
 
+#elif defined(CONFIG_CPU_XSCALE)
+
+                .macro  addruart, rx
+                .endm
+
+                .macro  senduart, rd, rx
+                mcr     p14, 0, \rd, c8, c0, 0
+                .endm
+
+                .macro  busyuart, rd, rx
+1001:
+                mrc     p14, 0, \rx, c14, c0, 0
+                tst     \rx, #0x10000000
+                beq     1001b
+                .endm
+
+                .macro  waituart, rd, rx
+                mov     \rd, #0x10000000
+1001:
+                subs    \rd, \rd, #1
+                bmi     1002f
+                mrc     p14, 0, \rx, c14, c0, 0
+                tst     \rx, #0x10000000
+                bne     1001b
+1002:
+                .endm
+
 #else
 
                 .macro  addruart, rx
diff --git a/arch/arm/kernel/dma-isa.c b/arch/arm/kernel/dma-isa.c
index 4a3a50495c60..0e88e46fc732 100644
--- a/arch/arm/kernel/dma-isa.c
+++ b/arch/arm/kernel/dma-isa.c
@@ -24,11 +24,6 @@
 #include <asm/dma.h>
 #include <asm/mach/dma.h>
 
-#define ISA_DMA_MODE_READ       0x44
-#define ISA_DMA_MODE_WRITE      0x48
-#define ISA_DMA_MODE_CASCADE    0xc0
-#define ISA_DMA_AUTOINIT        0x10
-
 #define ISA_DMA_MASK            0
 #define ISA_DMA_MODE            1
 #define ISA_DMA_CLRFF           2
@@ -49,38 +44,35 @@ static unsigned int isa_dma_port[8][7] = {
         {  0xd4,  0xd6,  0xd8,  0x48a,  0x08a,  0xcc, 0xce }
 };
 
-static int isa_get_dma_residue(dmach_t channel, dma_t *dma)
+static int isa_get_dma_residue(unsigned int chan, dma_t *dma)
 {
-        unsigned int io_port = isa_dma_port[channel][ISA_DMA_COUNT];
+        unsigned int io_port = isa_dma_port[chan][ISA_DMA_COUNT];
         int count;
 
         count = 1 + inb(io_port);
         count |= inb(io_port) << 8;
 
-        return channel < 4 ? count : (count << 1);
+        return chan < 4 ? count : (count << 1);
 }
 
-static void isa_enable_dma(dmach_t channel, dma_t *dma)
+static void isa_enable_dma(unsigned int chan, dma_t *dma)
 {
         if (dma->invalid) {
                 unsigned long address, length;
                 unsigned int mode;
                 enum dma_data_direction direction;
 
-                mode = channel & 3;
+                mode = (chan & 3) | dma->dma_mode;
                 switch (dma->dma_mode & DMA_MODE_MASK) {
                 case DMA_MODE_READ:
-                        mode |= ISA_DMA_MODE_READ;
                         direction = DMA_FROM_DEVICE;
                         break;
 
                 case DMA_MODE_WRITE:
-                        mode |= ISA_DMA_MODE_WRITE;
                         direction = DMA_TO_DEVICE;
                         break;
 
                 case DMA_MODE_CASCADE:
-                        mode |= ISA_DMA_MODE_CASCADE;
                         direction = DMA_BIDIRECTIONAL;
                         break;
 
@@ -105,34 +97,31 @@ static void isa_enable_dma(dmach_t channel, dma_t *dma)
                 address = dma->buf.dma_address;
                 length  = dma->buf.length - 1;
 
-                outb(address >> 16, isa_dma_port[channel][ISA_DMA_PGLO]);
-                outb(address >> 24, isa_dma_port[channel][ISA_DMA_PGHI]);
+                outb(address >> 16, isa_dma_port[chan][ISA_DMA_PGLO]);
+                outb(address >> 24, isa_dma_port[chan][ISA_DMA_PGHI]);
 
-                if (channel >= 4) {
+                if (chan >= 4) {
                         address >>= 1;
                         length >>= 1;
                 }
 
-                outb(0, isa_dma_port[channel][ISA_DMA_CLRFF]);
-
-                outb(address, isa_dma_port[channel][ISA_DMA_ADDR]);
-                outb(address >> 8, isa_dma_port[channel][ISA_DMA_ADDR]);
+                outb(0, isa_dma_port[chan][ISA_DMA_CLRFF]);
 
-                outb(length, isa_dma_port[channel][ISA_DMA_COUNT]);
-                outb(length >> 8, isa_dma_port[channel][ISA_DMA_COUNT]);
+                outb(address, isa_dma_port[chan][ISA_DMA_ADDR]);
+                outb(address >> 8, isa_dma_port[chan][ISA_DMA_ADDR]);
 
-                if (dma->dma_mode & DMA_AUTOINIT)
-                        mode |= ISA_DMA_AUTOINIT;
+                outb(length, isa_dma_port[chan][ISA_DMA_COUNT]);
+                outb(length >> 8, isa_dma_port[chan][ISA_DMA_COUNT]);
 
-                outb(mode, isa_dma_port[channel][ISA_DMA_MODE]);
+                outb(mode, isa_dma_port[chan][ISA_DMA_MODE]);
                 dma->invalid = 0;
         }
-        outb(channel & 3, isa_dma_port[channel][ISA_DMA_MASK]);
+        outb(chan & 3, isa_dma_port[chan][ISA_DMA_MASK]);
 }
 
-static void isa_disable_dma(dmach_t channel, dma_t *dma)
+static void isa_disable_dma(unsigned int chan, dma_t *dma)
 {
-        outb(channel | 4, isa_dma_port[channel][ISA_DMA_MASK]);
+        outb(chan | 4, isa_dma_port[chan][ISA_DMA_MASK]);
 }
 
 static struct dma_ops isa_dma_ops = {
@@ -160,7 +149,12 @@ static struct resource dma_resources[] = { {
         .end    = 0x048f
 } };
 
-void __init isa_init_dma(dma_t *dma)
+static dma_t isa_dma[8];
+
+/*
+ * ISA DMA always starts at channel 0
+ */
+void __init isa_init_dma(void)
 {
         /*
          * Try to autodetect presence of an ISA DMA controller.
@@ -178,11 +172,11 @@ void __init isa_init_dma(dma_t *dma)
         outb(0xaa, 0x00);
 
         if (inb(0) == 0x55 && inb(0) == 0xaa) {
-                int channel, i;
+                unsigned int chan, i;
 
-                for (channel = 0; channel < 8; channel++) {
-                        dma[channel].d_ops = &isa_dma_ops;
-                        isa_disable_dma(channel, NULL);
+                for (chan = 0; chan < 8; chan++) {
+                        isa_dma[chan].d_ops = &isa_dma_ops;
+                        isa_disable_dma(chan, NULL);
                 }
 
                 outb(0x40, 0x0b);
@@ -217,5 +211,12 @@ void __init isa_init_dma(dma_t *dma)
 
                 for (i = 0; i < ARRAY_SIZE(dma_resources); i++)
                         request_resource(&ioport_resource, dma_resources + i);
+
+                for (chan = 0; chan < 8; chan++) {
+                        int ret = isa_dma_add(chan, &isa_dma[chan]);
+                        if (ret)
+                                printk(KERN_ERR "ISADMA%u: unable to register: %d\n",
+                                        chan, ret);
+                }
         }
 }
diff --git a/arch/arm/kernel/dma.c b/arch/arm/kernel/dma.c
index d006085ed7e7..7d5b9fb01e71 100644
--- a/arch/arm/kernel/dma.c
+++ b/arch/arm/kernel/dma.c
@@ -15,6 +15,7 @@
 #include <linux/init.h>
 #include <linux/spinlock.h>
 #include <linux/errno.h>
+#include <linux/scatterlist.h>
 
 #include <asm/dma.h>
 
@@ -23,19 +24,40 @@
 DEFINE_SPINLOCK(dma_spin_lock);
 EXPORT_SYMBOL(dma_spin_lock);
 
-static dma_t dma_chan[MAX_DMA_CHANNELS];
+static dma_t *dma_chan[MAX_DMA_CHANNELS];
+
+static inline dma_t *dma_channel(unsigned int chan)
+{
+        if (chan >= MAX_DMA_CHANNELS)
+                return NULL;
+
+        return dma_chan[chan];
+}
+
+int __init isa_dma_add(unsigned int chan, dma_t *dma)
+{
+        if (!dma->d_ops)
+                return -EINVAL;
+
+        sg_init_table(&dma->buf, 1);
+
+        if (dma_chan[chan])
+                return -EBUSY;
+        dma_chan[chan] = dma;
+        return 0;
+}
 
 /*
  * Request DMA channel
  *
  * On certain platforms, we have to allocate an interrupt as well...
  */
-int request_dma(dmach_t channel, const char *device_id)
+int request_dma(unsigned int chan, const char *device_id)
 {
-        dma_t *dma = dma_chan + channel;
+        dma_t *dma = dma_channel(chan);
         int ret;
 
-        if (channel >= MAX_DMA_CHANNELS || !dma->d_ops)
+        if (!dma)
                 goto bad_dma;
 
         if (xchg(&dma->lock, 1) != 0)
@@ -47,7 +69,7 @@ int request_dma(dmach_t channel, const char *device_id)
 
         ret = 0;
         if (dma->d_ops->request)
-                ret = dma->d_ops->request(channel, dma);
+                ret = dma->d_ops->request(chan, dma);
 
         if (ret)
                 xchg(&dma->lock, 0);
@@ -55,7 +77,7 @@ int request_dma(dmach_t channel, const char *device_id)
         return ret;
 
 bad_dma:
-        printk(KERN_ERR "dma: trying to allocate DMA%d\n", channel);
+        printk(KERN_ERR "dma: trying to allocate DMA%d\n", chan);
         return -EINVAL;
 
 busy:
@@ -68,42 +90,42 @@ EXPORT_SYMBOL(request_dma);
  *
  * On certain platforms, we have to free interrupt as well...
  */
-void free_dma(dmach_t channel)
+void free_dma(unsigned int chan)
 {
-        dma_t *dma = dma_chan + channel;
+        dma_t *dma = dma_channel(chan);
 
-        if (channel >= MAX_DMA_CHANNELS || !dma->d_ops)
+        if (!dma)
                 goto bad_dma;
 
         if (dma->active) {
-                printk(KERN_ERR "dma%d: freeing active DMA\n", channel);
-                dma->d_ops->disable(channel, dma);
+                printk(KERN_ERR "dma%d: freeing active DMA\n", chan);
+                dma->d_ops->disable(chan, dma);
                 dma->active = 0;
         }
 
         if (xchg(&dma->lock, 0) != 0) {
                 if (dma->d_ops->free)
-                        dma->d_ops->free(channel, dma);
+                        dma->d_ops->free(chan, dma);
                 return;
         }
 
-        printk(KERN_ERR "dma%d: trying to free free DMA\n", channel);
+        printk(KERN_ERR "dma%d: trying to free free DMA\n", chan);
         return;
 
 bad_dma:
-        printk(KERN_ERR "dma: trying to free DMA%d\n", channel);
+        printk(KERN_ERR "dma: trying to free DMA%d\n", chan);
 }
 EXPORT_SYMBOL(free_dma);
 
 /* Set DMA Scatter-Gather list
  */
-void set_dma_sg (dmach_t channel, struct scatterlist *sg, int nr_sg)
+void set_dma_sg (unsigned int chan, struct scatterlist *sg, int nr_sg)
 {
-        dma_t *dma = dma_chan + channel;
+        dma_t *dma = dma_channel(chan);
 
         if (dma->active)
                 printk(KERN_ERR "dma%d: altering DMA SG while "
-                       "DMA active\n", channel);
+                       "DMA active\n", chan);
 
         dma->sg = sg;
         dma->sgcount = nr_sg;
@@ -115,13 +137,13 @@ EXPORT_SYMBOL(set_dma_sg);
  *
  * Copy address to the structure, and set the invalid bit
  */
-void __set_dma_addr (dmach_t channel, void *addr)
+void __set_dma_addr (unsigned int chan, void *addr)
 {
-        dma_t *dma = dma_chan + channel;
+        dma_t *dma = dma_channel(chan);
 
         if (dma->active)
                 printk(KERN_ERR "dma%d: altering DMA address while "
-                       "DMA active\n", channel);
+                       "DMA active\n", chan);
 
         dma->sg = NULL;
         dma->addr = addr;
@@ -133,13 +155,13 @@ EXPORT_SYMBOL(__set_dma_addr);
  *
  * Copy address to the structure, and set the invalid bit
  */
-void set_dma_count (dmach_t channel, unsigned long count)
+void set_dma_count (unsigned int chan, unsigned long count)
 {
-        dma_t *dma = dma_chan + channel;
+        dma_t *dma = dma_channel(chan);
 
         if (dma->active)
                 printk(KERN_ERR "dma%d: altering DMA count while "
-                       "DMA active\n", channel);
+                       "DMA active\n", chan);
 
         dma->sg = NULL;
         dma->count = count;
@@ -149,13 +171,13 @@ EXPORT_SYMBOL(set_dma_count);
 
 /* Set DMA direction mode
  */
-void set_dma_mode (dmach_t channel, dmamode_t mode)
+void set_dma_mode (unsigned int chan, unsigned int mode)
 {
-        dma_t *dma = dma_chan + channel;
+        dma_t *dma = dma_channel(chan);
 
         if (dma->active)
                 printk(KERN_ERR "dma%d: altering DMA mode while "
-                       "DMA active\n", channel);
+                       "DMA active\n", chan);
 
         dma->dma_mode = mode;
         dma->invalid = 1;
@@ -164,42 +186,42 @@ EXPORT_SYMBOL(set_dma_mode);
 
 /* Enable DMA channel
  */
-void enable_dma (dmach_t channel)
+void enable_dma (unsigned int chan)
 {
-        dma_t *dma = dma_chan + channel;
+        dma_t *dma = dma_channel(chan);
 
         if (!dma->lock)
                 goto free_dma;
 
         if (dma->active == 0) {
                 dma->active = 1;
-                dma->d_ops->enable(channel, dma);
+                dma->d_ops->enable(chan, dma);
         }
         return;
 
 free_dma:
-        printk(KERN_ERR "dma%d: trying to enable free DMA\n", channel);
+        printk(KERN_ERR "dma%d: trying to enable free DMA\n", chan);
         BUG();
 }
 EXPORT_SYMBOL(enable_dma);
 
 /* Disable DMA channel
  */
-void disable_dma (dmach_t channel)
+void disable_dma (unsigned int chan)
 {
-        dma_t *dma = dma_chan + channel;
+        dma_t *dma = dma_channel(chan);
 
         if (!dma->lock)
                 goto free_dma;
 
         if (dma->active == 1) {
                 dma->active = 0;
-                dma->d_ops->disable(channel, dma);
+                dma->d_ops->disable(chan, dma);
         }
         return;
 
 free_dma:
-        printk(KERN_ERR "dma%d: trying to disable free DMA\n", channel);
+        printk(KERN_ERR "dma%d: trying to disable free DMA\n", chan);
         BUG();
 }
 EXPORT_SYMBOL(disable_dma);
@@ -207,45 +229,38 @@ EXPORT_SYMBOL(disable_dma);
 /*
  * Is the specified DMA channel active?
  */
-int dma_channel_active(dmach_t channel)
+int dma_channel_active(unsigned int chan)
 {
-        return dma_chan[channel].active;
+        dma_t *dma = dma_channel(chan);
+        return dma->active;
 }
 EXPORT_SYMBOL(dma_channel_active);
 
-void set_dma_page(dmach_t channel, char pagenr)
+void set_dma_page(unsigned int chan, char pagenr)
 {
-        printk(KERN_ERR "dma%d: trying to set_dma_page\n", channel);
+        printk(KERN_ERR "dma%d: trying to set_dma_page\n", chan);
 }
 EXPORT_SYMBOL(set_dma_page);
 
-void set_dma_speed(dmach_t channel, int cycle_ns)
+void set_dma_speed(unsigned int chan, int cycle_ns)
 {
-        dma_t *dma = dma_chan + channel;
+        dma_t *dma = dma_channel(chan);
         int ret = 0;
 
         if (dma->d_ops->setspeed)
-                ret = dma->d_ops->setspeed(channel, dma, cycle_ns);
+                ret = dma->d_ops->setspeed(chan, dma, cycle_ns);
         dma->speed = ret;
 }
 EXPORT_SYMBOL(set_dma_speed);
 
-int get_dma_residue(dmach_t channel)
+int get_dma_residue(unsigned int chan)
 {
-        dma_t *dma = dma_chan + channel;
+        dma_t *dma = dma_channel(chan);
         int ret = 0;
 
         if (dma->d_ops->residue)
-                ret = dma->d_ops->residue(channel, dma);
+                ret = dma->d_ops->residue(chan, dma);
 
         return ret;
 }
 EXPORT_SYMBOL(get_dma_residue);
-
-static int __init init_dma(void)
-{
-        arch_dma_init(dma_chan);
-        return 0;
-}
-
-core_initcall(init_dma);
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 85040cfeb5e5..d662a2f1fd85 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -20,6 +20,7 @@
 #include <asm/vfpmacros.h>
 #include <mach/entry-macro.S>
 #include <asm/thread_notify.h>
+#include <asm/unwind.h>
 
 #include "entry-header.S"
 
@@ -123,6 +124,8 @@ ENDPROC(__und_invalid)
 #endif
 
         .macro  svc_entry, stack_hole=0
+ UNWIND(.fnstart                )
+ UNWIND(.save {r0 - pc}         )
         sub     sp, sp, #(S_FRAME_SIZE + \stack_hole)
  SPFIX( tst     sp, #4          )
  SPFIX( bicne   sp, sp, #4      )
@@ -196,6 +199,7 @@ __dabt_svc:
         ldr     r0, [sp, #S_PSR]
         msr     spsr_cxsf, r0
         ldmia   sp, {r0 - pc}^                  @ load r0 - pc, cpsr
+ UNWIND(.fnend          )
 ENDPROC(__dabt_svc)
 
         .align  5
@@ -228,6 +232,7 @@ __irq_svc:
         bleq    trace_hardirqs_on
 #endif
         ldmia   sp, {r0 - pc}^                  @ load r0 - pc, cpsr
+ UNWIND(.fnend          )
 ENDPROC(__irq_svc)
 
         .ltorg
@@ -278,6 +283,7 @@ __und_svc:
         ldr     lr, [sp, #S_PSR]                @ Get SVC cpsr
         msr     spsr_cxsf, lr
         ldmia   sp, {r0 - pc}^                  @ Restore SVC registers
+ UNWIND(.fnend          )
 ENDPROC(__und_svc)
 
         .align  5
@@ -320,6 +326,7 @@ __pabt_svc:
         ldr     r0, [sp, #S_PSR]
         msr     spsr_cxsf, r0
         ldmia   sp, {r0 - pc}^                  @ load r0 - pc, cpsr
+ UNWIND(.fnend          )
 ENDPROC(__pabt_svc)
 
         .align  5
@@ -343,6 +350,8 @@ ENDPROC(__pabt_svc)
 #endif
 
         .macro  usr_entry
+ UNWIND(.fnstart        )
+ UNWIND(.cantunwind     )       @ don't unwind the user space
         sub     sp, sp, #S_FRAME_SIZE
         stmib   sp, {r1 - r12}
 
@@ -420,6 +429,7 @@ __dabt_usr:
         mov     r2, sp
         adr     lr, ret_from_exception
         b       do_DataAbort
+ UNWIND(.fnend          )
 ENDPROC(__dabt_usr)
 
         .align  5
@@ -450,6 +460,7 @@ __irq_usr:
 
         mov     why, #0
         b       ret_to_user
+ UNWIND(.fnend          )
 ENDPROC(__irq_usr)
 
         .ltorg
@@ -484,6 +495,7 @@ __und_usr:
 #else
         b       __und_usr_unknown
 #endif
+ UNWIND(.fnend          )
 ENDPROC(__und_usr)
 
         @
@@ -671,14 +683,18 @@ __pabt_usr:
         enable_irq                              @ Enable interrupts
         mov     r1, sp                          @ regs
         bl      do_PrefetchAbort                @ call abort handler
+ UNWIND(.fnend          )
         /* fall through */
 /*
  * This is the return code to user mode for abort handlers
  */
 ENTRY(ret_from_exception)
+ UNWIND(.fnstart        )
+ UNWIND(.cantunwind     )
         get_thread_info tsk
         mov     why, #0
         b       ret_to_user
+ UNWIND(.fnend          )
 ENDPROC(__pabt_usr)
 ENDPROC(ret_from_exception)
 
@@ -688,6 +704,8 @@ ENDPROC(ret_from_exception)
  * previous and next are guaranteed not to be the same.
  */
 ENTRY(__switch_to)
+ UNWIND(.fnstart        )
+ UNWIND(.cantunwind     )
         add     ip, r1, #TI_CPU_SAVE
         ldr     r3, [r2, #TI_TP_VALUE]
         stmia   ip!, {r4 - sl, fp, sp, lr}      @ Store most regs on stack
@@ -717,6 +735,7 @@ ENTRY(__switch_to)
         bl      atomic_notifier_call_chain
         mov     r0, r5
         ldmia   r4, {r4 - sl, fp, sp, pc}       @ Load all regs saved previously
+ UNWIND(.fnend          )
 ENDPROC(__switch_to)
 
         __INIT
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 159d0416f270..b55cb0331809 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -11,6 +11,7 @@
 #include <asm/unistd.h>
 #include <asm/ftrace.h>
 #include <mach/entry-macro.S>
+#include <asm/unwind.h>
 
 #include "entry-header.S"
 
@@ -22,6 +23,8 @@
  * stack.
  */
 ret_fast_syscall:
+ UNWIND(.fnstart        )
+ UNWIND(.cantunwind     )
         disable_irq                             @ disable interrupts
         ldr     r1, [tsk, #TI_FLAGS]
         tst     r1, #_TIF_WORK_MASK
@@ -38,6 +41,7 @@ ret_fast_syscall:
         mov     r0, r0
         add     sp, sp, #S_FRAME_SIZE - S_PC
         movs    pc, lr                          @ return & move spsr_svc into cpsr
+ UNWIND(.fnend          )
 
 /*
  * Ok, we need to do extra processing, enter the slow path.
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index dab48f27263f..d1731e39b496 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -22,6 +22,7 @@
 
 #include <asm/pgtable.h>
 #include <asm/sections.h>
+#include <asm/unwind.h>
 
 #ifdef CONFIG_XIP_KERNEL
 /*
@@ -66,6 +67,24 @@ int module_frob_arch_sections(Elf_Ehdr *hdr,
                               char *secstrings,
                               struct module *mod)
 {
+#ifdef CONFIG_ARM_UNWIND
+        Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum;
+
+        for (s = sechdrs; s < sechdrs_end; s++) {
+                if (strcmp(".ARM.exidx.init.text", secstrings + s->sh_name) == 0)
+                        mod->arch.unw_sec_init = s;
+                else if (strcmp(".ARM.exidx.devinit.text", secstrings + s->sh_name) == 0)
+                        mod->arch.unw_sec_devinit = s;
+                else if (strcmp(".ARM.exidx", secstrings + s->sh_name) == 0)
+                        mod->arch.unw_sec_core = s;
+                else if (strcmp(".init.text", secstrings + s->sh_name) == 0)
+                        mod->arch.sec_init_text = s;
+                else if (strcmp(".devinit.text", secstrings + s->sh_name) == 0)
+                        mod->arch.sec_devinit_text = s;
+                else if (strcmp(".text", secstrings + s->sh_name) == 0)
+                        mod->arch.sec_core_text = s;
+        }
+#endif
         return 0;
 }
 
@@ -104,6 +123,10 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
                 loc = dstsec->sh_addr + rel->r_offset;
 
                 switch (ELF32_R_TYPE(rel->r_info)) {
+                case R_ARM_NONE:
+                        /* ignore */
+                        break;
+
                 case R_ARM_ABS32:
                         *(u32 *)loc += sym->st_value;
                         break;
@@ -132,6 +155,20 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
                         *(u32 *)loc |= offset & 0x00ffffff;
                         break;
 
+               case R_ARM_V4BX:
+                       /* Preserve Rm and the condition code. Alter
+                        * other bits to re-code instruction as
+                        * MOV PC,Rm.
+                        */
+                       *(u32 *)loc &= 0xf000000f;
+                       *(u32 *)loc |= 0x01a0f000;
+                       break;
+
+                case R_ARM_PREL31:
+                        offset = *(u32 *)loc + sym->st_value - loc;
+                        *(u32 *)loc = offset & 0x7fffffff;
+                        break;
+
                 default:
                         printk(KERN_ERR "%s: unknown relocation: %u\n",
                                module->name, ELF32_R_TYPE(rel->r_info));
@@ -150,14 +187,50 @@ apply_relocate_add(Elf32_Shdr *sechdrs, const char *strtab,
         return -ENOEXEC;
 }
 
+#ifdef CONFIG_ARM_UNWIND
+static void register_unwind_tables(struct module *mod)
+{
+        if (mod->arch.unw_sec_init && mod->arch.sec_init_text)
+                mod->arch.unwind_init =
+                        unwind_table_add(mod->arch.unw_sec_init->sh_addr,
+                                         mod->arch.unw_sec_init->sh_size,
+                                         mod->arch.sec_init_text->sh_addr,
+                                         mod->arch.sec_init_text->sh_size);
+        if (mod->arch.unw_sec_devinit && mod->arch.sec_devinit_text)
+                mod->arch.unwind_devinit =
+                        unwind_table_add(mod->arch.unw_sec_devinit->sh_addr,
+                                         mod->arch.unw_sec_devinit->sh_size,
+                                         mod->arch.sec_devinit_text->sh_addr,
+                                         mod->arch.sec_devinit_text->sh_size);
+        if (mod->arch.unw_sec_core && mod->arch.sec_core_text)
+                mod->arch.unwind_core =
+                        unwind_table_add(mod->arch.unw_sec_core->sh_addr,
+                                         mod->arch.unw_sec_core->sh_size,
+                                         mod->arch.sec_core_text->sh_addr,
+                                         mod->arch.sec_core_text->sh_size);
+}
+
+static void unregister_unwind_tables(struct module *mod)
+{
+        unwind_table_del(mod->arch.unwind_init);
+        unwind_table_del(mod->arch.unwind_devinit);
+        unwind_table_del(mod->arch.unwind_core);
+}
+#else
+static inline void register_unwind_tables(struct module *mod) { }
+static inline void unregister_unwind_tables(struct module *mod) { }
+#endif
+
 int
 module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
                 struct module *module)
 {
+        register_unwind_tables(module);
         return 0;
 }
 
 void
 module_arch_cleanup(struct module *mod)
 {
+        unregister_unwind_tables(mod);
 }
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index d3ea6fa89521..2de14e2afdc5 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -34,6 +34,7 @@
 #include <asm/processor.h>
 #include <asm/system.h>
 #include <asm/thread_notify.h>
+#include <asm/stacktrace.h>
 #include <asm/mach/time.h>
 
 static const char *processor_modes[] = {
@@ -82,7 +83,7 @@ static int __init hlt_setup(char *__unused)
 __setup("nohlt", nohlt_setup);
 __setup("hlt", hlt_setup);
 
-void arm_machine_restart(char mode)
+void arm_machine_restart(char mode, const char *cmd)
 {
         /*
          * Clean and disable cache, and turn off interrupts
@@ -99,7 +100,7 @@ void arm_machine_restart(char mode)
         /*
          * Now call the architecture specific reboot code.
          */
-        arch_reset(mode);
+        arch_reset(mode, cmd);
 
         /*
          * Whoops - the architecture was unable to reboot.
@@ -119,7 +120,7 @@ EXPORT_SYMBOL(pm_idle);
 void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
-void (*arm_pm_restart)(char str) = arm_machine_restart;
+void (*arm_pm_restart)(char str, const char *cmd) = arm_machine_restart;
 EXPORT_SYMBOL_GPL(arm_pm_restart);
 
 
@@ -194,9 +195,9 @@ void machine_power_off(void)
                 pm_power_off();
 }
 
-void machine_restart(char * __unused)
+void machine_restart(char *cmd)
 {
-        arm_pm_restart(reboot_mode);
+        arm_pm_restart(reboot_mode, cmd);
 }
 
 void __show_regs(struct pt_regs *regs)
@@ -372,23 +373,21 @@ EXPORT_SYMBOL(kernel_thread);
 
 unsigned long get_wchan(struct task_struct *p)
 {
-        unsigned long fp, lr;
-        unsigned long stack_start, stack_end;
+        struct stackframe frame;
         int count = 0;
         if (!p || p == current || p->state == TASK_RUNNING)
                 return 0;
 
-        stack_start = (unsigned long)end_of_stack(p);
-        stack_end = (unsigned long)task_stack_page(p) + THREAD_SIZE;
-
-        fp = thread_saved_fp(p);
+        frame.fp = thread_saved_fp(p);
+        frame.sp = thread_saved_sp(p);
+        frame.lr = 0;                   /* recovered from the stack */
+        frame.pc = thread_saved_pc(p);
         do {
-                if (fp < stack_start || fp > stack_end)
+                int ret = unwind_frame(&frame);
+                if (ret < 0)
                         return 0;
-                lr = ((unsigned long *)fp)[-1];
-                if (!in_sched_functions(lr))
-                        return lr;
-                fp = *(unsigned long *) (fp - 12);
+                if (!in_sched_functions(frame.pc))
+                        return frame.pc;
         } while (count ++ < 16);
         return 0;
 }
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index df653ea59250..89882a1d0187 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -653,6 +653,54 @@ static int ptrace_setcrunchregs(struct task_struct *tsk, void __user *ufp)
 }
 #endif
 
+#ifdef CONFIG_VFP
+/*
+ * Get the child VFP state.
+ */
+static int ptrace_getvfpregs(struct task_struct *tsk, void __user *data)
+{
+        struct thread_info *thread = task_thread_info(tsk);
+        union vfp_state *vfp = &thread->vfpstate;
+        struct user_vfp __user *ufp = data;
+
+        vfp_sync_state(thread);
+
+        /* copy the floating point registers */
+        if (copy_to_user(&ufp->fpregs, &vfp->hard.fpregs,
+                         sizeof(vfp->hard.fpregs)))
+                return -EFAULT;
+
+        /* copy the status and control register */
+        if (put_user(vfp->hard.fpscr, &ufp->fpscr))
+                return -EFAULT;
+
+        return 0;
+}
+
+/*
+ * Set the child VFP state.
+ */
+static int ptrace_setvfpregs(struct task_struct *tsk, void __user *data)
+{
+        struct thread_info *thread = task_thread_info(tsk);
+        union vfp_state *vfp = &thread->vfpstate;
+        struct user_vfp __user *ufp = data;
+
+        vfp_sync_state(thread);
+
+        /* copy the floating point registers */
+        if (copy_from_user(&vfp->hard.fpregs, &ufp->fpregs,
+                           sizeof(vfp->hard.fpregs)))
+                return -EFAULT;
+
+        /* copy the status and control register */
+        if (get_user(vfp->hard.fpscr, &ufp->fpscr))
+                return -EFAULT;
+
+        return 0;
+}
+#endif
+
 long arch_ptrace(struct task_struct *child, long request, long addr, long data)
 {
         int ret;
@@ -775,6 +823,16 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                         break;
 #endif
 
+#ifdef CONFIG_VFP
+                case PTRACE_GETVFPREGS:
+                        ret = ptrace_getvfpregs(child, (void __user *)data);
+                        break;
+
+                case PTRACE_SETVFPREGS:
+                        ret = ptrace_setvfpregs(child, (void __user *)data);
+                        break;
+#endif
+
                 default:
                         ret = ptrace_request(child, request, addr, data);
                         break;
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 68d6494c0389..bc5e4128f9f3 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -40,6 +40,7 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
 #include <asm/traps.h>
+#include <asm/unwind.h>
 
 #include "compat.h"
 #include "atags.h"
@@ -685,6 +686,8 @@ void __init setup_arch(char **cmdline_p)
         struct machine_desc *mdesc;
         char *from = default_command_line;
 
+        unwind_init();
+
         setup_processor();
         mdesc = setup_machine(machine_arch_type);
         machine_name = mdesc->name;
@@ -780,6 +783,8 @@ static const char *hwcap_str[] = {
         "crunch",
         "thumbee",
         "neon",
+        "vfpv3",
+        "vfpv3d16",
         NULL
 };
 
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 55fa7ff96a3e..7801aac3c043 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -93,6 +93,7 @@ int __cpuinit __cpu_up(unsigned int cpu)
         pmd = pmd_offset(pgd + pgd_index(PHYS_OFFSET), PHYS_OFFSET);
         *pmd = __pmd((PHYS_OFFSET & PGDIR_MASK) |
                      PMD_TYPE_SECT | PMD_SECT_AP_WRITE);
+        flush_pmd_entry(pmd);
 
         /*
          * We need to tell the secondary core where to find
@@ -130,6 +131,7 @@ int __cpuinit __cpu_up(unsigned int cpu)
         secondary_data.pgdir = 0;
 
         *pmd = __pmd(0);
+        clean_pmd_entry(pmd);
         pgd_free(&init_mm, pgd);
 
         if (ret) {
diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c
index fc650f64df43..9f444e5cc165 100644
--- a/arch/arm/kernel/stacktrace.c
+++ b/arch/arm/kernel/stacktrace.c
@@ -2,35 +2,60 @@
 #include <linux/sched.h>
 #include <linux/stacktrace.h>
 
-#include "stacktrace.h"
-
-int walk_stackframe(unsigned long fp, unsigned long low, unsigned long high,
-                    int (*fn)(struct stackframe *, void *), void *data)
+#include <asm/stacktrace.h>
+
+#if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND)
+/*
+ * Unwind the current stack frame and store the new register values in the
+ * structure passed as argument. Unwinding is equivalent to a function return,
+ * hence the new PC value rather than LR should be used for backtrace.
+ *
+ * With framepointer enabled, a simple function prologue looks like this:
+ *      mov     ip, sp
+ *      stmdb   sp!, {fp, ip, lr, pc}
+ *      sub     fp, ip, #4
+ *
+ * A simple function epilogue looks like this:
+ *      ldm     sp, {fp, sp, pc}
+ *
+ * Note that with framepointer enabled, even the leaf functions have the same
+ * prologue and epilogue, therefore we can ignore the LR value in this case.
+ */
+int unwind_frame(struct stackframe *frame)
 {
-        struct stackframe *frame;
-
-        do {
-                /*
-                 * Check current frame pointer is within bounds
-                 */
-                if (fp < (low + 12) || fp + 4 >= high)
-                        break;
+        unsigned long high, low;
+        unsigned long fp = frame->fp;
 
-                frame = (struct stackframe *)(fp - 12);
+        /* only go to a higher address on the stack */
+        low = frame->sp;
+        high = ALIGN(low, THREAD_SIZE) + THREAD_SIZE;
 
-                if (fn(frame, data))
-                        break;
+        /* check current frame pointer is within bounds */
+        if (fp < (low + 12) || fp + 4 >= high)
+                return -EINVAL;
 
-                /*
-                 * Update the low bound - the next frame must always
-                 * be at a higher address than the current frame.
-                 */
-                low = fp + 4;
-                fp = frame->fp;
-        } while (fp);
+        /* restore the registers from the stack frame */
+        frame->fp = *(unsigned long *)(fp - 12);
+        frame->sp = *(unsigned long *)(fp - 8);
+        frame->pc = *(unsigned long *)(fp - 4);
 
         return 0;
 }
+#endif
+
+void walk_stackframe(struct stackframe *frame,
+                     int (*fn)(struct stackframe *, void *), void *data)
+{
+        while (1) {
+                int ret;
+
+                if (fn(frame, data))
+                        break;
+                ret = unwind_frame(frame);
+                if (ret < 0)
+                        break;
+        }
+}
 EXPORT_SYMBOL(walk_stackframe);
 
 #ifdef CONFIG_STACKTRACE
@@ -44,7 +69,7 @@ static int save_trace(struct stackframe *frame, void *d)
 {
         struct stack_trace_data *data = d;
         struct stack_trace *trace = data->trace;
-        unsigned long addr = frame->lr;
+        unsigned long addr = frame->pc;
 
         if (data->no_sched_functions && in_sched_functions(addr))
                 return 0;
@@ -61,11 +86,10 @@ static int save_trace(struct stackframe *frame, void *d)
 void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
 {
         struct stack_trace_data data;
-        unsigned long fp, base;
+        struct stackframe frame;
 
         data.trace = trace;
         data.skip = trace->skip;
-        base = (unsigned long)task_stack_page(tsk);
 
         if (tsk != current) {
 #ifdef CONFIG_SMP
@@ -76,14 +100,22 @@ void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
                 BUG();
 #else
                 data.no_sched_functions = 1;
-                fp = thread_saved_fp(tsk);
+                frame.fp = thread_saved_fp(tsk);
+                frame.sp = thread_saved_sp(tsk);
+                frame.lr = 0;           /* recovered from the stack */
+                frame.pc = thread_saved_pc(tsk);
 #endif
         } else {
+                register unsigned long current_sp asm ("sp");
+
                 data.no_sched_functions = 0;
-                asm("mov %0, fp" : "=r" (fp));
+                frame.fp = (unsigned long)__builtin_frame_address(0);
+                frame.sp = current_sp;
+                frame.lr = (unsigned long)__builtin_return_address(0);
+                frame.pc = (unsigned long)save_stack_trace_tsk;
         }
 
-        walk_stackframe(fp, base, base + THREAD_SIZE, save_trace, &data);
+        walk_stackframe(&frame, save_trace, &data);
         if (trace->nr_entries < trace->max_entries)
                 trace->entries[trace->nr_entries++] = ULONG_MAX;
 }
diff --git a/arch/arm/kernel/stacktrace.h b/arch/arm/kernel/stacktrace.h
deleted file mode 100644
index e9fd20cb5662..000000000000
--- a/arch/arm/kernel/stacktrace.h
+++ /dev/null
@@ -1,9 +0,0 @@
-struct stackframe {
-        unsigned long fp;
-        unsigned long sp;
-        unsigned long lr;
-        unsigned long pc;
-};
-
-int walk_stackframe(unsigned long fp, unsigned long low, unsigned long high,
-                    int (*fn)(struct stackframe *, void *), void *data);
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index c68b44aa88d2..4cdc4a0bd02d 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -33,6 +33,7 @@
 
 #include <asm/leds.h>
 #include <asm/thread_info.h>
+#include <asm/stacktrace.h>
 #include <asm/mach/time.h>
 
 /*
@@ -55,14 +56,22 @@ EXPORT_SYMBOL(rtc_lock);
 #ifdef CONFIG_SMP
 unsigned long profile_pc(struct pt_regs *regs)
 {
-        unsigned long fp, pc = instruction_pointer(regs);
+        struct stackframe frame;
 
-        if (in_lock_functions(pc)) {
-                fp = regs->ARM_fp;
-                pc = ((unsigned long *)fp)[-1];
-        }
+        if (!in_lock_functions(regs->ARM_pc))
+                return regs->ARM_pc;
+
+        frame.fp = regs->ARM_fp;
+        frame.sp = regs->ARM_sp;
+        frame.lr = regs->ARM_lr;
+        frame.pc = regs->ARM_pc;
+        do {
+                int ret = unwind_frame(&frame);
+                if (ret < 0)
+                        return 0;
+        } while (in_lock_functions(frame.pc));
 
-        return pc;
+        return frame.pc;
 }
 EXPORT_SYMBOL(profile_pc);
 #endif
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 79abc4ddc0cf..57eb0f6f6005 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -27,6 +27,7 @@
 #include <asm/system.h>
 #include <asm/unistd.h>
 #include <asm/traps.h>
+#include <asm/unwind.h>
 
 #include "ptrace.h"
 #include "signal.h"
@@ -61,6 +62,7 @@ void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long
                 dump_mem("Exception stack", frame + 4, frame + 4 + sizeof(struct pt_regs));
 }
 
+#ifndef CONFIG_ARM_UNWIND
 /*
  * Stack pointers should always be within the kernels view of
  * physical memory.  If it is not there, then we can't dump
@@ -74,6 +76,7 @@ static int verify_stack(unsigned long sp)
 
         return 0;
 }
+#endif
 
 /*
  * Dump out the contents of some memory nicely...
@@ -150,13 +153,33 @@ static void dump_instr(struct pt_regs *regs)
         set_fs(fs);
 }
 
+#ifdef CONFIG_ARM_UNWIND
+static inline void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
+{
+        unwind_backtrace(regs, tsk);
+}
+#else
 static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
 {
-        unsigned int fp;
+        unsigned int fp, mode;
         int ok = 1;
 
         printk("Backtrace: ");
-        fp = regs->ARM_fp;
+
+        if (!tsk)
+                tsk = current;
+
+        if (regs) {
+                fp = regs->ARM_fp;
+                mode = processor_mode(regs);
+        } else if (tsk != current) {
+                fp = thread_saved_fp(tsk);
+                mode = 0x10;
+        } else {
+                asm("mov %0, fp" : "=r" (fp) : : "cc");
+                mode = 0x10;
+        }
+
         if (!fp) {
                 printk("no frame pointer");
                 ok = 0;
@@ -168,29 +191,20 @@ static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
         printk("\n");
 
         if (ok)
-                c_backtrace(fp, processor_mode(regs));
+                c_backtrace(fp, mode);
 }
+#endif
 
 void dump_stack(void)
 {
-        __backtrace();
+        dump_backtrace(NULL, NULL);
 }
 
 EXPORT_SYMBOL(dump_stack);
 
 void show_stack(struct task_struct *tsk, unsigned long *sp)
 {
-        unsigned long fp;
-
-        if (!tsk)
-                tsk = current;
-
-        if (tsk != current)
-                fp = thread_saved_fp(tsk);
-        else
-                asm("mov %0, fp" : "=r" (fp) : : "cc");
-
-        c_backtrace(fp, 0x10);
+        dump_backtrace(NULL, tsk);
         barrier();
 }
 
diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c
new file mode 100644
index 000000000000..1dedc2c7ff49
--- /dev/null
+++ b/arch/arm/kernel/unwind.c
@@ -0,0 +1,434 @@
+/*
+ * arch/arm/kernel/unwind.c
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ *
+ * Stack unwinding support for ARM
+ *
+ * An ARM EABI version of gcc is required to generate the unwind
+ * tables. For information about the structure of the unwind tables,
+ * see "Exception Handling ABI for the ARM Architecture" at:
+ *
+ * http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/list.h>
+
+#include <asm/stacktrace.h>
+#include <asm/traps.h>
+#include <asm/unwind.h>
+
+/* Dummy functions to avoid linker complaints */
+void __aeabi_unwind_cpp_pr0(void)
+{
+};
+EXPORT_SYMBOL(__aeabi_unwind_cpp_pr0);
+
+void __aeabi_unwind_cpp_pr1(void)
+{
+};
+EXPORT_SYMBOL(__aeabi_unwind_cpp_pr1);
+
+void __aeabi_unwind_cpp_pr2(void)
+{
+};
+EXPORT_SYMBOL(__aeabi_unwind_cpp_pr2);
+
+struct unwind_ctrl_block {
+        unsigned long vrs[16];          /* virtual register set */
+        unsigned long *insn;            /* pointer to the current instructions word */
+        int entries;                    /* number of entries left to interpret */
+        int byte;                       /* current byte number in the instructions word */
+};
+
+enum regs {
+        FP = 11,
+        SP = 13,
+        LR = 14,
+        PC = 15
+};
+
+extern struct unwind_idx __start_unwind_idx[];
+extern struct unwind_idx __stop_unwind_idx[];
+
+static DEFINE_SPINLOCK(unwind_lock);
+static LIST_HEAD(unwind_tables);
+
+/* Convert a prel31 symbol to an absolute address */
+#define prel31_to_addr(ptr)                             \
+({                                                      \
+        /* sign-extend to 32 bits */                    \
+        long offset = (((long)*(ptr)) << 1) >> 1;       \
+        (unsigned long)(ptr) + offset;                  \
+})
+
+/*
+ * Binary search in the unwind index. The entries entries are
+ * guaranteed to be sorted in ascending order by the linker.
+ */
+static struct unwind_idx *search_index(unsigned long addr,
+                                       struct unwind_idx *first,
+                                       struct unwind_idx *last)
+{
+        pr_debug("%s(%08lx, %p, %p)\n", __func__, addr, first, last);
+
+        if (addr < first->addr) {
+                pr_warning("unwind: Unknown symbol address %08lx\n", addr);
+                return NULL;
+        } else if (addr >= last->addr)
+                return last;
+
+        while (first < last - 1) {
+                struct unwind_idx *mid = first + ((last - first + 1) >> 1);
+
+                if (addr < mid->addr)
+                        last = mid;
+                else
+                        first = mid;
+        }
+
+        return first;
+}
+
+static struct unwind_idx *unwind_find_idx(unsigned long addr)
+{
+        struct unwind_idx *idx = NULL;
+        unsigned long flags;
+
+        pr_debug("%s(%08lx)\n", __func__, addr);
+
+        if (core_kernel_text(addr))
+                /* main unwind table */
+                idx = search_index(addr, __start_unwind_idx,
+                                   __stop_unwind_idx - 1);
+        else {
+                /* module unwind tables */
+                struct unwind_table *table;
+
+                spin_lock_irqsave(&unwind_lock, flags);
+                list_for_each_entry(table, &unwind_tables, list) {
+                        if (addr >= table->begin_addr &&
+                            addr < table->end_addr) {
+                                idx = search_index(addr, table->start,
+                                                   table->stop - 1);
+                                break;
+                        }
+                }
+                spin_unlock_irqrestore(&unwind_lock, flags);
+        }
+
+        pr_debug("%s: idx = %p\n", __func__, idx);
+        return idx;
+}
+
+static unsigned long unwind_get_byte(struct unwind_ctrl_block *ctrl)
+{
+        unsigned long ret;
+
+        if (ctrl->entries <= 0) {
+                pr_warning("unwind: Corrupt unwind table\n");
+                return 0;
+        }
+
+        ret = (*ctrl->insn >> (ctrl->byte * 8)) & 0xff;
+
+        if (ctrl->byte == 0) {
+                ctrl->insn++;
+                ctrl->entries--;
+                ctrl->byte = 3;
+        } else
+                ctrl->byte--;
+
+        return ret;
+}
+
+/*
+ * Execute the current unwind instruction.
+ */
+static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
+{
+        unsigned long insn = unwind_get_byte(ctrl);
+
+        pr_debug("%s: insn = %08lx\n", __func__, insn);
+
+        if ((insn & 0xc0) == 0x00)
+                ctrl->vrs[SP] += ((insn & 0x3f) << 2) + 4;
+        else if ((insn & 0xc0) == 0x40)
+                ctrl->vrs[SP] -= ((insn & 0x3f) << 2) + 4;
+        else if ((insn & 0xf0) == 0x80) {
+                unsigned long mask;
+                unsigned long *vsp = (unsigned long *)ctrl->vrs[SP];
+                int load_sp, reg = 4;
+
+                insn = (insn << 8) | unwind_get_byte(ctrl);
+                mask = insn & 0x0fff;
+                if (mask == 0) {
+                        pr_warning("unwind: 'Refuse to unwind' instruction %04lx\n",
+                                   insn);
+                        return -URC_FAILURE;
+                }
+
+                /* pop R4-R15 according to mask */
+                load_sp = mask & (1 << (13 - 4));
+                while (mask) {
+                        if (mask & 1)
+                                ctrl->vrs[reg] = *vsp++;
+                        mask >>= 1;
+                        reg++;
+                }
+                if (!load_sp)
+                        ctrl->vrs[SP] = (unsigned long)vsp;
+        } else if ((insn & 0xf0) == 0x90 &&
+                   (insn & 0x0d) != 0x0d)
+                ctrl->vrs[SP] = ctrl->vrs[insn & 0x0f];
+        else if ((insn & 0xf0) == 0xa0) {
+                unsigned long *vsp = (unsigned long *)ctrl->vrs[SP];
+                int reg;
+
+                /* pop R4-R[4+bbb] */
+                for (reg = 4; reg <= 4 + (insn & 7); reg++)
+                        ctrl->vrs[reg] = *vsp++;
+                if (insn & 0x80)
+                        ctrl->vrs[14] = *vsp++;
+                ctrl->vrs[SP] = (unsigned long)vsp;
+        } else if (insn == 0xb0) {
+                ctrl->vrs[PC] = ctrl->vrs[LR];
+                /* no further processing */
+                ctrl->entries = 0;
+        } else if (insn == 0xb1) {
+                unsigned long mask = unwind_get_byte(ctrl);
+                unsigned long *vsp = (unsigned long *)ctrl->vrs[SP];
+                int reg = 0;
+
+                if (mask == 0 || mask & 0xf0) {
+                        pr_warning("unwind: Spare encoding %04lx\n",
+                               (insn << 8) | mask);
+                        return -URC_FAILURE;
+                }
+
+                /* pop R0-R3 according to mask */
+                while (mask) {
+                        if (mask & 1)
+                                ctrl->vrs[reg] = *vsp++;
+                        mask >>= 1;
+                        reg++;
+                }
+                ctrl->vrs[SP] = (unsigned long)vsp;
+        } else if (insn == 0xb2) {
+                unsigned long uleb128 = unwind_get_byte(ctrl);
+
+                ctrl->vrs[SP] += 0x204 + (uleb128 << 2);
+        } else {
+                pr_warning("unwind: Unhandled instruction %02lx\n", insn);
+                return -URC_FAILURE;
+        }
+
+        pr_debug("%s: fp = %08lx sp = %08lx lr = %08lx pc = %08lx\n", __func__,
+                 ctrl->vrs[FP], ctrl->vrs[SP], ctrl->vrs[LR], ctrl->vrs[PC]);
+
+        return URC_OK;
+}
+
+/*
+ * Unwind a single frame starting with *sp for the symbol at *pc. It
+ * updates the *pc and *sp with the new values.
+ */
+int unwind_frame(struct stackframe *frame)
+{
+        unsigned long high, low;
+        struct unwind_idx *idx;
+        struct unwind_ctrl_block ctrl;
+
+        /* only go to a higher address on the stack */
+        low = frame->sp;
+        high = ALIGN(low, THREAD_SIZE) + THREAD_SIZE;
+
+        pr_debug("%s(pc = %08lx lr = %08lx sp = %08lx)\n", __func__,
+                 frame->pc, frame->lr, frame->sp);
+
+        if (!kernel_text_address(frame->pc))
+                return -URC_FAILURE;
+
+        idx = unwind_find_idx(frame->pc);
+        if (!idx) {
+                pr_warning("unwind: Index not found %08lx\n", frame->pc);
+                return -URC_FAILURE;
+        }
+
+        ctrl.vrs[FP] = frame->fp;
+        ctrl.vrs[SP] = frame->sp;
+        ctrl.vrs[LR] = frame->lr;
+        ctrl.vrs[PC] = 0;
+
+        if (idx->insn == 1)
+                /* can't unwind */
+                return -URC_FAILURE;
+        else if ((idx->insn & 0x80000000) == 0)
+                /* prel31 to the unwind table */
+                ctrl.insn = (unsigned long *)prel31_to_addr(&idx->insn);
+        else if ((idx->insn & 0xff000000) == 0x80000000)
+                /* only personality routine 0 supported in the index */
+                ctrl.insn = &idx->insn;
+        else {
+                pr_warning("unwind: Unsupported personality routine %08lx in the index at %p\n",
+                           idx->insn, idx);
+                return -URC_FAILURE;
+        }
+
+        /* check the personality routine */
+        if ((*ctrl.insn & 0xff000000) == 0x80000000) {
+                ctrl.byte = 2;
+                ctrl.entries = 1;
+        } else if ((*ctrl.insn & 0xff000000) == 0x81000000) {
+                ctrl.byte = 1;
+                ctrl.entries = 1 + ((*ctrl.insn & 0x00ff0000) >> 16);
+        } else {
+                pr_warning("unwind: Unsupported personality routine %08lx at %p\n",
+                           *ctrl.insn, ctrl.insn);
+                return -URC_FAILURE;
+        }
+
+        while (ctrl.entries > 0) {
+                int urc;
+
+                if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= high)
+                        return -URC_FAILURE;
+                urc = unwind_exec_insn(&ctrl);
+                if (urc < 0)
+                        return urc;
+        }
+
+        if (ctrl.vrs[PC] == 0)
+                ctrl.vrs[PC] = ctrl.vrs[LR];
+
+        frame->fp = ctrl.vrs[FP];
+        frame->sp = ctrl.vrs[SP];
+        frame->lr = ctrl.vrs[LR];
+        frame->pc = ctrl.vrs[PC];
+
+        return URC_OK;
+}
+
+void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk)
+{
+        struct stackframe frame;
+        unsigned long high, low;
+        register unsigned long current_sp asm ("sp");
+
+        pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk);
+
+        if (!tsk)
+                tsk = current;
+
+        if (regs) {
+                frame.fp = regs->ARM_fp;
+                frame.sp = regs->ARM_sp;
+                frame.lr = regs->ARM_lr;
+                frame.pc = regs->ARM_pc;
+        } else if (tsk == current) {
+                frame.fp = (unsigned long)__builtin_frame_address(0);
+                frame.sp = current_sp;
+                frame.lr = (unsigned long)__builtin_return_address(0);
+                frame.pc = (unsigned long)unwind_backtrace;
+        } else {
+                /* task blocked in __switch_to */
+                frame.fp = thread_saved_fp(tsk);
+                frame.sp = thread_saved_sp(tsk);
+                /*
+                 * The function calling __switch_to cannot be a leaf function
+                 * so LR is recovered from the stack.
+                 */
+                frame.lr = 0;
+                frame.pc = thread_saved_pc(tsk);
+        }
+
+        low = frame.sp & ~(THREAD_SIZE - 1);
+        high = low + THREAD_SIZE;
+
+        while (1) {
+                int urc;
+                unsigned long where = frame.pc;
+
+                urc = unwind_frame(&frame);
+                if (urc < 0)
+                        break;
+                dump_backtrace_entry(where, frame.pc, frame.sp - 4);
+        }
+}
+
+struct unwind_table *unwind_table_add(unsigned long start, unsigned long size,
+                                      unsigned long text_addr,
+                                      unsigned long text_size)
+{
+        unsigned long flags;
+        struct unwind_idx *idx;
+        struct unwind_table *tab = kmalloc(sizeof(*tab), GFP_KERNEL);
+
+        pr_debug("%s(%08lx, %08lx, %08lx, %08lx)\n", __func__, start, size,
+                 text_addr, text_size);
+
+        if (!tab)
+                return tab;
+
+        tab->start = (struct unwind_idx *)start;
+        tab->stop = (struct unwind_idx *)(start + size);
+        tab->begin_addr = text_addr;
+        tab->end_addr = text_addr + text_size;
+
+        /* Convert the symbol addresses to absolute values */
+        for (idx = tab->start; idx < tab->stop; idx++)
+                idx->addr = prel31_to_addr(&idx->addr);
+
+        spin_lock_irqsave(&unwind_lock, flags);
+        list_add_tail(&tab->list, &unwind_tables);
+        spin_unlock_irqrestore(&unwind_lock, flags);
+
+        return tab;
+}
+
+void unwind_table_del(struct unwind_table *tab)
+{
+        unsigned long flags;
+
+        if (!tab)
+                return;
+
+        spin_lock_irqsave(&unwind_lock, flags);
+        list_del(&tab->list);
+        spin_unlock_irqrestore(&unwind_lock, flags);
+
+        kfree(tab);
+}
+
+int __init unwind_init(void)
+{
+        struct unwind_idx *idx;
+
+        /* Convert the symbol addresses to absolute values */
+        for (idx = __start_unwind_idx; idx < __stop_unwind_idx; idx++)
+                idx->addr = prel31_to_addr(&idx->addr);
+
+        pr_debug("unwind: ARM stack unwinding initialised\n");
+
+        return 0;
+}
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 1602373e539c..c90f27250ead 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -82,6 +82,8 @@ SECTIONS
                 EXIT_TEXT
                 EXIT_DATA
                 *(.exitcall.exit)
+                *(.ARM.exidx.exit.text)
+                *(.ARM.extab.exit.text)
 #ifndef CONFIG_MMU
                 *(.fixup)
                 *(__ex_table)
@@ -112,6 +114,23 @@ SECTIONS
 
         _etext = .;                     /* End of text and rodata section */
 
+#ifdef CONFIG_ARM_UNWIND
+        /*
+         * Stack unwinding tables
+         */
+        . = ALIGN(8);
+        .ARM.unwind_idx : {
+                __start_unwind_idx = .;
+                *(.ARM.exidx*)
+                __stop_unwind_idx = .;
+        }
+        .ARM.unwind_tab : {
+                __start_unwind_tab = .;
+                *(.ARM.extab*)
+                __stop_unwind_tab = .;
+        }
+#endif
+
 #ifdef CONFIG_XIP_KERNEL
         __data_loc = ALIGN(4);          /* location in binary */
         . = PAGE_OFFSET + TEXT_OFFSET;
diff --git a/arch/arm/mach-aaec2000/include/mach/system.h b/arch/arm/mach-aaec2000/include/mach/system.h
index 8f4115d734ce..fe08ca1add6f 100644
--- a/arch/arm/mach-aaec2000/include/mach/system.h
+++ b/arch/arm/mach-aaec2000/include/mach/system.h
@@ -16,7 +16,7 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         cpu_reset(0);
 }
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 81439fe6fb3d..438efbb17482 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -238,6 +238,10 @@ static void __init ek_board_init(void)
         at91_add_device_i2c(NULL, 0);
         /* LEDs */
         at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+        /* PCK0 provides MCLK to the WM8731 */
+        at91_set_B_periph(AT91_PIN_PC1, 0);
+        /* SSC (for WM8731) */
+        at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
 }
 
 MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 7b9ce7a336b0..b5daf7f5e011 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -47,9 +47,6 @@ extern void at91_irq_resume(void);
 #define AT91RM9200_BGA          4       /* AT91RM9200 BGA package has 4 banks */
 
 struct at91_gpio_bank {
-        unsigned chipbase;              /* bank's first GPIO number */
-        void __iomem *regbase;          /* base of register bank */
-        struct at91_gpio_bank *next;    /* bank sharing same IRQ/clock/... */
         unsigned short id;              /* peripheral ID */
         unsigned long offset;           /* offset from system peripheral base */
         struct clk *clock;              /* associated clock */
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 2f7d4977dce9..f2236f0e101f 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -24,19 +24,59 @@
 #include <mach/at91_pio.h>
 #include <mach/gpio.h>
 
+#include <asm/gpio.h>
+
 #include "generic.h"
 
+struct at91_gpio_chip {
+        struct gpio_chip        chip;
+        struct at91_gpio_chip   *next;          /* Bank sharing same clock */
+        struct at91_gpio_bank   *bank;          /* Bank definition */
+        void __iomem            *regbase;       /* Base of register bank */
+};
 
-static struct at91_gpio_bank *gpio;
-static int gpio_banks;
+#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
+
+static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
+static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
+static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
+static int at91_gpiolib_direction_output(struct gpio_chip *chip,
+                                         unsigned offset, int val);
+static int at91_gpiolib_direction_input(struct gpio_chip *chip,
+                                        unsigned offset);
+static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset);
+
+#define AT91_GPIO_CHIP(name, base_gpio, nr_gpio)                        \
+        {                                                               \
+                .chip = {                                               \
+                        .label            = name,                       \
+                        .request          = at91_gpiolib_request,       \
+                        .direction_input  = at91_gpiolib_direction_input, \
+                        .direction_output = at91_gpiolib_direction_output, \
+                        .get              = at91_gpiolib_get,           \
+                        .set              = at91_gpiolib_set,           \
+                        .dbg_show         = at91_gpiolib_dbg_show,      \
+                        .base             = base_gpio,                  \
+                        .ngpio            = nr_gpio,                    \
+                },                                                      \
+        }
+
+static struct at91_gpio_chip gpio_chip[] = {
+        AT91_GPIO_CHIP("A", 0x00 + PIN_BASE, 32),
+        AT91_GPIO_CHIP("B", 0x20 + PIN_BASE, 32),
+        AT91_GPIO_CHIP("C", 0x40 + PIN_BASE, 32),
+        AT91_GPIO_CHIP("D", 0x60 + PIN_BASE, 32),
+        AT91_GPIO_CHIP("E", 0x80 + PIN_BASE, 32),
+};
 
+static int gpio_banks;
 
 static inline void __iomem *pin_to_controller(unsigned pin)
 {
         pin -= PIN_BASE;
         pin /= 32;
         if (likely(pin < gpio_banks))
-                return gpio[pin].regbase;
+                return gpio_chip[pin].regbase;
 
         return NULL;
 }
@@ -197,39 +237,6 @@ int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
 }
 EXPORT_SYMBOL(at91_set_multi_drive);
 
-/*--------------------------------------------------------------------------*/
-
-/* new-style GPIO calls; these expect at91_set_GPIO_periph to have been
- * called, and maybe at91_set_multi_drive() for putout pins.
- */
-
-int gpio_direction_input(unsigned pin)
-{
-        void __iomem    *pio = pin_to_controller(pin);
-        unsigned        mask = pin_to_mask(pin);
-
-        if (!pio || !(__raw_readl(pio + PIO_PSR) & mask))
-                return -EINVAL;
-        __raw_writel(mask, pio + PIO_ODR);
-        return 0;
-}
-EXPORT_SYMBOL(gpio_direction_input);
-
-int gpio_direction_output(unsigned pin, int value)
-{
-        void __iomem    *pio = pin_to_controller(pin);
-        unsigned        mask = pin_to_mask(pin);
-
-        if (!pio || !(__raw_readl(pio + PIO_PSR) & mask))
-                return -EINVAL;
-        __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
-        __raw_writel(mask, pio + PIO_OER);
-        return 0;
-}
-EXPORT_SYMBOL(gpio_direction_output);
-
-/*--------------------------------------------------------------------------*/
-
 /*
  * assuming the pin is muxed as a gpio output, set its value.
  */
@@ -282,7 +289,7 @@ static int gpio_irq_set_wake(unsigned pin, unsigned state)
         else
                 wakeups[bank] &= ~mask;
 
-        set_irq_wake(gpio[bank].id, state);
+        set_irq_wake(gpio_chip[bank].bank->id, state);
 
         return 0;
 }
@@ -292,14 +299,14 @@ void at91_gpio_suspend(void)
         int i;
 
         for (i = 0; i < gpio_banks; i++) {
-                void __iomem    *pio = gpio[i].regbase;
+                void __iomem    *pio = gpio_chip[i].regbase;
 
                 backups[i] = __raw_readl(pio + PIO_IMR);
                 __raw_writel(backups[i], pio + PIO_IDR);
                 __raw_writel(wakeups[i], pio + PIO_IER);
 
                 if (!wakeups[i])
-                        clk_disable(gpio[i].clock);
+                        clk_disable(gpio_chip[i].bank->clock);
                 else {
 #ifdef CONFIG_PM_DEBUG
                         printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
@@ -313,10 +320,10 @@ void at91_gpio_resume(void)
         int i;
 
         for (i = 0; i < gpio_banks; i++) {
-                void __iomem    *pio = gpio[i].regbase;
+                void __iomem    *pio = gpio_chip[i].regbase;
 
                 if (!wakeups[i])
-                        clk_enable(gpio[i].clock);
+                        clk_enable(gpio_chip[i].bank->clock);
 
                 __raw_writel(wakeups[i], pio + PIO_IDR);
                 __raw_writel(backups[i], pio + PIO_IER);
@@ -380,12 +387,12 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
         unsigned        pin;
         struct irq_desc *gpio;
-        struct at91_gpio_bank *bank;
+        struct at91_gpio_chip *at91_gpio;
         void __iomem    *pio;
         u32             isr;
 
-        bank = get_irq_chip_data(irq);
-        pio = bank->regbase;
+        at91_gpio = get_irq_chip_data(irq);
+        pio = at91_gpio->regbase;
 
         /* temporarily mask (level sensitive) parent IRQ */
         desc->chip->ack(irq);
@@ -396,14 +403,14 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                  */
                 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
                 if (!isr) {
-                        if (!bank->next)
+                        if (!at91_gpio->next)
                                 break;
-                        bank = bank->next;
-                        pio = bank->regbase;
+                        at91_gpio = at91_gpio->next;
+                        pio = at91_gpio->regbase;
                         continue;
                 }
 
-                pin = bank->chipbase;
+                pin = at91_gpio->chip.base;
                 gpio = &irq_desc[pin];
 
                 while (isr) {
@@ -502,17 +509,17 @@ static struct lock_class_key gpio_lock_class;
 void __init at91_gpio_irq_setup(void)
 {
         unsigned                pioc, pin;
-        struct at91_gpio_bank   *this, *prev;
+        struct at91_gpio_chip   *this, *prev;
 
-        for (pioc = 0, pin = PIN_BASE, this = gpio, prev = NULL;
+        for (pioc = 0, pin = PIN_BASE, this = gpio_chip, prev = NULL;
                         pioc++ < gpio_banks;
                         prev = this, this++) {
-                unsigned        id = this->id;
+                unsigned        id = this->bank->id;
                 unsigned        i;
 
                 __raw_writel(~0, this->regbase + PIO_IDR);
 
-                for (i = 0, pin = this->chipbase; i < 32; i++, pin++) {
+                for (i = 0, pin = this->chip.base; i < 32; i++, pin++) {
                         lockdep_set_class(&irq_desc[pin].lock, &gpio_lock_class);
 
                         /*
@@ -537,32 +544,117 @@ void __init at91_gpio_irq_setup(void)
         pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
 }
 
+/* gpiolib support */
+static int at91_gpiolib_direction_input(struct gpio_chip *chip,
+                                        unsigned offset)
+{
+        struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+        void __iomem *pio = at91_gpio->regbase;
+        unsigned mask = 1 << offset;
+
+        __raw_writel(mask, pio + PIO_ODR);
+        return 0;
+}
+
+static int at91_gpiolib_direction_output(struct gpio_chip *chip,
+                                         unsigned offset, int val)
+{
+        struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+        void __iomem *pio = at91_gpio->regbase;
+        unsigned mask = 1 << offset;
+
+        __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
+        __raw_writel(mask, pio + PIO_OER);
+        return 0;
+}
+
+static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+        void __iomem *pio = at91_gpio->regbase;
+        unsigned mask = 1 << offset;
+        u32 pdsr;
+
+        pdsr = __raw_readl(pio + PIO_PDSR);
+        return (pdsr & mask) != 0;
+}
+
+static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
+{
+        struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+        void __iomem *pio = at91_gpio->regbase;
+        unsigned mask = 1 << offset;
+
+        __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
+}
+
+static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset)
+{
+        unsigned pin = chip->base + offset;
+        void __iomem *pio = pin_to_controller(pin);
+        unsigned mask = pin_to_mask(pin);
+
+        /* Cannot request GPIOs that are in alternate function mode */
+        if (!(__raw_readl(pio + PIO_PSR) & mask))
+                return -EPERM;
+
+        return 0;
+}
+
+static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
+{
+        int i;
+
+        for (i = 0; i < chip->ngpio; i++) {
+                unsigned pin = chip->base + i;
+                void __iomem *pio = pin_to_controller(pin);
+                unsigned mask = pin_to_mask(pin);
+                const char *gpio_label;
+
+                gpio_label = gpiochip_is_requested(chip, i);
+                if (gpio_label) {
+                        seq_printf(s, "[%s] GPIO%s%d: ",
+                                   gpio_label, chip->label, i);
+                        if (__raw_readl(pio + PIO_PSR) & mask)
+                                seq_printf(s, "[gpio] %s\n",
+                                           at91_get_gpio_value(pin) ?
+                                           "set" : "clear");
+                        else
+                                seq_printf(s, "[periph %s]\n",
+                                           __raw_readl(pio + PIO_ABSR) &
+                                           mask ? "B" : "A");
+                }
+        }
+}
+
 /*
  * Called from the processor-specific init to enable GPIO pin support.
  */
 void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
 {
         unsigned                i;
-        struct at91_gpio_bank   *last;
+        struct at91_gpio_chip *at91_gpio, *last = NULL;
 
         BUG_ON(nr_banks > MAX_GPIO_BANKS);
 
-        gpio = data;
         gpio_banks = nr_banks;
 
-        for (i = 0, last = NULL; i < nr_banks; i++, last = data, data++) {
-                data->chipbase = PIN_BASE + i * 32;
-                data->regbase = data->offset + (void __iomem *)AT91_VA_BASE_SYS;
+        for (i = 0; i < nr_banks; i++) {
+                at91_gpio = &gpio_chip[i];
+
+                at91_gpio->bank = &data[i];
+                at91_gpio->chip.base = PIN_BASE + i * 32;
+                at91_gpio->regbase = at91_gpio->bank->offset +
+                        (void __iomem *)AT91_VA_BASE_SYS;
 
                 /* enable PIO controller's clock */
-                clk_enable(data->clock);
+                clk_enable(at91_gpio->bank->clock);
 
-                /*
-                 * Some processors share peripheral ID between multiple GPIO banks.
-                 *  SAM9263 (PIOC, PIOD, PIOE)
-                 *  CAP9 (PIOA, PIOB, PIOC, PIOD)
-                 */
-                if (last && last->id == data->id)
-                        last->next = data;
+                /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
+                if (last && last->bank->id == at91_gpio->bank->id)
+                        last->next = at91_gpio;
+                last = at91_gpio;
+
+                gpiochip_add(&at91_gpio->chip);
         }
 }
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index bffa6741a751..04c91e31c9c5 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -213,32 +213,12 @@ extern void at91_gpio_resume(void);
  */
 
 #include <asm/errno.h>
-
-static inline int gpio_request(unsigned gpio, const char *label)
-{
-        return 0;
-}
-
-static inline void gpio_free(unsigned gpio)
-{
-        might_sleep();
-}
-
-extern int gpio_direction_input(unsigned gpio);
-extern int gpio_direction_output(unsigned gpio, int value);
-
-static inline int gpio_get_value(unsigned gpio)
-{
-        return at91_get_gpio_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
-        at91_set_gpio_value(gpio, value);
-}
-
 #include <asm-generic/gpio.h>           /* cansleep wrappers */
 
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+
 static inline int gpio_to_irq(unsigned gpio)
 {
         return gpio;
diff --git a/arch/arm/mach-at91/include/mach/system.h b/arch/arm/mach-at91/include/mach/system.h
index e712658d966c..5268af3933c2 100644
--- a/arch/arm/mach-at91/include/mach/system.h
+++ b/arch/arm/mach-at91/include/mach/system.h
@@ -43,7 +43,7 @@ static inline void arch_idle(void)
 
 void (*at91_arch_reset)(void);
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         /* call the CPU-specific reset function */
         if (at91_arch_reset)
diff --git a/arch/arm/mach-clps711x/include/mach/system.h b/arch/arm/mach-clps711x/include/mach/system.h
index 24e96159e3e7..f916cd7a477d 100644
--- a/arch/arm/mach-clps711x/include/mach/system.h
+++ b/arch/arm/mach-clps711x/include/mach/system.h
@@ -32,7 +32,7 @@ static inline void arch_idle(void)
         mov     r0, r0");
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         cpu_reset(0);
 }
diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h
index 17ca41dc2c53..b7e7036674fa 100644
--- a/arch/arm/mach-davinci/include/mach/system.h
+++ b/arch/arm/mach-davinci/include/mach/system.h
@@ -21,7 +21,7 @@ static void arch_idle(void)
         cpu_do_idle();
 }
 
-static void arch_reset(char mode)
+static void arch_reset(char mode, const char *cmd)
 {
         davinci_watchdog_reset();
 }
diff --git a/arch/arm/mach-ebsa110/include/mach/system.h b/arch/arm/mach-ebsa110/include/mach/system.h
index 350a028997ef..9a26245bf1fc 100644
--- a/arch/arm/mach-ebsa110/include/mach/system.h
+++ b/arch/arm/mach-ebsa110/include/mach/system.h
@@ -34,6 +34,6 @@ static inline void arch_idle(void)
         asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
 }
 
-#define arch_reset(mode)        cpu_reset(0x80000000)
+#define arch_reset(mode, cmd)   cpu_reset(0x80000000)
 
 #endif
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index 944e42d51646..9522e205b73f 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -1,7 +1,7 @@
 #
 # Makefile for the linux kernel.
 #
-obj-y                   := core.o clock.o gpio.o
+obj-y                   := core.o clock.o dma-m2p.o gpio.o
 obj-m                   :=
 obj-n                   :=
 obj-                    :=
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index 96049283a10a..e8ebeaea6c48 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -41,6 +41,56 @@ static struct clk clk_usb_host = {
         .enable_mask    = EP93XX_SYSCON_CLOCK_USH_EN,
 };
 
+/* DMA Clocks */
+static struct clk clk_m2p0 = {
+        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_mask    = 0x00020000,
+};
+static struct clk clk_m2p1 = {
+        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_mask    = 0x00010000,
+};
+static struct clk clk_m2p2 = {
+        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_mask    = 0x00080000,
+};
+static struct clk clk_m2p3 = {
+        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_mask    = 0x00040000,
+};
+static struct clk clk_m2p4 = {
+        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_mask    = 0x00200000,
+};
+static struct clk clk_m2p5 = {
+        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_mask    = 0x00100000,
+};
+static struct clk clk_m2p6 = {
+        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_mask    = 0x00800000,
+};
+static struct clk clk_m2p7 = {
+        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_mask    = 0x00400000,
+};
+static struct clk clk_m2p8 = {
+        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_mask    = 0x02000000,
+};
+static struct clk clk_m2p9 = {
+        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_mask    = 0x01000000,
+};
+static struct clk clk_m2m0 = {
+        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_mask    = 0x04000000,
+};
+static struct clk clk_m2m1 = {
+        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_mask    = 0x08000000,
+};
+
 #define INIT_CK(dev,con,ck)                                     \
         { .dev_id = dev, .con_id = con, .clk = ck }
 
@@ -54,6 +104,18 @@ static struct clk_lookup clocks[] = {
         INIT_CK(NULL, "pclk", &clk_p),
         INIT_CK(NULL, "pll2", &clk_pll2),
         INIT_CK(NULL, "usb_host", &clk_usb_host),
+        INIT_CK(NULL, "m2p0", &clk_m2p0),
+        INIT_CK(NULL, "m2p1", &clk_m2p1),
+        INIT_CK(NULL, "m2p2", &clk_m2p2),
+        INIT_CK(NULL, "m2p3", &clk_m2p3),
+        INIT_CK(NULL, "m2p4", &clk_m2p4),
+        INIT_CK(NULL, "m2p5", &clk_m2p5),
+        INIT_CK(NULL, "m2p6", &clk_m2p6),
+        INIT_CK(NULL, "m2p7", &clk_m2p7),
+        INIT_CK(NULL, "m2p8", &clk_m2p8),
+        INIT_CK(NULL, "m2p9", &clk_m2p9),
+        INIT_CK(NULL, "m2m0", &clk_m2m0),
+        INIT_CK(NULL, "m2m1", &clk_m2m1),
 };
 
 
@@ -110,6 +172,22 @@ static unsigned long calc_pll_rate(u32 config_word)
         return (unsigned long)rate;
 }
 
+static void __init ep93xx_dma_clock_init(void)
+{
+        clk_m2p0.rate = clk_h.rate;
+        clk_m2p1.rate = clk_h.rate;
+        clk_m2p2.rate = clk_h.rate;
+        clk_m2p3.rate = clk_h.rate;
+        clk_m2p4.rate = clk_h.rate;
+        clk_m2p5.rate = clk_h.rate;
+        clk_m2p6.rate = clk_h.rate;
+        clk_m2p7.rate = clk_h.rate;
+        clk_m2p8.rate = clk_h.rate;
+        clk_m2p9.rate = clk_h.rate;
+        clk_m2m0.rate = clk_h.rate;
+        clk_m2m1.rate = clk_h.rate;
+}
+
 static int __init ep93xx_clock_init(void)
 {
         u32 value;
@@ -124,6 +202,7 @@ static int __init ep93xx_clock_init(void)
         clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
         clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
         clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
+        ep93xx_dma_clock_init();
 
         value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2);
         if (!(value & 0x00080000)) {                    /* PLL2 bypassed?  */
diff --git a/arch/arm/mach-ep93xx/dma-m2p.c b/arch/arm/mach-ep93xx/dma-m2p.c
new file mode 100644
index 000000000000..a2df5bb7dff0
--- /dev/null
+++ b/arch/arm/mach-ep93xx/dma-m2p.c
@@ -0,0 +1,408 @@
+/*
+ * arch/arm/mach-ep93xx/dma-m2p.c
+ * M2P DMA handling for Cirrus EP93xx chips.
+ *
+ * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
+ * Copyright (C) 2006 Applied Data Systems
+ *
+ * Copyright (C) 2009 Ryan Mallon <ryan@bluewatersys.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+/*
+ * On the EP93xx chip the following peripherals my be allocated to the 10
+ * Memory to Internal Peripheral (M2P) channels (5 transmit + 5 receive).
+ *
+ *      I2S     contains 3 Tx and 3 Rx DMA Channels
+ *      AAC     contains 3 Tx and 3 Rx DMA Channels
+ *      UART1   contains 1 Tx and 1 Rx DMA Channels
+ *      UART2   contains 1 Tx and 1 Rx DMA Channels
+ *      UART3   contains 1 Tx and 1 Rx DMA Channels
+ *      IrDA    contains 1 Tx and 1 Rx DMA Channels
+ *
+ * SSP and IDE use the Memory to Memory (M2M) channels and are not covered
+ * with this implementation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+
+#include <mach/dma.h>
+#include <mach/hardware.h>
+
+#define M2P_CONTROL                     0x00
+#define  M2P_CONTROL_STALL_IRQ_EN       (1 << 0)
+#define  M2P_CONTROL_NFB_IRQ_EN         (1 << 1)
+#define  M2P_CONTROL_ERROR_IRQ_EN       (1 << 3)
+#define  M2P_CONTROL_ENABLE             (1 << 4)
+#define M2P_INTERRUPT                   0x04
+#define  M2P_INTERRUPT_STALL            (1 << 0)
+#define  M2P_INTERRUPT_NFB              (1 << 1)
+#define  M2P_INTERRUPT_ERROR            (1 << 3)
+#define M2P_PPALLOC                     0x08
+#define M2P_STATUS                      0x0c
+#define M2P_REMAIN                      0x14
+#define M2P_MAXCNT0                     0x20
+#define M2P_BASE0                       0x24
+#define M2P_MAXCNT1                     0x30
+#define M2P_BASE1                       0x34
+
+#define STATE_IDLE      0       /* Channel is inactive.  */
+#define STATE_STALL     1       /* Channel is active, no buffers pending.  */
+#define STATE_ON        2       /* Channel is active, one buffer pending.  */
+#define STATE_NEXT      3       /* Channel is active, two buffers pending.  */
+
+struct m2p_channel {
+        char                            *name;
+        void __iomem                    *base;
+        int                             irq;
+
+        struct clk                      *clk;
+        spinlock_t                      lock;
+
+        void                            *client;
+        unsigned                        next_slot:1;
+        struct ep93xx_dma_buffer        *buffer_xfer;
+        struct ep93xx_dma_buffer        *buffer_next;
+        struct list_head                buffers_pending;
+};
+
+static struct m2p_channel m2p_rx[] = {
+        {"m2p1", EP93XX_DMA_BASE + 0x0040, IRQ_EP93XX_DMAM2P1},
+        {"m2p3", EP93XX_DMA_BASE + 0x00c0, IRQ_EP93XX_DMAM2P3},
+        {"m2p5", EP93XX_DMA_BASE + 0x0200, IRQ_EP93XX_DMAM2P5},
+        {"m2p7", EP93XX_DMA_BASE + 0x0280, IRQ_EP93XX_DMAM2P7},
+        {"m2p9", EP93XX_DMA_BASE + 0x0300, IRQ_EP93XX_DMAM2P9},
+        {NULL},
+};
+
+static struct m2p_channel m2p_tx[] = {
+        {"m2p0", EP93XX_DMA_BASE + 0x0000, IRQ_EP93XX_DMAM2P0},
+        {"m2p2", EP93XX_DMA_BASE + 0x0080, IRQ_EP93XX_DMAM2P2},
+        {"m2p4", EP93XX_DMA_BASE + 0x0240, IRQ_EP93XX_DMAM2P4},
+        {"m2p6", EP93XX_DMA_BASE + 0x02c0, IRQ_EP93XX_DMAM2P6},
+        {"m2p8", EP93XX_DMA_BASE + 0x0340, IRQ_EP93XX_DMAM2P8},
+        {NULL},
+};
+
+static void feed_buf(struct m2p_channel *ch, struct ep93xx_dma_buffer *buf)
+{
+        if (ch->next_slot == 0) {
+                writel(buf->size, ch->base + M2P_MAXCNT0);
+                writel(buf->bus_addr, ch->base + M2P_BASE0);
+        } else {
+                writel(buf->size, ch->base + M2P_MAXCNT1);
+                writel(buf->bus_addr, ch->base + M2P_BASE1);
+        }
+        ch->next_slot ^= 1;
+}
+
+static void choose_buffer_xfer(struct m2p_channel *ch)
+{
+        struct ep93xx_dma_buffer *buf;
+
+        ch->buffer_xfer = NULL;
+        if (!list_empty(&ch->buffers_pending)) {
+                buf = list_entry(ch->buffers_pending.next,
+                                 struct ep93xx_dma_buffer, list);
+                list_del(&buf->list);
+                feed_buf(ch, buf);
+                ch->buffer_xfer = buf;
+        }
+}
+
+static void choose_buffer_next(struct m2p_channel *ch)
+{
+        struct ep93xx_dma_buffer *buf;
+
+        ch->buffer_next = NULL;
+        if (!list_empty(&ch->buffers_pending)) {
+                buf = list_entry(ch->buffers_pending.next,
+                                 struct ep93xx_dma_buffer, list);
+                list_del(&buf->list);
+                feed_buf(ch, buf);
+                ch->buffer_next = buf;
+        }
+}
+
+static inline void m2p_set_control(struct m2p_channel *ch, u32 v)
+{
+        /*
+         * The control register must be read immediately after being written so
+         * that the internal state machine is correctly updated. See the ep93xx
+         * users' guide for details.
+         */
+        writel(v, ch->base + M2P_CONTROL);
+        readl(ch->base + M2P_CONTROL);
+}
+
+static inline int m2p_channel_state(struct m2p_channel *ch)
+{
+        return (readl(ch->base + M2P_STATUS) >> 4) & 0x3;
+}
+
+static irqreturn_t m2p_irq(int irq, void *dev_id)
+{
+        struct m2p_channel *ch = dev_id;
+        struct ep93xx_dma_m2p_client *cl;
+        u32 irq_status, v;
+        int error = 0;
+
+        cl = ch->client;
+
+        spin_lock(&ch->lock);
+        irq_status = readl(ch->base + M2P_INTERRUPT);
+
+        if (irq_status & M2P_INTERRUPT_ERROR) {
+                writel(M2P_INTERRUPT_ERROR, ch->base + M2P_INTERRUPT);
+                error = 1;
+        }
+
+        if ((irq_status & (M2P_INTERRUPT_STALL | M2P_INTERRUPT_NFB)) == 0) {
+                spin_unlock(&ch->lock);
+                return IRQ_NONE;
+        }
+
+        switch (m2p_channel_state(ch)) {
+        case STATE_IDLE:
+                pr_crit("m2p_irq: dma interrupt without a dma buffer\n");
+                BUG();
+                break;
+
+        case STATE_STALL:
+                cl->buffer_finished(cl->cookie, ch->buffer_xfer, 0, error);
+                if (ch->buffer_next != NULL) {
+                        cl->buffer_finished(cl->cookie, ch->buffer_next,
+                                            0, error);
+                }
+                choose_buffer_xfer(ch);
+                choose_buffer_next(ch);
+                if (ch->buffer_xfer != NULL)
+                        cl->buffer_started(cl->cookie, ch->buffer_xfer);
+                break;
+
+        case STATE_ON:
+                cl->buffer_finished(cl->cookie, ch->buffer_xfer, 0, error);
+                ch->buffer_xfer = ch->buffer_next;
+                choose_buffer_next(ch);
+                cl->buffer_started(cl->cookie, ch->buffer_xfer);
+                break;
+
+        case STATE_NEXT:
+                pr_crit("m2p_irq: dma interrupt while next\n");
+                BUG();
+                break;
+        }
+
+        v = readl(ch->base + M2P_CONTROL) & ~(M2P_CONTROL_STALL_IRQ_EN |
+                                              M2P_CONTROL_NFB_IRQ_EN);
+        if (ch->buffer_xfer != NULL)
+                v |= M2P_CONTROL_STALL_IRQ_EN;
+        if (ch->buffer_next != NULL)
+                v |= M2P_CONTROL_NFB_IRQ_EN;
+        m2p_set_control(ch, v);
+
+        spin_unlock(&ch->lock);
+        return IRQ_HANDLED;
+}
+
+static struct m2p_channel *find_free_channel(struct ep93xx_dma_m2p_client *cl)
+{
+        struct m2p_channel *ch;
+        int i;
+
+        if (cl->flags & EP93XX_DMA_M2P_RX)
+                ch = m2p_rx;
+        else
+                ch = m2p_tx;
+
+        for (i = 0; ch[i].base; i++) {
+                struct ep93xx_dma_m2p_client *client;
+
+                client = ch[i].client;
+                if (client != NULL) {
+                        int port;
+
+                        port = cl->flags & EP93XX_DMA_M2P_PORT_MASK;
+                        if (port == (client->flags &
+                                     EP93XX_DMA_M2P_PORT_MASK)) {
+                                pr_warning("DMA channel already used by %s\n",
+                                           cl->name ? : "unknown client");
+                                return ERR_PTR(-EBUSY);
+                        }
+                }
+        }
+
+        for (i = 0; ch[i].base; i++) {
+                if (ch[i].client == NULL)
+                        return ch + i;
+        }
+
+        pr_warning("No free DMA channel for %s\n",
+                   cl->name ? : "unknown client");
+        return ERR_PTR(-ENODEV);
+}
+
+static void channel_enable(struct m2p_channel *ch)
+{
+        struct ep93xx_dma_m2p_client *cl = ch->client;
+        u32 v;
+
+        clk_enable(ch->clk);
+
+        v = cl->flags & EP93XX_DMA_M2P_PORT_MASK;
+        writel(v, ch->base + M2P_PPALLOC);
+
+        v = cl->flags & EP93XX_DMA_M2P_ERROR_MASK;
+        v |= M2P_CONTROL_ENABLE | M2P_CONTROL_ERROR_IRQ_EN;
+        m2p_set_control(ch, v);
+}
+
+static void channel_disable(struct m2p_channel *ch)
+{
+        u32 v;
+
+        v = readl(ch->base + M2P_CONTROL);
+        v &= ~(M2P_CONTROL_STALL_IRQ_EN | M2P_CONTROL_NFB_IRQ_EN);
+        m2p_set_control(ch, v);
+
+        while (m2p_channel_state(ch) == STATE_ON)
+                cpu_relax();
+
+        m2p_set_control(ch, 0x0);
+
+        while (m2p_channel_state(ch) == STATE_STALL)
+                cpu_relax();
+
+        clk_disable(ch->clk);
+}
+
+int ep93xx_dma_m2p_client_register(struct ep93xx_dma_m2p_client *cl)
+{
+        struct m2p_channel *ch;
+        int err;
+
+        ch = find_free_channel(cl);
+        if (IS_ERR(ch))
+                return PTR_ERR(ch);
+
+        err = request_irq(ch->irq, m2p_irq, 0, cl->name ? : "dma-m2p", ch);
+        if (err)
+                return err;
+
+        ch->client = cl;
+        ch->next_slot = 0;
+        ch->buffer_xfer = NULL;
+        ch->buffer_next = NULL;
+        INIT_LIST_HEAD(&ch->buffers_pending);
+
+        cl->channel = ch;
+
+        channel_enable(ch);
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_client_register);
+
+void ep93xx_dma_m2p_client_unregister(struct ep93xx_dma_m2p_client *cl)
+{
+        struct m2p_channel *ch = cl->channel;
+
+        channel_disable(ch);
+        free_irq(ch->irq, ch);
+        ch->client = NULL;
+}
+EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_client_unregister);
+
+void ep93xx_dma_m2p_submit(struct ep93xx_dma_m2p_client *cl,
+                           struct ep93xx_dma_buffer *buf)
+{
+        struct m2p_channel *ch = cl->channel;
+        unsigned long flags;
+        u32 v;
+
+        spin_lock_irqsave(&ch->lock, flags);
+        v = readl(ch->base + M2P_CONTROL);
+        if (ch->buffer_xfer == NULL) {
+                ch->buffer_xfer = buf;
+                feed_buf(ch, buf);
+                cl->buffer_started(cl->cookie, buf);
+
+                v |= M2P_CONTROL_STALL_IRQ_EN;
+                m2p_set_control(ch, v);
+
+        } else if (ch->buffer_next == NULL) {
+                ch->buffer_next = buf;
+                feed_buf(ch, buf);
+
+                v |= M2P_CONTROL_NFB_IRQ_EN;
+                m2p_set_control(ch, v);
+        } else {
+                list_add_tail(&buf->list, &ch->buffers_pending);
+        }
+        spin_unlock_irqrestore(&ch->lock, flags);
+}
+EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_submit);
+
+void ep93xx_dma_m2p_submit_recursive(struct ep93xx_dma_m2p_client *cl,
+                                     struct ep93xx_dma_buffer *buf)
+{
+        struct m2p_channel *ch = cl->channel;
+
+        list_add_tail(&buf->list, &ch->buffers_pending);
+}
+EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_submit_recursive);
+
+void ep93xx_dma_m2p_flush(struct ep93xx_dma_m2p_client *cl)
+{
+        struct m2p_channel *ch = cl->channel;
+
+        channel_disable(ch);
+        ch->next_slot = 0;
+        ch->buffer_xfer = NULL;
+        ch->buffer_next = NULL;
+        INIT_LIST_HEAD(&ch->buffers_pending);
+        channel_enable(ch);
+}
+EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_flush);
+
+static int init_channel(struct m2p_channel *ch)
+{
+        ch->clk = clk_get(NULL, ch->name);
+        if (IS_ERR(ch->clk))
+                return PTR_ERR(ch->clk);
+
+        spin_lock_init(&ch->lock);
+        ch->client = NULL;
+
+        return 0;
+}
+
+static int __init ep93xx_dma_m2p_init(void)
+{
+        int i;
+        int ret;
+
+        for (i = 0; m2p_rx[i].base; i++) {
+                ret = init_channel(m2p_rx + i);
+                if (ret)
+                        return ret;
+        }
+
+        for (i = 0; m2p_tx[i].base; i++) {
+                ret = init_channel(m2p_tx + i);
+                if (ret)
+                        return ret;
+        }
+
+        pr_info("M2P DMA subsystem initialized\n");
+        return 0;
+}
+arch_initcall(ep93xx_dma_m2p_init);
diff --git a/arch/arm/mach-ep93xx/edb9307a.c b/arch/arm/mach-ep93xx/edb9307a.c
index 5b5c22b681be..6171167d3315 100644
--- a/arch/arm/mach-ep93xx/edb9307a.c
+++ b/arch/arm/mach-ep93xx/edb9307a.c
@@ -48,12 +48,24 @@ static struct ep93xx_eth_data edb9307a_eth_data = {
         .phy_id         = 1,
 };
 
+static struct i2c_board_info __initdata edb9307a_i2c_data[] = {
+        {
+                /* On-board battery backed RTC */
+                I2C_BOARD_INFO("isl1208", 0x6f),
+        },
+        /*
+         * The I2C signals are also routed to the Expansion Connector (J4)
+         */
+};
+
 static void __init edb9307a_init_machine(void)
 {
         ep93xx_init_devices();
         platform_device_register(&edb9307a_flash);
 
         ep93xx_register_eth(&edb9307a_eth_data, 1);
+
+        ep93xx_init_i2c(edb9307a_i2c_data, ARRAY_SIZE(edb9307a_i2c_data));
 }
 
 MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board")
diff --git a/arch/arm/mach-ep93xx/include/mach/dma.h b/arch/arm/mach-ep93xx/include/mach/dma.h
new file mode 100644
index 000000000000..ef6bd9d13148
--- /dev/null
+++ b/arch/arm/mach-ep93xx/include/mach/dma.h
@@ -0,0 +1,52 @@
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#include <linux/list.h>
+#include <linux/types.h>
+
+struct ep93xx_dma_buffer {
+        struct list_head        list;
+        u32                     bus_addr;
+        u16                     size;
+};
+
+struct ep93xx_dma_m2p_client {
+        char                    *name;
+        u8                      flags;
+        void                    *cookie;
+        void                    (*buffer_started)(void *cookie,
+                                        struct ep93xx_dma_buffer *buf);
+        void                    (*buffer_finished)(void *cookie,
+                                        struct ep93xx_dma_buffer *buf,
+                                        int bytes, int error);
+
+        /* Internal to the DMA code.  */
+        void                    *channel;
+};
+
+#define EP93XX_DMA_M2P_PORT_I2S1        0x00
+#define EP93XX_DMA_M2P_PORT_I2S2        0x01
+#define EP93XX_DMA_M2P_PORT_AAC1        0x02
+#define EP93XX_DMA_M2P_PORT_AAC2        0x03
+#define EP93XX_DMA_M2P_PORT_AAC3        0x04
+#define EP93XX_DMA_M2P_PORT_I2S3        0x05
+#define EP93XX_DMA_M2P_PORT_UART1       0x06
+#define EP93XX_DMA_M2P_PORT_UART2       0x07
+#define EP93XX_DMA_M2P_PORT_UART3       0x08
+#define EP93XX_DMA_M2P_PORT_IRDA        0x09
+#define EP93XX_DMA_M2P_PORT_MASK        0x0f
+#define EP93XX_DMA_M2P_TX               0x00
+#define EP93XX_DMA_M2P_RX               0x10
+#define EP93XX_DMA_M2P_ABORT_ON_ERROR   0x20
+#define EP93XX_DMA_M2P_IGNORE_ERROR     0x40
+#define EP93XX_DMA_M2P_ERROR_MASK       0x60
+
+int  ep93xx_dma_m2p_client_register(struct ep93xx_dma_m2p_client *m2p);
+void ep93xx_dma_m2p_client_unregister(struct ep93xx_dma_m2p_client *m2p);
+void ep93xx_dma_m2p_submit(struct ep93xx_dma_m2p_client *m2p,
+                           struct ep93xx_dma_buffer *buf);
+void ep93xx_dma_m2p_submit_recursive(struct ep93xx_dma_m2p_client *m2p,
+                                     struct ep93xx_dma_buffer *buf);
+void ep93xx_dma_m2p_flush(struct ep93xx_dma_m2p_client *m2p);
+
+#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index 22d6c9a6e4ca..f66be12b856e 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -58,7 +58,8 @@
 
 
 /* AHB peripherals */
-#define EP93XX_DMA_BASE                 (EP93XX_AHB_VIRT_BASE + 0x00000000)
+#define EP93XX_DMA_BASE                 ((void __iomem *)               \
+                                         (EP93XX_AHB_VIRT_BASE + 0x00000000))
 
 #define EP93XX_ETHERNET_BASE            (EP93XX_AHB_VIRT_BASE + 0x00010000)
 #define EP93XX_ETHERNET_PHYS_BASE       (EP93XX_AHB_PHYS_BASE + 0x00010000)
diff --git a/arch/arm/mach-ep93xx/include/mach/system.h b/arch/arm/mach-ep93xx/include/mach/system.h
index 67789d0f329e..ed8f35e4f068 100644
--- a/arch/arm/mach-ep93xx/include/mach/system.h
+++ b/arch/arm/mach-ep93xx/include/mach/system.h
@@ -9,7 +9,7 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         u32 devicecfg;
 
diff --git a/arch/arm/mach-footbridge/dma.c b/arch/arm/mach-footbridge/dma.c
index 4f3506346969..e2e0df8bcee2 100644
--- a/arch/arm/mach-footbridge/dma.c
+++ b/arch/arm/mach-footbridge/dma.c
@@ -21,16 +21,16 @@
 #include <asm/hardware/dec21285.h>
 
 #if 0
-static int fb_dma_request(dmach_t channel, dma_t *dma)
+static int fb_dma_request(unsigned int chan, dma_t *dma)
 {
         return -EINVAL;
 }
 
-static void fb_dma_enable(dmach_t channel, dma_t *dma)
+static void fb_dma_enable(unsigned int chan, dma_t *dma)
 {
 }
 
-static void fb_dma_disable(dmach_t channel, dma_t *dma)
+static void fb_dma_disable(unsigned int chan, dma_t *dma)
 {
 }
 
@@ -42,7 +42,7 @@ static struct dma_ops fb_dma_ops = {
 };
 #endif
 
-void __init arch_dma_init(dma_t *dma)
+static int __init fb_dma_init(void)
 {
 #if 0
         dma[_DC21285_DMA(0)].d_ops = &fb_dma_ops;
@@ -50,6 +50,8 @@ void __init arch_dma_init(dma_t *dma)
 #endif
 #ifdef CONFIG_ISA_DMA
         if (footbridge_cfn_mode())
-                isa_init_dma(dma + _ISA_DMA(0));
+                isa_init_dma();
 #endif
+        return 0;
 }
+core_initcall(fb_dma_init);
diff --git a/arch/arm/mach-footbridge/include/mach/system.h b/arch/arm/mach-footbridge/include/mach/system.h
index 2db7f36bd6ca..0b2931566209 100644
--- a/arch/arm/mach-footbridge/include/mach/system.h
+++ b/arch/arm/mach-footbridge/include/mach/system.h
@@ -18,7 +18,7 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         if (mode == 's') {
                 /*
diff --git a/arch/arm/mach-gemini/Kconfig b/arch/arm/mach-gemini/Kconfig
new file mode 100644
index 000000000000..515b75cf2e8b
--- /dev/null
+++ b/arch/arm/mach-gemini/Kconfig
@@ -0,0 +1,19 @@
+if ARCH_GEMINI
+
+menu "Cortina Systems Gemini Implementations"
+
+config MACH_RUT100
+        bool "Teltonika RUT100"
+        select GEMINI_MEM_SWAP
+        help
+          Say Y here if you intend to run this kernel on a
+          Teltonika 3G Router RUT100.
+
+endmenu
+
+config GEMINI_MEM_SWAP
+        bool "Gemini memory is swapped"
+        help
+          Say Y here if Gemini memory is swapped by bootloader.
+
+endif
diff --git a/arch/arm/mach-gemini/Makefile b/arch/arm/mach-gemini/Makefile
new file mode 100644
index 000000000000..719505b81821
--- /dev/null
+++ b/arch/arm/mach-gemini/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Object file lists.
+
+obj-y                   := irq.o mm.o time.o devices.o gpio.o
+
+# Board-specific support
+obj-$(CONFIG_MACH_RUT100)       += board-rut1xx.o
diff --git a/arch/arm/mach-gemini/Makefile.boot b/arch/arm/mach-gemini/Makefile.boot
new file mode 100644
index 000000000000..22a52c228d93
--- /dev/null
+++ b/arch/arm/mach-gemini/Makefile.boot
@@ -0,0 +1,9 @@
+ifeq ($(CONFIG_GEMINI_MEM_SWAP),y)
+   zreladdr-y   := 0x00008000
+params_phys-y   := 0x00000100
+initrd_phys-y   := 0x00800000
+else
+   zreladdr-y   := 0x10008000
+params_phys-y   := 0x10000100
+initrd_phys-y   := 0x10800000
+endif
diff --git a/arch/arm/mach-gemini/board-rut1xx.c b/arch/arm/mach-gemini/board-rut1xx.c
new file mode 100644
index 000000000000..e0de968e32a6
--- /dev/null
+++ b/arch/arm/mach-gemini/board-rut1xx.c
@@ -0,0 +1,95 @@
+/*
+ *  Support for Teltonika RUT1xx
+ *
+ *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "common.h"
+
+static struct gpio_keys_button rut1xx_keys[] = {
+        {
+                .code           = KEY_SETUP,
+                .gpio           = 60,
+                .active_low     = 1,
+                .desc           = "Reset to defaults",
+                .type           = EV_KEY,
+        },
+};
+
+static struct gpio_keys_platform_data rut1xx_keys_data = {
+        .buttons        = rut1xx_keys,
+        .nbuttons       = ARRAY_SIZE(rut1xx_keys),
+};
+
+static struct platform_device rut1xx_keys_device = {
+        .name   = "gpio-keys",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &rut1xx_keys_data,
+        },
+};
+
+static struct gpio_led rut100_leds[] = {
+        {
+                .name                   = "Power",
+                .default_trigger        = "heartbeat",
+                .gpio                   = 17,
+        },
+        {
+                .name                   = "GSM",
+                .default_trigger        = "default-on",
+                .gpio                   = 7,
+                .active_low             = 1,
+        },
+};
+
+static struct gpio_led_platform_data rut100_leds_data = {
+        .num_leds       = ARRAY_SIZE(rut100_leds),
+        .leds           = rut100_leds,
+};
+
+static struct platform_device rut1xx_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &rut100_leds_data,
+        },
+};
+
+static struct sys_timer rut1xx_timer = {
+        .init   = gemini_timer_init,
+};
+
+static void __init rut1xx_init(void)
+{
+        gemini_gpio_init();
+        platform_register_uart();
+        platform_register_pflash(SZ_8M, NULL, 0);
+        platform_device_register(&rut1xx_leds);
+        platform_device_register(&rut1xx_keys_device);
+}
+
+MACHINE_START(RUT100, "Teltonika RUT100")
+        .phys_io        = 0x7fffc000,
+        .io_pg_offst    = ((0xffffc000) >> 18) & 0xfffc,
+        .boot_params    = 0x100,
+        .map_io         = gemini_map_io,
+        .init_irq       = gemini_init_irq,
+        .timer          = &rut1xx_timer,
+        .init_machine   = rut1xx_init,
+MACHINE_END
diff --git a/arch/arm/mach-gemini/common.h b/arch/arm/mach-gemini/common.h
new file mode 100644
index 000000000000..9392834a214f
--- /dev/null
+++ b/arch/arm/mach-gemini/common.h
@@ -0,0 +1,28 @@
+/*
+ * Common Gemini architecture functions
+ *
+ * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __GEMINI_COMMON_H__
+#define __GEMINI_COMMON_H__
+
+struct mtd_partition;
+
+extern void gemini_map_io(void);
+extern void gemini_init_irq(void);
+extern void gemini_timer_init(void);
+extern void gemini_gpio_init(void);
+
+/* Common platform devices registration functions */
+extern int platform_register_uart(void);
+extern int platform_register_pflash(unsigned int size,
+                                    struct mtd_partition *parts,
+                                    unsigned int nr_parts);
+
+#endif /* __GEMINI_COMMON_H__ */
diff --git a/arch/arm/mach-gemini/devices.c b/arch/arm/mach-gemini/devices.c
new file mode 100644
index 000000000000..6b525253d027
--- /dev/null
+++ b/arch/arm/mach-gemini/devices.c
@@ -0,0 +1,92 @@
+/*
+ * Common devices definition for Gemini
+ *
+ * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/mtd/physmap.h>
+
+#include <mach/irqs.h>
+#include <mach/hardware.h>
+#include <mach/global_reg.h>
+
+static struct plat_serial8250_port serial_platform_data[] = {
+        {
+                .membase        = (void *)IO_ADDRESS(GEMINI_UART_BASE),
+                .mapbase        = GEMINI_UART_BASE,
+                .irq            = IRQ_UART,
+                .uartclk        = UART_CLK,
+                .regshift       = 2,
+                .iotype         = UPIO_MEM,
+                .type           = PORT_16550A,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_FIXED_TYPE,
+        },
+        {},
+};
+
+static struct platform_device serial_device = {
+        .name   = "serial8250",
+        .id     = PLAT8250_DEV_PLATFORM,
+        .dev    = {
+                .platform_data = serial_platform_data,
+        },
+};
+
+int platform_register_uart(void)
+{
+        return platform_device_register(&serial_device);
+}
+
+static struct resource flash_resource = {
+        .start  = GEMINI_FLASH_BASE,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct physmap_flash_data pflash_platform_data = {};
+
+static struct platform_device pflash_device = {
+        .name   = "physmap-flash",
+        .id     = 0,
+        .dev    = {
+                .platform_data = &pflash_platform_data,
+        },
+        .resource = &flash_resource,
+        .num_resources = 1,
+};
+
+int platform_register_pflash(unsigned int size, struct mtd_partition *parts,
+                             unsigned int nr_parts)
+{
+        unsigned int reg;
+
+        reg = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_STATUS);
+
+        if ((reg & FLASH_TYPE_MASK) != FLASH_TYPE_PARALLEL)
+                return -ENXIO;
+
+        if (reg & FLASH_WIDTH_16BIT)
+                pflash_platform_data.width = 2;
+        else
+                pflash_platform_data.width = 1;
+
+        /* enable parallel flash pins and disable others */
+        reg = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL);
+        reg &= ~PFLASH_PADS_DISABLE;
+        reg |= SFLASH_PADS_DISABLE | NAND_PADS_DISABLE;
+        __raw_writel(reg, IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL);
+
+        flash_resource.end = flash_resource.start + size - 1;
+
+        pflash_platform_data.parts = parts;
+        pflash_platform_data.nr_parts = nr_parts;
+
+        return platform_device_register(&pflash_device);
+}
diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c
new file mode 100644
index 000000000000..e7263854bc7b
--- /dev/null
+++ b/arch/arm/mach-gemini/gpio.c
@@ -0,0 +1,232 @@
+/*
+ * Gemini gpiochip and interrupt routines
+ *
+ * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * Based on plat-mxc/gpio.c:
+ *  MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
+ *  Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+
+#define GPIO_BASE(x)            IO_ADDRESS(GEMINI_GPIO_BASE(x))
+
+/* GPIO registers definition */
+#define GPIO_DATA_OUT           0x0
+#define GPIO_DATA_IN            0x4
+#define GPIO_DIR                0x8
+#define GPIO_DATA_SET           0x10
+#define GPIO_DATA_CLR           0x14
+#define GPIO_PULL_EN            0x18
+#define GPIO_PULL_TYPE          0x1C
+#define GPIO_INT_EN             0x20
+#define GPIO_INT_STAT           0x24
+#define GPIO_INT_MASK           0x2C
+#define GPIO_INT_CLR            0x30
+#define GPIO_INT_TYPE           0x34
+#define GPIO_INT_BOTH_EDGE      0x38
+#define GPIO_INT_LEVEL          0x3C
+#define GPIO_DEBOUNCE_EN        0x40
+#define GPIO_DEBOUNCE_PRESCALE  0x44
+
+#define GPIO_PORT_NUM           3
+
+static void _set_gpio_irqenable(unsigned int base, unsigned int index,
+                                int enable)
+{
+        unsigned int reg;
+
+        reg = __raw_readl(base + GPIO_INT_EN);
+        reg = (reg & (~(1 << index))) | (!!enable << index);
+        __raw_writel(reg, base + GPIO_INT_EN);
+}
+
+static void gpio_ack_irq(unsigned int irq)
+{
+        unsigned int gpio = irq_to_gpio(irq);
+        unsigned int base = GPIO_BASE(gpio / 32);
+
+        __raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR);
+}
+
+static void gpio_mask_irq(unsigned int irq)
+{
+        unsigned int gpio = irq_to_gpio(irq);
+        unsigned int base = GPIO_BASE(gpio / 32);
+
+        _set_gpio_irqenable(base, gpio % 32, 0);
+}
+
+static void gpio_unmask_irq(unsigned int irq)
+{
+        unsigned int gpio = irq_to_gpio(irq);
+        unsigned int base = GPIO_BASE(gpio / 32);
+
+        _set_gpio_irqenable(base, gpio % 32, 1);
+}
+
+static int gpio_set_irq_type(unsigned int irq, unsigned int type)
+{
+        unsigned int gpio = irq_to_gpio(irq);
+        unsigned int gpio_mask = 1 << (gpio % 32);
+        unsigned int base = GPIO_BASE(gpio / 32);
+        unsigned int reg_both, reg_level, reg_type;
+
+        reg_type = __raw_readl(base + GPIO_INT_TYPE);
+        reg_level = __raw_readl(base + GPIO_INT_BOTH_EDGE);
+        reg_both = __raw_readl(base + GPIO_INT_BOTH_EDGE);
+
+        switch (type) {
+        case IRQ_TYPE_EDGE_BOTH:
+                reg_type &= ~gpio_mask;
+                reg_both |= gpio_mask;
+                break;
+        case IRQ_TYPE_EDGE_RISING:
+                reg_type &= ~gpio_mask;
+                reg_both &= ~gpio_mask;
+                reg_level &= ~gpio_mask;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                reg_type &= ~gpio_mask;
+                reg_both &= ~gpio_mask;
+                reg_level |= gpio_mask;
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                reg_type |= gpio_mask;
+                reg_level &= ~gpio_mask;
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                reg_type |= gpio_mask;
+                reg_level |= gpio_mask;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        __raw_writel(reg_type, base + GPIO_INT_TYPE);
+        __raw_writel(reg_level, base + GPIO_INT_BOTH_EDGE);
+        __raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE);
+
+        gpio_ack_irq(irq);
+
+        return 0;
+}
+
+static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned int gpio_irq_no, irq_stat;
+        unsigned int port = (unsigned int)get_irq_data(irq);
+
+        irq_stat = __raw_readl(GPIO_BASE(port) + GPIO_INT_STAT);
+
+        gpio_irq_no = GPIO_IRQ_BASE + port * 32;
+        for (; irq_stat != 0; irq_stat >>= 1, gpio_irq_no++) {
+
+                if ((irq_stat & 1) == 0)
+                        continue;
+
+                BUG_ON(!(irq_desc[gpio_irq_no].handle_irq));
+                irq_desc[gpio_irq_no].handle_irq(gpio_irq_no,
+                                &irq_desc[gpio_irq_no]);
+        }
+}
+
+static struct irq_chip gpio_irq_chip = {
+        .name = "GPIO",
+        .ack = gpio_ack_irq,
+        .mask = gpio_mask_irq,
+        .unmask = gpio_unmask_irq,
+        .set_type = gpio_set_irq_type,
+};
+
+static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
+                                int dir)
+{
+        unsigned int base = GPIO_BASE(offset / 32);
+        unsigned int reg;
+
+        reg = __raw_readl(base + GPIO_DIR);
+        if (dir)
+                reg |= 1 << (offset % 32);
+        else
+                reg &= ~(1 << (offset % 32));
+        __raw_writel(reg, base + GPIO_DIR);
+}
+
+static void gemini_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        unsigned int base = GPIO_BASE(offset / 32);
+
+        if (value)
+                __raw_writel(1 << (offset % 32), base + GPIO_DATA_SET);
+        else
+                __raw_writel(1 << (offset % 32), base + GPIO_DATA_CLR);
+}
+
+static int gemini_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        unsigned int base = GPIO_BASE(offset / 32);
+
+        return (__raw_readl(base + GPIO_DATA_IN) >> (offset % 32)) & 1;
+}
+
+static int gemini_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        _set_gpio_direction(chip, offset, 0);
+        return 0;
+}
+
+static int gemini_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
+                                        int value)
+{
+        _set_gpio_direction(chip, offset, 1);
+        gemini_gpio_set(chip, offset, value);
+        return 0;
+}
+
+static struct gpio_chip gemini_gpio_chip = {
+        .label                  = "Gemini",
+        .direction_input        = gemini_gpio_direction_input,
+        .get                    = gemini_gpio_get,
+        .direction_output       = gemini_gpio_direction_output,
+        .set                    = gemini_gpio_set,
+        .base                   = 0,
+        .ngpio                  = GPIO_PORT_NUM * 32,
+};
+
+void __init gemini_gpio_init(void)
+{
+        int i, j;
+
+        for (i = 0; i < GPIO_PORT_NUM; i++) {
+                /* disable, unmask and clear all interrupts */
+                __raw_writel(0x0, GPIO_BASE(i) + GPIO_INT_EN);
+                __raw_writel(0x0, GPIO_BASE(i) + GPIO_INT_MASK);
+                __raw_writel(~0x0, GPIO_BASE(i) + GPIO_INT_CLR);
+
+                for (j = GPIO_IRQ_BASE + i * 32;
+                     j < GPIO_IRQ_BASE + (i + 1) * 32; j++) {
+                        set_irq_chip(j, &gpio_irq_chip);
+                        set_irq_handler(j, handle_edge_irq);
+                        set_irq_flags(j, IRQF_VALID);
+                }
+
+                set_irq_chained_handler(IRQ_GPIO(i), gpio_irq_handler);
+                set_irq_data(IRQ_GPIO(i), (void *)i);
+        }
+
+        BUG_ON(gpiochip_add(&gemini_gpio_chip));
+}
diff --git a/arch/arm/mach-gemini/include/mach/debug-macro.S b/arch/arm/mach-gemini/include/mach/debug-macro.S
new file mode 100644
index 000000000000..d04a6eaeae14
--- /dev/null
+++ b/arch/arm/mach-gemini/include/mach/debug-macro.S
@@ -0,0 +1,23 @@
+/*
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Copyright (C) 2001-2006 Storlink, Corp.
+ *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <mach/hardware.h>
+
+        .macro  addruart,rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                                 @ MMU enabled?
+        ldreq   \rx, =GEMINI_UART_BASE                  @ physical
+        ldrne   \rx, =IO_ADDRESS(GEMINI_UART_BASE)      @ virtual
+        .endm
+
+#define UART_SHIFT      2
+#define FLOW_CONTROL
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-gemini/include/mach/entry-macro.S b/arch/arm/mach-gemini/include/mach/entry-macro.S
new file mode 100644
index 000000000000..1624f91a2b8b
--- /dev/null
+++ b/arch/arm/mach-gemini/include/mach/entry-macro.S
@@ -0,0 +1,39 @@
+/*
+ * Low-level IRQ helper macros for Gemini platform.
+ *
+ *  Copyright (C) 2001-2006 Storlink, Corp.
+ *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/hardware.h>
+
+#define IRQ_STATUS      0x14
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        ldr     \irqstat, =IO_ADDRESS(GEMINI_INTERRUPT_BASE + IRQ_STATUS)
+        ldr     \irqnr, [\irqstat]
+        cmp     \irqnr, #0
+        beq     2313f
+        mov     \tmp, \irqnr
+        mov     \irqnr, #0
+2312:
+        tst     \tmp, #1
+        bne     2313f
+        add     \irqnr, \irqnr, #1
+        mov     \tmp, \tmp, lsr #1
+        cmp     \irqnr, #31
+        bcc     2312b
+2313:
+        .endm
diff --git a/arch/arm/mach-gemini/include/mach/global_reg.h b/arch/arm/mach-gemini/include/mach/global_reg.h
new file mode 100644
index 000000000000..de7ff7e849fc
--- /dev/null
+++ b/arch/arm/mach-gemini/include/mach/global_reg.h
@@ -0,0 +1,278 @@
+/*
+ *  This file contains the hardware definitions for Gemini.
+ *
+ *  Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __MACH_GLOBAL_REG_H
+#define __MACH_GLOBAL_REG_H
+
+/* Global Word ID Register*/
+#define GLOBAL_ID                       0x00
+
+#define CHIP_ID(reg)                    ((reg) >> 8)
+#define CHIP_REVISION(reg)              ((reg) & 0xFF)
+
+/* Global Status Register */
+#define GLOBAL_STATUS                   0x04
+
+#define CPU_BIG_ENDIAN                  (1 << 31)
+#define PLL_OSC_30M                     (1 << 30)       /* else 60MHz */
+
+#define OPERATION_MODE_MASK             (0xF << 26)
+#define OPM_IDDQ                        (0xF << 26)
+#define OPM_NAND                        (0xE << 26)
+#define OPM_RING                        (0xD << 26)
+#define OPM_DIRECT_BOOT                 (0xC << 26)
+#define OPM_USB1_PHY_TEST               (0xB << 26)
+#define OPM_USB0_PHY_TEST               (0xA << 26)
+#define OPM_SATA1_PHY_TEST              (0x9 << 26)
+#define OPM_SATA0_PHY_TEST              (0x8 << 26)
+#define OPM_ICE_ARM                     (0x7 << 26)
+#define OPM_ICE_FARADAY                 (0x6 << 26)
+#define OPM_PLL_BYPASS                  (0x5 << 26)
+#define OPM_DEBUG                       (0x4 << 26)
+#define OPM_BURN_IN                     (0x3 << 26)
+#define OPM_MBIST                       (0x2 << 26)
+#define OPM_SCAN                        (0x1 << 26)
+#define OPM_REAL                        (0x0 << 26)
+
+#define FLASH_TYPE_MASK                 (0x3 << 24)
+#define FLASH_TYPE_NAND_2K              (0x3 << 24)
+#define FLASH_TYPE_NAND_512             (0x2 << 24)
+#define FLASH_TYPE_PARALLEL             (0x1 << 24)
+#define FLASH_TYPE_SERIAL               (0x0 << 24)
+/* if parallel */
+#define FLASH_WIDTH_16BIT               (1 << 23)       /* else 8 bit */
+/* if serial */
+#define FLASH_ATMEL                     (1 << 23)       /* else STM */
+
+#define FLASH_SIZE_MASK                 (0x3 << 21)
+#define NAND_256M                       (0x3 << 21)     /* and more */
+#define NAND_128M                       (0x2 << 21)
+#define NAND_64M                        (0x1 << 21)
+#define NAND_32M                        (0x0 << 21)
+#define ATMEL_16M                       (0x3 << 21)     /* and more */
+#define ATMEL_8M                        (0x2 << 21)
+#define ATMEL_4M_2M                     (0x1 << 21)
+#define ATMEL_1M                        (0x0 << 21)     /* and less */
+#define STM_32M                         (1 << 22)       /* and more */
+#define STM_16M                         (0 << 22)       /* and less */
+
+#define FLASH_PARALLEL_HIGH_PIN_CNT     (1 << 20)       /* else low pin cnt */
+
+#define CPU_AHB_RATIO_MASK              (0x3 << 18)
+#define CPU_AHB_1_1                     (0x0 << 18)
+#define CPU_AHB_3_2                     (0x1 << 18)
+#define CPU_AHB_24_13                   (0x2 << 18)
+#define CPU_AHB_2_1                     (0x3 << 18)
+
+#define REG_TO_AHB_SPEED(reg)           ((((reg) >> 15) & 0x7) * 10 + 130)
+#define AHB_SPEED_TO_REG(x)             ((((x - 130)) / 10) << 15)
+
+/* it is posible to override some settings, use >> OVERRIDE_xxxx_SHIFT */
+#define OVERRIDE_FLASH_TYPE_SHIFT       16
+#define OVERRIDE_FLASH_WIDTH_SHIFT      16
+#define OVERRIDE_FLASH_SIZE_SHIFT       16
+#define OVERRIDE_CPU_AHB_RATIO_SHIFT    15
+#define OVERRIDE_AHB_SPEED_SHIFT        15
+
+/* Global PLL Control Register */
+#define GLOBAL_PLL_CTRL                 0x08
+
+#define PLL_BYPASS                      (1 << 31)
+#define PLL_POWER_DOWN                  (1 << 8)
+#define PLL_CONTROL_Q                   (0x1F << 0)
+
+/* Global Soft Reset Control Register */
+#define GLOBAL_RESET                    0x0C
+
+#define RESET_GLOBAL                    (1 << 31)
+#define RESET_CPU1                      (1 << 30)
+#define RESET_TVE                       (1 << 28)
+#define RESET_SATA1                     (1 << 27)
+#define RESET_SATA0                     (1 << 26)
+#define RESET_CIR                       (1 << 25)
+#define RESET_EXT_DEV                   (1 << 24)
+#define RESET_WD                        (1 << 23)
+#define RESET_GPIO2                     (1 << 22)
+#define RESET_GPIO1                     (1 << 21)
+#define RESET_GPIO0                     (1 << 20)
+#define RESET_SSP                       (1 << 19)
+#define RESET_UART                      (1 << 18)
+#define RESET_TIMER                     (1 << 17)
+#define RESET_RTC                       (1 << 16)
+#define RESET_INT1                      (1 << 15)
+#define RESET_INT0                      (1 << 14)
+#define RESET_LCD                       (1 << 13)
+#define RESET_LPC                       (1 << 12)
+#define RESET_APB                       (1 << 11)
+#define RESET_DMA                       (1 << 10)
+#define RESET_USB1                      (1 << 9)
+#define RESET_USB0                      (1 << 8)
+#define RESET_PCI                       (1 << 7)
+#define RESET_GMAC1                     (1 << 6)
+#define RESET_GMAC0                     (1 << 5)
+#define RESET_SECURITY                  (1 << 4)
+#define RESET_RAID                      (1 << 3)
+#define RESET_IDE                       (1 << 2)
+#define RESET_FLASH                     (1 << 1)
+#define RESET_DRAM                      (1 << 0)
+
+/* Global IO Pad Driving Capability Control Register */
+#define GLOBAL_IO_DRIVING_CTRL          0x10
+
+#define DRIVING_CURRENT_MASK            0x3
+
+/* here 00-4mA, 01-8mA, 10-12mA, 11-16mA */
+#define GPIO1_PADS_31_28_SHIFT          28
+#define GPIO0_PADS_31_16_SHIFT          26
+#define GPIO0_PADS_15_0_SHIFT           24
+#define PCI_AND_EXT_RESET_PADS_SHIFT    22
+#define IDE_PADS_SHIFT                  20
+#define GMAC1_PADS_SHIFT                18
+#define GMAC0_PADS_SHIFT                16
+/* DRAM is not in mA and poorly documented */
+#define DRAM_CLOCK_PADS_SHIFT           8
+#define DRAM_DATA_PADS_SHIFT            4
+#define DRAM_CONTROL_PADS_SHIFT         0
+
+/* Global IO Pad Slew Rate Control Register */
+#define GLOBAL_IO_SLEW_RATE_CTRL        0x14
+
+#define GPIO1_PADS_31_28_SLOW           (1 << 10)
+#define GPIO0_PADS_31_16_SLOW           (1 << 9)
+#define GPIO0_PADS_15_0_SLOW            (1 << 8)
+#define PCI_PADS_SLOW                   (1 << 7)
+#define IDE_PADS_SLOW                   (1 << 6)
+#define GMAC1_PADS_SLOW                 (1 << 5)
+#define GMAC0_PADS_SLOW                 (1 << 4)
+#define DRAM_CLOCK_PADS_SLOW            (1 << 1)
+#define DRAM_IO_PADS_SLOW               (1 << 0)
+
+/*
+ * General skew control defines
+ * 16 steps, each step is around 0.2ns
+ */
+#define SKEW_MASK                       0xF
+
+/* Global IDE PAD Skew Control Register */
+#define GLOBAL_IDE_SKEW_CTRL            0x18
+
+#define IDE1_HOST_STROBE_DELAY_SHIFT    28
+#define IDE1_DEVICE_STROBE_DELAY_SHIFT  24
+#define IDE1_OUTPUT_IO_SKEW_SHIFT       20
+#define IDE1_INPUT_IO_SKEW_SHIFT        16
+#define IDE0_HOST_STROBE_DELAY_SHIFT    12
+#define IDE0_DEVICE_STROBE_DELAY_SHIFT  8
+#define IDE0_OUTPUT_IO_SKEW_SHIFT       4
+#define IDE0_INPUT_IO_SKEW_SHIFT        0
+
+/* Global GMAC Control Pad Skew Control Register */
+#define GLOBAL_GMAC_CTRL_SKEW_CTRL      0x1C
+
+#define GMAC1_TXC_SKEW_SHIFT            28
+#define GMAC1_TXEN_SKEW_SHIFT           24
+#define GMAC1_RXC_SKEW_SHIFT            20
+#define GMAC1_RXDV_SKEW_SHIFT           16
+#define GMAC0_TXC_SKEW_SHIFT            12
+#define GMAC0_TXEN_SKEW_SHIFT           8
+#define GMAC0_RXC_SKEW_SHIFT            4
+#define GMAC0_RXDV_SKEW_SHIFT           0
+
+/* Global GMAC0 Data PAD Skew Control Register */
+#define GLOBAL_GMAC0_DATA_SKEW_CTRL     0x20
+/* Global GMAC1 Data PAD Skew Control Register */
+#define GLOBAL_GMAC1_DATA_SKEW_CTRL     0x24
+
+#define GMAC_TXD_SKEW_SHIFT(x)          (((x) * 4) + 16)
+#define GMAC_RXD_SKEW_SHIFT(x)          ((x) * 4)
+
+/* CPU has two AHB busses. */
+
+/* Global Arbitration0 Control Register */
+#define GLOBAL_ARBITRATION0_CTRL        0x28
+
+#define BOOT_CONTROLLER_HIGH_PRIO       (1 << 3)
+#define DMA_BUS1_HIGH_PRIO              (1 << 2)
+#define CPU0_HIGH_PRIO                  (1 << 0)
+
+/* Global Arbitration1 Control Register */
+#define GLOBAL_ARBITRATION1_CTRL        0x2C
+
+#define TVE_HIGH_PRIO                   (1 << 9)
+#define PCI_HIGH_PRIO                   (1 << 8)
+#define USB1_HIGH_PRIO                  (1 << 7)
+#define USB0_HIGH_PRIO                  (1 << 6)
+#define GMAC1_HIGH_PRIO                 (1 << 5)
+#define GMAC0_HIGH_PRIO                 (1 << 4)
+#define SECURITY_HIGH_PRIO              (1 << 3)
+#define RAID_HIGH_PRIO                  (1 << 2)
+#define IDE_HIGH_PRIO                   (1 << 1)
+#define DMA_BUS2_HIGH_PRIO              (1 << 0)
+
+/* Common bits for both arbitration registers */
+#define BURST_LENGTH_SHIFT              16
+#define BURST_LENGTH_MASK               (0x3F << 16)
+
+/* Miscellaneous Control Register */
+#define GLOBAL_MISC_CTRL                0x30
+
+#define MEMORY_SPACE_SWAP               (1 << 31)
+#define USB1_PLUG_MINIB                 (1 << 30) /* else plug is mini-A */
+#define USB0_PLUG_MINIB                 (1 << 29)
+#define GMAC_GMII                       (1 << 28)
+#define GMAC_1_ENABLE                   (1 << 27)
+/* TODO: define ATA/SATA bits */
+#define USB1_VBUS_ON                    (1 << 23)
+#define USB0_VBUS_ON                    (1 << 22)
+#define APB_CLKOUT_ENABLE               (1 << 21)
+#define TVC_CLKOUT_ENABLE               (1 << 20)
+#define EXT_CLKIN_ENABLE                (1 << 19)
+#define PCI_66MHZ                       (1 << 18) /* else 33 MHz */
+#define PCI_CLKOUT_ENABLE               (1 << 17)
+#define LPC_CLKOUT_ENABLE               (1 << 16)
+#define USB1_WAKEUP_ON                  (1 << 15)
+#define USB0_WAKEUP_ON                  (1 << 14)
+/* TODO: define PCI idle detect bits */
+#define TVC_PADS_ENABLE                 (1 << 9)
+#define SSP_PADS_ENABLE                 (1 << 8)
+#define LCD_PADS_ENABLE                 (1 << 7)
+#define LPC_PADS_ENABLE                 (1 << 6)
+#define PCI_PADS_ENABLE                 (1 << 5)
+#define IDE_PADS_ENABLE                 (1 << 4)
+#define DRAM_PADS_POWER_DOWN            (1 << 3)
+#define NAND_PADS_DISABLE               (1 << 2)
+#define PFLASH_PADS_DISABLE             (1 << 1)
+#define SFLASH_PADS_DISABLE             (1 << 0)
+
+/* Global Clock Control Register */
+#define GLOBAL_CLOCK_CTRL               0x34
+
+#define POWER_STATE_G0                  (1 << 31)
+#define POWER_STATE_S1                  (1 << 30) /* else it is S3/S4 state */
+#define SECURITY_APB_AHB                (1 << 29)
+/* else Security APB clk will be 0.75xAHB */
+/* TODO: TVC clock divider */
+#define PCI_CLKRUN_ENABLE               (1 << 16)
+#define BOOT_CLK_DISABLE                (1 << 13)
+#define TVC_CLK_DISABLE                 (1 << 12)
+#define FLASH_CLK_DISABLE               (1 << 11)
+#define DDR_CLK_DISABLE                 (1 << 10)
+#define PCI_CLK_DISABLE                 (1 << 9)
+#define IDE_CLK_DISABLE                 (1 << 8)
+#define USB1_CLK_DISABLE                (1 << 7)
+#define USB0_CLK_DISABLE                (1 << 6)
+#define SATA1_CLK_DISABLE               (1 << 5)
+#define SATA0_CLK_DISABLE               (1 << 4)
+#define GMAC1_CLK_DISABLE               (1 << 3)
+#define GMAC0_CLK_DISABLE               (1 << 2)
+#define SECURITY_CLK_DISABLE            (1 << 1)
+
+/* TODO: other registers definitions if needed */
+
+#endif /* __MACH_GLOBAL_REG_H */
diff --git a/arch/arm/mach-gemini/include/mach/gpio.h b/arch/arm/mach-gemini/include/mach/gpio.h
new file mode 100644
index 000000000000..3bc2c70f2989
--- /dev/null
+++ b/arch/arm/mach-gemini/include/mach/gpio.h
@@ -0,0 +1,25 @@
+/*
+ * Gemini gpiolib specific defines
+ *
+ * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __MACH_GPIO_H__
+#define __MACH_GPIO_H__
+
+#include <mach/irqs.h>
+#include <asm-generic/gpio.h>
+
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+
+#define gpio_to_irq(x)  ((x) + GPIO_IRQ_BASE)
+#define irq_to_gpio(x)  ((x) - GPIO_IRQ_BASE)
+
+#endif /* __MACH_GPIO_H__ */
diff --git a/arch/arm/mach-gemini/include/mach/hardware.h b/arch/arm/mach-gemini/include/mach/hardware.h
new file mode 100644
index 000000000000..de6752674c05
--- /dev/null
+++ b/arch/arm/mach-gemini/include/mach/hardware.h
@@ -0,0 +1,75 @@
+/*
+ *  This file contains the hardware definitions for Gemini.
+ *
+ *  Copyright (C) 2001-2006 Storlink, Corp.
+ *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __MACH_HARDWARE_H
+#define __MACH_HARDWARE_H
+
+/*
+ * Memory Map definitions
+ */
+/* FIXME: Does it really swap SRAM like this? */
+#ifdef CONFIG_GEMINI_MEM_SWAP
+# define GEMINI_DRAM_BASE       0x00000000
+# define GEMINI_SRAM_BASE       0x20000000
+#else
+# define GEMINI_SRAM_BASE       0x00000000
+# define GEMINI_DRAM_BASE       0x10000000
+#endif
+#define GEMINI_FLASH_BASE       0x30000000
+#define GEMINI_GLOBAL_BASE      0x40000000
+#define GEMINI_WAQTCHDOG_BASE   0x41000000
+#define GEMINI_UART_BASE        0x42000000
+#define GEMINI_TIMER_BASE       0x43000000
+#define GEMINI_LCD_BASE         0x44000000
+#define GEMINI_RTC_BASE         0x45000000
+#define GEMINI_SATA_BASE        0x46000000
+#define GEMINI_LPC_HOST_BASE    0x47000000
+#define GEMINI_LPC_IO_BASE      0x47800000
+#define GEMINI_INTERRUPT_BASE   0x48000000
+/* TODO: Different interrupt controlers when SMP
+ * #define GEMINI_INTERRUPT0_BASE       0x48000000
+ * #define GEMINI_INTERRUPT1_BASE       0x49000000
+ */
+#define GEMINI_SSP_CTRL_BASE    0x4A000000
+#define GEMINI_POWER_CTRL_BASE  0x4B000000
+#define GEMINI_CIR_BASE         0x4C000000
+#define GEMINI_GPIO_BASE(x)     (0x4D000000 + (x) * 0x1000000)
+#define GEMINI_PCI_IO_BASE      0x50000000
+#define GEMINI_PCI_MEM_BASE     0x58000000
+#define GEMINI_TOE_BASE         0x60000000
+#define GEMINI_GMAC0_BASE       0x6000A000
+#define GEMINI_GMAC1_BASE       0x6000E000
+#define GEMINI_SECURITY_BASE    0x62000000
+#define GEMINI_IDE0_BASE        0x63000000
+#define GEMINI_IDE1_BASE        0x63400000
+#define GEMINI_RAID_BASE        0x64000000
+#define GEMINI_FLASH_CTRL_BASE  0x65000000
+#define GEMINI_DRAM_CTRL_BASE   0x66000000
+#define GEMINI_GENERAL_DMA_BASE 0x67000000
+#define GEMINI_USB0_BASE        0x68000000
+#define GEMINI_USB1_BASE        0x69000000
+#define GEMINI_BIG_ENDIAN_BASE  0x80000000
+
+#define GEMINI_TIMER1_BASE      GEMINI_TIMER_BASE
+#define GEMINI_TIMER2_BASE      (GEMINI_TIMER_BASE + 0x10)
+#define GEMINI_TIMER3_BASE      (GEMINI_TIMER_BASE + 0x20)
+
+/*
+ * UART Clock when System clk is 150MHz
+ */
+#define UART_CLK        48000000
+
+/*
+ * macro to get at IO space when running virtually
+ */
+#define IO_ADDRESS(x)   ((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000)
+
+#endif
diff --git a/arch/arm/mach-gemini/include/mach/io.h b/arch/arm/mach-gemini/include/mach/io.h
new file mode 100644
index 000000000000..c548056b98b2
--- /dev/null
+++ b/arch/arm/mach-gemini/include/mach/io.h
@@ -0,0 +1,18 @@
+/*
+ *  Copyright (C) 2001-2006 Storlink, Corp.
+ *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __MACH_IO_H
+#define __MACH_IO_H
+
+#define IO_SPACE_LIMIT  0xffffffff
+
+#define __io(a)         __typesafe_io(a)
+#define __mem_pci(a)    (a)
+
+#endif /* __MACH_IO_H */
diff --git a/arch/arm/mach-gemini/include/mach/irqs.h b/arch/arm/mach-gemini/include/mach/irqs.h
new file mode 100644
index 000000000000..06bc47e77e8b
--- /dev/null
+++ b/arch/arm/mach-gemini/include/mach/irqs.h
@@ -0,0 +1,53 @@
+/*
+ *  Copyright (C) 2001-2006 Storlink, Corp.
+ *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __MACH_IRQS_H__
+#define __MACH_IRQS_H__
+
+#define IRQ_SERIRQ1     31
+#define IRQ_SERIRQ0     30
+#define IRQ_PCID        29
+#define IRQ_PCIC        28
+#define IRQ_PCIB        27
+#define IRQ_PWR         26
+#define IRQ_CIR         25
+#define IRQ_GPIO(x)     (22 + (x))
+#define IRQ_SSP         21
+#define IRQ_LPC         20
+#define IRQ_LCD         19
+#define IRQ_UART        18
+#define IRQ_RTC         17
+#define IRQ_TIMER3      16
+#define IRQ_TIMER2      15
+#define IRQ_TIMER1      14
+#define IRQ_FLASH       12
+#define IRQ_USB1        11
+#define IRQ_USB0        10
+#define IRQ_DMA         9
+#define IRQ_PCI         8
+#define IRQ_IPSEC       7
+#define IRQ_RAID        6
+#define IRQ_IDE1        5
+#define IRQ_IDE0        4
+#define IRQ_WATCHDOG    3
+#define IRQ_GMAC1       2
+#define IRQ_GMAC0       1
+#define IRQ_IPI         0
+
+#define NORMAL_IRQ_NUM  32
+
+#define GPIO_IRQ_BASE   NORMAL_IRQ_NUM
+#define GPIO_IRQ_NUM    (3 * 32)
+
+#define ARCH_TIMER_IRQ  IRQ_TIMER2
+
+#define NR_IRQS         (NORMAL_IRQ_NUM + GPIO_IRQ_NUM)
+
+#endif /* __MACH_IRQS_H__ */
diff --git a/arch/arm/mach-gemini/include/mach/memory.h b/arch/arm/mach-gemini/include/mach/memory.h
new file mode 100644
index 000000000000..2d14d5bf1f9f
--- /dev/null
+++ b/arch/arm/mach-gemini/include/mach/memory.h
@@ -0,0 +1,19 @@
+/*
+ *  Copyright (C) 2001-2006 Storlink, Corp.
+ *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __MACH_MEMORY_H
+#define __MACH_MEMORY_H
+
+#ifdef CONFIG_GEMINI_MEM_SWAP
+# define PHYS_OFFSET    UL(0x00000000)
+#else
+# define PHYS_OFFSET    UL(0x10000000)
+#endif
+
+#endif /* __MACH_MEMORY_H */
diff --git a/arch/arm/mach-gemini/include/mach/system.h b/arch/arm/mach-gemini/include/mach/system.h
new file mode 100644
index 000000000000..bbbd72767a02
--- /dev/null
+++ b/arch/arm/mach-gemini/include/mach/system.h
@@ -0,0 +1,37 @@
+/*
+ *  Copyright (C) 2001-2006 Storlink, Corp.
+ *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __MACH_SYSTEM_H
+#define __MACH_SYSTEM_H
+
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/global_reg.h>
+
+static inline void arch_idle(void)
+{
+        /*
+         * Because of broken hardware we have to enable interrupts or the CPU
+         * will never wakeup... Acctualy it is not very good to enable
+         * interrupts here since scheduler can miss a tick, but there is
+         * no other way around this. Platforms that needs it for power saving
+         * should call enable_hlt() in init code, since by default it is
+         * disabled.
+         */
+        local_irq_enable();
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        __raw_writel(RESET_GLOBAL | RESET_CPU1,
+                     IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_RESET);
+}
+
+#endif /* __MACH_SYSTEM_H */
diff --git a/arch/arm/mach-gemini/include/mach/timex.h b/arch/arm/mach-gemini/include/mach/timex.h
new file mode 100644
index 000000000000..dc5690ba975c
--- /dev/null
+++ b/arch/arm/mach-gemini/include/mach/timex.h
@@ -0,0 +1,13 @@
+/*
+ * Gemini timex specifications
+ *
+ * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/* When AHB bus frequency is 150MHz */
+#define CLOCK_TICK_RATE 38000000
diff --git a/arch/arm/mach-gemini/include/mach/uncompress.h b/arch/arm/mach-gemini/include/mach/uncompress.h
new file mode 100644
index 000000000000..59c5df7e716c
--- /dev/null
+++ b/arch/arm/mach-gemini/include/mach/uncompress.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * Based on mach-pxa/include/mach/uncompress.h:
+ * Copyright:   (C) 2001 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __MACH_UNCOMPRESS_H
+#define __MACH_UNCOMPRESS_H
+
+#include <linux/serial_reg.h>
+#include <mach/hardware.h>
+
+static volatile unsigned long *UART = (unsigned long *)GEMINI_UART_BASE;
+
+/*
+ * The following code assumes the serial port has already been
+ * initialized by the bootloader.  If you didn't setup a port in
+ * your bootloader then nothing will appear (which might be desired).
+ */
+static inline void putc(char c)
+{
+        while (!(UART[UART_LSR] & UART_LSR_THRE))
+                barrier();
+        UART[UART_TX] = c;
+}
+
+#define flush() do { } while (0)
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
+
+#endif /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-gemini/include/mach/vmalloc.h b/arch/arm/mach-gemini/include/mach/vmalloc.h
new file mode 100644
index 000000000000..83e536d9436c
--- /dev/null
+++ b/arch/arm/mach-gemini/include/mach/vmalloc.h
@@ -0,0 +1,10 @@
+/*
+ *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#define VMALLOC_END     0xF0000000
diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c
new file mode 100644
index 000000000000..9e613ca8120d
--- /dev/null
+++ b/arch/arm/mach-gemini/irq.c
@@ -0,0 +1,102 @@
+/*
+ *  Interrupt routines for Gemini
+ *
+ *  Copyright (C) 2001-2006 Storlink, Corp.
+ *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/stddef.h>
+#include <linux/list.h>
+#include <linux/sched.h>
+#include <asm/irq.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+
+#define IRQ_SOURCE(base_addr)   (base_addr + 0x00)
+#define IRQ_MASK(base_addr)     (base_addr + 0x04)
+#define IRQ_CLEAR(base_addr)    (base_addr + 0x08)
+#define IRQ_TMODE(base_addr)    (base_addr + 0x0C)
+#define IRQ_TLEVEL(base_addr)   (base_addr + 0x10)
+#define IRQ_STATUS(base_addr)   (base_addr + 0x14)
+#define FIQ_SOURCE(base_addr)   (base_addr + 0x20)
+#define FIQ_MASK(base_addr)     (base_addr + 0x24)
+#define FIQ_CLEAR(base_addr)    (base_addr + 0x28)
+#define FIQ_TMODE(base_addr)    (base_addr + 0x2C)
+#define FIQ_LEVEL(base_addr)    (base_addr + 0x30)
+#define FIQ_STATUS(base_addr)   (base_addr + 0x34)
+
+static void gemini_ack_irq(unsigned int irq)
+{
+        __raw_writel(1 << irq, IRQ_CLEAR(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
+}
+
+static void gemini_mask_irq(unsigned int irq)
+{
+        unsigned int mask;
+
+        mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
+        mask &= ~(1 << irq);
+        __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
+}
+
+static void gemini_unmask_irq(unsigned int irq)
+{
+        unsigned int mask;
+
+        mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
+        mask |= (1 << irq);
+        __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
+}
+
+static struct irq_chip gemini_irq_chip = {
+        .name   = "INTC",
+        .ack    = gemini_ack_irq,
+        .mask   = gemini_mask_irq,
+        .unmask = gemini_unmask_irq,
+};
+
+static struct resource irq_resource = {
+        .name   = "irq_handler",
+        .start  = IO_ADDRESS(GEMINI_INTERRUPT_BASE),
+        .end    = IO_ADDRESS(FIQ_STATUS(GEMINI_INTERRUPT_BASE)) + 4,
+};
+
+void __init gemini_init_irq(void)
+{
+        unsigned int i, mode = 0, level = 0;
+
+        /*
+         * Disable arch_idle() by default since it is buggy
+         * For more info see arch/arm/mach-gemini/include/mach/system.h
+         */
+        disable_hlt();
+
+        request_resource(&iomem_resource, &irq_resource);
+
+        for (i = 0; i < NR_IRQS; i++) {
+                set_irq_chip(i, &gemini_irq_chip);
+                if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) {
+                        set_irq_handler(i, handle_edge_irq);
+                        mode |= 1 << i;
+                        level |= 1 << i;
+                } else {                        
+                        set_irq_handler(i, handle_level_irq);
+                }
+                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+        }
+
+        /* Disable all interrupts */
+        __raw_writel(0, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
+        __raw_writel(0, FIQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
+
+        /* Set interrupt mode */
+        __raw_writel(mode, IRQ_TMODE(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
+        __raw_writel(level, IRQ_TLEVEL(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
+}
diff --git a/arch/arm/mach-gemini/mm.c b/arch/arm/mach-gemini/mm.c
new file mode 100644
index 000000000000..51948242ec09
--- /dev/null
+++ b/arch/arm/mach-gemini/mm.c
@@ -0,0 +1,82 @@
+/*
+ *  Static mappings for Gemini
+ *
+ *  Copyright (C) 2001-2006 Storlink, Corp.
+ *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/mm.h>
+#include <linux/init.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+
+/* Page table mapping for I/O region */
+static struct map_desc gemini_io_desc[] __initdata = {
+        {
+                .virtual        = IO_ADDRESS(GEMINI_GLOBAL_BASE),
+                .pfn            =__phys_to_pfn(GEMINI_GLOBAL_BASE),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(GEMINI_UART_BASE),
+                .pfn            = __phys_to_pfn(GEMINI_UART_BASE),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(GEMINI_TIMER_BASE),
+                .pfn            = __phys_to_pfn(GEMINI_TIMER_BASE),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(GEMINI_INTERRUPT_BASE),
+                .pfn            = __phys_to_pfn(GEMINI_INTERRUPT_BASE),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(GEMINI_POWER_CTRL_BASE),
+                .pfn            = __phys_to_pfn(GEMINI_POWER_CTRL_BASE),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(GEMINI_GPIO_BASE(0)),
+                .pfn            = __phys_to_pfn(GEMINI_GPIO_BASE(0)),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(GEMINI_GPIO_BASE(1)),
+                .pfn            = __phys_to_pfn(GEMINI_GPIO_BASE(1)),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(GEMINI_GPIO_BASE(2)),
+                .pfn            = __phys_to_pfn(GEMINI_GPIO_BASE(2)),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(GEMINI_FLASH_CTRL_BASE),
+                .pfn            = __phys_to_pfn(GEMINI_FLASH_CTRL_BASE),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(GEMINI_DRAM_CTRL_BASE),
+                .pfn            = __phys_to_pfn(GEMINI_DRAM_CTRL_BASE),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(GEMINI_GENERAL_DMA_BASE),
+                .pfn            = __phys_to_pfn(GEMINI_GENERAL_DMA_BASE),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        },
+};
+
+void __init gemini_map_io(void)
+{
+        iotable_init(gemini_io_desc, ARRAY_SIZE(gemini_io_desc));
+}
diff --git a/arch/arm/mach-gemini/time.c b/arch/arm/mach-gemini/time.c
new file mode 100644
index 000000000000..21dc5a89d1c4
--- /dev/null
+++ b/arch/arm/mach-gemini/time.c
@@ -0,0 +1,89 @@
+/*
+ *  Copyright (C) 2001-2006 Storlink, Corp.
+ *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/global_reg.h>
+#include <asm/mach/time.h>
+
+/*
+ * Register definitions for the timers
+ */
+#define TIMER_COUNT(BASE_ADDR)          (BASE_ADDR  + 0x00)
+#define TIMER_LOAD(BASE_ADDR)           (BASE_ADDR  + 0x04)
+#define TIMER_MATCH1(BASE_ADDR)         (BASE_ADDR  + 0x08)
+#define TIMER_MATCH2(BASE_ADDR)         (BASE_ADDR  + 0x0C)
+#define TIMER_CR(BASE_ADDR)             (BASE_ADDR  + 0x30)
+
+#define TIMER_1_CR_ENABLE               (1 << 0)
+#define TIMER_1_CR_CLOCK                (1 << 1)
+#define TIMER_1_CR_INT                  (1 << 2)
+#define TIMER_2_CR_ENABLE               (1 << 3)
+#define TIMER_2_CR_CLOCK                (1 << 4)
+#define TIMER_2_CR_INT                  (1 << 5)
+#define TIMER_3_CR_ENABLE               (1 << 6)
+#define TIMER_3_CR_CLOCK                (1 << 7)
+#define TIMER_3_CR_INT                  (1 << 8)
+
+/*
+ * IRQ handler for the timer
+ */
+static irqreturn_t gemini_timer_interrupt(int irq, void *dev_id)
+{
+        timer_tick();
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction gemini_timer_irq = {
+        .name           = "Gemini Timer Tick",
+        .flags          = IRQF_DISABLED | IRQF_TIMER,
+        .handler        = gemini_timer_interrupt,
+};
+
+/*
+ * Set up timer interrupt, and return the current time in seconds.
+ */
+void __init gemini_timer_init(void)
+{
+        unsigned int tick_rate, reg_v;
+
+        reg_v = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE + GLOBAL_STATUS));
+        tick_rate = REG_TO_AHB_SPEED(reg_v) * 1000000;
+
+        printk(KERN_INFO "Bus: %dMHz", tick_rate / 1000000);
+
+        tick_rate /= 6;         /* APB bus run AHB*(1/6) */
+
+        switch(reg_v & CPU_AHB_RATIO_MASK) {
+        case CPU_AHB_1_1:
+                printk(KERN_CONT "(1/1)\n");
+                break;
+        case CPU_AHB_3_2:
+                printk(KERN_CONT "(3/2)\n");
+                break;
+        case CPU_AHB_24_13:
+                printk(KERN_CONT "(24/13)\n");
+                break;
+        case CPU_AHB_2_1:
+                printk(KERN_CONT "(2/1)\n");
+                break;
+        }
+
+        /*
+         * Make irqs happen for the system timer
+         */
+        setup_irq(IRQ_TIMER2, &gemini_timer_irq);
+        /* Start the timer */
+        __raw_writel(tick_rate / HZ, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE)));
+        __raw_writel(tick_rate / HZ, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE)));
+        __raw_writel(TIMER_2_CR_ENABLE | TIMER_2_CR_INT, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
+}
diff --git a/arch/arm/mach-h720x/include/mach/system.h b/arch/arm/mach-h720x/include/mach/system.h
index e4a7c760d52a..a708d24ee46d 100644
--- a/arch/arm/mach-h720x/include/mach/system.h
+++ b/arch/arm/mach-h720x/include/mach/system.h
@@ -25,7 +25,7 @@ static void arch_idle(void)
 }
 
 
-static __inline__ void arch_reset(char mode)
+static __inline__ void arch_reset(char mode, const char *cmd)
 {
         CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET;
 }
diff --git a/arch/arm/mach-imx/generic.c b/arch/arm/mach-imx/generic.c
index 887cb21f75b0..05f1739ee127 100644
--- a/arch/arm/mach-imx/generic.c
+++ b/arch/arm/mach-imx/generic.c
@@ -29,7 +29,6 @@
 #include <linux/string.h>
 
 #include <asm/errno.h>
-#include <mach/imxfb.h>
 #include <mach/hardware.h>
 #include <mach/imx-regs.h>
 
@@ -245,43 +244,8 @@ void __init imx_set_mmc_info(struct imxmmc_platform_data *info)
         imx_mmc_device.dev.platform_data = info;
 }
 
-static struct imx_fb_platform_data imx_fb_info;
-
-void __init set_imx_fb_info(struct imx_fb_platform_data *hard_imx_fb_info)
-{
-        memcpy(&imx_fb_info,hard_imx_fb_info,sizeof(struct imx_fb_platform_data));
-}
-
-static struct resource imxfb_resources[] = {
-        [0] = {
-                .start  = 0x00205000,
-                .end    = 0x002050FF,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = LCDC_INT,
-                .end    = LCDC_INT,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static u64 fb_dma_mask = ~(u64)0;
-
-static struct platform_device imxfb_device = {
-        .name           = "imx-fb",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &imx_fb_info,
-                .dma_mask       = &fb_dma_mask,
-                .coherent_dma_mask = 0xffffffff,
-        },
-        .num_resources  = ARRAY_SIZE(imxfb_resources),
-        .resource       = imxfb_resources,
-};
-
 static struct platform_device *devices[] __initdata = {
         &imx_mmc_device,
-        &imxfb_device,
 };
 
 static struct map_desc imx_io_desc[] __initdata = {
diff --git a/arch/arm/mach-imx/include/mach/system.h b/arch/arm/mach-imx/include/mach/system.h
index adee7e51bab2..46d4ca91af79 100644
--- a/arch/arm/mach-imx/include/mach/system.h
+++ b/arch/arm/mach-imx/include/mach/system.h
@@ -32,7 +32,7 @@ arch_idle(void)
 }
 
 static inline void
-arch_reset(char mode)
+arch_reset(char mode, const char *cmd)
 {
         cpu_reset(0);
 }
diff --git a/arch/arm/mach-integrator/include/mach/system.h b/arch/arm/mach-integrator/include/mach/system.h
index c485345c8c77..e1551b8dab77 100644
--- a/arch/arm/mach-integrator/include/mach/system.h
+++ b/arch/arm/mach-integrator/include/mach/system.h
@@ -32,7 +32,7 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         /*
          * To reset, we hit the on-board reset register
diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h
index e012bf13c955..42ae29b288a1 100644
--- a/arch/arm/mach-iop13xx/include/mach/memory.h
+++ b/arch/arm/mach-iop13xx/include/mach/memory.h
@@ -59,7 +59,10 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x)
         })
 
 #define __arch_page_to_dma(dev, page)                                   \
-        __arch_virt_to_dma(dev, page_address(page))
+        ({                                                              \
+                /* __is_lbus_virt() can never be true for RAM pages */  \
+                (dma_addr_t)page_to_phys(page);                         \
+        })
 
 #endif /* CONFIG_ARCH_IOP13XX */
 #endif /* !ASSEMBLY */
diff --git a/arch/arm/mach-iop13xx/include/mach/system.h b/arch/arm/mach-iop13xx/include/mach/system.h
index c7127f416e1f..d0c66ef450a7 100644
--- a/arch/arm/mach-iop13xx/include/mach/system.h
+++ b/arch/arm/mach-iop13xx/include/mach/system.h
@@ -13,7 +13,7 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         /*
          * Reset the internal bus (warning both cores are reset)
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 673b0db22034..4873f26a42e1 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -1026,8 +1026,10 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
                 which_atu = 0;
         }
 
-        if (!which_atu)
+        if (!which_atu) {
+                kfree(res);
                 return 0;
+        }
 
         switch(which_atu) {
         case IOP13XX_INIT_ATU_ATUX:
@@ -1074,6 +1076,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
                 sys->map_irq = iop13xx_pcie_map_irq;
                 break;
         default:
+                kfree(res);
                 return 0;
         }
 
diff --git a/arch/arm/mach-iop32x/include/mach/system.h b/arch/arm/mach-iop32x/include/mach/system.h
index 32d9e5b0a28d..a4b808fe0d81 100644
--- a/arch/arm/mach-iop32x/include/mach/system.h
+++ b/arch/arm/mach-iop32x/include/mach/system.h
@@ -16,7 +16,7 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         local_irq_disable();
 
diff --git a/arch/arm/mach-iop33x/include/mach/system.h b/arch/arm/mach-iop33x/include/mach/system.h
index 0cb3ad862acd..f192a34be073 100644
--- a/arch/arm/mach-iop33x/include/mach/system.h
+++ b/arch/arm/mach-iop33x/include/mach/system.h
@@ -14,7 +14,7 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         *IOP3XX_PCSR = 0x30;
 
diff --git a/arch/arm/mach-ixp2000/include/mach/system.h b/arch/arm/mach-ixp2000/include/mach/system.h
index 2e9c68f95a24..de370992c848 100644
--- a/arch/arm/mach-ixp2000/include/mach/system.h
+++ b/arch/arm/mach-ixp2000/include/mach/system.h
@@ -17,7 +17,7 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         local_irq_disable();
 
diff --git a/arch/arm/mach-ixp23xx/include/mach/system.h b/arch/arm/mach-ixp23xx/include/mach/system.h
index d57c3fc10f1f..8920ff2dff1f 100644
--- a/arch/arm/mach-ixp23xx/include/mach/system.h
+++ b/arch/arm/mach-ixp23xx/include/mach/system.h
@@ -19,7 +19,7 @@ static inline void arch_idle(void)
 #endif
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         /* First try machine specific support */
         if (machine_is_ixdp2351()) {
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index d816c51320c7..70afcfe5b881 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -366,7 +366,7 @@ void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size,
 }
 
 void __init ixp4xx_pci_preinit(void)
-{  
+{
         unsigned long cpuid = read_cpuid_id();
 
         /*
@@ -386,17 +386,17 @@ void __init ixp4xx_pci_preinit(void)
 
         pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n");
 
-        /* 
+        /*
          * We use identity AHB->PCI address translation
          * in the 0x48000000 to 0x4bffffff address space
          */
         *PCI_PCIMEMBASE = 0x48494A4B;
 
-        /* 
+        /*
          * We also use identity PCI->AHB address translation
          * in 4 16MB BARs that begin at the physical memory start
          */
-        *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) + 
+        *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) +
                 ((PHYS_OFFSET & 0xFF000000) >> 8) +
                 ((PHYS_OFFSET & 0xFF000000) >> 16) +
                 ((PHYS_OFFSET & 0xFF000000) >> 24) +
@@ -408,18 +408,19 @@ void __init ixp4xx_pci_preinit(void)
                 pr_debug("setup BARs in controller\n");
 
                 /*
-                 * We configure the PCI inbound memory windows to be 
+                 * We configure the PCI inbound memory windows to be
                  * 1:1 mapped to SDRAM
                  */
-                local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET + 0x00000000);
-                local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + 0x01000000);
-                local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + 0x02000000);
-                local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + 0x03000000);
+                local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET);
+                local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M);
+                local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M);
+                local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + SZ_48M);
 
                 /*
-                 * Enable CSR window at 0xff000000.
+                 * Enable CSR window at 64 MiB to allow PCI masters
+                 * to continue prefetching past 64 MiB boundary.
                  */
-                local_write_config(PCI_BASE_ADDRESS_4, 4, 0xff000008);
+                local_write_config(PCI_BASE_ADDRESS_4, 4, PHYS_OFFSET + SZ_64M);
 
                 /*
                  * Enable the IO window to be way up high, at 0xfffffc00
@@ -500,7 +501,7 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
         return 1;
 }
 
-struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys)
+struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys)
 {
         return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys);
 }
diff --git a/arch/arm/mach-ixp4xx/include/mach/cpu.h b/arch/arm/mach-ixp4xx/include/mach/cpu.h
index 51bd69c46d94..def7773be67c 100644
--- a/arch/arm/mach-ixp4xx/include/mach/cpu.h
+++ b/arch/arm/mach-ixp4xx/include/mach/cpu.h
@@ -17,26 +17,31 @@
 #include <asm/cputype.h>
 
 /* Processor id value in CP15 Register 0 */
-#define IXP425_PROCESSOR_ID_VALUE       0x690541c0
-#define IXP435_PROCESSOR_ID_VALUE       0x69054040
-#define IXP465_PROCESSOR_ID_VALUE       0x69054200
-#define IXP4XX_PROCESSOR_ID_MASK        0xfffffff0
-
-#define cpu_is_ixp42x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \
-                          IXP425_PROCESSOR_ID_VALUE)
-#define cpu_is_ixp43x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \
-                          IXP435_PROCESSOR_ID_VALUE)
-#define cpu_is_ixp46x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \
-                          IXP465_PROCESSOR_ID_VALUE)
+#define IXP42X_PROCESSOR_ID_VALUE       0x690541c0 /* including unused 0x690541Ex */
+#define IXP42X_PROCESSOR_ID_MASK        0xffffffc0
+
+#define IXP43X_PROCESSOR_ID_VALUE       0x69054040
+#define IXP43X_PROCESSOR_ID_MASK        0xfffffff0
+
+#define IXP46X_PROCESSOR_ID_VALUE       0x69054200 /* including IXP455 */
+#define IXP46X_PROCESSOR_ID_MASK        0xfffffff0
+
+#define cpu_is_ixp42x() ((read_cpuid_id() & IXP42X_PROCESSOR_ID_MASK) == \
+                         IXP42X_PROCESSOR_ID_VALUE)
+#define cpu_is_ixp43x() ((read_cpuid_id() & IXP43X_PROCESSOR_ID_MASK) == \
+                         IXP43X_PROCESSOR_ID_VALUE)
+#define cpu_is_ixp46x() ((read_cpuid_id() & IXP46X_PROCESSOR_ID_MASK) == \
+                         IXP46X_PROCESSOR_ID_VALUE)
 
 static inline u32 ixp4xx_read_feature_bits(void)
 {
         unsigned int val = ~*IXP4XX_EXP_CFG2;
-        val &= ~IXP4XX_FEATURE_RESERVED;
-        if (!cpu_is_ixp46x())
-                val &= ~IXP4XX_FEATURE_IXP46X_ONLY;
 
-        return val;
+        if (cpu_is_ixp42x())
+                return val & IXP42X_FEATURE_MASK;
+        if (cpu_is_ixp43x())
+                return val & IXP43X_FEATURE_MASK;
+        return val & IXP46X_FEATURE_MASK;
 }
 
 static inline void ixp4xx_write_feature_bits(u32 value)
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
index ad9c888dd850..97c530f66e78 100644
--- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
@@ -604,6 +604,7 @@
 #define DCMD_LENGTH     0x01fff         /* length mask (max = 8K - 1) */
 
 /* "fuse" bits of IXP_EXP_CFG2 */
+/* All IXP4xx CPUs */
 #define IXP4XX_FEATURE_RCOMP            (1 << 0)
 #define IXP4XX_FEATURE_USB_DEVICE       (1 << 1)
 #define IXP4XX_FEATURE_HASH             (1 << 2)
@@ -619,20 +620,41 @@
 #define IXP4XX_FEATURE_RESET_NPEB       (1 << 12)
 #define IXP4XX_FEATURE_RESET_NPEC       (1 << 13)
 #define IXP4XX_FEATURE_PCI              (1 << 14)
-#define IXP4XX_FEATURE_ECC_TIMESYNC     (1 << 15)
 #define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)
+#define IXP4XX_FEATURE_XSCALE_MAX_FREQ  (3 << 22)
+#define IXP42X_FEATURE_MASK             (IXP4XX_FEATURE_RCOMP            | \
+                                         IXP4XX_FEATURE_USB_DEVICE       | \
+                                         IXP4XX_FEATURE_HASH             | \
+                                         IXP4XX_FEATURE_AES              | \
+                                         IXP4XX_FEATURE_DES              | \
+                                         IXP4XX_FEATURE_HDLC             | \
+                                         IXP4XX_FEATURE_AAL              | \
+                                         IXP4XX_FEATURE_HSS              | \
+                                         IXP4XX_FEATURE_UTOPIA           | \
+                                         IXP4XX_FEATURE_NPEB_ETH0        | \
+                                         IXP4XX_FEATURE_NPEC_ETH         | \
+                                         IXP4XX_FEATURE_RESET_NPEA       | \
+                                         IXP4XX_FEATURE_RESET_NPEB       | \
+                                         IXP4XX_FEATURE_RESET_NPEC       | \
+                                         IXP4XX_FEATURE_PCI              | \
+                                         IXP4XX_FEATURE_UTOPIA_PHY_LIMIT | \
+                                         IXP4XX_FEATURE_XSCALE_MAX_FREQ)
+
+
+/* IXP43x/46x CPUs */
+#define IXP4XX_FEATURE_ECC_TIMESYNC     (1 << 15)
 #define IXP4XX_FEATURE_USB_HOST         (1 << 18)
 #define IXP4XX_FEATURE_NPEA_ETH         (1 << 19)
+#define IXP43X_FEATURE_MASK             (IXP42X_FEATURE_MASK             | \
+                                         IXP4XX_FEATURE_ECC_TIMESYNC     | \
+                                         IXP4XX_FEATURE_USB_HOST         | \
+                                         IXP4XX_FEATURE_NPEA_ETH)
+
+/* IXP46x CPU (including IXP455) only */
 #define IXP4XX_FEATURE_NPEB_ETH_1_TO_3  (1 << 20)
 #define IXP4XX_FEATURE_RSA              (1 << 21)
-#define IXP4XX_FEATURE_XSCALE_MAX_FREQ  (3 << 22)
-#define IXP4XX_FEATURE_RESERVED         (0xFF << 24)
-
-#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC |       \
-                                    IXP4XX_FEATURE_USB_HOST |           \
-                                    IXP4XX_FEATURE_NPEA_ETH |           \
-                                    IXP4XX_FEATURE_NPEB_ETH_1_TO_3 |    \
-                                    IXP4XX_FEATURE_RSA |                \
-                                    IXP4XX_FEATURE_XSCALE_MAX_FREQ)
+#define IXP46X_FEATURE_MASK             (IXP43X_FEATURE_MASK             | \
+                                         IXP4XX_FEATURE_NPEB_ETH_1_TO_3  | \
+                                         IXP4XX_FEATURE_RSA)
 
 #endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/system.h b/arch/arm/mach-ixp4xx/include/mach/system.h
index 92a7e8ddf69a..d2aa26f5acd7 100644
--- a/arch/arm/mach-ixp4xx/include/mach/system.h
+++ b/arch/arm/mach-ixp4xx/include/mach/system.h
@@ -20,7 +20,7 @@ static inline void arch_idle(void)
 }
 
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         if ( 1 && mode == 's') {
                 /* Jump into ROM at address 0 */
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
index c73a94d0ca2b..252310234903 100644
--- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c
+++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
@@ -575,8 +575,8 @@ int npe_load_firmware(struct npe *npe, const char *name, struct device *dev)
                 for (i = 0; i < image->size; i++)
                         image->data[i] = swab32(image->data[i]);
 
-        if (!cpu_is_ixp46x() && ((image->id >> 28) & 0xF /* device ID */)) {
-                print_npe(KERN_INFO, npe, "IXP46x firmware ignored on "
+        if (cpu_is_ixp42x() && ((image->id >> 28) & 0xF /* device ID */)) {
+                print_npe(KERN_INFO, npe, "IXP43x/IXP46x firmware ignored on "
                           "IXP42x\n");
                 goto err;
         }
@@ -596,7 +596,7 @@ int npe_load_firmware(struct npe *npe, const char *name, struct device *dev)
                   "revision 0x%X:%X\n", (image->id >> 16) & 0xFF,
                   (image->id >> 8) & 0xFF, image->id & 0xFF);
 
-        if (!cpu_is_ixp46x()) {
+        if (cpu_is_ixp42x()) {
                 if (!npe->id)
                         instr_size = NPE_A_42X_INSTR_SIZE;
                 else
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 3600cd9f0519..b5421cccd7e1 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -20,6 +20,18 @@ config MACH_RD88F6281
           Say 'Y' here if you want your kernel to support the
           Marvell RD-88F6281 Reference Board.
 
+config MACH_SHEEVAPLUG
+        bool "Marvell SheevaPlug Reference Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell SheevaPlug Reference Board.
+
+config MACH_TS219
+        bool "QNAP TS-119 and TS-219 Turbo NAS"
+        help
+          Say 'Y' here if you want your kernel to support the
+          QNAP TS-119 and TS-219 Turbo NAS devices.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index b96c55dad343..8f03c9b9bdd9 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -1,5 +1,7 @@
-obj-y                           += common.o addr-map.o irq.o pcie.o
+obj-y                           += common.o addr-map.o irq.o pcie.o mpp.o
 
 obj-$(CONFIG_MACH_DB88F6281_BP)         += db88f6281-bp-setup.o
 obj-$(CONFIG_MACH_RD88F6192_NAS)        += rd88f6192-nas-setup.o
 obj-$(CONFIG_MACH_RD88F6281)            += rd88f6281-setup.o
+obj-$(CONFIG_MACH_SHEEVAPLUG)           += sheevaplug-setup.o
+obj-$(CONFIG_MACH_TS219)                += ts219-setup.o
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 0d2074f51a59..3d2fae846512 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -14,6 +14,7 @@
 #include <linux/serial_8250.h>
 #include <linux/mbus.h>
 #include <linux/mv643xx_eth.h>
+#include <linux/mv643xx_i2c.h>
 #include <linux/ata_platform.h>
 #include <linux/spi/orion_spi.h>
 #include <net/dsa.h>
@@ -24,6 +25,7 @@
 #include <mach/kirkwood.h>
 #include <plat/cache-feroceon-l2.h>
 #include <plat/ehci-orion.h>
+#include <plat/mvsdio.h>
 #include <plat/mv_xor.h>
 #include <plat/orion_nand.h>
 #include <plat/time.h>
@@ -257,7 +259,7 @@ static struct resource kirkwood_rtc_resource = {
         .flags  = IORESOURCE_MEM,
 };
 
-void __init kirkwood_rtc_init(void)
+static void __init kirkwood_rtc_init(void)
 {
         platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1);
 }
@@ -299,6 +301,50 @@ void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
 
 
 /*****************************************************************************
+ * SD/SDIO/MMC
+ ****************************************************************************/
+static struct resource mvsdio_resources[] = {
+        [0] = {
+                .start  = SDIO_PHYS_BASE,
+                .end    = SDIO_PHYS_BASE + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_KIRKWOOD_SDIO,
+                .end    = IRQ_KIRKWOOD_SDIO,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 mvsdio_dmamask = 0xffffffffUL;
+
+static struct platform_device kirkwood_sdio = {
+        .name           = "mvsdio",
+        .id             = -1,
+        .dev            = {
+                .dma_mask = &mvsdio_dmamask,
+                .coherent_dma_mask = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(mvsdio_resources),
+        .resource       = mvsdio_resources,
+};
+
+void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
+{
+        u32 dev, rev;
+
+        kirkwood_pcie_id(&dev, &rev);
+        if (rev == 0)  /* catch all Kirkwood Z0's */
+                mvsdio_data->clock = 100000000;
+        else
+                mvsdio_data->clock = 200000000;
+        mvsdio_data->dram = &kirkwood_mbus_dram_info;
+        kirkwood_sdio.dev.platform_data = mvsdio_data;
+        platform_device_register(&kirkwood_sdio);
+}
+
+
+/*****************************************************************************
  * SPI
  ****************************************************************************/
 static struct orion_spi_info kirkwood_spi_plat_data = {
@@ -329,6 +375,45 @@ void __init kirkwood_spi_init()
 
 
 /*****************************************************************************
+ * I2C
+ ****************************************************************************/
+static struct mv64xxx_i2c_pdata kirkwood_i2c_pdata = {
+        .freq_m         = 8, /* assumes 166 MHz TCLK */
+        .freq_n         = 3,
+        .timeout        = 1000, /* Default timeout of 1 second */
+};
+
+static struct resource kirkwood_i2c_resources[] = {
+        {
+                .name   = "i2c",
+                .start  = I2C_PHYS_BASE,
+                .end    = I2C_PHYS_BASE + 0x1f,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "i2c",
+                .start  = IRQ_KIRKWOOD_TWSI,
+                .end    = IRQ_KIRKWOOD_TWSI,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device kirkwood_i2c = {
+        .name           = MV64XXX_I2C_CTLR_NAME,
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(kirkwood_i2c_resources),
+        .resource       = kirkwood_i2c_resources,
+        .dev            = {
+                .platform_data  = &kirkwood_i2c_pdata,
+        },
+};
+
+void __init kirkwood_i2c_init(void)
+{
+        platform_device_register(&kirkwood_i2c);
+}
+
+
+/*****************************************************************************
  * UART0
  ****************************************************************************/
 static struct plat_serial8250_port kirkwood_uart0_data[] = {
@@ -505,7 +590,7 @@ static struct platform_device kirkwood_xor01_channel = {
         },
 };
 
-void __init kirkwood_xor0_init(void)
+static void __init kirkwood_xor0_init(void)
 {
         platform_device_register(&kirkwood_xor0_shared);
 
@@ -603,7 +688,7 @@ static struct platform_device kirkwood_xor11_channel = {
         },
 };
 
-void __init kirkwood_xor1_init(void)
+static void __init kirkwood_xor1_init(void)
 {
         platform_device_register(&kirkwood_xor1_shared);
 
@@ -711,4 +796,9 @@ void __init kirkwood_init(void)
 #ifdef CONFIG_CACHE_FEROCEON_L2
         kirkwood_l2_init();
 #endif
+
+        /* internal devices that every board has */
+        kirkwood_rtc_init();
+        kirkwood_xor0_init();
+        kirkwood_xor1_init();
 }
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index fe367c18e722..6ee88406f381 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -14,6 +14,7 @@
 struct dsa_platform_data;
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
+struct mvsdio_platform_data;
 
 /*
  * Basic Kirkwood init functions used early by machine-setup.
@@ -33,14 +34,14 @@ void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq);
 void kirkwood_pcie_init(void);
-void kirkwood_rtc_init(void);
 void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
+void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data);
 void kirkwood_spi_init(void);
+void kirkwood_i2c_init(void);
 void kirkwood_uart0_init(void);
 void kirkwood_uart1_init(void);
-void kirkwood_xor0_init(void);
-void kirkwood_xor1_init(void);
 
+extern int kirkwood_tclk;
 extern struct sys_timer kirkwood_timer;
 
 
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index a14c2948c62a..5505d5837752 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -11,18 +11,59 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/mtd/physmap.h>
 #include <linux/mtd/nand.h>
-#include <linux/timer.h>
+#include <linux/mtd/partitions.h>
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
 #include <mach/kirkwood.h>
+#include <plat/orion_nand.h>
+#include <plat/mvsdio.h>
 #include "common.h"
+#include "mpp.h"
+
+static struct mtd_partition db88f6281_nand_parts[] = {
+        {
+                .name = "u-boot",
+                .offset = 0,
+                .size = SZ_1M
+        }, {
+                .name = "uImage",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size = SZ_4M
+        }, {
+                .name = "root",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size = MTDPART_SIZ_FULL
+        },
+};
+
+static struct resource db88f6281_nand_resource = {
+        .flags          = IORESOURCE_MEM,
+        .start          = KIRKWOOD_NAND_MEM_PHYS_BASE,
+        .end            = KIRKWOOD_NAND_MEM_PHYS_BASE +
+                          KIRKWOOD_NAND_MEM_SIZE - 1,
+};
+
+static struct orion_nand_data db88f6281_nand_data = {
+        .parts          = db88f6281_nand_parts,
+        .nr_parts       = ARRAY_SIZE(db88f6281_nand_parts),
+        .cle            = 0,
+        .ale            = 1,
+        .width          = 8,
+        .chip_delay     = 25,
+};
+
+static struct platform_device db88f6281_nand_flash = {
+        .name           = "orion_nand",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &db88f6281_nand_data,
+        },
+        .resource       = &db88f6281_nand_resource,
+        .num_resources  = 1,
+};
 
 static struct mv643xx_eth_platform_data db88f6281_ge00_data = {
         .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
@@ -32,18 +73,32 @@ static struct mv_sata_platform_data db88f6281_sata_data = {
         .n_ports        = 2,
 };
 
+static struct mvsdio_platform_data db88f6281_mvsdio_data = {
+        .gpio_write_protect     = 37,
+        .gpio_card_detect       = 38,
+};
+
+static unsigned int db88f6281_mpp_config[] __initdata = {
+        MPP37_GPIO,
+        MPP38_GPIO,
+        0
+};
+
 static void __init db88f6281_init(void)
 {
         /*
          * Basic setup. Needs to be called early.
          */
         kirkwood_init();
+        kirkwood_mpp_conf(db88f6281_mpp_config);
 
         kirkwood_ehci_init();
         kirkwood_ge00_init(&db88f6281_ge00_data);
-        kirkwood_rtc_init();
         kirkwood_sata_init(&db88f6281_sata_data);
         kirkwood_uart0_init();
+        kirkwood_sdio_init(&db88f6281_mvsdio_data);
+        
+        platform_device_register(&db88f6281_nand_flash);
 }
 
 static int __init db88f6281_pci_init(void)
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index ada480c0e197..38c986853590 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -93,6 +93,7 @@
 #define  DEVICE_ID              (DEV_BUS_VIRT_BASE | 0x0034)
 #define  RTC_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0300)
 #define  SPI_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0600)
+#define  I2C_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x1000)
 #define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
 #define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
 #define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
@@ -116,5 +117,7 @@
 
 #define SATA_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
 
+#define SDIO_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x90000)
+
 
 #endif
diff --git a/arch/arm/mach-kirkwood/include/mach/system.h b/arch/arm/mach-kirkwood/include/mach/system.h
index 8510f6cfdabf..23a1914c1da8 100644
--- a/arch/arm/mach-kirkwood/include/mach/system.h
+++ b/arch/arm/mach-kirkwood/include/mach/system.h
@@ -17,7 +17,7 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         /*
          * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
new file mode 100644
index 000000000000..63c44934391a
--- /dev/null
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -0,0 +1,97 @@
+/*
+ * arch/arm/mach-kirkwood/mpp.c
+ *
+ * MPP functions for Marvell Kirkwood SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <asm/gpio.h>
+#include <mach/hardware.h>
+#include "common.h"
+#include "mpp.h"
+
+static unsigned int __init kirkwood_variant(void)
+{
+        u32 dev, rev;
+
+        kirkwood_pcie_id(&dev, &rev);
+
+        if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0)
+                return MPP_F6281_MASK;
+        if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0)
+                return MPP_F6192_MASK;
+        if (dev == MV88F6180_DEV_ID)
+                return MPP_F6180_MASK;
+
+        printk(KERN_ERR "MPP setup: unknown kirkwood variant "
+                        "(dev %#x rev %#x)\n", dev, rev);
+        return 0;
+}
+
+#define MPP_CTRL(i)     (DEV_BUS_VIRT_BASE + (i) * 4)
+#define MPP_NR_REGS     (1 + MPP_MAX/8)
+
+void __init kirkwood_mpp_conf(unsigned int *mpp_list)
+{
+        u32 mpp_ctrl[MPP_NR_REGS];
+        unsigned int variant_mask;
+        int i;
+
+        variant_mask = kirkwood_variant();
+        if (!variant_mask)
+                return;
+
+        printk(KERN_DEBUG "initial MPP regs:");
+        for (i = 0; i < MPP_NR_REGS; i++) {
+                mpp_ctrl[i] = readl(MPP_CTRL(i));
+                printk(" %08x", mpp_ctrl[i]);
+        }
+        printk("\n");
+
+        while (*mpp_list) {
+                unsigned int num = MPP_NUM(*mpp_list);
+                unsigned int sel = MPP_SEL(*mpp_list);
+                int shift, gpio_mode;
+
+                if (num > MPP_MAX) {
+                        printk(KERN_ERR "kirkwood_mpp_conf: invalid MPP "
+                                        "number (%u)\n", num);
+                        continue;
+                }
+                if (!(*mpp_list & variant_mask)) {
+                        printk(KERN_WARNING
+                               "kirkwood_mpp_conf: requested MPP%u config "
+                               "unavailable on this hardware\n", num);
+                        continue;
+                }
+
+                shift = (num & 7) << 2;
+                mpp_ctrl[num / 8] &= ~(0xf << shift);
+                mpp_ctrl[num / 8] |= sel << shift;
+
+                gpio_mode = 0;
+                if (*mpp_list & MPP_INPUT_MASK)
+                        gpio_mode |= GPIO_INPUT_OK;
+                if (*mpp_list & MPP_OUTPUT_MASK)
+                        gpio_mode |= GPIO_OUTPUT_OK;
+                if (sel != 0)
+                        gpio_mode = 0;
+                orion_gpio_set_valid(num, gpio_mode);
+
+                mpp_list++;
+        }
+
+        printk(KERN_DEBUG "  final MPP regs:");
+        for (i = 0; i < MPP_NR_REGS; i++) {
+                writel(mpp_ctrl[i], MPP_CTRL(i));
+                printk(" %08x", mpp_ctrl[i]);
+        }
+        printk("\n");
+}
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
new file mode 100644
index 000000000000..e021a80c2caf
--- /dev/null
+++ b/arch/arm/mach-kirkwood/mpp.h
@@ -0,0 +1,303 @@
+/*
+ * linux/arch/arm/mach-kirkwood/mpp.h -- Multi Purpose Pins
+ *
+ * Copyright 2009: Marvell Technology Group Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __KIRKWOOD_MPP_H
+#define __KIRKWOOD_MPP_H
+
+#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \
+        /* MPP number */                ((_num) & 0xff) | \
+        /* MPP select value */          (((_sel) & 0xf) << 8) | \
+        /* may be input signal */       ((!!(_in)) << 12) | \
+        /* may be output signal */      ((!!(_out)) << 13) | \
+        /* available on F6180 */        ((!!(_F6180)) << 14) | \
+        /* available on F6190 */        ((!!(_F6190)) << 15) | \
+        /* available on F6192 */        ((!!(_F6192)) << 16) | \
+        /* available on F6281 */        ((!!(_F6281)) << 17))
+
+#define MPP_NUM(x)      ((x) & 0xff)
+#define MPP_SEL(x)      (((x) >> 8) & 0xf)
+
+                                /*   num sel  i  o  6180 6190 6192 6281 */
+
+#define MPP_INPUT_MASK          MPP(  0, 0x0, 1, 0, 0,   0,   0,   0    )
+#define MPP_OUTPUT_MASK         MPP(  0, 0x0, 0, 1, 0,   0,   0,   0    )
+
+#define MPP_F6180_MASK          MPP(  0, 0x0, 0, 0, 1,   0,   0,   0    )
+#define MPP_F6190_MASK          MPP(  0, 0x0, 0, 0, 0,   1,   0,   0    )
+#define MPP_F6192_MASK          MPP(  0, 0x0, 0, 0, 0,   0,   1,   0    )
+#define MPP_F6281_MASK          MPP(  0, 0x0, 0, 0, 0,   0,   0,   1    )
+
+#define MPP0_GPIO               MPP(  0, 0x0, 1, 1, 1,   1,   1,   1    )
+#define MPP0_NF_IO2             MPP(  0, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP0_SPI_SCn            MPP(  0, 0x2, 0, 1, 1,   1,   1,   1    )
+
+#define MPP1_GPO                MPP(  1, 0x0, 0, 1, 1,   1,   1,   1    )
+#define MPP1_NF_IO3             MPP(  1, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP1_SPI_MOSI           MPP(  1, 0x2, 0, 1, 1,   1,   1,   1    )
+
+#define MPP2_GPO                MPP(  2, 0x0, 0, 1, 1,   1,   1,   1    )
+#define MPP2_NF_IO4             MPP(  2, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP2_SPI_SCK            MPP(  2, 0x2, 0, 1, 1,   1,   1,   1    )
+
+#define MPP3_GPO                MPP(  3, 0x0, 0, 1, 1,   1,   1,   1    )
+#define MPP3_NF_IO5             MPP(  3, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP3_SPI_MISO           MPP(  3, 0x2, 1, 0, 1,   1,   1,   1    )
+
+#define MPP4_GPIO               MPP(  4, 0x0, 1, 1, 1,   1,   1,   1    )
+#define MPP4_NF_IO6             MPP(  4, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP4_UART0_RXD          MPP(  4, 0x2, 1, 0, 1,   1,   1,   1    )
+#define MPP4_SATA1_ACTn         MPP(  4, 0x5, 0, 1, 0,   0,   1,   1    )
+#define MPP4_PTP_CLK            MPP(  4, 0xd, 1, 0, 1,   1,   1,   1    )
+
+#define MPP5_GPO                MPP(  5, 0x0, 0, 1, 1,   1,   1,   1    )
+#define MPP5_NF_IO7             MPP(  5, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP5_UART0_TXD          MPP(  5, 0x2, 0, 1, 1,   1,   1,   1    )
+#define MPP5_PTP_TRIG_GEN       MPP(  5, 0x4, 0, 1, 1,   1,   1,   1    )
+#define MPP5_SATA0_ACTn         MPP(  5, 0x5, 0, 1, 0,   1,   1,   1    )
+
+#define MPP6_SYSRST_OUTn        MPP(  6, 0x1, 0, 1, 1,   1,   1,   1    )
+#define MPP6_SPI_MOSI           MPP(  6, 0x2, 0, 1, 1,   1,   1,   1    )
+#define MPP6_PTP_TRIG_GEN       MPP(  6, 0x3, 0, 1, 1,   1,   1,   1    )
+
+#define MPP7_GPO                MPP(  7, 0x0, 0, 1, 1,   1,   1,   1    )
+#define MPP7_PEX_RST_OUTn       MPP(  7, 0x1, 0, 1, 1,   1,   1,   1    )
+#define MPP7_SPI_SCn            MPP(  7, 0x2, 0, 1, 1,   1,   1,   1    )
+#define MPP7_PTP_TRIG_GEN       MPP(  7, 0x3, 0, 1, 1,   1,   1,   1    )
+
+#define MPP8_GPIO               MPP(  8, 0x0, 1, 1, 1,    1,  1,   1    )
+#define MPP8_TW_SDA             MPP(  8, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP8_UART0_RTS          MPP(  8, 0x2, 0, 1, 1,   1,   1,   1    )
+#define MPP8_UART1_RTS          MPP(  8, 0x3, 0, 1, 1,   1,   1,   1    )
+#define MPP8_MII0_RXERR         MPP(  8, 0x4, 1, 0, 0,   1,   1,   1    )
+#define MPP8_SATA1_PRESENTn     MPP(  8, 0x5, 0, 1, 0,   0,   1,   1    )
+#define MPP8_PTP_CLK            MPP(  8, 0xc, 1, 0, 1,   1,   1,   1    )
+#define MPP8_MII0_COL           MPP(  8, 0xd, 1, 0, 1,   1,   1,   1    )
+
+#define MPP9_GPIO               MPP(  9, 0x0, 1, 1, 1,   1,   1,   1    )
+#define MPP9_TW_SCK             MPP(  9, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP9_UART0_CTS          MPP(  9, 0x2, 1, 0, 1,   1,   1,   1    )
+#define MPP9_UART1_CTS          MPP(  9, 0x3, 1, 0, 1,   1,   1,   1    )
+#define MPP9_SATA0_PRESENTn     MPP(  9, 0x5, 0, 1, 0,   1,   1,   1    )
+#define MPP9_PTP_EVENT_REQ      MPP(  9, 0xc, 1, 0, 1,   1,   1,   1    )
+#define MPP9_MII0_CRS           MPP(  9, 0xd, 1, 0, 1,   1,   1,   1    )
+
+#define MPP10_GPO               MPP( 10, 0x0, 0, 1, 1,   1,   1,   1    )
+#define MPP10_SPI_SCK           MPP( 10, 0x2, 0, 1, 1,   1,   1,   1    )
+#define MPP10_UART0_TXD         MPP( 10, 0X3, 0, 1, 1,   1,   1,   1    )
+#define MPP10_SATA1_ACTn        MPP( 10, 0x5, 0, 1, 0,   0,   1,   1    )
+#define MPP10_PTP_TRIG_GEN      MPP( 10, 0xc, 0, 1, 1,   1,   1,   1    )
+
+#define MPP11_GPIO              MPP( 11, 0x0, 1, 1, 1,   1,   1,   1    )
+#define MPP11_SPI_MISO          MPP( 11, 0x2, 1, 0, 1,   1,   1,   1    )
+#define MPP11_UART0_RXD         MPP( 11, 0x3, 1, 0, 1,   1,   1,   1    )
+#define MPP11_PTP_EVENT_REQ     MPP( 11, 0x4, 1, 0, 1,   1,   1,   1    )
+#define MPP11_PTP_TRIG_GEN      MPP( 11, 0xc, 0, 1, 1,   1,   1,   1    )
+#define MPP11_PTP_CLK           MPP( 11, 0xd, 1, 0, 1,   1,   1,   1    )
+#define MPP11_SATA0_ACTn        MPP( 11, 0x5, 0, 1, 0,   1,   1,   1    )
+
+#define MPP12_GPO               MPP( 12, 0x0, 0, 1, 1,   1,   1,   1    )
+#define MPP12_SD_CLK            MPP( 12, 0x1, 0, 1, 1,   1,   1,   1    )
+
+#define MPP13_GPIO              MPP( 13, 0x0, 1, 1, 1,   1,   1,   1    )
+#define MPP13_SD_CMD            MPP( 13, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP13_UART1_TXD         MPP( 13, 0x3, 0, 1, 1,   1,   1,   1    )
+
+#define MPP14_GPIO              MPP( 14, 0x0, 1, 1, 1,   1,   1,   1    )
+#define MPP14_SD_D0             MPP( 14, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP14_UART1_RXD         MPP( 14, 0x3, 1, 0, 1,   1,   1,   1    )
+#define MPP14_SATA1_PRESENTn    MPP( 14, 0x4, 0, 1, 0,   0,   1,   1    )
+#define MPP14_MII0_COL          MPP( 14, 0xd, 1, 0, 1,   1,   1,   1    )
+
+#define MPP15_GPIO              MPP( 15, 0x0, 1, 1, 1,   1,   1,   1    )
+#define MPP15_SD_D1             MPP( 15, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP15_UART0_RTS         MPP( 15, 0x2, 0, 1, 1,   1,   1,   1    )
+#define MPP15_UART1_TXD         MPP( 15, 0x3, 0, 1, 1,   1,   1,   1    )
+#define MPP15_SATA0_ACTn        MPP( 15, 0x4, 0, 1, 0,   1,   1,   1    )
+
+#define MPP16_GPIO              MPP( 16, 0x0, 1, 1, 1,   1,   1,   1    )
+#define MPP16_SD_D2             MPP( 16, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP16_UART0_CTS         MPP( 16, 0x2, 1, 0, 1,   1,   1,   1    )
+#define MPP16_UART1_RXD         MPP( 16, 0x3, 1, 0, 1,   1,   1,   1    )
+#define MPP16_SATA1_ACTn        MPP( 16, 0x4, 0, 1, 0,   0,   1,   1    )
+#define MPP16_MII0_CRS          MPP( 16, 0xd, 1, 0, 1,   1,   1,   1    )
+
+#define MPP17_GPIO              MPP( 17, 0x0, 1, 1, 1,   1,   1,   1    )
+#define MPP17_SD_D3             MPP( 17, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP17_SATA0_PRESENTn    MPP( 17, 0x4, 0, 1, 0,   1,   1,   1    )
+
+#define MPP18_GPO               MPP( 18, 0x0, 0, 1, 1,   1,   1,   1    )
+#define MPP18_NF_IO0            MPP( 18, 0x1, 1, 1, 1,   1,   1,   1    )
+
+#define MPP19_GPO               MPP( 19, 0x0, 0, 1, 1,   1,   1,   1    )
+#define MPP19_NF_IO1            MPP( 19, 0x1, 1, 1, 1,   1,   1,   1    )
+
+#define MPP20_GPIO              MPP( 20, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP20_TSMP0             MPP( 20, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP20_TDM_CH0_TX_QL     MPP( 20, 0x2, 0, 1, 0,   0,   1,   1    )
+#define MPP20_GE1_0             MPP( 20, 0x3, 0, 0, 0,   1,   1,   1    )
+#define MPP20_AUDIO_SPDIFI      MPP( 20, 0x4, 1, 0, 0,   0,   1,   1    )
+#define MPP20_SATA1_ACTn        MPP( 20, 0x5, 0, 1, 0,   0,   1,   1    )
+
+#define MPP21_GPIO              MPP( 21, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP21_TSMP1             MPP( 21, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP21_TDM_CH0_RX_QL     MPP( 21, 0x2, 0, 1, 0,   0,   1,   1    )
+#define MPP21_GE1_1             MPP( 21, 0x3, 0, 0, 0,   1,   1,   1    )
+#define MPP21_AUDIO_SPDIFO      MPP( 21, 0x4, 0, 1, 0,   0,   1,   1    )
+#define MPP21_SATA0_ACTn        MPP( 21, 0x5, 0, 1, 0,   1,   1,   1    )
+
+#define MPP22_GPIO              MPP( 22, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP22_TSMP2             MPP( 22, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP22_TDM_CH2_TX_QL     MPP( 22, 0x2, 0, 1, 0,   0,   1,   1    )
+#define MPP22_GE1_2             MPP( 22, 0x3, 0, 0, 0,   1,   1,   1    )
+#define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0,   0,   1,   1    )
+#define MPP22_SATA1_PRESENTn    MPP( 22, 0x5, 0, 1, 0,   0,   1,   1    )
+
+#define MPP23_GPIO              MPP( 23, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP23_TSMP3             MPP( 23, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP23_TDM_CH2_RX_QL     MPP( 23, 0x2, 1, 0, 0,   0,   1,   1    )
+#define MPP23_GE1_3             MPP( 23, 0x3, 0, 0, 0,   1,   1,   1    )
+#define MPP23_AUDIO_I2SBCLK     MPP( 23, 0x4, 0, 1, 0,   0,   1,   1    )
+#define MPP23_SATA0_PRESENTn    MPP( 23, 0x5, 0, 1, 0,   1,   1,   1    )
+
+#define MPP24_GPIO              MPP( 24, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP24_TSMP4             MPP( 24, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP24_TDM_SPI_CS0       DEV( 24, 0x2, 0, 1, 0,   0,   1,   1    )
+#define MPP24_GE1_4             MPP( 24, 0x3, 0, 0, 0,   1,   1,   1    )
+#define MPP24_AUDIO_I2SDO       MPP( 24, 0x4, 0, 1, 0,   0,   1,   1    )
+
+#define MPP25_GPIO              MPP( 25, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP25_TSMP5             MPP( 25, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP25_TDM_SPI_SCK       MPP( 25, 0x2, 0, 1, 0,   0,   1,   1    )
+#define MPP25_GE1_5             MPP( 25, 0x3, 0, 0, 0,   1,   1,   1    )
+#define MPP25_AUDIO_I2SLRCLK    MPP( 25, 0x4, 0, 1, 0,   0,   1,   1    )
+
+#define MPP26_GPIO              MPP( 26, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP26_TSMP6             MPP( 26, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP26_TDM_SPI_MISO      MPP( 26, 0x2, 1, 0, 0,   0,   1,   1    )
+#define MPP26_GE1_6             MPP( 26, 0x3, 0, 0, 0,   1,   1,   1    )
+#define MPP26_AUDIO_I2SMCLK     MPP( 26, 0x4, 0, 1, 0,   0,   1,   1    )
+
+#define MPP27_GPIO              MPP( 27, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP27_TSMP7             MPP( 27, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP27_TDM_SPI_MOSI      MPP( 27, 0x2, 0, 1, 0,   0,   1,   1    )
+#define MPP27_GE1_7             MPP( 27, 0x3, 0, 0, 0,   1,   1,   1    )
+#define MPP27_AUDIO_I2SDI       MPP( 27, 0x4, 1, 0, 0,   0,   1,   1    )
+
+#define MPP28_GPIO              MPP( 28, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP28_TSMP8             MPP( 28, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP28_TDM_CODEC_INTn    MPP( 28, 0x2, 0, 0, 0,   0,   1,   1    )
+#define MPP28_GE1_8             MPP( 28, 0x3, 0, 0, 0,   1,   1,   1    )
+#define MPP28_AUDIO_EXTCLK      MPP( 28, 0x4, 1, 0, 0,   0,   1,   1    )
+
+#define MPP29_GPIO              MPP( 29, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP29_TSMP9             MPP( 29, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP29_TDM_CODEC_RSTn    MPP( 29, 0x2, 0, 0, 0,   0,   1,   1    )
+#define MPP29_GE1_9             MPP( 29, 0x3, 0, 0, 0,   1,   1,   1    )
+
+#define MPP30_GPIO              MPP( 30, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP30_TSMP10            MPP( 30, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP30_TDM_PCLK          MPP( 30, 0x2, 1, 1, 0,   0,   1,   1    )
+#define MPP30_GE1_10            MPP( 30, 0x3, 0, 0, 0,   1,   1,   1    )
+
+#define MPP31_GPIO              MPP( 31, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP31_TSMP11            MPP( 31, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP31_TDM_FS            MPP( 31, 0x2, 1, 1, 0,   0,   1,   1    )
+#define MPP31_GE1_11            MPP( 31, 0x3, 0, 0, 0,   1,   1,   1    )
+
+#define MPP32_GPIO              MPP( 32, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP32_TSMP12            MPP( 32, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP32_TDM_DRX           MPP( 32, 0x2, 1, 0, 0,   0,   1,   1    )
+#define MPP32_GE1_12            MPP( 32, 0x3, 0, 0, 0,   1,   1,   1    )
+
+#define MPP33_GPIO              MPP( 33, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP33_TDM_DTX           MPP( 33, 0x2, 0, 1, 0,   0,   1,   1    )
+#define MPP33_GE1_13            MPP( 33, 0x3, 0, 0, 0,   1,   1,   1    )
+
+#define MPP34_GPIO              MPP( 34, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP34_TDM_SPI_CS1       MPP( 34, 0x2, 0, 1, 0,   0,   1,   1    )
+#define MPP34_GE1_14            MPP( 34, 0x3, 0, 0, 0,   1,   1,   1    )
+
+#define MPP35_GPIO              MPP( 35, 0x0, 1, 1, 1,   1,   1,   1    )
+#define MPP35_TDM_CH0_TX_QL     MPP( 35, 0x2, 0, 1, 0,   0,   1,   1    )
+#define MPP35_GE1_15            MPP( 35, 0x3, 0, 0, 0,   1,   1,   1    )
+#define MPP35_SATA0_ACTn        MPP( 35, 0x5, 0, 1, 0,   1,   1,   1    )
+#define MPP35_MII0_RXERR        MPP( 35, 0xc, 1, 0, 1,   1,   1,   1    )
+
+#define MPP36_GPIO              MPP( 36, 0x0, 1, 1, 1,   0,   0,   1    )
+#define MPP36_TSMP0             MPP( 36, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP36_TDM_SPI_CS1       MPP( 36, 0x2, 0, 1, 0,   0,   0,   1    )
+#define MPP36_AUDIO_SPDIFI      MPP( 36, 0x4, 1, 0, 1,   0,   0,   1    )
+
+#define MPP37_GPIO              MPP( 37, 0x0, 1, 1, 1,   0,   0,   1    )
+#define MPP37_TSMP1             MPP( 37, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP37_TDM_CH2_TX_QL     MPP( 37, 0x2, 0, 1, 0,   0,   0,   1    )
+#define MPP37_AUDIO_SPDIFO      MPP( 37, 0x4, 0, 1, 1,   0,   0,   1    )
+
+#define MPP38_GPIO              MPP( 38, 0x0, 1, 1, 1,   0,   0,   1    )
+#define MPP38_TSMP2             MPP( 38, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP38_TDM_CH2_RX_QL     MPP( 38, 0x2, 0, 1, 0,   0,   0,   1    )
+#define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1,   0,   0,   1    )
+
+#define MPP39_GPIO              MPP( 39, 0x0, 1, 1, 1,   0,   0,   1    )
+#define MPP39_TSMP3             MPP( 39, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP39_TDM_SPI_CS0       MPP( 39, 0x2, 0, 1, 0,   0,   0,   1    )
+#define MPP39_AUDIO_I2SBCLK     MPP( 39, 0x4, 0, 1, 1,   0,   0,   1    )
+
+#define MPP40_GPIO              MPP( 40, 0x0, 1, 1, 1,   0,   0,   1    )
+#define MPP40_TSMP4             MPP( 40, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP40_TDM_SPI_SCK       MPP( 40, 0x2, 0, 1, 0,   0,   0,   1    )
+#define MPP40_AUDIO_I2SDO       MPP( 40, 0x4, 0, 1, 1,   0,   0,   1    )
+
+#define MPP41_GPIO              MPP( 41, 0x0, 1, 1, 1,   0,   0,   1    )
+#define MPP41_TSMP5             MPP( 41, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP41_TDM_SPI_MISO      MPP( 41, 0x2, 1, 0, 0,   0,   0,   1    )
+#define MPP41_AUDIO_I2SLRC      MPP( 41, 0x4, 0, 1, 1,   0,   0,   1    )
+
+#define MPP42_GPIO              MPP( 42, 0x0, 1, 1, 1,   0,   0,   1    )
+#define MPP42_TSMP6             MPP( 42, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP42_TDM_SPI_MOSI      MPP( 42, 0x2, 0, 1, 0,   0,   0,   1    )
+#define MPP42_AUDIO_I2SMCLK     MPP( 42, 0x4, 0, 1, 1,   0,   0,   1    )
+
+#define MPP43_GPIO              MPP( 43, 0x0, 1, 1, 1,   0,   0,   1    )
+#define MPP43_TSMP7             MPP( 43, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP43_TDM_CODEC_INTn    MPP( 43, 0x2, 0, 0, 0,   0,   0,   1    )
+#define MPP43_AUDIO_I2SDI       MPP( 43, 0x4, 1, 0, 1,   0,   0,   1    )
+
+#define MPP44_GPIO              MPP( 44, 0x0, 1, 1, 1,   0,   0,   1    )
+#define MPP44_TSMP8             MPP( 44, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP44_TDM_CODEC_RSTn    MPP( 44, 0x2, 0, 0, 0,   0,   0,   1    )
+#define MPP44_AUDIO_EXTCLK      MPP( 44, 0x4, 1, 0, 1,   0,   0,   1    )
+
+#define MPP45_GPIO              MPP( 45, 0x0, 1, 1, 0,   0,   0,   1    )
+#define MPP45_TSMP9             MPP( 45, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP45_TDM_PCLK          MPP( 45, 0x2, 1, 1, 0,   0,   0,   1    )
+
+#define MPP46_GPIO              MPP( 46, 0x0, 1, 1, 0,   0,   0,   1    )
+#define MPP46_TSMP10            MPP( 46, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP46_TDM_FS            MPP( 46, 0x2, 1, 1, 0,   0,   0,   1    )
+
+#define MPP47_GPIO              MPP( 47, 0x0, 1, 1, 0,   0,   0,   1    )
+#define MPP47_TSMP11            MPP( 47, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP47_TDM_DRX           MPP( 47, 0x2, 1, 0, 0,   0,   0,   1    )
+
+#define MPP48_GPIO              MPP( 48, 0x0, 1, 1, 0,   0,   0,   1    )
+#define MPP48_TSMP12            MPP( 48, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP48_TDM_DTX           MPP( 48. 0x2, 0, 1, 0,   0,   0,   1    )
+
+#define MPP49_GPIO              MPP( 49, 0x0, 1, 1, 0,   0,   0,   1    )
+#define MPP49_TSMP9             MPP( 49, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP49_TDM_CH0_RX_QL     MPP( 49, 0x2, 0, 1, 0,   0,   0,   1    )
+#define MPP49_PTP_CLK           MPP( 49, 0x5, 1, 0, 0,   0,   0,   1    )
+
+#define MPP_MAX                 49
+
+void kirkwood_mpp_conf(unsigned int *mpp_list);
+
+#endif
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index b1d1a87a6821..2f0e4ef3db0f 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -11,11 +11,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/mtd/physmap.h>
 #include <linux/mtd/nand.h>
-#include <linux/timer.h>
+#include <linux/mtd/partitions.h>
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/spi/flash.h>
@@ -23,7 +20,6 @@
 #include <linux/spi/orion_spi.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
 #include <mach/kirkwood.h>
 #include "common.h"
 
@@ -61,14 +57,11 @@ static void __init rd88f6192_init(void)
 
         kirkwood_ehci_init();
         kirkwood_ge00_init(&rd88f6192_ge00_data);
-        kirkwood_rtc_init();
         kirkwood_sata_init(&rd88f6192_sata_data);
         spi_register_board_info(rd88F6192_spi_slave_info,
                                 ARRAY_SIZE(rd88F6192_spi_slave_info));
         kirkwood_spi_init();
         kirkwood_uart0_init();
-        kirkwood_xor0_init();
-        kirkwood_xor1_init();
 }
 
 static int __init rd88f6192_pci_init(void)
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index e1c0516c4df3..31e996d65fc4 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -11,21 +11,20 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/pci.h>
 #include <linux/irq.h>
-#include <linux/mtd/physmap.h>
 #include <linux/mtd/nand.h>
-#include <linux/timer.h>
+#include <linux/mtd/partitions.h>
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/ethtool.h>
 #include <net/dsa.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
 #include <mach/kirkwood.h>
+#include <plat/mvsdio.h>
 #include <plat/orion_nand.h>
 #include "common.h"
+#include "mpp.h"
 
 static struct mtd_partition rd88f6281_nand_parts[] = {
         {
@@ -96,6 +95,15 @@ static struct mv_sata_platform_data rd88f6281_sata_data = {
         .n_ports        = 2,
 };
 
+static struct mvsdio_platform_data rd88f6281_mvsdio_data = {
+        .gpio_card_detect = 28,
+};
+
+static unsigned int rd88f6281_mpp_config[] __initdata = {
+        MPP28_GPIO,
+        0
+};
+
 static void __init rd88f6281_init(void)
 {
         u32 dev, rev;
@@ -104,6 +112,7 @@ static void __init rd88f6281_init(void)
          * Basic setup. Needs to be called early.
          */
         kirkwood_init();
+        kirkwood_mpp_conf(rd88f6281_mpp_config);
 
         kirkwood_ehci_init();
 
@@ -117,8 +126,8 @@ static void __init rd88f6281_init(void)
         }
         kirkwood_ge00_switch_init(&rd88f6281_switch_plat_data, NO_IRQ);
 
-        kirkwood_rtc_init();
         kirkwood_sata_init(&rd88f6281_sata_data);
+        kirkwood_sdio_init(&rd88f6281_mvsdio_data);
         kirkwood_uart0_init();
 
         platform_device_register(&rd88f6281_nand_flash);
diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c
new file mode 100644
index 000000000000..831e4a56cae1
--- /dev/null
+++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c
@@ -0,0 +1,136 @@
+/*
+ * arch/arm/mach-kirkwood/sheevaplug-setup.c
+ *
+ * Marvell SheevaPlug Reference Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include <plat/mvsdio.h>
+#include <plat/orion_nand.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mtd_partition sheevaplug_nand_parts[] = {
+        {
+                .name = "u-boot",
+                .offset = 0,
+                .size = SZ_1M
+        }, {
+                .name = "uImage",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size = SZ_4M
+        }, {
+                .name = "root",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size = MTDPART_SIZ_FULL
+        },
+};
+
+static struct resource sheevaplug_nand_resource = {
+        .flags          = IORESOURCE_MEM,
+        .start          = KIRKWOOD_NAND_MEM_PHYS_BASE,
+        .end            = KIRKWOOD_NAND_MEM_PHYS_BASE +
+                          KIRKWOOD_NAND_MEM_SIZE - 1,
+};
+
+static struct orion_nand_data sheevaplug_nand_data = {
+        .parts          = sheevaplug_nand_parts,
+        .nr_parts       = ARRAY_SIZE(sheevaplug_nand_parts),
+        .cle            = 0,
+        .ale            = 1,
+        .width          = 8,
+        .chip_delay     = 25,
+};
+
+static struct platform_device sheevaplug_nand_flash = {
+        .name           = "orion_nand",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &sheevaplug_nand_data,
+        },
+        .resource       = &sheevaplug_nand_resource,
+        .num_resources  = 1,
+};
+
+static struct mv643xx_eth_platform_data sheevaplug_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+
+static struct mvsdio_platform_data sheevaplug_mvsdio_data = {
+        // unfortunately the CD signal has not been connected */
+};
+
+static struct gpio_led sheevaplug_led_pins[] = {
+        {
+                .name                   = "plug:green:health",
+                .default_trigger        = "default-on",
+                .gpio                   = 49,
+                .active_low             = 1,
+        },
+};
+
+static struct gpio_led_platform_data sheevaplug_led_data = {
+        .leds           = sheevaplug_led_pins,
+        .num_leds       = ARRAY_SIZE(sheevaplug_led_pins),
+};
+
+static struct platform_device sheevaplug_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &sheevaplug_led_data,
+        }
+};
+
+static unsigned int sheevaplug_mpp_config[] __initdata = {
+        MPP29_GPIO,     /* USB Power Enable */
+        MPP49_GPIO,     /* LED */
+        0
+};
+
+static void __init sheevaplug_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+        kirkwood_mpp_conf(sheevaplug_mpp_config);
+
+        kirkwood_uart0_init();
+
+        if (gpio_request(29, "USB Power Enable") != 0 ||
+            gpio_direction_output(29, 1) != 0)
+                printk(KERN_ERR "can't set up GPIO 29 (USB Power Enable)\n");
+        kirkwood_ehci_init();
+
+        kirkwood_ge00_init(&sheevaplug_ge00_data);
+        kirkwood_sdio_init(&sheevaplug_mvsdio_data);
+
+        platform_device_register(&sheevaplug_nand_flash);
+        platform_device_register(&sheevaplug_leds);
+}
+
+MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board")
+        /* Maintainer: shadi Ammouri <shadi@marvell.com> */
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = sheevaplug_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+MACHINE_END
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
new file mode 100644
index 000000000000..dda5743cf3e0
--- /dev/null
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -0,0 +1,220 @@
+/*
+ *
+ * QNAP TS-119/TS-219 Turbo NAS Board Setup
+ *
+ * Copyright (C) 2009  Martin Michlmayr <tbm@cyrius.com>
+ * Copyright (C) 2008  Byron Bradley <byron.bbradley@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/orion_spi.h>
+#include <linux/i2c.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ata_platform.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/timex.h>
+#include <linux/serial_reg.h>
+#include <linux/pci.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+#include "mpp.h"
+
+/****************************************************************************
+ * 16 MiB NOR flash. The struct mtd_partition is not in the same order as the
+ *     partitions on the device because we want to keep compatability with
+ *     the QNAP firmware.
+ * Layout as used by QNAP:
+ *  0x00000000-0x00080000 : "U-Boot"
+ *  0x00200000-0x00400000 : "Kernel"
+ *  0x00400000-0x00d00000 : "RootFS"
+ *  0x00d00000-0x01000000 : "RootFS2"
+ *  0x00080000-0x000c0000 : "U-Boot Config"
+ *  0x000c0000-0x00200000 : "NAS Config"
+ *
+ * We'll use "RootFS1" instead of "RootFS" to stay compatible with the layout
+ * used by the QNAP TS-109/TS-209.
+ *
+ ***************************************************************************/
+
+static struct mtd_partition qnap_ts219_partitions[] = {
+        {
+                .name           = "U-Boot",
+                .size           = 0x00080000,
+                .offset         = 0,
+                .mask_flags     = MTD_WRITEABLE,
+        }, {
+                .name           = "Kernel",
+                .size           = 0x00200000,
+                .offset         = 0x00200000,
+        }, {
+                .name           = "RootFS1",
+                .size           = 0x00900000,
+                .offset         = 0x00400000,
+        }, {
+                .name           = "RootFS2",
+                .size           = 0x00300000,
+                .offset         = 0x00d00000,
+        }, {
+                .name           = "U-Boot Config",
+                .size           = 0x00040000,
+                .offset         = 0x00080000,
+        }, {
+                .name           = "NAS Config",
+                .size           = 0x00140000,
+                .offset         = 0x000c0000,
+        },
+};
+
+static const struct flash_platform_data qnap_ts219_flash = {
+        .type           = "m25p128",
+        .name           = "spi_flash",
+        .parts          = qnap_ts219_partitions,
+        .nr_parts       = ARRAY_SIZE(qnap_ts219_partitions),
+};
+
+static struct spi_board_info __initdata qnap_ts219_spi_slave_info[] = {
+        {
+                .modalias       = "m25p80",
+                .platform_data  = &qnap_ts219_flash,
+                .irq            = -1,
+                .max_speed_hz   = 20000000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+        },
+};
+
+static struct i2c_board_info __initdata qnap_ts219_i2c_rtc = {
+        I2C_BOARD_INFO("s35390a", 0x30),
+};
+
+static struct mv643xx_eth_platform_data qnap_ts219_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+
+static struct mv_sata_platform_data qnap_ts219_sata_data = {
+        .n_ports        = 2,
+};
+
+static struct gpio_keys_button qnap_ts219_buttons[] = {
+        {
+                .code           = KEY_COPY,
+                .gpio           = 15,
+                .desc           = "USB Copy",
+                .active_low     = 1,
+        },
+        {
+                .code           = KEY_RESTART,
+                .gpio           = 16,
+                .desc           = "Reset",
+                .active_low     = 1,
+        },
+};
+
+static struct gpio_keys_platform_data qnap_ts219_button_data = {
+        .buttons        = qnap_ts219_buttons,
+        .nbuttons       = ARRAY_SIZE(qnap_ts219_buttons),
+};
+
+static struct platform_device qnap_ts219_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &qnap_ts219_button_data,
+        }
+};
+
+static unsigned int qnap_ts219_mpp_config[] __initdata = {
+        MPP0_SPI_SCn,
+        MPP1_SPI_MOSI,
+        MPP2_SPI_SCK,
+        MPP3_SPI_MISO,
+        MPP8_TW_SDA,
+        MPP9_TW_SCK,
+        MPP10_UART0_TXD,
+        MPP11_UART0_RXD,
+        MPP13_UART1_TXD,        /* PIC controller */
+        MPP14_UART1_RXD,        /* PIC controller */
+        MPP15_GPIO,             /* USB Copy button */
+        MPP16_GPIO,             /* Reset button */
+        MPP20_SATA1_ACTn,
+        MPP21_SATA0_ACTn,
+        MPP22_SATA1_PRESENTn,
+        MPP23_SATA0_PRESENTn,
+        0
+};
+
+
+/*****************************************************************************
+ * QNAP TS-x19 specific power off method via UART1-attached PIC
+ ****************************************************************************/
+
+#define UART1_REG(x)    (UART1_VIRT_BASE + ((UART_##x) << 2))
+
+void qnap_ts219_power_off(void)
+{
+        /* 19200 baud divisor */
+        const unsigned divisor = ((kirkwood_tclk + (8 * 19200)) / (16 * 19200));
+
+        pr_info("%s: triggering power-off...\n", __func__);
+
+        /* hijack UART1 and reset into sane state (19200,8n1) */
+        writel(0x83, UART1_REG(LCR));
+        writel(divisor & 0xff, UART1_REG(DLL));
+        writel((divisor >> 8) & 0xff, UART1_REG(DLM));
+        writel(0x03, UART1_REG(LCR));
+        writel(0x00, UART1_REG(IER));
+        writel(0x00, UART1_REG(FCR));
+        writel(0x00, UART1_REG(MCR));
+
+        /* send the power-off command 'A' to PIC */
+        writel('A', UART1_REG(TX));
+}
+
+static void __init qnap_ts219_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+        kirkwood_mpp_conf(qnap_ts219_mpp_config);
+
+        kirkwood_uart0_init();
+        kirkwood_uart1_init(); /* A PIC controller is connected here. */
+        spi_register_board_info(qnap_ts219_spi_slave_info,
+                                ARRAY_SIZE(qnap_ts219_spi_slave_info));
+        kirkwood_spi_init();
+        kirkwood_i2c_init();
+        i2c_register_board_info(0, &qnap_ts219_i2c_rtc, 1);
+        kirkwood_ge00_init(&qnap_ts219_ge00_data);
+        kirkwood_sata_init(&qnap_ts219_sata_data);
+        kirkwood_ehci_init();
+        platform_device_register(&qnap_ts219_button_device);
+
+        pm_power_off = qnap_ts219_power_off;
+
+}
+
+MACHINE_START(TS219, "QNAP TS-119/TS-219")
+        /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = qnap_ts219_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+MACHINE_END
diff --git a/arch/arm/mach-ks8695/Kconfig b/arch/arm/mach-ks8695/Kconfig
index 2754daabda55..fe0c82e30b2d 100644
--- a/arch/arm/mach-ks8695/Kconfig
+++ b/arch/arm/mach-ks8695/Kconfig
@@ -14,6 +14,12 @@ config MACH_DSM320
           Say 'Y' here if you want your kernel to run on the D-Link
           DSM-320 Wireless Media Player.
 
+config MACH_ACS5K
+        bool "Brivo Systems LLC, ACS-5000 Master board"
+        help
+          say 'Y' here if you want your kernel to run on the Brivo
+          Systems LLC, ACS-5000 Master board.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-ks8695/Makefile b/arch/arm/mach-ks8695/Makefile
index f735d2cc0294..7e3e8160ed30 100644
--- a/arch/arm/mach-ks8695/Makefile
+++ b/arch/arm/mach-ks8695/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_LEDS)		+= leds.o
 # Board-specific support
 obj-$(CONFIG_MACH_KS8695)       += board-micrel.o
 obj-$(CONFIG_MACH_DSM320)       += board-dsm320.o
+obj-$(CONFIG_MACH_ACS5K)        += board-acs5k.o
diff --git a/arch/arm/mach-ks8695/board-acs5k.c b/arch/arm/mach-ks8695/board-acs5k.c
new file mode 100644
index 000000000000..9e3e5a640ad2
--- /dev/null
+++ b/arch/arm/mach-ks8695/board-acs5k.c
@@ -0,0 +1,233 @@
+/*
+ * arch/arm/mach-ks8695/board-acs5k.c
+ *
+ * Brivo Systems LLC, ACS-5000 Master Board
+ *
+ * Copyright 2008 Simtec Electronics
+ *                Daniel Silverstone <dsilvers@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
+#include <linux/i2c-gpio.h>
+#include <linux/i2c/pca953x.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-types.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/devices.h>
+#include <mach/gpio.h>
+
+#include "generic.h"
+
+static struct i2c_gpio_platform_data acs5k_i2c_device_platdata = {
+        .sda_pin        = 4,
+        .scl_pin        = 5,
+        .udelay         = 10,
+};
+
+static struct platform_device acs5k_i2c_device = {
+        .name           = "i2c-gpio",
+        .id             = -1,
+        .num_resources  = 0,
+        .resource       = NULL,
+        .dev            = {
+                .platform_data  = &acs5k_i2c_device_platdata,
+        },
+};
+
+static int acs5k_pca9555_setup(struct i2c_client *client,
+                               unsigned gpio_base, unsigned ngpio,
+                               void *context)
+{
+        static int acs5k_gpio_value[] = {
+                -1, -1, -1, -1, -1, -1, -1, 0, 1, 1, -1, 0, 1, 0, -1, -1
+        };
+        int n;
+
+        for (n = 0; n < ARRAY_SIZE(acs5k_gpio_value); ++n) {
+                gpio_request(gpio_base + n, "ACS-5000 GPIO Expander");
+                if (acs5k_gpio_value[n] < 0)
+                        gpio_direction_input(gpio_base + n);
+                else
+                        gpio_direction_output(gpio_base + n,
+                                              acs5k_gpio_value[n]);
+                gpio_export(gpio_base + n, 0); /* Export, direction locked down */
+        }
+
+        return 0;
+}
+
+static struct pca953x_platform_data acs5k_i2c_pca9555_platdata = {
+        .gpio_base      = 16, /* Start directly after the CPU's GPIO */
+        .invert         = 0, /* Do not invert */
+        .setup          = acs5k_pca9555_setup,
+};
+
+static struct i2c_board_info acs5k_i2c_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("pcf8563", 0x51),
+        },
+        {
+                I2C_BOARD_INFO("pca9555", 0x20),
+                .platform_data = &acs5k_i2c_pca9555_platdata,
+        },
+};
+
+static void __devinit acs5k_i2c_init(void)
+{
+        /* The gpio interface */
+        platform_device_register(&acs5k_i2c_device);
+        /* I2C devices */
+        i2c_register_board_info(0, acs5k_i2c_devs,
+                                ARRAY_SIZE(acs5k_i2c_devs));
+}
+
+static struct mtd_partition acs5k_nor_partitions[] = {
+        [0] = {
+                .name   = "Boot Agent and config",
+                .size   = SZ_256K,
+                .offset = 0,
+                .mask_flags = MTD_WRITEABLE,
+        },
+        [1] = {
+                .name   = "Kernel",
+                .size   = SZ_1M,
+                .offset = SZ_256K,
+        },
+        [2] = {
+                .name   = "SquashFS1",
+                .size   = SZ_2M,
+                .offset = SZ_256K + SZ_1M,
+        },
+        [3] = {
+                .name   = "SquashFS2",
+                .size   = SZ_4M + SZ_2M,
+                .offset = SZ_256K + SZ_1M + SZ_2M,
+        },
+        [4] = {
+                .name   = "Data",
+                .size   = SZ_16M + SZ_4M + SZ_2M + SZ_512K, /* 22.5 MB */
+                .offset = SZ_256K + SZ_8M + SZ_1M,
+        }
+};
+
+static struct physmap_flash_data acs5k_nor_pdata = {
+        .width          = 4,
+        .nr_parts       = ARRAY_SIZE(acs5k_nor_partitions),
+        .parts          = acs5k_nor_partitions,
+};
+
+static struct resource acs5k_nor_resource[] = {
+        [0] = {
+                .start = SZ_32M, /* We expect the bootloader to map
+                                  * the flash here.
+                                  */
+                .end   = SZ_32M + SZ_16M - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = SZ_32M + SZ_16M,
+                .end   = SZ_32M + SZ_32M - SZ_256K - 1,
+                .flags = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device acs5k_device_nor = {
+        .name           = "physmap-flash",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(acs5k_nor_resource),
+        .resource       = acs5k_nor_resource,
+        .dev            = {
+                .platform_data = &acs5k_nor_pdata,
+        },
+};
+
+static void __init acs5k_register_nor(void)
+{
+        int ret;
+
+        if (acs5k_nor_partitions[0].mask_flags == 0)
+                printk(KERN_WARNING "Warning: Unprotecting bootloader and configuration partition\n");
+
+        ret = platform_device_register(&acs5k_device_nor);
+        if (ret < 0)
+                printk(KERN_ERR "failed to register physmap-flash device\n");
+}
+
+static int __init acs5k_protection_setup(char *s)
+{
+        /* We can't allocate anything here but we should be able
+         * to trivially parse s and decide if we can protect the
+         * bootloader partition or not
+         */
+        if (strcmp(s, "no") == 0)
+                acs5k_nor_partitions[0].mask_flags = 0;
+
+        return 1;
+}
+
+__setup("protect_bootloader=", acs5k_protection_setup);
+
+static void __init acs5k_init_gpio(void)
+{
+        int i;
+
+        ks8695_register_gpios();
+        for (i = 0; i < 4; ++i)
+                gpio_request(i, "ACS5K IRQ");
+        gpio_request(7, "ACS5K KS_FRDY");
+        for (i = 8; i < 16; ++i)
+                gpio_request(i, "ACS5K Unused");
+
+        gpio_request(3, "ACS5K CAN Control");
+        gpio_request(6, "ACS5K Heartbeat");
+        gpio_direction_output(3, 1); /* Default CAN_RESET high */
+        gpio_direction_output(6, 0); /* Default KS8695_ACTIVE low */
+        gpio_export(3, 0); /* export CAN_RESET as output only */
+        gpio_export(6, 0); /* export KS8695_ACTIVE as output only */
+}
+
+static void __init acs5k_init(void)
+{
+        acs5k_init_gpio();
+
+        /* Network device */
+        ks8695_add_device_lan();        /* eth0 = LAN */
+        ks8695_add_device_wan();        /* ethX = WAN */
+
+        /* NOR devices */
+        acs5k_register_nor();
+
+        /* I2C bus */
+        acs5k_i2c_init();
+}
+
+MACHINE_START(ACS5K, "Brivo Systems LLC ACS-5000 Master board")
+        /* Maintainer: Simtec Electronics. */
+        .phys_io        = KS8695_IO_PA,
+        .io_pg_offst    = (KS8695_IO_VA >> 18) & 0xfffc,
+        .boot_params    = KS8695_SDRAM_PA + 0x100,
+        .map_io         = ks8695_map_io,
+        .init_irq       = ks8695_init_irq,
+        .init_machine   = acs5k_init,
+        .timer          = &ks8695_timer,
+MACHINE_END
diff --git a/arch/arm/mach-ks8695/include/mach/memory.h b/arch/arm/mach-ks8695/include/mach/memory.h
index 6d5887cf5742..76e5308685a4 100644
--- a/arch/arm/mach-ks8695/include/mach/memory.h
+++ b/arch/arm/mach-ks8695/include/mach/memory.h
@@ -35,7 +35,11 @@ extern struct bus_type platform_bus_type;
                                         __phys_to_virt(x) : __bus_to_virt(x)); })
 #define __arch_virt_to_dma(dev, x)      ({ is_lbus_device(dev) ? \
                                         (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); })
-#define __arch_page_to_dma(dev, x)      __arch_virt_to_dma(dev, page_address(x))
+#define __arch_page_to_dma(dev, x)      \
+        ({ dma_addr_t __dma = page_to_phys(page); \
+           if (!is_lbus_device(dev)) \
+                __dma = __dma - PHYS_OFFSET + KS8695_PCIMEM_PA; \
+           __dma; })
 
 #endif
 
diff --git a/arch/arm/mach-ks8695/include/mach/system.h b/arch/arm/mach-ks8695/include/mach/system.h
index 5a9b032bdbeb..fb1dda9be2d0 100644
--- a/arch/arm/mach-ks8695/include/mach/system.h
+++ b/arch/arm/mach-ks8695/include/mach/system.h
@@ -27,7 +27,7 @@ static void arch_idle(void)
 
 }
 
-static void arch_reset(char mode)
+static void arch_reset(char mode, const char *cmd)
 {
         unsigned int reg;
 
diff --git a/arch/arm/mach-l7200/include/mach/system.h b/arch/arm/mach-l7200/include/mach/system.h
index 5272abee0d0e..e0dd3b6ae4aa 100644
--- a/arch/arm/mach-l7200/include/mach/system.h
+++ b/arch/arm/mach-l7200/include/mach/system.h
@@ -19,7 +19,7 @@ static inline void arch_idle(void)
         *(unsigned long *)(IO_BASE + 0x50004) = 1;      /* idle mode */
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         if (mode == 's') {
                 cpu_reset(0);
diff --git a/arch/arm/mach-lh7a40x/include/mach/system.h b/arch/arm/mach-lh7a40x/include/mach/system.h
index fa46bb1ef07b..45a56d3b93d7 100644
--- a/arch/arm/mach-lh7a40x/include/mach/system.h
+++ b/arch/arm/mach-lh7a40x/include/mach/system.h
@@ -13,7 +13,7 @@ static inline void arch_idle(void)
         cpu_do_idle ();
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         cpu_reset (0);
 }
diff --git a/arch/arm/mach-loki/include/mach/system.h b/arch/arm/mach-loki/include/mach/system.h
index 8db1147d4ec5..c1de36fe9b37 100644
--- a/arch/arm/mach-loki/include/mach/system.h
+++ b/arch/arm/mach-loki/include/mach/system.h
@@ -17,7 +17,7 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         /*
          * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
new file mode 100644
index 000000000000..c6a564fc4a7c
--- /dev/null
+++ b/arch/arm/mach-mmp/Kconfig
@@ -0,0 +1,47 @@
+if ARCH_MMP
+
+menu "Marvell PXA168/910 Implmentations"
+
+config MACH_ASPENITE
+        bool "Marvell's PXA168 Aspenite Development Board"
+        select CPU_PXA168
+        help
+          Say 'Y' here if you want to support the Marvell PXA168-based
+          Aspenite Development Board.
+
+config MACH_ZYLONITE2
+        bool "Marvell's PXA168 Zylonite2 Development Board"
+        select CPU_PXA168
+        help
+          Say 'Y' here if you want to support the Marvell PXA168-based
+          Zylonite2 Development Board.
+
+config MACH_TAVOREVB
+        bool "Marvell's PXA910 TavorEVB Development Board"
+        select CPU_PXA910
+        help
+          Say 'Y' here if you want to support the Marvell PXA910-based
+          TavorEVB Development Board.
+
+config MACH_TTC_DKB
+        bool "Marvell's PXA910 TavorEVB Development Board"
+        select CPU_PXA910
+        help
+          Say 'Y' here if you want to support the Marvell PXA910-based
+          TTC_DKB Development Board.
+
+endmenu
+
+config CPU_PXA168
+        bool
+        select CPU_MOHAWK
+        help
+          Select code specific to PXA168
+
+config CPU_PXA910
+        bool
+        select CPU_MOHAWK
+        help
+          Select code specific to PXA910
+
+endif
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
new file mode 100644
index 000000000000..6883e6584883
--- /dev/null
+++ b/arch/arm/mach-mmp/Makefile
@@ -0,0 +1,15 @@
+#
+# Makefile for Marvell's PXA168 processors line
+#
+
+obj-y                           += common.o clock.o devices.o irq.o time.o
+
+# SoC support
+obj-$(CONFIG_CPU_PXA168)        += pxa168.o
+obj-$(CONFIG_CPU_PXA910)        += pxa910.o
+
+# board support
+obj-$(CONFIG_MACH_ASPENITE)     += aspenite.o
+obj-$(CONFIG_MACH_ZYLONITE2)    += aspenite.o
+obj-$(CONFIG_MACH_TAVOREVB)     += tavorevb.o
+obj-$(CONFIG_MACH_TTC_DKB)      += ttc_dkb.o
diff --git a/arch/arm/mach-mmp/Makefile.boot b/arch/arm/mach-mmp/Makefile.boot
new file mode 100644
index 000000000000..574a4aa8321a
--- /dev/null
+++ b/arch/arm/mach-mmp/Makefile.boot
@@ -0,0 +1 @@
+   zreladdr-y   := 0x00008000
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
new file mode 100644
index 000000000000..4562452d4074
--- /dev/null
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -0,0 +1,117 @@
+/*
+ *  linux/arch/arm/mach-mmp/aspenite.c
+ *
+ *  Support for the Marvell PXA168-based Aspenite and Zylonite2
+ *  Development Platform.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/smc91x.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/addr-map.h>
+#include <mach/mfp-pxa168.h>
+#include <mach/pxa168.h>
+#include <mach/gpio.h>
+
+#include "common.h"
+
+static unsigned long common_pin_config[] __initdata = {
+        /* Data Flash Interface */
+        GPIO0_DFI_D15,
+        GPIO1_DFI_D14,
+        GPIO2_DFI_D13,
+        GPIO3_DFI_D12,
+        GPIO4_DFI_D11,
+        GPIO5_DFI_D10,
+        GPIO6_DFI_D9,
+        GPIO7_DFI_D8,
+        GPIO8_DFI_D7,
+        GPIO9_DFI_D6,
+        GPIO10_DFI_D5,
+        GPIO11_DFI_D4,
+        GPIO12_DFI_D3,
+        GPIO13_DFI_D2,
+        GPIO14_DFI_D1,
+        GPIO15_DFI_D0,
+
+        /* Static Memory Controller */
+        GPIO18_SMC_nCS0,
+        GPIO34_SMC_nCS1,
+        GPIO23_SMC_nLUA,
+        GPIO25_SMC_nLLA,
+        GPIO28_SMC_RDY,
+        GPIO29_SMC_SCLK,
+        GPIO35_SMC_BE1,
+        GPIO36_SMC_BE2,
+        GPIO27_GPIO,    /* Ethernet IRQ */
+
+        /* UART1 */
+        GPIO107_UART1_RXD,
+        GPIO108_UART1_TXD,
+};
+
+static struct smc91x_platdata smc91x_info = {
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
+};
+
+static struct resource smc91x_resources[] = {
+        [0] = {
+                .start  = SMC_CS1_PHYS_BASE + 0x300,
+                .end    = SMC_CS1_PHYS_BASE + 0xfffff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gpio_to_irq(27),
+                .end    = gpio_to_irq(27),
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+        }
+};
+
+static struct platform_device smc91x_device = {
+        .name           = "smc91x",
+        .id             = 0,
+        .dev            = {
+                .platform_data = &smc91x_info,
+        },
+        .num_resources  = ARRAY_SIZE(smc91x_resources),
+        .resource       = smc91x_resources,
+};
+
+static void __init common_init(void)
+{
+        mfp_config(ARRAY_AND_SIZE(common_pin_config));
+
+        /* on-chip devices */
+        pxa168_add_uart(1);
+
+        /* off-chip devices */
+        platform_device_register(&smc91x_device);
+}
+
+MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform")
+        .phys_io        = APB_PHYS_BASE,
+        .boot_params    = 0x00000100,
+        .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa168_init_irq,
+        .timer          = &pxa168_timer,
+        .init_machine   = common_init,
+MACHINE_END
+
+MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform")
+        .phys_io        = APB_PHYS_BASE,
+        .boot_params    = 0x00000100,
+        .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa168_init_irq,
+        .timer          = &pxa168_timer,
+        .init_machine   = common_init,
+MACHINE_END
diff --git a/arch/arm/mach-mmp/clock.c b/arch/arm/mach-mmp/clock.c
new file mode 100644
index 000000000000..2d9cc5a7122f
--- /dev/null
+++ b/arch/arm/mach-mmp/clock.c
@@ -0,0 +1,83 @@
+/*
+ *  linux/arch/arm/mach-mmp/clock.c
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <mach/regs-apbc.h>
+#include "clock.h"
+
+static void apbc_clk_enable(struct clk *clk)
+{
+        uint32_t clk_rst;
+
+        clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(clk->fnclksel);
+        __raw_writel(clk_rst, clk->clk_rst);
+}
+
+static void apbc_clk_disable(struct clk *clk)
+{
+        __raw_writel(0, clk->clk_rst);
+}
+
+struct clkops apbc_clk_ops = {
+        .enable         = apbc_clk_enable,
+        .disable        = apbc_clk_disable,
+};
+
+static DEFINE_SPINLOCK(clocks_lock);
+
+int clk_enable(struct clk *clk)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&clocks_lock, flags);
+        if (clk->enabled++ == 0)
+                clk->ops->enable(clk);
+        spin_unlock_irqrestore(&clocks_lock, flags);
+        return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+        unsigned long flags;
+
+        WARN_ON(clk->enabled == 0);
+
+        spin_lock_irqsave(&clocks_lock, flags);
+        if (--clk->enabled == 0)
+                clk->ops->disable(clk);
+        spin_unlock_irqrestore(&clocks_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+        unsigned long rate;
+
+        if (clk->ops->getrate)
+                rate = clk->ops->getrate(clk);
+        else
+                rate = clk->rate;
+
+        return rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+void clks_register(struct clk_lookup *clks, size_t num)
+{
+        int i;
+
+        for (i = 0; i < num; i++)
+                clkdev_add(&clks[i]);
+}
diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h
new file mode 100644
index 000000000000..ed967e78e6a8
--- /dev/null
+++ b/arch/arm/mach-mmp/clock.h
@@ -0,0 +1,71 @@
+/*
+ *  linux/arch/arm/mach-mmp/clock.h
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <asm/clkdev.h>
+
+struct clkops {
+        void                    (*enable)(struct clk *);
+        void                    (*disable)(struct clk *);
+        unsigned long           (*getrate)(struct clk *);
+};
+
+struct clk {
+        const struct clkops     *ops;
+
+        void __iomem    *clk_rst;       /* clock reset control register */
+        int             fnclksel;       /* functional clock select (APBC) */
+        uint32_t        enable_val;     /* value for clock enable (APMU) */
+        unsigned long   rate;
+        int             enabled;
+};
+
+extern struct clkops apbc_clk_ops;
+
+#define APBC_CLK(_name, _reg, _fnclksel, _rate)                 \
+struct clk clk_##_name = {                                      \
+                .clk_rst        = (void __iomem *)APBC_##_reg,  \
+                .fnclksel       = _fnclksel,                    \
+                .rate           = _rate,                        \
+                .ops            = &apbc_clk_ops,                \
+}
+
+#define APBC_CLK_OPS(_name, _reg, _fnclksel, _rate, _ops)       \
+struct clk clk_##_name = {                                      \
+                .clk_rst        = (void __iomem *)APBC_##_reg,  \
+                .fnclksel       = _fnclksel,                    \
+                .rate           = _rate,                        \
+                .ops            = _ops,                         \
+}
+
+#define APMU_CLK(_name, _reg, _eval, _rate)                     \
+struct clk clk_##_name = {                                      \
+                .clk_rst        = (void __iomem *)APMU_##_reg,  \
+                .enable_val     = _eval,                        \
+                .rate           = _rate,                        \
+                .ops            = &apmu_clk_ops,                \
+}
+
+#define APMU_CLK_OPS(_name, _reg, _eval, _rate, _ops)           \
+struct clk clk_##_name = {                                      \
+                .clk_rst        = (void __iomem *)APMU_##_reg,  \
+                .enable_val     = _eval,                        \
+                .rate           = _rate,                        \
+                .ops            = _ops,                         \
+}
+
+#define INIT_CLKREG(_clk, _devname, _conname)                   \
+        {                                                       \
+                .clk            = _clk,                         \
+                .dev_id         = _devname,                     \
+                .con_id         = _conname,                     \
+        }
+
+extern struct clk clk_pxa168_gpio;
+extern struct clk clk_pxa168_timers;
+
+extern void clks_register(struct clk_lookup *, size_t);
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
new file mode 100644
index 000000000000..e1e66c18b446
--- /dev/null
+++ b/arch/arm/mach-mmp/common.c
@@ -0,0 +1,37 @@
+/*
+ *  linux/arch/arm/mach-mmp/common.c
+ *
+ *  Code common to PXA168 processor lines
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <asm/page.h>
+#include <asm/mach/map.h>
+#include <mach/addr-map.h>
+
+#include "common.h"
+
+static struct map_desc standard_io_desc[] __initdata = {
+        {
+                .pfn            = __phys_to_pfn(APB_PHYS_BASE),
+                .virtual        = APB_VIRT_BASE,
+                .length         = APB_PHYS_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .pfn            = __phys_to_pfn(AXI_PHYS_BASE),
+                .virtual        = AXI_VIRT_BASE,
+                .length         = AXI_PHYS_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
+void __init pxa_map_io(void)
+{
+        iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
+}
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
new file mode 100644
index 000000000000..c33fbbc49417
--- /dev/null
+++ b/arch/arm/mach-mmp/common.h
@@ -0,0 +1,13 @@
+#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
+
+struct sys_timer;
+
+extern void timer_init(int irq);
+
+extern struct sys_timer pxa168_timer;
+extern struct sys_timer pxa910_timer;
+extern void __init pxa168_init_irq(void);
+extern void __init pxa910_init_irq(void);
+
+extern void __init icu_init_irq(void);
+extern void __init pxa_map_io(void);
diff --git a/arch/arm/mach-mmp/devices.c b/arch/arm/mach-mmp/devices.c
new file mode 100644
index 000000000000..191d9dea8731
--- /dev/null
+++ b/arch/arm/mach-mmp/devices.c
@@ -0,0 +1,69 @@
+/*
+ * linux/arch/arm/mach-mmp/devices.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/irq.h>
+#include <mach/devices.h>
+
+int __init pxa_register_device(struct pxa_device_desc *desc,
+                                void *data, size_t size)
+{
+        struct platform_device *pdev;
+        struct resource res[2 + MAX_RESOURCE_DMA];
+        int i, ret = 0, nres = 0;
+
+        pdev = platform_device_alloc(desc->drv_name, desc->id);
+        if (pdev == NULL)
+                return -ENOMEM;
+
+        pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+
+        memset(res, 0, sizeof(res));
+
+        if (desc->start != -1ul && desc->size > 0) {
+                res[nres].start = desc->start;
+                res[nres].end   = desc->start + desc->size - 1;
+                res[nres].flags = IORESOURCE_MEM;
+                nres++;
+        }
+
+        if (desc->irq != NO_IRQ) {
+                res[nres].start = desc->irq;
+                res[nres].end   = desc->irq;
+                res[nres].flags = IORESOURCE_IRQ;
+                nres++;
+        }
+
+        for (i = 0; i < MAX_RESOURCE_DMA; i++, nres++) {
+                if (desc->dma[i] == 0)
+                        break;
+
+                res[nres].start = desc->dma[i];
+                res[nres].end   = desc->dma[i];
+                res[nres].flags = IORESOURCE_DMA;
+        }
+
+        ret = platform_device_add_resources(pdev, res, nres);
+        if (ret) {
+                platform_device_put(pdev);
+                return ret;
+        }
+
+        if (data && size) {
+                ret = platform_device_add_data(pdev, data, size);
+                if (ret) {
+                        platform_device_put(pdev);
+                        return ret;
+                }
+        }
+
+        return platform_device_add(pdev);
+}
diff --git a/arch/arm/mach-mmp/include/mach/addr-map.h b/arch/arm/mach-mmp/include/mach/addr-map.h
new file mode 100644
index 000000000000..3254089a644d
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/addr-map.h
@@ -0,0 +1,34 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/addr-map.h
+ *
+ *   Common address map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_ADDR_MAP_H
+#define __ASM_MACH_ADDR_MAP_H
+
+/* APB - Application Subsystem Peripheral Bus
+ *
+ * NOTE: the DMA controller registers are actually on the AXI fabric #1
+ * slave port to AHB/APB bridge, due to its close relationship to those
+ * peripherals on APB, let's count it into the ABP mapping area.
+ */
+#define APB_PHYS_BASE           0xd4000000
+#define APB_VIRT_BASE           0xfe000000
+#define APB_PHYS_SIZE           0x00200000
+
+#define AXI_PHYS_BASE           0xd4200000
+#define AXI_VIRT_BASE           0xfe200000
+#define AXI_PHYS_SIZE           0x00200000
+
+/* Static Memory Controller - Chip Select 0 and 1 */
+#define SMC_CS0_PHYS_BASE       0x80000000
+#define SMC_CS0_PHYS_SIZE       0x10000000
+#define SMC_CS1_PHYS_BASE       0x90000000
+#define SMC_CS1_PHYS_SIZE       0x10000000
+
+#endif /* __ASM_MACH_ADDR_MAP_H */
diff --git a/arch/arm/mach-mmp/include/mach/clkdev.h b/arch/arm/mach-mmp/include/mach/clkdev.h
new file mode 100644
index 000000000000..2fb354e54e0d
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif /* __ASM_MACH_CLKDEV_H */
diff --git a/arch/arm/mach-mmp/include/mach/cputype.h b/arch/arm/mach-mmp/include/mach/cputype.h
new file mode 100644
index 000000000000..25e797b09083
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/cputype.h
@@ -0,0 +1,30 @@
+#ifndef __ASM_MACH_CPUTYPE_H
+#define __ASM_MACH_CPUTYPE_H
+
+#include <asm/cputype.h>
+
+/*
+ *  CPU   Stepping   OLD_ID       CPU_ID      CHIP_ID
+ *
+ * PXA168    A0    0x41159263   0x56158400   0x00A0A333
+ * PXA910    Y0    0x41159262   0x56158000   0x00F0C910
+ */
+
+#ifdef CONFIG_CPU_PXA168
+#  define __cpu_is_pxa168(id)   \
+        ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x84; })
+#else
+#  define __cpu_is_pxa168(id)   (0)
+#endif
+
+#ifdef CONFIG_CPU_PXA910
+#  define __cpu_is_pxa910(id)   \
+        ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x80; })
+#else
+#  define __cpu_is_pxa910(id)   (0)
+#endif
+
+#define cpu_is_pxa168()         ({ __cpu_is_pxa168(read_cpuid_id()); })
+#define cpu_is_pxa910()         ({ __cpu_is_pxa910(read_cpuid_id()); })
+
+#endif /* __ASM_MACH_CPUTYPE_H */
diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S
new file mode 100644
index 000000000000..a850f87de51d
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/debug-macro.S
@@ -0,0 +1,23 @@
+/* arch/arm/mach-mmp/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copied from arch/arm/mach-pxa/include/mach/debug.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <mach/addr-map.h>
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                         @ MMU enabled?
+                ldreq   \rx, =APB_PHYS_BASE             @ physical
+                ldrne   \rx, =APB_VIRT_BASE             @ virtual
+                orr     \rx, \rx, #0x00017000
+                .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-mmp/include/mach/devices.h b/arch/arm/mach-mmp/include/mach/devices.h
new file mode 100644
index 000000000000..24585397217e
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/devices.h
@@ -0,0 +1,37 @@
+#include <linux/types.h>
+
+#define MAX_RESOURCE_DMA        2
+
+/* structure for describing the on-chip devices */
+struct pxa_device_desc {
+        const char      *dev_name;
+        const char      *drv_name;
+        int             id;
+        int             irq;
+        unsigned long   start;
+        unsigned long   size;
+        int             dma[MAX_RESOURCE_DMA];
+};
+
+#define PXA168_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...)   \
+struct pxa_device_desc pxa168_device_##_name __initdata = {             \
+        .dev_name       = "pxa168-" #_name,                             \
+        .drv_name       = _drv,                                         \
+        .id             = _id,                                          \
+        .irq            = IRQ_PXA168_##_irq,                            \
+        .start          = _start,                                       \
+        .size           = _size,                                        \
+        .dma            = { _dma },                                     \
+};
+
+#define PXA910_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...)   \
+struct pxa_device_desc pxa910_device_##_name __initdata = {             \
+        .dev_name       = "pxa910-" #_name,                             \
+        .drv_name       = _drv,                                         \
+        .id             = _id,                                          \
+        .irq            = IRQ_PXA910_##_irq,                            \
+        .start          = _start,                                       \
+        .size           = _size,                                        \
+        .dma            = { _dma },                                     \
+};
+extern int pxa_register_device(struct pxa_device_desc *, void *, size_t);
diff --git a/arch/arm/mach-mmp/include/mach/dma.h b/arch/arm/mach-mmp/include/mach/dma.h
new file mode 100644
index 000000000000..1d6914544da4
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/dma.h
@@ -0,0 +1,13 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/dma.h
+ */
+
+#ifndef __ASM_MACH_DMA_H
+#define __ASM_MACH_DMA_H
+
+#include <mach/addr-map.h>
+
+#define DMAC_REGS_VIRT  (APB_VIRT_BASE + 0x00000)
+
+#include <plat/dma.h>
+#endif /* __ASM_MACH_DMA_H */
diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S
new file mode 100644
index 000000000000..6d3cd35478b5
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/entry-macro.S
@@ -0,0 +1,25 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/entry-macro.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <mach/regs-icu.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =ICU_AP_IRQ_SEL_INT_NUM
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        ldr     \tmp, [\base, #0]
+        and     \irqnr, \tmp, #0x3f
+        tst     \tmp, #(1 << 6)
+        .endm
diff --git a/arch/arm/mach-mmp/include/mach/gpio.h b/arch/arm/mach-mmp/include/mach/gpio.h
new file mode 100644
index 000000000000..ab26d13295c4
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/gpio.h
@@ -0,0 +1,36 @@
+#ifndef __ASM_MACH_GPIO_H
+#define __ASM_MACH_GPIO_H
+
+#include <mach/addr-map.h>
+#include <mach/irqs.h>
+#include <asm-generic/gpio.h>
+
+#define GPIO_REGS_VIRT  (APB_VIRT_BASE + 0x19000)
+
+#define BANK_OFF(n)     (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
+#define GPIO_REG(x)     (*((volatile u32 *)(GPIO_REGS_VIRT + (x))))
+
+#define NR_BUILTIN_GPIO (128)
+
+#define gpio_to_bank(gpio)      ((gpio) >> 5)
+#define gpio_to_irq(gpio)       (IRQ_GPIO_START + (gpio))
+#define irq_to_gpio(irq)        ((irq) - IRQ_GPIO_START)
+
+
+#define __gpio_is_inverted(gpio)        (0)
+#define __gpio_is_occupied(gpio)        (0)
+
+/* NOTE: these macros are defined here to make optimization of
+ * gpio_{get,set}_value() to work when 'gpio' is a constant.
+ * Usage of these macros otherwise is no longer recommended,
+ * use generic GPIO API whenever possible.
+ */
+#define GPIO_bit(gpio)  (1 << ((gpio) & 0x1f))
+
+#define GPLR(x)         GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x00)
+#define GPDR(x)         GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x0c)
+#define GPSR(x)         GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x18)
+#define GPCR(x)         GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x24)
+
+#include <plat/gpio.h>
+#endif /* __ASM_MACH_GPIO_H */
diff --git a/arch/arm/mach-mmp/include/mach/hardware.h b/arch/arm/mach-mmp/include/mach/hardware.h
new file mode 100644
index 000000000000..99264a5ce5e4
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/hardware.h
@@ -0,0 +1,4 @@
+#ifndef __ASM_MACH_HARDWARE_H
+#define __ASM_MACH_HARDWARE_H
+
+#endif /* __ASM_MACH_HARDWARE_H */
diff --git a/arch/arm/mach-mmp/include/mach/io.h b/arch/arm/mach-mmp/include/mach/io.h
new file mode 100644
index 000000000000..e7adf3d012c1
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/io.h
@@ -0,0 +1,21 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/io.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_IO_H
+#define __ASM_MACH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a)         __typesafe_io(a)
+#define __mem_pci(a)    (a)
+
+#endif /* __ASM_MACH_IO_H */
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h
new file mode 100644
index 000000000000..e83e45ebf7a4
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/irqs.h
@@ -0,0 +1,119 @@
+#ifndef __ASM_MACH_IRQS_H
+#define __ASM_MACH_IRQS_H
+
+/*
+ * Interrupt numbers for PXA168
+ */
+#define IRQ_PXA168_NONE                 (-1)
+#define IRQ_PXA168_SSP3                 0
+#define IRQ_PXA168_SSP2                 1
+#define IRQ_PXA168_SSP1                 2
+#define IRQ_PXA168_SSP0                 3
+#define IRQ_PXA168_PMIC_INT             4
+#define IRQ_PXA168_RTC_INT              5
+#define IRQ_PXA168_RTC_ALARM            6
+#define IRQ_PXA168_TWSI0                7
+#define IRQ_PXA168_GPU                  8
+#define IRQ_PXA168_KEYPAD               9
+#define IRQ_PXA168_ONEWIRE              12
+#define IRQ_PXA168_TIMER1               13
+#define IRQ_PXA168_TIMER2               14
+#define IRQ_PXA168_TIMER3               15
+#define IRQ_PXA168_CMU                  16
+#define IRQ_PXA168_SSP4                 17
+#define IRQ_PXA168_MSP_WAKEUP           19
+#define IRQ_PXA168_CF_WAKEUP            20
+#define IRQ_PXA168_XD_WAKEUP            21
+#define IRQ_PXA168_MFU                  22
+#define IRQ_PXA168_MSP                  23
+#define IRQ_PXA168_CF                   24
+#define IRQ_PXA168_XD                   25
+#define IRQ_PXA168_DDR_INT              26
+#define IRQ_PXA168_UART1                27
+#define IRQ_PXA168_UART2                28
+#define IRQ_PXA168_WDT                  35
+#define IRQ_PXA168_FRQ_CHANGE           38
+#define IRQ_PXA168_SDH1                 39
+#define IRQ_PXA168_SDH2                 40
+#define IRQ_PXA168_LCD                  41
+#define IRQ_PXA168_CI                   42
+#define IRQ_PXA168_USB1                 44
+#define IRQ_PXA168_NAND                 45
+#define IRQ_PXA168_HIFI_DMA             46
+#define IRQ_PXA168_DMA_INT0             47
+#define IRQ_PXA168_DMA_INT1             48
+#define IRQ_PXA168_GPIOX                49
+#define IRQ_PXA168_USB2                 51
+#define IRQ_PXA168_AC97                 57
+#define IRQ_PXA168_TWSI1                58
+#define IRQ_PXA168_PMU                  60
+#define IRQ_PXA168_SM_INT               63
+
+/*
+ * Interrupt numbers for PXA910
+ */
+#define IRQ_PXA910_AIRQ                 0
+#define IRQ_PXA910_SSP3                 1
+#define IRQ_PXA910_SSP2                 2
+#define IRQ_PXA910_SSP1                 3
+#define IRQ_PXA910_PMIC_INT             4
+#define IRQ_PXA910_RTC_INT              5
+#define IRQ_PXA910_RTC_ALARM            6
+#define IRQ_PXA910_TWSI0                7
+#define IRQ_PXA910_GPU                  8
+#define IRQ_PXA910_KEYPAD               9
+#define IRQ_PXA910_ROTARY               10
+#define IRQ_PXA910_TRACKBALL            11
+#define IRQ_PXA910_ONEWIRE              12
+#define IRQ_PXA910_AP1_TIMER1           13
+#define IRQ_PXA910_AP1_TIMER2           14
+#define IRQ_PXA910_AP1_TIMER3           15
+#define IRQ_PXA910_IPC_AP0              16
+#define IRQ_PXA910_IPC_AP1              17
+#define IRQ_PXA910_IPC_AP2              18
+#define IRQ_PXA910_IPC_AP3              19
+#define IRQ_PXA910_IPC_AP4              20
+#define IRQ_PXA910_IPC_CP0              21
+#define IRQ_PXA910_IPC_CP1              22
+#define IRQ_PXA910_IPC_CP2              23
+#define IRQ_PXA910_IPC_CP3              24
+#define IRQ_PXA910_IPC_CP4              25
+#define IRQ_PXA910_L2_DDR               26
+#define IRQ_PXA910_UART2                27
+#define IRQ_PXA910_UART3                28
+#define IRQ_PXA910_AP2_TIMER1           29
+#define IRQ_PXA910_AP2_TIMER2           30
+#define IRQ_PXA910_CP2_TIMER1           31
+#define IRQ_PXA910_CP2_TIMER2           32
+#define IRQ_PXA910_CP2_TIMER3           33
+#define IRQ_PXA910_GSSP                 34
+#define IRQ_PXA910_CP2_WDT              35
+#define IRQ_PXA910_MAIN_PMU             36
+#define IRQ_PXA910_CP_FREQ_CHG          37
+#define IRQ_PXA910_AP_FREQ_CHG          38
+#define IRQ_PXA910_MMC                  39
+#define IRQ_PXA910_AEU                  40
+#define IRQ_PXA910_LCD                  41
+#define IRQ_PXA910_CCIC                 42
+#define IRQ_PXA910_IRE                  43
+#define IRQ_PXA910_USB1                 44
+#define IRQ_PXA910_NAND                 45
+#define IRQ_PXA910_HIFI_DMA             46
+#define IRQ_PXA910_DMA_INT0             47
+#define IRQ_PXA910_DMA_INT1             48
+#define IRQ_PXA910_AP_GPIO              49
+#define IRQ_PXA910_AP2_TIMER3           50
+#define IRQ_PXA910_USB2                 51
+#define IRQ_PXA910_TWSI1                54
+#define IRQ_PXA910_CP_GPIO              55
+#define IRQ_PXA910_UART1                59      /* Slow UART */
+#define IRQ_PXA910_AP_PMU               60
+#define IRQ_PXA910_SM_INT               63      /* from PinMux */
+
+#define IRQ_GPIO_START                  64
+#define IRQ_GPIO_NUM                    128
+#define IRQ_GPIO(x)                     (IRQ_GPIO_START + (x))
+
+#define NR_IRQS         (IRQ_GPIO_START + IRQ_GPIO_NUM)
+
+#endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-mmp/include/mach/memory.h b/arch/arm/mach-mmp/include/mach/memory.h
new file mode 100644
index 000000000000..bdb21d70714c
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/memory.h
@@ -0,0 +1,14 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/memory.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_MEMORY_H
+#define __ASM_MACH_MEMORY_H
+
+#define PHYS_OFFSET     UL(0x00000000)
+
+#endif /* __ASM_MACH_MEMORY_H */
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
new file mode 100644
index 000000000000..d0bdb6e3682b
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
@@ -0,0 +1,258 @@
+#ifndef __ASM_MACH_MFP_PXA168_H
+#define __ASM_MACH_MFP_PXA168_H
+
+#include <mach/mfp.h>
+
+/* GPIO */
+#define GPIO0_GPIO              MFP_CFG(GPIO0, AF5)
+#define GPIO1_GPIO              MFP_CFG(GPIO1, AF5)
+#define GPIO2_GPIO              MFP_CFG(GPIO2, AF5)
+#define GPIO3_GPIO              MFP_CFG(GPIO3, AF5)
+#define GPIO4_GPIO              MFP_CFG(GPIO4, AF5)
+#define GPIO5_GPIO              MFP_CFG(GPIO5, AF5)
+#define GPIO6_GPIO              MFP_CFG(GPIO6, AF5)
+#define GPIO7_GPIO              MFP_CFG(GPIO7, AF5)
+#define GPIO8_GPIO              MFP_CFG(GPIO8, AF5)
+#define GPIO9_GPIO              MFP_CFG(GPIO9, AF5)
+#define GPIO10_GPIO             MFP_CFG(GPIO10, AF5)
+#define GPIO11_GPIO             MFP_CFG(GPIO11, AF5)
+#define GPIO12_GPIO             MFP_CFG(GPIO12, AF5)
+#define GPIO13_GPIO             MFP_CFG(GPIO13, AF5)
+#define GPIO14_GPIO             MFP_CFG(GPIO14, AF5)
+#define GPIO15_GPIO             MFP_CFG(GPIO15, AF5)
+#define GPIO16_GPIO             MFP_CFG(GPIO16, AF0)
+#define GPIO17_GPIO             MFP_CFG(GPIO17, AF5)
+#define GPIO18_GPIO             MFP_CFG(GPIO18, AF0)
+#define GPIO19_GPIO             MFP_CFG(GPIO19, AF5)
+#define GPIO20_GPIO             MFP_CFG(GPIO20, AF0)
+#define GPIO21_GPIO             MFP_CFG(GPIO21, AF5)
+#define GPIO22_GPIO             MFP_CFG(GPIO22, AF5)
+#define GPIO23_GPIO             MFP_CFG(GPIO23, AF5)
+#define GPIO24_GPIO             MFP_CFG(GPIO24, AF5)
+#define GPIO25_GPIO             MFP_CFG(GPIO25, AF5)
+#define GPIO26_GPIO             MFP_CFG(GPIO26, AF0)
+#define GPIO27_GPIO             MFP_CFG(GPIO27, AF5)
+#define GPIO28_GPIO             MFP_CFG(GPIO28, AF5)
+#define GPIO29_GPIO             MFP_CFG(GPIO29, AF5)
+#define GPIO30_GPIO             MFP_CFG(GPIO30, AF5)
+#define GPIO31_GPIO             MFP_CFG(GPIO31, AF5)
+#define GPIO32_GPIO             MFP_CFG(GPIO32, AF5)
+#define GPIO33_GPIO             MFP_CFG(GPIO33, AF5)
+#define GPIO34_GPIO             MFP_CFG(GPIO34, AF0)
+#define GPIO35_GPIO             MFP_CFG(GPIO35, AF0)
+#define GPIO36_GPIO             MFP_CFG(GPIO36, AF0)
+#define GPIO37_GPIO             MFP_CFG(GPIO37, AF0)
+#define GPIO38_GPIO             MFP_CFG(GPIO38, AF0)
+#define GPIO39_GPIO             MFP_CFG(GPIO39, AF0)
+#define GPIO40_GPIO             MFP_CFG(GPIO40, AF0)
+#define GPIO41_GPIO             MFP_CFG(GPIO41, AF0)
+#define GPIO42_GPIO             MFP_CFG(GPIO42, AF0)
+#define GPIO43_GPIO             MFP_CFG(GPIO43, AF0)
+#define GPIO44_GPIO             MFP_CFG(GPIO44, AF0)
+#define GPIO45_GPIO             MFP_CFG(GPIO45, AF0)
+#define GPIO46_GPIO             MFP_CFG(GPIO46, AF0)
+#define GPIO47_GPIO             MFP_CFG(GPIO47, AF0)
+#define GPIO48_GPIO             MFP_CFG(GPIO48, AF0)
+#define GPIO49_GPIO             MFP_CFG(GPIO49, AF0)
+#define GPIO50_GPIO             MFP_CFG(GPIO50, AF0)
+#define GPIO51_GPIO             MFP_CFG(GPIO51, AF0)
+#define GPIO52_GPIO             MFP_CFG(GPIO52, AF0)
+#define GPIO53_GPIO             MFP_CFG(GPIO53, AF0)
+#define GPIO54_GPIO             MFP_CFG(GPIO54, AF0)
+#define GPIO55_GPIO             MFP_CFG(GPIO55, AF0)
+#define GPIO56_GPIO             MFP_CFG(GPIO56, AF0)
+#define GPIO57_GPIO             MFP_CFG(GPIO57, AF0)
+#define GPIO58_GPIO             MFP_CFG(GPIO58, AF0)
+#define GPIO59_GPIO             MFP_CFG(GPIO59, AF0)
+#define GPIO60_GPIO             MFP_CFG(GPIO60, AF0)
+#define GPIO61_GPIO             MFP_CFG(GPIO61, AF0)
+#define GPIO62_GPIO             MFP_CFG(GPIO62, AF0)
+#define GPIO63_GPIO             MFP_CFG(GPIO63, AF0)
+#define GPIO64_GPIO             MFP_CFG(GPIO64, AF0)
+#define GPIO65_GPIO             MFP_CFG(GPIO65, AF0)
+#define GPIO66_GPIO             MFP_CFG(GPIO66, AF0)
+#define GPIO67_GPIO             MFP_CFG(GPIO67, AF0)
+#define GPIO68_GPIO             MFP_CFG(GPIO68, AF0)
+#define GPIO69_GPIO             MFP_CFG(GPIO69, AF0)
+#define GPIO70_GPIO             MFP_CFG(GPIO70, AF0)
+#define GPIO71_GPIO             MFP_CFG(GPIO71, AF0)
+#define GPIO72_GPIO             MFP_CFG(GPIO72, AF0)
+#define GPIO73_GPIO             MFP_CFG(GPIO73, AF0)
+#define GPIO74_GPIO             MFP_CFG(GPIO74, AF0)
+#define GPIO75_GPIO             MFP_CFG(GPIO75, AF0)
+#define GPIO76_GPIO             MFP_CFG(GPIO76, AF0)
+#define GPIO77_GPIO             MFP_CFG(GPIO77, AF0)
+#define GPIO78_GPIO             MFP_CFG(GPIO78, AF0)
+#define GPIO79_GPIO             MFP_CFG(GPIO79, AF0)
+#define GPIO80_GPIO             MFP_CFG(GPIO80, AF0)
+#define GPIO81_GPIO             MFP_CFG(GPIO81, AF0)
+#define GPIO82_GPIO             MFP_CFG(GPIO82, AF0)
+#define GPIO83_GPIO             MFP_CFG(GPIO83, AF0)
+#define GPIO84_GPIO             MFP_CFG(GPIO84, AF0)
+#define GPIO85_GPIO             MFP_CFG(GPIO85, AF0)
+#define GPIO86_GPIO             MFP_CFG(GPIO86, AF0)
+#define GPIO87_GPIO             MFP_CFG(GPIO87, AF0)
+#define GPIO88_GPIO             MFP_CFG(GPIO88, AF0)
+#define GPIO89_GPIO             MFP_CFG(GPIO89, AF0)
+#define GPIO90_GPIO             MFP_CFG(GPIO90, AF0)
+#define GPIO91_GPIO             MFP_CFG(GPIO91, AF0)
+#define GPIO92_GPIO             MFP_CFG(GPIO92, AF0)
+#define GPIO93_GPIO             MFP_CFG(GPIO93, AF0)
+#define GPIO94_GPIO             MFP_CFG(GPIO94, AF0)
+#define GPIO95_GPIO             MFP_CFG(GPIO95, AF0)
+#define GPIO96_GPIO             MFP_CFG(GPIO96, AF0)
+#define GPIO97_GPIO             MFP_CFG(GPIO97, AF0)
+#define GPIO98_GPIO             MFP_CFG(GPIO98, AF0)
+#define GPIO99_GPIO             MFP_CFG(GPIO99, AF0)
+#define GPIO100_GPIO            MFP_CFG(GPIO100, AF0)
+#define GPIO101_GPIO            MFP_CFG(GPIO101, AF0)
+#define GPIO102_GPIO            MFP_CFG(GPIO102, AF0)
+#define GPIO103_GPIO            MFP_CFG(GPIO103, AF0)
+#define GPIO104_GPIO            MFP_CFG(GPIO104, AF0)
+#define GPIO105_GPIO            MFP_CFG(GPIO105, AF0)
+#define GPIO106_GPIO            MFP_CFG(GPIO106, AF0)
+#define GPIO107_GPIO            MFP_CFG(GPIO107, AF0)
+#define GPIO108_GPIO            MFP_CFG(GPIO108, AF0)
+#define GPIO109_GPIO            MFP_CFG(GPIO109, AF0)
+#define GPIO110_GPIO            MFP_CFG(GPIO110, AF0)
+#define GPIO111_GPIO            MFP_CFG(GPIO111, AF0)
+#define GPIO112_GPIO            MFP_CFG(GPIO112, AF0)
+#define GPIO113_GPIO            MFP_CFG(GPIO113, AF0)
+#define GPIO114_GPIO            MFP_CFG(GPIO114, AF0)
+#define GPIO115_GPIO            MFP_CFG(GPIO115, AF0)
+#define GPIO116_GPIO            MFP_CFG(GPIO116, AF0)
+#define GPIO117_GPIO            MFP_CFG(GPIO117, AF0)
+#define GPIO118_GPIO            MFP_CFG(GPIO118, AF0)
+#define GPIO119_GPIO            MFP_CFG(GPIO119, AF0)
+#define GPIO120_GPIO            MFP_CFG(GPIO120, AF0)
+#define GPIO121_GPIO            MFP_CFG(GPIO121, AF0)
+#define GPIO122_GPIO            MFP_CFG(GPIO122, AF0)
+
+/* DFI */
+#define GPIO0_DFI_D15           MFP_CFG(GPIO0, AF0)
+#define GPIO1_DFI_D14           MFP_CFG(GPIO1, AF0)
+#define GPIO2_DFI_D13           MFP_CFG(GPIO2, AF0)
+#define GPIO3_DFI_D12           MFP_CFG(GPIO3, AF0)
+#define GPIO4_DFI_D11           MFP_CFG(GPIO4, AF0)
+#define GPIO5_DFI_D10           MFP_CFG(GPIO5, AF0)
+#define GPIO6_DFI_D9            MFP_CFG(GPIO6, AF0)
+#define GPIO7_DFI_D8            MFP_CFG(GPIO7, AF0)
+#define GPIO8_DFI_D7            MFP_CFG(GPIO8, AF0)
+#define GPIO9_DFI_D6            MFP_CFG(GPIO9, AF0)
+#define GPIO10_DFI_D5           MFP_CFG(GPIO10, AF0)
+#define GPIO11_DFI_D4           MFP_CFG(GPIO11, AF0)
+#define GPIO12_DFI_D3           MFP_CFG(GPIO12, AF0)
+#define GPIO13_DFI_D2           MFP_CFG(GPIO13, AF0)
+#define GPIO14_DFI_D1           MFP_CFG(GPIO14, AF0)
+#define GPIO15_DFI_D0           MFP_CFG(GPIO15, AF0)
+
+#define GPIO30_DFI_ADDR0        MFP_CFG(GPIO30, AF0)
+#define GPIO31_DFI_ADDR1        MFP_CFG(GPIO31, AF0)
+#define GPIO32_DFI_ADDR2        MFP_CFG(GPIO32, AF0)
+#define GPIO33_DFI_ADDR3        MFP_CFG(GPIO33, AF0)
+
+/* NAND */
+#define GPIO16_ND_nCS0          MFP_CFG(GPIO16, AF1)
+#define GPIO17_ND_nWE           MFP_CFG(GPIO17, AF0)
+#define GPIO21_ND_ALE           MFP_CFG(GPIO21, AF0)
+#define GPIO22_ND_CLE           MFP_CFG(GPIO22, AF0)
+#define GPIO24_ND_nRE           MFP_CFG(GPIO24, AF0)
+#define GPIO26_ND_RnB1          MFP_CFG(GPIO26, AF1)
+#define GPIO27_ND_RnB2          MFP_CFG(GPIO27, AF1)
+
+/* Static Memory Controller */
+#define GPIO18_SMC_nCS0         MFP_CFG(GPIO18, AF3)
+#define GPIO18_SMC_nCS1         MFP_CFG(GPIO18, AF2)
+#define GPIO16_SMC_nCS0         MFP_CFG(GPIO16, AF2)
+#define GPIO16_SMC_nCS1         MFP_CFG(GPIO16, AF3)
+#define GPIO19_SMC_nCS0         MFP_CFG(GPIO19, AF0)
+#define GPIO20_SMC_nCS1         MFP_CFG(GPIO20, AF2)
+#define GPIO23_SMC_nLUA         MFP_CFG(GPIO23, AF0)
+#define GPIO25_SMC_nLLA         MFP_CFG(GPIO25, AF0)
+#define GPIO27_SMC_IRQ          MFP_CFG(GPIO27, AF0)
+#define GPIO28_SMC_RDY          MFP_CFG(GPIO28, AF0)
+#define GPIO29_SMC_SCLK         MFP_CFG(GPIO29, AF0)
+#define GPIO34_SMC_nCS1         MFP_CFG(GPIO34, AF2)
+#define GPIO35_SMC_BE1          MFP_CFG(GPIO35, AF2)
+#define GPIO36_SMC_BE2          MFP_CFG(GPIO36, AF2)
+
+/* Compact Flash */
+#define GPIO19_CF_nCE1          MFP_CFG(GPIO19, AF3)
+#define GPIO20_CF_nCE2          MFP_CFG(GPIO20, AF3)
+#define GPIO23_CF_nALE          MFP_CFG(GPIO23, AF3)
+#define GPIO25_CF_nRESET        MFP_CFG(GPIO25, AF3)
+#define GPIO28_CF_RDY           MFP_CFG(GPIO28, AF3)
+#define GPIO29_CF_STSCH         MFP_CFG(GPIO29, AF3)
+#define GPIO30_CF_nREG          MFP_CFG(GPIO30, AF3)
+#define GPIO31_CF_nIOIS16       MFP_CFG(GPIO31, AF3)
+#define GPIO32_CF_nCD1          MFP_CFG(GPIO32, AF3)
+#define GPIO33_CF_nCD2          MFP_CFG(GPIO33, AF3)
+
+/* UART1 */
+#define GPIO107_UART1_TXD       MFP_CFG_DRV(GPIO107, AF1, FAST)
+#define GPIO107_UART1_RXD       MFP_CFG_DRV(GPIO107, AF2, FAST)
+#define GPIO108_UART1_RXD       MFP_CFG_DRV(GPIO108, AF1, FAST)
+#define GPIO108_UART1_TXD       MFP_CFG_DRV(GPIO108, AF2, FAST)
+#define GPIO109_UART1_CTS       MFP_CFG(GPIO109, AF1)
+#define GPIO109_UART1_RTS       MFP_CFG(GPIO109, AF2)
+#define GPIO110_UART1_RTS       MFP_CFG(GPIO110, AF1)
+#define GPIO110_UART1_CTS       MFP_CFG(GPIO110, AF2)
+#define GPIO111_UART1_RI        MFP_CFG(GPIO111, AF1)
+#define GPIO111_UART1_DSR       MFP_CFG(GPIO111, AF2)
+#define GPIO112_UART1_DTR       MFP_CFG(GPIO111, AF1)
+#define GPIO112_UART1_DCD       MFP_CFG(GPIO112, AF2)
+
+/* MMC1 */
+#define GPIO37_MMC1_DAT7        MFP_CFG(GPIO37, AF1)
+#define GPIO38_MMC1_DAT6        MFP_CFG(GPIO38, AF1)
+#define GPIO54_MMC1_DAT5        MFP_CFG(GPIO54, AF1)
+#define GPIO48_MMC1_DAT4        MFP_CFG(GPIO48, AF1)
+#define GPIO51_MMC1_DAT3        MFP_CFG(GPIO51, AF1)
+#define GPIO52_MMC1_DAT2        MFP_CFG(GPIO52, AF1)
+#define GPIO40_MMC1_DAT1        MFP_CFG(GPIO40, AF1)
+#define GPIO41_MMC1_DAT0        MFP_CFG(GPIO41, AF1)
+#define GPIO49_MMC1_CMD         MFP_CFG(GPIO49, AF1)
+#define GPIO43_MMC1_CLK         MFP_CFG(GPIO43, AF1)
+#define GPIO53_MMC1_CD          MFP_CFG(GPIO53, AF1)
+#define GPIO46_MMC1_WP          MFP_CFG(GPIO46, AF1)
+
+/* LCD */
+#define GPIO84_LCD_CS           MFP_CFG(GPIO84, AF1)
+#define GPIO60_LCD_DD0          MFP_CFG(GPIO60, AF1)
+#define GPIO61_LCD_DD1          MFP_CFG(GPIO61, AF1)
+#define GPIO70_LCD_DD10         MFP_CFG(GPIO70, AF1)
+#define GPIO71_LCD_DD11         MFP_CFG(GPIO71, AF1)
+#define GPIO72_LCD_DD12         MFP_CFG(GPIO72, AF1)
+#define GPIO73_LCD_DD13         MFP_CFG(GPIO73, AF1)
+#define GPIO74_LCD_DD14         MFP_CFG(GPIO74, AF1)
+#define GPIO75_LCD_DD15         MFP_CFG(GPIO75, AF1)
+#define GPIO76_LCD_DD16         MFP_CFG(GPIO76, AF1)
+#define GPIO77_LCD_DD17         MFP_CFG(GPIO77, AF1)
+#define GPIO78_LCD_DD18         MFP_CFG(GPIO78, AF1)
+#define GPIO79_LCD_DD19         MFP_CFG(GPIO79, AF1)
+#define GPIO62_LCD_DD2          MFP_CFG(GPIO62, AF1)
+#define GPIO80_LCD_DD20         MFP_CFG(GPIO80, AF1)
+#define GPIO81_LCD_DD21         MFP_CFG(GPIO81, AF1)
+#define GPIO82_LCD_DD22         MFP_CFG(GPIO82, AF1)
+#define GPIO83_LCD_DD23         MFP_CFG(GPIO83, AF1)
+#define GPIO63_LCD_DD3          MFP_CFG(GPIO63, AF1)
+#define GPIO64_LCD_DD4          MFP_CFG(GPIO64, AF1)
+#define GPIO65_LCD_DD5          MFP_CFG(GPIO65, AF1)
+#define GPIO66_LCD_DD6          MFP_CFG(GPIO66, AF1)
+#define GPIO67_LCD_DD7          MFP_CFG(GPIO67, AF1)
+#define GPIO68_LCD_DD8          MFP_CFG(GPIO68, AF1)
+#define GPIO69_LCD_DD9          MFP_CFG(GPIO69, AF1)
+#define GPIO59_LCD_DENA_BIAS    MFP_CFG(GPIO59, AF1)
+#define GPIO56_LCD_FCLK_RD      MFP_CFG(GPIO56, AF1)
+#define GPIO57_LCD_LCLK_A0      MFP_CFG(GPIO57, AF1)
+#define GPIO58_LCD_PCLK_WR      MFP_CFG(GPIO58, AF1)
+#define GPIO85_LCD_VSYNC        MFP_CFG(GPIO85, AF1)
+
+/* I2S */
+#define GPIO113_I2S_MCLK        MFP_CFG(GPIO113,AF6)
+#define GPIO114_I2S_FRM         MFP_CFG(GPIO114,AF1)
+#define GPIO115_I2S_BCLK        MFP_CFG(GPIO115,AF1)
+#define GPIO116_I2S_RXD         MFP_CFG(GPIO116,AF2)
+#define GPIO117_I2S_TXD         MFP_CFG(GPIO117,AF2)
+
+#endif /* __ASM_MACH_MFP_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
new file mode 100644
index 000000000000..48a1cbc7c56b
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
@@ -0,0 +1,157 @@
+#ifndef __ASM_MACH_MFP_PXA910_H
+#define __ASM_MACH_MFP_PXA910_H
+
+#include <mach/mfp.h>
+
+/* UART2 */
+#define GPIO47_UART2_RXD        MFP_CFG(GPIO47, AF6)
+#define GPIO48_UART2_TXD        MFP_CFG(GPIO48, AF6)
+
+/* UART3 */
+#define GPIO31_UART3_RXD        MFP_CFG(GPIO31, AF4)
+#define GPIO32_UART3_TXD        MFP_CFG(GPIO32, AF4)
+
+/*IRDA*/
+#define GPIO51_IRDA_SHDN        MFP_CFG(GPIO51, AF0)
+
+/* SMC */
+#define SM_nCS0_nCS0            MFP_CFG(SM_nCS0, AF0)
+#define SM_ADV_SM_ADV           MFP_CFG(SM_ADV, AF0)
+#define SM_SCLK_SM_SCLK         MFP_CFG(SM_SCLK, AF0)
+#define SM_SCLK_SM_SCLK         MFP_CFG(SM_SCLK, AF0)
+#define SM_BE0_SM_BE0           MFP_CFG(SM_BE0, AF1)
+#define SM_BE1_SM_BE1           MFP_CFG(SM_BE1, AF1)
+
+/* I2C */
+#define GPIO53_CI2C_SCL         MFP_CFG(GPIO53, AF2)
+#define GPIO54_CI2C_SDA         MFP_CFG(GPIO54, AF2)
+
+/* SSP1 (I2S) */
+#define GPIO24_SSP1_SDATA_IN    MFP_CFG_DRV(GPIO24, AF1, MEDIUM)
+#define GPIO21_SSP1_BITCLK      MFP_CFG_DRV(GPIO21, AF1, MEDIUM)
+#define GPIO20_SSP1_SYSCLK      MFP_CFG_DRV(GPIO20, AF1, MEDIUM)
+#define GPIO22_SSP1_SYNC        MFP_CFG_DRV(GPIO22, AF1, MEDIUM)
+#define GPIO23_SSP1_DATA_OUT    MFP_CFG_DRV(GPIO23, AF1, MEDIUM)
+#define GPIO124_MN_CLK_OUT      MFP_CFG_DRV(GPIO124, AF1, MEDIUM)
+#define GPIO123_CLK_REQ         MFP_CFG_DRV(GPIO123, AF0, MEDIUM)
+
+/* DFI */
+#define DF_IO0_ND_IO0           MFP_CFG(DF_IO0, AF0)
+#define DF_IO1_ND_IO1           MFP_CFG(DF_IO1, AF0)
+#define DF_IO2_ND_IO2           MFP_CFG(DF_IO2, AF0)
+#define DF_IO3_ND_IO3           MFP_CFG(DF_IO3, AF0)
+#define DF_IO4_ND_IO4           MFP_CFG(DF_IO4, AF0)
+#define DF_IO5_ND_IO5           MFP_CFG(DF_IO5, AF0)
+#define DF_IO6_ND_IO6           MFP_CFG(DF_IO6, AF0)
+#define DF_IO7_ND_IO7           MFP_CFG(DF_IO7, AF0)
+#define DF_IO8_ND_IO8           MFP_CFG(DF_IO8, AF0)
+#define DF_IO9_ND_IO9           MFP_CFG(DF_IO9, AF0)
+#define DF_IO10_ND_IO10         MFP_CFG(DF_IO10, AF0)
+#define DF_IO11_ND_IO11         MFP_CFG(DF_IO11, AF0)
+#define DF_IO12_ND_IO12         MFP_CFG(DF_IO12, AF0)
+#define DF_IO13_ND_IO13         MFP_CFG(DF_IO13, AF0)
+#define DF_IO14_ND_IO14         MFP_CFG(DF_IO14, AF0)
+#define DF_IO15_ND_IO15         MFP_CFG(DF_IO15, AF0)
+#define DF_nCS0_SM_nCS2_nCS0    MFP_CFG(DF_nCS0_SM_nCS2, AF0)
+#define DF_ALE_SM_WEn_ND_ALE    MFP_CFG(DF_ALE_SM_WEn, AF1)
+#define DF_CLE_SM_OEn_ND_CLE    MFP_CFG(DF_CLE_SM_OEn, AF0)
+#define DF_WEn_DF_WEn           MFP_CFG(DF_WEn, AF1)
+#define DF_REn_DF_REn           MFP_CFG(DF_REn, AF1)
+#define DF_RDY0_DF_RDY0         MFP_CFG(DF_RDY0, AF0)
+
+/*keypad*/
+#define GPIO00_KP_MKIN0         MFP_CFG(GPIO0, AF1)
+#define GPIO01_KP_MKOUT0        MFP_CFG(GPIO1, AF1)
+#define GPIO02_KP_MKIN1         MFP_CFG(GPIO2, AF1)
+#define GPIO03_KP_MKOUT1        MFP_CFG(GPIO3, AF1)
+#define GPIO04_KP_MKIN2         MFP_CFG(GPIO4, AF1)
+#define GPIO05_KP_MKOUT2        MFP_CFG(GPIO5, AF1)
+#define GPIO06_KP_MKIN3         MFP_CFG(GPIO6, AF1)
+#define GPIO07_KP_MKOUT3        MFP_CFG(GPIO7, AF1)
+#define GPIO08_KP_MKIN4         MFP_CFG(GPIO8, AF1)
+#define GPIO09_KP_MKOUT4        MFP_CFG(GPIO9, AF1)
+#define GPIO10_KP_MKIN5         MFP_CFG(GPIO10, AF1)
+#define GPIO11_KP_MKOUT5        MFP_CFG(GPIO11, AF1)
+#define GPIO12_KP_MKIN6         MFP_CFG(GPIO12, AF1)
+#define GPIO13_KP_MKOUT6        MFP_CFG(GPIO13, AF1)
+#define GPIO14_KP_MKIN7         MFP_CFG(GPIO14, AF1)
+#define GPIO15_KP_MKOUT7        MFP_CFG(GPIO15, AF1)
+#define GPIO16_KP_DKIN0         MFP_CFG(GPIO16, AF1)
+#define GPIO17_KP_DKIN1         MFP_CFG(GPIO17, AF1)
+#define GPIO18_KP_DKIN2         MFP_CFG(GPIO18, AF1)
+#define GPIO19_KP_DKIN3         MFP_CFG(GPIO19, AF1)
+
+/* LCD */
+#define GPIO81_LCD_FCLK         MFP_CFG(GPIO81, AF1)
+#define GPIO82_LCD_LCLK         MFP_CFG(GPIO82, AF1)
+#define GPIO83_LCD_PCLK         MFP_CFG(GPIO83, AF1)
+#define GPIO84_LCD_DENA         MFP_CFG(GPIO84, AF1)
+#define GPIO85_LCD_DD0          MFP_CFG(GPIO85, AF1)
+#define GPIO86_LCD_DD1          MFP_CFG(GPIO86, AF1)
+#define GPIO87_LCD_DD2          MFP_CFG(GPIO87, AF1)
+#define GPIO88_LCD_DD3          MFP_CFG(GPIO88, AF1)
+#define GPIO89_LCD_DD4          MFP_CFG(GPIO89, AF1)
+#define GPIO90_LCD_DD5          MFP_CFG(GPIO90, AF1)
+#define GPIO91_LCD_DD6          MFP_CFG(GPIO91, AF1)
+#define GPIO92_LCD_DD7          MFP_CFG(GPIO92, AF1)
+#define GPIO93_LCD_DD8          MFP_CFG(GPIO93, AF1)
+#define GPIO94_LCD_DD9          MFP_CFG(GPIO94, AF1)
+#define GPIO95_LCD_DD10         MFP_CFG(GPIO95, AF1)
+#define GPIO96_LCD_DD11         MFP_CFG(GPIO96, AF1)
+#define GPIO97_LCD_DD12         MFP_CFG(GPIO97, AF1)
+#define GPIO98_LCD_DD13         MFP_CFG(GPIO98, AF1)
+#define GPIO100_LCD_DD14        MFP_CFG(GPIO100, AF1)
+#define GPIO101_LCD_DD15        MFP_CFG(GPIO101, AF1)
+#define GPIO102_LCD_DD16        MFP_CFG(GPIO102, AF1)
+#define GPIO103_LCD_DD17        MFP_CFG(GPIO103, AF1)
+#define GPIO104_LCD_DD18        MFP_CFG(GPIO104, AF1)
+#define GPIO105_LCD_DD19        MFP_CFG(GPIO105, AF1)
+#define GPIO106_LCD_DD20        MFP_CFG(GPIO106, AF1)
+#define GPIO107_LCD_DD21        MFP_CFG(GPIO107, AF1)
+#define GPIO108_LCD_DD22        MFP_CFG(GPIO108, AF1)
+#define GPIO109_LCD_DD23        MFP_CFG(GPIO109, AF1)
+
+#define GPIO104_LCD_SPIDOUT     MFP_CFG(GPIO104, AF3)
+#define GPIO105_LCD_SPIDIN      MFP_CFG(GPIO105, AF3)
+#define GPIO107_LCD_CS1         MFP_CFG(GPIO107, AF3)
+#define GPIO108_LCD_DCLK        MFP_CFG(GPIO108, AF3)
+
+#define GPIO106_LCD_RESET       MFP_CFG(GPIO106, AF0)
+
+/*smart panel*/
+#define GPIO82_LCD_A0           MFP_CFG(GPIO82, AF0)
+#define GPIO83_LCD_WR           MFP_CFG(GPIO83, AF0)
+#define GPIO103_LCD_CS          MFP_CFG(GPIO103, AF0)
+
+/*1wire*/
+#define GPIO106_1WIRE           MFP_CFG(GPIO106, AF3)
+
+/*CCIC*/
+#define GPIO67_CCIC_IN7         MFP_CFG_DRV(GPIO67, AF1, MEDIUM)
+#define GPIO68_CCIC_IN6         MFP_CFG_DRV(GPIO68, AF1, MEDIUM)
+#define GPIO69_CCIC_IN5         MFP_CFG_DRV(GPIO69, AF1, MEDIUM)
+#define GPIO70_CCIC_IN4         MFP_CFG_DRV(GPIO70, AF1, MEDIUM)
+#define GPIO71_CCIC_IN3         MFP_CFG_DRV(GPIO71, AF1, MEDIUM)
+#define GPIO72_CCIC_IN2         MFP_CFG_DRV(GPIO72, AF1, MEDIUM)
+#define GPIO73_CCIC_IN1         MFP_CFG_DRV(GPIO73, AF1, MEDIUM)
+#define GPIO74_CCIC_IN0         MFP_CFG_DRV(GPIO74, AF1, MEDIUM)
+#define GPIO75_CAM_HSYNC        MFP_CFG_DRV(GPIO75, AF1, MEDIUM)
+#define GPIO76_CAM_VSYNC        MFP_CFG_DRV(GPIO76, AF1, MEDIUM)
+#define GPIO77_CAM_MCLK         MFP_CFG_DRV(GPIO77, AF1, MEDIUM)
+#define GPIO78_CAM_PCLK         MFP_CFG_DRV(GPIO78, AF1, MEDIUM)
+
+/* MMC1 */
+#define MMC1_DAT7_MMC1_DAT7     MFP_CFG_DRV(MMC1_DAT7, AF0, MEDIUM)
+#define MMC1_DAT6_MMC1_DAT6     MFP_CFG_DRV(MMC1_DAT6, AF0, MEDIUM)
+#define MMC1_DAT5_MMC1_DAT5     MFP_CFG_DRV(MMC1_DAT5, AF0, MEDIUM)
+#define MMC1_DAT4_MMC1_DAT4     MFP_CFG_DRV(MMC1_DAT4, AF0, MEDIUM)
+#define MMC1_DAT3_MMC1_DAT3     MFP_CFG_DRV(MMC1_DAT3, AF0, MEDIUM)
+#define MMC1_DAT2_MMC1_DAT2     MFP_CFG_DRV(MMC1_DAT2, AF0, MEDIUM)
+#define MMC1_DAT1_MMC1_DAT1     MFP_CFG_DRV(MMC1_DAT1, AF0, MEDIUM)
+#define MMC1_DAT0_MMC1_DAT0     MFP_CFG_DRV(MMC1_DAT0, AF0, MEDIUM)
+#define MMC1_CMD_MMC1_CMD       MFP_CFG_DRV(MMC1_CMD, AF0, MEDIUM)
+#define MMC1_CLK_MMC1_CLK       MFP_CFG_DRV(MMC1_CLK, AF0, MEDIUM)
+#define MMC1_CD_MMC1_CD         MFP_CFG_DRV(MMC1_CD, AF0, MEDIUM)
+#define MMC1_WP_MMC1_WP         MFP_CFG_DRV(MMC1_WP, AF0, MEDIUM)
+
+#endif /* __ASM_MACH MFP_PXA910_H */
diff --git a/arch/arm/mach-mmp/include/mach/mfp.h b/arch/arm/mach-mmp/include/mach/mfp.h
new file mode 100644
index 000000000000..277ea4cd0f9f
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/mfp.h
@@ -0,0 +1,37 @@
+#ifndef __ASM_MACH_MFP_H
+#define __ASM_MACH_MFP_H
+
+#include <plat/mfp.h>
+
+/*
+ * NOTE: the MFPR register bit definitions on PXA168 processor lines are a
+ * bit different from those on PXA3xx.  Bit [7:10] are now reserved, which
+ * were SLEEP_OE_N, SLEEP_DATA, SLEEP_SEL and the LSB of DRIVE bits.
+ *
+ * To cope with this difference and re-use the pxa3xx mfp code as much as
+ * possible, we make the following compromise:
+ *
+ * 1. SLEEP_OE_N will always be programmed to '1' (by MFP_LPM_FLOAT)
+ * 2. DRIVE strength definitions redefined to include the reserved bit10
+ * 3. Override MFP_CFG() and MFP_CFG_DRV()
+ * 4. Drop the use of MFP_CFG_LPM() and MFP_CFG_X()
+ */
+
+#define MFP_DRIVE_VERY_SLOW     (0x0 << 13)
+#define MFP_DRIVE_SLOW          (0x2 << 13)
+#define MFP_DRIVE_MEDIUM        (0x4 << 13)
+#define MFP_DRIVE_FAST          (0x8 << 13)
+
+#undef MFP_CFG
+#undef MFP_CFG_DRV
+#undef MFP_CFG_LPM
+#undef MFP_CFG_X
+#undef MFP_CFG_DEFAULT
+
+#define MFP_CFG(pin, af)                \
+        (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM)
+
+#define MFP_CFG_DRV(pin, af, drv)       \
+        (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv)
+
+#endif /* __ASM_MACH_MFP_H */
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
new file mode 100644
index 000000000000..ef0a8a2076e9
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -0,0 +1,23 @@
+#ifndef __ASM_MACH_PXA168_H
+#define __ASM_MACH_PXA168_H
+
+#include <mach/devices.h>
+
+extern struct pxa_device_desc pxa168_device_uart1;
+extern struct pxa_device_desc pxa168_device_uart2;
+
+static inline int pxa168_add_uart(int id)
+{
+        struct pxa_device_desc *d = NULL;
+
+        switch (id) {
+        case 1: d = &pxa168_device_uart1; break;
+        case 2: d = &pxa168_device_uart2; break;
+        }
+
+        if (d == NULL)
+                return -EINVAL;
+
+        return pxa_register_device(d, NULL, 0);
+}
+#endif /* __ASM_MACH_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
new file mode 100644
index 000000000000..b7aeaf574c36
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/pxa910.h
@@ -0,0 +1,23 @@
+#ifndef __ASM_MACH_PXA910_H
+#define __ASM_MACH_PXA910_H
+
+#include <mach/devices.h>
+
+extern struct pxa_device_desc pxa910_device_uart1;
+extern struct pxa_device_desc pxa910_device_uart2;
+
+static inline int pxa910_add_uart(int id)
+{
+        struct pxa_device_desc *d = NULL;
+
+        switch (id) {
+        case 1: d = &pxa910_device_uart1; break;
+        case 2: d = &pxa910_device_uart2; break;
+        }
+
+        if (d == NULL)
+                return -EINVAL;
+
+        return pxa_register_device(d, NULL, 0);
+}
+#endif /* __ASM_MACH_PXA910_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h
new file mode 100644
index 000000000000..c6b8c9dc2026
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h
@@ -0,0 +1,78 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/regs-apbc.h
+ *
+ *   Application Peripheral Bus Clock Unit
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_REGS_APBC_H
+#define __ASM_MACH_REGS_APBC_H
+
+#include <mach/addr-map.h>
+
+#define APBC_VIRT_BASE  (APB_VIRT_BASE + 0x015000)
+#define APBC_REG(x)     (APBC_VIRT_BASE + (x))
+
+/*
+ * APB clock register offsets for PXA168
+ */
+#define APBC_PXA168_UART1       APBC_REG(0x000)
+#define APBC_PXA168_UART2       APBC_REG(0x004)
+#define APBC_PXA168_GPIO        APBC_REG(0x008)
+#define APBC_PXA168_PWM0        APBC_REG(0x00c)
+#define APBC_PXA168_PWM1        APBC_REG(0x010)
+#define APBC_PXA168_SSP1        APBC_REG(0x01c)
+#define APBC_PXA168_SSP2        APBC_REG(0x020)
+#define APBC_PXA168_RTC         APBC_REG(0x028)
+#define APBC_PXA168_TWSI0       APBC_REG(0x02c)
+#define APBC_PXA168_KPC         APBC_REG(0x030)
+#define APBC_PXA168_TIMERS      APBC_REG(0x034)
+#define APBC_PXA168_AIB         APBC_REG(0x03c)
+#define APBC_PXA168_SW_JTAG     APBC_REG(0x040)
+#define APBC_PXA168_ONEWIRE     APBC_REG(0x048)
+#define APBC_PXA168_SSP3        APBC_REG(0x04c)
+#define APBC_PXA168_ASFAR       APBC_REG(0x050)
+#define APBC_PXA168_ASSAR       APBC_REG(0x054)
+#define APBC_PXA168_SSP4        APBC_REG(0x058)
+#define APBC_PXA168_SSP5        APBC_REG(0x05c)
+#define APBC_PXA168_TWSI1       APBC_REG(0x06c)
+#define APBC_PXA168_UART3       APBC_REG(0x070)
+#define APBC_PXA168_AC97        APBC_REG(0x084)
+
+/*
+ * APB Clock register offsets for PXA910
+ */
+#define APBC_PXA910_UART0       APBC_REG(0x000)
+#define APBC_PXA910_UART1       APBC_REG(0x004)
+#define APBC_PXA910_GPIO        APBC_REG(0x008)
+#define APBC_PXA910_PWM0        APBC_REG(0x00c)
+#define APBC_PXA910_PWM1        APBC_REG(0x010)
+#define APBC_PXA910_PWM2        APBC_REG(0x014)
+#define APBC_PXA910_PWM3        APBC_REG(0x018)
+#define APBC_PXA910_SSP1        APBC_REG(0x01c)
+#define APBC_PXA910_SSP2        APBC_REG(0x020)
+#define APBC_PXA910_IPC         APBC_REG(0x024)
+#define APBC_PXA910_TWSI0       APBC_REG(0x02c)
+#define APBC_PXA910_KPC         APBC_REG(0x030)
+#define APBC_PXA910_TIMERS      APBC_REG(0x034)
+#define APBC_PXA910_TBROT       APBC_REG(0x038)
+#define APBC_PXA910_AIB         APBC_REG(0x03c)
+#define APBC_PXA910_SW_JTAG     APBC_REG(0x040)
+#define APBC_PXA910_TIMERS1     APBC_REG(0x044)
+#define APBC_PXA910_ONEWIRE     APBC_REG(0x048)
+#define APBC_PXA910_SSP3        APBC_REG(0x04c)
+#define APBC_PXA910_ASFAR       APBC_REG(0x050)
+#define APBC_PXA910_ASSAR       APBC_REG(0x054)
+
+/* Common APB clock register bit definitions */
+#define APBC_APBCLK     (1 << 0)  /* APB Bus Clock Enable */
+#define APBC_FNCLK      (1 << 1)  /* Functional Clock Enable */
+#define APBC_RST        (1 << 2)  /* Reset Generation */
+
+/* Functional Clock Selection Mask */
+#define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
+
+#endif /* __ASM_MACH_REGS_APBC_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h
new file mode 100644
index 000000000000..919030514120
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -0,0 +1,36 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/regs-apmu.h
+ *
+ *   Application Subsystem Power Management Unit
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_REGS_APMU_H
+#define __ASM_MACH_REGS_APMU_H
+
+#include <mach/addr-map.h>
+
+#define APMU_VIRT_BASE  (AXI_VIRT_BASE + 0x82800)
+#define APMU_REG(x)     (APMU_VIRT_BASE + (x))
+
+/* Clock Reset Control */
+#define APMU_IRE        APMU_REG(0x048)
+#define APMU_LCD        APMU_REG(0x04c)
+#define APMU_CCIC       APMU_REG(0x050)
+#define APMU_SDH0       APMU_REG(0x054)
+#define APMU_SDH1       APMU_REG(0x058)
+#define APMU_USB        APMU_REG(0x05c)
+#define APMU_NAND       APMU_REG(0x060)
+#define APMU_DMA        APMU_REG(0x064)
+#define APMU_GEU        APMU_REG(0x068)
+#define APMU_BUS        APMU_REG(0x06c)
+
+#define APMU_FNCLK_EN   (1 << 4)
+#define APMU_AXICLK_EN  (1 << 3)
+#define APMU_FNRST_DIS  (1 << 1)
+#define APMU_AXIRST_DIS (1 << 0)
+
+#endif /* __ASM_MACH_REGS_APMU_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-icu.h b/arch/arm/mach-mmp/include/mach/regs-icu.h
new file mode 100644
index 000000000000..e5f08723e0cc
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/regs-icu.h
@@ -0,0 +1,31 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/regs-icu.h
+ *
+ *   Interrupt Control Unit
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_ICU_H
+#define __ASM_MACH_ICU_H
+
+#include <mach/addr-map.h>
+
+#define ICU_VIRT_BASE   (AXI_VIRT_BASE + 0x82000)
+#define ICU_REG(x)      (ICU_VIRT_BASE + (x))
+
+#define ICU_INT_CONF(n)         ICU_REG((n) << 2)
+#define ICU_INT_CONF_AP_INT     (1 << 6)
+#define ICU_INT_CONF_CP_INT     (1 << 5)
+#define ICU_INT_CONF_IRQ        (1 << 4)
+#define ICU_INT_CONF_MASK       (0xf)
+
+#define ICU_AP_FIQ_SEL_INT_NUM  ICU_REG(0x108)  /* AP FIQ Selected Interrupt */
+#define ICU_AP_IRQ_SEL_INT_NUM  ICU_REG(0x10C)  /* AP IRQ Selected Interrupt */
+#define ICU_AP_GBL_IRQ_MSK      ICU_REG(0x114)  /* AP Global Interrupt Mask */
+#define ICU_INT_STATUS_0        ICU_REG(0x128)  /* Interrupt Stuats 0 */
+#define ICU_INT_STATUS_1        ICU_REG(0x12C)  /* Interrupt Status 1 */
+
+#endif /* __ASM_MACH_ICU_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-timers.h b/arch/arm/mach-mmp/include/mach/regs-timers.h
new file mode 100644
index 000000000000..45589fec9fc7
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/regs-timers.h
@@ -0,0 +1,44 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/regs-timers.h
+ *
+ *   Timers Module
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_REGS_TIMERS_H
+#define __ASM_MACH_REGS_TIMERS_H
+
+#include <mach/addr-map.h>
+
+#define TIMERS1_VIRT_BASE       (APB_VIRT_BASE + 0x14000)
+#define TIMERS2_VIRT_BASE       (APB_VIRT_BASE + 0x16000)
+
+#define TMR_CCR         (0x0000)
+#define TMR_TN_MM(n, m) (0x0004 + ((n) << 3) + (((n) + (m)) << 2))
+#define TMR_CR(n)       (0x0028 + ((n) << 2))
+#define TMR_SR(n)       (0x0034 + ((n) << 2))
+#define TMR_IER(n)      (0x0040 + ((n) << 2))
+#define TMR_PLVR(n)     (0x004c + ((n) << 2))
+#define TMR_PLCR(n)     (0x0058 + ((n) << 2))
+#define TMR_WMER        (0x0064)
+#define TMR_WMR         (0x0068)
+#define TMR_WVR         (0x006c)
+#define TMR_WSR         (0x0070)
+#define TMR_ICR(n)      (0x0074 + ((n) << 2))
+#define TMR_WICR        (0x0080)
+#define TMR_CER         (0x0084)
+#define TMR_CMR         (0x0088)
+#define TMR_ILR(n)      (0x008c + ((n) << 2))
+#define TMR_WCR         (0x0098)
+#define TMR_WFAR        (0x009c)
+#define TMR_WSAR        (0x00A0)
+#define TMR_CVWR(n)     (0x00A4 + ((n) << 2))
+
+#define TMR_CCR_CS_0(x) (((x) & 0x3) << 0)
+#define TMR_CCR_CS_1(x) (((x) & 0x7) << 2)
+#define TMR_CCR_CS_2(x) (((x) & 0x3) << 5)
+
+#endif /* __ASM_MACH_REGS_TIMERS_H */
diff --git a/arch/arm/mach-mmp/include/mach/system.h b/arch/arm/mach-mmp/include/mach/system.h
new file mode 100644
index 000000000000..001edfefec19
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/system.h
@@ -0,0 +1,21 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/system.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_SYSTEM_H
+#define __ASM_MACH_SYSTEM_H
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        cpu_reset(0);
+}
+#endif /* __ASM_MACH_SYSTEM_H */
diff --git a/arch/arm/mach-mmp/include/mach/timex.h b/arch/arm/mach-mmp/include/mach/timex.h
new file mode 100644
index 000000000000..6cebbd0ca8f4
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/timex.h
@@ -0,0 +1,9 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/timex.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define CLOCK_TICK_RATE         3250000
diff --git a/arch/arm/mach-mmp/include/mach/uncompress.h b/arch/arm/mach-mmp/include/mach/uncompress.h
new file mode 100644
index 000000000000..c93d5fa5865c
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/uncompress.h
@@ -0,0 +1,41 @@
+/*
+ * arch/arm/mach-mmp/include/mach/uncompress.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/serial_reg.h>
+#include <mach/addr-map.h>
+
+#define UART1_BASE      (APB_PHYS_BASE + 0x36000)
+#define UART2_BASE      (APB_PHYS_BASE + 0x17000)
+#define UART3_BASE      (APB_PHYS_BASE + 0x18000)
+
+static inline void putc(char c)
+{
+        volatile unsigned long *UART = (unsigned long *)UART2_BASE;
+
+        /* UART enabled? */
+        if (!(UART[UART_IER] & UART_IER_UUE))
+                return;
+
+        while (!(UART[UART_LSR] & UART_LSR_THRE))
+                barrier();
+
+        UART[UART_TX] = c;
+}
+
+/*
+ * This does not append a newline
+ */
+static inline void flush(void)
+{
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-mmp/include/mach/vmalloc.h b/arch/arm/mach-mmp/include/mach/vmalloc.h
new file mode 100644
index 000000000000..b60ccaf9fee7
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/vmalloc.h
+ */
+
+#define VMALLOC_END     0xfe000000
diff --git a/arch/arm/mach-mmp/irq.c b/arch/arm/mach-mmp/irq.c
new file mode 100644
index 000000000000..52ff2f065eba
--- /dev/null
+++ b/arch/arm/mach-mmp/irq.c
@@ -0,0 +1,55 @@
+/*
+ *  linux/arch/arm/mach-mmp/irq.c
+ *
+ *  Generic IRQ handling, GPIO IRQ demultiplexing, etc.
+ *
+ *  Author:     Bin Yang <bin.yang@marvell.com>
+ *  Created:    Sep 30, 2008
+ *  Copyright:  Marvell International Ltd.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+
+#include <mach/regs-icu.h>
+
+#include "common.h"
+
+#define IRQ_ROUTE_TO_AP         (ICU_INT_CONF_AP_INT | ICU_INT_CONF_IRQ)
+
+#define PRIORITY_DEFAULT        0x1
+#define PRIORITY_NONE           0x0     /* means IRQ disabled */
+
+static void icu_mask_irq(unsigned int irq)
+{
+        __raw_writel(PRIORITY_NONE, ICU_INT_CONF(irq));
+}
+
+static void icu_unmask_irq(unsigned int irq)
+{
+        __raw_writel(IRQ_ROUTE_TO_AP | PRIORITY_DEFAULT, ICU_INT_CONF(irq));
+}
+
+static struct irq_chip icu_irq_chip = {
+        .name   = "icu_irq",
+        .ack    = icu_mask_irq,
+        .mask   = icu_mask_irq,
+        .unmask = icu_unmask_irq,
+};
+
+void __init icu_init_irq(void)
+{
+        int irq;
+
+        for (irq = 0; irq < 64; irq++) {
+                icu_mask_irq(irq);
+                set_irq_chip(irq, &icu_irq_chip);
+                set_irq_handler(irq, handle_level_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+}
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
new file mode 100644
index 000000000000..ae924468658c
--- /dev/null
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -0,0 +1,111 @@
+/*
+ *  linux/arch/arm/mach-mmp/pxa168.c
+ *
+ *  Code specific to PXA168
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+
+#include <asm/mach/time.h>
+#include <mach/addr-map.h>
+#include <mach/cputype.h>
+#include <mach/regs-apbc.h>
+#include <mach/irqs.h>
+#include <mach/gpio.h>
+#include <mach/dma.h>
+#include <mach/devices.h>
+#include <mach/mfp.h>
+
+#include "common.h"
+#include "clock.h"
+
+#define MFPR_VIRT_BASE  (APB_VIRT_BASE + 0x1e000)
+
+static struct mfp_addr_map pxa168_mfp_addr_map[] __initdata =
+{
+        MFP_ADDR_X(GPIO0,   GPIO36,  0x04c),
+        MFP_ADDR_X(GPIO37,  GPIO55,  0x000),
+        MFP_ADDR_X(GPIO56,  GPIO123, 0x0e0),
+        MFP_ADDR_X(GPIO124, GPIO127, 0x0f4),
+
+        MFP_ADDR_END,
+};
+
+#define APMASK(i)       (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c)
+
+static void __init pxa168_init_gpio(void)
+{
+        int i;
+
+        /* enable GPIO clock */
+        __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA168_GPIO);
+
+        /* unmask GPIO edge detection for all 4 banks - APMASKx */
+        for (i = 0; i < 4; i++)
+                __raw_writel(0xffffffff, APMASK(i));
+
+        pxa_init_gpio(IRQ_PXA168_GPIOX, 0, 127, NULL);
+}
+
+void __init pxa168_init_irq(void)
+{
+        icu_init_irq();
+        pxa168_init_gpio();
+}
+
+/* APB peripheral clocks */
+static APBC_CLK(uart1, PXA168_UART1, 1, 14745600);
+static APBC_CLK(uart2, PXA168_UART2, 1, 14745600);
+
+/* device and clock bindings */
+static struct clk_lookup pxa168_clkregs[] = {
+        INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
+        INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
+};
+
+static int __init pxa168_init(void)
+{
+        if (cpu_is_pxa168()) {
+                mfp_init_base(MFPR_VIRT_BASE);
+                mfp_init_addr(pxa168_mfp_addr_map);
+                pxa_init_dma(IRQ_PXA168_DMA_INT0, 32);
+                clks_register(ARRAY_AND_SIZE(pxa168_clkregs));
+        }
+
+        return 0;
+}
+postcore_initcall(pxa168_init);
+
+/* system timer - clock enabled, 3.25MHz */
+#define TIMER_CLK_RST   (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
+
+static void __init pxa168_timer_init(void)
+{
+        /* this is early, we have to initialize the CCU registers by
+         * ourselves instead of using clk_* API. Clock rate is defined
+         * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running
+         */
+        __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS);
+
+        /* 3.25MHz, bus/functional clock enabled, release reset */
+        __raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS);
+
+        timer_init(IRQ_PXA168_TIMER1);
+}
+
+struct sys_timer pxa168_timer = {
+        .init   = pxa168_timer_init,
+};
+
+/* on-chip devices */
+PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22);
+PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24);
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
new file mode 100644
index 000000000000..453f8f7758bf
--- /dev/null
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -0,0 +1,158 @@
+/*
+ *  linux/arch/arm/mach-mmp/pxa910.c
+ *
+ *  Code specific to PXA910
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/io.h>
+
+#include <asm/mach/time.h>
+#include <mach/addr-map.h>
+#include <mach/regs-apbc.h>
+#include <mach/regs-apmu.h>
+#include <mach/cputype.h>
+#include <mach/irqs.h>
+#include <mach/gpio.h>
+#include <mach/dma.h>
+#include <mach/mfp.h>
+#include <mach/devices.h>
+
+#include "common.h"
+#include "clock.h"
+
+#define MFPR_VIRT_BASE  (APB_VIRT_BASE + 0x1e000)
+
+static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata =
+{
+        MFP_ADDR_X(GPIO0, GPIO54, 0xdc),
+        MFP_ADDR_X(GPIO67, GPIO98, 0x1b8),
+        MFP_ADDR_X(GPIO100, GPIO109, 0x238),
+
+        MFP_ADDR(GPIO123, 0xcc),
+        MFP_ADDR(GPIO124, 0xd0),
+
+        MFP_ADDR(DF_IO0, 0x40),
+        MFP_ADDR(DF_IO1, 0x3c),
+        MFP_ADDR(DF_IO2, 0x38),
+        MFP_ADDR(DF_IO3, 0x34),
+        MFP_ADDR(DF_IO4, 0x30),
+        MFP_ADDR(DF_IO5, 0x2c),
+        MFP_ADDR(DF_IO6, 0x28),
+        MFP_ADDR(DF_IO7, 0x24),
+        MFP_ADDR(DF_IO8, 0x20),
+        MFP_ADDR(DF_IO9, 0x1c),
+        MFP_ADDR(DF_IO10, 0x18),
+        MFP_ADDR(DF_IO11, 0x14),
+        MFP_ADDR(DF_IO12, 0x10),
+        MFP_ADDR(DF_IO13, 0xc),
+        MFP_ADDR(DF_IO14, 0x8),
+        MFP_ADDR(DF_IO15, 0x4),
+
+        MFP_ADDR(DF_nCS0_SM_nCS2, 0x44),
+        MFP_ADDR(DF_nCS1_SM_nCS3, 0x48),
+        MFP_ADDR(SM_nCS0, 0x4c),
+        MFP_ADDR(SM_nCS1, 0x50),
+        MFP_ADDR(DF_WEn, 0x54),
+        MFP_ADDR(DF_REn, 0x58),
+        MFP_ADDR(DF_CLE_SM_OEn, 0x5c),
+        MFP_ADDR(DF_ALE_SM_WEn, 0x60),
+        MFP_ADDR(SM_SCLK, 0x64),
+        MFP_ADDR(DF_RDY0, 0x68),
+        MFP_ADDR(SM_BE0, 0x6c),
+        MFP_ADDR(SM_BE1, 0x70),
+        MFP_ADDR(SM_ADV, 0x74),
+        MFP_ADDR(DF_RDY1, 0x78),
+        MFP_ADDR(SM_ADVMUX, 0x7c),
+        MFP_ADDR(SM_RDY, 0x80),
+
+        MFP_ADDR_X(MMC1_DAT7, MMC1_WP, 0x84),
+
+        MFP_ADDR_END,
+};
+
+#define APMASK(i)       (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c)
+
+static void __init pxa910_init_gpio(void)
+{
+        int i;
+
+        /* enable GPIO clock */
+        __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA910_GPIO);
+
+        /* unmask GPIO edge detection for all 4 banks - APMASKx */
+        for (i = 0; i < 4; i++)
+                __raw_writel(0xffffffff, APMASK(i));
+
+        pxa_init_gpio(IRQ_PXA910_AP_GPIO, 0, 127, NULL);
+}
+
+void __init pxa910_init_irq(void)
+{
+        icu_init_irq();
+        pxa910_init_gpio();
+}
+
+/* APB peripheral clocks */
+static APBC_CLK(uart1, PXA910_UART0, 1, 14745600);
+static APBC_CLK(uart2, PXA910_UART1, 1, 14745600);
+
+/* device and clock bindings */
+static struct clk_lookup pxa910_clkregs[] = {
+        INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
+        INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
+};
+
+static int __init pxa910_init(void)
+{
+        if (cpu_is_pxa910()) {
+                mfp_init_base(MFPR_VIRT_BASE);
+                mfp_init_addr(pxa910_mfp_addr_map);
+                pxa_init_dma(IRQ_PXA910_DMA_INT0, 32);
+                clks_register(ARRAY_AND_SIZE(pxa910_clkregs));
+        }
+
+        return 0;
+}
+postcore_initcall(pxa910_init);
+
+/* system timer - clock enabled, 3.25MHz */
+#define TIMER_CLK_RST   (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
+
+static void __init pxa910_timer_init(void)
+{
+        /* reset and configure */
+        __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA910_TIMERS);
+        __raw_writel(TIMER_CLK_RST, APBC_PXA910_TIMERS);
+
+        timer_init(IRQ_PXA910_AP1_TIMER1);
+}
+
+struct sys_timer pxa910_timer = {
+        .init   = pxa910_timer_init,
+};
+
+/* on-chip devices */
+
+/* NOTE: there are totally 3 UARTs on PXA910:
+ *
+ *   UART1   - Slow UART (can be used both by AP and CP)
+ *   UART2/3 - Fast UART
+ *
+ * To be backward compatible with the legacy FFUART/BTUART/STUART sequence,
+ * they are re-ordered as:
+ *
+ *   pxa910_device_uart1 - UART2 as FFUART
+ *   pxa910_device_uart2 - UART3 as BTUART
+ *
+ * UART1 is not used by AP for the moment.
+ */
+PXA910_DEVICE(uart1, "pxa2xx-uart", 0, UART2, 0xd4017000, 0x30, 21, 22);
+PXA910_DEVICE(uart2, "pxa2xx-uart", 1, UART3, 0xd4018000, 0x30, 23, 24);
diff --git a/arch/arm/mach-mmp/tavorevb.c b/arch/arm/mach-mmp/tavorevb.c
new file mode 100644
index 000000000000..0e0c9220eaba
--- /dev/null
+++ b/arch/arm/mach-mmp/tavorevb.c
@@ -0,0 +1,109 @@
+/*
+ *  linux/arch/arm/mach-mmp/tavorevb.c
+ *
+ *  Support for the Marvell PXA910-based TavorEVB Development Platform.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/smc91x.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/addr-map.h>
+#include <mach/mfp-pxa910.h>
+#include <mach/pxa910.h>
+#include <mach/gpio.h>
+
+#include "common.h"
+
+static unsigned long tavorevb_pin_config[] __initdata = {
+        /* UART2 */
+        GPIO47_UART2_RXD,
+        GPIO48_UART2_TXD,
+
+        /* SMC */
+        SM_nCS0_nCS0,
+        SM_ADV_SM_ADV,
+        SM_SCLK_SM_SCLK,
+        SM_SCLK_SM_SCLK,
+        SM_BE0_SM_BE0,
+        SM_BE1_SM_BE1,
+
+        /* DFI */
+        DF_IO0_ND_IO0,
+        DF_IO1_ND_IO1,
+        DF_IO2_ND_IO2,
+        DF_IO3_ND_IO3,
+        DF_IO4_ND_IO4,
+        DF_IO5_ND_IO5,
+        DF_IO6_ND_IO6,
+        DF_IO7_ND_IO7,
+        DF_IO8_ND_IO8,
+        DF_IO9_ND_IO9,
+        DF_IO10_ND_IO10,
+        DF_IO11_ND_IO11,
+        DF_IO12_ND_IO12,
+        DF_IO13_ND_IO13,
+        DF_IO14_ND_IO14,
+        DF_IO15_ND_IO15,
+        DF_nCS0_SM_nCS2_nCS0,
+        DF_ALE_SM_WEn_ND_ALE,
+        DF_CLE_SM_OEn_ND_CLE,
+        DF_WEn_DF_WEn,
+        DF_REn_DF_REn,
+        DF_RDY0_DF_RDY0,
+};
+
+static struct smc91x_platdata tavorevb_smc91x_info = {
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
+};
+
+static struct resource smc91x_resources[] = {
+        [0] = {
+                .start  = SMC_CS1_PHYS_BASE + 0x300,
+                .end    = SMC_CS1_PHYS_BASE + 0xfffff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gpio_to_irq(80),
+                .end    = gpio_to_irq(80),
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+        }
+};
+
+static struct platform_device smc91x_device = {
+        .name           = "smc91x",
+        .id             = 0,
+        .dev            = {
+                .platform_data = &tavorevb_smc91x_info,
+        },
+        .num_resources  = ARRAY_SIZE(smc91x_resources),
+        .resource       = smc91x_resources,
+};
+
+static void __init tavorevb_init(void)
+{
+        mfp_config(ARRAY_AND_SIZE(tavorevb_pin_config));
+
+        /* on-chip devices */
+        pxa910_add_uart(1);
+
+        /* off-chip devices */
+        platform_device_register(&smc91x_device);
+}
+
+MACHINE_START(TAVOREVB, "PXA910 Evaluation Board (aka TavorEVB)")
+        .phys_io        = APB_PHYS_BASE,
+        .boot_params    = 0x00000100,
+        .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa910_init_irq,
+        .timer          = &pxa910_timer,
+        .init_machine   = tavorevb_init,
+MACHINE_END
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
new file mode 100644
index 000000000000..b03a6eda7419
--- /dev/null
+++ b/arch/arm/mach-mmp/time.c
@@ -0,0 +1,199 @@
+/*
+ * linux/arch/arm/mach-mmp/time.c
+ *
+ *   Support for clocksource and clockevents
+ *
+ * Copyright (C) 2008 Marvell International Ltd.
+ * All rights reserved.
+ *
+ *   2008-04-11: Jason Chagas <Jason.chagas@marvell.com>
+ *   2008-10-08: Bin Yang <bin.yang@marvell.com>
+ *
+ * The timers module actually includes three timers, each timer with upto
+ * three match comparators. Timer #0 is used here in free-running mode as
+ * the clock source, and match comparator #1 used as clock event device.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/clockchips.h>
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/sched.h>
+#include <linux/cnt32_to_63.h>
+
+#include <mach/addr-map.h>
+#include <mach/regs-timers.h>
+#include <mach/irqs.h>
+
+#include "clock.h"
+
+#define TIMERS_VIRT_BASE        TIMERS1_VIRT_BASE
+
+#define MAX_DELTA               (0xfffffffe)
+#define MIN_DELTA               (16)
+
+#define TCR2NS_SCALE_FACTOR     10
+
+static unsigned long tcr2ns_scale;
+
+static void __init set_tcr2ns_scale(unsigned long tcr_rate)
+{
+        unsigned long long v = 1000000000ULL << TCR2NS_SCALE_FACTOR;
+        do_div(v, tcr_rate);
+        tcr2ns_scale = v;
+        /*
+         * We want an even value to automatically clear the top bit
+         * returned by cnt32_to_63() without an additional run time
+         * instruction. So if the LSB is 1 then round it up.
+         */
+        if (tcr2ns_scale & 1)
+                tcr2ns_scale++;
+}
+
+/*
+ * FIXME: the timer needs some delay to stablize the counter capture
+ */
+static inline uint32_t timer_read(void)
+{
+        int delay = 100;
+
+        __raw_writel(1, TIMERS_VIRT_BASE + TMR_CVWR(0));
+
+        while (delay--)
+                cpu_relax();
+
+        return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(0));
+}
+
+unsigned long long sched_clock(void)
+{
+        unsigned long long v = cnt32_to_63(timer_read());
+        return (v * tcr2ns_scale) >> TCR2NS_SCALE_FACTOR;
+}
+
+static irqreturn_t timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *c = dev_id;
+
+        /* disable and clear pending interrupt status */
+        __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0));
+        __raw_writel(0x1, TIMERS_VIRT_BASE + TMR_ICR(0));
+        c->event_handler(c);
+        return IRQ_HANDLED;
+}
+
+static int timer_set_next_event(unsigned long delta,
+                                struct clock_event_device *dev)
+{
+        unsigned long flags, next;
+
+        local_irq_save(flags);
+
+        /* clear pending interrupt status and enable */
+        __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
+        __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_IER(0));
+
+        next = timer_read() + delta;
+        __raw_writel(next, TIMERS_VIRT_BASE + TMR_TN_MM(0, 0));
+
+        local_irq_restore(flags);
+        return 0;
+}
+
+static void timer_set_mode(enum clock_event_mode mode,
+                           struct clock_event_device *dev)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        switch (mode) {
+        case CLOCK_EVT_MODE_ONESHOT:
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+                /* disable the matching interrupt */
+                __raw_writel(0x00, TIMERS_VIRT_BASE + TMR_IER(0));
+                break;
+        case CLOCK_EVT_MODE_RESUME:
+        case CLOCK_EVT_MODE_PERIODIC:
+                break;
+        }
+        local_irq_restore(flags);
+}
+
+static struct clock_event_device ckevt = {
+        .name           = "clockevent",
+        .features       = CLOCK_EVT_FEAT_ONESHOT,
+        .shift          = 32,
+        .rating         = 200,
+        .set_next_event = timer_set_next_event,
+        .set_mode       = timer_set_mode,
+};
+
+static cycle_t clksrc_read(void)
+{
+        return timer_read();
+}
+
+static struct clocksource cksrc = {
+        .name           = "clocksource",
+        .shift          = 20,
+        .rating         = 200,
+        .read           = clksrc_read,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void __init timer_config(void)
+{
+        uint32_t ccr = __raw_readl(TIMERS_VIRT_BASE + TMR_CCR);
+        uint32_t cer = __raw_readl(TIMERS_VIRT_BASE + TMR_CER);
+        uint32_t cmr = __raw_readl(TIMERS_VIRT_BASE + TMR_CMR);
+
+        __raw_writel(cer & ~0x1, TIMERS_VIRT_BASE + TMR_CER); /* disable */
+
+        ccr &= TMR_CCR_CS_0(0x3);
+        __raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR);
+
+        /* free-running mode */
+        __raw_writel(cmr | 0x01, TIMERS_VIRT_BASE + TMR_CMR);
+
+        __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(0)); /* free-running */
+        __raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(0));  /* clear status */
+        __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0));
+
+        /* enable timer counter */
+        __raw_writel(cer | 0x01, TIMERS_VIRT_BASE + TMR_CER);
+}
+
+static struct irqaction timer_irq = {
+        .name           = "timer",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = timer_interrupt,
+        .dev_id         = &ckevt,
+};
+
+void __init timer_init(int irq)
+{
+        timer_config();
+
+        set_tcr2ns_scale(CLOCK_TICK_RATE);
+
+        ckevt.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt.shift);
+        ckevt.max_delta_ns = clockevent_delta2ns(MAX_DELTA, &ckevt);
+        ckevt.min_delta_ns = clockevent_delta2ns(MIN_DELTA, &ckevt);
+        ckevt.cpumask = cpumask_of(0);
+
+        cksrc.mult = clocksource_hz2mult(CLOCK_TICK_RATE, cksrc.shift);
+
+        setup_irq(irq, &timer_irq);
+
+        clocksource_register(&cksrc);
+        clockevents_register_device(&ckevt);
+}
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
new file mode 100644
index 000000000000..08cfef6c92a2
--- /dev/null
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -0,0 +1,47 @@
+/*
+ *  linux/arch/arm/mach-mmp/ttc_dkb.c
+ *
+ *  Support for the Marvell PXA910-based TTC_DKB Development Platform.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/addr-map.h>
+#include <mach/mfp-pxa910.h>
+#include <mach/pxa910.h>
+
+#include "common.h"
+
+#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
+
+static unsigned long ttc_dkb_pin_config[] __initdata = {
+        /* UART2 */
+        GPIO47_UART2_RXD,
+        GPIO48_UART2_TXD,
+};
+
+static void __init ttc_dkb_init(void)
+{
+        mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config));
+
+        /* on-chip devices */
+        pxa910_add_uart(1);
+}
+
+MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform")
+        .phys_io        = APB_PHYS_BASE,
+        .boot_params    = 0x00000100,
+        .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa910_init_irq,
+        .timer          = &pxa910_timer,
+        .init_machine   = ttc_dkb_init,
+MACHINE_END
diff --git a/arch/arm/mach-msm/include/mach/system.h b/arch/arm/mach-msm/include/mach/system.h
index f05ad2e0f235..574ccc493daf 100644
--- a/arch/arm/mach-msm/include/mach/system.h
+++ b/arch/arm/mach-msm/include/mach/system.h
@@ -17,7 +17,7 @@
 
 void arch_idle(void);
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         for (;;) ;  /* depends on IPC w/ other core */
 }
diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig
index d83cb86837db..6fbe68fe4412 100644
--- a/arch/arm/mach-mv78xx0/Kconfig
+++ b/arch/arm/mach-mv78xx0/Kconfig
@@ -8,6 +8,12 @@ config MACH_DB78X00_BP
           Say 'Y' here if you want your kernel to support the
           Marvell DB-78x00-BP Development Board.
 
+config MACH_RD78X00_MASA
+        bool "Marvell RD-78x00-mASA Reference Design"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell RD-78x00-mASA Reference Design.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile
index ec16c05c3b1b..da628b7f3bb6 100644
--- a/arch/arm/mach-mv78xx0/Makefile
+++ b/arch/arm/mach-mv78xx0/Makefile
@@ -1,2 +1,3 @@
 obj-y                           += common.o addr-map.o irq.o pcie.o
 obj-$(CONFIG_MACH_DB78X00_BP)   += db78x00-bp-setup.o
+obj-$(CONFIG_MACH_RD78X00_MASA) += rd78x00-masa-setup.o
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index b0e4e0d8f506..a575daaa62d1 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -14,7 +14,9 @@
 #include <linux/serial_8250.h>
 #include <linux/mbus.h>
 #include <linux/mv643xx_eth.h>
+#include <linux/mv643xx_i2c.h>
 #include <linux/ata_platform.h>
+#include <linux/ethtool.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <mach/mv78xx0.h>
@@ -430,9 +432,22 @@ static struct platform_device mv78xx0_ge10 = {
 
 void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
 {
+        u32 dev, rev;
+
         eth_data->shared = &mv78xx0_ge10_shared;
         mv78xx0_ge10.dev.platform_data = eth_data;
 
+        /*
+         * On the Z0, ge10 and ge11 are internally connected back
+         * to back, and not brought out.
+         */
+        mv78xx0_pcie_id(&dev, &rev);
+        if (dev == MV78X00_Z0_DEV_ID) {
+                eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
+                eth_data->speed = SPEED_1000;
+                eth_data->duplex = DUPLEX_FULL;
+        }
+
         platform_device_register(&mv78xx0_ge10_shared);
         platform_device_register(&mv78xx0_ge10);
 }
@@ -484,13 +499,101 @@ static struct platform_device mv78xx0_ge11 = {
 
 void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
 {
+        u32 dev, rev;
+
         eth_data->shared = &mv78xx0_ge11_shared;
         mv78xx0_ge11.dev.platform_data = eth_data;
 
+        /*
+         * On the Z0, ge10 and ge11 are internally connected back
+         * to back, and not brought out.
+         */
+        mv78xx0_pcie_id(&dev, &rev);
+        if (dev == MV78X00_Z0_DEV_ID) {
+                eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
+                eth_data->speed = SPEED_1000;
+                eth_data->duplex = DUPLEX_FULL;
+        }
+
         platform_device_register(&mv78xx0_ge11_shared);
         platform_device_register(&mv78xx0_ge11);
 }
 
+/*****************************************************************************
+ * I2C bus 0
+ ****************************************************************************/
+
+static struct mv64xxx_i2c_pdata mv78xx0_i2c_0_pdata = {
+        .freq_m         = 8, /* assumes 166 MHz TCLK */
+        .freq_n         = 3,
+        .timeout        = 1000, /* Default timeout of 1 second */
+};
+
+static struct resource mv78xx0_i2c_0_resources[] = {
+        {
+                .name   = "i2c 0 base",
+                .start  = I2C_0_PHYS_BASE,
+                .end    = I2C_0_PHYS_BASE + 0x1f,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "i2c 0 irq",
+                .start  = IRQ_MV78XX0_I2C_0,
+                .end    = IRQ_MV78XX0_I2C_0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+
+static struct platform_device mv78xx0_i2c_0 = {
+        .name           = MV64XXX_I2C_CTLR_NAME,
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(mv78xx0_i2c_0_resources),
+        .resource       = mv78xx0_i2c_0_resources,
+        .dev            = {
+                .platform_data  = &mv78xx0_i2c_0_pdata,
+        },
+};
+
+/*****************************************************************************
+ * I2C bus 1
+ ****************************************************************************/
+
+static struct mv64xxx_i2c_pdata mv78xx0_i2c_1_pdata = {
+        .freq_m         = 8, /* assumes 166 MHz TCLK */
+        .freq_n         = 3,
+        .timeout        = 1000, /* Default timeout of 1 second */
+};
+
+static struct resource mv78xx0_i2c_1_resources[] = {
+        {
+                .name   = "i2c 1 base",
+                .start  = I2C_1_PHYS_BASE,
+                .end    = I2C_1_PHYS_BASE + 0x1f,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "i2c 1 irq",
+                .start  = IRQ_MV78XX0_I2C_1,
+                .end    = IRQ_MV78XX0_I2C_1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+
+static struct platform_device mv78xx0_i2c_1 = {
+        .name           = MV64XXX_I2C_CTLR_NAME,
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(mv78xx0_i2c_1_resources),
+        .resource       = mv78xx0_i2c_1_resources,
+        .dev            = {
+                .platform_data  = &mv78xx0_i2c_1_pdata,
+        },
+};
+
+void __init mv78xx0_i2c_init(void)
+{
+        platform_device_register(&mv78xx0_i2c_0);
+        platform_device_register(&mv78xx0_i2c_1);
+}
 
 /*****************************************************************************
  * SATA
@@ -719,6 +822,32 @@ struct sys_timer mv78xx0_timer = {
 /*****************************************************************************
  * General
  ****************************************************************************/
+static char * __init mv78xx0_id(void)
+{
+        u32 dev, rev;
+
+        mv78xx0_pcie_id(&dev, &rev);
+
+        if (dev == MV78X00_Z0_DEV_ID) {
+                if (rev == MV78X00_REV_Z0)
+                        return "MV78X00-Z0";
+                else
+                        return "MV78X00-Rev-Unsupported";
+        } else if (dev == MV78100_DEV_ID) {
+                if (rev == MV78100_REV_A0)
+                        return "MV78100-A0";
+                else
+                        return "MV78100-Rev-Unsupported";
+        } else if (dev == MV78200_DEV_ID) {
+                if (rev == MV78100_REV_A0)
+                        return "MV78200-A0";
+                else
+                        return "MV78200-Rev-Unsupported";
+        } else {
+                return "Device-Unknown";
+        }
+}
+
 static int __init is_l2_writethrough(void)
 {
         return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
@@ -737,7 +866,8 @@ void __init mv78xx0_init(void)
         get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
         tclk = get_tclk();
 
-        printk(KERN_INFO "MV78xx0 core #%d, ", core_index);
+        printk(KERN_INFO "%s ", mv78xx0_id());
+        printk("core #%d, ", core_index);
         printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
         printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
         printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
index 78af5de319dd..befc22475469 100644
--- a/arch/arm/mach-mv78xx0/common.h
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -29,6 +29,8 @@ void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
 void mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
                                 int maj, int min);
 
+void mv78xx0_pcie_id(u32 *dev, u32 *rev);
+
 void mv78xx0_ehci0_init(void);
 void mv78xx0_ehci1_init(void);
 void mv78xx0_ehci2_init(void);
@@ -42,6 +44,7 @@ void mv78xx0_uart0_init(void);
 void mv78xx0_uart1_init(void);
 void mv78xx0_uart2_init(void);
 void mv78xx0_uart3_init(void);
+void mv78xx0_i2c_init(void);
 
 extern struct sys_timer mv78xx0_timer;
 
diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
index 2e285bbb7bbd..efdabe04c69e 100644
--- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
+++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
@@ -14,6 +14,7 @@
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/ethtool.h>
+#include <linux/i2c.h>
 #include <mach/mv78xx0.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -28,21 +29,22 @@ static struct mv643xx_eth_platform_data db78x00_ge01_data = {
 };
 
 static struct mv643xx_eth_platform_data db78x00_ge10_data = {
-        .phy_addr       = MV643XX_ETH_PHY_NONE,
-        .speed          = SPEED_1000,
-        .duplex         = DUPLEX_FULL,
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(10),
 };
 
 static struct mv643xx_eth_platform_data db78x00_ge11_data = {
-        .phy_addr       = MV643XX_ETH_PHY_NONE,
-        .speed          = SPEED_1000,
-        .duplex         = DUPLEX_FULL,
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(11),
 };
 
 static struct mv_sata_platform_data db78x00_sata_data = {
         .n_ports        = 2,
 };
 
+static struct i2c_board_info __initdata db78x00_i2c_rtc = {
+        I2C_BOARD_INFO("ds1338", 0x68),
+};
+
+
 static void __init db78x00_init(void)
 {
         /*
@@ -64,6 +66,8 @@ static void __init db78x00_init(void)
                 mv78xx0_sata_init(&db78x00_sata_data);
                 mv78xx0_uart0_init();
                 mv78xx0_uart2_init();
+                mv78xx0_i2c_init();
+                i2c_register_board_info(0, &db78x00_i2c_rtc, 1);
         } else {
                 mv78xx0_uart1_init();
                 mv78xx0_uart3_init();
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
index e930ea5330a2..582cffc733ad 100644
--- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -80,6 +80,18 @@
 #define  TIMER_VIRT_BASE        (BRIDGE_VIRT_BASE | 0x0300)
 
 /*
+ * Supported devices and revisions.
+ */
+#define MV78X00_Z0_DEV_ID       0x6381
+#define MV78X00_REV_Z0          1
+
+#define MV78100_DEV_ID          0x7810
+#define MV78100_REV_A0          1
+
+#define MV78200_DEV_ID          0x7820
+#define MV78200_REV_A0          1
+
+/*
  * Register Map
  */
 #define DDR_VIRT_BASE           (MV78XX0_REGS_VIRT_BASE | 0x00000)
@@ -90,6 +102,8 @@
 #define DEV_BUS_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x10000)
 #define  SAMPLE_AT_RESET_LOW    (DEV_BUS_VIRT_BASE | 0x0030)
 #define  SAMPLE_AT_RESET_HIGH   (DEV_BUS_VIRT_BASE | 0x0034)
+#define  I2C_0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x1000)
+#define  I2C_1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x1100)
 #define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
 #define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
 #define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
diff --git a/arch/arm/mach-mv78xx0/include/mach/system.h b/arch/arm/mach-mv78xx0/include/mach/system.h
index 7d5179408832..1d6350b22d0b 100644
--- a/arch/arm/mach-mv78xx0/include/mach/system.h
+++ b/arch/arm/mach-mv78xx0/include/mach/system.h
@@ -17,7 +17,7 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         /*
          * Enable soft reset to assert RSTOUTn.
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index aad3a7a2f830..a560439dcc3c 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -33,6 +33,12 @@ static struct resource pcie_io_space;
 static struct resource pcie_mem_space;
 
 
+void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
+{
+        *dev = orion_pcie_dev_id((void __iomem *)PCIE00_VIRT_BASE);
+        *rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE);
+}
+
 static void __init mv78xx0_pcie_preinit(void)
 {
         int i;
diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
new file mode 100644
index 000000000000..e136b7a03355
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
@@ -0,0 +1,88 @@
+/*
+ * arch/arm/mach-mv78x00/rd78x00-masa-setup.c
+ *
+ * Marvell RD-78x00-mASA Development Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ethtool.h>
+#include <mach/mv78xx0.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include "common.h"
+
+static struct mv643xx_eth_platform_data rd78x00_masa_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+
+static struct mv643xx_eth_platform_data rd78x00_masa_ge01_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(9),
+};
+
+static struct mv643xx_eth_platform_data rd78x00_masa_ge10_data = {
+};
+
+static struct mv643xx_eth_platform_data rd78x00_masa_ge11_data = {
+};
+
+static struct mv_sata_platform_data rd78x00_masa_sata_data = {
+        .n_ports        = 2,
+};
+
+static void __init rd78x00_masa_init(void)
+{
+        /*
+         * Basic MV78x00 setup. Needs to be called early.
+         */
+        mv78xx0_init();
+
+        /*
+         * Partition on-chip peripherals between the two CPU cores.
+         */
+        if (mv78xx0_core_index() == 0) {
+                mv78xx0_ehci0_init();
+                mv78xx0_ehci1_init();
+                mv78xx0_ge00_init(&rd78x00_masa_ge00_data);
+                mv78xx0_ge10_init(&rd78x00_masa_ge10_data);
+                mv78xx0_sata_init(&rd78x00_masa_sata_data);
+                mv78xx0_uart0_init();
+                mv78xx0_uart2_init();
+        } else {
+                mv78xx0_ehci2_init();
+                mv78xx0_ge01_init(&rd78x00_masa_ge01_data);
+                mv78xx0_ge11_init(&rd78x00_masa_ge11_data);
+                mv78xx0_uart1_init();
+                mv78xx0_uart3_init();
+        }
+}
+
+static int __init rd78x00_pci_init(void)
+{
+        /*
+         * Assign all PCIe devices to CPU core #0.
+         */
+        if (machine_is_rd78x00_masa() && mv78xx0_core_index() == 0)
+                mv78xx0_pcie_init(1, 1);
+
+        return 0;
+}
+subsys_initcall(rd78x00_pci_init);
+
+MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board")
+        /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
+        .phys_io        = MV78XX0_REGS_PHYS_BASE,
+        .io_pg_offst    = ((MV78XX0_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = rd78x00_masa_init,
+        .map_io         = mv78xx0_map_io,
+        .init_irq       = mv78xx0_init_irq,
+        .timer          = &mv78xx0_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx1/Kconfig b/arch/arm/mach-mx1/Kconfig
index 2b59fc74784f..eb7660f5d4b7 100644
--- a/arch/arm/mach-mx1/Kconfig
+++ b/arch/arm/mach-mx1/Kconfig
@@ -1,6 +1,6 @@
 if ARCH_MX1
 
-comment "MX1 Platforms"
+comment "MX1 platforms:"
 
 config MACH_MXLADS
         bool
@@ -11,4 +11,9 @@ config ARCH_MX1ADS
         help
           Say Y here if you are using Motorola MX1ADS/MXLADS boards
 
+config MACH_SCB9328
+        bool "Synertronixx scb9328"
+        help
+          Say Y here if you are using a Synertronixx scb9328 board
+
 endif
diff --git a/arch/arm/mach-mx1/Makefile b/arch/arm/mach-mx1/Makefile
index b969719011fa..82f1309568ef 100644
--- a/arch/arm/mach-mx1/Makefile
+++ b/arch/arm/mach-mx1/Makefile
@@ -8,3 +8,4 @@ obj-y			+= generic.o clock.o devices.o
 
 # Specific board support
 obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o
+obj-$(CONFIG_MACH_SCB9328) += scb9328.o
\ No newline at end of file
diff --git a/arch/arm/mach-mx1/clock.c b/arch/arm/mach-mx1/clock.c
index 4bcd1ece55f5..0d0f306851d0 100644
--- a/arch/arm/mach-mx1/clock.c
+++ b/arch/arm/mach-mx1/clock.c
@@ -25,6 +25,7 @@
 
 #include <mach/clock.h>
 #include <mach/hardware.h>
+#include <mach/common.h>
 #include "crm_regs.h"
 
 static int _clk_enable(struct clk *clk)
@@ -87,33 +88,6 @@ static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
         return clk->parent->set_rate(clk->parent, rate);
 }
 
-/*
- *  get the system pll clock in Hz
- *
- *                  mfi + mfn / (mfd +1)
- *  f = 2 * f_ref * --------------------
- *                        pd + 1
- */
-static unsigned long mx1_decode_pll(unsigned int pll, u32 f_ref)
-{
-        unsigned long long ll;
-        unsigned long quot;
-
-        u32 mfi = (pll >> 10) & 0xf;
-        u32 mfn = pll & 0x3ff;
-        u32 mfd = (pll >> 16) & 0x3ff;
-        u32 pd =  (pll >> 26) & 0xf;
-
-        mfi = mfi <= 5 ? 5 : mfi;
-
-        ll = 2 * (unsigned long long)f_ref *
-                ((mfi << 16) + (mfn << 16) / (mfd + 1));
-        quot = (pd + 1) * (1 << 16);
-        ll += quot / 2;
-        do_div(ll, quot);
-        return (unsigned long)ll;
-}
-
 static unsigned long clk16m_get_rate(struct clk *clk)
 {
         return 16000000;
@@ -188,7 +162,7 @@ static struct clk prem_clk = {
 
 static unsigned long system_clk_get_rate(struct clk *clk)
 {
-        return mx1_decode_pll(__raw_readl(CCM_SPCTL0),
+        return mxc_decode_pll(__raw_readl(CCM_SPCTL0),
                               clk_get_rate(clk->parent));
 }
 
@@ -200,7 +174,7 @@ static struct clk system_clk = {
 
 static unsigned long mcu_clk_get_rate(struct clk *clk)
 {
-        return mx1_decode_pll(__raw_readl(CCM_MPCTL0),
+        return mxc_decode_pll(__raw_readl(CCM_MPCTL0),
                               clk_get_rate(clk->parent));
 }
 
@@ -488,7 +462,7 @@ static struct clk clko_clk = {
 };
 
 static struct clk dma_clk = {
-        .name = "dma_clk",
+        .name = "dma",
         .parent = &hclk,
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
@@ -539,7 +513,7 @@ static struct clk gpt_clk = {
 };
 
 static struct clk uart_clk = {
-        .name = "uart_clk",
+        .name = "uart",
         .parent = &perclk[0],
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
@@ -621,7 +595,7 @@ static struct clk *mxc_clks[] = {
         &rtc_clk,
 };
 
-int __init mxc_clocks_init(unsigned long fref)
+int __init mx1_clocks_init(unsigned long fref)
 {
         struct clk **clkp;
         unsigned int reg;
@@ -652,5 +626,7 @@ int __init mxc_clocks_init(unsigned long fref)
         clk_enable(&hclk);
         clk_enable(&fclk);
 
+        mxc_timer_init(&gpt_clk);
+
         return 0;
 }
diff --git a/arch/arm/mach-mx1/devices.c b/arch/arm/mach-mx1/devices.c
index a95644193f3f..97f42d96d7a1 100644
--- a/arch/arm/mach-mx1/devices.c
+++ b/arch/arm/mach-mx1/devices.c
@@ -23,10 +23,11 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
-
 #include <mach/irqs.h>
 #include <mach/hardware.h>
 
+#include "devices.h"
+
 static struct resource imx_csi_resources[] = {
         [0] = {
                 .start  = 0x00224000,
diff --git a/arch/arm/mach-mx1/mx1ads.c b/arch/arm/mach-mx1/mx1ads.c
index 3200cf60e384..7ae229bc1b79 100644
--- a/arch/arm/mach-mx1/mx1ads.c
+++ b/arch/arm/mach-mx1/mx1ads.c
@@ -16,6 +16,8 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
+#include <linux/i2c.h>
+#include <linux/i2c/pcf857x.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -25,7 +27,11 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/imx-uart.h>
-#include <mach/iomux-mx1-mx2.h>
+#include <mach/irqs.h>
+#ifdef CONFIG_I2C_IMX
+#include <mach/i2c.h>
+#endif
+#include <mach/iomux.h>
 #include "devices.h"
 
 /*
@@ -105,6 +111,55 @@ static struct platform_device flash_device = {
 };
 
 /*
+ * I2C
+ */
+
+#ifdef CONFIG_I2C_IMX
+static int i2c_pins[] = {
+        PA15_PF_I2C_SDA,
+        PA16_PF_I2C_SCL,
+};
+
+static int i2c_init(struct device *dev)
+{
+        return mxc_gpio_setup_multiple_pins(i2c_pins,
+                        ARRAY_SIZE(i2c_pins), "I2C");
+}
+
+static void i2c_exit(struct device *dev)
+{
+        mxc_gpio_release_multiple_pins(i2c_pins,
+                        ARRAY_SIZE(i2c_pins));
+}
+
+static struct pcf857x_platform_data pcf857x_data[] = {
+        {
+                .gpio_base = 4 * 32,
+        }, {
+                .gpio_base = 4 * 32 + 16,
+        }
+};
+
+static struct imxi2c_platform_data mx1ads_i2c_data = {
+        .bitrate = 100000,
+        .init = i2c_init,
+        .exit = i2c_exit,
+};
+
+static struct i2c_board_info mx1ads_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("pcf857x", 0x22),
+                .type = "pcf8575",
+                .platform_data = &pcf857x_data[0],
+        }, {
+                I2C_BOARD_INFO("pcf857x", 0x24),
+                .type = "pcf8575",
+                .platform_data = &pcf857x_data[1],
+        },
+};
+#endif
+
+/*
  * Board init
  */
 static void __init mx1ads_init(void)
@@ -115,12 +170,19 @@ static void __init mx1ads_init(void)
 
         /* Physmap flash */
         mxc_register_device(&flash_device, &mx1ads_flash_data);
+
+        /* I2C */
+#ifdef CONFIG_I2C_IMX
+        i2c_register_board_info(0, mx1ads_i2c_devices,
+                                ARRAY_SIZE(mx1ads_i2c_devices));
+
+        mxc_register_device(&imx_i2c_device, &mx1ads_i2c_data);
+#endif
 }
 
 static void __init mx1ads_timer_init(void)
 {
-        mxc_clocks_init(32000);
-        mxc_timer_init("gpt_clk");
+        mx1_clocks_init(32000);
 }
 
 struct sys_timer mx1ads_timer = {
diff --git a/arch/arm/mach-mx1/scb9328.c b/arch/arm/mach-mx1/scb9328.c
new file mode 100644
index 000000000000..0e71f3fa28bf
--- /dev/null
+++ b/arch/arm/mach-mx1/scb9328.c
@@ -0,0 +1,160 @@
+/*
+ * linux/arch/arm/mach-mx1/scb9328.c
+ *
+ * Copyright (c) 2004 Sascha Hauer <saschahauer@web.de>
+ * Copyright (c) 2006-2008 Juergen Beisert <jbeisert@netscape.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/interrupt.h>
+#include <linux/dm9000.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux.h>
+
+#include "devices.h"
+
+/*
+ * This scb9328 has a 32MiB flash
+ */
+static struct resource flash_resource = {
+        .start  = IMX_CS0_PHYS,
+        .end    = IMX_CS0_PHYS + (32 * 1024 * 1024) - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct physmap_flash_data scb_flash_data = {
+        .width  = 2,
+};
+
+static struct platform_device scb_flash_device = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev = {
+                .platform_data = &scb_flash_data,
+        },
+        .resource = &flash_resource,
+        .num_resources = 1,
+};
+
+/*
+ * scb9328 has a DM9000 network controller
+ * connected to CS5, with 16 bit data path
+ * and interrupt connected to GPIO 3
+ */
+
+/*
+ * internal datapath is fixed 16 bit
+ */
+static struct dm9000_plat_data dm9000_platdata = {
+        .flags  = DM9000_PLATF_16BITONLY,
+};
+
+/*
+ * the DM9000 drivers wants two defined address spaces
+ * to gain access to address latch registers and the data path.
+ */
+static struct resource dm9000x_resources[] = {
+        [0] = {
+                .name   = "address area",
+                .start  = IMX_CS5_PHYS,
+                .end    = IMX_CS5_PHYS + 1,
+                .flags  = IORESOURCE_MEM        /* address access */
+        },
+        [1] = {
+                .name   = "data area",
+                .start  = IMX_CS5_PHYS + 4,
+                .end    = IMX_CS5_PHYS + 5,
+                .flags  = IORESOURCE_MEM        /* data access */
+        },
+        [2] = {
+                .start  = IRQ_GPIOC(3),
+                .end    = IRQ_GPIOC(3),
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL
+        },
+};
+
+static struct platform_device dm9000x_device = {
+        .name           = "dm9000",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(dm9000x_resources),
+        .resource       = dm9000x_resources,
+        .dev            = {
+                .platform_data = &dm9000_platdata,
+        }
+};
+
+static int mxc_uart1_pins[] = {
+        PC9_PF_UART1_CTS,
+        PC10_PF_UART1_RTS,
+        PC11_PF_UART1_TXD,
+        PC12_PF_UART1_RXD,
+};
+
+static int uart1_mxc_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
+                        ARRAY_SIZE(mxc_uart1_pins), "UART1");
+}
+
+static int uart1_mxc_exit(struct platform_device *pdev)
+{
+        mxc_gpio_release_multiple_pins(mxc_uart1_pins,
+                        ARRAY_SIZE(mxc_uart1_pins));
+        return 0;
+}
+
+static struct imxuart_platform_data uart_pdata = {
+        .init = uart1_mxc_init,
+        .exit = uart1_mxc_exit,
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct platform_device *devices[] __initdata = {
+        &scb_flash_device,
+        &dm9000x_device,
+};
+
+/*
+ * scb9328_init - Init the CPU card itself
+ */
+static void __init scb9328_init(void)
+{
+        mxc_register_device(&imx_uart1_device, &uart_pdata);
+
+        printk(KERN_INFO"Scb9328: Adding devices\n");
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+static void __init scb9328_timer_init(void)
+{
+        mx1_clocks_init(32000);
+}
+
+static struct sys_timer scb9328_timer = {
+        .init   = scb9328_timer_init,
+};
+
+MACHINE_START(SCB9328, "Synertronixx scb9328")
+    /* Sascha Hauer */
+        .phys_io        = 0x00200000,
+        .io_pg_offst    = ((0xe0200000) >> 18) & 0xfffc,
+        .boot_params    = 0x08000100,
+        .map_io         = mxc_map_io,
+        .init_irq       = mxc_init_irq,
+        .timer          = &scb9328_timer,
+        .init_machine   = scb9328_init,
+MACHINE_END
diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig
index 1eaa97cb716d..42a788842f49 100644
--- a/arch/arm/mach-mx2/Kconfig
+++ b/arch/arm/mach-mx2/Kconfig
@@ -1,14 +1,22 @@
-comment "MX2 family CPU support"
-        depends on ARCH_MX2
+if ARCH_MX2
+
+choice
+        prompt "CPUs:"
+        default MACH_MX21
+
+config MACH_MX21
+        bool "i.MX21 support"
+        help
+          This enables support for Freescale's MX2 based i.MX21 processor.
 
 config MACH_MX27
         bool "i.MX27 support"
-        depends on ARCH_MX2
         help
           This enables support for Freescale's MX2 based i.MX27 processor.
 
-comment "MX2 Platforms"
-        depends on ARCH_MX2
+endchoice
+
+comment "MX2 platforms:"
 
 config MACH_MX27ADS
         bool "MX27ADS platform"
@@ -37,3 +45,5 @@ config MACH_PCM970_BASEBOARD
           PCM970 evaluation board.
 
 endchoice
+
+endif
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile
index 382d86080e86..950649a91540 100644
--- a/arch/arm/mach-mx2/Makefile
+++ b/arch/arm/mach-mx2/Makefile
@@ -4,7 +4,9 @@
 
 # Object file lists.
 
-obj-y   :=  system.o generic.o devices.o serial.o
+obj-y   :=  generic.o devices.o serial.o
+
+obj-$(CONFIG_MACH_MX21) += clock_imx21.o
 
 obj-$(CONFIG_MACH_MX27) += cpu_imx27.o
 obj-$(CONFIG_MACH_MX27) += clock_imx27.o
diff --git a/arch/arm/mach-mx2/Makefile.boot b/arch/arm/mach-mx2/Makefile.boot
index 696831dcd485..e867398a8fdb 100644
--- a/arch/arm/mach-mx2/Makefile.boot
+++ b/arch/arm/mach-mx2/Makefile.boot
@@ -1,3 +1,7 @@
-   zreladdr-y   := 0xA0008000
-params_phys-y   := 0xA0000100
-initrd_phys-y   := 0xA0800000
+zreladdr-$(CONFIG_MACH_MX21)    := 0xC0008000
+params_phys-$(CONFIG_MACH_MX21) := 0xC0000100
+initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000
+
+zreladdr-$(CONFIG_MACH_MX27)    := 0xA0008000
+params_phys-$(CONFIG_MACH_MX27) := 0xA0000100
+initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000
diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c
new file mode 100644
index 000000000000..2dee5c87614c
--- /dev/null
+++ b/arch/arm/mach-mx2/clock_imx21.c
@@ -0,0 +1,984 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+
+#include <mach/clock.h>
+#include <mach/common.h>
+#include <asm/clkdev.h>
+#include <asm/div64.h>
+
+#include "crm_regs.h"
+
+static int _clk_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 1 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+        return 0;
+}
+
+static void _clk_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(1 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+
+static int _clk_spll_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(CCM_CSCR);
+        reg |= CCM_CSCR_SPEN;
+        __raw_writel(reg, CCM_CSCR);
+
+        while ((__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF) == 0)
+                ;
+        return 0;
+}
+
+static void _clk_spll_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(CCM_CSCR);
+        reg &= ~CCM_CSCR_SPEN;
+        __raw_writel(reg, CCM_CSCR);
+}
+
+
+#define CSCR() (__raw_readl(CCM_CSCR))
+#define PCDR0() (__raw_readl(CCM_PCDR0))
+#define PCDR1() (__raw_readl(CCM_PCDR1))
+
+static unsigned long _clk_perclkx_round_rate(struct clk *clk,
+                                             unsigned long rate)
+{
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+        if (parent_rate % rate)
+                div++;
+
+        if (div > 64)
+                div = 64;
+
+        return parent_rate / div;
+}
+
+static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg;
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (clk->id < 0 || clk->id > 3)
+                return -EINVAL;
+
+        div = parent_rate / rate;
+        if (div > 64 || div < 1 || ((parent_rate / div) != rate))
+                return -EINVAL;
+        div--;
+
+        reg =
+            __raw_readl(CCM_PCDR1) & ~(CCM_PCDR1_PERDIV1_MASK <<
+                                       (clk->id << 3));
+        reg |= div << (clk->id << 3);
+        __raw_writel(reg, CCM_PCDR1);
+
+        return 0;
+}
+
+static unsigned long _clk_usb_recalc(struct clk *clk)
+{
+        unsigned long usb_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        usb_pdf = (CSCR() & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET;
+
+        return parent_rate / (usb_pdf + 1U);
+}
+
+static unsigned long _clk_ssix_recalc(struct clk *clk, unsigned long pdf)
+{
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        pdf = (pdf < 2) ? 124UL : pdf;  /* MX21 & MX27 TO1 */
+
+        return 2UL * parent_rate / pdf;
+}
+
+static unsigned long _clk_ssi1_recalc(struct clk *clk)
+{
+        return _clk_ssix_recalc(clk,
+                (PCDR0() & CCM_PCDR0_SSI1BAUDDIV_MASK)
+                >> CCM_PCDR0_SSI1BAUDDIV_OFFSET);
+}
+
+static unsigned long _clk_ssi2_recalc(struct clk *clk)
+{
+        return _clk_ssix_recalc(clk,
+                (PCDR0() & CCM_PCDR0_SSI2BAUDDIV_MASK) >>
+                CCM_PCDR0_SSI2BAUDDIV_OFFSET);
+}
+
+static unsigned long _clk_nfc_recalc(struct clk *clk)
+{
+        unsigned long nfc_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        nfc_pdf = (PCDR0() & CCM_PCDR0_NFCDIV_MASK)
+                >> CCM_PCDR0_NFCDIV_OFFSET;
+
+        return parent_rate / (nfc_pdf + 1);
+}
+
+static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate)
+{
+        return clk->parent->round_rate(clk->parent, rate);
+}
+
+static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
+{
+        return clk->parent->set_rate(clk->parent, rate);
+}
+
+static unsigned long external_high_reference; /* in Hz */
+
+static unsigned long get_high_reference_clock_rate(struct clk *clk)
+{
+        return external_high_reference;
+}
+
+/*
+ * the high frequency external clock reference
+ * Default case is 26MHz.
+ */
+static struct clk ckih_clk = {
+        .get_rate = get_high_reference_clock_rate,
+};
+
+static unsigned long external_low_reference; /* in Hz */
+
+static unsigned long get_low_reference_clock_rate(struct clk *clk)
+{
+        return external_low_reference;
+}
+
+/*
+ * the low frequency external clock reference
+ * Default case is 32.768kHz.
+ */
+static struct clk ckil_clk = {
+        .get_rate = get_low_reference_clock_rate,
+};
+
+
+static unsigned long _clk_fpm_recalc(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) * 512;
+}
+
+/* Output of frequency pre multiplier */
+static struct clk fpm_clk = {
+        .parent = &ckil_clk,
+        .get_rate = _clk_fpm_recalc,
+};
+
+static unsigned long get_mpll_clk(struct clk *clk)
+{
+        uint32_t reg;
+        unsigned long ref_clk;
+        unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
+        unsigned long long temp;
+
+        ref_clk = clk_get_rate(clk->parent);
+
+        reg = __raw_readl(CCM_MPCTL0);
+        pdf = (reg & CCM_MPCTL0_PD_MASK)  >> CCM_MPCTL0_PD_OFFSET;
+        mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET;
+        mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET;
+        mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET;
+
+        mfi = (mfi <= 5) ? 5 : mfi;
+        temp = 2LL * ref_clk * mfn;
+        do_div(temp, mfd + 1);
+        temp = 2LL * ref_clk * mfi + temp;
+        do_div(temp, pdf + 1);
+
+        return (unsigned long)temp;
+}
+
+static struct clk mpll_clk = {
+        .parent = &ckih_clk,
+        .get_rate = get_mpll_clk,
+};
+
+static unsigned long _clk_fclk_get_rate(struct clk *clk)
+{
+        unsigned long parent_rate;
+        u32 div;
+
+        div = (CSCR() & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET;
+        parent_rate = clk_get_rate(clk->parent);
+
+        return parent_rate / (div+1);
+}
+
+static struct clk fclk_clk = {
+        .parent = &mpll_clk,
+        .get_rate = _clk_fclk_get_rate
+};
+
+static unsigned long get_spll_clk(struct clk *clk)
+{
+        uint32_t reg;
+        unsigned long ref_clk;
+        unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
+        unsigned long long temp;
+
+        ref_clk = clk_get_rate(clk->parent);
+
+        reg = __raw_readl(CCM_SPCTL0);
+        pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET;
+        mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET;
+        mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET;
+        mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET;
+
+        mfi = (mfi <= 5) ? 5 : mfi;
+        temp = 2LL * ref_clk * mfn;
+        do_div(temp, mfd + 1);
+        temp = 2LL * ref_clk * mfi + temp;
+        do_div(temp, pdf + 1);
+
+        return (unsigned long)temp;
+}
+
+static struct clk spll_clk = {
+        .parent = &ckih_clk,
+        .get_rate = get_spll_clk,
+        .enable = _clk_spll_enable,
+        .disable = _clk_spll_disable,
+};
+
+static unsigned long get_hclk_clk(struct clk *clk)
+{
+        unsigned long rate;
+        unsigned long bclk_pdf;
+
+        bclk_pdf = (CSCR() & CCM_CSCR_BCLK_MASK)
+                >> CCM_CSCR_BCLK_OFFSET;
+
+        rate = clk_get_rate(clk->parent);
+        return rate / (bclk_pdf + 1);
+}
+
+static struct clk hclk_clk = {
+        .parent = &fclk_clk,
+        .get_rate = get_hclk_clk,
+};
+
+static unsigned long get_ipg_clk(struct clk *clk)
+{
+        unsigned long rate;
+        unsigned long ipg_pdf;
+
+        ipg_pdf = (CSCR() & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET;
+
+        rate = clk_get_rate(clk->parent);
+        return rate / (ipg_pdf + 1);
+}
+
+static struct clk ipg_clk = {
+        .parent = &hclk_clk,
+        .get_rate = get_ipg_clk,
+};
+
+static unsigned long _clk_perclkx_recalc(struct clk *clk)
+{
+        unsigned long perclk_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (clk->id < 0 || clk->id > 3)
+                return 0;
+
+        perclk_pdf = (PCDR1() >> (clk->id << 3)) & CCM_PCDR1_PERDIV1_MASK;
+
+        return parent_rate / (perclk_pdf + 1);
+}
+
+static struct clk per_clk[] = {
+        {
+                .id = 0,
+                .parent = &mpll_clk,
+                .get_rate = _clk_perclkx_recalc,
+        }, {
+                .id = 1,
+                .parent = &mpll_clk,
+                .get_rate = _clk_perclkx_recalc,
+        }, {
+                .id = 2,
+                .parent = &mpll_clk,
+                .round_rate = _clk_perclkx_round_rate,
+                .set_rate = _clk_perclkx_set_rate,
+                .get_rate = _clk_perclkx_recalc,
+                /* Enable/Disable done via lcd_clkc[1] */
+        }, {
+                .id = 3,
+                .parent = &mpll_clk,
+                .round_rate = _clk_perclkx_round_rate,
+                .set_rate = _clk_perclkx_set_rate,
+                .get_rate = _clk_perclkx_recalc,
+                /* Enable/Disable done via csi_clk[1] */
+        },
+};
+
+static struct clk uart_ipg_clk[];
+
+static struct clk uart_clk[] = {
+        {
+                .id = 0,
+                .parent = &per_clk[0],
+                .secondary = &uart_ipg_clk[0],
+        }, {
+                .id = 1,
+                .parent = &per_clk[0],
+                .secondary = &uart_ipg_clk[1],
+        }, {
+                .id = 2,
+                .parent = &per_clk[0],
+                .secondary = &uart_ipg_clk[2],
+        }, {
+                .id = 3,
+                .parent = &per_clk[0],
+                .secondary = &uart_ipg_clk[3],
+        },
+};
+
+static struct clk uart_ipg_clk[] = {
+        {
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_UART1_REG,
+                .enable_shift = CCM_PCCR_UART1_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_UART2_REG,
+                .enable_shift = CCM_PCCR_UART2_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .id = 2,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_UART3_REG,
+                .enable_shift = CCM_PCCR_UART3_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .id = 3,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_UART4_REG,
+                .enable_shift = CCM_PCCR_UART4_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk gpt_ipg_clk[];
+
+static struct clk gpt_clk[] = {
+        {
+                .id = 0,
+                .parent = &per_clk[0],
+                .secondary = &gpt_ipg_clk[0],
+        }, {
+                .id = 1,
+                .parent = &per_clk[0],
+                .secondary = &gpt_ipg_clk[1],
+        }, {
+                .id = 2,
+                .parent = &per_clk[0],
+                .secondary = &gpt_ipg_clk[2],
+        },
+};
+
+static struct clk gpt_ipg_clk[] = {
+        {
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_GPT1_REG,
+                .enable_shift = CCM_PCCR_GPT1_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_GPT2_REG,
+                .enable_shift = CCM_PCCR_GPT2_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .id = 2,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_GPT3_REG,
+                .enable_shift = CCM_PCCR_GPT3_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk pwm_clk[] = {
+        {
+                .parent = &per_clk[0],
+                .secondary = &pwm_clk[1],
+        }, {
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_PWM_REG,
+                .enable_shift = CCM_PCCR_PWM_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk sdhc_ipg_clk[];
+
+static struct clk sdhc_clk[] = {
+        {
+                .id = 0,
+                .parent = &per_clk[1],
+                .secondary = &sdhc_ipg_clk[0],
+        }, {
+                .id = 1,
+                .parent = &per_clk[1],
+                .secondary = &sdhc_ipg_clk[1],
+        },
+};
+
+static struct clk sdhc_ipg_clk[] = {
+        {
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_SDHC1_REG,
+                .enable_shift = CCM_PCCR_SDHC1_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_SDHC2_REG,
+                .enable_shift = CCM_PCCR_SDHC2_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk cspi_ipg_clk[];
+
+static struct clk cspi_clk[] = {
+        {
+                .id = 0,
+                .parent = &per_clk[1],
+                .secondary = &cspi_ipg_clk[0],
+        }, {
+                .id = 1,
+                .parent = &per_clk[1],
+                .secondary = &cspi_ipg_clk[1],
+        }, {
+                .id = 2,
+                .parent = &per_clk[1],
+                .secondary = &cspi_ipg_clk[2],
+        },
+};
+
+static struct clk cspi_ipg_clk[] = {
+        {
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_CSPI1_REG,
+                .enable_shift = CCM_PCCR_CSPI1_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_CSPI2_REG,
+                .enable_shift = CCM_PCCR_CSPI2_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .id = 3,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_CSPI3_REG,
+                .enable_shift = CCM_PCCR_CSPI3_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk lcdc_clk[] = {
+        {
+                .parent = &per_clk[2],
+                .secondary = &lcdc_clk[1],
+                .round_rate = _clk_parent_round_rate,
+                .set_rate = _clk_parent_set_rate,
+        }, {
+                .parent = &ipg_clk,
+                .secondary = &lcdc_clk[2],
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_LCDC_REG,
+                .enable_shift = CCM_PCCR_LCDC_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .parent = &hclk_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_HCLK_LCDC_REG,
+                .enable_shift = CCM_PCCR_HCLK_LCDC_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk csi_clk[] = {
+        {
+                .parent = &per_clk[3],
+                .secondary = &csi_clk[1],
+                .round_rate = _clk_parent_round_rate,
+                .set_rate = _clk_parent_set_rate,
+        }, {
+                .parent = &hclk_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_HCLK_CSI_REG,
+                .enable_shift = CCM_PCCR_HCLK_CSI_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk usb_clk[] = {
+        {
+                .parent = &spll_clk,
+                .get_rate = _clk_usb_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_USBOTG_REG,
+                .enable_shift = CCM_PCCR_USBOTG_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .parent = &hclk_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_HCLK_USBOTG_REG,
+                .enable_shift = CCM_PCCR_HCLK_USBOTG_OFFSET,
+                .disable = _clk_disable,
+        }
+};
+
+static struct clk ssi_ipg_clk[];
+
+static struct clk ssi_clk[] = {
+        {
+                .id = 0,
+                .parent = &mpll_clk,
+                .secondary = &ssi_ipg_clk[0],
+                .get_rate = _clk_ssi1_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_SSI1_BAUD_REG,
+                .enable_shift = CCM_PCCR_SSI1_BAUD_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .id = 1,
+                .parent = &mpll_clk,
+                .secondary = &ssi_ipg_clk[1],
+                .get_rate = _clk_ssi2_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_SSI2_BAUD_REG,
+                .enable_shift = CCM_PCCR_SSI2_BAUD_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk ssi_ipg_clk[] = {
+        {
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_SSI1_REG,
+                .enable_shift = CCM_PCCR_SSI1_IPG_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_SSI2_REG,
+                .enable_shift = CCM_PCCR_SSI2_IPG_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+
+static struct clk nfc_clk = {
+        .parent = &fclk_clk,
+        .get_rate = _clk_nfc_recalc,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR_NFC_REG,
+        .enable_shift = CCM_PCCR_NFC_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk dma_clk[] = {
+        {
+                .parent = &hclk_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_DMA_REG,
+                .enable_shift = CCM_PCCR_DMA_OFFSET,
+                .disable = _clk_disable,
+                .secondary = &dma_clk[1],
+        },  {
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_HCLK_DMA_REG,
+                .enable_shift = CCM_PCCR_HCLK_DMA_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk brom_clk = {
+        .parent = &hclk_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR_HCLK_BROM_REG,
+        .enable_shift = CCM_PCCR_HCLK_BROM_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk emma_clk[] = {
+        {
+                .parent = &hclk_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_EMMA_REG,
+                .enable_shift = CCM_PCCR_EMMA_OFFSET,
+                .disable = _clk_disable,
+                .secondary = &emma_clk[1],
+        }, {
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_HCLK_EMMA_REG,
+                .enable_shift = CCM_PCCR_HCLK_EMMA_OFFSET,
+                .disable = _clk_disable,
+        }
+};
+
+static struct clk slcdc_clk[] = {
+        {
+                .parent = &hclk_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_SLCDC_REG,
+                .enable_shift = CCM_PCCR_SLCDC_OFFSET,
+                .disable = _clk_disable,
+                .secondary = &slcdc_clk[1],
+        }, {
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR_HCLK_SLCDC_REG,
+                .enable_shift = CCM_PCCR_HCLK_SLCDC_OFFSET,
+                .disable = _clk_disable,
+        }
+};
+
+static struct clk wdog_clk = {
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR_WDT_REG,
+        .enable_shift = CCM_PCCR_WDT_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk gpio_clk = {
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR_GPIO_REG,
+        .enable_shift = CCM_PCCR_GPIO_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk i2c_clk = {
+        .id = 0,
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR_I2C1_REG,
+        .enable_shift = CCM_PCCR_I2C1_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk kpp_clk = {
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR_KPP_REG,
+        .enable_shift = CCM_PCCR_KPP_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk owire_clk = {
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR_OWIRE_REG,
+        .enable_shift = CCM_PCCR_OWIRE_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk rtc_clk = {
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR_RTC_REG,
+        .enable_shift = CCM_PCCR_RTC_OFFSET,
+        .disable = _clk_disable,
+};
+
+static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate)
+{
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+        div = parent_rate / rate;
+        if (parent_rate % rate)
+                div++;
+
+        if (div > 8)
+                div = 8;
+
+        return parent_rate / div;
+}
+
+static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg;
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+
+        if (div > 8 || div < 1 || ((parent_rate / div) != rate))
+                return -EINVAL;
+        div--;
+
+        reg = __raw_readl(CCM_PCDR0);
+
+        if (clk->parent == &usb_clk[0]) {
+                reg &= ~CCM_PCDR0_48MDIV_MASK;
+                reg |= div << CCM_PCDR0_48MDIV_OFFSET;
+        }
+        __raw_writel(reg, CCM_PCDR0);
+
+        return 0;
+}
+
+static unsigned long _clk_clko_recalc(struct clk *clk)
+{
+        u32 div = 0;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (clk->parent == &usb_clk[0]) /* 48M */
+                div = __raw_readl(CCM_PCDR0) & CCM_PCDR0_48MDIV_MASK
+                         >> CCM_PCDR0_48MDIV_OFFSET;
+        div++;
+
+        return parent_rate / div;
+}
+
+static struct clk clko_clk;
+
+static int _clk_clko_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 reg;
+
+        reg = __raw_readl(CCM_CCSR) & ~CCM_CCSR_CLKOSEL_MASK;
+
+        if (parent == &ckil_clk)
+                reg |= 0 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &fpm_clk)
+                reg |= 1 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &ckih_clk)
+                reg |= 2 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == mpll_clk.parent)
+                reg |= 3 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == spll_clk.parent)
+                reg |= 4 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &mpll_clk)
+                reg |= 5 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &spll_clk)
+                reg |= 6 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &fclk_clk)
+                reg |= 7 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &hclk_clk)
+                reg |= 8 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &ipg_clk)
+                reg |= 9 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &per_clk[0])
+                reg |= 0xA << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &per_clk[1])
+                reg |= 0xB << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &per_clk[2])
+                reg |= 0xC << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &per_clk[3])
+                reg |= 0xD << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &ssi_clk[0])
+                reg |= 0xE << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &ssi_clk[1])
+                reg |= 0xF << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &nfc_clk)
+                reg |= 0x10 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &usb_clk[0])
+                reg |= 0x14 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &clko_clk)
+                reg |= 0x15 << CCM_CCSR_CLKOSEL_OFFSET;
+        else
+                return -EINVAL;
+
+        __raw_writel(reg, CCM_CCSR);
+
+        return 0;
+}
+
+static struct clk clko_clk = {
+        .get_rate = _clk_clko_recalc,
+        .set_rate = _clk_clko_set_rate,
+        .round_rate = _clk_clko_round_rate,
+        .set_parent = _clk_clko_set_parent,
+};
+
+
+#define _REGISTER_CLOCK(d, n, c) \
+        { \
+                .dev_id = d, \
+                .con_id = n, \
+                .clk = &c, \
+        },
+static struct clk_lookup lookups[] __initdata = {
+/* It's unlikely that any driver wants one of them directly:
+        _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
+        _REGISTER_CLOCK(NULL, "ckil", ckil_clk)
+        _REGISTER_CLOCK(NULL, "fpm", fpm_clk)
+        _REGISTER_CLOCK(NULL, "mpll", mpll_clk)
+        _REGISTER_CLOCK(NULL, "spll", spll_clk)
+        _REGISTER_CLOCK(NULL, "fclk", fclk_clk)
+        _REGISTER_CLOCK(NULL, "hclk", hclk_clk)
+        _REGISTER_CLOCK(NULL, "ipg", ipg_clk)
+*/
+        _REGISTER_CLOCK(NULL, "perclk1", per_clk[0])
+        _REGISTER_CLOCK(NULL, "perclk2", per_clk[1])
+        _REGISTER_CLOCK(NULL, "perclk3", per_clk[2])
+        _REGISTER_CLOCK(NULL, "perclk4", per_clk[3])
+        _REGISTER_CLOCK(NULL, "clko", clko_clk)
+        _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0])
+        _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1])
+        _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[2])
+        _REGISTER_CLOCK("imx-uart.3", NULL, uart_clk[3])
+        _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[0])
+        _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[1])
+        _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[2])
+        _REGISTER_CLOCK(NULL, "pwm", pwm_clk[0])
+        _REGISTER_CLOCK(NULL, "sdhc1", sdhc_clk[0])
+        _REGISTER_CLOCK(NULL, "sdhc2", sdhc_clk[1])
+        _REGISTER_CLOCK(NULL, "cspi1", cspi_clk[0])
+        _REGISTER_CLOCK(NULL, "cspi2", cspi_clk[1])
+        _REGISTER_CLOCK(NULL, "cspi3", cspi_clk[2])
+        _REGISTER_CLOCK(NULL, "lcdc", lcdc_clk[0])
+        _REGISTER_CLOCK(NULL, "csi", csi_clk[0])
+        _REGISTER_CLOCK(NULL, "usb", usb_clk[0])
+        _REGISTER_CLOCK(NULL, "ssi1", ssi_clk[0])
+        _REGISTER_CLOCK(NULL, "ssi2", ssi_clk[1])
+        _REGISTER_CLOCK(NULL, "nfc", nfc_clk)
+        _REGISTER_CLOCK(NULL, "dma", dma_clk[0])
+        _REGISTER_CLOCK(NULL, "brom", brom_clk)
+        _REGISTER_CLOCK(NULL, "emma", emma_clk[0])
+        _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk[0])
+        _REGISTER_CLOCK(NULL, "wdog", wdog_clk)
+        _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
+        _REGISTER_CLOCK(NULL, "i2c", i2c_clk)
+        _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk)
+        _REGISTER_CLOCK(NULL, "owire", owire_clk)
+        _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
+};
+
+/*
+ * must be called very early to get information about the
+ * available clock rate when the timer framework starts
+ */
+int __init mx21_clocks_init(unsigned long lref, unsigned long href)
+{
+        int i;
+        u32 cscr;
+
+        external_low_reference = lref;
+        external_high_reference = href;
+
+        /* detect clock reference for both system PLL */
+        cscr = CSCR();
+        if (cscr & CCM_CSCR_MCU)
+                mpll_clk.parent = &ckih_clk;
+        else
+                mpll_clk.parent = &fpm_clk;
+
+        if (cscr & CCM_CSCR_SP)
+                spll_clk.parent = &ckih_clk;
+        else
+                spll_clk.parent = &fpm_clk;
+
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
+
+        /* Turn off all clock gates */
+        __raw_writel(0, CCM_PCCR0);
+        __raw_writel(CCM_PCCR_GPT1_MASK, CCM_PCCR1);
+
+        /* This turns of the serial PLL as well */
+        spll_clk.disable(&spll_clk);
+
+        /* This will propagate to all children and init all the clock rates. */
+        clk_enable(&per_clk[0]);
+        clk_enable(&gpio_clk);
+
+#ifdef CONFIG_DEBUG_LL_CONSOLE
+        clk_enable(&uart_clk[0]);
+#endif
+
+        mxc_timer_init(&gpt_clk[0]);
+        return 0;
+}
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c
index c69896d011a1..3f7280c490f0 100644
--- a/arch/arm/mach-mx2/clock_imx27.c
+++ b/arch/arm/mach-mx2/clock_imx27.c
@@ -1,6 +1,7 @@
 /*
  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -20,23 +21,60 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/module.h>
-#include <linux/spinlock.h>
 
-#include <mach/clock.h>
-#include <mach/common.h>
+#include <asm/clkdev.h>
 #include <asm/div64.h>
 
-#include "crm_regs.h"
-
-static struct clk ckil_clk;
-static struct clk mpll_clk;
-static struct clk mpll_main_clk[];
-static struct clk spll_clk;
-
-static int _clk_enable(struct clk *clk)
+#include <mach/clock.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+
+/* Register offsets */
+#define CCM_CSCR                (IO_ADDRESS(CCM_BASE_ADDR) + 0x0)
+#define CCM_MPCTL0              (IO_ADDRESS(CCM_BASE_ADDR) + 0x4)
+#define CCM_MPCTL1              (IO_ADDRESS(CCM_BASE_ADDR) + 0x8)
+#define CCM_SPCTL0              (IO_ADDRESS(CCM_BASE_ADDR) + 0xC)
+#define CCM_SPCTL1              (IO_ADDRESS(CCM_BASE_ADDR) + 0x10)
+#define CCM_OSC26MCTL           (IO_ADDRESS(CCM_BASE_ADDR) + 0x14)
+#define CCM_PCDR0               (IO_ADDRESS(CCM_BASE_ADDR) + 0x18)
+#define CCM_PCDR1               (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c)
+#define CCM_PCCR0               (IO_ADDRESS(CCM_BASE_ADDR) + 0x20)
+#define CCM_PCCR1               (IO_ADDRESS(CCM_BASE_ADDR) + 0x24)
+#define CCM_CCSR                (IO_ADDRESS(CCM_BASE_ADDR) + 0x28)
+#define CCM_PMCTL               (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c)
+#define CCM_PMCOUNT             (IO_ADDRESS(CCM_BASE_ADDR) + 0x30)
+#define CCM_WKGDCTL             (IO_ADDRESS(CCM_BASE_ADDR) + 0x34)
+
+#define CCM_CSCR_UPDATE_DIS     (1 << 31)
+#define CCM_CSCR_SSI2           (1 << 23)
+#define CCM_CSCR_SSI1           (1 << 22)
+#define CCM_CSCR_VPU            (1 << 21)
+#define CCM_CSCR_MSHC           (1 << 20)
+#define CCM_CSCR_SPLLRES        (1 << 19)
+#define CCM_CSCR_MPLLRES        (1 << 18)
+#define CCM_CSCR_SP             (1 << 17)
+#define CCM_CSCR_MCU            (1 << 16)
+#define CCM_CSCR_OSC26MDIV      (1 << 4)
+#define CCM_CSCR_OSC26M         (1 << 3)
+#define CCM_CSCR_FPM            (1 << 2)
+#define CCM_CSCR_SPEN           (1 << 1)
+#define CCM_CSCR_MPEN           (1 << 0)
+
+/* i.MX27 TO 2+ */
+#define CCM_CSCR_ARM_SRC        (1 << 15)
+
+#define CCM_SPCTL1_LF           (1 << 15)
+#define CCM_SPCTL1_BRMO         (1 << 6)
+
+static struct clk mpll_main1_clk, mpll_main2_clk;
+
+static int clk_pccr_enable(struct clk *clk)
 {
         unsigned long reg;
 
+        if (!clk->enable_reg)
+                return 0;
+
         reg = __raw_readl(clk->enable_reg);
         reg |= 1 << clk->enable_shift;
         __raw_writel(reg, clk->enable_reg);
@@ -44,16 +82,19 @@ static int _clk_enable(struct clk *clk)
         return 0;
 }
 
-static void _clk_disable(struct clk *clk)
+static void clk_pccr_disable(struct clk *clk)
 {
         unsigned long reg;
 
+        if (!clk->enable_reg)
+                return;
+
         reg = __raw_readl(clk->enable_reg);
         reg &= ~(1 << clk->enable_shift);
         __raw_writel(reg, clk->enable_reg);
 }
 
-static int _clk_spll_enable(struct clk *clk)
+static int clk_spll_enable(struct clk *clk)
 {
         unsigned long reg;
 
@@ -61,13 +102,12 @@ static int _clk_spll_enable(struct clk *clk)
         reg |= CCM_CSCR_SPEN;
         __raw_writel(reg, CCM_CSCR);
 
-        while ((__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF) == 0)
-                ;
+        while (!(__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF));
 
         return 0;
 }
 
-static void _clk_spll_disable(struct clk *clk)
+static void clk_spll_disable(struct clk *clk)
 {
         unsigned long reg;
 
@@ -76,192 +116,30 @@ static void _clk_spll_disable(struct clk *clk)
         __raw_writel(reg, CCM_CSCR);
 }
 
-static void _clk_pccr01_enable(unsigned long mask0, unsigned long mask1)
-{
-        unsigned long reg;
-
-        reg = __raw_readl(CCM_PCCR0);
-        reg |= mask0;
-        __raw_writel(reg, CCM_PCCR0);
-
-        reg = __raw_readl(CCM_PCCR1);
-        reg |= mask1;
-        __raw_writel(reg, CCM_PCCR1);
-
-}
-
-static void _clk_pccr01_disable(unsigned long mask0, unsigned long mask1)
-{
-        unsigned long reg;
-
-        reg = __raw_readl(CCM_PCCR0);
-        reg &= ~mask0;
-        __raw_writel(reg, CCM_PCCR0);
-
-        reg = __raw_readl(CCM_PCCR1);
-        reg &= ~mask1;
-        __raw_writel(reg, CCM_PCCR1);
-}
-
-static void _clk_pccr10_enable(unsigned long mask1, unsigned long mask0)
-{
-        unsigned long reg;
-
-        reg = __raw_readl(CCM_PCCR1);
-        reg |= mask1;
-        __raw_writel(reg, CCM_PCCR1);
-
-        reg = __raw_readl(CCM_PCCR0);
-        reg |= mask0;
-        __raw_writel(reg, CCM_PCCR0);
-}
-
-static void _clk_pccr10_disable(unsigned long mask1, unsigned long mask0)
-{
-        unsigned long reg;
-
-        reg = __raw_readl(CCM_PCCR1);
-        reg &= ~mask1;
-        __raw_writel(reg, CCM_PCCR1);
-
-        reg = __raw_readl(CCM_PCCR0);
-        reg &= ~mask0;
-        __raw_writel(reg, CCM_PCCR0);
-}
-
-static int _clk_dma_enable(struct clk *clk)
-{
-        _clk_pccr01_enable(CCM_PCCR0_DMA_MASK, CCM_PCCR1_HCLK_DMA_MASK);
-
-        return 0;
-}
-
-static void _clk_dma_disable(struct clk *clk)
-{
-        _clk_pccr01_disable(CCM_PCCR0_DMA_MASK, CCM_PCCR1_HCLK_DMA_MASK);
-}
-
-static int _clk_rtic_enable(struct clk *clk)
-{
-        _clk_pccr01_enable(CCM_PCCR0_RTIC_MASK, CCM_PCCR1_HCLK_RTIC_MASK);
-
-        return 0;
-}
-
-static void _clk_rtic_disable(struct clk *clk)
-{
-        _clk_pccr01_disable(CCM_PCCR0_RTIC_MASK, CCM_PCCR1_HCLK_RTIC_MASK);
-}
-
-static int _clk_emma_enable(struct clk *clk)
-{
-        _clk_pccr01_enable(CCM_PCCR0_EMMA_MASK, CCM_PCCR1_HCLK_EMMA_MASK);
-
-        return 0;
-}
-
-static void _clk_emma_disable(struct clk *clk)
-{
-        _clk_pccr01_disable(CCM_PCCR0_EMMA_MASK, CCM_PCCR1_HCLK_EMMA_MASK);
-}
-
-static int _clk_slcdc_enable(struct clk *clk)
-{
-        _clk_pccr01_enable(CCM_PCCR0_SLCDC_MASK, CCM_PCCR1_HCLK_SLCDC_MASK);
-
-        return 0;
-}
-
-static void _clk_slcdc_disable(struct clk *clk)
-{
-        _clk_pccr01_disable(CCM_PCCR0_SLCDC_MASK, CCM_PCCR1_HCLK_SLCDC_MASK);
-}
-
-static int _clk_fec_enable(struct clk *clk)
-{
-        _clk_pccr01_enable(CCM_PCCR0_FEC_MASK, CCM_PCCR1_HCLK_FEC_MASK);
-
-        return 0;
-}
-
-static void _clk_fec_disable(struct clk *clk)
-{
-        _clk_pccr01_disable(CCM_PCCR0_FEC_MASK, CCM_PCCR1_HCLK_FEC_MASK);
-}
-
-static int _clk_vpu_enable(struct clk *clk)
-{
-        unsigned long reg;
-
-        reg = __raw_readl(CCM_PCCR1);
-        reg |= CCM_PCCR1_VPU_BAUD_MASK | CCM_PCCR1_HCLK_VPU_MASK;
-        __raw_writel(reg, CCM_PCCR1);
-
-        return 0;
-}
-
-static void _clk_vpu_disable(struct clk *clk)
+static int clk_cpu_set_parent(struct clk *clk, struct clk *parent)
 {
-        unsigned long reg;
-
-        reg = __raw_readl(CCM_PCCR1);
-        reg &= ~(CCM_PCCR1_VPU_BAUD_MASK | CCM_PCCR1_HCLK_VPU_MASK);
-        __raw_writel(reg, CCM_PCCR1);
-}
-
-static int _clk_sahara2_enable(struct clk *clk)
-{
-        _clk_pccr01_enable(CCM_PCCR0_SAHARA_MASK, CCM_PCCR1_HCLK_SAHARA_MASK);
-
-        return 0;
-}
-
-static void _clk_sahara2_disable(struct clk *clk)
-{
-        _clk_pccr01_disable(CCM_PCCR0_SAHARA_MASK, CCM_PCCR1_HCLK_SAHARA_MASK);
-}
-
-static int _clk_mstick1_enable(struct clk *clk)
-{
-        _clk_pccr10_enable(CCM_PCCR1_MSHC_BAUD_MASK, CCM_PCCR0_MSHC_MASK);
-
-        return 0;
-}
-
-static void _clk_mstick1_disable(struct clk *clk)
-{
-        _clk_pccr10_disable(CCM_PCCR1_MSHC_BAUD_MASK, CCM_PCCR0_MSHC_MASK);
-}
-
-#define CSCR() (__raw_readl(CCM_CSCR))
-#define PCDR0() (__raw_readl(CCM_PCDR0))
-#define PCDR1() (__raw_readl(CCM_PCDR1))
-
-static int _clk_cpu_set_parent(struct clk *clk, struct clk *parent)
-{
-        int cscr = CSCR();
+        int cscr = __raw_readl(CCM_CSCR);
 
         if (clk->parent == parent)
                 return 0;
 
         if (mx27_revision() >= CHIP_REV_2_0) {
-                if (parent == &mpll_main_clk[0]) {
+                if (parent == &mpll_main1_clk) {
                         cscr |= CCM_CSCR_ARM_SRC;
                 } else {
-                        if (parent == &mpll_main_clk[1])
+                        if (parent == &mpll_main2_clk)
                                 cscr &= ~CCM_CSCR_ARM_SRC;
                         else
                                 return -EINVAL;
                 }
                 __raw_writel(cscr, CCM_CSCR);
-        } else
-                return -ENODEV;
-
-        clk->parent = parent;
-        return 0;
+                clk->parent = parent;
+                return 0;
+        }
+        return -ENODEV;
 }
 
-static unsigned long _clk_cpu_round_rate(struct clk *clk, unsigned long rate)
+static unsigned long round_rate_cpu(struct clk *clk, unsigned long rate)
 {
         int div;
         unsigned long parent_rate;
@@ -278,7 +156,7 @@ static unsigned long _clk_cpu_round_rate(struct clk *clk, unsigned long rate)
         return parent_rate / div;
 }
 
-static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate)
+static int set_rate_cpu(struct clk *clk, unsigned long rate)
 {
         unsigned int div;
         uint32_t reg;
@@ -295,19 +173,18 @@ static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate)
 
         reg = __raw_readl(CCM_CSCR);
         if (mx27_revision() >= CHIP_REV_2_0) {
-                reg &= ~CCM_CSCR_ARM_MASK;
-                reg |= div << CCM_CSCR_ARM_OFFSET;
-                reg &= ~0x06;
-                __raw_writel(reg | 0x80000000, CCM_CSCR);
+                reg &= ~(3 << 12);
+                reg |= div << 12;
+                reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN);
+                __raw_writel(reg | CCM_CSCR_UPDATE_DIS, CCM_CSCR);
         } else {
-                printk(KERN_ERR "Cant set CPU frequency!\n");
+                printk(KERN_ERR "Can't set CPU frequency!\n");
         }
 
         return 0;
 }
 
-static unsigned long _clk_perclkx_round_rate(struct clk *clk,
-                                             unsigned long rate)
+static unsigned long round_rate_per(struct clk *clk, unsigned long rate)
 {
         u32 div;
         unsigned long parent_rate;
@@ -324,7 +201,7 @@ static unsigned long _clk_perclkx_round_rate(struct clk *clk,
         return parent_rate / div;
 }
 
-static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate)
+static int set_rate_per(struct clk *clk, unsigned long rate)
 {
         u32 reg;
         u32 div;
@@ -340,84 +217,65 @@ static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate)
                 return -EINVAL;
         div--;
 
-        reg =
-            __raw_readl(CCM_PCDR1) & ~(CCM_PCDR1_PERDIV1_MASK <<
-                                       (clk->id << 3));
+        reg = __raw_readl(CCM_PCDR1) & ~(0x3f << (clk->id << 3));
         reg |= div << (clk->id << 3);
         __raw_writel(reg, CCM_PCDR1);
 
         return 0;
 }
 
-static unsigned long _clk_usb_recalc(struct clk *clk)
+static unsigned long get_rate_usb(struct clk *clk)
 {
         unsigned long usb_pdf;
         unsigned long parent_rate;
 
         parent_rate = clk_get_rate(clk->parent);
 
-        usb_pdf = (CSCR() & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET;
+        usb_pdf = (__raw_readl(CCM_CSCR) >> 28) & 0x7;
 
         return parent_rate / (usb_pdf + 1U);
 }
 
-static unsigned long _clk_ssi1_recalc(struct clk *clk)
+static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf)
 {
-        unsigned long ssi1_pdf;
         unsigned long parent_rate;
 
         parent_rate = clk_get_rate(clk->parent);
 
-        ssi1_pdf = (PCDR0() & CCM_PCDR0_SSI1BAUDDIV_MASK) >>
-                                        CCM_PCDR0_SSI1BAUDDIV_OFFSET;
-
         if (mx27_revision() >= CHIP_REV_2_0)
-                ssi1_pdf += 4;
+                pdf += 4;  /* MX27 TO2+ */
         else
-                ssi1_pdf = (ssi1_pdf < 2) ? 124UL : ssi1_pdf;
+                pdf = (pdf < 2) ? 124UL : pdf;  /* MX21 & MX27 TO1 */
 
-        return 2UL * parent_rate / ssi1_pdf;
+        return 2UL * parent_rate / pdf;
 }
 
-static unsigned long _clk_ssi2_recalc(struct clk *clk)
+static unsigned long get_rate_ssi1(struct clk *clk)
 {
-        unsigned long ssi2_pdf;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        ssi2_pdf = (PCDR0() & CCM_PCDR0_SSI2BAUDDIV_MASK) >>
-            CCM_PCDR0_SSI2BAUDDIV_OFFSET;
-
-        if (mx27_revision() >= CHIP_REV_2_0)
-                ssi2_pdf += 4;
-        else
-                ssi2_pdf = (ssi2_pdf < 2) ? 124UL : ssi2_pdf;
+        return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 16) & 0x3f);
+}
 
-        return 2UL * parent_rate / ssi2_pdf;
+static unsigned long get_rate_ssi2(struct clk *clk)
+{
+        return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 26) & 0x3f);
 }
 
-static unsigned long _clk_nfc_recalc(struct clk *clk)
+static unsigned long get_rate_nfc(struct clk *clk)
 {
         unsigned long nfc_pdf;
         unsigned long parent_rate;
 
         parent_rate = clk_get_rate(clk->parent);
 
-        if (mx27_revision() >= CHIP_REV_2_0) {
-                nfc_pdf =
-                    (PCDR0() & CCM_PCDR0_NFCDIV2_MASK) >>
-                    CCM_PCDR0_NFCDIV2_OFFSET;
-        } else {
-                nfc_pdf =
-                    (PCDR0() & CCM_PCDR0_NFCDIV_MASK) >>
-                    CCM_PCDR0_NFCDIV_OFFSET;
-        }
+        if (mx27_revision() >= CHIP_REV_2_0)
+                nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf;
+        else
+                nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf;
 
         return parent_rate / (nfc_pdf + 1);
 }
 
-static unsigned long _clk_vpu_recalc(struct clk *clk)
+static unsigned long get_rate_vpu(struct clk *clk)
 {
         unsigned long vpu_pdf;
         unsigned long parent_rate;
@@ -425,25 +283,27 @@ static unsigned long _clk_vpu_recalc(struct clk *clk)
         parent_rate = clk_get_rate(clk->parent);
 
         if (mx27_revision() >= CHIP_REV_2_0) {
-                vpu_pdf =
-                    (PCDR0() & CCM_PCDR0_VPUDIV2_MASK) >>
-                    CCM_PCDR0_VPUDIV2_OFFSET;
+                vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f;
                 vpu_pdf += 4;
         } else {
-                vpu_pdf =
-                    (PCDR0() & CCM_PCDR0_VPUDIV_MASK) >>
-                    CCM_PCDR0_VPUDIV_OFFSET;
+                vpu_pdf = (__raw_readl(CCM_PCDR0) >> 8) & 0xf;
                 vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf;
         }
+
         return 2UL * parent_rate / vpu_pdf;
 }
 
-static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate)
+static unsigned long round_rate_parent(struct clk *clk, unsigned long rate)
 {
         return clk->parent->round_rate(clk->parent, rate);
 }
 
-static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
+static unsigned long get_rate_parent(struct clk *clk)
+{
+        return clk_get_rate(clk->parent);
+}
+
+static int set_rate_parent(struct clk *clk, unsigned long rate)
 {
         return clk->parent->set_rate(clk->parent, rate);
 }
@@ -451,1112 +311,380 @@ static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
 /* in Hz */
 static unsigned long external_high_reference = 26000000;
 
-static unsigned long get_high_reference_clock_rate(struct clk *clk)
+static unsigned long get_rate_high_reference(struct clk *clk)
 {
         return external_high_reference;
 }
 
-/*
- * the high frequency external clock reference
- * Default case is 26MHz. Could be changed at runtime
- * with a call to change_external_high_reference()
- */
-static struct clk ckih_clk = {
-        .name = "ckih",
-        .get_rate = get_high_reference_clock_rate,
-};
-
 /* in Hz */
 static unsigned long external_low_reference = 32768;
 
-static unsigned long get_low_reference_clock_rate(struct clk *clk)
+static unsigned long get_rate_low_reference(struct clk *clk)
 {
         return external_low_reference;
 }
 
-/*
- * the low frequency external clock reference
- * Default case is 32.768kHz Could be changed at runtime
- * with a call to change_external_low_reference()
- */
-static struct clk ckil_clk = {
-        .name = "ckil",
-        .get_rate = get_low_reference_clock_rate,
-};
-
-static unsigned long get_mpll_clk(struct clk *clk)
+static unsigned long get_rate_fpm(struct clk *clk)
 {
-        uint32_t reg;
-        unsigned long ref_clk;
-        unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
-        unsigned long long temp;
-
-        ref_clk = clk_get_rate(clk->parent);
-
-        reg = __raw_readl(CCM_MPCTL0);
-        pdf = (reg & CCM_MPCTL0_PD_MASK) >> CCM_MPCTL0_PD_OFFSET;
-        mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET;
-        mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET;
-        mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET;
-
-        mfi = (mfi <= 5) ? 5 : mfi;
-        temp = 2LL * ref_clk * mfn;
-        do_div(temp, mfd + 1);
-        temp = 2LL * ref_clk * mfi + temp;
-        do_div(temp, pdf + 1);
-
-        return (unsigned long)temp;
+        return clk_get_rate(clk->parent) * 1024;
 }
 
-static struct clk mpll_clk = {
-        .name = "mpll",
-        .parent = &ckih_clk,
-        .get_rate = get_mpll_clk,
-};
+static unsigned long get_rate_mpll(struct clk *clk)
+{
+        return mxc_decode_pll(__raw_readl(CCM_MPCTL0),
+                        clk_get_rate(clk->parent));
+}
 
-static unsigned long _clk_mpll_main_get_rate(struct clk *clk)
+static unsigned long get_rate_mpll_main(struct clk *clk)
 {
         unsigned long parent_rate;
 
         parent_rate = clk_get_rate(clk->parent);
 
         /* i.MX27 TO2:
-         * clk->id == 0: arm clock source path 1 which is from 2*MPLL/DIV_2
-         * clk->id == 1: arm clock source path 2 which is from 2*MPLL/DIV_3
+         * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2
+         * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3
          */
-
         if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1)
                 return 2UL * parent_rate / 3UL;
 
         return parent_rate;
 }
 
-static struct clk mpll_main_clk[] = {
-        {
-                /* For i.MX27 TO2, it is the MPLL path 1 of ARM core
-                 * It provide the clock source whose rate is same as MPLL
-                 */
-                .name = "mpll_main",
-                .id = 0,
-                .parent = &mpll_clk,
-                .get_rate = _clk_mpll_main_get_rate
-        }, {
-                /* For i.MX27 TO2, it is the MPLL path 2 of ARM core
-                 * It provide the clock source whose rate is same MPLL * 2/3
-                 */
-                .name = "mpll_main",
-                .id = 1,
-                .parent = &mpll_clk,
-                .get_rate = _clk_mpll_main_get_rate
-        }
-};
-
-static unsigned long get_spll_clk(struct clk *clk)
+static unsigned long get_rate_spll(struct clk *clk)
 {
         uint32_t reg;
-        unsigned long ref_clk;
-        unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
-        unsigned long long temp;
+        unsigned long rate;
 
-        ref_clk = clk_get_rate(clk->parent);
+        rate = clk_get_rate(clk->parent);
 
         reg = __raw_readl(CCM_SPCTL0);
-        /*TODO: This is TO2 Bug */
+
+        /* On TO2 we have to write the value back. Otherwise we
+         * read 0 from this register the next time.
+         */
         if (mx27_revision() >= CHIP_REV_2_0)
                 __raw_writel(reg, CCM_SPCTL0);
 
-        pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET;
-        mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET;
-        mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET;
-        mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET;
-
-        mfi = (mfi <= 5) ? 5 : mfi;
-        temp = 2LL * ref_clk * mfn;
-        do_div(temp, mfd + 1);
-        temp = 2LL * ref_clk * mfi + temp;
-        do_div(temp, pdf + 1);
-
-        return (unsigned long)temp;
+        return mxc_decode_pll(reg, rate);
 }
 
-static struct clk spll_clk = {
-        .name = "spll",
-        .parent = &ckih_clk,
-        .get_rate = get_spll_clk,
-        .enable = _clk_spll_enable,
-        .disable = _clk_spll_disable,
-};
-
-static unsigned long get_cpu_clk(struct clk *clk)
+static unsigned long get_rate_cpu(struct clk *clk)
 {
         u32 div;
         unsigned long rate;
 
         if (mx27_revision() >= CHIP_REV_2_0)
-                div = (CSCR() & CCM_CSCR_ARM_MASK) >> CCM_CSCR_ARM_OFFSET;
+                div = (__raw_readl(CCM_CSCR) >> 12) & 0x3;
         else
-                div = (CSCR() & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET;
+                div = (__raw_readl(CCM_CSCR) >> 13) & 0x7;
 
         rate = clk_get_rate(clk->parent);
         return rate / (div + 1);
 }
 
-static struct clk cpu_clk = {
-        .name = "cpu_clk",
-        .parent = &mpll_main_clk[1],
-        .set_parent = _clk_cpu_set_parent,
-        .round_rate = _clk_cpu_round_rate,
-        .get_rate = get_cpu_clk,
-        .set_rate = _clk_cpu_set_rate,
-};
-
-static unsigned long get_ahb_clk(struct clk *clk)
+static unsigned long get_rate_ahb(struct clk *clk)
 {
-        unsigned long rate;
-        unsigned long bclk_pdf;
+        unsigned long rate, bclk_pdf;
 
         if (mx27_revision() >= CHIP_REV_2_0)
-                bclk_pdf = (CSCR() & CCM_CSCR_AHB_MASK)
-                                        >> CCM_CSCR_AHB_OFFSET;
+                bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3;
         else
-                bclk_pdf = (CSCR() & CCM_CSCR_BCLK_MASK)
-                                        >> CCM_CSCR_BCLK_OFFSET;
+                bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf;
 
         rate = clk_get_rate(clk->parent);
         return rate / (bclk_pdf + 1);
 }
 
-static struct clk ahb_clk = {
-        .name = "ahb_clk",
-        .parent = &mpll_main_clk[1],
-        .get_rate = get_ahb_clk,
-};
-
-static unsigned long get_ipg_clk(struct clk *clk)
+static unsigned long get_rate_ipg(struct clk *clk)
 {
-        unsigned long rate;
-        unsigned long ipg_pdf;
+        unsigned long rate, ipg_pdf;
 
         if (mx27_revision() >= CHIP_REV_2_0)
                 return clk_get_rate(clk->parent);
         else
-                ipg_pdf = (CSCR() & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET;
+                ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1;
 
         rate = clk_get_rate(clk->parent);
         return rate / (ipg_pdf + 1);
 }
 
-static struct clk ipg_clk = {
-        .name = "ipg_clk",
-        .parent = &ahb_clk,
-        .get_rate = get_ipg_clk,
-};
-
-static unsigned long _clk_perclkx_recalc(struct clk *clk)
+static unsigned long get_rate_per(struct clk *clk)
 {
-        unsigned long perclk_pdf;
-        unsigned long parent_rate;
+        unsigned long perclk_pdf, parent_rate;
 
         parent_rate = clk_get_rate(clk->parent);
 
         if (clk->id < 0 || clk->id > 3)
                 return 0;
 
-        perclk_pdf = (PCDR1() >> (clk->id << 3)) & CCM_PCDR1_PERDIV1_MASK;
+        perclk_pdf = (__raw_readl(CCM_PCDR1) >> (clk->id << 3)) & 0x3f;
 
         return parent_rate / (perclk_pdf + 1);
 }
 
-static struct clk per_clk[] = {
-        {
-                .name = "per_clk",
-                .id = 0,
-                .parent = &mpll_main_clk[1],
-                .get_rate = _clk_perclkx_recalc,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR1,
-                .enable_shift = CCM_PCCR1_PERCLK1_OFFSET,
-                .disable = _clk_disable,
-        }, {
-                .name = "per_clk",
-                .id = 1,
-                .parent = &mpll_main_clk[1],
-                .get_rate = _clk_perclkx_recalc,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR1,
-                .enable_shift = CCM_PCCR1_PERCLK2_OFFSET,
-                .disable = _clk_disable,
-        }, {
-                .name = "per_clk",
-                .id = 2,
-                .parent = &mpll_main_clk[1],
-                .round_rate = _clk_perclkx_round_rate,
-                .set_rate = _clk_perclkx_set_rate,
-                .get_rate = _clk_perclkx_recalc,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR1,
-                .enable_shift = CCM_PCCR1_PERCLK3_OFFSET,
-                .disable = _clk_disable,
-        }, {
-                .name = "per_clk",
-                .id = 3,
-                .parent = &mpll_main_clk[1],
-                .round_rate = _clk_perclkx_round_rate,
-                .set_rate = _clk_perclkx_set_rate,
-                .get_rate = _clk_perclkx_recalc,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR1,
-                .enable_shift = CCM_PCCR1_PERCLK4_OFFSET,
-                .disable = _clk_disable,
-        },
-};
-
-struct clk uart1_clk[] = {
-        {
-                .name = "uart_clk",
-                .id = 0,
-                .parent = &per_clk[0],
-                .secondary = &uart1_clk[1],
-        }, {
-                .name = "uart_ipg_clk",
-                .id = 0,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR1,
-                .enable_shift = CCM_PCCR1_UART1_OFFSET,
-                .disable = _clk_disable,
-        },
-};
-
-struct clk uart2_clk[] = {
-        {
-                .name = "uart_clk",
-                .id = 1,
-                .parent = &per_clk[0],
-                .secondary = &uart2_clk[1],
-        }, {
-                .name = "uart_ipg_clk",
-                .id = 1,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR1,
-                .enable_shift = CCM_PCCR1_UART2_OFFSET,
-                .disable = _clk_disable,
-        },
-};
-
-struct clk uart3_clk[] = {
-        {
-                .name = "uart_clk",
-                .id = 2,
-                .parent = &per_clk[0],
-                .secondary = &uart3_clk[1],
-        }, {
-                .name = "uart_ipg_clk",
-                .id = 2,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR1,
-                .enable_shift = CCM_PCCR1_UART3_OFFSET,
-                .disable = _clk_disable,
-        },
-};
-
-struct clk uart4_clk[] = {
-        {
-                .name = "uart_clk",
-                .id = 3,
-                .parent = &per_clk[0],
-                .secondary = &uart4_clk[1],
-        }, {
-                .name = "uart_ipg_clk",
-                .id = 3,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR1,
-                .enable_shift = CCM_PCCR1_UART4_OFFSET,
-                .disable = _clk_disable,
-        },
-};
-
-struct clk uart5_clk[] = {
-        {
-                .name = "uart_clk",
-                .id = 4,
-                .parent = &per_clk[0],
-                .secondary = &uart5_clk[1],
-        }, {
-                .name = "uart_ipg_clk",
-                .id = 4,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR1,
-                .enable_shift = CCM_PCCR1_UART5_OFFSET,
-                .disable = _clk_disable,
-        },
-};
-
-struct clk uart6_clk[] = {
-        {
-                .name = "uart_clk",
-                .id = 5,
-                .parent = &per_clk[0],
-                .secondary = &uart6_clk[1],
-        }, {
-                .name = "uart_ipg_clk",
-                .id = 5,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR1,
-                .enable_shift = CCM_PCCR1_UART6_OFFSET,
-                .disable = _clk_disable,
-        },
-};
-
-static struct clk gpt1_clk[] = {
-        {
-                .name = "gpt_clk",
-                .id = 0,
-                .parent = &per_clk[0],
-                .secondary = &gpt1_clk[1],
-        }, {
-                .name = "gpt_ipg_clk",
-                .id = 0,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR0,
-                .enable_shift = CCM_PCCR0_GPT1_OFFSET,
-                .disable = _clk_disable,
-        },
-};
-
-static struct clk gpt2_clk[] = {
-        {
-                .name = "gpt_clk",
-                .id = 1,
-                .parent = &per_clk[0],
-                .secondary = &gpt2_clk[1],
-        }, {
-                .name = "gpt_ipg_clk",
-                .id = 1,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR0,
-                .enable_shift = CCM_PCCR0_GPT2_OFFSET,
-                .disable = _clk_disable,
-        },
-};
-
-static struct clk gpt3_clk[] = {
-        {
-                .name = "gpt_clk",
-                .id = 2,
-                .parent = &per_clk[0],
-                .secondary = &gpt3_clk[1],
-        }, {
-                .name = "gpt_ipg_clk",
-                .id = 2,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR0,
-                .enable_shift = CCM_PCCR0_GPT3_OFFSET,
-                .disable = _clk_disable,
-        },
-};
-
-static struct clk gpt4_clk[] = {
-        {
-                .name = "gpt_clk",
-                .id = 3,
-                .parent = &per_clk[0],
-                .secondary = &gpt4_clk[1],
-        }, {
-                .name = "gpt_ipg_clk",
-                .id = 3,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR0,
-                .enable_shift = CCM_PCCR0_GPT4_OFFSET,
-                .disable = _clk_disable,
-        },
-};
-
-static struct clk gpt5_clk[] = {
-        {
-                .name = "gpt_clk",
-                .id = 4,
-                .parent = &per_clk[0],
-                .secondary = &gpt5_clk[1],
-        }, {
-                .name = "gpt_ipg_clk",
-                .id = 4,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR0,
-                .enable_shift = CCM_PCCR0_GPT5_OFFSET,
-                .disable = _clk_disable,
-        },
+/*
+ * the high frequency external clock reference
+ * Default case is 26MHz. Could be changed at runtime
+ * with a call to change_external_high_reference()
+ */
+static struct clk ckih_clk = {
+        .get_rate       = get_rate_high_reference,
 };
 
-static struct clk gpt6_clk[] = {
-        {
-                .name = "gpt_clk",
-                .id = 5,
-                .parent = &per_clk[0],
-                .secondary = &gpt6_clk[1],
-        }, {
-                .name = "gpt_ipg_clk",
-                .id = 5,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR0,
-                .enable_shift = CCM_PCCR0_GPT6_OFFSET,
-                .disable = _clk_disable,
-        },
+static struct clk mpll_clk = {
+        .parent         = &ckih_clk,
+        .get_rate       = get_rate_mpll,
 };
 
-static struct clk pwm_clk[] = {
-        {
-                .name = "pwm_clk",
-                .parent = &per_clk[0],
-                .secondary = &pwm_clk[1],
-        }, {
-                .name = "pwm_clk",
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR0,
-                .enable_shift = CCM_PCCR0_PWM_OFFSET,
-                .disable = _clk_disable,
-        },
+/* For i.MX27 TO2, it is the MPLL path 1 of ARM core
+ * It provides the clock source whose rate is same as MPLL
+ */
+static struct clk mpll_main1_clk = {
+        .id             = 0,
+        .parent         = &mpll_clk,
+        .get_rate       = get_rate_mpll_main,
 };
 
-static struct clk sdhc1_clk[] = {
-        {
-                .name = "sdhc_clk",
-                .id = 0,
-                .parent = &per_clk[1],
-                .secondary = &sdhc1_clk[1],
-        }, {
-                .name = "sdhc_ipg_clk",
-                .id = 0,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR0,
-                .enable_shift = CCM_PCCR0_SDHC1_OFFSET,
-                .disable = _clk_disable,
-        },
+/* For i.MX27 TO2, it is the MPLL path 2 of ARM core
+ * It provides the clock source whose rate is same MPLL * 2 / 3
+ */
+static struct clk mpll_main2_clk = {
+        .id             = 1,
+        .parent         = &mpll_clk,
+        .get_rate       = get_rate_mpll_main,
 };
 
-static struct clk sdhc2_clk[] = {
-        {
-                .name = "sdhc_clk",
-                .id = 1,
-                .parent = &per_clk[1],
-                .secondary = &sdhc2_clk[1],
-        }, {
-                .name = "sdhc_ipg_clk",
-                .id = 1,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR0,
-                .enable_shift = CCM_PCCR0_SDHC2_OFFSET,
-                .disable = _clk_disable,
-        },
+static struct clk ahb_clk = {
+        .parent         = &mpll_main2_clk,
+        .get_rate       = get_rate_ahb,
 };
 
-static struct clk sdhc3_clk[] = {
-        {
-                .name = "sdhc_clk",
-                .id = 2,
-                .parent = &per_clk[1],
-                .secondary = &sdhc3_clk[1],
-        }, {
-                .name = "sdhc_ipg_clk",
-                .id = 2,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR0,
-                .enable_shift = CCM_PCCR0_SDHC3_OFFSET,
-                .disable = _clk_disable,
-        },
+static struct clk ipg_clk = {
+        .parent         = &ahb_clk,
+        .get_rate       = get_rate_ipg,
 };
 
-static struct clk cspi1_clk[] = {
-        {
-                .name = "cspi_clk",
-                .id = 0,
-                .parent = &per_clk[1],
-                .secondary = &cspi1_clk[1],
-        }, {
-                .name = "cspi_ipg_clk",
-                .id = 0,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR0,
-                .enable_shift = CCM_PCCR0_CSPI1_OFFSET,
-                .disable = _clk_disable,
-        },
+static struct clk cpu_clk = {
+        .parent = &mpll_main2_clk,
+        .set_parent = clk_cpu_set_parent,
+        .round_rate = round_rate_cpu,
+        .get_rate = get_rate_cpu,
+        .set_rate = set_rate_cpu,
 };
 
-static struct clk cspi2_clk[] = {
-        {
-                .name = "cspi_clk",
-                .id = 1,
-                .parent = &per_clk[1],
-                .secondary = &cspi2_clk[1],
-        }, {
-                .name = "cspi_ipg_clk",
-                .id = 1,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR0,
-                .enable_shift = CCM_PCCR0_CSPI2_OFFSET,
-                .disable = _clk_disable,
-        },
+static struct clk spll_clk = {
+        .parent = &ckih_clk,
+        .get_rate = get_rate_spll,
+        .enable = clk_spll_enable,
+        .disable = clk_spll_disable,
 };
 
-static struct clk cspi3_clk[] = {
-        {
-                .name = "cspi_clk",
-                .id = 2,
-                .parent = &per_clk[1],
-                .secondary = &cspi3_clk[1],
-        }, {
-                .name = "cspi_ipg_clk",
-                .id = 2,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR0,
-                .enable_shift = CCM_PCCR0_CSPI3_OFFSET,
-                .disable = _clk_disable,
-        },
+/*
+ * the low frequency external clock reference
+ * Default case is 32.768kHz.
+ */
+static struct clk ckil_clk = {
+        .get_rate = get_rate_low_reference,
 };
 
-static struct clk lcdc_clk[] = {
-        {
-                .name = "lcdc_clk",
-                .parent = &per_clk[2],
-                .secondary = &lcdc_clk[1],
-                .round_rate = _clk_parent_round_rate,
-                .set_rate = _clk_parent_set_rate,
-        }, {
-                .name = "lcdc_ipg_clk",
-                .parent = &ipg_clk,
-                .secondary = &lcdc_clk[2],
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR0,
-                .enable_shift = CCM_PCCR0_LCDC_OFFSET,
-                .disable = _clk_disable,
-        }, {
-                .name = "lcdc_ahb_clk",
-                .parent = &ahb_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR1,
-                .enable_shift = CCM_PCCR1_HCLK_LCDC_OFFSET,
-                .disable = _clk_disable,
-        },
+/* Output of frequency pre multiplier */
+static struct clk fpm_clk = {
+        .parent = &ckil_clk,
+        .get_rate = get_rate_fpm,
 };
 
-static struct clk csi_clk[] = {
-        {
-                .name = "csi_perclk",
-                .parent = &per_clk[3],
-                .secondary = &csi_clk[1],
-                .round_rate = _clk_parent_round_rate,
-                .set_rate = _clk_parent_set_rate,
-        }, {
-                .name = "csi_ahb_clk",
-                .parent = &ahb_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR1,
-                .enable_shift = CCM_PCCR1_HCLK_CSI_OFFSET,
-                .disable = _clk_disable,
-        },
-};
+#define PCCR0 CCM_PCCR0
+#define PCCR1 CCM_PCCR1
 
-static struct clk usb_clk[] = {
-        {
-                .name = "usb_clk",
-                .parent = &spll_clk,
-                .get_rate = _clk_usb_recalc,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR1,
-                .enable_shift = CCM_PCCR1_USBOTG_OFFSET,
-                .disable = _clk_disable,
-        }, {
-                .name = "usb_ahb_clk",
-                .parent = &ahb_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR1,
-                .enable_shift = CCM_PCCR1_HCLK_USBOTG_OFFSET,
-                .disable = _clk_disable,
+#define DEFINE_CLOCK(name, i, er, es, gr, s, p)         \
+        static struct clk name = {                      \
+                .id             = i,                    \
+                .enable_reg     = er,                   \
+                .enable_shift   = es,                   \
+                .get_rate       = gr,                   \
+                .enable         = clk_pccr_enable,      \
+                .disable        = clk_pccr_disable,     \
+                .secondary      = s,                    \
+                .parent         = p,                    \
         }
-};
 
-static struct clk ssi1_clk[] = {
-        {
-                .name = "ssi_clk",
-                .id = 0,
-                .parent = &mpll_main_clk[1],
-                .secondary = &ssi1_clk[1],
-                .get_rate = _clk_ssi1_recalc,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR1,
-                .enable_shift = CCM_PCCR1_SSI1_BAUD_OFFSET,
-                .disable = _clk_disable,
-        }, {
-                .name = "ssi_ipg_clk",
-                .id = 0,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR0,
-                .enable_shift = CCM_PCCR0_SSI1_IPG_OFFSET,
-                .disable = _clk_disable,
-        },
-};
+#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p)       \
+        static struct clk name = {                              \
+                .id             = i,                            \
+                .enable_reg     = er,                           \
+                .enable_shift   = es,                           \
+                .get_rate       = get_rate_##getsetround,       \
+                .set_rate       = set_rate_##getsetround,       \
+                .round_rate     = round_rate_##getsetround,     \
+                .enable         = clk_pccr_enable,              \
+                .disable        = clk_pccr_disable,             \
+                .secondary      = s,                            \
+                .parent         = p,                            \
+        }
 
-static struct clk ssi2_clk[] = {
-        {
-                .name = "ssi_clk",
-                .id = 1,
-                .parent = &mpll_main_clk[1],
-                .secondary = &ssi2_clk[1],
-                .get_rate = _clk_ssi2_recalc,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR1,
-                .enable_shift = CCM_PCCR1_SSI2_BAUD_OFFSET,
-                .disable = _clk_disable,
-        }, {
-                .name = "ssi_ipg_clk",
-                .id = 1,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR0,
-                .enable_shift = CCM_PCCR0_SSI2_IPG_OFFSET,
-                .disable = _clk_disable,
+/* Forward declaration to keep the following list in order */
+static struct clk slcdc_clk1, sahara2_clk1, rtic_clk1, fec_clk1, emma_clk1,
+                  dma_clk1, lcdc_clk2, vpu_clk1;
+
+/* All clocks we can gate through PCCRx in the order of PCCRx bits */
+DEFINE_CLOCK(ssi2_clk1,    1, PCCR0,  0, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(ssi1_clk1,    0, PCCR0,  1, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(slcdc_clk,    0, PCCR0,  2, NULL, &slcdc_clk1, &ahb_clk);
+DEFINE_CLOCK(sdhc3_clk1,   0, PCCR0,  3, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(sdhc2_clk1,   0, PCCR0,  4, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(sdhc1_clk1,   0, PCCR0,  5, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(scc_clk,      0, PCCR0,  6, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(sahara2_clk,  0, PCCR0,  7, NULL, &sahara2_clk1, &ahb_clk);
+DEFINE_CLOCK(rtic_clk,     0, PCCR0,  8, NULL, &rtic_clk1, &ahb_clk);
+DEFINE_CLOCK(rtc_clk,      0, PCCR0,  9, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(pwm_clk1,     0, PCCR0, 11, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(owire_clk,    0, PCCR0, 12, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(mstick_clk1,  0, PCCR0, 13, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(lcdc_clk1,    0, PCCR0, 14, NULL, &lcdc_clk2, &ipg_clk);
+DEFINE_CLOCK(kpp_clk,      0, PCCR0, 15, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(iim_clk,      0, PCCR0, 16, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(i2c2_clk,     1, PCCR0, 17, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(i2c1_clk,     0, PCCR0, 18, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(gpt6_clk1,    0, PCCR0, 29, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(gpt5_clk1,    0, PCCR0, 20, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(gpt4_clk1,    0, PCCR0, 21, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(gpt3_clk1,    0, PCCR0, 22, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(gpt2_clk1,    0, PCCR0, 23, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(gpt1_clk1,    0, PCCR0, 24, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(gpio_clk,     0, PCCR0, 25, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(fec_clk,      0, PCCR0, 26, NULL, &fec_clk1, &ahb_clk);
+DEFINE_CLOCK(emma_clk,     0, PCCR0, 27, NULL, &emma_clk1, &ahb_clk);
+DEFINE_CLOCK(dma_clk,      0, PCCR0, 28, NULL, &dma_clk1, &ahb_clk);
+DEFINE_CLOCK(cspi13_clk1,  0, PCCR0, 29, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(cspi2_clk1,   0, PCCR0, 30, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(cspi1_clk1,   0, PCCR0, 31, NULL, NULL, &ipg_clk);
+
+DEFINE_CLOCK(mstick_clk,   0, PCCR1,  2, NULL, &mstick_clk1, &ipg_clk);
+DEFINE_CLOCK(nfc_clk,      0, PCCR1,  3, get_rate_nfc, NULL, &cpu_clk);
+DEFINE_CLOCK(ssi2_clk,     1, PCCR1,  4, get_rate_ssi2, &ssi2_clk1, &mpll_main2_clk);
+DEFINE_CLOCK(ssi1_clk,     0, PCCR1,  5, get_rate_ssi1, &ssi1_clk1, &mpll_main2_clk);
+DEFINE_CLOCK(vpu_clk,      0, PCCR1,  6, get_rate_vpu, &vpu_clk1, &mpll_main2_clk);
+DEFINE_CLOCK1(per4_clk,    3, PCCR1,  7, per, NULL, &mpll_main2_clk);
+DEFINE_CLOCK1(per3_clk,    2, PCCR1,  8, per, NULL, &mpll_main2_clk);
+DEFINE_CLOCK1(per2_clk,    1, PCCR1,  9, per, NULL, &mpll_main2_clk);
+DEFINE_CLOCK1(per1_clk,    0, PCCR1, 10, per, NULL, &mpll_main2_clk);
+DEFINE_CLOCK(usb_clk1,     0, PCCR1, 11, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(slcdc_clk1,   0, PCCR1, 12, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(sahara2_clk1, 0, PCCR1, 13, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(rtic_clk1,    0, PCCR1, 14, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(lcdc_clk2,    0, PCCR1, 15, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(vpu_clk1,     0, PCCR1, 16, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(fec_clk1,     0, PCCR1, 17, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(emma_clk1,    0, PCCR1, 18, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(emi_clk,      0, PCCR1, 19, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(dma_clk1,     0, PCCR1, 20, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(csi_clk1,     0, PCCR1, 21, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(brom_clk,     0, PCCR1, 22, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(ata_clk,      0, PCCR1, 23, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(wdog_clk,     0, PCCR1, 24, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(usb_clk,      0, PCCR1, 25, get_rate_usb, &usb_clk1, &spll_clk);
+DEFINE_CLOCK(uart6_clk1,   0, PCCR1, 26, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(uart5_clk1,   0, PCCR1, 27, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(uart4_clk1,   0, PCCR1, 28, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(uart3_clk1,   0, PCCR1, 29, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(uart2_clk1,   0, PCCR1, 30, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(uart1_clk1,   0, PCCR1, 31, NULL, NULL, &ipg_clk);
+
+/* Clocks we cannot directly gate, but drivers need their rates */
+DEFINE_CLOCK(cspi1_clk,    0, 0,      0, NULL, &cspi1_clk1, &per2_clk);
+DEFINE_CLOCK(cspi2_clk,    1, 0,      0, NULL, &cspi2_clk1, &per2_clk);
+DEFINE_CLOCK(cspi3_clk,    2, 0,      0, NULL, &cspi13_clk1, &per2_clk);
+DEFINE_CLOCK(sdhc1_clk,    0, 0,      0, NULL, &sdhc1_clk1, &per2_clk);
+DEFINE_CLOCK(sdhc2_clk,    1, 0,      0, NULL, &sdhc2_clk1, &per2_clk);
+DEFINE_CLOCK(sdhc3_clk,    2, 0,      0, NULL, &sdhc3_clk1, &per2_clk);
+DEFINE_CLOCK(pwm_clk,      0, 0,      0, NULL, &pwm_clk1, &per1_clk);
+DEFINE_CLOCK(gpt1_clk,     0, 0,      0, NULL, &gpt1_clk1, &per1_clk);
+DEFINE_CLOCK(gpt2_clk,     1, 0,      0, NULL, &gpt2_clk1, &per1_clk);
+DEFINE_CLOCK(gpt3_clk,     2, 0,      0, NULL, &gpt3_clk1, &per1_clk);
+DEFINE_CLOCK(gpt4_clk,     3, 0,      0, NULL, &gpt4_clk1, &per1_clk);
+DEFINE_CLOCK(gpt5_clk,     4, 0,      0, NULL, &gpt5_clk1, &per1_clk);
+DEFINE_CLOCK(gpt6_clk,     5, 0,      0, NULL, &gpt6_clk1, &per1_clk);
+DEFINE_CLOCK(uart1_clk,    0, 0,      0, NULL, &uart1_clk1, &per1_clk);
+DEFINE_CLOCK(uart2_clk,    1, 0,      0, NULL, &uart2_clk1, &per1_clk);
+DEFINE_CLOCK(uart3_clk,    2, 0,      0, NULL, &uart3_clk1, &per1_clk);
+DEFINE_CLOCK(uart4_clk,    3, 0,      0, NULL, &uart4_clk1, &per1_clk);
+DEFINE_CLOCK(uart5_clk,    4, 0,      0, NULL, &uart5_clk1, &per1_clk);
+DEFINE_CLOCK(uart6_clk,    5, 0,      0, NULL, &uart6_clk1, &per1_clk);
+DEFINE_CLOCK1(lcdc_clk,    0, 0,      0, parent, &lcdc_clk1, &per3_clk);
+DEFINE_CLOCK1(csi_clk,     0, 0,      0, parent, &csi_clk1, &per4_clk);
+
+#define _REGISTER_CLOCK(d, n, c) \
+        { \
+                .dev_id = d, \
+                .con_id = n, \
+                .clk = &c, \
         },
-};
-
-static struct clk nfc_clk = {
-        .name = "nfc_clk",
-        .parent = &cpu_clk,
-        .get_rate = _clk_nfc_recalc,
-        .enable = _clk_enable,
-        .enable_reg = CCM_PCCR1,
-        .enable_shift = CCM_PCCR1_NFC_BAUD_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk vpu_clk = {
-        .name = "vpu_clk",
-        .parent = &mpll_main_clk[1],
-        .get_rate = _clk_vpu_recalc,
-        .enable = _clk_vpu_enable,
-        .disable = _clk_vpu_disable,
-};
-
-static struct clk dma_clk = {
-        .name = "dma_clk",
-        .parent = &ahb_clk,
-        .enable = _clk_dma_enable,
-        .disable = _clk_dma_disable,
-};
-
-static struct clk rtic_clk = {
-        .name = "rtic_clk",
-        .parent = &ahb_clk,
-        .enable = _clk_rtic_enable,
-        .disable = _clk_rtic_disable,
-};
 
-static struct clk brom_clk = {
-        .name = "brom_clk",
-        .parent = &ahb_clk,
-        .enable = _clk_enable,
-        .enable_reg = CCM_PCCR1,
-        .enable_shift = CCM_PCCR1_HCLK_BROM_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk emma_clk = {
-        .name = "emma_clk",
-        .parent = &ahb_clk,
-        .enable = _clk_emma_enable,
-        .disable = _clk_emma_disable,
-};
-
-static struct clk slcdc_clk = {
-        .name = "slcdc_clk",
-        .parent = &ahb_clk,
-        .enable = _clk_slcdc_enable,
-        .disable = _clk_slcdc_disable,
-};
-
-static struct clk fec_clk = {
-        .name = "fec_clk",
-        .parent = &ahb_clk,
-        .enable = _clk_fec_enable,
-        .disable = _clk_fec_disable,
-};
-
-static struct clk emi_clk = {
-        .name = "emi_clk",
-        .parent = &ahb_clk,
-        .enable = _clk_enable,
-        .enable_reg = CCM_PCCR1,
-        .enable_shift = CCM_PCCR1_HCLK_EMI_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk sahara2_clk = {
-        .name = "sahara_clk",
-        .parent = &ahb_clk,
-        .enable = _clk_sahara2_enable,
-        .disable = _clk_sahara2_disable,
-};
-
-static struct clk ata_clk = {
-        .name = "ata_clk",
-        .parent = &ahb_clk,
-        .enable = _clk_enable,
-        .enable_reg = CCM_PCCR1,
-        .enable_shift = CCM_PCCR1_HCLK_ATA_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk mstick1_clk = {
-        .name = "mstick1_clk",
-        .parent = &ipg_clk,
-        .enable = _clk_mstick1_enable,
-        .disable = _clk_mstick1_disable,
-};
-
-static struct clk wdog_clk = {
-        .name = "wdog_clk",
-        .parent = &ipg_clk,
-        .enable = _clk_enable,
-        .enable_reg = CCM_PCCR1,
-        .enable_shift = CCM_PCCR1_WDT_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk gpio_clk = {
-        .name = "gpio_clk",
-        .parent = &ipg_clk,
-        .enable = _clk_enable,
-        .enable_reg = CCM_PCCR1,
-        .enable_shift = CCM_PCCR0_GPIO_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk i2c_clk[] = {
-        {
-                .name = "i2c_clk",
-                .id = 0,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR0,
-                .enable_shift = CCM_PCCR0_I2C1_OFFSET,
-                .disable = _clk_disable,
-        }, {
-                .name = "i2c_clk",
-                .id = 1,
-                .parent = &ipg_clk,
-                .enable = _clk_enable,
-                .enable_reg = CCM_PCCR0,
-                .enable_shift = CCM_PCCR0_I2C2_OFFSET,
-                .disable = _clk_disable,
-        },
-};
-
-static struct clk iim_clk = {
-        .name = "iim_clk",
-        .parent = &ipg_clk,
-        .enable = _clk_enable,
-        .enable_reg = CCM_PCCR0,
-        .enable_shift = CCM_PCCR0_IIM_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk kpp_clk = {
-        .name = "kpp_clk",
-        .parent = &ipg_clk,
-        .enable = _clk_enable,
-        .enable_reg = CCM_PCCR0,
-        .enable_shift = CCM_PCCR0_KPP_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk owire_clk = {
-        .name = "owire_clk",
-        .parent = &ipg_clk,
-        .enable = _clk_enable,
-        .enable_reg = CCM_PCCR0,
-        .enable_shift = CCM_PCCR0_OWIRE_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk rtc_clk = {
-        .name = "rtc_clk",
-        .parent = &ipg_clk,
-        .enable = _clk_enable,
-        .enable_reg = CCM_PCCR0,
-        .enable_shift = CCM_PCCR0_RTC_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk scc_clk = {
-        .name = "scc_clk",
-        .parent = &ipg_clk,
-        .enable = _clk_enable,
-        .enable_reg = CCM_PCCR0,
-        .enable_shift = CCM_PCCR0_SCC_OFFSET,
-        .disable = _clk_disable,
-};
-
-static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate)
-{
-        u32 div;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-        div = parent_rate / rate;
-        if (parent_rate % rate)
-                div++;
-
-        if (div > 8)
-                div = 8;
-
-        return parent_rate / div;
-}
-
-static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
-{
-        u32 reg;
-        u32 div;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        div = parent_rate / rate;
-
-        if (div > 8 || div < 1 || ((parent_rate / div) != rate))
-                return -EINVAL;
-        div--;
-
-        reg = __raw_readl(CCM_PCDR0) & ~CCM_PCDR0_CLKODIV_MASK;
-        reg |= div << CCM_PCDR0_CLKODIV_OFFSET;
-        __raw_writel(reg, CCM_PCDR0);
-
-        return 0;
-}
-
-static unsigned long _clk_clko_recalc(struct clk *clk)
-{
-        u32 div;
-        unsigned long parent_rate;
-
-        parent_rate = clk_get_rate(clk->parent);
-
-        div = __raw_readl(CCM_PCDR0) & CCM_PCDR0_CLKODIV_MASK >>
-                CCM_PCDR0_CLKODIV_OFFSET;
-        div++;
-
-        return parent_rate / div;
-}
-
-static int _clk_clko_set_parent(struct clk *clk, struct clk *parent)
-{
-        u32 reg;
-
-        reg = __raw_readl(CCM_CCSR) & ~CCM_CCSR_CLKOSEL_MASK;
-
-        if (parent == &ckil_clk)
-                reg |= 0 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &ckih_clk)
-                reg |= 2 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == mpll_clk.parent)
-                reg |= 3 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == spll_clk.parent)
-                reg |= 4 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &mpll_clk)
-                reg |= 5 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &spll_clk)
-                reg |= 6 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &cpu_clk)
-                reg |= 7 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &ahb_clk)
-                reg |= 8 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &ipg_clk)
-                reg |= 9 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &per_clk[0])
-                reg |= 0xA << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &per_clk[1])
-                reg |= 0xB << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &per_clk[2])
-                reg |= 0xC << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &per_clk[3])
-                reg |= 0xD << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &ssi1_clk[0])
-                reg |= 0xE << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &ssi2_clk[0])
-                reg |= 0xF << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &nfc_clk)
-                reg |= 0x10 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &mstick1_clk)
-                reg |= 0x11 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &vpu_clk)
-                reg |= 0x12 << CCM_CCSR_CLKOSEL_OFFSET;
-        else if (parent == &usb_clk[0])
-                reg |= 0x15 << CCM_CCSR_CLKOSEL_OFFSET;
-        else
-                return -EINVAL;
-
-        __raw_writel(reg, CCM_CCSR);
-
-        return 0;
-}
-
-static int _clk_clko_enable(struct clk *clk)
-{
-        u32 reg;
-
-        reg = __raw_readl(CCM_PCDR0) | CCM_PCDR0_CLKO_EN;
-        __raw_writel(reg, CCM_PCDR0);
-
-        return 0;
-}
-
-static void _clk_clko_disable(struct clk *clk)
-{
-        u32 reg;
-
-        reg = __raw_readl(CCM_PCDR0) & ~CCM_PCDR0_CLKO_EN;
-        __raw_writel(reg, CCM_PCDR0);
-}
-
-static struct clk clko_clk = {
-        .name = "clko_clk",
-        .get_rate = _clk_clko_recalc,
-        .set_rate = _clk_clko_set_rate,
-        .round_rate = _clk_clko_round_rate,
-        .set_parent = _clk_clko_set_parent,
-        .enable = _clk_clko_enable,
-        .disable = _clk_clko_disable,
-};
-
-static struct clk *mxc_clks[] = {
-        &ckih_clk,
-        &ckil_clk,
-        &mpll_clk,
-        &mpll_main_clk[0],
-        &mpll_main_clk[1],
-        &spll_clk,
-        &cpu_clk,
-        &ahb_clk,
-        &ipg_clk,
-        &per_clk[0],
-        &per_clk[1],
-        &per_clk[2],
-        &per_clk[3],
-        &clko_clk,
-        &uart1_clk[0],
-        &uart1_clk[1],
-        &uart2_clk[0],
-        &uart2_clk[1],
-        &uart3_clk[0],
-        &uart3_clk[1],
-        &uart4_clk[0],
-        &uart4_clk[1],
-        &uart5_clk[0],
-        &uart5_clk[1],
-        &uart6_clk[0],
-        &uart6_clk[1],
-        &gpt1_clk[0],
-        &gpt1_clk[1],
-        &gpt2_clk[0],
-        &gpt2_clk[1],
-        &gpt3_clk[0],
-        &gpt3_clk[1],
-        &gpt4_clk[0],
-        &gpt4_clk[1],
-        &gpt5_clk[0],
-        &gpt5_clk[1],
-        &gpt6_clk[0],
-        &gpt6_clk[1],
-        &pwm_clk[0],
-        &pwm_clk[1],
-        &sdhc1_clk[0],
-        &sdhc1_clk[1],
-        &sdhc2_clk[0],
-        &sdhc2_clk[1],
-        &sdhc3_clk[0],
-        &sdhc3_clk[1],
-        &cspi1_clk[0],
-        &cspi1_clk[1],
-        &cspi2_clk[0],
-        &cspi2_clk[1],
-        &cspi3_clk[0],
-        &cspi3_clk[1],
-        &lcdc_clk[0],
-        &lcdc_clk[1],
-        &lcdc_clk[2],
-        &csi_clk[0],
-        &csi_clk[1],
-        &usb_clk[0],
-        &usb_clk[1],
-        &ssi1_clk[0],
-        &ssi1_clk[1],
-        &ssi2_clk[0],
-        &ssi2_clk[1],
-        &nfc_clk,
-        &vpu_clk,
-        &dma_clk,
-        &rtic_clk,
-        &brom_clk,
-        &emma_clk,
-        &slcdc_clk,
-        &fec_clk,
-        &emi_clk,
-        &sahara2_clk,
-        &ata_clk,
-        &mstick1_clk,
-        &wdog_clk,
-        &gpio_clk,
-        &i2c_clk[0],
-        &i2c_clk[1],
-        &iim_clk,
-        &kpp_clk,
-        &owire_clk,
-        &rtc_clk,
-        &scc_clk,
-};
-
-void __init change_external_low_reference(unsigned long new_ref)
-{
-        external_low_reference = new_ref;
-}
-
-unsigned long __init clk_early_get_timer_rate(void)
-{
-        return clk_get_rate(&per_clk[0]);
-}
-
-static void __init probe_mxc_clocks(void)
-{
-        int i;
+static struct clk_lookup lookups[] __initdata = {
+        _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
+        _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
+        _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
+        _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
+        _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
+        _REGISTER_CLOCK("imx-uart.5", NULL, uart6_clk)
+        _REGISTER_CLOCK(NULL, "gpt1", gpt1_clk)
+        _REGISTER_CLOCK(NULL, "gpt2", gpt2_clk)
+        _REGISTER_CLOCK(NULL, "gpt3", gpt3_clk)
+        _REGISTER_CLOCK(NULL, "gpt4", gpt4_clk)
+        _REGISTER_CLOCK(NULL, "gpt5", gpt5_clk)
+        _REGISTER_CLOCK(NULL, "gpt6", gpt6_clk)
+        _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
+        _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
+        _REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk)
+        _REGISTER_CLOCK(NULL, "cspi1", cspi1_clk)
+        _REGISTER_CLOCK(NULL, "cspi2", cspi2_clk)
+        _REGISTER_CLOCK(NULL, "cspi3", cspi3_clk)
+        _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
+        _REGISTER_CLOCK(NULL, "csi", csi_clk)
+        _REGISTER_CLOCK(NULL, "usb", usb_clk)
+        _REGISTER_CLOCK(NULL, "ssi1", ssi1_clk)
+        _REGISTER_CLOCK(NULL, "ssi2", ssi2_clk)
+        _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
+        _REGISTER_CLOCK(NULL, "vpu", vpu_clk)
+        _REGISTER_CLOCK(NULL, "dma", dma_clk)
+        _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
+        _REGISTER_CLOCK(NULL, "brom", brom_clk)
+        _REGISTER_CLOCK(NULL, "emma", emma_clk)
+        _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk)
+        _REGISTER_CLOCK("fec.0", NULL, fec_clk)
+        _REGISTER_CLOCK(NULL, "emi", emi_clk)
+        _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk)
+        _REGISTER_CLOCK(NULL, "ata", ata_clk)
+        _REGISTER_CLOCK(NULL, "mstick", mstick_clk)
+        _REGISTER_CLOCK(NULL, "wdog", wdog_clk)
+        _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
+        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
+        _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
+        _REGISTER_CLOCK(NULL, "iim", iim_clk)
+        _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
+        _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
+        _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
+        _REGISTER_CLOCK(NULL, "scc", scc_clk)
+};
+
+/* Adjust the clock path for TO2 and later */
+static void __init to2_adjust_clocks(void)
+{
+        unsigned long cscr = __raw_readl(CCM_CSCR);
 
         if (mx27_revision() >= CHIP_REV_2_0) {
-                if (CSCR() & 0x8000)
-                        cpu_clk.parent = &mpll_main_clk[0];
+                if (cscr & CCM_CSCR_ARM_SRC)
+                        cpu_clk.parent = &mpll_main1_clk;
 
-                if (!(CSCR() & 0x00800000))
-                        ssi2_clk[0].parent = &spll_clk;
+                if (!(cscr & CCM_CSCR_SSI2))
+                        ssi1_clk.parent = &spll_clk;
 
-                if (!(CSCR() & 0x00400000))
-                        ssi1_clk[0].parent = &spll_clk;
+                if (!(cscr & CCM_CSCR_SSI1))
+                        ssi1_clk.parent = &spll_clk;
 
-                if (!(CSCR() & 0x00200000))
+                if (!(cscr & CCM_CSCR_VPU))
                         vpu_clk.parent = &spll_clk;
         } else {
                 cpu_clk.parent = &mpll_clk;
@@ -1565,11 +693,13 @@ static void __init probe_mxc_clocks(void)
                 cpu_clk.set_rate = NULL;
                 ahb_clk.parent = &mpll_clk;
 
-                for (i = 0; i < sizeof(per_clk) / sizeof(per_clk[0]); i++)
-                        per_clk[i].parent = &mpll_clk;
+                per1_clk.parent = &mpll_clk;
+                per2_clk.parent = &mpll_clk;
+                per3_clk.parent = &mpll_clk;
+                per4_clk.parent = &mpll_clk;
 
-                ssi1_clk[0].parent = &mpll_clk;
-                ssi2_clk[0].parent = &mpll_clk;
+                ssi1_clk.parent = &mpll_clk;
+                ssi2_clk.parent = &mpll_clk;
 
                 vpu_clk.parent = &mpll_clk;
         }
@@ -1579,47 +709,47 @@ static void __init probe_mxc_clocks(void)
  * must be called very early to get information about the
  * available clock rate when the timer framework starts
  */
-int __init mxc_clocks_init(unsigned long fref)
+int __init mx27_clocks_init(unsigned long fref)
 {
-        u32 cscr;
-        struct clk **clkp;
+        u32 cscr = __raw_readl(CCM_CSCR);
+        int i;
 
         external_high_reference = fref;
 
-        /* detect clock reference for both system PLL */
-        cscr = CSCR();
+        /* detect clock reference for both system PLLs */
         if (cscr & CCM_CSCR_MCU)
                 mpll_clk.parent = &ckih_clk;
         else
-                mpll_clk.parent = &ckil_clk;
+                mpll_clk.parent = &fpm_clk;
 
         if (cscr & CCM_CSCR_SP)
                 spll_clk.parent = &ckih_clk;
         else
-                spll_clk.parent = &ckil_clk;
+                spll_clk.parent = &fpm_clk;
 
-        probe_mxc_clocks();
+        to2_adjust_clocks();
 
-        per_clk[0].enable(&per_clk[0]);
-        gpt1_clk[1].enable(&gpt1_clk[1]);
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
 
-        for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++)
-                clk_register(*clkp);
+        /* Turn off all clocks we do not need */
+        __raw_writel(0, CCM_PCCR0);
+        __raw_writel((1 << 10) | (1 << 19), CCM_PCCR1);
 
-        /* Turn off all possible clocks */
-        __raw_writel(CCM_PCCR0_GPT1_MASK, CCM_PCCR0);
-        __raw_writel(CCM_PCCR1_PERCLK1_MASK | CCM_PCCR1_HCLK_EMI_MASK,
-                     CCM_PCCR1);
         spll_clk.disable(&spll_clk);
 
-        /* This will propagate to all children and init all the clock rates */
-
-        clk_enable(&emi_clk);
+        /* enable basic clocks */
+        clk_enable(&per1_clk);
         clk_enable(&gpio_clk);
+        clk_enable(&emi_clk);
         clk_enable(&iim_clk);
-        clk_enable(&gpt1_clk[0]);
+
 #ifdef CONFIG_DEBUG_LL_CONSOLE
-        clk_enable(&uart1_clk[0]);
+        clk_enable(&uart1_clk);
 #endif
+
+        mxc_timer_init(&gpt1_clk);
+
         return 0;
 }
+
diff --git a/arch/arm/mach-mx2/cpu_imx27.c b/arch/arm/mach-mx2/cpu_imx27.c
index 239308fe6652..d9e3bf9644c9 100644
--- a/arch/arm/mach-mx2/cpu_imx27.c
+++ b/arch/arm/mach-mx2/cpu_imx27.c
@@ -26,11 +26,11 @@
 
 #include <mach/hardware.h>
 
-#include "crm_regs.h"
-
 static int cpu_silicon_rev = -1;
 static int cpu_partnumber;
 
+#define SYS_CHIP_ID             0x00    /* The offset of CHIP ID register */
+
 static void query_silicon_parameter(void)
 {
         u32 val;
diff --git a/arch/arm/mach-mx2/crm_regs.h b/arch/arm/mach-mx2/crm_regs.h
index 94644cd0a0fc..749de76b3f95 100644
--- a/arch/arm/mach-mx2/crm_regs.h
+++ b/arch/arm/mach-mx2/crm_regs.h
@@ -38,42 +38,36 @@
 #define CCM_PMCOUNT             (IO_ADDRESS(CCM_BASE_ADDR) + 0x30)
 #define CCM_WKGDCTL             (IO_ADDRESS(CCM_BASE_ADDR) + 0x34)
 
-#define CCM_CSCR_USB_OFFSET     28
-#define CCM_CSCR_USB_MASK       (0x7 << 28)
+#define CCM_CSCR_PRESC_OFFSET   29
+#define CCM_CSCR_PRESC_MASK     (0x7 << CCM_CSCR_PRESC_OFFSET)
+
+#define CCM_CSCR_USB_OFFSET     26
+#define CCM_CSCR_USB_MASK       (0x7 << CCM_CSCR_USB_OFFSET)
 #define CCM_CSCR_SD_OFFSET      24
-#define CCM_CSCR_SD_MASK        (0x3 << 24)
-#define CCM_CSCR_SSI2           (1 << 23)
-#define CCM_CSCR_SSI2_OFFSET    23
-#define CCM_CSCR_SSI1           (1 << 22)
-#define CCM_CSCR_SSI1_OFFSET    22
-#define CCM_CSCR_VPU           (1 << 21)
-#define CCM_CSCR_VPU_OFFSET    21
-#define CCM_CSCR_MSHC           (1 << 20)
-#define CCM_CSCR_SPLLRES        (1 << 19)
-#define CCM_CSCR_MPLLRES        (1 << 18)
+#define CCM_CSCR_SD_MASK        (0x3 << CCM_CSCR_SD_OFFSET)
+#define CCM_CSCR_SPLLRES        (1 << 22)
+#define CCM_CSCR_MPLLRES        (1 << 21)
+#define CCM_CSCR_SSI2_OFFSET    20
+#define CCM_CSCR_SSI2           (1 << CCM_CSCR_SSI2_OFFSET)
+#define CCM_CSCR_SSI1_OFFSET    19
+#define CCM_CSCR_SSI1           (1 << CCM_CSCR_SSI1_OFFSET)
+#define CCM_CSCR_FIR_OFFSET     18
+#define CCM_CSCR_FIR            (1 << CCM_CSCR_FIR_OFFSET)
 #define CCM_CSCR_SP             (1 << 17)
 #define CCM_CSCR_MCU            (1 << 16)
-/* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/
-#define CCM_CSCR_ARM_SRC        (1 << 15)
-#define CCM_CSCR_ARM_OFFSET     12
-#define CCM_CSCR_ARM_MASK       (0x3 << 12)
-/* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/
-#define CCM_CSCR_PRESC_OFFSET   13
-#define CCM_CSCR_PRESC_MASK     (0x7 << 13)
-#define CCM_CSCR_BCLK_OFFSET    9
-#define CCM_CSCR_BCLK_MASK      (0xf << 9)
-#define CCM_CSCR_IPDIV_OFFSET   8
-#define CCM_CSCR_IPDIV          (1 << 8)
-/* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/
-#define CCM_CSCR_AHB_OFFSET     8
-#define CCM_CSCR_AHB_MASK       (0x3 << 8)
-/* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/
+#define CCM_CSCR_BCLK_OFFSET    10
+#define CCM_CSCR_BCLK_MASK      (0xf << CCM_CSCR_BCLK_OFFSET)
+#define CCM_CSCR_IPDIV_OFFSET   9
+#define CCM_CSCR_IPDIV          (1 << CCM_CSCR_IPDIV_OFFSET)
+
 #define CCM_CSCR_OSC26MDIV      (1 << 4)
 #define CCM_CSCR_OSC26M         (1 << 3)
 #define CCM_CSCR_FPM            (1 << 2)
 #define CCM_CSCR_SPEN           (1 << 1)
 #define CCM_CSCR_MPEN           1
 
+
+
 #define CCM_MPCTL0_CPLM         (1 << 31)
 #define CCM_MPCTL0_PD_OFFSET    26
 #define CCM_MPCTL0_PD_MASK      (0xf << 26)
@@ -109,25 +103,14 @@
 
 #define CCM_PCDR0_SSI2BAUDDIV_OFFSET    26
 #define CCM_PCDR0_SSI2BAUDDIV_MASK      (0x3f << 26)
-#define CCM_PCDR0_CLKO_EN               25
-#define CCM_PCDR0_CLKODIV_OFFSET        22
-#define CCM_PCDR0_CLKODIV_MASK          (0x7 << 22)
 #define CCM_PCDR0_SSI1BAUDDIV_OFFSET    16
 #define CCM_PCDR0_SSI1BAUDDIV_MASK      (0x3f << 16)
-/*The difinition for i.MX27 TO2*/
-#define CCM_PCDR0_VPUDIV2_OFFSET        10
-#define CCM_PCDR0_VPUDIV2_MASK          (0x3f << 10)
-#define CCM_PCDR0_NFCDIV2_OFFSET         6
-#define CCM_PCDR0_NFCDIV2_MASK           (0xf << 6)
-#define CCM_PCDR0_MSHCDIV2_MASK          0x3f
-/*The difinition for i.MX27 TO2*/
 #define CCM_PCDR0_NFCDIV_OFFSET         12
 #define CCM_PCDR0_NFCDIV_MASK           (0xf << 12)
-#define CCM_PCDR0_VPUDIV_OFFSET        8
-#define CCM_PCDR0_VPUDIV_MASK          (0xf << 8)
-#define CCM_PCDR0_MSHCDIV_OFFSET        0
-#define CCM_PCDR0_MSHCDIV_MASK          0x1f
-
+#define CCM_PCDR0_48MDIV_OFFSET         5
+#define CCM_PCDR0_48MDIV_MASK           (0x7 << CCM_PCDR0_48MDIV_OFFSET)
+#define CCM_PCDR0_FIRIDIV_OFFSET        0
+#define CCM_PCDR0_FIRIDIV_MASK          0x1f
 #define CCM_PCDR1_PERDIV4_OFFSET        24
 #define CCM_PCDR1_PERDIV4_MASK          (0x3f << 24)
 #define CCM_PCDR1_PERDIV3_OFFSET        16
@@ -137,133 +120,135 @@
 #define CCM_PCDR1_PERDIV1_OFFSET        0
 #define CCM_PCDR1_PERDIV1_MASK          0x3f
 
-#define CCM_PCCR0_CSPI1_OFFSET          31
-#define CCM_PCCR0_CSPI1_MASK            (1 << 31)
-#define CCM_PCCR0_CSPI2_OFFSET          30
-#define CCM_PCCR0_CSPI2_MASK            (1 << 30)
-#define CCM_PCCR0_CSPI3_OFFSET          29
-#define CCM_PCCR0_CSPI3_MASK            (1 << 29)
-#define CCM_PCCR0_DMA_OFFSET            28
-#define CCM_PCCR0_DMA_MASK              (1 << 28)
-#define CCM_PCCR0_EMMA_OFFSET           27
-#define CCM_PCCR0_EMMA_MASK             (1 << 27)
-#define CCM_PCCR0_FEC_OFFSET            26
-#define CCM_PCCR0_FEC_MASK              (1 << 26)
-#define CCM_PCCR0_GPIO_OFFSET           25
-#define CCM_PCCR0_GPIO_MASK             (1 << 25)
-#define CCM_PCCR0_GPT1_OFFSET           24
-#define CCM_PCCR0_GPT1_MASK             (1 << 24)
-#define CCM_PCCR0_GPT2_OFFSET           23
-#define CCM_PCCR0_GPT2_MASK             (1 << 23)
-#define CCM_PCCR0_GPT3_OFFSET           22
-#define CCM_PCCR0_GPT3_MASK             (1 << 22)
-#define CCM_PCCR0_GPT4_OFFSET           21
-#define CCM_PCCR0_GPT4_MASK             (1 << 21)
-#define CCM_PCCR0_GPT5_OFFSET           20
-#define CCM_PCCR0_GPT5_MASK             (1 << 20)
-#define CCM_PCCR0_GPT6_OFFSET           19
-#define CCM_PCCR0_GPT6_MASK             (1 << 19)
-#define CCM_PCCR0_I2C1_OFFSET           18
-#define CCM_PCCR0_I2C1_MASK             (1 << 18)
-#define CCM_PCCR0_I2C2_OFFSET           17
-#define CCM_PCCR0_I2C2_MASK             (1 << 17)
-#define CCM_PCCR0_IIM_OFFSET            16
-#define CCM_PCCR0_IIM_MASK              (1 << 16)
-#define CCM_PCCR0_KPP_OFFSET            15
-#define CCM_PCCR0_KPP_MASK              (1 << 15)
-#define CCM_PCCR0_LCDC_OFFSET           14
-#define CCM_PCCR0_LCDC_MASK             (1 << 14)
-#define CCM_PCCR0_MSHC_OFFSET           13
-#define CCM_PCCR0_MSHC_MASK             (1 << 13)
-#define CCM_PCCR0_OWIRE_OFFSET          12
-#define CCM_PCCR0_OWIRE_MASK            (1 << 12)
-#define CCM_PCCR0_PWM_OFFSET            11
-#define CCM_PCCR0_PWM_MASK              (1 << 11)
-#define CCM_PCCR0_RTC_OFFSET            9
-#define CCM_PCCR0_RTC_MASK              (1 << 9)
-#define CCM_PCCR0_RTIC_OFFSET           8
-#define CCM_PCCR0_RTIC_MASK             (1 << 8)
-#define CCM_PCCR0_SAHARA_OFFSET         7
-#define CCM_PCCR0_SAHARA_MASK           (1 << 7)
-#define CCM_PCCR0_SCC_OFFSET            6
-#define CCM_PCCR0_SCC_MASK              (1 << 6)
-#define CCM_PCCR0_SDHC1_OFFSET          5
-#define CCM_PCCR0_SDHC1_MASK            (1 << 5)
-#define CCM_PCCR0_SDHC2_OFFSET          4
-#define CCM_PCCR0_SDHC2_MASK            (1 << 4)
-#define CCM_PCCR0_SDHC3_OFFSET          3
-#define CCM_PCCR0_SDHC3_MASK            (1 << 3)
-#define CCM_PCCR0_SLCDC_OFFSET          2
-#define CCM_PCCR0_SLCDC_MASK            (1 << 2)
-#define CCM_PCCR0_SSI1_IPG_OFFSET       1
-#define CCM_PCCR0_SSI1_IPG_MASK         (1 << 1)
-#define CCM_PCCR0_SSI2_IPG_OFFSET       0
-#define CCM_PCCR0_SSI2_IPG_MASK         (1 << 0)
+#define CCM_PCCR_HCLK_CSI_OFFSET        31
+#define CCM_PCCR_HCLK_CSI_REG           CCM_PCCR0
+#define CCM_PCCR_HCLK_DMA_OFFSET        30
+#define CCM_PCCR_HCLK_DMA_REG           CCM_PCCR0
+#define CCM_PCCR_HCLK_BROM_OFFSET       28
+#define CCM_PCCR_HCLK_BROM_REG          CCM_PCCR0
+#define CCM_PCCR_HCLK_EMMA_OFFSET       27
+#define CCM_PCCR_HCLK_EMMA_REG          CCM_PCCR0
+#define CCM_PCCR_HCLK_LCDC_OFFSET       26
+#define CCM_PCCR_HCLK_LCDC_REG          CCM_PCCR0
+#define CCM_PCCR_HCLK_SLCDC_OFFSET      25
+#define CCM_PCCR_HCLK_SLCDC_REG         CCM_PCCR0
+#define CCM_PCCR_HCLK_USBOTG_OFFSET     24
+#define CCM_PCCR_HCLK_USBOTG_REG        CCM_PCCR0
+#define CCM_PCCR_HCLK_BMI_OFFSET        23
+#define CCM_PCCR_BMI_MASK               (1 << CCM_PCCR_BMI_MASK)
+#define CCM_PCCR_HCLK_BMI_REG           CCM_PCCR0
+#define CCM_PCCR_PERCLK4_OFFSET         22
+#define CCM_PCCR_PERCLK4_REG            CCM_PCCR0
+#define CCM_PCCR_SLCDC_OFFSET           21
+#define CCM_PCCR_SLCDC_REG              CCM_PCCR0
+#define CCM_PCCR_FIRI_BAUD_OFFSET       20
+#define CCM_PCCR_FIRI_BAUD_MASK         (1 << CCM_PCCR_FIRI_BAUD_MASK)
+#define CCM_PCCR_FIRI_BAUD_REG          CCM_PCCR0
+#define CCM_PCCR_NFC_OFFSET             19
+#define CCM_PCCR_NFC_REG                CCM_PCCR0
+#define CCM_PCCR_LCDC_OFFSET            18
+#define CCM_PCCR_LCDC_REG               CCM_PCCR0
+#define CCM_PCCR_SSI1_BAUD_OFFSET       17
+#define CCM_PCCR_SSI1_BAUD_REG          CCM_PCCR0
+#define CCM_PCCR_SSI2_BAUD_OFFSET       16
+#define CCM_PCCR_SSI2_BAUD_REG          CCM_PCCR0
+#define CCM_PCCR_EMMA_OFFSET            15
+#define CCM_PCCR_EMMA_REG               CCM_PCCR0
+#define CCM_PCCR_USBOTG_OFFSET          14
+#define CCM_PCCR_USBOTG_REG             CCM_PCCR0
+#define CCM_PCCR_DMA_OFFSET             13
+#define CCM_PCCR_DMA_REG                CCM_PCCR0
+#define CCM_PCCR_I2C1_OFFSET            12
+#define CCM_PCCR_I2C1_REG               CCM_PCCR0
+#define CCM_PCCR_GPIO_OFFSET            11
+#define CCM_PCCR_GPIO_REG               CCM_PCCR0
+#define CCM_PCCR_SDHC2_OFFSET           10
+#define CCM_PCCR_SDHC2_REG              CCM_PCCR0
+#define CCM_PCCR_SDHC1_OFFSET           9
+#define CCM_PCCR_SDHC1_REG              CCM_PCCR0
+#define CCM_PCCR_FIRI_OFFSET            8
+#define CCM_PCCR_FIRI_MASK              (1 << CCM_PCCR_BAUD_MASK)
+#define CCM_PCCR_FIRI_REG               CCM_PCCR0
+#define CCM_PCCR_SSI2_IPG_OFFSET        7
+#define CCM_PCCR_SSI2_REG               CCM_PCCR0
+#define CCM_PCCR_SSI1_IPG_OFFSET        6
+#define CCM_PCCR_SSI1_REG               CCM_PCCR0
+#define CCM_PCCR_CSPI2_OFFSET           5
+#define CCM_PCCR_CSPI2_REG              CCM_PCCR0
+#define CCM_PCCR_CSPI1_OFFSET           4
+#define CCM_PCCR_CSPI1_REG              CCM_PCCR0
+#define CCM_PCCR_UART4_OFFSET           3
+#define CCM_PCCR_UART4_REG              CCM_PCCR0
+#define CCM_PCCR_UART3_OFFSET           2
+#define CCM_PCCR_UART3_REG              CCM_PCCR0
+#define CCM_PCCR_UART2_OFFSET           1
+#define CCM_PCCR_UART2_REG              CCM_PCCR0
+#define CCM_PCCR_UART1_OFFSET           0
+#define CCM_PCCR_UART1_REG              CCM_PCCR0
+
+#define CCM_PCCR_OWIRE_OFFSET           31
+#define CCM_PCCR_OWIRE_REG              CCM_PCCR1
+#define CCM_PCCR_KPP_OFFSET             30
+#define CCM_PCCR_KPP_REG                CCM_PCCR1
+#define CCM_PCCR_RTC_OFFSET             29
+#define CCM_PCCR_RTC_REG                CCM_PCCR1
+#define CCM_PCCR_PWM_OFFSET             28
+#define CCM_PCCR_PWM_REG                CCM_PCCR1
+#define CCM_PCCR_GPT3_OFFSET            27
+#define CCM_PCCR_GPT3_REG               CCM_PCCR1
+#define CCM_PCCR_GPT2_OFFSET            26
+#define CCM_PCCR_GPT2_REG               CCM_PCCR1
+#define CCM_PCCR_GPT1_OFFSET            25
+#define CCM_PCCR_GPT1_REG               CCM_PCCR1
+#define CCM_PCCR_WDT_OFFSET             24
+#define CCM_PCCR_WDT_REG                CCM_PCCR1
+#define CCM_PCCR_CSPI3_OFFSET           23
+#define CCM_PCCR_CSPI3_REG              CCM_PCCR1
+
+#define CCM_PCCR_CSPI1_MASK             (1 << CCM_PCCR_CSPI1_OFFSET)
+#define CCM_PCCR_CSPI2_MASK             (1 << CCM_PCCR_CSPI2_OFFSET)
+#define CCM_PCCR_CSPI3_MASK             (1 << CCM_PCCR_CSPI3_OFFSET)
+#define CCM_PCCR_DMA_MASK               (1 << CCM_PCCR_DMA_OFFSET)
+#define CCM_PCCR_EMMA_MASK              (1 << CCM_PCCR_EMMA_OFFSET)
+#define CCM_PCCR_GPIO_MASK              (1 << CCM_PCCR_GPIO_OFFSET)
+#define CCM_PCCR_GPT1_MASK              (1 << CCM_PCCR_GPT1_OFFSET)
+#define CCM_PCCR_GPT2_MASK              (1 << CCM_PCCR_GPT2_OFFSET)
+#define CCM_PCCR_GPT3_MASK              (1 << CCM_PCCR_GPT3_OFFSET)
+#define CCM_PCCR_HCLK_BROM_MASK         (1 << CCM_PCCR_HCLK_BROM_OFFSET)
+#define CCM_PCCR_HCLK_CSI_MASK          (1 << CCM_PCCR_HCLK_CSI_OFFSET)
+#define CCM_PCCR_HCLK_DMA_MASK          (1 << CCM_PCCR_HCLK_DMA_OFFSET)
+#define CCM_PCCR_HCLK_EMMA_MASK         (1 << CCM_PCCR_HCLK_EMMA_OFFSET)
+#define CCM_PCCR_HCLK_LCDC_MASK         (1 << CCM_PCCR_HCLK_LCDC_OFFSET)
+#define CCM_PCCR_HCLK_SLCDC_MASK        (1 << CCM_PCCR_HCLK_SLCDC_OFFSET)
+#define CCM_PCCR_HCLK_USBOTG_MASK       (1 << CCM_PCCR_HCLK_USBOTG_OFFSET)
+#define CCM_PCCR_I2C1_MASK              (1 << CCM_PCCR_I2C1_OFFSET)
+#define CCM_PCCR_KPP_MASK               (1 << CCM_PCCR_KPP_OFFSET)
+#define CCM_PCCR_LCDC_MASK              (1 << CCM_PCCR_LCDC_OFFSET)
+#define CCM_PCCR_NFC_MASK               (1 << CCM_PCCR_NFC_OFFSET)
+#define CCM_PCCR_OWIRE_MASK             (1 << CCM_PCCR_OWIRE_OFFSET)
+#define CCM_PCCR_PERCLK4_MASK           (1 << CCM_PCCR_PERCLK4_OFFSET)
+#define CCM_PCCR_PWM_MASK               (1 << CCM_PCCR_PWM_OFFSET)
+#define CCM_PCCR_RTC_MASK               (1 << CCM_PCCR_RTC_OFFSET)
+#define CCM_PCCR_SDHC1_MASK             (1 << CCM_PCCR_SDHC1_OFFSET)
+#define CCM_PCCR_SDHC2_MASK             (1 << CCM_PCCR_SDHC2_OFFSET)
+#define CCM_PCCR_SLCDC_MASK             (1 << CCM_PCCR_SLCDC_OFFSET)
+#define CCM_PCCR_SSI1_BAUD_MASK         (1 << CCM_PCCR_SSI1_BAUD_OFFSET)
+#define CCM_PCCR_SSI1_IPG_MASK          (1 << CCM_PCCR_SSI1_IPG_OFFSET)
+#define CCM_PCCR_SSI2_BAUD_MASK         (1 << CCM_PCCR_SSI2_BAUD_OFFSET)
+#define CCM_PCCR_SSI2_IPG_MASK          (1 << CCM_PCCR_SSI2_IPG_OFFSET)
+#define CCM_PCCR_UART1_MASK             (1 << CCM_PCCR_UART1_OFFSET)
+#define CCM_PCCR_UART2_MASK             (1 << CCM_PCCR_UART2_OFFSET)
+#define CCM_PCCR_UART3_MASK             (1 << CCM_PCCR_UART3_OFFSET)
+#define CCM_PCCR_UART4_MASK             (1 << CCM_PCCR_UART4_OFFSET)
+#define CCM_PCCR_USBOTG_MASK            (1 << CCM_PCCR_USBOTG_OFFSET)
+#define CCM_PCCR_WDT_MASK               (1 << CCM_PCCR_WDT_OFFSET)
 
-#define CCM_PCCR1_UART1_OFFSET          31
-#define CCM_PCCR1_UART1_MASK            (1 << 31)
-#define CCM_PCCR1_UART2_OFFSET          30
-#define CCM_PCCR1_UART2_MASK            (1 << 30)
-#define CCM_PCCR1_UART3_OFFSET          29
-#define CCM_PCCR1_UART3_MASK            (1 << 29)
-#define CCM_PCCR1_UART4_OFFSET          28
-#define CCM_PCCR1_UART4_MASK            (1 << 28)
-#define CCM_PCCR1_UART5_OFFSET          27
-#define CCM_PCCR1_UART5_MASK            (1 << 27)
-#define CCM_PCCR1_UART6_OFFSET          26
-#define CCM_PCCR1_UART6_MASK            (1 << 26)
-#define CCM_PCCR1_USBOTG_OFFSET         25
-#define CCM_PCCR1_USBOTG_MASK           (1 << 25)
-#define CCM_PCCR1_WDT_OFFSET            24
-#define CCM_PCCR1_WDT_MASK              (1 << 24)
-#define CCM_PCCR1_HCLK_ATA_OFFSET       23
-#define CCM_PCCR1_HCLK_ATA_MASK         (1 << 23)
-#define CCM_PCCR1_HCLK_BROM_OFFSET      22
-#define CCM_PCCR1_HCLK_BROM_MASK        (1 << 22)
-#define CCM_PCCR1_HCLK_CSI_OFFSET       21
-#define CCM_PCCR1_HCLK_CSI_MASK         (1 << 21)
-#define CCM_PCCR1_HCLK_DMA_OFFSET       20
-#define CCM_PCCR1_HCLK_DMA_MASK         (1 << 20)
-#define CCM_PCCR1_HCLK_EMI_OFFSET       19
-#define CCM_PCCR1_HCLK_EMI_MASK         (1 << 19)
-#define CCM_PCCR1_HCLK_EMMA_OFFSET      18
-#define CCM_PCCR1_HCLK_EMMA_MASK        (1 << 18)
-#define CCM_PCCR1_HCLK_FEC_OFFSET       17
-#define CCM_PCCR1_HCLK_FEC_MASK         (1 << 17)
-#define CCM_PCCR1_HCLK_VPU_OFFSET       16
-#define CCM_PCCR1_HCLK_VPU_MASK         (1 << 16)
-#define CCM_PCCR1_HCLK_LCDC_OFFSET      15
-#define CCM_PCCR1_HCLK_LCDC_MASK        (1 << 15)
-#define CCM_PCCR1_HCLK_RTIC_OFFSET      14
-#define CCM_PCCR1_HCLK_RTIC_MASK        (1 << 14)
-#define CCM_PCCR1_HCLK_SAHARA_OFFSET    13
-#define CCM_PCCR1_HCLK_SAHARA_MASK      (1 << 13)
-#define CCM_PCCR1_HCLK_SLCDC_OFFSET     12
-#define CCM_PCCR1_HCLK_SLCDC_MASK       (1 << 12)
-#define CCM_PCCR1_HCLK_USBOTG_OFFSET    11
-#define CCM_PCCR1_HCLK_USBOTG_MASK      (1 << 11)
-#define CCM_PCCR1_PERCLK1_OFFSET        10
-#define CCM_PCCR1_PERCLK1_MASK          (1 << 10)
-#define CCM_PCCR1_PERCLK2_OFFSET        9
-#define CCM_PCCR1_PERCLK2_MASK          (1 << 9)
-#define CCM_PCCR1_PERCLK3_OFFSET        8
-#define CCM_PCCR1_PERCLK3_MASK          (1 << 8)
-#define CCM_PCCR1_PERCLK4_OFFSET        7
-#define CCM_PCCR1_PERCLK4_MASK          (1 << 7)
-#define CCM_PCCR1_VPU_BAUD_OFFSET       6
-#define CCM_PCCR1_VPU_BAUD_MASK         (1 << 6)
-#define CCM_PCCR1_SSI1_BAUD_OFFSET      5
-#define CCM_PCCR1_SSI1_BAUD_MASK        (1 << 5)
-#define CCM_PCCR1_SSI2_BAUD_OFFSET      4
-#define CCM_PCCR1_SSI2_BAUD_MASK        (1 << 4)
-#define CCM_PCCR1_NFC_BAUD_OFFSET       3
-#define CCM_PCCR1_NFC_BAUD_MASK         (1 << 3)
-#define CCM_PCCR1_MSHC_BAUD_OFFSET      2
-#define CCM_PCCR1_MSHC_BAUD_MASK        (1 << 2)
 
 #define CCM_CCSR_32KSR          (1 << 15)
+
 #define CCM_CCSR_CLKMODE1       (1 << 9)
 #define CCM_CCSR_CLKMODE0       (1 << 8)
+
 #define CCM_CCSR_CLKOSEL_OFFSET 0
 #define CCM_CCSR_CLKOSEL_MASK   0x1f
 
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
index 2f9240be1c76..a0f1b3674327 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-mx2/devices.c
@@ -34,6 +34,10 @@
 
 #include <mach/irqs.h>
 #include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/mmc.h>
+
+#include "devices.h"
 
 /*
  * Resource definition for the MXC IrDA
@@ -225,37 +229,215 @@ struct platform_device mxc_nand_device = {
         .resource = mxc_nand_resources,
 };
 
+/*
+ * lcdc:
+ * - i.MX1: the basic controller
+ * - i.MX21: to be checked
+ * - i.MX27: like i.MX1, with slightly variations
+ */
+static struct resource mxc_fb[] = {
+        {
+                .start = LCDC_BASE_ADDR,
+                .end   = LCDC_BASE_ADDR + 0xFFF,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = MXC_INT_LCDC,
+                .end   = MXC_INT_LCDC,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+/* mxc lcd driver */
+struct platform_device mxc_fb_device = {
+        .name = "imx-fb",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_fb),
+        .resource = mxc_fb,
+        .dev = {
+                .coherent_dma_mask = 0xFFFFFFFF,
+        },
+};
+
+#ifdef CONFIG_MACH_MX27
+static struct resource mxc_fec_resources[] = {
+        {
+                .start  = FEC_BASE_ADDR,
+                .end    = FEC_BASE_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM
+        }, {
+                .start  = MXC_INT_FEC,
+                .end    = MXC_INT_FEC,
+                .flags  = IORESOURCE_IRQ
+        },
+};
+
+struct platform_device mxc_fec_device = {
+        .name = "fec",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_fec_resources),
+        .resource = mxc_fec_resources,
+};
+#endif
+
+static struct resource mxc_i2c_1_resources[] = {
+        [0] = {
+                .start  = I2C_BASE_ADDR,
+                .end    = I2C_BASE_ADDR + 0x0fff,
+                .flags  = IORESOURCE_MEM
+        },
+        [1] = {
+                .start  = MXC_INT_I2C,
+                .end    = MXC_INT_I2C,
+                .flags  = IORESOURCE_IRQ
+        }
+};
+
+struct platform_device mxc_i2c_device0 = {
+        .name = "imx-i2c",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
+        .resource = mxc_i2c_1_resources
+};
+
+#ifdef CONFIG_MACH_MX27
+static struct resource mxc_i2c_2_resources[] = {
+        [0] = {
+                .start  = I2C2_BASE_ADDR,
+                .end    = I2C2_BASE_ADDR + 0x0fff,
+                .flags  = IORESOURCE_MEM
+        },
+        [1] = {
+                .start  = MXC_INT_I2C2,
+                .end    = MXC_INT_I2C2,
+                .flags  = IORESOURCE_IRQ
+        }
+};
+
+struct platform_device mxc_i2c_device1 = {
+        .name = "imx-i2c",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
+        .resource = mxc_i2c_2_resources
+};
+#endif
+
+static struct resource mxc_pwm_resources[] = {
+        [0] = {
+                .start  = PWM_BASE_ADDR,
+                .end    = PWM_BASE_ADDR + 0x0fff,
+                .flags  = IORESOURCE_MEM
+        },
+        [1] = {
+                .start   = MXC_INT_PWM,
+                .end     = MXC_INT_PWM,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_pwm_device = {
+        .name = "mxc_pwm",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_pwm_resources),
+        .resource = mxc_pwm_resources
+};
+
+/*
+ * Resource definition for the MXC SDHC
+ */
+static struct resource mxc_sdhc1_resources[] = {
+        [0] = {
+                        .start = SDHC1_BASE_ADDR,
+                        .end   = SDHC1_BASE_ADDR + SZ_4K - 1,
+                        .flags = IORESOURCE_MEM,
+                        },
+        [1] = {
+                        .start = MXC_INT_SDHC1,
+                        .end   = MXC_INT_SDHC1,
+                        .flags = IORESOURCE_IRQ,
+                        },
+        [2] = {
+                        .start  = DMA_REQ_SDHC1,
+                        .end    = DMA_REQ_SDHC1,
+                        .flags  = IORESOURCE_DMA
+                },
+};
+
+static u64 mxc_sdhc1_dmamask = 0xffffffffUL;
+
+struct platform_device mxc_sdhc_device0 = {
+       .name           = "mxc-mmc",
+       .id             = 0,
+       .dev            = {
+               .dma_mask = &mxc_sdhc1_dmamask,
+               .coherent_dma_mask = 0xffffffff,
+       },
+       .num_resources  = ARRAY_SIZE(mxc_sdhc1_resources),
+       .resource       = mxc_sdhc1_resources,
+};
+
+static struct resource mxc_sdhc2_resources[] = {
+        [0] = {
+                        .start = SDHC2_BASE_ADDR,
+                        .end   = SDHC2_BASE_ADDR + SZ_4K - 1,
+                        .flags = IORESOURCE_MEM,
+                        },
+        [1] = {
+                        .start = MXC_INT_SDHC2,
+                        .end   = MXC_INT_SDHC2,
+                        .flags = IORESOURCE_IRQ,
+                        },
+        [2] = {
+                        .start  = DMA_REQ_SDHC2,
+                        .end    = DMA_REQ_SDHC2,
+                        .flags  = IORESOURCE_DMA
+                },
+};
+
+static u64 mxc_sdhc2_dmamask = 0xffffffffUL;
+
+struct platform_device mxc_sdhc_device1 = {
+       .name           = "mxc-mmc",
+       .id             = 1,
+       .dev            = {
+               .dma_mask = &mxc_sdhc2_dmamask,
+               .coherent_dma_mask = 0xffffffff,
+       },
+       .num_resources  = ARRAY_SIZE(mxc_sdhc2_resources),
+       .resource       = mxc_sdhc2_resources,
+};
+
 /* GPIO port description */
 static struct mxc_gpio_port imx_gpio_ports[] = {
         [0] = {
                 .chip.label = "gpio-0",
                 .irq = MXC_INT_GPIO,
-                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 0),
+                .base = IO_ADDRESS(GPIO_BASE_ADDR),
                 .virtual_irq_start = MXC_GPIO_IRQ_START,
         },
         [1] = {
                 .chip.label = "gpio-1",
-                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 1),
+                .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
         },
         [2] = {
                 .chip.label = "gpio-2",
-                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 2),
+                .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
         },
         [3] = {
                 .chip.label = "gpio-3",
-                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 3),
+                .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
         },
         [4] = {
                 .chip.label = "gpio-4",
-                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 4),
+                .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
         },
         [5] = {
                 .chip.label = "gpio-5",
-                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 5),
+                .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
         }
 };
diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h
index 1e8cb577a642..049005bb6aa9 100644
--- a/arch/arm/mach-mx2/devices.h
+++ b/arch/arm/mach-mx2/devices.h
@@ -1,4 +1,3 @@
-
 extern struct platform_device mxc_gpt1;
 extern struct platform_device mxc_gpt2;
 extern struct platform_device mxc_gpt3;
@@ -14,3 +13,10 @@ extern struct platform_device mxc_uart_device4;
 extern struct platform_device mxc_uart_device5;
 extern struct platform_device mxc_w1_master_device;
 extern struct platform_device mxc_nand_device;
+extern struct platform_device mxc_fb_device;
+extern struct platform_device mxc_fec_device;
+extern struct platform_device mxc_pwm_device;
+extern struct platform_device mxc_i2c_device0;
+extern struct platform_device mxc_i2c_device1;
+extern struct platform_device mxc_sdhc_device0;
+extern struct platform_device mxc_sdhc_device1;
diff --git a/arch/arm/mach-mx2/generic.c b/arch/arm/mach-mx2/generic.c
index dea6521d4d5c..bd51dd04948e 100644
--- a/arch/arm/mach-mx2/generic.c
+++ b/arch/arm/mach-mx2/generic.c
@@ -21,6 +21,7 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <mach/hardware.h>
+#include <mach/common.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
 
diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mx27ads.c
index 2b5c67f54571..4a3b097adc12 100644
--- a/arch/arm/mach-mx2/mx27ads.c
+++ b/arch/arm/mach-mx2/mx27ads.c
@@ -31,7 +31,7 @@
 #include <asm/mach/map.h>
 #include <mach/gpio.h>
 #include <mach/imx-uart.h>
-#include <mach/iomux-mx1-mx2.h>
+#include <mach/iomux.h>
 #include <mach/board-mx27ads.h>
 
 #include "devices.h"
@@ -135,6 +135,7 @@ static int uart_mxc_port3_exit(struct platform_device *pdev)
 {
         mxc_gpio_release_multiple_pins(mxc_uart3_pins,
                         ARRAY_SIZE(mxc_uart3_pins));
+        return 0;
 }
 
 static int mxc_uart4_pins[] = {
@@ -179,6 +180,7 @@ static int uart_mxc_port5_exit(struct platform_device *pdev)
 
 static struct platform_device *platform_devices[] __initdata = {
         &mx27ads_nor_mtd_device,
+        &mxc_fec_device,
 };
 
 static int mxc_fec_pins[] = {
@@ -196,7 +198,7 @@ static int mxc_fec_pins[] = {
         PD11_AOUT_FEC_TX_CLK,
         PD12_AOUT_FEC_RXD0,
         PD13_AOUT_FEC_RX_DV,
-        PD14_AOUT_FEC_CLR,
+        PD14_AOUT_FEC_RX_CLK,
         PD15_AOUT_FEC_COL,
         PD16_AIN_FEC_TX_ER,
         PF23_AIN_FEC_TX_EN
@@ -208,12 +210,6 @@ static void gpio_fec_active(void)
                         ARRAY_SIZE(mxc_fec_pins), "FEC");
 }
 
-static void gpio_fec_inactive(void)
-{
-        mxc_gpio_release_multiple_pins(mxc_fec_pins,
-                        ARRAY_SIZE(mxc_fec_pins));
-}
-
 static struct imxuart_platform_data uart_pdata[] = {
         {
                 .init = uart_mxc_port0_init,
@@ -263,11 +259,10 @@ static void __init mx27ads_timer_init(void)
         if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
                 fref = 27000000;
 
-        mxc_clocks_init(fref);
-        mxc_timer_init("gpt_clk.0");
+        mx27_clocks_init(fref);
 }
 
-struct sys_timer mx27ads_timer = {
+static struct sys_timer mx27ads_timer = {
         .init   = mx27ads_timer_init,
 };
 
@@ -280,7 +275,7 @@ static struct map_desc mx27ads_io_desc[] __initdata = {
         },
 };
 
-void __init mx27ads_map_io(void)
+static void __init mx27ads_map_io(void)
 {
         mxc_map_io();
         iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/pcm038.c
index dfd4156da7d5..aa4eaa61d1b5 100644
--- a/arch/arm/mach-mx2/pcm038.c
+++ b/arch/arm/mach-mx2/pcm038.c
@@ -20,11 +20,18 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/plat-ram.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/iomux-mx1-mx2.h>
+#include <mach/iomux.h>
+#ifdef CONFIG_I2C_IMX
+#include <mach/i2c.h>
+#endif
 #include <asm/mach/time.h>
 #include <mach/imx-uart.h>
 #include <mach/board-pcm038.h>
@@ -121,10 +128,10 @@ static int uart_mxc_port1_exit(struct platform_device *pdev)
         return 0;
 }
 
-static int mxc_uart2_pins[] = { PE10_PF_UART3_CTS,
+static int mxc_uart2_pins[] = { PE8_PF_UART3_TXD,
                                 PE9_PF_UART3_RXD,
                                 PE10_PF_UART3_CTS,
-                                PE9_PF_UART3_RXD };
+                                PE11_PF_UART3_RTS };
 
 static int uart_mxc_port2_init(struct platform_device *pdev)
 {
@@ -170,7 +177,7 @@ static int mxc_fec_pins[] = {
         PD11_AOUT_FEC_TX_CLK,
         PD12_AOUT_FEC_RXD0,
         PD13_AOUT_FEC_RX_DV,
-        PD14_AOUT_FEC_CLR,
+        PD14_AOUT_FEC_RX_CLK,
         PD15_AOUT_FEC_COL,
         PD16_AIN_FEC_TX_ER,
         PF23_AIN_FEC_TX_EN
@@ -182,12 +189,6 @@ static void gpio_fec_active(void)
                         ARRAY_SIZE(mxc_fec_pins), "FEC");
 }
 
-static void gpio_fec_inactive(void)
-{
-        mxc_gpio_release_multiple_pins(mxc_fec_pins,
-                        ARRAY_SIZE(mxc_fec_pins));
-}
-
 static struct mxc_nand_platform_data pcm038_nand_board_info = {
         .width = 1,
         .hw_ecc = 1,
@@ -196,6 +197,7 @@ static struct mxc_nand_platform_data pcm038_nand_board_info = {
 static struct platform_device *platform_devices[] __initdata = {
         &pcm038_nor_mtd_device,
         &mxc_w1_master_device,
+        &mxc_fec_device,
         &pcm038_sram_mtd_device,
 };
 
@@ -208,6 +210,51 @@ static void __init pcm038_init_sram(void)
         __raw_writel(0x22220a00, CSCR_A(1));
 }
 
+#ifdef CONFIG_I2C_IMX
+static int mxc_i2c1_pins[] = {
+        PC5_PF_I2C2_SDA,
+        PC6_PF_I2C2_SCL
+};
+
+static int pcm038_i2c_1_init(struct device *dev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins),
+                        "I2C1");
+}
+
+static void pcm038_i2c_1_exit(struct device *dev)
+{
+        mxc_gpio_release_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins));
+}
+
+static struct imxi2c_platform_data pcm038_i2c_1_data = {
+        .bitrate = 100000,
+        .init = pcm038_i2c_1_init,
+        .exit = pcm038_i2c_1_exit,
+};
+
+static struct at24_platform_data board_eeprom = {
+        .byte_len = 4096,
+        .page_size = 32,
+        .flags = AT24_FLAG_ADDR16,
+};
+
+static struct i2c_board_info pcm038_i2c_devices[] = {
+        [0] = {
+                I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
+                .platform_data = &board_eeprom,
+        },
+        [1] = {
+                I2C_BOARD_INFO("rtc-pcf8563", 0x51),
+                .type = "pcf8563"
+        },
+        [2] = {
+                I2C_BOARD_INFO("lm75", 0x4a),
+                .type = "lm75"
+        }
+};
+#endif
+
 static void __init pcm038_init(void)
 {
         gpio_fec_active();
@@ -217,9 +264,17 @@ static void __init pcm038_init(void)
         mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
         mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
 
-        mxc_gpio_mode(PE16_AF_RTCK); /* OWIRE */
+        mxc_gpio_mode(PE16_AF_OWIRE);
         mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info);
 
+#ifdef CONFIG_I2C_IMX
+        /* only the i2c master 1 is used on this CPU card */
+        i2c_register_board_info(1, pcm038_i2c_devices,
+                                ARRAY_SIZE(pcm038_i2c_devices));
+
+        mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data);
+#endif
+
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 
 #ifdef CONFIG_MACH_PCM970_BASEBOARD
@@ -229,11 +284,10 @@ static void __init pcm038_init(void)
 
 static void __init pcm038_timer_init(void)
 {
-        mxc_clocks_init(26000000);
-        mxc_timer_init("gpt_clk.0");
+        mx27_clocks_init(26000000);
 }
 
-struct sys_timer pcm038_timer = {
+static struct sys_timer pcm038_timer = {
         .init = pcm038_timer_init,
 };
 
diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-mx2/pcm970-baseboard.c
index a560cd6ad23d..bf4e520bc1bc 100644
--- a/arch/arm/mach-mx2/pcm970-baseboard.c
+++ b/arch/arm/mach-mx2/pcm970-baseboard.c
@@ -17,9 +17,138 @@
  */
 
 #include <linux/platform_device.h>
-#include <mach/hardware.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+
 #include <asm/mach/arch.h>
 
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/mmc.h>
+#include <mach/imxfb.h>
+#include <mach/iomux.h>
+
+#include "devices.h"
+
+static int pcm970_sdhc2_get_ro(struct device *dev)
+{
+        return gpio_get_value(GPIO_PORTC + 28);
+}
+
+static int pcm970_sdhc2_pins[] = {
+        PB4_PF_SD2_D0,
+        PB5_PF_SD2_D1,
+        PB6_PF_SD2_D2,
+        PB7_PF_SD2_D3,
+        PB8_PF_SD2_CMD,
+        PB9_PF_SD2_CLK,
+};
+
+static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void *data)
+{
+        int ret;
+
+        ret = mxc_gpio_setup_multiple_pins(pcm970_sdhc2_pins,
+                ARRAY_SIZE(pcm970_sdhc2_pins), "sdhc2");
+        if(ret)
+                return ret;
+
+        ret = request_irq(IRQ_GPIOC(29), detect_irq, 0,
+                                "imx-mmc-detect", data);
+        if (ret)
+                goto out_release_gpio;
+
+        set_irq_type(IRQ_GPIOC(29), IRQF_TRIGGER_FALLING);
+
+        ret = gpio_request(GPIO_PORTC + 28, "imx-mmc-ro");
+        if (ret)
+                goto out_release_gpio;
+
+        mxc_gpio_mode((GPIO_PORTC | 28) | GPIO_GPIO | GPIO_IN);
+        gpio_direction_input(GPIO_PORTC + 28);
+
+        return 0;
+
+out_release_gpio:
+        mxc_gpio_release_multiple_pins(pcm970_sdhc2_pins,
+                        ARRAY_SIZE(pcm970_sdhc2_pins));
+        return ret;
+}
+
+static void pcm970_sdhc2_exit(struct device *dev, void *data)
+{
+        free_irq(IRQ_GPIOC(29), data);
+        gpio_free(GPIO_PORTC + 28);
+        mxc_gpio_release_multiple_pins(pcm970_sdhc2_pins,
+                        ARRAY_SIZE(pcm970_sdhc2_pins));
+}
+
+static struct imxmmc_platform_data sdhc_pdata = {
+        .get_ro = pcm970_sdhc2_get_ro,
+        .init = pcm970_sdhc2_init,
+        .exit = pcm970_sdhc2_exit,
+};
+
+static int mxc_fb_pins[] = {
+        PA5_PF_LSCLK,   PA6_PF_LD0,     PA7_PF_LD1,     PA8_PF_LD2,
+        PA9_PF_LD3,     PA10_PF_LD4,    PA11_PF_LD5,    PA12_PF_LD6,
+        PA13_PF_LD7,    PA14_PF_LD8,    PA15_PF_LD9,    PA16_PF_LD10,
+        PA17_PF_LD11,   PA18_PF_LD12,   PA19_PF_LD13,   PA20_PF_LD14,
+        PA21_PF_LD15,   PA22_PF_LD16,   PA23_PF_LD17,   PA24_PF_REV,
+        PA25_PF_CLS,    PA26_PF_PS,     PA27_PF_SPL_SPR, PA28_PF_HSYNC,
+        PA29_PF_VSYNC,  PA30_PF_CONTRAST, PA31_PF_OE_ACD
+};
+
+static int pcm038_fb_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_fb_pins,
+                        ARRAY_SIZE(mxc_fb_pins), "FB");
+}
+
+static int pcm038_fb_exit(struct platform_device *pdev)
+{
+        mxc_gpio_release_multiple_pins(mxc_fb_pins, ARRAY_SIZE(mxc_fb_pins));
+
+        return 0;
+}
+
+/*
+ * Connected is a portrait Sharp-QVGA display
+ * of type: LQ035Q7DH06
+ */
+static struct imx_fb_platform_data pcm038_fb_data = {
+        .pixclock       = 188679, /* in ps (5.3MHz) */
+        .xres           = 240,
+        .yres           = 320,
+
+        .bpp            = 16,
+        .hsync_len      = 7,
+        .left_margin    = 5,
+        .right_margin   = 16,
+
+        .vsync_len      = 1,
+        .upper_margin   = 7,
+        .lower_margin   = 9,
+        .fixed_screen_cpu = 0,
+
+        /*
+         * - HSYNC active high
+         * - VSYNC active high
+         * - clk notenabled while idle
+         * - clock not inverted
+         * - data not inverted
+         * - data enable low active
+         * - enable sharp mode
+         */
+        .pcr            = 0xFA0080C0,
+        .pwmr           = 0x00A903FF,
+        .lscr1          = 0x00120300,
+        .dmacr          = 0x00020010,
+
+        .init = pcm038_fb_init,
+        .exit = pcm038_fb_exit,
+};
+
 /*
  * system init for baseboard usage. Will be called by pcm038 init.
  *
@@ -28,4 +157,6 @@
  */
 void __init pcm970_baseboard_init(void)
 {
+        mxc_register_device(&mxc_fb_device, &pcm038_fb_data);
+        mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
 }
diff --git a/arch/arm/mach-mx2/serial.c b/arch/arm/mach-mx2/serial.c
index 16debc296dad..40a485cdc10e 100644
--- a/arch/arm/mach-mx2/serial.c
+++ b/arch/arm/mach-mx2/serial.c
@@ -22,6 +22,7 @@
 #include <linux/serial.h>
 #include <mach/hardware.h>
 #include <mach/imx-uart.h>
+#include "devices.h"
 
 static struct resource uart0[] = {
         {
@@ -99,6 +100,7 @@ struct platform_device mxc_uart_device3 = {
         .num_resources = ARRAY_SIZE(uart3),
 };
 
+#ifdef CONFIG_MACH_MX27
 static struct resource uart4[] = {
         {
                 .start = UART5_BASE_ADDR,
@@ -136,3 +138,4 @@ struct platform_device mxc_uart_device5 = {
         .resource = uart5,
         .num_resources = ARRAY_SIZE(uart5),
 };
+#endif
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index e79659e8176e..d6235583e979 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -1,21 +1,40 @@
-menu "MX3 Options"
-        depends on ARCH_MX3
+if ARCH_MX3
+
+config ARCH_MX31
+        bool
+
+config ARCH_MX35
+        bool
+
+comment "MX3 platforms:"
 
 config MACH_MX31ADS
         bool "Support MX31ADS platforms"
+        select ARCH_MX31
         default y
         help
           Include support for MX31ADS platform. This includes specific
           configurations for the board and its peripherals.
 
+config MACH_MX31ADS_WM1133_EV1
+        bool "Support Wolfson Microelectronics 1133-EV1 module"
+        depends on MACH_MX31ADS
+        select MFD_WM8350_CONFIG_MODE_0
+        select MFD_WM8352_CONFIG_MODE_0
+        help
+          Include support for the Wolfson Microelectronics 1133-EV1 PMU
+          and audio module for the MX31ADS platform.
+
 config MACH_PCM037
-        bool "Support Phytec pcm037 platforms"
+        bool "Support Phytec pcm037 (i.MX31) platforms"
+        select ARCH_MX31
         help
           Include support for Phytec pcm037 platform. This includes
           specific configurations for the board and its peripherals.
 
 config MACH_MX31LITE
         bool "Support MX31 LITEKIT (LogicPD)"
+        select ARCH_MX31
         default n
         help
           Include support for MX31 LITEKIT platform. This includes specific
@@ -23,6 +42,7 @@ config MACH_MX31LITE
 
 config MACH_MX31_3DS
         bool "Support MX31PDK (3DS)"
+        select ARCH_MX31
         default n
         help
           Include support for MX31PDK (3DS) platform. This includes specific
@@ -30,10 +50,18 @@ config MACH_MX31_3DS
 
 config MACH_MX31MOBOARD
         bool "Support mx31moboard platforms (EPFL Mobots group)"
+        select ARCH_MX31
         default n
         help
           Include support for mx31moboard platform. This includes specific
           configurations for the board and its peripherals.
 
-endmenu
+config MACH_QONG
+        bool "Support Dave/DENX QongEVB-LITE platform"
+        select ARCH_MX31
+        default n
+        help
+          Include support for Dave/DENX QongEVB-LITE platform. This includes
+          specific configurations for the board and its peripherals.
 
+endif
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 5a151540fe83..272c8a953b30 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -4,9 +4,13 @@
 
 # Object file lists.
 
-obj-y                   := mm.o clock.o devices.o iomux.o
+obj-y                           := mm.o devices.o
+obj-$(CONFIG_ARCH_MX31)         += clock.o iomux.o
+obj-$(CONFIG_ARCH_MX35)         += clock-imx35.o
 obj-$(CONFIG_MACH_MX31ADS)      += mx31ads.o
 obj-$(CONFIG_MACH_MX31LITE)     += mx31lite.o
 obj-$(CONFIG_MACH_PCM037)       += pcm037.o
 obj-$(CONFIG_MACH_MX31_3DS)     += mx31pdk.o
-obj-$(CONFIG_MACH_MX31MOBOARD)  += mx31moboard.o
+obj-$(CONFIG_MACH_MX31MOBOARD)  += mx31moboard.o mx31moboard-devboard.o \
+                                   mx31moboard-marxbot.o
+obj-$(CONFIG_MACH_QONG)         += qong.o
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
new file mode 100644
index 000000000000..53a112d4e04a
--- /dev/null
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -0,0 +1,487 @@
+/*
+ * Copyright (C) 2009 by Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <asm/clkdev.h>
+
+#include <mach/clock.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+
+#define CCM_BASE        IO_ADDRESS(CCM_BASE_ADDR)
+
+#define CCM_CCMR        0x00
+#define CCM_PDR0        0x04
+#define CCM_PDR1        0x08
+#define CCM_PDR2        0x0C
+#define CCM_PDR3        0x10
+#define CCM_PDR4        0x14
+#define CCM_RCSR        0x18
+#define CCM_MPCTL       0x1C
+#define CCM_PPCTL       0x20
+#define CCM_ACMR        0x24
+#define CCM_COSR        0x28
+#define CCM_CGR0        0x2C
+#define CCM_CGR1        0x30
+#define CCM_CGR2        0x34
+#define CCM_CGR3        0x38
+
+#ifdef HAVE_SET_RATE_SUPPORT
+static void calc_dividers(u32 div, u32 *pre, u32 *post, u32 maxpost)
+{
+        u32 min_pre, temp_pre, old_err, err;
+
+        min_pre = (div - 1) / maxpost + 1;
+        old_err = 8;
+
+        for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
+                if (div > (temp_pre * maxpost))
+                        break;
+
+                if (div < (temp_pre * temp_pre))
+                        continue;
+
+                err = div % temp_pre;
+
+                if (err == 0) {
+                        *pre = temp_pre;
+                        break;
+                }
+
+                err = temp_pre - err;
+
+                if (err < old_err) {
+                        old_err = err;
+                        *pre = temp_pre;
+                }
+        }
+
+        *post = (div + *pre - 1) / *pre;
+}
+
+/* get the best values for a 3-bit divider combined with a 6-bit divider */
+static void calc_dividers_3_6(u32 div, u32 *pre, u32 *post)
+{
+        if (div >= 512) {
+                *pre = 8;
+                *post = 64;
+        } else if (div >= 64) {
+                calc_dividers(div, pre, post, 64);
+        } else if (div <= 8) {
+                *pre = div;
+                *post = 1;
+        } else {
+                *pre = 1;
+                *post = div;
+        }
+}
+
+/* get the best values for two cascaded 3-bit dividers */
+static void calc_dividers_3_3(u32 div, u32 *pre, u32 *post)
+{
+        if (div >= 64) {
+                *pre = *post = 8;
+        } else if (div > 8) {
+                calc_dividers(div, pre, post, 8);
+        } else {
+                *pre = 1;
+                *post = div;
+        }
+}
+#endif
+
+static unsigned long get_rate_mpll(void)
+{
+        ulong mpctl = __raw_readl(CCM_BASE + CCM_MPCTL);
+
+        return mxc_decode_pll(mpctl, 24000000);
+}
+
+static unsigned long get_rate_ppll(void)
+{
+        ulong ppctl = __raw_readl(CCM_BASE + CCM_PPCTL);
+
+        return mxc_decode_pll(ppctl, 24000000);
+}
+
+struct arm_ahb_div {
+        unsigned char arm, ahb, sel;
+};
+
+static struct arm_ahb_div clk_consumer[] = {
+        { .arm = 1, .ahb = 4, .sel = 0},
+        { .arm = 1, .ahb = 3, .sel = 1},
+        { .arm = 2, .ahb = 2, .sel = 0},
+        { .arm = 0, .ahb = 0, .sel = 0},
+        { .arm = 0, .ahb = 0, .sel = 0},
+        { .arm = 0, .ahb = 0, .sel = 0},
+        { .arm = 4, .ahb = 1, .sel = 0},
+        { .arm = 1, .ahb = 5, .sel = 0},
+        { .arm = 1, .ahb = 8, .sel = 0},
+        { .arm = 1, .ahb = 6, .sel = 1},
+        { .arm = 2, .ahb = 4, .sel = 0},
+        { .arm = 0, .ahb = 0, .sel = 0},
+        { .arm = 0, .ahb = 0, .sel = 0},
+        { .arm = 0, .ahb = 0, .sel = 0},
+        { .arm = 4, .ahb = 2, .sel = 0},
+        { .arm = 0, .ahb = 0, .sel = 0},
+};
+
+static struct arm_ahb_div clk_automotive[] = {
+        { .arm = 1, .ahb = 3, .sel = 0},
+        { .arm = 1, .ahb = 2, .sel = 1},
+        { .arm = 2, .ahb = 1, .sel = 1},
+        { .arm = 0, .ahb = 0, .sel = 0},
+        { .arm = 1, .ahb = 6, .sel = 0},
+        { .arm = 1, .ahb = 4, .sel = 1},
+        { .arm = 2, .ahb = 2, .sel = 1},
+        { .arm = 0, .ahb = 0, .sel = 0},
+};
+
+static unsigned long get_rate_arm(void)
+{
+        unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
+        struct arm_ahb_div *aad;
+        unsigned long fref = get_rate_mpll();
+
+        if (pdr0 & 1) {
+                /* consumer path */
+                aad = &clk_consumer[(pdr0 >> 16) & 0xf];
+                if (aad->sel)
+                        fref = fref * 2 / 3;
+        } else {
+                /* auto path */
+                aad = &clk_automotive[(pdr0 >> 9) & 0x7];
+                if (aad->sel)
+                        fref = fref * 3 / 4;
+        }
+        return fref / aad->arm;
+}
+
+static unsigned long get_rate_ahb(struct clk *clk)
+{
+        unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
+        struct arm_ahb_div *aad;
+        unsigned long fref = get_rate_mpll();
+
+        if (pdr0 & 1)
+                /* consumer path */
+                aad = &clk_consumer[(pdr0 >> 16) & 0xf];
+        else
+                /* auto path */
+                aad = &clk_automotive[(pdr0 >> 9) & 0x7];
+
+        return fref / aad->ahb;
+}
+
+static unsigned long get_rate_ipg(struct clk *clk)
+{
+        return get_rate_ahb(NULL) >> 1;
+}
+
+static unsigned long get_3_3_div(unsigned long in)
+{
+        return (((in >> 3) & 0x7) + 1) * ((in & 0x7) + 1);
+}
+
+static unsigned long get_rate_uart(struct clk *clk)
+{
+        unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3);
+        unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
+        unsigned long div = get_3_3_div(pdr4 >> 10);
+
+        if (pdr3 & (1 << 14))
+                return get_rate_arm() / div;
+        else
+                return get_rate_ppll() / div;
+}
+
+static unsigned long get_rate_sdhc(struct clk *clk)
+{
+        unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3);
+        unsigned long div, rate;
+
+        if (pdr3 & (1 << 6))
+                rate = get_rate_arm();
+        else
+                rate = get_rate_ppll();
+
+        switch (clk->id) {
+        default:
+        case 0:
+                div = pdr3 & 0x3f;
+                break;
+        case 1:
+                div = (pdr3 >> 8) & 0x3f;
+                break;
+        case 2:
+                div = (pdr3 >> 16) & 0x3f;
+                break;
+        }
+
+        return rate / get_3_3_div(div);
+}
+
+static unsigned long get_rate_mshc(struct clk *clk)
+{
+        unsigned long pdr1 = __raw_readl(CCM_BASE + CCM_PDR1);
+        unsigned long div1, div2, rate;
+
+        if (pdr1 & (1 << 7))
+                rate = get_rate_arm();
+        else
+                rate = get_rate_ppll();
+
+        div1 = (pdr1 >> 29) & 0x7;
+        div2 = (pdr1 >> 22) & 0x3f;
+
+        return rate / ((div1 + 1) * (div2 + 1));
+}
+
+static unsigned long get_rate_ssi(struct clk *clk)
+{
+        unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
+        unsigned long div1, div2, rate;
+
+        if (pdr2 & (1 << 6))
+                rate = get_rate_arm();
+        else
+                rate = get_rate_ppll();
+
+        switch (clk->id) {
+        default:
+        case 0:
+                div1 = pdr2 & 0x3f;
+                div2 = (pdr2 >> 24) & 0x7;
+                break;
+        case 1:
+                div1 = (pdr2 >> 8) & 0x3f;
+                div2 = (pdr2 >> 27) & 0x7;
+                break;
+        }
+
+        return rate / ((div1 + 1) * (div2 + 1));
+}
+
+static unsigned long get_rate_csi(struct clk *clk)
+{
+        unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
+        unsigned long rate;
+
+        if (pdr2 & (1 << 7))
+                rate = get_rate_arm();
+        else
+                rate = get_rate_ppll();
+
+        return rate / get_3_3_div((pdr2 >> 16) & 0x3f);
+}
+
+static unsigned long get_rate_ipg_per(struct clk *clk)
+{
+        unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
+        unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
+        unsigned long div1, div2;
+
+        if (pdr0 & (1 << 26)) {
+                div1 = (pdr4 >> 19) & 0x7;
+                div2 = (pdr4 >> 16) & 0x7;
+                return get_rate_arm() / ((div1 + 1) * (div2 + 1));
+        } else {
+                div1 = (pdr0 >> 12) & 0x7;
+                return get_rate_ahb(NULL) / div1;
+        }
+}
+
+static int clk_cgr_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 3 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+
+        return 0;
+}
+
+static void clk_cgr_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(3 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+
+#define DEFINE_CLOCK(name, i, er, es, gr, sr)           \
+        static struct clk name = {                      \
+                .id             = i,                    \
+                .enable_reg     = CCM_BASE + er,        \
+                .enable_shift   = es,                   \
+                .get_rate       = gr,                   \
+                .set_rate       = sr,                   \
+                .enable         = clk_cgr_enable,       \
+                .disable        = clk_cgr_disable,      \
+        }
+
+DEFINE_CLOCK(asrc_clk,   0, CCM_CGR0,  0, NULL, NULL);
+DEFINE_CLOCK(ata_clk,    0, CCM_CGR0,  2, get_rate_ipg, NULL);
+DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0,  4, NULL, NULL);
+DEFINE_CLOCK(can1_clk,   0, CCM_CGR0,  6, get_rate_ipg, NULL);
+DEFINE_CLOCK(can2_clk,   1, CCM_CGR0,  8, get_rate_ipg, NULL);
+DEFINE_CLOCK(cspi1_clk,  0, CCM_CGR0, 10, get_rate_ipg, NULL);
+DEFINE_CLOCK(cspi2_clk,  1, CCM_CGR0, 12, get_rate_ipg, NULL);
+DEFINE_CLOCK(ect_clk,    0, CCM_CGR0, 14, get_rate_ipg, NULL);
+DEFINE_CLOCK(edio_clk,   0, CCM_CGR0, 16, NULL, NULL);
+DEFINE_CLOCK(emi_clk,    0, CCM_CGR0, 18, get_rate_ipg, NULL);
+DEFINE_CLOCK(epit1_clk,  0, CCM_CGR0, 20, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(epit2_clk,  1, CCM_CGR0, 22, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(esai_clk,   0, CCM_CGR0, 24, NULL, NULL);
+DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGR0, 26, get_rate_sdhc, NULL);
+DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGR0, 28, get_rate_sdhc, NULL);
+DEFINE_CLOCK(esdhc3_clk, 2, CCM_CGR0, 30, get_rate_sdhc, NULL);
+
+DEFINE_CLOCK(fec_clk,    0, CCM_CGR1,  0, get_rate_ipg, NULL);
+DEFINE_CLOCK(gpio1_clk,  0, CCM_CGR1,  2, NULL, NULL);
+DEFINE_CLOCK(gpio2_clk,  1, CCM_CGR1,  4, NULL, NULL);
+DEFINE_CLOCK(gpio3_clk,  2, CCM_CGR1,  6, NULL, NULL);
+DEFINE_CLOCK(gpt_clk,    0, CCM_CGR1,  8, get_rate_ipg, NULL);
+DEFINE_CLOCK(i2c1_clk,   0, CCM_CGR1, 10, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(i2c2_clk,   1, CCM_CGR1, 12, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(i2c3_clk,   2, CCM_CGR1, 14, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL);
+DEFINE_CLOCK(ipu_clk,    0, CCM_CGR1, 18, NULL, NULL);
+DEFINE_CLOCK(kpp_clk,    0, CCM_CGR1, 20, get_rate_ipg, NULL);
+DEFINE_CLOCK(mlb_clk,    0, CCM_CGR1, 22, get_rate_ahb, NULL);
+DEFINE_CLOCK(mshc_clk,   0, CCM_CGR1, 24, get_rate_mshc, NULL);
+DEFINE_CLOCK(owire_clk,  0, CCM_CGR1, 26, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(pwm_clk,    0, CCM_CGR1, 28, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(rngc_clk,   0, CCM_CGR1, 30, get_rate_ipg, NULL);
+
+DEFINE_CLOCK(rtc_clk,    0, CCM_CGR2,  0, get_rate_ipg, NULL);
+DEFINE_CLOCK(rtic_clk,   0, CCM_CGR2,  2, get_rate_ahb, NULL);
+DEFINE_CLOCK(scc_clk,    0, CCM_CGR2,  4, get_rate_ipg, NULL);
+DEFINE_CLOCK(sdma_clk,   0, CCM_CGR2,  6, NULL, NULL);
+DEFINE_CLOCK(spba_clk,   0, CCM_CGR2,  8, get_rate_ipg, NULL);
+DEFINE_CLOCK(spdif_clk,  0, CCM_CGR2, 10, NULL, NULL);
+DEFINE_CLOCK(ssi1_clk,   0, CCM_CGR2, 12, get_rate_ssi, NULL);
+DEFINE_CLOCK(ssi2_clk,   1, CCM_CGR2, 14, get_rate_ssi, NULL);
+DEFINE_CLOCK(uart1_clk,  0, CCM_CGR2, 16, get_rate_uart, NULL);
+DEFINE_CLOCK(uart2_clk,  1, CCM_CGR2, 18, get_rate_uart, NULL);
+DEFINE_CLOCK(uart3_clk,  2, CCM_CGR2, 20, get_rate_uart, NULL);
+DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, NULL, NULL);
+DEFINE_CLOCK(wdog_clk,   0, CCM_CGR2, 24, NULL, NULL);
+DEFINE_CLOCK(max_clk,    0, CCM_CGR2, 26, NULL, NULL);
+DEFINE_CLOCK(admux_clk,  0, CCM_CGR2, 30, NULL, NULL);
+
+DEFINE_CLOCK(csi_clk,    0, CCM_CGR3,  0, get_rate_csi, NULL);
+DEFINE_CLOCK(iim_clk,    0, CCM_CGR3,  2, NULL, NULL);
+DEFINE_CLOCK(gpu2d_clk,  0, CCM_CGR3,  4, NULL, NULL);
+
+#define _REGISTER_CLOCK(d, n, c)        \
+        {                               \
+                .dev_id = d,            \
+                .con_id = n,            \
+                .clk = &c,              \
+        },
+
+static struct clk_lookup lookups[] __initdata = {
+        _REGISTER_CLOCK(NULL, "asrc", asrc_clk)
+        _REGISTER_CLOCK(NULL, "ata", ata_clk)
+        _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
+        _REGISTER_CLOCK(NULL, "can", can1_clk)
+        _REGISTER_CLOCK(NULL, "can", can2_clk)
+        _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
+        _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
+        _REGISTER_CLOCK(NULL, "ect", ect_clk)
+        _REGISTER_CLOCK(NULL, "edio", edio_clk)
+        _REGISTER_CLOCK(NULL, "emi", emi_clk)
+        _REGISTER_CLOCK(NULL, "epit", epit1_clk)
+        _REGISTER_CLOCK(NULL, "epit", epit2_clk)
+        _REGISTER_CLOCK(NULL, "esai", esai_clk)
+        _REGISTER_CLOCK(NULL, "sdhc", esdhc1_clk)
+        _REGISTER_CLOCK(NULL, "sdhc", esdhc2_clk)
+        _REGISTER_CLOCK(NULL, "sdhc", esdhc3_clk)
+        _REGISTER_CLOCK("fec.0", NULL, fec_clk)
+        _REGISTER_CLOCK(NULL, "gpio", gpio1_clk)
+        _REGISTER_CLOCK(NULL, "gpio", gpio2_clk)
+        _REGISTER_CLOCK(NULL, "gpio", gpio3_clk)
+        _REGISTER_CLOCK("gpt.0", NULL, gpt_clk)
+        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
+        _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
+        _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
+        _REGISTER_CLOCK(NULL, "iomuxc", iomuxc_clk)
+        _REGISTER_CLOCK(NULL, "ipu", ipu_clk)
+        _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
+        _REGISTER_CLOCK(NULL, "mlb", mlb_clk)
+        _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
+        _REGISTER_CLOCK("mxc_w1", NULL, owire_clk)
+        _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
+        _REGISTER_CLOCK(NULL, "rngc", rngc_clk)
+        _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
+        _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
+        _REGISTER_CLOCK(NULL, "scc", scc_clk)
+        _REGISTER_CLOCK(NULL, "sdma", sdma_clk)
+        _REGISTER_CLOCK(NULL, "spba", spba_clk)
+        _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
+        _REGISTER_CLOCK(NULL, "ssi", ssi1_clk)
+        _REGISTER_CLOCK(NULL, "ssi", ssi2_clk)
+        _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
+        _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
+        _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
+        _REGISTER_CLOCK(NULL, "usbotg", usbotg_clk)
+        _REGISTER_CLOCK("mxc_wdt.0", NULL, wdog_clk)
+        _REGISTER_CLOCK(NULL, "max", max_clk)
+        _REGISTER_CLOCK(NULL, "admux", admux_clk)
+        _REGISTER_CLOCK(NULL, "csi", csi_clk)
+        _REGISTER_CLOCK(NULL, "iim", iim_clk)
+        _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk)
+};
+
+int __init mx35_clocks_init()
+{
+        int i;
+        unsigned int ll = 0;
+
+        mxc_set_cpu_type(MXC_CPU_MX35);
+
+#ifdef CONFIG_DEBUG_LL_CONSOLE
+        ll = (3 << 16);
+#endif
+
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
+
+        /* Turn off all clocks except the ones we need to survive, namely:
+         * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart
+         */
+        __raw_writel((3 << 18), CCM_BASE + CCM_CGR0);
+        __raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16),
+                        CCM_BASE + CCM_CGR1);
+        __raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2);
+        __raw_writel(0, CCM_BASE + CCM_CGR3);
+
+        mxc_timer_init(&gpt_clk);
+
+        return 0;
+}
+
diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c
index b1746aae1f89..ca46f4801c3d 100644
--- a/arch/arm/mach-mx3/clock.c
+++ b/arch/arm/mach-mx3/clock.c
@@ -23,9 +23,13 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
+
+#include <asm/clkdev.h>
+#include <asm/div64.h>
+
 #include <mach/clock.h>
 #include <mach/hardware.h>
-#include <asm/div64.h>
+#include <mach/common.h>
 
 #include "crm_regs.h"
 
@@ -64,17 +68,17 @@ static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post)
 }
 
 static struct clk mcu_pll_clk;
-static struct clk mcu_main_clk;
-static struct clk usb_pll_clk;
 static struct clk serial_pll_clk;
 static struct clk ipg_clk;
 static struct clk ckih_clk;
-static struct clk ahb_clk;
 
-static int _clk_enable(struct clk *clk)
+static int cgr_enable(struct clk *clk)
 {
         u32 reg;
 
+        if (!clk->enable_reg)
+                return 0;
+
         reg = __raw_readl(clk->enable_reg);
         reg |= 3 << clk->enable_shift;
         __raw_writel(reg, clk->enable_reg);
@@ -82,133 +86,69 @@ static int _clk_enable(struct clk *clk)
         return 0;
 }
 
-static void _clk_disable(struct clk *clk)
+static void cgr_disable(struct clk *clk)
 {
         u32 reg;
 
+        if (!clk->enable_reg)
+                return;
+
         reg = __raw_readl(clk->enable_reg);
         reg &= ~(3 << clk->enable_shift);
+
+        /* special case for EMI clock */
+        if (clk->enable_reg == MXC_CCM_CGR2 && clk->enable_shift == 8)
+                reg |= (1 << clk->enable_shift);
+
         __raw_writel(reg, clk->enable_reg);
 }
 
-static void _clk_emi_disable(struct clk *clk)
+static unsigned long pll_ref_get_rate(void)
 {
-        u32 reg;
+        unsigned long ccmr;
+        unsigned int prcs;
 
-        reg = __raw_readl(clk->enable_reg);
-        reg &= ~(3 << clk->enable_shift);
-        reg |= (1 << clk->enable_shift);
-        __raw_writel(reg, clk->enable_reg);
+        ccmr = __raw_readl(MXC_CCM_CCMR);
+        prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
+        if (prcs == 0x1)
+                return CKIL_CLK_FREQ * 1024;
+        else
+                return clk_get_rate(&ckih_clk);
 }
 
-static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
+static unsigned long usb_pll_get_rate(struct clk *clk)
 {
-        u32 reg;
-        signed long pd = 1;     /* Pre-divider */
-        signed long mfi;        /* Multiplication Factor (Integer part) */
-        signed long mfn;        /* Multiplication Factor (Integer part) */
-        signed long mfd;        /* Multiplication Factor (Denominator Part) */
-        signed long tmp;
-        u32 ref_freq = clk_get_rate(clk->parent);
+        unsigned long reg;
 
-        while (((ref_freq / pd) * 10) > rate)
-                pd++;
+        reg = __raw_readl(MXC_CCM_UPCTL);
 
-        if ((ref_freq / pd) < PRE_DIV_MIN_FREQ)
-                return -EINVAL;
+        return mxc_decode_pll(reg, pll_ref_get_rate());
+}
 
-        /* the ref_freq/2 in the following is to round up */
-        mfi = (((rate / 2) * pd) + (ref_freq / 2)) / ref_freq;
-        if (mfi < 5 || mfi > 15)
-                return -EINVAL;
+static unsigned long serial_pll_get_rate(struct clk *clk)
+{
+        unsigned long reg;
 
-        /* pick a mfd value that will work
-         * then solve for mfn */
-        mfd = ref_freq / 50000;
-
-        /*
-         *          pll_freq * pd * mfd
-         *   mfn = --------------------  -  (mfi * mfd)
-         *           2 * ref_freq
-         */
-        /* the tmp/2 is for rounding */
-        tmp = ref_freq / 10000;
-        mfn =
-            ((((((rate / 2) + (tmp / 2)) / tmp) * pd) * mfd) / 10000) -
-            (mfi * mfd);
-
-        mfn = mfn & 0x3ff;
-        pd--;
-        mfd--;
-
-        /* Change the Pll value */
-        reg = (mfi << MXC_CCM_PCTL_MFI_OFFSET) |
-            (mfn << MXC_CCM_PCTL_MFN_OFFSET) |
-            (mfd << MXC_CCM_PCTL_MFD_OFFSET) | (pd << MXC_CCM_PCTL_PD_OFFSET);
-
-        if (clk == &mcu_pll_clk)
-                __raw_writel(reg, MXC_CCM_MPCTL);
-        else if (clk == &usb_pll_clk)
-                __raw_writel(reg, MXC_CCM_UPCTL);
-        else if (clk == &serial_pll_clk)
-                __raw_writel(reg, MXC_CCM_SRPCTL);
+        reg = __raw_readl(MXC_CCM_SRPCTL);
 
-        return 0;
+        return mxc_decode_pll(reg, pll_ref_get_rate());
 }
 
-static unsigned long _clk_pll_get_rate(struct clk *clk)
+static unsigned long mcu_pll_get_rate(struct clk *clk)
 {
-        long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
         unsigned long reg, ccmr;
-        s64 temp;
-        unsigned int prcs;
 
         ccmr = __raw_readl(MXC_CCM_CCMR);
-        prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
-        if (prcs == 0x1)
-                ref_clk = CKIL_CLK_FREQ * 1024;
-        else
-                ref_clk = clk_get_rate(&ckih_clk);
-
-        if (clk == &mcu_pll_clk) {
-                if ((ccmr & MXC_CCM_CCMR_MPE) == 0)
-                        return ref_clk;
-                if ((ccmr & MXC_CCM_CCMR_MDS) != 0)
-                        return ref_clk;
-                reg = __raw_readl(MXC_CCM_MPCTL);
-        } else if (clk == &usb_pll_clk)
-                reg = __raw_readl(MXC_CCM_UPCTL);
-        else if (clk == &serial_pll_clk)
-                reg = __raw_readl(MXC_CCM_SRPCTL);
-        else {
-                BUG();
-                return 0;
-        }
-
-        pdf = (reg & MXC_CCM_PCTL_PD_MASK) >> MXC_CCM_PCTL_PD_OFFSET;
-        mfd = (reg & MXC_CCM_PCTL_MFD_MASK) >> MXC_CCM_PCTL_MFD_OFFSET;
-        mfi = (reg & MXC_CCM_PCTL_MFI_MASK) >> MXC_CCM_PCTL_MFI_OFFSET;
-        mfi = (mfi <= 5) ? 5 : mfi;
-        mfn = mfn_abs = reg & MXC_CCM_PCTL_MFN_MASK;
 
-        if (mfn >= 0x200) {
-                mfn |= 0xFFFFFE00;
-                mfn_abs = -mfn;
-        }
-
-        ref_clk *= 2;
-        ref_clk /= pdf + 1;
+        if (!(ccmr & MXC_CCM_CCMR_MPE) || (ccmr & MXC_CCM_CCMR_MDS))
+                return clk_get_rate(&ckih_clk);
 
-        temp = (u64) ref_clk * mfn_abs;
-        do_div(temp, mfd + 1);
-        if (mfn < 0)
-                temp = -temp;
-        temp = (ref_clk * mfi) + temp;
+        reg = __raw_readl(MXC_CCM_MPCTL);
 
-        return temp;
+        return mxc_decode_pll(reg, pll_ref_get_rate());
 }
 
-static int _clk_usb_pll_enable(struct clk *clk)
+static int usb_pll_enable(struct clk *clk)
 {
         u32 reg;
 
@@ -222,7 +162,7 @@ static int _clk_usb_pll_enable(struct clk *clk)
         return 0;
 }
 
-static void _clk_usb_pll_disable(struct clk *clk)
+static void usb_pll_disable(struct clk *clk)
 {
         u32 reg;
 
@@ -231,7 +171,7 @@ static void _clk_usb_pll_disable(struct clk *clk)
         __raw_writel(reg, MXC_CCM_CCMR);
 }
 
-static int _clk_serial_pll_enable(struct clk *clk)
+static int serial_pll_enable(struct clk *clk)
 {
         u32 reg;
 
@@ -245,7 +185,7 @@ static int _clk_serial_pll_enable(struct clk *clk)
         return 0;
 }
 
-static void _clk_serial_pll_disable(struct clk *clk)
+static void serial_pll_disable(struct clk *clk)
 {
         u32 reg;
 
@@ -258,7 +198,7 @@ static void _clk_serial_pll_disable(struct clk *clk)
 #define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off)
 #define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off)
 
-static unsigned long _clk_mcu_main_get_rate(struct clk *clk)
+static unsigned long mcu_main_get_rate(struct clk *clk)
 {
         u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0);
 
@@ -268,7 +208,7 @@ static unsigned long _clk_mcu_main_get_rate(struct clk *clk)
                 return clk_get_rate(&mcu_pll_clk);
 }
 
-static unsigned long _clk_hclk_get_rate(struct clk *clk)
+static unsigned long ahb_get_rate(struct clk *clk)
 {
         unsigned long max_pdf;
 
@@ -277,7 +217,7 @@ static unsigned long _clk_hclk_get_rate(struct clk *clk)
         return clk_get_rate(clk->parent) / (max_pdf + 1);
 }
 
-static unsigned long _clk_ipg_get_rate(struct clk *clk)
+static unsigned long ipg_get_rate(struct clk *clk)
 {
         unsigned long ipg_pdf;
 
@@ -286,7 +226,7 @@ static unsigned long _clk_ipg_get_rate(struct clk *clk)
         return clk_get_rate(clk->parent) / (ipg_pdf + 1);
 }
 
-static unsigned long _clk_nfc_get_rate(struct clk *clk)
+static unsigned long nfc_get_rate(struct clk *clk)
 {
         unsigned long nfc_pdf;
 
@@ -295,7 +235,7 @@ static unsigned long _clk_nfc_get_rate(struct clk *clk)
         return clk_get_rate(clk->parent) / (nfc_pdf + 1);
 }
 
-static unsigned long _clk_hsp_get_rate(struct clk *clk)
+static unsigned long hsp_get_rate(struct clk *clk)
 {
         unsigned long hsp_pdf;
 
@@ -304,7 +244,7 @@ static unsigned long _clk_hsp_get_rate(struct clk *clk)
         return clk_get_rate(clk->parent) / (hsp_pdf + 1);
 }
 
-static unsigned long _clk_usb_get_rate(struct clk *clk)
+static unsigned long usb_get_rate(struct clk *clk)
 {
         unsigned long usb_pdf, usb_prepdf;
 
@@ -315,7 +255,7 @@ static unsigned long _clk_usb_get_rate(struct clk *clk)
         return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1);
 }
 
-static unsigned long _clk_csi_get_rate(struct clk *clk)
+static unsigned long csi_get_rate(struct clk *clk)
 {
         u32 reg, pre, post;
 
@@ -329,7 +269,7 @@ static unsigned long _clk_csi_get_rate(struct clk *clk)
         return clk_get_rate(clk->parent) / (pre * post);
 }
 
-static unsigned long _clk_csi_round_rate(struct clk *clk, unsigned long rate)
+static unsigned long csi_round_rate(struct clk *clk, unsigned long rate)
 {
         u32 pre, post, parent = clk_get_rate(clk->parent);
         u32 div = parent / rate;
@@ -342,7 +282,7 @@ static unsigned long _clk_csi_round_rate(struct clk *clk, unsigned long rate)
         return parent / (pre * post);
 }
 
-static int _clk_csi_set_rate(struct clk *clk, unsigned long rate)
+static int csi_set_rate(struct clk *clk, unsigned long rate)
 {
         u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
 
@@ -363,16 +303,7 @@ static int _clk_csi_set_rate(struct clk *clk, unsigned long rate)
         return 0;
 }
 
-static unsigned long _clk_per_get_rate(struct clk *clk)
-{
-        unsigned long per_pdf;
-
-        per_pdf = PDR0(MXC_CCM_PDR0_PER_PODF_MASK,
-                       MXC_CCM_PDR0_PER_PODF_OFFSET);
-        return clk_get_rate(clk->parent) / (per_pdf + 1);
-}
-
-static unsigned long _clk_ssi1_get_rate(struct clk *clk)
+static unsigned long ssi1_get_rate(struct clk *clk)
 {
         unsigned long ssi1_pdf, ssi1_prepdf;
 
@@ -383,7 +314,7 @@ static unsigned long _clk_ssi1_get_rate(struct clk *clk)
         return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1);
 }
 
-static unsigned long _clk_ssi2_get_rate(struct clk *clk)
+static unsigned long ssi2_get_rate(struct clk *clk)
 {
         unsigned long ssi2_pdf, ssi2_prepdf;
 
@@ -394,7 +325,7 @@ static unsigned long _clk_ssi2_get_rate(struct clk *clk)
         return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1);
 }
 
-static unsigned long _clk_firi_get_rate(struct clk *clk)
+static unsigned long firi_get_rate(struct clk *clk)
 {
         unsigned long firi_pdf, firi_prepdf;
 
@@ -405,7 +336,7 @@ static unsigned long _clk_firi_get_rate(struct clk *clk)
         return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1);
 }
 
-static unsigned long _clk_firi_round_rate(struct clk *clk, unsigned long rate)
+static unsigned long firi_round_rate(struct clk *clk, unsigned long rate)
 {
         u32 pre, post;
         u32 parent = clk_get_rate(clk->parent);
@@ -420,7 +351,7 @@ static unsigned long _clk_firi_round_rate(struct clk *clk, unsigned long rate)
 
 }
 
-static int _clk_firi_set_rate(struct clk *clk, unsigned long rate)
+static int firi_set_rate(struct clk *clk, unsigned long rate)
 {
         u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
 
@@ -441,12 +372,12 @@ static int _clk_firi_set_rate(struct clk *clk, unsigned long rate)
         return 0;
 }
 
-static unsigned long _clk_mbx_get_rate(struct clk *clk)
+static unsigned long mbx_get_rate(struct clk *clk)
 {
         return clk_get_rate(clk->parent) / 2;
 }
 
-static unsigned long _clk_mstick1_get_rate(struct clk *clk)
+static unsigned long mstick1_get_rate(struct clk *clk)
 {
         unsigned long msti_pdf;
 
@@ -455,7 +386,7 @@ static unsigned long _clk_mstick1_get_rate(struct clk *clk)
         return clk_get_rate(clk->parent) / (msti_pdf + 1);
 }
 
-static unsigned long _clk_mstick2_get_rate(struct clk *clk)
+static unsigned long mstick2_get_rate(struct clk *clk)
 {
         unsigned long msti_pdf;
 
@@ -472,661 +403,185 @@ static unsigned long clk_ckih_get_rate(struct clk *clk)
 }
 
 static struct clk ckih_clk = {
-        .name = "ckih",
         .get_rate = clk_ckih_get_rate,
 };
 
-static unsigned long clk_ckil_get_rate(struct clk *clk)
-{
-        return CKIL_CLK_FREQ;
-}
-
-static struct clk ckil_clk = {
-        .name = "ckil",
-        .get_rate = clk_ckil_get_rate,
-};
-
 static struct clk mcu_pll_clk = {
-        .name = "mcu_pll",
         .parent = &ckih_clk,
-        .set_rate = _clk_pll_set_rate,
-        .get_rate = _clk_pll_get_rate,
+        .get_rate = mcu_pll_get_rate,
 };
 
 static struct clk mcu_main_clk = {
-        .name = "mcu_main_clk",
         .parent = &mcu_pll_clk,
-        .get_rate = _clk_mcu_main_get_rate,
+        .get_rate = mcu_main_get_rate,
 };
 
 static struct clk serial_pll_clk = {
-        .name = "serial_pll",
         .parent = &ckih_clk,
-        .set_rate = _clk_pll_set_rate,
-        .get_rate = _clk_pll_get_rate,
-        .enable = _clk_serial_pll_enable,
-        .disable = _clk_serial_pll_disable,
+        .get_rate = serial_pll_get_rate,
+        .enable = serial_pll_enable,
+        .disable = serial_pll_disable,
 };
 
 static struct clk usb_pll_clk = {
-        .name = "usb_pll",
         .parent = &ckih_clk,
-        .set_rate = _clk_pll_set_rate,
-        .get_rate = _clk_pll_get_rate,
-        .enable = _clk_usb_pll_enable,
-        .disable = _clk_usb_pll_disable,
+        .get_rate = usb_pll_get_rate,
+        .enable = usb_pll_enable,
+        .disable = usb_pll_disable,
 };
 
 static struct clk ahb_clk = {
-        .name = "ahb_clk",
         .parent = &mcu_main_clk,
-        .get_rate = _clk_hclk_get_rate,
-};
-
-static struct clk per_clk = {
-        .name = "per_clk",
-        .parent = &usb_pll_clk,
-        .get_rate = _clk_per_get_rate,
-};
-
-static struct clk perclk_clk = {
-        .name = "perclk_clk",
-        .parent = &ipg_clk,
-};
-
-static struct clk cspi_clk[] = {
-        {
-         .name = "cspi_clk",
-         .id = 0,
-         .parent = &ipg_clk,
-         .enable = _clk_enable,
-         .enable_reg = MXC_CCM_CGR2,
-         .enable_shift = MXC_CCM_CGR2_CSPI1_OFFSET,
-         .disable = _clk_disable,},
-        {
-         .name = "cspi_clk",
-         .id = 1,
-         .parent = &ipg_clk,
-         .enable = _clk_enable,
-         .enable_reg = MXC_CCM_CGR2,
-         .enable_shift = MXC_CCM_CGR2_CSPI2_OFFSET,
-         .disable = _clk_disable,},
-        {
-         .name = "cspi_clk",
-         .id = 2,
-         .parent = &ipg_clk,
-         .enable = _clk_enable,
-         .enable_reg = MXC_CCM_CGR0,
-         .enable_shift = MXC_CCM_CGR0_CSPI3_OFFSET,
-         .disable = _clk_disable,},
-};
-
-static struct clk ipg_clk = {
-        .name = "ipg_clk",
-        .parent = &ahb_clk,
-        .get_rate = _clk_ipg_get_rate,
-};
-
-static struct clk emi_clk = {
-        .name = "emi_clk",
-        .parent = &ahb_clk,
-        .enable = _clk_enable,
-        .enable_reg = MXC_CCM_CGR2,
-        .enable_shift = MXC_CCM_CGR2_EMI_OFFSET,
-        .disable = _clk_emi_disable,
-};
-
-static struct clk gpt_clk = {
-        .name = "gpt_clk",
-        .parent = &perclk_clk,
-        .enable = _clk_enable,
-        .enable_reg = MXC_CCM_CGR0,
-        .enable_shift = MXC_CCM_CGR0_GPT_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk pwm_clk = {
-        .name = "pwm_clk",
-        .parent = &perclk_clk,
-        .enable = _clk_enable,
-        .enable_reg = MXC_CCM_CGR0,
-        .enable_shift = MXC_CCM_CGR1_PWM_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk epit_clk[] = {
-        {
-         .name = "epit_clk",
-         .id = 0,
-         .parent = &perclk_clk,
-         .enable = _clk_enable,
-         .enable_reg = MXC_CCM_CGR0,
-         .enable_shift = MXC_CCM_CGR0_EPIT1_OFFSET,
-         .disable = _clk_disable,},
-        {
-         .name = "epit_clk",
-         .id = 1,
-         .parent = &perclk_clk,
-         .enable = _clk_enable,
-         .enable_reg = MXC_CCM_CGR0,
-         .enable_shift = MXC_CCM_CGR0_EPIT2_OFFSET,
-         .disable = _clk_disable,},
-};
-
-static struct clk nfc_clk = {
-        .name = "nfc_clk",
-        .parent = &ahb_clk,
-        .get_rate = _clk_nfc_get_rate,
-};
-
-static struct clk scc_clk = {
-        .name = "scc_clk",
-        .parent = &ipg_clk,
-};
-
-static struct clk ipu_clk = {
-        .name = "ipu_clk",
-        .parent = &mcu_main_clk,
-        .get_rate = _clk_hsp_get_rate,
-        .enable = _clk_enable,
-        .enable_reg = MXC_CCM_CGR1,
-        .enable_shift = MXC_CCM_CGR1_IPU_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk kpp_clk = {
-        .name = "kpp_clk",
-        .parent = &ipg_clk,
-        .enable = _clk_enable,
-        .enable_reg = MXC_CCM_CGR1,
-        .enable_shift = MXC_CCM_CGR1_KPP_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk wdog_clk = {
-        .name = "wdog_clk",
-        .parent = &ipg_clk,
-        .enable = _clk_enable,
-        .enable_reg = MXC_CCM_CGR1,
-        .enable_shift = MXC_CCM_CGR1_WDOG_OFFSET,
-        .disable = _clk_disable,
-};
-static struct clk rtc_clk = {
-        .name = "rtc_clk",
-        .parent = &ipg_clk,
-        .enable = _clk_enable,
-        .enable_reg = MXC_CCM_CGR1,
-        .enable_shift = MXC_CCM_CGR1_RTC_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk usb_clk[] = {
-        {
-         .name = "usb_clk",
-         .parent = &usb_pll_clk,
-         .get_rate = _clk_usb_get_rate,},
-        {
-         .name = "usb_ahb_clk",
-         .parent = &ahb_clk,
-         .enable = _clk_enable,
-         .enable_reg = MXC_CCM_CGR1,
-         .enable_shift = MXC_CCM_CGR1_USBOTG_OFFSET,
-         .disable = _clk_disable,},
-};
-
-static struct clk csi_clk = {
-        .name = "csi_clk",
-        .parent = &serial_pll_clk,
-        .get_rate = _clk_csi_get_rate,
-        .round_rate = _clk_csi_round_rate,
-        .set_rate = _clk_csi_set_rate,
-        .enable = _clk_enable,
-        .enable_reg = MXC_CCM_CGR1,
-        .enable_shift = MXC_CCM_CGR1_CSI_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk uart_clk[] = {
-        {
-         .name = "uart_clk",
-         .id = 0,
-         .parent = &perclk_clk,
-         .enable = _clk_enable,
-         .enable_reg = MXC_CCM_CGR0,
-         .enable_shift = MXC_CCM_CGR0_UART1_OFFSET,
-         .disable = _clk_disable,},
-        {
-         .name = "uart_clk",
-         .id = 1,
-         .parent = &perclk_clk,
-         .enable = _clk_enable,
-         .enable_reg = MXC_CCM_CGR0,
-         .enable_shift = MXC_CCM_CGR0_UART2_OFFSET,
-         .disable = _clk_disable,},
-        {
-         .name = "uart_clk",
-         .id = 2,
-         .parent = &perclk_clk,
-         .enable = _clk_enable,
-         .enable_reg = MXC_CCM_CGR1,
-         .enable_shift = MXC_CCM_CGR1_UART3_OFFSET,
-         .disable = _clk_disable,},
-        {
-         .name = "uart_clk",
-         .id = 3,
-         .parent = &perclk_clk,
-         .enable = _clk_enable,
-         .enable_reg = MXC_CCM_CGR1,
-         .enable_shift = MXC_CCM_CGR1_UART4_OFFSET,
-         .disable = _clk_disable,},
-        {
-         .name = "uart_clk",
-         .id = 4,
-         .parent = &perclk_clk,
-         .enable = _clk_enable,
-         .enable_reg = MXC_CCM_CGR1,
-         .enable_shift = MXC_CCM_CGR1_UART5_OFFSET,
-         .disable = _clk_disable,},
-};
-
-static struct clk i2c_clk[] = {
-        {
-         .name = "i2c_clk",
-         .id = 0,
-         .parent = &perclk_clk,
-         .enable = _clk_enable,
-         .enable_reg = MXC_CCM_CGR0,
-         .enable_shift = MXC_CCM_CGR0_I2C1_OFFSET,
-         .disable = _clk_disable,},
-        {
-         .name = "i2c_clk",
-         .id = 1,
-         .parent = &perclk_clk,
-         .enable = _clk_enable,
-         .enable_reg = MXC_CCM_CGR0,
-         .enable_shift = MXC_CCM_CGR0_I2C2_OFFSET,
-         .disable = _clk_disable,},
-        {
-         .name = "i2c_clk",
-         .id = 2,
-         .parent = &perclk_clk,
-         .enable = _clk_enable,
-         .enable_reg = MXC_CCM_CGR0,
-         .enable_shift = MXC_CCM_CGR0_I2C3_OFFSET,
-         .disable = _clk_disable,},
-};
-
-static struct clk owire_clk = {
-        .name = "owire_clk",
-        .parent = &perclk_clk,
-        .enable_reg = MXC_CCM_CGR1,
-        .enable_shift = MXC_CCM_CGR1_OWIRE_OFFSET,
-        .enable = _clk_enable,
-        .disable = _clk_disable,
-};
-
-static struct clk sdhc_clk[] = {
-        {
-         .name = "sdhc_clk",
-         .id = 0,
-         .parent = &perclk_clk,
-         .enable = _clk_enable,
-         .enable_reg = MXC_CCM_CGR0,
-         .enable_shift = MXC_CCM_CGR0_SD_MMC1_OFFSET,
-         .disable = _clk_disable,},
-        {
-         .name = "sdhc_clk",
-         .id = 1,
-         .parent = &perclk_clk,
-         .enable = _clk_enable,
-         .enable_reg = MXC_CCM_CGR0,
-         .enable_shift = MXC_CCM_CGR0_SD_MMC2_OFFSET,
-         .disable = _clk_disable,},
-};
-
-static struct clk ssi_clk[] = {
-        {
-         .name = "ssi_clk",
-         .parent = &serial_pll_clk,
-         .get_rate = _clk_ssi1_get_rate,
-         .enable = _clk_enable,
-         .enable_reg = MXC_CCM_CGR0,
-         .enable_shift = MXC_CCM_CGR0_SSI1_OFFSET,
-         .disable = _clk_disable,},
-        {
-         .name = "ssi_clk",
-         .id = 1,
-         .parent = &serial_pll_clk,
-         .get_rate = _clk_ssi2_get_rate,
-         .enable = _clk_enable,
-         .enable_reg = MXC_CCM_CGR2,
-         .enable_shift = MXC_CCM_CGR2_SSI2_OFFSET,
-         .disable = _clk_disable,},
-};
-
-static struct clk firi_clk = {
-        .name = "firi_clk",
-        .parent = &usb_pll_clk,
-        .round_rate = _clk_firi_round_rate,
-        .set_rate = _clk_firi_set_rate,
-        .get_rate = _clk_firi_get_rate,
-        .enable = _clk_enable,
-        .enable_reg = MXC_CCM_CGR2,
-        .enable_shift = MXC_CCM_CGR2_FIRI_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk ata_clk = {
-        .name = "ata_clk",
-        .parent = &ipg_clk,
-        .enable = _clk_enable,
-        .enable_reg = MXC_CCM_CGR0,
-        .enable_shift = MXC_CCM_CGR0_ATA_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk mbx_clk = {
-        .name = "mbx_clk",
-        .parent = &ahb_clk,
-        .enable = _clk_enable,
-        .enable_reg = MXC_CCM_CGR2,
-        .enable_shift = MXC_CCM_CGR2_GACC_OFFSET,
-        .get_rate = _clk_mbx_get_rate,
-};
-
-static struct clk vpu_clk = {
-        .name = "vpu_clk",
-        .parent = &ahb_clk,
-        .enable = _clk_enable,
-        .enable_reg = MXC_CCM_CGR2,
-        .enable_shift = MXC_CCM_CGR2_GACC_OFFSET,
-        .get_rate = _clk_mbx_get_rate,
-};
-
-static struct clk rtic_clk = {
-        .name = "rtic_clk",
-        .parent = &ahb_clk,
-        .enable = _clk_enable,
-        .enable_reg = MXC_CCM_CGR2,
-        .enable_shift = MXC_CCM_CGR2_RTIC_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk rng_clk = {
-        .name = "rng_clk",
-        .parent = &ipg_clk,
-        .enable = _clk_enable,
-        .enable_reg = MXC_CCM_CGR0,
-        .enable_shift = MXC_CCM_CGR0_RNG_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk sdma_clk[] = {
-        {
-         .name = "sdma_ahb_clk",
-         .parent = &ahb_clk,
-         .enable = _clk_enable,
-         .enable_reg = MXC_CCM_CGR0,
-         .enable_shift = MXC_CCM_CGR0_SDMA_OFFSET,
-         .disable = _clk_disable,},
-        {
-         .name = "sdma_ipg_clk",
-         .parent = &ipg_clk,}
-};
-
-static struct clk mpeg4_clk = {
-        .name = "mpeg4_clk",
-        .parent = &ahb_clk,
-        .enable = _clk_enable,
-        .enable_reg = MXC_CCM_CGR1,
-        .enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk vl2cc_clk = {
-        .name = "vl2cc_clk",
-        .parent = &ahb_clk,
-        .enable = _clk_enable,
-        .enable_reg = MXC_CCM_CGR1,
-        .enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET,
-        .disable = _clk_disable,
-};
-
-static struct clk mstick_clk[] = {
-        {
-         .name = "mstick_clk",
-         .id = 0,
-         .parent = &usb_pll_clk,
-         .get_rate = _clk_mstick1_get_rate,
-         .enable = _clk_enable,
-         .enable_reg = MXC_CCM_CGR1,
-         .enable_shift = MXC_CCM_CGR1_MEMSTICK1_OFFSET,
-         .disable = _clk_disable,},
-        {
-         .name = "mstick_clk",
-         .id = 1,
-         .parent = &usb_pll_clk,
-         .get_rate = _clk_mstick2_get_rate,
-         .enable = _clk_enable,
-         .enable_reg = MXC_CCM_CGR1,
-         .enable_shift = MXC_CCM_CGR1_MEMSTICK2_OFFSET,
-         .disable = _clk_disable,},
-};
-
-static struct clk iim_clk = {
-        .name = "iim_clk",
-        .parent = &ipg_clk,
-        .enable = _clk_enable,
-        .enable_reg = MXC_CCM_CGR0,
-        .enable_shift = MXC_CCM_CGR0_IIM_OFFSET,
-        .disable = _clk_disable,
-};
-
-static unsigned long _clk_cko1_round_rate(struct clk *clk, unsigned long rate)
-{
-        u32 div, parent = clk_get_rate(clk->parent);
-
-        div = parent / rate;
-        if (parent % rate)
-                div++;
-
-        if (div > 8)
-                div = 16;
-        else if (div > 4)
-                div = 8;
-        else if (div > 2)
-                div = 4;
-
-        return parent / div;
-}
-
-static int _clk_cko1_set_rate(struct clk *clk, unsigned long rate)
-{
-        u32 reg, div, parent = clk_get_rate(clk->parent);
-
-        div = parent / rate;
-
-        if (div == 16)
-                div = 4;
-        else if (div == 8)
-                div = 3;
-        else if (div == 4)
-                div = 2;
-        else if (div == 2)
-                div = 1;
-        else if (div == 1)
-                div = 0;
-        else
-                return -EINVAL;
-
-        reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOUTDIV_MASK;
-        reg |= div << MXC_CCM_COSR_CLKOUTDIV_OFFSET;
-        __raw_writel(reg, MXC_CCM_COSR);
-
-        return 0;
-}
-
-static unsigned long _clk_cko1_get_rate(struct clk *clk)
-{
-        u32 div;
-
-        div = __raw_readl(MXC_CCM_COSR) & MXC_CCM_COSR_CLKOUTDIV_MASK >>
-            MXC_CCM_COSR_CLKOUTDIV_OFFSET;
-
-        return clk_get_rate(clk->parent) / (1 << div);
-}
-
-static int _clk_cko1_set_parent(struct clk *clk, struct clk *parent)
-{
-        u32 reg;
-
-        reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOSEL_MASK;
-
-        if (parent == &mcu_main_clk)
-                reg |= 0 << MXC_CCM_COSR_CLKOSEL_OFFSET;
-        else if (parent == &ipg_clk)
-                reg |= 1 << MXC_CCM_COSR_CLKOSEL_OFFSET;
-        else if (parent == &usb_pll_clk)
-                reg |= 2 << MXC_CCM_COSR_CLKOSEL_OFFSET;
-        else if (parent == mcu_main_clk.parent)
-                reg |= 3 << MXC_CCM_COSR_CLKOSEL_OFFSET;
-        else if (parent == &ahb_clk)
-                reg |= 5 << MXC_CCM_COSR_CLKOSEL_OFFSET;
-        else if (parent == &serial_pll_clk)
-                reg |= 7 << MXC_CCM_COSR_CLKOSEL_OFFSET;
-        else if (parent == &ckih_clk)
-                reg |= 8 << MXC_CCM_COSR_CLKOSEL_OFFSET;
-        else if (parent == &emi_clk)
-                reg |= 9 << MXC_CCM_COSR_CLKOSEL_OFFSET;
-        else if (parent == &ipu_clk)
-                reg |= 0xA << MXC_CCM_COSR_CLKOSEL_OFFSET;
-        else if (parent == &nfc_clk)
-                reg |= 0xB << MXC_CCM_COSR_CLKOSEL_OFFSET;
-        else if (parent == &uart_clk[0])
-                reg |= 0xC << MXC_CCM_COSR_CLKOSEL_OFFSET;
-        else
-                return -EINVAL;
-
-        __raw_writel(reg, MXC_CCM_COSR);
-
-        return 0;
-}
-
-static int _clk_cko1_enable(struct clk *clk)
-{
-        u32 reg;
-
-        reg = __raw_readl(MXC_CCM_COSR) | MXC_CCM_COSR_CLKOEN;
-        __raw_writel(reg, MXC_CCM_COSR);
+        .get_rate = ahb_get_rate,
+};
+
+#define DEFINE_CLOCK(name, i, er, es, gr, s, p)         \
+        static struct clk name = {                      \
+                .id             = i,                    \
+                .enable_reg     = er,                   \
+                .enable_shift   = es,                   \
+                .get_rate       = gr,                   \
+                .enable         = cgr_enable,           \
+                .disable        = cgr_disable,          \
+                .secondary      = s,                    \
+                .parent         = p,                    \
+        }
 
-        return 0;
-}
+#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p)       \
+        static struct clk name = {                              \
+                .id             = i,                            \
+                .enable_reg     = er,                           \
+                .enable_shift   = es,                           \
+                .get_rate       = getsetround##_get_rate,       \
+                .set_rate       = getsetround##_set_rate,       \
+                .round_rate     = getsetround##_round_rate,     \
+                .enable         = cgr_enable,                   \
+                .disable        = cgr_disable,                  \
+                .secondary      = s,                            \
+                .parent         = p,                            \
+        }
 
-static void _clk_cko1_disable(struct clk *clk)
+DEFINE_CLOCK(perclk_clk,  0, NULL,          0, NULL, NULL, &ipg_clk);
+
+DEFINE_CLOCK(sdhc1_clk,   0, MXC_CCM_CGR0,  0, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(sdhc2_clk,   1, MXC_CCM_CGR0,  2, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(gpt_clk,     0, MXC_CCM_CGR0,  4, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(epit1_clk,   0, MXC_CCM_CGR0,  6, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(epit2_clk,   1, MXC_CCM_CGR0,  8, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(iim_clk,     0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(ata_clk,     0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(sdma_clk1,   0, MXC_CCM_CGR0, 14, NULL, &sdma_clk1, &ahb_clk);
+DEFINE_CLOCK(cspi3_clk,   2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(rng_clk,     0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(uart1_clk,   0, MXC_CCM_CGR0, 20, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(uart2_clk,   1, MXC_CCM_CGR0, 22, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(ssi1_clk,    0, MXC_CCM_CGR0, 24, ssi1_get_rate, NULL, &serial_pll_clk);
+DEFINE_CLOCK(i2c1_clk,    0, MXC_CCM_CGR0, 26, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(i2c2_clk,    1, MXC_CCM_CGR0, 28, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(i2c3_clk,    2, MXC_CCM_CGR0, 30, NULL, NULL, &perclk_clk);
+
+DEFINE_CLOCK(mpeg4_clk,   0, MXC_CCM_CGR1,  0, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1,  2, mstick1_get_rate, NULL, &usb_pll_clk);
+DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1,  4, mstick2_get_rate, NULL, &usb_pll_clk);
+DEFINE_CLOCK1(csi_clk,    0, MXC_CCM_CGR1,  6, csi, NULL, &ahb_clk);
+DEFINE_CLOCK(rtc_clk,     0, MXC_CCM_CGR1,  8, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(wdog_clk,    0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(pwm_clk,     0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(usb_clk2,    0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk);
+DEFINE_CLOCK(kpp_clk,     0, MXC_CCM_CGR1, 20, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(ipu_clk,     0, MXC_CCM_CGR1, 22, hsp_get_rate, NULL, &mcu_main_clk);
+DEFINE_CLOCK(uart3_clk,   2, MXC_CCM_CGR1, 24, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(uart4_clk,   3, MXC_CCM_CGR1, 26, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(uart5_clk,   4, MXC_CCM_CGR1, 28, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(owire_clk,   0, MXC_CCM_CGR1, 30, NULL, NULL, &perclk_clk);
+
+DEFINE_CLOCK(ssi2_clk,    1, MXC_CCM_CGR2,  0, ssi2_get_rate, NULL, &serial_pll_clk);
+DEFINE_CLOCK(cspi1_clk,   0, MXC_CCM_CGR2,  2, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(cspi2_clk,   1, MXC_CCM_CGR2,  4, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(mbx_clk,     0, MXC_CCM_CGR2,  6, mbx_get_rate, NULL, &ahb_clk);
+DEFINE_CLOCK(emi_clk,     0, MXC_CCM_CGR2,  8, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(rtic_clk,    0, MXC_CCM_CGR2, 10, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK1(firi_clk,   0, MXC_CCM_CGR2, 12, firi, NULL, &usb_pll_clk);
+
+DEFINE_CLOCK(sdma_clk2,   0, NULL,          0, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(usb_clk1,    0, NULL,          0, usb_get_rate, NULL, &usb_pll_clk);
+DEFINE_CLOCK(nfc_clk,     0, NULL,          0, nfc_get_rate, NULL, &ahb_clk);
+DEFINE_CLOCK(scc_clk,     0, NULL,          0, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(ipg_clk,     0, NULL,          0, ipg_get_rate, NULL, &ahb_clk);
+
+#define _REGISTER_CLOCK(d, n, c) \
+        { \
+                .dev_id = d, \
+                .con_id = n, \
+                .clk = &c, \
+        },
+
+static struct clk_lookup lookups[] __initdata = {
+        _REGISTER_CLOCK(NULL, "emi", emi_clk)
+        _REGISTER_CLOCK(NULL, "cspi", cspi1_clk)
+        _REGISTER_CLOCK(NULL, "cspi", cspi2_clk)
+        _REGISTER_CLOCK(NULL, "cspi", cspi3_clk)
+        _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
+        _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
+        _REGISTER_CLOCK(NULL, "wdog", wdog_clk)
+        _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
+        _REGISTER_CLOCK(NULL, "epit", epit1_clk)
+        _REGISTER_CLOCK(NULL, "epit", epit2_clk)
+        _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
+        _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
+        _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
+        _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2)
+        _REGISTER_CLOCK("mx3-camera.0", "csi", csi_clk)
+        _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
+        _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
+        _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
+        _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
+        _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
+        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
+        _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
+        _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
+        _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
+        _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
+        _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
+        _REGISTER_CLOCK(NULL, "ssi", ssi1_clk)
+        _REGISTER_CLOCK(NULL, "ssi", ssi2_clk)
+        _REGISTER_CLOCK(NULL, "firi", firi_clk)
+        _REGISTER_CLOCK(NULL, "ata", ata_clk)
+        _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
+        _REGISTER_CLOCK(NULL, "rng", rng_clk)
+        _REGISTER_CLOCK(NULL, "sdma_ahb", sdma_clk1)
+        _REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2)
+        _REGISTER_CLOCK(NULL, "mstick", mstick1_clk)
+        _REGISTER_CLOCK(NULL, "mstick", mstick2_clk)
+        _REGISTER_CLOCK(NULL, "scc", scc_clk)
+        _REGISTER_CLOCK(NULL, "iim", iim_clk)
+        _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
+        _REGISTER_CLOCK(NULL, "mbx", mbx_clk)
+};
+
+int __init mx31_clocks_init(unsigned long fref)
 {
         u32 reg;
+        int i;
 
-        reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOEN;
-        __raw_writel(reg, MXC_CCM_COSR);
-}
-
-static struct clk cko1_clk = {
-        .name = "cko1_clk",
-        .get_rate = _clk_cko1_get_rate,
-        .set_rate = _clk_cko1_set_rate,
-        .round_rate = _clk_cko1_round_rate,
-        .set_parent = _clk_cko1_set_parent,
-        .enable = _clk_cko1_enable,
-        .disable = _clk_cko1_disable,
-};
-
-static struct clk *mxc_clks[] = {
-        &ckih_clk,
-        &ckil_clk,
-        &mcu_pll_clk,
-        &usb_pll_clk,
-        &serial_pll_clk,
-        &mcu_main_clk,
-        &ahb_clk,
-        &per_clk,
-        &perclk_clk,
-        &cko1_clk,
-        &emi_clk,
-        &cspi_clk[0],
-        &cspi_clk[1],
-        &cspi_clk[2],
-        &ipg_clk,
-        &gpt_clk,
-        &pwm_clk,
-        &wdog_clk,
-        &rtc_clk,
-        &epit_clk[0],
-        &epit_clk[1],
-        &nfc_clk,
-        &ipu_clk,
-        &kpp_clk,
-        &usb_clk[0],
-        &usb_clk[1],
-        &csi_clk,
-        &uart_clk[0],
-        &uart_clk[1],
-        &uart_clk[2],
-        &uart_clk[3],
-        &uart_clk[4],
-        &i2c_clk[0],
-        &i2c_clk[1],
-        &i2c_clk[2],
-        &owire_clk,
-        &sdhc_clk[0],
-        &sdhc_clk[1],
-        &ssi_clk[0],
-        &ssi_clk[1],
-        &firi_clk,
-        &ata_clk,
-        &rtic_clk,
-        &rng_clk,
-        &sdma_clk[0],
-        &sdma_clk[1],
-        &mstick_clk[0],
-        &mstick_clk[1],
-        &scc_clk,
-        &iim_clk,
-};
-
-int __init mxc_clocks_init(unsigned long fref)
-{
-        u32 reg;
-        struct clk **clkp;
+        mxc_set_cpu_type(MXC_CPU_MX31);
 
         ckih_rate = fref;
 
-        for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++)
-                clk_register(*clkp);
-
-        if (cpu_is_mx31()) {
-                clk_register(&mpeg4_clk);
-                clk_register(&mbx_clk);
-        } else {
-                clk_register(&vpu_clk);
-                clk_register(&vl2cc_clk);
-        }
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
 
         /* Turn off all possible clocks */
-        __raw_writel(MXC_CCM_CGR0_GPT_MASK, MXC_CCM_CGR0);
+        __raw_writel((3 << 4), MXC_CCM_CGR0);
         __raw_writel(0, MXC_CCM_CGR1);
-
-        __raw_writel(MXC_CCM_CGR2_EMI_MASK |
-                     MXC_CCM_CGR2_IPMUX1_MASK |
-                     MXC_CCM_CGR2_IPMUX2_MASK |
-                     MXC_CCM_CGR2_MXCCLKENSEL_MASK |    /* for MX32 */
-                     MXC_CCM_CGR2_CHIKCAMPEN_MASK |     /* for MX32 */
-                     MXC_CCM_CGR2_OVRVPUBUSY_MASK |     /* for MX32 */
+        __raw_writel((3 << 8) | (3 << 14) | (3 << 16)|
                      1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for
                                            MX32, but still required to be set */
                      MXC_CCM_CGR2);
 
-        clk_disable(&cko1_clk);
-        clk_disable(&usb_pll_clk);
+        usb_pll_disable(&usb_pll_clk);
 
         pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk));
 
@@ -1143,6 +598,8 @@ int __init mxc_clocks_init(unsigned long fref)
                 __raw_writel(reg, MXC_CCM_PMCR1);
         }
 
+        mxc_timer_init(&ipg_clk);
+
         return 0;
 }
 
diff --git a/arch/arm/mach-mx3/crm_regs.h b/arch/arm/mach-mx3/crm_regs.h
index 4a0e0ede23bb..adfa3627ad84 100644
--- a/arch/arm/mach-mx3/crm_regs.h
+++ b/arch/arm/mach-mx3/crm_regs.h
@@ -91,47 +91,6 @@
 #define MXC_CCM_PDR0_MCU_PODF_OFFSET            0
 #define MXC_CCM_PDR0_MCU_PODF_MASK              0x7
 
-#define MXC_CCM_PDR0_HSP_DIV_1                  (0x0 << 11)
-#define MXC_CCM_PDR0_HSP_DIV_2                  (0x1 << 11)
-#define MXC_CCM_PDR0_HSP_DIV_3                  (0x2 << 11)
-#define MXC_CCM_PDR0_HSP_DIV_4                  (0x3 << 11)
-#define MXC_CCM_PDR0_HSP_DIV_5                  (0x4 << 11)
-#define MXC_CCM_PDR0_HSP_DIV_6                  (0x5 << 11)
-#define MXC_CCM_PDR0_HSP_DIV_7                  (0x6 << 11)
-#define MXC_CCM_PDR0_HSP_DIV_8                  (0x7 << 11)
-
-#define MXC_CCM_PDR0_IPG_DIV_1                  (0x0 << 6)
-#define MXC_CCM_PDR0_IPG_DIV_2                  (0x1 << 6)
-#define MXC_CCM_PDR0_IPG_DIV_3                  (0x2 << 6)
-#define MXC_CCM_PDR0_IPG_DIV_4                  (0x3 << 6)
-
-#define MXC_CCM_PDR0_MAX_DIV_1                  (0x0 << 3)
-#define MXC_CCM_PDR0_MAX_DIV_2                  (0x1 << 3)
-#define MXC_CCM_PDR0_MAX_DIV_3                  (0x2 << 3)
-#define MXC_CCM_PDR0_MAX_DIV_4                  (0x3 << 3)
-#define MXC_CCM_PDR0_MAX_DIV_5                  (0x4 << 3)
-#define MXC_CCM_PDR0_MAX_DIV_6                  (0x5 << 3)
-#define MXC_CCM_PDR0_MAX_DIV_7                  (0x6 << 3)
-#define MXC_CCM_PDR0_MAX_DIV_8                  (0x7 << 3)
-
-#define MXC_CCM_PDR0_NFC_DIV_1                  (0x0 << 8)
-#define MXC_CCM_PDR0_NFC_DIV_2                  (0x1 << 8)
-#define MXC_CCM_PDR0_NFC_DIV_3                  (0x2 << 8)
-#define MXC_CCM_PDR0_NFC_DIV_4                  (0x3 << 8)
-#define MXC_CCM_PDR0_NFC_DIV_5                  (0x4 << 8)
-#define MXC_CCM_PDR0_NFC_DIV_6                  (0x5 << 8)
-#define MXC_CCM_PDR0_NFC_DIV_7                  (0x6 << 8)
-#define MXC_CCM_PDR0_NFC_DIV_8                  (0x7 << 8)
-
-#define MXC_CCM_PDR0_MCU_DIV_1                  0x0
-#define MXC_CCM_PDR0_MCU_DIV_2                  0x1
-#define MXC_CCM_PDR0_MCU_DIV_3                  0x2
-#define MXC_CCM_PDR0_MCU_DIV_4                  0x3
-#define MXC_CCM_PDR0_MCU_DIV_5                  0x4
-#define MXC_CCM_PDR0_MCU_DIV_6                  0x5
-#define MXC_CCM_PDR0_MCU_DIV_7                  0x6
-#define MXC_CCM_PDR0_MCU_DIV_8                  0x7
-
 #define MXC_CCM_PDR1_USB_PRDF_OFFSET            30
 #define MXC_CCM_PDR1_USB_PRDF_MASK              (0x3 << 30)
 #define MXC_CCM_PDR1_USB_PODF_OFFSET            27
@@ -152,118 +111,6 @@
 /* Bit definitions for RCSR */
 #define MXC_CCM_RCSR_NF16B                      0x80000000
 
-/* Bit definitions for both MCU, USB and SR PLL control registers */
-#define MXC_CCM_PCTL_BRM                        0x80000000
-#define MXC_CCM_PCTL_PD_OFFSET                  26
-#define MXC_CCM_PCTL_PD_MASK                    (0xF << 26)
-#define MXC_CCM_PCTL_MFD_OFFSET                 16
-#define MXC_CCM_PCTL_MFD_MASK                   (0x3FF << 16)
-#define MXC_CCM_PCTL_MFI_OFFSET                 10
-#define MXC_CCM_PCTL_MFI_MASK                   (0xF << 10)
-#define MXC_CCM_PCTL_MFN_OFFSET                 0
-#define MXC_CCM_PCTL_MFN_MASK                   0x3FF
-
-#define MXC_CCM_CGR0_SD_MMC1_OFFSET             0
-#define MXC_CCM_CGR0_SD_MMC1_MASK               (0x3 << 0)
-#define MXC_CCM_CGR0_SD_MMC2_OFFSET             2
-#define MXC_CCM_CGR0_SD_MMC2_MASK               (0x3 << 2)
-#define MXC_CCM_CGR0_GPT_OFFSET                 4
-#define MXC_CCM_CGR0_GPT_MASK                   (0x3 << 4)
-#define MXC_CCM_CGR0_EPIT1_OFFSET               6
-#define MXC_CCM_CGR0_EPIT1_MASK                 (0x3 << 6)
-#define MXC_CCM_CGR0_EPIT2_OFFSET               8
-#define MXC_CCM_CGR0_EPIT2_MASK                 (0x3 << 8)
-#define MXC_CCM_CGR0_IIM_OFFSET                 10
-#define MXC_CCM_CGR0_IIM_MASK                   (0x3 << 10)
-#define MXC_CCM_CGR0_ATA_OFFSET                 12
-#define MXC_CCM_CGR0_ATA_MASK                   (0x3 << 12)
-#define MXC_CCM_CGR0_SDMA_OFFSET                14
-#define MXC_CCM_CGR0_SDMA_MASK                  (0x3 << 14)
-#define MXC_CCM_CGR0_CSPI3_OFFSET               16
-#define MXC_CCM_CGR0_CSPI3_MASK                 (0x3 << 16)
-#define MXC_CCM_CGR0_RNG_OFFSET                 18
-#define MXC_CCM_CGR0_RNG_MASK                   (0x3 << 18)
-#define MXC_CCM_CGR0_UART1_OFFSET               20
-#define MXC_CCM_CGR0_UART1_MASK                 (0x3 << 20)
-#define MXC_CCM_CGR0_UART2_OFFSET               22
-#define MXC_CCM_CGR0_UART2_MASK                 (0x3 << 22)
-#define MXC_CCM_CGR0_SSI1_OFFSET                24
-#define MXC_CCM_CGR0_SSI1_MASK                  (0x3 << 24)
-#define MXC_CCM_CGR0_I2C1_OFFSET                26
-#define MXC_CCM_CGR0_I2C1_MASK                  (0x3 << 26)
-#define MXC_CCM_CGR0_I2C2_OFFSET                28
-#define MXC_CCM_CGR0_I2C2_MASK                  (0x3 << 28)
-#define MXC_CCM_CGR0_I2C3_OFFSET                30
-#define MXC_CCM_CGR0_I2C3_MASK                  (0x3 << 30)
-
-#define MXC_CCM_CGR1_HANTRO_OFFSET              0
-#define MXC_CCM_CGR1_HANTRO_MASK                (0x3 << 0)
-#define MXC_CCM_CGR1_MEMSTICK1_OFFSET           2
-#define MXC_CCM_CGR1_MEMSTICK1_MASK             (0x3 << 2)
-#define MXC_CCM_CGR1_MEMSTICK2_OFFSET           4
-#define MXC_CCM_CGR1_MEMSTICK2_MASK             (0x3 << 4)
-#define MXC_CCM_CGR1_CSI_OFFSET                 6
-#define MXC_CCM_CGR1_CSI_MASK                   (0x3 << 6)
-#define MXC_CCM_CGR1_RTC_OFFSET                 8
-#define MXC_CCM_CGR1_RTC_MASK                   (0x3 << 8)
-#define MXC_CCM_CGR1_WDOG_OFFSET                10
-#define MXC_CCM_CGR1_WDOG_MASK                  (0x3 << 10)
-#define MXC_CCM_CGR1_PWM_OFFSET                 12
-#define MXC_CCM_CGR1_PWM_MASK                   (0x3 << 12)
-#define MXC_CCM_CGR1_SIM_OFFSET                 14
-#define MXC_CCM_CGR1_SIM_MASK                   (0x3 << 14)
-#define MXC_CCM_CGR1_ECT_OFFSET                 16
-#define MXC_CCM_CGR1_ECT_MASK                   (0x3 << 16)
-#define MXC_CCM_CGR1_USBOTG_OFFSET              18
-#define MXC_CCM_CGR1_USBOTG_MASK                (0x3 << 18)
-#define MXC_CCM_CGR1_KPP_OFFSET                 20
-#define MXC_CCM_CGR1_KPP_MASK                   (0x3 << 20)
-#define MXC_CCM_CGR1_IPU_OFFSET                 22
-#define MXC_CCM_CGR1_IPU_MASK                   (0x3 << 22)
-#define MXC_CCM_CGR1_UART3_OFFSET               24
-#define MXC_CCM_CGR1_UART3_MASK                 (0x3 << 24)
-#define MXC_CCM_CGR1_UART4_OFFSET               26
-#define MXC_CCM_CGR1_UART4_MASK                 (0x3 << 26)
-#define MXC_CCM_CGR1_UART5_OFFSET               28
-#define MXC_CCM_CGR1_UART5_MASK                 (0x3 << 28)
-#define MXC_CCM_CGR1_OWIRE_OFFSET               30
-#define MXC_CCM_CGR1_OWIRE_MASK                 (0x3 << 30)
-
-#define MXC_CCM_CGR2_SSI2_OFFSET                0
-#define MXC_CCM_CGR2_SSI2_MASK                  (0x3 << 0)
-#define MXC_CCM_CGR2_CSPI1_OFFSET               2
-#define MXC_CCM_CGR2_CSPI1_MASK                 (0x3 << 2)
-#define MXC_CCM_CGR2_CSPI2_OFFSET               4
-#define MXC_CCM_CGR2_CSPI2_MASK                 (0x3 << 4)
-#define MXC_CCM_CGR2_GACC_OFFSET                6
-#define MXC_CCM_CGR2_GACC_MASK                  (0x3 << 6)
-#define MXC_CCM_CGR2_EMI_OFFSET                 8
-#define MXC_CCM_CGR2_EMI_MASK                   (0x3 << 8)
-#define MXC_CCM_CGR2_RTIC_OFFSET                10
-#define MXC_CCM_CGR2_RTIC_MASK                  (0x3 << 10)
-#define MXC_CCM_CGR2_FIRI_OFFSET                12
-#define MXC_CCM_CGR2_FIRI_MASK                  (0x3 << 12)
-#define MXC_CCM_CGR2_IPMUX1_OFFSET              14
-#define MXC_CCM_CGR2_IPMUX1_MASK                (0x3 << 14)
-#define MXC_CCM_CGR2_IPMUX2_OFFSET              16
-#define MXC_CCM_CGR2_IPMUX2_MASK                (0x3 << 16)
-
-/* These new CGR2 bits are added in MX32 */
-#define MXC_CCM_CGR2_APMSYSCLKSEL_OFFSET        18
-#define MXC_CCM_CGR2_APMSYSCLKSEL_MASK          (0x3 << 18)
-#define MXC_CCM_CGR2_APMSSICLKSEL_OFFSET        20
-#define MXC_CCM_CGR2_APMSSICLKSEL_MASK          (0x3 << 20)
-#define MXC_CCM_CGR2_APMPERCLKSEL_OFFSET        22
-#define MXC_CCM_CGR2_APMPERCLKSEL_MASK          (0x3 << 22)
-#define MXC_CCM_CGR2_MXCCLKENSEL_OFFSET         24
-#define MXC_CCM_CGR2_MXCCLKENSEL_MASK           (0x1 << 24)
-#define MXC_CCM_CGR2_CHIKCAMPEN_OFFSET          25
-#define MXC_CCM_CGR2_CHIKCAMPEN_MASK            (0x1 << 25)
-#define MXC_CCM_CGR2_OVRVPUBUSY_OFFSET          26
-#define MXC_CCM_CGR2_OVRVPUBUSY_MASK            (0x1 << 26)
-#define MXC_CCM_CGR2_APMENA_OFFSET              30
-#define MXC_CCM_CGR2_AOMENA_MASK                (0x1 << 30)
-
 /*
  * LTR0 register offsets
  */
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index f8428800f286..380be0c9b213 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -25,6 +25,8 @@
 #include <mach/irqs.h>
 #include <mach/imx-uart.h>
 
+#include "devices.h"
+
 static struct resource uart0[] = {
         {
                 .start = UART1_BASE_ADDR,
@@ -82,6 +84,7 @@ struct platform_device mxc_uart_device2 = {
         .num_resources = ARRAY_SIZE(uart2),
 };
 
+#ifdef CONFIG_ARCH_MX31
 static struct resource uart3[] = {
         {
                 .start = UART4_BASE_ADDR,
@@ -119,6 +122,7 @@ struct platform_device mxc_uart_device4 = {
         .resource = uart4,
         .num_resources = ARRAY_SIZE(uart4),
 };
+#endif /* CONFIG_ARCH_MX31 */
 
 /* GPIO port description */
 static struct mxc_gpio_port imx_gpio_ports[] = {
@@ -164,8 +168,8 @@ struct platform_device mxc_w1_master_device = {
 
 static struct resource mxc_nand_resources[] = {
         {
-                .start  = NFC_BASE_ADDR,
-                .end    = NFC_BASE_ADDR + 0xfff,
+                .start  = 0, /* runtime dependent */
+                .end    = 0,
                 .flags  = IORESOURCE_MEM
         }, {
                 .start  = MXC_INT_NANDFC,
@@ -180,3 +184,188 @@ struct platform_device mxc_nand_device = {
         .num_resources = ARRAY_SIZE(mxc_nand_resources),
         .resource = mxc_nand_resources,
 };
+
+static struct resource mxc_i2c0_resources[] = {
+        {
+                .start = I2C_BASE_ADDR,
+                .end = I2C_BASE_ADDR + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = MXC_INT_I2C,
+                .end = MXC_INT_I2C,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_i2c_device0 = {
+        .name = "imx-i2c",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_i2c0_resources),
+        .resource = mxc_i2c0_resources,
+};
+
+static struct resource mxc_i2c1_resources[] = {
+        {
+                .start = I2C2_BASE_ADDR,
+                .end = I2C2_BASE_ADDR + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = MXC_INT_I2C2,
+                .end = MXC_INT_I2C2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_i2c_device1 = {
+        .name = "imx-i2c",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_i2c1_resources),
+        .resource = mxc_i2c1_resources,
+};
+
+static struct resource mxc_i2c2_resources[] = {
+        {
+                .start = I2C3_BASE_ADDR,
+                .end = I2C3_BASE_ADDR + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = MXC_INT_I2C3,
+                .end = MXC_INT_I2C3,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_i2c_device2 = {
+        .name = "imx-i2c",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(mxc_i2c2_resources),
+        .resource = mxc_i2c2_resources,
+};
+
+#ifdef CONFIG_ARCH_MX31
+static struct resource mxcsdhc0_resources[] = {
+        {
+                .start = MMC_SDHC1_BASE_ADDR,
+                .end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_MMC_SDHC1,
+                .end = MXC_INT_MMC_SDHC1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource mxcsdhc1_resources[] = {
+        {
+                .start = MMC_SDHC2_BASE_ADDR,
+                .end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_MMC_SDHC2,
+                .end = MXC_INT_MMC_SDHC2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxcsdhc_device0 = {
+        .name = "mxc-mmc",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxcsdhc0_resources),
+        .resource = mxcsdhc0_resources,
+};
+
+struct platform_device mxcsdhc_device1 = {
+        .name = "mxc-mmc",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxcsdhc1_resources),
+        .resource = mxcsdhc1_resources,
+};
+#endif /* CONFIG_ARCH_MX31 */
+
+/* i.MX31 Image Processing Unit */
+
+/* The resource order is important! */
+static struct resource mx3_ipu_rsrc[] = {
+        {
+                .start = IPU_CTRL_BASE_ADDR,
+                .end = IPU_CTRL_BASE_ADDR + 0x5F,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = IPU_CTRL_BASE_ADDR + 0x88,
+                .end = IPU_CTRL_BASE_ADDR + 0xB3,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_IPU_SYN,
+                .end = MXC_INT_IPU_SYN,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC_INT_IPU_ERR,
+                .end = MXC_INT_IPU_ERR,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mx3_ipu = {
+        .name = "ipu-core",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
+        .resource = mx3_ipu_rsrc,
+};
+
+static struct resource fb_resources[] = {
+        {
+                .start  = IPU_CTRL_BASE_ADDR + 0xB4,
+                .end    = IPU_CTRL_BASE_ADDR + 0x1BF,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device mx3_fb = {
+        .name           = "mx3_sdc_fb",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(fb_resources),
+        .resource       = fb_resources,
+        .dev            = {
+                .coherent_dma_mask = 0xffffffff,
+       },
+};
+
+#ifdef CONFIG_ARCH_MX35
+static struct resource mxc_fec_resources[] = {
+        {
+                .start  = MXC_FEC_BASE_ADDR,
+                .end    = MXC_FEC_BASE_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM
+        }, {
+                .start  = MXC_INT_FEC,
+                .end    = MXC_INT_FEC,
+                .flags  = IORESOURCE_IRQ
+        },
+};
+
+struct platform_device mxc_fec_device = {
+        .name = "fec",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_fec_resources),
+        .resource = mxc_fec_resources,
+};
+#endif
+
+static int mx3_devices_init(void)
+{
+        if (cpu_is_mx31()) {
+                mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
+                mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
+        }
+        if (cpu_is_mx35()) {
+                mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
+                mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff;
+        }
+
+        return 0;
+}
+
+subsys_initcall(mx3_devices_init);
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index 9949ef4e0694..88c04b296fab 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -6,3 +6,11 @@ extern struct platform_device mxc_uart_device3;
 extern struct platform_device mxc_uart_device4;
 extern struct platform_device mxc_w1_master_device;
 extern struct platform_device mxc_nand_device;
+extern struct platform_device mxc_i2c_device0;
+extern struct platform_device mxc_i2c_device1;
+extern struct platform_device mxc_i2c_device2;
+extern struct platform_device mx3_ipu;
+extern struct platform_device mx3_fb;
+extern struct platform_device mxc_fec_device;
+extern struct platform_device mxcsdhc_device0;
+extern struct platform_device mxcsdhc_device1;
diff --git a/arch/arm/mach-mx3/iomux.c b/arch/arm/mach-mx3/iomux.c
index 7a5088b519a8..40ffc5a664d9 100644
--- a/arch/arm/mach-mx3/iomux.c
+++ b/arch/arm/mach-mx3/iomux.c
@@ -1,6 +1,7 @@
 /*
  * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ * Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -21,6 +22,7 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/kernel.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
 #include <mach/iomux-mx3.h>
@@ -38,6 +40,8 @@
 static DEFINE_SPINLOCK(gpio_mux_lock);
 
 #define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
+
+unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
 /*
  * set the mode for a IOMUX pin.
  */
@@ -50,9 +54,6 @@ int mxc_iomux_mode(unsigned int pin_mode)
         field = pin_mode & 0x3;
         mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT;
 
-        pr_debug("%s: reg offset = 0x%x field = %d mode = 0x%02x\n",
-                        __func__, (pin_mode & IOMUX_REG_MASK), field, mode);
-
         spin_lock(&gpio_mux_lock);
 
         l = __raw_readl(reg);
@@ -93,6 +94,86 @@ void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
 EXPORT_SYMBOL(mxc_iomux_set_pad);
 
 /*
+ * setups a single pin:
+ *      - reserves the pin so that it is not claimed by another driver
+ *      - setups the iomux according to the configuration
+ *      - if the pin is configured as a GPIO, we claim it through kernel gpiolib
+ */
+int mxc_iomux_setup_pin(const unsigned int pin, const char *label)
+{
+        unsigned pad = pin & IOMUX_PADNUM_MASK;
+        unsigned gpio;
+
+        if (pad >= (PIN_MAX + 1)) {
+                printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n",
+                        pad, label ? label : "?");
+                return -EINVAL;
+        }
+
+        if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
+                printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
+                        pad, label ? label : "?");
+                return -EINVAL;
+        }
+        mxc_iomux_mode(pin);
+
+        /* if we have a gpio, we can allocate it */
+        gpio = (pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT;
+        if (gpio < (GPIO_PORT_MAX + 1) * 32)
+                if (gpio_request(gpio, label))
+                        return -EINVAL;
+
+        return 0;
+}
+EXPORT_SYMBOL(mxc_iomux_setup_pin);
+
+int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
+                const char *label)
+{
+        unsigned int *p = pin_list;
+        int i;
+        int ret = -EINVAL;
+
+        for (i = 0; i < count; i++) {
+                if (mxc_iomux_setup_pin(*p, label))
+                        goto setup_error;
+                p++;
+        }
+        return 0;
+
+setup_error:
+        mxc_iomux_release_multiple_pins(pin_list, i);
+        return ret;
+}
+EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
+
+void mxc_iomux_release_pin(const unsigned int pin)
+{
+        unsigned pad = pin & IOMUX_PADNUM_MASK;
+        unsigned gpio;
+
+        if (pad < (PIN_MAX + 1))
+                clear_bit(pad, mxc_pin_alloc_map);
+
+        gpio = (pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT;
+        if (gpio < (GPIO_PORT_MAX + 1) * 32)
+                gpio_free(gpio);
+}
+EXPORT_SYMBOL(mxc_iomux_release_pin);
+
+void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count)
+{
+        unsigned int *p = pin_list;
+        int i;
+
+        for (i = 0; i < count; i++) {
+                mxc_iomux_release_pin(*p);
+                p++;
+        }
+}
+EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
+
+/*
  * This function enables/disables the general purpose function for a particular
  * signal.
  */
@@ -111,4 +192,3 @@ void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
         spin_unlock(&gpio_mux_lock);
 }
 EXPORT_SYMBOL(mxc_iomux_set_gpr);
-
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index 0589b5cd33c7..9e1459cb4b74 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -22,10 +22,14 @@
 
 #include <linux/mm.h>
 #include <linux/init.h>
-#include <mach/hardware.h>
+#include <linux/err.h>
+
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
+#include <asm/hardware/cache-l2x0.h>
+
 #include <mach/common.h>
+#include <mach/hardware.h>
 
 /*!
  * @file mm.c
@@ -50,6 +54,16 @@ static struct map_desc mxc_io_desc[] __initdata = {
                 .pfn            = __phys_to_pfn(AVIC_BASE_ADDR),
                 .length         = AVIC_SIZE,
                 .type           = MT_DEVICE_NONSHARED
+        }, {
+                .virtual        = AIPS1_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(AIPS1_BASE_ADDR),
+                .length         = AIPS1_SIZE,
+                .type           = MT_DEVICE_NONSHARED
+        }, {
+                .virtual        = AIPS2_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(AIPS2_BASE_ADDR),
+                .length         = AIPS2_SIZE,
+                .type           = MT_DEVICE_NONSHARED
         },
 };
 
@@ -62,3 +76,24 @@ void __init mxc_map_io(void)
 {
         iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
+
+#ifdef CONFIG_CACHE_L2X0
+static int mxc_init_l2x0(void)
+{
+        void __iomem *l2x0_base;
+
+        l2x0_base = ioremap(L2CC_BASE_ADDR, 4096);
+        if (IS_ERR(l2x0_base)) {
+                printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
+                                PTR_ERR(l2x0_base));
+                return 0;
+        }
+
+        l2x0_init(l2x0_base, 0x00030024, 0x00000000);
+
+        return 0;
+}
+
+arch_initcall(mxc_init_l2x0);
+#endif
+
diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c
index f902a7c37c31..83e5e8e1276f 100644
--- a/arch/arm/mach-mx3/mx31ads.c
+++ b/arch/arm/mach-mx3/mx31ads.c
@@ -22,6 +22,8 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 #include <linux/serial_8250.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
 #include <linux/irq.h>
 
 #include <mach/hardware.h>
@@ -35,6 +37,12 @@
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 
+#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
+#include <linux/mfd/wm8350/audio.h>
+#include <linux/mfd/wm8350/core.h>
+#include <linux/mfd/wm8350/pmic.h>
+#endif
+
 #include "devices.h"
 
 /*!
@@ -94,13 +102,16 @@ static struct imxuart_platform_data uart_pdata = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
+static int uart_pins[] = {
+        MX31_PIN_CTS1__CTS1,
+        MX31_PIN_RTS1__RTS1,
+        MX31_PIN_TXD1__TXD1,
+        MX31_PIN_RXD1__RXD1
+};
+
 static inline void mxc_init_imx_uart(void)
 {
-        mxc_iomux_mode(MX31_PIN_CTS1__CTS1);
-        mxc_iomux_mode(MX31_PIN_RTS1__RTS1);
-        mxc_iomux_mode(MX31_PIN_TXD1__TXD1);
-        mxc_iomux_mode(MX31_PIN_RXD1__RXD1);
-
+        mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
         mxc_register_device(&mxc_uart_device0, &uart_pdata);
 }
 #else /* !SERIAL_IMX */
@@ -176,7 +187,7 @@ static void __init mx31ads_init_expio(void)
         /*
          * Configure INT line as GPIO input
          */
-        mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO));
+        mxc_iomux_setup_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
 
         /* disable the interrupt and clear the status */
         __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
@@ -191,26 +202,301 @@ static void __init mx31ads_init_expio(void)
         set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
 }
 
+#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
+/* This section defines setup for the Wolfson Microelectronics
+ * 1133-EV1 PMU/audio board.  When other PMU boards are supported the
+ * regulator definitions may be shared with them, but for now they can
+ * only be used with this board so would generate warnings about
+ * unused statics and some of the configuration is specific to this
+ * module.
+ */
+
+/* CPU */
+static struct regulator_consumer_supply sw1a_consumers[] = {
+        {
+                .supply = "cpu_vcc",
+        }
+};
+
+static struct regulator_init_data sw1a_data = {
+        .constraints = {
+                .name = "SW1A",
+                .min_uV = 1275000,
+                .max_uV = 1600000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                  REGULATOR_CHANGE_MODE,
+                .valid_modes_mask = REGULATOR_MODE_NORMAL |
+                                    REGULATOR_MODE_FAST,
+                .state_mem = {
+                         .uV = 1400000,
+                         .mode = REGULATOR_MODE_NORMAL,
+                         .enabled = 1,
+                 },
+                .initial_state = PM_SUSPEND_MEM,
+                .always_on = 1,
+                .boot_on = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
+        .consumer_supplies = sw1a_consumers,
+};
+
+/* System IO - High */
+static struct regulator_init_data viohi_data = {
+        .constraints = {
+                .name = "VIOHO",
+                .min_uV = 2800000,
+                .max_uV = 2800000,
+                .state_mem = {
+                         .uV = 2800000,
+                         .mode = REGULATOR_MODE_NORMAL,
+                         .enabled = 1,
+                 },
+                .initial_state = PM_SUSPEND_MEM,
+                .always_on = 1,
+                .boot_on = 1,
+        },
+};
+
+/* System IO - Low */
+static struct regulator_init_data violo_data = {
+        .constraints = {
+                .name = "VIOLO",
+                .min_uV = 1800000,
+                .max_uV = 1800000,
+                .state_mem = {
+                         .uV = 1800000,
+                         .mode = REGULATOR_MODE_NORMAL,
+                         .enabled = 1,
+                 },
+                .initial_state = PM_SUSPEND_MEM,
+                .always_on = 1,
+                .boot_on = 1,
+        },
+};
+
+/* DDR RAM */
+static struct regulator_init_data sw2a_data = {
+        .constraints = {
+                .name = "SW2A",
+                .min_uV = 1800000,
+                .max_uV = 1800000,
+                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                .state_mem = {
+                         .uV = 1800000,
+                         .mode = REGULATOR_MODE_NORMAL,
+                         .enabled = 1,
+                 },
+                .state_disk = {
+                         .mode = REGULATOR_MODE_NORMAL,
+                         .enabled = 0,
+                 },
+                .always_on = 1,
+                .boot_on = 1,
+                .initial_state = PM_SUSPEND_MEM,
+        },
+};
+
+static struct regulator_init_data ldo1_data = {
+        .constraints = {
+                .name = "VCAM/VMMC1/VMMC2",
+                .min_uV = 2800000,
+                .max_uV = 2800000,
+                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                .apply_uV = 1,
+        },
+};
+
+static struct regulator_consumer_supply ldo2_consumers[] = {
+        {
+                .supply = "AVDD",
+        },
+        {
+                .supply = "HPVDD",
+        },
+};
+
+/* CODEC and SIM */
+static struct regulator_init_data ldo2_data = {
+        .constraints = {
+                .name = "VESIM/VSIM/AVDD",
+                .min_uV = 3300000,
+                .max_uV = 3300000,
+                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                .apply_uV = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
+        .consumer_supplies = ldo2_consumers,
+};
+
+/* General */
+static struct regulator_init_data vdig_data = {
+        .constraints = {
+                .name = "VDIG",
+                .min_uV = 1500000,
+                .max_uV = 1500000,
+                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                .apply_uV = 1,
+                .always_on = 1,
+                .boot_on = 1,
+        },
+};
+
+/* Tranceivers */
+static struct regulator_init_data ldo4_data = {
+        .constraints = {
+                .name = "VRF1/CVDD_2.775",
+                .min_uV = 2500000,
+                .max_uV = 2500000,
+                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                .apply_uV = 1,
+                .always_on = 1,
+                .boot_on = 1,
+        },
+};
+
+static struct wm8350_led_platform_data wm8350_led_data = {
+        .name            = "wm8350:white",
+        .default_trigger = "heartbeat",
+        .max_uA          = 27899,
+};
+
+static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
+        .vmid_discharge_msecs = 1000,
+        .drain_msecs = 30,
+        .cap_discharge_msecs = 700,
+        .vmid_charge_msecs = 700,
+        .vmid_s_curve = WM8350_S_CURVE_SLOW,
+        .dis_out4 = WM8350_DISCHARGE_SLOW,
+        .dis_out3 = WM8350_DISCHARGE_SLOW,
+        .dis_out2 = WM8350_DISCHARGE_SLOW,
+        .dis_out1 = WM8350_DISCHARGE_SLOW,
+        .vroi_out4 = WM8350_TIE_OFF_500R,
+        .vroi_out3 = WM8350_TIE_OFF_500R,
+        .vroi_out2 = WM8350_TIE_OFF_500R,
+        .vroi_out1 = WM8350_TIE_OFF_500R,
+        .vroi_enable = 0,
+        .codec_current_on = WM8350_CODEC_ISEL_1_0,
+        .codec_current_standby = WM8350_CODEC_ISEL_0_5,
+        .codec_current_charge = WM8350_CODEC_ISEL_1_5,
+};
+
+static int mx31_wm8350_init(struct wm8350 *wm8350)
+{
+        int i;
+
+        wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
+                           WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
+                           WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
+                           WM8350_GPIO_DEBOUNCE_ON);
+
+        wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
+                           WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
+                           WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
+                           WM8350_GPIO_DEBOUNCE_ON);
+
+        wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
+                           WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
+                           WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
+                           WM8350_GPIO_DEBOUNCE_OFF);
+
+        wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
+                           WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
+                           WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
+                           WM8350_GPIO_DEBOUNCE_OFF);
+
+        wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
+                           WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
+                           WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
+                           WM8350_GPIO_DEBOUNCE_OFF);
+
+        wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
+                           WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
+                           WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
+                           WM8350_GPIO_DEBOUNCE_OFF);
+
+        wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
+                           WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
+                           WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
+                           WM8350_GPIO_DEBOUNCE_OFF);
+
+        /* Fix up for our own supplies. */
+        for (i = 0; i < ARRAY_SIZE(ldo2_consumers); i++)
+                ldo2_consumers[i].dev = wm8350->dev;
+
+        wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
+        wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
+        wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
+        wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
+        wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
+        wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
+        wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
+        wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
+
+        /* LEDs */
+        wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
+                             WM8350_DC5_ERRACT_SHUTDOWN_CONV);
+        wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
+                               WM8350_ISINK_FLASH_DISABLE,
+                               WM8350_ISINK_FLASH_TRIG_BIT,
+                               WM8350_ISINK_FLASH_DUR_32MS,
+                               WM8350_ISINK_FLASH_ON_INSTANT,
+                               WM8350_ISINK_FLASH_OFF_INSTANT,
+                               WM8350_ISINK_FLASH_MODE_EN);
+        wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
+                               WM8350_ISINK_MODE_BOOST,
+                               WM8350_ISINK_ILIM_NORMAL,
+                               WM8350_DC5_RMP_20V,
+                               WM8350_DC5_FBSRC_ISINKA);
+        wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
+                            &wm8350_led_data);
+
+        wm8350->codec.platform_data = &imx32ads_wm8350_setup;
+
+        return 0;
+}
+
+static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
+        .init = mx31_wm8350_init,
+};
+#endif
+
+#if defined(CONFIG_I2C_IMX) || defined(CONFIG_I2C_IMX_MODULE)
+static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
+#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
+        {
+                I2C_BOARD_INFO("wm8350", 0x1a),
+                .platform_data = &mx31_wm8350_pdata,
+                .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+        },
+#endif
+};
+
+static void mxc_init_i2c(void)
+{
+        i2c_register_board_info(1, mx31ads_i2c1_devices,
+                                ARRAY_SIZE(mx31ads_i2c1_devices));
+
+        mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
+        mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
+
+        mxc_register_device(&mxc_i2c_device1, NULL);
+}
+#else
+static void mxc_init_i2c(void)
+{
+}
+#endif
+
 /*!
  * This structure defines static mappings for the i.MX31ADS board.
  */
 static struct map_desc mx31ads_io_desc[] __initdata = {
         {
-                .virtual        = AIPS1_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(AIPS1_BASE_ADDR),
-                .length         = AIPS1_SIZE,
-                .type           = MT_DEVICE_NONSHARED
-        }, {
                 .virtual        = SPBA0_BASE_ADDR_VIRT,
                 .pfn            = __phys_to_pfn(SPBA0_BASE_ADDR),
                 .length         = SPBA0_SIZE,
                 .type           = MT_DEVICE_NONSHARED
         }, {
-                .virtual        = AIPS2_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(AIPS2_BASE_ADDR),
-                .length         = AIPS2_SIZE,
-                .type           = MT_DEVICE_NONSHARED
-        }, {
                 .virtual        = CS4_BASE_ADDR_VIRT,
                 .pfn            = __phys_to_pfn(CS4_BASE_ADDR),
                 .length         = CS4_SIZE / 2,
@@ -221,13 +507,13 @@ static struct map_desc mx31ads_io_desc[] __initdata = {
 /*!
  * Set up static virtual mappings.
  */
-void __init mx31ads_map_io(void)
+static void __init mx31ads_map_io(void)
 {
         mxc_map_io();
         iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
 }
 
-void __init mx31ads_init_irq(void)
+static void __init mx31ads_init_irq(void)
 {
         mxc_init_irq();
         mx31ads_init_expio();
@@ -240,15 +526,15 @@ static void __init mxc_board_init(void)
 {
         mxc_init_extuart();
         mxc_init_imx_uart();
+        mxc_init_i2c();
 }
 
 static void __init mx31ads_timer_init(void)
 {
-        mxc_clocks_init(26000000);
-        mxc_timer_init("ipg_clk.0");
+        mx31_clocks_init(26000000);
 }
 
-struct sys_timer mx31ads_timer = {
+static struct sys_timer mx31ads_timer = {
         .init   = mx31ads_timer_init,
 };
 
diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c
index c43440070143..894d98cd9941 100644
--- a/arch/arm/mach-mx3/mx31lite.c
+++ b/arch/arm/mach-mx3/mx31lite.c
@@ -42,21 +42,11 @@
  */
 static struct map_desc mx31lite_io_desc[] __initdata = {
         {
-                .virtual = AIPS1_BASE_ADDR_VIRT,
-                .pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
-                .length = AIPS1_SIZE,
-                .type = MT_DEVICE_NONSHARED
-        }, {
                 .virtual = SPBA0_BASE_ADDR_VIRT,
                 .pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
                 .length = SPBA0_SIZE,
                 .type = MT_DEVICE_NONSHARED
         }, {
-                .virtual = AIPS2_BASE_ADDR_VIRT,
-                .pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
-                .length = AIPS2_SIZE,
-                .type = MT_DEVICE_NONSHARED
-        }, {
                 .virtual = CS4_BASE_ADDR_VIRT,
                 .pfn = __phys_to_pfn(CS4_BASE_ADDR),
                 .length = CS4_SIZE,
@@ -82,8 +72,7 @@ static void __init mxc_board_init(void)
 
 static void __init mx31lite_timer_init(void)
 {
-        mxc_clocks_init(26000000);
-        mxc_timer_init("ipg_clk.0");
+        mx31_clocks_init(26000000);
 }
 
 struct sys_timer mx31lite_timer = {
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
new file mode 100644
index 000000000000..d080b4add79c
--- /dev/null
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <linux/platform_device.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx3.h>
+
+#include "devices.h"
+
+static struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static int mxc_uart1_pins[] = {
+        MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2,
+        MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2,
+};
+
+/*
+ * system init for baseboard usage. Will be called by mx31moboard init.
+ */
+void __init mx31moboard_devboard_init(void)
+{
+        printk(KERN_INFO "Initializing mx31devboard peripherals\n");
+        mxc_iomux_setup_multiple_pins(mxc_uart1_pins, ARRAY_SIZE(mxc_uart1_pins), "uart1");
+        mxc_register_device(&mxc_uart_device1, &uart_pdata);
+}
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
new file mode 100644
index 000000000000..9ef9566823fb
--- /dev/null
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <linux/platform_device.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx3.h>
+
+#include "devices.h"
+
+/*
+ * system init for baseboard usage. Will be called by mx31moboard init.
+ */
+void __init mx31moboard_marxbot_init(void)
+{
+        printk(KERN_INFO "Initializing mx31marxbot peripherals\n");
+}
diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c
index c29098af7394..34c2a1b99d4f 100644
--- a/arch/arm/mach-mx3/mx31moboard.c
+++ b/arch/arm/mach-mx3/mx31moboard.c
@@ -32,6 +32,7 @@
 #include <mach/common.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
+#include <mach/board-mx31moboard.h>
 
 #include "devices.h"
 
@@ -63,6 +64,18 @@ static struct platform_device *devices[] __initdata = {
         &mx31moboard_flash,
 };
 
+static int mxc_uart0_pins[] = {
+        MX31_PIN_CTS1__CTS1, MX31_PIN_RTS1__RTS1,
+        MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1,
+};
+static int mxc_uart4_pins[] = {
+        MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5,
+        MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5,
+};
+
+static int mx31moboard_baseboard;
+core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444);
+
 /*
  * Board specific initialization.
  */
@@ -70,58 +83,29 @@ static void __init mxc_board_init(void)
 {
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
-        mxc_iomux_mode(MX31_PIN_CTS1__CTS1);
-        mxc_iomux_mode(MX31_PIN_RTS1__RTS1);
-        mxc_iomux_mode(MX31_PIN_TXD1__TXD1);
-        mxc_iomux_mode(MX31_PIN_RXD1__RXD1);
-
+        mxc_iomux_setup_multiple_pins(mxc_uart0_pins, ARRAY_SIZE(mxc_uart0_pins), "uart0");
         mxc_register_device(&mxc_uart_device0, &uart_pdata);
 
-        mxc_iomux_mode(MX31_PIN_CTS2__CTS2);
-        mxc_iomux_mode(MX31_PIN_RTS2__RTS2);
-        mxc_iomux_mode(MX31_PIN_TXD2__TXD2);
-        mxc_iomux_mode(MX31_PIN_RXD2__RXD2);
-
-        mxc_register_device(&mxc_uart_device1, &uart_pdata);
-
-        mxc_iomux_mode(MX31_PIN_PC_RST__CTS5);
-        mxc_iomux_mode(MX31_PIN_PC_VS2__RTS5);
-        mxc_iomux_mode(MX31_PIN_PC_BVD2__TXD5);
-        mxc_iomux_mode(MX31_PIN_PC_BVD1__RXD5);
-
+        mxc_iomux_setup_multiple_pins(mxc_uart4_pins, ARRAY_SIZE(mxc_uart4_pins), "uart4");
         mxc_register_device(&mxc_uart_device4, &uart_pdata);
-}
 
-/*
- * This structure defines static mappings for the mx31moboard.
- */
-static struct map_desc mx31moboard_io_desc[] __initdata = {
-        {
-                .virtual        = AIPS1_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(AIPS1_BASE_ADDR),
-                .length         = AIPS1_SIZE,
-                .type           = MT_DEVICE_NONSHARED
-        }, {
-                .virtual        = AIPS2_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(AIPS2_BASE_ADDR),
-                .length         = AIPS2_SIZE,
-                .type           = MT_DEVICE_NONSHARED
-        },
-};
-
-/*
- * Set up static virtual mappings.
- */
-void __init mx31moboard_map_io(void)
-{
-        mxc_map_io();
-        iotable_init(mx31moboard_io_desc, ARRAY_SIZE(mx31moboard_io_desc));
+        switch (mx31moboard_baseboard) {
+        case MX31NOBOARD:
+                break;
+        case MX31DEVBOARD:
+                mx31moboard_devboard_init();
+                break;
+        case MX31MARXBOT:
+                mx31moboard_marxbot_init();
+                break;
+        default:
+                printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n", mx31moboard_baseboard);
+        }
 }
 
 static void __init mx31moboard_timer_init(void)
 {
-        mxc_clocks_init(26000000);
-        mxc_timer_init("ipg_clk.0");
+        mx31_clocks_init(26000000);
 }
 
 struct sys_timer mx31moboard_timer = {
@@ -133,7 +117,7 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
         .phys_io        = AIPS1_BASE_ADDR,
         .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
-        .map_io         = mx31moboard_map_io,
+        .map_io         = mxc_map_io,
         .init_irq       = mxc_init_irq,
         .init_machine   = mxc_board_init,
         .timer          = &mx31moboard_timer,
diff --git a/arch/arm/mach-mx3/mx31pdk.c b/arch/arm/mach-mx3/mx31pdk.c
index d464d068a4a6..bc63f1785691 100644
--- a/arch/arm/mach-mx3/mx31pdk.c
+++ b/arch/arm/mach-mx3/mx31pdk.c
@@ -45,40 +45,17 @@ static struct imxuart_platform_data uart_pdata = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static inline void mxc_init_imx_uart(void)
-{
-        mxc_iomux_mode(MX31_PIN_CTS1__CTS1);
-        mxc_iomux_mode(MX31_PIN_RTS1__RTS1);
-        mxc_iomux_mode(MX31_PIN_TXD1__TXD1);
-        mxc_iomux_mode(MX31_PIN_RXD1__RXD1);
-
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
-}
-
-/*!
- * This structure defines static mappings for the i.MX31PDK board.
- */
-static struct map_desc mx31pdk_io_desc[] __initdata = {
-        {
-                .virtual        = AIPS1_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(AIPS1_BASE_ADDR),
-                .length         = AIPS1_SIZE,
-                .type           = MT_DEVICE_NONSHARED
-        }, {
-                .virtual        = AIPS2_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(AIPS2_BASE_ADDR),
-                .length         = AIPS2_SIZE,
-                .type           = MT_DEVICE_NONSHARED
-        },
+static int uart_pins[] = {
+        MX31_PIN_CTS1__CTS1,
+        MX31_PIN_RTS1__RTS1,
+        MX31_PIN_TXD1__TXD1,
+        MX31_PIN_RXD1__RXD1
 };
 
-/*!
- * Set up static virtual mappings.
- */
-static void __init mx31pdk_map_io(void)
+static inline void mxc_init_imx_uart(void)
 {
-        mxc_map_io();
-        iotable_init(mx31pdk_io_desc, ARRAY_SIZE(mx31pdk_io_desc));
+        mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
 }
 
 /*!
@@ -91,8 +68,7 @@ static void __init mxc_board_init(void)
 
 static void __init mx31pdk_timer_init(void)
 {
-        mxc_clocks_init(26000000);
-        mxc_timer_init("ipg_clk.0");
+        mx31_clocks_init(26000000);
 }
 
 static struct sys_timer mx31pdk_timer = {
@@ -108,7 +84,7 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
         .phys_io        = AIPS1_BASE_ADDR,
         .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
-        .map_io         = mx31pdk_map_io,
+        .map_io         = mxc_map_io,
         .init_irq       = mxc_init_irq,
         .init_machine   = mxc_board_init,
         .timer          = &mx31pdk_timer,
diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c
index 8cea82587222..5fce022114de 100644
--- a/arch/arm/mach-mx3/pcm037.c
+++ b/arch/arm/mach-mx3/pcm037.c
@@ -26,6 +26,8 @@
 #include <linux/gpio.h>
 #include <linux/smc911x.h>
 #include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -37,6 +39,10 @@
 #include <mach/iomux-mx3.h>
 #include <mach/board-pcm037.h>
 #include <mach/mxc_nand.h>
+#include <mach/mmc.h>
+#ifdef CONFIG_I2C_IMX
+#include <mach/i2c.h>
+#endif
 
 #include "devices.h"
 
@@ -117,12 +123,90 @@ static struct mxc_nand_platform_data pcm037_nand_board_info = {
         .hw_ecc = 1,
 };
 
+#ifdef CONFIG_I2C_IMX
+static int i2c_1_pins[] = {
+        MX31_PIN_CSPI2_MOSI__SCL,
+        MX31_PIN_CSPI2_MISO__SDA,
+};
+
+static int pcm037_i2c_1_init(struct device *dev)
+{
+        return mxc_iomux_setup_multiple_pins(i2c_1_pins, ARRAY_SIZE(i2c_1_pins),
+                        "i2c-1");
+}
+
+static void pcm037_i2c_1_exit(struct device *dev)
+{
+        mxc_iomux_release_multiple_pins(i2c_1_pins, ARRAY_SIZE(i2c_1_pins));
+}
+
+static struct imxi2c_platform_data pcm037_i2c_1_data = {
+        .bitrate = 100000,
+        .init = pcm037_i2c_1_init,
+        .exit = pcm037_i2c_1_exit,
+};
+
+static struct at24_platform_data board_eeprom = {
+        .byte_len = 4096,
+        .page_size = 32,
+        .flags = AT24_FLAG_ADDR16,
+};
+
+static struct i2c_board_info pcm037_i2c_devices[] = {
+       {
+                I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
+                .platform_data = &board_eeprom,
+        }, {
+                I2C_BOARD_INFO("rtc-pcf8563", 0x51),
+                .type = "pcf8563",
+        }
+};
+#endif
+
+static int sdhc1_pins[] = {
+        MX31_PIN_SD1_DATA3__SD1_DATA3,
+        MX31_PIN_SD1_DATA2__SD1_DATA2,
+        MX31_PIN_SD1_DATA1__SD1_DATA1,
+        MX31_PIN_SD1_DATA0__SD1_DATA0,
+        MX31_PIN_SD1_CLK__SD1_CLK,
+        MX31_PIN_SD1_CMD__SD1_CMD,
+};
+
+static int pcm970_sdhc1_init(struct device *dev, irq_handler_t h, void *data)
+{
+        return mxc_iomux_setup_multiple_pins(sdhc1_pins, ARRAY_SIZE(sdhc1_pins),
+                                "sdhc-1");
+}
+
+static void pcm970_sdhc1_exit(struct device *dev, void *data)
+{
+        mxc_iomux_release_multiple_pins(sdhc1_pins, ARRAY_SIZE(sdhc1_pins));
+}
+
+/* No card and rw detection at the moment */
+static struct imxmmc_platform_data sdhc_pdata = {
+        .init = pcm970_sdhc1_init,
+        .exit = pcm970_sdhc1_exit,
+};
+
 static struct platform_device *devices[] __initdata = {
         &pcm037_flash,
         &pcm037_eth,
         &pcm037_sram_device,
 };
 
+static int uart0_pins[] = {
+        MX31_PIN_CTS1__CTS1,
+        MX31_PIN_RTS1__RTS1,
+        MX31_PIN_TXD1__TXD1,
+        MX31_PIN_RXD1__RXD1
+};
+
+static int uart2_pins[] = {
+        MX31_PIN_CSPI3_MOSI__RXD3,
+        MX31_PIN_CSPI3_MISO__TXD3
+};
+
 /*
  * Board specific initialization.
  */
@@ -130,59 +214,33 @@ static void __init mxc_board_init(void)
 {
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
-        mxc_iomux_mode(MX31_PIN_CTS1__CTS1);
-        mxc_iomux_mode(MX31_PIN_RTS1__RTS1);
-        mxc_iomux_mode(MX31_PIN_TXD1__TXD1);
-        mxc_iomux_mode(MX31_PIN_RXD1__RXD1);
-
+        mxc_iomux_setup_multiple_pins(uart0_pins, ARRAY_SIZE(uart0_pins), "uart-0");
         mxc_register_device(&mxc_uart_device0, &uart_pdata);
 
-        mxc_iomux_mode(MX31_PIN_CSPI3_MOSI__RXD3);
-        mxc_iomux_mode(MX31_PIN_CSPI3_MISO__TXD3);
-
+        mxc_iomux_setup_multiple_pins(uart2_pins, ARRAY_SIZE(uart2_pins), "uart-2");
         mxc_register_device(&mxc_uart_device2, &uart_pdata);
 
-        mxc_iomux_mode(MX31_PIN_BATT_LINE__OWIRE);
+        mxc_iomux_setup_pin(MX31_PIN_BATT_LINE__OWIRE, "batt-0wire");
         mxc_register_device(&mxc_w1_master_device, NULL);
 
         /* SMSC9215 IRQ pin */
-        mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO));
-        if (!gpio_request(MX31_PIN_GPIO3_1, "pcm037-eth"))
+        if (!mxc_iomux_setup_pin(IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
+                                "pcm037-eth"))
                 gpio_direction_input(MX31_PIN_GPIO3_1);
 
-        mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
-}
+#ifdef CONFIG_I2C_IMX
+        i2c_register_board_info(1, pcm037_i2c_devices,
+                        ARRAY_SIZE(pcm037_i2c_devices));
 
-/*
- * This structure defines static mappings for the pcm037 board.
- */
-static struct map_desc pcm037_io_desc[] __initdata = {
-        {
-                .virtual        = AIPS1_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(AIPS1_BASE_ADDR),
-                .length         = AIPS1_SIZE,
-                .type           = MT_DEVICE_NONSHARED
-        }, {
-                .virtual        = AIPS2_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(AIPS2_BASE_ADDR),
-                .length         = AIPS2_SIZE,
-                .type           = MT_DEVICE_NONSHARED
-        },
-};
-
-/*
- * Set up static virtual mappings.
- */
-void __init pcm037_map_io(void)
-{
-        mxc_map_io();
-        iotable_init(pcm037_io_desc, ARRAY_SIZE(pcm037_io_desc));
+        mxc_register_device(&mxc_i2c_device1, &pcm037_i2c_1_data);
+#endif
+        mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
+        mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
 }
 
 static void __init pcm037_timer_init(void)
 {
-        mxc_clocks_init(26000000);
-        mxc_timer_init("ipg_clk.0");
+        mx31_clocks_init(26000000);
 }
 
 struct sys_timer pcm037_timer = {
@@ -194,7 +252,7 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037")
         .phys_io        = AIPS1_BASE_ADDR,
         .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
-        .map_io         = pcm037_map_io,
+        .map_io         = mxc_map_io,
         .init_irq       = mxc_init_irq,
         .init_machine   = mxc_board_init,
         .timer          = &pcm037_timer,
diff --git a/arch/arm/mach-mx3/qong.c b/arch/arm/mach-mx3/qong.c
new file mode 100644
index 000000000000..6c4283cec6f4
--- /dev/null
+++ b/arch/arm/mach-mx3/qong.c
@@ -0,0 +1,312 @@
+/*
+ *  Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/memory.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/nand.h>
+#include <linux/gpio.h>
+
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <mach/common.h>
+#include <asm/page.h>
+#include <asm/setup.h>
+#include <mach/board-qong.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx3.h>
+#include "devices.h"
+
+/* FPGA defines */
+#define QONG_FPGA_VERSION(major, minor, rev)    \
+        (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF))
+
+#define QONG_FPGA_BASEADDR              CS1_BASE_ADDR
+#define QONG_FPGA_PERIPH_SIZE           (1 << 24)
+
+#define QONG_FPGA_CTRL_BASEADDR         QONG_FPGA_BASEADDR
+#define QONG_FPGA_CTRL_SIZE             0x10
+/* FPGA control registers */
+#define QONG_FPGA_CTRL_VERSION          0x00
+
+#define QONG_DNET_ID            1
+#define QONG_DNET_BASEADDR      \
+        (QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
+#define QONG_DNET_SIZE          0x00001000
+
+#define QONG_FPGA_IRQ           IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
+
+/*
+ * This file contains the board-specific initialization routines.
+ */
+
+static struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static int uart_pins[] = {
+        MX31_PIN_CTS1__CTS1,
+        MX31_PIN_RTS1__RTS1,
+        MX31_PIN_TXD1__TXD1,
+        MX31_PIN_RXD1__RXD1
+};
+
+static inline void mxc_init_imx_uart(void)
+{
+        mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins),
+                        "uart-0");
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+}
+
+static struct resource dnet_resources[] = {
+        [0] = {
+                .name   = "dnet-memory",
+                .start  = QONG_DNET_BASEADDR,
+                .end    = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = QONG_FPGA_IRQ,
+                .end    = QONG_FPGA_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device dnet_device = {
+        .name                   = "dnet",
+        .id                     = -1,
+        .num_resources          = ARRAY_SIZE(dnet_resources),
+        .resource               = dnet_resources,
+};
+
+static int __init qong_init_dnet(void)
+{
+        int ret;
+
+        ret = platform_device_register(&dnet_device);
+        return ret;
+}
+
+/* MTD NOR flash */
+
+static struct physmap_flash_data qong_flash_data = {
+        .width = 2,
+};
+
+static struct resource qong_flash_resource = {
+        .start = CS0_BASE_ADDR,
+        .end = CS0_BASE_ADDR + QONG_NOR_SIZE - 1,
+        .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device qong_nor_mtd_device = {
+        .name = "physmap-flash",
+        .id = 0,
+        .dev = {
+                .platform_data = &qong_flash_data,
+                },
+        .resource = &qong_flash_resource,
+        .num_resources = 1,
+};
+
+static void qong_init_nor_mtd(void)
+{
+        (void)platform_device_register(&qong_nor_mtd_device);
+}
+
+/*
+ * Hardware specific access to control-lines
+ */
+static void qong_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+        struct nand_chip *nand_chip = mtd->priv;
+
+        if (cmd == NAND_CMD_NONE)
+                return;
+
+        if (ctrl & NAND_CLE)
+                writeb(cmd, nand_chip->IO_ADDR_W + (1 << 24));
+        else
+                writeb(cmd, nand_chip->IO_ADDR_W + (1 << 23));
+}
+
+/*
+ * Read the Device Ready pin.
+ */
+static int qong_nand_device_ready(struct mtd_info *mtd)
+{
+        return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_NFRB));
+}
+
+static void qong_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+        if (chip >= 0)
+                gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
+        else
+                gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 1);
+}
+
+static struct platform_nand_data qong_nand_data = {
+        .chip = {
+                .chip_delay             = 20,
+                .options                = 0,
+        },
+        .ctrl = {
+                .cmd_ctrl               = qong_nand_cmd_ctrl,
+                .dev_ready              = qong_nand_device_ready,
+                .select_chip            = qong_nand_select_chip,
+        }
+};
+
+static struct resource qong_nand_resource = {
+        .start          = CS3_BASE_ADDR,
+        .end            = CS3_BASE_ADDR + SZ_32M - 1,
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device qong_nand_device = {
+        .name           = "gen_nand",
+        .id             = -1,
+        .dev            = {
+                .platform_data = &qong_nand_data,
+        },
+        .num_resources  = 1,
+        .resource       = &qong_nand_resource,
+};
+
+static void __init qong_init_nand_mtd(void)
+{
+        /* init CS */
+        __raw_writel(0x00004f00, CSCR_U(3));
+        __raw_writel(0x20013b31, CSCR_L(3));
+        __raw_writel(0x00020800, CSCR_A(3));
+        mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);
+
+        /* enable pin */
+        mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFCE_B, IOMUX_CONFIG_GPIO));
+        if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), "nand_enable"))
+                gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
+
+        /* ready/busy pin */
+        mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFRB, IOMUX_CONFIG_GPIO));
+        if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFRB), "nand_rdy"))
+                gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFRB));
+
+        /* write protect pin */
+        mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFWP_B, IOMUX_CONFIG_GPIO));
+        if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFWP_B), "nand_wp"))
+                gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFWP_B));
+
+        platform_device_register(&qong_nand_device);
+}
+
+static void __init qong_init_fpga(void)
+{
+        void __iomem *regs;
+        u32 fpga_ver;
+
+        regs = ioremap(QONG_FPGA_CTRL_BASEADDR, QONG_FPGA_CTRL_SIZE);
+        if (!regs) {
+                printk(KERN_ERR "%s: failed to map registers, aborting.\n",
+                                __func__);
+                return;
+        }
+
+        fpga_ver = readl(regs + QONG_FPGA_CTRL_VERSION);
+        iounmap(regs);
+        printk(KERN_INFO "Qong FPGA version %d.%d.%d\n",
+                        (fpga_ver & 0xF000) >> 12,
+                        (fpga_ver & 0x0F00) >> 8, fpga_ver & 0x00FF);
+        if (fpga_ver < QONG_FPGA_VERSION(0, 8, 7)) {
+                printk(KERN_ERR "qong: Unexpected FPGA version, FPGA-based "
+                                "devices won't be registered!\n");
+                return;
+        }
+
+        /* register FPGA-based devices */
+        qong_init_nand_mtd();
+        qong_init_dnet();
+}
+
+/*
+ * This structure defines the MX31 memory map.
+ */
+static struct map_desc qong_io_desc[] __initdata = {
+        {
+                .virtual = AIPS1_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
+                .length = AIPS1_SIZE,
+                .type = MT_DEVICE_NONSHARED
+        }, {
+                .virtual = AIPS2_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
+                .length = AIPS2_SIZE,
+                .type = MT_DEVICE_NONSHARED
+        }
+};
+
+/*
+ * Set up static virtual mappings.
+ */
+static void __init qong_map_io(void)
+{
+        mxc_map_io();
+        iotable_init(qong_io_desc, ARRAY_SIZE(qong_io_desc));
+}
+
+/*
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+        mxc_init_imx_uart();
+        qong_init_nor_mtd();
+        qong_init_fpga();
+}
+
+static void __init qong_timer_init(void)
+{
+        mx31_clocks_init(26000000);
+}
+
+static struct sys_timer qong_timer = {
+        .init   = qong_timer_init,
+};
+
+/*
+ * The following uses standard kernel macros defined in arch.h in order to
+ * initialize __mach_desc_QONG data structure.
+ */
+
+MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
+        /* Maintainer: DENX Software Engineering GmbH */
+        .phys_io        = AIPS1_BASE_ADDR,
+        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = qong_map_io,
+        .init_irq       = mxc_init_irq,
+        .init_machine   = mxc_board_init,
+        .timer          = &qong_timer,
+MACHINE_END
diff --git a/arch/arm/mach-netx/include/mach/system.h b/arch/arm/mach-netx/include/mach/system.h
index 6c1023b8a9ab..dc7b4bc003c5 100644
--- a/arch/arm/mach-netx/include/mach/system.h
+++ b/arch/arm/mach-netx/include/mach/system.h
@@ -28,7 +28,7 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES,
                NETX_SYSTEM_RES_CR);
diff --git a/arch/arm/mach-ns9xxx/include/mach/system.h b/arch/arm/mach-ns9xxx/include/mach/system.h
index e2068c57415f..1561588ca364 100644
--- a/arch/arm/mach-ns9xxx/include/mach/system.h
+++ b/arch/arm/mach-ns9xxx/include/mach/system.h
@@ -20,7 +20,7 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
 #ifdef CONFIG_PROCESSOR_NS9360
         if (processor_is_ns9360())
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 10a301e32434..3f325d3718a9 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -7,6 +7,11 @@ config ARCH_OMAP730
         select CPU_ARM926T
         select ARCH_OMAP_OTG
 
+config ARCH_OMAP850
+        depends on ARCH_OMAP1
+        bool "OMAP850 Based System"
+        select CPU_ARM926T
+
 config ARCH_OMAP15XX
         depends on ARCH_OMAP1
         default y
@@ -46,6 +51,12 @@ config MACH_OMAP_H3
           TI OMAP 1710 H3 board support. Say Y here if you have such
           a board.
 
+config MACH_OMAP_HTCWIZARD
+        bool "HTC Wizard"
+        depends on ARCH_OMAP850
+        help
+          HTC Wizard smartphone support (AKA QTEK 9100, ...)
+
 config MACH_OMAP_OSK
         bool "TI OSK Support"
         depends on ARCH_OMAP1 && ARCH_OMAP16XX
@@ -163,7 +174,7 @@ config OMAP_ARM_216MHZ
 
 config OMAP_ARM_195MHZ
         bool "OMAP ARM 195 MHz CPU"
-        depends on ARCH_OMAP1 && ARCH_OMAP730
+        depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850)
         help
           Enable 195MHz clock for OMAP CPU. If unsure, say N.
 
@@ -175,13 +186,13 @@ config OMAP_ARM_192MHZ
 
 config OMAP_ARM_182MHZ
         bool "OMAP ARM 182 MHz CPU"
-        depends on ARCH_OMAP1 && ARCH_OMAP730
+        depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850)
         help
           Enable 182MHz clock for OMAP CPU. If unsure, say N.
 
 config OMAP_ARM_168MHZ
         bool "OMAP ARM 168 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730)
+        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
         help
           Enable 168MHz clock for OMAP CPU. If unsure, say N.
 
@@ -193,20 +204,20 @@ config OMAP_ARM_150MHZ
 
 config OMAP_ARM_120MHZ
         bool "OMAP ARM 120 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730)
+        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
         help
           Enable 120MHz clock for OMAP CPU. If unsure, say N.
 
 config OMAP_ARM_60MHZ
         bool "OMAP ARM 60 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730)
+        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
         default y
         help
           Enable 60MHz clock for OMAP CPU. If unsure, say Y.
 
 config OMAP_ARM_30MHZ
         bool "OMAP ARM 30 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730)
+        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
         help
           Enable 30MHz clock for OMAP CPU. If unsure, say N.
 
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 2e618391cc51..8b40aace9db4 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -175,7 +175,6 @@ static struct omap_usb_config ams_delta_usb_config __initdata = {
 static struct omap_board_config_kernel ams_delta_config[] = {
         { OMAP_TAG_LCD,         &ams_delta_lcd_config },
         { OMAP_TAG_UART,        &ams_delta_uart_config },
-        { OMAP_TAG_USB,         &ams_delta_usb_config },
 };
 
 static struct resource ams_delta_kp_resources[] = {
@@ -232,6 +231,7 @@ static void __init ams_delta_init(void)
         /* Clear latch2 (NAND, LCD, modem enable) */
         ams_delta_latch2_write(~0, 0);
 
+        omap_usb_init(&ams_delta_usb_config);
         platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices));
 }
 
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 30308294e7c1..19e0e9232336 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -34,7 +34,39 @@
 #include <mach/keypad.h>
 #include <mach/common.h>
 #include <mach/board.h>
-#include <mach/board-fsample.h>
+
+/* fsample is pretty close to p2-sample */
+
+#define fsample_cpld_read(reg) __raw_readb(reg)
+#define fsample_cpld_write(val, reg) __raw_writeb(val, reg)
+
+#define FSAMPLE_CPLD_BASE    0xE8100000
+#define FSAMPLE_CPLD_SIZE    SZ_4K
+#define FSAMPLE_CPLD_START   0x05080000
+
+#define FSAMPLE_CPLD_REG_A   (FSAMPLE_CPLD_BASE + 0x00)
+#define FSAMPLE_CPLD_SWITCH  (FSAMPLE_CPLD_BASE + 0x02)
+#define FSAMPLE_CPLD_UART    (FSAMPLE_CPLD_BASE + 0x02)
+#define FSAMPLE_CPLD_REG_B   (FSAMPLE_CPLD_BASE + 0x04)
+#define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06)
+#define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06)
+
+#define FSAMPLE_CPLD_BIT_BT_RESET         0
+#define FSAMPLE_CPLD_BIT_LCD_RESET        1
+#define FSAMPLE_CPLD_BIT_CAM_PWDN         2
+#define FSAMPLE_CPLD_BIT_CHARGER_ENABLE   3
+#define FSAMPLE_CPLD_BIT_SD_MMC_EN        4
+#define FSAMPLE_CPLD_BIT_aGPS_PWREN       5
+#define FSAMPLE_CPLD_BIT_BACKLIGHT        6
+#define FSAMPLE_CPLD_BIT_aGPS_EN_RESET    7
+#define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N    8
+#define FSAMPLE_CPLD_BIT_OTG_RESET        9
+
+#define fsample_cpld_set(bit) \
+    fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR)
+
+#define fsample_cpld_clear(bit) \
+    fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR)
 
 static int fsample_keymap[] = {
         KEY(0,0,KEY_UP),
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index 7d2670205373..e724940e86f2 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -62,7 +62,6 @@ static struct omap_uart_config generic_uart_config __initdata = {
 };
 
 static struct omap_board_config_kernel generic_config[] __initdata = {
-        { OMAP_TAG_USB,         NULL },
         { OMAP_TAG_UART,        &generic_uart_config },
 };
 
@@ -70,12 +69,12 @@ static void __init omap_generic_init(void)
 {
 #ifdef CONFIG_ARCH_OMAP15XX
         if (cpu_is_omap15xx()) {
-                generic_config[0].data = &generic1510_usb_config;
+                omap_usb_init(&generic1510_usb_config);
         }
 #endif
 #if defined(CONFIG_ARCH_OMAP16XX)
         if (!cpu_is_omap1510()) {
-                generic_config[0].data = &generic1610_usb_config;
+                omap_usb_init(&generic1610_usb_config);
         }
 #endif
 
diff --git a/arch/arm/mach-omap1/board-h2-mmc.c b/arch/arm/mach-omap1/board-h2-mmc.c
index 409fa56d0a87..44d4a966bed9 100644
--- a/arch/arm/mach-omap1/board-h2-mmc.c
+++ b/arch/arm/mach-omap1/board-h2-mmc.c
@@ -19,6 +19,8 @@
 #include <mach/mmc.h>
 #include <mach/gpio.h>
 
+#include "board-h2.h"
+
 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
 
 static int mmc_set_power(struct device *dev, int slot, int power_on,
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 0d784a795092..f695aa053ac8 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -46,6 +46,11 @@
 #include <mach/keypad.h>
 #include <mach/common.h>
 
+#include "board-h2.h"
+
+/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
+#define OMAP1610_ETHR_START             0x04000300
+
 static int h2_keymap[] = {
         KEY(0, 0, KEY_LEFT),
         KEY(0, 1, KEY_RIGHT),
@@ -364,7 +369,6 @@ static struct omap_lcd_config h2_lcd_config __initdata = {
 };
 
 static struct omap_board_config_kernel h2_config[] __initdata = {
-        { OMAP_TAG_USB,         &h2_usb_config },
         { OMAP_TAG_UART,        &h2_uart_config },
         { OMAP_TAG_LCD,         &h2_lcd_config },
 };
@@ -413,6 +417,7 @@ static void __init h2_init(void)
         omap_serial_init();
         omap_register_i2c_bus(1, 100, h2_i2c_board_info,
                               ARRAY_SIZE(h2_i2c_board_info));
+        omap_usb_init(&h2_usb_config);
         h2_mmc_init();
 }
 
diff --git a/arch/arm/plat-omap/include/mach/board-h2.h b/arch/arm/mach-omap1/board-h2.h
index 15531c8dc0e6..315e2662547e 100644
--- a/arch/arm/plat-omap/include/mach/board-h2.h
+++ b/arch/arm/mach-omap1/board-h2.h
@@ -1,5 +1,5 @@
 /*
- * arch/arm/plat-omap/include/mach/board-h2.h
+ * arch/arm/mach-omap1/board-h2.h
  *
  * Hardware definitions for TI OMAP1610 H2 board.
  *
@@ -29,9 +29,6 @@
 #ifndef __ASM_ARCH_OMAP_H2_H
 #define __ASM_ARCH_OMAP_H2_H
 
-/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
-#define OMAP1610_ETHR_START             0x04000300
-
 #define H2_TPS_GPIO_BASE                (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */)
 #       define H2_TPS_GPIO_MMC_PWR_EN   (H2_TPS_GPIO_BASE + 3)
 
diff --git a/arch/arm/mach-omap1/board-h3-mmc.c b/arch/arm/mach-omap1/board-h3-mmc.c
index fdfe793d56f2..0d8a3c195e2e 100644
--- a/arch/arm/mach-omap1/board-h3-mmc.c
+++ b/arch/arm/mach-omap1/board-h3-mmc.c
@@ -19,6 +19,8 @@
 #include <mach/mmc.h>
 #include <mach/gpio.h>
 
+#include "board-h3.h"
+
 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
 
 static int mmc_set_power(struct device *dev, int slot, int power_on,
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index bf08b6ad22ee..4695965114c4 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -50,6 +50,11 @@
 #include <mach/dma.h>
 #include <mach/common.h>
 
+#include "board-h3.h"
+
+/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
+#define OMAP1710_ETHR_START             0x04000300
+
 #define H3_TS_GPIO      48
 
 static int h3_keymap[] = {
@@ -418,7 +423,6 @@ static struct omap_lcd_config h3_lcd_config __initdata = {
 };
 
 static struct omap_board_config_kernel h3_config[] __initdata = {
-        { OMAP_TAG_USB,         &h3_usb_config },
         { OMAP_TAG_UART,        &h3_uart_config },
         { OMAP_TAG_LCD,         &h3_lcd_config },
 };
@@ -472,6 +476,7 @@ static void __init h3_init(void)
         omap_serial_init();
         omap_register_i2c_bus(1, 100, h3_i2c_board_info,
                               ARRAY_SIZE(h3_i2c_board_info));
+        omap_usb_init(&h3_usb_config);
         h3_mmc_init();
 }
 
diff --git a/arch/arm/plat-omap/include/mach/board-h3.h b/arch/arm/mach-omap1/board-h3.h
index 1888326da7ea..78de535be3c5 100644
--- a/arch/arm/plat-omap/include/mach/board-h3.h
+++ b/arch/arm/mach-omap1/board-h3.h
@@ -1,5 +1,5 @@
 /*
- * arch/arm/plat-omap/include/mach/board-h3.h
+ * arch/arm/mach-omap1/board-h3.h
  *
  * Copyright (C) 2001 RidgeRun, Inc.
  * Copyright (C) 2004 Texas Instruments, Inc.
@@ -27,9 +27,6 @@
 #ifndef __ASM_ARCH_OMAP_H3_H
 #define __ASM_ARCH_OMAP_H3_H
 
-/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
-#define OMAP1710_ETHR_START             0x04000300
-
 #define H3_TPS_GPIO_BASE                (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */)
 #       define H3_TPS_GPIO_MMC_PWR_EN   (H3_TPS_GPIO_BASE + 4)
 
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 071cd02a734e..2fd98260ea49 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -39,6 +39,9 @@
 #include <mach/common.h>
 #include <mach/mmc.h>
 
+/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
+#define INNOVATOR1610_ETHR_START        0x04000300
+
 static int innovator_keymap[] = {
         KEY(0, 0, KEY_F1),
         KEY(0, 3, KEY_DOWN),
@@ -370,7 +373,6 @@ static struct omap_uart_config innovator_uart_config __initdata = {
 };
 
 static struct omap_board_config_kernel innovator_config[] = {
-        { OMAP_TAG_USB,         NULL },
         { OMAP_TAG_LCD,         NULL },
         { OMAP_TAG_UART,        &innovator_uart_config },
 };
@@ -392,13 +394,13 @@ static void __init innovator_init(void)
 
 #ifdef CONFIG_ARCH_OMAP15XX
         if (cpu_is_omap1510()) {
-                innovator_config[0].data = &innovator1510_usb_config;
+                omap_usb_init(&innovator1510_usb_config);
                 innovator_config[1].data = &innovator1510_lcd_config;
         }
 #endif
 #ifdef CONFIG_ARCH_OMAP16XX
         if (cpu_is_omap1610()) {
-                innovator_config[0].data = &h2_usb_config;
+                omap_usb_init(&h2_usb_config);
                 innovator_config[1].data = &innovator1610_lcd_config;
         }
 #endif
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index af51e0b180f2..7bc7a3cb9c51 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -233,10 +233,6 @@ static inline void nokia770_mmc_init(void)
 }
 #endif
 
-static struct omap_board_config_kernel nokia770_config[] __initdata = {
-        { OMAP_TAG_USB,         NULL },
-};
-
 #if     defined(CONFIG_OMAP_DSP)
 /*
  * audio power control
@@ -371,19 +367,16 @@ static __init int omap_dsp_init(void)
 
 static void __init omap_nokia770_init(void)
 {
-        nokia770_config[0].data = &nokia770_usb_config;
-
         platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices));
         spi_register_board_info(nokia770_spi_board_info,
                                 ARRAY_SIZE(nokia770_spi_board_info));
-        omap_board_config = nokia770_config;
-        omap_board_config_size = ARRAY_SIZE(nokia770_config);
         omap_gpio_init();
         omap_serial_init();
         omap_register_i2c_bus(1, 100, NULL, 0);
         omap_dsp_init();
         ads7846_dev_init();
         mipid_dev_init();
+        omap_usb_init(&nokia770_usb_config);
         nokia770_mmc_init();
 }
 
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 1a16ecb2ccc8..cf3247b15f87 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -52,6 +52,20 @@
 #include <mach/tc.h>
 #include <mach/common.h>
 
+/* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
+#define OMAP_OSK_ETHR_START             0x04800300
+
+/* TPS65010 has four GPIOs.  nPG and LED2 can be treated like GPIOs with
+ * alternate pin configurations for hardware-controlled blinking.
+ */
+#define OSK_TPS_GPIO_BASE               (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */)
+#       define OSK_TPS_GPIO_USB_PWR_EN  (OSK_TPS_GPIO_BASE + 0)
+#       define OSK_TPS_GPIO_LED_D3      (OSK_TPS_GPIO_BASE + 1)
+#       define OSK_TPS_GPIO_LAN_RESET   (OSK_TPS_GPIO_BASE + 2)
+#       define OSK_TPS_GPIO_DSP_PWR_EN  (OSK_TPS_GPIO_BASE + 3)
+#       define OSK_TPS_GPIO_LED_D9      (OSK_TPS_GPIO_BASE + 4)
+#       define OSK_TPS_GPIO_LED_D2      (OSK_TPS_GPIO_BASE + 5)
+
 static struct mtd_partition osk_partitions[] = {
         /* bootloader (U-Boot, etc) in first sector */
         {
@@ -290,7 +304,6 @@ static struct omap_lcd_config osk_lcd_config __initdata = {
 #endif
 
 static struct omap_board_config_kernel osk_config[] __initdata = {
-        { OMAP_TAG_USB,           &osk_usb_config },
         { OMAP_TAG_UART,                &osk_uart_config },
 #ifdef  CONFIG_OMAP_OSK_MISTRAL
         { OMAP_TAG_LCD,                 &osk_lcd_config },
@@ -541,6 +554,8 @@ static void __init osk_init(void)
         l |= (3 << 1);
         omap_writel(l, USB_TRANSCEIVER_CTRL);
 
+        omap_usb_init(&osk_usb_config);
+
         /* irq for tps65010 chip */
         /* bootloader effectively does:  omap_cfg_reg(U19_1610_MPUIO1); */
         if (gpio_request(OMAP_MPUIO(1), "tps65010") == 0)
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 99f2b43f2541..886b4c0569bd 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -43,6 +43,21 @@
 #include <mach/keypad.h>
 #include <mach/common.h>
 
+#define PALMTE_USBDETECT_GPIO   0
+#define PALMTE_USB_OR_DC_GPIO   1
+#define PALMTE_TSC_GPIO         4
+#define PALMTE_PINTDAV_GPIO     6
+#define PALMTE_MMC_WP_GPIO      8
+#define PALMTE_MMC_POWER_GPIO   9
+#define PALMTE_HDQ_GPIO         11
+#define PALMTE_HEADPHONES_GPIO  14
+#define PALMTE_SPEAKER_GPIO     15
+#define PALMTE_DC_GPIO          OMAP_MPUIO(2)
+#define PALMTE_MMC_SWITCH_GPIO  OMAP_MPUIO(4)
+#define PALMTE_MMC1_GPIO        OMAP_MPUIO(6)
+#define PALMTE_MMC2_GPIO        OMAP_MPUIO(7)
+#define PALMTE_MMC3_GPIO        OMAP_MPUIO(11)
+
 static void __init omap_palmte_init_irq(void)
 {
         omap1_init_common_hw();
@@ -286,7 +301,6 @@ static void palmte_get_power_status(struct apm_power_info *info, int *battery)
 #endif
 
 static struct omap_board_config_kernel palmte_config[] __initdata = {
-        { OMAP_TAG_USB,         &palmte_usb_config },
         { OMAP_TAG_LCD,         &palmte_lcd_config },
         { OMAP_TAG_UART,        &palmte_uart_config },
 };
@@ -341,6 +355,7 @@ static void __init omap_palmte_init(void)
         spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info));
         palmte_misc_gpio_setup();
         omap_serial_init();
+        omap_usb_init(&palmte_usb_config);
         omap_register_i2c_bus(1, 100, NULL, 0);
 }
 
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 1cbc1275c95f..4f1b44831d37 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -43,6 +43,13 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 
+#define PALMTT_USBDETECT_GPIO   0
+#define PALMTT_CABLE_GPIO       1
+#define PALMTT_LED_GPIO         3
+#define PALMTT_PENIRQ_GPIO      6
+#define PALMTT_MMC_WP_GPIO      8
+#define PALMTT_HDQ_GPIO         11
+
 static int palmtt_keymap[] = {
         KEY(0, 0, KEY_ESC),
         KEY(0, 1, KEY_SPACE),
@@ -272,7 +279,6 @@ static struct omap_uart_config palmtt_uart_config __initdata = {
 };
 
 static struct omap_board_config_kernel palmtt_config[] __initdata = {
-        { OMAP_TAG_USB,         &palmtt_usb_config      },
         { OMAP_TAG_LCD,         &palmtt_lcd_config      },
         { OMAP_TAG_UART,        &palmtt_uart_config     },
 };
@@ -297,6 +303,7 @@ static void __init omap_palmtt_init(void)
 
         spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo));
         omap_serial_init();
+        omap_usb_init(&palmtt_usb_config);
         omap_register_i2c_bus(1, 100, NULL, 0);
 }
 
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index baf5efbfe3e8..9a55c3c58218 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -46,6 +46,16 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 
+#define PALMZ71_USBDETECT_GPIO  0
+#define PALMZ71_PENIRQ_GPIO     6
+#define PALMZ71_MMC_WP_GPIO     8
+#define PALMZ71_HDQ_GPIO        11
+
+#define PALMZ71_HOTSYNC_GPIO    OMAP_MPUIO(1)
+#define PALMZ71_CABLE_GPIO      OMAP_MPUIO(2)
+#define PALMZ71_SLIDER_GPIO     OMAP_MPUIO(3)
+#define PALMZ71_MMC_IN_GPIO     OMAP_MPUIO(4)
+
 static void __init
 omap_palmz71_init_irq(void)
 {
@@ -239,7 +249,6 @@ static struct omap_uart_config palmz71_uart_config __initdata = {
 };
 
 static struct omap_board_config_kernel palmz71_config[] __initdata = {
-        {OMAP_TAG_USB,  &palmz71_usb_config},
         {OMAP_TAG_LCD,  &palmz71_lcd_config},
         {OMAP_TAG_UART, &palmz71_uart_config},
 };
@@ -313,6 +322,7 @@ omap_palmz71_init(void)
 
         spi_register_board_info(palmz71_boardinfo,
                                 ARRAY_SIZE(palmz71_boardinfo));
+        omap_usb_init(&palmz71_usb_config);
         omap_serial_init();
         omap_register_i2c_bus(1, 100, NULL, 0);
         palmz71_gpio_setup(0);
diff --git a/arch/arm/mach-omap1/board-sx1-mmc.c b/arch/arm/mach-omap1/board-sx1-mmc.c
index 66a4d7d5255d..58a46e4e45c3 100644
--- a/arch/arm/mach-omap1/board-sx1-mmc.c
+++ b/arch/arm/mach-omap1/board-sx1-mmc.c
@@ -17,6 +17,7 @@
 #include <mach/hardware.h>
 #include <mach/mmc.h>
 #include <mach/gpio.h>
+#include <mach/board-sx1.h>
 
 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
 
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 28c76a1e71c0..c096577695fe 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -41,6 +41,7 @@
 #include <mach/board.h>
 #include <mach/common.h>
 #include <mach/keypad.h>
+#include <mach/board-sx1.h>
 
 /* Write to I2C device */
 int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value)
@@ -373,7 +374,6 @@ static struct omap_uart_config sx1_uart_config __initdata = {
 };
 
 static struct omap_board_config_kernel sx1_config[] __initdata = {
-        { OMAP_TAG_USB, &sx1_usb_config },
         { OMAP_TAG_LCD, &sx1_lcd_config },
         { OMAP_TAG_UART,        &sx1_uart_config },
 };
@@ -388,6 +388,7 @@ static void __init omap_sx1_init(void)
         omap_board_config_size = ARRAY_SIZE(sx1_config);
         omap_serial_init();
         omap_register_i2c_bus(1, 100, NULL, 0);
+        omap_usb_init(&sx1_usb_config);
         sx1_mmc_init();
 
         /* turn on USB power */
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index a7653542a2b0..98275e03dad1 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -145,7 +145,6 @@ static struct omap_uart_config voiceblue_uart_config __initdata = {
 };
 
 static struct omap_board_config_kernel voiceblue_config[] = {
-        { OMAP_TAG_USB,  &voiceblue_usb_config },
         { OMAP_TAG_UART, &voiceblue_uart_config },
 };
 
@@ -185,6 +184,7 @@ static void __init voiceblue_init(void)
         omap_board_config = voiceblue_config;
         omap_board_config_size = ARRAY_SIZE(voiceblue_config);
         omap_serial_init();
+        omap_usb_init(&voiceblue_usb_config);
         omap_register_i2c_bus(1, 100, NULL, 0);
 
         /* There is a good chance board is going up, so enable power LED
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 5fba20731710..dafe4f71d15f 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -20,41 +20,161 @@
 #include <linux/io.h>
 
 #include <asm/mach-types.h>
+#include <asm/clkdev.h>
 
 #include <mach/cpu.h>
 #include <mach/usb.h>
 #include <mach/clock.h>
 #include <mach/sram.h>
 
+static const struct clkops clkops_generic;
+static const struct clkops clkops_uart;
+static const struct clkops clkops_dspck;
+
 #include "clock.h"
 
+static int clk_omap1_dummy_enable(struct clk *clk)
+{
+        return 0;
+}
+
+static void clk_omap1_dummy_disable(struct clk *clk)
+{
+}
+
+static const struct clkops clkops_dummy = {
+        .enable = clk_omap1_dummy_enable,
+        .disable = clk_omap1_dummy_disable,
+};
+
+static struct clk dummy_ck = {
+        .name   = "dummy",
+        .ops    = &clkops_dummy,
+        .flags  = RATE_FIXED,
+};
+
+struct omap_clk {
+        u32             cpu;
+        struct clk_lookup lk;
+};
+
+#define CLK(dev, con, ck, cp)           \
+        {                               \
+                 .cpu = cp,             \
+                .lk = {                 \
+                        .dev_id = dev,  \
+                        .con_id = con,  \
+                        .clk = ck,      \
+                },                      \
+        }
+
+#define CK_310  (1 << 0)
+#define CK_730  (1 << 1)
+#define CK_1510 (1 << 2)
+#define CK_16XX (1 << 3)
+
+static struct omap_clk omap_clks[] = {
+        /* non-ULPD clocks */
+        CLK(NULL,       "ck_ref",       &ck_ref,        CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "ck_dpll1",     &ck_dpll1,      CK_16XX | CK_1510 | CK_310),
+        /* CK_GEN1 clocks */
+        CLK(NULL,       "ck_dpll1out",  &ck_dpll1out.clk, CK_16XX),
+        CLK(NULL,       "ck_sossi",     &sossi_ck,      CK_16XX),
+        CLK(NULL,       "arm_ck",       &arm_ck,        CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "armper_ck",    &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "arm_gpio_ck",  &arm_gpio_ck,   CK_1510 | CK_310),
+        CLK(NULL,       "armxor_ck",    &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "armtim_ck",    &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
+        CLK("omap_wdt", "fck",          &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
+        CLK("omap_wdt", "ick",          &armper_ck.clk, CK_16XX),
+        CLK("omap_wdt", "ick",          &dummy_ck,      CK_1510 | CK_310),
+        CLK(NULL,       "arminth_ck",   &arminth_ck1510, CK_1510 | CK_310),
+        CLK(NULL,       "arminth_ck",   &arminth_ck16xx, CK_16XX),
+        /* CK_GEN2 clocks */
+        CLK(NULL,       "dsp_ck",       &dsp_ck,        CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "dspmmu_ck",    &dspmmu_ck,     CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "dspper_ck",    &dspper_ck,     CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "dspxor_ck",    &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "dsptim_ck",    &dsptim_ck,     CK_16XX | CK_1510 | CK_310),
+        /* CK_GEN3 clocks */
+        CLK(NULL,       "tc_ck",        &tc_ck.clk,     CK_16XX | CK_1510 | CK_310 | CK_730),
+        CLK(NULL,       "tipb_ck",      &tipb_ck,       CK_1510 | CK_310),
+        CLK(NULL,       "l3_ocpi_ck",   &l3_ocpi_ck,    CK_16XX),
+        CLK(NULL,       "tc1_ck",       &tc1_ck,        CK_16XX),
+        CLK(NULL,       "tc2_ck",       &tc2_ck,        CK_16XX),
+        CLK(NULL,       "dma_ck",       &dma_ck,        CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
+        CLK(NULL,       "api_ck",       &api_ck.clk,    CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "lb_ck",        &lb_ck.clk,     CK_1510 | CK_310),
+        CLK(NULL,       "rhea1_ck",     &rhea1_ck,      CK_16XX),
+        CLK(NULL,       "rhea2_ck",     &rhea2_ck,      CK_16XX),
+        CLK(NULL,       "lcd_ck",       &lcd_ck_16xx,   CK_16XX | CK_730),
+        CLK(NULL,       "lcd_ck",       &lcd_ck_1510.clk, CK_1510 | CK_310),
+        /* ULPD clocks */
+        CLK(NULL,       "uart1_ck",     &uart1_1510,    CK_1510 | CK_310),
+        CLK(NULL,       "uart1_ck",     &uart1_16xx.clk, CK_16XX),
+        CLK(NULL,       "uart2_ck",     &uart2_ck,      CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "uart3_ck",     &uart3_1510,    CK_1510 | CK_310),
+        CLK(NULL,       "uart3_ck",     &uart3_16xx.clk, CK_16XX),
+        CLK(NULL,       "usb_clko",     &usb_clko,      CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck1510, CK_1510 | CK_310),
+        CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck16xx, CK_16XX),
+        CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX),
+        CLK(NULL,       "mclk",         &mclk_1510,     CK_1510 | CK_310),
+        CLK(NULL,       "mclk",         &mclk_16xx,     CK_16XX),
+        CLK(NULL,       "bclk",         &bclk_1510,     CK_1510 | CK_310),
+        CLK(NULL,       "bclk",         &bclk_16xx,     CK_16XX),
+        CLK("mmci-omap.0", "fck",       &mmc1_ck,       CK_16XX | CK_1510 | CK_310),
+        CLK("mmci-omap.0", "ick",       &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
+        CLK("mmci-omap.1", "fck",       &mmc2_ck,       CK_16XX),
+        CLK("mmci-omap.1", "ick",       &armper_ck.clk, CK_16XX),
+        /* Virtual clocks */
+        CLK(NULL,       "mpu",          &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
+        CLK("i2c_omap.1", "fck",        &i2c_fck,       CK_16XX | CK_1510 | CK_310),
+        CLK("i2c_omap.1", "ick",        &i2c_ick,       CK_16XX),
+        CLK("i2c_omap.1", "ick",        &dummy_ck,      CK_1510 | CK_310),
+        CLK("omap_uwire", "fck",        &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
+        CLK("omap-mcbsp.1", "ick",      &dspper_ck,     CK_16XX),
+        CLK("omap-mcbsp.1", "ick",      &dummy_ck,      CK_1510 | CK_310),
+        CLK("omap-mcbsp.2", "ick",      &armper_ck.clk, CK_16XX),
+        CLK("omap-mcbsp.2", "ick",      &dummy_ck,      CK_1510 | CK_310),
+        CLK("omap-mcbsp.3", "ick",      &dspper_ck,     CK_16XX),
+        CLK("omap-mcbsp.3", "ick",      &dummy_ck,      CK_1510 | CK_310),
+        CLK("omap-mcbsp.1", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
+        CLK("omap-mcbsp.2", "fck",      &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
+        CLK("omap-mcbsp.3", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
+};
+
+static int omap1_clk_enable_generic(struct clk * clk);
+static int omap1_clk_enable(struct clk *clk);
+static void omap1_clk_disable_generic(struct clk * clk);
+static void omap1_clk_disable(struct clk *clk);
+
 __u32 arm_idlect1_mask;
 
 /*-------------------------------------------------------------------------
  * Omap1 specific clock functions
  *-------------------------------------------------------------------------*/
 
-static void omap1_watchdog_recalc(struct clk * clk)
+static unsigned long omap1_watchdog_recalc(struct clk *clk)
 {
-        clk->rate = clk->parent->rate / 14;
+        return clk->parent->rate / 14;
 }
 
-static void omap1_uart_recalc(struct clk * clk)
+static unsigned long omap1_uart_recalc(struct clk *clk)
 {
-        unsigned int val = omap_readl(clk->enable_reg);
-        if (val & clk->enable_bit)
-                clk->rate = 48000000;
-        else
-                clk->rate = 12000000;
+        unsigned int val = __raw_readl(clk->enable_reg);
+        return val & clk->enable_bit ? 48000000 : 12000000;
 }
 
-static void omap1_sossi_recalc(struct clk *clk)
+static unsigned long omap1_sossi_recalc(struct clk *clk)
 {
         u32 div = omap_readl(MOD_CONF_CTRL_1);
 
         div = (div >> 17) & 0x7;
         div++;
-        clk->rate = clk->parent->rate / div;
+
+        return clk->parent->rate / div;
 }
 
 static int omap1_clk_enable_dsp_domain(struct clk *clk)
@@ -78,6 +198,11 @@ static void omap1_clk_disable_dsp_domain(struct clk *clk)
         }
 }
 
+static const struct clkops clkops_dspck = {
+        .enable         = &omap1_clk_enable_dsp_domain,
+        .disable        = &omap1_clk_disable_dsp_domain,
+};
+
 static int omap1_clk_enable_uart_functional(struct clk *clk)
 {
         int ret;
@@ -105,6 +230,11 @@ static void omap1_clk_disable_uart_functional(struct clk *clk)
         omap1_clk_disable_generic(clk);
 }
 
+static const struct clkops clkops_uart = {
+        .enable         = &omap1_clk_enable_uart_functional,
+        .disable        = &omap1_clk_disable_uart_functional,
+};
+
 static void omap1_clk_allow_idle(struct clk *clk)
 {
         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
@@ -197,9 +327,6 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate)
         struct clk * parent;
         unsigned  dsor_exp;
 
-        if (unlikely(!(clk->flags & RATE_CKCTL)))
-                return -EINVAL;
-
         parent = clk->parent;
         if (unlikely(parent == NULL))
                 return -EIO;
@@ -215,22 +342,15 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate)
         return dsor_exp;
 }
 
-static void omap1_ckctl_recalc(struct clk * clk)
+static unsigned long omap1_ckctl_recalc(struct clk *clk)
 {
-        int dsor;
-
         /* Calculate divisor encoded as 2-bit exponent */
-        dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
+        int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
 
-        if (unlikely(clk->rate == clk->parent->rate / dsor))
-                return; /* No change, quick exit */
-        clk->rate = clk->parent->rate / dsor;
-
-        if (unlikely(clk->flags & RATE_PROPAGATES))
-                propagate_rate(clk);
+        return clk->parent->rate / dsor;
 }
 
-static void omap1_ckctl_recalc_dsp_domain(struct clk * clk)
+static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
 {
         int dsor;
 
@@ -245,12 +365,7 @@ static void omap1_ckctl_recalc_dsp_domain(struct clk * clk)
         dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
         omap1_clk_disable(&api_ck.clk);
 
-        if (unlikely(clk->rate == clk->parent->rate / dsor))
-                return; /* No change, quick exit */
-        clk->rate = clk->parent->rate / dsor;
-
-        if (unlikely(clk->flags & RATE_PROPAGATES))
-                propagate_rate(clk);
+        return clk->parent->rate / dsor;
 }
 
 /* MPU virtual clock functions */
@@ -289,35 +404,57 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
 
         ck_dpll1.rate = ptr->pll_rate;
-        propagate_rate(&ck_dpll1);
         return 0;
 }
 
 static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
 {
-        int  ret = -EINVAL;
-        int  dsor_exp;
-        __u16  regval;
-
-        if (clk->flags & RATE_CKCTL) {
-                dsor_exp = calc_dsor_exp(clk, rate);
-                if (dsor_exp > 3)
-                        dsor_exp = -EINVAL;
-                if (dsor_exp < 0)
-                        return dsor_exp;
-
-                regval = __raw_readw(DSP_CKCTL);
-                regval &= ~(3 << clk->rate_offset);
-                regval |= dsor_exp << clk->rate_offset;
-                __raw_writew(regval, DSP_CKCTL);
-                clk->rate = clk->parent->rate / (1 << dsor_exp);
-                ret = 0;
-        }
+        int dsor_exp;
+        u16 regval;
 
-        if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
-                propagate_rate(clk);
+        dsor_exp = calc_dsor_exp(clk, rate);
+        if (dsor_exp > 3)
+                dsor_exp = -EINVAL;
+        if (dsor_exp < 0)
+                return dsor_exp;
 
-        return ret;
+        regval = __raw_readw(DSP_CKCTL);
+        regval &= ~(3 << clk->rate_offset);
+        regval |= dsor_exp << clk->rate_offset;
+        __raw_writew(regval, DSP_CKCTL);
+        clk->rate = clk->parent->rate / (1 << dsor_exp);
+
+        return 0;
+}
+
+static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
+{
+        int dsor_exp = calc_dsor_exp(clk, rate);
+        if (dsor_exp < 0)
+                return dsor_exp;
+        if (dsor_exp > 3)
+                dsor_exp = 3;
+        return clk->parent->rate / (1 << dsor_exp);
+}
+
+static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
+{
+        int dsor_exp;
+        u16 regval;
+
+        dsor_exp = calc_dsor_exp(clk, rate);
+        if (dsor_exp > 3)
+                dsor_exp = -EINVAL;
+        if (dsor_exp < 0)
+                return dsor_exp;
+
+        regval = omap_readw(ARM_CKCTL);
+        regval &= ~(3 << clk->rate_offset);
+        regval |= dsor_exp << clk->rate_offset;
+        regval = verify_ckctl_value(regval);
+        omap_writew(regval, ARM_CKCTL);
+        clk->rate = clk->parent->rate / (1 << dsor_exp);
+        return 0;
 }
 
 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate)
@@ -372,14 +509,14 @@ static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
 {
         unsigned int val;
 
-        val = omap_readl(clk->enable_reg);
+        val = __raw_readl(clk->enable_reg);
         if (rate == 12000000)
                 val &= ~(1 << clk->enable_bit);
         else if (rate == 48000000)
                 val |= (1 << clk->enable_bit);
         else
                 return -EINVAL;
-        omap_writel(val, clk->enable_reg);
+        __raw_writel(val, clk->enable_reg);
         clk->rate = rate;
 
         return 0;
@@ -398,8 +535,8 @@ static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
         else
                 ratio_bits = (dsor - 2) << 2;
 
-        ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
-        omap_writew(ratio_bits, clk->enable_reg);
+        ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd;
+        __raw_writew(ratio_bits, clk->enable_reg);
 
         return 0;
 }
@@ -423,8 +560,6 @@ static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
         omap_writel(l, MOD_CONF_CTRL_1);
 
         clk->rate = p_rate / (div + 1);
-        if (unlikely(clk->flags & RATE_PROPAGATES))
-                propagate_rate(clk);
 
         return 0;
 }
@@ -440,8 +575,8 @@ static void omap1_init_ext_clk(struct clk * clk)
         __u16 ratio_bits;
 
         /* Determine current rate and ensure clock is based on 96MHz APLL */
-        ratio_bits = omap_readw(clk->enable_reg) & ~1;
-        omap_writew(ratio_bits, clk->enable_reg);
+        ratio_bits = __raw_readw(clk->enable_reg) & ~1;
+        __raw_writew(ratio_bits, clk->enable_reg);
 
         ratio_bits = (ratio_bits & 0xfc) >> 2;
         if (ratio_bits > 6)
@@ -468,7 +603,7 @@ static int omap1_clk_enable(struct clk *clk)
                                 omap1_clk_deny_idle(clk->parent);
                 }
 
-                ret = clk->enable(clk);
+                ret = clk->ops->enable(clk);
 
                 if (unlikely(ret != 0) && clk->parent) {
                         omap1_clk_disable(clk->parent);
@@ -482,7 +617,7 @@ static int omap1_clk_enable(struct clk *clk)
 static void omap1_clk_disable(struct clk *clk)
 {
         if (clk->usecount > 0 && !(--clk->usecount)) {
-                clk->disable(clk);
+                clk->ops->disable(clk);
                 if (likely(clk->parent)) {
                         omap1_clk_disable(clk->parent);
                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
@@ -496,9 +631,6 @@ static int omap1_clk_enable_generic(struct clk *clk)
         __u16 regval16;
         __u32 regval32;
 
-        if (clk->flags & ALWAYS_ENABLED)
-                return 0;
-
         if (unlikely(clk->enable_reg == NULL)) {
                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
                        clk->name);
@@ -506,25 +638,13 @@ static int omap1_clk_enable_generic(struct clk *clk)
         }
 
         if (clk->flags & ENABLE_REG_32BIT) {
-                if (clk->flags & VIRTUAL_IO_ADDRESS) {
-                        regval32 = __raw_readl(clk->enable_reg);
-                        regval32 |= (1 << clk->enable_bit);
-                        __raw_writel(regval32, clk->enable_reg);
-                } else {
-                        regval32 = omap_readl(clk->enable_reg);
-                        regval32 |= (1 << clk->enable_bit);
-                        omap_writel(regval32, clk->enable_reg);
-                }
+                regval32 = __raw_readl(clk->enable_reg);
+                regval32 |= (1 << clk->enable_bit);
+                __raw_writel(regval32, clk->enable_reg);
         } else {
-                if (clk->flags & VIRTUAL_IO_ADDRESS) {
-                        regval16 = __raw_readw(clk->enable_reg);
-                        regval16 |= (1 << clk->enable_bit);
-                        __raw_writew(regval16, clk->enable_reg);
-                } else {
-                        regval16 = omap_readw(clk->enable_reg);
-                        regval16 |= (1 << clk->enable_bit);
-                        omap_writew(regval16, clk->enable_reg);
-                }
+                regval16 = __raw_readw(clk->enable_reg);
+                regval16 |= (1 << clk->enable_bit);
+                __raw_writew(regval16, clk->enable_reg);
         }
 
         return 0;
@@ -539,44 +659,26 @@ static void omap1_clk_disable_generic(struct clk *clk)
                 return;
 
         if (clk->flags & ENABLE_REG_32BIT) {
-                if (clk->flags & VIRTUAL_IO_ADDRESS) {
-                        regval32 = __raw_readl(clk->enable_reg);
-                        regval32 &= ~(1 << clk->enable_bit);
-                        __raw_writel(regval32, clk->enable_reg);
-                } else {
-                        regval32 = omap_readl(clk->enable_reg);
-                        regval32 &= ~(1 << clk->enable_bit);
-                        omap_writel(regval32, clk->enable_reg);
-                }
+                regval32 = __raw_readl(clk->enable_reg);
+                regval32 &= ~(1 << clk->enable_bit);
+                __raw_writel(regval32, clk->enable_reg);
         } else {
-                if (clk->flags & VIRTUAL_IO_ADDRESS) {
-                        regval16 = __raw_readw(clk->enable_reg);
-                        regval16 &= ~(1 << clk->enable_bit);
-                        __raw_writew(regval16, clk->enable_reg);
-                } else {
-                        regval16 = omap_readw(clk->enable_reg);
-                        regval16 &= ~(1 << clk->enable_bit);
-                        omap_writew(regval16, clk->enable_reg);
-                }
+                regval16 = __raw_readw(clk->enable_reg);
+                regval16 &= ~(1 << clk->enable_bit);
+                __raw_writew(regval16, clk->enable_reg);
         }
 }
 
+static const struct clkops clkops_generic = {
+        .enable         = &omap1_clk_enable_generic,
+        .disable        = &omap1_clk_disable_generic,
+};
+
 static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
 {
-        int dsor_exp;
-
         if (clk->flags & RATE_FIXED)
                 return clk->rate;
 
-        if (clk->flags & RATE_CKCTL) {
-                dsor_exp = calc_dsor_exp(clk, rate);
-                if (dsor_exp < 0)
-                        return dsor_exp;
-                if (dsor_exp > 3)
-                        dsor_exp = 3;
-                return clk->parent->rate / (1 << dsor_exp);
-        }
-
         if (clk->round_rate != NULL)
                 return clk->round_rate(clk, rate);
 
@@ -586,30 +688,9 @@ static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
 static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
 {
         int  ret = -EINVAL;
-        int  dsor_exp;
-        __u16  regval;
 
         if (clk->set_rate)
                 ret = clk->set_rate(clk, rate);
-        else if (clk->flags & RATE_CKCTL) {
-                dsor_exp = calc_dsor_exp(clk, rate);
-                if (dsor_exp > 3)
-                        dsor_exp = -EINVAL;
-                if (dsor_exp < 0)
-                        return dsor_exp;
-
-                regval = omap_readw(ARM_CKCTL);
-                regval &= ~(3 << clk->rate_offset);
-                regval |= dsor_exp << clk->rate_offset;
-                regval = verify_ckctl_value(regval);
-                omap_writew(regval, ARM_CKCTL);
-                clk->rate = clk->parent->rate / (1 << dsor_exp);
-                ret = 0;
-        }
-
-        if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
-                propagate_rate(clk);
-
         return ret;
 }
 
@@ -632,17 +713,10 @@ static void __init omap1_clk_disable_unused(struct clk *clk)
         }
 
         /* Is the clock already disabled? */
-        if (clk->flags & ENABLE_REG_32BIT) {
-                if (clk->flags & VIRTUAL_IO_ADDRESS)
-                        regval32 = __raw_readl(clk->enable_reg);
-                        else
-                                regval32 = omap_readl(clk->enable_reg);
-        } else {
-                if (clk->flags & VIRTUAL_IO_ADDRESS)
-                        regval32 = __raw_readw(clk->enable_reg);
-                else
-                        regval32 = omap_readw(clk->enable_reg);
-        }
+        if (clk->flags & ENABLE_REG_32BIT)
+                regval32 = __raw_readl(clk->enable_reg);
+        else
+                regval32 = __raw_readw(clk->enable_reg);
 
         if ((regval32 & (1 << clk->enable_bit)) == 0)
                 return;
@@ -659,7 +733,7 @@ static void __init omap1_clk_disable_unused(struct clk *clk)
         }
 
         printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
-        clk->disable(clk);
+        clk->ops->disable(clk);
         printk(" done\n");
 }
 
@@ -677,10 +751,10 @@ static struct clk_functions omap1_clk_functions = {
 
 int __init omap1_clk_init(void)
 {
-        struct clk ** clkp;
+        struct omap_clk *c;
         const struct omap_clock_config *info;
         int crystal_type = 0; /* Default 12 MHz */
-        u32 reg;
+        u32 reg, cpu_mask;
 
 #ifdef CONFIG_DEBUG_LL
         /* Resets some clocks that may be left on from bootloader,
@@ -700,27 +774,24 @@ int __init omap1_clk_init(void)
         /* By default all idlect1 clocks are allowed to idle */
         arm_idlect1_mask = ~0;
 
-        for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
-                if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) {
-                        clk_register(*clkp);
-                        continue;
-                }
-
-                if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) {
-                        clk_register(*clkp);
-                        continue;
-                }
-
-                if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) {
-                        clk_register(*clkp);
-                        continue;
-                }
+        for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
+                clk_init_one(c->lk.clk);
 
-                if (((*clkp)->flags &CLOCK_IN_OMAP310) && cpu_is_omap310()) {
-                        clk_register(*clkp);
-                        continue;
+        cpu_mask = 0;
+        if (cpu_is_omap16xx())
+                cpu_mask |= CK_16XX;
+        if (cpu_is_omap1510())
+                cpu_mask |= CK_1510;
+        if (cpu_is_omap730())
+                cpu_mask |= CK_730;
+        if (cpu_is_omap310())
+                cpu_mask |= CK_310;
+
+        for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
+                if (c->cpu & cpu_mask) {
+                        clkdev_add(&c->lk);
+                        clk_register(c->lk.clk);
                 }
-        }
 
         info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
         if (info != NULL) {
@@ -769,7 +840,6 @@ int __init omap1_clk_init(void)
                         }
                 }
         }
-        propagate_rate(&ck_dpll1);
 #else
         /* Find the highest supported frequency and enable it */
         if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
@@ -778,9 +848,9 @@ int __init omap1_clk_init(void)
                 omap_writew(0x2290, DPLL_CTL);
                 omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
                 ck_dpll1.rate = 60000000;
-                propagate_rate(&ck_dpll1);
         }
 #endif
+        propagate_rate(&ck_dpll1);
         /* Cache rates for clocks connected to ck_ref (not dpll1) */
         propagate_rate(&ck_ref);
         printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
@@ -832,4 +902,3 @@ int __init omap1_clk_init(void)
 
         return 0;
 }
-
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index c1dcdf18d8dd..17f874271255 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -13,27 +13,22 @@
 #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H
 
-static int omap1_clk_enable_generic(struct clk * clk);
-static void omap1_clk_disable_generic(struct clk * clk);
-static void omap1_ckctl_recalc(struct clk * clk);
-static void omap1_watchdog_recalc(struct clk * clk);
+static unsigned long omap1_ckctl_recalc(struct clk *clk);
+static unsigned long omap1_watchdog_recalc(struct clk *clk);
 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
-static void omap1_sossi_recalc(struct clk *clk);
-static void omap1_ckctl_recalc_dsp_domain(struct clk * clk);
-static int omap1_clk_enable_dsp_domain(struct clk * clk);
+static unsigned long omap1_sossi_recalc(struct clk *clk);
+static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
 static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
-static void omap1_clk_disable_dsp_domain(struct clk * clk);
 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
-static void omap1_uart_recalc(struct clk * clk);
-static int omap1_clk_enable_uart_functional(struct clk * clk);
-static void omap1_clk_disable_uart_functional(struct clk * clk);
+static unsigned long omap1_uart_recalc(struct clk *clk);
 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
 static void omap1_init_ext_clk(struct clk * clk);
 static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
-static int omap1_clk_enable(struct clk *clk);
-static void omap1_clk_disable(struct clk *clk);
+
+static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
+static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
 
 struct mpu_rate {
         unsigned long           rate;
@@ -152,101 +147,84 @@ static struct mpu_rate rate_table[] = {
 
 static struct clk ck_ref = {
         .name           = "ck_ref",
+        .ops            = &clkops_null,
         .rate           = 12000000,
-        .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                          CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct clk ck_dpll1 = {
         .name           = "ck_dpll1",
+        .ops            = &clkops_null,
         .parent         = &ck_ref,
-        .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                          CLOCK_IN_OMAP310 | RATE_PROPAGATES | ALWAYS_ENABLED,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct arm_idlect1_clk ck_dpll1out = {
         .clk = {
                 .name           = "ck_dpll1out",
+                .ops            = &clkops_generic,
                 .parent         = &ck_dpll1,
-                .flags          = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL |
-                                  ENABLE_REG_32BIT | RATE_PROPAGATES,
-                .enable_reg     = (void __iomem *)ARM_IDLECT2,
+                .flags          = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
                 .enable_bit     = EN_CKOUT_ARM,
                 .recalc         = &followparent_recalc,
-                .enable         = &omap1_clk_enable_generic,
-                .disable        = &omap1_clk_disable_generic,
         },
         .idlect_shift   = 12,
 };
 
 static struct clk sossi_ck = {
         .name           = "ck_sossi",
+        .ops            = &clkops_generic,
         .parent         = &ck_dpll1out.clk,
-        .flags          = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT |
-                          ENABLE_REG_32BIT,
-        .enable_reg     = (void __iomem *)MOD_CONF_CTRL_1,
+        .flags          = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
+        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
         .enable_bit     = 16,
         .recalc         = &omap1_sossi_recalc,
         .set_rate       = &omap1_set_sossi_rate,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct clk arm_ck = {
         .name           = "arm_ck",
+        .ops            = &clkops_null,
         .parent         = &ck_dpll1,
-        .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                          CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES |
-                          ALWAYS_ENABLED,
         .rate_offset    = CKCTL_ARMDIV_OFFSET,
         .recalc         = &omap1_ckctl_recalc,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
+        .round_rate     = omap1_clk_round_rate_ckctl_arm,
+        .set_rate       = omap1_clk_set_rate_ckctl_arm,
 };
 
 static struct arm_idlect1_clk armper_ck = {
         .clk = {
                 .name           = "armper_ck",
+                .ops            = &clkops_generic,
                 .parent         = &ck_dpll1,
-                .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                                  CLOCK_IN_OMAP310 | RATE_CKCTL |
-                                  CLOCK_IDLE_CONTROL,
-                .enable_reg     = (void __iomem *)ARM_IDLECT2,
+                .flags          = CLOCK_IDLE_CONTROL,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
                 .enable_bit     = EN_PERCK,
                 .rate_offset    = CKCTL_PERDIV_OFFSET,
                 .recalc         = &omap1_ckctl_recalc,
-                .enable         = &omap1_clk_enable_generic,
-                .disable        = &omap1_clk_disable_generic,
+                .round_rate     = omap1_clk_round_rate_ckctl_arm,
+                .set_rate       = omap1_clk_set_rate_ckctl_arm,
         },
         .idlect_shift   = 2,
 };
 
 static struct clk arm_gpio_ck = {
         .name           = "arm_gpio_ck",
+        .ops            = &clkops_generic,
         .parent         = &ck_dpll1,
-        .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
-        .enable_reg     = (void __iomem *)ARM_IDLECT2,
+        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
         .enable_bit     = EN_GPIOCK,
         .recalc         = &followparent_recalc,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct arm_idlect1_clk armxor_ck = {
         .clk = {
                 .name           = "armxor_ck",
+                .ops            = &clkops_generic,
                 .parent         = &ck_ref,
-                .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                                  CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
-                .enable_reg     = (void __iomem *)ARM_IDLECT2,
+                .flags          = CLOCK_IDLE_CONTROL,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
                 .enable_bit     = EN_XORPCK,
                 .recalc         = &followparent_recalc,
-                .enable         = &omap1_clk_enable_generic,
-                .disable        = &omap1_clk_disable_generic,
         },
         .idlect_shift   = 1,
 };
@@ -254,14 +232,12 @@ static struct arm_idlect1_clk armxor_ck = {
 static struct arm_idlect1_clk armtim_ck = {
         .clk = {
                 .name           = "armtim_ck",
+                .ops            = &clkops_generic,
                 .parent         = &ck_ref,
-                .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                                  CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
-                .enable_reg     = (void __iomem *)ARM_IDLECT2,
+                .flags          = CLOCK_IDLE_CONTROL,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
                 .enable_bit     = EN_TIMCK,
                 .recalc         = &followparent_recalc,
-                .enable         = &omap1_clk_enable_generic,
-                .disable        = &omap1_clk_disable_generic,
         },
         .idlect_shift   = 9,
 };
@@ -269,201 +245,166 @@ static struct arm_idlect1_clk armtim_ck = {
 static struct arm_idlect1_clk armwdt_ck = {
         .clk = {
                 .name           = "armwdt_ck",
+                .ops            = &clkops_generic,
                 .parent         = &ck_ref,
-                .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                                  CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
-                .enable_reg     = (void __iomem *)ARM_IDLECT2,
+                .flags          = CLOCK_IDLE_CONTROL,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
                 .enable_bit     = EN_WDTCK,
                 .recalc         = &omap1_watchdog_recalc,
-                .enable         = &omap1_clk_enable_generic,
-                .disable        = &omap1_clk_disable_generic,
         },
         .idlect_shift   = 0,
 };
 
 static struct clk arminth_ck16xx = {
         .name           = "arminth_ck",
+        .ops            = &clkops_null,
         .parent         = &arm_ck,
-        .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
         .recalc         = &followparent_recalc,
         /* Note: On 16xx the frequency can be divided by 2 by programming
          * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
          *
          * 1510 version is in TC clocks.
          */
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct clk dsp_ck = {
         .name           = "dsp_ck",
+        .ops            = &clkops_generic,
         .parent         = &ck_dpll1,
-        .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                          RATE_CKCTL,
-        .enable_reg     = (void __iomem *)ARM_CKCTL,
+        .enable_reg     = OMAP1_IO_ADDRESS(ARM_CKCTL),
         .enable_bit     = EN_DSPCK,
         .rate_offset    = CKCTL_DSPDIV_OFFSET,
         .recalc         = &omap1_ckctl_recalc,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
+        .round_rate     = omap1_clk_round_rate_ckctl_arm,
+        .set_rate       = omap1_clk_set_rate_ckctl_arm,
 };
 
 static struct clk dspmmu_ck = {
         .name           = "dspmmu_ck",
+        .ops            = &clkops_null,
         .parent         = &ck_dpll1,
-        .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                          RATE_CKCTL | ALWAYS_ENABLED,
         .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
         .recalc         = &omap1_ckctl_recalc,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
+        .round_rate     = omap1_clk_round_rate_ckctl_arm,
+        .set_rate       = omap1_clk_set_rate_ckctl_arm,
 };
 
 static struct clk dspper_ck = {
         .name           = "dspper_ck",
+        .ops            = &clkops_dspck,
         .parent         = &ck_dpll1,
-        .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                          RATE_CKCTL | VIRTUAL_IO_ADDRESS,
         .enable_reg     = DSP_IDLECT2,
         .enable_bit     = EN_PERCK,
         .rate_offset    = CKCTL_PERDIV_OFFSET,
         .recalc         = &omap1_ckctl_recalc_dsp_domain,
+        .round_rate     = omap1_clk_round_rate_ckctl_arm,
         .set_rate       = &omap1_clk_set_rate_dsp_domain,
-        .enable         = &omap1_clk_enable_dsp_domain,
-        .disable        = &omap1_clk_disable_dsp_domain,
 };
 
 static struct clk dspxor_ck = {
         .name           = "dspxor_ck",
+        .ops            = &clkops_dspck,
         .parent         = &ck_ref,
-        .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                          VIRTUAL_IO_ADDRESS,
         .enable_reg     = DSP_IDLECT2,
         .enable_bit     = EN_XORPCK,
         .recalc         = &followparent_recalc,
-        .enable         = &omap1_clk_enable_dsp_domain,
-        .disable        = &omap1_clk_disable_dsp_domain,
 };
 
 static struct clk dsptim_ck = {
         .name           = "dsptim_ck",
+        .ops            = &clkops_dspck,
         .parent         = &ck_ref,
-        .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                          VIRTUAL_IO_ADDRESS,
         .enable_reg     = DSP_IDLECT2,
         .enable_bit     = EN_DSPTIMCK,
         .recalc         = &followparent_recalc,
-        .enable         = &omap1_clk_enable_dsp_domain,
-        .disable        = &omap1_clk_disable_dsp_domain,
 };
 
 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
 static struct arm_idlect1_clk tc_ck = {
         .clk = {
                 .name           = "tc_ck",
+                .ops            = &clkops_null,
                 .parent         = &ck_dpll1,
-                .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                                  CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
-                                  RATE_CKCTL | RATE_PROPAGATES |
-                                  ALWAYS_ENABLED | CLOCK_IDLE_CONTROL,
+                .flags          = CLOCK_IDLE_CONTROL,
                 .rate_offset    = CKCTL_TCDIV_OFFSET,
                 .recalc         = &omap1_ckctl_recalc,
-                .enable         = &omap1_clk_enable_generic,
-                .disable        = &omap1_clk_disable_generic,
+                .round_rate     = omap1_clk_round_rate_ckctl_arm,
+                .set_rate       = omap1_clk_set_rate_ckctl_arm,
         },
         .idlect_shift   = 6,
 };
 
 static struct clk arminth_ck1510 = {
         .name           = "arminth_ck",
+        .ops            = &clkops_null,
         .parent         = &tc_ck.clk,
-        .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
-                          ALWAYS_ENABLED,
         .recalc         = &followparent_recalc,
         /* Note: On 1510 the frequency follows TC_CK
          *
          * 16xx version is in MPU clocks.
          */
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct clk tipb_ck = {
         /* No-idle controlled by "tc_ck" */
         .name           = "tipb_ck",
+        .ops            = &clkops_null,
         .parent         = &tc_ck.clk,
-        .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
-                          ALWAYS_ENABLED,
         .recalc         = &followparent_recalc,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct clk l3_ocpi_ck = {
         /* No-idle controlled by "tc_ck" */
         .name           = "l3_ocpi_ck",
+        .ops            = &clkops_generic,
         .parent         = &tc_ck.clk,
-        .flags          = CLOCK_IN_OMAP16XX,
-        .enable_reg     = (void __iomem *)ARM_IDLECT3,
+        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
         .enable_bit     = EN_OCPI_CK,
         .recalc         = &followparent_recalc,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct clk tc1_ck = {
         .name           = "tc1_ck",
+        .ops            = &clkops_generic,
         .parent         = &tc_ck.clk,
-        .flags          = CLOCK_IN_OMAP16XX,
-        .enable_reg     = (void __iomem *)ARM_IDLECT3,
+        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
         .enable_bit     = EN_TC1_CK,
         .recalc         = &followparent_recalc,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct clk tc2_ck = {
         .name           = "tc2_ck",
+        .ops            = &clkops_generic,
         .parent         = &tc_ck.clk,
-        .flags          = CLOCK_IN_OMAP16XX,
-        .enable_reg     = (void __iomem *)ARM_IDLECT3,
+        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
         .enable_bit     = EN_TC2_CK,
         .recalc         = &followparent_recalc,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct clk dma_ck = {
         /* No-idle controlled by "tc_ck" */
         .name           = "dma_ck",
+        .ops            = &clkops_null,
         .parent         = &tc_ck.clk,
-        .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                          CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
         .recalc         = &followparent_recalc,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct clk dma_lcdfree_ck = {
         .name           = "dma_lcdfree_ck",
+        .ops            = &clkops_null,
         .parent         = &tc_ck.clk,
-        .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
         .recalc         = &followparent_recalc,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct arm_idlect1_clk api_ck = {
         .clk = {
                 .name           = "api_ck",
+                .ops            = &clkops_generic,
                 .parent         = &tc_ck.clk,
-                .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                                  CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
-                .enable_reg     = (void __iomem *)ARM_IDLECT2,
+                .flags          = CLOCK_IDLE_CONTROL,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
                 .enable_bit     = EN_APICK,
                 .recalc         = &followparent_recalc,
-                .enable         = &omap1_clk_enable_generic,
-                .disable        = &omap1_clk_disable_generic,
         },
         .idlect_shift   = 8,
 };
@@ -471,276 +412,238 @@ static struct arm_idlect1_clk api_ck = {
 static struct arm_idlect1_clk lb_ck = {
         .clk = {
                 .name           = "lb_ck",
+                .ops            = &clkops_generic,
                 .parent         = &tc_ck.clk,
-                .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
-                                  CLOCK_IDLE_CONTROL,
-                .enable_reg     = (void __iomem *)ARM_IDLECT2,
+                .flags          = CLOCK_IDLE_CONTROL,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
                 .enable_bit     = EN_LBCK,
                 .recalc         = &followparent_recalc,
-                .enable         = &omap1_clk_enable_generic,
-                .disable        = &omap1_clk_disable_generic,
         },
         .idlect_shift   = 4,
 };
 
 static struct clk rhea1_ck = {
         .name           = "rhea1_ck",
+        .ops            = &clkops_null,
         .parent         = &tc_ck.clk,
-        .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
         .recalc         = &followparent_recalc,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct clk rhea2_ck = {
         .name           = "rhea2_ck",
+        .ops            = &clkops_null,
         .parent         = &tc_ck.clk,
-        .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
         .recalc         = &followparent_recalc,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct clk lcd_ck_16xx = {
         .name           = "lcd_ck",
+        .ops            = &clkops_generic,
         .parent         = &ck_dpll1,
-        .flags          = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL,
-        .enable_reg     = (void __iomem *)ARM_IDLECT2,
+        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
         .enable_bit     = EN_LCDCK,
         .rate_offset    = CKCTL_LCDDIV_OFFSET,
         .recalc         = &omap1_ckctl_recalc,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
+        .round_rate     = omap1_clk_round_rate_ckctl_arm,
+        .set_rate       = omap1_clk_set_rate_ckctl_arm,
 };
 
 static struct arm_idlect1_clk lcd_ck_1510 = {
         .clk = {
                 .name           = "lcd_ck",
+                .ops            = &clkops_generic,
                 .parent         = &ck_dpll1,
-                .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
-                                  RATE_CKCTL | CLOCK_IDLE_CONTROL,
-                .enable_reg     = (void __iomem *)ARM_IDLECT2,
+                .flags          = CLOCK_IDLE_CONTROL,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
                 .enable_bit     = EN_LCDCK,
                 .rate_offset    = CKCTL_LCDDIV_OFFSET,
                 .recalc         = &omap1_ckctl_recalc,
-                .enable         = &omap1_clk_enable_generic,
-                .disable        = &omap1_clk_disable_generic,
+                .round_rate     = omap1_clk_round_rate_ckctl_arm,
+                .set_rate       = omap1_clk_set_rate_ckctl_arm,
         },
         .idlect_shift   = 3,
 };
 
 static struct clk uart1_1510 = {
         .name           = "uart1_ck",
+        .ops            = &clkops_null,
         /* Direct from ULPD, no real parent */
         .parent         = &armper_ck.clk,
         .rate           = 12000000,
-        .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
-                          ENABLE_REG_32BIT | ALWAYS_ENABLED |
-                          CLOCK_NO_IDLE_PARENT,
-        .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
+        .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
+        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
         .enable_bit     = 29,   /* Chooses between 12MHz and 48MHz */
         .set_rate       = &omap1_set_uart_rate,
         .recalc         = &omap1_uart_recalc,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct uart_clk uart1_16xx = {
         .clk    = {
                 .name           = "uart1_ck",
+                .ops            = &clkops_uart,
                 /* Direct from ULPD, no real parent */
                 .parent         = &armper_ck.clk,
                 .rate           = 48000000,
-                .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED |
-                                  ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
-                .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
+                .flags          = RATE_FIXED | ENABLE_REG_32BIT |
+                                  CLOCK_NO_IDLE_PARENT,
+                .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
                 .enable_bit     = 29,
-                .enable         = &omap1_clk_enable_uart_functional,
-                .disable        = &omap1_clk_disable_uart_functional,
         },
         .sysc_addr      = 0xfffb0054,
 };
 
 static struct clk uart2_ck = {
         .name           = "uart2_ck",
+        .ops            = &clkops_null,
         /* Direct from ULPD, no real parent */
         .parent         = &armper_ck.clk,
         .rate           = 12000000,
-        .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                          CLOCK_IN_OMAP310 | ENABLE_REG_32BIT |
-                          ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT,
-        .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
+        .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
+        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
         .enable_bit     = 30,   /* Chooses between 12MHz and 48MHz */
         .set_rate       = &omap1_set_uart_rate,
         .recalc         = &omap1_uart_recalc,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct clk uart3_1510 = {
         .name           = "uart3_ck",
+        .ops            = &clkops_null,
         /* Direct from ULPD, no real parent */
         .parent         = &armper_ck.clk,
         .rate           = 12000000,
-        .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
-                          ENABLE_REG_32BIT | ALWAYS_ENABLED |
-                          CLOCK_NO_IDLE_PARENT,
-        .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
+        .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
+        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
         .enable_bit     = 31,   /* Chooses between 12MHz and 48MHz */
         .set_rate       = &omap1_set_uart_rate,
         .recalc         = &omap1_uart_recalc,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct uart_clk uart3_16xx = {
         .clk    = {
                 .name           = "uart3_ck",
+                .ops            = &clkops_uart,
                 /* Direct from ULPD, no real parent */
                 .parent         = &armper_ck.clk,
                 .rate           = 48000000,
-                .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED |
-                                  ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
-                .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
+                .flags          = RATE_FIXED | ENABLE_REG_32BIT |
+                                  CLOCK_NO_IDLE_PARENT,
+                .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
                 .enable_bit     = 31,
-                .enable         = &omap1_clk_enable_uart_functional,
-                .disable        = &omap1_clk_disable_uart_functional,
         },
         .sysc_addr      = 0xfffb9854,
 };
 
 static struct clk usb_clko = {  /* 6 MHz output on W4_USB_CLKO */
         .name           = "usb_clko",
+        .ops            = &clkops_generic,
         /* Direct from ULPD, no parent */
         .rate           = 6000000,
-        .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                          CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT,
-        .enable_reg     = (void __iomem *)ULPD_CLOCK_CTRL,
+        .flags          = RATE_FIXED | ENABLE_REG_32BIT,
+        .enable_reg     = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
         .enable_bit     = USB_MCLK_EN_BIT,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct clk usb_hhc_ck1510 = {
         .name           = "usb_hhc_ck",
+        .ops            = &clkops_generic,
         /* Direct from ULPD, no parent */
         .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
-        .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
-                          RATE_FIXED | ENABLE_REG_32BIT,
-        .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
+        .flags          = RATE_FIXED | ENABLE_REG_32BIT,
+        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
         .enable_bit     = USB_HOST_HHC_UHOST_EN,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct clk usb_hhc_ck16xx = {
         .name           = "usb_hhc_ck",
+        .ops            = &clkops_generic,
         /* Direct from ULPD, no parent */
         .rate           = 48000000,
         /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
-        .flags          = CLOCK_IN_OMAP16XX |
-                          RATE_FIXED | ENABLE_REG_32BIT,
-        .enable_reg     = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
+        .flags          = RATE_FIXED | ENABLE_REG_32BIT,
+        .enable_reg     = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
         .enable_bit     = 8 /* UHOST_EN */,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct clk usb_dc_ck = {
         .name           = "usb_dc_ck",
+        .ops            = &clkops_generic,
         /* Direct from ULPD, no parent */
         .rate           = 48000000,
-        .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED,
-        .enable_reg     = (void __iomem *)SOFT_REQ_REG,
+        .flags          = RATE_FIXED,
+        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
         .enable_bit     = 4,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct clk mclk_1510 = {
         .name           = "mclk",
+        .ops            = &clkops_generic,
         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
         .rate           = 12000000,
-        .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
-        .enable_reg     = (void __iomem *)SOFT_REQ_REG,
-        .enable_bit     = 6,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
+        .flags          = RATE_FIXED,
+        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
+        .enable_bit     = 6,
 };
 
 static struct clk mclk_16xx = {
         .name           = "mclk",
+        .ops            = &clkops_generic,
         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
-        .flags          = CLOCK_IN_OMAP16XX,
-        .enable_reg     = (void __iomem *)COM_CLK_DIV_CTRL_SEL,
+        .enable_reg     = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
         .enable_bit     = COM_ULPD_PLL_CLK_REQ,
         .set_rate       = &omap1_set_ext_clk_rate,
         .round_rate     = &omap1_round_ext_clk_rate,
         .init           = &omap1_init_ext_clk,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct clk bclk_1510 = {
         .name           = "bclk",
+        .ops            = &clkops_generic,
         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
         .rate           = 12000000,
-        .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
+        .flags          = RATE_FIXED,
 };
 
 static struct clk bclk_16xx = {
         .name           = "bclk",
+        .ops            = &clkops_generic,
         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
-        .flags          = CLOCK_IN_OMAP16XX,
-        .enable_reg     = (void __iomem *)SWD_CLK_DIV_CTRL_SEL,
+        .enable_reg     = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
         .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
         .set_rate       = &omap1_set_ext_clk_rate,
         .round_rate     = &omap1_round_ext_clk_rate,
         .init           = &omap1_init_ext_clk,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct clk mmc1_ck = {
         .name           = "mmc_ck",
+        .ops            = &clkops_generic,
         /* Functional clock is direct from ULPD, interface clock is ARMPER */
         .parent         = &armper_ck.clk,
         .rate           = 48000000,
-        .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                          CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT |
-                          CLOCK_NO_IDLE_PARENT,
-        .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
+        .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
+        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
         .enable_bit     = 23,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct clk mmc2_ck = {
         .name           = "mmc_ck",
         .id             = 1,
+        .ops            = &clkops_generic,
         /* Functional clock is direct from ULPD, interface clock is ARMPER */
         .parent         = &armper_ck.clk,
         .rate           = 48000000,
-        .flags          = CLOCK_IN_OMAP16XX |
-                          RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
-        .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
+        .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
+        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
         .enable_bit     = 20,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct clk virtual_ck_mpu = {
         .name           = "mpu",
-        .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                          CLOCK_IN_OMAP310 | VIRTUAL_CLOCK | ALWAYS_ENABLED,
+        .ops            = &clkops_null,
         .parent         = &arm_ck, /* Is smarter alias for */
         .recalc         = &followparent_recalc,
         .set_rate       = &omap1_select_table_rate,
         .round_rate     = &omap1_round_to_table_rate,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
@@ -748,78 +651,19 @@ remains active during MPU idle whenever this is enabled */
 static struct clk i2c_fck = {
         .name           = "i2c_fck",
         .id             = 1,
-        .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
-                          VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT |
-                          ALWAYS_ENABLED,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_NO_IDLE_PARENT,
         .parent         = &armxor_ck.clk,
         .recalc         = &followparent_recalc,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
 };
 
 static struct clk i2c_ick = {
         .name           = "i2c_ick",
         .id             = 1,
-        .flags          = CLOCK_IN_OMAP16XX |
-                          VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT |
-                          ALWAYS_ENABLED,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_NO_IDLE_PARENT,
         .parent         = &armper_ck.clk,
         .recalc         = &followparent_recalc,
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
-};
-
-static struct clk * onchip_clks[] = {
-        /* non-ULPD clocks */
-        &ck_ref,
-        &ck_dpll1,
-        /* CK_GEN1 clocks */
-        &ck_dpll1out.clk,
-        &sossi_ck,
-        &arm_ck,
-        &armper_ck.clk,
-        &arm_gpio_ck,
-        &armxor_ck.clk,
-        &armtim_ck.clk,
-        &armwdt_ck.clk,
-        &arminth_ck1510,  &arminth_ck16xx,
-        /* CK_GEN2 clocks */
-        &dsp_ck,
-        &dspmmu_ck,
-        &dspper_ck,
-        &dspxor_ck,
-        &dsptim_ck,
-        /* CK_GEN3 clocks */
-        &tc_ck.clk,
-        &tipb_ck,
-        &l3_ocpi_ck,
-        &tc1_ck,
-        &tc2_ck,
-        &dma_ck,
-        &dma_lcdfree_ck,
-        &api_ck.clk,
-        &lb_ck.clk,
-        &rhea1_ck,
-        &rhea2_ck,
-        &lcd_ck_16xx,
-        &lcd_ck_1510.clk,
-        /* ULPD clocks */
-        &uart1_1510,
-        &uart1_16xx.clk,
-        &uart2_ck,
-        &uart3_1510,
-        &uart3_16xx.clk,
-        &usb_clko,
-        &usb_hhc_ck1510, &usb_hhc_ck16xx,
-        &usb_dc_ck,
-        &mclk_1510,  &mclk_16xx,
-        &bclk_1510,  &bclk_16xx,
-        &mmc1_ck,
-        &mmc2_ck,
-        /* Virtual clocks */
-        &virtual_ck_mpu,
-        &i2c_fck,
-        &i2c_ick,
 };
 
 #endif
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index ba5d7c08dc17..bbbaeb0abcd3 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -86,7 +86,7 @@ static struct resource mbox_resources[] = {
 };
 
 static struct platform_device mbox_device = {
-        .name           = "mailbox",
+        .name           = "omap1-mailbox",
         .id             = -1,
         .num_resources  = ARRAY_SIZE(mbox_resources),
         .resource       = mbox_resources,
diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c
index 89bb8756f450..4ef26faf083e 100644
--- a/arch/arm/mach-omap1/id.c
+++ b/arch/arm/mach-omap1/id.c
@@ -38,6 +38,7 @@ static struct omap_id omap_ids[] __initdata = {
         { .jtag_id = 0xb574, .die_rev = 0x2, .omap_id = 0x03310315, .type = 0x03100000},
         { .jtag_id = 0x355f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300100},
         { .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300300},
+        { .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320500, .type = 0x08500000},
         { .jtag_id = 0xb470, .die_rev = 0x0, .omap_id = 0x03310100, .type = 0x15100000},
         { .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x16100000},
         { .jtag_id = 0xb576, .die_rev = 0x2, .omap_id = 0x03320100, .type = 0x16110000},
@@ -77,7 +78,7 @@ static u16 __init omap_get_jtag_id(void)
         prod_id = omap_readl(OMAP_PRODUCTION_ID_1);
         omap_id = omap_readl(OMAP32_ID_1);
 
-        /* Check for unusable OMAP_PRODUCTION_ID_1 on 1611B/5912 and 730 */
+        /* Check for unusable OMAP_PRODUCTION_ID_1 on 1611B/5912 and 730/850 */
         if (((prod_id >> 20) == 0) || (prod_id == omap_id))
                 prod_id = 0;
         else
@@ -178,6 +179,7 @@ void __init omap_check_revision(void)
 
         switch (cpu_type) {
         case 0x07:
+        case 0x08:
                 omap_revision |= 0x07;
                 break;
         case 0x03:
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 4c3e582f3d3c..3afe540149f7 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -52,6 +52,22 @@ static struct map_desc omap730_io_desc[] __initdata = {
 };
 #endif
 
+#ifdef CONFIG_ARCH_OMAP850
+static struct map_desc omap850_io_desc[] __initdata = {
+        {
+                .virtual        = OMAP850_DSP_BASE,
+                .pfn            = __phys_to_pfn(OMAP850_DSP_START),
+                .length         = OMAP850_DSP_SIZE,
+                .type           = MT_DEVICE
+        }, {
+                .virtual        = OMAP850_DSPREG_BASE,
+                .pfn            = __phys_to_pfn(OMAP850_DSPREG_START),
+                .length         = OMAP850_DSPREG_SIZE,
+                .type           = MT_DEVICE
+        }
+};
+#endif
+
 #ifdef CONFIG_ARCH_OMAP15XX
 static struct map_desc omap1510_io_desc[] __initdata = {
         {
@@ -109,6 +125,13 @@ void __init omap1_map_common_io(void)
                 iotable_init(omap730_io_desc, ARRAY_SIZE(omap730_io_desc));
         }
 #endif
+
+#ifdef CONFIG_ARCH_OMAP850
+        if (cpu_is_omap850()) {
+                iotable_init(omap850_io_desc, ARRAY_SIZE(omap850_io_desc));
+        }
+#endif
+
 #ifdef CONFIG_ARCH_OMAP15XX
         if (cpu_is_omap15xx()) {
                 iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc));
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index 9ad5197075ff..de03c8448994 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -145,6 +145,14 @@ static struct omap_irq_bank omap730_irq_banks[] = {
 };
 #endif
 
+#ifdef CONFIG_ARCH_OMAP850
+static struct omap_irq_bank omap850_irq_banks[] = {
+        { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3f8e22f },
+        { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0xfdb9c1f2 },
+        { .base_reg = OMAP_IH2_BASE + 0x100,    .trigger_map = 0x800040f3 },
+};
+#endif
+
 #ifdef CONFIG_ARCH_OMAP15XX
 static struct omap_irq_bank omap1510_irq_banks[] = {
         { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3febfff },
@@ -184,6 +192,12 @@ void __init omap_init_irq(void)
                 irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
         }
 #endif
+#ifdef CONFIG_ARCH_OMAP850
+        if (cpu_is_omap850()) {
+                irq_banks = omap850_irq_banks;
+                irq_bank_count = ARRAY_SIZE(omap850_irq_banks);
+        }
+#endif
 #ifdef CONFIG_ARCH_OMAP15XX
         if (cpu_is_omap1510()) {
                 irq_banks = omap1510_irq_banks;
@@ -214,9 +228,8 @@ void __init omap_init_irq(void)
         irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET);
 
         /* Enable interrupts in global mask */
-        if (cpu_is_omap730()) {
+        if (cpu_is_omap7xx())
                 irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET);
-        }
 
         /* Install the interrupt handlers for each bank */
         for (i = 0; i < irq_bank_count; i++) {
@@ -236,6 +249,8 @@ void __init omap_init_irq(void)
 
         if (cpu_is_omap730())
                 omap_unmask_irq(INT_730_IH2_IRQ);
+        else if (cpu_is_omap850())
+                omap_unmask_irq(INT_850_IH2_IRQ);
         else if (cpu_is_omap15xx())
                 omap_unmask_irq(INT_1510_IH2_IRQ);
         else if (cpu_is_omap16xx())
diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c
index 59abbf331a96..0af4d6c85b47 100644
--- a/arch/arm/mach-omap1/mailbox.c
+++ b/arch/arm/mach-omap1/mailbox.c
@@ -1,7 +1,7 @@
 /*
  * Mailbox reservation modules for DSP
  *
- * Copyright (C) 2006 Nokia Corporation
+ * Copyright (C) 2006-2009 Nokia Corporation
  * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
  *
  * This file is subject to the terms and conditions of the GNU General Public
@@ -27,7 +27,7 @@
 #define MAILBOX_DSP2ARM1_Flag           0x1c
 #define MAILBOX_DSP2ARM2_Flag           0x20
 
-unsigned long mbox_base;
+static void __iomem *mbox_base;
 
 struct omap_mbox1_fifo {
         unsigned long cmd;
@@ -40,14 +40,14 @@ struct omap_mbox1_priv {
         struct omap_mbox1_fifo rx_fifo;
 };
 
-static inline int mbox_read_reg(unsigned int reg)
+static inline int mbox_read_reg(size_t ofs)
 {
-        return __raw_readw(mbox_base + reg);
+        return __raw_readw(mbox_base + ofs);
 }
 
-static inline void mbox_write_reg(unsigned int val, unsigned int reg)
+static inline void mbox_write_reg(u32 val, size_t ofs)
 {
-        __raw_writew(val, mbox_base + reg);
+        __raw_writew(val, mbox_base + ofs);
 }
 
 /* msg */
@@ -143,7 +143,7 @@ struct omap_mbox mbox_dsp_info = {
 };
 EXPORT_SYMBOL(mbox_dsp_info);
 
-static int __init omap1_mbox_probe(struct platform_device *pdev)
+static int __devinit omap1_mbox_probe(struct platform_device *pdev)
 {
         struct resource *res;
         int ret = 0;
@@ -170,12 +170,10 @@ static int __init omap1_mbox_probe(struct platform_device *pdev)
         }
         mbox_dsp_info.irq = res->start;
 
-        ret = omap_mbox_register(&mbox_dsp_info);
-
-        return ret;
+        return omap_mbox_register(&pdev->dev, &mbox_dsp_info);
 }
 
-static int omap1_mbox_remove(struct platform_device *pdev)
+static int __devexit omap1_mbox_remove(struct platform_device *pdev)
 {
         omap_mbox_unregister(&mbox_dsp_info);
 
@@ -184,9 +182,9 @@ static int omap1_mbox_remove(struct platform_device *pdev)
 
 static struct platform_driver omap1_mbox_driver = {
         .probe  = omap1_mbox_probe,
-        .remove = omap1_mbox_remove,
+        .remove = __devexit_p(omap1_mbox_remove),
         .driver = {
-                .name   = "mailbox",
+                .name   = "omap1-mailbox",
         },
 };
 
@@ -203,4 +201,7 @@ static void __exit omap1_mbox_exit(void)
 module_init(omap1_mbox_init);
 module_exit(omap1_mbox_exit);
 
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("omap mailbox: omap1 architecture specific functions");
+MODULE_AUTHOR("Hiroshi DOYU" <Hiroshi.DOYU@nokia.com>);
+MODULE_ALIAS("platform:omap1-mailbox");
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index 575ba31295cf..d040c3f1027f 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -28,9 +28,9 @@
 #define DPS_RSTCT2_PER_EN       (1 << 0)
 #define DSP_RSTCT2_WD_PER_EN    (1 << 1)
 
-#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
-const char *clk_names[] = { "dsp_ck", "api_ck", "dspxor_ck" };
-#endif
+static int dsp_use;
+static struct clk *api_clk;
+static struct clk *dsp_clk;
 
 static void omap1_mcbsp_request(unsigned int id)
 {
@@ -39,20 +39,40 @@ static void omap1_mcbsp_request(unsigned int id)
          * are DSP public peripherals.
          */
         if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
-                omap_dsp_request_mem();
-                /*
-                 * DSP external peripheral reset
-                 * FIXME: This should be moved to dsp code
-                 */
-                __raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN |
-                                DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2);
+                if (dsp_use++ == 0) {
+                        api_clk = clk_get(NULL, "api_clk");
+                        dsp_clk = clk_get(NULL, "dsp_clk");
+                        if (!IS_ERR(api_clk) && !IS_ERR(dsp_clk)) {
+                                clk_enable(api_clk);
+                                clk_enable(dsp_clk);
+
+                                omap_dsp_request_mem();
+                                /*
+                                 * DSP external peripheral reset
+                                 * FIXME: This should be moved to dsp code
+                                 */
+                                __raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN |
+                                                DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2);
+                        }
+                }
         }
 }
 
 static void omap1_mcbsp_free(unsigned int id)
 {
-        if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
-                omap_dsp_release_mem();
+        if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
+                if (--dsp_use == 0) {
+                        omap_dsp_release_mem();
+                        if (!IS_ERR(api_clk)) {
+                                clk_disable(api_clk);
+                                clk_put(api_clk);
+                        }
+                        if (!IS_ERR(dsp_clk)) {
+                                clk_disable(dsp_clk);
+                                clk_put(dsp_clk);
+                        }
+                }
+        }
 }
 
 static struct omap_mcbsp_ops omap1_mcbsp_ops = {
@@ -94,8 +114,6 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
                 .rx_irq         = INT_McBSP1RX,
                 .tx_irq         = INT_McBSP1TX,
                 .ops            = &omap1_mcbsp_ops,
-                .clk_names      = clk_names,
-                .num_clks       = 3,
         },
         {
                 .phys_base      = OMAP1510_MCBSP2_BASE,
@@ -112,8 +130,6 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
                 .rx_irq         = INT_McBSP3RX,
                 .tx_irq         = INT_McBSP3TX,
                 .ops            = &omap1_mcbsp_ops,
-                .clk_names      = clk_names,
-                .num_clks       = 3,
         },
 };
 #define OMAP15XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap15xx_mcbsp_pdata)
@@ -131,8 +147,6 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
                 .rx_irq         = INT_McBSP1RX,
                 .tx_irq         = INT_McBSP1TX,
                 .ops            = &omap1_mcbsp_ops,
-                .clk_names      = clk_names,
-                .num_clks       = 3,
         },
         {
                 .phys_base      = OMAP1610_MCBSP2_BASE,
@@ -149,8 +163,6 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
                 .rx_irq         = INT_McBSP3RX,
                 .tx_irq         = INT_McBSP3TX,
                 .ops            = &omap1_mcbsp_ops,
-                .clk_names      = clk_names,
-                .num_clks       = 3,
         },
 };
 #define OMAP16XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap16xx_mcbsp_pdata)
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index 062c905c2ba6..721e0d9d8b1d 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -58,6 +58,25 @@ MUX_CFG_730("W17_730_USB_VBUSI",   2,   29,    0,   28,   0, 0)
 #define OMAP730_PINS_SZ         0
 #endif  /* CONFIG_ARCH_OMAP730 */
 
+#ifdef CONFIG_ARCH_OMAP850
+struct pin_config __initdata_or_module omap850_pins[] = {
+MUX_CFG_850("E2_850_KBR0",        12,   21,    0,   20,   1, 0)
+MUX_CFG_850("J7_850_KBR1",        12,   25,    0,   24,   1, 0)
+MUX_CFG_850("E1_850_KBR2",        12,   29,    0,   28,   1, 0)
+MUX_CFG_850("F3_850_KBR3",        13,    1,    0,    0,   1, 0)
+MUX_CFG_850("D2_850_KBR4",        13,    5,    0,    4,   1, 0)
+MUX_CFG_850("C2_850_KBC0",        13,    9,    0,    8,   1, 0)
+MUX_CFG_850("D3_850_KBC1",        13,   13,    0,   12,   1, 0)
+MUX_CFG_850("E4_850_KBC2",        13,   17,    0,   16,   1, 0)
+MUX_CFG_850("F4_850_KBC3",        13,   21,    0,   20,   1, 0)
+MUX_CFG_850("E3_850_KBC4",        13,   25,    0,   24,   1, 0)
+
+MUX_CFG_850("AA17_850_USB_DM",     2,   21,    0,   20,   0, 0)
+MUX_CFG_850("W16_850_USB_PU_EN",   2,   25,    0,   24,   0, 0)
+MUX_CFG_850("W17_850_USB_VBUSI",   2,   29,    0,   28,   0, 0)
+};
+#endif
+
 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
 static struct pin_config __initdata_or_module omap1xxx_pins[] = {
 /*
@@ -419,6 +438,11 @@ int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
                         printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
                                cfg->pull_name, cfg->pull_reg, pull_orig, pull);
         }
+
+#ifdef CONFIG_ARCH_OMAP850
+        omap_mux_register(omap850_pins, ARRAY_SIZE(omap850_pins));
+#endif
+
 #endif
 
 #ifdef CONFIG_OMAP_MUX_ERRORS
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c
index 0002084e0655..842090b148f1 100644
--- a/arch/arm/mach-omap1/serial.c
+++ b/arch/arm/mach-omap1/serial.c
@@ -121,6 +121,13 @@ void __init omap_serial_init(void)
                 serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2;
         }
 
+        if (cpu_is_omap850()) {
+                serial_platform_data[0].regshift = 0;
+                serial_platform_data[1].regshift = 0;
+                serial_platform_data[0].irq = INT_850_UART_MODEM_1;
+                serial_platform_data[1].irq = INT_850_UART_MODEM_IRDA_2;
+        }
+
         if (cpu_is_omap15xx()) {
                 serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16;
                 serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16;
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 3754b79092ab..64ab386a65c7 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -58,4 +58,12 @@ config MACH_OVERO
 
 config MACH_OMAP3_PANDORA
         bool "OMAP3 Pandora"
-        depends on ARCH_OMAP3 && ARCH_OMAP34XX
\ No newline at end of file
+        depends on ARCH_OMAP3 && ARCH_OMAP34XX
+
+config MACH_OMAP_3430SDP
+        bool "OMAP 3430 SDP board"
+        depends on ARCH_OMAP3 && ARCH_OMAP34XX
+
+config MACH_NOKIA_RX51
+        bool "Nokia RX-51 board"
+        depends on ARCH_OMAP3 && ARCH_OMAP34XX
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index bbd12bc10fdc..a2c3fcc27a22 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,7 +3,7 @@
 #
 
 # Common support
-obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \
+obj-y := irq.o id.o io.o sdrc.o control.o prcm.o clock.o mux.o \
                 devices.o serial.o gpmc.o timer-gp.o powerdomain.o \
                 clockdomain.o
 
@@ -14,6 +14,10 @@ obj-$(CONFIG_ARCH_OMAP2420)		+= sram242x.o
 obj-$(CONFIG_ARCH_OMAP2430)             += sram243x.o
 obj-$(CONFIG_ARCH_OMAP3)                += sram34xx.o
 
+# SMS/SDRC
+obj-$(CONFIG_ARCH_OMAP2)                += sdrc2xxx.o
+# obj-$(CONFIG_ARCH_OMAP3)              += sdrc3xxx.o
+
 # Power Management
 ifeq ($(CONFIG_PM),y)
 obj-y                                   += pm.o
@@ -38,4 +42,12 @@ obj-$(CONFIG_MACH_OVERO)		+= board-overo.o \
                                            mmc-twl4030.o
 obj-$(CONFIG_MACH_OMAP3_PANDORA)        += board-omap3pandora.o \
                                            mmc-twl4030.o
+obj-$(CONFIG_MACH_OMAP_3430SDP)         += board-3430sdp.o \
+                                           mmc-twl4030.o
 
+obj-$(CONFIG_MACH_NOKIA_RX51)           += board-rx51.o \
+                                           board-rx51-peripherals.o \
+# Platform specific device init code
+ifeq ($(CONFIG_USB_MUSB_SOC),y)
+obj-y                                   += usb-musb.o
+endif
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 83fa37211d77..22143651037e 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -35,12 +35,16 @@
 #include <mach/board.h>
 #include <mach/common.h>
 #include <mach/gpmc.h>
+#include <mach/usb.h>
 
 #include "mmc-twl4030.h"
 
+#define SDP2430_CS0_BASE        0x04000000
 #define SDP2430_FLASH_CS        0
 #define SDP2430_SMC91X_CS       5
 
+#define SDP2430_ETHR_GPIO_IRQ           149
+
 static struct mtd_partition sdp2430_partitions[] = {
         /* bootloader (U-Boot, etc) in first sector */
         {
@@ -102,8 +106,8 @@ static struct resource sdp2430_smc91x_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ),
-                .end    = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ),
+                .start  = OMAP_GPIO_IRQ(SDP2430_ETHR_GPIO_IRQ),
+                .end    = OMAP_GPIO_IRQ(SDP2430_ETHR_GPIO_IRQ),
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
         },
 };
@@ -170,13 +174,13 @@ static inline void __init sdp2430_init_smc91x(void)
         sdp2430_smc91x_resources[0].end = cs_mem_base + 0x30f;
         udelay(100);
 
-        if (gpio_request(OMAP24XX_ETHR_GPIO_IRQ, "SMC91x irq") < 0) {
+        if (gpio_request(SDP2430_ETHR_GPIO_IRQ, "SMC91x irq") < 0) {
                 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
-                        OMAP24XX_ETHR_GPIO_IRQ);
+                        SDP2430_ETHR_GPIO_IRQ);
                 gpmc_cs_free(eth_cs);
                 goto out;
         }
-        gpio_direction_input(OMAP24XX_ETHR_GPIO_IRQ);
+        gpio_direction_input(SDP2430_ETHR_GPIO_IRQ);
 
 out:
         clk_disable(gpmc_fck);
@@ -185,7 +189,7 @@ out:
 
 static void __init omap_2430sdp_init_irq(void)
 {
-        omap2_init_common_hw();
+        omap2_init_common_hw(NULL);
         omap_init_irq();
         omap_gpio_init();
         sdp2430_init_smc91x();
@@ -251,6 +255,7 @@ static void __init omap_2430sdp_init(void)
         omap_board_config_size = ARRAY_SIZE(sdp2430_config);
         omap_serial_init();
         twl4030_mmc_init(mmc);
+        usb_musb_init();
 }
 
 static void __init omap_2430sdp_map_io(void)
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
new file mode 100644
index 000000000000..ed9274972122
--- /dev/null
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -0,0 +1,542 @@
+/*
+ * linux/arch/arm/mach-omap2/board-3430sdp.c
+ *
+ * Copyright (C) 2007 Texas Instruments
+ *
+ * Modified from mach-omap2/board-generic.c
+ *
+ * Initial code: Syed Mohammed Khasim
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/input.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/ads7846.h>
+#include <linux/i2c/twl4030.h>
+#include <linux/regulator/machine.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/mcspi.h>
+#include <mach/mux.h>
+#include <mach/board.h>
+#include <mach/usb.h>
+#include <mach/common.h>
+#include <mach/dma.h>
+#include <mach/gpmc.h>
+
+#include <mach/control.h>
+#include <mach/keypad.h>
+
+#include "mmc-twl4030.h"
+
+#define CONFIG_DISABLE_HFCLK 1
+
+#define SDP3430_ETHR_GPIO_IRQ_SDPV1     29
+#define SDP3430_ETHR_GPIO_IRQ_SDPV2     6
+#define SDP3430_SMC91X_CS               3
+
+#define SDP3430_TS_GPIO_IRQ_SDPV1       3
+#define SDP3430_TS_GPIO_IRQ_SDPV2       2
+
+#define ENABLE_VAUX3_DEDICATED  0x03
+#define ENABLE_VAUX3_DEV_GRP    0x20
+
+#define TWL4030_MSECURE_GPIO 22
+
+static struct resource sdp3430_smc91x_resources[] = {
+        [0] = {
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 0,
+                .end    = 0,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
+        },
+};
+
+static struct platform_device sdp3430_smc91x_device = {
+        .name           = "smc91x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(sdp3430_smc91x_resources),
+        .resource       = sdp3430_smc91x_resources,
+};
+
+static int sdp3430_keymap[] = {
+        KEY(0, 0, KEY_LEFT),
+        KEY(0, 1, KEY_RIGHT),
+        KEY(0, 2, KEY_A),
+        KEY(0, 3, KEY_B),
+        KEY(0, 4, KEY_C),
+        KEY(1, 0, KEY_DOWN),
+        KEY(1, 1, KEY_UP),
+        KEY(1, 2, KEY_E),
+        KEY(1, 3, KEY_F),
+        KEY(1, 4, KEY_G),
+        KEY(2, 0, KEY_ENTER),
+        KEY(2, 1, KEY_I),
+        KEY(2, 2, KEY_J),
+        KEY(2, 3, KEY_K),
+        KEY(2, 4, KEY_3),
+        KEY(3, 0, KEY_M),
+        KEY(3, 1, KEY_N),
+        KEY(3, 2, KEY_O),
+        KEY(3, 3, KEY_P),
+        KEY(3, 4, KEY_Q),
+        KEY(4, 0, KEY_R),
+        KEY(4, 1, KEY_4),
+        KEY(4, 2, KEY_T),
+        KEY(4, 3, KEY_U),
+        KEY(4, 4, KEY_D),
+        KEY(5, 0, KEY_V),
+        KEY(5, 1, KEY_W),
+        KEY(5, 2, KEY_L),
+        KEY(5, 3, KEY_S),
+        KEY(5, 4, KEY_H),
+        0
+};
+
+static struct twl4030_keypad_data sdp3430_kp_data = {
+        .rows           = 5,
+        .cols           = 6,
+        .keymap         = sdp3430_keymap,
+        .keymapsize     = ARRAY_SIZE(sdp3430_keymap),
+        .rep            = 1,
+};
+
+static int ts_gpio;     /* Needed for ads7846_get_pendown_state */
+
+/**
+ * @brief ads7846_dev_init : Requests & sets GPIO line for pen-irq
+ *
+ * @return - void. If request gpio fails then Flag KERN_ERR.
+ */
+static void ads7846_dev_init(void)
+{
+        if (gpio_request(ts_gpio, "ADS7846 pendown") < 0) {
+                printk(KERN_ERR "can't get ads746 pen down GPIO\n");
+                return;
+        }
+
+        gpio_direction_input(ts_gpio);
+
+        omap_set_gpio_debounce(ts_gpio, 1);
+        omap_set_gpio_debounce_time(ts_gpio, 0xa);
+}
+
+static int ads7846_get_pendown_state(void)
+{
+        return !gpio_get_value(ts_gpio);
+}
+
+static struct ads7846_platform_data tsc2046_config __initdata = {
+        .get_pendown_state      = ads7846_get_pendown_state,
+        .keep_vref_on           = 1,
+};
+
+
+static struct omap2_mcspi_device_config tsc2046_mcspi_config = {
+        .turbo_mode     = 0,
+        .single_channel = 1,    /* 0: slave, 1: master */
+};
+
+static struct spi_board_info sdp3430_spi_board_info[] __initdata = {
+        [0] = {
+                /*
+                 * TSC2046 operates at a max freqency of 2MHz, so
+                 * operate slightly below at 1.5MHz
+                 */
+                .modalias               = "ads7846",
+                .bus_num                = 1,
+                .chip_select            = 0,
+                .max_speed_hz           = 1500000,
+                .controller_data        = &tsc2046_mcspi_config,
+                .irq                    = 0,
+                .platform_data          = &tsc2046_config,
+        },
+};
+
+static struct platform_device sdp3430_lcd_device = {
+        .name           = "sdp2430_lcd",
+        .id             = -1,
+};
+
+static struct regulator_consumer_supply sdp3430_vdac_supply = {
+        .supply         = "vdac",
+        .dev            = &sdp3430_lcd_device.dev,
+};
+
+static struct regulator_consumer_supply sdp3430_vdvi_supply = {
+        .supply         = "vdvi",
+        .dev            = &sdp3430_lcd_device.dev,
+};
+
+static struct platform_device *sdp3430_devices[] __initdata = {
+        &sdp3430_smc91x_device,
+        &sdp3430_lcd_device,
+};
+
+static inline void __init sdp3430_init_smc91x(void)
+{
+        int eth_cs;
+        unsigned long cs_mem_base;
+        int eth_gpio = 0;
+
+        eth_cs = SDP3430_SMC91X_CS;
+
+        if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
+                printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
+                return;
+        }
+
+        sdp3430_smc91x_resources[0].start = cs_mem_base + 0x300;
+        sdp3430_smc91x_resources[0].end = cs_mem_base + 0x30f;
+        udelay(100);
+
+        if (omap_rev() > OMAP3430_REV_ES1_0)
+                eth_gpio = SDP3430_ETHR_GPIO_IRQ_SDPV2;
+        else
+                eth_gpio = SDP3430_ETHR_GPIO_IRQ_SDPV1;
+
+        sdp3430_smc91x_resources[1].start = gpio_to_irq(eth_gpio);
+
+        if (gpio_request(eth_gpio, "SMC91x irq") < 0) {
+                printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
+                        eth_gpio);
+                return;
+        }
+        gpio_direction_input(eth_gpio);
+}
+
+static void __init omap_3430sdp_init_irq(void)
+{
+        omap2_init_common_hw(NULL);
+        omap_init_irq();
+        omap_gpio_init();
+        sdp3430_init_smc91x();
+}
+
+static struct omap_uart_config sdp3430_uart_config __initdata = {
+        .enabled_uarts  = ((1 << 0) | (1 << 1) | (1 << 2)),
+};
+
+static struct omap_lcd_config sdp3430_lcd_config __initdata = {
+        .ctrl_name      = "internal",
+};
+
+static struct omap_board_config_kernel sdp3430_config[] __initdata = {
+        { OMAP_TAG_UART,        &sdp3430_uart_config },
+        { OMAP_TAG_LCD,         &sdp3430_lcd_config },
+};
+
+static int sdp3430_batt_table[] = {
+/* 0 C*/
+30800, 29500, 28300, 27100,
+26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
+17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
+11600, 11200, 10800, 10400, 10000, 9630,   9280,   8950,   8620,   8310,
+8020,   7730,   7460,   7200,   6950,   6710,   6470,   6250,   6040,   5830,
+5640,   5450,   5260,   5090,   4920,   4760,   4600,   4450,   4310,   4170,
+4040,   3910,   3790,   3670,   3550
+};
+
+static struct twl4030_bci_platform_data sdp3430_bci_data = {
+        .battery_tmp_tbl        = sdp3430_batt_table,
+        .tblsize                = ARRAY_SIZE(sdp3430_batt_table),
+};
+
+static struct twl4030_hsmmc_info mmc[] = {
+        {
+                .mmc            = 1,
+                /* 8 bits (default) requires S6.3 == ON,
+                 * so the SIM card isn't used; else 4 bits.
+                 */
+                .wires          = 8,
+                .gpio_wp        = 4,
+        },
+        {
+                .mmc            = 2,
+                .wires          = 8,
+                .gpio_wp        = 7,
+        },
+        {}      /* Terminator */
+};
+
+static struct regulator_consumer_supply sdp3430_vmmc1_supply = {
+        .supply                 = "vmmc",
+};
+
+static struct regulator_consumer_supply sdp3430_vsim_supply = {
+        .supply                 = "vmmc_aux",
+};
+
+static struct regulator_consumer_supply sdp3430_vmmc2_supply = {
+        .supply                 = "vmmc",
+};
+
+static int sdp3430_twl_gpio_setup(struct device *dev,
+                unsigned gpio, unsigned ngpio)
+{
+        /* gpio + 0 is "mmc0_cd" (input/IRQ),
+         * gpio + 1 is "mmc1_cd" (input/IRQ)
+         */
+        mmc[0].gpio_cd = gpio + 0;
+        mmc[1].gpio_cd = gpio + 1;
+        twl4030_mmc_init(mmc);
+
+        /* link regulators to MMC adapters ... we "know" the
+         * regulators will be set up only *after* we return.
+         */
+        sdp3430_vmmc1_supply.dev = mmc[0].dev;
+        sdp3430_vsim_supply.dev = mmc[0].dev;
+        sdp3430_vmmc2_supply.dev = mmc[1].dev;
+
+        /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
+        gpio_request(gpio + 7, "sub_lcd_en_bkl");
+        gpio_direction_output(gpio + 7, 0);
+
+        /* gpio + 15 is "sub_lcd_nRST" (output) */
+        gpio_request(gpio + 15, "sub_lcd_nRST");
+        gpio_direction_output(gpio + 15, 0);
+
+        return 0;
+}
+
+static struct twl4030_gpio_platform_data sdp3430_gpio_data = {
+        .gpio_base      = OMAP_MAX_GPIO_LINES,
+        .irq_base       = TWL4030_GPIO_IRQ_BASE,
+        .irq_end        = TWL4030_GPIO_IRQ_END,
+        .pulldowns      = BIT(2) | BIT(6) | BIT(8) | BIT(13)
+                                | BIT(16) | BIT(17),
+        .setup          = sdp3430_twl_gpio_setup,
+};
+
+static struct twl4030_usb_data sdp3430_usb_data = {
+        .usb_mode       = T2_USB_MODE_ULPI,
+};
+
+static struct twl4030_madc_platform_data sdp3430_madc_data = {
+        .irq_line       = 1,
+};
+
+/*
+ * Apply all the fixed voltages since most versions of U-Boot
+ * don't bother with that initialization.
+ */
+
+/* VAUX1 for mainboard (irda and sub-lcd) */
+static struct regulator_init_data sdp3430_vaux1 = {
+        .constraints = {
+                .min_uV                 = 2800000,
+                .max_uV                 = 2800000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+};
+
+/* VAUX2 for camera module */
+static struct regulator_init_data sdp3430_vaux2 = {
+        .constraints = {
+                .min_uV                 = 2800000,
+                .max_uV                 = 2800000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+};
+
+/* VAUX3 for LCD board */
+static struct regulator_init_data sdp3430_vaux3 = {
+        .constraints = {
+                .min_uV                 = 2800000,
+                .max_uV                 = 2800000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+};
+
+/* VAUX4 for OMAP VDD_CSI2 (camera) */
+static struct regulator_init_data sdp3430_vaux4 = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+};
+
+/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
+static struct regulator_init_data sdp3430_vmmc1 = {
+        .constraints = {
+                .min_uV                 = 1850000,
+                .max_uV                 = 3150000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &sdp3430_vmmc1_supply,
+};
+
+/* VMMC2 for MMC2 card */
+static struct regulator_init_data sdp3430_vmmc2 = {
+        .constraints = {
+                .min_uV                 = 1850000,
+                .max_uV                 = 1850000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &sdp3430_vmmc2_supply,
+};
+
+/* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
+static struct regulator_init_data sdp3430_vsim = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 3000000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &sdp3430_vsim_supply,
+};
+
+/* VDAC for DSS driving S-Video */
+static struct regulator_init_data sdp3430_vdac = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &sdp3430_vdac_supply,
+};
+
+/* VPLL2 for digital video outputs */
+static struct regulator_init_data sdp3430_vpll2 = {
+        .constraints = {
+                .name                   = "VDVI",
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &sdp3430_vdvi_supply,
+};
+
+static struct twl4030_platform_data sdp3430_twldata = {
+        .irq_base       = TWL4030_IRQ_BASE,
+        .irq_end        = TWL4030_IRQ_END,
+
+        /* platform_data for children goes here */
+        .bci            = &sdp3430_bci_data,
+        .gpio           = &sdp3430_gpio_data,
+        .madc           = &sdp3430_madc_data,
+        .keypad         = &sdp3430_kp_data,
+        .usb            = &sdp3430_usb_data,
+
+        .vaux1          = &sdp3430_vaux1,
+        .vaux2          = &sdp3430_vaux2,
+        .vaux3          = &sdp3430_vaux3,
+        .vaux4          = &sdp3430_vaux4,
+        .vmmc1          = &sdp3430_vmmc1,
+        .vmmc2          = &sdp3430_vmmc2,
+        .vsim           = &sdp3430_vsim,
+        .vdac           = &sdp3430_vdac,
+        .vpll2          = &sdp3430_vpll2,
+};
+
+static struct i2c_board_info __initdata sdp3430_i2c_boardinfo[] = {
+        {
+                I2C_BOARD_INFO("twl4030", 0x48),
+                .flags = I2C_CLIENT_WAKE,
+                .irq = INT_34XX_SYS_NIRQ,
+                .platform_data = &sdp3430_twldata,
+        },
+};
+
+static int __init omap3430_i2c_init(void)
+{
+        /* i2c1 for PMIC only */
+        omap_register_i2c_bus(1, 2600, sdp3430_i2c_boardinfo,
+                        ARRAY_SIZE(sdp3430_i2c_boardinfo));
+        /* i2c2 on camera connector (for sensor control) and optional isp1301 */
+        omap_register_i2c_bus(2, 400, NULL, 0);
+        /* i2c3 on display connector (for DVI, tfp410) */
+        omap_register_i2c_bus(3, 400, NULL, 0);
+        return 0;
+}
+
+static void __init omap_3430sdp_init(void)
+{
+        omap3430_i2c_init();
+        platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices));
+        omap_board_config = sdp3430_config;
+        omap_board_config_size = ARRAY_SIZE(sdp3430_config);
+        if (omap_rev() > OMAP3430_REV_ES1_0)
+                ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV2;
+        else
+                ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV1;
+        sdp3430_spi_board_info[0].irq = gpio_to_irq(ts_gpio);
+        spi_register_board_info(sdp3430_spi_board_info,
+                                ARRAY_SIZE(sdp3430_spi_board_info));
+        ads7846_dev_init();
+        omap_serial_init();
+        usb_musb_init();
+}
+
+static void __init omap_3430sdp_map_io(void)
+{
+        omap2_set_globals_343x();
+        omap2_map_common_io();
+}
+
+MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
+        /* Maintainer: Syed Khasim - Texas Instruments Inc */
+        .phys_io        = 0x48000000,
+        .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
+        .boot_params    = 0x80000100,
+        .map_io         = omap_3430sdp_map_io,
+        .init_irq       = omap_3430sdp_init_irq,
+        .init_machine   = omap_3430sdp_init,
+        .timer          = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 0a7b24ba1652..06dfba888b0c 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -51,6 +51,7 @@
 
 #define APOLLON_FLASH_CS        0
 #define APOLLON_ETH_CS          1
+#define APOLLON_ETHR_GPIO_IRQ   74
 
 static struct mtd_partition apollon_partitions[] = {
         {
@@ -249,7 +250,7 @@ out:
 
 static void __init omap_apollon_init_irq(void)
 {
-        omap2_init_common_hw();
+        omap2_init_common_hw(NULL);
         omap_init_irq();
         omap_gpio_init();
         apollon_init_smc91x();
@@ -272,7 +273,6 @@ static struct omap_lcd_config apollon_lcd_config __initdata = {
 
 static struct omap_board_config_kernel apollon_config[] = {
         { OMAP_TAG_UART,        &apollon_uart_config },
-        { OMAP_TAG_USB,         &apollon_usb_config },
         { OMAP_TAG_LCD,         &apollon_lcd_config },
 };
 
@@ -299,6 +299,7 @@ static void __init apollon_usb_init(void)
         omap_cfg_reg(P21_242X_GPIO12);
         gpio_request(12, "USB suspend");
         gpio_direction_output(12, 0);
+        omap_usb_init(&apollon_usb_config);
 }
 
 static void __init omap_apollon_init(void)
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 3b34c20d1df4..3492162a65c3 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -33,7 +33,7 @@
 
 static void __init omap_generic_init_irq(void)
 {
-        omap2_init_common_hw();
+        omap2_init_common_hw(NULL);
         omap_init_irq();
 }
 
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 5e9b14675b1e..a0267a9ab466 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -47,6 +47,8 @@
 #define H4_FLASH_CS     0
 #define H4_SMC91X_CS    1
 
+#define H4_ETHR_GPIO_IRQ                92
+
 static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 };
 static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 };
 
@@ -341,7 +343,7 @@ static inline void __init h4_init_debug(void)
         udelay(100);
 
         omap_cfg_reg(M15_24XX_GPIO92);
-        if (debug_card_init(cs_mem_base, OMAP24XX_ETHR_GPIO_IRQ) < 0)
+        if (debug_card_init(cs_mem_base, H4_ETHR_GPIO_IRQ) < 0)
                 gpmc_cs_free(eth_cs);
 
 out:
@@ -363,7 +365,7 @@ static void __init h4_init_flash(void)
 
 static void __init omap_h4_init_irq(void)
 {
-        omap2_init_common_hw();
+        omap2_init_common_hw(NULL);
         omap_init_irq();
         omap_gpio_init();
         h4_init_flash();
@@ -377,6 +379,39 @@ static struct omap_lcd_config h4_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
 
+static struct omap_usb_config h4_usb_config __initdata = {
+#ifdef  CONFIG_MACH_OMAP2_H4_USB1
+        /* NOTE:  usb1 could also be used with 3 wire signaling */
+        .pins[1]        = 4,
+#endif
+
+#ifdef  CONFIG_MACH_OMAP_H4_OTG
+        /* S1.10 ON -- USB OTG port
+         * usb0 switched to Mini-AB port and isp1301 transceiver;
+         * S2.POS3 = OFF, S2.POS4 = ON ... to allow battery charging
+         */
+        .otg            = 1,
+        .pins[0]        = 4,
+#ifdef  CONFIG_USB_GADGET_OMAP
+        /* use OTG cable, or standard A-to-MiniB */
+        .hmc_mode       = 0x14, /* 0:dev/otg 1:host 2:disable */
+#elif   defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+        /* use OTG cable, or NONSTANDARD (B-to-MiniB) */
+        .hmc_mode       = 0x11, /* 0:host 1:host 2:disable */
+#endif  /* XX */
+
+#else
+        /* S1.10 OFF -- usb "download port"
+         * usb0 switched to Mini-B port and isp1105 transceiver;
+         * S2.POS3 = ON, S2.POS4 = OFF ... to enable battery charging
+         */
+        .register_dev   = 1,
+        .pins[0]        = 3,
+/*      .hmc_mode       = 0x14,*/       /* 0:dev 1:host 2:disable */
+        .hmc_mode       = 0x00,         /* 0:dev|otg 1:disable 2:disable */
+#endif
+};
+
 static struct omap_board_config_kernel h4_config[] = {
         { OMAP_TAG_UART,        &h4_uart_config },
         { OMAP_TAG_LCD,         &h4_lcd_config },
@@ -428,6 +463,7 @@ static void __init omap_h4_init(void)
         platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
         omap_board_config = h4_config;
         omap_board_config_size = ARRAY_SIZE(h4_config);
+        omap_usb_init(&h4_usb_config);
         omap_serial_init();
 }
 
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 6031e179926b..e096f776f996 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -22,31 +22,34 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 #include <linux/i2c/twl4030.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <mach/board-ldp.h>
 #include <mach/mcspi.h>
 #include <mach/gpio.h>
 #include <mach/board.h>
 #include <mach/common.h>
 #include <mach/gpmc.h>
 
-#include <asm/io.h>
 #include <asm/delay.h>
 #include <mach/control.h>
+#include <mach/usb.h>
 
 #include "mmc-twl4030.h"
 
-#define SDP3430_SMC91X_CS       3
+#define LDP_SMC911X_CS          1
+#define LDP_SMC911X_GPIO        152
+#define DEBUG_BASE              0x08000000
+#define LDP_ETHR_START          DEBUG_BASE
 
 static struct resource ldp_smc911x_resources[] = {
         [0] = {
-                .start  = OMAP34XX_ETHR_START,
-                .end    = OMAP34XX_ETHR_START + SZ_4K,
+                .start  = LDP_ETHR_START,
+                .end    = LDP_ETHR_START + SZ_4K,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -98,7 +101,7 @@ static inline void __init ldp_init_smc911x(void)
 
 static void __init omap_ldp_init_irq(void)
 {
-        omap2_init_common_hw();
+        omap2_init_common_hw(NULL);
         omap_init_irq();
         omap_gpio_init();
         ldp_init_smc911x();
@@ -162,6 +165,7 @@ static void __init omap_ldp_init(void)
         omap_board_config_size = ARRAY_SIZE(ldp_config);
         omap_serial_init();
         twl4030_mmc_init(mmc);
+        usb_musb_init();
 }
 
 static void __init omap_ldp_map_io(void)
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index e39cd2c46cfa..744740ae1b9c 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -41,6 +41,7 @@
 #include <mach/gpmc.h>
 #include <mach/nand.h>
 #include <mach/mux.h>
+#include <mach/usb.h>
 
 #include "mmc-twl4030.h"
 
@@ -175,9 +176,6 @@ static int __init omap3_beagle_i2c_init(void)
 {
         omap_register_i2c_bus(1, 2600, beagle_i2c_boardinfo,
                         ARRAY_SIZE(beagle_i2c_boardinfo));
-#ifdef CONFIG_I2C2_OMAP_BEAGLE
-        omap_register_i2c_bus(2, 400, NULL, 0);
-#endif
         /* Bus 3 is attached to the DVI port where devices like the pico DLP
          * projector don't work reliably with 400kHz */
         omap_register_i2c_bus(3, 100, NULL, 0);
@@ -186,7 +184,7 @@ static int __init omap3_beagle_i2c_init(void)
 
 static void __init omap3_beagle_init_irq(void)
 {
-        omap2_init_common_hw();
+        omap2_init_common_hw(NULL);
         omap_init_irq();
         omap_gpio_init();
 }
@@ -316,6 +314,7 @@ static void __init omap3_beagle_init(void)
         /* REVISIT leave DVI powered down until it's needed ... */
         gpio_direction_output(170, true);
 
+        usb_musb_init();
         omap3beagle_flash_init();
 }
 
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index b3196107afdb..402f09c6cf10 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -34,6 +34,7 @@
 #include <mach/gpio.h>
 #include <mach/hardware.h>
 #include <mach/mcspi.h>
+#include <mach/usb.h>
 
 #include "mmc-twl4030.h"
 
@@ -53,6 +54,13 @@ static struct twl4030_hsmmc_info omap3pandora_mmc[] = {
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = 127,
                 .ext_clock      = 1,
+                .transceiver    = true,
+        },
+        {
+                .mmc            = 3,
+                .wires          = 4,
+                .gpio_cd        = -EINVAL,
+                .gpio_wp        = -EINVAL,
         },
         {}      /* Terminator */
 };
@@ -110,7 +118,7 @@ static int __init omap3pandora_i2c_init(void)
 
 static void __init omap3pandora_init_irq(void)
 {
-        omap2_init_common_hw();
+        omap2_init_common_hw(NULL);
         omap_init_irq();
         omap_gpio_init();
 }
@@ -193,6 +201,7 @@ static void __init omap3pandora_init(void)
         spi_register_board_info(omap3pandora_spi_board_info,
                         ARRAY_SIZE(omap3pandora_spi_board_info));
         omap3pandora_ads7846_init();
+        usb_musb_init();
 }
 
 static void __init omap3pandora_map_io(void)
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 82b3dc557c96..b3f6e9d81807 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -37,20 +37,85 @@
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
 
-#include <mach/board-overo.h>
 #include <mach/board.h>
 #include <mach/common.h>
 #include <mach/gpio.h>
 #include <mach/gpmc.h>
 #include <mach/hardware.h>
 #include <mach/nand.h>
+#include <mach/usb.h>
 
 #include "mmc-twl4030.h"
 
+#define OVERO_GPIO_BT_XGATE     15
+#define OVERO_GPIO_W2W_NRESET   16
+#define OVERO_GPIO_BT_NRESET    164
+#define OVERO_GPIO_USBH_CPEN    168
+#define OVERO_GPIO_USBH_NRESET  183
+
 #define NAND_BLOCK_SIZE SZ_128K
 #define GPMC_CS0_BASE  0x60
 #define GPMC_CS_SIZE   0x30
 
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
+        defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+
+#include <mach/mcspi.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/ads7846.h>
+
+static struct omap2_mcspi_device_config ads7846_mcspi_config = {
+        .turbo_mode     = 0,
+        .single_channel = 1,    /* 0: slave, 1: master */
+};
+
+static int ads7846_get_pendown_state(void)
+{
+        return !gpio_get_value(OVERO_GPIO_PENDOWN);
+}
+
+static struct ads7846_platform_data ads7846_config = {
+        .x_max                  = 0x0fff,
+        .y_max                  = 0x0fff,
+        .x_plate_ohms           = 180,
+        .pressure_max           = 255,
+        .debounce_max           = 10,
+        .debounce_tol           = 3,
+        .debounce_rep           = 1,
+        .get_pendown_state      = ads7846_get_pendown_state,
+        .keep_vref_on           = 1,
+};
+
+static struct spi_board_info overo_spi_board_info[] __initdata = {
+        {
+                .modalias               = "ads7846",
+                .bus_num                = 1,
+                .chip_select            = 0,
+                .max_speed_hz           = 1500000,
+                .controller_data        = &ads7846_mcspi_config,
+                .irq                    = OMAP_GPIO_IRQ(OVERO_GPIO_PENDOWN),
+                .platform_data          = &ads7846_config,
+        }
+};
+
+static void __init overo_ads7846_init(void)
+{
+        if ((gpio_request(OVERO_GPIO_PENDOWN, "ADS7846_PENDOWN") == 0) &&
+            (gpio_direction_input(OVERO_GPIO_PENDOWN) == 0)) {
+                gpio_export(OVERO_GPIO_PENDOWN, 0);
+        } else {
+                printk(KERN_ERR "could not obtain gpio for ADS7846_PENDOWN\n");
+                return;
+        }
+
+        spi_register_board_info(overo_spi_board_info,
+                        ARRAY_SIZE(overo_spi_board_info));
+}
+
+#else
+static inline void __init overo_ads7846_init(void) { return; }
+#endif
+
 static struct mtd_partition overo_nand_partitions[] = {
         {
                 .name           = "xloader",
@@ -174,7 +239,7 @@ static int __init overo_i2c_init(void)
 
 static void __init overo_init_irq(void)
 {
-        omap2_init_common_hw();
+        omap2_init_common_hw(NULL);
         omap_init_irq();
         omap_gpio_init();
 }
@@ -209,6 +274,7 @@ static struct twl4030_hsmmc_info mmc[] __initdata = {
                 .wires          = 4,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
+                .transceiver    = true,
         },
         {}      /* Terminator */
 };
@@ -222,6 +288,8 @@ static void __init overo_init(void)
         omap_serial_init();
         twl4030_mmc_init(mmc);
         overo_flash_init();
+        usb_musb_init();
+        overo_ads7846_init();
 
         if ((gpio_request(OVERO_GPIO_W2W_NRESET,
                           "OVERO_GPIO_W2W_NRESET") == 0) &&
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
new file mode 100644
index 000000000000..a7381729645c
--- /dev/null
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -0,0 +1,419 @@
+/*
+ * linux/arch/arm/mach-omap2/board-rx51-flash.c
+ *
+ * Copyright (C) 2008-2009 Nokia
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <linux/spi/spi.h>
+#include <linux/i2c.h>
+#include <linux/i2c/twl4030.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/regulator/machine.h>
+#include <linux/gpio.h>
+
+#include <mach/mcspi.h>
+#include <mach/mux.h>
+#include <mach/board.h>
+#include <mach/common.h>
+#include <mach/dma.h>
+#include <mach/gpmc.h>
+#include <mach/keypad.h>
+
+#include "mmc-twl4030.h"
+
+
+#define SMC91X_CS                       1
+#define SMC91X_GPIO_IRQ                 54
+#define SMC91X_GPIO_RESET               164
+#define SMC91X_GPIO_PWRDWN              86
+
+static struct resource rx51_smc91x_resources[] = {
+        [0] = {
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .flags          = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+        },
+};
+
+static struct platform_device rx51_smc91x_device = {
+        .name           = "smc91x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(rx51_smc91x_resources),
+        .resource       = rx51_smc91x_resources,
+};
+
+static int rx51_keymap[] = {
+        KEY(0, 0, KEY_Q),
+        KEY(0, 1, KEY_W),
+        KEY(0, 2, KEY_E),
+        KEY(0, 3, KEY_R),
+        KEY(0, 4, KEY_T),
+        KEY(0, 5, KEY_Y),
+        KEY(0, 6, KEY_U),
+        KEY(0, 7, KEY_I),
+        KEY(1, 0, KEY_O),
+        KEY(1, 1, KEY_D),
+        KEY(1, 2, KEY_DOT),
+        KEY(1, 3, KEY_V),
+        KEY(1, 4, KEY_DOWN),
+        KEY(2, 0, KEY_P),
+        KEY(2, 1, KEY_F),
+        KEY(2, 2, KEY_UP),
+        KEY(2, 3, KEY_B),
+        KEY(2, 4, KEY_RIGHT),
+        KEY(3, 0, KEY_COMMA),
+        KEY(3, 1, KEY_G),
+        KEY(3, 2, KEY_ENTER),
+        KEY(3, 3, KEY_N),
+        KEY(4, 0, KEY_BACKSPACE),
+        KEY(4, 1, KEY_H),
+        KEY(4, 3, KEY_M),
+        KEY(4, 4, KEY_LEFTCTRL),
+        KEY(5, 1, KEY_J),
+        KEY(5, 2, KEY_Z),
+        KEY(5, 3, KEY_SPACE),
+        KEY(5, 4, KEY_LEFTSHIFT),
+        KEY(6, 0, KEY_A),
+        KEY(6, 1, KEY_K),
+        KEY(6, 2, KEY_X),
+        KEY(6, 3, KEY_SPACE),
+        KEY(6, 4, KEY_FN),
+        KEY(7, 0, KEY_S),
+        KEY(7, 1, KEY_L),
+        KEY(7, 2, KEY_C),
+        KEY(7, 3, KEY_LEFT),
+        KEY(0xff, 0, KEY_F6),
+        KEY(0xff, 1, KEY_F7),
+        KEY(0xff, 2, KEY_F8),
+        KEY(0xff, 4, KEY_F9),
+        KEY(0xff, 5, KEY_F10),
+};
+
+static struct twl4030_keypad_data rx51_kp_data = {
+        .rows           = 8,
+        .cols           = 8,
+        .keymap         = rx51_keymap,
+        .keymapsize     = ARRAY_SIZE(rx51_keymap),
+        .rep            = 1,
+};
+
+static struct platform_device *rx51_peripherals_devices[] = {
+        &rx51_smc91x_device,
+};
+
+/*
+ * Timings are taken from smsc-lan91c96-ms.pdf
+ */
+static int smc91x_init_gpmc(int cs)
+{
+        struct gpmc_timings t;
+        const int t2_r = 45;            /* t2 in Figure 12.10 */
+        const int t2_w = 30;            /* t2 in Figure 12.11 */
+        const int t3 = 15;              /* t3 in Figure 12.10 */
+        const int t5_r = 0;             /* t5 in Figure 12.10 */
+        const int t6_r = 45;            /* t6 in Figure 12.10 */
+        const int t6_w = 0;             /* t6 in Figure 12.11 */
+        const int t7_w = 15;            /* t7 in Figure 12.11 */
+        const int t15 = 12;             /* t15 in Figure 12.2 */
+        const int t20 = 185;            /* t20 in Figure 12.2 */
+
+        memset(&t, 0, sizeof(t));
+
+        t.cs_on = t15;
+        t.cs_rd_off = t3 + t2_r + t5_r; /* Figure 12.10 */
+        t.cs_wr_off = t3 + t2_w + t6_w; /* Figure 12.11 */
+        t.adv_on = t3;                  /* Figure 12.10 */
+        t.adv_rd_off = t3 + t2_r;       /* Figure 12.10 */
+        t.adv_wr_off = t3 + t2_w;       /* Figure 12.11 */
+        t.oe_off = t3 + t2_r + t5_r;    /* Figure 12.10 */
+        t.oe_on = t.oe_off - t6_r;      /* Figure 12.10 */
+        t.we_off = t3 + t2_w + t6_w;    /* Figure 12.11 */
+        t.we_on = t.we_off - t7_w;      /* Figure 12.11 */
+        t.rd_cycle = t20;               /* Figure 12.2 */
+        t.wr_cycle = t20;               /* Figure 12.4 */
+        t.access = t3 + t2_r + t5_r;    /* Figure 12.10 */
+        t.wr_access = t3 + t2_w + t6_w; /* Figure 12.11 */
+
+        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, GPMC_CONFIG1_DEVICESIZE_16);
+
+        return gpmc_cs_set_timings(cs, &t);
+}
+
+static void __init rx51_init_smc91x(void)
+{
+        unsigned long cs_mem_base;
+        int ret;
+
+        omap_cfg_reg(U8_34XX_GPIO54_DOWN);
+        omap_cfg_reg(G25_34XX_GPIO86_OUT);
+        omap_cfg_reg(H19_34XX_GPIO164_OUT);
+
+        if (gpmc_cs_request(SMC91X_CS, SZ_16M, &cs_mem_base) < 0) {
+                printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
+                return;
+        }
+
+        rx51_smc91x_resources[0].start = cs_mem_base + 0x300;
+        rx51_smc91x_resources[0].end = cs_mem_base + 0x30f;
+
+        smc91x_init_gpmc(SMC91X_CS);
+
+        if (gpio_request(SMC91X_GPIO_IRQ, "SMC91X irq") < 0)
+                goto free1;
+
+        gpio_direction_input(SMC91X_GPIO_IRQ);
+        rx51_smc91x_resources[1].start = gpio_to_irq(SMC91X_GPIO_IRQ);
+
+        ret = gpio_request(SMC91X_GPIO_PWRDWN, "SMC91X powerdown");
+        if (ret)
+                goto free2;
+        gpio_direction_output(SMC91X_GPIO_PWRDWN, 0);
+
+        ret = gpio_request(SMC91X_GPIO_RESET, "SMC91X reset");
+        if (ret)
+                goto free3;
+        gpio_direction_output(SMC91X_GPIO_RESET, 0);
+        gpio_set_value(SMC91X_GPIO_RESET, 1);
+        msleep(100);
+        gpio_set_value(SMC91X_GPIO_RESET, 0);
+
+        return;
+
+free3:
+        gpio_free(SMC91X_GPIO_PWRDWN);
+free2:
+        gpio_free(SMC91X_GPIO_IRQ);
+free1:
+        gpmc_cs_free(SMC91X_CS);
+
+        printk(KERN_ERR "Could not initialize smc91x\n");
+}
+
+static struct twl4030_madc_platform_data rx51_madc_data = {
+        .irq_line               = 1,
+};
+
+static struct twl4030_hsmmc_info mmc[] = {
+        {
+                .name           = "external",
+                .mmc            = 1,
+                .wires          = 4,
+                .cover_only     = true,
+                .gpio_cd        = 160,
+                .gpio_wp        = -EINVAL,
+        },
+        {
+                .name           = "internal",
+                .mmc            = 2,
+                .wires          = 8,
+                .gpio_cd        = -EINVAL,
+                .gpio_wp        = -EINVAL,
+        },
+        {}      /* Terminator */
+};
+
+static struct regulator_consumer_supply rx51_vmmc1_supply = {
+        .supply                 = "vmmc",
+};
+
+static struct regulator_consumer_supply rx51_vmmc2_supply = {
+        .supply                 = "vmmc",
+};
+
+static struct regulator_consumer_supply rx51_vsim_supply = {
+        .supply                 = "vmmc_aux",
+};
+
+static struct regulator_init_data rx51_vaux1 = {
+        .constraints = {
+                .name                   = "V28",
+                .min_uV                 = 2800000,
+                .max_uV                 = 2800000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+};
+
+static struct regulator_init_data rx51_vaux2 = {
+        .constraints = {
+                .name                   = "VCSI",
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+};
+
+/* VAUX3 - adds more power to VIO_18 rail */
+static struct regulator_init_data rx51_vaux3 = {
+        .constraints = {
+                .name                   = "VCAM_DIG_18",
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+};
+
+static struct regulator_init_data rx51_vaux4 = {
+        .constraints = {
+                .name                   = "VCAM_ANA_28",
+                .min_uV                 = 2800000,
+                .max_uV                 = 2800000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+};
+
+static struct regulator_init_data rx51_vmmc1 = {
+        .constraints = {
+                .min_uV                 = 1850000,
+                .max_uV                 = 3150000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &rx51_vmmc1_supply,
+};
+
+static struct regulator_init_data rx51_vmmc2 = {
+        .constraints = {
+                .name                   = "VMMC2_30",
+                .min_uV                 = 1850000,
+                .max_uV                 = 3150000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &rx51_vmmc2_supply,
+};
+
+static struct regulator_init_data rx51_vsim = {
+        .constraints = {
+                .name                   = "VMMC2_IO_18",
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &rx51_vsim_supply,
+};
+
+static struct regulator_init_data rx51_vdac = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+};
+
+static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n)
+{
+        /* FIXME this gpio setup is just a placeholder for now */
+        gpio_request(gpio + 6, "backlight_pwm");
+        gpio_direction_output(gpio + 6, 0);
+        gpio_request(gpio + 7, "speaker_en");
+        gpio_direction_output(gpio + 7, 1);
+
+        /* set up MMC adapters, linking their regulators to them */
+        twl4030_mmc_init(mmc);
+        rx51_vmmc1_supply.dev = mmc[0].dev;
+        rx51_vmmc2_supply.dev = mmc[1].dev;
+        rx51_vsim_supply.dev = mmc[1].dev;
+
+        return 0;
+}
+
+static struct twl4030_gpio_platform_data rx51_gpio_data = {
+        .gpio_base              = OMAP_MAX_GPIO_LINES,
+        .irq_base               = TWL4030_GPIO_IRQ_BASE,
+        .irq_end                = TWL4030_GPIO_IRQ_END,
+        .pulldowns              = BIT(0) | BIT(1) | BIT(2) | BIT(3)
+                                | BIT(4) | BIT(5)
+                                | BIT(8) | BIT(9) | BIT(10) | BIT(11)
+                                | BIT(12) | BIT(13) | BIT(14) | BIT(15)
+                                | BIT(16) | BIT(17) ,
+        .setup                  = rx51_twlgpio_setup,
+};
+
+static struct twl4030_platform_data rx51_twldata = {
+        .irq_base               = TWL4030_IRQ_BASE,
+        .irq_end                = TWL4030_IRQ_END,
+
+        /* platform_data for children goes here */
+        .gpio                   = &rx51_gpio_data,
+        .keypad                 = &rx51_kp_data,
+        .madc                   = &rx51_madc_data,
+
+        .vaux1                  = &rx51_vaux1,
+        .vaux2                  = &rx51_vaux2,
+        .vaux3                  = &rx51_vaux3,
+        .vaux4                  = &rx51_vaux4,
+        .vmmc1                  = &rx51_vmmc1,
+        .vmmc2                  = &rx51_vmmc2,
+        .vsim                   = &rx51_vsim,
+        .vdac                   = &rx51_vdac,
+};
+
+static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = {
+        {
+                I2C_BOARD_INFO("twl5030", 0x48),
+                .flags = I2C_CLIENT_WAKE,
+                .irq = INT_34XX_SYS_NIRQ,
+                .platform_data = &rx51_twldata,
+        },
+};
+
+static int __init rx51_i2c_init(void)
+{
+        omap_register_i2c_bus(1, 2600, rx51_peripherals_i2c_board_info_1,
+                        ARRAY_SIZE(rx51_peripherals_i2c_board_info_1));
+        omap_register_i2c_bus(2, 100, NULL, 0);
+        omap_register_i2c_bus(3, 400, NULL, 0);
+        return 0;
+}
+
+
+void __init rx51_peripherals_init(void)
+{
+        platform_add_devices(rx51_peripherals_devices,
+                                ARRAY_SIZE(rx51_peripherals_devices));
+        rx51_i2c_init();
+        rx51_init_smc91x();
+}
+
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
new file mode 100644
index 000000000000..3a0daac6c839
--- /dev/null
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -0,0 +1,96 @@
+/*
+ * linux/arch/arm/mach-omap2/board-rx51.c
+ *
+ * Copyright (C) 2007, 2008 Nokia
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/mcspi.h>
+#include <mach/mux.h>
+#include <mach/board.h>
+#include <mach/common.h>
+#include <mach/keypad.h>
+#include <mach/dma.h>
+#include <mach/gpmc.h>
+#include <mach/usb.h>
+
+static struct omap_uart_config rx51_uart_config = {
+        .enabled_uarts  = ((1 << 0) | (1 << 1) | (1 << 2)),
+};
+
+static struct omap_lcd_config rx51_lcd_config = {
+        .ctrl_name      = "internal",
+};
+
+static struct omap_fbmem_config rx51_fbmem0_config = {
+        .size = 752 * 1024,
+};
+
+static struct omap_fbmem_config rx51_fbmem1_config = {
+        .size = 752 * 1024,
+};
+
+static struct omap_fbmem_config rx51_fbmem2_config = {
+        .size = 752 * 1024,
+};
+
+static struct omap_board_config_kernel rx51_config[] = {
+        { OMAP_TAG_UART,        &rx51_uart_config },
+        { OMAP_TAG_FBMEM,       &rx51_fbmem0_config },
+        { OMAP_TAG_FBMEM,       &rx51_fbmem1_config },
+        { OMAP_TAG_FBMEM,       &rx51_fbmem2_config },
+        { OMAP_TAG_LCD,         &rx51_lcd_config },
+};
+
+static void __init rx51_init_irq(void)
+{
+        omap2_init_common_hw(NULL);
+        omap_init_irq();
+        omap_gpio_init();
+}
+
+extern void __init rx51_peripherals_init(void);
+
+static void __init rx51_init(void)
+{
+        omap_board_config = rx51_config;
+        omap_board_config_size = ARRAY_SIZE(rx51_config);
+        omap_serial_init();
+        usb_musb_init();
+        rx51_peripherals_init();
+}
+
+static void __init rx51_map_io(void)
+{
+        omap2_set_globals_343x();
+        omap2_map_common_io();
+}
+
+MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
+        /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */
+        .phys_io        = 0x48000000,
+        .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
+        .boot_params    = 0x80000100,
+        .map_io         = rx51_map_io,
+        .init_irq       = rx51_init_irq,
+        .init_machine   = rx51_init,
+        .timer          = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ce4d46a4a838..4247a1534411 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -26,11 +26,10 @@
 
 #include <mach/clock.h>
 #include <mach/clockdomain.h>
-#include <mach/sram.h>
 #include <mach/cpu.h>
 #include <asm/div64.h>
 
-#include "memory.h"
+#include <mach/sdrc.h>
 #include "sdrc.h"
 #include "clock.h"
 #include "prm.h"
@@ -46,7 +45,7 @@
 #define DPLL_MIN_DIVIDER                1
 
 /* Possible error results from _dpll_test_mult */
-#define DPLL_MULT_UNDERFLOW             (1 << 0)
+#define DPLL_MULT_UNDERFLOW             -1
 
 /*
  * Scale factor to mitigate roundoff errors in DPLL rate rounding.
@@ -59,6 +58,16 @@
 #define DPLL_ROUNDING_VAL               ((DPLL_SCALE_BASE / 2) * \
                                          (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
 
+/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
+#define DPLL_FINT_BAND1_MIN             750000
+#define DPLL_FINT_BAND1_MAX             2100000
+#define DPLL_FINT_BAND2_MIN             7500000
+#define DPLL_FINT_BAND2_MAX             21000000
+
+/* _dpll_test_fint() return codes */
+#define DPLL_FINT_UNDERFLOW             -1
+#define DPLL_FINT_INVALID               -2
+
 u8 cpu_mask;
 
 /*-------------------------------------------------------------------------
@@ -66,6 +75,74 @@ u8 cpu_mask;
  *-------------------------------------------------------------------------*/
 
 /**
+ * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware
+ * @clk: struct clk *
+ *
+ * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes
+ * don't take effect until the VALID_CONFIG bit is written, write the
+ * VALID_CONFIG bit and wait for the write to complete.  No return value.
+ */
+static void _omap2xxx_clk_commit(struct clk *clk)
+{
+        if (!cpu_is_omap24xx())
+                return;
+
+        if (!(clk->flags & DELAYED_APP))
+                return;
+
+        prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD,
+                OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
+        /* OCP barrier */
+        prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
+}
+
+/*
+ * _dpll_test_fint - test whether an Fint value is valid for the DPLL
+ * @clk: DPLL struct clk to test
+ * @n: divider value (N) to test
+ *
+ * Tests whether a particular divider @n will result in a valid DPLL
+ * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
+ * Correction".  Returns 0 if OK, -1 if the enclosing loop can terminate
+ * (assuming that it is counting N upwards), or -2 if the enclosing loop
+ * should skip to the next iteration (again assuming N is increasing).
+ */
+static int _dpll_test_fint(struct clk *clk, u8 n)
+{
+        struct dpll_data *dd;
+        long fint;
+        int ret = 0;
+
+        dd = clk->dpll_data;
+
+        /* DPLL divider must result in a valid jitter correction val */
+        fint = clk->parent->rate / (n + 1);
+        if (fint < DPLL_FINT_BAND1_MIN) {
+
+                pr_debug("rejecting n=%d due to Fint failure, "
+                         "lowering max_divider\n", n);
+                dd->max_divider = n;
+                ret = DPLL_FINT_UNDERFLOW;
+
+        } else if (fint > DPLL_FINT_BAND1_MAX &&
+                   fint < DPLL_FINT_BAND2_MIN) {
+
+                pr_debug("rejecting n=%d due to Fint failure\n", n);
+                ret = DPLL_FINT_INVALID;
+
+        } else if (fint > DPLL_FINT_BAND2_MAX) {
+
+                pr_debug("rejecting n=%d due to Fint failure, "
+                         "boosting min_divider\n", n);
+                dd->min_divider = n;
+                ret = DPLL_FINT_INVALID;
+
+        }
+
+        return ret;
+}
+
+/**
  * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
  * @clk: OMAP clock struct ptr to use
  *
@@ -120,7 +197,7 @@ void omap2_init_clksel_parent(struct clk *clk)
                                                  clk->name, clks->parent->name,
                                                  ((clk->parent) ?
                                                   clk->parent->name : "NULL"));
-                                        clk->parent = clks->parent;
+                                        clk_reparent(clk, clks->parent);
                                 };
                                 found = 1;
                         }
@@ -134,25 +211,52 @@ void omap2_init_clksel_parent(struct clk *clk)
         return;
 }
 
-/* Returns the DPLL rate */
+/**
+ * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
+ * @clk: struct clk * of a DPLL
+ *
+ * DPLLs can be locked or bypassed - basically, enabled or disabled.
+ * When locked, the DPLL output depends on the M and N values.  When
+ * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
+ * or sys_clk.  Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
+ * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
+ * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
+ * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
+ * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
+ * if the clock @clk is not a DPLL.
+ */
 u32 omap2_get_dpll_rate(struct clk *clk)
 {
         long long dpll_clk;
-        u32 dpll_mult, dpll_div, dpll;
+        u32 dpll_mult, dpll_div, v;
         struct dpll_data *dd;
 
         dd = clk->dpll_data;
-        /* REVISIT: What do we return on error? */
         if (!dd)
                 return 0;
 
-        dpll = __raw_readl(dd->mult_div1_reg);
-        dpll_mult = dpll & dd->mult_mask;
+        /* Return bypass rate if DPLL is bypassed */
+        v = __raw_readl(dd->control_reg);
+        v &= dd->enable_mask;
+        v >>= __ffs(dd->enable_mask);
+
+        if (cpu_is_omap24xx()) {
+                if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
+                    v == OMAP2XXX_EN_DPLL_FRBYPASS)
+                        return dd->clk_bypass->rate;
+        } else if (cpu_is_omap34xx()) {
+                if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
+                    v == OMAP3XXX_EN_DPLL_FRBYPASS)
+                        return dd->clk_bypass->rate;
+        }
+
+        v = __raw_readl(dd->mult_div1_reg);
+        dpll_mult = v & dd->mult_mask;
         dpll_mult >>= __ffs(dd->mult_mask);
-        dpll_div = dpll & dd->div1_mask;
+        dpll_div = v & dd->div1_mask;
         dpll_div >>= __ffs(dd->div1_mask);
 
-        dpll_clk = (long long)clk->parent->rate * dpll_mult;
+        dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
         do_div(dpll_clk, dpll_div + 1);
 
         return dpll_clk;
@@ -162,14 +266,11 @@ u32 omap2_get_dpll_rate(struct clk *clk)
  * Used for clocks that have the same value as the parent clock,
  * divided by some factor
  */
-void omap2_fixed_divisor_recalc(struct clk *clk)
+unsigned long omap2_fixed_divisor_recalc(struct clk *clk)
 {
         WARN_ON(!clk->fixed_div);
 
-        clk->rate = clk->parent->rate / clk->fixed_div;
-
-        if (clk->flags & RATE_PROPAGATES)
-                propagate_rate(clk);
+        return clk->parent->rate / clk->fixed_div;
 }
 
 /**
@@ -190,11 +291,10 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
          * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
          * 34xx reverses this, just to keep us on our toes
          */
-        if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) {
+        if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
                 ena = mask;
-        } else if (cpu_mask & RATE_IN_343X) {
+        else if (cpu_mask & RATE_IN_343X)
                 ena = 0;
-        }
 
         /* Wait for lock */
         while (((__raw_readl(reg) & mask) != ena) &&
@@ -228,31 +328,12 @@ static void omap2_clk_wait_ready(struct clk *clk)
          * it and pull it into struct clk itself somehow.
          */
         reg = clk->enable_reg;
-        if ((((u32)reg & 0xff) >= CM_FCLKEN1) &&
-            (((u32)reg & 0xff) <= OMAP24XX_CM_FCLKEN2))
-                other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
-        else if ((((u32)reg & 0xff) >= CM_ICLKEN1) &&
-                 (((u32)reg & 0xff) <= OMAP24XX_CM_ICLKEN4))
-                other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
-        else
-                return;
 
-        /* REVISIT: What are the appropriate exclusions for 34XX? */
-        /* No check for DSS or cam clocks */
-        if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
-                if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
-                    clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
-                    clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
-                        return;
-        }
-
-        /* REVISIT: What are the appropriate exclusions for 34XX? */
-        /* OMAP3: ignore DSS-mod clocks */
-        if (cpu_is_omap34xx() &&
-            (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
-             ((((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(CORE_MOD, 0)) &&
-             clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
-                return;
+        /*
+         * Convert CM_ICLKEN* <-> CM_FCLKEN*.  This conversion assumes
+         * it's just a matter of XORing the bits.
+         */
+        other_reg = (void __iomem *)((u32)reg ^ (CM_FCLKEN ^ CM_ICLKEN));
 
         /* Check if both functional and interface clocks
          * are running. */
@@ -264,18 +345,9 @@ static void omap2_clk_wait_ready(struct clk *clk)
         omap2_wait_clock_ready(st_reg, bit, clk->name);
 }
 
-/* Enables clock without considering parent dependencies or use count
- * REVISIT: Maybe change this to use clk->enable like on omap1?
- */
-int _omap2_clk_enable(struct clk *clk)
+static int omap2_dflt_clk_enable(struct clk *clk)
 {
-        u32 regval32;
-
-        if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
-                return 0;
-
-        if (clk->enable)
-                return clk->enable(clk);
+        u32 v;
 
         if (unlikely(clk->enable_reg == NULL)) {
                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
@@ -283,33 +355,38 @@ int _omap2_clk_enable(struct clk *clk)
                 return 0; /* REVISIT: -EINVAL */
         }
 
-        regval32 = __raw_readl(clk->enable_reg);
+        v = __raw_readl(clk->enable_reg);
         if (clk->flags & INVERT_ENABLE)
-                regval32 &= ~(1 << clk->enable_bit);
+                v &= ~(1 << clk->enable_bit);
         else
-                regval32 |= (1 << clk->enable_bit);
-        __raw_writel(regval32, clk->enable_reg);
-        wmb();
-
-        omap2_clk_wait_ready(clk);
+                v |= (1 << clk->enable_bit);
+        __raw_writel(v, clk->enable_reg);
+        v = __raw_readl(clk->enable_reg); /* OCP barrier */
 
         return 0;
 }
 
-/* Disables clock without considering parent dependencies or use count */
-void _omap2_clk_disable(struct clk *clk)
+static int omap2_dflt_clk_enable_wait(struct clk *clk)
 {
-        u32 regval32;
-
-        if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
-                return;
+        int ret;
 
-        if (clk->disable) {
-                clk->disable(clk);
-                return;
+        if (!clk->enable_reg) {
+                printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
+                       clk->name);
+                return 0; /* REVISIT: -EINVAL */
         }
 
-        if (clk->enable_reg == NULL) {
+        ret = omap2_dflt_clk_enable(clk);
+        if (ret == 0)
+                omap2_clk_wait_ready(clk);
+        return ret;
+}
+
+static void omap2_dflt_clk_disable(struct clk *clk)
+{
+        u32 v;
+
+        if (!clk->enable_reg) {
                 /*
                  * 'Independent' here refers to a clock which is not
                  * controlled by its parent.
@@ -319,20 +396,44 @@ void _omap2_clk_disable(struct clk *clk)
                 return;
         }
 
-        regval32 = __raw_readl(clk->enable_reg);
+        v = __raw_readl(clk->enable_reg);
         if (clk->flags & INVERT_ENABLE)
-                regval32 |= (1 << clk->enable_bit);
+                v |= (1 << clk->enable_bit);
         else
-                regval32 &= ~(1 << clk->enable_bit);
-        __raw_writel(regval32, clk->enable_reg);
-        wmb();
+                v &= ~(1 << clk->enable_bit);
+        __raw_writel(v, clk->enable_reg);
+        /* No OCP barrier needed here since it is a disable operation */
+}
+
+const struct clkops clkops_omap2_dflt_wait = {
+        .enable         = omap2_dflt_clk_enable_wait,
+        .disable        = omap2_dflt_clk_disable,
+};
+
+const struct clkops clkops_omap2_dflt = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+};
+
+/* Enables clock without considering parent dependencies or use count
+ * REVISIT: Maybe change this to use clk->enable like on omap1?
+ */
+static int _omap2_clk_enable(struct clk *clk)
+{
+        return clk->ops->enable(clk);
+}
+
+/* Disables clock without considering parent dependencies or use count */
+static void _omap2_clk_disable(struct clk *clk)
+{
+        clk->ops->disable(clk);
 }
 
 void omap2_clk_disable(struct clk *clk)
 {
         if (clk->usecount > 0 && !(--clk->usecount)) {
                 _omap2_clk_disable(clk);
-                if (likely((u32)clk->parent))
+                if (clk->parent)
                         omap2_clk_disable(clk->parent);
                 if (clk->clkdm)
                         omap2_clkdm_clk_disable(clk->clkdm, clk);
@@ -345,30 +446,29 @@ int omap2_clk_enable(struct clk *clk)
         int ret = 0;
 
         if (clk->usecount++ == 0) {
-                if (likely((u32)clk->parent))
-                        ret = omap2_clk_enable(clk->parent);
-
-                if (unlikely(ret != 0)) {
-                        clk->usecount--;
-                        return ret;
-                }
-
                 if (clk->clkdm)
                         omap2_clkdm_clk_enable(clk->clkdm, clk);
 
-                ret = _omap2_clk_enable(clk);
-
-                if (unlikely(ret != 0)) {
-                        if (clk->clkdm)
-                                omap2_clkdm_clk_disable(clk->clkdm, clk);
+                if (clk->parent) {
+                        ret = omap2_clk_enable(clk->parent);
+                        if (ret)
+                                goto err;
+                }
 
-                        if (clk->parent) {
+                ret = _omap2_clk_enable(clk);
+                if (ret) {
+                        if (clk->parent)
                                 omap2_clk_disable(clk->parent);
-                                clk->usecount--;
-                        }
+
+                        goto err;
                 }
         }
+        return ret;
 
+err:
+        if (clk->clkdm)
+                omap2_clkdm_clk_disable(clk->clkdm, clk);
+        clk->usecount--;
         return ret;
 }
 
@@ -376,24 +476,22 @@ int omap2_clk_enable(struct clk *clk)
  * Used for clocks that are part of CLKSEL_xyz governed clocks.
  * REVISIT: Maybe change to use clk->enable() functions like on omap1?
  */
-void omap2_clksel_recalc(struct clk *clk)
+unsigned long omap2_clksel_recalc(struct clk *clk)
 {
+        unsigned long rate;
         u32 div = 0;
 
         pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
 
         div = omap2_clksel_get_divisor(clk);
         if (div == 0)
-                return;
+                return clk->rate;
 
-        if (unlikely(clk->rate == clk->parent->rate / div))
-                return;
-        clk->rate = clk->parent->rate / div;
+        rate = clk->parent->rate / div;
 
-        pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
+        pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div);
 
-        if (unlikely(clk->flags & RATE_PROPAGATES))
-                propagate_rate(clk);
+        return rate;
 }
 
 /**
@@ -405,8 +503,8 @@ void omap2_clksel_recalc(struct clk *clk)
  * the element associated with the supplied parent clock address.
  * Returns a pointer to the struct clksel on success or NULL on error.
  */
-const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
-                                                struct clk *src_clk)
+static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
+                                                       struct clk *src_clk)
 {
         const struct clksel *clks;
 
@@ -455,7 +553,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
         *new_div = 1;
 
         clks = omap2_get_clksel_by_parent(clk, clk->parent);
-        if (clks == NULL)
+        if (!clks)
                 return ~0;
 
         for (clkr = clks->rates; clkr->div; clkr++) {
@@ -514,7 +612,7 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
 /* Given a clock and a rate apply a clock specific rounding function */
 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
 {
-        if (clk->round_rate != NULL)
+        if (clk->round_rate)
                 return clk->round_rate(clk, rate);
 
         if (clk->flags & RATE_FIXED)
@@ -540,7 +638,7 @@ u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
         const struct clksel_rate *clkr;
 
         clks = omap2_get_clksel_by_parent(clk, clk->parent);
-        if (clks == NULL)
+        if (!clks)
                 return 0;
 
         for (clkr = clks->rates; clkr->div; clkr++) {
@@ -576,7 +674,7 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
         WARN_ON(div == 0);
 
         clks = omap2_get_clksel_by_parent(clk, clk->parent);
-        if (clks == NULL)
+        if (!clks)
                 return ~0;
 
         for (clkr = clks->rates; clkr->div; clkr++) {
@@ -595,23 +693,6 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
 }
 
 /**
- * omap2_get_clksel - find clksel register addr & field mask for a clk
- * @clk: struct clk to use
- * @field_mask: ptr to u32 to store the register field mask
- *
- * Returns the address of the clksel register upon success or NULL on error.
- */
-void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
-{
-        if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL)))
-                return NULL;
-
-        *field_mask = clk->clksel_mask;
-
-        return clk->clksel_reg;
-}
-
-/**
  * omap2_clksel_get_divisor - get current divider applied to parent clock.
  * @clk: OMAP struct clk to use.
  *
@@ -619,49 +700,41 @@ void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
  */
 u32 omap2_clksel_get_divisor(struct clk *clk)
 {
-        u32 field_mask, field_val;
-        void __iomem *div_addr;
+        u32 v;
 
-        div_addr = omap2_get_clksel(clk, &field_mask);
-        if (div_addr == NULL)
+        if (!clk->clksel_mask)
                 return 0;
 
-        field_val = __raw_readl(div_addr) & field_mask;
-        field_val >>= __ffs(field_mask);
+        v = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
+        v >>= __ffs(clk->clksel_mask);
 
-        return omap2_clksel_to_divisor(clk, field_val);
+        return omap2_clksel_to_divisor(clk, v);
 }
 
 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
 {
-        u32 field_mask, field_val, reg_val, validrate, new_div = 0;
-        void __iomem *div_addr;
+        u32 v, field_val, validrate, new_div = 0;
 
-        validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
-        if (validrate != rate)
+        if (!clk->clksel_mask)
                 return -EINVAL;
 
-        div_addr = omap2_get_clksel(clk, &field_mask);
-        if (div_addr == NULL)
+        validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
+        if (validrate != rate)
                 return -EINVAL;
 
         field_val = omap2_divisor_to_clksel(clk, new_div);
         if (field_val == ~0)
                 return -EINVAL;
 
-        reg_val = __raw_readl(div_addr);
-        reg_val &= ~field_mask;
-        reg_val |= (field_val << __ffs(field_mask));
-        __raw_writel(reg_val, div_addr);
-        wmb();
+        v = __raw_readl(clk->clksel_reg);
+        v &= ~clk->clksel_mask;
+        v |= field_val << __ffs(clk->clksel_mask);
+        __raw_writel(v, clk->clksel_reg);
+        v = __raw_readl(clk->clksel_reg); /* OCP barrier */
 
         clk->rate = clk->parent->rate / new_div;
 
-        if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
-                prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
-                        OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
-                wmb();
-        }
+        _omap2xxx_clk_commit(clk);
 
         return 0;
 }
@@ -680,31 +753,24 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
                 return -EINVAL;
 
         /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
-        if (clk->set_rate != NULL)
+        if (clk->set_rate)
                 ret = clk->set_rate(clk, rate);
 
-        if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
-                propagate_rate(clk);
-
         return ret;
 }
 
 /*
  * Converts encoded control register address into a full address
- * On error, *src_addr will be returned as 0.
+ * On error, the return value (parent_div) will be 0.
  */
-static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
-                                      struct clk *src_clk, u32 *field_mask,
-                                      struct clk *clk, u32 *parent_div)
+static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
+                                       u32 *field_val)
 {
         const struct clksel *clks;
         const struct clksel_rate *clkr;
 
-        *parent_div = 0;
-        *src_addr = NULL;
-
         clks = omap2_get_clksel_by_parent(clk, src_clk);
-        if (clks == NULL)
+        if (!clks)
                 return 0;
 
         for (clkr = clks->rates; clkr->div; clkr++) {
@@ -722,47 +788,35 @@ static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
         /* Should never happen.  Add a clksel mask to the struct clk. */
         WARN_ON(clk->clksel_mask == 0);
 
-        *field_mask = clk->clksel_mask;
-        *src_addr = clk->clksel_reg;
-        *parent_div = clkr->div;
+        *field_val = clkr->val;
 
-        return clkr->val;
+        return clkr->div;
 }
 
 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 {
-        void __iomem *src_addr;
-        u32 field_val, field_mask, reg_val, parent_div;
+        u32 field_val, v, parent_div;
 
-        if (unlikely(clk->flags & CONFIG_PARTICIPANT))
+        if (clk->flags & CONFIG_PARTICIPANT)
                 return -EINVAL;
 
         if (!clk->clksel)
                 return -EINVAL;
 
-        field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
-                                               &field_mask, clk, &parent_div);
-        if (src_addr == NULL)
+        parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
+        if (!parent_div)
                 return -EINVAL;
 
-        if (clk->usecount > 0)
-                omap2_clk_disable(clk);
-
         /* Set new source value (previous dividers if any in effect) */
-        reg_val = __raw_readl(src_addr) & ~field_mask;
-        reg_val |= (field_val << __ffs(field_mask));
-        __raw_writel(reg_val, src_addr);
-        wmb();
-
-        if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
-                __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
-                wmb();
-        }
+        v = __raw_readl(clk->clksel_reg);
+        v &= ~clk->clksel_mask;
+        v |= field_val << __ffs(clk->clksel_mask);
+        __raw_writel(v, clk->clksel_reg);
+        v = __raw_readl(clk->clksel_reg);    /* OCP barrier */
 
-        clk->parent = new_parent;
+        _omap2xxx_clk_commit(clk);
 
-        if (clk->usecount > 0)
-                omap2_clk_enable(clk);
+        clk_reparent(clk, new_parent);
 
         /* CLKSEL clocks follow their parents' rates, divided by a divisor */
         clk->rate = new_parent->rate;
@@ -773,9 +827,6 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
         pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
                  clk->name, clk->parent->name, clk->rate);
 
-        if (unlikely(clk->flags & RATE_PROPAGATES))
-                propagate_rate(clk);
-
         return 0;
 }
 
@@ -805,7 +856,8 @@ int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
         return 0;
 }
 
-static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, unsigned int m, unsigned int n)
+static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
+                                            unsigned int m, unsigned int n)
 {
         unsigned long long num;
 
@@ -838,7 +890,7 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
                            unsigned long target_rate,
                            unsigned long parent_rate)
 {
-        int flags = 0, carry = 0;
+        int r = 0, carry = 0;
 
         /* Unscale m and round if necessary */
         if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
@@ -859,13 +911,13 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
         if (*m < DPLL_MIN_MULTIPLIER) {
                 *m = DPLL_MIN_MULTIPLIER;
                 *new_rate = 0;
-                flags = DPLL_MULT_UNDERFLOW;
+                r = DPLL_MULT_UNDERFLOW;
         }
 
         if (*new_rate == 0)
                 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
 
-        return flags;
+        return r;
 }
 
 /**
@@ -889,54 +941,65 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
         int m, n, r, e, scaled_max_m;
         unsigned long scaled_rt_rp, new_rate;
         int min_e = -1, min_e_m = -1, min_e_n = -1;
+        struct dpll_data *dd;
 
         if (!clk || !clk->dpll_data)
                 return ~0;
 
+        dd = clk->dpll_data;
+
         pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
                  "%ld\n", clk->name, target_rate);
 
-        scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
-        scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR;
+        scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
+        scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
 
-        clk->dpll_data->last_rounded_rate = 0;
+        dd->last_rounded_rate = 0;
 
-        for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) {
+        for (n = dd->min_divider; n <= dd->max_divider; n++) {
+
+                /* Is the (input clk, divider) pair valid for the DPLL? */
+                r = _dpll_test_fint(clk, n);
+                if (r == DPLL_FINT_UNDERFLOW)
+                        break;
+                else if (r == DPLL_FINT_INVALID)
+                        continue;
 
                 /* Compute the scaled DPLL multiplier, based on the divider */
                 m = scaled_rt_rp * n;
 
                 /*
-                 * Since we're counting n down, a m overflow means we can
-                 * can immediately skip to the next n
+                 * Since we're counting n up, a m overflow means we
+                 * can bail out completely (since as n increases in
+                 * the next iteration, there's no way that m can
+                 * increase beyond the current m)
                  */
                 if (m > scaled_max_m)
-                        continue;
+                        break;
 
                 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
-                                    clk->parent->rate);
+                                    dd->clk_ref->rate);
+
+                /* m can't be set low enough for this n - try with a larger n */
+                if (r == DPLL_MULT_UNDERFLOW)
+                        continue;
 
                 e = target_rate - new_rate;
                 pr_debug("clock: n = %d: m = %d: rate error is %d "
                          "(new_rate = %ld)\n", n, m, e, new_rate);
 
                 if (min_e == -1 ||
-                    min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) {
+                    min_e >= (int)(abs(e) - dd->rate_tolerance)) {
                         min_e = e;
                         min_e_m = m;
                         min_e_n = n;
 
                         pr_debug("clock: found new least error %d\n", min_e);
-                }
 
-                /*
-                 * Since we're counting n down, a m underflow means we
-                 * can bail out completely (since as n decreases in
-                 * the next iteration, there's no way that m can
-                 * increase beyond the current m)
-                 */
-                if (r & DPLL_MULT_UNDERFLOW)
-                        break;
+                        /* We found good settings -- bail out now */
+                        if (min_e <= dd->rate_tolerance)
+                                break;
+                }
         }
 
         if (min_e < 0) {
@@ -944,17 +1007,17 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
                 return ~0;
         }
 
-        clk->dpll_data->last_rounded_m = min_e_m;
-        clk->dpll_data->last_rounded_n = min_e_n;
-        clk->dpll_data->last_rounded_rate =
-                _dpll_compute_new_rate(clk->parent->rate, min_e_m,  min_e_n);
+        dd->last_rounded_m = min_e_m;
+        dd->last_rounded_n = min_e_n;
+        dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate,
+                                                       min_e_m,  min_e_n);
 
         pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
                  min_e, min_e_m, min_e_n);
         pr_debug("clock: final rate: %ld  (target rate: %ld)\n",
-                 clk->dpll_data->last_rounded_rate, target_rate);
+                 dd->last_rounded_rate, target_rate);
 
-        return clk->dpll_data->last_rounded_rate;
+        return dd->last_rounded_rate;
 }
 
 /*-------------------------------------------------------------------------
@@ -973,6 +1036,10 @@ void omap2_clk_disable_unused(struct clk *clk)
                 return;
 
         printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
-        _omap2_clk_disable(clk);
+        if (cpu_is_omap34xx()) {
+                omap2_clk_enable(clk);
+                omap2_clk_disable(clk);
+        } else
+                _omap2_clk_disable(clk);
 }
 #endif
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 1fb330e0847d..2679ddfa6424 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,13 +21,28 @@
 /* The maximum error between a target DPLL rate and the rounded rate in Hz */
 #define DEFAULT_DPLL_RATE_TOLERANCE     50000
 
+/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
+#define CORE_CLK_SRC_32K                0x0
+#define CORE_CLK_SRC_DPLL               0x1
+#define CORE_CLK_SRC_DPLL_X2            0x2
+
+/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
+#define OMAP2XXX_EN_DPLL_LPBYPASS               0x1
+#define OMAP2XXX_EN_DPLL_FRBYPASS               0x2
+#define OMAP2XXX_EN_DPLL_LOCKED                 0x3
+
+/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
+#define OMAP3XXX_EN_DPLL_LPBYPASS               0x5
+#define OMAP3XXX_EN_DPLL_FRBYPASS               0x6
+#define OMAP3XXX_EN_DPLL_LOCKED                 0x7
+
 int omap2_clk_init(void);
 int omap2_clk_enable(struct clk *clk);
 void omap2_clk_disable(struct clk *clk);
 long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
 int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
-int omap2_dpll_rate_tolerance_set(struct clk *clk, unsigned int tolerance);
+int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
 
 #ifdef CONFIG_OMAP_RESET_CLOCKS
@@ -36,7 +51,7 @@ void omap2_clk_disable_unused(struct clk *clk);
 #define omap2_clk_disable_unused        NULL
 #endif
 
-void omap2_clksel_recalc(struct clk *clk);
+unsigned long omap2_clksel_recalc(struct clk *clk);
 void omap2_init_clk_clkdm(struct clk *clk);
 void omap2_init_clksel_parent(struct clk *clk);
 u32 omap2_clksel_get_divisor(struct clk *clk);
@@ -44,13 +59,16 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
                                 u32 *new_div);
 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
-void omap2_fixed_divisor_recalc(struct clk *clk);
+unsigned long omap2_fixed_divisor_recalc(struct clk *clk);
 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
 u32 omap2_get_dpll_rate(struct clk *clk);
 int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
 void omap2_clk_prepare_for_reboot(void);
 
+extern const struct clkops clkops_omap2_dflt_wait;
+extern const struct clkops clkops_omap2_dflt;
+
 extern u8 cpu_mask;
 
 /* clksel_rate data common to 24xx/343x */
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index d382eb0184ac..1e839c5a28c5 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -31,15 +31,192 @@
 #include <mach/clock.h>
 #include <mach/sram.h>
 #include <asm/div64.h>
+#include <asm/clkdev.h>
 
-#include "memory.h"
+#include <mach/sdrc.h>
 #include "clock.h"
-#include "clock24xx.h"
 #include "prm.h"
 #include "prm-regbits-24xx.h"
 #include "cm.h"
 #include "cm-regbits-24xx.h"
 
+static const struct clkops clkops_oscck;
+static const struct clkops clkops_fixed;
+
+#include "clock24xx.h"
+
+struct omap_clk {
+        u32             cpu;
+        struct clk_lookup lk;
+};
+
+#define CLK(dev, con, ck, cp)           \
+        {                               \
+                 .cpu = cp,             \
+                .lk = {                 \
+                        .dev_id = dev,  \
+                        .con_id = con,  \
+                        .clk = ck,      \
+                },                      \
+        }
+
+#define CK_243X (1 << 0)
+#define CK_242X (1 << 1)
+
+static struct omap_clk omap24xx_clks[] = {
+        /* external root sources */
+        CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_243X | CK_242X),
+        CLK(NULL,       "osc_ck",       &osc_ck,        CK_243X | CK_242X),
+        CLK(NULL,       "sys_ck",       &sys_ck,        CK_243X | CK_242X),
+        CLK(NULL,       "alt_ck",       &alt_ck,        CK_243X | CK_242X),
+        /* internal analog sources */
+        CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_243X | CK_242X),
+        CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_243X | CK_242X),
+        CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_243X | CK_242X),
+        /* internal prcm root sources */
+        CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_243X | CK_242X),
+        CLK(NULL,       "core_ck",      &core_ck,       CK_243X | CK_242X),
+        CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_243X | CK_242X),
+        CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_243X | CK_242X),
+        CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_243X | CK_242X),
+        CLK(NULL,       "ck_wdt1_osc",  &wdt1_osc_ck,   CK_243X | CK_242X),
+        CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X),
+        CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_243X | CK_242X),
+        CLK(NULL,       "sys_clkout2_src", &sys_clkout2_src, CK_242X),
+        CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_242X),
+        CLK(NULL,       "emul_ck",      &emul_ck,       CK_242X),
+        /* mpu domain clocks */
+        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_243X | CK_242X),
+        /* dsp domain clocks */
+        CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_243X | CK_242X),
+        CLK(NULL,       "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X),
+        CLK(NULL,       "dsp_ick",      &dsp_ick,       CK_242X),
+        CLK(NULL,       "iva2_1_ick",   &iva2_1_ick,    CK_243X),
+        CLK(NULL,       "iva1_ifck",    &iva1_ifck,     CK_242X),
+        CLK(NULL,       "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
+        /* GFX domain clocks */
+        CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_243X | CK_242X),
+        CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_243X | CK_242X),
+        CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_243X | CK_242X),
+        /* Modem domain clocks */
+        CLK(NULL,       "mdm_ick",      &mdm_ick,       CK_243X),
+        CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck,    CK_243X),
+        /* DSS domain clocks */
+        CLK(NULL,       "dss_ick",      &dss_ick,       CK_243X | CK_242X),
+        CLK(NULL,       "dss1_fck",     &dss1_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_243X | CK_242X),
+        /* L3 domain clocks */
+        CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_243X | CK_242X),
+        CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_243X | CK_242X),
+        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_243X | CK_242X),
+        /* L4 domain clocks */
+        CLK(NULL,       "l4_ck",        &l4_ck,         CK_243X | CK_242X),
+        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_243X | CK_242X),
+        /* virtual meta-group clock */
+        CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X),
+        /* general l4 interface ck, multi-parent functional clk */
+        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_243X | CK_242X),
+        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_243X | CK_242X),
+        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_243X | CK_242X),
+        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_243X | CK_242X),
+        CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_243X | CK_242X),
+        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_243X | CK_242X),
+        CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_243X | CK_242X),
+        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_243X),
+        CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_243X),
+        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_243X),
+        CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_243X),
+        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_243X),
+        CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_243X),
+        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_243X | CK_242X),
+        CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_243X | CK_242X),
+        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_243X | CK_242X),
+        CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_243X | CK_242X),
+        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_243X),
+        CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_243X),
+        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_243X | CK_242X),
+        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_243X | CK_242X),
+        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_243X | CK_242X),
+        CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_243X | CK_242X),
+        CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_243X | CK_242X),
+        CLK("omap_wdt", "fck",          &mpu_wdt_fck,   CK_243X | CK_242X),
+        CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_243X | CK_242X),
+        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_243X | CK_242X),
+        CLK(NULL,       "icr_ick",      &icr_ick,       CK_243X),
+        CLK("omap24xxcam", "fck",       &cam_fck,       CK_243X | CK_242X),
+        CLK("omap24xxcam", "ick",       &cam_ick,       CK_243X | CK_242X),
+        CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_243X | CK_242X),
+        CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_242X),
+        CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_242X),
+        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_243X | CK_242X),
+        CLK("mmci-omap.0", "ick",       &mmc_ick,       CK_242X),
+        CLK("mmci-omap.0", "fck",       &mmc_fck,       CK_242X),
+        CLK(NULL,       "fac_ick",      &fac_ick,       CK_243X | CK_242X),
+        CLK(NULL,       "fac_fck",      &fac_fck,       CK_243X | CK_242X),
+        CLK(NULL,       "eac_ick",      &eac_ick,       CK_242X),
+        CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
+        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_243X | CK_242X),
+        CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_243X | CK_242X),
+        CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_243X | CK_242X),
+        CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_242X),
+        CLK("i2c_omap.1", "fck",        &i2chs1_fck,    CK_243X),
+        CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_243X | CK_242X),
+        CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_242X),
+        CLK("i2c_omap.2", "fck",        &i2chs2_fck,    CK_243X),
+        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "vlynq_ick",    &vlynq_ick,     CK_242X),
+        CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
+        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_243X),
+        CLK(NULL,       "des_ick",      &des_ick,       CK_243X | CK_242X),
+        CLK(NULL,       "sha_ick",      &sha_ick,       CK_243X | CK_242X),
+        CLK("omap_rng", "ick",          &rng_ick,       CK_243X | CK_242X),
+        CLK(NULL,       "aes_ick",      &aes_ick,       CK_243X | CK_242X),
+        CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X | CK_242X),
+        CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X | CK_242X),
+        CLK(NULL,       "usbhs_ick",    &usbhs_ick,     CK_243X),
+        CLK("mmci-omap-hs.0", "ick",    &mmchs1_ick,    CK_243X),
+        CLK("mmci-omap-hs.0", "fck",    &mmchs1_fck,    CK_243X),
+        CLK("mmci-omap-hs.1", "ick",    &mmchs2_ick,    CK_243X),
+        CLK("mmci-omap-hs.1", "fck",    &mmchs2_fck,    CK_243X),
+        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_243X),
+        CLK(NULL,       "gpio5_fck",    &gpio5_fck,     CK_243X),
+        CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
+        CLK("mmci-omap-hs.0", "mmchsdb_fck",    &mmchsdb1_fck,  CK_243X),
+        CLK("mmci-omap-hs.1", "mmchsdb_fck",    &mmchsdb2_fck,  CK_243X),
+};
+
 /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
 #define EN_APLL_STOPPED                 0
 #define EN_APLL_LOCKED                  3
@@ -59,19 +236,32 @@ static struct clk *sclk;
  * Omap24xx specific clock functions
  *-------------------------------------------------------------------------*/
 
-/* This actually returns the rate of core_ck, not dpll_ck. */
-static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
+/**
+ * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
+ * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
+ *
+ * Returns the CORE_CLK rate.  CORE_CLK can have one of three rate
+ * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
+ * (the latter is unusual).  This currently should be called with
+ * struct clk *dpll_ck, which is a composite clock of dpll_ck and
+ * core_ck.
+ */
+static unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
 {
-        long long dpll_clk;
-        u8 amult;
+        long long core_clk;
+        u32 v;
+
+        core_clk = omap2_get_dpll_rate(clk);
 
-        dpll_clk = omap2_get_dpll_rate(tclk);
+        v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        v &= OMAP24XX_CORE_CLK_SRC_MASK;
 
-        amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
-        amult &= OMAP24XX_CORE_CLK_SRC_MASK;
-        dpll_clk *= amult;
+        if (v == CORE_CLK_SRC_32K)
+                core_clk = 32768;
+        else
+                core_clk *= v;
 
-        return dpll_clk;
+        return core_clk;
 }
 
 static int omap2_enable_osc_ck(struct clk *clk)
@@ -96,6 +286,11 @@ static void omap2_disable_osc_ck(struct clk *clk)
                       OMAP24XX_PRCM_CLKSRC_CTRL);
 }
 
+static const struct clkops clkops_oscck = {
+        .enable         = &omap2_enable_osc_ck,
+        .disable        = &omap2_disable_osc_ck,
+};
+
 #ifdef OLD_CK
 /* Recalculate SYST_CLK */
 static void omap2_sys_clk_recalc(struct clk * clk)
@@ -149,11 +344,16 @@ static void omap2_clk_fixed_disable(struct clk *clk)
         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 }
 
+static const struct clkops clkops_fixed = {
+        .enable         = &omap2_clk_fixed_enable,
+        .disable        = &omap2_clk_fixed_disable,
+};
+
 /*
  * Uses the current prcm set to tell if a rate is valid.
  * You can go slower, but not faster within a given rate set.
  */
-long omap2_dpllcore_round_rate(unsigned long target_rate)
+static long omap2_dpllcore_round_rate(unsigned long target_rate)
 {
         u32 high, low, core_clk_src;
 
@@ -182,11 +382,9 @@ long omap2_dpllcore_round_rate(unsigned long target_rate)
 
 }
 
-static void omap2_dpllcore_recalc(struct clk *clk)
+static unsigned long omap2_dpllcore_recalc(struct clk *clk)
 {
-        clk->rate = omap2_get_dpll_rate_24xx(clk);
-
-        propagate_rate(clk);
+        return omap2xxx_clk_get_core_rate(clk);
 }
 
 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
@@ -195,22 +393,19 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
         u32 bypass = 0;
         struct prcm_config tmpset;
         const struct dpll_data *dd;
-        unsigned long flags;
-        int ret = -EINVAL;
 
-        local_irq_save(flags);
-        cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
+        cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
         mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
         mult &= OMAP24XX_CORE_CLK_SRC_MASK;
 
         if ((rate == (cur_rate / 2)) && (mult == 2)) {
-                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
         } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
-                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
         } else if (rate != cur_rate) {
                 valid_rate = omap2_dpllcore_round_rate(rate);
                 if (valid_rate != rate)
-                        goto dpll_exit;
+                        return -EINVAL;
 
                 if (mult == 1)
                         low = curr_prcm_set->dpll_speed;
@@ -219,7 +414,7 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
 
                 dd = clk->dpll_data;
                 if (!dd)
-                        goto dpll_exit;
+                        return -EINVAL;
 
                 tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
                 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
@@ -245,22 +440,19 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
                 if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
                         bypass = 1;
 
-                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */
+                /* For omap2xxx_sdrc_init_params() */
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
 
                 /* Force dll lock mode */
                 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
                                bypass);
 
                 /* Errata: ret dll entry state */
-                omap2_init_memory_params(omap2_dll_force_needed());
-                omap2_reprogram_sdrc(done_rate, 0);
+                omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
+                omap2xxx_sdrc_reprogram(done_rate, 0);
         }
-        omap2_dpllcore_recalc(&dpll_ck);
-        ret = 0;
 
-dpll_exit:
-        local_irq_restore(flags);
-        return(ret);
+        return 0;
 }
 
 /**
@@ -269,9 +461,9 @@ dpll_exit:
  *
  * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
  */
-static void omap2_table_mpu_recalc(struct clk *clk)
+static unsigned long omap2_table_mpu_recalc(struct clk *clk)
 {
-        clk->rate = curr_prcm_set->mpu_speed;
+        return curr_prcm_set->mpu_speed;
 }
 
 /*
@@ -337,12 +529,12 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
         }
 
         curr_prcm_set = prcm;
-        cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
+        cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
 
         if (prcm->dpll_speed == cur_rate / 2) {
-                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
         } else if (prcm->dpll_speed == cur_rate * 2) {
-                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
         } else if (prcm->dpll_speed != cur_rate) {
                 local_irq_save(flags);
 
@@ -366,27 +558,67 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
 
                 /* Major subsystem dividers */
                 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
-                cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1);
+                cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
+                                 CM_CLKSEL1);
+
                 if (cpu_is_omap2430())
                         cm_write_mod_reg(prcm->cm_clksel_mdm,
                                          OMAP2430_MDM_MOD, CM_CLKSEL);
 
-                /* x2 to enter init_mem */
-                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
+                /* x2 to enter omap2xxx_sdrc_init_params() */
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
 
                 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
                                bypass);
 
-                omap2_init_memory_params(omap2_dll_force_needed());
-                omap2_reprogram_sdrc(done_rate, 0);
+                omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
+                omap2xxx_sdrc_reprogram(done_rate, 0);
 
                 local_irq_restore(flags);
         }
-        omap2_dpllcore_recalc(&dpll_ck);
 
         return 0;
 }
 
+#ifdef CONFIG_CPU_FREQ
+/*
+ * Walk PRCM rate table and fillout cpufreq freq_table
+ */
+static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)];
+
+void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
+{
+        struct prcm_config *prcm;
+        int i = 0;
+
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+                if (prcm->xtal_speed != sys_ck.rate)
+                        continue;
+
+                /* don't put bypass rates in table */
+                if (prcm->dpll_speed == prcm->xtal_speed)
+                        continue;
+
+                freq_table[i].index = i;
+                freq_table[i].frequency = prcm->mpu_speed / 1000;
+                i++;
+        }
+
+        if (i == 0) {
+                printk(KERN_WARNING "%s: failed to initialize frequency "
+                       "table\n", __func__);
+                return;
+        }
+
+        freq_table[i].index = i;
+        freq_table[i].frequency = CPUFREQ_TABLE_END;
+
+        *table = &freq_table[0];
+}
+#endif
+
 static struct clk_functions omap2_clk_functions = {
         .clk_enable             = omap2_clk_enable,
         .clk_disable            = omap2_clk_disable,
@@ -394,24 +626,27 @@ static struct clk_functions omap2_clk_functions = {
         .clk_set_rate           = omap2_clk_set_rate,
         .clk_set_parent         = omap2_clk_set_parent,
         .clk_disable_unused     = omap2_clk_disable_unused,
+#ifdef  CONFIG_CPU_FREQ
+        .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
+#endif
 };
 
 static u32 omap2_get_apll_clkin(void)
 {
-        u32 aplls, sclk = 0;
+        u32 aplls, srate = 0;
 
         aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
         aplls &= OMAP24XX_APLLS_CLKIN_MASK;
         aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
 
         if (aplls == APLLS_CLKIN_19_2MHZ)
-                sclk = 19200000;
+                srate = 19200000;
         else if (aplls == APLLS_CLKIN_13MHZ)
-                sclk = 13000000;
+                srate = 13000000;
         else if (aplls == APLLS_CLKIN_12MHZ)
-                sclk = 12000000;
+                srate = 12000000;
 
-        return sclk;
+        return srate;
 }
 
 static u32 omap2_get_sysclkdiv(void)
@@ -425,16 +660,14 @@ static u32 omap2_get_sysclkdiv(void)
         return div;
 }
 
-static void omap2_osc_clk_recalc(struct clk *clk)
+static unsigned long omap2_osc_clk_recalc(struct clk *clk)
 {
-        clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
-        propagate_rate(clk);
+        return omap2_get_apll_clkin() * omap2_get_sysclkdiv();
 }
 
-static void omap2_sys_clk_recalc(struct clk *clk)
+static unsigned long omap2_sys_clk_recalc(struct clk *clk)
 {
-        clk->rate = clk->parent->rate / omap2_get_sysclkdiv();
-        propagate_rate(clk);
+        return clk->parent->rate / omap2_get_sysclkdiv();
 }
 
 /*
@@ -460,7 +693,7 @@ static int __init omap2_clk_arch_init(void)
         if (!mpurate)
                 return -EINVAL;
 
-        if (omap2_select_table_rate(&virt_prcm_set, mpurate))
+        if (clk_set_rate(&virt_prcm_set, mpurate))
                 printk(KERN_ERR "Could not find matching MPU rate\n");
 
         recalculate_root_clocks();
@@ -477,8 +710,8 @@ arch_initcall(omap2_clk_arch_init);
 int __init omap2_clk_init(void)
 {
         struct prcm_config *prcm;
-        struct clk **clkp;
-        u32 clkrate;
+        struct omap_clk *c;
+        u32 clkrate, cpu_mask;
 
         if (cpu_is_omap242x())
                 cpu_mask = RATE_IN_242X;
@@ -487,26 +720,28 @@ int __init omap2_clk_init(void)
 
         clk_init(&omap2_clk_functions);
 
-        omap2_osc_clk_recalc(&osc_ck);
-        omap2_sys_clk_recalc(&sys_ck);
+        osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
+        propagate_rate(&osc_ck);
+        sys_ck.rate = omap2_sys_clk_recalc(&sys_ck);
+        propagate_rate(&sys_ck);
 
-        for (clkp = onchip_24xx_clks;
-             clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
-             clkp++) {
+        for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
+                clk_init_one(c->lk.clk);
 
-                if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
-                        clk_register(*clkp);
-                        continue;
-                }
+        cpu_mask = 0;
+        if (cpu_is_omap2420())
+                cpu_mask |= CK_242X;
+        if (cpu_is_omap2430())
+                cpu_mask |= CK_243X;
 
-                if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
-                        clk_register(*clkp);
-                        continue;
+        for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
+                if (c->cpu & cpu_mask) {
+                        clkdev_add(&c->lk);
+                        clk_register(c->lk.clk);
                 }
-        }
 
         /* Check the MPU rate set by bootloader */
-        clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
+        clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
                 if (!(prcm->flags & cpu_mask))
                         continue;
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index ad6d98d177c5..33c3e5b14323 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -24,17 +24,13 @@
 #include "cm-regbits-24xx.h"
 #include "sdrc.h"
 
-static void omap2_table_mpu_recalc(struct clk *clk);
+static unsigned long omap2_table_mpu_recalc(struct clk *clk);
 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
-static void omap2_sys_clk_recalc(struct clk *clk);
-static void omap2_osc_clk_recalc(struct clk *clk);
-static void omap2_sys_clk_recalc(struct clk *clk);
-static void omap2_dpllcore_recalc(struct clk *clk);
-static int omap2_clk_fixed_enable(struct clk *clk);
-static void omap2_clk_fixed_disable(struct clk *clk);
-static int omap2_enable_osc_ck(struct clk *clk);
-static void omap2_disable_osc_ck(struct clk *clk);
+static unsigned long omap2_sys_clk_recalc(struct clk *clk);
+static unsigned long omap2_osc_clk_recalc(struct clk *clk);
+static unsigned long omap2_sys_clk_recalc(struct clk *clk);
+static unsigned long omap2_dpllcore_recalc(struct clk *clk);
 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
 
 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
@@ -623,41 +619,35 @@ static struct prcm_config rate_table[] = {
 /* Base external input clocks */
 static struct clk func_32k_ck = {
         .name           = "func_32k_ck",
+        .ops            = &clkops_null,
         .rate           = 32000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
+        .flags          = RATE_FIXED,
         .clkdm_name     = "wkup_clkdm",
-        .recalc         = &propagate_rate,
 };
 
 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
         .name           = "osc_ck",
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_PROPAGATES,
+        .ops            = &clkops_oscck,
         .clkdm_name     = "wkup_clkdm",
-        .enable         = &omap2_enable_osc_ck,
-        .disable        = &omap2_disable_osc_ck,
         .recalc         = &omap2_osc_clk_recalc,
 };
 
 /* Without modem likely 12MHz, with modem likely 13MHz */
 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
         .name           = "sys_ck",             /* ~ ref_clk also */
+        .ops            = &clkops_null,
         .parent         = &osc_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                ALWAYS_ENABLED | RATE_PROPAGATES,
         .clkdm_name     = "wkup_clkdm",
         .recalc         = &omap2_sys_clk_recalc,
 };
 
 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
         .name           = "alt_ck",
+        .ops            = &clkops_null,
         .rate           = 54000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
+        .flags          = RATE_FIXED,
         .clkdm_name     = "wkup_clkdm",
-        .recalc         = &propagate_rate,
 };
 
 /*
@@ -673,7 +663,12 @@ static struct dpll_data dpll_dd = {
         .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
+        .clk_bypass             = &sys_ck,
+        .clk_ref                = &sys_ck,
+        .control_reg            = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_mask            = OMAP24XX_EN_DPLL_MASK,
         .max_multiplier         = 1024,
+        .min_divider            = 1,
         .max_divider            = 16,
         .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -684,10 +679,9 @@ static struct dpll_data dpll_dd = {
  */
 static struct clk dpll_ck = {
         .name           = "dpll_ck",
+        .ops            = &clkops_null,
         .parent         = &sys_ck,              /* Can be func_32k also */
         .dpll_data      = &dpll_dd,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_PROPAGATES | ALWAYS_ENABLED,
         .clkdm_name     = "wkup_clkdm",
         .recalc         = &omap2_dpllcore_recalc,
         .set_rate       = &omap2_reprogram_dpllcore,
@@ -695,30 +689,24 @@ static struct clk dpll_ck = {
 
 static struct clk apll96_ck = {
         .name           = "apll96_ck",
+        .ops            = &clkops_fixed,
         .parent         = &sys_ck,
         .rate           = 96000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
+        .flags          = RATE_FIXED | ENABLE_ON_INIT,
         .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
-        .enable         = &omap2_clk_fixed_enable,
-        .disable        = &omap2_clk_fixed_disable,
-        .recalc         = &propagate_rate,
 };
 
 static struct clk apll54_ck = {
         .name           = "apll54_ck",
+        .ops            = &clkops_fixed,
         .parent         = &sys_ck,
         .rate           = 54000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
+        .flags          = RATE_FIXED | ENABLE_ON_INIT,
         .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
-        .enable         = &omap2_clk_fixed_enable,
-        .disable        = &omap2_clk_fixed_disable,
-        .recalc         = &propagate_rate,
 };
 
 /*
@@ -745,9 +733,8 @@ static const struct clksel func_54m_clksel[] = {
 
 static struct clk func_54m_ck = {
         .name           = "func_54m_ck",
+        .ops            = &clkops_null,
         .parent         = &apll54_ck,   /* can also be alt_clk */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
         .clkdm_name     = "wkup_clkdm",
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -758,9 +745,8 @@ static struct clk func_54m_ck = {
 
 static struct clk core_ck = {
         .name           = "core_ck",
+        .ops            = &clkops_null,
         .parent         = &dpll_ck,             /* can also be 32k */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                ALWAYS_ENABLED | RATE_PROPAGATES,
         .clkdm_name     = "wkup_clkdm",
         .recalc         = &followparent_recalc,
 };
@@ -785,9 +771,8 @@ static const struct clksel func_96m_clksel[] = {
 /* The parent of this clock is not selectable on 2420. */
 static struct clk func_96m_ck = {
         .name           = "func_96m_ck",
+        .ops            = &clkops_null,
         .parent         = &apll96_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
         .clkdm_name     = "wkup_clkdm",
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -818,9 +803,8 @@ static const struct clksel func_48m_clksel[] = {
 
 static struct clk func_48m_ck = {
         .name           = "func_48m_ck",
+        .ops            = &clkops_null,
         .parent         = &apll96_ck,    /* 96M or Alt */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
         .clkdm_name     = "wkup_clkdm",
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -833,10 +817,9 @@ static struct clk func_48m_ck = {
 
 static struct clk func_12m_ck = {
         .name           = "func_12m_ck",
+        .ops            = &clkops_null,
         .parent         = &func_48m_ck,
         .fixed_div      = 4,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
         .clkdm_name     = "wkup_clkdm",
         .recalc         = &omap2_fixed_divisor_recalc,
 };
@@ -844,8 +827,8 @@ static struct clk func_12m_ck = {
 /* Secure timer, only available in secure mode */
 static struct clk wdt1_osc_ck = {
         .name           = "ck_wdt1_osc",
+        .ops            = &clkops_null, /* RMK: missing? */
         .parent         = &osc_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .recalc         = &followparent_recalc,
 };
 
@@ -887,9 +870,8 @@ static const struct clksel common_clkout_src_clksel[] = {
 
 static struct clk sys_clkout_src = {
         .name           = "sys_clkout_src",
+        .ops            = &clkops_omap2_dflt,
         .parent         = &func_54m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_PROPAGATES,
         .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
@@ -918,9 +900,8 @@ static const struct clksel sys_clkout_clksel[] = {
 
 static struct clk sys_clkout = {
         .name           = "sys_clkout",
+        .ops            = &clkops_null,
         .parent         = &sys_clkout_src,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                PARENT_CONTROLS_CLOCK,
         .clkdm_name     = "wkup_clkdm",
         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
@@ -933,8 +914,8 @@ static struct clk sys_clkout = {
 /* In 2430, new in 2420 ES2 */
 static struct clk sys_clkout2_src = {
         .name           = "sys_clkout2_src",
+        .ops            = &clkops_omap2_dflt,
         .parent         = &func_54m_ck,
-        .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
         .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
@@ -955,8 +936,8 @@ static const struct clksel sys_clkout2_clksel[] = {
 /* In 2430, new in 2420 ES2 */
 static struct clk sys_clkout2 = {
         .name           = "sys_clkout2",
+        .ops            = &clkops_null,
         .parent         = &sys_clkout2_src,
-        .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
         .clkdm_name     = "wkup_clkdm",
         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
@@ -968,8 +949,8 @@ static struct clk sys_clkout2 = {
 
 static struct clk emul_ck = {
         .name           = "emul_ck",
+        .ops            = &clkops_omap2_dflt,
         .parent         = &func_54m_ck,
-        .flags          = CLOCK_IN_OMAP242X,
         .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
@@ -1003,10 +984,9 @@ static const struct clksel mpu_clksel[] = {
 
 static struct clk mpu_ck = {    /* Control cpu */
         .name           = "mpu_ck",
+        .ops            = &clkops_null,
         .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                ALWAYS_ENABLED | DELAYED_APP |
-                                CONFIG_PARTICIPANT | RATE_PROPAGATES,
+        .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
         .clkdm_name     = "mpu_clkdm",
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
@@ -1046,9 +1026,9 @@ static const struct clksel dsp_fck_clksel[] = {
 
 static struct clk dsp_fck = {
         .name           = "dsp_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
-                                CONFIG_PARTICIPANT | RATE_PROPAGATES,
+        .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
         .clkdm_name     = "dsp_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
@@ -1076,9 +1056,9 @@ static const struct clksel dsp_irate_ick_clksel[] = {
 /* This clock does not exist as such in the TRM. */
 static struct clk dsp_irate_ick = {
         .name           = "dsp_irate_ick",
+        .ops            = &clkops_null,
         .parent         = &dsp_fck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
-                                CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
+        .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
         .clksel         = dsp_irate_ick_clksel,
@@ -1090,8 +1070,9 @@ static struct clk dsp_irate_ick = {
 /* 2420 only */
 static struct clk dsp_ick = {
         .name           = "dsp_ick",     /* apparently ipi and isp */
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &dsp_irate_ick,
-        .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
+        .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
 };
@@ -1099,8 +1080,9 @@ static struct clk dsp_ick = {
 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
 static struct clk iva2_1_ick = {
         .name           = "iva2_1_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &dsp_irate_ick,
-        .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
+        .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 };
@@ -1112,9 +1094,9 @@ static struct clk iva2_1_ick = {
  */
 static struct clk iva1_ifck = {
         .name           = "iva1_ifck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
-                                RATE_PROPAGATES | DELAYED_APP,
+        .flags          = CONFIG_PARTICIPANT | DELAYED_APP,
         .clkdm_name     = "iva1_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
@@ -1129,8 +1111,8 @@ static struct clk iva1_ifck = {
 /* IVA1 mpu/int/i/f clocks are /2 of parent */
 static struct clk iva1_mpu_int_ifck = {
         .name           = "iva1_mpu_int_ifck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &iva1_ifck,
-        .flags          = CLOCK_IN_OMAP242X,
         .clkdm_name     = "iva1_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
@@ -1175,10 +1157,9 @@ static const struct clksel core_l3_clksel[] = {
 
 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
         .name           = "core_l3_ck",
+        .ops            = &clkops_null,
         .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                ALWAYS_ENABLED | DELAYED_APP |
-                                CONFIG_PARTICIPANT | RATE_PROPAGATES,
+        .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
         .clkdm_name     = "core_l3_clkdm",
         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
@@ -1204,9 +1185,9 @@ static const struct clksel usb_l4_ick_clksel[] = {
 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
         .name           = "usb_l4_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                DELAYED_APP | CONFIG_PARTICIPANT,
+        .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
@@ -1238,9 +1219,9 @@ static const struct clksel l4_clksel[] = {
 
 static struct clk l4_ck = {             /* used both as an ick and fck */
         .name           = "l4_ck",
+        .ops            = &clkops_null,
         .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
+        .flags          = DELAYED_APP,
         .clkdm_name     = "core_l4_clkdm",
         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
@@ -1276,9 +1257,9 @@ static const struct clksel ssi_ssr_sst_fck_clksel[] = {
 
 static struct clk ssi_ssr_sst_fck = {
         .name           = "ssi_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                DELAYED_APP,
+        .flags          = DELAYED_APP,
         .clkdm_name     = "core_l3_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
@@ -1290,6 +1271,20 @@ static struct clk ssi_ssr_sst_fck = {
         .set_rate       = &omap2_clksel_set_rate
 };
 
+/*
+ * Presumably this is the same as SSI_ICLK.
+ * TRM contradicts itself on what clockdomain SSI_ICLK is in
+ */
+static struct clk ssi_l4_ick = {
+        .name           = "ssi_l4_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
 
 /*
  * GFX clock domain
@@ -1312,8 +1307,8 @@ static const struct clksel gfx_fck_clksel[] = {
 
 static struct clk gfx_3d_fck = {
         .name           = "gfx_3d_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "gfx_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
@@ -1327,8 +1322,8 @@ static struct clk gfx_3d_fck = {
 
 static struct clk gfx_2d_fck = {
         .name           = "gfx_2d_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "gfx_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
@@ -1342,8 +1337,8 @@ static struct clk gfx_2d_fck = {
 
 static struct clk gfx_ick = {
         .name           = "gfx_ick",            /* From l3 */
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "gfx_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
         .enable_bit     = OMAP_EN_GFX_SHIFT,
@@ -1372,8 +1367,9 @@ static const struct clksel mdm_ick_clksel[] = {
 
 static struct clk mdm_ick = {           /* used both as a ick and fck */
         .name           = "mdm_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
+        .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
         .clkdm_name     = "mdm_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
@@ -1387,8 +1383,8 @@ static struct clk mdm_ick = {		/* used both as a ick and fck */
 
 static struct clk mdm_osc_ck = {
         .name           = "mdm_osc_ck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &osc_ck,
-        .flags          = CLOCK_IN_OMAP243X,
         .clkdm_name     = "mdm_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
@@ -1432,8 +1428,8 @@ static const struct clksel dss1_fck_clksel[] = {
 
 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
         .name           = "dss_ick",
+        .ops            = &clkops_omap2_dflt,
         .parent         = &l4_ck,       /* really both l3 and l4 */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "dss_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
@@ -1442,9 +1438,9 @@ static struct clk dss_ick = {		/* Enables both L3,L4 ICLK's */
 
 static struct clk dss1_fck = {
         .name           = "dss1_fck",
+        .ops            = &clkops_omap2_dflt,
         .parent         = &core_ck,             /* Core or sys */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                DELAYED_APP,
+        .flags          = DELAYED_APP,
         .clkdm_name     = "dss_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
@@ -1475,9 +1471,9 @@ static const struct clksel dss2_fck_clksel[] = {
 
 static struct clk dss2_fck = {          /* Alt clk used in power management */
         .name           = "dss2_fck",
+        .ops            = &clkops_omap2_dflt,
         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                DELAYED_APP,
+        .flags          = DELAYED_APP,
         .clkdm_name     = "dss_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
@@ -1490,8 +1486,8 @@ static struct clk dss2_fck = {		/* Alt clk used in power management */
 
 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
         .name           = "dss_54m_fck",        /* 54m tv clk */
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_54m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "dss_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
@@ -1518,8 +1514,8 @@ static const struct clksel omap24xx_gpt_clksel[] = {
 
 static struct clk gpt1_ick = {
         .name           = "gpt1_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
@@ -1528,8 +1524,8 @@ static struct clk gpt1_ick = {
 
 static struct clk gpt1_fck = {
         .name           = "gpt1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
@@ -1544,8 +1540,8 @@ static struct clk gpt1_fck = {
 
 static struct clk gpt2_ick = {
         .name           = "gpt2_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
@@ -1554,8 +1550,8 @@ static struct clk gpt2_ick = {
 
 static struct clk gpt2_fck = {
         .name           = "gpt2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
@@ -1568,8 +1564,8 @@ static struct clk gpt2_fck = {
 
 static struct clk gpt3_ick = {
         .name           = "gpt3_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
@@ -1578,8 +1574,8 @@ static struct clk gpt3_ick = {
 
 static struct clk gpt3_fck = {
         .name           = "gpt3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
@@ -1592,8 +1588,8 @@ static struct clk gpt3_fck = {
 
 static struct clk gpt4_ick = {
         .name           = "gpt4_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
@@ -1602,8 +1598,8 @@ static struct clk gpt4_ick = {
 
 static struct clk gpt4_fck = {
         .name           = "gpt4_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
@@ -1616,8 +1612,8 @@ static struct clk gpt4_fck = {
 
 static struct clk gpt5_ick = {
         .name           = "gpt5_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
@@ -1626,8 +1622,8 @@ static struct clk gpt5_ick = {
 
 static struct clk gpt5_fck = {
         .name           = "gpt5_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
@@ -1640,8 +1636,8 @@ static struct clk gpt5_fck = {
 
 static struct clk gpt6_ick = {
         .name           = "gpt6_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
@@ -1650,8 +1646,8 @@ static struct clk gpt6_ick = {
 
 static struct clk gpt6_fck = {
         .name           = "gpt6_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
@@ -1664,8 +1660,8 @@ static struct clk gpt6_fck = {
 
 static struct clk gpt7_ick = {
         .name           = "gpt7_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1673,8 +1669,8 @@ static struct clk gpt7_ick = {
 
 static struct clk gpt7_fck = {
         .name           = "gpt7_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
@@ -1687,8 +1683,8 @@ static struct clk gpt7_fck = {
 
 static struct clk gpt8_ick = {
         .name           = "gpt8_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
@@ -1697,8 +1693,8 @@ static struct clk gpt8_ick = {
 
 static struct clk gpt8_fck = {
         .name           = "gpt8_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
@@ -1711,8 +1707,8 @@ static struct clk gpt8_fck = {
 
 static struct clk gpt9_ick = {
         .name           = "gpt9_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
@@ -1721,8 +1717,8 @@ static struct clk gpt9_ick = {
 
 static struct clk gpt9_fck = {
         .name           = "gpt9_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
@@ -1735,8 +1731,8 @@ static struct clk gpt9_fck = {
 
 static struct clk gpt10_ick = {
         .name           = "gpt10_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
@@ -1745,8 +1741,8 @@ static struct clk gpt10_ick = {
 
 static struct clk gpt10_fck = {
         .name           = "gpt10_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
@@ -1759,8 +1755,8 @@ static struct clk gpt10_fck = {
 
 static struct clk gpt11_ick = {
         .name           = "gpt11_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
@@ -1769,8 +1765,8 @@ static struct clk gpt11_ick = {
 
 static struct clk gpt11_fck = {
         .name           = "gpt11_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
@@ -1783,8 +1779,8 @@ static struct clk gpt11_fck = {
 
 static struct clk gpt12_ick = {
         .name           = "gpt12_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
@@ -1793,8 +1789,8 @@ static struct clk gpt12_ick = {
 
 static struct clk gpt12_fck = {
         .name           = "gpt12_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
@@ -1807,9 +1803,9 @@ static struct clk gpt12_fck = {
 
 static struct clk mcbsp1_ick = {
         .name           = "mcbsp_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 1,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
@@ -1818,9 +1814,9 @@ static struct clk mcbsp1_ick = {
 
 static struct clk mcbsp1_fck = {
         .name           = "mcbsp_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 1,
         .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
@@ -1829,9 +1825,9 @@ static struct clk mcbsp1_fck = {
 
 static struct clk mcbsp2_ick = {
         .name           = "mcbsp_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 2,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
@@ -1840,9 +1836,9 @@ static struct clk mcbsp2_ick = {
 
 static struct clk mcbsp2_fck = {
         .name           = "mcbsp_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 2,
         .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
@@ -1851,9 +1847,9 @@ static struct clk mcbsp2_fck = {
 
 static struct clk mcbsp3_ick = {
         .name           = "mcbsp_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 3,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
@@ -1862,9 +1858,9 @@ static struct clk mcbsp3_ick = {
 
 static struct clk mcbsp3_fck = {
         .name           = "mcbsp_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 3,
         .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
@@ -1873,9 +1869,9 @@ static struct clk mcbsp3_fck = {
 
 static struct clk mcbsp4_ick = {
         .name           = "mcbsp_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 4,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
@@ -1884,9 +1880,9 @@ static struct clk mcbsp4_ick = {
 
 static struct clk mcbsp4_fck = {
         .name           = "mcbsp_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 4,
         .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
@@ -1895,9 +1891,9 @@ static struct clk mcbsp4_fck = {
 
 static struct clk mcbsp5_ick = {
         .name           = "mcbsp_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 5,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
@@ -1906,9 +1902,9 @@ static struct clk mcbsp5_ick = {
 
 static struct clk mcbsp5_fck = {
         .name           = "mcbsp_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 5,
         .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
@@ -1917,10 +1913,10 @@ static struct clk mcbsp5_fck = {
 
 static struct clk mcspi1_ick = {
         .name           = "mcspi_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 1,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1928,9 +1924,9 @@ static struct clk mcspi1_ick = {
 
 static struct clk mcspi1_fck = {
         .name           = "mcspi_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 1,
         .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
@@ -1939,9 +1935,9 @@ static struct clk mcspi1_fck = {
 
 static struct clk mcspi2_ick = {
         .name           = "mcspi_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 2,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
@@ -1950,9 +1946,9 @@ static struct clk mcspi2_ick = {
 
 static struct clk mcspi2_fck = {
         .name           = "mcspi_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 2,
         .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
@@ -1961,9 +1957,9 @@ static struct clk mcspi2_fck = {
 
 static struct clk mcspi3_ick = {
         .name           = "mcspi_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 3,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
@@ -1972,9 +1968,9 @@ static struct clk mcspi3_ick = {
 
 static struct clk mcspi3_fck = {
         .name           = "mcspi_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 3,
         .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
@@ -1983,8 +1979,8 @@ static struct clk mcspi3_fck = {
 
 static struct clk uart1_ick = {
         .name           = "uart1_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
@@ -1993,8 +1989,8 @@ static struct clk uart1_ick = {
 
 static struct clk uart1_fck = {
         .name           = "uart1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
@@ -2003,8 +1999,8 @@ static struct clk uart1_fck = {
 
 static struct clk uart2_ick = {
         .name           = "uart2_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
@@ -2013,8 +2009,8 @@ static struct clk uart2_ick = {
 
 static struct clk uart2_fck = {
         .name           = "uart2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
@@ -2023,8 +2019,8 @@ static struct clk uart2_fck = {
 
 static struct clk uart3_ick = {
         .name           = "uart3_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
@@ -2033,8 +2029,8 @@ static struct clk uart3_ick = {
 
 static struct clk uart3_fck = {
         .name           = "uart3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
@@ -2043,8 +2039,8 @@ static struct clk uart3_fck = {
 
 static struct clk gpios_ick = {
         .name           = "gpios_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
@@ -2053,8 +2049,8 @@ static struct clk gpios_ick = {
 
 static struct clk gpios_fck = {
         .name           = "gpios_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
@@ -2063,8 +2059,8 @@ static struct clk gpios_fck = {
 
 static struct clk mpu_wdt_ick = {
         .name           = "mpu_wdt_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
@@ -2073,8 +2069,8 @@ static struct clk mpu_wdt_ick = {
 
 static struct clk mpu_wdt_fck = {
         .name           = "mpu_wdt_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
@@ -2083,9 +2079,9 @@ static struct clk mpu_wdt_fck = {
 
 static struct clk sync_32k_ick = {
         .name           = "sync_32k_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                ENABLE_ON_INIT,
+        .flags          = ENABLE_ON_INIT,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
@@ -2094,8 +2090,8 @@ static struct clk sync_32k_ick = {
 
 static struct clk wdt1_ick = {
         .name           = "wdt1_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
@@ -2104,9 +2100,9 @@ static struct clk wdt1_ick = {
 
 static struct clk omapctrl_ick = {
         .name           = "omapctrl_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                ENABLE_ON_INIT,
+        .flags          = ENABLE_ON_INIT,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
@@ -2115,8 +2111,8 @@ static struct clk omapctrl_ick = {
 
 static struct clk icr_ick = {
         .name           = "icr_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
@@ -2125,8 +2121,8 @@ static struct clk icr_ick = {
 
 static struct clk cam_ick = {
         .name           = "cam_ick",
+        .ops            = &clkops_omap2_dflt,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
@@ -2140,8 +2136,8 @@ static struct clk cam_ick = {
  */
 static struct clk cam_fck = {
         .name           = "cam_fck",
+        .ops            = &clkops_omap2_dflt,
         .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l3_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
@@ -2150,8 +2146,8 @@ static struct clk cam_fck = {
 
 static struct clk mailboxes_ick = {
         .name           = "mailboxes_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
@@ -2160,8 +2156,8 @@ static struct clk mailboxes_ick = {
 
 static struct clk wdt4_ick = {
         .name           = "wdt4_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
@@ -2170,8 +2166,8 @@ static struct clk wdt4_ick = {
 
 static struct clk wdt4_fck = {
         .name           = "wdt4_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
@@ -2180,8 +2176,8 @@ static struct clk wdt4_fck = {
 
 static struct clk wdt3_ick = {
         .name           = "wdt3_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
@@ -2190,8 +2186,8 @@ static struct clk wdt3_ick = {
 
 static struct clk wdt3_fck = {
         .name           = "wdt3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
@@ -2200,8 +2196,8 @@ static struct clk wdt3_fck = {
 
 static struct clk mspro_ick = {
         .name           = "mspro_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
@@ -2210,8 +2206,8 @@ static struct clk mspro_ick = {
 
 static struct clk mspro_fck = {
         .name           = "mspro_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
@@ -2220,8 +2216,8 @@ static struct clk mspro_fck = {
 
 static struct clk mmc_ick = {
         .name           = "mmc_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
@@ -2230,8 +2226,8 @@ static struct clk mmc_ick = {
 
 static struct clk mmc_fck = {
         .name           = "mmc_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
@@ -2240,8 +2236,8 @@ static struct clk mmc_fck = {
 
 static struct clk fac_ick = {
         .name           = "fac_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
@@ -2250,8 +2246,8 @@ static struct clk fac_ick = {
 
 static struct clk fac_fck = {
         .name           = "fac_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_12m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
@@ -2260,8 +2256,8 @@ static struct clk fac_fck = {
 
 static struct clk eac_ick = {
         .name           = "eac_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
@@ -2270,8 +2266,8 @@ static struct clk eac_ick = {
 
 static struct clk eac_fck = {
         .name           = "eac_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
@@ -2280,8 +2276,8 @@ static struct clk eac_fck = {
 
 static struct clk hdq_ick = {
         .name           = "hdq_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
@@ -2290,8 +2286,8 @@ static struct clk hdq_ick = {
 
 static struct clk hdq_fck = {
         .name           = "hdq_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_12m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
@@ -2300,9 +2296,9 @@ static struct clk hdq_fck = {
 
 static struct clk i2c2_ick = {
         .name           = "i2c_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 2,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
@@ -2311,9 +2307,9 @@ static struct clk i2c2_ick = {
 
 static struct clk i2c2_fck = {
         .name           = "i2c_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 2,
         .parent         = &func_12m_ck,
-        .flags          = CLOCK_IN_OMAP242X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
@@ -2322,9 +2318,9 @@ static struct clk i2c2_fck = {
 
 static struct clk i2chs2_fck = {
         .name           = "i2c_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 2,
         .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
@@ -2333,9 +2329,9 @@ static struct clk i2chs2_fck = {
 
 static struct clk i2c1_ick = {
         .name           = "i2c_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 1,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
@@ -2344,9 +2340,9 @@ static struct clk i2c1_ick = {
 
 static struct clk i2c1_fck = {
         .name           = "i2c_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 1,
         .parent         = &func_12m_ck,
-        .flags          = CLOCK_IN_OMAP242X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
@@ -2355,9 +2351,9 @@ static struct clk i2c1_fck = {
 
 static struct clk i2chs1_fck = {
         .name           = "i2c_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 1,
         .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
@@ -2366,33 +2362,33 @@ static struct clk i2chs1_fck = {
 
 static struct clk gpmc_fck = {
         .name           = "gpmc_fck",
+        .ops            = &clkops_null, /* RMK: missing? */
         .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                ENABLE_ON_INIT,
+        .flags          = ENABLE_ON_INIT,
         .clkdm_name     = "core_l3_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk sdma_fck = {
         .name           = "sdma_fck",
+        .ops            = &clkops_null, /* RMK: missing? */
         .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l3_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk sdma_ick = {
         .name           = "sdma_ick",
+        .ops            = &clkops_null, /* RMK: missing? */
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l3_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk vlynq_ick = {
         .name           = "vlynq_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X,
         .clkdm_name     = "core_l3_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
@@ -2426,8 +2422,9 @@ static const struct clksel vlynq_fck_clksel[] = {
 
 static struct clk vlynq_fck = {
         .name           = "vlynq_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
+        .flags          = DELAYED_APP,
         .clkdm_name     = "core_l3_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
@@ -2442,8 +2439,9 @@ static struct clk vlynq_fck = {
 
 static struct clk sdrc_ick = {
         .name           = "sdrc_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
+        .flags          = ENABLE_ON_INIT,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
@@ -2452,8 +2450,8 @@ static struct clk sdrc_ick = {
 
 static struct clk des_ick = {
         .name           = "des_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
@@ -2462,8 +2460,8 @@ static struct clk des_ick = {
 
 static struct clk sha_ick = {
         .name           = "sha_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
@@ -2472,8 +2470,8 @@ static struct clk sha_ick = {
 
 static struct clk rng_ick = {
         .name           = "rng_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
@@ -2482,8 +2480,8 @@ static struct clk rng_ick = {
 
 static struct clk aes_ick = {
         .name           = "aes_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
@@ -2492,8 +2490,8 @@ static struct clk aes_ick = {
 
 static struct clk pka_ick = {
         .name           = "pka_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
@@ -2502,8 +2500,8 @@ static struct clk pka_ick = {
 
 static struct clk usb_fck = {
         .name           = "usb_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
         .clkdm_name     = "core_l3_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
@@ -2512,8 +2510,8 @@ static struct clk usb_fck = {
 
 static struct clk usbhs_ick = {
         .name           = "usbhs_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l3_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
@@ -2522,8 +2520,8 @@ static struct clk usbhs_ick = {
 
 static struct clk mmchs1_ick = {
         .name           = "mmchs_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
@@ -2532,8 +2530,8 @@ static struct clk mmchs1_ick = {
 
 static struct clk mmchs1_fck = {
         .name           = "mmchs_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l3_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
@@ -2542,9 +2540,9 @@ static struct clk mmchs1_fck = {
 
 static struct clk mmchs2_ick = {
         .name           = "mmchs_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 1,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
@@ -2553,9 +2551,9 @@ static struct clk mmchs2_ick = {
 
 static struct clk mmchs2_fck = {
         .name           = "mmchs_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 1,
         .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
         .recalc         = &followparent_recalc,
@@ -2563,8 +2561,8 @@ static struct clk mmchs2_fck = {
 
 static struct clk gpio5_ick = {
         .name           = "gpio5_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
@@ -2573,8 +2571,8 @@ static struct clk gpio5_ick = {
 
 static struct clk gpio5_fck = {
         .name           = "gpio5_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
@@ -2583,8 +2581,8 @@ static struct clk gpio5_fck = {
 
 static struct clk mdm_intc_ick = {
         .name           = "mdm_intc_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
@@ -2593,8 +2591,8 @@ static struct clk mdm_intc_ick = {
 
 static struct clk mmchsdb1_fck = {
         .name           = "mmchsdb_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
@@ -2603,9 +2601,9 @@ static struct clk mmchsdb1_fck = {
 
 static struct clk mmchsdb2_fck = {
         .name           = "mmchsdb_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 1,
         .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP243X,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
@@ -2628,166 +2626,13 @@ static struct clk mmchsdb2_fck = {
  */
 static struct clk virt_prcm_set = {
         .name           = "virt_prcm_set",
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
+        .ops            = &clkops_null,
+        .flags          = DELAYED_APP,
         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
         .set_rate       = &omap2_select_table_rate,
         .round_rate     = &omap2_round_to_table_rate,
 };
 
-static struct clk *onchip_24xx_clks[] __initdata = {
-        /* external root sources */
-        &func_32k_ck,
-        &osc_ck,
-        &sys_ck,
-        &alt_ck,
-        /* internal analog sources */
-        &dpll_ck,
-        &apll96_ck,
-        &apll54_ck,
-        /* internal prcm root sources */
-        &func_54m_ck,
-        &core_ck,
-        &func_96m_ck,
-        &func_48m_ck,
-        &func_12m_ck,
-        &wdt1_osc_ck,
-        &sys_clkout_src,
-        &sys_clkout,
-        &sys_clkout2_src,
-        &sys_clkout2,
-        &emul_ck,
-        /* mpu domain clocks */
-        &mpu_ck,
-        /* dsp domain clocks */
-        &dsp_fck,
-        &dsp_irate_ick,
-        &dsp_ick,               /* 242x */
-        &iva2_1_ick,            /* 243x */
-        &iva1_ifck,             /* 242x */
-        &iva1_mpu_int_ifck,     /* 242x */
-        /* GFX domain clocks */
-        &gfx_3d_fck,
-        &gfx_2d_fck,
-        &gfx_ick,
-        /* Modem domain clocks */
-        &mdm_ick,
-        &mdm_osc_ck,
-        /* DSS domain clocks */
-        &dss_ick,
-        &dss1_fck,
-        &dss2_fck,
-        &dss_54m_fck,
-        /* L3 domain clocks */
-        &core_l3_ck,
-        &ssi_ssr_sst_fck,
-        &usb_l4_ick,
-        /* L4 domain clocks */
-        &l4_ck,                 /* used as both core_l4 and wu_l4 */
-        /* virtual meta-group clock */
-        &virt_prcm_set,
-        /* general l4 interface ck, multi-parent functional clk */
-        &gpt1_ick,
-        &gpt1_fck,
-        &gpt2_ick,
-        &gpt2_fck,
-        &gpt3_ick,
-        &gpt3_fck,
-        &gpt4_ick,
-        &gpt4_fck,
-        &gpt5_ick,
-        &gpt5_fck,
-        &gpt6_ick,
-        &gpt6_fck,
-        &gpt7_ick,
-        &gpt7_fck,
-        &gpt8_ick,
-        &gpt8_fck,
-        &gpt9_ick,
-        &gpt9_fck,
-        &gpt10_ick,
-        &gpt10_fck,
-        &gpt11_ick,
-        &gpt11_fck,
-        &gpt12_ick,
-        &gpt12_fck,
-        &mcbsp1_ick,
-        &mcbsp1_fck,
-        &mcbsp2_ick,
-        &mcbsp2_fck,
-        &mcbsp3_ick,
-        &mcbsp3_fck,
-        &mcbsp4_ick,
-        &mcbsp4_fck,
-        &mcbsp5_ick,
-        &mcbsp5_fck,
-        &mcspi1_ick,
-        &mcspi1_fck,
-        &mcspi2_ick,
-        &mcspi2_fck,
-        &mcspi3_ick,
-        &mcspi3_fck,
-        &uart1_ick,
-        &uart1_fck,
-        &uart2_ick,
-        &uart2_fck,
-        &uart3_ick,
-        &uart3_fck,
-        &gpios_ick,
-        &gpios_fck,
-        &mpu_wdt_ick,
-        &mpu_wdt_fck,
-        &sync_32k_ick,
-        &wdt1_ick,
-        &omapctrl_ick,
-        &icr_ick,
-        &cam_fck,
-        &cam_ick,
-        &mailboxes_ick,
-        &wdt4_ick,
-        &wdt4_fck,
-        &wdt3_ick,
-        &wdt3_fck,
-        &mspro_ick,
-        &mspro_fck,
-        &mmc_ick,
-        &mmc_fck,
-        &fac_ick,
-        &fac_fck,
-        &eac_ick,
-        &eac_fck,
-        &hdq_ick,
-        &hdq_fck,
-        &i2c1_ick,
-        &i2c1_fck,
-        &i2chs1_fck,
-        &i2c2_ick,
-        &i2c2_fck,
-        &i2chs2_fck,
-        &gpmc_fck,
-        &sdma_fck,
-        &sdma_ick,
-        &vlynq_ick,
-        &vlynq_fck,
-        &sdrc_ick,
-        &des_ick,
-        &sha_ick,
-        &rng_ick,
-        &aes_ick,
-        &pka_ick,
-        &usb_fck,
-        &usbhs_ick,
-        &mmchs1_ick,
-        &mmchs1_fck,
-        &mmchs2_ick,
-        &mmchs2_fck,
-        &gpio5_ick,
-        &gpio5_fck,
-        &mdm_intc_ick,
-        &mmchsdb1_fck,
-        &mmchsdb2_fck,
-};
-
 #endif
 
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 31bb7010bd48..0a14dca31e30 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -30,15 +30,251 @@
 #include <mach/clock.h>
 #include <mach/sram.h>
 #include <asm/div64.h>
+#include <asm/clkdev.h>
 
-#include "memory.h"
+#include <mach/sdrc.h>
 #include "clock.h"
-#include "clock34xx.h"
 #include "prm.h"
 #include "prm-regbits-34xx.h"
 #include "cm.h"
 #include "cm-regbits-34xx.h"
 
+static const struct clkops clkops_noncore_dpll_ops;
+
+#include "clock34xx.h"
+
+struct omap_clk {
+        u32             cpu;
+        struct clk_lookup lk;
+};
+
+#define CLK(dev, con, ck, cp)           \
+        {                               \
+                 .cpu = cp,             \
+                .lk = {                 \
+                        .dev_id = dev,  \
+                        .con_id = con,  \
+                        .clk = ck,      \
+                },                      \
+        }
+
+#define CK_343X         (1 << 0)
+#define CK_3430ES1      (1 << 1)
+#define CK_3430ES2      (1 << 2)
+
+static struct omap_clk omap34xx_clks[] = {
+        CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_343X),
+        CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_343X),
+        CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_343X),
+        CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
+        CLK(NULL,       "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
+        CLK(NULL,       "virt_26m_ck",  &virt_26m_ck,   CK_343X),
+        CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
+        CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_343X),
+        CLK(NULL,       "sys_ck",       &sys_ck,        CK_343X),
+        CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_343X),
+        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_343X),
+        CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_343X),
+        CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_343X),
+        CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_343X),
+        CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
+        CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_343X),
+        CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_343X),
+        CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_343X),
+        CLK(NULL,       "core_ck",      &core_ck,       CK_343X),
+        CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_343X),
+        CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_343X),
+        CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
+        CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_343X),
+        CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
+        CLK(NULL,       "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
+        CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_343X),
+        CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_343X),
+        CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
+        CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_343X),
+        CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_343X),
+        CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_343X),
+        CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_343X),
+        CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_343X),
+        CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_343X),
+        CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
+        CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_343X),
+        CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
+        CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_343X),
+        CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
+        CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_343X),
+        CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
+        CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_343X),
+        CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
+        CLK(NULL,       "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
+        CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2),
+        CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2),
+        CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_343X),
+        CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_343X),
+        CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_343X),
+        CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_343X),
+        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_343X),
+        CLK(NULL,       "arm_fck",      &arm_fck,       CK_343X),
+        CLK(NULL,       "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
+        CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_343X),
+        CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_343X),
+        CLK(NULL,       "l3_ick",       &l3_ick,        CK_343X),
+        CLK(NULL,       "l4_ick",       &l4_ick,        CK_343X),
+        CLK(NULL,       "rm_ick",       &rm_ick,        CK_343X),
+        CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck,     CK_3430ES1),
+        CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck,    CK_3430ES1),
+        CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
+        CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
+        CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
+        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2),
+        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2),
+        CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
+        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_343X),
+        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_343X),
+        CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2),
+        CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2),
+        CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2),
+        CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_343X),
+        CLK("mmci-omap-hs.2",   "fck",  &mmchs3_fck,    CK_3430ES2),
+        CLK("mmci-omap-hs.1",   "fck",  &mmchs2_fck,    CK_343X),
+        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_343X),
+        CLK("mmci-omap-hs.0",   "fck",  &mmchs1_fck,    CK_343X),
+        CLK("i2c_omap.3", "fck",        &i2c3_fck,      CK_343X),
+        CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_343X),
+        CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_343X),
+        CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_343X),
+        CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_343X),
+        CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_343X),
+        CLK("omap2_mcspi.4", "fck",     &mcspi4_fck,    CK_343X),
+        CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_343X),
+        CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_343X),
+        CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_343X),
+        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_343X),
+        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_343X),
+        CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
+        CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_343X),
+        CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_343X),
+        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck,   CK_343X),
+        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck,   CK_343X),
+        CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_343X),
+        CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick,  CK_343X),
+        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_343X),
+        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_343X),
+        CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_343X),
+        CLK(NULL,       "pka_ick",      &pka_ick,       CK_343X),
+        CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_343X),
+        CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2),
+        CLK("mmci-omap-hs.2",   "ick",  &mmchs3_ick,    CK_3430ES2),
+        CLK(NULL,       "icr_ick",      &icr_ick,       CK_343X),
+        CLK(NULL,       "aes2_ick",     &aes2_ick,      CK_343X),
+        CLK(NULL,       "sha12_ick",    &sha12_ick,     CK_343X),
+        CLK(NULL,       "des2_ick",     &des2_ick,      CK_343X),
+        CLK("mmci-omap-hs.1",   "ick",  &mmchs2_ick,    CK_343X),
+        CLK("mmci-omap-hs.0",   "ick",  &mmchs1_ick,    CK_343X),
+        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_343X),
+        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_343X),
+        CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_343X),
+        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_343X),
+        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_343X),
+        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_343X),
+        CLK("i2c_omap.3", "ick",        &i2c3_ick,      CK_343X),
+        CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_343X),
+        CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_343X),
+        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_343X),
+        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_343X),
+        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_343X),
+        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_343X),
+        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_343X),
+        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_343X),
+        CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
+        CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_343X),
+        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_343X),
+        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_343X),
+        CLK(NULL,       "ssi_ick",      &ssi_ick,       CK_343X),
+        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
+        CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_343X),
+        CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_343X),
+        CLK("omap_rng", "ick",          &rng_ick,       CK_343X),
+        CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_343X),
+        CLK(NULL,       "des1_ick",     &des1_ick,      CK_343X),
+        CLK(NULL,       "dss1_alwon_fck", &dss1_alwon_fck, CK_343X),
+        CLK(NULL,       "dss_tv_fck",   &dss_tv_fck,    CK_343X),
+        CLK(NULL,       "dss_96m_fck",  &dss_96m_fck,   CK_343X),
+        CLK(NULL,       "dss2_alwon_fck", &dss2_alwon_fck, CK_343X),
+        CLK(NULL,       "dss_ick",      &dss_ick,       CK_343X),
+        CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_343X),
+        CLK(NULL,       "cam_ick",      &cam_ick,       CK_343X),
+        CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_343X),
+        CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
+        CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
+        CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2),
+        CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2),
+        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_343X),
+        CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_343X),
+        CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_343X),
+        CLK("omap_wdt", "fck",          &wdt2_fck,      CK_343X),
+        CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_343X),
+        CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2),
+        CLK("omap_wdt", "ick",          &wdt2_ick,      CK_343X),
+        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_343X),
+        CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_343X),
+        CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
+        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_343X),
+        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_343X),
+        CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_343X),
+        CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_343X),
+        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_343X),
+        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_343X),
+        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_343X),
+        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_343X),
+        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_343X),
+        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_343X),
+        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_343X),
+        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_343X),
+        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_343X),
+        CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
+        CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_343X),
+        CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_343X),
+        CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_343X),
+        CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_343X),
+        CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_343X),
+        CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_343X),
+        CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_343X),
+        CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_343X),
+        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_343X),
+        CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_343X),
+        CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_343X),
+        CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_343X),
+        CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_343X),
+        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_343X),
+        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_343X),
+        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_343X),
+        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_343X),
+        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_343X),
+        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_343X),
+        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_343X),
+        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_343X),
+        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_343X),
+        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_343X),
+        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_343X),
+        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_343X),
+        CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_343X),
+        CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_343X),
+        CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_343X),
+        CLK(NULL,       "emu_src_ck",   &emu_src_ck,    CK_343X),
+        CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_343X),
+        CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_343X),
+        CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_343X),
+        CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_343X),
+        CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_343X),
+        CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_343X),
+        CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_343X),
+        CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_343X),
+        CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_343X),
+        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_343X),
+        CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_343X),
+};
+
 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
 #define DPLL_AUTOIDLE_DISABLE                   0x0
 #define DPLL_AUTOIDLE_LOW_POWER_STOP            0x1
@@ -51,11 +287,9 @@
  *
  * Recalculate and propagate the DPLL rate.
  */
-static void omap3_dpll_recalc(struct clk *clk)
+static unsigned long omap3_dpll_recalc(struct clk *clk)
 {
-        clk->rate = omap2_get_dpll_rate(clk);
-
-        propagate_rate(clk);
+        return omap2_get_dpll_rate(clk);
 }
 
 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
@@ -78,14 +312,12 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
         const struct dpll_data *dd;
         int i = 0;
         int ret = -EINVAL;
-        u32 idlest_mask;
 
         dd = clk->dpll_data;
 
-        state <<= dd->idlest_bit;
-        idlest_mask = 1 << dd->idlest_bit;
+        state <<= __ffs(dd->idlest_mask);
 
-        while (((__raw_readl(dd->idlest_reg) & idlest_mask) != state) &&
+        while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
                i < MAX_DPLL_WAIT_TRIES) {
                 i++;
                 udelay(1);
@@ -104,6 +336,42 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
         return ret;
 }
 
+/* From 3430 TRM ES2 4.7.6.2 */
+static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
+{
+        unsigned long fint;
+        u16 f = 0;
+
+        fint = clk->dpll_data->clk_ref->rate / (n + 1);
+
+        pr_debug("clock: fint is %lu\n", fint);
+
+        if (fint >= 750000 && fint <= 1000000)
+                f = 0x3;
+        else if (fint > 1000000 && fint <= 1250000)
+                f = 0x4;
+        else if (fint > 1250000 && fint <= 1500000)
+                f = 0x5;
+        else if (fint > 1500000 && fint <= 1750000)
+                f = 0x6;
+        else if (fint > 1750000 && fint <= 2100000)
+                f = 0x7;
+        else if (fint > 7500000 && fint <= 10000000)
+                f = 0xB;
+        else if (fint > 10000000 && fint <= 12500000)
+                f = 0xC;
+        else if (fint > 12500000 && fint <= 15000000)
+                f = 0xD;
+        else if (fint > 15000000 && fint <= 17500000)
+                f = 0xE;
+        else if (fint > 17500000 && fint <= 21000000)
+                f = 0xF;
+        else
+                pr_debug("clock: unknown freqsel setting for %d\n", n);
+
+        return f;
+}
+
 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
 
 /*
@@ -128,25 +396,20 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
 
         ai = omap3_dpll_autoidle_read(clk);
 
+        omap3_dpll_deny_idle(clk);
+
         _omap3_dpll_write_clken(clk, DPLL_LOCKED);
 
-        if (ai) {
-                /*
-                 * If no downstream clocks are enabled, CM_IDLEST bit
-                 * may never become active, so don't wait for DPLL to lock.
-                 */
-                r = 0;
+        r = _omap3_wait_dpll_status(clk, 1);
+
+        if (ai)
                 omap3_dpll_allow_idle(clk);
-        } else {
-                r = _omap3_wait_dpll_status(clk, 1);
-                omap3_dpll_deny_idle(clk);
-        };
 
         return r;
 }
 
 /*
- * omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
+ * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
  * @clk: pointer to a DPLL struct clk
  *
  * Instructs a non-CORE DPLL to enter low-power bypass mode.  In
@@ -236,14 +499,25 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
 static int omap3_noncore_dpll_enable(struct clk *clk)
 {
         int r;
+        struct dpll_data *dd;
 
         if (clk == &dpll3_ck)
                 return -EINVAL;
 
-        if (clk->parent->rate == clk_get_rate(clk))
+        dd = clk->dpll_data;
+        if (!dd)
+                return -EINVAL;
+
+        if (clk->rate == dd->clk_bypass->rate) {
+                WARN_ON(clk->parent != dd->clk_bypass);
                 r = _omap3_noncore_dpll_bypass(clk);
-        else
+        } else {
+                WARN_ON(clk->parent != dd->clk_ref);
                 r = _omap3_noncore_dpll_lock(clk);
+        }
+        /* FIXME: this is dubious - if clk->rate has changed, what about propagating? */
+        if (!r)
+                clk->rate = omap2_get_dpll_rate(clk);
 
         return r;
 }
@@ -270,6 +544,215 @@ static void omap3_noncore_dpll_disable(struct clk *clk)
         _omap3_noncore_dpll_stop(clk);
 }
 
+
+/* Non-CORE DPLL rate set code */
+
+/*
+ * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
+ * @clk: struct clk * of DPLL to set
+ * @m: DPLL multiplier to set
+ * @n: DPLL divider to set
+ * @freqsel: FREQSEL value to set
+ *
+ * Program the DPLL with the supplied M, N values, and wait for the DPLL to
+ * lock..  Returns -EINVAL upon error, or 0 upon success.
+ */
+static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
+{
+        struct dpll_data *dd = clk->dpll_data;
+        u32 v;
+
+        /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
+        _omap3_noncore_dpll_bypass(clk);
+
+        /* Set jitter correction */
+        v = __raw_readl(dd->control_reg);
+        v &= ~dd->freqsel_mask;
+        v |= freqsel << __ffs(dd->freqsel_mask);
+        __raw_writel(v, dd->control_reg);
+
+        /* Set DPLL multiplier, divider */
+        v = __raw_readl(dd->mult_div1_reg);
+        v &= ~(dd->mult_mask | dd->div1_mask);
+        v |= m << __ffs(dd->mult_mask);
+        v |= (n - 1) << __ffs(dd->div1_mask);
+        __raw_writel(v, dd->mult_div1_reg);
+
+        /* We let the clock framework set the other output dividers later */
+
+        /* REVISIT: Set ramp-up delay? */
+
+        _omap3_noncore_dpll_lock(clk);
+
+        return 0;
+}
+
+/**
+ * omap3_noncore_dpll_set_rate - set non-core DPLL rate
+ * @clk: struct clk * of DPLL to set
+ * @rate: rounded target rate
+ *
+ * Set the DPLL CLKOUT to the target rate.  If the DPLL can enter
+ * low-power bypass, and the target rate is the bypass source clock
+ * rate, then configure the DPLL for bypass.  Otherwise, round the
+ * target rate if it hasn't been done already, then program and lock
+ * the DPLL.  Returns -EINVAL upon error, or 0 upon success.
+ */
+static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
+{
+        struct clk *new_parent = NULL;
+        u16 freqsel;
+        struct dpll_data *dd;
+        int ret;
+
+        if (!clk || !rate)
+                return -EINVAL;
+
+        dd = clk->dpll_data;
+        if (!dd)
+                return -EINVAL;
+
+        if (rate == omap2_get_dpll_rate(clk))
+                return 0;
+
+        /*
+         * Ensure both the bypass and ref clocks are enabled prior to
+         * doing anything; we need the bypass clock running to reprogram
+         * the DPLL.
+         */
+        omap2_clk_enable(dd->clk_bypass);
+        omap2_clk_enable(dd->clk_ref);
+
+        if (dd->clk_bypass->rate == rate &&
+            (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
+                pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
+
+                ret = _omap3_noncore_dpll_bypass(clk);
+                if (!ret)
+                        new_parent = dd->clk_bypass;
+        } else {
+                if (dd->last_rounded_rate != rate)
+                        omap2_dpll_round_rate(clk, rate);
+
+                if (dd->last_rounded_rate == 0)
+                        return -EINVAL;
+
+                freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
+                if (!freqsel)
+                        WARN_ON(1);
+
+                pr_debug("clock: %s: set rate: locking rate to %lu.\n",
+                         clk->name, rate);
+
+                ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
+                                                 dd->last_rounded_n, freqsel);
+                if (!ret)
+                        new_parent = dd->clk_ref;
+        }
+        if (!ret) {
+                /*
+                 * Switch the parent clock in the heirarchy, and make sure
+                 * that the new parent's usecount is correct.  Note: we
+                 * enable the new parent before disabling the old to avoid
+                 * any unnecessary hardware disable->enable transitions.
+                 */
+                if (clk->usecount) {
+                        omap2_clk_enable(new_parent);
+                        omap2_clk_disable(clk->parent);
+                }
+                clk_reparent(clk, new_parent);
+                clk->rate = rate;
+        }
+        omap2_clk_disable(dd->clk_ref);
+        omap2_clk_disable(dd->clk_bypass);
+
+        return 0;
+}
+
+static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
+{
+        /*
+         * According to the 12-5 CDP code from TI, "Limitation 2.5"
+         * on 3430ES1 prevents us from changing DPLL multipliers or dividers
+         * on DPLL4.
+         */
+        if (omap_rev() == OMAP3430_REV_ES1_0) {
+                printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
+                       "silicon 'Limitation 2.5' on 3430ES1.\n");
+                return -EINVAL;
+        }
+        return omap3_noncore_dpll_set_rate(clk, rate);
+}
+
+
+/*
+ * CORE DPLL (DPLL3) rate programming functions
+ *
+ * These call into SRAM code to do the actual CM writes, since the SDRAM
+ * is clocked from DPLL3.
+ */
+
+/**
+ * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
+ * @clk: struct clk * of DPLL to set
+ * @rate: rounded target rate
+ *
+ * Program the DPLL M2 divider with the rounded target rate.  Returns
+ * -EINVAL upon error, or 0 upon success.
+ */
+static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 new_div = 0;
+        unsigned long validrate, sdrcrate;
+        struct omap_sdrc_params *sp;
+
+        if (!clk || !rate)
+                return -EINVAL;
+
+        if (clk != &dpll3_m2_ck)
+                return -EINVAL;
+
+        if (rate == clk->rate)
+                return 0;
+
+        validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
+        if (validrate != rate)
+                return -EINVAL;
+
+        sdrcrate = sdrc_ick.rate;
+        if (rate > clk->rate)
+                sdrcrate <<= ((rate / clk->rate) - 1);
+        else
+                sdrcrate >>= ((clk->rate / rate) - 1);
+
+        sp = omap2_sdrc_get_params(sdrcrate);
+        if (!sp)
+                return -EINVAL;
+
+        pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
+                validrate);
+        pr_info("clock: SDRC timing params used: %08x %08x %08x\n",
+                sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
+
+        /* REVISIT: SRAM code doesn't support other M2 divisors yet */
+        WARN_ON(new_div != 1 && new_div != 2);
+
+        /* REVISIT: Add SDRC_MR changing to this code also */
+        omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
+                                  sp->actim_ctrlb, new_div);
+
+        return 0;
+}
+
+
+static const struct clkops clkops_noncore_dpll_ops = {
+        .enable         = &omap3_noncore_dpll_enable,
+        .disable        = &omap3_noncore_dpll_disable,
+};
+
+/* DPLL autoidle read/set code */
+
+
 /**
  * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
  * @clk: struct clk * of the DPLL to read
@@ -356,9 +839,10 @@ static void omap3_dpll_deny_idle(struct clk *clk)
  * Using parent clock DPLL data, look up DPLL state.  If locked, set our
  * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
  */
-static void omap3_clkoutx2_recalc(struct clk *clk)
+static unsigned long omap3_clkoutx2_recalc(struct clk *clk)
 {
         const struct dpll_data *dd;
+        unsigned long rate;
         u32 v;
         struct clk *pclk;
 
@@ -372,17 +856,15 @@ static void omap3_clkoutx2_recalc(struct clk *clk)
 
         dd = pclk->dpll_data;
 
-        WARN_ON(!dd->control_reg || !dd->enable_mask);
+        WARN_ON(!dd->enable_mask);
 
         v = __raw_readl(dd->control_reg) & dd->enable_mask;
         v >>= __ffs(dd->enable_mask);
-        if (v != DPLL_LOCKED)
-                clk->rate = clk->parent->rate;
+        if (v != OMAP3XXX_EN_DPLL_LOCKED)
+                rate = clk->parent->rate;
         else
-                clk->rate = clk->parent->rate * 2;
-
-        if (clk->flags & RATE_PROPAGATES)
-                propagate_rate(clk);
+                rate = clk->parent->rate * 2;
+        return rate;
 }
 
 /* Common clock code */
@@ -432,7 +914,7 @@ static int __init omap2_clk_arch_init(void)
 
         /* REVISIT: not yet ready for 343x */
 #if 0
-        if (omap2_select_table_rate(&virt_prcm_set, mpurate))
+        if (clk_set_rate(&virt_prcm_set, mpurate))
                 printk(KERN_ERR "Could not find matching MPU rate\n");
 #endif
 
@@ -450,26 +932,13 @@ arch_initcall(omap2_clk_arch_init);
 int __init omap2_clk_init(void)
 {
         /* struct prcm_config *prcm; */
-        struct clk **clkp;
+        struct omap_clk *c;
         /* u32 clkrate; */
         u32 cpu_clkflg;
 
-        /* REVISIT: Ultimately this will be used for multiboot */
-#if 0
-        if (cpu_is_omap242x()) {
-                cpu_mask = RATE_IN_242X;
-                cpu_clkflg = CLOCK_IN_OMAP242X;
-                clkp = onchip_24xx_clks;
-        } else if (cpu_is_omap2430()) {
-                cpu_mask = RATE_IN_243X;
-                cpu_clkflg = CLOCK_IN_OMAP243X;
-                clkp = onchip_24xx_clks;
-        }
-#endif
         if (cpu_is_omap34xx()) {
                 cpu_mask = RATE_IN_343X;
-                cpu_clkflg = CLOCK_IN_OMAP343X;
-                clkp = onchip_34xx_clks;
+                cpu_clkflg = CK_343X;
 
                 /*
                  * Update this if there are further clock changes between ES2
@@ -477,23 +946,24 @@ int __init omap2_clk_init(void)
                  */
                 if (omap_rev() == OMAP3430_REV_ES1_0) {
                         /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
-                        cpu_clkflg |= CLOCK_IN_OMAP3430ES1;
+                        cpu_clkflg |= CK_3430ES1;
                 } else {
                         cpu_mask |= RATE_IN_3430ES2;
-                        cpu_clkflg |= CLOCK_IN_OMAP3430ES2;
+                        cpu_clkflg |= CK_3430ES2;
                 }
         }
 
         clk_init(&omap2_clk_functions);
 
-        for (clkp = onchip_34xx_clks;
-             clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
-             clkp++) {
-                if ((*clkp)->flags & cpu_clkflg) {
-                        clk_register(*clkp);
-                        omap2_init_clk_clkdm(*clkp);
+        for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
+                clk_init_one(c->lk.clk);
+
+        for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
+                if (c->cpu & cpu_clkflg) {
+                        clkdev_add(&c->lk);
+                        clk_register(c->lk.clk);
+                        omap2_init_clk_clkdm(c->lk.clk);
                 }
-        }
 
         /* REVISIT: Not yet ready for OMAP3 */
 #if 0
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index a826094d89b5..70ec10deb654 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -27,13 +27,14 @@
 #include "prm.h"
 #include "prm-regbits-34xx.h"
 
-static void omap3_dpll_recalc(struct clk *clk);
-static void omap3_clkoutx2_recalc(struct clk *clk);
+static unsigned long omap3_dpll_recalc(struct clk *clk);
+static unsigned long omap3_clkoutx2_recalc(struct clk *clk);
 static void omap3_dpll_allow_idle(struct clk *clk);
 static void omap3_dpll_deny_idle(struct clk *clk);
 static u32 omap3_dpll_autoidle_read(struct clk *clk);
-static int omap3_noncore_dpll_enable(struct clk *clk);
-static void omap3_noncore_dpll_disable(struct clk *clk);
+static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
+static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
+static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
 
 /* Maximum DPLL multiplier, divider values for OMAP3 */
 #define OMAP3_MAX_DPLL_MULT             2048
@@ -47,6 +48,10 @@ static void omap3_noncore_dpll_disable(struct clk *clk);
  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  */
 
+/* Forward declarations for DPLL bypass clocks */
+static struct clk dpll1_fck;
+static struct clk dpll2_fck;
+
 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
 #define DPLL_LOW_POWER_STOP             0x1
 #define DPLL_LOW_POWER_BYPASS           0x5
@@ -57,67 +62,59 @@ static void omap3_noncore_dpll_disable(struct clk *clk);
 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
 static struct clk omap_32k_fck = {
         .name           = "omap_32k_fck",
+        .ops            = &clkops_null,
         .rate           = 32768,
-        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
-                                ALWAYS_ENABLED,
-        .recalc         = &propagate_rate,
+        .flags          = RATE_FIXED,
 };
 
 static struct clk secure_32k_fck = {
         .name           = "secure_32k_fck",
+        .ops            = &clkops_null,
         .rate           = 32768,
-        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
-                                ALWAYS_ENABLED,
-        .recalc         = &propagate_rate,
+        .flags          = RATE_FIXED,
 };
 
 /* Virtual source clocks for osc_sys_ck */
 static struct clk virt_12m_ck = {
         .name           = "virt_12m_ck",
+        .ops            = &clkops_null,
         .rate           = 12000000,
-        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
-                                ALWAYS_ENABLED,
-        .recalc         = &propagate_rate,
+        .flags          = RATE_FIXED,
 };
 
 static struct clk virt_13m_ck = {
         .name           = "virt_13m_ck",
+        .ops            = &clkops_null,
         .rate           = 13000000,
-        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
-                                ALWAYS_ENABLED,
-        .recalc         = &propagate_rate,
+        .flags          = RATE_FIXED,
 };
 
 static struct clk virt_16_8m_ck = {
         .name           = "virt_16_8m_ck",
+        .ops            = &clkops_null,
         .rate           = 16800000,
-        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
-                                ALWAYS_ENABLED,
-        .recalc         = &propagate_rate,
+        .flags          = RATE_FIXED,
 };
 
 static struct clk virt_19_2m_ck = {
         .name           = "virt_19_2m_ck",
+        .ops            = &clkops_null,
         .rate           = 19200000,
-        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
-                                ALWAYS_ENABLED,
-        .recalc         = &propagate_rate,
+        .flags          = RATE_FIXED,
 };
 
 static struct clk virt_26m_ck = {
         .name           = "virt_26m_ck",
+        .ops            = &clkops_null,
         .rate           = 26000000,
-        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
-                                ALWAYS_ENABLED,
-        .recalc         = &propagate_rate,
+        .flags          = RATE_FIXED,
 };
 
 static struct clk virt_38_4m_ck = {
         .name           = "virt_38_4m_ck",
+        .ops            = &clkops_null,
         .rate           = 38400000,
-        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
-                                ALWAYS_ENABLED,
-        .recalc         = &propagate_rate,
+        .flags          = RATE_FIXED,
 };
 
 static const struct clksel_rate osc_sys_12m_rates[] = {
@@ -164,13 +161,13 @@ static const struct clksel osc_sys_clksel[] = {
 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 static struct clk osc_sys_ck = {
         .name           = "osc_sys_ck",
+        .ops            = &clkops_null,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP3430_PRM_CLKSEL,
         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
         .clksel         = osc_sys_clksel,
         /* REVISIT: deal with autoextclkmode? */
-        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
-                                ALWAYS_ENABLED,
+        .flags          = RATE_FIXED,
         .recalc         = &omap2_clksel_recalc,
 };
 
@@ -189,36 +186,34 @@ static const struct clksel sys_clksel[] = {
 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 static struct clk sys_ck = {
         .name           = "sys_ck",
+        .ops            = &clkops_null,
         .parent         = &osc_sys_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
         .clksel         = sys_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
         .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk sys_altclk = {
         .name           = "sys_altclk",
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
-        .recalc         = &propagate_rate,
+        .ops            = &clkops_null,
 };
 
 /* Optional external clock input for some McBSPs */
 static struct clk mcbsp_clks = {
         .name           = "mcbsp_clks",
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
-        .recalc         = &propagate_rate,
+        .ops            = &clkops_null,
 };
 
 /* PRM EXTERNAL CLOCK OUTPUT */
 
 static struct clk sys_clkout1 = {
         .name           = "sys_clkout1",
+        .ops            = &clkops_omap2_dflt,
         .parent         = &osc_sys_ck,
         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .recalc         = &followparent_recalc,
 };
 
@@ -226,16 +221,6 @@ static struct clk sys_clkout1 = {
 
 /* CM CLOCKS */
 
-static const struct clksel_rate dpll_bypass_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate dpll_locked_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
 static const struct clksel_rate div16_dpll_rates[] = {
         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
         { .div = 2, .val = 2, .flags = RATE_IN_343X },
@@ -263,6 +248,9 @@ static struct dpll_data dpll1_dd = {
         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
+        .clk_bypass     = &dpll1_fck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
@@ -272,18 +260,21 @@ static struct dpll_data dpll1_dd = {
         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
-        .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
+        .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
         .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
         .max_divider    = OMAP3_MAX_DPLL_DIV,
         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct clk dpll1_ck = {
         .name           = "dpll1_ck",
+        .ops            = &clkops_null,
         .parent         = &sys_ck,
         .dpll_data      = &dpll1_dd,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
         .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .clkdm_name     = "dpll1_clkdm",
         .recalc         = &omap3_dpll_recalc,
 };
 
@@ -293,9 +284,9 @@ static struct clk dpll1_ck = {
  */
 static struct clk dpll1_x2_ck = {
         .name           = "dpll1_x2_ck",
+        .ops            = &clkops_null,
         .parent         = &dpll1_ck,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
+        .clkdm_name     = "dpll1_clkdm",
         .recalc         = &omap3_clkoutx2_recalc,
 };
 
@@ -311,13 +302,13 @@ static const struct clksel div16_dpll1_x2m2_clksel[] = {
  */
 static struct clk dpll1_x2m2_ck = {
         .name           = "dpll1_x2m2_ck",
+        .ops            = &clkops_null,
         .parent         = &dpll1_x2_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
         .clksel         = div16_dpll1_x2m2_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
+        .clkdm_name     = "dpll1_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
@@ -329,6 +320,9 @@ static struct dpll_data dpll2_dd = {
         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
+        .clk_bypass     = &dpll2_fck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
@@ -339,20 +333,21 @@ static struct dpll_data dpll2_dd = {
         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
-        .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
+        .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
         .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
         .max_divider    = OMAP3_MAX_DPLL_DIV,
         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct clk dpll2_ck = {
         .name           = "dpll2_ck",
+        .ops            = &clkops_noncore_dpll_ops,
         .parent         = &sys_ck,
         .dpll_data      = &dpll2_dd,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
-        .enable         = &omap3_noncore_dpll_enable,
-        .disable        = &omap3_noncore_dpll_disable,
         .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .clkdm_name     = "dpll2_clkdm",
         .recalc         = &omap3_dpll_recalc,
 };
 
@@ -367,14 +362,14 @@ static const struct clksel div16_dpll2_m2x2_clksel[] = {
  */
 static struct clk dpll2_m2_ck = {
         .name           = "dpll2_m2_ck",
+        .ops            = &clkops_null,
         .parent         = &dpll2_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
                                           OMAP3430_CM_CLKSEL2_PLL),
         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
         .clksel         = div16_dpll2_m2x2_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
+        .clkdm_name     = "dpll2_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
@@ -387,6 +382,9 @@ static struct dpll_data dpll3_dd = {
         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
+        .clk_bypass     = &sys_ck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
@@ -394,17 +392,21 @@ static struct dpll_data dpll3_dd = {
         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
         .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
         .max_divider    = OMAP3_MAX_DPLL_DIV,
         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct clk dpll3_ck = {
         .name           = "dpll3_ck",
+        .ops            = &clkops_null,
         .parent         = &sys_ck,
         .dpll_data      = &dpll3_dd,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
         .round_rate     = &omap2_dpll_round_rate,
+        .clkdm_name     = "dpll3_clkdm",
         .recalc         = &omap3_dpll_recalc,
 };
 
@@ -414,9 +416,9 @@ static struct clk dpll3_ck = {
  */
 static struct clk dpll3_x2_ck = {
         .name           = "dpll3_x2_ck",
+        .ops            = &clkops_null,
         .parent         = &dpll3_ck,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
+        .clkdm_name     = "dpll3_clkdm",
         .recalc         = &omap3_clkoutx2_recalc,
 };
 
@@ -460,55 +462,34 @@ static const struct clksel div31_dpll3m2_clksel[] = {
         { .parent = NULL }
 };
 
-/*
- * DPLL3 output M2
- * REVISIT: This DPLL output divider must be changed in SRAM, so until
- * that code is ready, this should remain a 'read-only' clksel clock.
- */
+/* DPLL3 output M2 - primary control point for CORE speed */
 static struct clk dpll3_m2_ck = {
         .name           = "dpll3_m2_ck",
+        .ops            = &clkops_null,
         .parent         = &dpll3_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
         .clksel         = div31_dpll3m2_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
+        .clkdm_name     = "dpll3_clkdm",
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap3_core_dpll_m2_set_rate,
         .recalc         = &omap2_clksel_recalc,
 };
 
-static const struct clksel core_ck_clksel[] = {
-        { .parent = &sys_ck,      .rates = dpll_bypass_rates },
-        { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
-        { .parent = NULL }
-};
-
 static struct clk core_ck = {
         .name           = "core_ck",
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
-        .clksel         = core_ck_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static const struct clksel dpll3_m2x2_ck_clksel[] = {
-        { .parent = &sys_ck,      .rates = dpll_bypass_rates },
-        { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
-        { .parent = NULL }
+        .ops            = &clkops_null,
+        .parent         = &dpll3_m2_ck,
+        .recalc         = &followparent_recalc,
 };
 
 static struct clk dpll3_m2x2_ck = {
         .name           = "dpll3_m2x2_ck",
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
-        .clksel         = dpll3_m2x2_ck_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
-        .recalc         = &omap2_clksel_recalc,
+        .ops            = &clkops_null,
+        .parent         = &dpll3_x2_ck,
+        .clkdm_name     = "dpll3_clkdm",
+        .recalc         = &followparent_recalc,
 };
 
 /* The PWRDN bit is apparently only available on 3430ES2 and above */
@@ -520,42 +501,34 @@ static const struct clksel div16_dpll3_clksel[] = {
 /* This virtual clock is the source for dpll3_m3x2_ck */
 static struct clk dpll3_m3_ck = {
         .name           = "dpll3_m3_ck",
+        .ops            = &clkops_null,
         .parent         = &dpll3_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
         .clksel         = div16_dpll3_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
+        .clkdm_name     = "dpll3_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 static struct clk dpll3_m3x2_ck = {
         .name           = "dpll3_m3x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &dpll3_m3_ck,
         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll3_clkdm",
         .recalc         = &omap3_clkoutx2_recalc,
 };
 
-static const struct clksel emu_core_alwon_ck_clksel[] = {
-        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
-        { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
-        { .parent = NULL }
-};
-
 static struct clk emu_core_alwon_ck = {
         .name           = "emu_core_alwon_ck",
+        .ops            = &clkops_null,
         .parent         = &dpll3_m3x2_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
-        .clksel         = emu_core_alwon_ck_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
-        .recalc         = &omap2_clksel_recalc,
+        .clkdm_name     = "dpll3_clkdm",
+        .recalc         = &followparent_recalc,
 };
 
 /* DPLL4 */
@@ -565,6 +538,9 @@ static struct dpll_data dpll4_dd = {
         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
+        .clk_bypass     = &sys_ck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
@@ -574,20 +550,21 @@ static struct dpll_data dpll4_dd = {
         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
+        .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
         .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
         .max_divider    = OMAP3_MAX_DPLL_DIV,
         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct clk dpll4_ck = {
         .name           = "dpll4_ck",
+        .ops            = &clkops_noncore_dpll_ops,
         .parent         = &sys_ck,
         .dpll_data      = &dpll4_dd,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
-        .enable         = &omap3_noncore_dpll_enable,
-        .disable        = &omap3_noncore_dpll_disable,
         .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_dpll4_set_rate,
+        .clkdm_name     = "dpll4_clkdm",
         .recalc         = &omap3_dpll_recalc,
 };
 
@@ -598,9 +575,9 @@ static struct clk dpll4_ck = {
  */
 static struct clk dpll4_x2_ck = {
         .name           = "dpll4_x2_ck",
+        .ops            = &clkops_null,
         .parent         = &dpll4_ck,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
+        .clkdm_name     = "dpll4_clkdm",
         .recalc         = &omap3_clkoutx2_recalc,
 };
 
@@ -612,112 +589,101 @@ static const struct clksel div16_dpll4_clksel[] = {
 /* This virtual clock is the source for dpll4_m2x2_ck */
 static struct clk dpll4_m2_ck = {
         .name           = "dpll4_m2_ck",
+        .ops            = &clkops_null,
         .parent         = &dpll4_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
         .clksel_mask    = OMAP3430_DIV_96M_MASK,
         .clksel         = div16_dpll4_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
+        .clkdm_name     = "dpll4_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 static struct clk dpll4_m2x2_ck = {
         .name           = "dpll4_m2x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &dpll4_m2_ck,
         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
         .recalc         = &omap3_clkoutx2_recalc,
 };
 
-static const struct clksel omap_96m_alwon_fck_clksel[] = {
-        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
-        { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
-        { .parent = NULL }
-};
-
+/*
+ * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
+ * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
+ * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
+ * CM_96K_(F)CLK.
+ */
 static struct clk omap_96m_alwon_fck = {
         .name           = "omap_96m_alwon_fck",
+        .ops            = &clkops_null,
         .parent         = &dpll4_m2x2_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
-        .clksel         = omap_96m_alwon_fck_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                 PARENT_CONTROLS_CLOCK,
-        .recalc         = &omap2_clksel_recalc,
+        .recalc         = &followparent_recalc,
 };
 
-static struct clk omap_96m_fck = {
-        .name           = "omap_96m_fck",
+static struct clk cm_96m_fck = {
+        .name           = "cm_96m_fck",
+        .ops            = &clkops_null,
         .parent         = &omap_96m_alwon_fck,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
         .recalc         = &followparent_recalc,
 };
 
-static const struct clksel cm_96m_fck_clksel[] = {
-        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
-        { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
+static const struct clksel_rate omap_96m_dpll_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate omap_96m_sys_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel omap_96m_fck_clksel[] = {
+        { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
+        { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
         { .parent = NULL }
 };
 
-static struct clk cm_96m_fck = {
-        .name           = "cm_96m_fck",
-        .parent         = &dpll4_m2x2_ck,
+static struct clk omap_96m_fck = {
+        .name           = "omap_96m_fck",
+        .ops            = &clkops_null,
+        .parent         = &sys_ck,
         .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
-        .clksel         = cm_96m_fck_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
+        .clksel         = omap_96m_fck_clksel,
         .recalc         = &omap2_clksel_recalc,
 };
 
 /* This virtual clock is the source for dpll4_m3x2_ck */
 static struct clk dpll4_m3_ck = {
         .name           = "dpll4_m3_ck",
+        .ops            = &clkops_null,
         .parent         = &dpll4_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
         .clksel         = div16_dpll4_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
+        .clkdm_name     = "dpll4_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 static struct clk dpll4_m3x2_ck = {
         .name           = "dpll4_m3x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &dpll4_m3_ck,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
         .recalc         = &omap3_clkoutx2_recalc,
 };
 
-static const struct clksel virt_omap_54m_fck_clksel[] = {
-        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
-        { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
-        { .parent = NULL }
-};
-
-static struct clk virt_omap_54m_fck = {
-        .name           = "virt_omap_54m_fck",
-        .parent         = &dpll4_m3x2_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
-        .clksel         = virt_omap_54m_fck_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
-        .recalc         = &omap2_clksel_recalc,
-};
-
 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
         { .div = 0 }
@@ -729,23 +695,22 @@ static const struct clksel_rate omap_54m_alt_rates[] = {
 };
 
 static const struct clksel omap_54m_clksel[] = {
-        { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
+        { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
         { .parent = NULL }
 };
 
 static struct clk omap_54m_fck = {
         .name           = "omap_54m_fck",
+        .ops            = &clkops_null,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_SOURCE_54M,
+        .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
         .clksel         = omap_54m_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
         .recalc         = &omap2_clksel_recalc,
 };
 
-static const struct clksel_rate omap_48m_96md2_rates[] = {
+static const struct clksel_rate omap_48m_cm96m_rates[] = {
         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
         { .div = 0 }
 };
@@ -756,106 +721,112 @@ static const struct clksel_rate omap_48m_alt_rates[] = {
 };
 
 static const struct clksel omap_48m_clksel[] = {
-        { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
+        { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
         { .parent = NULL }
 };
 
 static struct clk omap_48m_fck = {
         .name           = "omap_48m_fck",
+        .ops            = &clkops_null,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_SOURCE_48M,
+        .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
         .clksel         = omap_48m_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
         .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk omap_12m_fck = {
         .name           = "omap_12m_fck",
+        .ops            = &clkops_null,
         .parent         = &omap_48m_fck,
         .fixed_div      = 4,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
         .recalc         = &omap2_fixed_divisor_recalc,
 };
 
 /* This virstual clock is the source for dpll4_m4x2_ck */
 static struct clk dpll4_m4_ck = {
         .name           = "dpll4_m4_ck",
+        .ops            = &clkops_null,
         .parent         = &dpll4_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
         .clksel         = div16_dpll4_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
+        .clkdm_name     = "dpll4_clkdm",
         .recalc         = &omap2_clksel_recalc,
+        .set_rate       = &omap2_clksel_set_rate,
+        .round_rate     = &omap2_clksel_round_rate,
 };
 
 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 static struct clk dpll4_m4x2_ck = {
         .name           = "dpll4_m4x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &dpll4_m4_ck,
         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
         .recalc         = &omap3_clkoutx2_recalc,
 };
 
 /* This virtual clock is the source for dpll4_m5x2_ck */
 static struct clk dpll4_m5_ck = {
         .name           = "dpll4_m5_ck",
+        .ops            = &clkops_null,
         .parent         = &dpll4_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
         .clksel         = div16_dpll4_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
+        .clkdm_name     = "dpll4_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 static struct clk dpll4_m5x2_ck = {
         .name           = "dpll4_m5x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &dpll4_m5_ck,
         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
         .recalc         = &omap3_clkoutx2_recalc,
 };
 
 /* This virtual clock is the source for dpll4_m6x2_ck */
 static struct clk dpll4_m6_ck = {
         .name           = "dpll4_m6_ck",
+        .ops            = &clkops_null,
         .parent         = &dpll4_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
         .clksel         = div16_dpll4_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
+        .clkdm_name     = "dpll4_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 static struct clk dpll4_m6x2_ck = {
         .name           = "dpll4_m6x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &dpll4_m6_ck,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
         .recalc         = &omap3_clkoutx2_recalc,
 };
 
 static struct clk emu_per_alwon_ck = {
         .name           = "emu_per_alwon_ck",
+        .ops            = &clkops_null,
         .parent         = &dpll4_m6x2_ck,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
+        .clkdm_name     = "dpll4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
@@ -867,6 +838,9 @@ static struct dpll_data dpll5_dd = {
         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
+        .clk_bypass     = &sys_ck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
@@ -876,20 +850,21 @@ static struct dpll_data dpll5_dd = {
         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
-        .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
+        .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
         .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
         .max_divider    = OMAP3_MAX_DPLL_DIV,
         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct clk dpll5_ck = {
         .name           = "dpll5_ck",
+        .ops            = &clkops_noncore_dpll_ops,
         .parent         = &sys_ck,
         .dpll_data      = &dpll5_dd,
-        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
-        .enable         = &omap3_noncore_dpll_enable,
-        .disable        = &omap3_noncore_dpll_disable,
         .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .clkdm_name     = "dpll5_clkdm",
         .recalc         = &omap3_dpll_recalc,
 };
 
@@ -900,31 +875,13 @@ static const struct clksel div16_dpll5_clksel[] = {
 
 static struct clk dpll5_m2_ck = {
         .name           = "dpll5_m2_ck",
+        .ops            = &clkops_null,
         .parent         = &dpll5_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
         .clksel         = div16_dpll5_clksel,
-        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static const struct clksel omap_120m_fck_clksel[] = {
-        { .parent = &sys_ck,      .rates = dpll_bypass_rates },
-        { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
-        { .parent = NULL }
-};
-
-static struct clk omap_120m_fck = {
-        .name           = "omap_120m_fck",
-        .parent         = &dpll5_m2_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
-        .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
-        .clksel         = omap_120m_fck_clksel,
-        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
+        .clkdm_name     = "dpll5_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
@@ -951,22 +908,23 @@ static const struct clksel_rate clkout2_src_54m_rates[] = {
 };
 
 static const struct clksel clkout2_src_clksel[] = {
-        { .parent = &core_ck,             .rates = clkout2_src_core_rates },
-        { .parent = &sys_ck,              .rates = clkout2_src_sys_rates },
-        { .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
-        { .parent = &omap_54m_fck,        .rates = clkout2_src_54m_rates },
+        { .parent = &core_ck,           .rates = clkout2_src_core_rates },
+        { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
+        { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
+        { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
         { .parent = NULL }
 };
 
 static struct clk clkout2_src_ck = {
         .name           = "clkout2_src_ck",
+        .ops            = &clkops_omap2_dflt,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
         .clksel         = clkout2_src_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+        .clkdm_name     = "core_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
@@ -986,11 +944,11 @@ static const struct clksel sys_clkout2_clksel[] = {
 
 static struct clk sys_clkout2 = {
         .name           = "sys_clkout2",
+        .ops            = &clkops_null,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
         .clksel         = sys_clkout2_clksel,
-        .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
         .recalc         = &omap2_clksel_recalc,
 };
 
@@ -998,16 +956,22 @@ static struct clk sys_clkout2 = {
 
 static struct clk corex2_fck = {
         .name           = "corex2_fck",
+        .ops            = &clkops_null,
         .parent         = &dpll3_m2x2_ck,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
         .recalc         = &followparent_recalc,
 };
 
 /* DPLL power domain clock controls */
 
-static const struct clksel div2_core_clksel[] = {
-        { .parent = &core_ck, .rates = div2_rates },
+static const struct clksel_rate div4_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 0 }
+};
+
+static const struct clksel div4_core_clksel[] = {
+        { .parent = &core_ck, .rates = div4_rates },
         { .parent = NULL }
 };
 
@@ -1017,39 +981,21 @@ static const struct clksel div2_core_clksel[] = {
  */
 static struct clk dpll1_fck = {
         .name           = "dpll1_fck",
+        .ops            = &clkops_null,
         .parent         = &core_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
-        .clksel         = div2_core_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
+        .clksel         = div4_core_clksel,
         .recalc         = &omap2_clksel_recalc,
 };
 
-/*
- * MPU clksel:
- * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
- * derives from the high-frequency bypass clock originating from DPLL3,
- * called 'dpll1_fck'
- */
-static const struct clksel mpu_clksel[] = {
-        { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
-        { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
-        { .parent = NULL }
-};
-
 static struct clk mpu_ck = {
         .name           = "mpu_ck",
+        .ops            = &clkops_null,
         .parent         = &dpll1_x2m2_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
-        .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
-        .clksel         = mpu_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
         .clkdm_name     = "mpu_clkdm",
-        .recalc         = &omap2_clksel_recalc,
+        .recalc         = &followparent_recalc,
 };
 
 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
@@ -1066,13 +1012,12 @@ static const struct clksel arm_fck_clksel[] = {
 
 static struct clk arm_fck = {
         .name           = "arm_fck",
+        .ops            = &clkops_null,
         .parent         = &mpu_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
         .clksel         = arm_fck_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
         .recalc         = &omap2_clksel_recalc,
 };
 
@@ -1084,63 +1029,48 @@ static struct clk arm_fck = {
  */
 static struct clk emu_mpu_alwon_ck = {
         .name           = "emu_mpu_alwon_ck",
+        .ops            = &clkops_null,
         .parent         = &mpu_ck,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
         .recalc         = &followparent_recalc,
 };
 
 static struct clk dpll2_fck = {
         .name           = "dpll2_fck",
+        .ops            = &clkops_null,
         .parent         = &core_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
-        .clksel         = div2_core_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
+        .clksel         = div4_core_clksel,
         .recalc         = &omap2_clksel_recalc,
 };
 
-/*
- * IVA2 clksel:
- * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
- * derives from the high-frequency bypass clock originating from DPLL3,
- * called 'dpll2_fck'
- */
-
-static const struct clksel iva2_clksel[] = {
-        { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
-        { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
-        { .parent = NULL }
-};
-
 static struct clk iva2_ck = {
         .name           = "iva2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &dpll2_m2_ck,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
-                                          OMAP3430_CM_IDLEST_PLL),
-        .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
-        .clksel         = iva2_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
         .clkdm_name     = "iva2_clkdm",
-        .recalc         = &omap2_clksel_recalc,
+        .recalc         = &followparent_recalc,
 };
 
 /* Common interface clocks */
 
+static const struct clksel div2_core_clksel[] = {
+        { .parent = &core_ck, .rates = div2_rates },
+        { .parent = NULL }
+};
+
 static struct clk l3_ick = {
         .name           = "l3_ick",
+        .ops            = &clkops_null,
         .parent         = &core_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
         .clksel         = div2_core_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
         .clkdm_name     = "core_l3_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
@@ -1152,13 +1082,12 @@ static const struct clksel div2_l3_clksel[] = {
 
 static struct clk l4_ick = {
         .name           = "l4_ick",
+        .ops            = &clkops_null,
         .parent         = &l3_ick,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
         .clksel         = div2_l3_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &omap2_clksel_recalc,
 
@@ -1171,12 +1100,12 @@ static const struct clksel div2_l4_clksel[] = {
 
 static struct clk rm_ick = {
         .name           = "rm_ick",
+        .ops            = &clkops_null,
         .parent         = &l4_ick,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
         .clksel         = div2_l4_clksel,
-        .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
         .recalc         = &omap2_clksel_recalc,
 };
 
@@ -1192,53 +1121,52 @@ static const struct clksel gfx_l3_clksel[] = {
 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
 static struct clk gfx_l3_ck = {
         .name           = "gfx_l3_ck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l3_ick,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
         .enable_bit     = OMAP_EN_GFX_SHIFT,
-        .flags          = CLOCK_IN_OMAP3430ES1,
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gfx_l3_fck = {
         .name           = "gfx_l3_fck",
+        .ops            = &clkops_null,
         .parent         = &gfx_l3_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
         .clksel         = gfx_l3_clksel,
-        .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
         .clkdm_name     = "gfx_3430es1_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk gfx_l3_ick = {
         .name           = "gfx_l3_ick",
+        .ops            = &clkops_null,
         .parent         = &gfx_l3_ck,
-        .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
         .clkdm_name     = "gfx_3430es1_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gfx_cg1_ck = {
         .name           = "gfx_cg1_ck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
         .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
-        .flags          = CLOCK_IN_OMAP3430ES1,
         .clkdm_name     = "gfx_3430es1_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gfx_cg2_ck = {
         .name           = "gfx_cg2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
         .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
-        .flags          = CLOCK_IN_OMAP3430ES1,
         .clkdm_name     = "gfx_3430es1_clkdm",
         .recalc         = &followparent_recalc,
 };
@@ -1265,24 +1193,24 @@ static const struct clksel sgx_clksel[] = {
 
 static struct clk sgx_fck = {
         .name           = "sgx_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
+        .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
         .clksel         = sgx_clksel,
-        .flags          = CLOCK_IN_OMAP3430ES2,
         .clkdm_name     = "sgx_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk sgx_ick = {
         .name           = "sgx_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l3_ick,
         .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
-        .flags          = CLOCK_IN_OMAP3430ES2,
+        .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
         .clkdm_name     = "sgx_clkdm",
         .recalc         = &followparent_recalc,
 };
@@ -1291,11 +1219,11 @@ static struct clk sgx_ick = {
 
 static struct clk d2d_26m_fck = {
         .name           = "d2d_26m_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &sys_ck,
         .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
-        .flags          = CLOCK_IN_OMAP3430ES1,
         .clkdm_name     = "d2d_clkdm",
         .recalc         = &followparent_recalc,
 };
@@ -1308,6 +1236,7 @@ static const struct clksel omap343x_gpt_clksel[] = {
 
 static struct clk gpt10_fck = {
         .name           = "gpt10_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &sys_ck,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1315,13 +1244,13 @@ static struct clk gpt10_fck = {
         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
         .clksel         = omap343x_gpt_clksel,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk gpt11_fck = {
         .name           = "gpt11_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &sys_ck,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1329,35 +1258,34 @@ static struct clk gpt11_fck = {
         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
         .clksel         = omap343x_gpt_clksel,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk cpefuse_fck = {
         .name           = "cpefuse_fck",
+        .ops            = &clkops_omap2_dflt,
         .parent         = &sys_ck,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
-        .flags          = CLOCK_IN_OMAP3430ES2,
         .recalc         = &followparent_recalc,
 };
 
 static struct clk ts_fck = {
         .name           = "ts_fck",
+        .ops            = &clkops_omap2_dflt,
         .parent         = &omap_32k_fck,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
-        .flags          = CLOCK_IN_OMAP3430ES2,
         .recalc         = &followparent_recalc,
 };
 
 static struct clk usbtll_fck = {
         .name           = "usbtll_fck",
-        .parent         = &omap_120m_fck,
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &dpll5_m2_ck,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
-        .flags          = CLOCK_IN_OMAP3430ES2,
         .recalc         = &followparent_recalc,
 };
 
@@ -1365,84 +1293,83 @@ static struct clk usbtll_fck = {
 
 static struct clk core_96m_fck = {
         .name           = "core_96m_fck",
+        .ops            = &clkops_null,
         .parent         = &omap_96m_fck,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk mmchs3_fck = {
         .name           = "mmchs_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 2,
         .parent         = &core_96m_fck,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
-        .flags          = CLOCK_IN_OMAP3430ES2,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk mmchs2_fck = {
         .name           = "mmchs_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 1,
         .parent         = &core_96m_fck,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk mspro_fck = {
         .name           = "mspro_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_96m_fck,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk mmchs1_fck = {
         .name           = "mmchs_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_96m_fck,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk i2c3_fck = {
         .name           = "i2c_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 3,
         .parent         = &core_96m_fck,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk i2c2_fck = {
         .name           = "i2c_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 2,
         .parent         = &core_96m_fck,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk i2c1_fck = {
         .name           = "i2c_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 1,
         .parent         = &core_96m_fck,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
@@ -1469,6 +1396,7 @@ static const struct clksel mcbsp_15_clksel[] = {
 
 static struct clk mcbsp5_fck = {
         .name           = "mcbsp_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 5,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1476,13 +1404,13 @@ static struct clk mcbsp5_fck = {
         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
         .clksel         = mcbsp_15_clksel,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcbsp1_fck = {
         .name           = "mcbsp_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 1,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1490,7 +1418,6 @@ static struct clk mcbsp1_fck = {
         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
         .clksel         = mcbsp_15_clksel,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
@@ -1499,77 +1426,76 @@ static struct clk mcbsp1_fck = {
 
 static struct clk core_48m_fck = {
         .name           = "core_48m_fck",
+        .ops            = &clkops_null,
         .parent         = &omap_48m_fck,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk mcspi4_fck = {
         .name           = "mcspi_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 4,
         .parent         = &core_48m_fck,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .recalc         = &followparent_recalc,
 };
 
 static struct clk mcspi3_fck = {
         .name           = "mcspi_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 3,
         .parent         = &core_48m_fck,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .recalc         = &followparent_recalc,
 };
 
 static struct clk mcspi2_fck = {
         .name           = "mcspi_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 2,
         .parent         = &core_48m_fck,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .recalc         = &followparent_recalc,
 };
 
 static struct clk mcspi1_fck = {
         .name           = "mcspi_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 1,
         .parent         = &core_48m_fck,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .recalc         = &followparent_recalc,
 };
 
 static struct clk uart2_fck = {
         .name           = "uart2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_48m_fck,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .recalc         = &followparent_recalc,
 };
 
 static struct clk uart1_fck = {
         .name           = "uart1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_48m_fck,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .recalc         = &followparent_recalc,
 };
 
 static struct clk fshostusb_fck = {
         .name           = "fshostusb_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_48m_fck,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
-        .flags          = CLOCK_IN_OMAP3430ES1,
         .recalc         = &followparent_recalc,
 };
 
@@ -1577,19 +1503,18 @@ static struct clk fshostusb_fck = {
 
 static struct clk core_12m_fck = {
         .name           = "core_12m_fck",
+        .ops            = &clkops_null,
         .parent         = &omap_12m_fck,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk hdq_fck = {
         .name           = "hdq_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_12m_fck,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .recalc         = &followparent_recalc,
 };
 
@@ -1612,22 +1537,22 @@ static const struct clksel ssi_ssr_clksel[] = {
 
 static struct clk ssi_ssr_fck = {
         .name           = "ssi_ssr_fck",
+        .ops            = &clkops_omap2_dflt,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
         .clksel         = ssi_ssr_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk ssi_sst_fck = {
         .name           = "ssi_sst_fck",
+        .ops            = &clkops_null,
         .parent         = &ssi_ssr_fck,
         .fixed_div      = 2,
-        .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
         .recalc         = &omap2_fixed_divisor_recalc,
 };
 
@@ -1641,39 +1566,39 @@ static struct clk ssi_sst_fck = {
  */
 static struct clk core_l3_ick = {
         .name           = "core_l3_ick",
+        .ops            = &clkops_null,
         .parent         = &l3_ick,
         .init           = &omap2_init_clk_clkdm,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
         .clkdm_name     = "core_l3_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk hsotgusb_ick = {
         .name           = "hsotgusb_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_l3_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l3_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk sdrc_ick = {
         .name           = "sdrc_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_l3_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
+        .flags          = ENABLE_ON_INIT,
         .clkdm_name     = "core_l3_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpmc_fck = {
         .name           = "gpmc_fck",
+        .ops            = &clkops_null,
         .parent         = &core_l3_ick,
-        .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
-                                ENABLE_ON_INIT,
+        .flags          = ENABLE_ON_INIT, /* huh? */
         .clkdm_name     = "core_l3_clkdm",
         .recalc         = &followparent_recalc,
 };
@@ -1682,18 +1607,17 @@ static struct clk gpmc_fck = {
 
 static struct clk security_l3_ick = {
         .name           = "security_l3_ick",
+        .ops            = &clkops_null,
         .parent         = &l3_ick,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
         .recalc         = &followparent_recalc,
 };
 
 static struct clk pka_ick = {
         .name           = "pka_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &security_l3_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .recalc         = &followparent_recalc,
 };
 
@@ -1701,31 +1625,30 @@ static struct clk pka_ick = {
 
 static struct clk core_l4_ick = {
         .name           = "core_l4_ick",
+        .ops            = &clkops_null,
         .parent         = &l4_ick,
         .init           = &omap2_init_clk_clkdm,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk usbtll_ick = {
         .name           = "usbtll_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
-        .flags          = CLOCK_IN_OMAP3430ES2,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk mmchs3_ick = {
         .name           = "mmchs_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 2,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
-        .flags          = CLOCK_IN_OMAP3430ES2,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
@@ -1733,250 +1656,251 @@ static struct clk mmchs3_ick = {
 /* Intersystem Communication Registers - chassis mode only */
 static struct clk icr_ick = {
         .name           = "icr_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk aes2_ick = {
         .name           = "aes2_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk sha12_ick = {
         .name           = "sha12_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk des2_ick = {
         .name           = "des2_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk mmchs2_ick = {
         .name           = "mmchs_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 1,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk mmchs1_ick = {
         .name           = "mmchs_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk mspro_ick = {
         .name           = "mspro_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk hdq_ick = {
         .name           = "hdq_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk mcspi4_ick = {
         .name           = "mcspi_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 4,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk mcspi3_ick = {
         .name           = "mcspi_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 3,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk mcspi2_ick = {
         .name           = "mcspi_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 2,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk mcspi1_ick = {
         .name           = "mcspi_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 1,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk i2c3_ick = {
         .name           = "i2c_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 3,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk i2c2_ick = {
         .name           = "i2c_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 2,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk i2c1_ick = {
         .name           = "i2c_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 1,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk uart2_ick = {
         .name           = "uart2_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk uart1_ick = {
         .name           = "uart1_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpt11_ick = {
         .name           = "gpt11_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpt10_ick = {
         .name           = "gpt10_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk mcbsp5_ick = {
         .name           = "mcbsp_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 5,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk mcbsp1_ick = {
         .name           = "mcbsp_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 1,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk fac_ick = {
         .name           = "fac_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
-        .flags          = CLOCK_IN_OMAP3430ES1,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk mailboxes_ick = {
         .name           = "mailboxes_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk omapctrl_ick = {
         .name           = "omapctrl_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
+        .flags          = ENABLE_ON_INIT,
         .recalc         = &followparent_recalc,
 };
 
@@ -1984,19 +1908,18 @@ static struct clk omapctrl_ick = {
 
 static struct clk ssi_l4_ick = {
         .name           = "ssi_l4_ick",
+        .ops            = &clkops_null,
         .parent         = &l4_ick,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk ssi_ick = {
         .name           = "ssi_ick",
+        .ops            = &clkops_omap2_dflt,
         .parent         = &ssi_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
@@ -2011,6 +1934,7 @@ static const struct clksel usb_l4_clksel[] = {
 
 static struct clk usb_l4_ick = {
         .name           = "usb_l4_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ick,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -2018,7 +1942,6 @@ static struct clk usb_l4_ick = {
         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
         .clksel         = usb_l4_clksel,
-        .flags          = CLOCK_IN_OMAP3430ES1,
         .recalc         = &omap2_clksel_recalc,
 };
 
@@ -2028,98 +1951,87 @@ static struct clk usb_l4_ick = {
 
 static struct clk security_l4_ick2 = {
         .name           = "security_l4_ick2",
+        .ops            = &clkops_null,
         .parent         = &l4_ick,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
         .recalc         = &followparent_recalc,
 };
 
 static struct clk aes1_ick = {
         .name           = "aes1_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &security_l4_ick2,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .recalc         = &followparent_recalc,
 };
 
 static struct clk rng_ick = {
         .name           = "rng_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &security_l4_ick2,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .recalc         = &followparent_recalc,
 };
 
 static struct clk sha11_ick = {
         .name           = "sha11_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &security_l4_ick2,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .recalc         = &followparent_recalc,
 };
 
 static struct clk des1_ick = {
         .name           = "des1_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &security_l4_ick2,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .recalc         = &followparent_recalc,
 };
 
 /* DSS */
-static const struct clksel dss1_alwon_fck_clksel[] = {
-        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
-        { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
-        { .parent = NULL }
-};
-
 static struct clk dss1_alwon_fck = {
         .name           = "dss1_alwon_fck",
+        .ops            = &clkops_omap2_dflt,
         .parent         = &dpll4_m4x2_ck,
-        .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
-        .clksel         = dss1_alwon_fck_clksel,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "dss_clkdm",
-        .recalc         = &omap2_clksel_recalc,
+        .recalc         = &followparent_recalc,
 };
 
 static struct clk dss_tv_fck = {
         .name           = "dss_tv_fck",
+        .ops            = &clkops_omap2_dflt,
         .parent         = &omap_54m_fck,
         .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_TV_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "dss_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk dss_96m_fck = {
         .name           = "dss_96m_fck",
+        .ops            = &clkops_omap2_dflt,
         .parent         = &omap_96m_fck,
         .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_TV_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "dss_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk dss2_alwon_fck = {
         .name           = "dss2_alwon_fck",
+        .ops            = &clkops_omap2_dflt,
         .parent         = &sys_ck,
         .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "dss_clkdm",
         .recalc         = &followparent_recalc,
 };
@@ -2127,45 +2039,46 @@ static struct clk dss2_alwon_fck = {
 static struct clk dss_ick = {
         /* Handles both L3 and L4 clocks */
         .name           = "dss_ick",
+        .ops            = &clkops_omap2_dflt,
         .parent         = &l4_ick,
         .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "dss_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 /* CAM */
 
-static const struct clksel cam_mclk_clksel[] = {
-        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
-        { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
-        { .parent = NULL }
-};
-
 static struct clk cam_mclk = {
         .name           = "cam_mclk",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &dpll4_m5x2_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
-        .clksel         = cam_mclk_clksel,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "cam_clkdm",
-        .recalc         = &omap2_clksel_recalc,
+        .recalc         = &followparent_recalc,
 };
 
 static struct clk cam_ick = {
         /* Handles both L3 and L4 clocks */
         .name           = "cam_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ick,
         .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
+        .clkdm_name     = "cam_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk csi2_96m_fck = {
+        .name           = "csi2_96m_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_96m_fck,
+        .init           = &omap2_init_clk_clkdm,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
         .clkdm_name     = "cam_clkdm",
         .recalc         = &followparent_recalc,
 };
@@ -2174,22 +2087,22 @@ static struct clk cam_ick = {
 
 static struct clk usbhost_120m_fck = {
         .name           = "usbhost_120m_fck",
-        .parent         = &omap_120m_fck,
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dpll5_m2_ck,
         .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
-        .flags          = CLOCK_IN_OMAP3430ES2,
         .clkdm_name     = "usbhost_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk usbhost_48m_fck = {
         .name           = "usbhost_48m_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &omap_48m_fck,
         .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
-        .flags          = CLOCK_IN_OMAP3430ES2,
         .clkdm_name     = "usbhost_clkdm",
         .recalc         = &followparent_recalc,
 };
@@ -2197,22 +2110,11 @@ static struct clk usbhost_48m_fck = {
 static struct clk usbhost_ick = {
         /* Handles both L3 and L4 clocks */
         .name           = "usbhost_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l4_ick,
         .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
-        .flags          = CLOCK_IN_OMAP3430ES2,
-        .clkdm_name     = "usbhost_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk usbhost_sar_fck = {
-        .name           = "usbhost_sar_fck",
-        .parent         = &osc_sys_ck,
-        .init           = &omap2_init_clk_clkdm,
-        .enable_reg     = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
-        .enable_bit     = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
-        .flags          = CLOCK_IN_OMAP3430ES2,
         .clkdm_name     = "usbhost_clkdm",
         .recalc         = &followparent_recalc,
 };
@@ -2237,7 +2139,7 @@ static const struct clksel_rate usim_120m_rates[] = {
 
 static const struct clksel usim_clksel[] = {
         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
-        { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
+        { .parent = &dpll5_m2_ck,       .rates = usim_120m_rates },
         { .parent = &sys_ck,            .rates = div2_rates },
         { .parent = NULL },
 };
@@ -2245,63 +2147,63 @@ static const struct clksel usim_clksel[] = {
 /* 3430ES2 only */
 static struct clk usim_fck = {
         .name           = "usim_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
         .clksel         = usim_clksel,
-        .flags          = CLOCK_IN_OMAP3430ES2,
         .recalc         = &omap2_clksel_recalc,
 };
 
 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
 static struct clk gpt1_fck = {
         .name           = "gpt1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
         .clksel         = omap343x_gpt_clksel,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "wkup_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk wkup_32k_fck = {
         .name           = "wkup_32k_fck",
+        .ops            = &clkops_null,
         .init           = &omap2_init_clk_clkdm,
         .parent         = &omap_32k_fck,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
         .clkdm_name     = "wkup_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpio1_dbck = {
         .name           = "gpio1_dbck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &wkup_32k_fck,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "wkup_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk wdt2_fck = {
         .name           = "wdt2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &wkup_32k_fck,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "wkup_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk wkup_l4_ick = {
         .name           = "wkup_l4_ick",
+        .ops            = &clkops_null,
         .parent         = &sys_ck,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
         .clkdm_name     = "wkup_clkdm",
         .recalc         = &followparent_recalc,
 };
@@ -2310,50 +2212,50 @@ static struct clk wkup_l4_ick = {
 /* Never specifically named in the TRM, so we have to infer a likely name */
 static struct clk usim_ick = {
         .name           = "usim_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &wkup_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
-        .flags          = CLOCK_IN_OMAP3430ES2,
         .clkdm_name     = "wkup_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk wdt2_ick = {
         .name           = "wdt2_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &wkup_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "wkup_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk wdt1_ick = {
         .name           = "wdt1_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &wkup_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "wkup_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpio1_ick = {
         .name           = "gpio1_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &wkup_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "wkup_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk omap_32ksync_ick = {
         .name           = "omap_32ksync_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &wkup_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "wkup_clkdm",
         .recalc         = &followparent_recalc,
 };
@@ -2361,20 +2263,20 @@ static struct clk omap_32ksync_ick = {
 /* XXX This clock no longer exists in 3430 TRM rev F */
 static struct clk gpt12_ick = {
         .name           = "gpt12_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &wkup_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "wkup_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpt1_ick = {
         .name           = "gpt1_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &wkup_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "wkup_clkdm",
         .recalc         = &followparent_recalc,
 };
@@ -2385,406 +2287,404 @@ static struct clk gpt1_ick = {
 
 static struct clk per_96m_fck = {
         .name           = "per_96m_fck",
+        .ops            = &clkops_null,
         .parent         = &omap_96m_alwon_fck,
         .init           = &omap2_init_clk_clkdm,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk per_48m_fck = {
         .name           = "per_48m_fck",
+        .ops            = &clkops_null,
         .parent         = &omap_48m_fck,
         .init           = &omap2_init_clk_clkdm,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk uart3_fck = {
         .name           = "uart3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &per_48m_fck,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpt2_fck = {
         .name           = "gpt2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
         .clksel         = omap343x_gpt_clksel,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk gpt3_fck = {
         .name           = "gpt3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
         .clksel         = omap343x_gpt_clksel,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk gpt4_fck = {
         .name           = "gpt4_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
         .clksel         = omap343x_gpt_clksel,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk gpt5_fck = {
         .name           = "gpt5_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
         .clksel         = omap343x_gpt_clksel,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk gpt6_fck = {
         .name           = "gpt6_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
         .clksel         = omap343x_gpt_clksel,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk gpt7_fck = {
         .name           = "gpt7_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
         .clksel         = omap343x_gpt_clksel,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk gpt8_fck = {
         .name           = "gpt8_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
         .clksel         = omap343x_gpt_clksel,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk gpt9_fck = {
         .name           = "gpt9_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
         .clksel         = omap343x_gpt_clksel,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk per_32k_alwon_fck = {
         .name           = "per_32k_alwon_fck",
+        .ops            = &clkops_null,
         .parent         = &omap_32k_fck,
         .clkdm_name     = "per_clkdm",
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpio6_dbck = {
         .name           = "gpio6_dbck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &per_32k_alwon_fck,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpio5_dbck = {
         .name           = "gpio5_dbck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &per_32k_alwon_fck,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpio4_dbck = {
         .name           = "gpio4_dbck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &per_32k_alwon_fck,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpio3_dbck = {
         .name           = "gpio3_dbck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &per_32k_alwon_fck,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpio2_dbck = {
         .name           = "gpio2_dbck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &per_32k_alwon_fck,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk wdt3_fck = {
         .name           = "wdt3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &per_32k_alwon_fck,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk per_l4_ick = {
         .name           = "per_l4_ick",
+        .ops            = &clkops_null,
         .parent         = &l4_ick,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                                PARENT_CONTROLS_CLOCK,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpio6_ick = {
         .name           = "gpio6_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpio5_ick = {
         .name           = "gpio5_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpio4_ick = {
         .name           = "gpio4_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpio3_ick = {
         .name           = "gpio3_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpio2_ick = {
         .name           = "gpio2_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk wdt3_ick = {
         .name           = "wdt3_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk uart3_ick = {
         .name           = "uart3_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpt9_ick = {
         .name           = "gpt9_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpt8_ick = {
         .name           = "gpt8_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpt7_ick = {
         .name           = "gpt7_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpt6_ick = {
         .name           = "gpt6_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpt5_ick = {
         .name           = "gpt5_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpt4_ick = {
         .name           = "gpt4_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpt3_ick = {
         .name           = "gpt3_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk gpt2_ick = {
         .name           = "gpt2_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk mcbsp2_ick = {
         .name           = "mcbsp_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 2,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk mcbsp3_ick = {
         .name           = "mcbsp_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 3,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static struct clk mcbsp4_ick = {
         .name           = "mcbsp_ick",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 4,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
 
 static const struct clksel mcbsp_234_clksel[] = {
-        { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
-        { .parent = &mcbsp_clks,  .rates = common_mcbsp_mcbsp_rates },
+        { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
         { .parent = NULL }
 };
 
 static struct clk mcbsp2_fck = {
         .name           = "mcbsp_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 2,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
@@ -2792,13 +2692,13 @@ static struct clk mcbsp2_fck = {
         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
         .clksel         = mcbsp_234_clksel,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcbsp3_fck = {
         .name           = "mcbsp_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 3,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
@@ -2806,13 +2706,13 @@ static struct clk mcbsp3_fck = {
         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
         .clksel         = mcbsp_234_clksel,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcbsp4_fck = {
         .name           = "mcbsp_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .id             = 4,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
@@ -2820,7 +2720,6 @@ static struct clk mcbsp4_fck = {
         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
         .clksel         = mcbsp_234_clksel,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "per_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
@@ -2864,11 +2763,11 @@ static const struct clksel emu_src_clksel[] = {
  */
 static struct clk emu_src_ck = {
         .name           = "emu_src_ck",
+        .ops            = &clkops_null,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
         .clksel         = emu_src_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
         .clkdm_name     = "emu_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
@@ -2888,11 +2787,11 @@ static const struct clksel pclk_emu_clksel[] = {
 
 static struct clk pclk_fck = {
         .name           = "pclk_fck",
+        .ops            = &clkops_null,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
         .clksel         = pclk_emu_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
         .clkdm_name     = "emu_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
@@ -2911,11 +2810,11 @@ static const struct clksel pclkx2_emu_clksel[] = {
 
 static struct clk pclkx2_fck = {
         .name           = "pclkx2_fck",
+        .ops            = &clkops_null,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
         .clksel         = pclkx2_emu_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
         .clkdm_name     = "emu_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
@@ -2927,22 +2826,22 @@ static const struct clksel atclk_emu_clksel[] = {
 
 static struct clk atclk_fck = {
         .name           = "atclk_fck",
+        .ops            = &clkops_null,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
         .clksel         = atclk_emu_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
         .clkdm_name     = "emu_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk traceclk_src_fck = {
         .name           = "traceclk_src_fck",
+        .ops            = &clkops_null,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
         .clksel         = emu_src_clksel,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
         .clkdm_name     = "emu_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
@@ -2961,11 +2860,11 @@ static const struct clksel traceclk_clksel[] = {
 
 static struct clk traceclk_fck = {
         .name           = "traceclk_fck",
+        .ops            = &clkops_null,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
         .clksel         = traceclk_clksel,
-        .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
         .clkdm_name     = "emu_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
@@ -2975,27 +2874,27 @@ static struct clk traceclk_fck = {
 /* SmartReflex fclk (VDD1) */
 static struct clk sr1_fck = {
         .name           = "sr1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &sys_ck,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
         .recalc         = &followparent_recalc,
 };
 
 /* SmartReflex fclk (VDD2) */
 static struct clk sr2_fck = {
         .name           = "sr2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
         .parent         = &sys_ck,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
         .recalc         = &followparent_recalc,
 };
 
 static struct clk sr_l4_ick = {
         .name           = "sr_l4_ick",
+        .ops            = &clkops_null, /* RMK: missing? */
         .parent         = &l4_ick,
-        .flags          = CLOCK_IN_OMAP343X,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
@@ -3005,231 +2904,16 @@ static struct clk sr_l4_ick = {
 /* XXX This clock no longer exists in 3430 TRM rev F */
 static struct clk gpt12_fck = {
         .name           = "gpt12_fck",
+        .ops            = &clkops_null,
         .parent         = &secure_32k_fck,
-        .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
         .recalc         = &followparent_recalc,
 };
 
 static struct clk wdt1_fck = {
         .name           = "wdt1_fck",
+        .ops            = &clkops_null,
         .parent         = &secure_32k_fck,
-        .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk *onchip_34xx_clks[] __initdata = {
-        &omap_32k_fck,
-        &virt_12m_ck,
-        &virt_13m_ck,
-        &virt_16_8m_ck,
-        &virt_19_2m_ck,
-        &virt_26m_ck,
-        &virt_38_4m_ck,
-        &osc_sys_ck,
-        &sys_ck,
-        &sys_altclk,
-        &mcbsp_clks,
-        &sys_clkout1,
-        &dpll1_ck,
-        &dpll1_x2_ck,
-        &dpll1_x2m2_ck,
-        &dpll2_ck,
-        &dpll2_m2_ck,
-        &dpll3_ck,
-        &core_ck,
-        &dpll3_x2_ck,
-        &dpll3_m2_ck,
-        &dpll3_m2x2_ck,
-        &dpll3_m3_ck,
-        &dpll3_m3x2_ck,
-        &emu_core_alwon_ck,
-        &dpll4_ck,
-        &dpll4_x2_ck,
-        &omap_96m_alwon_fck,
-        &omap_96m_fck,
-        &cm_96m_fck,
-        &virt_omap_54m_fck,
-        &omap_54m_fck,
-        &omap_48m_fck,
-        &omap_12m_fck,
-        &dpll4_m2_ck,
-        &dpll4_m2x2_ck,
-        &dpll4_m3_ck,
-        &dpll4_m3x2_ck,
-        &dpll4_m4_ck,
-        &dpll4_m4x2_ck,
-        &dpll4_m5_ck,
-        &dpll4_m5x2_ck,
-        &dpll4_m6_ck,
-        &dpll4_m6x2_ck,
-        &emu_per_alwon_ck,
-        &dpll5_ck,
-        &dpll5_m2_ck,
-        &omap_120m_fck,
-        &clkout2_src_ck,
-        &sys_clkout2,
-        &corex2_fck,
-        &dpll1_fck,
-        &mpu_ck,
-        &arm_fck,
-        &emu_mpu_alwon_ck,
-        &dpll2_fck,
-        &iva2_ck,
-        &l3_ick,
-        &l4_ick,
-        &rm_ick,
-        &gfx_l3_ck,
-        &gfx_l3_fck,
-        &gfx_l3_ick,
-        &gfx_cg1_ck,
-        &gfx_cg2_ck,
-        &sgx_fck,
-        &sgx_ick,
-        &d2d_26m_fck,
-        &gpt10_fck,
-        &gpt11_fck,
-        &cpefuse_fck,
-        &ts_fck,
-        &usbtll_fck,
-        &core_96m_fck,
-        &mmchs3_fck,
-        &mmchs2_fck,
-        &mspro_fck,
-        &mmchs1_fck,
-        &i2c3_fck,
-        &i2c2_fck,
-        &i2c1_fck,
-        &mcbsp5_fck,
-        &mcbsp1_fck,
-        &core_48m_fck,
-        &mcspi4_fck,
-        &mcspi3_fck,
-        &mcspi2_fck,
-        &mcspi1_fck,
-        &uart2_fck,
-        &uart1_fck,
-        &fshostusb_fck,
-        &core_12m_fck,
-        &hdq_fck,
-        &ssi_ssr_fck,
-        &ssi_sst_fck,
-        &core_l3_ick,
-        &hsotgusb_ick,
-        &sdrc_ick,
-        &gpmc_fck,
-        &security_l3_ick,
-        &pka_ick,
-        &core_l4_ick,
-        &usbtll_ick,
-        &mmchs3_ick,
-        &icr_ick,
-        &aes2_ick,
-        &sha12_ick,
-        &des2_ick,
-        &mmchs2_ick,
-        &mmchs1_ick,
-        &mspro_ick,
-        &hdq_ick,
-        &mcspi4_ick,
-        &mcspi3_ick,
-        &mcspi2_ick,
-        &mcspi1_ick,
-        &i2c3_ick,
-        &i2c2_ick,
-        &i2c1_ick,
-        &uart2_ick,
-        &uart1_ick,
-        &gpt11_ick,
-        &gpt10_ick,
-        &mcbsp5_ick,
-        &mcbsp1_ick,
-        &fac_ick,
-        &mailboxes_ick,
-        &omapctrl_ick,
-        &ssi_l4_ick,
-        &ssi_ick,
-        &usb_l4_ick,
-        &security_l4_ick2,
-        &aes1_ick,
-        &rng_ick,
-        &sha11_ick,
-        &des1_ick,
-        &dss1_alwon_fck,
-        &dss_tv_fck,
-        &dss_96m_fck,
-        &dss2_alwon_fck,
-        &dss_ick,
-        &cam_mclk,
-        &cam_ick,
-        &usbhost_120m_fck,
-        &usbhost_48m_fck,
-        &usbhost_ick,
-        &usbhost_sar_fck,
-        &usim_fck,
-        &gpt1_fck,
-        &wkup_32k_fck,
-        &gpio1_dbck,
-        &wdt2_fck,
-        &wkup_l4_ick,
-        &usim_ick,
-        &wdt2_ick,
-        &wdt1_ick,
-        &gpio1_ick,
-        &omap_32ksync_ick,
-        &gpt12_ick,
-        &gpt1_ick,
-        &per_96m_fck,
-        &per_48m_fck,
-        &uart3_fck,
-        &gpt2_fck,
-        &gpt3_fck,
-        &gpt4_fck,
-        &gpt5_fck,
-        &gpt6_fck,
-        &gpt7_fck,
-        &gpt8_fck,
-        &gpt9_fck,
-        &per_32k_alwon_fck,
-        &gpio6_dbck,
-        &gpio5_dbck,
-        &gpio4_dbck,
-        &gpio3_dbck,
-        &gpio2_dbck,
-        &wdt3_fck,
-        &per_l4_ick,
-        &gpio6_ick,
-        &gpio5_ick,
-        &gpio4_ick,
-        &gpio3_ick,
-        &gpio2_ick,
-        &wdt3_ick,
-        &uart3_ick,
-        &gpt9_ick,
-        &gpt8_ick,
-        &gpt7_ick,
-        &gpt6_ick,
-        &gpt5_ick,
-        &gpt4_ick,
-        &gpt3_ick,
-        &gpt2_ick,
-        &mcbsp2_ick,
-        &mcbsp3_ick,
-        &mcbsp4_ick,
-        &mcbsp2_fck,
-        &mcbsp3_fck,
-        &mcbsp4_fck,
-        &emu_src_ck,
-        &pclk_fck,
-        &pclkx2_fck,
-        &atclk_fck,
-        &traceclk_src_fck,
-        &traceclk_fck,
-        &sr1_fck,
-        &sr2_fck,
-        &sr_l4_ick,
-        &secure_32k_fck,
-        &gpt12_fck,
-        &wdt1_fck,
+        .recalc         = &followparent_recalc,
 };
 
 #endif
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 4c3ce9cfd948..0e7d501865b6 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -22,6 +22,7 @@
 #include <linux/delay.h>
 #include <linux/clk.h>
 #include <linux/limits.h>
+#include <linux/err.h>
 
 #include <linux/io.h>
 
@@ -71,16 +72,13 @@ static void _autodep_lookup(struct clkdm_pwrdm_autodep *autodep)
         if (!omap_chip_is(autodep->omap_chip))
                 return;
 
-        pwrdm = pwrdm_lookup(autodep->pwrdm_name);
+        pwrdm = pwrdm_lookup(autodep->pwrdm.name);
         if (!pwrdm) {
-                pr_debug("clockdomain: _autodep_lookup: powerdomain %s "
-                         "does not exist\n", autodep->pwrdm_name);
-                WARN_ON(1);
-                return;
+                pr_err("clockdomain: autodeps: powerdomain %s does not exist\n",
+                         autodep->pwrdm.name);
+                pwrdm = ERR_PTR(-ENOENT);
         }
-        autodep->pwrdm = pwrdm;
-
-        return;
+        autodep->pwrdm.ptr = pwrdm;
 }
 
 /*
@@ -95,16 +93,19 @@ static void _clkdm_add_autodeps(struct clockdomain *clkdm)
 {
         struct clkdm_pwrdm_autodep *autodep;
 
-        for (autodep = autodeps; autodep->pwrdm_name; autodep++) {
-                if (!autodep->pwrdm)
+        for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) {
+                if (IS_ERR(autodep->pwrdm.ptr))
+                        continue;
+
+                if (!omap_chip_is(autodep->omap_chip))
                         continue;
 
                 pr_debug("clockdomain: adding %s sleepdep/wkdep for "
-                         "pwrdm %s\n", autodep->pwrdm_name,
-                         clkdm->pwrdm->name);
+                         "pwrdm %s\n", autodep->pwrdm.ptr->name,
+                         clkdm->pwrdm.ptr->name);
 
-                pwrdm_add_sleepdep(clkdm->pwrdm, autodep->pwrdm);
-                pwrdm_add_wkdep(clkdm->pwrdm, autodep->pwrdm);
+                pwrdm_add_sleepdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr);
+                pwrdm_add_wkdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr);
         }
 }
 
@@ -120,16 +121,19 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm)
 {
         struct clkdm_pwrdm_autodep *autodep;
 
-        for (autodep = autodeps; autodep->pwrdm_name; autodep++) {
-                if (!autodep->pwrdm)
+        for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) {
+                if (IS_ERR(autodep->pwrdm.ptr))
+                        continue;
+
+                if (!omap_chip_is(autodep->omap_chip))
                         continue;
 
                 pr_debug("clockdomain: removing %s sleepdep/wkdep for "
-                         "pwrdm %s\n", autodep->pwrdm_name,
-                         clkdm->pwrdm->name);
+                         "pwrdm %s\n", autodep->pwrdm.ptr->name,
+                         clkdm->pwrdm.ptr->name);
 
-                pwrdm_del_sleepdep(clkdm->pwrdm, autodep->pwrdm);
-                pwrdm_del_wkdep(clkdm->pwrdm, autodep->pwrdm);
+                pwrdm_del_sleepdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr);
+                pwrdm_del_wkdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr);
         }
 }
 
@@ -179,7 +183,7 @@ void clkdm_init(struct clockdomain **clkdms,
 
         autodeps = init_autodeps;
         if (autodeps)
-                for (autodep = autodeps; autodep->pwrdm_name; autodep++)
+                for (autodep = autodeps; autodep->pwrdm.ptr; autodep++)
                         _autodep_lookup(autodep);
 }
 
@@ -202,20 +206,20 @@ int clkdm_register(struct clockdomain *clkdm)
         if (!omap_chip_is(clkdm->omap_chip))
                 return -EINVAL;
 
-        pwrdm = pwrdm_lookup(clkdm->pwrdm_name);
+        pwrdm = pwrdm_lookup(clkdm->pwrdm.name);
         if (!pwrdm) {
-                pr_debug("clockdomain: clkdm_register %s: powerdomain %s "
-                         "does not exist\n", clkdm->name, clkdm->pwrdm_name);
+                pr_err("clockdomain: %s: powerdomain %s does not exist\n",
+                        clkdm->name, clkdm->pwrdm.name);
                 return -EINVAL;
         }
-        clkdm->pwrdm = pwrdm;
+        clkdm->pwrdm.ptr = pwrdm;
 
         mutex_lock(&clkdm_mutex);
         /* Verify that the clockdomain is not already registered */
         if (_clkdm_lookup(clkdm->name)) {
                 ret = -EEXIST;
                 goto cr_unlock;
-        };
+        }
 
         list_add(&clkdm->node, &clkdm_list);
 
@@ -242,7 +246,7 @@ int clkdm_unregister(struct clockdomain *clkdm)
         if (!clkdm)
                 return -EINVAL;
 
-        pwrdm_del_clkdm(clkdm->pwrdm, clkdm);
+        pwrdm_del_clkdm(clkdm->pwrdm.ptr, clkdm);
 
         mutex_lock(&clkdm_mutex);
         list_del(&clkdm->node);
@@ -327,7 +331,7 @@ struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm)
         if (!clkdm)
                 return NULL;
 
-        return clkdm->pwrdm;
+        return clkdm->pwrdm.ptr;
 }
 
 
@@ -348,7 +352,7 @@ static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm)
         if (!clkdm)
                 return -EINVAL;
 
-        v = cm_read_mod_reg(clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
+        v = cm_read_mod_reg(clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
         v &= clkdm->clktrctrl_mask;
         v >>= __ffs(clkdm->clktrctrl_mask);
 
@@ -380,7 +384,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
         if (cpu_is_omap24xx()) {
 
                 cm_set_mod_reg_bits(OMAP24XX_FORCESTATE,
-                                    clkdm->pwrdm->prcm_offs, PM_PWSTCTRL);
+                                    clkdm->pwrdm.ptr->prcm_offs, PM_PWSTCTRL);
 
         } else if (cpu_is_omap34xx()) {
 
@@ -388,7 +392,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
                          __ffs(clkdm->clktrctrl_mask));
 
                 cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v,
-                                    clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
+                                    clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
 
         } else {
                 BUG();
@@ -422,7 +426,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
         if (cpu_is_omap24xx()) {
 
                 cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE,
-                                      clkdm->pwrdm->prcm_offs, PM_PWSTCTRL);
+                                      clkdm->pwrdm.ptr->prcm_offs, PM_PWSTCTRL);
 
         } else if (cpu_is_omap34xx()) {
 
@@ -430,7 +434,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
                          __ffs(clkdm->clktrctrl_mask));
 
                 cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v,
-                                    clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
+                                    clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
 
         } else {
                 BUG();
@@ -478,7 +482,7 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
 
         cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
                             v << __ffs(clkdm->clktrctrl_mask),
-                            clkdm->pwrdm->prcm_offs,
+                            clkdm->pwrdm.ptr->prcm_offs,
                             CM_CLKSTCTRL);
 }
 
@@ -516,7 +520,7 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
 
         cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
                             v << __ffs(clkdm->clktrctrl_mask),
-                            clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
+                            clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
 
         if (atomic_read(&clkdm->usecount) > 0)
                 _clkdm_del_autodeps(clkdm);
@@ -567,6 +571,8 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
         else
                 omap2_clkdm_wakeup(clkdm);
 
+        pwrdm_wait_transition(clkdm->pwrdm.ptr);
+
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h
index cd86dcc7b424..281d5da19188 100644
--- a/arch/arm/mach-omap2/clockdomains.h
+++ b/arch/arm/mach-omap2/clockdomains.h
@@ -14,12 +14,29 @@
 
 /*
  * OMAP2/3-common clockdomains
+ *
+ * Even though the 2420 has a single PRCM module from the
+ * interconnect's perspective, internally it does appear to have
+ * separate PRM and CM clockdomains.  The usual test case is
+ * sys_clkout/sys_clkout2.
  */
 
 /* This is an implicit clockdomain - it is never defined as such in TRM */
 static struct clockdomain wkup_clkdm = {
         .name           = "wkup_clkdm",
-        .pwrdm_name     = "wkup_pwrdm",
+        .pwrdm          = { .name = "wkup_pwrdm" },
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
+};
+
+static struct clockdomain prm_clkdm = {
+        .name           = "prm_clkdm",
+        .pwrdm          = { .name = "wkup_pwrdm" },
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
+};
+
+static struct clockdomain cm_clkdm = {
+        .name           = "cm_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 };
 
@@ -31,7 +48,7 @@ static struct clockdomain wkup_clkdm = {
 
 static struct clockdomain mpu_2420_clkdm = {
         .name           = "mpu_clkdm",
-        .pwrdm_name     = "mpu_pwrdm",
+        .pwrdm          = { .name = "mpu_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
@@ -39,7 +56,7 @@ static struct clockdomain mpu_2420_clkdm = {
 
 static struct clockdomain iva1_2420_clkdm = {
         .name           = "iva1_clkdm",
-        .pwrdm_name     = "dsp_pwrdm",
+        .pwrdm          = { .name = "dsp_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
         .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
@@ -56,7 +73,7 @@ static struct clockdomain iva1_2420_clkdm = {
 
 static struct clockdomain mpu_2430_clkdm = {
         .name           = "mpu_clkdm",
-        .pwrdm_name     = "mpu_pwrdm",
+        .pwrdm          = { .name = "mpu_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
@@ -64,7 +81,7 @@ static struct clockdomain mpu_2430_clkdm = {
 
 static struct clockdomain mdm_clkdm = {
         .name           = "mdm_clkdm",
-        .pwrdm_name     = "mdm_pwrdm",
+        .pwrdm          = { .name = "mdm_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
         .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
@@ -81,7 +98,7 @@ static struct clockdomain mdm_clkdm = {
 
 static struct clockdomain dsp_clkdm = {
         .name           = "dsp_clkdm",
-        .pwrdm_name     = "dsp_pwrdm",
+        .pwrdm          = { .name = "dsp_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
@@ -89,7 +106,7 @@ static struct clockdomain dsp_clkdm = {
 
 static struct clockdomain gfx_24xx_clkdm = {
         .name           = "gfx_clkdm",
-        .pwrdm_name     = "gfx_pwrdm",
+        .pwrdm          = { .name = "gfx_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
@@ -97,7 +114,7 @@ static struct clockdomain gfx_24xx_clkdm = {
 
 static struct clockdomain core_l3_24xx_clkdm = {
         .name           = "core_l3_clkdm",
-        .pwrdm_name     = "core_pwrdm",
+        .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
@@ -105,7 +122,7 @@ static struct clockdomain core_l3_24xx_clkdm = {
 
 static struct clockdomain core_l4_24xx_clkdm = {
         .name           = "core_l4_clkdm",
-        .pwrdm_name     = "core_pwrdm",
+        .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
@@ -113,7 +130,7 @@ static struct clockdomain core_l4_24xx_clkdm = {
 
 static struct clockdomain dss_24xx_clkdm = {
         .name           = "dss_clkdm",
-        .pwrdm_name     = "core_pwrdm",
+        .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
@@ -130,7 +147,7 @@ static struct clockdomain dss_24xx_clkdm = {
 
 static struct clockdomain mpu_34xx_clkdm = {
         .name           = "mpu_clkdm",
-        .pwrdm_name     = "mpu_pwrdm",
+        .pwrdm          = { .name = "mpu_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -138,7 +155,7 @@ static struct clockdomain mpu_34xx_clkdm = {
 
 static struct clockdomain neon_clkdm = {
         .name           = "neon_clkdm",
-        .pwrdm_name     = "neon_pwrdm",
+        .pwrdm          = { .name = "neon_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -146,7 +163,7 @@ static struct clockdomain neon_clkdm = {
 
 static struct clockdomain iva2_clkdm = {
         .name           = "iva2_clkdm",
-        .pwrdm_name     = "iva2_pwrdm",
+        .pwrdm          = { .name = "iva2_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -154,7 +171,7 @@ static struct clockdomain iva2_clkdm = {
 
 static struct clockdomain gfx_3430es1_clkdm = {
         .name           = "gfx_clkdm",
-        .pwrdm_name     = "gfx_pwrdm",
+        .pwrdm          = { .name = "gfx_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
         .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
@@ -162,10 +179,10 @@ static struct clockdomain gfx_3430es1_clkdm = {
 
 static struct clockdomain sgx_clkdm = {
         .name           = "sgx_clkdm",
-        .pwrdm_name     = "sgx_pwrdm",
+        .pwrdm          = { .name = "sgx_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 };
 
 /*
@@ -177,7 +194,7 @@ static struct clockdomain sgx_clkdm = {
  */
 static struct clockdomain d2d_clkdm = {
         .name           = "d2d_clkdm",
-        .pwrdm_name     = "core_pwrdm",
+        .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
         .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -185,7 +202,7 @@ static struct clockdomain d2d_clkdm = {
 
 static struct clockdomain core_l3_34xx_clkdm = {
         .name           = "core_l3_clkdm",
-        .pwrdm_name     = "core_pwrdm",
+        .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -193,7 +210,7 @@ static struct clockdomain core_l3_34xx_clkdm = {
 
 static struct clockdomain core_l4_34xx_clkdm = {
         .name           = "core_l4_clkdm",
-        .pwrdm_name     = "core_pwrdm",
+        .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -201,7 +218,7 @@ static struct clockdomain core_l4_34xx_clkdm = {
 
 static struct clockdomain dss_34xx_clkdm = {
         .name           = "dss_clkdm",
-        .pwrdm_name     = "dss_pwrdm",
+        .pwrdm          = { .name = "dss_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -209,7 +226,7 @@ static struct clockdomain dss_34xx_clkdm = {
 
 static struct clockdomain cam_clkdm = {
         .name           = "cam_clkdm",
-        .pwrdm_name     = "cam_pwrdm",
+        .pwrdm          = { .name = "cam_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -217,28 +234,62 @@ static struct clockdomain cam_clkdm = {
 
 static struct clockdomain usbhost_clkdm = {
         .name           = "usbhost_clkdm",
-        .pwrdm_name     = "usbhost_pwrdm",
+        .pwrdm          = { .name = "usbhost_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 };
 
 static struct clockdomain per_clkdm = {
         .name           = "per_clkdm",
-        .pwrdm_name     = "per_pwrdm",
+        .pwrdm          = { .name = "per_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
+/*
+ * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
+ * switched of even if sdti is in use
+ */
 static struct clockdomain emu_clkdm = {
         .name           = "emu_clkdm",
-        .pwrdm_name     = "emu_pwrdm",
-        .flags          = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP,
+        .pwrdm          = { .name = "emu_pwrdm" },
+        .flags          = /* CLKDM_CAN_ENABLE_AUTO |  */CLKDM_CAN_SWSUP,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
+static struct clockdomain dpll1_clkdm = {
+        .name           = "dpll1_clkdm",
+        .pwrdm          = { .name = "dpll1_pwrdm" },
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct clockdomain dpll2_clkdm = {
+        .name           = "dpll2_clkdm",
+        .pwrdm          = { .name = "dpll2_pwrdm" },
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct clockdomain dpll3_clkdm = {
+        .name           = "dpll3_clkdm",
+        .pwrdm          = { .name = "dpll3_pwrdm" },
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct clockdomain dpll4_clkdm = {
+        .name           = "dpll4_clkdm",
+        .pwrdm          = { .name = "dpll4_pwrdm" },
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct clockdomain dpll5_clkdm = {
+        .name           = "dpll5_clkdm",
+        .pwrdm          = { .name = "dpll5_pwrdm" },
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
+};
+
 #endif   /* CONFIG_ARCH_OMAP34XX */
 
 /*
@@ -247,14 +298,16 @@ static struct clockdomain emu_clkdm = {
 
 static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
         {
-                .pwrdm_name = "mpu_pwrdm",
+                .pwrdm     = { .name = "mpu_pwrdm" },
                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
         },
         {
-                .pwrdm_name = "iva2_pwrdm",
+                .pwrdm     = { .name = "iva2_pwrdm" },
                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
         },
-        { NULL }
+        {
+                .pwrdm     = { .name = NULL },
+        }
 };
 
 /*
@@ -264,6 +317,8 @@ static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
 static struct clockdomain *clockdomains_omap[] = {
 
         &wkup_clkdm,
+        &cm_clkdm,
+        &prm_clkdm,
 
 #ifdef CONFIG_ARCH_OMAP2420
         &mpu_2420_clkdm,
@@ -297,6 +352,11 @@ static struct clockdomain *clockdomains_omap[] = {
         &usbhost_clkdm,
         &per_clkdm,
         &emu_clkdm,
+        &dpll1_clkdm,
+        &dpll2_clkdm,
+        &dpll3_clkdm,
+        &dpll4_clkdm,
+        &dpll5_clkdm,
 #endif
 
         NULL,
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index 1098ecfab861..297a2fe634ea 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -110,35 +110,56 @@
 #define OMAP24XX_EN_DES                                 (1 << 0)
 
 /* CM_IDLEST1_CORE specific bits */
-#define OMAP24XX_ST_MAILBOXES                           (1 << 30)
-#define OMAP24XX_ST_WDT4                                (1 << 29)
-#define OMAP2420_ST_WDT3                                (1 << 28)
-#define OMAP24XX_ST_MSPRO                               (1 << 27)
-#define OMAP24XX_ST_FAC                                 (1 << 25)
-#define OMAP2420_ST_EAC                                 (1 << 24)
-#define OMAP24XX_ST_HDQ                                 (1 << 23)
-#define OMAP24XX_ST_I2C2                                (1 << 20)
-#define OMAP24XX_ST_I2C1                                (1 << 19)
-#define OMAP24XX_ST_MCBSP2                              (1 << 16)
-#define OMAP24XX_ST_MCBSP1                              (1 << 15)
-#define OMAP24XX_ST_DSS                                 (1 << 0)
+#define OMAP24XX_ST_MAILBOXES_SHIFT                     30
+#define OMAP24XX_ST_MAILBOXES_MASK                      (1 << 30)
+#define OMAP24XX_ST_WDT4_SHIFT                          29
+#define OMAP24XX_ST_WDT4_MASK                           (1 << 29)
+#define OMAP2420_ST_WDT3_SHIFT                          28
+#define OMAP2420_ST_WDT3_MASK                           (1 << 28)
+#define OMAP24XX_ST_MSPRO_SHIFT                         27
+#define OMAP24XX_ST_MSPRO_MASK                          (1 << 27)
+#define OMAP24XX_ST_FAC_SHIFT                           25
+#define OMAP24XX_ST_FAC_MASK                            (1 << 25)
+#define OMAP2420_ST_EAC_SHIFT                           24
+#define OMAP2420_ST_EAC_MASK                            (1 << 24)
+#define OMAP24XX_ST_HDQ_SHIFT                           23
+#define OMAP24XX_ST_HDQ_MASK                            (1 << 23)
+#define OMAP2420_ST_I2C2_SHIFT                          20
+#define OMAP2420_ST_I2C2_MASK                           (1 << 20)
+#define OMAP2420_ST_I2C1_SHIFT                          19
+#define OMAP2420_ST_I2C1_MASK                           (1 << 19)
+#define OMAP24XX_ST_MCBSP2_SHIFT                        16
+#define OMAP24XX_ST_MCBSP2_MASK                         (1 << 16)
+#define OMAP24XX_ST_MCBSP1_SHIFT                        15
+#define OMAP24XX_ST_MCBSP1_MASK                         (1 << 15)
+#define OMAP24XX_ST_DSS_SHIFT                           0
+#define OMAP24XX_ST_DSS_MASK                            (1 << 0)
 
 /* CM_IDLEST2_CORE */
-#define OMAP2430_ST_MCBSP5                              (1 << 5)
-#define OMAP2430_ST_MCBSP4                              (1 << 4)
-#define OMAP2430_ST_MCBSP3                              (1 << 3)
-#define OMAP24XX_ST_SSI                                 (1 << 1)
+#define OMAP2430_ST_MCBSP5_SHIFT                        5
+#define OMAP2430_ST_MCBSP5_MASK                         (1 << 5)
+#define OMAP2430_ST_MCBSP4_SHIFT                                4
+#define OMAP2430_ST_MCBSP4_MASK                         (1 << 4)
+#define OMAP2430_ST_MCBSP3_SHIFT                                3
+#define OMAP2430_ST_MCBSP3_MASK                         (1 << 3)
+#define OMAP24XX_ST_SSI_SHIFT                           1
+#define OMAP24XX_ST_SSI_MASK                            (1 << 1)
 
 /* CM_IDLEST3_CORE */
 /* 2430 only */
-#define OMAP2430_ST_SDRC                                (1 << 2)
+#define OMAP2430_ST_SDRC_MASK                           (1 << 2)
 
 /* CM_IDLEST4_CORE */
-#define OMAP24XX_ST_PKA                                 (1 << 4)
-#define OMAP24XX_ST_AES                                 (1 << 3)
-#define OMAP24XX_ST_RNG                                 (1 << 2)
-#define OMAP24XX_ST_SHA                                 (1 << 1)
-#define OMAP24XX_ST_DES                                 (1 << 0)
+#define OMAP24XX_ST_PKA_SHIFT                           4
+#define OMAP24XX_ST_PKA_MASK                            (1 << 4)
+#define OMAP24XX_ST_AES_SHIFT                           3
+#define OMAP24XX_ST_AES_MASK                            (1 << 3)
+#define OMAP24XX_ST_RNG_SHIFT                           2
+#define OMAP24XX_ST_RNG_MASK                            (1 << 2)
+#define OMAP24XX_ST_SHA_SHIFT                           1
+#define OMAP24XX_ST_SHA_MASK                            (1 << 1)
+#define OMAP24XX_ST_DES_SHIFT                           0
+#define OMAP24XX_ST_DES_MASK                            (1 << 0)
 
 /* CM_AUTOIDLE1_CORE */
 #define OMAP24XX_AUTO_CAM                               (1 << 31)
@@ -275,11 +296,16 @@
 #define OMAP24XX_EN_32KSYNC                             (1 << 1)
 
 /* CM_IDLEST_WKUP specific bits */
-#define OMAP2430_ST_ICR                                 (1 << 6)
-#define OMAP24XX_ST_OMAPCTRL                            (1 << 5)
-#define OMAP24XX_ST_WDT1                                (1 << 4)
-#define OMAP24XX_ST_MPU_WDT                             (1 << 3)
-#define OMAP24XX_ST_32KSYNC                             (1 << 1)
+#define OMAP2430_ST_ICR_SHIFT                           6
+#define OMAP2430_ST_ICR_MASK                            (1 << 6)
+#define OMAP24XX_ST_OMAPCTRL_SHIFT                      5
+#define OMAP24XX_ST_OMAPCTRL_MASK                       (1 << 5)
+#define OMAP24XX_ST_WDT1_SHIFT                          4
+#define OMAP24XX_ST_WDT1_MASK                           (1 << 4)
+#define OMAP24XX_ST_MPU_WDT_SHIFT                       3
+#define OMAP24XX_ST_MPU_WDT_MASK                        (1 << 3)
+#define OMAP24XX_ST_32KSYNC_SHIFT                       1
+#define OMAP24XX_ST_32KSYNC_MASK                        (1 << 1)
 
 /* CM_AUTOIDLE_WKUP */
 #define OMAP24XX_AUTO_OMAPCTRL                          (1 << 5)
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 219f5c8d9659..6f3f5a36aae6 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -183,31 +183,58 @@
 #define OMAP3430ES2_EN_CPEFUSE_MASK                     (1 << 0)
 
 /* CM_IDLEST1_CORE specific bits */
-#define OMAP3430_ST_ICR                                 (1 << 29)
-#define OMAP3430_ST_AES2                                (1 << 28)
-#define OMAP3430_ST_SHA12                               (1 << 27)
-#define OMAP3430_ST_DES2                                (1 << 26)
-#define OMAP3430_ST_MSPRO                               (1 << 23)
-#define OMAP3430_ST_HDQ                                 (1 << 22)
-#define OMAP3430ES1_ST_FAC                              (1 << 8)
-#define OMAP3430ES1_ST_MAILBOXES                        (1 << 7)
-#define OMAP3430_ST_OMAPCTRL                            (1 << 6)
-#define OMAP3430_ST_SDMA                                (1 << 2)
-#define OMAP3430_ST_SDRC                                (1 << 1)
-#define OMAP3430_ST_SSI                                 (1 << 0)
+#define OMAP3430ES2_ST_MMC3_SHIFT                       30
+#define OMAP3430ES2_ST_MMC3_MASK                        (1 << 30)
+#define OMAP3430_ST_ICR_SHIFT                           29
+#define OMAP3430_ST_ICR_MASK                            (1 << 29)
+#define OMAP3430_ST_AES2_SHIFT                          28
+#define OMAP3430_ST_AES2_MASK                           (1 << 28)
+#define OMAP3430_ST_SHA12_SHIFT                         27
+#define OMAP3430_ST_SHA12_MASK                          (1 << 27)
+#define OMAP3430_ST_DES2_SHIFT                          26
+#define OMAP3430_ST_DES2_MASK                           (1 << 26)
+#define OMAP3430_ST_MSPRO_SHIFT                         23
+#define OMAP3430_ST_MSPRO_MASK                          (1 << 23)
+#define OMAP3430_ST_HDQ_SHIFT                           22
+#define OMAP3430_ST_HDQ_MASK                            (1 << 22)
+#define OMAP3430ES1_ST_FAC_SHIFT                        8
+#define OMAP3430ES1_ST_FAC_MASK                         (1 << 8)
+#define OMAP3430ES2_ST_SSI_IDLE_SHIFT                   8
+#define OMAP3430ES2_ST_SSI_IDLE_MASK                    (1 << 8)
+#define OMAP3430_ST_MAILBOXES_SHIFT                     7
+#define OMAP3430_ST_MAILBOXES_MASK                      (1 << 7)
+#define OMAP3430_ST_OMAPCTRL_SHIFT                      6
+#define OMAP3430_ST_OMAPCTRL_MASK                       (1 << 6)
+#define OMAP3430_ST_SDMA_SHIFT                          2
+#define OMAP3430_ST_SDMA_MASK                           (1 << 2)
+#define OMAP3430_ST_SDRC_SHIFT                          1
+#define OMAP3430_ST_SDRC_MASK                           (1 << 1)
+#define OMAP3430_ST_SSI_STDBY_SHIFT                     0
+#define OMAP3430_ST_SSI_STDBY_MASK                      (1 << 0)
 
 /* CM_IDLEST2_CORE */
-#define OMAP3430_ST_PKA                                 (1 << 4)
-#define OMAP3430_ST_AES1                                (1 << 3)
-#define OMAP3430_ST_RNG                                 (1 << 2)
-#define OMAP3430_ST_SHA11                               (1 << 1)
-#define OMAP3430_ST_DES1                                (1 << 0)
+#define OMAP3430_ST_PKA_SHIFT                           4
+#define OMAP3430_ST_PKA_MASK                            (1 << 4)
+#define OMAP3430_ST_AES1_SHIFT                          3
+#define OMAP3430_ST_AES1_MASK                           (1 << 3)
+#define OMAP3430_ST_RNG_SHIFT                           2
+#define OMAP3430_ST_RNG_MASK                            (1 << 2)
+#define OMAP3430_ST_SHA11_SHIFT                         1
+#define OMAP3430_ST_SHA11_MASK                          (1 << 1)
+#define OMAP3430_ST_DES1_SHIFT                          0
+#define OMAP3430_ST_DES1_MASK                           (1 << 0)
 
 /* CM_IDLEST3_CORE */
 #define OMAP3430ES2_ST_USBTLL_SHIFT                     2
 #define OMAP3430ES2_ST_USBTLL_MASK                      (1 << 2)
+#define OMAP3430ES2_ST_CPEFUSE_SHIFT                    0
+#define OMAP3430ES2_ST_CPEFUSE_MASK                     (1 << 0)
 
 /* CM_AUTOIDLE1_CORE */
+#define OMAP3430ES2_AUTO_MMC3                           (1 << 30)
+#define OMAP3430ES2_AUTO_MMC3_SHIFT                     30
+#define OMAP3430ES2_AUTO_ICR                            (1 << 29)
+#define OMAP3430ES2_AUTO_ICR_SHIFT                      29
 #define OMAP3430_AUTO_AES2                              (1 << 28)
 #define OMAP3430_AUTO_AES2_SHIFT                        28
 #define OMAP3430_AUTO_SHA12                             (1 << 27)
@@ -276,6 +303,9 @@
 #define OMAP3430_AUTO_DES1_SHIFT                        0
 
 /* CM_AUTOIDLE3_CORE */
+#define OMAP3430ES2_AUTO_USBHOST                        (1 << 0)
+#define OMAP3430ES2_AUTO_USBHOST_SHIFT                  0
+#define OMAP3430ES2_AUTO_USBTLL                         (1 << 2)
 #define OMAP3430ES2_AUTO_USBTLL_SHIFT                   2
 #define OMAP3430ES2_AUTO_USBTLL_MASK                    (1 << 2)
 
@@ -332,8 +362,12 @@
 #define OMAP3430ES1_CLKACTIVITY_GFX_MASK                (1 << 0)
 
 /* CM_FCLKEN_SGX */
-#define OMAP3430ES2_EN_SGX_SHIFT                        1
-#define OMAP3430ES2_EN_SGX_MASK                         (1 << 1)
+#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT          1
+#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK           (1 << 1)
+
+/* CM_ICLKEN_SGX */
+#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT          0
+#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK           (1 << 0)
 
 /* CM_CLKSEL_SGX */
 #define OMAP3430ES2_CLKSEL_SGX_SHIFT                    0
@@ -349,6 +383,7 @@
 
 /* CM_FCLKEN_WKUP specific bits */
 #define OMAP3430ES2_EN_USIMOCP_SHIFT                    9
+#define OMAP3430ES2_EN_USIMOCP_MASK                     (1 << 9)
 
 /* CM_ICLKEN_WKUP specific bits */
 #define OMAP3430_EN_WDT1                                (1 << 4)
@@ -357,11 +392,18 @@
 #define OMAP3430_EN_32KSYNC_SHIFT                       2
 
 /* CM_IDLEST_WKUP specific bits */
-#define OMAP3430_ST_WDT2                                (1 << 5)
-#define OMAP3430_ST_WDT1                                (1 << 4)
-#define OMAP3430_ST_32KSYNC                             (1 << 2)
+#define OMAP3430ES2_ST_USIMOCP_SHIFT                    9
+#define OMAP3430ES2_ST_USIMOCP_MASK                     (1 << 9)
+#define OMAP3430_ST_WDT2_SHIFT                          5
+#define OMAP3430_ST_WDT2_MASK                           (1 << 5)
+#define OMAP3430_ST_WDT1_SHIFT                          4
+#define OMAP3430_ST_WDT1_MASK                           (1 << 4)
+#define OMAP3430_ST_32KSYNC_SHIFT                       2
+#define OMAP3430_ST_32KSYNC_MASK                        (1 << 2)
 
 /* CM_AUTOIDLE_WKUP */
+#define OMAP3430ES2_AUTO_USIMOCP                                (1 << 9)
+#define OMAP3430ES2_AUTO_USIMOCP_SHIFT                  9
 #define OMAP3430_AUTO_WDT2                              (1 << 5)
 #define OMAP3430_AUTO_WDT2_SHIFT                        5
 #define OMAP3430_AUTO_WDT1                              (1 << 4)
@@ -426,6 +468,8 @@
 #define OMAP3430_ST_CORE_CLK_MASK                       (1 << 0)
 
 /* CM_IDLEST2_CKGEN */
+#define OMAP3430ES2_ST_USIM_CLK_SHIFT                   2
+#define OMAP3430ES2_ST_USIM_CLK_MASK                    (1 << 2)
 #define OMAP3430ES2_ST_120M_CLK_SHIFT                   1
 #define OMAP3430ES2_ST_120M_CLK_MASK                    (1 << 1)
 #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT                0
@@ -449,8 +493,12 @@
 #define OMAP3430_CORE_DPLL_MULT_MASK                    (0x7ff << 16)
 #define OMAP3430_CORE_DPLL_DIV_SHIFT                    8
 #define OMAP3430_CORE_DPLL_DIV_MASK                     (0x7f << 8)
-#define OMAP3430_SOURCE_54M                             (1 << 5)
-#define OMAP3430_SOURCE_48M                             (1 << 3)
+#define OMAP3430_SOURCE_96M_SHIFT                       6
+#define OMAP3430_SOURCE_96M_MASK                        (1 << 6)
+#define OMAP3430_SOURCE_54M_SHIFT                       5
+#define OMAP3430_SOURCE_54M_MASK                        (1 << 5)
+#define OMAP3430_SOURCE_48M_SHIFT                       3
+#define OMAP3430_SOURCE_48M_MASK                        (1 << 3)
 
 /* CM_CLKSEL2_PLL */
 #define OMAP3430_PERIPH_DPLL_MULT_SHIFT                 8
@@ -493,7 +541,12 @@
 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT             0
 
 /* CM_IDLEST_DSS */
-#define OMAP3430_ST_DSS                                 (1 << 0)
+#define OMAP3430ES2_ST_DSS_IDLE_SHIFT                   1
+#define OMAP3430ES2_ST_DSS_IDLE_MASK                    (1 << 1)
+#define OMAP3430ES2_ST_DSS_STDBY_SHIFT                  0
+#define OMAP3430ES2_ST_DSS_STDBY_MASK                   (1 << 0)
+#define OMAP3430ES1_ST_DSS_SHIFT                        0
+#define OMAP3430ES1_ST_DSS_MASK                         (1 << 0)
 
 /* CM_AUTOIDLE_DSS */
 #define OMAP3430_AUTO_DSS                               (1 << 0)
@@ -516,6 +569,8 @@
 #define OMAP3430_CLKACTIVITY_DSS_MASK                   (1 << 0)
 
 /* CM_FCLKEN_CAM specific bits */
+#define OMAP3430_EN_CSI2                                (1 << 1)
+#define OMAP3430_EN_CSI2_SHIFT                          1
 
 /* CM_ICLKEN_CAM specific bits */
 
@@ -545,10 +600,14 @@
 /* CM_ICLKEN_PER specific bits */
 
 /* CM_IDLEST_PER */
-#define OMAP3430_ST_WDT3                                (1 << 12)
-#define OMAP3430_ST_MCBSP4                              (1 << 2)
-#define OMAP3430_ST_MCBSP3                              (1 << 1)
-#define OMAP3430_ST_MCBSP2                              (1 << 0)
+#define OMAP3430_ST_WDT3_SHIFT                          12
+#define OMAP3430_ST_WDT3_MASK                           (1 << 12)
+#define OMAP3430_ST_MCBSP4_SHIFT                        2
+#define OMAP3430_ST_MCBSP4_MASK                         (1 << 2)
+#define OMAP3430_ST_MCBSP3_SHIFT                        1
+#define OMAP3430_ST_MCBSP3_MASK                         (1 << 1)
+#define OMAP3430_ST_MCBSP2_SHIFT                        0
+#define OMAP3430_ST_MCBSP2_MASK                         (1 << 0)
 
 /* CM_AUTOIDLE_PER */
 #define OMAP3430_AUTO_GPIO6                             (1 << 17)
@@ -676,6 +735,10 @@
 #define OMAP3430ES2_EN_USBHOST_MASK                     (1 << 0)
 
 /* CM_IDLEST_USBHOST */
+#define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT               1
+#define OMAP3430ES2_ST_USBHOST_IDLE_MASK                (1 << 1)
+#define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT              0
+#define OMAP3430ES2_ST_USBHOST_STDBY_MASK               (1 << 0)
 
 /* CM_AUTOIDLE_USBHOST */
 #define OMAP3430ES2_AUTO_USBHOST_SHIFT                  0
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index ce03fa750775..d6b4b2f8722f 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -28,13 +28,121 @@
 #include <mach/eac.h>
 #include <mach/mmc.h>
 
-#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
-#define OMAP2_MBOX_BASE         IO_ADDRESS(OMAP24XX_MAILBOX_BASE)
+#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
 
-static struct resource mbox_resources[] = {
+static struct resource cam_resources[] = {
         {
-                .start          = OMAP2_MBOX_BASE,
-                .end            = OMAP2_MBOX_BASE + 0x11f,
+                .start          = OMAP24XX_CAMERA_BASE,
+                .end            = OMAP24XX_CAMERA_BASE + 0xfff,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = INT_24XX_CAM_IRQ,
+                .flags          = IORESOURCE_IRQ,
+        }
+};
+
+static struct platform_device omap_cam_device = {
+        .name           = "omap24xxcam",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(cam_resources),
+        .resource       = cam_resources,
+};
+
+static inline void omap_init_camera(void)
+{
+        platform_device_register(&omap_cam_device);
+}
+
+#elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
+
+static struct resource omap3isp_resources[] = {
+        {
+                .start          = OMAP3430_ISP_BASE,
+                .end            = OMAP3430_ISP_END,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = OMAP3430_ISP_CBUFF_BASE,
+                .end            = OMAP3430_ISP_CBUFF_END,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = OMAP3430_ISP_CCP2_BASE,
+                .end            = OMAP3430_ISP_CCP2_END,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = OMAP3430_ISP_CCDC_BASE,
+                .end            = OMAP3430_ISP_CCDC_END,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = OMAP3430_ISP_HIST_BASE,
+                .end            = OMAP3430_ISP_HIST_END,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = OMAP3430_ISP_H3A_BASE,
+                .end            = OMAP3430_ISP_H3A_END,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = OMAP3430_ISP_PREV_BASE,
+                .end            = OMAP3430_ISP_PREV_END,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = OMAP3430_ISP_RESZ_BASE,
+                .end            = OMAP3430_ISP_RESZ_END,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = OMAP3430_ISP_SBL_BASE,
+                .end            = OMAP3430_ISP_SBL_END,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = OMAP3430_ISP_CSI2A_BASE,
+                .end            = OMAP3430_ISP_CSI2A_END,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = OMAP3430_ISP_CSI2PHY_BASE,
+                .end            = OMAP3430_ISP_CSI2PHY_END,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = INT_34XX_CAM_IRQ,
+                .flags          = IORESOURCE_IRQ,
+        }
+};
+
+static struct platform_device omap3isp_device = {
+        .name           = "omap3isp",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(omap3isp_resources),
+        .resource       = omap3isp_resources,
+};
+
+static inline void omap_init_camera(void)
+{
+        platform_device_register(&omap3isp_device);
+}
+#else
+static inline void omap_init_camera(void)
+{
+}
+#endif
+
+#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
+
+#define MBOX_REG_SIZE   0x120
+
+static struct resource omap2_mbox_resources[] = {
+        {
+                .start          = OMAP24XX_MAILBOX_BASE,
+                .end            = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
                 .flags          = IORESOURCE_MEM,
         },
         {
@@ -47,20 +155,40 @@ static struct resource mbox_resources[] = {
         },
 };
 
+static struct resource omap3_mbox_resources[] = {
+        {
+                .start          = OMAP34XX_MAILBOX_BASE,
+                .end            = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = INT_24XX_MAIL_U0_MPU,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
 static struct platform_device mbox_device = {
-        .name           = "mailbox",
+        .name           = "omap2-mailbox",
         .id             = -1,
-        .num_resources  = ARRAY_SIZE(mbox_resources),
-        .resource       = mbox_resources,
 };
 
 static inline void omap_init_mbox(void)
 {
+        if (cpu_is_omap2420()) {
+                mbox_device.num_resources = ARRAY_SIZE(omap2_mbox_resources);
+                mbox_device.resource = omap2_mbox_resources;
+        } else if (cpu_is_omap3430()) {
+                mbox_device.num_resources = ARRAY_SIZE(omap3_mbox_resources);
+                mbox_device.resource = omap3_mbox_resources;
+        } else {
+                pr_err("%s: platform not supported\n", __func__);
+                return;
+        }
         platform_device_register(&mbox_device);
 }
 #else
 static inline void omap_init_mbox(void) { }
-#endif
+#endif /* CONFIG_OMAP_MBOX_FWK */
 
 #if defined(CONFIG_OMAP_STI)
 
@@ -348,11 +476,12 @@ static void __init omap_hsmmc_reset(void)
                 }
 
                 dummy_pdev.id = i;
-                iclk = clk_get(dev, "mmchs_ick");
+                dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
+                iclk = clk_get(dev, "ick");
                 if (iclk && clk_enable(iclk))
                         iclk = NULL;
 
-                fclk = clk_get(dev, "mmchs_fck");
+                fclk = clk_get(dev, "fck");
                 if (fclk && clk_enable(fclk))
                         fclk = NULL;
 
@@ -506,6 +635,7 @@ static int __init omap2_init_devices(void)
          * in alphabetical order so they're easier to sort through.
          */
         omap_hsmmc_reset();
+        omap_init_camera();
         omap_init_mbox();
         omap_init_mcspi();
         omap_hdq_init();
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index b52a02fc7cd6..34b5914e0f8b 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -217,8 +217,13 @@ void __init omap2_check_revision(void)
                 omap_chip.oc = CHIP_IS_OMAP3430;
                 if (omap_rev() == OMAP3430_REV_ES1_0)
                         omap_chip.oc |= CHIP_IS_OMAP3430ES1;
-                else if (omap_rev() > OMAP3430_REV_ES1_0)
+                else if (omap_rev() >= OMAP3430_REV_ES2_0 &&
+                         omap_rev() <= OMAP3430_REV_ES2_1)
                         omap_chip.oc |= CHIP_IS_OMAP3430ES2;
+                else if (omap_rev() == OMAP3430_REV_ES3_0)
+                        omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
+                else if (omap_rev() == OMAP3430_REV_ES3_1)
+                        omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
         } else {
                 pr_err("Uninitialized omap_chip, please fix!\n");
         }
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 5ea64f926ed5..916fcd3a2328 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -27,8 +27,8 @@
 #include <mach/mux.h>
 #include <mach/omapfb.h>
 #include <mach/sram.h>
-
-#include "memory.h"
+#include <mach/sdrc.h>
+#include <mach/gpmc.h>
 
 #include "clock.h"
 
@@ -195,12 +195,12 @@ void __init omap2_map_common_io(void)
         omapfb_reserve_sdram();
 }
 
-void __init omap2_init_common_hw(void)
+void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
 {
         omap2_mux_init();
         pwrdm_init(powerdomains_omap);
         clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
         omap2_clk_init();
-        omap2_init_memory();
+        omap2_sdrc_init(sp);
         gpmc_init();
 }
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 32b7af3c610b..fd5b8a5925cc 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -1,9 +1,9 @@
 /*
- * Mailbox reservation modules for OMAP2
+ * Mailbox reservation modules for OMAP2/3
  *
- * Copyright (C) 2006 Nokia Corporation
+ * Copyright (C) 2006-2009 Nokia Corporation
  * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
- *        and  Paul Mundt <paul.mundt@nokia.com>
+ *        and  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -18,40 +18,22 @@
 #include <mach/mailbox.h>
 #include <mach/irqs.h>
 
-#define MAILBOX_REVISION                0x00
-#define MAILBOX_SYSCONFIG               0x10
-#define MAILBOX_SYSSTATUS               0x14
-#define MAILBOX_MESSAGE_0               0x40
-#define MAILBOX_MESSAGE_1               0x44
-#define MAILBOX_MESSAGE_2               0x48
-#define MAILBOX_MESSAGE_3               0x4c
-#define MAILBOX_MESSAGE_4               0x50
-#define MAILBOX_MESSAGE_5               0x54
-#define MAILBOX_FIFOSTATUS_0            0x80
-#define MAILBOX_FIFOSTATUS_1            0x84
-#define MAILBOX_FIFOSTATUS_2            0x88
-#define MAILBOX_FIFOSTATUS_3            0x8c
-#define MAILBOX_FIFOSTATUS_4            0x90
-#define MAILBOX_FIFOSTATUS_5            0x94
-#define MAILBOX_MSGSTATUS_0             0xc0
-#define MAILBOX_MSGSTATUS_1             0xc4
-#define MAILBOX_MSGSTATUS_2             0xc8
-#define MAILBOX_MSGSTATUS_3             0xcc
-#define MAILBOX_MSGSTATUS_4             0xd0
-#define MAILBOX_MSGSTATUS_5             0xd4
-#define MAILBOX_IRQSTATUS_0             0x100
-#define MAILBOX_IRQENABLE_0             0x104
-#define MAILBOX_IRQSTATUS_1             0x108
-#define MAILBOX_IRQENABLE_1             0x10c
-#define MAILBOX_IRQSTATUS_2             0x110
-#define MAILBOX_IRQENABLE_2             0x114
-#define MAILBOX_IRQSTATUS_3             0x118
-#define MAILBOX_IRQENABLE_3             0x11c
-
-static unsigned long mbox_base;
-
-#define MAILBOX_IRQ_NOTFULL(n)          (1 << (2 * (n) + 1))
-#define MAILBOX_IRQ_NEWMSG(n)           (1 << (2 * (n)))
+#define MAILBOX_REVISION                0x000
+#define MAILBOX_SYSCONFIG               0x010
+#define MAILBOX_SYSSTATUS               0x014
+#define MAILBOX_MESSAGE(m)              (0x040 + 4 * (m))
+#define MAILBOX_FIFOSTATUS(m)           (0x080 + 4 * (m))
+#define MAILBOX_MSGSTATUS(m)            (0x0c0 + 4 * (m))
+#define MAILBOX_IRQSTATUS(u)            (0x100 + 8 * (u))
+#define MAILBOX_IRQENABLE(u)            (0x104 + 8 * (u))
+
+#define MAILBOX_IRQ_NEWMSG(u)           (1 << (2 * (u)))
+#define MAILBOX_IRQ_NOTFULL(u)          (1 << (2 * (u) + 1))
+
+#define MBOX_REG_SIZE                   0x120
+#define MBOX_NR_REGS                    (MBOX_REG_SIZE / sizeof(u32))
+
+static void __iomem *mbox_base;
 
 struct omap_mbox2_fifo {
         unsigned long msg;
@@ -66,6 +48,7 @@ struct omap_mbox2_priv {
         unsigned long irqstatus;
         u32 newmsg_bit;
         u32 notfull_bit;
+        u32 ctx[MBOX_NR_REGS];
 };
 
 static struct clk *mbox_ick_handle;
@@ -73,14 +56,14 @@ static struct clk *mbox_ick_handle;
 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
                                   omap_mbox_type_t irq);
 
-static inline unsigned int mbox_read_reg(unsigned int reg)
+static inline unsigned int mbox_read_reg(size_t ofs)
 {
-        return __raw_readl(mbox_base + reg);
+        return __raw_readl(mbox_base + ofs);
 }
 
-static inline void mbox_write_reg(unsigned int val, unsigned int reg)
+static inline void mbox_write_reg(u32 val, size_t ofs)
 {
-        __raw_writel(val, mbox_base + reg);
+        __raw_writel(val, mbox_base + ofs);
 }
 
 /* Mailbox H/W preparations */
@@ -95,6 +78,9 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
         }
         clk_enable(mbox_ick_handle);
 
+        l = mbox_read_reg(MAILBOX_REVISION);
+        pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
+
         /* set smart-idle & autoidle */
         l = mbox_read_reg(MAILBOX_SYSCONFIG);
         l |= 0x00000011;
@@ -183,6 +169,32 @@ static int omap2_mbox_is_irq(struct omap_mbox *mbox,
         return (enable & status & bit);
 }
 
+static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
+{
+        int i;
+        struct omap_mbox2_priv *p = mbox->priv;
+
+        for (i = 0; i < MBOX_NR_REGS; i++) {
+                p->ctx[i] = mbox_read_reg(i * sizeof(u32));
+
+                dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
+                        i, p->ctx[i]);
+        }
+}
+
+static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
+{
+        int i;
+        struct omap_mbox2_priv *p = mbox->priv;
+
+        for (i = 0; i < MBOX_NR_REGS; i++) {
+                mbox_write_reg(p->ctx[i], i * sizeof(u32));
+
+                dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
+                        i, p->ctx[i]);
+        }
+}
+
 static struct omap_mbox_ops omap2_mbox_ops = {
         .type           = OMAP_MBOX_TYPE2,
         .startup        = omap2_mbox_startup,
@@ -195,6 +207,8 @@ static struct omap_mbox_ops omap2_mbox_ops = {
         .disable_irq    = omap2_mbox_disable_irq,
         .ack_irq        = omap2_mbox_ack_irq,
         .is_irq         = omap2_mbox_is_irq,
+        .save_ctx       = omap2_mbox_save_ctx,
+        .restore_ctx    = omap2_mbox_restore_ctx,
 };
 
 /*
@@ -209,15 +223,15 @@ static struct omap_mbox_ops omap2_mbox_ops = {
 /* DSP */
 static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
         .tx_fifo = {
-                .msg            = MAILBOX_MESSAGE_0,
-                .fifo_stat      = MAILBOX_FIFOSTATUS_0,
+                .msg            = MAILBOX_MESSAGE(0),
+                .fifo_stat      = MAILBOX_FIFOSTATUS(0),
         },
         .rx_fifo = {
-                .msg            = MAILBOX_MESSAGE_1,
-                .msg_stat       = MAILBOX_MSGSTATUS_1,
+                .msg            = MAILBOX_MESSAGE(1),
+                .msg_stat       = MAILBOX_MSGSTATUS(1),
         },
-        .irqenable      = MAILBOX_IRQENABLE_0,
-        .irqstatus      = MAILBOX_IRQSTATUS_0,
+        .irqenable      = MAILBOX_IRQENABLE(0),
+        .irqstatus      = MAILBOX_IRQSTATUS(0),
         .notfull_bit    = MAILBOX_IRQ_NOTFULL(0),
         .newmsg_bit     = MAILBOX_IRQ_NEWMSG(1),
 };
@@ -229,18 +243,18 @@ struct omap_mbox mbox_dsp_info = {
 };
 EXPORT_SYMBOL(mbox_dsp_info);
 
-/* IVA */
+#if defined(CONFIG_ARCH_OMAP2420) /* IVA */
 static struct omap_mbox2_priv omap2_mbox_iva_priv = {
         .tx_fifo = {
-                .msg            = MAILBOX_MESSAGE_2,
-                .fifo_stat      = MAILBOX_FIFOSTATUS_2,
+                .msg            = MAILBOX_MESSAGE(2),
+                .fifo_stat      = MAILBOX_FIFOSTATUS(2),
         },
         .rx_fifo = {
-                .msg            = MAILBOX_MESSAGE_3,
-                .msg_stat       = MAILBOX_MSGSTATUS_3,
+                .msg            = MAILBOX_MESSAGE(3),
+                .msg_stat       = MAILBOX_MSGSTATUS(3),
         },
-        .irqenable      = MAILBOX_IRQENABLE_3,
-        .irqstatus      = MAILBOX_IRQSTATUS_3,
+        .irqenable      = MAILBOX_IRQENABLE(3),
+        .irqstatus      = MAILBOX_IRQSTATUS(3),
         .notfull_bit    = MAILBOX_IRQ_NOTFULL(2),
         .newmsg_bit     = MAILBOX_IRQ_NEWMSG(3),
 };
@@ -250,17 +264,12 @@ static struct omap_mbox mbox_iva_info = {
         .ops    = &omap2_mbox_ops,
         .priv   = &omap2_mbox_iva_priv,
 };
+#endif
 
-static int __init omap2_mbox_probe(struct platform_device *pdev)
+static int __devinit omap2_mbox_probe(struct platform_device *pdev)
 {
         struct resource *res;
-        int ret = 0;
-
-        if (pdev->num_resources != 3) {
-                dev_err(&pdev->dev, "invalid number of resources: %d\n",
-                        pdev->num_resources);
-                return -ENODEV;
-        }
+        int ret;
 
         /* MBOX base */
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -268,42 +277,61 @@ static int __init omap2_mbox_probe(struct platform_device *pdev)
                 dev_err(&pdev->dev, "invalid mem resource\n");
                 return -ENODEV;
         }
-        mbox_base = res->start;
+        mbox_base = ioremap(res->start, res->end - res->start);
+        if (!mbox_base)
+                return -ENOMEM;
 
-        /* DSP IRQ */
-        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-        if (unlikely(!res)) {
+        /* DSP or IVA2 IRQ */
+        mbox_dsp_info.irq = platform_get_irq(pdev, 0);
+        if (mbox_dsp_info.irq < 0) {
                 dev_err(&pdev->dev, "invalid irq resource\n");
-                return -ENODEV;
+                ret = -ENODEV;
+                goto err_dsp;
         }
-        mbox_dsp_info.irq = res->start;
 
-        ret = omap_mbox_register(&mbox_dsp_info);
-
-        /* IVA IRQ */
-        res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
-        if (unlikely(!res)) {
-                dev_err(&pdev->dev, "invalid irq resource\n");
-                return -ENODEV;
+        ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info);
+        if (ret)
+                goto err_dsp;
+
+#if defined(CONFIG_ARCH_OMAP2420) /* IVA */
+        if (cpu_is_omap2420()) {
+                /* IVA IRQ */
+                res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+                if (unlikely(!res)) {
+                        dev_err(&pdev->dev, "invalid irq resource\n");
+                        ret = -ENODEV;
+                        goto err_iva1;
+                }
+                mbox_iva_info.irq = res->start;
+                ret = omap_mbox_register(&pdev->dev, &mbox_iva_info);
+                if (ret)
+                        goto err_iva1;
         }
-        mbox_iva_info.irq = res->start;
-
-        ret = omap_mbox_register(&mbox_iva_info);
+#endif
+        return 0;
 
+err_iva1:
+        omap_mbox_unregister(&mbox_dsp_info);
+err_dsp:
+        iounmap(mbox_base);
         return ret;
 }
 
-static int omap2_mbox_remove(struct platform_device *pdev)
+static int __devexit omap2_mbox_remove(struct platform_device *pdev)
 {
+#if defined(CONFIG_ARCH_OMAP2420)
+        omap_mbox_unregister(&mbox_iva_info);
+#endif
         omap_mbox_unregister(&mbox_dsp_info);
+        iounmap(mbox_base);
         return 0;
 }
 
 static struct platform_driver omap2_mbox_driver = {
         .probe = omap2_mbox_probe,
-        .remove = omap2_mbox_remove,
+        .remove = __devexit_p(omap2_mbox_remove),
         .driver = {
-                .name = "mailbox",
+                .name = "omap2-mailbox",
         },
 };
 
@@ -320,4 +348,7 @@ static void __exit omap2_mbox_exit(void)
 module_init(omap2_mbox_init);
 module_exit(omap2_mbox_exit);
 
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("omap mailbox: omap2/3 architecture specific functions");
+MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, Paul Mundt");
+MODULE_ALIAS("platform:omap2-mailbox");
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index a9e631fc1134..a5c0f0435cd6 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -24,8 +24,6 @@
 #include <mach/cpu.h>
 #include <mach/mcbsp.h>
 
-const char *clk_names[] = { "mcbsp_ick", "mcbsp_fck" };
-
 static void omap2_mcbsp2_mux_setup(void)
 {
         omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
@@ -57,8 +55,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
                 .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
                 .ops            = &omap2_mcbsp_ops,
-                .clk_names      = clk_names,
-                .num_clks       = 2,
         },
         {
                 .phys_base      = OMAP24XX_MCBSP2_BASE,
@@ -67,8 +63,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
                 .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
                 .ops            = &omap2_mcbsp_ops,
-                .clk_names      = clk_names,
-                .num_clks       = 2,
         },
 };
 #define OMAP2420_MCBSP_PDATA_SZ         ARRAY_SIZE(omap2420_mcbsp_pdata)
@@ -86,8 +80,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
                 .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
                 .ops            = &omap2_mcbsp_ops,
-                .clk_names      = clk_names,
-                .num_clks       = 2,
         },
         {
                 .phys_base      = OMAP24XX_MCBSP2_BASE,
@@ -96,8 +88,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
                 .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
                 .ops            = &omap2_mcbsp_ops,
-                .clk_names      = clk_names,
-                .num_clks       = 2,
         },
         {
                 .phys_base      = OMAP2430_MCBSP3_BASE,
@@ -106,8 +96,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
                 .rx_irq         = INT_24XX_MCBSP3_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP3_IRQ_TX,
                 .ops            = &omap2_mcbsp_ops,
-                .clk_names      = clk_names,
-                .num_clks       = 2,
         },
         {
                 .phys_base      = OMAP2430_MCBSP4_BASE,
@@ -116,8 +104,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
                 .rx_irq         = INT_24XX_MCBSP4_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP4_IRQ_TX,
                 .ops            = &omap2_mcbsp_ops,
-                .clk_names      = clk_names,
-                .num_clks       = 2,
         },
         {
                 .phys_base      = OMAP2430_MCBSP5_BASE,
@@ -126,8 +112,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
                 .rx_irq         = INT_24XX_MCBSP5_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP5_IRQ_TX,
                 .ops            = &omap2_mcbsp_ops,
-                .clk_names      = clk_names,
-                .num_clks       = 2,
         },
 };
 #define OMAP2430_MCBSP_PDATA_SZ         ARRAY_SIZE(omap2430_mcbsp_pdata)
@@ -145,8 +129,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                 .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
                 .ops            = &omap2_mcbsp_ops,
-                .clk_names      = clk_names,
-                .num_clks       = 2,
         },
         {
                 .phys_base      = OMAP34XX_MCBSP2_BASE,
@@ -155,8 +137,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                 .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
                 .ops            = &omap2_mcbsp_ops,
-                .clk_names      = clk_names,
-                .num_clks       = 2,
         },
         {
                 .phys_base      = OMAP34XX_MCBSP3_BASE,
@@ -165,8 +145,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                 .rx_irq         = INT_24XX_MCBSP3_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP3_IRQ_TX,
                 .ops            = &omap2_mcbsp_ops,
-                .clk_names      = clk_names,
-                .num_clks       = 2,
         },
         {
                 .phys_base      = OMAP34XX_MCBSP4_BASE,
@@ -175,8 +153,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                 .rx_irq         = INT_24XX_MCBSP4_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP4_IRQ_TX,
                 .ops            = &omap2_mcbsp_ops,
-                .clk_names      = clk_names,
-                .num_clks       = 2,
         },
         {
                 .phys_base      = OMAP34XX_MCBSP5_BASE,
@@ -185,8 +161,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                 .rx_irq         = INT_24XX_MCBSP5_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP5_IRQ_TX,
                 .ops            = &omap2_mcbsp_ops,
-                .clk_names      = clk_names,
-                .num_clks       = 2,
         },
 };
 #define OMAP34XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap34xx_mcbsp_pdata)
diff --git a/arch/arm/mach-omap2/memory.h b/arch/arm/mach-omap2/memory.h
deleted file mode 100644
index bb3db80a7c46..000000000000
--- a/arch/arm/mach-omap2/memory.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/memory.h
- *
- * Interface for memory timing related functions for OMAP24XX
- *
- * Copyright (C) 2005 Texas Instruments Inc.
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * Copyright (C) 2005 Nokia Corporation
- * Tony Lindgren <tony@atomide.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef ARCH_ARM_MACH_OMAP2_MEMORY_H
-#define ARCH_ARM_MACH_OMAP2_MEMORY_H
-
-/* Memory timings */
-#define M_DDR           1
-#define M_LOCK_CTRL     (1 << 2)
-#define M_UNLOCK        0
-#define M_LOCK          1
-
-struct memory_timings {
-        u32 m_type;             /* ddr = 1, sdr = 0 */
-        u32 dll_mode;           /* use lock mode = 1, unlock mode = 0 */
-        u32 slow_dll_ctrl;      /* unlock mode, dll value for slow speed */
-        u32 fast_dll_ctrl;      /* unlock mode, dll value for fast speed */
-        u32 base_cs;            /* base chip select to use for calculations */
-};
-
-extern void omap2_init_memory_params(u32 force_lock_to_unlock_mode);
-extern u32 omap2_memory_get_slow_dll_ctrl(void);
-extern u32 omap2_memory_get_fast_dll_ctrl(void);
-extern u32 omap2_memory_get_type(void);
-u32 omap2_dll_force_needed(void);
-u32 omap2_reprogram_sdrc(u32 level, u32 force);
-void __init omap2_init_memory(void);
-void __init gpmc_init(void);
-
-#endif
diff --git a/arch/arm/mach-omap2/mmc-twl4030.c b/arch/arm/mach-omap2/mmc-twl4030.c
index 437f52073f6e..dc40b3e72206 100644
--- a/arch/arm/mach-omap2/mmc-twl4030.c
+++ b/arch/arm/mach-omap2/mmc-twl4030.c
@@ -17,6 +17,7 @@
 #include <linux/delay.h>
 #include <linux/gpio.h>
 #include <linux/i2c/twl4030.h>
+#include <linux/regulator/machine.h>
 
 #include <mach/hardware.h>
 #include <mach/control.h>
@@ -44,6 +45,7 @@
 #define VMMC2_315V              0x0c
 #define VMMC2_300V              0x0b
 #define VMMC2_285V              0x0a
+#define VMMC2_280V              0x09
 #define VMMC2_260V              0x08
 #define VMMC2_185V              0x06
 #define VMMC2_DEDICATED         0x2E
@@ -59,8 +61,8 @@ static struct twl_mmc_controller {
         struct omap_mmc_platform_data   *mmc;
         u8              twl_vmmc_dev_grp;
         u8              twl_mmc_dedicated;
-        char            name[HSMMC_NAME_LEN];
-} hsmmc[] = {
+        char            name[HSMMC_NAME_LEN + 1];
+} hsmmc[OMAP34XX_NR_MMC] = {
         {
                 .twl_vmmc_dev_grp               = VMMC1_DEV_GRP,
                 .twl_mmc_dedicated              = VMMC1_DEDICATED,
@@ -98,6 +100,14 @@ static int twl_mmc_get_ro(struct device *dev, int slot)
         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
 }
 
+static int twl_mmc_get_cover_state(struct device *dev, int slot)
+{
+        struct omap_mmc_platform_data *mmc = dev->platform_data;
+
+        /* NOTE: assumes card detect signal is active-low */
+        return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
+}
+
 /*
  * MMC Slot Initialization.
  */
@@ -166,66 +176,85 @@ static int twl_mmc_resume(struct device *dev, int slot)
 /*
  * Sets the MMC voltage in twl4030
  */
+
+#define MMC1_OCR        (MMC_VDD_165_195 \
+                |MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32)
+#define MMC2_OCR        (MMC_VDD_165_195 \
+                |MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28 \
+                |MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32)
+
 static int twl_mmc_set_voltage(struct twl_mmc_controller *c, int vdd)
 {
         int ret;
-        u8 vmmc, dev_grp_val;
-
-        switch (1 << vdd) {
-        case MMC_VDD_35_36:
-        case MMC_VDD_34_35:
-        case MMC_VDD_33_34:
-        case MMC_VDD_32_33:
-        case MMC_VDD_31_32:
-        case MMC_VDD_30_31:
-                if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
-                        vmmc = VMMC1_315V;
-                else
-                        vmmc = VMMC2_315V;
-                break;
-        case MMC_VDD_29_30:
-                if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
-                        vmmc = VMMC1_315V;
-                else
-                        vmmc = VMMC2_300V;
-                break;
-        case MMC_VDD_27_28:
-        case MMC_VDD_26_27:
-                if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
-                        vmmc = VMMC1_285V;
-                else
-                        vmmc = VMMC2_285V;
-                break;
-        case MMC_VDD_25_26:
-        case MMC_VDD_24_25:
-        case MMC_VDD_23_24:
-        case MMC_VDD_22_23:
-        case MMC_VDD_21_22:
-        case MMC_VDD_20_21:
-                if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
-                        vmmc = VMMC1_285V;
-                else
-                        vmmc = VMMC2_260V;
-                break;
-        case MMC_VDD_165_195:
-                if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
+        u8 vmmc = 0, dev_grp_val;
+
+        if (!vdd)
+                goto doit;
+
+        if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) {
+                /* VMMC1:  max 220 mA.  And for 8-bit mode,
+                 * VSIM:  max 50 mA
+                 */
+                switch (1 << vdd) {
+                case MMC_VDD_165_195:
                         vmmc = VMMC1_185V;
-                else
+                        /* and VSIM_180V */
+                        break;
+                case MMC_VDD_28_29:
+                        vmmc = VMMC1_285V;
+                        /* and VSIM_280V */
+                        break;
+                case MMC_VDD_29_30:
+                case MMC_VDD_30_31:
+                        vmmc = VMMC1_300V;
+                        /* and VSIM_300V */
+                        break;
+                case MMC_VDD_31_32:
+                        vmmc = VMMC1_315V;
+                        /* error if VSIM needed */
+                        break;
+                default:
+                        return -EINVAL;
+                }
+        } else if (c->twl_vmmc_dev_grp == VMMC2_DEV_GRP) {
+                /* VMMC2:  max 100 mA */
+                switch (1 << vdd) {
+                case MMC_VDD_165_195:
                         vmmc = VMMC2_185V;
-                break;
-        default:
-                vmmc = 0;
-                break;
+                        break;
+                case MMC_VDD_25_26:
+                case MMC_VDD_26_27:
+                        vmmc = VMMC2_260V;
+                        break;
+                case MMC_VDD_27_28:
+                        vmmc = VMMC2_280V;
+                        break;
+                case MMC_VDD_28_29:
+                        vmmc = VMMC2_285V;
+                        break;
+                case MMC_VDD_29_30:
+                case MMC_VDD_30_31:
+                        vmmc = VMMC2_300V;
+                        break;
+                case MMC_VDD_31_32:
+                        vmmc = VMMC2_315V;
+                        break;
+                default:
+                        return -EINVAL;
+                }
+        } else {
+                return -EINVAL;
         }
 
-        if (vmmc)
+doit:
+        if (vdd)
                 dev_grp_val = VMMC_DEV_GRP_P1;  /* Power up */
         else
                 dev_grp_val = LDO_CLR;          /* Power down */
 
         ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
                                         dev_grp_val, c->twl_vmmc_dev_grp);
-        if (ret)
+        if (ret || !vdd)
                 return ret;
 
         ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
@@ -242,6 +271,14 @@ static int twl_mmc1_set_power(struct device *dev, int slot, int power_on,
         struct twl_mmc_controller *c = &hsmmc[0];
         struct omap_mmc_platform_data *mmc = dev->platform_data;
 
+        /*
+         * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
+         * card using the same TWL VMMC1 supply (hsmmc[0]); OMAP has both
+         * 1.8V and 3.0V modes, controlled by the PBIAS register.
+         *
+         * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
+         * is most naturally TWL VSIM; those pins also use PBIAS.
+         */
         if (power_on) {
                 if (cpu_is_omap2430()) {
                         reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
@@ -298,6 +335,12 @@ static int twl_mmc2_set_power(struct device *dev, int slot, int power_on, int vd
         struct twl_mmc_controller *c = &hsmmc[1];
         struct omap_mmc_platform_data *mmc = dev->platform_data;
 
+        /*
+         * Assume TWL VMMC2 (hsmmc[1]) is used only to power the card ... OMAP
+         * VDDS is used to power the pins, optionally with a transceiver to
+         * support cards using voltages other than VDDS (1.8V nominal).  When a
+         * transceiver is used, DAT3..7 are muxed as transceiver control pins.
+         */
         if (power_on) {
                 if (mmc->slots[0].internal_clock) {
                         u32 reg;
@@ -314,6 +357,16 @@ static int twl_mmc2_set_power(struct device *dev, int slot, int power_on, int vd
         return ret;
 }
 
+static int twl_mmc3_set_power(struct device *dev, int slot, int power_on,
+                int vdd)
+{
+        /*
+         * Assume MMC3 has self-powered device connected, for example on-board
+         * chip with external power source.
+         */
+        return 0;
+}
+
 static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;
 
 void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
@@ -349,13 +402,13 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
                         return;
                 }
 
-                sprintf(twl->name, "mmc%islot%i", c->mmc, 1);
+                if (c->name)
+                        strncpy(twl->name, c->name, HSMMC_NAME_LEN);
+                else
+                        snprintf(twl->name, ARRAY_SIZE(twl->name),
+                                "mmc%islot%i", c->mmc, 1);
                 mmc->slots[0].name = twl->name;
                 mmc->nr_slots = 1;
-                mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
-                                        MMC_VDD_26_27 | MMC_VDD_27_28 |
-                                        MMC_VDD_29_30 |
-                                        MMC_VDD_30_31 | MMC_VDD_31_32;
                 mmc->slots[0].wires = c->wires;
                 mmc->slots[0].internal_clock = !c->ext_clock;
                 mmc->dma_mask = 0xffffffff;
@@ -369,7 +422,10 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
 
                         mmc->slots[0].switch_pin = c->gpio_cd;
                         mmc->slots[0].card_detect_irq = gpio_to_irq(c->gpio_cd);
-                        mmc->slots[0].card_detect = twl_mmc_card_detect;
+                        if (c->cover_only)
+                                mmc->slots[0].get_cover_state = twl_mmc_get_cover_state;
+                        else
+                                mmc->slots[0].card_detect = twl_mmc_card_detect;
                 } else
                         mmc->slots[0].switch_pin = -EINVAL;
 
@@ -385,24 +441,43 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
 
                 /* NOTE:  we assume OMAP's MMC1 and MMC2 use
                  * the TWL4030's VMMC1 and VMMC2, respectively;
-                 * and that OMAP's MMC3 isn't used.
+                 * and that MMC3 device has it's own power source.
                  */
 
                 switch (c->mmc) {
                 case 1:
                         mmc->slots[0].set_power = twl_mmc1_set_power;
+                        mmc->slots[0].ocr_mask = MMC1_OCR;
                         break;
                 case 2:
                         mmc->slots[0].set_power = twl_mmc2_set_power;
+                        if (c->transceiver)
+                                mmc->slots[0].ocr_mask = MMC2_OCR;
+                        else
+                                mmc->slots[0].ocr_mask = MMC_VDD_165_195;
+                        break;
+                case 3:
+                        mmc->slots[0].set_power = twl_mmc3_set_power;
+                        mmc->slots[0].ocr_mask = MMC_VDD_165_195;
                         break;
                 default:
                         pr_err("MMC%d configuration not supported!\n", c->mmc);
+                        kfree(mmc);
                         continue;
                 }
                 hsmmc_data[c->mmc - 1] = mmc;
         }
 
         omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
+
+        /* pass the device nodes back to board setup code */
+        for (c = controllers; c->mmc; c++) {
+                struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
+
+                if (!c->mmc || c->mmc > nr_hsmmc)
+                        continue;
+                c->dev = mmc->dev;
+        }
 }
 
 #endif
diff --git a/arch/arm/mach-omap2/mmc-twl4030.h b/arch/arm/mach-omap2/mmc-twl4030.h
index e1c8076400ca..ea59e8624290 100644
--- a/arch/arm/mach-omap2/mmc-twl4030.h
+++ b/arch/arm/mach-omap2/mmc-twl4030.h
@@ -9,9 +9,13 @@
 struct twl4030_hsmmc_info {
         u8      mmc;            /* controller 1/2/3 */
         u8      wires;          /* 1/4/8 wires */
+        bool    transceiver;    /* MMC-2 option */
+        bool    ext_clock;      /* use external pin for input clock */
+        bool    cover_only;     /* No card detect - just cover switch */
         int     gpio_cd;        /* or -EINVAL */
         int     gpio_wp;        /* or -EINVAL */
-        int     ext_clock:1;    /* use external pin for input clock */
+        char    *name;          /* or NULL for default */
+        struct device *dev;     /* returned: pointer to mmc adapter */
 };
 
 #if     defined(CONFIG_TWL4030_CORE) && \
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index dacb41f130c0..026c4fc883a7 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -453,10 +453,37 @@ MUX_CFG_34XX("AC1_3430_USB3FS_PHY_MM3_TXEN_N", 0x18a,
 
 
 /* 34XX GPIO - bidirectional, unless the name has an "_OUT" suffix.
+ * (Always specify PIN_INPUT, except for names suffixed by "_OUT".)
  * No internal pullup/pulldown without "_UP" or "_DOWN" suffix.
  */
+MUX_CFG_34XX("AF26_34XX_GPIO0", 0x1e0,
+                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
+MUX_CFG_34XX("AF22_34XX_GPIO9", 0xa18,
+                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
 MUX_CFG_34XX("AH8_34XX_GPIO29", 0x5fa,
                 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
+MUX_CFG_34XX("U8_34XX_GPIO54_OUT", 0x0b4,
+                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("U8_34XX_GPIO54_DOWN", 0x0b4,
+                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("L8_34XX_GPIO63", 0x0ce,
+                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
+MUX_CFG_34XX("G25_34XX_GPIO86_OUT", 0x0fc,
+                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("AG4_34XX_GPIO134_OUT", 0x160,
+                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("AE4_34XX_GPIO136_OUT", 0x164,
+                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("AF6_34XX_GPIO140_UP", 0x16c,
+                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("AE6_34XX_GPIO141", 0x16e,
+                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
+MUX_CFG_34XX("AF5_34XX_GPIO142", 0x170,
+                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
+MUX_CFG_34XX("AE5_34XX_GPIO143", 0x172,
+                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
+MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c,
+                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
 MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
                 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
 };
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 55361c16c9d9..ea8ceaed09cb 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -103,7 +103,7 @@ static struct platform_suspend_ops omap_pm_ops = {
         .valid          = suspend_valid_only_mem,
 };
 
-int __init omap2_pm_init(void)
+static int __init omap2_pm_init(void)
 {
         return 0;
 }
diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h
index 1e151faebbd3..691470ea4c6a 100644
--- a/arch/arm/mach-omap2/powerdomains.h
+++ b/arch/arm/mach-omap2/powerdomains.h
@@ -171,13 +171,19 @@ static struct powerdomain *powerdomains_omap[] __initdata = {
         &iva2_pwrdm,
         &mpu_34xx_pwrdm,
         &neon_pwrdm,
-        &core_34xx_pwrdm,
+        &core_34xx_pre_es3_1_pwrdm,
+        &core_34xx_es3_1_pwrdm,
         &cam_pwrdm,
         &dss_pwrdm,
         &per_pwrdm,
         &emu_pwrdm,
         &sgx_pwrdm,
         &usbhost_pwrdm,
+        &dpll1_pwrdm,
+        &dpll2_pwrdm,
+        &dpll3_pwrdm,
+        &dpll4_pwrdm,
+        &dpll5_pwrdm,
 #endif
 
         NULL
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
index f573f7108398..4dcf94b800ab 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -200,12 +200,33 @@ static struct powerdomain mpu_34xx_pwrdm = {
 };
 
 /* No wkdeps or sleepdeps for 34xx core apparently */
-static struct powerdomain core_34xx_pwrdm = {
+static struct powerdomain core_34xx_pre_es3_1_pwrdm = {
         .name             = "core_pwrdm",
         .prcm_offs        = CORE_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
+                                           CHIP_IS_OMAP3430ES2 |
+                                           CHIP_IS_OMAP3430ES3_0),
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .dep_bit          = OMAP3430_EN_CORE_SHIFT,
+        .banks            = 2,
+        .pwrsts_mem_ret   = {
+                [0] = PWRSTS_OFF_RET,    /* MEM1RETSTATE */
+                [1] = PWRSTS_OFF_RET,    /* MEM2RETSTATE */
+        },
+        .pwrsts_mem_on    = {
+                [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
+                [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
+        },
+};
+
+/* No wkdeps or sleepdeps for 34xx core apparently */
+static struct powerdomain core_34xx_es3_1_pwrdm = {
+        .name             = "core_pwrdm",
+        .prcm_offs        = CORE_MOD,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .dep_bit          = OMAP3430_EN_CORE_SHIFT,
+        .flags            = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
         .banks            = 2,
         .pwrsts_mem_ret   = {
                 [0] = PWRSTS_OFF_RET,    /* MEM1RETSTATE */
@@ -236,14 +257,19 @@ static struct powerdomain dss_pwrdm = {
         },
 };
 
+/*
+ * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
+ * possible SGX powerstate, the SGX device itself does not support
+ * retention.
+ */
 static struct powerdomain sgx_pwrdm = {
         .name             = "sgx_pwrdm",
         .prcm_offs        = OMAP3430ES2_SGX_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
         .wkdep_srcs       = gfx_sgx_wkdeps,
         .sleepdep_srcs    = cam_gfx_sleepdeps,
         /* XXX This is accurate for 3430 SGX, but what about GFX? */
-        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts           = PWRSTS_OFF_ON,
         .pwrsts_logic_ret = PWRDM_POWER_RET,
         .banks            = 1,
         .pwrsts_mem_ret   = {
@@ -307,11 +333,12 @@ static struct powerdomain neon_pwrdm = {
 static struct powerdomain usbhost_pwrdm = {
         .name             = "usbhost_pwrdm",
         .prcm_offs        = OMAP3430ES2_USBHOST_MOD,
-        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
         .wkdep_srcs       = per_usbhost_wkdeps,
         .sleepdep_srcs    = dss_per_usbhost_sleepdeps,
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRDM_POWER_RET,
+        .flags            = PWRDM_HAS_HDWR_SAR, /* for USBHOST ctrlr only */
         .banks            = 1,
         .pwrsts_mem_ret   = {
                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
@@ -321,6 +348,37 @@ static struct powerdomain usbhost_pwrdm = {
         },
 };
 
+static struct powerdomain dpll1_pwrdm = {
+        .name           = "dpll1_pwrdm",
+        .prcm_offs      = MPU_MOD,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct powerdomain dpll2_pwrdm = {
+        .name           = "dpll2_pwrdm",
+        .prcm_offs      = OMAP3430_IVA2_MOD,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct powerdomain dpll3_pwrdm = {
+        .name           = "dpll3_pwrdm",
+        .prcm_offs      = PLL_MOD,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct powerdomain dpll4_pwrdm = {
+        .name           = "dpll4_pwrdm",
+        .prcm_offs      = PLL_MOD,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct powerdomain dpll5_pwrdm = {
+        .name           = "dpll5_pwrdm",
+        .prcm_offs      = PLL_MOD,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
+};
+
+
 #endif    /* CONFIG_ARCH_OMAP34XX */
 
 
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 4a32822ff3fc..812d50ee495d 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -113,33 +113,58 @@
 #define OMAP2430_EN_USBHS                               (1 << 6)
 
 /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
-#define OMAP2420_ST_MMC                                 (1 << 26)
-#define OMAP24XX_ST_UART2                               (1 << 22)
-#define OMAP24XX_ST_UART1                               (1 << 21)
-#define OMAP24XX_ST_MCSPI2                              (1 << 18)
-#define OMAP24XX_ST_MCSPI1                              (1 << 17)
-#define OMAP24XX_ST_GPT12                               (1 << 14)
-#define OMAP24XX_ST_GPT11                               (1 << 13)
-#define OMAP24XX_ST_GPT10                               (1 << 12)
-#define OMAP24XX_ST_GPT9                                (1 << 11)
-#define OMAP24XX_ST_GPT8                                (1 << 10)
-#define OMAP24XX_ST_GPT7                                (1 << 9)
-#define OMAP24XX_ST_GPT6                                (1 << 8)
-#define OMAP24XX_ST_GPT5                                (1 << 7)
-#define OMAP24XX_ST_GPT4                                (1 << 6)
-#define OMAP24XX_ST_GPT3                                (1 << 5)
-#define OMAP24XX_ST_GPT2                                (1 << 4)
-#define OMAP2420_ST_VLYNQ                               (1 << 3)
+#define OMAP2420_ST_MMC_SHIFT                           26
+#define OMAP2420_ST_MMC_MASK                            (1 << 26)
+#define OMAP24XX_ST_UART2_SHIFT                         22
+#define OMAP24XX_ST_UART2_MASK                          (1 << 22)
+#define OMAP24XX_ST_UART1_SHIFT                         21
+#define OMAP24XX_ST_UART1_MASK                          (1 << 21)
+#define OMAP24XX_ST_MCSPI2_SHIFT                        18
+#define OMAP24XX_ST_MCSPI2_MASK                         (1 << 18)
+#define OMAP24XX_ST_MCSPI1_SHIFT                        17
+#define OMAP24XX_ST_MCSPI1_MASK                         (1 << 17)
+#define OMAP24XX_ST_GPT12_SHIFT                         14
+#define OMAP24XX_ST_GPT12_MASK                          (1 << 14)
+#define OMAP24XX_ST_GPT11_SHIFT                         13
+#define OMAP24XX_ST_GPT11_MASK                          (1 << 13)
+#define OMAP24XX_ST_GPT10_SHIFT                         12
+#define OMAP24XX_ST_GPT10_MASK                          (1 << 12)
+#define OMAP24XX_ST_GPT9_SHIFT                          11
+#define OMAP24XX_ST_GPT9_MASK                           (1 << 11)
+#define OMAP24XX_ST_GPT8_SHIFT                          10
+#define OMAP24XX_ST_GPT8_MASK                           (1 << 10)
+#define OMAP24XX_ST_GPT7_SHIFT                          9
+#define OMAP24XX_ST_GPT7_MASK                           (1 << 9)
+#define OMAP24XX_ST_GPT6_SHIFT                          8
+#define OMAP24XX_ST_GPT6_MASK                           (1 << 8)
+#define OMAP24XX_ST_GPT5_SHIFT                          7
+#define OMAP24XX_ST_GPT5_MASK                           (1 << 7)
+#define OMAP24XX_ST_GPT4_SHIFT                          6
+#define OMAP24XX_ST_GPT4_MASK                           (1 << 6)
+#define OMAP24XX_ST_GPT3_SHIFT                          5
+#define OMAP24XX_ST_GPT3_MASK                           (1 << 5)
+#define OMAP24XX_ST_GPT2_SHIFT                          4
+#define OMAP24XX_ST_GPT2_MASK                           (1 << 4)
+#define OMAP2420_ST_VLYNQ_SHIFT                         3
+#define OMAP2420_ST_VLYNQ_MASK                          (1 << 3)
 
 /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
-#define OMAP2430_ST_MDM_INTC                            (1 << 11)
-#define OMAP2430_ST_GPIO5                               (1 << 10)
-#define OMAP2430_ST_MCSPI3                              (1 << 9)
-#define OMAP2430_ST_MMCHS2                              (1 << 8)
-#define OMAP2430_ST_MMCHS1                              (1 << 7)
-#define OMAP2430_ST_USBHS                               (1 << 6)
-#define OMAP24XX_ST_UART3                               (1 << 2)
-#define OMAP24XX_ST_USB                                 (1 << 0)
+#define OMAP2430_ST_MDM_INTC_SHIFT                      11
+#define OMAP2430_ST_MDM_INTC_MASK                       (1 << 11)
+#define OMAP2430_ST_GPIO5_SHIFT                         10
+#define OMAP2430_ST_GPIO5_MASK                          (1 << 10)
+#define OMAP2430_ST_MCSPI3_SHIFT                        9
+#define OMAP2430_ST_MCSPI3_MASK                         (1 << 9)
+#define OMAP2430_ST_MMCHS2_SHIFT                        8
+#define OMAP2430_ST_MMCHS2_MASK                         (1 << 8)
+#define OMAP2430_ST_MMCHS1_SHIFT                        7
+#define OMAP2430_ST_MMCHS1_MASK                         (1 << 7)
+#define OMAP2430_ST_USBHS_SHIFT                         6
+#define OMAP2430_ST_USBHS_MASK                          (1 << 6)
+#define OMAP24XX_ST_UART3_SHIFT                         2
+#define OMAP24XX_ST_UART3_MASK                          (1 << 2)
+#define OMAP24XX_ST_USB_SHIFT                           0
+#define OMAP24XX_ST_USB_MASK                            (1 << 0)
 
 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
 #define OMAP24XX_EN_GPIOS_SHIFT                         2
@@ -148,11 +173,13 @@
 #define OMAP24XX_EN_GPT1                                (1 << 0)
 
 /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
-#define OMAP24XX_ST_GPIOS                               (1 << 2)
-#define OMAP24XX_ST_GPT1                                (1 << 0)
+#define OMAP24XX_ST_GPIOS_SHIFT                         (1 << 2)
+#define OMAP24XX_ST_GPIOS_MASK                          2
+#define OMAP24XX_ST_GPT1_SHIFT                          (1 << 0)
+#define OMAP24XX_ST_GPT1_MASK                           0
 
 /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
-#define OMAP2430_ST_MDM                                 (1 << 0)
+#define OMAP2430_ST_MDM_SHIFT                           (1 << 0)
 
 
 /* 3430 register bits shared between CM & PRM registers */
@@ -205,24 +232,46 @@
 #define OMAP3430_EN_HSOTGUSB_SHIFT                              4
 
 /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
-#define OMAP3430_ST_MMC2                                (1 << 25)
-#define OMAP3430_ST_MMC1                                (1 << 24)
-#define OMAP3430_ST_MCSPI4                              (1 << 21)
-#define OMAP3430_ST_MCSPI3                              (1 << 20)
-#define OMAP3430_ST_MCSPI2                              (1 << 19)
-#define OMAP3430_ST_MCSPI1                              (1 << 18)
-#define OMAP3430_ST_I2C3                                (1 << 17)
-#define OMAP3430_ST_I2C2                                (1 << 16)
-#define OMAP3430_ST_I2C1                                (1 << 15)
-#define OMAP3430_ST_UART2                               (1 << 14)
-#define OMAP3430_ST_UART1                               (1 << 13)
-#define OMAP3430_ST_GPT11                               (1 << 12)
-#define OMAP3430_ST_GPT10                               (1 << 11)
-#define OMAP3430_ST_MCBSP5                              (1 << 10)
-#define OMAP3430_ST_MCBSP1                              (1 << 9)
-#define OMAP3430_ST_FSHOSTUSB                           (1 << 5)
-#define OMAP3430_ST_HSOTGUSB                            (1 << 4)
-#define OMAP3430_ST_D2D                                 (1 << 3)
+#define OMAP3430_ST_MMC2_SHIFT                          25
+#define OMAP3430_ST_MMC2_MASK                           (1 << 25)
+#define OMAP3430_ST_MMC1_SHIFT                          24
+#define OMAP3430_ST_MMC1_MASK                           (1 << 24)
+#define OMAP3430_ST_MCSPI4_SHIFT                        21
+#define OMAP3430_ST_MCSPI4_MASK                         (1 << 21)
+#define OMAP3430_ST_MCSPI3_SHIFT                        20
+#define OMAP3430_ST_MCSPI3_MASK                         (1 << 20)
+#define OMAP3430_ST_MCSPI2_SHIFT                        19
+#define OMAP3430_ST_MCSPI2_MASK                         (1 << 19)
+#define OMAP3430_ST_MCSPI1_SHIFT                        18
+#define OMAP3430_ST_MCSPI1_MASK                         (1 << 18)
+#define OMAP3430_ST_I2C3_SHIFT                          17
+#define OMAP3430_ST_I2C3_MASK                           (1 << 17)
+#define OMAP3430_ST_I2C2_SHIFT                          16
+#define OMAP3430_ST_I2C2_MASK                           (1 << 16)
+#define OMAP3430_ST_I2C1_SHIFT                          15
+#define OMAP3430_ST_I2C1_MASK                           (1 << 15)
+#define OMAP3430_ST_UART2_SHIFT                         14
+#define OMAP3430_ST_UART2_MASK                          (1 << 14)
+#define OMAP3430_ST_UART1_SHIFT                         13
+#define OMAP3430_ST_UART1_MASK                          (1 << 13)
+#define OMAP3430_ST_GPT11_SHIFT                         12
+#define OMAP3430_ST_GPT11_MASK                          (1 << 12)
+#define OMAP3430_ST_GPT10_SHIFT                         11
+#define OMAP3430_ST_GPT10_MASK                          (1 << 11)
+#define OMAP3430_ST_MCBSP5_SHIFT                        10
+#define OMAP3430_ST_MCBSP5_MASK                         (1 << 10)
+#define OMAP3430_ST_MCBSP1_SHIFT                        9
+#define OMAP3430_ST_MCBSP1_MASK                         (1 << 9)
+#define OMAP3430ES1_ST_FSHOSTUSB_SHIFT                  5
+#define OMAP3430ES1_ST_FSHOSTUSB_MASK                   (1 << 5)
+#define OMAP3430ES1_ST_HSOTGUSB_SHIFT                   4
+#define OMAP3430ES1_ST_HSOTGUSB_MASK                    (1 << 4)
+#define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT              5
+#define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK               (1 << 5)
+#define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT             4
+#define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK              (1 << 4)
+#define OMAP3430_ST_D2D_SHIFT                           3
+#define OMAP3430_ST_D2D_MASK                            (1 << 3)
 
 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
 #define OMAP3430_EN_GPIO1                               (1 << 3)
@@ -241,11 +290,16 @@
 #define OMAP3430_EN_GPT12_SHIFT                         1
 
 /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
-#define OMAP3430_ST_SR2                                 (1 << 7)
-#define OMAP3430_ST_SR1                                 (1 << 6)
-#define OMAP3430_ST_GPIO1                               (1 << 3)
-#define OMAP3430_ST_GPT12                               (1 << 1)
-#define OMAP3430_ST_GPT1                                (1 << 0)
+#define OMAP3430_ST_SR2_SHIFT                           7
+#define OMAP3430_ST_SR2_MASK                            (1 << 7)
+#define OMAP3430_ST_SR1_SHIFT                           6
+#define OMAP3430_ST_SR1_MASK                            (1 << 6)
+#define OMAP3430_ST_GPIO1_SHIFT                         3
+#define OMAP3430_ST_GPIO1_MASK                          (1 << 3)
+#define OMAP3430_ST_GPT12_SHIFT                         1
+#define OMAP3430_ST_GPT12_MASK                          (1 << 1)
+#define OMAP3430_ST_GPT1_SHIFT                          0
+#define OMAP3430_ST_GPT1_MASK                           (1 << 0)
 
 /*
  * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
@@ -296,20 +350,34 @@
 #define OMAP3430_EN_MCBSP2_SHIFT                        0
 
 /* CM_IDLEST_PER, PM_WKST_PER shared bits */
-#define OMAP3430_ST_GPIO6                               (1 << 17)
-#define OMAP3430_ST_GPIO5                               (1 << 16)
-#define OMAP3430_ST_GPIO4                               (1 << 15)
-#define OMAP3430_ST_GPIO3                               (1 << 14)
-#define OMAP3430_ST_GPIO2                               (1 << 13)
-#define OMAP3430_ST_UART3                               (1 << 11)
-#define OMAP3430_ST_GPT9                                (1 << 10)
-#define OMAP3430_ST_GPT8                                (1 << 9)
-#define OMAP3430_ST_GPT7                                (1 << 8)
-#define OMAP3430_ST_GPT6                                (1 << 7)
-#define OMAP3430_ST_GPT5                                (1 << 6)
-#define OMAP3430_ST_GPT4                                (1 << 5)
-#define OMAP3430_ST_GPT3                                (1 << 4)
-#define OMAP3430_ST_GPT2                                (1 << 3)
+#define OMAP3430_ST_GPIO6_SHIFT                         17
+#define OMAP3430_ST_GPIO6_MASK                          (1 << 17)
+#define OMAP3430_ST_GPIO5_SHIFT                         16
+#define OMAP3430_ST_GPIO5_MASK                          (1 << 16)
+#define OMAP3430_ST_GPIO4_SHIFT                         15
+#define OMAP3430_ST_GPIO4_MASK                          (1 << 15)
+#define OMAP3430_ST_GPIO3_SHIFT                         14
+#define OMAP3430_ST_GPIO3_MASK                          (1 << 14)
+#define OMAP3430_ST_GPIO2_SHIFT                         13
+#define OMAP3430_ST_GPIO2_MASK                          (1 << 13)
+#define OMAP3430_ST_UART3_SHIFT                         11
+#define OMAP3430_ST_UART3_MASK                          (1 << 11)
+#define OMAP3430_ST_GPT9_SHIFT                          10
+#define OMAP3430_ST_GPT9_MASK                           (1 << 10)
+#define OMAP3430_ST_GPT8_SHIFT                          9
+#define OMAP3430_ST_GPT8_MASK                           (1 << 9)
+#define OMAP3430_ST_GPT7_SHIFT                          8
+#define OMAP3430_ST_GPT7_MASK                           (1 << 8)
+#define OMAP3430_ST_GPT6_SHIFT                          7
+#define OMAP3430_ST_GPT6_MASK                           (1 << 7)
+#define OMAP3430_ST_GPT5_SHIFT                          6
+#define OMAP3430_ST_GPT5_MASK                           (1 << 6)
+#define OMAP3430_ST_GPT4_SHIFT                          5
+#define OMAP3430_ST_GPT4_MASK                           (1 << 5)
+#define OMAP3430_ST_GPT3_SHIFT                          4
+#define OMAP3430_ST_GPT3_MASK                           (1 << 4)
+#define OMAP3430_ST_GPT2_SHIFT                          3
+#define OMAP3430_ST_GPT2_MASK                           (1 << 3)
 
 /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
 #define OMAP3430_EN_CORE_SHIFT                          0
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index 5b5ecfe6c999..c6a7940f4287 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -366,6 +366,7 @@
 
 /* PM_WKEN_WKUP specific bits */
 #define OMAP3430_EN_IO                                  (1 << 8)
+#define OMAP3430_EN_GPIO1                               (1 << 3)
 
 /* PM_MPUGRPSEL_WKUP specific bits */
 
@@ -452,6 +453,14 @@
 #define OMAP3430_CMDRA0_MASK                            (0xff << 0)
 
 /* PRM_VC_CMD_VAL_0 specific bits */
+#define OMAP3430_VC_CMD_ON_SHIFT                        24
+#define OMAP3430_VC_CMD_ON_MASK                         (0xFF << 24)
+#define OMAP3430_VC_CMD_ONLP_SHIFT                      16
+#define OMAP3430_VC_CMD_ONLP_MASK                       (0xFF << 16)
+#define OMAP3430_VC_CMD_RET_SHIFT                       8
+#define OMAP3430_VC_CMD_RET_MASK                        (0xFF << 8)
+#define OMAP3430_VC_CMD_OFF_SHIFT                       0
+#define OMAP3430_VC_CMD_OFF_MASK                        (0xFF << 0)
 
 /* PRM_VC_CMD_VAL_1 specific bits */
 
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index e4dc4b17881d..826d326b8062 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -141,6 +141,19 @@
 #define PM_PWSTCTRL                                     0x00e0
 #define PM_PWSTST                                       0x00e4
 
+/* Omap2 specific registers */
+#define OMAP24XX_PM_WKEN2                               0x00a4
+#define OMAP24XX_PM_WKST2                               0x00b4
+
+#define OMAP24XX_PRCM_IRQSTATUS_DSP                     0x00f0  /* IVA mod */
+#define OMAP24XX_PRCM_IRQENABLE_DSP                     0x00f4  /* IVA mod */
+#define OMAP24XX_PRCM_IRQSTATUS_IVA                     0x00f8
+#define OMAP24XX_PRCM_IRQENABLE_IVA                     0x00fc
+
+/* Omap3 specific registers */
+#define OMAP3430ES2_PM_WKEN3                            0x00f0
+#define OMAP3430ES2_PM_WKST3                            0x00b8
+
 #define OMAP3430_PM_MPUGRPSEL                           0x00a4
 #define OMAP3430_PM_MPUGRPSEL1                          OMAP3430_PM_MPUGRPSEL
 
@@ -153,16 +166,6 @@
 #define OMAP3430_PRM_IRQENABLE_IVA2                     0x00fc
 
 
-/* Architecture-specific registers */
-
-#define OMAP24XX_PM_WKEN2                               0x00a4
-#define OMAP24XX_PM_WKST2                               0x00b4
-
-#define OMAP24XX_PRCM_IRQSTATUS_DSP                     0x00f0  /* IVA mod */
-#define OMAP24XX_PRCM_IRQENABLE_DSP                     0x00f4  /* IVA mod */
-#define OMAP24XX_PRCM_IRQSTATUS_IVA                     0x00f8
-#define OMAP24XX_PRCM_IRQENABLE_IVA                     0x00fc
-
 #ifndef __ASSEMBLER__
 
 /* Power/reset management domain register get/set */
@@ -228,7 +231,6 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
 #define OMAP_RSTTIME1_SHIFT                             0
 #define OMAP_RSTTIME1_MASK                              (0xff << 0)
 
-
 /* PRM_RSTCTRL */
 /* Named RM_RSTCTRL_WKUP on the 24xx */
 /* 2420 calls RST_DPLL3 'RST_DPLL' */
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
new file mode 100644
index 000000000000..2a30060cb4b7
--- /dev/null
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -0,0 +1,93 @@
+/*
+ * SMS/SDRC (SDRAM controller) common code for OMAP2/3
+ *
+ * Copyright (C) 2005, 2008 Texas Instruments Inc.
+ * Copyright (C) 2005, 2008 Nokia Corporation
+ *
+ * Tony Lindgren <tony@atomide.com>
+ * Paul Walmsley
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <mach/common.h>
+#include <mach/clock.h>
+#include <mach/sram.h>
+
+#include "prm.h"
+
+#include <mach/sdrc.h>
+#include "sdrc.h"
+
+static struct omap_sdrc_params *sdrc_init_params;
+
+void __iomem *omap2_sdrc_base;
+void __iomem *omap2_sms_base;
+
+
+/**
+ * omap2_sdrc_get_params - return SDRC register values for a given clock rate
+ * @r: SDRC clock rate (in Hz)
+ *
+ * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
+ * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given
+ * SDRC clock rate 'r'.  These parameters control various timing
+ * delays in the SDRAM controller that are expressed in terms of the
+ * number of SDRC clock cycles to wait; hence the clock rate
+ * dependency. Note that sdrc_init_params must be sorted rate
+ * descending.  Also assumes that both chip-selects use the same
+ * timing parameters.  Returns a struct omap_sdrc_params * upon
+ * success, or NULL upon failure.
+ */
+struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
+{
+        struct omap_sdrc_params *sp;
+
+        sp = sdrc_init_params;
+
+        while (sp->rate != r)
+                sp++;
+
+        if (!sp->rate)
+                return NULL;
+
+        return sp;
+}
+
+
+void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
+{
+        omap2_sdrc_base = omap2_globals->sdrc;
+        omap2_sms_base = omap2_globals->sms;
+}
+
+/* turn on smart idle modes for SDRAM scheduler and controller */
+void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
+{
+        u32 l;
+
+        l = sms_read_reg(SMS_SYSCONFIG);
+        l &= ~(0x3 << 3);
+        l |= (0x2 << 3);
+        sms_write_reg(l, SMS_SYSCONFIG);
+
+        l = sdrc_read_reg(SDRC_SYSCONFIG);
+        l &= ~(0x3 << 3);
+        l |= (0x2 << 3);
+        sdrc_write_reg(l, SDRC_SYSCONFIG);
+
+        sdrc_init_params = sp;
+}
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 882c70224292..0afdad5ae9fb 100644
--- a/arch/arm/mach-omap2/memory.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -1,13 +1,14 @@
 /*
- * linux/arch/arm/mach-omap2/memory.c
+ * linux/arch/arm/mach-omap2/sdrc2xxx.c
  *
- * Memory timing related functions for OMAP24XX
+ * SDRAM timing related functions for OMAP2xxx
  *
- * Copyright (C) 2005 Texas Instruments Inc.
- * Richard Woodruff <r-woodruff2@ti.com>
+ * Copyright (C) 2005, 2008 Texas Instruments Inc.
+ * Copyright (C) 2005, 2008 Nokia Corporation
  *
- * Copyright (C) 2005 Nokia Corporation
  * Tony Lindgren <tony@atomide.com>
+ * Paul Walmsley
+ * Richard Woodruff <r-woodruff2@ti.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -28,27 +29,31 @@
 #include <mach/sram.h>
 
 #include "prm.h"
-
-#include "memory.h"
+#include "clock.h"
+#include <mach/sdrc.h>
 #include "sdrc.h"
 
-void __iomem *omap2_sdrc_base;
-void __iomem *omap2_sms_base;
+/* Memory timing, DLL mode flags */
+#define M_DDR           1
+#define M_LOCK_CTRL     (1 << 2)
+#define M_UNLOCK        0
+#define M_LOCK          1
+
 
 static struct memory_timings mem_timings;
 static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
 
-u32 omap2_memory_get_slow_dll_ctrl(void)
+static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void)
 {
         return mem_timings.slow_dll_ctrl;
 }
 
-u32 omap2_memory_get_fast_dll_ctrl(void)
+static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void)
 {
         return mem_timings.fast_dll_ctrl;
 }
 
-u32 omap2_memory_get_type(void)
+static u32 omap2xxx_sdrc_get_type(void)
 {
         return mem_timings.m_type;
 }
@@ -57,7 +62,7 @@ u32 omap2_memory_get_type(void)
  * Check the DLL lock state, and return tue if running in unlock mode.
  * This is needed to compensate for the shifted DLL value in unlock mode.
  */
-u32 omap2_dll_force_needed(void)
+u32 omap2xxx_sdrc_dll_is_unlocked(void)
 {
         /* dlla and dllb are a set */
         u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
@@ -72,8 +77,10 @@ u32 omap2_dll_force_needed(void)
  * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
  * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
  * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
+ *
+ * Used by the clock framework during CORE DPLL changes
  */
-u32 omap2_reprogram_sdrc(u32 level, u32 force)
+u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
 {
         u32 dll_ctrl, m_type;
         u32 prev = curr_perf_level;
@@ -82,15 +89,14 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force)
         if ((curr_perf_level == level) && !force)
                 return prev;
 
-        if (level == CORE_CLK_SRC_DPLL) {
-                dll_ctrl = omap2_memory_get_slow_dll_ctrl();
-        } else if (level == CORE_CLK_SRC_DPLL_X2) {
-                dll_ctrl = omap2_memory_get_fast_dll_ctrl();
-        } else {
+        if (level == CORE_CLK_SRC_DPLL)
+                dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl();
+        else if (level == CORE_CLK_SRC_DPLL_X2)
+                dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl();
+        else
                 return prev;
-        }
 
-        m_type = omap2_memory_get_type();
+        m_type = omap2xxx_sdrc_get_type();
 
         local_irq_save(flags);
         __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP);
@@ -101,23 +107,14 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force)
         return prev;
 }
 
-#if !defined(CONFIG_ARCH_OMAP2)
-void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
-                                u32 base_cs, u32 force_unlock)
-{
-}
-void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
-                                      u32 mem_type)
-{
-}
-#endif
-
-void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
+/* Used by the clock framework during CORE DPLL changes */
+void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
 {
         unsigned long dll_cnt;
         u32 fast_dll = 0;
 
-        mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
+        /* DDR = 1, SDR = 0 */
+        mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);
 
         /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
          * In the case of 2422, its ok to use CS1 instead of CS0.
@@ -164,28 +161,3 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
         /* 90 degree phase for anything below 133Mhz + disable DLL filter */
         mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
 }
-
-void __init omap2_set_globals_memory(struct omap_globals *omap2_globals)
-{
-        omap2_sdrc_base = omap2_globals->sdrc;
-        omap2_sms_base = omap2_globals->sms;
-}
-
-/* turn on smart idle modes for SDRAM scheduler and controller */
-void __init omap2_init_memory(void)
-{
-        u32 l;
-
-        if (!cpu_is_omap2420())
-                return;
-
-        l = sms_read_reg(SMS_SYSCONFIG);
-        l &= ~(0x3 << 3);
-        l |= (0x2 << 3);
-        sms_write_reg(l, SMS_SYSCONFIG);
-
-        l = sdrc_read_reg(SDRC_SYSCONFIG);
-        l &= ~(0x3 << 3);
-        l |= (0x2 << 3);
-        sdrc_write_reg(l, SDRC_SYSCONFIG);
-}
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
new file mode 100644
index 000000000000..fc74e913c415
--- /dev/null
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -0,0 +1,187 @@
+/*
+ * linux/arch/arm/mach-omap2/usb-musb.c
+ *
+ * This file will contain the board specific details for the
+ * MENTOR USB OTG controller on OMAP3430
+ *
+ * Copyright (C) 2007-2008 Texas Instruments
+ * Copyright (C) 2008 Nokia Corporation
+ * Author: Vikram Pandita
+ *
+ * Generalization by:
+ * Felipe Balbi <felipe.balbi@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+
+#include <linux/usb/musb.h>
+
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/pm.h>
+#include <mach/mux.h>
+#include <mach/usb.h>
+
+static struct resource musb_resources[] = {
+        [0] = { /* start and end set dynamically */
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = { /* general IRQ */
+                .start  = INT_243X_HS_USB_MC,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = { /* DMA IRQ */
+                .start  = INT_243X_HS_USB_DMA,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static int clk_on;
+
+static int musb_set_clock(struct clk *clk, int state)
+{
+        if (state) {
+                if (clk_on > 0)
+                        return -ENODEV;
+
+                clk_enable(clk);
+                clk_on = 1;
+        } else {
+                if (clk_on == 0)
+                        return -ENODEV;
+
+                clk_disable(clk);
+                clk_on = 0;
+        }
+
+        return 0;
+}
+
+static struct musb_hdrc_eps_bits musb_eps[] = {
+        {       "ep1_tx", 10,   },
+        {       "ep1_rx", 10,   },
+        {       "ep2_tx", 9,    },
+        {       "ep2_rx", 9,    },
+        {       "ep3_tx", 3,    },
+        {       "ep3_rx", 3,    },
+        {       "ep4_tx", 3,    },
+        {       "ep4_rx", 3,    },
+        {       "ep5_tx", 3,    },
+        {       "ep5_rx", 3,    },
+        {       "ep6_tx", 3,    },
+        {       "ep6_rx", 3,    },
+        {       "ep7_tx", 3,    },
+        {       "ep7_rx", 3,    },
+        {       "ep8_tx", 2,    },
+        {       "ep8_rx", 2,    },
+        {       "ep9_tx", 2,    },
+        {       "ep9_rx", 2,    },
+        {       "ep10_tx", 2,   },
+        {       "ep10_rx", 2,   },
+        {       "ep11_tx", 2,   },
+        {       "ep11_rx", 2,   },
+        {       "ep12_tx", 2,   },
+        {       "ep12_rx", 2,   },
+        {       "ep13_tx", 2,   },
+        {       "ep13_rx", 2,   },
+        {       "ep14_tx", 2,   },
+        {       "ep14_rx", 2,   },
+        {       "ep15_tx", 2,   },
+        {       "ep15_rx", 2,   },
+};
+
+static struct musb_hdrc_config musb_config = {
+        .multipoint     = 1,
+        .dyn_fifo       = 1,
+        .soft_con       = 1,
+        .dma            = 1,
+        .num_eps        = 16,
+        .dma_channels   = 7,
+        .dma_req_chan   = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3),
+        .ram_bits       = 12,
+        .eps_bits       = musb_eps,
+};
+
+static struct musb_hdrc_platform_data musb_plat = {
+#ifdef CONFIG_USB_MUSB_OTG
+        .mode           = MUSB_OTG,
+#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
+        .mode           = MUSB_HOST,
+#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
+        .mode           = MUSB_PERIPHERAL,
+#endif
+        /* .clock is set dynamically */
+        .set_clock      = musb_set_clock,
+        .config         = &musb_config,
+
+        /* REVISIT charge pump on TWL4030 can supply up to
+         * 100 mA ... but this value is board-specific, like
+         * "mode", and should be passed to usb_musb_init().
+         */
+        .power          = 50,                   /* up to 100 mA */
+};
+
+static u64 musb_dmamask = DMA_32BIT_MASK;
+
+static struct platform_device musb_device = {
+        .name           = "musb_hdrc",
+        .id             = -1,
+        .dev = {
+                .dma_mask               = &musb_dmamask,
+                .coherent_dma_mask      = DMA_32BIT_MASK,
+                .platform_data          = &musb_plat,
+        },
+        .num_resources  = ARRAY_SIZE(musb_resources),
+        .resource       = musb_resources,
+};
+
+#ifdef CONFIG_NOP_USB_XCEIV
+static u64 nop_xceiv_dmamask = DMA_32BIT_MASK;
+
+static struct platform_device nop_xceiv_device = {
+        .name           = "nop_usb_xceiv",
+        .id             = -1,
+        .dev = {
+                .dma_mask               = &nop_xceiv_dmamask,
+                .coherent_dma_mask      = DMA_32BIT_MASK,
+                .platform_data          = NULL,
+        },
+};
+#endif
+
+void __init usb_musb_init(void)
+{
+        if (cpu_is_omap243x())
+                musb_resources[0].start = OMAP243X_HS_BASE;
+        else
+                musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE;
+        musb_resources[0].end = musb_resources[0].start + SZ_8K - 1;
+
+        /*
+         * REVISIT: This line can be removed once all the platforms using
+         * musb_core.c have been converted to use use clkdev.
+         */
+        musb_plat.clock = "ick";
+
+#ifdef CONFIG_NOP_USB_XCEIV
+        if (platform_device_register(&nop_xceiv_device) < 0) {
+                printk(KERN_ERR "Unable to register NOP-XCEIV device\n");
+                return;
+        }
+#endif
+
+        if (platform_device_register(&musb_device) < 0) {
+                printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n");
+                return;
+        }
+}
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index f59a8d0e0824..2c7035d8dcbf 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -71,6 +71,7 @@ config MACH_WRT350N_V2
 
 config MACH_TS78XX
         bool "Technologic Systems TS-78xx"
+        select PM
         help
           Say 'Y' here if you want your kernel to support the
           Technologic Systems TS-78xx platform.
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 0722d6510df1..b31ca4cef365 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -76,7 +76,7 @@ static int __init dns323_dev_id(void)
 
 static int __init dns323_pci_init(void)
 {
-        /* The 5182 doesn't really use it's PCI bus, and initialising PCI
+        /* The 5182 doesn't really use its PCI bus, and initialising PCI
          * gets in the way of initialising the SATA controller.
          */
         if (machine_is_dns323() && dns323_dev_id() != MV88F5182_DEV_ID)
@@ -418,7 +418,7 @@ static void __init dns323_init(void)
         orion5x_i2c_init();
         orion5x_uart0_init();
 
-        /* The 5182 has it's SATA controller on-chip, and needs it's own little
+        /* The 5182 has its SATA controller on-chip, and needs its own little
          * init routine.
          */
         if (dns323_dev_id() == MV88F5182_DEV_ID)
diff --git a/arch/arm/mach-orion5x/include/mach/system.h b/arch/arm/mach-orion5x/include/mach/system.h
index 08e430757890..9b8db1dcfa83 100644
--- a/arch/arm/mach-orion5x/include/mach/system.h
+++ b/arch/arm/mach-orion5x/include/mach/system.h
@@ -19,7 +19,7 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         /*
          * Enable and issue soft reset
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index e0c43b8beb72..c9bf6b81a80d 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -186,7 +186,7 @@ static struct mv_sata_platform_data lsmini_sata_data = {
 
 static void lsmini_power_off(void)
 {
-        arch_reset(0);
+        arch_reset(0, NULL);
 }
 
 
diff --git a/arch/arm/mach-orion5x/ts78xx-fpga.h b/arch/arm/mach-orion5x/ts78xx-fpga.h
new file mode 100644
index 000000000000..0f9cdf458952
--- /dev/null
+++ b/arch/arm/mach-orion5x/ts78xx-fpga.h
@@ -0,0 +1,35 @@
+#define FPGAID(_magic, _rev) ((_magic << 8) + _rev)
+
+/*
+ * get yer id's from http://ts78xx.digriz.org.uk/
+ * do *not* make up your own or 'borrow' any!
+ */
+enum fpga_ids {
+        /* Technologic Systems */
+        TS7800_REV_1    = FPGAID(0x00b480, 0x01),
+        TS7800_REV_2    = FPGAID(0x00b480, 0x02),
+        TS7800_REV_3    = FPGAID(0x00b480, 0x03),
+        TS7800_REV_4    = FPGAID(0x00b480, 0x04),
+        TS7800_REV_5    = FPGAID(0x00b480, 0x05),
+
+        /* Unaffordable & Expensive */
+        UAE_DUMMY       = FPGAID(0xffffff, 0x01),
+};
+
+struct fpga_device {
+        unsigned                present:1;
+        unsigned                init:1;
+};
+
+struct fpga_devices {
+        /* Technologic Systems */
+        struct fpga_device      ts_rtc;
+        struct fpga_device      ts_nand;
+};
+
+struct ts78xx_fpga_data {
+        unsigned int            id;
+        int                     state;
+
+        struct fpga_devices     supports;
+};
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index 1368e9fd1a06..9a6b397f972d 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -10,17 +10,20 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/sysfs.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/ata_platform.h>
 #include <linux/m48t86.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <mach/orion5x.h>
 #include "common.h"
 #include "mpp.h"
+#include "ts78xx-fpga.h"
 
 /*****************************************************************************
  * TS-78xx Info
@@ -33,18 +36,11 @@
 #define TS78XX_FPGA_REGS_VIRT_BASE      0xff900000
 #define TS78XX_FPGA_REGS_SIZE           SZ_1M
 
-#define TS78XX_FPGA_REGS_SYSCON_ID      (TS78XX_FPGA_REGS_VIRT_BASE | 0x000)
-#define TS78XX_FPGA_REGS_SYSCON_LCDI    (TS78XX_FPGA_REGS_VIRT_BASE | 0x004)
-#define TS78XX_FPGA_REGS_SYSCON_LCDO    (TS78XX_FPGA_REGS_VIRT_BASE | 0x008)
-
-#define TS78XX_FPGA_REGS_RTC_CTRL       (TS78XX_FPGA_REGS_VIRT_BASE | 0x808)
-#define TS78XX_FPGA_REGS_RTC_DATA       (TS78XX_FPGA_REGS_VIRT_BASE | 0x80c)
-
-/*
- * 512kB NOR flash Device
- */
-#define TS78XX_NOR_BOOT_BASE            0xff800000
-#define TS78XX_NOR_BOOT_SIZE            SZ_512K
+static struct ts78xx_fpga_data ts78xx_fpga = {
+        .id             = 0,
+        .state          = 1,
+/*      .supports       = ... - populated by ts78xx_fpga_supports() */
+};
 
 /*****************************************************************************
  * I/O Address Mapping
@@ -65,73 +61,47 @@ void __init ts78xx_map_io(void)
 }
 
 /*****************************************************************************
- * 512kB NOR Boot Flash - the chip is a M25P40
+ * Ethernet
  ****************************************************************************/
-static struct mtd_partition ts78xx_nor_boot_flash_resources[] = {
-        {
-                .name           = "ts-bootrom",
-                .offset         = 0,
-                /* only the first 256kB is used */
-                .size           = SZ_256K,
-                .mask_flags     = MTD_WRITEABLE,
-        },
-};
-
-static struct physmap_flash_data ts78xx_nor_boot_flash_data = {
-        .width          = 1,
-        .parts          = ts78xx_nor_boot_flash_resources,
-        .nr_parts       = ARRAY_SIZE(ts78xx_nor_boot_flash_resources),
-};
-
-static struct resource ts78xx_nor_boot_flash_resource = {
-        .flags          = IORESOURCE_MEM,
-        .start          = TS78XX_NOR_BOOT_BASE,
-        .end            = TS78XX_NOR_BOOT_BASE + TS78XX_NOR_BOOT_SIZE - 1,
-};
-
-static struct platform_device ts78xx_nor_boot_flash = {
-        .name           = "physmap-flash",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &ts78xx_nor_boot_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &ts78xx_nor_boot_flash_resource,
+static struct mv643xx_eth_platform_data ts78xx_eth_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
 };
 
 /*****************************************************************************
- * Ethernet
+ * SATA
  ****************************************************************************/
-static struct mv643xx_eth_platform_data ts78xx_eth_data = {
-        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+static struct mv_sata_platform_data ts78xx_sata_data = {
+        .n_ports        = 2,
 };
 
 /*****************************************************************************
  * RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c
  ****************************************************************************/
-#ifdef CONFIG_RTC_DRV_M48T86
-static unsigned char ts78xx_rtc_readbyte(unsigned long addr)
+#define TS_RTC_CTRL     (TS78XX_FPGA_REGS_VIRT_BASE | 0x808)
+#define TS_RTC_DATA     (TS78XX_FPGA_REGS_VIRT_BASE | 0x80c)
+
+static unsigned char ts78xx_ts_rtc_readbyte(unsigned long addr)
 {
-        writeb(addr, TS78XX_FPGA_REGS_RTC_CTRL);
-        return readb(TS78XX_FPGA_REGS_RTC_DATA);
+        writeb(addr, TS_RTC_CTRL);
+        return readb(TS_RTC_DATA);
 }
 
-static void ts78xx_rtc_writebyte(unsigned char value, unsigned long addr)
+static void ts78xx_ts_rtc_writebyte(unsigned char value, unsigned long addr)
 {
-        writeb(addr, TS78XX_FPGA_REGS_RTC_CTRL);
-        writeb(value, TS78XX_FPGA_REGS_RTC_DATA);
+        writeb(addr, TS_RTC_CTRL);
+        writeb(value, TS_RTC_DATA);
 }
 
-static struct m48t86_ops ts78xx_rtc_ops = {
-        .readbyte       = ts78xx_rtc_readbyte,
-        .writebyte      = ts78xx_rtc_writebyte,
+static struct m48t86_ops ts78xx_ts_rtc_ops = {
+        .readbyte       = ts78xx_ts_rtc_readbyte,
+        .writebyte      = ts78xx_ts_rtc_writebyte,
 };
 
-static struct platform_device ts78xx_rtc_device = {
+static struct platform_device ts78xx_ts_rtc_device = {
         .name           = "rtc-m48t86",
         .id             = -1,
         .dev            = {
-                .platform_data  = &ts78xx_rtc_ops,
+                .platform_data  = &ts78xx_ts_rtc_ops,
         },
         .num_resources  = 0,
 };
@@ -146,59 +116,314 @@ static struct platform_device ts78xx_rtc_device = {
  * TODO: track down a guinea pig without an RTC to see if we can work out a
  *              better RTC detection routine
  */
-static int __init ts78xx_rtc_init(void)
+static int ts78xx_ts_rtc_load(void)
 {
+        int rc;
         unsigned char tmp_rtc0, tmp_rtc1;
 
-        tmp_rtc0 = ts78xx_rtc_readbyte(126);
-        tmp_rtc1 = ts78xx_rtc_readbyte(127);
-
-        ts78xx_rtc_writebyte(0x00, 126);
-        ts78xx_rtc_writebyte(0x55, 127);
-        if (ts78xx_rtc_readbyte(127) == 0x55) {
-                ts78xx_rtc_writebyte(0xaa, 127);
-                if (ts78xx_rtc_readbyte(127) == 0xaa
-                                && ts78xx_rtc_readbyte(126) == 0x00) {
-                        ts78xx_rtc_writebyte(tmp_rtc0, 126);
-                        ts78xx_rtc_writebyte(tmp_rtc1, 127);
-                        platform_device_register(&ts78xx_rtc_device);
-                        return 1;
+        tmp_rtc0 = ts78xx_ts_rtc_readbyte(126);
+        tmp_rtc1 = ts78xx_ts_rtc_readbyte(127);
+
+        ts78xx_ts_rtc_writebyte(0x00, 126);
+        ts78xx_ts_rtc_writebyte(0x55, 127);
+        if (ts78xx_ts_rtc_readbyte(127) == 0x55) {
+                ts78xx_ts_rtc_writebyte(0xaa, 127);
+                if (ts78xx_ts_rtc_readbyte(127) == 0xaa
+                                && ts78xx_ts_rtc_readbyte(126) == 0x00) {
+                        ts78xx_ts_rtc_writebyte(tmp_rtc0, 126);
+                        ts78xx_ts_rtc_writebyte(tmp_rtc1, 127);
+
+                        if (ts78xx_fpga.supports.ts_rtc.init == 0) {
+                                rc = platform_device_register(&ts78xx_ts_rtc_device);
+                                if (!rc)
+                                        ts78xx_fpga.supports.ts_rtc.init = 1;
+                        } else
+                                rc = platform_device_add(&ts78xx_ts_rtc_device);
+
+                        return rc;
                 }
         }
 
-        return 0;
+        return -ENODEV;
 };
-#else
-static int __init ts78xx_rtc_init(void)
+
+static void ts78xx_ts_rtc_unload(void)
 {
-        return 0;
+        platform_device_del(&ts78xx_ts_rtc_device);
 }
-#endif
 
 /*****************************************************************************
- * SATA
+ * NAND Flash
  ****************************************************************************/
-static struct mv_sata_platform_data ts78xx_sata_data = {
-        .n_ports        = 2,
+#define TS_NAND_CTRL    (TS78XX_FPGA_REGS_VIRT_BASE | 0x800)    /* VIRT */
+#define TS_NAND_DATA    (TS78XX_FPGA_REGS_PHYS_BASE | 0x804)    /* PHYS */
+
+/*
+ * hardware specific access to control-lines
+ *
+ * ctrl:
+ * NAND_NCE: bit 0 -> bit 2
+ * NAND_CLE: bit 1 -> bit 1
+ * NAND_ALE: bit 2 -> bit 0
+ */
+static void ts78xx_ts_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
+                        unsigned int ctrl)
+{
+        struct nand_chip *this = mtd->priv;
+
+        if (ctrl & NAND_CTRL_CHANGE) {
+                unsigned char bits;
+
+                bits = (ctrl & NAND_NCE) << 2;
+                bits |= ctrl & NAND_CLE;
+                bits |= (ctrl & NAND_ALE) >> 2;
+
+                writeb((readb(TS_NAND_CTRL) & ~0x7) | bits, TS_NAND_CTRL);
+        }
+
+        if (cmd != NAND_CMD_NONE)
+                writeb(cmd, this->IO_ADDR_W);
+}
+
+static int ts78xx_ts_nand_dev_ready(struct mtd_info *mtd)
+{
+        return readb(TS_NAND_CTRL) & 0x20;
+}
+
+const char *ts_nand_part_probes[] = { "cmdlinepart", NULL };
+
+static struct mtd_partition ts78xx_ts_nand_parts[] = {
+        {
+                .name           = "mbr",
+                .offset         = 0,
+                .size           = SZ_128K,
+                .mask_flags     = MTD_WRITEABLE,
+        }, {
+                .name           = "kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_4M,
+        }, {
+                .name           = "initrd",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_4M,
+        }, {
+                .name           = "rootfs",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+        }
 };
 
+static struct platform_nand_data ts78xx_ts_nand_data = {
+        .chip   = {
+                .part_probe_types       = ts_nand_part_probes,
+                .partitions             = ts78xx_ts_nand_parts,
+                .nr_partitions          = ARRAY_SIZE(ts78xx_ts_nand_parts),
+                .chip_delay             = 15,
+                .options                = NAND_USE_FLASH_BBT,
+        },
+        .ctrl   = {
+                /*
+                 * The HW ECC offloading functions, used to give about a 9%
+                 * performance increase for 'dd if=/dev/mtdblockX' and 5% for
+                 * nanddump.  This all however was changed by git commit
+                 * e6cf5df1838c28bb060ac45b5585e48e71bbc740 so now there is
+                 * no performance advantage to be had so we no longer bother
+                 */
+                .cmd_ctrl               = ts78xx_ts_nand_cmd_ctrl,
+                .dev_ready              = ts78xx_ts_nand_dev_ready,
+        },
+};
+
+static struct resource ts78xx_ts_nand_resources = {
+        .start          = TS_NAND_DATA,
+        .end            = TS_NAND_DATA + 4,
+        .flags          = IORESOURCE_IO,
+};
+
+static struct platform_device ts78xx_ts_nand_device = {
+        .name           = "gen_nand",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &ts78xx_ts_nand_data,
+        },
+        .resource       = &ts78xx_ts_nand_resources,
+        .num_resources  = 1,
+};
+
+static int ts78xx_ts_nand_load(void)
+{
+        int rc;
+
+        if (ts78xx_fpga.supports.ts_nand.init == 0) {
+                rc = platform_device_register(&ts78xx_ts_nand_device);
+                if (!rc)
+                        ts78xx_fpga.supports.ts_nand.init = 1;
+        } else
+                rc = platform_device_add(&ts78xx_ts_nand_device);
+
+        return rc;
+};
+
+static void ts78xx_ts_nand_unload(void)
+{
+        platform_device_del(&ts78xx_ts_nand_device);
+}
+
 /*****************************************************************************
- * print some information regarding the board
+ * FPGA 'hotplug' support code
  ****************************************************************************/
-static void __init ts78xx_print_board_id(void)
+static void ts78xx_fpga_devices_zero_init(void)
 {
-        unsigned int board_info;
-
-        board_info = readl(TS78XX_FPGA_REGS_SYSCON_ID);
-        printk(KERN_INFO "TS-78xx Info: FPGA rev=%.2x, Board Magic=%.6x, ",
-                                board_info & 0xff,
-                                (board_info >> 8) & 0xffffff);
-        board_info = readl(TS78XX_FPGA_REGS_SYSCON_LCDI);
-        printk("JP1=%d, JP2=%d\n",
-                                (board_info >> 30) & 0x1,
-                                (board_info >> 31) & 0x1);
+        ts78xx_fpga.supports.ts_rtc.init = 0;
+        ts78xx_fpga.supports.ts_nand.init = 0;
+}
+
+static void ts78xx_fpga_supports(void)
+{
+        /* TODO: put this 'table' into ts78xx-fpga.h */
+        switch (ts78xx_fpga.id) {
+        case TS7800_REV_1:
+        case TS7800_REV_2:
+        case TS7800_REV_3:
+        case TS7800_REV_4:
+        case TS7800_REV_5:
+                ts78xx_fpga.supports.ts_rtc.present = 1;
+                ts78xx_fpga.supports.ts_nand.present = 1;
+                break;
+        default:
+                ts78xx_fpga.supports.ts_rtc.present = 0;
+                ts78xx_fpga.supports.ts_nand.present = 0;
+        }
+}
+
+static int ts78xx_fpga_load_devices(void)
+{
+        int tmp, ret = 0;
+
+        if (ts78xx_fpga.supports.ts_rtc.present == 1) {
+                tmp = ts78xx_ts_rtc_load();
+                if (tmp) {
+                        printk(KERN_INFO "TS-78xx: RTC not registered\n");
+                        ts78xx_fpga.supports.ts_rtc.present = 0;
+                }
+                ret |= tmp;
+        }
+        if (ts78xx_fpga.supports.ts_nand.present == 1) {
+                tmp = ts78xx_ts_nand_load();
+                if (tmp) {
+                        printk(KERN_INFO "TS-78xx: NAND not registered\n");
+                        ts78xx_fpga.supports.ts_nand.present = 0;
+                }
+                ret |= tmp;
+        }
+
+        return ret;
+}
+
+static int ts78xx_fpga_unload_devices(void)
+{
+        int ret = 0;
+
+        if (ts78xx_fpga.supports.ts_rtc.present == 1)
+                ts78xx_ts_rtc_unload();
+        if (ts78xx_fpga.supports.ts_nand.present == 1)
+                ts78xx_ts_nand_unload();
+
+        return ret;
+}
+
+static int ts78xx_fpga_load(void)
+{
+        ts78xx_fpga.id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
+
+        printk(KERN_INFO "TS-78xx FPGA: magic=0x%.6x, rev=0x%.2x\n",
+                        (ts78xx_fpga.id >> 8) & 0xffffff,
+                        ts78xx_fpga.id & 0xff);
+
+        ts78xx_fpga_supports();
+
+        if (ts78xx_fpga_load_devices()) {
+                ts78xx_fpga.state = -1;
+                return -EBUSY;
+        }
+
+        return 0;
 };
 
+static int ts78xx_fpga_unload(void)
+{
+        unsigned int fpga_id;
+
+        fpga_id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
+
+        /*
+         * There does not seem to be a feasible way to block access to the GPIO
+         * pins from userspace (/dev/mem).  This if clause should hopefully warn
+         * those foolish enough not to follow 'policy' :)
+         *
+         * UrJTAG SVN since r1381 can be used to reprogram the FPGA
+         */
+        if (ts78xx_fpga.id != fpga_id) {
+                printk(KERN_ERR "TS-78xx FPGA: magic/rev mismatch\n"
+                        "TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n",
+                        (ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff,
+                        (fpga_id >> 8) & 0xffffff, fpga_id & 0xff);
+                ts78xx_fpga.state = -1;
+                return -EBUSY;
+        }
+
+        if (ts78xx_fpga_unload_devices()) {
+                ts78xx_fpga.state = -1;
+                return -EBUSY;
+        }
+
+        return 0;
+};
+
+static ssize_t ts78xx_fpga_show(struct kobject *kobj,
+                        struct kobj_attribute *attr, char *buf)
+{
+        if (ts78xx_fpga.state < 0)
+                return sprintf(buf, "borked\n");
+
+        return sprintf(buf, "%s\n", (ts78xx_fpga.state) ? "online" : "offline");
+}
+
+static ssize_t ts78xx_fpga_store(struct kobject *kobj,
+                        struct kobj_attribute *attr, const char *buf, size_t n)
+{
+        int value, ret;
+
+        if (ts78xx_fpga.state < 0) {
+                printk(KERN_ERR "TS-78xx FPGA: borked, you must powercycle asap\n");
+                return -EBUSY;
+        }
+
+        if (strncmp(buf, "online", sizeof("online") - 1) == 0)
+                value = 1;
+        else if (strncmp(buf, "offline", sizeof("offline") - 1) == 0)
+                value = 0;
+        else {
+                printk(KERN_ERR "ts78xx_fpga_store: Invalid value\n");
+                return -EINVAL;
+        }
+
+        if (ts78xx_fpga.state == value)
+                return n;
+
+        ret = (ts78xx_fpga.state == 0)
+                ? ts78xx_fpga_load()
+                : ts78xx_fpga_unload();
+
+        if (!(ret < 0))
+                ts78xx_fpga.state = value;
+
+        return n;
+}
+
+static struct kobj_attribute ts78xx_fpga_attr =
+        __ATTR(ts78xx_fpga, 0644, ts78xx_fpga_show, ts78xx_fpga_store);
+
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
@@ -223,30 +448,29 @@ static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = {
         { 17, MPP_UART },
         { 18, MPP_UART },
         { 19, MPP_UART },
+        /*
+         * MPP[20] PCI Clock Out 1
+         * MPP[21] PCI Clock Out 0
+         * MPP[22] Unused
+         * MPP[23] Unused
+         * MPP[24] Unused
+         * MPP[25] Unused
+         */
         { -1 },
 };
 
 static void __init ts78xx_init(void)
 {
+        int ret;
+
         /*
          * Setup basic Orion functions. Need to be called early.
          */
         orion5x_init();
 
-        ts78xx_print_board_id();
-
         orion5x_mpp_conf(ts78xx_mpp_modes);
 
         /*
-         * MPP[20] PCI Clock Out 1
-         * MPP[21] PCI Clock Out 0
-         * MPP[22] Unused
-         * MPP[23] Unused
-         * MPP[24] Unused
-         * MPP[25] Unused
-         */
-
-        /*
          * Configure peripherals.
          */
         orion5x_ehci0_init();
@@ -257,12 +481,12 @@ static void __init ts78xx_init(void)
         orion5x_uart1_init();
         orion5x_xor_init();
 
-        orion5x_setup_dev_boot_win(TS78XX_NOR_BOOT_BASE,
-                                   TS78XX_NOR_BOOT_SIZE);
-        platform_device_register(&ts78xx_nor_boot_flash);
-
-        if (!ts78xx_rtc_init())
-                printk(KERN_INFO "TS-78xx RTC not detected or enabled\n");
+        /* FPGA init */
+        ts78xx_fpga_devices_zero_init();
+        ret = ts78xx_fpga_load();
+        ret = sysfs_create_file(power_kobj, &ts78xx_fpga_attr.attr);
+        if (ret)
+                printk(KERN_ERR "sysfs_create_file failed: %d\n", ret);
 }
 
 MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
diff --git a/arch/arm/mach-pnx4008/include/mach/system.h b/arch/arm/mach-pnx4008/include/mach/system.h
index e12e7abfcbcf..5dda2bb55f8d 100644
--- a/arch/arm/mach-pnx4008/include/mach/system.h
+++ b/arch/arm/mach-pnx4008/include/mach/system.h
@@ -30,7 +30,7 @@ static void arch_idle(void)
         cpu_do_idle();
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         cpu_reset(0);
 }
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 8eea7306f29b..96a2006cb597 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -40,6 +40,9 @@ choice
 config GUMSTIX_AM200EPD
         bool "Enable AM200EPD board support"
 
+config GUMSTIX_AM300EPD
+        bool "Enable AM300EPD board support"
+
 endchoice
 
 config MACH_INTELMOTE2
@@ -254,10 +257,24 @@ config MACH_EM_X270
         bool "CompuLab EM-x270 platform"
         select PXA27x
 
+config MACH_EXEDA
+        bool "CompuLab eXeda platform"
+        select PXA27x
+
 config MACH_COLIBRI
-        bool "Toradex Colibri PX27x"
+        bool "Toradex Colibri PXA270"
         select PXA27x
 
+config MACH_COLIBRI300
+        bool "Toradex Colibri PXA300/310"
+        select PXA3xx
+        select CPU_PXA300
+
+config MACH_COLIBRI320
+        bool "Toradex Colibri PXA320"
+        select PXA3xx
+        select CPU_PXA320
+
 config MACH_ZYLONITE
         bool "PXA3xx Development Platform (aka Zylonite)"
         select PXA3xx
@@ -295,8 +312,15 @@ config MACH_MAGICIAN
         bool "Enable HTC Magician Support"
         select PXA27x
         select IWMMXT
+        select PXA_SSP
+        select HAVE_PWM
         select PXA_HAVE_BOARD_IRQS
 
+config MACH_HIMALAYA
+        bool "HTC Himalaya Support"
+        select CPU_PXA26x
+        select FB_W100
+
 config MACH_MIOA701
         bool "Mitac Mio A701 Support"
         select PXA27x
@@ -319,6 +343,16 @@ config ARCH_PXA_PALM
         bool "PXA based Palm PDAs"
         select HAVE_PWM
 
+config MACH_PALMT5
+        bool "Palm Tungsten|T5"
+        default y
+        depends on ARCH_PXA_PALM
+        select PXA27x
+        select IWMMXT
+        help
+          Say Y here if you intend to run this kernel on a Palm Tungsten|T5
+          handheld computer.
+
 config MACH_PALMTX
         bool "Palm T|X"
         default y
@@ -339,6 +373,16 @@ config MACH_PALMZ72
           Say Y here if you intend to run this kernel on Palm Zire 72
           handheld computer.
 
+config MACH_PALMLD
+        bool "Palm LifeDrive"
+        default y
+        depends on ARCH_PXA_PALM
+        select PXA27x
+        select IWMMXT
+        help
+          Say Y here if you intend to run this kernel on a Palm LifeDrive
+          handheld computer.
+
 config MACH_PCM990_BASEBOARD
         bool "PHYTEC PCM-990 development board"
         select HAVE_PWM
@@ -359,6 +403,18 @@ config PCM990_DISPLAY_NONE
 
 endchoice
 
+config MACH_CSB726
+        bool "Enable Cogent CSB726 System On a Module"
+        select PXA27x
+        select IWMMXT
+        help
+          Say Y here if you intend to run this kernel on a Cogent
+          CSB726 System On Module.
+
+config CSB726_CSB701
+        bool "Enable supprot for CSB701 baseboard"
+        depends on MACH_CSB726
+
 config PXA_EZX
         bool "Motorola EZX Platform"
         select PXA27x
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 7b28bb561d63..c80e1bac4945 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -3,8 +3,8 @@
 #
 
 # Common support (must be linked before board specific support)
-obj-y                           += clock.o devices.o generic.o irq.o dma.o \
-                                   time.o gpio.o reset.o
+obj-y                           += clock.o devices.o generic.o irq.o \
+                                   time.o reset.o
 obj-$(CONFIG_PM)                += pm.o sleep.o standby.o
 
 ifeq ($(CONFIG_CPU_FREQ),y)
@@ -28,13 +28,16 @@ obj-$(CONFIG_CPU_PXA930)	+= pxa930.o
 # Specific board support
 obj-$(CONFIG_ARCH_GUMSTIX)      += gumstix.o
 obj-$(CONFIG_GUMSTIX_AM200EPD)  += am200epd.o
+obj-$(CONFIG_GUMSTIX_AM300EPD)  += am300epd.o
 obj-$(CONFIG_ARCH_LUBBOCK)      += lubbock.o
 obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o
 obj-$(CONFIG_MACH_MAINSTONE)    += mainstone.o
 obj-$(CONFIG_MACH_MP900C)       += mp900.o
 obj-$(CONFIG_ARCH_PXA_IDP)      += idp.o
 obj-$(CONFIG_MACH_TRIZEPS4)     += trizeps4.o
-obj-$(CONFIG_MACH_COLIBRI)      += colibri.o
+obj-$(CONFIG_MACH_COLIBRI)      += colibri-pxa270.o
+obj-$(CONFIG_MACH_COLIBRI300)   += colibri-pxa3xx.o colibri-pxa300.o
+obj-$(CONFIG_MACH_COLIBRI320)   += colibri-pxa3xx.o colibri-pxa320.o
 obj-$(CONFIG_MACH_H5000)        += h5000.o
 obj-$(CONFIG_PXA_SHARP_C7xx)    += corgi.o sharpsl_pm.o corgi_pm.o
 obj-$(CONFIG_PXA_SHARP_Cxx00)   += spitz.o sharpsl_pm.o spitz_pm.o
@@ -45,6 +48,7 @@ obj-$(CONFIG_MACH_PCM990_BASEBOARD)	+= pcm990-baseboard.o
 obj-$(CONFIG_MACH_TOSA)         += tosa.o
 obj-$(CONFIG_MACH_EM_X270)      += em-x270.o
 obj-$(CONFIG_MACH_MAGICIAN)     += magician.o
+obj-$(CONFIG_MACH_HIMALAYA)     += himalaya.o
 obj-$(CONFIG_MACH_MIOA701)      += mioa701.o mioa701_bootresume.o
 obj-$(CONFIG_ARCH_PXA_ESERIES)  += eseries.o
 obj-$(CONFIG_MACH_E330)         += e330.o
@@ -53,7 +57,9 @@ obj-$(CONFIG_MACH_E740)		+= e740.o
 obj-$(CONFIG_MACH_E750)         += e750.o
 obj-$(CONFIG_MACH_E400)         += e400.o
 obj-$(CONFIG_MACH_E800)         += e800.o
+obj-$(CONFIG_MACH_PALMT5)       += palmt5.o
 obj-$(CONFIG_MACH_PALMTX)       += palmtx.o
+obj-$(CONFIG_MACH_PALMLD)       += palmld.o
 obj-$(CONFIG_MACH_PALMZ72)      += palmz72.o
 obj-$(CONFIG_ARCH_VIPER)        += viper.o
 
@@ -71,6 +77,8 @@ obj-$(CONFIG_MACH_CM_X300)      += cm-x300.o
 obj-$(CONFIG_PXA_EZX)           += ezx.o
 
 obj-$(CONFIG_MACH_INTELMOTE2)   += imote2.o
+obj-$(CONFIG_MACH_CSB726)       += csb726.o
+obj-$(CONFIG_CSB726_CSB701)     += csb701.o
 
 # Support for blinky lights
 led-y := leds.o
diff --git a/arch/arm/mach-pxa/am200epd.c b/arch/arm/mach-pxa/am200epd.c
index 77ee80e5e47b..3499fada73ae 100644
--- a/arch/arm/mach-pxa/am200epd.c
+++ b/arch/arm/mach-pxa/am200epd.c
@@ -30,8 +30,8 @@
 #include <linux/irq.h>
 #include <linux/gpio.h>
 
+#include <mach/pxa25x.h>
 #include <mach/gumstix.h>
-#include <mach/mfp-pxa25x.h>
 #include <mach/pxafb.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/am300epd.c b/arch/arm/mach-pxa/am300epd.c
new file mode 100644
index 000000000000..4bd10a17332e
--- /dev/null
+++ b/arch/arm/mach-pxa/am300epd.c
@@ -0,0 +1,295 @@
+/*
+ * am300epd.c -- Platform device for AM300 EPD kit
+ *
+ * Copyright (C) 2008, Jaya Kumar
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive for
+ * more details.
+ *
+ * This work was made possible by help and equipment support from E-Ink
+ * Corporation. http://support.eink.com/community
+ *
+ * This driver is written to be used with the Broadsheet display controller.
+ * on the AM300 EPD prototype kit/development kit with an E-Ink 800x600
+ * Vizplex EPD on a Gumstix board using the Broadsheet interface board.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+
+#include <mach/gumstix.h>
+#include <mach/mfp-pxa25x.h>
+#include <mach/pxafb.h>
+
+#include "generic.h"
+
+#include <video/broadsheetfb.h>
+
+static unsigned int panel_type = 6;
+static struct platform_device *am300_device;
+static struct broadsheet_board am300_board;
+
+static unsigned long am300_pin_config[] __initdata = {
+        GPIO16_GPIO,
+        GPIO17_GPIO,
+        GPIO32_GPIO,
+        GPIO48_GPIO,
+        GPIO49_GPIO,
+        GPIO51_GPIO,
+        GPIO74_GPIO,
+        GPIO75_GPIO,
+        GPIO76_GPIO,
+        GPIO77_GPIO,
+
+        /* this is the 16-bit hdb bus 58-73 */
+        GPIO58_GPIO,
+        GPIO59_GPIO,
+        GPIO60_GPIO,
+        GPIO61_GPIO,
+
+        GPIO62_GPIO,
+        GPIO63_GPIO,
+        GPIO64_GPIO,
+        GPIO65_GPIO,
+
+        GPIO66_GPIO,
+        GPIO67_GPIO,
+        GPIO68_GPIO,
+        GPIO69_GPIO,
+
+        GPIO70_GPIO,
+        GPIO71_GPIO,
+        GPIO72_GPIO,
+        GPIO73_GPIO,
+};
+
+/* register offsets for gpio control */
+#define PWR_GPIO_PIN    16
+#define CFG_GPIO_PIN    17
+#define RDY_GPIO_PIN    32
+#define DC_GPIO_PIN     48
+#define RST_GPIO_PIN    49
+#define LED_GPIO_PIN    51
+#define RD_GPIO_PIN     74
+#define WR_GPIO_PIN     75
+#define CS_GPIO_PIN     76
+#define IRQ_GPIO_PIN    77
+
+/* hdb bus */
+#define DB0_GPIO_PIN    58
+#define DB15_GPIO_PIN   73
+
+static int gpios[] = { PWR_GPIO_PIN, CFG_GPIO_PIN, RDY_GPIO_PIN, DC_GPIO_PIN,
+                        RST_GPIO_PIN, RD_GPIO_PIN, WR_GPIO_PIN, CS_GPIO_PIN,
+                        IRQ_GPIO_PIN, LED_GPIO_PIN };
+static char *gpio_names[] = { "PWR", "CFG", "RDY", "DC", "RST", "RD", "WR",
+                                "CS", "IRQ", "LED" };
+
+static int am300_wait_event(struct broadsheetfb_par *par)
+{
+        /* todo: improve err recovery */
+        wait_event(par->waitq, gpio_get_value(RDY_GPIO_PIN));
+        return 0;
+}
+
+static int am300_init_gpio_regs(struct broadsheetfb_par *par)
+{
+        int i;
+        int err;
+        char dbname[8];
+
+        for (i = 0; i < ARRAY_SIZE(gpios); i++) {
+                err = gpio_request(gpios[i], gpio_names[i]);
+                if (err) {
+                        dev_err(&am300_device->dev, "failed requesting "
+                                "gpio %s, err=%d\n", gpio_names[i], err);
+                        goto err_req_gpio;
+                }
+        }
+
+        /* we also need to take care of the hdb bus */
+        for (i = DB0_GPIO_PIN; i <= DB15_GPIO_PIN; i++) {
+                sprintf(dbname, "DB%d", i);
+                err = gpio_request(i, dbname);
+                if (err) {
+                        dev_err(&am300_device->dev, "failed requesting "
+                                "gpio %d, err=%d\n", i, err);
+                        while (i >= DB0_GPIO_PIN)
+                                gpio_free(i--);
+                        i = ARRAY_SIZE(gpios) - 1;
+                        goto err_req_gpio;
+                }
+        }
+
+        /* setup the outputs and init values */
+        gpio_direction_output(PWR_GPIO_PIN, 0);
+        gpio_direction_output(CFG_GPIO_PIN, 1);
+        gpio_direction_output(DC_GPIO_PIN, 0);
+        gpio_direction_output(RD_GPIO_PIN, 1);
+        gpio_direction_output(WR_GPIO_PIN, 1);
+        gpio_direction_output(CS_GPIO_PIN, 1);
+        gpio_direction_output(RST_GPIO_PIN, 0);
+
+        /* setup the inputs */
+        gpio_direction_input(RDY_GPIO_PIN);
+        gpio_direction_input(IRQ_GPIO_PIN);
+
+        /* start the hdb bus as an input */
+        for (i = DB0_GPIO_PIN; i <= DB15_GPIO_PIN; i++)
+                gpio_direction_output(i, 0);
+
+        /* go into command mode */
+        gpio_set_value(CFG_GPIO_PIN, 1);
+        gpio_set_value(RST_GPIO_PIN, 0);
+        msleep(10);
+        gpio_set_value(RST_GPIO_PIN, 1);
+        msleep(10);
+        am300_wait_event(par);
+
+        return 0;
+
+err_req_gpio:
+        while (i > 0)
+                gpio_free(gpios[i--]);
+
+        return err;
+}
+
+static int am300_init_board(struct broadsheetfb_par *par)
+{
+        return am300_init_gpio_regs(par);
+}
+
+static void am300_cleanup(struct broadsheetfb_par *par)
+{
+        int i;
+
+        free_irq(IRQ_GPIO(RDY_GPIO_PIN), par);
+
+        for (i = 0; i < ARRAY_SIZE(gpios); i++)
+                gpio_free(gpios[i]);
+
+        for (i = DB0_GPIO_PIN; i <= DB15_GPIO_PIN; i++)
+                gpio_free(i);
+
+}
+
+static u16 am300_get_hdb(struct broadsheetfb_par *par)
+{
+        u16 res = 0;
+        int i;
+
+        for (i = 0; i <= (DB15_GPIO_PIN - DB0_GPIO_PIN) ; i++)
+                res |= (gpio_get_value(DB0_GPIO_PIN + i)) ? (1 << i) : 0;
+
+        return res;
+}
+
+static void am300_set_hdb(struct broadsheetfb_par *par, u16 data)
+{
+        int i;
+
+        for (i = 0; i <= (DB15_GPIO_PIN - DB0_GPIO_PIN) ; i++)
+                gpio_set_value(DB0_GPIO_PIN + i, (data >> i) & 0x01);
+}
+
+
+static void am300_set_ctl(struct broadsheetfb_par *par, unsigned char bit,
+                                u8 state)
+{
+        switch (bit) {
+        case BS_CS:
+                gpio_set_value(CS_GPIO_PIN, state);
+                break;
+        case BS_DC:
+                gpio_set_value(DC_GPIO_PIN, state);
+                break;
+        case BS_WR:
+                gpio_set_value(WR_GPIO_PIN, state);
+                break;
+        }
+}
+
+static int am300_get_panel_type(void)
+{
+        return panel_type;
+}
+
+static irqreturn_t am300_handle_irq(int irq, void *dev_id)
+{
+        struct broadsheetfb_par *par = dev_id;
+
+        wake_up(&par->waitq);
+        return IRQ_HANDLED;
+}
+
+static int am300_setup_irq(struct fb_info *info)
+{
+        int ret;
+        struct broadsheetfb_par *par = info->par;
+
+        ret = request_irq(IRQ_GPIO(RDY_GPIO_PIN), am300_handle_irq,
+                                IRQF_DISABLED|IRQF_TRIGGER_RISING,
+                                "AM300", par);
+        if (ret)
+                dev_err(&am300_device->dev, "request_irq failed: %d\n", ret);
+
+        return ret;
+}
+
+static struct broadsheet_board am300_board = {
+        .owner                  = THIS_MODULE,
+        .init                   = am300_init_board,
+        .cleanup                = am300_cleanup,
+        .set_hdb                = am300_set_hdb,
+        .get_hdb                = am300_get_hdb,
+        .set_ctl                = am300_set_ctl,
+        .wait_for_rdy           = am300_wait_event,
+        .get_panel_type         = am300_get_panel_type,
+        .setup_irq              = am300_setup_irq,
+};
+
+int __init am300_init(void)
+{
+        int ret;
+
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(am300_pin_config));
+
+        /* request our platform independent driver */
+        request_module("broadsheetfb");
+
+        am300_device = platform_device_alloc("broadsheetfb", -1);
+        if (!am300_device)
+                return -ENOMEM;
+
+        /* the am300_board that will be seen by broadsheetfb is a copy */
+        platform_device_add_data(am300_device, &am300_board,
+                                        sizeof(am300_board));
+
+        ret = platform_device_add(am300_device);
+
+        if (ret) {
+                platform_device_put(am300_device);
+                return ret;
+        }
+
+        return 0;
+}
+
+module_param(panel_type, uint, 0);
+MODULE_PARM_DESC(panel_type, "Select the panel type: 6, 8, 97");
+
+MODULE_DESCRIPTION("board driver for am300 epd kit");
+MODULE_AUTHOR("Jaya Kumar");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index 40b774084514..db52d2c4791d 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -87,7 +87,7 @@ void clks_register(struct clk_lookup *clks, size_t num)
                 clkdev_add(&clks[i]);
 }
 
-int clk_add_alias(char *alias, struct device *alias_dev, char *id,
+int clk_add_alias(const char *alias, const char *alias_dev_name, char *id,
         struct device *dev)
 {
         struct clk *r = clk_get(dev, id);
@@ -96,7 +96,7 @@ int clk_add_alias(char *alias, struct device *alias_dev, char *id,
         if (!r)
                 return -ENODEV;
 
-        l = clkdev_alloc(r, alias, alias_dev ? dev_name(alias_dev) : NULL);
+        l = clkdev_alloc(r, alias, alias_dev_name);
         clk_put(r);
         if (!l)
                 return -ENODEV;
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
index 4e9c613c6767..5599bceff738 100644
--- a/arch/arm/mach-pxa/clock.h
+++ b/arch/arm/mach-pxa/clock.h
@@ -69,6 +69,6 @@ extern void clk_pxa3xx_cken_disable(struct clk *);
 #endif
 
 void clks_register(struct clk_lookup *clks, size_t num);
-int clk_add_alias(char *alias, struct device *alias_dev, char *id,
+int clk_add_alias(const char *alias, const char *alias_name, char *id,
         struct device *dev);
 
diff --git a/arch/arm/mach-pxa/cm-x255.c b/arch/arm/mach-pxa/cm-x255.c
index 83a4cdf08176..253fd76142d6 100644
--- a/arch/arm/mach-pxa/cm-x255.c
+++ b/arch/arm/mach-pxa/cm-x255.c
@@ -22,10 +22,8 @@
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 
-#include <mach/pxa2xx-regs.h>
-#include <mach/mfp-pxa25x.h>
+#include <mach/pxa25x.h>
 #include <mach/pxa2xx_spi.h>
-#include <mach/bitfield.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
index df83b97f303f..34576ba5f5fd 100644
--- a/arch/arm/mach-pxa/cm-x270.c
+++ b/arch/arm/mach-pxa/cm-x270.c
@@ -17,7 +17,7 @@
 #include <linux/rtc-v3020.h>
 #include <video/mbxfb.h>
 
-#include <mach/mfp-pxa27x.h>
+#include <mach/pxa27x.h>
 #include <mach/ohci.h>
 #include <mach/mmc.h>
 
diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c
index 3156b25f6e9d..7873fa3d8fa4 100644
--- a/arch/arm/mach-pxa/cm-x2xx-pci.c
+++ b/arch/arm/mach-pxa/cm-x2xx-pci.c
@@ -22,7 +22,6 @@
 #include <linux/gpio.h>
 
 #include <asm/mach/pci.h>
-#include <mach/pxa-regs.h>
 #include <asm/mach-types.h>
 
 #include <asm/hardware/it8152.h>
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
index d99fd9e4d888..117b5435f8d5 100644
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -22,8 +22,6 @@
 #include <asm/mach/map.h>
 
 #include <mach/pxa2xx-regs.h>
-#include <mach/mfp-pxa27x.h>
-#include <mach/pxa-regs.h>
 #include <mach/audio.h>
 #include <mach/pxafb.h>
 
@@ -96,7 +94,7 @@ static struct resource cmx270_dm9000_resource[] = {
 };
 
 static struct dm9000_plat_data cmx270_dm9000_platdata = {
-        .flags          = DM9000_PLATF_32BITONLY,
+        .flags          = DM9000_PLATF_32BITONLY | DM9000_PLATF_NO_EEPROM,
 };
 
 static struct platform_device cmx2xx_dm9000_device = {
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index ff0c577cd1ac..a9f48b1cb54a 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -28,9 +28,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/mfp-pxa300.h>
-
-#include <mach/hardware.h>
+#include <mach/pxa300.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
 #include <mach/ohci.h>
@@ -162,7 +160,7 @@ static struct resource dm9000_resources[] = {
 };
 
 static struct dm9000_plat_data cm_x300_dm9000_platdata = {
-        .flags          = DM9000_PLATF_16BITONLY,
+        .flags          = DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM,
 };
 
 static struct platform_device dm9000_device = {
diff --git a/arch/arm/mach-pxa/colibri.c b/arch/arm/mach-pxa/colibri-pxa270.c
index e8473624427e..01bcfaae75bc 100644
--- a/arch/arm/mach-pxa/colibri.c
+++ b/arch/arm/mach-pxa/colibri-pxa270.c
@@ -1,7 +1,7 @@
 /*
- *  linux/arch/arm/mach-pxa/colibri.c
+ *  linux/arch/arm/mach-pxa/colibri-pxa270.c
  *
- *  Support for Toradex PXA27x based Colibri module
+ *  Support for Toradex PXA270 based Colibri module
  *  Daniel Mack <daniel@caiaq.de>
  *
  *  This program is free software; you can redistribute it and/or modify
@@ -20,6 +20,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
+#include <linux/gpio.h>
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -28,20 +29,23 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/flash.h>
-#include <mach/pxa-regs.h>
-#include <mach/mfp-pxa27x.h>
+
+#include <mach/pxa27x.h>
 #include <mach/colibri.h>
 
 #include "generic.h"
 #include "devices.h"
 
-static unsigned long colibri_pin_config[] __initdata = {
+/*
+ * GPIO configuration
+ */
+static mfp_cfg_t colibri_pxa270_pin_config[] __initdata = {
         GPIO78_nCS_2,   /* Ethernet CS */
         GPIO114_GPIO,   /* Ethernet IRQ */
 };
 
 /*
- * Flash
+ * NOR flash
  */
 static struct mtd_partition colibri_partitions[] = {
         {
@@ -70,39 +74,40 @@ static struct physmap_flash_data colibri_flash_data[] = {
         }
 };
 
-static struct resource flash_resource = {
+static struct resource colibri_pxa270_flash_resource = {
         .start  = PXA_CS0_PHYS,
         .end    = PXA_CS0_PHYS + SZ_32M - 1,
         .flags  = IORESOURCE_MEM,
 };
 
-static struct platform_device flash_device = {
+static struct platform_device colibri_pxa270_flash_device = {
         .name   = "physmap-flash",
         .id     = 0,
         .dev    = {
                 .platform_data = colibri_flash_data,
         },
-        .resource = &flash_resource,
+        .resource = &colibri_pxa270_flash_resource,
         .num_resources = 1,
 };
 
 /*
  * DM9000 Ethernet
  */
+#if defined(CONFIG_DM9000)
 static struct resource dm9000_resources[] = {
         [0] = {
-                .start  = COLIBRI_ETH_PHYS,
-                .end    = COLIBRI_ETH_PHYS + 3,
+                .start  = COLIBRI_PXA270_ETH_PHYS,
+                .end    = COLIBRI_PXA270_ETH_PHYS + 3,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = COLIBRI_ETH_PHYS + 4,
-                .end    = COLIBRI_ETH_PHYS + 4 + 500,
+                .start  = COLIBRI_PXA270_ETH_PHYS + 4,
+                .end    = COLIBRI_PXA270_ETH_PHYS + 4 + 500,
                 .flags  = IORESOURCE_MEM,
         },
         [2] = {
-                .start  = COLIBRI_ETH_IRQ,
-                .end    = COLIBRI_ETH_IRQ,
+                .start  = COLIBRI_PXA270_ETH_IRQ,
+                .end    = COLIBRI_PXA270_ETH_IRQ,
                 .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_RISING,
         },
 };
@@ -113,25 +118,28 @@ static struct platform_device dm9000_device = {
         .num_resources  = ARRAY_SIZE(dm9000_resources),
         .resource       = dm9000_resources,
 };
+#endif /* CONFIG_DM9000 */
 
-static struct platform_device *colibri_devices[] __initdata = {
-        &flash_device,
+static struct platform_device *colibri_pxa270_devices[] __initdata = {
+        &colibri_pxa270_flash_device,
+#if defined(CONFIG_DM9000)
         &dm9000_device,
+#endif
 };
 
-static void __init colibri_init(void)
+static void __init colibri_pxa270_init(void)
 {
-        pxa2xx_mfp_config(ARRAY_AND_SIZE(colibri_pin_config));
-
-        platform_add_devices(colibri_devices, ARRAY_SIZE(colibri_devices));
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa270_pin_config));
+        platform_add_devices(ARRAY_AND_SIZE(colibri_pxa270_devices));
 }
 
-MACHINE_START(COLIBRI, "Toradex Colibri PXA27x")
+MACHINE_START(COLIBRI, "Toradex Colibri PXA270")
         .phys_io        = 0x40000000,
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = COLIBRI_SDRAM_BASE + 0x100,
-        .init_machine   = colibri_init,
+        .init_machine   = colibri_pxa270_init,
         .map_io         = pxa_map_io,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
 MACHINE_END
+
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c
new file mode 100644
index 000000000000..10c2eaf93230
--- /dev/null
+++ b/arch/arm/mach-pxa/colibri-pxa300.c
@@ -0,0 +1,190 @@
+/*
+ *  arch/arm/mach-pxa/colibri-pxa300.c
+ *
+ *  Support for Toradex PXA300/310 based Colibri module
+ *
+ *  Daniel Mack <daniel@caiaq.de>
+ *  Matthias Meier <matthias.j.meier@gmx.net>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <net/ax88796.h>
+
+#include <asm/mach-types.h>
+#include <asm/sizes.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+
+#include <mach/pxa300.h>
+#include <mach/colibri.h>
+#include <mach/ohci.h>
+#include <mach/pxafb.h>
+
+#include "generic.h"
+#include "devices.h"
+
+#if defined(CONFIG_AX88796)
+#define COLIBRI_ETH_IRQ_GPIO    mfp_to_gpio(GPIO26_GPIO)
+/*
+ * Asix AX88796 Ethernet
+ */
+static struct ax_plat_data colibri_asix_platdata = {
+        .flags          = AXFLG_MAC_FROMDEV,
+        .wordlength     = 2
+};
+
+static struct resource colibri_asix_resource[] = {
+        [0] = {
+                .start = PXA3xx_CS2_PHYS,
+                .end   = PXA3xx_CS2_PHYS + (0x20 * 2) - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO),
+                .end   = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO),
+                .flags = IORESOURCE_IRQ
+        }
+};
+
+static struct platform_device asix_device = {
+        .name           = "ax88796",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(colibri_asix_resource),
+        .resource       = colibri_asix_resource,
+        .dev            = {
+                .platform_data = &colibri_asix_platdata
+        }
+};
+
+static mfp_cfg_t colibri_pxa300_eth_pin_config[] __initdata = {
+        GPIO1_nCS2,                     /* AX88796 chip select */
+        GPIO26_GPIO | MFP_PULL_HIGH     /* AX88796 IRQ */
+};
+
+static void __init colibri_pxa300_init_eth(void)
+{
+        pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_eth_pin_config));
+        set_irq_type(gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), IRQ_TYPE_EDGE_FALLING);
+        platform_device_register(&asix_device);
+}
+#else
+static inline void __init colibri_pxa300_init_eth(void) {}
+#endif /* CONFIG_AX88796 */
+
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static mfp_cfg_t colibri_pxa300_usb_pin_config[] __initdata = {
+        GPIO0_2_USBH_PEN,
+        GPIO1_2_USBH_PWR,
+};
+
+static struct pxaohci_platform_data colibri_pxa300_ohci_info = {
+        .port_mode      = PMM_GLOBAL_MODE,
+        .flags          = ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW,
+};
+
+void __init colibri_pxa300_init_ohci(void)
+{
+        pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_usb_pin_config));
+        pxa_set_ohci_info(&colibri_pxa300_ohci_info);
+}
+#else
+static inline void colibri_pxa300_init_ohci(void) {}
+#endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */
+
+static mfp_cfg_t colibri_pxa300_mmc_pin_config[] __initdata = {
+        GPIO7_MMC1_CLK,
+        GPIO14_MMC1_CMD,
+        GPIO3_MMC1_DAT0,
+        GPIO4_MMC1_DAT1,
+        GPIO5_MMC1_DAT2,
+        GPIO6_MMC1_DAT3,
+};
+
+#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
+static mfp_cfg_t colibri_pxa300_lcd_pin_config[] __initdata = {
+        GPIO54_LCD_LDD_0,
+        GPIO55_LCD_LDD_1,
+        GPIO56_LCD_LDD_2,
+        GPIO57_LCD_LDD_3,
+        GPIO58_LCD_LDD_4,
+        GPIO59_LCD_LDD_5,
+        GPIO60_LCD_LDD_6,
+        GPIO61_LCD_LDD_7,
+        GPIO62_LCD_LDD_8,
+        GPIO63_LCD_LDD_9,
+        GPIO64_LCD_LDD_10,
+        GPIO65_LCD_LDD_11,
+        GPIO66_LCD_LDD_12,
+        GPIO67_LCD_LDD_13,
+        GPIO68_LCD_LDD_14,
+        GPIO69_LCD_LDD_15,
+        GPIO70_LCD_LDD_16,
+        GPIO71_LCD_LDD_17,
+        GPIO62_LCD_CS_N,
+        GPIO72_LCD_FCLK,
+        GPIO73_LCD_LCLK,
+        GPIO74_LCD_PCLK,
+        GPIO75_LCD_BIAS,
+        GPIO76_LCD_VSYNC,
+};
+
+static void __init colibri_pxa300_init_lcd(void)
+{
+        pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_lcd_pin_config));
+}
+
+#else
+static inline void colibri_pxa300_init_lcd(void) {}
+#endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULE */
+
+#if defined(SND_AC97_CODEC) || defined(SND_AC97_CODEC_MODULE)
+static mfp_cfg_t colibri_pxa310_ac97_pin_config[] __initdata = {
+        GPIO24_AC97_SYSCLK,
+        GPIO23_AC97_nACRESET,
+        GPIO25_AC97_SDATA_IN_0,
+        GPIO27_AC97_SDATA_OUT,
+        GPIO28_AC97_SYNC,
+        GPIO29_AC97_BITCLK
+};
+
+static inline void __init colibri_pxa310_init_ac97(void)
+{
+        /* no AC97 codec on Colibri PXA300 */
+        if (!cpu_is_pxa310())
+                return;
+
+        pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa310_ac97_pin_config));
+        pxa_set_ac97_info(NULL);
+}
+#else
+static inline void colibri_pxa310_init_ac97(void) {}
+#endif
+
+void __init colibri_pxa300_init(void)
+{
+        colibri_pxa300_init_eth();
+        colibri_pxa300_init_ohci();
+        colibri_pxa300_init_lcd();
+        colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO39_GPIO));
+        colibri_pxa310_init_ac97();
+        colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa300_mmc_pin_config),
+                                mfp_to_gpio(MFP_PIN_GPIO13));
+}
+
+MACHINE_START(COLIBRI300, "Toradex Colibri PXA300")
+        .phys_io        = 0x40000000,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .boot_params    = COLIBRI_SDRAM_BASE + 0x100,
+        .init_machine   = colibri_pxa300_init,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa3xx_init_irq,
+        .timer          = &pxa_timer,
+MACHINE_END
+
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c
new file mode 100644
index 000000000000..55b74a7a6151
--- /dev/null
+++ b/arch/arm/mach-pxa/colibri-pxa320.c
@@ -0,0 +1,187 @@
+/*
+ *  arch/arm/mach-pxa/colibri-pxa320.c
+ *
+ *  Support for Toradex PXA320/310 based Colibri module
+ *
+ *  Daniel Mack <daniel@caiaq.de>
+ *  Matthias Meier <matthias.j.meier@gmx.net>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <net/ax88796.h>
+
+#include <asm/mach-types.h>
+#include <asm/sizes.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+
+#include <mach/pxa3xx-regs.h>
+#include <mach/mfp-pxa320.h>
+#include <mach/colibri.h>
+#include <mach/pxafb.h>
+#include <mach/ohci.h>
+
+#include "generic.h"
+#include "devices.h"
+
+#if defined(CONFIG_AX88796)
+#define COLIBRI_ETH_IRQ_GPIO    mfp_to_gpio(GPIO36_GPIO)
+
+/*
+ * Asix AX88796 Ethernet
+ */
+static struct ax_plat_data colibri_asix_platdata = {
+        .flags          = AXFLG_MAC_FROMDEV,
+        .wordlength     = 2
+};
+
+static struct resource colibri_asix_resource[] = {
+        [0] = {
+                .start = PXA3xx_CS2_PHYS,
+                .end   = PXA3xx_CS2_PHYS + (0x20 * 2) - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO),
+                .end   = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO),
+                .flags = IORESOURCE_IRQ
+        }
+};
+
+static struct platform_device asix_device = {
+        .name           = "ax88796",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(colibri_asix_resource),
+        .resource       = colibri_asix_resource,
+        .dev            = {
+                .platform_data = &colibri_asix_platdata
+        }
+};
+
+static mfp_cfg_t colibri_pxa320_eth_pin_config[] __initdata = {
+        GPIO3_nCS2,                     /* AX88796 chip select */
+        GPIO36_GPIO | MFP_PULL_HIGH     /* AX88796 IRQ */
+};
+
+static void __init colibri_pxa320_init_eth(void)
+{
+        pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_eth_pin_config));
+        set_irq_type(gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), IRQ_TYPE_EDGE_FALLING);
+        platform_device_register(&asix_device);
+}
+#else
+static inline void __init colibri_pxa320_init_eth(void) {}
+#endif /* CONFIG_AX88796 */
+
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static mfp_cfg_t colibri_pxa320_usb_pin_config[] __initdata = {
+        GPIO2_2_USBH_PEN,
+        GPIO3_2_USBH_PWR,
+};
+
+static struct pxaohci_platform_data colibri_pxa320_ohci_info = {
+        .port_mode      = PMM_GLOBAL_MODE,
+        .flags          = ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW,
+};
+
+void __init colibri_pxa320_init_ohci(void)
+{
+        pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_usb_pin_config));
+        pxa_set_ohci_info(&colibri_pxa320_ohci_info);
+}
+#else
+static inline void colibri_pxa320_init_ohci(void) {}
+#endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */
+
+static mfp_cfg_t colibri_pxa320_mmc_pin_config[] __initdata = {
+        GPIO22_MMC1_CLK,
+        GPIO23_MMC1_CMD,
+        GPIO18_MMC1_DAT0,
+        GPIO19_MMC1_DAT1,
+        GPIO20_MMC1_DAT2,
+        GPIO21_MMC1_DAT3
+};
+
+#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
+static mfp_cfg_t colibri_pxa320_lcd_pin_config[] __initdata = {
+        GPIO6_2_LCD_LDD_0,
+        GPIO7_2_LCD_LDD_1,
+        GPIO8_2_LCD_LDD_2,
+        GPIO9_2_LCD_LDD_3,
+        GPIO10_2_LCD_LDD_4,
+        GPIO11_2_LCD_LDD_5,
+        GPIO12_2_LCD_LDD_6,
+        GPIO13_2_LCD_LDD_7,
+        GPIO63_LCD_LDD_8,
+        GPIO64_LCD_LDD_9,
+        GPIO65_LCD_LDD_10,
+        GPIO66_LCD_LDD_11,
+        GPIO67_LCD_LDD_12,
+        GPIO68_LCD_LDD_13,
+        GPIO69_LCD_LDD_14,
+        GPIO70_LCD_LDD_15,
+        GPIO71_LCD_LDD_16,
+        GPIO72_LCD_LDD_17,
+        GPIO73_LCD_CS_N,
+        GPIO74_LCD_VSYNC,
+        GPIO14_2_LCD_FCLK,
+        GPIO15_2_LCD_LCLK,
+        GPIO16_2_LCD_PCLK,
+        GPIO17_2_LCD_BIAS,
+};
+
+static void __init colibri_pxa320_init_lcd(void)
+{
+        pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_lcd_pin_config));
+}
+#else
+static inline void colibri_pxa320_init_lcd(void) {}
+#endif
+
+#if defined(SND_AC97_CODEC) || defined(SND_AC97_CODEC_MODULE)
+static mfp_cfg_t colibri_pxa320_ac97_pin_config[] __initdata = {
+        GPIO34_AC97_SYSCLK,
+        GPIO35_AC97_SDATA_IN_0,
+        GPIO37_AC97_SDATA_OUT,
+        GPIO38_AC97_SYNC,
+        GPIO39_AC97_BITCLK,
+        GPIO40_AC97_nACRESET
+};
+
+static inline void __init colibri_pxa320_init_ac97(void)
+{
+        pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_ac97_pin_config));
+        pxa_set_ac97_info(NULL);
+}
+#else
+static inline void colibri_pxa320_init_ac97(void) {}
+#endif
+
+void __init colibri_pxa320_init(void)
+{
+        colibri_pxa320_init_eth();
+        colibri_pxa320_init_ohci();
+        colibri_pxa320_init_lcd();
+        colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO49_GPIO));
+        colibri_pxa320_init_ac97();
+        colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa320_mmc_pin_config),
+                                mfp_to_gpio(MFP_PIN_GPIO28));
+}
+
+MACHINE_START(COLIBRI320, "Toradex Colibri PXA320")
+        .phys_io        = 0x40000000,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .boot_params    = COLIBRI_SDRAM_BASE + 0x100,
+        .init_machine   = colibri_pxa320_init,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa3xx_init_irq,
+        .timer          = &pxa_timer,
+MACHINE_END
+
diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c
new file mode 100644
index 000000000000..12d0afc54aa5
--- /dev/null
+++ b/arch/arm/mach-pxa/colibri-pxa3xx.c
@@ -0,0 +1,121 @@
+/*
+ *  arch/arm/mach-pxa/colibri-pxa3xx.c
+ *
+ *  Common functions for all Toradex PXA3xx modules
+ *
+ *  Daniel Mack <daniel@caiaq.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+#include <asm/sizes.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <mach/pxa3xx-regs.h>
+#include <mach/mfp-pxa300.h>
+#include <mach/colibri.h>
+#include <mach/mmc.h>
+#include <mach/pxafb.h>
+
+#include "generic.h"
+#include "devices.h"
+
+#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
+static int mmc_detect_pin;
+
+static int colibri_pxa3xx_mci_init(struct device *dev,
+                                   irq_handler_t colibri_mmc_detect_int,
+                                   void *data)
+{
+        int ret;
+
+        ret = gpio_request(mmc_detect_pin, "mmc card detect");
+        if (ret)
+                return ret;
+
+        gpio_direction_input(mmc_detect_pin);
+        ret = request_irq(gpio_to_irq(mmc_detect_pin), colibri_mmc_detect_int,
+                          IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+                          "MMC card detect", data);
+        if (ret) {
+                gpio_free(mmc_detect_pin);
+                return ret;
+        }
+
+        return 0;
+}
+
+static void colibri_pxa3xx_mci_exit(struct device *dev, void *data)
+{
+        free_irq(mmc_detect_pin, data);
+        gpio_free(gpio_to_irq(mmc_detect_pin));
+}
+
+static struct pxamci_platform_data colibri_pxa3xx_mci_platform_data = {
+        .detect_delay   = 20,
+        .ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34,
+        .init           = colibri_pxa3xx_mci_init,
+        .exit           = colibri_pxa3xx_mci_exit,
+};
+
+void __init colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin)
+{
+        pxa3xx_mfp_config(pins, len);
+        mmc_detect_pin = detect_pin;
+        pxa_set_mci_info(&colibri_pxa3xx_mci_platform_data);
+}
+#endif /* CONFIG_MMC_PXA || CONFIG_MMC_PXA_MODULE */
+
+#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
+static int lcd_bl_pin;
+
+/*
+ * LCD panel (Sharp LQ043T3DX02)
+ */
+static void colibri_lcd_backlight(int on)
+{
+        gpio_set_value(lcd_bl_pin, !!on);
+}
+
+static struct pxafb_mode_info sharp_lq43_mode = {
+        .pixclock       = 101936,
+        .xres           = 480,
+        .yres           = 272,
+        .bpp            = 32,
+        .depth          = 18,
+        .hsync_len      = 41,
+        .left_margin    = 2,
+        .right_margin   = 2,
+        .vsync_len      = 10,
+        .upper_margin   = 2,
+        .lower_margin   = 2,
+        .sync           = 0,
+        .cmap_greyscale = 0,
+};
+
+static struct pxafb_mach_info sharp_lq43_info = {
+        .modes          = &sharp_lq43_mode,
+        .num_modes      = 1,
+        .cmap_inverse   = 0,
+        .cmap_static    = 0,
+        .lcd_conn       = LCD_COLOR_TFT_18BPP,
+        .pxafb_backlight_power = colibri_lcd_backlight,
+};
+
+void __init colibri_pxa3xx_init_lcd(int bl_pin)
+{
+        lcd_bl_pin = bl_pin;
+        gpio_request(bl_pin, "lcd backlight");
+        gpio_direction_output(bl_pin, 0);
+        set_pxa_fb_info(&sharp_lq43_info);
+}
+#endif
+
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index a8d91b6c136b..cdf21dd135b4 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -41,9 +41,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/pxa-regs.h>
-#include <mach/pxa2xx-regs.h>
-#include <mach/mfp-pxa25x.h>
+#include <mach/pxa25x.h>
 #include <mach/i2c.h>
 #include <mach/irda.h>
 #include <mach/mmc.h>
@@ -637,16 +635,16 @@ static void corgi_poweroff(void)
                 /* Green LED off tells the bootloader to halt */
                 gpio_set_value(CORGI_GPIO_LED_GREEN, 0);
 
-        arm_machine_restart('h');
+        arm_machine_restart('h', NULL);
 }
 
-static void corgi_restart(char mode)
+static void corgi_restart(char mode, const char *cmd)
 {
         if (!machine_is_corgi())
                 /* Green LED on tells the bootloader to reboot */
                 gpio_set_value(CORGI_GPIO_LED_GREEN, 1);
 
-        arm_machine_restart('h');
+        arm_machine_restart('h', cmd);
 }
 
 static void __init corgi_init(void)
diff --git a/arch/arm/mach-pxa/corgi_lcd.c b/arch/arm/mach-pxa/corgi_lcd.c
index 411607bc1fc2..d9b96319d498 100644
--- a/arch/arm/mach-pxa/corgi_lcd.c
+++ b/arch/arm/mach-pxa/corgi_lcd.c
@@ -22,7 +22,6 @@
 #include <linux/string.h>
 #include <mach/corgi.h>
 #include <mach/hardware.h>
-#include <mach/pxa-regs.h>
 #include <mach/sharpsl.h>
 #include <mach/spitz.h>
 #include <asm/hardware/scoop.h>
diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c
index e35259032813..7f04b3a761d1 100644
--- a/arch/arm/mach-pxa/corgi_pm.c
+++ b/arch/arm/mach-pxa/corgi_pm.c
@@ -24,7 +24,6 @@
 
 #include <mach/sharpsl.h>
 #include <mach/corgi.h>
-#include <mach/pxa-regs.h>
 #include <mach/pxa2xx-regs.h>
 #include <mach/pxa2xx-gpio.h>
 #include "sharpsl.h"
diff --git a/arch/arm/mach-pxa/corgi_ssp.c b/arch/arm/mach-pxa/corgi_ssp.c
index 8e2f2215c4ba..a5ee70735e04 100644
--- a/arch/arm/mach-pxa/corgi_ssp.c
+++ b/arch/arm/mach-pxa/corgi_ssp.c
@@ -20,7 +20,6 @@
 #include <asm/mach-types.h>
 
 #include <mach/ssp.h>
-#include <mach/pxa-regs.h>
 #include <mach/pxa2xx-gpio.h>
 #include <mach/regs-ssp.h>
 #include "sharpsl.h"
diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
index 771dd4eac935..083a1d851d49 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
@@ -37,8 +37,6 @@
 #include <linux/init.h>
 #include <linux/cpufreq.h>
 
-#include <mach/hardware.h>
-#include <mach/pxa-regs.h>
 #include <mach/pxa2xx-regs.h>
 
 #ifdef DEBUG
diff --git a/arch/arm/mach-pxa/cpufreq-pxa3xx.c b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
index 968c8309ec37..67f34a8d8e60 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa3xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
@@ -15,8 +15,6 @@
 #include <linux/init.h>
 #include <linux/cpufreq.h>
 
-#include <mach/hardware.h>
-#include <mach/pxa-regs.h>
 #include <mach/pxa3xx-regs.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/csb701.c b/arch/arm/mach-pxa/csb701.c
new file mode 100644
index 000000000000..4a2a2952c374
--- /dev/null
+++ b/arch/arm/mach-pxa/csb701.c
@@ -0,0 +1,61 @@
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/leds.h>
+
+static struct gpio_keys_button csb701_buttons[] = {
+        {
+                .code   = 0x7,
+                .gpio   = 1,
+                .active_low = 1,
+                .desc   = "SW2",
+                .type   = EV_SW,
+                .wakeup = 1,
+        },
+};
+
+static struct gpio_keys_platform_data csb701_gpio_keys_data = {
+        .buttons = csb701_buttons,
+        .nbuttons = ARRAY_SIZE(csb701_buttons),
+};
+
+static struct gpio_led csb701_leds[] = {
+        {
+                .name   = "csb701:yellow:heartbeat",
+                .default_trigger = "heartbeat",
+                .gpio   = 11,
+                .active_low = 1,
+        },
+};
+
+static struct platform_device csb701_gpio_keys = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev.platform_data = &csb701_gpio_keys_data,
+};
+
+static struct gpio_led_platform_data csb701_leds_gpio_data = {
+        .leds           = csb701_leds,
+        .num_leds       = ARRAY_SIZE(csb701_leds),
+};
+
+static struct platform_device csb701_leds_gpio = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev.platform_data = &csb701_leds_gpio_data,
+};
+
+static struct platform_device *devices[] __initdata = {
+        &csb701_gpio_keys,
+        &csb701_leds_gpio,
+};
+
+static int __init csb701_init(void)
+{
+        return platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+module_init(csb701_init);
+
diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c
new file mode 100644
index 000000000000..2b289f83a61a
--- /dev/null
+++ b/arch/arm/mach-pxa/csb726.c
@@ -0,0 +1,318 @@
+/*
+ *  Support for Cogent CSB726
+ *
+ *  Copyright (c) 2008 Dmitry Eremin-Solenikov
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/partitions.h>
+#include <linux/sm501.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/csb726.h>
+#include <mach/mfp-pxa27x.h>
+#include <mach/i2c.h>
+#include <mach/mmc.h>
+#include <mach/ohci.h>
+#include <mach/pxa2xx-regs.h>
+
+#include "generic.h"
+#include "devices.h"
+
+/*
+ * n/a: 2, 5, 6, 7, 8, 23, 24, 25, 26, 27, 87, 88, 89,
+ * nu: 58 -- 77, 90, 91, 93, 102, 105-108, 114-116,
+ * XXX: 21,
+ * XXX: 79 CS_3 for LAN9215 or PSKTSEL on R2, R3
+ * XXX: 33 CS_5 for LAN9215 on R1
+ */
+
+static unsigned long csb726_pin_config[] = {
+        GPIO78_nCS_2, /* EXP_CS */
+        GPIO79_nCS_3, /* SMSC9215 */
+        GPIO80_nCS_4, /* SM501 */
+
+        GPIO52_GPIO, /* #SMSC9251 int */
+        GPIO53_GPIO, /* SM501 int */
+
+        GPIO1_GPIO, /* GPIO0 */
+        GPIO11_GPIO, /* GPIO1 */
+        GPIO9_GPIO, /* GPIO2 */
+        GPIO10_GPIO, /* GPIO3 */
+        GPIO16_PWM0_OUT, /* or GPIO4 */
+        GPIO17_PWM1_OUT, /* or GPIO5 */
+        GPIO94_GPIO, /* GPIO6 */
+        GPIO95_GPIO, /* GPIO7 */
+        GPIO96_GPIO, /* GPIO8 */
+        GPIO97_GPIO, /* GPIO9 */
+        GPIO15_GPIO, /* EXP_IRQ */
+        GPIO18_RDY, /* EXP_WAIT */
+
+        GPIO0_GPIO, /* PWR_INT */
+        GPIO104_GPIO, /* PWR_OFF */
+
+        GPIO12_GPIO, /* touch irq */
+
+        GPIO13_SSP2_TXD,
+        GPIO14_SSP2_SFRM,
+        MFP_CFG_OUT(GPIO19, AF1, DRIVE_LOW),/* SSP2_SYSCLK */
+        GPIO22_SSP2_SCLK,
+
+        GPIO81_SSP3_TXD,
+        GPIO82_SSP3_RXD,
+        GPIO83_SSP3_SFRM,
+        GPIO84_SSP3_SCLK,
+
+        GPIO20_GPIO, /* SDIO int */
+        GPIO32_MMC_CLK,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+        GPIO112_MMC_CMD,
+        GPIO100_GPIO, /* SD CD */
+        GPIO101_GPIO, /* SD WP */
+
+        GPIO28_AC97_BITCLK,
+        GPIO29_AC97_SDATA_IN_0,
+        GPIO30_AC97_SDATA_OUT,
+        GPIO31_AC97_SYNC,
+        GPIO113_AC97_nRESET,
+
+        GPIO34_FFUART_RXD,
+        GPIO35_FFUART_CTS,
+        GPIO36_FFUART_DCD,
+        GPIO37_FFUART_DSR,
+        GPIO38_FFUART_RI,
+        GPIO39_FFUART_TXD,
+        GPIO40_FFUART_DTR,
+        GPIO41_FFUART_RTS,
+
+        GPIO42_BTUART_RXD,
+        GPIO43_BTUART_TXD,
+        GPIO44_BTUART_CTS,
+        GPIO45_BTUART_RTS,
+
+        GPIO46_STUART_RXD,
+        GPIO47_STUART_TXD,
+
+        GPIO48_nPOE,
+        GPIO49_nPWE,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO54_nPCE_2,
+        GPIO55_nPREG,
+        GPIO56_nPWAIT,
+        GPIO57_nIOIS16, /* maybe unused */
+        GPIO85_nPCE_1,
+        GPIO98_GPIO, /* CF IRQ */
+        GPIO99_GPIO, /* CF CD */
+        GPIO103_GPIO, /* Reset */
+
+        GPIO117_I2C_SCL,
+        GPIO118_I2C_SDA,
+};
+
+static struct pxamci_platform_data csb726_mci_data;
+
+static int csb726_mci_init(struct device *dev,
+                irq_handler_t detect, void *data)
+{
+        int err;
+
+        csb726_mci_data.detect_delay = msecs_to_jiffies(500);
+
+        err = gpio_request(CSB726_GPIO_MMC_DETECT, "MMC detect");
+        if (err)
+                goto err_det_req;
+
+        err = gpio_direction_input(CSB726_GPIO_MMC_DETECT);
+        if (err)
+                goto err_det_dir;
+
+        err = gpio_request(CSB726_GPIO_MMC_RO, "MMC ro");
+        if (err)
+                goto err_ro_req;
+
+        err = gpio_direction_input(CSB726_GPIO_MMC_RO);
+        if (err)
+                goto err_ro_dir;
+
+        err = request_irq(gpio_to_irq(CSB726_GPIO_MMC_DETECT), detect,
+                        IRQF_DISABLED, "MMC card detect", data);
+        if (err)
+                goto err_irq;
+
+        return 0;
+
+err_irq:
+err_ro_dir:
+        gpio_free(CSB726_GPIO_MMC_RO);
+err_ro_req:
+err_det_dir:
+        gpio_free(CSB726_GPIO_MMC_DETECT);
+err_det_req:
+        return err;
+}
+
+static int csb726_mci_get_ro(struct device *dev)
+{
+        return gpio_get_value(CSB726_GPIO_MMC_RO);
+}
+
+static void csb726_mci_exit(struct device *dev, void *data)
+{
+        free_irq(gpio_to_irq(CSB726_GPIO_MMC_DETECT), data);
+        gpio_free(CSB726_GPIO_MMC_RO);
+        gpio_free(CSB726_GPIO_MMC_DETECT);
+}
+
+static struct pxamci_platform_data csb726_mci = {
+        .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
+        .init           = csb726_mci_init,
+        .get_ro         = csb726_mci_get_ro,
+        /* FIXME setpower */
+        .exit           = csb726_mci_exit,
+};
+
+static struct pxaohci_platform_data csb726_ohci_platform_data = {
+        .port_mode      = PMM_NPS_MODE,
+        .flags          = ENABLE_PORT1 | NO_OC_PROTECTION,
+};
+
+static struct mtd_partition csb726_flash_partitions[] = {
+        {
+                .name           = "Bootloader",
+                .offset         = 0,
+                .size           = CSB726_FLASH_uMON,
+                .mask_flags     = MTD_WRITEABLE  /* force read-only */
+        },
+        {
+                .name           = "root",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+        }
+};
+
+static struct physmap_flash_data csb726_flash_data = {
+        .width          = 2,
+        .parts          = csb726_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(csb726_flash_partitions),
+};
+
+static struct resource csb726_flash_resources[] = {
+        {
+                .start          = PXA_CS0_PHYS,
+                .end            = PXA_CS0_PHYS + CSB726_FLASH_SIZE - 1 ,
+                .flags          = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device csb726_flash = {
+        .name           = "physmap-flash",
+        .dev            = {
+                .platform_data  = &csb726_flash_data,
+        },
+        .resource       = csb726_flash_resources,
+        .num_resources  = ARRAY_SIZE(csb726_flash_resources),
+};
+
+static struct resource csb726_sm501_resources[] = {
+        {
+                .start          = PXA_CS4_PHYS,
+                .end            = PXA_CS4_PHYS + SZ_8M - 1,
+                .flags          = IORESOURCE_MEM,
+                .name           = "sm501-localmem",
+        },
+        {
+                .start          = PXA_CS4_PHYS + SZ_64M - SZ_2M,
+                .end            = PXA_CS4_PHYS + SZ_64M - 1,
+                .flags          = IORESOURCE_MEM,
+                .name           = "sm501-regs",
+        },
+        {
+                .start          = CSB726_IRQ_SM501,
+                .end            = CSB726_IRQ_SM501,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct sm501_initdata csb726_sm501_initdata = {
+/*      .devices        = SM501_USE_USB_HOST, */
+        .devices        = SM501_USE_USB_HOST | SM501_USE_UART0 | SM501_USE_UART1,
+};
+
+static struct sm501_platdata csb726_sm501_platdata = {
+        .init           = &csb726_sm501_initdata,
+};
+
+static struct platform_device csb726_sm501 = {
+        .name           = "sm501",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(csb726_sm501_resources),
+        .resource       = csb726_sm501_resources,
+        .dev            = {
+                .platform_data = &csb726_sm501_platdata,
+        },
+};
+
+static struct resource csb726_lan_resources[] = {
+        {
+                .start  = PXA_CS3_PHYS,
+                .end    = PXA_CS3_PHYS + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = CSB726_IRQ_LAN,
+                .end    = CSB726_IRQ_LAN,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device csb726_lan = {
+        .name           = "smc911x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(csb726_lan_resources),
+        .resource       = csb726_lan_resources,
+};
+
+static struct platform_device *devices[] __initdata = {
+        &csb726_flash,
+        &csb726_sm501,
+        &csb726_lan,
+};
+
+static void __init csb726_init(void)
+{
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(csb726_pin_config));
+/*      MSC1 = 0x7ffc3ffc; *//* LAN9215/EXP_CS */
+/*      MSC2 = 0x06697ff4; *//* none/SM501 */
+        MSC2 = (MSC2 & ~0xffff) | 0x7ff4; /* SM501 */
+
+        pxa_set_i2c_info(NULL);
+        pxa27x_set_i2c_power_info(NULL);
+        pxa_set_mci_info(&csb726_mci);
+        pxa_set_ohci_info(&csb726_ohci_platform_data);
+
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+MACHINE_START(CSB726, "Cogent CSB726")
+        .phys_io        = 0x40000000,
+        .boot_params    = 0xa0000100,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa27x_init_irq,
+        .init_machine   = csb726_init,
+        .timer          = &pxa_timer,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index e16f8e3d58d3..d245e59c51b1 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -4,7 +4,6 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 
-#include <mach/pxa-regs.h>
 #include <mach/udc.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
diff --git a/arch/arm/mach-pxa/e330.c b/arch/arm/mach-pxa/e330.c
index 1bd7f740427c..74d3f8987c5c 100644
--- a/arch/arm/mach-pxa/e330.c
+++ b/arch/arm/mach-pxa/e330.c
@@ -20,9 +20,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
-#include <mach/mfp-pxa25x.h>
-#include <mach/hardware.h>
-#include <mach/pxa-regs.h>
+#include <mach/pxa25x.h>
 #include <mach/eseries-gpio.h>
 #include <mach/udc.h>
 
diff --git a/arch/arm/mach-pxa/e350.c b/arch/arm/mach-pxa/e350.c
index edcd9d5ce545..080036272131 100644
--- a/arch/arm/mach-pxa/e350.c
+++ b/arch/arm/mach-pxa/e350.c
@@ -21,9 +21,7 @@
 #include <asm/mach-types.h>
 
 #include <mach/irqs.h>
-#include <mach/mfp-pxa25x.h>
-#include <mach/pxa-regs.h>
-#include <mach/hardware.h>
+#include <mach/pxa25x.h>
 #include <mach/eseries-gpio.h>
 #include <mach/udc.h>
 
diff --git a/arch/arm/mach-pxa/e400.c b/arch/arm/mach-pxa/e400.c
index 77bb8e2c48c0..ed9c0c3f64a2 100644
--- a/arch/arm/mach-pxa/e400.c
+++ b/arch/arm/mach-pxa/e400.c
@@ -22,9 +22,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
-#include <mach/mfp-pxa25x.h>
-#include <mach/pxa-regs.h>
-#include <mach/hardware.h>
+#include <mach/pxa25x.h>
 #include <mach/eseries-gpio.h>
 #include <mach/pxafb.h>
 #include <mach/udc.h>
diff --git a/arch/arm/mach-pxa/e740.c b/arch/arm/mach-pxa/e740.c
index a6fff782e7a8..07500a04fd8c 100644
--- a/arch/arm/mach-pxa/e740.c
+++ b/arch/arm/mach-pxa/e740.c
@@ -24,9 +24,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
-#include <mach/mfp-pxa25x.h>
-#include <mach/pxa-regs.h>
-#include <mach/hardware.h>
+#include <mach/pxa25x.h>
 #include <mach/eseries-gpio.h>
 #include <mach/udc.h>
 #include <mach/irda.h>
@@ -194,7 +192,7 @@ static void __init e740_init(void)
 {
         pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config));
         eseries_register_clks();
-        clk_add_alias("CLK_CK48M", &e740_t7l66xb_device.dev,
+        clk_add_alias("CLK_CK48M", e740_t7l66xb_device.name,
                         "UDCCLK", &pxa25x_device_udc.dev),
         eseries_get_tmio_gpios();
         platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-pxa/e750.c b/arch/arm/mach-pxa/e750.c
index 665066fd280e..6126c04e02bc 100644
--- a/arch/arm/mach-pxa/e750.c
+++ b/arch/arm/mach-pxa/e750.c
@@ -23,9 +23,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
-#include <mach/mfp-pxa25x.h>
-#include <mach/pxa-regs.h>
-#include <mach/hardware.h>
+#include <mach/pxa25x.h>
 #include <mach/eseries-gpio.h>
 #include <mach/udc.h>
 #include <mach/irda.h>
@@ -195,7 +193,7 @@ static struct platform_device *devices[] __initdata = {
 static void __init e750_init(void)
 {
         pxa2xx_mfp_config(ARRAY_AND_SIZE(e750_pin_config));
-        clk_add_alias("CLK_CK3P6MI", &e750_tc6393xb_device.dev,
+        clk_add_alias("CLK_CK3P6MI", e750_tc6393xb_device.name,
                         "GPIO11_CLK", NULL),
         eseries_get_tmio_gpios();
         platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-pxa/e800.c b/arch/arm/mach-pxa/e800.c
index cc9b1293e866..74ab09812a72 100644
--- a/arch/arm/mach-pxa/e800.c
+++ b/arch/arm/mach-pxa/e800.c
@@ -23,9 +23,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
-#include <mach/mfp-pxa25x.h>
-#include <mach/pxa-regs.h>
-#include <mach/hardware.h>
+#include <mach/pxa25x.h>
 #include <mach/eseries-gpio.h>
 #include <mach/udc.h>
 #include <mach/irqs.h>
@@ -196,7 +194,7 @@ static struct platform_device *devices[] __initdata = {
 
 static void __init e800_init(void)
 {
-        clk_add_alias("CLK_CK3P6MI", &e800_tc6393xb_device.dev,
+        clk_add_alias("CLK_CK3P6MI", e800_tc6393xb_device.name,
                         "GPIO11_CLK", NULL),
         eseries_get_tmio_gpios();
         platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index f5ed8038ede5..920dfb8d36da 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -11,40 +11,63 @@
 
 #include <linux/irq.h>
 #include <linux/platform_device.h>
+#include <linux/delay.h>
 
 #include <linux/dm9000.h>
 #include <linux/rtc-v3020.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
 #include <linux/gpio.h>
+#include <linux/mfd/da903x.h>
+#include <linux/regulator/machine.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/tdo24m.h>
+#include <linux/power_supply.h>
+#include <linux/apm-emulation.h>
+
+#include <media/soc_camera.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/mfp-pxa27x.h>
-#include <mach/pxa-regs.h>
+#include <mach/pxa27x.h>
 #include <mach/pxa27x-udc.h>
 #include <mach/audio.h>
 #include <mach/pxafb.h>
 #include <mach/ohci.h>
 #include <mach/mmc.h>
 #include <mach/pxa27x_keypad.h>
+#include <mach/i2c.h>
+#include <mach/camera.h>
+#include <mach/pxa2xx_spi.h>
 
 #include "generic.h"
+#include "devices.h"
 
-/* GPIO IRQ usage */
-#define GPIO41_ETHIRQ           (41)
+/* EM-X270 specific GPIOs */
 #define GPIO13_MMC_CD           (13)
+#define GPIO95_MMC_WP           (95)
+#define GPIO56_NAND_RB          (56)
+
+/* eXeda specific GPIOs */
+#define GPIO114_MMC_CD          (114)
+#define GPIO20_NAND_RB          (20)
+#define GPIO38_SD_PWEN          (38)
+
+/* common  GPIOs */
+#define GPIO11_NAND_CS          (11)
+#define GPIO93_CAM_RESET        (93)
+#define GPIO41_ETHIRQ           (41)
 #define EM_X270_ETHIRQ          IRQ_GPIO(GPIO41_ETHIRQ)
-#define EM_X270_MMC_CD          IRQ_GPIO(GPIO13_MMC_CD)
 
-/* NAND control GPIOs */
-#define GPIO11_NAND_CS  (11)
-#define GPIO56_NAND_RB  (56)
+static int mmc_cd;
+static int nand_rb;
+static int dm9000_flags;
 
-static unsigned long em_x270_pin_config[] = {
+static unsigned long common_pin_config[] = {
         /* AC'97 */
         GPIO28_AC97_BITCLK,
         GPIO29_AC97_SDATA_IN_0,
@@ -150,21 +173,32 @@ static unsigned long em_x270_pin_config[] = {
         GPIO18_RDY,
 
         /* GPIO */
-        GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
+        GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,       /* sleep/resume button */
 
         /* power controls */
         GPIO20_GPIO     | MFP_LPM_DRIVE_LOW,    /* GPRS_PWEN */
+        GPIO93_GPIO     | MFP_LPM_DRIVE_LOW,    /* Camera reset */
         GPIO115_GPIO    | MFP_LPM_DRIVE_LOW,    /* WLAN_PWEN */
 
         /* NAND controls */
         GPIO11_GPIO     | MFP_LPM_DRIVE_HIGH,   /* NAND CE# */
-        GPIO56_GPIO,                            /* NAND Ready/Busy */
 
         /* interrupts */
-        GPIO13_GPIO,    /* MMC card detect */
         GPIO41_GPIO,    /* DM9000 interrupt */
 };
 
+static unsigned long em_x270_pin_config[] = {
+        GPIO13_GPIO,    /* MMC card detect */
+        GPIO56_GPIO,    /* NAND Ready/Busy */
+        GPIO95_GPIO,    /* MMC Write protect */
+};
+
+static unsigned long exeda_pin_config[] = {
+        GPIO20_GPIO,                            /* NAND Ready/Busy */
+        GPIO38_GPIO     | MFP_LPM_DRIVE_LOW,    /* SD slot power */
+        GPIO114_GPIO,                           /* MMC card detect */
+};
+
 #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
 static struct resource em_x270_dm9000_resource[] = {
         [0] = {
@@ -185,7 +219,7 @@ static struct resource em_x270_dm9000_resource[] = {
 };
 
 static struct dm9000_plat_data em_x270_dm9000_platdata = {
-        .flags          = DM9000_PLATF_32BITONLY,
+        .flags          = DM9000_PLATF_NO_EEPROM,
 };
 
 static struct platform_device em_x270_dm9000 = {
@@ -200,6 +234,7 @@ static struct platform_device em_x270_dm9000 = {
 
 static void __init em_x270_init_dm9000(void)
 {
+        em_x270_dm9000_platdata.flags |= dm9000_flags;
         platform_device_register(&em_x270_dm9000);
 }
 #else
@@ -289,7 +324,7 @@ static int em_x270_nand_device_ready(struct mtd_info *mtd)
 {
         dsb();
 
-        return gpio_get_value(GPIO56_NAND_RB);
+        return gpio_get_value(nand_rb);
 }
 
 static struct mtd_partition em_x270_partition_info[] = {
@@ -354,14 +389,14 @@ static void __init em_x270_init_nand(void)
 
         gpio_direction_output(GPIO11_NAND_CS, 1);
 
-        err = gpio_request(GPIO56_NAND_RB, "NAND R/B");
+        err = gpio_request(nand_rb, "NAND R/B");
         if (err) {
                 pr_warning("EM-X270: failed to request NAND R/B gpio\n");
                 gpio_free(GPIO11_NAND_CS);
                 return;
         }
 
-        gpio_direction_input(GPIO56_NAND_RB);
+        gpio_direction_input(nand_rb);
 
         platform_device_register(&em_x270_nand);
 }
@@ -369,6 +404,61 @@ static void __init em_x270_init_nand(void)
 static inline void em_x270_init_nand(void) {}
 #endif
 
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+static struct mtd_partition em_x270_nor_parts[] = {
+        {
+                .name =         "Bootloader",
+                .offset =       0x00000000,
+                .size =         0x00050000,
+                .mask_flags =   MTD_WRITEABLE  /* force read-only */
+        }, {
+                .name =         "Environment",
+                .offset =       0x00050000,
+                .size =         0x00010000,
+        }, {
+                .name =         "Reserved",
+                .offset =       0x00060000,
+                .size =         0x00050000,
+                .mask_flags =   MTD_WRITEABLE  /* force read-only */
+        }, {
+                .name =         "Splashscreen",
+                .offset =       0x000b0000,
+                .size =         0x00050000,
+        }
+};
+
+static struct physmap_flash_data em_x270_nor_data[] = {
+        [0] = {
+                .width = 2,
+                .parts = em_x270_nor_parts,
+                .nr_parts = ARRAY_SIZE(em_x270_nor_parts),
+        },
+};
+
+static struct resource em_x270_nor_flash_resource = {
+        .start  = PXA_CS0_PHYS,
+        .end    = PXA_CS0_PHYS + SZ_1M - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct platform_device em_x270_physmap_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = &em_x270_nor_flash_resource,
+        .dev            = {
+                .platform_data  = &em_x270_nor_data,
+        },
+};
+
+static void __init em_x270_init_nor(void)
+{
+        platform_device_register(&em_x270_physmap_flash);
+}
+#else
+static inline void em_x270_init_nor(void) {}
+#endif
+
 /* PXA27x OHCI controller setup */
 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
 static int em_x270_ohci_init(struct device *dev)
@@ -395,40 +485,93 @@ static inline void em_x270_init_ohci(void) {}
 
 /* MCI controller setup */
 #if defined(CONFIG_MMC) || defined(CONFIG_MMC_MODULE)
+static struct regulator *em_x270_sdio_ldo;
+
 static int em_x270_mci_init(struct device *dev,
                             irq_handler_t em_x270_detect_int,
                             void *data)
 {
-        int err = request_irq(EM_X270_MMC_CD, em_x270_detect_int,
-                              IRQF_DISABLED | IRQF_TRIGGER_FALLING,
+        int err;
+
+        em_x270_sdio_ldo = regulator_get(dev, "vcc sdio");
+        if (IS_ERR(em_x270_sdio_ldo)) {
+                dev_err(dev, "can't request SDIO power supply: %ld\n",
+                        PTR_ERR(em_x270_sdio_ldo));
+                return PTR_ERR(em_x270_sdio_ldo);
+        }
+
+        err = request_irq(gpio_to_irq(mmc_cd), em_x270_detect_int,
+                              IRQF_DISABLED | IRQF_TRIGGER_RISING |
+                              IRQF_TRIGGER_FALLING,
                               "MMC card detect", data);
         if (err) {
-                printk(KERN_ERR "%s: can't request MMC card detect IRQ: %d\n",
-                       __func__, err);
-                return err;
+                dev_err(dev, "can't request MMC card detect IRQ: %d\n", err);
+                goto err_irq;
+        }
+
+        if (machine_is_em_x270()) {
+                err = gpio_request(GPIO95_MMC_WP, "MMC WP");
+                if (err) {
+                        dev_err(dev, "can't request MMC write protect: %d\n",
+                                err);
+                        goto err_gpio_wp;
+                }
+                gpio_direction_input(GPIO95_MMC_WP);
+        } else {
+                err = gpio_request(GPIO38_SD_PWEN, "sdio power");
+                if (err) {
+                        dev_err(dev, "can't request MMC power control : %d\n",
+                                err);
+                        goto err_gpio_wp;
+                }
+                gpio_direction_output(GPIO38_SD_PWEN, 1);
         }
 
         return 0;
+
+err_gpio_wp:
+        free_irq(gpio_to_irq(mmc_cd), data);
+err_irq:
+        regulator_put(em_x270_sdio_ldo);
+
+        return err;
 }
 
 static void em_x270_mci_setpower(struct device *dev, unsigned int vdd)
 {
-        /*
-           FIXME: current hardware implementation does not allow to
-           enable/disable MMC power. This will be fixed in next HW releases,
-           and we'll need to add implmentation here.
-        */
-        return;
+        struct pxamci_platform_data* p_d = dev->platform_data;
+
+        if ((1 << vdd) & p_d->ocr_mask) {
+                int vdd_uV = (2000 + (vdd - __ffs(MMC_VDD_20_21)) * 100) * 1000;
+
+                regulator_set_voltage(em_x270_sdio_ldo, vdd_uV, vdd_uV);
+                regulator_enable(em_x270_sdio_ldo);
+        } else {
+                regulator_disable(em_x270_sdio_ldo);
+        }
 }
 
 static void em_x270_mci_exit(struct device *dev, void *data)
 {
-        int irq = gpio_to_irq(GPIO13_MMC_CD);
-        free_irq(irq, data);
+        free_irq(gpio_to_irq(mmc_cd), data);
+        regulator_put(em_x270_sdio_ldo);
+
+        if (machine_is_em_x270())
+                gpio_free(GPIO95_MMC_WP);
+        else
+                gpio_free(GPIO38_SD_PWEN);
+}
+
+static int em_x270_mci_get_ro(struct device *dev)
+{
+        return gpio_get_value(GPIO95_MMC_WP);
 }
 
 static struct pxamci_platform_data em_x270_mci_platform_data = {
-        .ocr_mask       = MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31,
+        .ocr_mask       = MMC_VDD_20_21|MMC_VDD_21_22|MMC_VDD_22_23|
+                          MMC_VDD_24_25|MMC_VDD_25_26|MMC_VDD_26_27|
+                          MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|
+                          MMC_VDD_30_31|MMC_VDD_31_32,
         .init           = em_x270_mci_init,
         .setpower       = em_x270_mci_setpower,
         .exit           = em_x270_mci_exit,
@@ -436,33 +579,53 @@ static struct pxamci_platform_data em_x270_mci_platform_data = {
 
 static void __init em_x270_init_mmc(void)
 {
+        if (machine_is_em_x270())
+                em_x270_mci_platform_data.get_ro = em_x270_mci_get_ro;
+
+        em_x270_mci_platform_data.detect_delay  = msecs_to_jiffies(250);
         pxa_set_mci_info(&em_x270_mci_platform_data);
 }
 #else
 static inline void em_x270_init_mmc(void) {}
 #endif
 
-/* LCD 480x640 */
+/* LCD */
 #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-static struct pxafb_mode_info em_x270_lcd_mode = {
-        .pixclock       = 50000,
-        .bpp            = 16,
-        .xres           = 480,
-        .yres           = 640,
-        .hsync_len      = 8,
-        .vsync_len      = 2,
-        .left_margin    = 8,
-        .upper_margin   = 0,
-        .right_margin   = 24,
-        .lower_margin   = 4,
-        .cmap_greyscale = 0,
+static struct pxafb_mode_info em_x270_lcd_modes[] = {
+        [0] = {
+                .pixclock       = 38250,
+                .bpp            = 16,
+                .xres           = 480,
+                .yres           = 640,
+                .hsync_len      = 8,
+                .vsync_len      = 2,
+                .left_margin    = 8,
+                .upper_margin   = 2,
+                .right_margin   = 24,
+                .lower_margin   = 4,
+                .sync           = 0,
+        },
+        [1] = {
+                .pixclock       = 153800,
+                .bpp            = 16,
+                .xres           = 240,
+                .yres           = 320,
+                .hsync_len      = 8,
+                .vsync_len      = 2,
+                .left_margin    = 8,
+                .upper_margin   = 2,
+                .right_margin   = 88,
+                .lower_margin   = 2,
+                .sync           = 0,
+        },
 };
 
 static struct pxafb_mach_info em_x270_lcd = {
-        .modes          = &em_x270_lcd_mode,
-        .num_modes      = 1,
+        .modes          = em_x270_lcd_modes,
+        .num_modes      = 2,
         .lcd_conn       = LCD_COLOR_TFT_16BPP,
 };
+
 static void __init em_x270_init_lcd(void)
 {
         set_pxa_fb_info(&em_x270_lcd);
@@ -471,6 +634,40 @@ static void __init em_x270_init_lcd(void)
 static inline void em_x270_init_lcd(void) {}
 #endif
 
+#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
+static struct pxa2xx_spi_master em_x270_spi_info = {
+        .num_chipselect = 1,
+};
+
+static struct pxa2xx_spi_chip em_x270_tdo24m_chip = {
+        .rx_threshold = 1,
+        .tx_threshold = 1,
+};
+
+static struct tdo24m_platform_data em_x270_tdo24m_pdata = {
+        .model = TDO35S,
+};
+
+static struct spi_board_info em_x270_spi_devices[] __initdata = {
+        {
+                .modalias = "tdo24m",
+                .max_speed_hz = 1000000,
+                .bus_num = 1,
+                .chip_select = 0,
+                .controller_data = &em_x270_tdo24m_chip,
+                .platform_data = &em_x270_tdo24m_pdata,
+        },
+};
+
+static void __init em_x270_init_spi(void)
+{
+        pxa2xx_set_spi_info(1, &em_x270_spi_info);
+        spi_register_board_info(ARRAY_AND_SIZE(em_x270_spi_devices));
+}
+#else
+static inline void em_x270_init_spi(void) {}
+#endif
+
 #if defined(CONFIG_SND_PXA2XX_AC97) || defined(CONFIG_SND_PXA2XX_AC97_MODULE)
 static void __init em_x270_init_ac97(void)
 {
@@ -481,23 +678,76 @@ static inline void em_x270_init_ac97(void) {}
 #endif
 
 #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static unsigned int em_x270_matrix_keys[] = {
+static unsigned int em_x270_module_matrix_keys[] = {
         KEY(0, 0, KEY_A), KEY(1, 0, KEY_UP), KEY(2, 1, KEY_B),
         KEY(0, 2, KEY_LEFT), KEY(1, 1, KEY_ENTER), KEY(2, 0, KEY_RIGHT),
         KEY(0, 1, KEY_C), KEY(1, 2, KEY_DOWN), KEY(2, 2, KEY_D),
 };
 
-struct pxa27x_keypad_platform_data em_x270_keypad_info = {
+struct pxa27x_keypad_platform_data em_x270_module_keypad_info = {
         /* code map for the matrix keys */
         .matrix_key_rows        = 3,
         .matrix_key_cols        = 3,
-        .matrix_key_map         = em_x270_matrix_keys,
-        .matrix_key_map_size    = ARRAY_SIZE(em_x270_matrix_keys),
+        .matrix_key_map         = em_x270_module_matrix_keys,
+        .matrix_key_map_size    = ARRAY_SIZE(em_x270_module_matrix_keys),
+};
+
+static unsigned int em_x270_exeda_matrix_keys[] = {
+        KEY(0, 0, KEY_RIGHTSHIFT), KEY(0, 1, KEY_RIGHTCTRL),
+        KEY(0, 2, KEY_RIGHTALT), KEY(0, 3, KEY_SPACE),
+        KEY(0, 4, KEY_LEFTALT), KEY(0, 5, KEY_LEFTCTRL),
+        KEY(0, 6, KEY_ENTER), KEY(0, 7, KEY_SLASH),
+
+        KEY(1, 0, KEY_DOT), KEY(1, 1, KEY_M),
+        KEY(1, 2, KEY_N), KEY(1, 3, KEY_B),
+        KEY(1, 4, KEY_V), KEY(1, 5, KEY_C),
+        KEY(1, 6, KEY_X), KEY(1, 7, KEY_Z),
+
+        KEY(2, 0, KEY_LEFTSHIFT), KEY(2, 1, KEY_SEMICOLON),
+        KEY(2, 2, KEY_L), KEY(2, 3, KEY_K),
+        KEY(2, 4, KEY_J), KEY(2, 5, KEY_H),
+        KEY(2, 6, KEY_G), KEY(2, 7, KEY_F),
+
+        KEY(3, 0, KEY_D), KEY(3, 1, KEY_S),
+        KEY(3, 2, KEY_A), KEY(3, 3, KEY_TAB),
+        KEY(3, 4, KEY_BACKSPACE), KEY(3, 5, KEY_P),
+        KEY(3, 6, KEY_O), KEY(3, 7, KEY_I),
+
+        KEY(4, 0, KEY_U), KEY(4, 1, KEY_Y),
+        KEY(4, 2, KEY_T), KEY(4, 3, KEY_R),
+        KEY(4, 4, KEY_E), KEY(4, 5, KEY_W),
+        KEY(4, 6, KEY_Q), KEY(4, 7, KEY_MINUS),
+
+        KEY(5, 0, KEY_0), KEY(5, 1, KEY_9),
+        KEY(5, 2, KEY_8), KEY(5, 3, KEY_7),
+        KEY(5, 4, KEY_6), KEY(5, 5, KEY_5),
+        KEY(5, 6, KEY_4), KEY(5, 7, KEY_3),
+
+        KEY(6, 0, KEY_2), KEY(6, 1, KEY_1),
+        KEY(6, 2, KEY_ENTER), KEY(6, 3, KEY_END),
+        KEY(6, 4, KEY_DOWN), KEY(6, 5, KEY_UP),
+        KEY(6, 6, KEY_MENU), KEY(6, 7, KEY_F1),
+
+        KEY(7, 0, KEY_LEFT), KEY(7, 1, KEY_RIGHT),
+        KEY(7, 2, KEY_BACK), KEY(7, 3, KEY_HOME),
+        KEY(7, 4, 0), KEY(7, 5, 0),
+        KEY(7, 6, 0), KEY(7, 7, 0),
+};
+
+struct pxa27x_keypad_platform_data em_x270_exeda_keypad_info = {
+        /* code map for the matrix keys */
+        .matrix_key_rows        = 8,
+        .matrix_key_cols        = 8,
+        .matrix_key_map         = em_x270_exeda_matrix_keys,
+        .matrix_key_map_size    = ARRAY_SIZE(em_x270_exeda_matrix_keys),
 };
 
 static void __init em_x270_init_keypad(void)
 {
-        pxa_set_keypad_info(&em_x270_keypad_info);
+        if (machine_is_em_x270())
+                pxa_set_keypad_info(&em_x270_module_keypad_info);
+        else
+                pxa_set_keypad_info(&em_x270_exeda_keypad_info);
 }
 #else
 static inline void em_x270_init_keypad(void) {}
@@ -535,19 +785,264 @@ static void __init em_x270_init_gpio_keys(void)
 static inline void em_x270_init_gpio_keys(void) {}
 #endif
 
-static void __init em_x270_init(void)
+/* Quick Capture Interface and sensor setup */
+#if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE)
+static struct regulator *em_x270_camera_ldo;
+
+static int em_x270_sensor_init(struct device *dev)
 {
+        int ret;
+
+        ret = gpio_request(GPIO93_CAM_RESET, "camera reset");
+        if (ret)
+                return ret;
+
+        gpio_direction_output(GPIO93_CAM_RESET, 0);
+
+        em_x270_camera_ldo = regulator_get(NULL, "vcc cam");
+        if (em_x270_camera_ldo == NULL) {
+                gpio_free(GPIO93_CAM_RESET);
+                return -ENODEV;
+        }
+
+        ret = regulator_enable(em_x270_camera_ldo);
+        if (ret) {
+                regulator_put(em_x270_camera_ldo);
+                gpio_free(GPIO93_CAM_RESET);
+                return ret;
+        }
+
+        gpio_set_value(GPIO93_CAM_RESET, 1);
+
+        return 0;
+}
+
+struct pxacamera_platform_data em_x270_camera_platform_data = {
+        .init   = em_x270_sensor_init,
+        .flags  = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 |
+                PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN,
+        .mclk_10khz = 2600,
+};
+
+static int em_x270_sensor_power(struct device *dev, int on)
+{
+        int ret;
+        int is_on = regulator_is_enabled(em_x270_camera_ldo);
+
+        if (on == is_on)
+                return 0;
+
+        gpio_set_value(GPIO93_CAM_RESET, !on);
+
+        if (on)
+                ret = regulator_enable(em_x270_camera_ldo);
+        else
+                ret = regulator_disable(em_x270_camera_ldo);
+
+        if (ret)
+                return ret;
+
+        gpio_set_value(GPIO93_CAM_RESET, on);
+
+        return 0;
+}
+
+static struct soc_camera_link iclink = {
+        .bus_id = 0,
+        .power = em_x270_sensor_power,
+};
+
+static struct i2c_board_info em_x270_i2c_cam_info[] = {
+        {
+                I2C_BOARD_INFO("mt9m111", 0x48),
+                .platform_data = &iclink,
+        },
+};
+
+static struct i2c_pxa_platform_data em_x270_i2c_info = {
+        .fast_mode = 1,
+};
+
+static void  __init em_x270_init_camera(void)
+{
+        pxa_set_i2c_info(&em_x270_i2c_info);
+        i2c_register_board_info(0, ARRAY_AND_SIZE(em_x270_i2c_cam_info));
+        pxa_set_camera_info(&em_x270_camera_platform_data);
+}
+#else
+static inline void em_x270_init_camera(void) {}
+#endif
+
+/* DA9030 related initializations */
+#define REGULATOR_CONSUMER(_name, _dev, _supply)                               \
+        static struct regulator_consumer_supply _name##_consumers[] = { \
+                {                                                       \
+                        .dev = _dev,                                    \
+                        .supply = _supply,                              \
+                },                                                      \
+        }
+
+REGULATOR_CONSUMER(ldo3, NULL, "vcc gps");
+REGULATOR_CONSUMER(ldo5, NULL, "vcc cam");
+REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio");
+REGULATOR_CONSUMER(ldo12, NULL, "vcc usb");
+REGULATOR_CONSUMER(ldo19, NULL, "vcc gprs");
+
+#define REGULATOR_INIT(_ldo, _min_uV, _max_uV, _ops_mask)               \
+        static struct regulator_init_data _ldo##_data = {               \
+                .constraints = {                                        \
+                        .min_uV = _min_uV,                              \
+                        .max_uV = _max_uV,                              \
+                        .state_mem = {                                  \
+                                .enabled = 0,                           \
+                        },                                              \
+                        .valid_ops_mask = _ops_mask,                    \
+                },                                                      \
+                .num_consumer_supplies = ARRAY_SIZE(_ldo##_consumers),  \
+                .consumer_supplies = _ldo##_consumers,                  \
+        };
+
+REGULATOR_INIT(ldo3, 3200000, 3200000, REGULATOR_CHANGE_STATUS);
+REGULATOR_INIT(ldo5, 3000000, 3000000, REGULATOR_CHANGE_STATUS);
+REGULATOR_INIT(ldo10, 2000000, 3200000,
+               REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE);
+REGULATOR_INIT(ldo12, 3000000, 3000000, REGULATOR_CHANGE_STATUS);
+REGULATOR_INIT(ldo19, 3200000, 3200000, REGULATOR_CHANGE_STATUS);
+
+struct led_info em_x270_led_info = {
+        .name = "em-x270:orange",
+        .default_trigger = "battery-charging-or-full",
+};
+
+struct power_supply_info em_x270_psy_info = {
+        .name = "LP555597P6H-FPS",
+        .technology = POWER_SUPPLY_TECHNOLOGY_LIPO,
+        .voltage_max_design = 4200000,
+        .voltage_min_design = 3000000,
+        .use_for_apm = 1,
+};
+
+static void em_x270_battery_low(void)
+{
+        apm_queue_event(APM_LOW_BATTERY);
+}
+
+static void em_x270_battery_critical(void)
+{
+        apm_queue_event(APM_CRITICAL_SUSPEND);
+}
+
+struct da9030_battery_info em_x270_batterty_info = {
+        .battery_info = &em_x270_psy_info,
+
+        .charge_milliamp = 1000,
+        .charge_millivolt = 4200,
+
+        .vbat_low = 3600,
+        .vbat_crit = 3400,
+        .vbat_charge_start = 4100,
+        .vbat_charge_stop = 4200,
+        .vbat_charge_restart = 4000,
+
+        .vcharge_min = 3200,
+        .vcharge_max = 5500,
+
+        .tbat_low = 197,
+        .tbat_high = 78,
+        .tbat_restart = 100,
+
+        .batmon_interval = 0,
+
+        .battery_low = em_x270_battery_low,
+        .battery_critical = em_x270_battery_critical,
+};
+
+#define DA9030_SUBDEV(_name, _id, _pdata)       \
+        {                                       \
+                .name = "da903x-" #_name,       \
+                .id = DA9030_ID_##_id,          \
+                .platform_data = _pdata,        \
+        }
+
+#define DA9030_LDO(num) DA9030_SUBDEV(regulator, LDO##num, &ldo##num##_data)
+
+struct da903x_subdev_info em_x270_da9030_subdevs[] = {
+        DA9030_LDO(3),
+        DA9030_LDO(5),
+        DA9030_LDO(10),
+        DA9030_LDO(12),
+        DA9030_LDO(19),
+
+        DA9030_SUBDEV(led, LED_PC, &em_x270_led_info),
+        DA9030_SUBDEV(backlight, WLED, &em_x270_led_info),
+        DA9030_SUBDEV(battery, BAT, &em_x270_batterty_info),
+};
+
+static struct da903x_platform_data em_x270_da9030_info = {
+        .num_subdevs = ARRAY_SIZE(em_x270_da9030_subdevs),
+        .subdevs = em_x270_da9030_subdevs,
+};
+
+static struct i2c_board_info em_x270_i2c_pmic_info = {
+        I2C_BOARD_INFO("da9030", 0x49),
+        .irq = IRQ_GPIO(0),
+        .platform_data = &em_x270_da9030_info,
+};
+
+static struct i2c_pxa_platform_data em_x270_pwr_i2c_info = {
+        .use_pio = 1,
+};
+
+static void __init em_x270_init_da9030(void)
+{
+        pxa27x_set_i2c_power_info(&em_x270_pwr_i2c_info);
+        i2c_register_board_info(1, &em_x270_i2c_pmic_info, 1);
+}
+
+static void __init em_x270_module_init(void)
+{
+        pr_info("%s\n", __func__);
         pxa2xx_mfp_config(ARRAY_AND_SIZE(em_x270_pin_config));
 
+        mmc_cd = GPIO13_MMC_CD;
+        nand_rb = GPIO56_NAND_RB;
+        dm9000_flags = DM9000_PLATF_32BITONLY;
+}
+
+static void __init em_x270_exeda_init(void)
+{
+        pr_info("%s\n", __func__);
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(exeda_pin_config));
+
+        mmc_cd = GPIO114_MMC_CD;
+        nand_rb = GPIO20_NAND_RB;
+        dm9000_flags = DM9000_PLATF_16BITONLY;
+}
+
+static void __init em_x270_init(void)
+{
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(common_pin_config));
+
+        if (machine_is_em_x270())
+                em_x270_module_init();
+        else if (machine_is_exeda())
+                em_x270_exeda_init();
+        else
+                panic("Unsupported machine: %d\n", machine_arch_type);
+
+        em_x270_init_da9030();
         em_x270_init_dm9000();
         em_x270_init_rtc();
         em_x270_init_nand();
+        em_x270_init_nor();
         em_x270_init_lcd();
         em_x270_init_mmc();
         em_x270_init_ohci();
         em_x270_init_keypad();
         em_x270_init_gpio_keys();
         em_x270_init_ac97();
+        em_x270_init_camera();
+        em_x270_init_spi();
 }
 
 MACHINE_START(EM_X270, "Compulab EM-X270")
@@ -559,3 +1054,13 @@ MACHINE_START(EM_X270, "Compulab EM-X270")
         .timer          = &pxa_timer,
         .init_machine   = em_x270_init,
 MACHINE_END
+
+MACHINE_START(EXEDA, "Compulab eXeda")
+        .boot_params    = 0xa0000100,
+        .phys_io        = 0x40000000,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa27x_init_irq,
+        .timer          = &pxa_timer,
+        .init_machine   = em_x270_init,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index dfce7d5b659e..c60dadf847a6 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -20,8 +20,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
-#include <mach/mfp-pxa25x.h>
-#include <mach/hardware.h>
+#include <mach/pxa25x.h>
 #include <mach/eseries-gpio.h>
 #include <mach/udc.h>
 #include <mach/irda.h>
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index df5f822f3b6c..92ba16e1b6fc 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -19,18 +19,16 @@
 #include <linux/input.h>
 
 #include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/pxa27x.h>
 #include <mach/pxafb.h>
 #include <mach/ohci.h>
 #include <mach/i2c.h>
 #include <mach/hardware.h>
 #include <mach/pxa27x_keypad.h>
 
-#include <mach/mfp-pxa27x.h>
-#include <mach/pxa-regs.h>
-#include <mach/pxa2xx-regs.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
 #include "devices.h"
 #include "generic.h"
 
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 0ccc91c92c44..3126a35aa002 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -26,8 +26,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach-types.h>
 
-#include <mach/pxa-regs.h>
 #include <mach/reset.h>
+#include <mach/gpio.h>
+#include <mach/pxa2xx-gpio.h>
 
 #include "generic.h"
 
@@ -127,3 +128,33 @@ void __init pxa_map_io(void)
         iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
         get_clk_frequency_khz(1);
 }
+
+/*
+ * Configure pins for GPIO or other functions
+ */
+int pxa_gpio_mode(int gpio_mode)
+{
+        unsigned long flags;
+        int gpio = gpio_mode & GPIO_MD_MASK_NR;
+        int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
+        int gafr;
+
+        if (gpio > pxa_last_gpio)
+                return -EINVAL;
+
+        local_irq_save(flags);
+        if (gpio_mode & GPIO_DFLT_LOW)
+                GPCR(gpio) = GPIO_bit(gpio);
+        else if (gpio_mode & GPIO_DFLT_HIGH)
+                GPSR(gpio) = GPIO_bit(gpio);
+        if (gpio_mode & GPIO_MD_MASK_DIR)
+                GPDR(gpio) |= GPIO_bit(gpio);
+        else
+                GPDR(gpio) &= ~GPIO_bit(gpio);
+        gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
+        GAFR(gpio) = gafr |  (fn  << (((gpio) & 0xf)*2));
+        local_irq_restore(flags);
+
+        return 0;
+}
+EXPORT_SYMBOL(pxa_gpio_mode);
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index dc876a8e6668..3465268ca716 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -9,20 +9,17 @@
  * published by the Free Software Foundation.
  */
 
-typedef int (*set_wake_t)(unsigned int, unsigned int);
-
 struct sys_timer;
 
 extern struct sys_timer pxa_timer;
-extern void __init pxa_init_irq(int irq_nr, set_wake_t fn);
-extern void __init pxa_init_gpio(int gpio_nr, set_wake_t fn);
+extern void __init pxa_init_irq(int irq_nr,
+                                int (*set_wake)(unsigned int, unsigned int));
 extern void __init pxa25x_init_irq(void);
 extern void __init pxa27x_init_irq(void);
 extern void __init pxa3xx_init_irq(void);
 extern void __init pxa_map_io(void);
 
 extern unsigned int get_clk_frequency_khz(int info);
-extern int pxa_last_gpio;
 
 #define SET_BANK(__nr,__start,__size) \
         mi->bank[__nr].start = (__start), \
diff --git a/arch/arm/mach-pxa/gpio.c b/arch/arm/mach-pxa/gpio.c
deleted file mode 100644
index 5fec1e479cb3..000000000000
--- a/arch/arm/mach-pxa/gpio.c
+++ /dev/null
@@ -1,453 +0,0 @@
-/*
- *  linux/arch/arm/mach-pxa/gpio.c
- *
- *  Generic PXA GPIO handling
- *
- *  Author:     Nicolas Pitre
- *  Created:    Jun 15, 2001
- *  Copyright:  MontaVista Software Inc.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <linux/sysdev.h>
-#include <linux/io.h>
-
-#include <asm/gpio.h>
-#include <mach/hardware.h>
-#include <mach/pxa-regs.h>
-#include <mach/pxa2xx-gpio.h>
-
-#include "generic.h"
-
-#define GPIO0_BASE      ((void __iomem *)io_p2v(0x40E00000))
-#define GPIO1_BASE      ((void __iomem *)io_p2v(0x40E00004))
-#define GPIO2_BASE      ((void __iomem *)io_p2v(0x40E00008))
-#define GPIO3_BASE      ((void __iomem *)io_p2v(0x40E00100))
-
-#define GPLR_OFFSET     0x00
-#define GPDR_OFFSET     0x0C
-#define GPSR_OFFSET     0x18
-#define GPCR_OFFSET     0x24
-#define GRER_OFFSET     0x30
-#define GFER_OFFSET     0x3C
-#define GEDR_OFFSET     0x48
-
-struct pxa_gpio_chip {
-        struct gpio_chip chip;
-        void __iomem     *regbase;
-};
-
-int pxa_last_gpio;
-
-#ifdef CONFIG_CPU_PXA26x
-/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted,
- * as well as their Alternate Function value being '1' for GPIO in GAFRx.
- */
-static int __gpio_is_inverted(unsigned gpio)
-{
-        return cpu_is_pxa25x() && gpio > 85;
-}
-#else
-#define __gpio_is_inverted(gpio)        (0)
-#endif
-
-/*
- * Configure pins for GPIO or other functions
- */
-int pxa_gpio_mode(int gpio_mode)
-{
-        unsigned long flags;
-        int gpio = gpio_mode & GPIO_MD_MASK_NR;
-        int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
-        int gafr;
-
-        if (gpio > pxa_last_gpio)
-                return -EINVAL;
-
-        local_irq_save(flags);
-        if (gpio_mode & GPIO_DFLT_LOW)
-                GPCR(gpio) = GPIO_bit(gpio);
-        else if (gpio_mode & GPIO_DFLT_HIGH)
-                GPSR(gpio) = GPIO_bit(gpio);
-        if (gpio_mode & GPIO_MD_MASK_DIR)
-                GPDR(gpio) |= GPIO_bit(gpio);
-        else
-                GPDR(gpio) &= ~GPIO_bit(gpio);
-        gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
-        GAFR(gpio) = gafr |  (fn  << (((gpio) & 0xf)*2));
-        local_irq_restore(flags);
-
-        return 0;
-}
-EXPORT_SYMBOL(pxa_gpio_mode);
-
-static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
-        unsigned long        flags;
-        u32                  mask = 1 << offset;
-        u32                  value;
-        struct pxa_gpio_chip *pxa;
-        void __iomem         *gpdr;
-
-        pxa = container_of(chip, struct pxa_gpio_chip, chip);
-        gpdr = pxa->regbase + GPDR_OFFSET;
-        local_irq_save(flags);
-        value = __raw_readl(gpdr);
-        if (__gpio_is_inverted(chip->base + offset))
-                value |= mask;
-        else
-                value &= ~mask;
-        __raw_writel(value, gpdr);
-        local_irq_restore(flags);
-
-        return 0;
-}
-
-static int pxa_gpio_direction_output(struct gpio_chip *chip,
-                                        unsigned offset, int value)
-{
-        unsigned long        flags;
-        u32                  mask = 1 << offset;
-        u32                  tmp;
-        struct pxa_gpio_chip *pxa;
-        void __iomem         *gpdr;
-
-        pxa = container_of(chip, struct pxa_gpio_chip, chip);
-        __raw_writel(mask,
-                        pxa->regbase + (value ? GPSR_OFFSET : GPCR_OFFSET));
-        gpdr = pxa->regbase + GPDR_OFFSET;
-        local_irq_save(flags);
-        tmp = __raw_readl(gpdr);
-        if (__gpio_is_inverted(chip->base + offset))
-                tmp &= ~mask;
-        else
-                tmp |= mask;
-        __raw_writel(tmp, gpdr);
-        local_irq_restore(flags);
-
-        return 0;
-}
-
-/*
- * Return GPIO level
- */
-static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
-        u32                  mask = 1 << offset;
-        struct pxa_gpio_chip *pxa;
-
-        pxa = container_of(chip, struct pxa_gpio_chip, chip);
-        return __raw_readl(pxa->regbase + GPLR_OFFSET) & mask;
-}
-
-/*
- * Set output GPIO level
- */
-static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
-        u32                  mask = 1 << offset;
-        struct pxa_gpio_chip *pxa;
-
-        pxa = container_of(chip, struct pxa_gpio_chip, chip);
-
-        if (value)
-                __raw_writel(mask, pxa->regbase + GPSR_OFFSET);
-        else
-                __raw_writel(mask, pxa->regbase + GPCR_OFFSET);
-}
-
-#define GPIO_CHIP(_n)                                                   \
-        [_n] = {                                                        \
-                .regbase = GPIO##_n##_BASE,                             \
-                .chip = {                                               \
-                        .label            = "gpio-" #_n,                \
-                        .direction_input  = pxa_gpio_direction_input,   \
-                        .direction_output = pxa_gpio_direction_output,  \
-                        .get              = pxa_gpio_get,               \
-                        .set              = pxa_gpio_set,               \
-                        .base             = (_n) * 32,                  \
-                        .ngpio            = 32,                         \
-                },                                                      \
-        }
-
-static struct pxa_gpio_chip pxa_gpio_chip[] = {
-        GPIO_CHIP(0),
-        GPIO_CHIP(1),
-        GPIO_CHIP(2),
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-        GPIO_CHIP(3),
-#endif
-};
-
-/*
- * PXA GPIO edge detection for IRQs:
- * IRQs are generated on Falling-Edge, Rising-Edge, or both.
- * Use this instead of directly setting GRER/GFER.
- */
-
-static unsigned long GPIO_IRQ_rising_edge[4];
-static unsigned long GPIO_IRQ_falling_edge[4];
-static unsigned long GPIO_IRQ_mask[4];
-
-/*
- * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
- * function of a GPIO, and GPDRx cannot be altered once configured. It
- * is attributed as "occupied" here (I know this terminology isn't
- * accurate, you are welcome to propose a better one :-)
- */
-static int __gpio_is_occupied(unsigned gpio)
-{
-        if (cpu_is_pxa27x() || cpu_is_pxa25x()) {
-                int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3;
-                int dir = GPDR(gpio) & GPIO_bit(gpio);
-
-                if (__gpio_is_inverted(gpio))
-                        return af != 1 || dir == 0;
-                else
-                        return af != 0 || dir != 0;
-        }
-
-        return 0;
-}
-
-static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
-{
-        int gpio, idx;
-
-        gpio = IRQ_TO_GPIO(irq);
-        idx = gpio >> 5;
-
-        if (type == IRQ_TYPE_PROBE) {
-                /* Don't mess with enabled GPIOs using preconfigured edges or
-                 * GPIOs set to alternate function or to output during probe
-                 */
-                if ((GPIO_IRQ_rising_edge[idx] & GPIO_bit(gpio)) ||
-                    (GPIO_IRQ_falling_edge[idx] & GPIO_bit(gpio)))
-                        return 0;
-
-                if (__gpio_is_occupied(gpio))
-                        return 0;
-
-                type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
-        }
-
-        if (__gpio_is_inverted(gpio))
-                GPDR(gpio) |= GPIO_bit(gpio);
-        else
-                GPDR(gpio) &= ~GPIO_bit(gpio);
-
-        if (type & IRQ_TYPE_EDGE_RISING)
-                __set_bit(gpio, GPIO_IRQ_rising_edge);
-        else
-                __clear_bit(gpio, GPIO_IRQ_rising_edge);
-
-        if (type & IRQ_TYPE_EDGE_FALLING)
-                __set_bit(gpio, GPIO_IRQ_falling_edge);
-        else
-                __clear_bit(gpio, GPIO_IRQ_falling_edge);
-
-        GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
-        GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
-
-        pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio,
-                ((type & IRQ_TYPE_EDGE_RISING)  ? " rising"  : ""),
-                ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
-        return 0;
-}
-
-/*
- * GPIO IRQs must be acknowledged.  This is for GPIO 0 and 1.
- */
-
-static void pxa_ack_low_gpio(unsigned int irq)
-{
-        GEDR0 = (1 << (irq - IRQ_GPIO0));
-}
-
-static void pxa_mask_low_gpio(unsigned int irq)
-{
-        ICMR &= ~(1 << (irq - PXA_IRQ(0)));
-}
-
-static void pxa_unmask_low_gpio(unsigned int irq)
-{
-        ICMR |= 1 << (irq - PXA_IRQ(0));
-}
-
-static struct irq_chip pxa_low_gpio_chip = {
-        .name           = "GPIO-l",
-        .ack            = pxa_ack_low_gpio,
-        .mask           = pxa_mask_low_gpio,
-        .unmask         = pxa_unmask_low_gpio,
-        .set_type       = pxa_gpio_irq_type,
-};
-
-/*
- * Demux handler for GPIO>=2 edge detect interrupts
- */
-
-#define GEDR_BITS       (sizeof(gedr) * BITS_PER_BYTE)
-
-static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
-{
-        int loop, bit, n;
-        unsigned long gedr[4];
-
-        do {
-                gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3;
-                gedr[1] = GEDR1 & GPIO_IRQ_mask[1];
-                gedr[2] = GEDR2 & GPIO_IRQ_mask[2];
-                gedr[3] = GEDR3 & GPIO_IRQ_mask[3];
-
-                GEDR0 = gedr[0]; GEDR1 = gedr[1];
-                GEDR2 = gedr[2]; GEDR3 = gedr[3];
-
-                loop = 0;
-                bit = find_first_bit(gedr, GEDR_BITS);
-                while (bit < GEDR_BITS) {
-                        loop = 1;
-
-                        n = PXA_GPIO_IRQ_BASE + bit;
-                        generic_handle_irq(n);
-
-                        bit = find_next_bit(gedr, GEDR_BITS, bit + 1);
-                }
-        } while (loop);
-}
-
-static void pxa_ack_muxed_gpio(unsigned int irq)
-{
-        int gpio = irq - IRQ_GPIO(2) + 2;
-        GEDR(gpio) = GPIO_bit(gpio);
-}
-
-static void pxa_mask_muxed_gpio(unsigned int irq)
-{
-        int gpio = irq - IRQ_GPIO(2) + 2;
-        __clear_bit(gpio, GPIO_IRQ_mask);
-        GRER(gpio) &= ~GPIO_bit(gpio);
-        GFER(gpio) &= ~GPIO_bit(gpio);
-}
-
-static void pxa_unmask_muxed_gpio(unsigned int irq)
-{
-        int gpio = irq - IRQ_GPIO(2) + 2;
-        int idx = gpio >> 5;
-        __set_bit(gpio, GPIO_IRQ_mask);
-        GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
-        GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
-}
-
-static struct irq_chip pxa_muxed_gpio_chip = {
-        .name           = "GPIO",
-        .ack            = pxa_ack_muxed_gpio,
-        .mask           = pxa_mask_muxed_gpio,
-        .unmask         = pxa_unmask_muxed_gpio,
-        .set_type       = pxa_gpio_irq_type,
-};
-
-void __init pxa_init_gpio(int gpio_nr, set_wake_t fn)
-{
-        int irq, i, gpio;
-
-        pxa_last_gpio = gpio_nr - 1;
-
-        /* clear all GPIO edge detects */
-        for (i = 0; i < gpio_nr; i += 32) {
-                GFER(i) = 0;
-                GRER(i) = 0;
-                GEDR(i) = GEDR(i);
-        }
-
-        /* GPIO 0 and 1 must have their mask bit always set */
-        GPIO_IRQ_mask[0] = 3;
-
-        for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
-                set_irq_chip(irq, &pxa_low_gpio_chip);
-                set_irq_handler(irq, handle_edge_irq);
-                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-        }
-
-        for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) {
-                set_irq_chip(irq, &pxa_muxed_gpio_chip);
-                set_irq_handler(irq, handle_edge_irq);
-                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-        }
-
-        /* Install handler for GPIO>=2 edge detect interrupts */
-        set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
-
-        pxa_low_gpio_chip.set_wake = fn;
-        pxa_muxed_gpio_chip.set_wake = fn;
-
-        /* add a GPIO chip for each register bank.
-         * the last PXA25x register only contains 21 GPIOs
-         */
-        for (gpio = 0, i = 0; gpio < gpio_nr; gpio += 32, i++) {
-                if (gpio + 32 > gpio_nr)
-                        pxa_gpio_chip[i].chip.ngpio = gpio_nr - gpio;
-                gpiochip_add(&pxa_gpio_chip[i].chip);
-        }
-}
-
-#ifdef CONFIG_PM
-
-static unsigned long saved_gplr[4];
-static unsigned long saved_gpdr[4];
-static unsigned long saved_grer[4];
-static unsigned long saved_gfer[4];
-
-static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state)
-{
-        int i, gpio;
-
-        for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
-                saved_gplr[i] = GPLR(gpio);
-                saved_gpdr[i] = GPDR(gpio);
-                saved_grer[i] = GRER(gpio);
-                saved_gfer[i] = GFER(gpio);
-
-                /* Clear GPIO transition detect bits */
-                GEDR(gpio) = GEDR(gpio);
-        }
-        return 0;
-}
-
-static int pxa_gpio_resume(struct sys_device *dev)
-{
-        int i, gpio;
-
-        for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
-                /* restore level with set/clear */
-                GPSR(gpio) = saved_gplr[i];
-                GPCR(gpio) = ~saved_gplr[i];
-
-                GRER(gpio) = saved_grer[i];
-                GFER(gpio) = saved_gfer[i];
-                GPDR(gpio) = saved_gpdr[i];
-        }
-        return 0;
-}
-#else
-#define pxa_gpio_suspend        NULL
-#define pxa_gpio_resume         NULL
-#endif
-
-struct sysdev_class pxa_gpio_sysclass = {
-        .name           = "gpio",
-        .suspend        = pxa_gpio_suspend,
-        .resume         = pxa_gpio_resume,
-};
-
-static int __init pxa_gpio_init(void)
-{
-        return sysdev_class_register(&pxa_gpio_sysclass);
-}
-
-core_initcall(pxa_gpio_init);
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
index e296ce11658c..ca9912ea78d9 100644
--- a/arch/arm/mach-pxa/gumstix.c
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -38,14 +38,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/flash.h>
+
+#include <mach/pxa25x.h>
 #include <mach/mmc.h>
 #include <mach/udc.h>
 #include <mach/gumstix.h>
 
-#include <mach/pxa-regs.h>
-#include <mach/pxa2xx-regs.h>
-#include <mach/mfp-pxa25x.h>
-
 #include "generic.h"
 
 static struct resource flash_resource = {
@@ -191,6 +189,11 @@ int __attribute__((weak)) am200_init(void)
         return 0;
 }
 
+int __attribute__((weak)) am300_init(void)
+{
+        return 0;
+}
+
 static void __init carrier_board_init(void)
 {
         /*
@@ -198,6 +201,7 @@ static void __init carrier_board_init(void)
          * they cannot be detected programatically
          */
         am200_init();
+        am300_init();
 }
 
 static void __init gumstix_init(void)
diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c
index 295ec413d804..f3d220c32e07 100644
--- a/arch/arm/mach-pxa/h5000.c
+++ b/arch/arm/mach-pxa/h5000.c
@@ -24,14 +24,15 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+
+#include <mach/pxa25x.h>
 #include <mach/h5000.h>
-#include <mach/pxa-regs.h>
-#include <mach/pxa2xx-regs.h>
-#include <mach/mfp-pxa25x.h>
 #include <mach/udc.h>
+
 #include "generic.h"
 
 /*
diff --git a/arch/arm/mach-pxa/himalaya.c b/arch/arm/mach-pxa/himalaya.c
new file mode 100644
index 000000000000..cea99fe65b97
--- /dev/null
+++ b/arch/arm/mach-pxa/himalaya.c
@@ -0,0 +1,166 @@
+/*
+ * linux/arch/arm/mach-pxa/himalaya.c
+ *
+ * Hardware definitions for the HTC Himalaya
+ *
+ * Based on 2.6.21-hh20's himalaya.c and himalaya_lcd.c
+ *
+ * Copyright (c) 2008 Zbynek Michl <Zbynek.Michl@seznam.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/fb.h>
+#include <linux/platform_device.h>
+
+#include <video/w100fb.h>
+
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/mfp-pxa25x.h>
+#include <mach/hardware.h>
+
+#include "generic.h"
+
+/* ---------------------- Himalaya LCD definitions -------------------- */
+
+static struct w100_gen_regs himalaya_lcd_regs = {
+        .lcd_format =        0x00000003,
+        .lcdd_cntl1 =        0x00000000,
+        .lcdd_cntl2 =        0x0003ffff,
+        .genlcd_cntl1 =      0x00fff003,
+        .genlcd_cntl2 =      0x00000003,
+        .genlcd_cntl3 =      0x000102aa,
+};
+
+static struct w100_mode himalaya4_lcd_mode = {
+        .xres           = 240,
+        .yres           = 320,
+        .left_margin    = 0,
+        .right_margin   = 31,
+        .upper_margin   = 15,
+        .lower_margin   = 0,
+        .crtc_ss        = 0x80150014,
+        .crtc_ls        = 0xa0fb00f7,
+        .crtc_gs        = 0xc0080007,
+        .crtc_vpos_gs   = 0x00080007,
+        .crtc_rev       = 0x0000000a,
+        .crtc_dclk      = 0x81700030,
+        .crtc_gclk      = 0x8015010f,
+        .crtc_goe       = 0x00000000,
+        .pll_freq       = 80,
+        .pixclk_divider = 15,
+        .pixclk_divider_rotated = 15,
+        .pixclk_src     = CLK_SRC_PLL,
+        .sysclk_divider = 0,
+        .sysclk_src     = CLK_SRC_PLL,
+};
+
+static struct w100_mode himalaya6_lcd_mode = {
+        .xres           = 240,
+        .yres           = 320,
+        .left_margin    = 9,
+        .right_margin   = 8,
+        .upper_margin   = 5,
+        .lower_margin   = 4,
+        .crtc_ss        = 0x80150014,
+        .crtc_ls        = 0xa0fb00f7,
+        .crtc_gs        = 0xc0080007,
+        .crtc_vpos_gs   = 0x00080007,
+        .crtc_rev       = 0x0000000a,
+        .crtc_dclk      = 0xa1700030,
+        .crtc_gclk      = 0x8015010f,
+        .crtc_goe       = 0x00000000,
+        .pll_freq       = 95,
+        .pixclk_divider = 0xb,
+        .pixclk_divider_rotated = 4,
+        .pixclk_src     = CLK_SRC_PLL,
+        .sysclk_divider = 1,
+        .sysclk_src     = CLK_SRC_PLL,
+};
+
+static struct w100_gpio_regs himalaya_w100_gpio_info = {
+        .init_data1 = 0xffff0000,       /* GPIO_DATA  */
+        .gpio_dir1  = 0x00000000,       /* GPIO_CNTL1 */
+        .gpio_oe1   = 0x003c0000,       /* GPIO_CNTL2 */
+        .init_data2 = 0x00000000,       /* GPIO_DATA2 */
+        .gpio_dir2  = 0x00000000,       /* GPIO_CNTL3 */
+        .gpio_oe2   = 0x00000000,       /* GPIO_CNTL4 */
+};
+
+static struct w100fb_mach_info himalaya_fb_info = {
+        .num_modes  = 1,
+        .regs       = &himalaya_lcd_regs,
+        .gpio       = &himalaya_w100_gpio_info,
+        .xtal_freq = 16000000,
+};
+
+static struct resource himalaya_fb_resources[] = {
+        [0] = {
+                .start  = 0x08000000,
+                .end    = 0x08ffffff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device himalaya_fb_device = {
+        .name           = "w100fb",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &himalaya_fb_info,
+        },
+        .num_resources  = ARRAY_SIZE(himalaya_fb_resources),
+        .resource       = himalaya_fb_resources,
+};
+
+/* ----------------------------------------------------------------------- */
+
+static struct platform_device *devices[] __initdata = {
+        &himalaya_fb_device,
+};
+
+static void __init himalaya_lcd_init(void)
+{
+        int himalaya_boardid;
+
+        himalaya_boardid = 0x4; /* hardcoded (detection needs ASIC3 functions) */
+        printk(KERN_INFO "himalaya LCD Driver init. boardid=%d\n",
+                himalaya_boardid);
+
+        switch (himalaya_boardid) {
+        case 0x4:
+                himalaya_fb_info.modelist = &himalaya4_lcd_mode;
+        break;
+        case 0x6:
+                himalaya_fb_info.modelist = &himalaya6_lcd_mode;
+        break;
+        default:
+                printk(KERN_INFO "himalaya lcd_init: unknown boardid=%d. Using 0x4\n",
+                        himalaya_boardid);
+                himalaya_fb_info.modelist = &himalaya4_lcd_mode;
+        }
+}
+
+static void __init himalaya_init(void)
+{
+        himalaya_lcd_init();
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+
+MACHINE_START(HIMALAYA, "HTC Himalaya")
+        .phys_io = 0x40000000,
+        .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .boot_params = 0xa0000100,
+        .map_io = pxa_map_io,
+        .init_irq = pxa25x_init_irq,
+        .init_machine = himalaya_init,
+        .timer = &pxa_timer,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index 013b15baa034..b6243b59d9be 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -31,8 +31,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <mach/pxa-regs.h>
-#include <mach/mfp-pxa25x.h>
+#include <mach/pxa25x.h>
 #include <mach/idp.h>
 #include <mach/pxafb.h>
 #include <mach/bitfield.h>
diff --git a/arch/arm/mach-pxa/imote2.c b/arch/arm/mach-pxa/imote2.c
index 364c5e271330..2121309b2474 100644
--- a/arch/arm/mach-pxa/imote2.c
+++ b/arch/arm/mach-pxa/imote2.c
@@ -28,11 +28,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
+#include <mach/pxa27x.h>
 #include <mach/i2c.h>
-#include <mach/pxa-regs.h>
-#include <mach/pxa2xx-regs.h>
-#include <mach/mfp-pxa27x.h>
-#include <mach/regs-ssp.h>
 #include <mach/udc.h>
 #include <mach/mmc.h>
 #include <mach/pxa2xx_spi.h>
diff --git a/arch/arm/mach-pxa/include/mach/colibri.h b/arch/arm/mach-pxa/include/mach/colibri.h
index 2ae373fb5675..3f2a01d6a03c 100644
--- a/arch/arm/mach-pxa/include/mach/colibri.h
+++ b/arch/arm/mach-pxa/include/mach/colibri.h
@@ -1,19 +1,31 @@
 #ifndef _COLIBRI_H_
 #define _COLIBRI_H_
+/*
+ * common settings for all modules
+ */
+
+#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
+extern void colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin);
+#else
+static inline void colibri_pxa3xx_init_mmc(mfp_cfg_t *, int, int) {}
+#endif
+
+#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
+extern void colibri_pxa3xx_init_lcd(int bl_pin);
+#else
+static inline void colibri_pxa3xx_init_lcd(int) {}
+#endif
 
 /* physical memory regions */
-#define COLIBRI_FLASH_PHYS      (PXA_CS0_PHYS)  /* Flash region */
-#define COLIBRI_ETH_PHYS        (PXA_CS2_PHYS)  /* Ethernet DM9000 region */
 #define COLIBRI_SDRAM_BASE      0xa0000000      /* SDRAM region */
 
-/* virtual memory regions */
-#define COLIBRI_DISK_VIRT       0xF0000000      /* Disk On Chip region */
+/* definitions for Colibri PXA270 */
 
-/* size of flash */
-#define COLIBRI_FLASH_SIZE      0x02000000      /* Flash size 32 MB */
-
-/* Ethernet Controller Davicom DM9000 */
-#define GPIO_DM9000             114
-#define COLIBRI_ETH_IRQ IRQ_GPIO(GPIO_DM9000)
+#define COLIBRI_PXA270_FLASH_PHYS       (PXA_CS0_PHYS)  /* Flash region */
+#define COLIBRI_PXA270_ETH_PHYS         (PXA_CS2_PHYS)  /* Ethernet */
+#define COLIBRI_PXA270_ETH_IRQ_GPIO     114
+#define COLIBRI_PXA270_ETH_IRQ          \
+        gpio_to_irq(mfp_to_gpio(COLIBRI_PXA270_ETH_IRQ_GPIO))
 
 #endif /* _COLIBRI_H_ */
+
diff --git a/arch/arm/mach-pxa/include/mach/csb726.h b/arch/arm/mach-pxa/include/mach/csb726.h
new file mode 100644
index 000000000000..747ab1a71f2f
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/csb726.h
@@ -0,0 +1,26 @@
+/*
+ *  Support for Cogent CSB726
+ *
+ *  Copyright (c) 2008 Dmitry Baryshkov
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+#ifndef CSB726_H
+#define CSB726_H
+
+#define CSB726_GPIO_IRQ_LAN     52
+#define CSB726_GPIO_IRQ_SM501   53
+#define CSB726_GPIO_MMC_DETECT  100
+#define CSB726_GPIO_MMC_RO      101
+
+#define CSB726_FLASH_SIZE       (64 * 1024 * 1024)
+#define CSB726_FLASH_uMON       (8 * 1024 * 1024)
+
+#define CSB726_IRQ_LAN          gpio_to_irq(CSB726_GPIO_IRQ_LAN)
+#define CSB726_IRQ_SM501        gpio_to_irq(CSB726_GPIO_IRQ_SM501)
+
+#endif
+
diff --git a/arch/arm/mach-pxa/include/mach/dma.h b/arch/arm/mach-pxa/include/mach/dma.h
index 7804637a6df3..5bd55894a48d 100644
--- a/arch/arm/mach-pxa/include/mach/dma.h
+++ b/arch/arm/mach-pxa/include/mach/dma.h
@@ -12,35 +12,10 @@
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H
 
-/*
- * Descriptor structure for PXA's DMA engine
- * Note: this structure must always be aligned to a 16-byte boundary.
- */
-
-typedef struct pxa_dma_desc {
-        volatile u32 ddadr;     /* Points to the next descriptor + flags */
-        volatile u32 dsadr;     /* DSADR value for the current transfer */
-        volatile u32 dtadr;     /* DTADR value for the current transfer */
-        volatile u32 dcmd;      /* DCMD value for the current transfer */
-} pxa_dma_desc;
-
-typedef enum {
-        DMA_PRIO_HIGH = 0,
-        DMA_PRIO_MEDIUM = 1,
-        DMA_PRIO_LOW = 2
-} pxa_dma_prio;
-
-/*
- * DMA registration
- */
-
-int __init pxa_init_dma(int num_ch);
-
-int pxa_request_dma (char *name,
-                         pxa_dma_prio prio,
-                         void (*irq_handler)(int, void *),
-                         void *data);
+#include <mach/hardware.h>
 
-void pxa_free_dma (int dma_ch);
+/* DMA Controller Registers Definitions */
+#define DMAC_REGS_VIRT  io_p2v(0x40000000)
 
+#include <plat/dma.h>
 #endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-pxa/include/mach/gpio.h b/arch/arm/mach-pxa/include/mach/gpio.h
index 2c538d8c362d..b024a8b37439 100644
--- a/arch/arm/mach-pxa/include/mach/gpio.h
+++ b/arch/arm/mach-pxa/include/mach/gpio.h
@@ -24,42 +24,118 @@
 #ifndef __ASM_ARCH_PXA_GPIO_H
 #define __ASM_ARCH_PXA_GPIO_H
 
-#include <mach/pxa-regs.h>
-#include <asm/irq.h>
+#include <mach/irqs.h>
 #include <mach/hardware.h>
-
 #include <asm-generic/gpio.h>
 
+#define GPIO_REGS_VIRT  io_p2v(0x40E00000)
+
+#define BANK_OFF(n)     (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
+#define GPIO_REG(x)     (*(volatile u32 *)(GPIO_REGS_VIRT + (x)))
+
+/* GPIO Pin Level Registers */
+#define GPLR0           GPIO_REG(BANK_OFF(0) + 0x00)
+#define GPLR1           GPIO_REG(BANK_OFF(1) + 0x00)
+#define GPLR2           GPIO_REG(BANK_OFF(2) + 0x00)
+#define GPLR3           GPIO_REG(BANK_OFF(3) + 0x00)
+
+/* GPIO Pin Direction Registers */
+#define GPDR0           GPIO_REG(BANK_OFF(0) + 0x0c)
+#define GPDR1           GPIO_REG(BANK_OFF(1) + 0x0c)
+#define GPDR2           GPIO_REG(BANK_OFF(2) + 0x0c)
+#define GPDR3           GPIO_REG(BANK_OFF(3) + 0x0c)
+
+/* GPIO Pin Output Set Registers */
+#define GPSR0           GPIO_REG(BANK_OFF(0) + 0x18)
+#define GPSR1           GPIO_REG(BANK_OFF(1) + 0x18)
+#define GPSR2           GPIO_REG(BANK_OFF(2) + 0x18)
+#define GPSR3           GPIO_REG(BANK_OFF(3) + 0x18)
+
+/* GPIO Pin Output Clear Registers */
+#define GPCR0           GPIO_REG(BANK_OFF(0) + 0x24)
+#define GPCR1           GPIO_REG(BANK_OFF(1) + 0x24)
+#define GPCR2           GPIO_REG(BANK_OFF(2) + 0x24)
+#define GPCR3           GPIO_REG(BANK_OFF(3) + 0x24)
+
+/* GPIO Rising Edge Detect Registers */
+#define GRER0           GPIO_REG(BANK_OFF(0) + 0x30)
+#define GRER1           GPIO_REG(BANK_OFF(1) + 0x30)
+#define GRER2           GPIO_REG(BANK_OFF(2) + 0x30)
+#define GRER3           GPIO_REG(BANK_OFF(3) + 0x30)
+
+/* GPIO Falling Edge Detect Registers */
+#define GFER0           GPIO_REG(BANK_OFF(0) + 0x3c)
+#define GFER1           GPIO_REG(BANK_OFF(1) + 0x3c)
+#define GFER2           GPIO_REG(BANK_OFF(2) + 0x3c)
+#define GFER3           GPIO_REG(BANK_OFF(3) + 0x3c)
+
+/* GPIO Edge Detect Status Registers */
+#define GEDR0           GPIO_REG(BANK_OFF(0) + 0x48)
+#define GEDR1           GPIO_REG(BANK_OFF(1) + 0x48)
+#define GEDR2           GPIO_REG(BANK_OFF(2) + 0x48)
+#define GEDR3           GPIO_REG(BANK_OFF(3) + 0x48)
+
+/* GPIO Alternate Function Select Registers */
+#define GAFR0_L         GPIO_REG(0x0054)
+#define GAFR0_U         GPIO_REG(0x0058)
+#define GAFR1_L         GPIO_REG(0x005C)
+#define GAFR1_U         GPIO_REG(0x0060)
+#define GAFR2_L         GPIO_REG(0x0064)
+#define GAFR2_U         GPIO_REG(0x0068)
+#define GAFR3_L         GPIO_REG(0x006C)
+#define GAFR3_U         GPIO_REG(0x0070)
+
+/* More handy macros.  The argument is a literal GPIO number. */
+
+#define GPIO_bit(x)     (1 << ((x) & 0x1f))
+
+#define GPLR(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x00)
+#define GPDR(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x0c)
+#define GPSR(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x18)
+#define GPCR(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x24)
+#define GRER(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x30)
+#define GFER(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x3c)
+#define GEDR(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x48)
+#define GAFR(x)         GPIO_REG(0x54 + (((x) & 0x70) >> 2))
+
 
-/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
- * Those cases currently cause holes in the GPIO number space.
- */
 #define NR_BUILTIN_GPIO 128
 
-static inline int gpio_get_value(unsigned gpio)
+#define gpio_to_bank(gpio)      ((gpio) >> 5)
+#define gpio_to_irq(gpio)       IRQ_GPIO(gpio)
+#define irq_to_gpio(irq)        IRQ_TO_GPIO(irq)
+
+#ifdef CONFIG_CPU_PXA26x
+/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted,
+ * as well as their Alternate Function value being '1' for GPIO in GAFRx.
+ */
+static inline int __gpio_is_inverted(unsigned gpio)
 {
-        if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO))
-                return GPLR(gpio) & GPIO_bit(gpio);
-        else
-                return __gpio_get_value(gpio);
+        return cpu_is_pxa25x() && gpio > 85;
 }
+#else
+static inline int __gpio_is_inverted(unsigned gpio) { return 0; }
+#endif
 
-static inline void gpio_set_value(unsigned gpio, int value)
+/*
+ * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
+ * function of a GPIO, and GPDRx cannot be altered once configured. It
+ * is attributed as "occupied" here (I know this terminology isn't
+ * accurate, you are welcome to propose a better one :-)
+ */
+static inline int __gpio_is_occupied(unsigned gpio)
 {
-        if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) {
-                if (value)
-                        GPSR(gpio) = GPIO_bit(gpio);
+        if (cpu_is_pxa27x() || cpu_is_pxa25x()) {
+                int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3;
+                int dir = GPDR(gpio) & GPIO_bit(gpio);
+
+                if (__gpio_is_inverted(gpio))
+                        return af != 1 || dir == 0;
                 else
-                        GPCR(gpio) = GPIO_bit(gpio);
-        } else {
-                __gpio_set_value(gpio, value);
-        }
+                        return af != 0 || dir != 0;
+        } else
+                return GPDR(gpio) & GPIO_bit(gpio);
 }
 
-#define gpio_cansleep __gpio_cansleep
-
-#define gpio_to_irq(gpio)       IRQ_GPIO(gpio)
-#define irq_to_gpio(irq)        IRQ_TO_GPIO(irq)
-
-
+#include <plat/gpio.h>
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/gumstix.h b/arch/arm/mach-pxa/include/mach/gumstix.h
index 099f54a41de4..06abd4160607 100644
--- a/arch/arm/mach-pxa/include/mach/gumstix.h
+++ b/arch/arm/mach-pxa/include/mach/gumstix.h
@@ -97,4 +97,5 @@ has detected a cable insertion; driven low otherwise. */
 
 /* for expansion boards that can't be programatically detected */
 extern int am200_init(void);
+extern int am300_init(void);
 
diff --git a/arch/arm/mach-pxa/include/mach/lubbock.h b/arch/arm/mach-pxa/include/mach/lubbock.h
index 4cb24154a5a8..751b74811d0f 100644
--- a/arch/arm/mach-pxa/include/mach/lubbock.h
+++ b/arch/arm/mach-pxa/include/mach/lubbock.h
@@ -25,7 +25,6 @@
 
 /* FPGA register virtual addresses */
 #define LUB_WHOAMI              __LUB_REG(LUBBOCK_FPGA_PHYS + 0x000)
-#define LUB_HEXLED              __LUB_REG(LUBBOCK_FPGA_PHYS + 0x010)
 #define LUB_DISC_BLNK_LED       __LUB_REG(LUBBOCK_FPGA_PHYS + 0x040)
 #define LUB_CONF_SWITCHES       __LUB_REG(LUBBOCK_FPGA_PHYS + 0x050)
 #define LUB_USER_SWITCHES       __LUB_REG(LUBBOCK_FPGA_PHYS + 0x060)
diff --git a/arch/arm/mach-pxa/include/mach/magician.h b/arch/arm/mach-pxa/include/mach/magician.h
index 38d68d99f585..82a399f3f9f2 100644
--- a/arch/arm/mach-pxa/include/mach/magician.h
+++ b/arch/arm/mach-pxa/include/mach/magician.h
@@ -69,7 +69,7 @@
 #define IRQ_MAGICIAN_SD         (IRQ_BOARD_START + 0)
 #define IRQ_MAGICIAN_EP         (IRQ_BOARD_START + 1)
 #define IRQ_MAGICIAN_BT         (IRQ_BOARD_START + 2)
-#define IRQ_MAGICIAN_AC         (IRQ_BOARD_START + 3)
+#define IRQ_MAGICIAN_VBUS       (IRQ_BOARD_START + 3)
 
 /*
  * CPLD EGPIOs
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
index a72869b73ee3..b13dc0269a6d 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
@@ -1,7 +1,6 @@
 #ifndef __ASM_ARCH_MFP_PXA25X_H
 #define __ASM_ARCH_MFP_PXA25X_H
 
-#include <mach/mfp.h>
 #include <mach/mfp-pxa2xx.h>
 
 /* GPIO */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
index da4f85a4f990..6543c05f47ed 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
@@ -8,7 +8,6 @@
  * specific controller, and this should work in most cases.
  */
 
-#include <mach/mfp.h>
 #include <mach/mfp-pxa2xx.h>
 
 /* Note: GPIO3/GPIO4 will be driven by Power I2C when PCFR/PI2C_EN
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
index 3e9211591e20..658b28ed129b 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
@@ -1,7 +1,7 @@
 #ifndef __ASM_ARCH_MFP_PXA2XX_H
 #define __ASM_ARCH_MFP_PXA2XX_H
 
-#include <mach/mfp.h>
+#include <plat/mfp.h>
 
 /*
  * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx:
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa300.h b/arch/arm/mach-pxa/include/mach/mfp-pxa300.h
index bc1fb33a6e70..ae8441192ef0 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa300.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa300.h
@@ -15,7 +15,6 @@
 #ifndef __ASM_ARCH_MFP_PXA300_H
 #define __ASM_ARCH_MFP_PXA300_H
 
-#include <mach/mfp.h>
 #include <mach/mfp-pxa3xx.h>
 
 /* GPIO */
@@ -41,6 +40,7 @@
 #endif
 
 /* Chip Select */
+#define GPIO1_nCS2              MFP_CFG(GPIO1,  AF1)
 #define GPIO2_nCS3              MFP_CFG(GPIO2,  AF1)
 
 /* AC97 */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa320.h b/arch/arm/mach-pxa/include/mach/mfp-pxa320.h
index 67f8385ea548..07897e61d05a 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa320.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa320.h
@@ -15,7 +15,6 @@
 #ifndef __ASM_ARCH_MFP_PXA320_H
 #define __ASM_ARCH_MFP_PXA320_H
 
-#include <mach/mfp.h>
 #include <mach/mfp-pxa3xx.h>
 
 /* GPIO */
@@ -38,6 +37,7 @@
 #define GPIO17_2_GPIO           MFP_CFG(GPIO17_2, AF0)
 
 /* Chip Select */
+#define GPIO3_nCS2              MFP_CFG(GPIO3, AF1)
 #define GPIO4_nCS3              MFP_CFG(GPIO4, AF1)
 
 /* AC97 */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h
index 1f6b35c015d0..d375195d982b 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h
@@ -1,68 +1,9 @@
 #ifndef __ASM_ARCH_MFP_PXA3XX_H
 #define __ASM_ARCH_MFP_PXA3XX_H
 
-#define MFPR_BASE       (0x40e10000)
-#define MFPR_SIZE       (PAGE_SIZE)
-
-/* MFPR register bit definitions */
-#define MFPR_PULL_SEL           (0x1 << 15)
-#define MFPR_PULLUP_EN          (0x1 << 14)
-#define MFPR_PULLDOWN_EN        (0x1 << 13)
-#define MFPR_SLEEP_SEL          (0x1 << 9)
-#define MFPR_SLEEP_OE_N         (0x1 << 7)
-#define MFPR_EDGE_CLEAR         (0x1 << 6)
-#define MFPR_EDGE_FALL_EN       (0x1 << 5)
-#define MFPR_EDGE_RISE_EN       (0x1 << 4)
-
-#define MFPR_SLEEP_DATA(x)      ((x) << 8)
-#define MFPR_DRIVE(x)           (((x) & 0x7) << 10)
-#define MFPR_AF_SEL(x)          (((x) & 0x7) << 0)
+#include <plat/mfp.h>
 
-#define MFPR_EDGE_NONE          (0)
-#define MFPR_EDGE_RISE          (MFPR_EDGE_RISE_EN)
-#define MFPR_EDGE_FALL          (MFPR_EDGE_FALL_EN)
-#define MFPR_EDGE_BOTH          (MFPR_EDGE_RISE | MFPR_EDGE_FALL)
-
-/*
- * Table that determines the low power modes outputs, with actual settings
- * used in parentheses for don't-care values. Except for the float output,
- * the configured driven and pulled levels match, so if there is a need for
- * non-LPM pulled output, the same configuration could probably be used.
- *
- * Output value  sleep_oe_n  sleep_data  pullup_en  pulldown_en  pull_sel
- *                 (bit 7)    (bit 8)    (bit 14)     (bit 13)   (bit 15)
- *
- * Input            0          X(0)        X(0)        X(0)       0
- * Drive 0          0          0           0           X(1)       0
- * Drive 1          0          1           X(1)        0          0
- * Pull hi (1)      1          X(1)        1           0          0
- * Pull lo (0)      1          X(0)        0           1          0
- * Z (float)        1          X(0)        0           0          0
- */
-#define MFPR_LPM_INPUT          (0)
-#define MFPR_LPM_DRIVE_LOW      (MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN)
-#define MFPR_LPM_DRIVE_HIGH     (MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN)
-#define MFPR_LPM_PULL_LOW       (MFPR_LPM_DRIVE_LOW  | MFPR_SLEEP_OE_N)
-#define MFPR_LPM_PULL_HIGH      (MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N)
-#define MFPR_LPM_FLOAT          (MFPR_SLEEP_OE_N)
-#define MFPR_LPM_MASK           (0xe080)
-
-/*
- * The pullup and pulldown state of the MFP pin at run mode is by default
- * determined by the selected alternate function. In case that some buggy
- * devices need to override this default behavior,  the definitions below
- * indicates the setting of corresponding MFPR bits
- *
- * Definition       pull_sel  pullup_en  pulldown_en
- * MFPR_PULL_NONE       0         0        0
- * MFPR_PULL_LOW        1         0        1
- * MFPR_PULL_HIGH       1         1        0
- * MFPR_PULL_BOTH       1         1        1
- */
-#define MFPR_PULL_NONE          (0)
-#define MFPR_PULL_LOW           (MFPR_PULL_SEL | MFPR_PULLDOWN_EN)
-#define MFPR_PULL_BOTH          (MFPR_PULL_LOW | MFPR_PULLUP_EN)
-#define MFPR_PULL_HIGH          (MFPR_PULL_SEL | MFPR_PULLUP_EN)
+#define MFPR_BASE       (0x40e10000)
 
 /* PXA3xx common MFP configurations - processor specific ones defined
  * in mfp-pxa300.h and mfp-pxa320.h
@@ -197,56 +138,21 @@
 #define GPIO5_2_GPIO            MFP_CFG(GPIO5_2, AF0)
 #define GPIO6_2_GPIO            MFP_CFG(GPIO6_2, AF0)
 
-/*
- * each MFP pin will have a MFPR register, since the offset of the
- * register varies between processors, the processor specific code
- * should initialize the pin offsets by pxa3xx_mfp_init_addr()
- *
- * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map"
- * structure, which represents a range of MFP pins from "start" to
- * "end", with the offset begining at "offset", to define a single
- * pin, let "end" = -1
- *
- * use
- *
- * MFP_ADDR_X() to define a range of pins
- * MFP_ADDR()   to define a single pin
- * MFP_ADDR_END to signal the end of pin offset definitions
- */
-struct pxa3xx_mfp_addr_map {
-        unsigned int    start;
-        unsigned int    end;
-        unsigned long   offset;
-};
-
-#define MFP_ADDR_X(start, end, offset) \
-        { MFP_PIN_##start, MFP_PIN_##end, offset }
-
-#define MFP_ADDR(pin, offset) \
-        { MFP_PIN_##pin, -1, offset }
-
-#define MFP_ADDR_END    { MFP_PIN_INVALID, 0 }
-
-/*
- * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access
- * to the MFPR register
- */
-unsigned long pxa3xx_mfp_read(int mfp);
-void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val);
-
-/*
- * pxa3xx_mfp_config - configure the MFPR registers
- *
- * used by board specific initialization code
- */
-void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num);
-
-/*
- * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin
- * index and MFPR register offset
- *
- * used by processor specific code
+/* NOTE: usage of these two functions is not recommended,
+ * use pxa3xx_mfp_config() instead.
  */
-void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *);
-void __init pxa3xx_init_mfp(void);
+static inline unsigned long pxa3xx_mfp_read(int mfp)
+{
+        return mfp_read(mfp);
+}
+
+static inline void pxa3xx_mfp_write(int mfp, unsigned long val)
+{
+        mfp_write(mfp, val);
+}
+
+static inline void pxa3xx_mfp_config(unsigned long *mfp_cfg, int num)
+{
+        mfp_config(mfp_cfg, num);
+}
 #endif /* __ASM_ARCH_MFP_PXA3XX_H */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
index fa73f56a1372..0d119d3b9221 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
@@ -13,7 +13,6 @@
 #ifndef __ASM_ARCH_MFP_PXA9xx_H
 #define __ASM_ARCH_MFP_PXA9xx_H
 
-#include <mach/mfp.h>
 #include <mach/mfp-pxa3xx.h>
 
 /* GPIO */
diff --git a/arch/arm/mach-pxa/include/mach/mtd-xip.h b/arch/arm/mach-pxa/include/mach/mtd-xip.h
index cfca8155be72..297387ec3618 100644
--- a/arch/arm/mach-pxa/include/mach/mtd-xip.h
+++ b/arch/arm/mach-pxa/include/mach/mtd-xip.h
@@ -15,8 +15,8 @@
 #ifndef __ARCH_PXA_MTD_XIP_H__
 #define __ARCH_PXA_MTD_XIP_H__
 
-#include <mach/hardware.h>
-#include <mach/pxa-regs.h>
+#include <mach/regs-ost.h>
+#include <mach/regs-intc.h>
 
 #define xip_irqpending()        (ICIP & ICMR)
 
diff --git a/arch/arm/mach-pxa/include/mach/palmld.h b/arch/arm/mach-pxa/include/mach/palmld.h
new file mode 100644
index 000000000000..7c295a48d784
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/palmld.h
@@ -0,0 +1,109 @@
+/*
+ * GPIOs and interrupts for Palm LifeDrive Handheld Computer
+ *
+ * Authors:     Alex Osborne <ato@meshy.org>
+ *              Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _INCLUDE_PALMLD_H_
+#define _INCLUDE_PALMLD_H_
+
+/** HERE ARE GPIOs **/
+
+/* GPIOs */
+#define GPIO_NR_PALMLD_GPIO_RESET       1
+#define GPIO_NR_PALMLD_POWER_DETECT     4
+#define GPIO_NR_PALMLD_HOTSYNC_BUTTON_N 10
+#define GPIO_NR_PALMLD_POWER_SWITCH     12
+#define GPIO_NR_PALMLD_EARPHONE_DETECT  13
+#define GPIO_NR_PALMLD_LOCK_SWITCH      15
+
+/* SD/MMC */
+#define GPIO_NR_PALMLD_SD_DETECT_N      14
+#define GPIO_NR_PALMLD_SD_POWER         114
+#define GPIO_NR_PALMLD_SD_READONLY      116
+
+/* TOUCHSCREEN */
+#define GPIO_NR_PALMLD_WM9712_IRQ       27
+
+/* IRDA */
+#define GPIO_NR_PALMLD_IR_DISABLE       108
+
+/* LCD/BACKLIGHT */
+#define GPIO_NR_PALMLD_BL_POWER         19
+#define GPIO_NR_PALMLD_LCD_POWER        96
+
+/* LCD BORDER */
+#define GPIO_NR_PALMLD_BORDER_SWITCH    21
+#define GPIO_NR_PALMLD_BORDER_SELECT    22
+
+/* BLUETOOTH */
+#define GPIO_NR_PALMLD_BT_POWER         17
+#define GPIO_NR_PALMLD_BT_RESET         83
+
+/* PCMCIA (WiFi) */
+#define GPIO_NR_PALMLD_PCMCIA_READY     38
+#define GPIO_NR_PALMLD_PCMCIA_POWER     36
+#define GPIO_NR_PALMLD_PCMCIA_RESET     81
+
+/* LEDs */
+#define GPIO_NR_PALMLD_LED_GREEN        52
+#define GPIO_NR_PALMLD_LED_AMBER        94
+
+/* IDE */
+#define GPIO_NR_PALMLD_IDE_IRQ          95
+#define GPIO_NR_PALMLD_IDE_RESET        98
+#define GPIO_NR_PALMLD_IDE_PWEN         115
+
+/* USB */
+#define GPIO_NR_PALMLD_USB_DETECT_N     3
+#define GPIO_NR_PALMLD_USB_READY        86
+#define GPIO_NR_PALMLD_USB_RESET        88
+#define GPIO_NR_PALMLD_USB_INT          106
+#define GPIO_NR_PALMLD_USB_POWER        118
+/* 20, 53 and 86 are usb related too */
+
+/* INTERRUPTS */
+#define IRQ_GPIO_PALMLD_GPIO_RESET      IRQ_GPIO(GPIO_NR_PALMLD_GPIO_RESET)
+#define IRQ_GPIO_PALMLD_SD_DETECT_N     IRQ_GPIO(GPIO_NR_PALMLD_SD_DETECT_N)
+#define IRQ_GPIO_PALMLD_WM9712_IRQ      IRQ_GPIO(GPIO_NR_PALMLD_WM9712_IRQ)
+#define IRQ_GPIO_PALMLD_IDE_IRQ         IRQ_GPIO(GPIO_NR_PALMLD_IDE_IRQ)
+
+
+/** HERE ARE INIT VALUES **/
+
+/* IO mappings */
+#define PALMLD_USB_PHYS         PXA_CS2_PHYS
+#define PALMLD_USB_VIRT         0xf0000000
+#define PALMLD_USB_SIZE         0x00100000
+
+#define PALMLD_IDE_PHYS         0x20000000
+#define PALMLD_IDE_VIRT         0xf1000000
+#define PALMLD_IDE_SIZE         0x00100000
+
+#define PALMLD_PHYS_IO_START    0x40000000
+
+/* BATTERY */
+#define PALMLD_BAT_MAX_VOLTAGE          4000    /* 4.00V maximum voltage */
+#define PALMLD_BAT_MIN_VOLTAGE          3550    /* 3.55V critical voltage */
+#define PALMLD_BAT_MAX_CURRENT          0       /* unknokn */
+#define PALMLD_BAT_MIN_CURRENT          0       /* unknown */
+#define PALMLD_BAT_MAX_CHARGE           1       /* unknown */
+#define PALMLD_BAT_MIN_CHARGE           1       /* unknown */
+#define PALMLD_MAX_LIFE_MINS            240     /* on-life in minutes */
+
+#define PALMLD_BAT_MEASURE_DELAY        (HZ * 1)
+
+/* BACKLIGHT */
+#define PALMLD_MAX_INTENSITY            0xFE
+#define PALMLD_DEFAULT_INTENSITY        0x7E
+#define PALMLD_LIMIT_MASK               0x7F
+#define PALMLD_PRESCALER                0x3F
+#define PALMLD_PERIOD_NS                3500
+
+#endif
diff --git a/arch/arm/mach-pxa/include/mach/palmt5.h b/arch/arm/mach-pxa/include/mach/palmt5.h
new file mode 100644
index 000000000000..94db2881f048
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/palmt5.h
@@ -0,0 +1,84 @@
+/*
+ * GPIOs and interrupts for Palm Tungsten|T5 Handheld Computer
+ *
+ * Authors:     Ales Snuparek <snuparek@atlas.cz>
+ *              Marek Vasut <marek.vasut@gmail.com>
+ *              Justin Kendrick <twilightsentry@gmail.com>
+ *              RichardT5 <richard_t5@users.sourceforge.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _INCLUDE_PALMT5_H_
+#define _INCLUDE_PALMT5_H_
+
+/** HERE ARE GPIOs **/
+
+/* GPIOs */
+#define GPIO_NR_PALMT5_GPIO_RESET               1
+
+#define GPIO_NR_PALMT5_POWER_DETECT             90
+#define GPIO_NR_PALMT5_HOTSYNC_BUTTON_N         10
+#define GPIO_NR_PALMT5_EARPHONE_DETECT          107
+
+/* SD/MMC */
+#define GPIO_NR_PALMT5_SD_DETECT_N              14
+#define GPIO_NR_PALMT5_SD_POWER                 114
+#define GPIO_NR_PALMT5_SD_READONLY              115
+
+/* TOUCHSCREEN */
+#define GPIO_NR_PALMT5_WM9712_IRQ               27
+
+/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */
+#define GPIO_NR_PALMT5_IR_DISABLE               40
+
+/* USB */
+#define GPIO_NR_PALMT5_USB_DETECT_N             15
+#define GPIO_NR_PALMT5_USB_POWER                95
+#define GPIO_NR_PALMT5_USB_PULLUP               93
+
+/* LCD/BACKLIGHT */
+#define GPIO_NR_PALMT5_BL_POWER                 84
+#define GPIO_NR_PALMT5_LCD_POWER                96
+
+/* BLUETOOTH */
+#define GPIO_NR_PALMT5_BT_POWER                 17
+#define GPIO_NR_PALMT5_BT_RESET                 83
+
+/* INTERRUPTS */
+#define IRQ_GPIO_PALMT5_SD_DETECT_N     IRQ_GPIO(GPIO_NR_PALMT5_SD_DETECT_N)
+#define IRQ_GPIO_PALMT5_WM9712_IRQ      IRQ_GPIO(GPIO_NR_PALMT5_WM9712_IRQ)
+#define IRQ_GPIO_PALMT5_USB_DETECT      IRQ_GPIO(GPIO_NR_PALMT5_USB_DETECT)
+#define IRQ_GPIO_PALMT5_GPIO_RESET      IRQ_GPIO(GPIO_NR_PALMT5_GPIO_RESET)
+
+/** HERE ARE INIT VALUES **/
+
+/* Various addresses  */
+#define PALMT5_PHYS_RAM_START   0xa0000000
+#define PALMT5_PHYS_IO_START    0x40000000
+
+/* TOUCHSCREEN */
+#define AC97_LINK_FRAME         21
+
+/* BATTERY */
+#define PALMT5_BAT_MAX_VOLTAGE          4000    /* 4.00v current voltage */
+#define PALMT5_BAT_MIN_VOLTAGE          3550    /* 3.55v critical voltage */
+#define PALMT5_BAT_MAX_CURRENT          0       /* unknokn */
+#define PALMT5_BAT_MIN_CURRENT          0       /* unknown */
+#define PALMT5_BAT_MAX_CHARGE           1       /* unknown */
+#define PALMT5_BAT_MIN_CHARGE           1       /* unknown */
+#define PALMT5_MAX_LIFE_MINS            360    /* on-life in minutes */
+
+#define PALMT5_BAT_MEASURE_DELAY        (HZ * 1)
+
+/* BACKLIGHT */
+#define PALMT5_MAX_INTENSITY            0xFE
+#define PALMT5_DEFAULT_INTENSITY        0x7E
+#define PALMT5_LIMIT_MASK               0x7F
+#define PALMT5_PRESCALER                0x3F
+#define PALMT5_PERIOD_NS                3500
+
+#endif
diff --git a/arch/arm/mach-pxa/include/mach/pm.h b/arch/arm/mach-pxa/include/mach/pm.h
index 83342469acac..a6eeef8a075f 100644
--- a/arch/arm/mach-pxa/include/mach/pm.h
+++ b/arch/arm/mach-pxa/include/mach/pm.h
@@ -27,3 +27,13 @@ extern void pxa27x_cpu_suspend(unsigned int);
 extern void pxa_cpu_resume(void);
 
 extern int pxa_pm_enter(suspend_state_t state);
+
+/* NOTE: this is for PM debugging on Lubbock,  it's really a big
+ * ugly, but let's keep the crap minimum here, instead of direct
+ * accessing the LUBBOCK CPLD registers in arch/arm/mach-pxa/pm.c
+ */
+#ifdef CONFIG_ARCH_LUBBOCK
+extern void lubbock_set_hexled(uint32_t value);
+#else
+#define lubbock_set_hexled(x)
+#endif
diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h
deleted file mode 100644
index 31d615aa7723..000000000000
--- a/arch/arm/mach-pxa/include/mach/pxa-regs.h
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- *  arch/arm/mach-pxa/include/mach/pxa-regs.h
- *
- *  Author:     Nicolas Pitre
- *  Created:    Jun 15, 2001
- *  Copyright:  MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __PXA_REGS_H
-#define __PXA_REGS_H
-
-#include <mach/hardware.h>
-
-/*
- * PXA Chip selects
- */
-
-#define PXA_CS0_PHYS    0x00000000
-#define PXA_CS1_PHYS    0x04000000
-#define PXA_CS2_PHYS    0x08000000
-#define PXA_CS3_PHYS    0x0C000000
-#define PXA_CS4_PHYS    0x10000000
-#define PXA_CS5_PHYS    0x14000000
-
-
-/*
- * Personal Computer Memory Card International Association (PCMCIA) sockets
- */
-
-#define PCMCIAPrtSp     0x04000000      /* PCMCIA Partition Space [byte]   */
-#define PCMCIASp        (4*PCMCIAPrtSp) /* PCMCIA Space [byte]             */
-#define PCMCIAIOSp      PCMCIAPrtSp     /* PCMCIA I/O Space [byte]         */
-#define PCMCIAAttrSp    PCMCIAPrtSp     /* PCMCIA Attribute Space [byte]   */
-#define PCMCIAMemSp     PCMCIAPrtSp     /* PCMCIA Memory Space [byte]      */
-
-#define PCMCIA0Sp       PCMCIASp        /* PCMCIA 0 Space [byte]           */
-#define PCMCIA0IOSp     PCMCIAIOSp      /* PCMCIA 0 I/O Space [byte]       */
-#define PCMCIA0AttrSp   PCMCIAAttrSp    /* PCMCIA 0 Attribute Space [byte] */
-#define PCMCIA0MemSp    PCMCIAMemSp     /* PCMCIA 0 Memory Space [byte]    */
-
-#define PCMCIA1Sp       PCMCIASp        /* PCMCIA 1 Space [byte]           */
-#define PCMCIA1IOSp     PCMCIAIOSp      /* PCMCIA 1 I/O Space [byte]       */
-#define PCMCIA1AttrSp   PCMCIAAttrSp    /* PCMCIA 1 Attribute Space [byte] */
-#define PCMCIA1MemSp    PCMCIAMemSp     /* PCMCIA 1 Memory Space [byte]    */
-
-#define _PCMCIA(Nb)                     /* PCMCIA [0..1]                   */ \
-                        (0x20000000 + (Nb)*PCMCIASp)
-#define _PCMCIAIO(Nb)   _PCMCIA (Nb)    /* PCMCIA I/O [0..1]               */
-#define _PCMCIAAttr(Nb)                 /* PCMCIA Attribute [0..1]         */ \
-                        (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
-#define _PCMCIAMem(Nb)                  /* PCMCIA Memory [0..1]            */ \
-                        (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
-
-#define _PCMCIA0        _PCMCIA (0)     /* PCMCIA 0                        */
-#define _PCMCIA0IO      _PCMCIAIO (0)   /* PCMCIA 0 I/O                    */
-#define _PCMCIA0Attr    _PCMCIAAttr (0) /* PCMCIA 0 Attribute              */
-#define _PCMCIA0Mem     _PCMCIAMem (0)  /* PCMCIA 0 Memory                 */
-
-#define _PCMCIA1        _PCMCIA (1)     /* PCMCIA 1                        */
-#define _PCMCIA1IO      _PCMCIAIO (1)   /* PCMCIA 1 I/O                    */
-#define _PCMCIA1Attr    _PCMCIAAttr (1) /* PCMCIA 1 Attribute              */
-#define _PCMCIA1Mem     _PCMCIAMem (1)  /* PCMCIA 1 Memory                 */
-
-
-
-/*
- * DMA Controller
- */
-#define DCSR(x)         __REG2(0x40000000, (x) << 2)
-
-#define DCSR_RUN        (1 << 31)       /* Run Bit (read / write) */
-#define DCSR_NODESC     (1 << 30)       /* No-Descriptor Fetch (read / write) */
-#define DCSR_STOPIRQEN  (1 << 29)       /* Stop Interrupt Enable (read / write) */
-#define DCSR_REQPEND    (1 << 8)        /* Request Pending (read-only) */
-#define DCSR_STOPSTATE  (1 << 3)        /* Stop State (read-only) */
-#define DCSR_ENDINTR    (1 << 2)        /* End Interrupt (read / write) */
-#define DCSR_STARTINTR  (1 << 1)        /* Start Interrupt (read / write) */
-#define DCSR_BUSERR     (1 << 0)        /* Bus Error Interrupt (read / write) */
-
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-#define DCSR_EORIRQEN   (1 << 28)       /* End of Receive Interrupt Enable (R/W) */
-#define DCSR_EORJMPEN   (1 << 27)       /* Jump to next descriptor on EOR */
-#define DCSR_EORSTOPEN  (1 << 26)       /* STOP on an EOR */
-#define DCSR_SETCMPST   (1 << 25)       /* Set Descriptor Compare Status */
-#define DCSR_CLRCMPST   (1 << 24)       /* Clear Descriptor Compare Status */
-#define DCSR_CMPST      (1 << 10)       /* The Descriptor Compare Status */
-#define DCSR_EORINTR    (1 << 9)        /* The end of Receive */
-#endif
-
-#define DALGN           __REG(0x400000a0)  /* DMA Alignment Register */
-#define DINT            __REG(0x400000f0)  /* DMA Interrupt Register */
-
-#define DRCMR(n)        (*(((n) < 64) ? \
-                        &__REG2(0x40000100, ((n) & 0x3f) << 2) : \
-                        &__REG2(0x40001100, ((n) & 0x3f) << 2)))
-
-#define DRCMR_MAPVLD    (1 << 7)        /* Map Valid (read / write) */
-#define DRCMR_CHLNUM    0x1f            /* mask for Channel Number (read / write) */
-
-#define DDADR(x)        __REG2(0x40000200, (x) << 4)
-#define DSADR(x)        __REG2(0x40000204, (x) << 4)
-#define DTADR(x)        __REG2(0x40000208, (x) << 4)
-#define DCMD(x)         __REG2(0x4000020c, (x) << 4)
-
-#define DDADR_DESCADDR  0xfffffff0      /* Address of next descriptor (mask) */
-#define DDADR_STOP      (1 << 0)        /* Stop (read / write) */
-
-#define DCMD_INCSRCADDR (1 << 31)       /* Source Address Increment Setting. */
-#define DCMD_INCTRGADDR (1 << 30)       /* Target Address Increment Setting. */
-#define DCMD_FLOWSRC    (1 << 29)       /* Flow Control by the source. */
-#define DCMD_FLOWTRG    (1 << 28)       /* Flow Control by the target. */
-#define DCMD_STARTIRQEN (1 << 22)       /* Start Interrupt Enable */
-#define DCMD_ENDIRQEN   (1 << 21)       /* End Interrupt Enable */
-#define DCMD_ENDIAN     (1 << 18)       /* Device Endian-ness. */
-#define DCMD_BURST8     (1 << 16)       /* 8 byte burst */
-#define DCMD_BURST16    (2 << 16)       /* 16 byte burst */
-#define DCMD_BURST32    (3 << 16)       /* 32 byte burst */
-#define DCMD_WIDTH1     (1 << 14)       /* 1 byte width */
-#define DCMD_WIDTH2     (2 << 14)       /* 2 byte width (HalfWord) */
-#define DCMD_WIDTH4     (3 << 14)       /* 4 byte width (Word) */
-#define DCMD_LENGTH     0x01fff         /* length mask (max = 8K - 1) */
-
-/*
- * Real Time Clock
- */
-
-#define RCNR            __REG(0x40900000)  /* RTC Count Register */
-#define RTAR            __REG(0x40900004)  /* RTC Alarm Register */
-#define RTSR            __REG(0x40900008)  /* RTC Status Register */
-#define RTTR            __REG(0x4090000C)  /* RTC Timer Trim Register */
-#define PIAR            __REG(0x40900038)  /* Periodic Interrupt Alarm Register */
-
-#define RTSR_PICE       (1 << 15)       /* Periodic interrupt count enable */
-#define RTSR_PIALE      (1 << 14)       /* Periodic interrupt Alarm enable */
-#define RTSR_HZE        (1 << 3)        /* HZ interrupt enable */
-#define RTSR_ALE        (1 << 2)        /* RTC alarm interrupt enable */
-#define RTSR_HZ         (1 << 1)        /* HZ rising-edge detected */
-#define RTSR_AL         (1 << 0)        /* RTC alarm detected */
-
-
-/*
- * OS Timer & Match Registers
- */
-
-#define OSMR0           __REG(0x40A00000)  /* */
-#define OSMR1           __REG(0x40A00004)  /* */
-#define OSMR2           __REG(0x40A00008)  /* */
-#define OSMR3           __REG(0x40A0000C)  /* */
-#define OSMR4           __REG(0x40A00080)  /* */
-#define OSCR            __REG(0x40A00010)  /* OS Timer Counter Register */
-#define OSCR4           __REG(0x40A00040)  /* OS Timer Counter Register */
-#define OMCR4           __REG(0x40A000C0)  /* */
-#define OSSR            __REG(0x40A00014)  /* OS Timer Status Register */
-#define OWER            __REG(0x40A00018)  /* OS Timer Watchdog Enable Register */
-#define OIER            __REG(0x40A0001C)  /* OS Timer Interrupt Enable Register */
-
-#define OSSR_M3         (1 << 3)        /* Match status channel 3 */
-#define OSSR_M2         (1 << 2)        /* Match status channel 2 */
-#define OSSR_M1         (1 << 1)        /* Match status channel 1 */
-#define OSSR_M0         (1 << 0)        /* Match status channel 0 */
-
-#define OWER_WME        (1 << 0)        /* Watchdog Match Enable */
-
-#define OIER_E3         (1 << 3)        /* Interrupt enable channel 3 */
-#define OIER_E2         (1 << 2)        /* Interrupt enable channel 2 */
-#define OIER_E1         (1 << 1)        /* Interrupt enable channel 1 */
-#define OIER_E0         (1 << 0)        /* Interrupt enable channel 0 */
-
-
-/*
- * Interrupt Controller
- */
-
-#define ICIP            __REG(0x40D00000)  /* Interrupt Controller IRQ Pending Register */
-#define ICMR            __REG(0x40D00004)  /* Interrupt Controller Mask Register */
-#define ICLR            __REG(0x40D00008)  /* Interrupt Controller Level Register */
-#define ICFP            __REG(0x40D0000C)  /* Interrupt Controller FIQ Pending Register */
-#define ICPR            __REG(0x40D00010)  /* Interrupt Controller Pending Register */
-#define ICCR            __REG(0x40D00014)  /* Interrupt Controller Control Register */
-
-#define ICIP2           __REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
-#define ICMR2           __REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
-#define ICLR2           __REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
-#define ICFP2           __REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
-#define ICPR2           __REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
-
-/*
- * General Purpose I/O
- */
-
-#define GPLR0           __REG(0x40E00000)  /* GPIO Pin-Level Register GPIO<31:0> */
-#define GPLR1           __REG(0x40E00004)  /* GPIO Pin-Level Register GPIO<63:32> */
-#define GPLR2           __REG(0x40E00008)  /* GPIO Pin-Level Register GPIO<80:64> */
-
-#define GPDR0           __REG(0x40E0000C)  /* GPIO Pin Direction Register GPIO<31:0> */
-#define GPDR1           __REG(0x40E00010)  /* GPIO Pin Direction Register GPIO<63:32> */
-#define GPDR2           __REG(0x40E00014)  /* GPIO Pin Direction Register GPIO<80:64> */
-
-#define GPSR0           __REG(0x40E00018)  /* GPIO Pin Output Set Register GPIO<31:0> */
-#define GPSR1           __REG(0x40E0001C)  /* GPIO Pin Output Set Register GPIO<63:32> */
-#define GPSR2           __REG(0x40E00020)  /* GPIO Pin Output Set Register GPIO<80:64> */
-
-#define GPCR0           __REG(0x40E00024)  /* GPIO Pin Output Clear Register GPIO<31:0> */
-#define GPCR1           __REG(0x40E00028)  /* GPIO Pin Output Clear Register GPIO <63:32> */
-#define GPCR2           __REG(0x40E0002C)  /* GPIO Pin Output Clear Register GPIO <80:64> */
-
-#define GRER0           __REG(0x40E00030)  /* GPIO Rising-Edge Detect Register GPIO<31:0> */
-#define GRER1           __REG(0x40E00034)  /* GPIO Rising-Edge Detect Register GPIO<63:32> */
-#define GRER2           __REG(0x40E00038)  /* GPIO Rising-Edge Detect Register GPIO<80:64> */
-
-#define GFER0           __REG(0x40E0003C)  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
-#define GFER1           __REG(0x40E00040)  /* GPIO Falling-Edge Detect Register GPIO<63:32> */
-#define GFER2           __REG(0x40E00044)  /* GPIO Falling-Edge Detect Register GPIO<80:64> */
-
-#define GEDR0           __REG(0x40E00048)  /* GPIO Edge Detect Status Register GPIO<31:0> */
-#define GEDR1           __REG(0x40E0004C)  /* GPIO Edge Detect Status Register GPIO<63:32> */
-#define GEDR2           __REG(0x40E00050)  /* GPIO Edge Detect Status Register GPIO<80:64> */
-
-#define GAFR0_L         __REG(0x40E00054)  /* GPIO Alternate Function Select Register GPIO<15:0> */
-#define GAFR0_U         __REG(0x40E00058)  /* GPIO Alternate Function Select Register GPIO<31:16> */
-#define GAFR1_L         __REG(0x40E0005C)  /* GPIO Alternate Function Select Register GPIO<47:32> */
-#define GAFR1_U         __REG(0x40E00060)  /* GPIO Alternate Function Select Register GPIO<63:48> */
-#define GAFR2_L         __REG(0x40E00064)  /* GPIO Alternate Function Select Register GPIO<79:64> */
-#define GAFR2_U         __REG(0x40E00068)  /* GPIO Alternate Function Select Register GPIO<95-80> */
-#define GAFR3_L         __REG(0x40E0006C)  /* GPIO Alternate Function Select Register GPIO<111:96> */
-#define GAFR3_U         __REG(0x40E00070)  /* GPIO Alternate Function Select Register GPIO<127:112> */
-
-#define GPLR3           __REG(0x40E00100)  /* GPIO Pin-Level Register GPIO<127:96> */
-#define GPDR3           __REG(0x40E0010C)  /* GPIO Pin Direction Register GPIO<127:96> */
-#define GPSR3           __REG(0x40E00118)  /* GPIO Pin Output Set Register GPIO<127:96> */
-#define GPCR3           __REG(0x40E00124)  /* GPIO Pin Output Clear Register GPIO<127:96> */
-#define GRER3           __REG(0x40E00130)  /* GPIO Rising-Edge Detect Register GPIO<127:96> */
-#define GFER3           __REG(0x40E0013C)  /* GPIO Falling-Edge Detect Register GPIO<127:96> */
-#define GEDR3           __REG(0x40E00148)  /* GPIO Edge Detect Status Register GPIO<127:96> */
-
-/* More handy macros.  The argument is a literal GPIO number. */
-
-#define GPIO_bit(x)     (1 << ((x) & 0x1f))
-
-#define _GPLR(x)        __REG2(0x40E00000, ((x) & 0x60) >> 3)
-#define _GPDR(x)        __REG2(0x40E0000C, ((x) & 0x60) >> 3)
-#define _GPSR(x)        __REG2(0x40E00018, ((x) & 0x60) >> 3)
-#define _GPCR(x)        __REG2(0x40E00024, ((x) & 0x60) >> 3)
-#define _GRER(x)        __REG2(0x40E00030, ((x) & 0x60) >> 3)
-#define _GFER(x)        __REG2(0x40E0003C, ((x) & 0x60) >> 3)
-#define _GEDR(x)        __REG2(0x40E00048, ((x) & 0x60) >> 3)
-#define _GAFR(x)        __REG2(0x40E00054, ((x) & 0x70) >> 2)
-
-#define GPLR(x)         (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
-#define GPDR(x)         (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
-#define GPSR(x)         (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
-#define GPCR(x)         (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
-#define GRER(x)         (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
-#define GFER(x)         (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
-#define GEDR(x)         (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
-#define GAFR(x)         (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
-                         ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
-
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/pxa25x.h b/arch/arm/mach-pxa/include/mach/pxa25x.h
new file mode 100644
index 000000000000..508c3ba1f4d0
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa25x.h
@@ -0,0 +1,8 @@
+#ifndef __MACH_PXA25x_H
+#define __MACH_PXA25x_H
+
+#include <mach/hardware.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/mfp-pxa25x.h>
+
+#endif /* __MACH_PXA25x_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa27x.h b/arch/arm/mach-pxa/include/mach/pxa27x.h
new file mode 100644
index 000000000000..6876e16c2970
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa27x.h
@@ -0,0 +1,19 @@
+#ifndef __MACH_PXA27x_H
+#define __MACH_PXA27x_H
+
+#include <mach/hardware.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/mfp-pxa27x.h>
+
+#define ARB_CNTRL       __REG(0x48000048)  /* Arbiter Control Register */
+
+#define ARB_DMA_SLV_PARK        (1<<31)    /* Be parked with DMA slave when idle */
+#define ARB_CI_PARK             (1<<30)    /* Be parked with Camera Interface when idle */
+#define ARB_EX_MEM_PARK         (1<<29)    /* Be parked with external MEMC when idle */
+#define ARB_INT_MEM_PARK        (1<<28)    /* Be parked with internal MEMC when idle */
+#define ARB_USB_PARK            (1<<27)    /* Be parked with USB when idle */
+#define ARB_LCD_PARK            (1<<26)    /* Be parked with LCD when idle */
+#define ARB_DMA_PARK            (1<<25)    /* Be parked with DMA when idle */
+#define ARB_CORE_PARK           (1<<24)    /* Be parked with core when idle */
+#define ARB_LOCK_FLAG           (1<<23)    /* Only Locking masters gain access to the bus */
+#endif /* __MACH_PXA27x_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h
index d83393e25273..1209c44aa6f1 100644
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h
+++ b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h
@@ -3,6 +3,8 @@
 
 #warning Please use mfp-pxa2[57]x.h instead of pxa2xx-gpio.h
 
+#include <mach/gpio.h>
+
 /* GPIO alternate function assignments */
 
 #define GPIO1_RST               1       /* reset */
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
index 77102d695cc7..4fcddd9cab76 100644
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
@@ -14,6 +14,19 @@
 #ifndef __PXA2XX_REGS_H
 #define __PXA2XX_REGS_H
 
+#include <mach/hardware.h>
+
+/*
+ * PXA Chip selects
+ */
+
+#define PXA_CS0_PHYS    0x00000000
+#define PXA_CS1_PHYS    0x04000000
+#define PXA_CS2_PHYS    0x08000000
+#define PXA_CS3_PHYS    0x0C000000
+#define PXA_CS4_PHYS    0x10000000
+#define PXA_CS5_PHYS    0x14000000
+
 /*
  * Memory controller
  */
@@ -69,24 +82,6 @@
 #define MDREFR_K0RUN    (1 << 13)       /* SDCLK0 Run Control/Status */
 #define MDREFR_E0PIN    (1 << 12)       /* SDCKE0 Level Control/Status */
 
-
-#ifdef CONFIG_PXA27x
-
-#define ARB_CNTRL       __REG(0x48000048)  /* Arbiter Control Register */
-
-#define ARB_DMA_SLV_PARK        (1<<31)    /* Be parked with DMA slave when idle */
-#define ARB_CI_PARK             (1<<30)    /* Be parked with Camera Interface when idle */
-#define ARB_EX_MEM_PARK         (1<<29)    /* Be parked with external MEMC when idle */
-#define ARB_INT_MEM_PARK        (1<<28)    /* Be parked with internal MEMC when idle */
-#define ARB_USB_PARK            (1<<27)    /* Be parked with USB when idle */
-#define ARB_LCD_PARK            (1<<26)    /* Be parked with LCD when idle */
-#define ARB_DMA_PARK            (1<<25)    /* Be parked with DMA when idle */
-#define ARB_CORE_PARK           (1<<24)    /* Be parked with core when idle */
-#define ARB_LOCK_FLAG           (1<<23)    /* Only Locking masters gain access to the bus */
-
-#endif
-
-
 /*
  * Power Manager
  */
diff --git a/arch/arm/mach-pxa/include/mach/pxa300.h b/arch/arm/mach-pxa/include/mach/pxa300.h
new file mode 100644
index 000000000000..2f33076c9e48
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa300.h
@@ -0,0 +1,8 @@
+#ifndef __MACH_PXA300_H
+#define __MACH_PXA300_H
+
+#include <mach/hardware.h>
+#include <mach/pxa3xx-regs.h>
+#include <mach/mfp-pxa300.h>
+
+#endif /* __MACH_PXA300_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa320.h b/arch/arm/mach-pxa/include/mach/pxa320.h
new file mode 100644
index 000000000000..cab78e903273
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa320.h
@@ -0,0 +1,9 @@
+#ifndef __MACH_PXA320_H
+#define __MACH_PXA320_H
+
+#include <mach/hardware.h>
+#include <mach/pxa3xx-regs.h>
+#include <mach/mfp-pxa320.h>
+
+#endif /* __MACH_PXA320_H */
+
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
index bcf3fb2c4b3a..7d1a059b3d43 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
@@ -13,6 +13,17 @@
 #ifndef __ASM_ARCH_PXA3XX_REGS_H
 #define __ASM_ARCH_PXA3XX_REGS_H
 
+#include <mach/hardware.h>
+
+/*
+ * Static Chip Selects
+ */
+
+#define PXA300_CS0_PHYS         (0x00000000)    /* PXA300/PXA310 _only_ */
+#define PXA300_CS1_PHYS         (0x30000000)    /* PXA300/PXA310 _only_ */
+#define PXA3xx_CS2_PHYS         (0x10000000)
+#define PXA3xx_CS3_PHYS         (0x14000000)
+
 /*
  * Oscillator Configuration Register (OSCC)
  */
diff --git a/arch/arm/mach-pxa/include/mach/pxa930.h b/arch/arm/mach-pxa/include/mach/pxa930.h
new file mode 100644
index 000000000000..d45f76a9b54d
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa930.h
@@ -0,0 +1,8 @@
+#ifndef __MACH_PXA930_H
+#define __MACH_PXA930_H
+
+#include <mach/hardware.h>
+#include <mach/pxa3xx-regs.h>
+#include <mach/mfp-pxa930.h>
+
+#endif /* __MACH_PXA930_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-intc.h b/arch/arm/mach-pxa/include/mach/regs-intc.h
new file mode 100644
index 000000000000..ad23e74b762f
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/regs-intc.h
@@ -0,0 +1,23 @@
+#ifndef __ASM_MACH_REGS_INTC_H
+#define __ASM_MACH_REGS_INTC_H
+
+#include <mach/hardware.h>
+
+/*
+ * Interrupt Controller
+ */
+
+#define ICIP            __REG(0x40D00000)  /* Interrupt Controller IRQ Pending Register */
+#define ICMR            __REG(0x40D00004)  /* Interrupt Controller Mask Register */
+#define ICLR            __REG(0x40D00008)  /* Interrupt Controller Level Register */
+#define ICFP            __REG(0x40D0000C)  /* Interrupt Controller FIQ Pending Register */
+#define ICPR            __REG(0x40D00010)  /* Interrupt Controller Pending Register */
+#define ICCR            __REG(0x40D00014)  /* Interrupt Controller Control Register */
+
+#define ICIP2           __REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
+#define ICMR2           __REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
+#define ICLR2           __REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
+#define ICFP2           __REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
+#define ICPR2           __REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
+
+#endif /* __ASM_MACH_REGS_INTC_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-ost.h b/arch/arm/mach-pxa/include/mach/regs-ost.h
new file mode 100644
index 000000000000..a3e5f86ef67e
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/regs-ost.h
@@ -0,0 +1,34 @@
+#ifndef __ASM_MACH_REGS_OST_H
+#define __ASM_MACH_REGS_OST_H
+
+#include <mach/hardware.h>
+
+/*
+ * OS Timer & Match Registers
+ */
+
+#define OSMR0           __REG(0x40A00000)  /* */
+#define OSMR1           __REG(0x40A00004)  /* */
+#define OSMR2           __REG(0x40A00008)  /* */
+#define OSMR3           __REG(0x40A0000C)  /* */
+#define OSMR4           __REG(0x40A00080)  /* */
+#define OSCR            __REG(0x40A00010)  /* OS Timer Counter Register */
+#define OSCR4           __REG(0x40A00040)  /* OS Timer Counter Register */
+#define OMCR4           __REG(0x40A000C0)  /* */
+#define OSSR            __REG(0x40A00014)  /* OS Timer Status Register */
+#define OWER            __REG(0x40A00018)  /* OS Timer Watchdog Enable Register */
+#define OIER            __REG(0x40A0001C)  /* OS Timer Interrupt Enable Register */
+
+#define OSSR_M3         (1 << 3)        /* Match status channel 3 */
+#define OSSR_M2         (1 << 2)        /* Match status channel 2 */
+#define OSSR_M1         (1 << 1)        /* Match status channel 1 */
+#define OSSR_M0         (1 << 0)        /* Match status channel 0 */
+
+#define OWER_WME        (1 << 0)        /* Watchdog Match Enable */
+
+#define OIER_E3         (1 << 3)        /* Interrupt enable channel 3 */
+#define OIER_E2         (1 << 2)        /* Interrupt enable channel 2 */
+#define OIER_E1         (1 << 1)        /* Interrupt enable channel 1 */
+#define OIER_E0         (1 << 0)        /* Interrupt enable channel 0 */
+
+#endif /* __ASM_MACH_REGS_OST_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-rtc.h b/arch/arm/mach-pxa/include/mach/regs-rtc.h
new file mode 100644
index 000000000000..f0e4a589bbe1
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/regs-rtc.h
@@ -0,0 +1,23 @@
+#ifndef __ASM_MACH_REGS_RTC_H
+#define __ASM_MACH_REGS_RTC_H
+
+#include <mach/hardware.h>
+
+/*
+ * Real Time Clock
+ */
+
+#define RCNR            __REG(0x40900000)  /* RTC Count Register */
+#define RTAR            __REG(0x40900004)  /* RTC Alarm Register */
+#define RTSR            __REG(0x40900008)  /* RTC Status Register */
+#define RTTR            __REG(0x4090000C)  /* RTC Timer Trim Register */
+#define PIAR            __REG(0x40900038)  /* Periodic Interrupt Alarm Register */
+
+#define RTSR_PICE       (1 << 15)       /* Periodic interrupt count enable */
+#define RTSR_PIALE      (1 << 14)       /* Periodic interrupt Alarm enable */
+#define RTSR_HZE        (1 << 3)        /* HZ interrupt enable */
+#define RTSR_ALE        (1 << 2)        /* RTC alarm interrupt enable */
+#define RTSR_HZ         (1 << 1)        /* HZ rising-edge detected */
+#define RTSR_AL         (1 << 0)        /* RTC alarm detected */
+
+#endif /* __ASM_MACH_REGS_RTC_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-ssp.h b/arch/arm/mach-pxa/include/mach/regs-ssp.h
index 018f6d65b57b..6a2ed35acd59 100644
--- a/arch/arm/mach-pxa/include/mach/regs-ssp.h
+++ b/arch/arm/mach-pxa/include/mach/regs-ssp.h
@@ -37,7 +37,6 @@
 #if defined(CONFIG_PXA25x)
 #define SSCR0_SCR       (0x0000ff00)    /* Serial Clock Rate (mask) */
 #define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
-
 #elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 #define SSCR0_SCR       (0x000fff00)    /* Serial Clock Rate (mask) */
 #define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
diff --git a/arch/arm/mach-pxa/include/mach/system.h b/arch/arm/mach-pxa/include/mach/system.h
index 0f381e692999..d1fce8b6d105 100644
--- a/arch/arm/mach-pxa/include/mach/system.h
+++ b/arch/arm/mach-pxa/include/mach/system.h
@@ -13,7 +13,6 @@
 #include <asm/proc-fns.h>
 #include "hardware.h"
 #include "pxa2xx-regs.h"
-#include "pxa-regs.h"
 
 static inline void arch_idle(void)
 {
@@ -21,4 +20,4 @@ static inline void arch_idle(void)
 }
 
 
-void arch_reset(char mode);
+void arch_reset(char mode, const char *cmd);
diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h
index f4b029c03957..5706cea95d11 100644
--- a/arch/arm/mach-pxa/include/mach/uncompress.h
+++ b/arch/arm/mach-pxa/include/mach/uncompress.h
@@ -35,7 +35,8 @@ static inline void flush(void)
 
 static inline void arch_decomp_setup(void)
 {
-        if (machine_is_littleton() || machine_is_intelmote2())
+        if (machine_is_littleton() || machine_is_intelmote2()
+                        || machine_is_csb726())
                 UART = STUART;
 }
 
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index fa69c3a6a38e..f6e0300e4f64 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -20,7 +20,8 @@
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
-#include <mach/pxa-regs.h>
+#include <mach/gpio.h>
+#include <mach/regs-intc.h>
 
 #include "generic.h"
 
@@ -51,6 +52,72 @@ static struct irq_chip pxa_internal_irq_chip = {
         .unmask         = pxa_unmask_irq,
 };
 
+/*
+ * GPIO IRQs for GPIO 0 and 1
+ */
+static int pxa_set_low_gpio_type(unsigned int irq, unsigned int type)
+{
+        int gpio = irq - IRQ_GPIO0;
+
+        if (__gpio_is_occupied(gpio)) {
+                pr_err("%s failed: GPIO is configured\n", __func__);
+                return -EINVAL;
+        }
+
+        if (type & IRQ_TYPE_EDGE_RISING)
+                GRER0 |= GPIO_bit(gpio);
+        else
+                GRER0 &= ~GPIO_bit(gpio);
+
+        if (type & IRQ_TYPE_EDGE_FALLING)
+                GFER0 |= GPIO_bit(gpio);
+        else
+                GFER0 &= ~GPIO_bit(gpio);
+
+        return 0;
+}
+
+static void pxa_ack_low_gpio(unsigned int irq)
+{
+        GEDR0 = (1 << (irq - IRQ_GPIO0));
+}
+
+static void pxa_mask_low_gpio(unsigned int irq)
+{
+        ICMR &= ~(1 << (irq - PXA_IRQ(0)));
+}
+
+static void pxa_unmask_low_gpio(unsigned int irq)
+{
+        ICMR |= 1 << (irq - PXA_IRQ(0));
+}
+
+static struct irq_chip pxa_low_gpio_chip = {
+        .name           = "GPIO-l",
+        .ack            = pxa_ack_low_gpio,
+        .mask           = pxa_mask_low_gpio,
+        .unmask         = pxa_unmask_low_gpio,
+        .set_type       = pxa_set_low_gpio_type,
+};
+
+static void __init pxa_init_low_gpio_irq(set_wake_t fn)
+{
+        int irq;
+
+        /* clear edge detection on GPIO 0 and 1 */
+        GFER0 &= ~0x3;
+        GRER0 &= ~0x3;
+        GEDR0 = 0x3;
+
+        for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
+                set_irq_chip(irq, &pxa_low_gpio_chip);
+                set_irq_handler(irq, handle_edge_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+
+        pxa_low_gpio_chip.set_wake = fn;
+}
+
 void __init pxa_init_irq(int irq_nr, set_wake_t fn)
 {
         int irq;
@@ -72,6 +139,7 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn)
         }
 
         pxa_internal_irq_chip.set_wake = fn;
+        pxa_init_low_gpio_irq(fn);
 }
 
 #ifdef CONFIG_PM
diff --git a/arch/arm/mach-pxa/leds-idp.c b/arch/arm/mach-pxa/leds-idp.c
index 18b20d469410..8b9c17142d5a 100644
--- a/arch/arm/mach-pxa/leds-idp.c
+++ b/arch/arm/mach-pxa/leds-idp.c
@@ -18,7 +18,7 @@
 #include <asm/leds.h>
 #include <asm/system.h>
 
-#include <mach/pxa-regs.h>
+#include <mach/pxa25x.h>
 #include <mach/idp.h>
 
 #include "leds.h"
diff --git a/arch/arm/mach-pxa/leds-lubbock.c b/arch/arm/mach-pxa/leds-lubbock.c
index 1a258029c33c..e26d5efe1969 100644
--- a/arch/arm/mach-pxa/leds-lubbock.c
+++ b/arch/arm/mach-pxa/leds-lubbock.c
@@ -16,7 +16,7 @@
 #include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/system.h>
-#include <mach/pxa-regs.h>
+#include <mach/pxa25x.h>
 #include <mach/lubbock.h>
 
 #include "leds.h"
diff --git a/arch/arm/mach-pxa/leds-mainstone.c b/arch/arm/mach-pxa/leds-mainstone.c
index 95e06b849634..db4af5eee8b2 100644
--- a/arch/arm/mach-pxa/leds-mainstone.c
+++ b/arch/arm/mach-pxa/leds-mainstone.c
@@ -16,7 +16,7 @@
 #include <asm/leds.h>
 #include <asm/system.h>
 
-#include <mach/pxa-regs.h>
+#include <mach/pxa27x.h>
 #include <mach/mainstone.h>
 
 #include "leds.h"
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 31da7f3c06f6..e13f6a81c223 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -39,8 +39,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/pxa-regs.h>
-#include <mach/mfp-pxa300.h>
+#include <mach/pxa300.h>
 #include <mach/pxafb.h>
 #include <mach/ssp.h>
 #include <mach/pxa2xx_spi.h>
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index de3f67daaacf..d64395f26a3e 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -38,9 +38,8 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/flash.h>
 
-#include <mach/pxa-regs.h>
-#include <mach/pxa2xx-regs.h>
-#include <mach/mfp-pxa27x.h>
+#include <mach/pxa27x.h>
+#include <mach/gpio.h>
 #include <mach/lpd270.h>
 #include <mach/audio.h>
 #include <mach/pxafb.h>
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index bff704354c1a..f04c8333dff7 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -41,15 +41,15 @@
 
 #include <asm/hardware/sa1111.h>
 
-#include <mach/pxa-regs.h>
-#include <mach/pxa2xx-regs.h>
-#include <mach/mfp-pxa25x.h>
+#include <mach/pxa25x.h>
+#include <mach/gpio.h>
 #include <mach/audio.h>
 #include <mach/lubbock.h>
 #include <mach/udc.h>
 #include <mach/irda.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
+#include <mach/pm.h>
 
 #include "generic.h"
 #include "clock.h"
@@ -113,8 +113,14 @@ static unsigned long lubbock_pin_config[] __initdata = {
         GPIO1_GPIO | WAKEUP_ON_EDGE_RISE,
 };
 
+#define LUB_HEXLED              __LUB_REG(LUBBOCK_FPGA_PHYS + 0x010)
 #define LUB_MISC_WR             __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080)
 
+void lubbock_set_hexled(uint32_t value)
+{
+        LUB_HEXLED = value;
+}
+
 void lubbock_set_misc_wr(unsigned int mask, unsigned int set)
 {
         unsigned long flags;
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 21b821e1a60d..d46b36746be2 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -25,14 +25,14 @@
 #include <linux/mtd/physmap.h>
 #include <linux/pda_power.h>
 #include <linux/pwm_backlight.h>
+#include <linux/usb/gpio_vbus.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+
+#include <mach/pxa27x.h>
 #include <mach/magician.h>
-#include <mach/mfp-pxa27x.h>
-#include <mach/pxa-regs.h>
-#include <mach/pxa2xx-regs.h>
 #include <mach/pxafb.h>
 #include <mach/i2c.h>
 #include <mach/mmc.h>
@@ -66,6 +66,11 @@ static unsigned long magician_pin_config[] __initdata = {
         GPIO31_I2S_SYNC,
         GPIO113_I2S_SYSCLK,
 
+        /* SSP 1 */
+        GPIO23_SSP1_SCLK,
+        GPIO24_SSP1_SFRM,
+        GPIO25_SSP1_TXD,
+
         /* SSP 2 */
         GPIO19_SSP2_SCLK,
         GPIO14_SSP2_SFRM,
@@ -148,22 +153,31 @@ static struct pxaficp_platform_data magician_ficp_info = {
  * GPIO Keys
  */
 
+#define INIT_KEY(_code, _gpio, _desc)   \
+        {                               \
+                .code   = KEY_##_code,  \
+                .gpio   = _gpio,        \
+                .desc   = _desc,        \
+                .type   = EV_KEY,       \
+                .wakeup = 1,            \
+        }
+
 static struct gpio_keys_button magician_button_table[] = {
-        {KEY_POWER,      GPIO0_MAGICIAN_KEY_POWER,      0, "Power button"},
-        {KEY_ESC,        GPIO37_MAGICIAN_KEY_HANGUP,    0, "Hangup button"},
-        {KEY_F10,        GPIO38_MAGICIAN_KEY_CONTACTS,  0, "Contacts button"},
-        {KEY_CALENDAR,   GPIO90_MAGICIAN_KEY_CALENDAR,  0, "Calendar button"},
-        {KEY_CAMERA,     GPIO91_MAGICIAN_KEY_CAMERA,    0, "Camera button"},
-        {KEY_UP,         GPIO93_MAGICIAN_KEY_UP,        0, "Up button"},
-        {KEY_DOWN,       GPIO94_MAGICIAN_KEY_DOWN,      0, "Down button"},
-        {KEY_LEFT,       GPIO95_MAGICIAN_KEY_LEFT,      0, "Left button"},
-        {KEY_RIGHT,      GPIO96_MAGICIAN_KEY_RIGHT,     0, "Right button"},
-        {KEY_KPENTER,    GPIO97_MAGICIAN_KEY_ENTER,     0, "Action button"},
-        {KEY_RECORD,     GPIO98_MAGICIAN_KEY_RECORD,    0, "Record button"},
-        {KEY_VOLUMEUP,   GPIO100_MAGICIAN_KEY_VOL_UP,   0, "Volume up"},
-        {KEY_VOLUMEDOWN, GPIO101_MAGICIAN_KEY_VOL_DOWN, 0, "Volume down"},
-        {KEY_PHONE,      GPIO102_MAGICIAN_KEY_PHONE,    0, "Phone button"},
-        {KEY_PLAY,       GPIO99_MAGICIAN_HEADPHONE_IN,  0, "Headset button"},
+        INIT_KEY(POWER,      GPIO0_MAGICIAN_KEY_POWER,      "Power button"),
+        INIT_KEY(ESC,        GPIO37_MAGICIAN_KEY_HANGUP,    "Hangup button"),
+        INIT_KEY(F10,        GPIO38_MAGICIAN_KEY_CONTACTS,  "Contacts button"),
+        INIT_KEY(CALENDAR,   GPIO90_MAGICIAN_KEY_CALENDAR,  "Calendar button"),
+        INIT_KEY(CAMERA,     GPIO91_MAGICIAN_KEY_CAMERA,    "Camera button"),
+        INIT_KEY(UP,         GPIO93_MAGICIAN_KEY_UP,        "Up button"),
+        INIT_KEY(DOWN,       GPIO94_MAGICIAN_KEY_DOWN,      "Down button"),
+        INIT_KEY(LEFT,       GPIO95_MAGICIAN_KEY_LEFT,      "Left button"),
+        INIT_KEY(RIGHT,      GPIO96_MAGICIAN_KEY_RIGHT,     "Right button"),
+        INIT_KEY(KPENTER,    GPIO97_MAGICIAN_KEY_ENTER,     "Action button"),
+        INIT_KEY(RECORD,     GPIO98_MAGICIAN_KEY_RECORD,    "Record button"),
+        INIT_KEY(VOLUMEUP,   GPIO100_MAGICIAN_KEY_VOL_UP,   "Volume up"),
+        INIT_KEY(VOLUMEDOWN, GPIO101_MAGICIAN_KEY_VOL_DOWN, "Volume down"),
+        INIT_KEY(PHONE,      GPIO102_MAGICIAN_KEY_PHONE,    "Phone button"),
+        INIT_KEY(PLAY,       GPIO99_MAGICIAN_HEADPHONE_IN,  "Headset button"),
 };
 
 static struct gpio_keys_platform_data gpio_keys_data = {
@@ -189,7 +203,7 @@ static struct platform_device gpio_keys = {
 static struct resource egpio_resources[] = {
         [0] = {
                 .start = PXA_CS3_PHYS,
-                .end   = PXA_CS3_PHYS + 0x20,
+                .end   = PXA_CS3_PHYS + 0x20 - 1,
                 .flags = IORESOURCE_MEM,
         },
         [1] = {
@@ -420,7 +434,7 @@ static struct gpio_led gpio_leds[] = {
         },
         {
                 .name = "magician::phone_bl",
-                .default_trigger = "none",
+                .default_trigger = "backlight",
                 .gpio = GPIO103_MAGICIAN_LED_KP,
         },
 };
@@ -468,8 +482,6 @@ static struct pasic3_led pasic3_leds[] = {
         },
 };
 
-static struct platform_device pasic3;
-
 static struct pasic3_leds_machinfo pasic3_leds_info = {
         .num_leds   = ARRAY_SIZE(pasic3_leds),
         .power_gpio = EGPIO_MAGICIAN_LED_POWER,
@@ -511,6 +523,31 @@ static struct platform_device pasic3 = {
 };
 
 /*
+ * USB "Transceiver"
+ */
+
+static struct resource gpio_vbus_resource = {
+        .flags = IORESOURCE_IRQ,
+        .start = IRQ_MAGICIAN_VBUS,
+        .end   = IRQ_MAGICIAN_VBUS,
+};
+
+static struct gpio_vbus_mach_info gpio_vbus_info = {
+        .gpio_pullup = GPIO27_MAGICIAN_USBC_PUEN,
+        .gpio_vbus   = EGPIO_MAGICIAN_CABLE_STATE_USB,
+};
+
+static struct platform_device gpio_vbus = {
+        .name          = "gpio-vbus",
+        .id            = -1,
+        .num_resources = 1,
+        .resource      = &gpio_vbus_resource,
+        .dev = {
+                .platform_data = &gpio_vbus_info,
+        },
+};
+
+/*
  * External power
  */
 
@@ -586,15 +623,17 @@ static struct pda_power_pdata power_supply_info = {
 static struct resource power_supply_resources[] = {
         [0] = {
                 .name  = "ac",
-                .flags = IORESOURCE_IRQ,
-                .start = IRQ_MAGICIAN_AC,
-                .end   = IRQ_MAGICIAN_AC,
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
+                         IORESOURCE_IRQ_LOWEDGE,
+                .start = IRQ_MAGICIAN_VBUS,
+                .end   = IRQ_MAGICIAN_VBUS,
         },
         [1] = {
                 .name  = "usb",
-                .flags = IORESOURCE_IRQ,
-                .start = IRQ_MAGICIAN_AC,
-                .end   = IRQ_MAGICIAN_AC,
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
+                         IORESOURCE_IRQ_LOWEDGE,
+                .start = IRQ_MAGICIAN_VBUS,
+                .end   = IRQ_MAGICIAN_VBUS,
         },
 };
 
@@ -688,11 +727,9 @@ static void magician_set_vpp(struct map_info *map, int vpp)
         gpio_set_value(EGPIO_MAGICIAN_FLASH_VPP, vpp);
 }
 
-#define PXA_CS_SIZE             0x04000000
-
 static struct resource strataflash_resource = {
         .start = PXA_CS0_PHYS,
-        .end   = PXA_CS0_PHYS + PXA_CS_SIZE - 1,
+        .end   = PXA_CS0_PHYS + SZ_64M - 1,
         .flags = IORESOURCE_MEM,
 };
 
@@ -720,6 +757,7 @@ static struct platform_device *devices[] __initdata = {
         &egpio,
         &backlight,
         &pasic3,
+        &gpio_vbus,
         &power_supply,
         &strataflash,
         &leds_gpio,
@@ -743,6 +781,7 @@ static void __init magician_init(void)
                 gpio_direction_output(GPIO83_MAGICIAN_nIR_EN, 1);
                 pxa_set_ficp_info(&magician_ficp_info);
         }
+        pxa27x_set_i2c_power_info(NULL);
         pxa_set_i2c_info(NULL);
         pxa_set_mci_info(&magician_mci_info);
         pxa_set_ohci_info(&magician_ohci_info);
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 5f224968043c..a6c8429e975f 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -41,9 +41,8 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/flash.h>
 
-#include <mach/pxa-regs.h>
-#include <mach/pxa2xx-regs.h>
-#include <mach/mfp-pxa27x.h>
+#include <mach/pxa27x.h>
+#include <mach/gpio.h>
 #include <mach/mainstone.h>
 #include <mach/audio.h>
 #include <mach/pxafb.h>
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index 33626de8cbf6..7ffb91d64c39 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -18,15 +18,12 @@
 #include <linux/init.h>
 #include <linux/sysdev.h>
 
-#include <mach/hardware.h>
-#include <mach/pxa-regs.h>
+#include <mach/gpio.h>
 #include <mach/pxa2xx-regs.h>
 #include <mach/mfp-pxa2xx.h>
 
 #include "generic.h"
 
-#define gpio_to_bank(gpio)      ((gpio) >> 5)
-
 #define PGSR(x)         __REG2(0x40F00020, (x) << 2)
 #define __GAFR(u, x)    __REG2((u) ? 0x40E00058 : 0x40E00054, (x) << 3)
 #define GAFR_L(x)       __GAFR(0, x)
diff --git a/arch/arm/mach-pxa/mfp-pxa3xx.c b/arch/arm/mach-pxa/mfp-pxa3xx.c
index eb197a6e8e94..7a270eecd480 100644
--- a/arch/arm/mach-pxa/mfp-pxa3xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa3xx.c
@@ -20,183 +20,9 @@
 #include <linux/sysdev.h>
 
 #include <mach/hardware.h>
-#include <mach/mfp.h>
 #include <mach/mfp-pxa3xx.h>
 #include <mach/pxa3xx-regs.h>
 
-/* mfp_spin_lock is used to ensure that MFP register configuration
- * (most likely a read-modify-write operation) is atomic, and that
- * mfp_table[] is consistent
- */
-static DEFINE_SPINLOCK(mfp_spin_lock);
-
-static void __iomem *mfpr_mmio_base = (void __iomem *)&__REG(MFPR_BASE);
-
-struct pxa3xx_mfp_pin {
-        unsigned long   config;         /* -1 for not configured */
-        unsigned long   mfpr_off;       /* MFPRxx Register offset */
-        unsigned long   mfpr_run;       /* Run-Mode Register Value */
-        unsigned long   mfpr_lpm;       /* Low Power Mode Register Value */
-};
-
-static struct pxa3xx_mfp_pin mfp_table[MFP_PIN_MAX];
-
-/* mapping of MFP_LPM_* definitions to MFPR_LPM_* register bits */
-static const unsigned long mfpr_lpm[] = {
-        MFPR_LPM_INPUT,
-        MFPR_LPM_DRIVE_LOW,
-        MFPR_LPM_DRIVE_HIGH,
-        MFPR_LPM_PULL_LOW,
-        MFPR_LPM_PULL_HIGH,
-        MFPR_LPM_FLOAT,
-};
-
-/* mapping of MFP_PULL_* definitions to MFPR_PULL_* register bits */
-static const unsigned long mfpr_pull[] = {
-        MFPR_PULL_NONE,
-        MFPR_PULL_LOW,
-        MFPR_PULL_HIGH,
-        MFPR_PULL_BOTH,
-};
-
-/* mapping of MFP_LPM_EDGE_* definitions to MFPR_EDGE_* register bits */
-static const unsigned long mfpr_edge[] = {
-        MFPR_EDGE_NONE,
-        MFPR_EDGE_RISE,
-        MFPR_EDGE_FALL,
-        MFPR_EDGE_BOTH,
-};
-
-#define mfpr_readl(off)                 \
-        __raw_readl(mfpr_mmio_base + (off))
-
-#define mfpr_writel(off, val)           \
-        __raw_writel(val, mfpr_mmio_base + (off))
-
-#define mfp_configured(p)       ((p)->config != -1)
-
-/*
- * perform a read-back of any MFPR register to make sure the
- * previous writings are finished
- */
-#define mfpr_sync()     (void)__raw_readl(mfpr_mmio_base + 0)
-
-static inline void __mfp_config_run(struct pxa3xx_mfp_pin *p)
-{
-        if (mfp_configured(p))
-                mfpr_writel(p->mfpr_off, p->mfpr_run);
-}
-
-static inline void __mfp_config_lpm(struct pxa3xx_mfp_pin *p)
-{
-        if (mfp_configured(p)) {
-                unsigned long mfpr_clr = (p->mfpr_run & ~MFPR_EDGE_BOTH) | MFPR_EDGE_CLEAR;
-                if (mfpr_clr != p->mfpr_run)
-                        mfpr_writel(p->mfpr_off, mfpr_clr);
-                if (p->mfpr_lpm != mfpr_clr)
-                        mfpr_writel(p->mfpr_off, p->mfpr_lpm);
-        }
-}
-
-void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num)
-{
-        unsigned long flags;
-        int i;
-
-        spin_lock_irqsave(&mfp_spin_lock, flags);
-
-        for (i = 0; i < num; i++, mfp_cfgs++) {
-                unsigned long tmp, c = *mfp_cfgs;
-                struct pxa3xx_mfp_pin *p;
-                int pin, af, drv, lpm, edge, pull;
-
-                pin = MFP_PIN(c);
-                BUG_ON(pin >= MFP_PIN_MAX);
-                p = &mfp_table[pin];
-
-                af  = MFP_AF(c);
-                drv = MFP_DS(c);
-                lpm = MFP_LPM_STATE(c);
-                edge = MFP_LPM_EDGE(c);
-                pull = MFP_PULL(c);
-
-                /* run-mode pull settings will conflict with MFPR bits of
-                 * low power mode state,  calculate mfpr_run and mfpr_lpm
-                 * individually if pull != MFP_PULL_NONE
-                 */
-                tmp = MFPR_AF_SEL(af) | MFPR_DRIVE(drv);
-
-                if (likely(pull == MFP_PULL_NONE)) {
-                        p->mfpr_run = tmp | mfpr_lpm[lpm] | mfpr_edge[edge];
-                        p->mfpr_lpm = p->mfpr_run;
-                } else {
-                        p->mfpr_lpm = tmp | mfpr_lpm[lpm] | mfpr_edge[edge];
-                        p->mfpr_run = tmp | mfpr_pull[pull];
-                }
-
-                p->config = c; __mfp_config_run(p);
-        }
-
-        mfpr_sync();
-        spin_unlock_irqrestore(&mfp_spin_lock, flags);
-}
-
-unsigned long pxa3xx_mfp_read(int mfp)
-{
-        unsigned long val, flags;
-
-        BUG_ON(mfp >= MFP_PIN_MAX);
-
-        spin_lock_irqsave(&mfp_spin_lock, flags);
-        val = mfpr_readl(mfp_table[mfp].mfpr_off);
-        spin_unlock_irqrestore(&mfp_spin_lock, flags);
-
-        return val;
-}
-
-void pxa3xx_mfp_write(int mfp, unsigned long val)
-{
-        unsigned long flags;
-
-        BUG_ON(mfp >= MFP_PIN_MAX);
-
-        spin_lock_irqsave(&mfp_spin_lock, flags);
-        mfpr_writel(mfp_table[mfp].mfpr_off, val);
-        mfpr_sync();
-        spin_unlock_irqrestore(&mfp_spin_lock, flags);
-}
-
-void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *map)
-{
-        struct pxa3xx_mfp_addr_map *p;
-        unsigned long offset, flags;
-        int i;
-
-        spin_lock_irqsave(&mfp_spin_lock, flags);
-
-        for (p = map; p->start != MFP_PIN_INVALID; p++) {
-                offset = p->offset;
-                i = p->start;
-
-                do {
-                        mfp_table[i].mfpr_off = offset;
-                        mfp_table[i].mfpr_run = 0;
-                        mfp_table[i].mfpr_lpm = 0;
-                        offset += 4; i++;
-                } while ((i <= p->end) && (p->end != -1));
-        }
-
-        spin_unlock_irqrestore(&mfp_spin_lock, flags);
-}
-
-void __init pxa3xx_init_mfp(void)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(mfp_table); i++)
-                mfp_table[i].config = -1;
-}
-
 #ifdef CONFIG_PM
 /*
  * Configure the MFPs appropriately for suspend/resume.
@@ -207,23 +33,13 @@ void __init pxa3xx_init_mfp(void)
  */
 static int pxa3xx_mfp_suspend(struct sys_device *d, pm_message_t state)
 {
-        int pin;
-
-        for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++) {
-                struct pxa3xx_mfp_pin *p = &mfp_table[pin];
-                __mfp_config_lpm(p);
-        }
+        mfp_config_lpm();
         return 0;
 }
 
 static int pxa3xx_mfp_resume(struct sys_device *d)
 {
-        int pin;
-
-        for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++) {
-                struct pxa3xx_mfp_pin *p = &mfp_table[pin];
-                __mfp_config_run(p);
-        }
+        mfp_config_run();
 
         /* clear RDH bit when MFP settings are restored
          *
@@ -231,7 +47,6 @@ static int pxa3xx_mfp_resume(struct sys_device *d)
          * preserve them here in case they will be referenced later
          */
         ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
-
         return 0;
 }
 #else
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index 2b427e015b6f..97c93a7a285c 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -36,13 +36,15 @@
 #include <linux/power_supply.h>
 #include <linux/wm97xx_batt.h>
 #include <linux/mtd/physmap.h>
+#include <linux/usb/gpio_vbus.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <mach/mfp-pxa27x.h>
+
+#include <mach/pxa27x.h>
+#include <mach/regs-rtc.h>
 #include <mach/pxa27x_keypad.h>
 #include <mach/pxafb.h>
-#include <mach/pxa2xx-regs.h>
 #include <mach/mmc.h>
 #include <mach/udc.h>
 #include <mach/pxa27x-udc.h>
@@ -411,21 +413,6 @@ static void gsm_exit(void)
 /*
  * USB UDC
  */
-static void udc_power_command(int cmd)
-{
-        switch (cmd) {
-        case PXA2XX_UDC_CMD_DISCONNECT:
-                gpio_set_value(GPIO22_USB_ENABLE, 0);
-                break;
-        case PXA2XX_UDC_CMD_CONNECT:
-                gpio_set_value(GPIO22_USB_ENABLE, 1);
-                break;
-        default:
-                printk(KERN_INFO "udc_control: unknown command (0x%x)!\n", cmd);
-                break;
-        }
-}
-
 static int is_usb_connected(void)
 {
         return !gpio_get_value(GPIO13_nUSB_DETECT);
@@ -433,24 +420,15 @@ static int is_usb_connected(void)
 
 static struct pxa2xx_udc_mach_info mioa701_udc_info = {
         .udc_is_connected = is_usb_connected,
-        .udc_command      = udc_power_command,
+        .gpio_pullup      = GPIO22_USB_ENABLE,
 };
 
-struct gpio_ress udc_gpios[] = {
-        MIO_GPIO_OUT(GPIO22_USB_ENABLE, 0, "USB Vbus enable")
+struct gpio_vbus_mach_info gpio_vbus_data = {
+        .gpio_vbus = GPIO13_nUSB_DETECT,
+        .gpio_vbus_inverted = 1,
+        .gpio_pullup = -1,
 };
 
-static int __init udc_init(void)
-{
-        pxa_set_udc_info(&mioa701_udc_info);
-        return mio_gpio_request(ARRAY_AND_SIZE(udc_gpios));
-}
-
-static void udc_exit(void)
-{
-        mio_gpio_free(ARRAY_AND_SIZE(udc_gpios));
-}
-
 /*
  * SDIO/MMC Card controller
  */
@@ -789,6 +767,7 @@ MIO_SIMPLE_DEV(pxa2xx_ac97,	  "pxa2xx-ac97",    NULL)
 MIO_PARENT_DEV(mio_wm9713_codec,  "wm9713-codec",   &pxa2xx_ac97.dev, NULL)
 MIO_SIMPLE_DEV(mioa701_sound,     "mioa701-wm9713", NULL)
 MIO_SIMPLE_DEV(mioa701_board,     "mioa701-board",  NULL)
+MIO_SIMPLE_DEV(gpio_vbus,         "gpio-vbus",      &gpio_vbus_data);
 
 static struct platform_device *devices[] __initdata = {
         &mioa701_gpio_keys,
@@ -800,7 +779,8 @@ static struct platform_device *devices[] __initdata = {
         &mioa701_sound,
         &power_dev,
         &strataflash,
-        &mioa701_board
+        &gpio_vbus,
+        &mioa701_board,
 };
 
 static void mioa701_machine_exit(void);
@@ -808,13 +788,13 @@ static void mioa701_machine_exit(void);
 static void mioa701_poweroff(void)
 {
         mioa701_machine_exit();
-        arm_machine_restart('s');
+        arm_machine_restart('s', NULL);
 }
 
-static void mioa701_restart(char c)
+static void mioa701_restart(char c, const char *cmd)
 {
         mioa701_machine_exit();
-        arm_machine_restart('s');
+        arm_machine_restart('s', cmd);
 }
 
 struct gpio_ress global_gpios[] = {
@@ -837,7 +817,7 @@ static void __init mioa701_machine_init(void)
         pxa_set_mci_info(&mioa701_mci_info);
         pxa_set_keypad_info(&mioa701_keypad_info);
         wm97xx_bat_set_pdata(&mioa701_battery_data);
-        udc_init();
+        pxa_set_udc_info(&mioa701_udc_info);
         pm_power_off = mioa701_poweroff;
         arm_pm_restart = mioa701_restart;
         platform_add_devices(devices, ARRAY_SIZE(devices));
@@ -850,7 +830,6 @@ static void __init mioa701_machine_init(void)
 
 static void mioa701_machine_exit(void)
 {
-        udc_exit();
         bootstrap_exit();
         gsm_exit();
 }
diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c
index 8a73814126b1..a65713ce019e 100644
--- a/arch/arm/mach-pxa/mp900.c
+++ b/arch/arm/mach-pxa/mp900.c
@@ -19,10 +19,10 @@
 #include <linux/types.h>
 #include <linux/usb/isp116x.h>
 
-#include <mach/hardware.h>
-#include <mach/pxa-regs.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+
+#include <mach/pxa25x.h>
 #include "generic.h"
 
 static void isp116x_pfm_delay(struct device *dev, int delay)
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
new file mode 100644
index 000000000000..8587477a9bb7
--- /dev/null
+++ b/arch/arm/mach-pxa/palmld.c
@@ -0,0 +1,565 @@
+/*
+ * Hardware definitions for Palm LifeDrive
+ *
+ * Author:     Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on work of:
+ *              Alex Osborne <ato@meshy.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * (find more info at www.hackndev.com)
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/pda_power.h>
+#include <linux/pwm_backlight.h>
+#include <linux/gpio.h>
+#include <linux/wm97xx_batt.h>
+#include <linux/power_supply.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/pxa27x.h>
+#include <mach/audio.h>
+#include <mach/palmld.h>
+#include <mach/mmc.h>
+#include <mach/pxafb.h>
+#include <mach/irda.h>
+#include <mach/pxa27x_keypad.h>
+#include <mach/palmasoc.h>
+
+#include "generic.h"
+#include "devices.h"
+
+/******************************************************************************
+ * Pin configuration
+ ******************************************************************************/
+static unsigned long palmld_pin_config[] __initdata = {
+        /* MMC */
+        GPIO32_MMC_CLK,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+        GPIO112_MMC_CMD,
+        GPIO14_GPIO,    /* SD detect */
+        GPIO114_GPIO,   /* SD power */
+        GPIO116_GPIO,   /* SD r/o switch */
+
+        /* AC97 */
+        GPIO28_AC97_BITCLK,
+        GPIO29_AC97_SDATA_IN_0,
+        GPIO30_AC97_SDATA_OUT,
+        GPIO31_AC97_SYNC,
+
+        /* IrDA */
+        GPIO108_GPIO,   /* ir disable */
+        GPIO46_FICP_RXD,
+        GPIO47_FICP_TXD,
+
+        /* MATRIX KEYPAD */
+        GPIO100_KP_MKIN_0,
+        GPIO101_KP_MKIN_1,
+        GPIO102_KP_MKIN_2,
+        GPIO97_KP_MKIN_3,
+        GPIO103_KP_MKOUT_0,
+        GPIO104_KP_MKOUT_1,
+        GPIO105_KP_MKOUT_2,
+
+        /* LCD */
+        GPIO58_LCD_LDD_0,
+        GPIO59_LCD_LDD_1,
+        GPIO60_LCD_LDD_2,
+        GPIO61_LCD_LDD_3,
+        GPIO62_LCD_LDD_4,
+        GPIO63_LCD_LDD_5,
+        GPIO64_LCD_LDD_6,
+        GPIO65_LCD_LDD_7,
+        GPIO66_LCD_LDD_8,
+        GPIO67_LCD_LDD_9,
+        GPIO68_LCD_LDD_10,
+        GPIO69_LCD_LDD_11,
+        GPIO70_LCD_LDD_12,
+        GPIO71_LCD_LDD_13,
+        GPIO72_LCD_LDD_14,
+        GPIO73_LCD_LDD_15,
+        GPIO74_LCD_FCLK,
+        GPIO75_LCD_LCLK,
+        GPIO76_LCD_PCLK,
+        GPIO77_LCD_BIAS,
+
+        /* PWM */
+        GPIO16_PWM0_OUT,
+
+        /* GPIO KEYS */
+        GPIO10_GPIO,    /* hotsync button */
+        GPIO12_GPIO,    /* power switch */
+        GPIO15_GPIO,    /* lock switch */
+
+        /* LEDs */
+        GPIO52_GPIO,    /* green led */
+        GPIO94_GPIO,    /* orange led */
+
+        /* PCMCIA */
+        GPIO48_nPOE,
+        GPIO49_nPWE,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO85_nPCE_1,
+        GPIO54_nPCE_2,
+        GPIO79_PSKTSEL,
+        GPIO55_nPREG,
+        GPIO56_nPWAIT,
+        GPIO57_nIOIS16,
+        GPIO36_GPIO,    /* wifi power */
+        GPIO38_GPIO,    /* wifi ready */
+        GPIO81_GPIO,    /* wifi reset */
+
+        /* HDD */
+        GPIO95_GPIO,    /* HDD irq */
+        GPIO115_GPIO,   /* HDD power */
+
+        /* MISC */
+        GPIO13_GPIO,    /* earphone detect */
+};
+
+/******************************************************************************
+ * SD/MMC card controller
+ ******************************************************************************/
+static int palmld_mci_init(struct device *dev, irq_handler_t palmld_detect_int,
+                                void *data)
+{
+        int err = 0;
+
+        /* Setup an interrupt for detecting card insert/remove events */
+        err = gpio_request(GPIO_NR_PALMLD_SD_DETECT_N, "SD IRQ");
+        if (err)
+                goto err;
+        err = gpio_direction_input(GPIO_NR_PALMLD_SD_DETECT_N);
+        if (err)
+                goto err2;
+        err = request_irq(gpio_to_irq(GPIO_NR_PALMLD_SD_DETECT_N),
+                        palmld_detect_int, IRQF_DISABLED | IRQF_SAMPLE_RANDOM |
+                        IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
+                        "SD/MMC card detect", data);
+        if (err) {
+                printk(KERN_ERR "%s: cannot request SD/MMC card detect IRQ\n",
+                                __func__);
+                goto err2;
+        }
+
+        err = gpio_request(GPIO_NR_PALMLD_SD_POWER, "SD_POWER");
+        if (err)
+                goto err3;
+        err = gpio_direction_output(GPIO_NR_PALMLD_SD_POWER, 0);
+        if (err)
+                goto err4;
+
+        err = gpio_request(GPIO_NR_PALMLD_SD_READONLY, "SD_READONLY");
+        if (err)
+                goto err4;
+        err = gpio_direction_input(GPIO_NR_PALMLD_SD_READONLY);
+        if (err)
+                goto err5;
+
+        printk(KERN_DEBUG "%s: irq registered\n", __func__);
+
+        return 0;
+
+err5:
+        gpio_free(GPIO_NR_PALMLD_SD_READONLY);
+err4:
+        gpio_free(GPIO_NR_PALMLD_SD_POWER);
+err3:
+        free_irq(gpio_to_irq(GPIO_NR_PALMLD_SD_DETECT_N), data);
+err2:
+        gpio_free(GPIO_NR_PALMLD_SD_DETECT_N);
+err:
+        return err;
+}
+
+static void palmld_mci_exit(struct device *dev, void *data)
+{
+        gpio_free(GPIO_NR_PALMLD_SD_READONLY);
+        gpio_free(GPIO_NR_PALMLD_SD_POWER);
+        free_irq(gpio_to_irq(GPIO_NR_PALMLD_SD_DETECT_N), data);
+        gpio_free(GPIO_NR_PALMLD_SD_DETECT_N);
+}
+
+static void palmld_mci_power(struct device *dev, unsigned int vdd)
+{
+        struct pxamci_platform_data *p_d = dev->platform_data;
+        gpio_set_value(GPIO_NR_PALMLD_SD_POWER, p_d->ocr_mask & (1 << vdd));
+}
+
+static int palmld_mci_get_ro(struct device *dev)
+{
+        return gpio_get_value(GPIO_NR_PALMLD_SD_READONLY);
+}
+
+static struct pxamci_platform_data palmld_mci_platform_data = {
+        .ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34,
+        .setpower       = palmld_mci_power,
+        .get_ro         = palmld_mci_get_ro,
+        .init           = palmld_mci_init,
+        .exit           = palmld_mci_exit,
+};
+
+/******************************************************************************
+ * GPIO keyboard
+ ******************************************************************************/
+static unsigned int palmld_matrix_keys[] = {
+        KEY(0, 1, KEY_F2),
+        KEY(0, 2, KEY_UP),
+
+        KEY(1, 0, KEY_F3),
+        KEY(1, 1, KEY_F4),
+        KEY(1, 2, KEY_RIGHT),
+
+        KEY(2, 0, KEY_F1),
+        KEY(2, 1, KEY_F5),
+        KEY(2, 2, KEY_DOWN),
+
+        KEY(3, 0, KEY_F6),
+        KEY(3, 1, KEY_ENTER),
+        KEY(3, 2, KEY_LEFT),
+};
+
+static struct pxa27x_keypad_platform_data palmld_keypad_platform_data = {
+        .matrix_key_rows        = 4,
+        .matrix_key_cols        = 3,
+        .matrix_key_map         = palmld_matrix_keys,
+        .matrix_key_map_size    = ARRAY_SIZE(palmld_matrix_keys),
+
+        .debounce_interval      = 30,
+};
+
+/******************************************************************************
+ * GPIO keys
+ ******************************************************************************/
+static struct gpio_keys_button palmld_pxa_buttons[] = {
+        {KEY_F8, GPIO_NR_PALMLD_HOTSYNC_BUTTON_N, 1, "HotSync Button" },
+        {KEY_F9, GPIO_NR_PALMLD_LOCK_SWITCH, 0, "Lock Switch" },
+        {KEY_POWER, GPIO_NR_PALMLD_POWER_SWITCH, 0, "Power Switch" },
+};
+
+static struct gpio_keys_platform_data palmld_pxa_keys_data = {
+        .buttons        = palmld_pxa_buttons,
+        .nbuttons       = ARRAY_SIZE(palmld_pxa_buttons),
+};
+
+static struct platform_device palmld_pxa_keys = {
+        .name   = "gpio-keys",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &palmld_pxa_keys_data,
+        },
+};
+
+/******************************************************************************
+ * Backlight
+ ******************************************************************************/
+static int palmld_backlight_init(struct device *dev)
+{
+        int ret;
+
+        ret = gpio_request(GPIO_NR_PALMLD_BL_POWER, "BL POWER");
+        if (ret)
+                goto err;
+        ret = gpio_direction_output(GPIO_NR_PALMLD_BL_POWER, 0);
+        if (ret)
+                goto err2;
+        ret = gpio_request(GPIO_NR_PALMLD_LCD_POWER, "LCD POWER");
+        if (ret)
+                goto err2;
+        ret = gpio_direction_output(GPIO_NR_PALMLD_LCD_POWER, 0);
+        if (ret)
+                goto err3;
+
+        return 0;
+err3:
+        gpio_free(GPIO_NR_PALMLD_LCD_POWER);
+err2:
+        gpio_free(GPIO_NR_PALMLD_BL_POWER);
+err:
+        return ret;
+}
+
+static int palmld_backlight_notify(int brightness)
+{
+        gpio_set_value(GPIO_NR_PALMLD_BL_POWER, brightness);
+        gpio_set_value(GPIO_NR_PALMLD_LCD_POWER, brightness);
+        return brightness;
+}
+
+static void palmld_backlight_exit(struct device *dev)
+{
+        gpio_free(GPIO_NR_PALMLD_BL_POWER);
+        gpio_free(GPIO_NR_PALMLD_LCD_POWER);
+}
+
+static struct platform_pwm_backlight_data palmld_backlight_data = {
+        .pwm_id         = 0,
+        .max_brightness = PALMLD_MAX_INTENSITY,
+        .dft_brightness = PALMLD_MAX_INTENSITY,
+        .pwm_period_ns  = PALMLD_PERIOD_NS,
+        .init           = palmld_backlight_init,
+        .notify         = palmld_backlight_notify,
+        .exit           = palmld_backlight_exit,
+};
+
+static struct platform_device palmld_backlight = {
+        .name   = "pwm-backlight",
+        .dev    = {
+                .parent         = &pxa27x_device_pwm0.dev,
+                .platform_data  = &palmld_backlight_data,
+        },
+};
+
+/******************************************************************************
+ * IrDA
+ ******************************************************************************/
+static int palmld_irda_startup(struct device *dev)
+{
+        int err;
+        err = gpio_request(GPIO_NR_PALMLD_IR_DISABLE, "IR DISABLE");
+        if (err)
+                goto err;
+        err = gpio_direction_output(GPIO_NR_PALMLD_IR_DISABLE, 1);
+        if (err)
+                gpio_free(GPIO_NR_PALMLD_IR_DISABLE);
+err:
+        return err;
+}
+
+static void palmld_irda_shutdown(struct device *dev)
+{
+        gpio_free(GPIO_NR_PALMLD_IR_DISABLE);
+}
+
+static void palmld_irda_transceiver_mode(struct device *dev, int mode)
+{
+        gpio_set_value(GPIO_NR_PALMLD_IR_DISABLE, mode & IR_OFF);
+        pxa2xx_transceiver_mode(dev, mode);
+}
+
+static struct pxaficp_platform_data palmld_ficp_platform_data = {
+        .startup                = palmld_irda_startup,
+        .shutdown               = palmld_irda_shutdown,
+        .transceiver_cap        = IR_SIRMODE | IR_FIRMODE | IR_OFF,
+        .transceiver_mode       = palmld_irda_transceiver_mode,
+};
+
+/******************************************************************************
+ * LEDs
+ ******************************************************************************/
+struct gpio_led gpio_leds[] = {
+{
+        .name                   = "palmld:green:led",
+        .default_trigger        = "none",
+        .gpio                   = GPIO_NR_PALMLD_LED_GREEN,
+}, {
+        .name                   = "palmld:amber:led",
+        .default_trigger        = "none",
+        .gpio                   = GPIO_NR_PALMLD_LED_AMBER,
+},
+};
+
+static struct gpio_led_platform_data gpio_led_info = {
+        .leds           = gpio_leds,
+        .num_leds       = ARRAY_SIZE(gpio_leds),
+};
+
+static struct platform_device palmld_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &gpio_led_info,
+        }
+};
+
+/******************************************************************************
+ * Power supply
+ ******************************************************************************/
+static int power_supply_init(struct device *dev)
+{
+        int ret;
+
+        ret = gpio_request(GPIO_NR_PALMLD_POWER_DETECT, "CABLE_STATE_AC");
+        if (ret)
+                goto err1;
+        ret = gpio_direction_input(GPIO_NR_PALMLD_POWER_DETECT);
+        if (ret)
+                goto err2;
+
+        ret = gpio_request(GPIO_NR_PALMLD_USB_DETECT_N, "CABLE_STATE_USB");
+        if (ret)
+                goto err2;
+        ret = gpio_direction_input(GPIO_NR_PALMLD_USB_DETECT_N);
+        if (ret)
+                goto err3;
+
+        return 0;
+
+err3:
+        gpio_free(GPIO_NR_PALMLD_USB_DETECT_N);
+err2:
+        gpio_free(GPIO_NR_PALMLD_POWER_DETECT);
+err1:
+        return ret;
+}
+
+static int palmld_is_ac_online(void)
+{
+        return gpio_get_value(GPIO_NR_PALMLD_POWER_DETECT);
+}
+
+static int palmld_is_usb_online(void)
+{
+        return !gpio_get_value(GPIO_NR_PALMLD_USB_DETECT_N);
+}
+
+static void power_supply_exit(struct device *dev)
+{
+        gpio_free(GPIO_NR_PALMLD_USB_DETECT_N);
+        gpio_free(GPIO_NR_PALMLD_POWER_DETECT);
+}
+
+static char *palmld_supplicants[] = {
+        "main-battery",
+};
+
+static struct pda_power_pdata power_supply_info = {
+        .init            = power_supply_init,
+        .is_ac_online    = palmld_is_ac_online,
+        .is_usb_online   = palmld_is_usb_online,
+        .exit            = power_supply_exit,
+        .supplied_to     = palmld_supplicants,
+        .num_supplicants = ARRAY_SIZE(palmld_supplicants),
+};
+
+static struct platform_device power_supply = {
+        .name = "pda-power",
+        .id   = -1,
+        .dev  = {
+                .platform_data = &power_supply_info,
+        },
+};
+
+/******************************************************************************
+ * WM97xx battery
+ ******************************************************************************/
+static struct wm97xx_batt_info wm97xx_batt_pdata = {
+        .batt_aux       = WM97XX_AUX_ID3,
+        .temp_aux       = WM97XX_AUX_ID2,
+        .charge_gpio    = -1,
+        .max_voltage    = PALMLD_BAT_MAX_VOLTAGE,
+        .min_voltage    = PALMLD_BAT_MIN_VOLTAGE,
+        .batt_mult      = 1000,
+        .batt_div       = 414,
+        .temp_mult      = 1,
+        .temp_div       = 1,
+        .batt_tech      = POWER_SUPPLY_TECHNOLOGY_LIPO,
+        .batt_name      = "main-batt",
+};
+
+/******************************************************************************
+ * aSoC audio
+ ******************************************************************************/
+static struct palm27x_asoc_info palm27x_asoc_pdata = {
+        .jack_gpio      = GPIO_NR_PALMLD_EARPHONE_DETECT,
+};
+
+/******************************************************************************
+ * Framebuffer
+ ******************************************************************************/
+static struct pxafb_mode_info palmld_lcd_modes[] = {
+{
+        .pixclock       = 57692,
+        .xres           = 320,
+        .yres           = 480,
+        .bpp            = 16,
+
+        .left_margin    = 32,
+        .right_margin   = 1,
+        .upper_margin   = 7,
+        .lower_margin   = 1,
+
+        .hsync_len      = 4,
+        .vsync_len      = 1,
+},
+};
+
+static struct pxafb_mach_info palmld_lcd_screen = {
+        .modes          = palmld_lcd_modes,
+        .num_modes      = ARRAY_SIZE(palmld_lcd_modes),
+        .lcd_conn       = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
+};
+
+/******************************************************************************
+ * Machine init
+ ******************************************************************************/
+static struct platform_device *devices[] __initdata = {
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+        &palmld_pxa_keys,
+#endif
+        &palmld_backlight,
+        &palmld_leds,
+        &power_supply,
+};
+
+static struct map_desc palmld_io_desc[] __initdata = {
+{
+        .virtual        = PALMLD_IDE_VIRT,
+        .pfn            = __phys_to_pfn(PALMLD_IDE_PHYS),
+        .length         = PALMLD_IDE_SIZE,
+        .type           = MT_DEVICE
+},
+{
+        .virtual        = PALMLD_USB_VIRT,
+        .pfn            = __phys_to_pfn(PALMLD_USB_PHYS),
+        .length         = PALMLD_USB_SIZE,
+        .type           = MT_DEVICE
+},
+};
+
+static void __init palmld_map_io(void)
+{
+        pxa_map_io();
+        iotable_init(palmld_io_desc, ARRAY_SIZE(palmld_io_desc));
+}
+
+static void __init palmld_init(void)
+{
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(palmld_pin_config));
+
+        set_pxa_fb_info(&palmld_lcd_screen);
+        pxa_set_mci_info(&palmld_mci_platform_data);
+        pxa_set_ac97_info(NULL);
+        pxa_set_ficp_info(&palmld_ficp_platform_data);
+        pxa_set_keypad_info(&palmld_keypad_platform_data);
+        wm97xx_bat_set_pdata(&wm97xx_batt_pdata);
+        palm27x_asoc_set_pdata(&palm27x_asoc_pdata);
+
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+MACHINE_START(PALMLD, "Palm LifeDrive")
+        .phys_io        = PALMLD_PHYS_IO_START,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .boot_params    = 0xa0000100,
+        .map_io         = palmld_map_io,
+        .init_irq       = pxa27x_init_irq,
+        .timer          = &pxa_timer,
+        .init_machine   = palmld_init
+MACHINE_END
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
new file mode 100644
index 000000000000..9521c7b33492
--- /dev/null
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -0,0 +1,496 @@
+/*
+ * Hardware definitions for Palm Tungsten|T5
+ *
+ * Author:      Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on work of:
+ *              Ales Snuparek <snuparek@atlas.cz>
+ *              Justin Kendrick <twilightsentry@gmail.com>
+ *              RichardT5 <richard_t5@users.sourceforge.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * (find more info at www.hackndev.com)
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/pda_power.h>
+#include <linux/pwm_backlight.h>
+#include <linux/gpio.h>
+#include <linux/wm97xx_batt.h>
+#include <linux/power_supply.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/pxa27x.h>
+#include <mach/audio.h>
+#include <mach/palmt5.h>
+#include <mach/mmc.h>
+#include <mach/pxafb.h>
+#include <mach/irda.h>
+#include <mach/pxa27x_keypad.h>
+#include <mach/udc.h>
+#include <mach/palmasoc.h>
+
+#include "generic.h"
+#include "devices.h"
+
+/******************************************************************************
+ * Pin configuration
+ ******************************************************************************/
+static unsigned long palmt5_pin_config[] __initdata = {
+        /* MMC */
+        GPIO32_MMC_CLK,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+        GPIO112_MMC_CMD,
+        GPIO14_GPIO,    /* SD detect */
+        GPIO114_GPIO,   /* SD power */
+        GPIO115_GPIO,   /* SD r/o switch */
+
+        /* AC97 */
+        GPIO28_AC97_BITCLK,
+        GPIO29_AC97_SDATA_IN_0,
+        GPIO30_AC97_SDATA_OUT,
+        GPIO31_AC97_SYNC,
+
+        /* IrDA */
+        GPIO40_GPIO,    /* ir disable */
+        GPIO46_FICP_RXD,
+        GPIO47_FICP_TXD,
+
+        /* USB */
+        GPIO15_GPIO,    /* usb detect */
+        GPIO95_GPIO,    /* usb power */
+
+        /* MATRIX KEYPAD */
+        GPIO100_KP_MKIN_0,
+        GPIO101_KP_MKIN_1,
+        GPIO102_KP_MKIN_2,
+        GPIO97_KP_MKIN_3,
+        GPIO103_KP_MKOUT_0,
+        GPIO104_KP_MKOUT_1,
+        GPIO105_KP_MKOUT_2,
+
+        /* LCD */
+        GPIO58_LCD_LDD_0,
+        GPIO59_LCD_LDD_1,
+        GPIO60_LCD_LDD_2,
+        GPIO61_LCD_LDD_3,
+        GPIO62_LCD_LDD_4,
+        GPIO63_LCD_LDD_5,
+        GPIO64_LCD_LDD_6,
+        GPIO65_LCD_LDD_7,
+        GPIO66_LCD_LDD_8,
+        GPIO67_LCD_LDD_9,
+        GPIO68_LCD_LDD_10,
+        GPIO69_LCD_LDD_11,
+        GPIO70_LCD_LDD_12,
+        GPIO71_LCD_LDD_13,
+        GPIO72_LCD_LDD_14,
+        GPIO73_LCD_LDD_15,
+        GPIO74_LCD_FCLK,
+        GPIO75_LCD_LCLK,
+        GPIO76_LCD_PCLK,
+        GPIO77_LCD_BIAS,
+
+        /* PWM */
+        GPIO16_PWM0_OUT,
+
+        /* MISC */
+        GPIO10_GPIO,    /* hotsync button */
+        GPIO90_GPIO,    /* power detect */
+        GPIO107_GPIO,   /* earphone detect */
+};
+
+/******************************************************************************
+ * SD/MMC card controller
+ ******************************************************************************/
+static int palmt5_mci_init(struct device *dev, irq_handler_t palmt5_detect_int,
+                                void *data)
+{
+        int err = 0;
+
+        /* Setup an interrupt for detecting card insert/remove events */
+        err = gpio_request(GPIO_NR_PALMT5_SD_DETECT_N, "SD IRQ");
+        if (err)
+                goto err;
+        err = gpio_direction_input(GPIO_NR_PALMT5_SD_DETECT_N);
+        if (err)
+                goto err2;
+        err = request_irq(gpio_to_irq(GPIO_NR_PALMT5_SD_DETECT_N),
+                        palmt5_detect_int, IRQF_DISABLED | IRQF_SAMPLE_RANDOM |
+                        IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
+                        "SD/MMC card detect", data);
+        if (err) {
+                printk(KERN_ERR "%s: cannot request SD/MMC card detect IRQ\n",
+                                __func__);
+                goto err2;
+        }
+
+        err = gpio_request(GPIO_NR_PALMT5_SD_POWER, "SD_POWER");
+        if (err)
+                goto err3;
+        err = gpio_direction_output(GPIO_NR_PALMT5_SD_POWER, 0);
+        if (err)
+                goto err4;
+
+        err = gpio_request(GPIO_NR_PALMT5_SD_READONLY, "SD_READONLY");
+        if (err)
+                goto err4;
+        err = gpio_direction_input(GPIO_NR_PALMT5_SD_READONLY);
+        if (err)
+                goto err5;
+
+        printk(KERN_DEBUG "%s: irq registered\n", __func__);
+
+        return 0;
+
+err5:
+        gpio_free(GPIO_NR_PALMT5_SD_READONLY);
+err4:
+        gpio_free(GPIO_NR_PALMT5_SD_POWER);
+err3:
+        free_irq(gpio_to_irq(GPIO_NR_PALMT5_SD_DETECT_N), data);
+err2:
+        gpio_free(GPIO_NR_PALMT5_SD_DETECT_N);
+err:
+        return err;
+}
+
+static void palmt5_mci_exit(struct device *dev, void *data)
+{
+        gpio_free(GPIO_NR_PALMT5_SD_READONLY);
+        gpio_free(GPIO_NR_PALMT5_SD_POWER);
+        free_irq(IRQ_GPIO_PALMT5_SD_DETECT_N, data);
+        gpio_free(GPIO_NR_PALMT5_SD_DETECT_N);
+}
+
+static void palmt5_mci_power(struct device *dev, unsigned int vdd)
+{
+        struct pxamci_platform_data *p_d = dev->platform_data;
+        gpio_set_value(GPIO_NR_PALMT5_SD_POWER, p_d->ocr_mask & (1 << vdd));
+}
+
+static int palmt5_mci_get_ro(struct device *dev)
+{
+        return gpio_get_value(GPIO_NR_PALMT5_SD_READONLY);
+}
+
+static struct pxamci_platform_data palmt5_mci_platform_data = {
+        .ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34,
+        .setpower       = palmt5_mci_power,
+        .get_ro         = palmt5_mci_get_ro,
+        .init           = palmt5_mci_init,
+        .exit           = palmt5_mci_exit,
+};
+
+/******************************************************************************
+ * GPIO keyboard
+ ******************************************************************************/
+static unsigned int palmt5_matrix_keys[] = {
+        KEY(0, 0, KEY_POWER),
+        KEY(0, 1, KEY_F1),
+        KEY(0, 2, KEY_ENTER),
+
+        KEY(1, 0, KEY_F2),
+        KEY(1, 1, KEY_F3),
+        KEY(1, 2, KEY_F4),
+
+        KEY(2, 0, KEY_UP),
+        KEY(2, 2, KEY_DOWN),
+
+        KEY(3, 0, KEY_RIGHT),
+        KEY(3, 2, KEY_LEFT),
+};
+
+static struct pxa27x_keypad_platform_data palmt5_keypad_platform_data = {
+        .matrix_key_rows        = 4,
+        .matrix_key_cols        = 3,
+        .matrix_key_map         = palmt5_matrix_keys,
+        .matrix_key_map_size    = ARRAY_SIZE(palmt5_matrix_keys),
+
+        .debounce_interval      = 30,
+};
+
+/******************************************************************************
+ * GPIO keys
+ ******************************************************************************/
+static struct gpio_keys_button palmt5_pxa_buttons[] = {
+        {KEY_F8, GPIO_NR_PALMT5_HOTSYNC_BUTTON_N, 1, "HotSync Button" },
+};
+
+static struct gpio_keys_platform_data palmt5_pxa_keys_data = {
+        .buttons        = palmt5_pxa_buttons,
+        .nbuttons       = ARRAY_SIZE(palmt5_pxa_buttons),
+};
+
+static struct platform_device palmt5_pxa_keys = {
+        .name   = "gpio-keys",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &palmt5_pxa_keys_data,
+        },
+};
+
+/******************************************************************************
+ * Backlight
+ ******************************************************************************/
+static int palmt5_backlight_init(struct device *dev)
+{
+        int ret;
+
+        ret = gpio_request(GPIO_NR_PALMT5_BL_POWER, "BL POWER");
+        if (ret)
+                goto err;
+        ret = gpio_direction_output(GPIO_NR_PALMT5_BL_POWER, 0);
+        if (ret)
+                goto err2;
+        ret = gpio_request(GPIO_NR_PALMT5_LCD_POWER, "LCD POWER");
+        if (ret)
+                goto err2;
+        ret = gpio_direction_output(GPIO_NR_PALMT5_LCD_POWER, 0);
+        if (ret)
+                goto err3;
+
+        return 0;
+err3:
+        gpio_free(GPIO_NR_PALMT5_LCD_POWER);
+err2:
+        gpio_free(GPIO_NR_PALMT5_BL_POWER);
+err:
+        return ret;
+}
+
+static int palmt5_backlight_notify(int brightness)
+{
+        gpio_set_value(GPIO_NR_PALMT5_BL_POWER, brightness);
+        gpio_set_value(GPIO_NR_PALMT5_LCD_POWER, brightness);
+        return brightness;
+}
+
+static void palmt5_backlight_exit(struct device *dev)
+{
+        gpio_free(GPIO_NR_PALMT5_BL_POWER);
+        gpio_free(GPIO_NR_PALMT5_LCD_POWER);
+}
+
+static struct platform_pwm_backlight_data palmt5_backlight_data = {
+        .pwm_id         = 0,
+        .max_brightness = PALMT5_MAX_INTENSITY,
+        .dft_brightness = PALMT5_MAX_INTENSITY,
+        .pwm_period_ns  = PALMT5_PERIOD_NS,
+        .init           = palmt5_backlight_init,
+        .notify         = palmt5_backlight_notify,
+        .exit           = palmt5_backlight_exit,
+};
+
+static struct platform_device palmt5_backlight = {
+        .name   = "pwm-backlight",
+        .dev    = {
+                .parent         = &pxa27x_device_pwm0.dev,
+                .platform_data  = &palmt5_backlight_data,
+        },
+};
+
+/******************************************************************************
+ * IrDA
+ ******************************************************************************/
+static int palmt5_irda_startup(struct device *dev)
+{
+        int err;
+        err = gpio_request(GPIO_NR_PALMT5_IR_DISABLE, "IR DISABLE");
+        if (err)
+                goto err;
+        err = gpio_direction_output(GPIO_NR_PALMT5_IR_DISABLE, 1);
+        if (err)
+                gpio_free(GPIO_NR_PALMT5_IR_DISABLE);
+err:
+        return err;
+}
+
+static void palmt5_irda_shutdown(struct device *dev)
+{
+        gpio_free(GPIO_NR_PALMT5_IR_DISABLE);
+}
+
+static void palmt5_irda_transceiver_mode(struct device *dev, int mode)
+{
+        gpio_set_value(GPIO_NR_PALMT5_IR_DISABLE, mode & IR_OFF);
+        pxa2xx_transceiver_mode(dev, mode);
+}
+
+static struct pxaficp_platform_data palmt5_ficp_platform_data = {
+        .startup                = palmt5_irda_startup,
+        .shutdown               = palmt5_irda_shutdown,
+        .transceiver_cap        = IR_SIRMODE | IR_FIRMODE | IR_OFF,
+        .transceiver_mode       = palmt5_irda_transceiver_mode,
+};
+
+/******************************************************************************
+ * UDC
+ ******************************************************************************/
+static struct pxa2xx_udc_mach_info palmt5_udc_info __initdata = {
+        .gpio_vbus              = GPIO_NR_PALMT5_USB_DETECT_N,
+        .gpio_vbus_inverted     = 1,
+        .gpio_pullup            = GPIO_NR_PALMT5_USB_POWER,
+        .gpio_pullup_inverted   = 0,
+};
+
+/******************************************************************************
+ * Power supply
+ ******************************************************************************/
+static int power_supply_init(struct device *dev)
+{
+        int ret;
+
+        ret = gpio_request(GPIO_NR_PALMT5_POWER_DETECT, "CABLE_STATE_AC");
+        if (ret)
+                goto err1;
+        ret = gpio_direction_input(GPIO_NR_PALMT5_POWER_DETECT);
+        if (ret)
+                goto err2;
+
+        return 0;
+err2:
+        gpio_free(GPIO_NR_PALMT5_POWER_DETECT);
+err1:
+        return ret;
+}
+
+static int palmt5_is_ac_online(void)
+{
+        return gpio_get_value(GPIO_NR_PALMT5_POWER_DETECT);
+}
+
+static void power_supply_exit(struct device *dev)
+{
+        gpio_free(GPIO_NR_PALMT5_POWER_DETECT);
+}
+
+static char *palmt5_supplicants[] = {
+        "main-battery",
+};
+
+static struct pda_power_pdata power_supply_info = {
+        .init            = power_supply_init,
+        .is_ac_online    = palmt5_is_ac_online,
+        .exit            = power_supply_exit,
+        .supplied_to     = palmt5_supplicants,
+        .num_supplicants = ARRAY_SIZE(palmt5_supplicants),
+};
+
+static struct platform_device power_supply = {
+        .name = "pda-power",
+        .id   = -1,
+        .dev  = {
+                .platform_data = &power_supply_info,
+        },
+};
+
+/******************************************************************************
+ * WM97xx battery
+ ******************************************************************************/
+static struct wm97xx_batt_info wm97xx_batt_pdata = {
+        .batt_aux       = WM97XX_AUX_ID3,
+        .temp_aux       = WM97XX_AUX_ID2,
+        .charge_gpio    = -1,
+        .max_voltage    = PALMT5_BAT_MAX_VOLTAGE,
+        .min_voltage    = PALMT5_BAT_MIN_VOLTAGE,
+        .batt_mult      = 1000,
+        .batt_div       = 414,
+        .temp_mult      = 1,
+        .temp_div       = 1,
+        .batt_tech      = POWER_SUPPLY_TECHNOLOGY_LIPO,
+        .batt_name      = "main-batt",
+};
+
+/******************************************************************************
+ * aSoC audio
+ ******************************************************************************/
+static struct palm27x_asoc_info palm27x_asoc_pdata = {
+        .jack_gpio      = GPIO_NR_PALMT5_EARPHONE_DETECT,
+};
+
+/******************************************************************************
+ * Framebuffer
+ ******************************************************************************/
+static struct pxafb_mode_info palmt5_lcd_modes[] = {
+{
+        .pixclock       = 57692,
+        .xres           = 320,
+        .yres           = 480,
+        .bpp            = 16,
+
+        .left_margin    = 32,
+        .right_margin   = 1,
+        .upper_margin   = 7,
+        .lower_margin   = 1,
+
+        .hsync_len      = 4,
+        .vsync_len      = 1,
+},
+};
+
+static struct pxafb_mach_info palmt5_lcd_screen = {
+        .modes          = palmt5_lcd_modes,
+        .num_modes      = ARRAY_SIZE(palmt5_lcd_modes),
+        .lcd_conn       = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
+};
+
+/******************************************************************************
+ * Machine init
+ ******************************************************************************/
+static struct platform_device *devices[] __initdata = {
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+        &palmt5_pxa_keys,
+#endif
+        &palmt5_backlight,
+        &power_supply,
+};
+
+/* setup udc GPIOs initial state */
+static void __init palmt5_udc_init(void)
+{
+        if (!gpio_request(GPIO_NR_PALMT5_USB_POWER, "UDC Vbus")) {
+                gpio_direction_output(GPIO_NR_PALMT5_USB_POWER, 1);
+                gpio_free(GPIO_NR_PALMT5_USB_POWER);
+        }
+}
+
+static void __init palmt5_init(void)
+{
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(palmt5_pin_config));
+
+        set_pxa_fb_info(&palmt5_lcd_screen);
+        pxa_set_mci_info(&palmt5_mci_platform_data);
+        palmt5_udc_init();
+        pxa_set_udc_info(&palmt5_udc_info);
+        pxa_set_ac97_info(NULL);
+        pxa_set_ficp_info(&palmt5_ficp_platform_data);
+        pxa_set_keypad_info(&palmt5_keypad_platform_data);
+        wm97xx_bat_set_pdata(&wm97xx_batt_pdata);
+        palm27x_asoc_set_pdata(&palm27x_asoc_pdata);
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+MACHINE_START(PALMT5, "Palm Tungsten|T5")
+        .phys_io        = PALMT5_PHYS_IO_START,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .boot_params    = 0xa0000100,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa27x_init_irq,
+        .timer          = &pxa_timer,
+        .init_machine   = palmt5_init
+MACHINE_END
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index a9d94f5dbec4..b490c0924619 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -32,12 +32,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
+#include <mach/pxa27x.h>
 #include <mach/audio.h>
 #include <mach/palmtx.h>
 #include <mach/mmc.h>
 #include <mach/pxafb.h>
-#include <mach/pxa-regs.h>
-#include <mach/mfp-pxa27x.h>
 #include <mach/irda.h>
 #include <mach/pxa27x_keypad.h>
 #include <mach/udc.h>
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index 2f730da3bba8..b88eb4dd2c84 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -33,13 +33,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
+#include <mach/pxa27x.h>
 #include <mach/audio.h>
 #include <mach/palmz72.h>
 #include <mach/mmc.h>
 #include <mach/pxafb.h>
-#include <mach/pxa-regs.h>
-#include <mach/pxa2xx-regs.h>
-#include <mach/mfp-pxa27x.h>
 #include <mach/irda.h>
 #include <mach/pxa27x_keypad.h>
 #include <mach/udc.h>
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
index 36135a02fdc7..6abfa2979c61 100644
--- a/arch/arm/mach-pxa/pcm027.c
+++ b/arch/arm/mach-pxa/pcm027.c
@@ -29,10 +29,7 @@
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <mach/hardware.h>
-#include <mach/pxa-regs.h>
-#include <mach/mfp-pxa27x.h>
-#include <mach/pxa2xx-regs.h>
+#include <mach/pxa27x.h>
 #include <mach/pxa2xx_spi.h>
 #include <mach/pcm027.h>
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index 34841c72815f..f46698e20c1f 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -31,13 +31,12 @@
 #include <mach/i2c.h>
 #include <mach/camera.h>
 #include <asm/mach/map.h>
-#include <mach/pxa-regs.h>
+#include <mach/pxa27x.h>
 #include <mach/audio.h>
 #include <mach/mmc.h>
 #include <mach/ohci.h>
 #include <mach/pcm990_baseboard.h>
 #include <mach/pxafb.h>
-#include <mach/mfp-pxa27x.h>
 
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c
index 164eb0bb6321..884b174c8ead 100644
--- a/arch/arm/mach-pxa/pm.c
+++ b/arch/arm/mach-pxa/pm.c
@@ -14,15 +14,8 @@
 #include <linux/module.h>
 #include <linux/suspend.h>
 #include <linux/errno.h>
-#include <linux/time.h>
 
-#include <mach/hardware.h>
-#include <asm/memory.h>
-#include <asm/system.h>
 #include <mach/pm.h>
-#include <mach/pxa-regs.h>
-#include <mach/lubbock.h>
-#include <asm/mach/time.h>
 
 struct pxa_cpu_pm_fns *pxa_cpu_pm_fns;
 static unsigned long *sleep_save;
@@ -57,9 +50,9 @@ int pxa_pm_enter(suspend_state_t state)
 
                 /* if invalid, display message and wait for a hardware reset */
                 if (checksum != sleep_save_checksum) {
-#ifdef CONFIG_ARCH_LUBBOCK
-                        LUB_HEXLED = 0xbadbadc5;
-#endif
+
+                        lubbock_set_hexled(0xbadbadc5);
+
                         while (1)
                                 pxa_cpu_pm_fns->enter(state);
                 }
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index f9093beba752..036bbde4d221 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -36,9 +36,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/pxa-regs.h>
-#include <mach/pxa2xx-regs.h>
-#include <mach/mfp-pxa25x.h>
+#include <mach/pxa25x.h>
 #include <mach/mmc.h>
 #include <mach/udc.h>
 #include <mach/i2c.h>
@@ -503,12 +501,12 @@ static struct platform_device *devices[] __initdata = {
 
 static void poodle_poweroff(void)
 {
-        arm_machine_restart('h');
+        arm_machine_restart('h', NULL);
 }
 
-static void poodle_restart(char mode)
+static void poodle_restart(char mode, const char *cmd)
 {
-        arm_machine_restart('h');
+        arm_machine_restart('h', cmd);
 }
 
 static void __init poodle_init(void)
diff --git a/arch/arm/mach-pxa/pwm.c b/arch/arm/mach-pxa/pwm.c
index 3ca7ffc6904b..fcdd374437a8 100644
--- a/arch/arm/mach-pxa/pwm.c
+++ b/arch/arm/mach-pxa/pwm.c
@@ -20,7 +20,6 @@
 #include <linux/pwm.h>
 
 #include <asm/div64.h>
-#include <mach/pxa-regs.h>
 
 /* PWM registers and bits definitions */
 #define PWMCR           (0x00)
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 6c57522e2469..77c2693cfeef 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -25,9 +25,8 @@
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
-#include <mach/pxa-regs.h>
-#include <mach/pxa2xx-regs.h>
-#include <mach/mfp-pxa25x.h>
+#include <mach/gpio.h>
+#include <mach/pxa25x.h>
 #include <mach/reset.h>
 #include <mach/pm.h>
 #include <mach/dma.h>
@@ -310,14 +309,14 @@ set_pwer:
 void __init pxa25x_init_irq(void)
 {
         pxa_init_irq(32, pxa25x_set_wake);
-        pxa_init_gpio(85, pxa25x_set_wake);
+        pxa_init_gpio(IRQ_GPIO_2_x, 2, 84, pxa25x_set_wake);
 }
 
 #ifdef CONFIG_CPU_PXA26x
 void __init pxa26x_init_irq(void)
 {
         pxa_init_irq(32, pxa25x_set_wake);
-        pxa_init_gpio(90, pxa25x_set_wake);
+        pxa_init_gpio(IRQ_GPIO_2_x, 2, 89, pxa25x_set_wake);
 }
 #endif
 
@@ -355,7 +354,7 @@ static int __init pxa25x_init(void)
 
                 clks_register(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs));
 
-                if ((ret = pxa_init_dma(16)))
+                if ((ret = pxa_init_dma(IRQ_DMA, 16)))
                         return ret;
 
                 pxa25x_init_pm();
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 411bec54fdc4..a425ec71e657 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -21,9 +21,8 @@
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <mach/irqs.h>
-#include <mach/pxa-regs.h>
-#include <mach/pxa2xx-regs.h>
-#include <mach/mfp-pxa27x.h>
+#include <mach/gpio.h>
+#include <mach/pxa27x.h>
 #include <mach/reset.h>
 #include <mach/ohci.h>
 #include <mach/pm.h>
@@ -332,7 +331,7 @@ static int pxa27x_set_wake(unsigned int irq, unsigned int on)
 void __init pxa27x_init_irq(void)
 {
         pxa_init_irq(34, pxa27x_set_wake);
-        pxa_init_gpio(121, pxa27x_set_wake);
+        pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake);
 }
 
 /*
@@ -381,7 +380,7 @@ static int __init pxa27x_init(void)
 
                 clks_register(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
 
-                if ((ret = pxa_init_dma(32)))
+                if ((ret = pxa_init_dma(IRQ_DMA, 32)))
                         return ret;
 
                 pxa27x_init_pm();
diff --git a/arch/arm/mach-pxa/pxa2xx.c b/arch/arm/mach-pxa/pxa2xx.c
index 73d04d81c75a..2f3394f85917 100644
--- a/arch/arm/mach-pxa/pxa2xx.c
+++ b/arch/arm/mach-pxa/pxa2xx.c
@@ -16,7 +16,6 @@
 
 #include <mach/hardware.h>
 #include <mach/pxa2xx-regs.h>
-#include <mach/mfp-pxa2xx.h>
 #include <mach/mfp-pxa25x.h>
 #include <mach/reset.h>
 #include <mach/irda.h>
diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c
index 83fb609b6eb7..4ba6d21f851c 100644
--- a/arch/arm/mach-pxa/pxa300.c
+++ b/arch/arm/mach-pxa/pxa300.c
@@ -17,15 +17,13 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 
-#include <mach/hardware.h>
-#include <mach/pxa3xx-regs.h>
-#include <mach/mfp-pxa300.h>
+#include <mach/pxa300.h>
 
 #include "generic.h"
 #include "devices.h"
 #include "clock.h"
 
-static struct pxa3xx_mfp_addr_map pxa300_mfp_addr_map[] __initdata = {
+static struct mfp_addr_map pxa300_mfp_addr_map[] __initdata = {
 
         MFP_ADDR_X(GPIO0,   GPIO2,   0x00b4),
         MFP_ADDR_X(GPIO3,   GPIO26,  0x027c),
@@ -74,7 +72,7 @@ static struct pxa3xx_mfp_addr_map pxa300_mfp_addr_map[] __initdata = {
 };
 
 /* override pxa300 MFP register addresses */
-static struct pxa3xx_mfp_addr_map pxa310_mfp_addr_map[] __initdata = {
+static struct mfp_addr_map pxa310_mfp_addr_map[] __initdata = {
         MFP_ADDR_X(GPIO30,  GPIO98,   0x0418),
         MFP_ADDR_X(GPIO7_2, GPIO12_2, 0x052C),
 
@@ -100,13 +98,13 @@ static struct clk_lookup pxa310_clkregs[] = {
 static int __init pxa300_init(void)
 {
         if (cpu_is_pxa300() || cpu_is_pxa310()) {
-                pxa3xx_init_mfp();
-                pxa3xx_mfp_init_addr(pxa300_mfp_addr_map);
+                mfp_init_base(io_p2v(MFPR_BASE));
+                mfp_init_addr(pxa300_mfp_addr_map);
                 clks_register(ARRAY_AND_SIZE(common_clkregs));
         }
 
         if (cpu_is_pxa310()) {
-                pxa3xx_mfp_init_addr(pxa310_mfp_addr_map);
+                mfp_init_addr(pxa310_mfp_addr_map);
                 clks_register(ARRAY_AND_SIZE(pxa310_clkregs));
         }
 
diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c
index 36f066196fa2..8b3d97efadab 100644
--- a/arch/arm/mach-pxa/pxa320.c
+++ b/arch/arm/mach-pxa/pxa320.c
@@ -17,16 +17,13 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 
-#include <mach/hardware.h>
-#include <mach/mfp.h>
-#include <mach/pxa3xx-regs.h>
-#include <mach/mfp-pxa320.h>
+#include <mach/pxa320.h>
 
 #include "generic.h"
 #include "devices.h"
 #include "clock.h"
 
-static struct pxa3xx_mfp_addr_map pxa320_mfp_addr_map[] __initdata = {
+static struct mfp_addr_map pxa320_mfp_addr_map[] __initdata = {
 
         MFP_ADDR_X(GPIO0,  GPIO4,   0x0124),
         MFP_ADDR_X(GPIO5,  GPIO9,   0x028C),
@@ -89,8 +86,8 @@ static struct clk_lookup pxa320_clkregs[] = {
 static int __init pxa320_init(void)
 {
         if (cpu_is_pxa320()) {
-                pxa3xx_init_mfp();
-                pxa3xx_mfp_init_addr(pxa320_mfp_addr_map);
+                mfp_init_base(io_p2v(MFPR_BASE));
+                mfp_init_addr(pxa320_mfp_addr_map);
                 clks_register(ARRAY_AND_SIZE(pxa320_clkregs));
         }
 
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 490893824e78..b02d4544dc95 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -23,6 +23,7 @@
 #include <linux/sysdev.h>
 
 #include <mach/hardware.h>
+#include <mach/gpio.h>
 #include <mach/pxa3xx-regs.h>
 #include <mach/reset.h>
 #include <mach/ohci.h>
@@ -538,7 +539,7 @@ void __init pxa3xx_init_irq(void)
         __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
 
         pxa_init_irq(56, pxa3xx_set_wake);
-        pxa_init_gpio(128, NULL);
+        pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
 }
 
 /*
@@ -594,7 +595,7 @@ static int __init pxa3xx_init(void)
 
                 clks_register(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
 
-                if ((ret = pxa_init_dma(32)))
+                if ((ret = pxa_init_dma(IRQ_DMA, 32)))
                         return ret;
 
                 pxa3xx_init_pm();
diff --git a/arch/arm/mach-pxa/pxa930.c b/arch/arm/mach-pxa/pxa930.c
index 13e6bfdfff60..71131742fffd 100644
--- a/arch/arm/mach-pxa/pxa930.c
+++ b/arch/arm/mach-pxa/pxa930.c
@@ -16,10 +16,9 @@
 #include <linux/irq.h>
 #include <linux/dma-mapping.h>
 
-#include <mach/hardware.h>
-#include <mach/mfp-pxa930.h>
+#include <mach/pxa930.h>
 
-static struct pxa3xx_mfp_addr_map pxa930_mfp_addr_map[] __initdata = {
+static struct mfp_addr_map pxa930_mfp_addr_map[] __initdata = {
 
         MFP_ADDR(GPIO0, 0x02e0),
         MFP_ADDR(GPIO1, 0x02dc),
@@ -180,8 +179,8 @@ static struct pxa3xx_mfp_addr_map pxa930_mfp_addr_map[] __initdata = {
 static int __init pxa930_init(void)
 {
         if (cpu_is_pxa930()) {
-                pxa3xx_init_mfp();
-                pxa3xx_mfp_init_addr(pxa930_mfp_addr_map);
+                mfp_init_base(io_p2v(MFPR_BASE));
+                mfp_init_addr(pxa930_mfp_addr_map);
         }
 
         return 0;
diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
index 00b2dc2a1074..df29d45fb4e7 100644
--- a/arch/arm/mach-pxa/reset.c
+++ b/arch/arm/mach-pxa/reset.c
@@ -10,7 +10,7 @@
 #include <linux/io.h>
 #include <asm/proc-fns.h>
 
-#include <mach/pxa-regs.h>
+#include <mach/regs-ost.h>
 #include <mach/reset.h>
 
 unsigned int reset_status;
@@ -81,7 +81,7 @@ static void do_hw_reset(void)
         OSMR3 = OSCR + 368640;  /* ... in 100 ms */
 }
 
-void arch_reset(char mode)
+void arch_reset(char mode, const char *cmd)
 {
         clear_reset_status(RESET_STATUS_ALL);
 
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c
index 5d02a7325586..ff8239991430 100644
--- a/arch/arm/mach-pxa/saar.c
+++ b/arch/arm/mach-pxa/saar.c
@@ -25,11 +25,9 @@
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <mach/hardware.h>
-#include <mach/pxa3xx-regs.h>
-#include <mach/mfp-pxa930.h>
+
+#include <mach/pxa930.h>
 #include <mach/i2c.h>
-#include <mach/regs-lcd.h>
 #include <mach/pxafb.h>
 
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index f0845c1b001c..16b4ec67e3b6 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -25,7 +25,6 @@
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <mach/pm.h>
-#include <mach/pxa-regs.h>
 #include <mach/pxa2xx-gpio.h>
 #include <mach/sharpsl.h>
 #include "sharpsl.h"
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index a62c8375eb53..2ed95f369cfc 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -15,7 +15,6 @@
 #include <asm/assembler.h>
 #include <mach/hardware.h>
 
-#include <mach/pxa-regs.h>
 #include <mach/pxa2xx-regs.h>
 
 #define MDREFR_KDIV     0x200a4000      // all banks
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 0d62d311d41a..8c61ddac119e 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -44,9 +44,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/pxa-regs.h>
-#include <mach/pxa2xx-regs.h>
-#include <mach/mfp-pxa27x.h>
+#include <mach/pxa27x.h>
 #include <mach/pxa27x-udc.h>
 #include <mach/reset.h>
 #include <mach/i2c.h>
@@ -709,10 +707,10 @@ static struct platform_device *devices[] __initdata = {
 
 static void spitz_poweroff(void)
 {
-        arm_machine_restart('g');
+        arm_machine_restart('g', NULL);
 }
 
-static void spitz_restart(char mode)
+static void spitz_restart(char mode, const char *cmd)
 {
         /* Bootloader magic for a reboot */
         if((MSC0 & 0xffff0000) == 0x7ff00000)
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
index 072e77cfe5a3..2e4490562c9e 100644
--- a/arch/arm/mach-pxa/spitz_pm.c
+++ b/arch/arm/mach-pxa/spitz_pm.c
@@ -24,7 +24,6 @@
 
 #include <mach/sharpsl.h>
 #include <mach/spitz.h>
-#include <mach/pxa-regs.h>
 #include <mach/pxa2xx-regs.h>
 #include <mach/pxa2xx-gpio.h>
 #include "sharpsl.h"
diff --git a/arch/arm/mach-pxa/ssp.c b/arch/arm/mach-pxa/ssp.c
index 6f42004db3ed..965e38c6bafe 100644
--- a/arch/arm/mach-pxa/ssp.c
+++ b/arch/arm/mach-pxa/ssp.c
@@ -33,7 +33,6 @@
 #include <asm/irq.h>
 #include <mach/hardware.h>
 #include <mach/ssp.h>
-#include <mach/pxa-regs.h>
 #include <mach/regs-ssp.h>
 
 #define TIMEOUT 100000
diff --git a/arch/arm/mach-pxa/standby.S b/arch/arm/mach-pxa/standby.S
index f3821cfda72f..29f5f5c180b7 100644
--- a/arch/arm/mach-pxa/standby.S
+++ b/arch/arm/mach-pxa/standby.S
@@ -13,7 +13,6 @@
 #include <asm/assembler.h>
 #include <mach/hardware.h>
 
-#include <mach/pxa-regs.h>
 #include <mach/pxa2xx-regs.h>
 
                 .text
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index 58ef08a5224b..b75353a2ec75 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -22,9 +22,8 @@
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <mach/hardware.h>
-#include <mach/pxa3xx-regs.h>
-#include <mach/mfp-pxa930.h>
+
+#include <mach/pxa930.h>
 #include <mach/pxafb.h>
 #include <mach/pxa27x_keypad.h>
 
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 95656a72268d..8eb3830fbb0b 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -22,8 +22,7 @@
 #include <asm/div64.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
-#include <mach/hardware.h>
-#include <mach/pxa-regs.h>
+#include <mach/regs-ost.h>
 
 /*
  * This is PXA's sched_clock implementation. This has a resolution
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 3332e5d0356c..6e8ade6ae339 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -36,8 +36,8 @@
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
-#include <mach/pxa2xx-regs.h>
-#include <mach/mfp-pxa25x.h>
+
+#include <mach/pxa25x.h>
 #include <mach/reset.h>
 #include <mach/irda.h>
 #include <mach/i2c.h>
@@ -876,10 +876,10 @@ static struct platform_device *devices[] __initdata = {
 
 static void tosa_poweroff(void)
 {
-        arm_machine_restart('g');
+        arm_machine_restart('g', NULL);
 }
 
-static void tosa_restart(char mode)
+static void tosa_restart(char mode, const char *cmd)
 {
         /* Bootloader magic for a reboot */
         if((MSC0 & 0xffff0000) == 0x7ff00000)
@@ -919,7 +919,7 @@ static void __init tosa_init(void)
         pxa2xx_set_spi_info(2, &pxa_ssp_master_info);
         spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
 
-        clk_add_alias("CLK_CK3P6MI", &tc6393xb_device.dev, "GPIO11_CLK", NULL);
+        clk_add_alias("CLK_CK3P6MI", tc6393xb_device.name, "GPIO11_CLK", NULL);
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
 }
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index a72e3add743c..f79c9cb70ae4 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -39,10 +39,7 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/flash.h>
 
-#include <mach/hardware.h>
-#include <mach/pxa-regs.h>
-#include <mach/pxa2xx-regs.h>
-#include <mach/mfp-pxa27x.h>
+#include <mach/pxa27x.h>
 #include <mach/pxa2xx_spi.h>
 #include <mach/trizeps4.h>
 #include <mach/audio.h>
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index 4b3120dbc049..0e65344e9f53 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -42,12 +42,9 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
 
-#include <mach/pxa-regs.h>
-#include <mach/pxa2xx-regs.h>
-#include <mach/bitfield.h>
+#include <mach/pxa25x.h>
 #include <mach/audio.h>
 #include <mach/pxafb.h>
-#include <mach/mfp-pxa25x.h>
 #include <mach/i2c.h>
 #include <mach/viper.h>
 
@@ -956,7 +953,7 @@ static struct map_desc viper_io_desc[] __initdata = {
         },
         {
                 .virtual = VIPER_PC104IO_BASE,
-                .pfn     = __phys_to_pfn(_PCMCIA1IO),
+                .pfn     = __phys_to_pfn(0x30000000),
                 .length  = 0x00800000,
                 .type    = MT_DEVICE,
         },
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c
index 46538885a58a..c1f73205d078 100644
--- a/arch/arm/mach-pxa/zylonite_pxa300.c
+++ b/arch/arm/mach-pxa/zylonite_pxa300.c
@@ -18,9 +18,9 @@
 #include <linux/init.h>
 #include <linux/i2c.h>
 #include <linux/i2c/pca953x.h>
+#include <linux/gpio.h>
 
-#include <asm/gpio.h>
-#include <mach/mfp-pxa300.h>
+#include <mach/pxa300.h>
 #include <mach/i2c.h>
 #include <mach/zylonite.h>
 
diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c
index 28e4e623780b..4e1c488c6906 100644
--- a/arch/arm/mach-pxa/zylonite_pxa320.c
+++ b/arch/arm/mach-pxa/zylonite_pxa320.c
@@ -18,7 +18,7 @@
 #include <linux/init.h>
 #include <linux/gpio.h>
 
-#include <mach/mfp-pxa320.h>
+#include <mach/pxa320.h>
 #include <mach/zylonite.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index ad911854eb4c..b6ec10627776 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -35,6 +35,7 @@ config MACH_REALVIEW_PB11MP
         bool "Support RealView/PB11MPCore platform"
         select CPU_V6
         select ARM_GIC
+        select HAVE_PATA_PLATFORM
         help
           Include support for the ARM(R) RealView MPCore Platform Baseboard.
           PB11MPCore is a platform with an on-board ARM11MPCore and has
@@ -51,6 +52,7 @@ config MACH_REALVIEW_PBA8
         bool "Support RealView/PB-A8 platform"
         select CPU_V7
         select ARM_GIC
+        select HAVE_PATA_PLATFORM
         help
           Include support for the ARM(R) RealView Cortex-A8 Platform Baseboard.
           PB-A8 is a platform with an on-board Cortex-A8 and has support for
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index bd2aa4f16141..d6766685cfc7 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -29,6 +29,7 @@
 #include <linux/clockchips.h>
 #include <linux/io.h>
 #include <linux/smc911x.h>
+#include <linux/ata_platform.h>
 
 #include <asm/clkdev.h>
 #include <asm/system.h>
@@ -150,6 +151,44 @@ int realview_eth_register(const char *name, struct resource *res)
         return platform_device_register(&realview_eth_device);
 }
 
+struct platform_device realview_usb_device = {
+        .name                   = "isp1760",
+        .num_resources          = 2,
+};
+
+int realview_usb_register(struct resource *res)
+{
+        realview_usb_device.resource = res;
+        return platform_device_register(&realview_usb_device);
+}
+
+static struct pata_platform_info pata_platform_data = {
+        .ioport_shift           = 1,
+};
+
+static struct resource pata_resources[] = {
+        [0] = {
+                .start          = REALVIEW_CF_BASE,
+                .end            = REALVIEW_CF_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = REALVIEW_CF_BASE + 0x100,
+                .end            = REALVIEW_CF_BASE + SZ_4K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device realview_cf_device = {
+        .name                   = "pata_platform",
+        .id                     = -1,
+        .num_resources          = ARRAY_SIZE(pata_resources),
+        .resource               = pata_resources,
+        .dev                    = {
+                .platform_data  = &pata_platform_data,
+        },
+};
+
 static struct resource realview_i2c_resource = {
         .start          = REALVIEW_I2C_BASE,
         .end            = REALVIEW_I2C_BASE + SZ_4K - 1,
@@ -158,11 +197,25 @@ static struct resource realview_i2c_resource = {
 
 struct platform_device realview_i2c_device = {
         .name           = "versatile-i2c",
-        .id             = -1,
+        .id             = 0,
         .num_resources  = 1,
         .resource       = &realview_i2c_resource,
 };
 
+static struct i2c_board_info realview_i2c_board_info[] = {
+        {
+                I2C_BOARD_INFO("rtc-ds1307", 0xd0 >> 1),
+                .type = "ds1338",
+        },
+};
+
+static int __init realview_i2c_init(void)
+{
+        return i2c_register_board_info(0, realview_i2c_board_info,
+                                       ARRAY_SIZE(realview_i2c_board_info));
+}
+arch_initcall(realview_i2c_init);
+
 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
 
 static unsigned int realview_mmc_status(struct device *dev)
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index 44269b162d49..21c08637683b 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -45,6 +45,7 @@ static struct amba_device name##_device = {			\
 }
 
 extern struct platform_device realview_flash_device;
+extern struct platform_device realview_cf_device;
 extern struct platform_device realview_i2c_device;
 extern struct mmc_platform_data realview_mmc0_plat_data;
 extern struct mmc_platform_data realview_mmc1_plat_data;
@@ -62,5 +63,6 @@ extern void realview_leds_event(led_event_t ledevt);
 extern void realview_timer_init(unsigned int timer_irq);
 extern int realview_flash_register(struct resource *res, u32 num);
 extern int realview_eth_register(const char *name, struct resource *res);
+extern int realview_usb_register(struct resource *res);
 
 #endif
diff --git a/arch/arm/mach-realview/include/mach/board-pba8.h b/arch/arm/mach-realview/include/mach/board-pba8.h
index c8bed8f58bab..307f97b16e5b 100644
--- a/arch/arm/mach-realview/include/mach/board-pba8.h
+++ b/arch/arm/mach-realview/include/mach/board-pba8.h
@@ -45,8 +45,6 @@
 #define REALVIEW_PBA8_DMC_BASE                  0x100E0000      /* DMC configuration */
 #define REALVIEW_PBA8_SMC_BASE                  0x100E1000      /* SMC configuration */
 #define REALVIEW_PBA8_CAN_BASE                  0x100E2000      /* CAN bus */
-#define REALVIEW_PBA8_CF_BASE                   0x18000000      /* Compact flash */
-#define REALVIEW_PBA8_CF_MEM_BASE               0x18003000      /* SMC for Compact flash */
 #define REALVIEW_PBA8_GIC_CPU_BASE              0x1E000000      /* Generic interrupt controller CPU interface */
 #define REALVIEW_PBA8_FLASH0_BASE               0x40000000
 #define REALVIEW_PBA8_FLASH0_SIZE               SZ_64M
diff --git a/arch/arm/mach-realview/include/mach/platform.h b/arch/arm/mach-realview/include/mach/platform.h
index 793a3a332712..c8f50835fed2 100644
--- a/arch/arm/mach-realview/include/mach/platform.h
+++ b/arch/arm/mach-realview/include/mach/platform.h
@@ -204,6 +204,12 @@
 #define REALVIEW_LT_BASE              0x80000000        /* Logic Tile expansion */
 
 /*
+ * CompactFlash
+ */
+#define REALVIEW_CF_BASE                0x18000000      /* CompactFlash */
+#define REALVIEW_CF_MEM_BASE            0x18003000      /* SMC for CompactFlash */
+
+/*
  * Disk on Chip
  */
 #define REALVIEW_DOC_BASE             0x2C000000
diff --git a/arch/arm/mach-realview/include/mach/system.h b/arch/arm/mach-realview/include/mach/system.h
index a2f61c78adbf..1a15a441e027 100644
--- a/arch/arm/mach-realview/include/mach/system.h
+++ b/arch/arm/mach-realview/include/mach/system.h
@@ -34,7 +34,7 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         void __iomem *hdr_ctrl = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_RESETCTL_OFFSET;
         unsigned int val;
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index bed39ed97613..c20fbef122b3 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -264,6 +264,19 @@ static int eth_device_register(void)
         return realview_eth_register(name, realview_eb_eth_resources);
 }
 
+static struct resource realview_eb_isp1761_resources[] = {
+        [0] = {
+                .start          = REALVIEW_EB_USB_BASE,
+                .end            = REALVIEW_EB_USB_BASE + SZ_128K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = IRQ_EB_USB,
+                .end            = IRQ_EB_USB,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
 static void __init gic_init_irq(void)
 {
         if (core_tile_eb11mp() || core_tile_a9mp()) {
@@ -323,6 +336,8 @@ static void realview_eb11mp_fixup(void)
         /* platform devices */
         realview_eb_eth_resources[1].start      = IRQ_EB11MP_ETH;
         realview_eb_eth_resources[1].end        = IRQ_EB11MP_ETH;
+        realview_eb_isp1761_resources[1].start  = IRQ_EB11MP_USB;
+        realview_eb_isp1761_resources[1].end    = IRQ_EB11MP_USB;
 }
 
 static void __init realview_eb_timer_init(void)
@@ -366,6 +381,7 @@ static void __init realview_eb_init(void)
         realview_flash_register(&realview_eb_flash_resource, 1);
         platform_device_register(&realview_i2c_device);
         eth_device_register();
+        realview_usb_register(realview_eb_isp1761_resources);
 
         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
                 struct amba_device *d = amba_devs[i];
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index 8f0683c22140..a64b84a7a3df 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -222,6 +222,19 @@ static struct resource realview_pb1176_smsc911x_resources[] = {
         },
 };
 
+static struct resource realview_pb1176_isp1761_resources[] = {
+        [0] = {
+                .start          = REALVIEW_PB1176_USB_BASE,
+                .end            = REALVIEW_PB1176_USB_BASE + SZ_128K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = IRQ_PB1176_USB,
+                .end            = IRQ_PB1176_USB,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
 static void __init gic_init_irq(void)
 {
         /* ARM1176 DevChip GIC, primary */
@@ -260,6 +273,8 @@ static void __init realview_pb1176_init(void)
 
         realview_flash_register(&realview_pb1176_flash_resource, 1);
         realview_eth_register(NULL, realview_pb1176_smsc911x_resources);
+        platform_device_register(&realview_i2c_device);
+        realview_usb_register(realview_pb1176_isp1761_resources);
 
         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
                 struct amba_device *d = amba_devs[i];
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index 3ebdb2dadd6f..ea1e60eca359 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -230,31 +230,19 @@ static struct resource realview_pb11mp_smsc911x_resources[] = {
         },
 };
 
-struct resource realview_pb11mp_cf_resources[] = {
+static struct resource realview_pb11mp_isp1761_resources[] = {
         [0] = {
-                .start          = REALVIEW_PB11MP_CF_BASE,
-                .end            = REALVIEW_PB11MP_CF_BASE + SZ_4K - 1,
+                .start          = REALVIEW_PB11MP_USB_BASE,
+                .end            = REALVIEW_PB11MP_USB_BASE + SZ_128K - 1,
                 .flags          = IORESOURCE_MEM,
         },
         [1] = {
-                .start          = REALVIEW_PB11MP_CF_MEM_BASE,
-                .end            = REALVIEW_PB11MP_CF_MEM_BASE + SZ_4K - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start          = -1,           /* FIXME: Find correct irq */
-                .end            = -1,
+                .start          = IRQ_TC11MP_USB,
+                .end            = IRQ_TC11MP_USB,
                 .flags          = IORESOURCE_IRQ,
         },
 };
 
-struct platform_device realview_pb11mp_cf_device = {
-        .name           = "compactflash",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(realview_pb11mp_cf_resources),
-        .resource       = realview_pb11mp_cf_resources,
-};
-
 static void __init gic_init_irq(void)
 {
         unsigned int pldctrl;
@@ -308,7 +296,8 @@ static void __init realview_pb11mp_init(void)
                                 ARRAY_SIZE(realview_pb11mp_flash_resource));
         realview_eth_register(NULL, realview_pb11mp_smsc911x_resources);
         platform_device_register(&realview_i2c_device);
-        platform_device_register(&realview_pb11mp_cf_device);
+        platform_device_register(&realview_cf_device);
+        realview_usb_register(realview_pb11mp_isp1761_resources);
 
         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
                 struct amba_device *d = amba_devs[i];
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 34c94435d2d8..d6ac1eb86576 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -221,31 +221,19 @@ static struct resource realview_pba8_smsc911x_resources[] = {
         },
 };
 
-struct resource realview_pba8_cf_resources[] = {
+static struct resource realview_pba8_isp1761_resources[] = {
         [0] = {
-                .start          = REALVIEW_PBA8_CF_BASE,
-                .end            = REALVIEW_PBA8_CF_BASE + SZ_4K - 1,
+                .start          = REALVIEW_PBA8_USB_BASE,
+                .end            = REALVIEW_PBA8_USB_BASE + SZ_128K - 1,
                 .flags          = IORESOURCE_MEM,
         },
         [1] = {
-                .start          = REALVIEW_PBA8_CF_MEM_BASE,
-                .end            = REALVIEW_PBA8_CF_MEM_BASE + SZ_4K - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start          = -1,           /* FIXME: Find correct irq */
-                .end            = -1,
+                .start          = IRQ_PBA8_USB,
+                .end            = IRQ_PBA8_USB,
                 .flags          = IORESOURCE_IRQ,
         },
 };
 
-struct platform_device realview_pba8_cf_device = {
-        .name           = "compactflash",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(realview_pba8_cf_resources),
-        .resource       = realview_pba8_cf_resources,
-};
-
 static void __init gic_init_irq(void)
 {
         /* ARM PB-A8 on-board GIC */
@@ -276,7 +264,8 @@ static void __init realview_pba8_init(void)
                                 ARRAY_SIZE(realview_pba8_flash_resource));
         realview_eth_register(NULL, realview_pba8_smsc911x_resources);
         platform_device_register(&realview_i2c_device);
-        platform_device_register(&realview_pba8_cf_device);
+        platform_device_register(&realview_cf_device);
+        realview_usb_register(realview_pba8_isp1761_resources);
 
         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
                 struct amba_device *d = amba_devs[i];
diff --git a/arch/arm/mach-rpc/dma.c b/arch/arm/mach-rpc/dma.c
index 7958a30f8932..c47d974d52bd 100644
--- a/arch/arm/mach-rpc/dma.c
+++ b/arch/arm/mach-rpc/dma.c
@@ -26,6 +26,16 @@
 #include <asm/mach/dma.h>
 #include <asm/hardware/iomd.h>
 
+struct iomd_dma {
+        struct dma_struct       dma;
+        unsigned int            state;
+        unsigned long           base;           /* Controller base address */
+        int                     irq;            /* Controller IRQ */
+        struct scatterlist      cur_sg;         /* Current controller buffer */
+        dma_addr_t              dma_addr;
+        unsigned int            dma_len;
+};
+
 #if 0
 typedef enum {
         dma_size_8      = 1,
@@ -44,15 +54,15 @@ typedef enum {
 #define CR      (IOMD_IO0CR - IOMD_IO0CURA)
 #define ST      (IOMD_IO0ST - IOMD_IO0CURA)
 
-static void iomd_get_next_sg(struct scatterlist *sg, dma_t *dma)
+static void iomd_get_next_sg(struct scatterlist *sg, struct iomd_dma *idma)
 {
         unsigned long end, offset, flags = 0;
 
-        if (dma->sg) {
-                sg->dma_address = dma->sg->dma_address;
+        if (idma->dma.sg) {
+                sg->dma_address = idma->dma_addr;
                 offset = sg->dma_address & ~PAGE_MASK;
 
-                end = offset + dma->sg->length;
+                end = offset + idma->dma_len;
 
                 if (end > PAGE_SIZE)
                         end = PAGE_SIZE;
@@ -62,15 +72,17 @@ static void iomd_get_next_sg(struct scatterlist *sg, dma_t *dma)
 
                 sg->length = end - TRANSFER_SIZE;
 
-                dma->sg->length -= end - offset;
-                dma->sg->dma_address += end - offset;
+                idma->dma_len -= end - offset;
+                idma->dma_addr += end - offset;
 
-                if (dma->sg->length == 0) {
-                        if (dma->sgcount > 1) {
-                                dma->sg++;
-                                dma->sgcount--;
+                if (idma->dma_len == 0) {
+                        if (idma->dma.sgcount > 1) {
+                                idma->dma.sg = sg_next(idma->dma.sg);
+                                idma->dma_addr = idma->dma.sg->dma_address;
+                                idma->dma_len = idma->dma.sg->length;
+                                idma->dma.sgcount--;
                         } else {
-                                dma->sg = NULL;
+                                idma->dma.sg = NULL;
                                 flags |= DMA_END_S;
                         }
                 }
@@ -85,8 +97,8 @@ static void iomd_get_next_sg(struct scatterlist *sg, dma_t *dma)
 
 static irqreturn_t iomd_dma_handle(int irq, void *dev_id)
 {
-        dma_t *dma = (dma_t *)dev_id;
-        unsigned long base = dma->dma_base;
+        struct iomd_dma *idma = dev_id;
+        unsigned long base = idma->base;
 
         do {
                 unsigned int status;
@@ -95,93 +107,99 @@ static irqreturn_t iomd_dma_handle(int irq, void *dev_id)
                 if (!(status & DMA_ST_INT))
                         return IRQ_HANDLED;
 
-                if ((dma->state ^ status) & DMA_ST_AB)
-                        iomd_get_next_sg(&dma->cur_sg, dma);
+                if ((idma->state ^ status) & DMA_ST_AB)
+                        iomd_get_next_sg(&idma->cur_sg, idma);
 
                 switch (status & (DMA_ST_OFL | DMA_ST_AB)) {
                 case DMA_ST_OFL:                        /* OIA */
                 case DMA_ST_AB:                         /* .IB */
-                        iomd_writel(dma->cur_sg.dma_address, base + CURA);
-                        iomd_writel(dma->cur_sg.length, base + ENDA);
-                        dma->state = DMA_ST_AB;
+                        iomd_writel(idma->cur_sg.dma_address, base + CURA);
+                        iomd_writel(idma->cur_sg.length, base + ENDA);
+                        idma->state = DMA_ST_AB;
                         break;
 
                 case DMA_ST_OFL | DMA_ST_AB:            /* OIB */
                 case 0:                                 /* .IA */
-                        iomd_writel(dma->cur_sg.dma_address, base + CURB);
-                        iomd_writel(dma->cur_sg.length, base + ENDB);
-                        dma->state = 0;
+                        iomd_writel(idma->cur_sg.dma_address, base + CURB);
+                        iomd_writel(idma->cur_sg.length, base + ENDB);
+                        idma->state = 0;
                         break;
                 }
 
                 if (status & DMA_ST_OFL &&
-                    dma->cur_sg.length == (DMA_END_S|DMA_END_L))
+                    idma->cur_sg.length == (DMA_END_S|DMA_END_L))
                         break;
         } while (1);
 
-        dma->state = ~DMA_ST_AB;
+        idma->state = ~DMA_ST_AB;
         disable_irq(irq);
 
         return IRQ_HANDLED;
 }
 
-static int iomd_request_dma(dmach_t channel, dma_t *dma)
+static int iomd_request_dma(unsigned int chan, dma_t *dma)
 {
-        return request_irq(dma->dma_irq, iomd_dma_handle,
-                           IRQF_DISABLED, dma->device_id, dma);
+        struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
+
+        return request_irq(idma->irq, iomd_dma_handle,
+                           IRQF_DISABLED, idma->dma.device_id, idma);
 }
 
-static void iomd_free_dma(dmach_t channel, dma_t *dma)
+static void iomd_free_dma(unsigned int chan, dma_t *dma)
 {
-        free_irq(dma->dma_irq, dma);
+        struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
+
+        free_irq(idma->irq, idma);
 }
 
-static void iomd_enable_dma(dmach_t channel, dma_t *dma)
+static void iomd_enable_dma(unsigned int chan, dma_t *dma)
 {
-        unsigned long dma_base = dma->dma_base;
+        struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
+        unsigned long dma_base = idma->base;
         unsigned int ctrl = TRANSFER_SIZE | DMA_CR_E;
 
-        if (dma->invalid) {
-                dma->invalid = 0;
+        if (idma->dma.invalid) {
+                idma->dma.invalid = 0;
 
                 /*
                  * Cope with ISA-style drivers which expect cache
                  * coherence.
                  */
-                if (!dma->sg) {
-                        dma->sg = &dma->buf;
-                        dma->sgcount = 1;
-                        dma->buf.length = dma->count;
-                        dma->buf.dma_address = dma_map_single(NULL,
-                                dma->addr, dma->count,
-                                dma->dma_mode == DMA_MODE_READ ?
+                if (!idma->dma.sg) {
+                        idma->dma.sg = &idma->dma.buf;
+                        idma->dma.sgcount = 1;
+                        idma->dma.buf.length = idma->dma.count;
+                        idma->dma.buf.dma_address = dma_map_single(NULL,
+                                idma->dma.addr, idma->dma.count,
+                                idma->dma.dma_mode == DMA_MODE_READ ?
                                 DMA_FROM_DEVICE : DMA_TO_DEVICE);
                 }
 
                 iomd_writeb(DMA_CR_C, dma_base + CR);
-                dma->state = DMA_ST_AB;
+                idma->state = DMA_ST_AB;
         }
-                
-        if (dma->dma_mode == DMA_MODE_READ)
+
+        if (idma->dma.dma_mode == DMA_MODE_READ)
                 ctrl |= DMA_CR_D;
 
         iomd_writeb(ctrl, dma_base + CR);
-        enable_irq(dma->dma_irq);
+        enable_irq(idma->irq);
 }
 
-static void iomd_disable_dma(dmach_t channel, dma_t *dma)
+static void iomd_disable_dma(unsigned int chan, dma_t *dma)
 {
-        unsigned long dma_base = dma->dma_base;
+        struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
+        unsigned long dma_base = idma->base;
         unsigned long flags;
 
         local_irq_save(flags);
-        if (dma->state != ~DMA_ST_AB)
-                disable_irq(dma->dma_irq);
+        if (idma->state != ~DMA_ST_AB)
+                disable_irq(idma->irq);
         iomd_writeb(0, dma_base + CR);
         local_irq_restore(flags);
 }
 
-static int iomd_set_dma_speed(dmach_t channel, dma_t *dma, int cycle)
+static int iomd_set_dma_speed(unsigned int chan, dma_t *dma, int cycle)
 {
         int tcr, speed;
 
@@ -197,7 +215,7 @@ static int iomd_set_dma_speed(dmach_t channel, dma_t *dma, int cycle)
         tcr = iomd_readb(IOMD_DMATCR);
         speed &= 3;
 
-        switch (channel) {
+        switch (chan) {
         case DMA_0:
                 tcr = (tcr & ~0x03) | speed;
                 break;
@@ -236,16 +254,22 @@ static struct fiq_handler fh = {
         .name   = "floppydma"
 };
 
-static void floppy_enable_dma(dmach_t channel, dma_t *dma)
+struct floppy_dma {
+        struct dma_struct       dma;
+        unsigned int            fiq;
+};
+
+static void floppy_enable_dma(unsigned int chan, dma_t *dma)
 {
+        struct floppy_dma *fdma = container_of(dma, struct floppy_dma, dma);
         void *fiqhandler_start;
         unsigned int fiqhandler_length;
         struct pt_regs regs;
 
-        if (dma->sg)
+        if (fdma->dma.sg)
                 BUG();
 
-        if (dma->dma_mode == DMA_MODE_READ) {
+        if (fdma->dma.dma_mode == DMA_MODE_READ) {
                 extern unsigned char floppy_fiqin_start, floppy_fiqin_end;
                 fiqhandler_start = &floppy_fiqin_start;
                 fiqhandler_length = &floppy_fiqin_end - &floppy_fiqin_start;
@@ -255,8 +279,8 @@ static void floppy_enable_dma(dmach_t channel, dma_t *dma)
                 fiqhandler_length = &floppy_fiqout_end - &floppy_fiqout_start;
         }
 
-        regs.ARM_r9  = dma->count;
-        regs.ARM_r10 = (unsigned long)dma->addr;
+        regs.ARM_r9  = fdma->dma.count;
+        regs.ARM_r10 = (unsigned long)fdma->dma.addr;
         regs.ARM_fp  = (unsigned long)FLOPPYDMA_BASE;
 
         if (claim_fiq(&fh)) {
@@ -266,16 +290,17 @@ static void floppy_enable_dma(dmach_t channel, dma_t *dma)
 
         set_fiq_handler(fiqhandler_start, fiqhandler_length);
         set_fiq_regs(&regs);
-        enable_fiq(dma->dma_irq);
+        enable_fiq(fdma->fiq);
 }
 
-static void floppy_disable_dma(dmach_t channel, dma_t *dma)
+static void floppy_disable_dma(unsigned int chan, dma_t *dma)
 {
-        disable_fiq(dma->dma_irq);
+        struct floppy_dma *fdma = container_of(dma, struct floppy_dma, dma);
+        disable_fiq(fdma->fiq);
         release_fiq(&fh);
 }
 
-static int floppy_get_residue(dmach_t channel, dma_t *dma)
+static int floppy_get_residue(unsigned int chan, dma_t *dma)
 {
         struct pt_regs regs;
         get_fiq_regs(&regs);
@@ -292,7 +317,7 @@ static struct dma_ops floppy_dma_ops = {
 /*
  * This is virtual DMA - we don't need anything here.
  */
-static void sound_enable_disable_dma(dmach_t channel, dma_t *dma)
+static void sound_enable_disable_dma(unsigned int chan, dma_t *dma)
 {
 }
 
@@ -302,8 +327,24 @@ static struct dma_ops sound_dma_ops = {
         .disable        = sound_enable_disable_dma,
 };
 
-void __init arch_dma_init(dma_t *dma)
+static struct iomd_dma iomd_dma[6];
+
+static struct floppy_dma floppy_dma = {
+        .dma            = {
+                .d_ops  = &floppy_dma_ops,
+        },
+        .fiq            = FIQ_FLOPPYDATA,
+};
+
+static dma_t sound_dma = {
+        .d_ops          = &sound_dma_ops,
+};
+
+static int __init rpc_dma_init(void)
 {
+        unsigned int i;
+        int ret;
+
         iomd_writeb(0, IOMD_IO0CR);
         iomd_writeb(0, IOMD_IO1CR);
         iomd_writeb(0, IOMD_IO2CR);
@@ -311,31 +352,39 @@ void __init arch_dma_init(dma_t *dma)
 
         iomd_writeb(0xa0, IOMD_DMATCR);
 
-        dma[DMA_0].dma_base             = IOMD_IO0CURA;
-        dma[DMA_0].dma_irq              = IRQ_DMA0;
-        dma[DMA_0].d_ops                = &iomd_dma_ops;
-        dma[DMA_1].dma_base             = IOMD_IO1CURA;
-        dma[DMA_1].dma_irq              = IRQ_DMA1;
-        dma[DMA_1].d_ops                = &iomd_dma_ops;
-        dma[DMA_2].dma_base             = IOMD_IO2CURA;
-        dma[DMA_2].dma_irq              = IRQ_DMA2;
-        dma[DMA_2].d_ops                = &iomd_dma_ops;
-        dma[DMA_3].dma_base             = IOMD_IO3CURA;
-        dma[DMA_3].dma_irq              = IRQ_DMA3;
-        dma[DMA_3].d_ops                = &iomd_dma_ops;
-        dma[DMA_S0].dma_base            = IOMD_SD0CURA;
-        dma[DMA_S0].dma_irq             = IRQ_DMAS0;
-        dma[DMA_S0].d_ops               = &iomd_dma_ops;
-        dma[DMA_S1].dma_base            = IOMD_SD1CURA;
-        dma[DMA_S1].dma_irq             = IRQ_DMAS1;
-        dma[DMA_S1].d_ops               = &iomd_dma_ops;
-        dma[DMA_VIRTUAL_FLOPPY].dma_irq = FIQ_FLOPPYDATA;
-        dma[DMA_VIRTUAL_FLOPPY].d_ops   = &floppy_dma_ops;
-        dma[DMA_VIRTUAL_SOUND].d_ops    = &sound_dma_ops;
-
         /*
          * Setup DMA channels 2,3 to be for podules
          * and channels 0,1 for internal devices
          */
         iomd_writeb(DMA_EXT_IO3|DMA_EXT_IO2, IOMD_DMAEXT);
+
+        iomd_dma[DMA_0].base    = IOMD_IO0CURA;
+        iomd_dma[DMA_0].irq     = IRQ_DMA0;
+        iomd_dma[DMA_1].base    = IOMD_IO1CURA;
+        iomd_dma[DMA_1].irq     = IRQ_DMA1;
+        iomd_dma[DMA_2].base    = IOMD_IO2CURA;
+        iomd_dma[DMA_2].irq     = IRQ_DMA2;
+        iomd_dma[DMA_3].base    = IOMD_IO3CURA;
+        iomd_dma[DMA_3].irq     = IRQ_DMA3;
+        iomd_dma[DMA_S0].base   = IOMD_SD0CURA;
+        iomd_dma[DMA_S0].irq    = IRQ_DMAS0;
+        iomd_dma[DMA_S1].base   = IOMD_SD1CURA;
+        iomd_dma[DMA_S1].irq    = IRQ_DMAS1;
+
+        for (i = DMA_0; i <= DMA_S1; i++) {
+                iomd_dma[i].dma.d_ops = &iomd_dma_ops;
+
+                ret = isa_dma_add(i, &iomd_dma[i].dma);
+                if (ret)
+                        printk("IOMDDMA%u: unable to register: %d\n", i, ret);
+        }
+
+        ret = isa_dma_add(DMA_VIRTUAL_FLOPPY, &floppy_dma.dma);
+        if (ret)
+                printk("IOMDFLOPPY: unable to register: %d\n", ret);
+        ret = isa_dma_add(DMA_VIRTUAL_SOUND, &sound_dma);
+        if (ret)
+                printk("IOMDSOUND: unable to register: %d\n", ret);
+        return 0;
 }
+core_initcall(rpc_dma_init);
diff --git a/arch/arm/mach-rpc/include/mach/isa-dma.h b/arch/arm/mach-rpc/include/mach/isa-dma.h
index bad720548587..67bfc6719c34 100644
--- a/arch/arm/mach-rpc/include/mach/isa-dma.h
+++ b/arch/arm/mach-rpc/include/mach/isa-dma.h
@@ -23,5 +23,7 @@
 
 #define DMA_FLOPPY              DMA_VIRTUAL_FLOPPY
 
+#define IOMD_DMA_BOUNDARY       (PAGE_SIZE - 1)
+
 #endif /* _ASM_ARCH_DMA_H */
 
diff --git a/arch/arm/mach-rpc/include/mach/system.h b/arch/arm/mach-rpc/include/mach/system.h
index bd7268ba17e2..45c7b935dc45 100644
--- a/arch/arm/mach-rpc/include/mach/system.h
+++ b/arch/arm/mach-rpc/include/mach/system.h
@@ -16,7 +16,7 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         iomd_writeb(0, IOMD_ROMCR0);
 
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
new file mode 100644
index 000000000000..ce1ec69806a1
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
@@ -0,0 +1,23 @@
+/* arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - GPIO bank numbering
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
+
+#define S3C2410_GPIO_BANKA   (32*0)
+#define S3C2410_GPIO_BANKB   (32*1)
+#define S3C2410_GPIO_BANKC   (32*2)
+#define S3C2410_GPIO_BANKD   (32*3)
+#define S3C2410_GPIO_BANKE   (32*4)
+#define S3C2410_GPIO_BANKF   (32*5)
+#define S3C2410_GPIO_BANKG   (32*6)
+#define S3C2410_GPIO_BANKH   (32*7)
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h
index 00476a573bbe..51a88cf9526b 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio.h
@@ -23,3 +23,6 @@
 #define ARCH_NR_GPIOS   (256 + CONFIG_S3C24XX_GPIO_EXTRA)
 
 #include <asm-generic/gpio.h>
+#include <mach/gpio-nrs.h>
+
+#define S3C_GPIO_END    (S3C2410_GPIO_BANKH + 32)
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h
index 49efce8cd4a7..2a2384ffa7b1 100644
--- a/arch/arm/mach-s3c2410/include/mach/irqs.h
+++ b/arch/arm/mach-s3c2410/include/mach/irqs.h
@@ -80,7 +80,7 @@
 #define IRQ_EINT22     S3C2410_IRQ(50)
 #define IRQ_EINT23     S3C2410_IRQ(51)
 
-
+#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4)
 #define IRQ_EINT(x)    (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
 
 #define IRQ_LCD_FIFO   S3C2410_IRQ(52)
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
index 321077613067..35a03df473fc 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -14,16 +14,7 @@
 #ifndef __ASM_ARCH_REGS_GPIO_H
 #define __ASM_ARCH_REGS_GPIO_H
 
-#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
-
-#define S3C2410_GPIO_BANKA   (32*0)
-#define S3C2410_GPIO_BANKB   (32*1)
-#define S3C2410_GPIO_BANKC   (32*2)
-#define S3C2410_GPIO_BANKD   (32*3)
-#define S3C2410_GPIO_BANKE   (32*4)
-#define S3C2410_GPIO_BANKF   (32*5)
-#define S3C2410_GPIO_BANKG   (32*6)
-#define S3C2410_GPIO_BANKH   (32*7)
+#include <mach/gpio-nrs.h>
 
 #ifdef CONFIG_CPU_S3C2400
 #define S3C24XX_GPIO_BASE(x)  S3C2400_GPIO_BASE(x)
diff --git a/arch/arm/mach-s3c2410/include/mach/system-reset.h b/arch/arm/mach-s3c2410/include/mach/system-reset.h
index 7613d0a384ba..b8687f71c304 100644
--- a/arch/arm/mach-s3c2410/include/mach/system-reset.h
+++ b/arch/arm/mach-s3c2410/include/mach/system-reset.h
@@ -22,7 +22,7 @@
 extern void (*s3c24xx_reset_hook)(void);
 
 static void
-arch_reset(char mode)
+arch_reset(char mode, const char *cmd)
 {
         struct clk *wdtclk;
 
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 821a1668c3ac..7a7c4da4c256 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -203,7 +203,7 @@ static void __init h1940_map_io(void)
 #ifdef CONFIG_PM_H1940
         memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
 #endif
-        s3c2410_pm_init();
+        s3c_pm_init();
 }
 
 static void __init h1940_init_irq(void)
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index 9678a53ceeb1..9f1ba9b63f70 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -355,7 +355,7 @@ static void __init qt2410_machine_init(void)
         s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);
 
         platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
-        s3c2410_pm_init();
+        s3c_pm_init();
 }
 
 MACHINE_START(QT2410, "QT2410")
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index a6970f613192..87fc481d92d4 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -37,21 +37,14 @@
 #include <plat/cpu.h>
 #include <plat/pm.h>
 
-#ifdef CONFIG_S3C2410_PM_DEBUG
-extern void pm_dbg(const char *fmt, ...);
-#define DBG(fmt...) pm_dbg(fmt)
-#else
-#define DBG(fmt...) printk(KERN_DEBUG fmt)
-#endif
-
 static void s3c2410_pm_prepare(void)
 {
         /* ensure at least GSTATUS3 has the resume address */
 
-        __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2410_GSTATUS3);
+        __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3);
 
-        DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
-        DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
+        S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
+        S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
 
         if (machine_is_h1940()) {
                 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index ecddbbb34832..72c266aee141 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -494,7 +494,7 @@ static int jive_pm_suspend(struct sys_device *sd, pm_message_t state)
          * correct address to resume from. */
 
         __raw_writel(0x2BED, S3C2412_INFORM0);
-        __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2412_INFORM1);
+        __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
 
         return 0;
 }
@@ -630,7 +630,7 @@ static void __init jive_machine_init(void)
 
         /* initialise the power management now we've setup everything. */
 
-        s3c2410_pm_init();
+        s3c_pm_init();
 
         s3c_device_nand.dev.platform_data = &jive_nand_info;
 
diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c
index 217e9e4ed45f..c9cfe40e21f6 100644
--- a/arch/arm/mach-s3c2412/pm.c
+++ b/arch/arm/mach-s3c2412/pm.c
@@ -85,7 +85,7 @@ static struct sleep_save s3c2412_sleep[] = {
 
 static int s3c2412_pm_suspend(struct sys_device *dev, pm_message_t state)
 {
-        s3c2410_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
+        s3c_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
         return 0;
 }
 
@@ -98,7 +98,7 @@ static int s3c2412_pm_resume(struct sys_device *dev)
         tmp |=  S3C2412_PWRCFG_STANDBYWFI_IDLE;
         __raw_writel(tmp, S3C2412_PWRCFG);
 
-        s3c2410_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
+        s3c_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
         return 0;
 }
 
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index 12d378f84ad2..bc8d8d1ebd1a 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -203,7 +203,7 @@ static void __init rx3715_init_machine(void)
 #ifdef CONFIG_PM_H1940
         memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
 #endif
-        s3c2410_pm_init();
+        s3c_pm_init();
 
         s3c24xx_fb_set_platdata(&rx3715_fb_info);
         platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices));
diff --git a/arch/arm/mach-s3c24a0/include/mach/irqs.h b/arch/arm/mach-s3c24a0/include/mach/irqs.h
index ae8c0e359783..83ce2a7a9dae 100644
--- a/arch/arm/mach-s3c24a0/include/mach/irqs.h
+++ b/arch/arm/mach-s3c24a0/include/mach/irqs.h
@@ -70,6 +70,8 @@
 #define IRQ_EINT17      S3C2410_IRQ(49)
 #define IRQ_EINT18      S3C2410_IRQ(50)
 
+#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT00)
+
 /* SUB IRQS */
 #define IRQ_S3CUART_RX0         S3C2410_IRQ(51) /* 67 */
 #define IRQ_S3CUART_TX0         S3C2410_IRQ(52)
diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h
index cff27d813fc6..baf1c0f1ea5a 100644
--- a/arch/arm/mach-s3c6400/include/mach/map.h
+++ b/arch/arm/mach-s3c6400/include/mach/map.h
@@ -52,6 +52,9 @@
 #define S3C64XX_PA_VIC0         (0x71200000)
 #define S3C64XX_PA_VIC1         (0x71300000)
 
+#define S3C64XX_PA_MODEM        (0x74108000)
+#define S3C64XX_VA_MODEM        S3C_ADDR(0x00600000)
+
 /* place VICs close together */
 #define S3C_VA_VIC0             (S3C_VA_IRQ + 0x00)
 #define S3C_VA_VIC1             (S3C_VA_IRQ + 0x10000)
diff --git a/arch/arm/mach-s3c6400/include/mach/system.h b/arch/arm/mach-s3c6400/include/mach/system.h
index 652bbc403f0b..090cfd969bc7 100644
--- a/arch/arm/mach-s3c6400/include/mach/system.h
+++ b/arch/arm/mach-s3c6400/include/mach/system.h
@@ -16,7 +16,7 @@ static void arch_idle(void)
         /* nothing here yet */
 }
 
-static void arch_reset(char mode)
+static void arch_reset(char mode, const char *cmd)
 {
         /* nothing here yet */
 }
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig
index f99d9013905f..81ffff7ed498 100644
--- a/arch/arm/mach-sa1100/Kconfig
+++ b/arch/arm/mach-sa1100/Kconfig
@@ -71,19 +71,9 @@ config SA1100_H3600
           <http://www.handhelds.org/Compaq/index.html#iPAQ_H3600>
           <http://www.compaq.com/products/handhelds/pocketpc/>
 
-config SA1100_H3800
-        bool "Compaq iPAQ H3800"
-        help
-          Say Y here if you intend to run this kernel on the Compaq iPAQ H3800
-          series handheld computer.  Information about this machine and the
-          Linux port to this machine can be found at:
-
-          <http://www.handhelds.org/Compaq/index.html#iPAQ_H3800>
-          <http://www.compaq.com/products/handhelds/pocketpc/>
-
 config SA1100_H3XXX
         bool
-        depends on SA1100_H3100 || SA1100_H3600 || SA1100_H3800
+        depends on SA1100_H3100 || SA1100_H3600
         default y
 
 config SA1100_BADGE4
@@ -157,15 +147,6 @@ config SA1100_SSP
           This isn't for audio support, but for attached sensors and
           other devices, eg for BadgePAD 4 sensor support.
 
-config H3600_SLEEVE
-        tristate "Compaq iPAQ Handheld sleeve support"
-        depends on SA1100_H3100 || SA1100_H3600
-        help
-          Choose this option to enable support for extension packs (sleeves)
-          for the Compaq iPAQ H3XXX series of handheld computers.  This option
-          is required for the CF, PCMCIA, Bluetooth and GSM/GPRS extension
-          packs.
-
 endmenu
 
 endif
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index 2052eb88c961..bbf2ebcc3066 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -25,6 +25,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/timer.h>
+#include <linux/gpio.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -145,7 +146,8 @@ static struct locomo_driver collie_uart_driver = {
         .remove = collie_uart_remove,
 };
 
-static int __init collie_uart_init(void) {
+static int __init collie_uart_init(void)
+{
         return locomo_driver_register(&collie_uart_driver);
 }
 device_initcall(collie_uart_init);
@@ -195,18 +197,34 @@ static struct mtd_partition collie_partitions[] = {
         }
 };
 
+static int collie_flash_init(void)
+{
+        int rc = gpio_request(COLLIE_GPIO_VPEN, "flash Vpp enable");
+        if (rc)
+                return rc;
+
+        rc = gpio_direction_output(COLLIE_GPIO_VPEN, 1);
+        if (rc)
+                gpio_free(COLLIE_GPIO_VPEN);
+
+        return rc;
+}
+
 static void collie_set_vpp(int vpp)
 {
-        write_scoop_reg(&colliescoop_device.dev, SCOOP_GPCR, read_scoop_reg(&colliescoop_device.dev, SCOOP_GPCR) | COLLIE_SCP_VPEN);
-        if (vpp)
-                write_scoop_reg(&colliescoop_device.dev, SCOOP_GPWR, read_scoop_reg(&colliescoop_device.dev, SCOOP_GPWR) | COLLIE_SCP_VPEN);
-        else
-                write_scoop_reg(&colliescoop_device.dev, SCOOP_GPWR, read_scoop_reg(&colliescoop_device.dev, SCOOP_GPWR) & ~COLLIE_SCP_VPEN);
+        gpio_set_value(COLLIE_GPIO_VPEN, vpp);
+}
+
+static void collie_flash_exit(void)
+{
+        gpio_free(COLLIE_GPIO_VPEN);
 }
 
 static struct flash_platform_data collie_flash_data = {
         .map_name       = "cfi_probe",
+        .init           = collie_flash_init,
         .set_vpp        = collie_set_vpp,
+        .exit           = collie_flash_exit,
         .parts          = collie_partitions,
         .nr_parts       = ARRAY_SIZE(collie_partitions),
 };
diff --git a/arch/arm/mach-sa1100/collie_pm.c b/arch/arm/mach-sa1100/collie_pm.c
index b39307f26b52..444f266ecc06 100644
--- a/arch/arm/mach-sa1100/collie_pm.c
+++ b/arch/arm/mach-sa1100/collie_pm.c
@@ -22,6 +22,7 @@
 #include <linux/interrupt.h>
 #include <linux/device.h>
 #include <linux/platform_device.h>
+#include <linux/gpio.h>
 
 #include <asm/irq.h>
 #include <mach/hardware.h>
@@ -58,6 +59,9 @@ static void collie_charger_init(void)
                 return;
         }
 
+        gpio_request(COLLIE_GPIO_CHARGE_ON, "charge on");
+        gpio_direction_output(COLLIE_GPIO_CHARGE_ON, 1);
+
         ucb1x00_io_set_dir(ucb, 0, COLLIE_TC35143_GPIO_MBAT_ON | COLLIE_TC35143_GPIO_TMP_ON |
                                    COLLIE_TC35143_GPIO_BBAT_ON);
         return;
@@ -73,17 +77,11 @@ static void collie_measure_temp(int on)
 
 static void collie_charge(int on)
 {
-        extern struct platform_device colliescoop_device;
-
         /* Zaurus seems to contain LTC1731; it should know when to
          * stop charging itself, so setting charge on should be
          * relatively harmless (as long as it is not done too often).
          */
-        if (on) {
-                set_scoop_gpio(&colliescoop_device.dev, COLLIE_SCP_CHARGE_ON);
-        } else {
-                reset_scoop_gpio(&colliescoop_device.dev, COLLIE_SCP_CHARGE_ON);
-        }
+        gpio_set_value(COLLIE_GPIO_CHARGE_ON, on);
 }
 
 static void collie_discharge(int on)
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c
index af25a78d705d..0eb2f159578b 100644
--- a/arch/arm/mach-sa1100/h3600.c
+++ b/arch/arm/mach-sa1100/h3600.c
@@ -42,19 +42,12 @@
 #include <asm/mach/serial_sa1100.h>
 
 #include <mach/h3600.h>
-
-#if defined (CONFIG_SA1100_H3600) || defined (CONFIG_SA1100_H3100)
 #include <mach/h3600_gpio.h>
-#endif
-
-#ifdef CONFIG_SA1100_H3800
-#include <mach/h3600_asic.h>
-#endif
 
 #include "generic.h"
 
-struct ipaq_model_ops ipaq_model_ops;
-EXPORT_SYMBOL(ipaq_model_ops);
+void (*assign_h3600_egpio)(enum ipaq_egpio_type x, int level);
+EXPORT_SYMBOL(assign_h3600_egpio);
 
 static struct mtd_partition h3xxx_partitions[] = {
         {
@@ -63,41 +56,9 @@ static struct mtd_partition h3xxx_partitions[] = {
                 .offset         = 0,
                 .mask_flags     = MTD_WRITEABLE,  /* force read-only */
         }, {
-#ifdef CONFIG_MTD_2PARTS_IPAQ
-                .name           = "H3XXX root jffs2",
+                .name           = "H3XXX rootfs",
                 .size           = MTDPART_SIZ_FULL,
                 .offset         = 0x00040000,
-#else
-                .name           = "H3XXX kernel",
-                .size           = 0x00080000,
-                .offset         = 0x00040000,
-        }, {
-                .name           = "H3XXX params",
-                .size           = 0x00040000,
-                .offset         = 0x000C0000,
-        }, {
-#ifdef CONFIG_JFFS2_FS
-                .name           = "H3XXX root jffs2",
-                .size           = MTDPART_SIZ_FULL,
-                .offset         = 0x00100000,
-#else
-                .name           = "H3XXX initrd",
-                .size           = 0x00100000,
-                .offset         = 0x00100000,
-        }, {
-                .name           = "H3XXX root cramfs",
-                .size           = 0x00300000,
-                .offset         = 0x00200000,
-        }, {
-                .name           = "H3XXX usr cramfs",
-                .size           = 0x00800000,
-                .offset         = 0x00500000,
-        }, {
-                .name           = "H3XXX usr local",
-                .size           = MTDPART_SIZ_FULL,
-                .offset         = 0x00d00000,
-#endif
-#endif
         }
 };
 
@@ -131,11 +92,7 @@ static int h3600_irda_set_power(struct device *dev, unsigned int state)
 
 static void h3600_irda_set_speed(struct device *dev, unsigned int speed)
 {
-        if (speed < 4000000) {
-                clr_h3600_egpio(IPAQ_EGPIO_IR_FSEL);
-        } else {
-                set_h3600_egpio(IPAQ_EGPIO_IR_FSEL);
-        }
+        assign_h3600_egpio(IPAQ_EGPIO_IR_FSEL, !(speed < 4000000));
 }
 
 static struct irda_platform_data h3600_irda_data = {
@@ -266,12 +223,6 @@ static void __init h3xxx_map_io(void)
         sa1100fb_lcd_power = h3xxx_lcd_power;
 }
 
-static __inline__ void do_blank(int setp)
-{
-        if (ipaq_model_ops.blank_callback)
-                ipaq_model_ops.blank_callback(1-setp);
-}
-
 /************************* H3100 *************************/
 
 #ifdef CONFIG_SA1100_H3100
@@ -289,7 +240,6 @@ static void h3100_control_egpio(enum ipaq_egpio_type x, int setp)
         case IPAQ_EGPIO_LCD_POWER:
                 egpio |= EGPIO_H3600_LCD_ON;
                 gpio  |= GPIO_H3100_LCD_3V_ON;
-                do_blank(setp);
                 break;
         case IPAQ_EGPIO_LCD_ENABLE:
                 break;
@@ -343,25 +293,6 @@ static void h3100_control_egpio(enum ipaq_egpio_type x, int setp)
         }
 }
 
-static unsigned long h3100_read_egpio(void)
-{
-        return h3100_egpio;
-}
-
-static int h3100_pm_callback(int req)
-{
-        if (ipaq_model_ops.pm_callback_aux)
-                return ipaq_model_ops.pm_callback_aux(req);
-        return 0;
-}
-
-static struct ipaq_model_ops h3100_model_ops __initdata = {
-        .generic_name   = "3100",
-        .control        = h3100_control_egpio,
-        .read           = h3100_read_egpio,
-        .pm_callback    = h3100_pm_callback
-};
-
 #define H3100_DIRECT_EGPIO (GPIO_H3100_BT_ON      \
                           | GPIO_H3100_GPIO3      \
                           | GPIO_H3100_QMUTE      \
@@ -387,7 +318,7 @@ static void __init h3100_map_io(void)
         GAFR &= ~H3100_DIRECT_EGPIO;
 
         H3100_EGPIO = h3100_egpio;
-        ipaq_model_ops = h3100_model_ops;
+        assign_h3600_egpio = h3100_control_egpio;
 }
 
 MACHINE_START(H3100, "Compaq iPAQ H3100")
@@ -420,7 +351,6 @@ static void h3600_control_egpio(enum ipaq_egpio_type x, int setp)
                          EGPIO_H3600_LCD_PCI |
                          EGPIO_H3600_LCD_5V_ON |
                          EGPIO_H3600_LVDD_ON;
-                do_blank(setp);
                 break;
         case IPAQ_EGPIO_LCD_ENABLE:
                 break;
@@ -471,25 +401,6 @@ static void h3600_control_egpio(enum ipaq_egpio_type x, int setp)
         }
 }
 
-static unsigned long h3600_read_egpio(void)
-{
-        return h3600_egpio;
-}
-
-static int h3600_pm_callback(int req)
-{
-        if (ipaq_model_ops.pm_callback_aux)
-                return ipaq_model_ops.pm_callback_aux(req);
-        return 0;
-}
-
-static struct ipaq_model_ops h3600_model_ops __initdata = {
-        .generic_name   = "3600",
-        .control        = h3600_control_egpio,
-        .read           = h3600_read_egpio,
-        .pm_callback    = h3600_pm_callback
-};
-
 static void __init h3600_map_io(void)
 {
         h3xxx_map_io();
@@ -504,7 +415,7 @@ static void __init h3600_map_io(void)
                GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9  | GPIO_LDD8;
 
         H3600_EGPIO = h3600_egpio;         /* Maintains across sleep? */
-        ipaq_model_ops = h3600_model_ops;
+        assign_h3600_egpio = h3600_control_egpio;
 }
 
 MACHINE_START(H3600, "Compaq iPAQ H3600")
@@ -519,388 +430,3 @@ MACHINE_END
 
 #endif /* CONFIG_SA1100_H3600 */
 
-#ifdef CONFIG_SA1100_H3800
-
-#define SET_ASIC1(x) \
-   do {if (setp) { H3800_ASIC1_GPIO_OUT |= (x); } else { H3800_ASIC1_GPIO_OUT &= ~(x); }} while(0)
-
-#define SET_ASIC2(x) \
-   do {if (setp) { H3800_ASIC2_GPIOPIOD |= (x); } else { H3800_ASIC2_GPIOPIOD &= ~(x); }} while(0)
-
-#define CLEAR_ASIC1(x) \
-   do {if (setp) { H3800_ASIC1_GPIO_OUT &= ~(x); } else { H3800_ASIC1_GPIO_OUT |= (x); }} while(0)
-
-#define CLEAR_ASIC2(x) \
-   do {if (setp) { H3800_ASIC2_GPIOPIOD &= ~(x); } else { H3800_ASIC2_GPIOPIOD |= (x); }} while(0)
-
-
-/*
-  On screen enable, we get
-
-     h3800_video_power_on(1)
-     LCD controller starts
-     h3800_video_lcd_enable(1)
-
-  On screen disable, we get
-
-     h3800_video_lcd_enable(0)
-     LCD controller stops
-     h3800_video_power_on(0)
-*/
-
-
-static void h3800_video_power_on(int setp)
-{
-        if (setp) {
-                H3800_ASIC1_GPIO_OUT |= GPIO1_LCD_ON;
-                msleep(30);
-                H3800_ASIC1_GPIO_OUT |= GPIO1_VGL_ON;
-                msleep(5);
-                H3800_ASIC1_GPIO_OUT |= GPIO1_VGH_ON;
-                msleep(50);
-                H3800_ASIC1_GPIO_OUT |= GPIO1_LCD_5V_ON;
-                msleep(5);
-        } else {
-                msleep(5);
-                H3800_ASIC1_GPIO_OUT &= ~GPIO1_LCD_5V_ON;
-                msleep(50);
-                H3800_ASIC1_GPIO_OUT &= ~GPIO1_VGL_ON;
-                msleep(5);
-                H3800_ASIC1_GPIO_OUT &= ~GPIO1_VGH_ON;
-                msleep(100);
-                H3800_ASIC1_GPIO_OUT &= ~GPIO1_LCD_ON;
-        }
-}
-
-static void h3800_video_lcd_enable(int setp)
-{
-        if (setp) {
-                msleep(17);     // Wait one from before turning on
-                H3800_ASIC1_GPIO_OUT |= GPIO1_LCD_PCI;
-        } else {
-                H3800_ASIC1_GPIO_OUT &= ~GPIO1_LCD_PCI;
-                msleep(30);     // Wait before turning off
-        }
-}
-
-
-static void h3800_control_egpio(enum ipaq_egpio_type x, int setp)
-{
-        switch (x) {
-        case IPAQ_EGPIO_LCD_POWER:
-                h3800_video_power_on(setp);
-                break;
-        case IPAQ_EGPIO_LCD_ENABLE:
-                h3800_video_lcd_enable(setp);
-                break;
-        case IPAQ_EGPIO_CODEC_NRESET:
-        case IPAQ_EGPIO_AUDIO_ON:
-        case IPAQ_EGPIO_QMUTE:
-                printk("%s: error - should not be called\n", __func__);
-                break;
-        case IPAQ_EGPIO_OPT_NVRAM_ON:
-                SET_ASIC2(GPIO2_OPT_ON_NVRAM);
-                break;
-        case IPAQ_EGPIO_OPT_ON:
-                SET_ASIC2(GPIO2_OPT_ON);
-                break;
-        case IPAQ_EGPIO_CARD_RESET:
-                SET_ASIC2(GPIO2_OPT_PCM_RESET);
-                break;
-        case IPAQ_EGPIO_OPT_RESET:
-                SET_ASIC2(GPIO2_OPT_RESET);
-                break;
-        case IPAQ_EGPIO_IR_ON:
-                CLEAR_ASIC1(GPIO1_IR_ON_N);
-                break;
-        case IPAQ_EGPIO_IR_FSEL:
-                break;
-        case IPAQ_EGPIO_RS232_ON:
-                SET_ASIC1(GPIO1_RS232_ON);
-                break;
-        case IPAQ_EGPIO_VPP_ON:
-                H3800_ASIC2_FlashWP_VPP_ON = setp;
-                break;
-        }
-}
-
-static unsigned long h3800_read_egpio(void)
-{
-        return H3800_ASIC1_GPIO_OUT | (H3800_ASIC2_GPIOPIOD << 16);
-}
-
-/* We need to fix ASIC2 GPIO over suspend/resume.  At the moment,
-   it doesn't appear that ASIC1 GPIO has the same problem */
-
-static int h3800_pm_callback(int req)
-{
-        static u16 asic1_data;
-        static u16 asic2_data;
-        int result = 0;
-
-        printk("%s %d\n", __func__, req);
-
-        switch (req) {
-        case PM_RESUME:
-                MSC2 = (MSC2 & 0x0000ffff) | 0xE4510000;  /* Set MSC2 correctly */
-
-                H3800_ASIC2_GPIOPIOD = asic2_data;
-                H3800_ASIC2_GPIODIR = GPIO2_PEN_IRQ
-                        | GPIO2_SD_DETECT
-                        | GPIO2_EAR_IN_N
-                        | GPIO2_USB_DETECT_N
-                        | GPIO2_SD_CON_SLT;
-
-                H3800_ASIC1_GPIO_OUT = asic1_data;
-
-                if (ipaq_model_ops.pm_callback_aux)
-                        result = ipaq_model_ops.pm_callback_aux(req);
-                break;
-
-        case PM_SUSPEND:
-                if (ipaq_model_ops.pm_callback_aux &&
-                     ((result = ipaq_model_ops.pm_callback_aux(req)) != 0))
-                        return result;
-
-                asic1_data = H3800_ASIC1_GPIO_OUT;
-                asic2_data = H3800_ASIC2_GPIOPIOD;
-                break;
-        default:
-                printk("%s: unrecognized PM callback\n", __func__);
-                break;
-        }
-        return result;
-}
-
-static struct ipaq_model_ops h3800_model_ops __initdata = {
-        .generic_name   = "3800",
-        .control        = h3800_control_egpio,
-        .read           = h3800_read_egpio,
-        .pm_callback    = h3800_pm_callback
-};
-
-#define MAX_ASIC_ISR_LOOPS    20
-
-/* The order of these is important - see #include <mach/irqs.h> */
-static u32 kpio_irq_mask[] = {
-        KPIO_KEY_ALL,
-        KPIO_SPI_INT,
-        KPIO_OWM_INT,
-        KPIO_ADC_INT,
-        KPIO_UART_0_INT,
-        KPIO_UART_1_INT,
-        KPIO_TIMER_0_INT,
-        KPIO_TIMER_1_INT,
-        KPIO_TIMER_2_INT
-};
-
-static u32 gpio_irq_mask[] = {
-        GPIO2_PEN_IRQ,
-        GPIO2_SD_DETECT,
-        GPIO2_EAR_IN_N,
-        GPIO2_USB_DETECT_N,
-        GPIO2_SD_CON_SLT,
-};
-
-static void h3800_IRQ_demux(unsigned int irq, struct irq_desc *desc)
-{
-        int i;
-
-        if (0) printk("%s: interrupt received\n", __func__);
-
-        desc->chip->ack(irq);
-
-        for (i = 0; i < MAX_ASIC_ISR_LOOPS && (GPLR & GPIO_H3800_ASIC); i++) {
-                u32 irq;
-                int j;
-
-                /* KPIO */
-                irq = H3800_ASIC2_KPIINTFLAG;
-                if (0) printk("%s KPIO 0x%08X\n", __func__, irq);
-                for (j = 0; j < H3800_KPIO_IRQ_COUNT; j++)
-                        if (irq & kpio_irq_mask[j])
-                                handle_edge_irq(H3800_KPIO_IRQ_COUNT + j, irq_desc + H3800_KPIO_IRQ_COUNT + j);
-
-                /* GPIO2 */
-                irq = H3800_ASIC2_GPIINTFLAG;
-                if (0) printk("%s GPIO 0x%08X\n", __func__, irq);
-                for (j = 0; j < H3800_GPIO_IRQ_COUNT; j++)
-                        if (irq & gpio_irq_mask[j])
-                                handle_edge_irq(H3800_GPIO_IRQ_COUNT + j, irq_desc + H3800_GPIO_IRQ_COUNT + j);
-        }
-
-        if (i >= MAX_ASIC_ISR_LOOPS)
-                printk("%s: interrupt processing overrun\n", __func__);
-
-        /* For level-based interrupts */
-        desc->chip->unmask(irq);
-
-}
-
-static struct irqaction h3800_irq = {
-        .name           = "h3800_asic",
-        .handler        = h3800_IRQ_demux,
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-};
-
-u32 kpio_int_shadow = 0;
-
-
-/* mask_ack <- IRQ is first serviced.
-       mask <- IRQ is disabled.
-     unmask <- IRQ is enabled
-
-     The INTCLR registers are poorly documented.  I believe that writing
-     a "1" to the register clears the specific interrupt, but the documentation
-     indicates writing a "0" clears the interrupt.  In any case, they shouldn't
-     be read (that's the INTFLAG register)
- */
-
-static void h3800_mask_ack_kpio_irq(unsigned int irq)
-{
-        u32 mask = kpio_irq_mask[irq - H3800_KPIO_IRQ_START];
-        kpio_int_shadow &= ~mask;
-        H3800_ASIC2_KPIINTSTAT = kpio_int_shadow;
-        H3800_ASIC2_KPIINTCLR  = mask;
-}
-
-static void h3800_mask_kpio_irq(unsigned int irq)
-{
-        u32 mask = kpio_irq_mask[irq - H3800_KPIO_IRQ_START];
-        kpio_int_shadow &= ~mask;
-        H3800_ASIC2_KPIINTSTAT = kpio_int_shadow;
-}
-
-static void h3800_unmask_kpio_irq(unsigned int irq)
-{
-        u32 mask = kpio_irq_mask[irq - H3800_KPIO_IRQ_START];
-        kpio_int_shadow |= mask;
-        H3800_ASIC2_KPIINTSTAT = kpio_int_shadow;
-}
-
-static void h3800_mask_ack_gpio_irq(unsigned int irq)
-{
-        u32 mask = gpio_irq_mask[irq - H3800_GPIO_IRQ_START];
-        H3800_ASIC2_GPIINTSTAT &= ~mask;
-        H3800_ASIC2_GPIINTCLR   = mask;
-}
-
-static void h3800_mask_gpio_irq(unsigned int irq)
-{
-        u32 mask = gpio_irq_mask[irq - H3800_GPIO_IRQ_START];
-        H3800_ASIC2_GPIINTSTAT &= ~mask;
-        }
-
-static void h3800_unmask_gpio_irq(unsigned int irq)
-{
-        u32 mask = gpio_irq_mask[irq - H3800_GPIO_IRQ_START];
-        H3800_ASIC2_GPIINTSTAT |= mask;
-}
-
-static void __init h3800_init_irq(void)
-{
-        int i;
-
-        /* Initialize standard IRQs */
-        sa1100_init_irq();
-
-        /* Disable all IRQs and set up clock */
-        H3800_ASIC2_KPIINTSTAT     =  0;     /* Disable all interrupts */
-        H3800_ASIC2_GPIINTSTAT     =  0;
-
-        H3800_ASIC2_KPIINTCLR      =  0;     /* Clear all KPIO interrupts */
-        H3800_ASIC2_GPIINTCLR      =  0;     /* Clear all GPIO interrupts */
-
-//      H3800_ASIC2_KPIINTCLR      =  0xffff;     /* Clear all KPIO interrupts */
-//      H3800_ASIC2_GPIINTCLR      =  0xffff;     /* Clear all GPIO interrupts */
-
-        H3800_ASIC2_CLOCK_Enable       |= ASIC2_CLOCK_EX0;   /* 32 kHZ crystal on */
-        H3800_ASIC2_INTR_ClockPrescale |= ASIC2_INTCPS_SET;
-        H3800_ASIC2_INTR_ClockPrescale  = ASIC2_INTCPS_CPS(0x0e) | ASIC2_INTCPS_SET;
-        H3800_ASIC2_INTR_TimerSet       = 1;
-
-#if 0
-        for (i = 0; i < H3800_KPIO_IRQ_COUNT; i++) {
-                int irq = i + H3800_KPIO_IRQ_START;
-                irq_desc[irq].valid    = 1;
-                irq_desc[irq].probe_ok = 1;
-                set_irq_chip(irq, &h3800_kpio_irqchip);
-        }
-
-        for (i = 0; i < H3800_GPIO_IRQ_COUNT; i++) {
-                int irq = i + H3800_GPIO_IRQ_START;
-                irq_desc[irq].valid    = 1;
-                irq_desc[irq].probe_ok = 1;
-                set_irq_chip(irq, &h3800_gpio_irqchip);
-        }
-#endif
-        set_irq_type(IRQ_GPIO_H3800_ASIC, IRQ_TYPE_EDGE_RISING);
-        set_irq_chained_handler(IRQ_GPIO_H3800_ASIC, h3800_IRQ_demux);
-}
-
-
-#define ASIC1_OUTPUTS    0x7fff   /* First 15 bits are used */
-
-static void __init h3800_map_io(void)
-{
-        h3xxx_map_io();
-
-        /* Add wakeup on AC plug/unplug */
-        PWER  |= PWER_GPIO12;
-
-        /* Initialize h3800-specific values here */
-        GPCR = 0x0fffffff;       /* All outputs are set low by default */
-        GAFR =  GPIO_H3800_CLK_OUT |
-                GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12 |
-                GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9  | GPIO_LDD8;
-        GPDR =  GPIO_H3800_CLK_OUT |
-                GPIO_H3600_COM_RTS  | GPIO_H3600_L3_CLOCK |
-                GPIO_H3600_L3_MODE  | GPIO_H3600_L3_DATA  |
-                GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12 |
-                GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9  | GPIO_LDD8;
-        TUCR =  TUCR_3_6864MHz;   /* Seems to be used only for the Bluetooth UART */
-
-        /* Fix the memory bus */
-        MSC2 = (MSC2 & 0x0000ffff) | 0xE4510000;
-
-        /* Set up ASIC #1 */
-        H3800_ASIC1_GPIO_DIR            = ASIC1_OUTPUTS;            /* All outputs */
-        H3800_ASIC1_GPIO_MASK           = ASIC1_OUTPUTS;            /* No interrupts */
-        H3800_ASIC1_GPIO_SLEEP_MASK     = ASIC1_OUTPUTS;
-        H3800_ASIC1_GPIO_SLEEP_DIR      = ASIC1_OUTPUTS;
-        H3800_ASIC1_GPIO_SLEEP_OUT      = GPIO1_EAR_ON_N;
-        H3800_ASIC1_GPIO_BATT_FAULT_DIR = ASIC1_OUTPUTS;
-        H3800_ASIC1_GPIO_BATT_FAULT_OUT = GPIO1_EAR_ON_N;
-
-        H3800_ASIC1_GPIO_OUT = GPIO1_IR_ON_N
-                                      | GPIO1_RS232_ON
-                                      | GPIO1_EAR_ON_N;
-
-        /* Set up ASIC #2 */
-        H3800_ASIC2_GPIOPIOD    = GPIO2_IN_Y1_N | GPIO2_IN_X1_N;
-        H3800_ASIC2_GPOBFSTAT   = GPIO2_IN_Y1_N | GPIO2_IN_X1_N;
-
-        H3800_ASIC2_GPIODIR     = GPIO2_PEN_IRQ
-                                      | GPIO2_SD_DETECT
-                                      | GPIO2_EAR_IN_N
-                                      | GPIO2_USB_DETECT_N
-                                      | GPIO2_SD_CON_SLT;
-
-        /* TODO : Set sleep states & battery fault states */
-
-        /* Clear VPP Enable */
-        H3800_ASIC2_FlashWP_VPP_ON = 0;
-        ipaq_model_ops = h3800_model_ops;
-}
-
-MACHINE_START(H3800, "Compaq iPAQ H3800")
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
-        .boot_params    = 0xc0000100,
-        .map_io         = h3800_map_io,
-        .init_irq       = h3800_init_irq,
-        .timer          = &sa1100_timer,
-        .init_machine   = h3xxx_mach_init,
-MACHINE_END
-
-#endif /* CONFIG_SA1100_H3800 */
diff --git a/arch/arm/mach-sa1100/include/mach/collie.h b/arch/arm/mach-sa1100/include/mach/collie.h
index 69e962416e3f..9efb569cdb60 100644
--- a/arch/arm/mach-sa1100/include/mach/collie.h
+++ b/arch/arm/mach-sa1100/include/mach/collie.h
@@ -14,21 +14,21 @@
 #define __ASM_ARCH_COLLIE_H
 
 
-#define COLLIE_SCP_CHARGE_ON    SCOOP_GPCR_PA11
+#define COLLIE_SCOOP_GPIO_BASE  (GPIO_MAX + 1)
+#define COLLIE_GPIO_CHARGE_ON   (COLLIE_SCOOP_GPIO_BASE + 0)
 #define COLLIE_SCP_DIAG_BOOT1   SCOOP_GPCR_PA12
 #define COLLIE_SCP_DIAG_BOOT2   SCOOP_GPCR_PA13
 #define COLLIE_SCP_MUTE_L       SCOOP_GPCR_PA14
 #define COLLIE_SCP_MUTE_R       SCOOP_GPCR_PA15
 #define COLLIE_SCP_5VON         SCOOP_GPCR_PA16
 #define COLLIE_SCP_AMP_ON       SCOOP_GPCR_PA17
-#define COLLIE_SCP_VPEN         SCOOP_GPCR_PA18
+#define COLLIE_GPIO_VPEN        (COLLIE_SCOOP_GPIO_BASE + 7)
 #define COLLIE_SCP_LB_VOL_CHG   SCOOP_GPCR_PA19
 
-#define COLLIE_SCOOP_IO_DIR     ( COLLIE_SCP_CHARGE_ON | COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \
-                                COLLIE_SCP_5VON | COLLIE_SCP_AMP_ON | COLLIE_SCP_VPEN | \
+#define COLLIE_SCOOP_IO_DIR     ( COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \
+                                COLLIE_SCP_5VON | COLLIE_SCP_AMP_ON | \
                                 COLLIE_SCP_LB_VOL_CHG )
-#define COLLIE_SCOOP_IO_OUT     ( COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | COLLIE_SCP_VPEN | \
-                                COLLIE_SCP_CHARGE_ON )
+#define COLLIE_SCOOP_IO_OUT     ( COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R )
 
 /* GPIOs for which the generic definition doesn't say much */
 
diff --git a/arch/arm/mach-sa1100/include/mach/h3600.h b/arch/arm/mach-sa1100/include/mach/h3600.h
index 9cc47fddb335..2827faa47421 100644
--- a/arch/arm/mach-sa1100/include/mach/h3600.h
+++ b/arch/arm/mach-sa1100/include/mach/h3600.h
@@ -29,7 +29,7 @@ typedef int __bitwise pm_request_t;
 #define PM_RESUME       ((__force pm_request_t) 2)      /* enter D0 */
 
 /* generalized support for H3xxx series Compaq Pocket PC's */
-#define machine_is_h3xxx() (machine_is_h3100() || machine_is_h3600() || machine_is_h3800())
+#define machine_is_h3xxx() (machine_is_h3100() || machine_is_h3600())
 
 /* Physical memory regions corresponding to chip selects */
 #define H3600_EGPIO_PHYS        (SA1100_CS5_PHYS + 0x01000000)
@@ -93,76 +93,7 @@ enum ipaq_egpio_type {
         IPAQ_EGPIO_LCD_ENABLE,    /* Enable/disable LCD controller */
 };
 
-struct ipaq_model_ops {
-        const char     *generic_name;
-        void          (*control)(enum ipaq_egpio_type, int);
-        unsigned long (*read)(void);
-        void          (*blank_callback)(int blank);
-        int           (*pm_callback)(int req);      /* Primary model callback */
-        int           (*pm_callback_aux)(int req);  /* Secondary callback (used by HAL modules) */
-};
-
-extern struct ipaq_model_ops ipaq_model_ops;
-
-static __inline__ const char * h3600_generic_name(void)
-{
-        return ipaq_model_ops.generic_name;
-}
-
-static __inline__ void assign_h3600_egpio(enum ipaq_egpio_type x, int level)
-{
-        if (ipaq_model_ops.control)
-                ipaq_model_ops.control(x,level);
-}
-
-static __inline__ void clr_h3600_egpio(enum ipaq_egpio_type x)
-{
-        if (ipaq_model_ops.control)
-                ipaq_model_ops.control(x,0);
-}
-
-static __inline__ void set_h3600_egpio(enum ipaq_egpio_type x)
-{
-        if (ipaq_model_ops.control)
-                ipaq_model_ops.control(x,1);
-}
-
-static __inline__ unsigned long read_h3600_egpio(void)
-{
-        if (ipaq_model_ops.read)
-                return ipaq_model_ops.read();
-        return 0;
-}
-
-static __inline__ int  h3600_register_blank_callback(void (*f)(int))
-{
-        ipaq_model_ops.blank_callback = f;
-        return 0;
-}
-
-static __inline__ void h3600_unregister_blank_callback(void (*f)(int))
-{
-        ipaq_model_ops.blank_callback = NULL;
-}
-
-
-static __inline__ int  h3600_register_pm_callback(int (*f)(int))
-{
-        ipaq_model_ops.pm_callback_aux = f;
-        return 0;
-}
-
-static __inline__ void h3600_unregister_pm_callback(int (*f)(int))
-{
-        ipaq_model_ops.pm_callback_aux = NULL;
-}
-
-static __inline__ int h3600_power_management(int req)
-{
-        if (ipaq_model_ops.pm_callback)
-                return ipaq_model_ops.pm_callback(req);
-        return 0;
-}
+extern void (*assign_h3600_egpio)(enum ipaq_egpio_type x, int level);
 
 #endif /* ASSEMBLY */
 
diff --git a/arch/arm/mach-sa1100/include/mach/h3600_gpio.h b/arch/arm/mach-sa1100/include/mach/h3600_gpio.h
index 62b0b7879685..a36ca76d018b 100644
--- a/arch/arm/mach-sa1100/include/mach/h3600_gpio.h
+++ b/arch/arm/mach-sa1100/include/mach/h3600_gpio.h
@@ -48,22 +48,11 @@
 #define GPIO_H3600_OPT_LOCK             GPIO_GPIO (22)
 #define GPIO_H3600_OPT_DET              GPIO_GPIO (27)
 
-/* H3800 specific pins */
-#define GPIO_H3800_AC_IN                GPIO_GPIO (12)
-#define GPIO_H3800_COM_DSR              GPIO_GPIO (13)
-#define GPIO_H3800_MMC_INT              GPIO_GPIO (18)
-#define GPIO_H3800_NOPT_IND             GPIO_GPIO (20)   /* Almost exactly the same as GPIO_H3600_OPT_DET */
-#define GPIO_H3800_OPT_BAT_FAULT        GPIO_GPIO (22)
-#define GPIO_H3800_CLK_OUT              GPIO_GPIO (27)
-
 /****************************************************/
 
 #define IRQ_GPIO_H3600_ACTION_BUTTON    IRQ_GPIO18
 #define IRQ_GPIO_H3600_OPT_DET          IRQ_GPIO27
 
-#define IRQ_GPIO_H3800_MMC_INT          IRQ_GPIO18
-#define IRQ_GPIO_H3800_NOPT_IND         IRQ_GPIO20 /* almost same as OPT_DET */
-
 /* H3100 / 3600 EGPIO pins */
 #define EGPIO_H3600_VPP_ON              (1 << 0)
 #define EGPIO_H3600_CARD_RESET          (1 << 1)   /* reset the attached pcmcia/compactflash card.  active high. */
@@ -84,457 +73,5 @@
 #define EGPIO_H3600_LCD_5V_ON           (1 << 14)  /* enable 5V to LCD. active high. */
 #define EGPIO_H3600_LVDD_ON             (1 << 15)  /* enable 9V and -6.5V to LCD. */
 
-/********************* H3800, ASIC #2 ********************/
-
-#define _H3800_ASIC2_Base            (H3600_EGPIO_VIRT)
-#define H3800_ASIC2_OFFSET(s,x,y)    \
-    (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _Base + _H3800_ASIC2_ ## x ## _ ## y)))
-#define H3800_ASIC2_NOFFSET(s,x,n,y) \
-    (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _ ## n ## _Base + _H3800_ASIC2_ ## x ## _ ## y)))
-
-#define _H3800_ASIC2_GPIO_Base                 0x0000
-#define _H3800_ASIC2_GPIO_Direction            0x0000    /* R/W, 16 bits 1:input, 0:output */
-#define _H3800_ASIC2_GPIO_InterruptType        0x0004    /* R/W, 12 bits 1:edge, 0:level          */
-#define _H3800_ASIC2_GPIO_InterruptEdgeType    0x0008    /* R/W, 12 bits 1:rising, 0:falling */
-#define _H3800_ASIC2_GPIO_InterruptLevelType   0x000C    /* R/W, 12 bits 1:high, 0:low  */
-#define _H3800_ASIC2_GPIO_InterruptClear       0x0010    /* W,   12 bits */
-#define _H3800_ASIC2_GPIO_InterruptFlag        0x0010    /* R,   12 bits - reads int status */
-#define _H3800_ASIC2_GPIO_Data                 0x0014    /* R/W, 16 bits */
-#define _H3800_ASIC2_GPIO_BattFaultOut         0x0018    /* R/W, 16 bit - sets level on batt fault */
-#define _H3800_ASIC2_GPIO_InterruptEnable      0x001c    /* R/W, 12 bits 1:enable interrupt */
-#define _H3800_ASIC2_GPIO_Alternate            0x003c    /* R/W, 12+1 bits - set alternate functions */
-
-#define H3800_ASIC2_GPIO_Direction          H3800_ASIC2_OFFSET( u16, GPIO, Direction )
-#define H3800_ASIC2_GPIO_InterruptType      H3800_ASIC2_OFFSET( u16, GPIO, InterruptType )
-#define H3800_ASIC2_GPIO_InterruptEdgeType  H3800_ASIC2_OFFSET( u16, GPIO, InterruptEdgeType )
-#define H3800_ASIC2_GPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, GPIO, InterruptLevelType )
-#define H3800_ASIC2_GPIO_InterruptClear     H3800_ASIC2_OFFSET( u16, GPIO, InterruptClear )
-#define H3800_ASIC2_GPIO_InterruptFlag      H3800_ASIC2_OFFSET( u16, GPIO, InterruptFlag )
-#define H3800_ASIC2_GPIO_Data               H3800_ASIC2_OFFSET( u16, GPIO, Data )
-#define H3800_ASIC2_GPIO_BattFaultOut       H3800_ASIC2_OFFSET( u16, GPIO, BattFaultOut )
-#define H3800_ASIC2_GPIO_InterruptEnable    H3800_ASIC2_OFFSET( u16, GPIO, InterruptEnable )
-#define H3800_ASIC2_GPIO_Alternate          H3800_ASIC2_OFFSET( u16, GPIO, Alternate )
-
-#define GPIO_H3800_ASIC2_IN_Y1_N          (1 << 0)   /* Output: Touchscreen Y1 */
-#define GPIO_H3800_ASIC2_IN_X0            (1 << 1)   /* Output: Touchscreen X0 */
-#define GPIO_H3800_ASIC2_IN_Y0            (1 << 2)   /* Output: Touchscreen Y0 */
-#define GPIO_H3800_ASIC2_IN_X1_N          (1 << 3)   /* Output: Touchscreen X1 */
-#define GPIO_H3800_ASIC2_BT_RST           (1 << 4)   /* Output: Bluetooth reset */
-#define GPIO_H3800_ASIC2_PEN_IRQ          (1 << 5)   /* Input : Pen down        */
-#define GPIO_H3800_ASIC2_SD_DETECT        (1 << 6)   /* Input : SD detect */
-#define GPIO_H3800_ASIC2_EAR_IN_N         (1 << 7)   /* Input : Audio jack plug inserted */
-#define GPIO_H3800_ASIC2_OPT_PCM_RESET    (1 << 8)   /* Output: */
-#define GPIO_H3800_ASIC2_OPT_RESET        (1 << 9)   /* Output: */
-#define GPIO_H3800_ASIC2_USB_DETECT_N     (1 << 10)  /* Input : */
-#define GPIO_H3800_ASIC2_SD_CON_SLT       (1 << 11)  /* Input : */
-
-#define _H3800_ASIC2_KPIO_Base                 0x0200
-#define _H3800_ASIC2_KPIO_Direction            0x0000    /* R/W, 12 bits 1:input, 0:output */
-#define _H3800_ASIC2_KPIO_InterruptType        0x0004    /* R/W, 12 bits 1:edge, 0:level          */
-#define _H3800_ASIC2_KPIO_InterruptEdgeType    0x0008    /* R/W, 12 bits 1:rising, 0:falling */
-#define _H3800_ASIC2_KPIO_InterruptLevelType   0x000C    /* R/W, 12 bits 1:high, 0:low  */
-#define _H3800_ASIC2_KPIO_InterruptClear       0x0010    /* W,   20 bits - 8 special */
-#define _H3800_ASIC2_KPIO_InterruptFlag        0x0010    /* R,   20 bits - 8 special - reads int status */
-#define _H3800_ASIC2_KPIO_Data                 0x0014    /* R/W, 16 bits */
-#define _H3800_ASIC2_KPIO_BattFaultOut         0x0018    /* R/W, 16 bit - sets level on batt fault */
-#define _H3800_ASIC2_KPIO_InterruptEnable      0x001c    /* R/W, 20 bits - 8 special */
-#define _H3800_ASIC2_KPIO_Alternate            0x003c    /* R/W, 6 bits */
-
-#define H3800_ASIC2_KPIO_Direction          H3800_ASIC2_OFFSET( u16, KPIO, Direction )
-#define H3800_ASIC2_KPIO_InterruptType      H3800_ASIC2_OFFSET( u16, KPIO, InterruptType )
-#define H3800_ASIC2_KPIO_InterruptEdgeType  H3800_ASIC2_OFFSET( u16, KPIO, InterruptEdgeType )
-#define H3800_ASIC2_KPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, KPIO, InterruptLevelType )
-#define H3800_ASIC2_KPIO_InterruptClear     H3800_ASIC2_OFFSET( u32, KPIO, InterruptClear )
-#define H3800_ASIC2_KPIO_InterruptFlag      H3800_ASIC2_OFFSET( u32, KPIO, InterruptFlag )
-#define H3800_ASIC2_KPIO_Data               H3800_ASIC2_OFFSET( u16, KPIO, Data )
-#define H3800_ASIC2_KPIO_BattFaultOut       H3800_ASIC2_OFFSET( u16, KPIO, BattFaultOut )
-#define H3800_ASIC2_KPIO_InterruptEnable    H3800_ASIC2_OFFSET( u32, KPIO, InterruptEnable )
-#define H3800_ASIC2_KPIO_Alternate          H3800_ASIC2_OFFSET( u16, KPIO, Alternate )
-
-#define H3800_ASIC2_KPIO_SPI_INT        ( 1 << 16 )
-#define H3800_ASIC2_KPIO_OWM_INT        ( 1 << 17 )
-#define H3800_ASIC2_KPIO_ADC_INT        ( 1 << 18 )
-#define H3800_ASIC2_KPIO_UART_0_INT     ( 1 << 19 )
-#define H3800_ASIC2_KPIO_UART_1_INT     ( 1 << 20 )
-#define H3800_ASIC2_KPIO_TIMER_0_INT    ( 1 << 21 )
-#define H3800_ASIC2_KPIO_TIMER_1_INT    ( 1 << 22 )
-#define H3800_ASIC2_KPIO_TIMER_2_INT    ( 1 << 23 )
-
-#define KPIO_H3800_ASIC2_RECORD_BTN_N     (1 << 0)   /* Record button */
-#define KPIO_H3800_ASIC2_KEY_5W1_N        (1 << 1)   /* Keypad */
-#define KPIO_H3800_ASIC2_KEY_5W2_N        (1 << 2)   /* */
-#define KPIO_H3800_ASIC2_KEY_5W3_N        (1 << 3)   /* */
-#define KPIO_H3800_ASIC2_KEY_5W4_N        (1 << 4)   /* */
-#define KPIO_H3800_ASIC2_KEY_5W5_N        (1 << 5)   /* */
-#define KPIO_H3800_ASIC2_KEY_LEFT_N       (1 << 6)   /* */
-#define KPIO_H3800_ASIC2_KEY_RIGHT_N      (1 << 7)   /* */
-#define KPIO_H3800_ASIC2_KEY_AP1_N        (1 << 8)   /* Old "Calendar" */
-#define KPIO_H3800_ASIC2_KEY_AP2_N        (1 << 9)   /* Old "Schedule" */
-#define KPIO_H3800_ASIC2_KEY_AP3_N        (1 << 10)  /* Old "Q"        */
-#define KPIO_H3800_ASIC2_KEY_AP4_N        (1 << 11)  /* Old "Undo"     */
-
-/* Alternate KPIO functions (set by default) */
-#define KPIO_ALT_H3800_ASIC2_KEY_5W1_N        (1 << 1)   /* Action key */
-#define KPIO_ALT_H3800_ASIC2_KEY_5W2_N        (1 << 2)   /* J1 of keypad input */
-#define KPIO_ALT_H3800_ASIC2_KEY_5W3_N        (1 << 3)   /* J2 of keypad input */
-#define KPIO_ALT_H3800_ASIC2_KEY_5W4_N        (1 << 4)   /* J3 of keypad input */
-#define KPIO_ALT_H3800_ASIC2_KEY_5W5_N        (1 << 5)   /* J4 of keypad input */
-
-#define _H3800_ASIC2_SPI_Base                  0x0400
-#define _H3800_ASIC2_SPI_Control               0x0000    /* R/W 8 bits */
-#define _H3800_ASIC2_SPI_Data                  0x0004    /* R/W 8 bits */
-#define _H3800_ASIC2_SPI_ChipSelectDisabled    0x0008    /* W   8 bits */
-
-#define H3800_ASIC2_SPI_Control             H3800_ASIC2_OFFSET( u8, SPI, Control )
-#define H3800_ASIC2_SPI_Data                H3800_ASIC2_OFFSET( u8, SPI, Data )
-#define H3800_ASIC2_SPI_ChipSelectDisabled  H3800_ASIC2_OFFSET( u8, SPI, ChipSelectDisabled )
-
-#define _H3800_ASIC2_PWM_0_Base                0x0600
-#define _H3800_ASIC2_PWM_1_Base                0x0700
-#define _H3800_ASIC2_PWM_TimeBase              0x0000    /* R/W 6 bits */
-#define _H3800_ASIC2_PWM_PeriodTime            0x0004    /* R/W 12 bits */
-#define _H3800_ASIC2_PWM_DutyTime              0x0008    /* R/W 12 bits */
-
-#define H3800_ASIC2_PWM_0_TimeBase          H3800_ASIC2_NOFFSET(  u8, PWM, 0, TimeBase )
-#define H3800_ASIC2_PWM_0_PeriodTime        H3800_ASIC2_NOFFSET( u16, PWM, 0, PeriodTime )
-#define H3800_ASIC2_PWM_0_DutyTime          H3800_ASIC2_NOFFSET( u16, PWM, 0, DutyTime )
-
-#define H3800_ASIC2_PWM_1_TimeBase          H3800_ASIC2_NOFFSET(  u8, PWM, 1, TimeBase )
-#define H3800_ASIC2_PWM_1_PeriodTime        H3800_ASIC2_NOFFSET( u16, PWM, 1, PeriodTime )
-#define H3800_ASIC2_PWM_1_DutyTime          H3800_ASIC2_NOFFSET( u16, PWM, 1, DutyTime )
-
-#define H3800_ASIC2_PWM_TIMEBASE_MASK             0xf    /* Low 4 bits sets time base, max = 8 */
-#define H3800_ASIC2_PWM_TIMEBASE_ENABLE    ( 1 << 4 )    /* Enable clock */
-#define H3800_ASIC2_PWM_TIMEBASE_CLEAR     ( 1 << 5 )    /* Clear the PWM */
-
-#define _H3800_ASIC2_LED_0_Base                0x0800
-#define _H3800_ASIC2_LED_1_Base                0x0880
-#define _H3800_ASIC2_LED_2_Base                0x0900
-#define _H3800_ASIC2_LED_TimeBase              0x0000    /* R/W  7 bits */
-#define _H3800_ASIC2_LED_PeriodTime            0x0004    /* R/W 12 bits */
-#define _H3800_ASIC2_LED_DutyTime              0x0008    /* R/W 12 bits */
-#define _H3800_ASIC2_LED_AutoStopCount         0x000c    /* R/W 16 bits */
-
-#define H3800_ASIC2_LED_0_TimeBase          H3800_ASIC2_NOFFSET(  u8, LED, 0, TimeBase )
-#define H3800_ASIC2_LED_0_PeriodTime        H3800_ASIC2_NOFFSET( u16, LED, 0, PeriodTime )
-#define H3800_ASIC2_LED_0_DutyTime          H3800_ASIC2_NOFFSET( u16, LED, 0, DutyTime )
-#define H3800_ASIC2_LED_0_AutoStopClock     H3800_ASIC2_NOFFSET( u16, LED, 0, AutoStopClock )
-
-#define H3800_ASIC2_LED_1_TimeBase          H3800_ASIC2_NOFFSET(  u8, LED, 1, TimeBase )
-#define H3800_ASIC2_LED_1_PeriodTime        H3800_ASIC2_NOFFSET( u16, LED, 1, PeriodTime )
-#define H3800_ASIC2_LED_1_DutyTime          H3800_ASIC2_NOFFSET( u16, LED, 1, DutyTime )
-#define H3800_ASIC2_LED_1_AutoStopClock     H3800_ASIC2_NOFFSET( u16, LED, 1, AutoStopClock )
-
-#define H3800_ASIC2_LED_2_TimeBase          H3800_ASIC2_NOFFSET(  u8, LED, 2, TimeBase )
-#define H3800_ASIC2_LED_2_PeriodTime        H3800_ASIC2_NOFFSET( u16, LED, 2, PeriodTime )
-#define H3800_ASIC2_LED_2_DutyTime          H3800_ASIC2_NOFFSET( u16, LED, 2, DutyTime )
-#define H3800_ASIC2_LED_2_AutoStopClock     H3800_ASIC2_NOFFSET( u16, LED, 2, AutoStopClock )
-
-#define H3800_ASIC2_LED_TIMEBASE_MASK            0x0f    /* Low 4 bits sets time base, max = 13 */
-#define H3800_ASIC2_LED_TIMEBASE_BLINK     ( 1 << 4 )    /* Enable blinking */
-#define H3800_ASIC2_LED_TIMEBASE_AUTOSTOP  ( 1 << 5 )
-#define H3800_ASIC2_LED_TIMEBASE_ALWAYS    ( 1 << 6 )    /* Enable blink always */
-
-#define _H3800_ASIC2_UART_0_Base               0x0A00
-#define _H3800_ASIC2_UART_1_Base               0x0C00
-#define _H3800_ASIC2_UART_Receive              0x0000    /* R    8 bits */
-#define _H3800_ASIC2_UART_Transmit             0x0000    /*   W  8 bits */
-#define _H3800_ASIC2_UART_IntEnable            0x0004    /* R/W  8 bits */
-#define _H3800_ASIC2_UART_IntVerify            0x0008    /* R/W  8 bits */
-#define _H3800_ASIC2_UART_FIFOControl          0x000c    /* R/W  8 bits */
-#define _H3800_ASIC2_UART_LineControl          0x0010    /* R/W  8 bits */
-#define _H3800_ASIC2_UART_ModemStatus          0x0014    /* R/W  8 bits */
-#define _H3800_ASIC2_UART_LineStatus           0x0018    /* R/W  8 bits */
-#define _H3800_ASIC2_UART_ScratchPad           0x001c    /* R/W  8 bits */
-#define _H3800_ASIC2_UART_DivisorLatchL        0x0020    /* R/W  8 bits */
-#define _H3800_ASIC2_UART_DivisorLatchH        0x0024    /* R/W  8 bits */
-
-#define H3800_ASIC2_UART_0_Receive          H3800_ASIC2_NOFFSET(  u8, UART, 0, Receive )
-#define H3800_ASIC2_UART_0_Transmit         H3800_ASIC2_NOFFSET(  u8, UART, 0, Transmit )
-#define H3800_ASIC2_UART_0_IntEnable        H3800_ASIC2_NOFFSET(  u8, UART, 0, IntEnable )
-#define H3800_ASIC2_UART_0_IntVerify        H3800_ASIC2_NOFFSET(  u8, UART, 0, IntVerify )
-#define H3800_ASIC2_UART_0_FIFOControl      H3800_ASIC2_NOFFSET(  u8, UART, 0, FIFOControl )
-#define H3800_ASIC2_UART_0_LineControl      H3800_ASIC2_NOFFSET(  u8, UART, 0, LineControl )
-#define H3800_ASIC2_UART_0_ModemStatus      H3800_ASIC2_NOFFSET(  u8, UART, 0, ModemStatus )
-#define H3800_ASIC2_UART_0_LineStatus       H3800_ASIC2_NOFFSET(  u8, UART, 0, LineStatus )
-#define H3800_ASIC2_UART_0_ScratchPad       H3800_ASIC2_NOFFSET(  u8, UART, 0, ScratchPad )
-#define H3800_ASIC2_UART_0_DivisorLatchL    H3800_ASIC2_NOFFSET(  u8, UART, 0, DivisorLatchL )
-#define H3800_ASIC2_UART_0_DivisorLatchH    H3800_ASIC2_NOFFSET(  u8, UART, 0, DivisorLatchH )
-
-#define H3800_ASIC2_UART_1_Receive          H3800_ASIC2_NOFFSET(  u8, UART, 1, Receive )
-#define H3800_ASIC2_UART_1_Transmit         H3800_ASIC2_NOFFSET(  u8, UART, 1, Transmit )
-#define H3800_ASIC2_UART_1_IntEnable        H3800_ASIC2_NOFFSET(  u8, UART, 1, IntEnable )
-#define H3800_ASIC2_UART_1_IntVerify        H3800_ASIC2_NOFFSET(  u8, UART, 1, IntVerify )
-#define H3800_ASIC2_UART_1_FIFOControl      H3800_ASIC2_NOFFSET(  u8, UART, 1, FIFOControl )
-#define H3800_ASIC2_UART_1_LineControl      H3800_ASIC2_NOFFSET(  u8, UART, 1, LineControl )
-#define H3800_ASIC2_UART_1_ModemStatus      H3800_ASIC2_NOFFSET(  u8, UART, 1, ModemStatus )
-#define H3800_ASIC2_UART_1_LineStatus       H3800_ASIC2_NOFFSET(  u8, UART, 1, LineStatus )
-#define H3800_ASIC2_UART_1_ScratchPad       H3800_ASIC2_NOFFSET(  u8, UART, 1, ScratchPad )
-#define H3800_ASIC2_UART_1_DivisorLatchL    H3800_ASIC2_NOFFSET(  u8, UART, 1, DivisorLatchL )
-#define H3800_ASIC2_UART_1_DivisorLatchH    H3800_ASIC2_NOFFSET(  u8, UART, 1, DivisorLatchH )
-
-#define _H3800_ASIC2_TIMER_Base                0x0E00
-#define _H3800_ASIC2_TIMER_Command             0x0000    /* R/W  8 bits */
-
-#define H3800_ASIC2_TIMER_Command           H3800_ASIC2_OFFSET( u8, Timer, Command )
-
-#define H3800_ASIC2_TIMER_GAT_0            ( 1 << 0 )    /* Gate enable, counter 0 */
-#define H3800_ASIC2_TIMER_GAT_1            ( 1 << 1 )    /* Gate enable, counter 1 */
-#define H3800_ASIC2_TIMER_GAT_2            ( 1 << 2 )    /* Gate enable, counter 2 */
-#define H3800_ASIC2_TIMER_CLK_0            ( 1 << 3 )    /* Clock enable, counter 0 */
-#define H3800_ASIC2_TIMER_CLK_1            ( 1 << 4 )    /* Clock enable, counter 1 */
-#define H3800_ASIC2_TIMER_CLK_2            ( 1 << 5 )    /* Clock enable, counter 2 */
-#define H3800_ASIC2_TIMER_MODE_0           ( 1 << 6 )    /* Mode 0 enable, counter 0 */
-#define H3800_ASIC2_TIMER_MODE_1           ( 1 << 7 )    /* Mode 0 enable, counter 1 */
-
-#define _H3800_ASIC2_CLOCK_Base                0x1000
-#define _H3800_ASIC2_CLOCK_Enable              0x0000    /* R/W  18 bits */
-
-#define H3800_ASIC2_CLOCK_Enable            H3800_ASIC2_OFFSET( u32, CLOCK, Enable )
-
-#define H3800_ASIC2_CLOCK_AUDIO_1              0x0001    /* Enable 4.1 MHz clock for 8Khz and 4khz sample rate */
-#define H3800_ASIC2_CLOCK_AUDIO_2              0x0002    /* Enable 12.3 MHz clock for 48Khz and 32khz sample rate */
-#define H3800_ASIC2_CLOCK_AUDIO_3              0x0004    /* Enable 5.6 MHz clock for 11 kHZ sample rate */
-#define H3800_ASIC2_CLOCK_AUDIO_4              0x0008    /* Enable 11.289 MHz clock for 44 and 22 kHz sample rate */
-#define H3800_ASIC2_CLOCK_ADC              ( 1 << 4 )    /* 1.024 MHz clock to ADC */
-#define H3800_ASIC2_CLOCK_SPI              ( 1 << 5 )    /* 4.096 MHz clock to SPI */
-#define H3800_ASIC2_CLOCK_OWM              ( 1 << 6 )    /* 4.096 MHz clock to OWM */
-#define H3800_ASIC2_CLOCK_PWM              ( 1 << 7 )    /* 2.048 MHz clock to PWM */
-#define H3800_ASIC2_CLOCK_UART_1           ( 1 << 8 )    /* 24.576 MHz clock to UART1 (turn off bit 16) */
-#define H3800_ASIC2_CLOCK_UART_0           ( 1 << 9 )    /* 24.576 MHz clock to UART0 (turn off bit 17) */
-#define H3800_ASIC2_CLOCK_SD_1             ( 1 << 10 )   /* 16.934 MHz to SD */
-#define H3800_ASIC2_CLOCK_SD_2             ( 2 << 10 )   /* 24.576 MHz to SD */
-#define H3800_ASIC2_CLOCK_SD_3             ( 3 << 10 )   /* 33.869 MHz to SD */
-#define H3800_ASIC2_CLOCK_SD_4             ( 4 << 10 )   /* 49.152 MHz to SD */
-#define H3800_ASIC2_CLOCK_EX0              ( 1 << 13 )   /* Enable 32.768 kHz crystal */
-#define H3800_ASIC2_CLOCK_EX1              ( 1 << 14 )   /* Enable 24.576 MHz crystal */
-#define H3800_ASIC2_CLOCK_EX2              ( 1 << 15 )   /* Enable 33.869 MHz crystal */
-#define H3800_ASIC2_CLOCK_SLOW_UART_1      ( 1 << 16 )   /* Enable 3.686 MHz to UART1 (turn off bit 8) */
-#define H3800_ASIC2_CLOCK_SLOW_UART_0      ( 1 << 17 )   /* Enable 3.686 MHz to UART0 (turn off bit 9) */
-
-#define _H3800_ASIC2_ADC_Base                  0x1200
-#define _H3800_ASIC2_ADC_Multiplexer           0x0000    /* R/W 4 bits - low 3 bits set channel */
-#define _H3800_ASIC2_ADC_ControlStatus         0x0004    /* R/W 8 bits */
-#define _H3800_ASIC2_ADC_Data                  0x0008    /* R   10 bits */
-
-#define H3800_ASIC2_ADC_Multiplexer       H3800_ASIC2_OFFSET(  u8, ADC, Multiplexer )
-#define H3800_ASIC2_ADC_ControlStatus     H3800_ASIC2_OFFSET(  u8, ADC, ControlStatus )
-#define H3800_ASIC2_ADC_Data              H3800_ASIC2_OFFSET( u16, ADC, Data )
-
-#define H3600_ASIC2_ADC_MUX_CHANNEL_MASK         0x07    /* Low 3 bits sets channel.  max = 4 */
-#define H3600_ASIC2_ADC_MUX_CLKEN          ( 1 << 3 )    /* Enable clock */
-
-#define H3600_ASIC2_ADC_CSR_ADPS_MASK            0x0f    /* Low 4 bits sets prescale, max = 8 */
-#define H3600_ASIC2_ADC_CSR_FREE_RUN       ( 1 << 4 )
-#define H3600_ASIC2_ADC_CSR_INT_ENABLE     ( 1 << 5 )
-#define H3600_ASIC2_ADC_CSR_START          ( 1 << 6 )    /* Set to start conversion.  Goes to 0 when done */
-#define H3600_ASIC2_ADC_CSR_ENABLE         ( 1 << 7 )    /* 1:power up ADC, 0:power down */
-
-
-#define _H3800_ASIC2_INTR_Base                 0x1600
-#define _H3800_ASIC2_INTR_MaskAndFlag          0x0000    /* R/(W) 8bits */
-#define _H3800_ASIC2_INTR_ClockPrescale        0x0004    /* R/(W) 5bits */
-#define _H3800_ASIC2_INTR_TimerSet             0x0008    /* R/(W) 8bits */
-
-#define H3800_ASIC2_INTR_MaskAndFlag      H3800_ASIC2_OFFSET( u8, INTR, MaskAndFlag )
-#define H3800_ASIC2_INTR_ClockPrescale    H3800_ASIC2_OFFSET( u8, INTR, ClockPrescale )
-#define H3800_ASIC2_INTR_TimerSet         H3800_ASIC2_OFFSET( u8, INTR, TimerSet )
-
-#define H3800_ASIC2_INTR_GLOBAL_MASK       ( 1 << 0 )    /* Global interrupt mask */
-#define H3800_ASIC2_INTR_POWER_ON_RESET    ( 1 << 1 )    /* 01: Power on reset (bits 1 & 2 ) */
-#define H3800_ASIC2_INTR_EXTERNAL_RESET    ( 2 << 1 )    /* 10: External reset (bits 1 & 2 ) */
-#define H3800_ASIC2_INTR_MASK_UART_0       ( 1 << 4 )
-#define H3800_ASIC2_INTR_MASK_UART_1       ( 1 << 5 )
-#define H3800_ASIC2_INTR_MASK_TIMER        ( 1 << 6 )
-#define H3800_ASIC2_INTR_MASK_OWM          ( 1 << 7 )
-
-#define H3800_ASIC2_INTR_CLOCK_PRESCALE          0x0f    /* 4 bits, max 14 */
-#define H3800_ASIC2_INTR_SET               ( 1 << 4 )    /* Time base enable */
-
-
-#define _H3800_ASIC2_OWM_Base                  0x1800
-#define _H3800_ASIC2_OWM_Command               0x0000    /* R/W 4 bits command register */
-#define _H3800_ASIC2_OWM_Data                  0x0004    /* R/W 8 bits, transmit / receive buffer */
-#define _H3800_ASIC2_OWM_Interrupt             0x0008    /* R/W Command register */
-#define _H3800_ASIC2_OWM_InterruptEnable       0x000c    /* R/W Command register */
-#define _H3800_ASIC2_OWM_ClockDivisor          0x0010    /* R/W 5 bits of divisor and pre-scale */
-
-#define H3800_ASIC2_OWM_Command            H3800_ASIC2_OFFSET( u8, OWM, Command )
-#define H3800_ASIC2_OWM_Data               H3800_ASIC2_OFFSET( u8, OWM, Data )
-#define H3800_ASIC2_OWM_Interrupt          H3800_ASIC2_OFFSET( u8, OWM, Interrupt )
-#define H3800_ASIC2_OWM_InterruptEnable    H3800_ASIC2_OFFSET( u8, OWM, InterruptEnable )
-#define H3800_ASIC2_OWM_ClockDivisor       H3800_ASIC2_OFFSET( u8, OWM, ClockDivisor )
-
-#define H3800_ASIC2_OWM_CMD_ONE_WIRE_RESET ( 1 << 0 )    /* Set to force reset on 1-wire bus */
-#define H3800_ASIC2_OWM_CMD_SRA            ( 1 << 1 )    /* Set to switch to Search ROM accelerator mode */
-#define H3800_ASIC2_OWM_CMD_DQ_OUTPUT      ( 1 << 2 )    /* Write only - forces bus low */
-#define H3800_ASIC2_OWM_CMD_DQ_INPUT       ( 1 << 3 )    /* Read only - reflects state of bus */
-
-#define H3800_ASIC2_OWM_INT_PD             ( 1 << 0 )    /* Presence detect */
-#define H3800_ASIC2_OWM_INT_PDR            ( 1 << 1 )    /* Presence detect result */
-#define H3800_ASIC2_OWM_INT_TBE            ( 1 << 2 )    /* Transmit buffer empty */
-#define H3800_ASIC2_OWM_INT_TEMT           ( 1 << 3 )    /* Transmit shift register empty */
-#define H3800_ASIC2_OWM_INT_RBF            ( 1 << 4 )    /* Receive buffer full */
-
-#define H3800_ASIC2_OWM_INTEN_EPD          ( 1 << 0 )    /* Enable receive buffer full interrupt */
-#define H3800_ASIC2_OWM_INTEN_IAS          ( 1 << 1 )    /* Enable transmit shift register empty interrupt */
-#define H3800_ASIC2_OWM_INTEN_ETBE         ( 1 << 2 )    /* Enable transmit buffer empty interrupt */
-#define H3800_ASIC2_OWM_INTEN_ETMT         ( 1 << 3 )    /* INTR active state */
-#define H3800_ASIC2_OWM_INTEN_ERBF         ( 1 << 4 )    /* Enable presence detect interrupt */
-
-#define _H3800_ASIC2_FlashCtl_Base             0x1A00
-
-/****************************************************/
-/* H3800, ASIC #1
- * This ASIC is accesed through ASIC #2, and
- * mapped into the 1c00 - 1f00 region
- */
-
-#define H3800_ASIC1_OFFSET(s,x,y)   \
-     (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC1_ ## x ## _Base + (_H3800_ASIC1_ ## x ## _ ## y << 1))))
-
-#define _H3800_ASIC1_MMC_Base             0x1c00
-
-#define _H3800_ASIC1_MMC_StartStopClock     0x00    /* R/W 8bit                                  */
-#define _H3800_ASIC1_MMC_Status             0x02    /* R   See below, default 0x0040             */
-#define _H3800_ASIC1_MMC_ClockRate          0x04    /* R/W 8bit, low 3 bits are clock divisor    */
-#define _H3800_ASIC1_MMC_SPIRegister        0x08    /* R/W 8bit, see below                       */
-#define _H3800_ASIC1_MMC_CmdDataCont        0x0a    /* R/W 8bit, write to start MMC adapter      */
-#define _H3800_ASIC1_MMC_ResponseTimeout    0x0c    /* R/W 8bit, clocks before response timeout  */
-#define _H3800_ASIC1_MMC_ReadTimeout        0x0e    /* R/W 16bit, clocks before received data timeout */
-#define _H3800_ASIC1_MMC_BlockLength        0x10    /* R/W 10bit */
-#define _H3800_ASIC1_MMC_NumOfBlocks        0x12    /* R/W 16bit, in block mode, number of blocks  */
-#define _H3800_ASIC1_MMC_InterruptMask      0x1a    /* R/W 8bit */
-#define _H3800_ASIC1_MMC_CommandNumber      0x1c    /* R/W 6 bits */
-#define _H3800_ASIC1_MMC_ArgumentH          0x1e    /* R/W 16 bits  */
-#define _H3800_ASIC1_MMC_ArgumentL          0x20    /* R/W 16 bits */
-#define _H3800_ASIC1_MMC_ResFifo            0x22    /* R   8 x 16 bits - contains response FIFO */
-#define _H3800_ASIC1_MMC_BufferPartFull     0x28    /* R/W 8 bits */
-
-#define H3800_ASIC1_MMC_StartStopClock    H3800_ASIC1_OFFSET(  u8, MMC, StartStopClock )
-#define H3800_ASIC1_MMC_Status            H3800_ASIC1_OFFSET( u16, MMC, Status )
-#define H3800_ASIC1_MMC_ClockRate         H3800_ASIC1_OFFSET(  u8, MMC, ClockRate )
-#define H3800_ASIC1_MMC_SPIRegister       H3800_ASIC1_OFFSET(  u8, MMC, SPIRegister )
-#define H3800_ASIC1_MMC_CmdDataCont       H3800_ASIC1_OFFSET(  u8, MMC, CmdDataCont )
-#define H3800_ASIC1_MMC_ResponseTimeout   H3800_ASIC1_OFFSET(  u8, MMC, ResponseTimeout )
-#define H3800_ASIC1_MMC_ReadTimeout       H3800_ASIC1_OFFSET( u16, MMC, ReadTimeout )
-#define H3800_ASIC1_MMC_BlockLength       H3800_ASIC1_OFFSET( u16, MMC, BlockLength )
-#define H3800_ASIC1_MMC_NumOfBlocks       H3800_ASIC1_OFFSET( u16, MMC, NumOfBlocks )
-#define H3800_ASIC1_MMC_InterruptMask     H3800_ASIC1_OFFSET(  u8, MMC, InterruptMask )
-#define H3800_ASIC1_MMC_CommandNumber     H3800_ASIC1_OFFSET(  u8, MMC, CommandNumber )
-#define H3800_ASIC1_MMC_ArgumentH         H3800_ASIC1_OFFSET( u16, MMC, ArgumentH )
-#define H3800_ASIC1_MMC_ArgumentL         H3800_ASIC1_OFFSET( u16, MMC, ArgumentL )
-#define H3800_ASIC1_MMC_ResFifo           H3800_ASIC1_OFFSET( u16, MMC, ResFifo )
-#define H3800_ASIC1_MMC_BufferPartFull    H3800_ASIC1_OFFSET(  u8, MMC, BufferPartFull )
-
-#define H3800_ASIC1_MMC_STOP_CLOCK                   (1 << 0)   /* Write to "StartStopClock" register */
-#define H3800_ASIC1_MMC_START_CLOCK                  (1 << 1)
-
-#define H3800_ASIC1_MMC_STATUS_READ_TIMEOUT          (1 << 0)
-#define H3800_ASIC1_MMC_STATUS_RESPONSE_TIMEOUT      (1 << 1)
-#define H3800_ASIC1_MMC_STATUS_CRC_WRITE_ERROR       (1 << 2)
-#define H3800_ASIC1_MMC_STATUS_CRC_READ_ERROR        (1 << 3)
-#define H3800_ASIC1_MMC_STATUS_SPI_READ_ERROR        (1 << 4)  /* SPI data token error received */
-#define H3800_ASIC1_MMC_STATUS_CRC_RESPONSE_ERROR    (1 << 5)
-#define H3800_ASIC1_MMC_STATUS_FIFO_EMPTY            (1 << 6)
-#define H3800_ASIC1_MMC_STATUS_FIFO_FULL             (1 << 7)
-#define H3800_ASIC1_MMC_STATUS_CLOCK_ENABLE          (1 << 8)  /* MultiMediaCard clock stopped */
-#define H3800_ASIC1_MMC_STATUS_DATA_TRANSFER_DONE    (1 << 11) /* Write operation, indicates transfer finished */
-#define H3800_ASIC1_MMC_STATUS_END_PROGRAM           (1 << 12) /* End write and read operations */
-#define H3800_ASIC1_MMC_STATUS_END_COMMAND_RESPONSE  (1 << 13) /* End command response */
-
-#define H3800_ASIC1_MMC_SPI_REG_SPI_ENABLE           (1 << 0)  /* Enables SPI mode */
-#define H3800_ASIC1_MMC_SPI_REG_CRC_ON               (1 << 1)  /* 1:turn on CRC    */
-#define H3800_ASIC1_MMC_SPI_REG_SPI_CS_ENABLE        (1 << 2)  /* 1:turn on SPI CS */
-#define H3800_ASIC1_MMC_SPI_REG_CS_ADDRESS_MASK      0x38      /* Bits 3,4,5 are the SPI CS relative address */
-
-#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_NO_RESPONSE  0x00
-#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R1           0x01
-#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R2           0x02
-#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R3           0x03
-#define H3800_ASIC1_MMC_CMD_DATA_CONT_DATA_ENABLE         (1 << 2)  /* This command contains a data transfer */
-#define H3800_ASIC1_MMC_CMD_DATA_CONT_WRITE               (1 << 3)  /* This data transfer is a write */
-#define H3800_ASIC1_MMC_CMD_DATA_CONT_STREAM_MODE         (1 << 4)  /* This data transfer is in stream mode */
-#define H3800_ASIC1_MMC_CMD_DATA_CONT_BUSY_BIT            (1 << 5)  /* Busy signal expected after current cmd */
-#define H3800_ASIC1_MMC_CMD_DATA_CONT_INITIALIZE          (1 << 6)  /* Enables the 80 bits for initializing card */
-
-#define H3800_ASIC1_MMC_INT_MASK_DATA_TRANSFER_DONE       (1 << 0)
-#define H3800_ASIC1_MMC_INT_MASK_PROGRAM_DONE             (1 << 1)
-#define H3800_ASIC1_MMC_INT_MASK_END_COMMAND_RESPONSE     (1 << 2)
-#define H3800_ASIC1_MMC_INT_MASK_BUFFER_READY             (1 << 3)
-
-#define H3800_ASIC1_MMC_BUFFER_PART_FULL                  (1 << 0)
-
-/********* GPIO **********/
-
-#define _H3800_ASIC1_GPIO_Base        0x1e00
-
-#define _H3800_ASIC1_GPIO_Mask          0x30    /* R/W 0:don't mask, 1:mask interrupt */
-#define _H3800_ASIC1_GPIO_Direction     0x32    /* R/W 0:input, 1:output              */
-#define _H3800_ASIC1_GPIO_Out           0x34    /* R/W 0:output low, 1:output high    */
-#define _H3800_ASIC1_GPIO_TriggerType   0x36    /* R/W 0:level, 1:edge                */
-#define _H3800_ASIC1_GPIO_EdgeTrigger   0x38    /* R/W 0:falling, 1:rising            */
-#define _H3800_ASIC1_GPIO_LevelTrigger  0x3A    /* R/W 0:low, 1:high level detect     */
-#define _H3800_ASIC1_GPIO_LevelStatus   0x3C    /* R/W 0:none, 1:detect               */
-#define _H3800_ASIC1_GPIO_EdgeStatus    0x3E    /* R/W 0:none, 1:detect               */
-#define _H3800_ASIC1_GPIO_State         0x40    /* R   See masks below  (default 0)         */
-#define _H3800_ASIC1_GPIO_Reset         0x42    /* R/W See masks below  (default 0x04)      */
-#define _H3800_ASIC1_GPIO_SleepMask     0x44    /* R/W 0:don't mask, 1:mask trigger in sleep mode  */
-#define _H3800_ASIC1_GPIO_SleepDir      0x46    /* R/W direction 0:input, 1:output in sleep mode    */
-#define _H3800_ASIC1_GPIO_SleepOut      0x48    /* R/W level 0:low, 1:high in sleep mode           */
-#define _H3800_ASIC1_GPIO_Status        0x4A    /* R   Pin status                                  */
-#define _H3800_ASIC1_GPIO_BattFaultDir  0x4C    /* R/W direction 0:input, 1:output in batt_fault   */
-#define _H3800_ASIC1_GPIO_BattFaultOut  0x4E    /* R/W level 0:low, 1:high in batt_fault           */
-
-#define H3800_ASIC1_GPIO_Mask         H3800_ASIC1_OFFSET( u16, GPIO, Mask )
-#define H3800_ASIC1_GPIO_Direction    H3800_ASIC1_OFFSET( u16, GPIO, Direction )
-#define H3800_ASIC1_GPIO_Out          H3800_ASIC1_OFFSET( u16, GPIO, Out )
-#define H3800_ASIC1_GPIO_TriggerType  H3800_ASIC1_OFFSET( u16, GPIO, TriggerType )
-#define H3800_ASIC1_GPIO_EdgeTrigger  H3800_ASIC1_OFFSET( u16, GPIO, EdgeTrigger )
-#define H3800_ASIC1_GPIO_LevelTrigger H3800_ASIC1_OFFSET( u16, GPIO, LevelTrigger )
-#define H3800_ASIC1_GPIO_LevelStatus  H3800_ASIC1_OFFSET( u16, GPIO, LevelStatus )
-#define H3800_ASIC1_GPIO_EdgeStatus   H3800_ASIC1_OFFSET( u16, GPIO, EdgeStatus )
-#define H3800_ASIC1_GPIO_State        H3800_ASIC1_OFFSET(  u8, GPIO, State )
-#define H3800_ASIC1_GPIO_Reset        H3800_ASIC1_OFFSET(  u8, GPIO, Reset )
-#define H3800_ASIC1_GPIO_SleepMask    H3800_ASIC1_OFFSET( u16, GPIO, SleepMask )
-#define H3800_ASIC1_GPIO_SleepDir     H3800_ASIC1_OFFSET( u16, GPIO, SleepDir )
-#define H3800_ASIC1_GPIO_SleepOut     H3800_ASIC1_OFFSET( u16, GPIO, SleepOut )
-#define H3800_ASIC1_GPIO_Status       H3800_ASIC1_OFFSET( u16, GPIO, Status )
-#define H3800_ASIC1_GPIO_BattFaultDir H3800_ASIC1_OFFSET( u16, GPIO, BattFaultDir )
-#define H3800_ASIC1_GPIO_BattFaultOut H3800_ASIC1_OFFSET( u16, GPIO, BattFaultOut )
-
-#define H3800_ASIC1_GPIO_STATE_MASK            (1 << 0)
-#define H3800_ASIC1_GPIO_STATE_DIRECTION       (1 << 1)
-#define H3800_ASIC1_GPIO_STATE_OUT             (1 << 2)
-#define H3800_ASIC1_GPIO_STATE_TRIGGER_TYPE    (1 << 3)
-#define H3800_ASIC1_GPIO_STATE_EDGE_TRIGGER    (1 << 4)
-#define H3800_ASIC1_GPIO_STATE_LEVEL_TRIGGER   (1 << 5)
-
-#define H3800_ASIC1_GPIO_RESET_SOFTWARE        (1 << 0)
-#define H3800_ASIC1_GPIO_RESET_AUTO_SLEEP      (1 << 1)
-#define H3800_ASIC1_GPIO_RESET_FIRST_PWR_ON    (1 << 2)
-
-/* These are all outputs */
-#define GPIO_H3800_ASIC1_IR_ON_N          (1 << 0)   /* Apply power to the IR Module */
-#define GPIO_H3800_ASIC1_SD_PWR_ON        (1 << 1)   /* Secure Digital power on */
-#define GPIO_H3800_ASIC1_RS232_ON         (1 << 2)   /* Turn on power to the RS232 chip ? */
-#define GPIO_H3800_ASIC1_PULSE_GEN        (1 << 3)   /* Goes to speaker / earphone */
-#define GPIO_H3800_ASIC1_CH_TIMER         (1 << 4)   /* */
-#define GPIO_H3800_ASIC1_LCD_5V_ON        (1 << 5)   /* Enables LCD_5V */
-#define GPIO_H3800_ASIC1_LCD_ON           (1 << 6)   /* Enables LCD_3V */
-#define GPIO_H3800_ASIC1_LCD_PCI          (1 << 7)   /* Connects to PDWN on LCD controller */
-#define GPIO_H3800_ASIC1_VGH_ON           (1 << 8)   /* Drives VGH on the LCD (+9??) */
-#define GPIO_H3800_ASIC1_VGL_ON           (1 << 9)   /* Drivers VGL on the LCD (-6??) */
-#define GPIO_H3800_ASIC1_FL_PWR_ON        (1 << 10)  /* Frontlight power on */
-#define GPIO_H3800_ASIC1_BT_PWR_ON        (1 << 11)  /* Bluetooth power on */
-#define GPIO_H3800_ASIC1_SPK_ON           (1 << 12)  /* */
-#define GPIO_H3800_ASIC1_EAR_ON_N         (1 << 13)  /* */
-#define GPIO_H3800_ASIC1_AUD_PWR_ON       (1 << 14)  /* */
-
-/* Write enable for the flash */
-
-#define _H3800_ASIC1_FlashWP_Base         0x1F00
-#define _H3800_ASIC1_FlashWP_VPP_ON         0x00    /* R   1: write, 0: protect */
-#define H3800_ASIC1_FlashWP_VPP_ON       H3800_ASIC1_OFFSET( u8, FlashWP, VPP_ON )
 
 #endif /* _INCLUDE_H3600_GPIO_H_ */
diff --git a/arch/arm/mach-sa1100/include/mach/irqs.h b/arch/arm/mach-sa1100/include/mach/irqs.h
index 0cb36609b3ac..ae81f80b0cf9 100644
--- a/arch/arm/mach-sa1100/include/mach/irqs.h
+++ b/arch/arm/mach-sa1100/include/mach/irqs.h
@@ -153,8 +153,6 @@
  */
 #ifdef CONFIG_SA1111
 #define NR_IRQS                 (IRQ_S1_BVD1_STSCHG + 1)
-#elif defined(CONFIG_SA1100_H3800)
-#define NR_IRQS                 (IRQ_BOARD_END)
 #elif defined(CONFIG_SHARP_LOCOMO)
 #define NR_IRQS                 (IRQ_LOCOMO_SPI_TEND + 1)
 #else
@@ -175,23 +173,3 @@
 #define IRQ_LOCOMO_LT_BASE      (IRQ_BOARD_START + 2)
 #define IRQ_LOCOMO_SPI_BASE     (IRQ_BOARD_START + 3)
 
-/* H3800-specific IRQs (CONFIG_SA1100_H3800) */
-#define H3800_KPIO_IRQ_START    (IRQ_BOARD_START)
-#define IRQ_H3800_KEY           (IRQ_BOARD_START + 0)
-#define IRQ_H3800_SPI           (IRQ_BOARD_START + 1)
-#define IRQ_H3800_OWM           (IRQ_BOARD_START + 2)
-#define IRQ_H3800_ADC           (IRQ_BOARD_START + 3)
-#define IRQ_H3800_UART_0        (IRQ_BOARD_START + 4)
-#define IRQ_H3800_UART_1        (IRQ_BOARD_START + 5)
-#define IRQ_H3800_TIMER_0       (IRQ_BOARD_START + 6)
-#define IRQ_H3800_TIMER_1       (IRQ_BOARD_START + 7)
-#define IRQ_H3800_TIMER_2       (IRQ_BOARD_START + 8)
-#define H3800_KPIO_IRQ_COUNT    9
-
-#define H3800_GPIO_IRQ_START    (IRQ_BOARD_START + 9)
-#define IRQ_H3800_PEN           (IRQ_BOARD_START + 9)
-#define IRQ_H3800_SD_DETECT     (IRQ_BOARD_START + 10)
-#define IRQ_H3800_EAR_IN        (IRQ_BOARD_START + 11)
-#define IRQ_H3800_USB_DETECT    (IRQ_BOARD_START + 12)
-#define IRQ_H3800_SD_CON_SLT    (IRQ_BOARD_START + 13)
-#define H3800_GPIO_IRQ_COUNT    5
diff --git a/arch/arm/mach-sa1100/include/mach/system.h b/arch/arm/mach-sa1100/include/mach/system.h
index 63755ca5b1b4..942b153e251d 100644
--- a/arch/arm/mach-sa1100/include/mach/system.h
+++ b/arch/arm/mach-sa1100/include/mach/system.h
@@ -10,7 +10,7 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         if (mode == 's') {
                 /* Jump into ROM at address 0 */
diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c
index 81848aa96424..fd776bb666cd 100644
--- a/arch/arm/mach-sa1100/jornada720.c
+++ b/arch/arm/mach-sa1100/jornada720.c
@@ -226,12 +226,22 @@ static struct platform_device jornada_ssp_device = {
         .id             = -1,
 };
 
+static struct platform_device jornada_kbd_device = {
+        .name           = "jornada720_kbd",
+        .id             = -1,
+};
+
+static struct platform_device jornada_ts_device = {
+        .name           = "jornada_ts",
+        .id             = -1,
+};
+
 static struct platform_device *devices[] __initdata = {
         &sa1111_device,
-#ifdef CONFIG_SA1100_JORNADA720_SSP
         &jornada_ssp_device,
-#endif
         &s1d13xxxfb_device,
+        &jornada_kbd_device,
+        &jornada_ts_device,
 };
 
 static int __init jornada720_init(void)
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index a23fd3d0163a..358d875ace14 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -16,12 +16,28 @@
 #include <asm/leds.h>
 #include <asm/param.h>
 
-#include <mach/hardware.h>
-
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
+#define IO_BASE                 0xe0000000
+#define IO_SIZE                 0x08000000
+#define IO_START                0x40000000
+#define ROMCARD_SIZE            0x08000000
+#define ROMCARD_START           0x10000000
+
+void arch_reset(char mode, const char *cmd)
+{
+        short temp;
+        local_irq_disable();
+        /* Reset the Machine via pc[3] of the sequoia chipset */
+        outw(0x09,0x24);
+        temp=inw(0x26);
+        temp = temp | (1<<3) | (1<<10);
+        outw(0x09,0x24);
+        outw(temp,0x26);
+}
+
 static struct plat_serial8250_port serial_platform_data[] = {
         {
                 .iobase         = 0x3f8,
@@ -50,14 +66,38 @@ static struct platform_device serial_device = {
         },
 };
 
+static struct resource rtc_resources[] = {
+        [0] = {
+                .start  = 0x70,
+                .end    = 0x73,
+                .flags  = IORESOURCE_IO,
+        },
+        [1] = {
+                .start  = IRQ_ISA_RTC_ALARM,
+                .end    = IRQ_ISA_RTC_ALARM,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static struct platform_device rtc_device = {
+        .name           = "rtc_cmos",
+        .id             = -1,
+        .resource       = rtc_resources,
+        .num_resources  = ARRAY_SIZE(rtc_resources),
+};
+
 static int __init shark_init(void)
 {
         int ret;
 
         if (machine_is_shark())
+        {
+                ret = platform_device_register(&rtc_device);
+                if (ret) printk(KERN_ERR "Unable to register RTC device: %d\n", ret);
                 ret = platform_device_register(&serial_device);
-
-        return ret;
+                if (ret) printk(KERN_ERR "Unable to register Serial device: %d\n", ret);
+        }
+        return 0;
 }
 
 arch_initcall(shark_init);
diff --git a/arch/arm/mach-shark/dma.c b/arch/arm/mach-shark/dma.c
index 6774b8d5d13d..10b5b8b3272a 100644
--- a/arch/arm/mach-shark/dma.c
+++ b/arch/arm/mach-shark/dma.c
@@ -13,9 +13,11 @@
 #include <asm/dma.h>
 #include <asm/mach/dma.h>
 
-void __init arch_dma_init(dma_t *dma)
+static int __init shark_dma_init(void)
 {
 #ifdef CONFIG_ISA_DMA
-        isa_init_dma(dma);
+        isa_init_dma();
 #endif
+        return 0;
 }
+core_initcall(shark_dma_init);
diff --git a/arch/arm/mach-shark/include/mach/debug-macro.S b/arch/arm/mach-shark/include/mach/debug-macro.S
index 0836cb78b29a..f97a7626bd58 100644
--- a/arch/arm/mach-shark/include/mach/debug-macro.S
+++ b/arch/arm/mach-shark/include/mach/debug-macro.S
@@ -27,5 +27,3 @@
                 bne     1001b
                 .endm
 
-                .macro  waituart,rd,rx
-                .endm
diff --git a/arch/arm/mach-shark/include/mach/framebuffer.h b/arch/arm/mach-shark/include/mach/framebuffer.h
new file mode 100644
index 000000000000..84a5bf6e5ba3
--- /dev/null
+++ b/arch/arm/mach-shark/include/mach/framebuffer.h
@@ -0,0 +1,16 @@
+/*
+ * arch/arm/mach-shark/include/mach/framebuffer.h
+ *
+ * by Alexander Schulz
+ *
+ */
+
+#ifndef __ASM_ARCH_FRAMEBUFFER_H
+#define __ASM_ARCH_FRAMEBUFFER_H
+
+/* defines for the Framebuffer */
+#define FB_START                0x06000000
+#define FB_SIZE                 0x01000000
+
+#endif
+
diff --git a/arch/arm/mach-shark/include/mach/hardware.h b/arch/arm/mach-shark/include/mach/hardware.h
index 01bf76099ce5..94d84b27a0cb 100644
--- a/arch/arm/mach-shark/include/mach/hardware.h
+++ b/arch/arm/mach-shark/include/mach/hardware.h
@@ -10,35 +10,8 @@
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
 
-#ifndef __ASSEMBLY__
-
-/*
- * Mapping areas
- */
-#define IO_BASE                 0xe0000000
-
-#else
-
-#define IO_BASE                 0
-
-#endif
-
-#define IO_SIZE                 0x08000000
-#define IO_START                0x40000000
-#define ROMCARD_SIZE            0x08000000
-#define ROMCARD_START           0x10000000
-
-
-/* defines for the Framebuffer */
-#define FB_START                0x06000000
-#define FB_SIZE                 0x01000000
-
 #define UNCACHEABLE_ADDR        0xdf010000
 
-#define SEQUOIA_LED_GREEN       (1<<6)
-#define SEQUOIA_LED_AMBER       (1<<5)
-#define SEQUOIA_LED_BACK        (1<<7)
-
 #define pcibios_assign_all_busses()     1
 
 #define PCIBIOS_MIN_IO          0x6000
diff --git a/arch/arm/mach-shark/include/mach/io.h b/arch/arm/mach-shark/include/mach/io.h
index c5cee829fc87..9ccbcecc430b 100644
--- a/arch/arm/mach-shark/include/mach/io.h
+++ b/arch/arm/mach-shark/include/mach/io.h
@@ -11,10 +11,10 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define PCIO_BASE       0xe0000000
-#define IO_SPACE_LIMIT  0xffffffff
+#define IO_SPACE_LIMIT 0xffffffff
 
-#define __io(a)         ((void __iomem *)(PCIO_BASE + (a)))
-#define __mem_pci(addr) (addr)
+#define __io(a)                 ((void __iomem *)(0xe0000000 + (a)))
+
+#define __mem_pci(addr) (addr)
 
 #endif
diff --git a/arch/arm/mach-shark/include/mach/irqs.h b/arch/arm/mach-shark/include/mach/irqs.h
index 0586acd7cdd5..c8e8a4e1f61a 100644
--- a/arch/arm/mach-shark/include/mach/irqs.h
+++ b/arch/arm/mach-shark/include/mach/irqs.h
@@ -7,7 +7,7 @@
 #define NR_IRQS                 16
 
 #define IRQ_ISA_KEYBOARD         1
-#define RTC_IRQ                  8
+#define IRQ_ISA_RTC_ALARM        8
 #define I8042_KBD_IRQ            1
 #define I8042_AUX_IRQ           12
 #define IRQ_HARDDISK            14
diff --git a/arch/arm/mach-shark/include/mach/isa-dma.h b/arch/arm/mach-shark/include/mach/isa-dma.h
index 864298ff3927..96c43b8f8dda 100644
--- a/arch/arm/mach-shark/include/mach/isa-dma.h
+++ b/arch/arm/mach-shark/include/mach/isa-dma.h
@@ -6,10 +6,6 @@
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H
 
-/* Use only the lowest 4MB, nothing else works.
- * The rest is not DMAable. See dev /  .properties
- * in OpenFirmware.
- */
 #define MAX_DMA_CHANNELS        8
 #define DMA_ISA_CASCADE         4
 
diff --git a/arch/arm/mach-shark/include/mach/memory.h b/arch/arm/mach-shark/include/mach/memory.h
index c5ab038925d6..3053e5b7f168 100644
--- a/arch/arm/mach-shark/include/mach/memory.h
+++ b/arch/arm/mach-shark/include/mach/memory.h
@@ -23,6 +23,7 @@ static inline void __arch_adjust_zones(int node, unsigned long *zone_size, unsig
 {
   if (node != 0) return;
   /* Only the first 4 MB (=1024 Pages) are usable for DMA */
+  /* See dev / -> .properties in OpenFirmware. */
   zone_size[1] = zone_size[0] - 1024;
   zone_size[0] = 1024;
   zhole_size[1] = zhole_size[0];
diff --git a/arch/arm/mach-shark/include/mach/system.h b/arch/arm/mach-shark/include/mach/system.h
index e45bd734a03e..21c373b30bbc 100644
--- a/arch/arm/mach-shark/include/mach/system.h
+++ b/arch/arm/mach-shark/include/mach/system.h
@@ -6,20 +6,8 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 
-#include <linux/io.h>
-
-static void arch_reset(char mode)
-{
-        short temp;
-        local_irq_disable();
-        /* Reset the Machine via pc[3] of the sequoia chipset */
-        outw(0x09,0x24);
-        temp=inw(0x26);
-        temp = temp | (1<<3) | (1<<10);
-        outw(0x09,0x24);
-        outw(temp,0x26);
-
-}
+/* Found in arch/mach-shark/core.c */
+extern void arch_reset(char mode, const char *cmd);
 
 static inline void arch_idle(void)
 {
diff --git a/arch/arm/mach-shark/include/mach/uncompress.h b/arch/arm/mach-shark/include/mach/uncompress.h
index 3725e1633418..22ccab4c3c5e 100644
--- a/arch/arm/mach-shark/include/mach/uncompress.h
+++ b/arch/arm/mach-shark/include/mach/uncompress.h
@@ -11,7 +11,7 @@
 
 static inline void putc(int c)
 {
-        int t;
+        volatile int t;
 
         SERIAL_BASE[0] = c;
         t=0x10000;
diff --git a/arch/arm/mach-shark/leds.c b/arch/arm/mach-shark/leds.c
index 8bd8d6bb4d92..c9e32de4adf9 100644
--- a/arch/arm/mach-shark/leds.c
+++ b/arch/arm/mach-shark/leds.c
@@ -22,12 +22,16 @@
 #include <linux/ioport.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/system.h>
 
 #define LED_STATE_ENABLED       1
 #define LED_STATE_CLAIMED       2
+
+#define SEQUOIA_LED_GREEN       (1<<6)
+#define SEQUOIA_LED_AMBER       (1<<5)
+#define SEQUOIA_LED_BACK        (1<<7)
+
 static char led_state;
 static short hw_led_state;
 static short saved_state;
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 1c43494f5c42..565776680d8c 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -335,11 +335,25 @@ static struct resource versatile_i2c_resource = {
 
 static struct platform_device versatile_i2c_device = {
         .name                   = "versatile-i2c",
-        .id                     = -1,
+        .id                     = 0,
         .num_resources          = 1,
         .resource               = &versatile_i2c_resource,
 };
 
+static struct i2c_board_info versatile_i2c_board_info[] = {
+        {
+                I2C_BOARD_INFO("rtc-ds1307", 0xd0 >> 1),
+                .type = "ds1338",
+        },
+};
+
+static int __init versatile_i2c_init(void)
+{
+        return i2c_register_board_info(0, versatile_i2c_board_info,
+                                       ARRAY_SIZE(versatile_i2c_board_info));
+}
+arch_initcall(versatile_i2c_init);
+
 #define VERSATILE_SYSMCI        (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
 
 unsigned int mmc_status(struct device *dev)
diff --git a/arch/arm/mach-versatile/include/mach/system.h b/arch/arm/mach-versatile/include/mach/system.h
index c59e6100c7e3..8ffc12a7cb25 100644
--- a/arch/arm/mach-versatile/include/mach/system.h
+++ b/arch/arm/mach-versatile/include/mach/system.h
@@ -34,7 +34,7 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         u32 val;
 
diff --git a/arch/arm/mach-w90x900/cpu.h b/arch/arm/mach-w90x900/cpu.h
index 40ff40845df0..de29ddcb9459 100644
--- a/arch/arm/mach-w90x900/cpu.h
+++ b/arch/arm/mach-w90x900/cpu.h
@@ -43,35 +43,16 @@ extern void w90p910_init_io(struct map_desc *mach_desc, int size);
 extern void w90p910_init_uarts(struct w90x900_uartcfg *cfg, int no);
 extern void w90p910_init_clocks(int xtal);
 extern void w90p910_map_io(struct map_desc *mach_desc, int size);
+extern struct platform_device w90p910_serial_device;
 extern struct sys_timer w90x900_timer;
 
-#define W90X900_RES(name)                               \
-struct resource w90x900_##name##_resource[] = {         \
-        [0] = {                                         \
-                .start = name##_PA,                     \
-                .end   = name##_PA + 0x0ff,             \
-                .flags = IORESOURCE_MEM,                \
-        },                                              \
-        [1] = {                                         \
-                .start = IRQ_##name,                    \
-                .end   = IRQ_##name,                    \
-                .flags = IORESOURCE_IRQ,                \
-        }                                               \
-}
-
-#define W90X900_DEVICE(devname, regname, devid, platdevname)            \
-struct platform_device w90x900_##devname = {                            \
-        .name           = platdevname,                                  \
-        .id             = devid,                                        \
-        .num_resources  = ARRAY_SIZE(w90x900_##regname##_resource),     \
-        .resource       = w90x900_##regname##_resource,                 \
-}
-
-#define W90X900_UARTCFG(port, flag, uc, ulc, ufc)       \
-{                                                       \
-                .hwport = port,                         \
-                .flags  = flag,                         \
-                .ucon   = uc,                           \
-                .ulcon  = ulc,                          \
-                .ufcon  = ufc,                          \
+#define W90X900_8250PORT(name)                                  \
+{                                                               \
+        .membase        = name##_BA,                            \
+        .mapbase        = name##_PA,                            \
+        .irq            = IRQ_##name,                           \
+        .uartclk        = 11313600,                             \
+        .regshift       = 2,                                    \
+        .iotype         = UPIO_MEM,                             \
+        .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,    \
 }
diff --git a/arch/arm/mach-w90x900/include/mach/system.h b/arch/arm/mach-w90x900/include/mach/system.h
index 93753f922618..940640066857 100644
--- a/arch/arm/mach-w90x900/include/mach/system.h
+++ b/arch/arm/mach-w90x900/include/mach/system.h
@@ -21,7 +21,7 @@ static void arch_idle(void)
 {
 }
 
-static void arch_reset(char mode)
+static void arch_reset(char mode, const char *cmd)
 {
         cpu_reset(0);
 }
diff --git a/arch/arm/mach-w90x900/mach-w90p910evb.c b/arch/arm/mach-w90x900/mach-w90p910evb.c
index 9ebc93f48530..726ff6798a56 100644
--- a/arch/arm/mach-w90x900/mach-w90p910evb.c
+++ b/arch/arm/mach-w90x900/mach-w90p910evb.c
@@ -22,6 +22,7 @@
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -32,28 +33,67 @@
 #include <mach/map.h>
 
 #include "cpu.h"
+/*w90p910 evb norflash driver data */
 
-static struct map_desc w90p910_iodesc[] __initdata = {
+#define W90P910_FLASH_BASE      0xA0000000
+#define W90P910_FLASH_SIZE      0x400000
+
+static struct mtd_partition w90p910_flash_partitions[] = {
+        {
+                .name   =       "NOR Partition 1 for kernel (960K)",
+                .size   =       0xF0000,
+                .offset =       0x10000,
+        },
+        {
+                .name   =       "NOR Partition 2 for image (1M)",
+                .size   =       0x100000,
+                .offset =       0x100000,
+        },
+        {
+                .name   =       "NOR Partition 3 for user (2M)",
+                .size   =       0x200000,
+                .offset =       0x00200000,
+        }
 };
 
-static struct w90x900_uartcfg w90p910_uartcfgs[] = {
-        W90X900_UARTCFG(0, 0, 0, 0, 0),
-        W90X900_UARTCFG(1, 0, 0, 0, 0),
-        W90X900_UARTCFG(2, 0, 0, 0, 0),
-        W90X900_UARTCFG(3, 0, 0, 0, 0),
-        W90X900_UARTCFG(4, 0, 0, 0, 0),
+static struct physmap_flash_data w90p910_flash_data = {
+        .width          =       2,
+        .parts          =       w90p910_flash_partitions,
+        .nr_parts       =       ARRAY_SIZE(w90p910_flash_partitions),
+};
+
+static struct resource w90p910_flash_resources[] = {
+        {
+                .start  =       W90P910_FLASH_BASE,
+                .end    =       W90P910_FLASH_BASE + W90P910_FLASH_SIZE - 1,
+                .flags  =       IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device w90p910_flash_device = {
+        .name           =       "physmap-flash",
+        .id             =       0,
+        .dev            = {
+                                .platform_data = &w90p910_flash_data,
+                        },
+        .resource       =       w90p910_flash_resources,
+        .num_resources  =       ARRAY_SIZE(w90p910_flash_resources),
+};
+
+static struct map_desc w90p910_iodesc[] __initdata = {
 };
 
 /*Here should be your evb resourse,such as LCD*/
 
 static struct platform_device *w90p910evb_dev[] __initdata = {
+        &w90p910_serial_device,
+        &w90p910_flash_device,
 };
 
 static void __init w90p910evb_map_io(void)
 {
         w90p910_map_io(w90p910_iodesc, ARRAY_SIZE(w90p910_iodesc));
         w90p910_init_clocks(0);
-        w90p910_init_uarts(w90p910_uartcfgs, ARRAY_SIZE(w90p910_uartcfgs));
 }
 
 static void __init w90p910evb_init(void)
diff --git a/arch/arm/mach-w90x900/w90p910.c b/arch/arm/mach-w90x900/w90p910.c
index aa783bc94310..2bcbaa681b99 100644
--- a/arch/arm/mach-w90x900/w90p910.c
+++ b/arch/arm/mach-w90x900/w90p910.c
@@ -25,6 +25,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/serial_8250.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -36,12 +37,6 @@
 
 #include "cpu.h"
 
-/*W90P910 has five uarts*/
-
-#define MAX_UART_COUNT 5
-static int uart_count;
-static struct platform_device *uart_devs[MAX_UART_COUNT-1];
-
 /* Initial IO mappings */
 
 static struct map_desc w90p910_iodesc[] __initdata = {
@@ -53,48 +48,19 @@ static struct map_desc w90p910_iodesc[] __initdata = {
         /*IODESC_ENT(LCD),*/
 };
 
-/*Init the dev resource*/
-
-static W90X900_RES(UART0);
-static W90X900_RES(UART1);
-static W90X900_RES(UART2);
-static W90X900_RES(UART3);
-static W90X900_RES(UART4);
-static W90X900_DEVICE(uart0, UART0, 0, "w90x900-uart");
-static W90X900_DEVICE(uart1, UART1, 1, "w90x900-uart");
-static W90X900_DEVICE(uart2, UART2, 2, "w90x900-uart");
-static W90X900_DEVICE(uart3, UART3, 3, "w90x900-uart");
-static W90X900_DEVICE(uart4, UART4, 4, "w90x900-uart");
-
-static struct platform_device *uart_devices[] __initdata = {
-        &w90x900_uart0,
-        &w90x900_uart1,
-        &w90x900_uart2,
-        &w90x900_uart3,
-        &w90x900_uart4
-};
+/* Initial serial platform data */
 
-/*Init W90P910 uart device*/
+struct plat_serial8250_port w90p910_uart_data[] = {
+        W90X900_8250PORT(UART0),
+};
 
-void __init w90p910_init_uarts(struct w90x900_uartcfg *cfg, int no)
-{
-        struct platform_device *platdev;
-        int uart, uartdev;
-
-        /*By min() to judge count of uart be used indeed*/
-
-        uartdev = ARRAY_SIZE(uart_devices);
-        no = min(uartdev, no);
-
-        for (uart = 0; uart < no; uart++, cfg++) {
-                if (cfg->hwport != uart)
-                        printk(KERN_ERR "w90x900_uartcfg[%d] error\n", uart);
-                platdev = uart_devices[cfg->hwport];
-                uart_devs[uart] = platdev;
-                platdev->dev.platform_data = cfg;
-        }
-        uart_count = uart;
-}
+struct platform_device w90p910_serial_device = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM,
+        .dev                    = {
+                .platform_data  = w90p910_uart_data,
+        },
+};
 
 /*Init W90P910 evb io*/
 
@@ -122,13 +88,6 @@ static int __init w90p910_init_cpu(void)
 
 static int __init w90x900_arch_init(void)
 {
-        int ret;
-
-        ret = w90p910_init_cpu();
-        if (ret != 0)
-                return ret;
-
-        return platform_add_devices(uart_devs, uart_count);
-
+        return w90p910_init_cpu();
 }
 arch_initcall(w90x900_arch_init);
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index d490f3773c01..20979564e7ee 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -186,6 +186,24 @@ config CPU_ARM926T
           Say Y if you want support for the ARM926T processor.
           Otherwise, say N.
 
+# FA526
+config CPU_FA526
+        bool
+        select CPU_32v4
+        select CPU_ABRT_EV4
+        select CPU_PABRT_NOIFAR
+        select CPU_CACHE_VIVT
+        select CPU_CP15_MMU
+        select CPU_CACHE_FA
+        select CPU_COPY_FA if MMU
+        select CPU_TLB_FA if MMU
+        help
+          The FA526 is a version of the ARMv4 compatible processor with
+          Branch Target Buffer, Unified TLB and cache line size 16.
+
+          Say Y if you want support for the FA526 processor.
+          Otherwise, say N.
+
 # ARM940T
 config CPU_ARM940T
         bool "Support ARM940T processor" if ARCH_INTEGRATOR
@@ -340,6 +358,17 @@ config CPU_XSC3
         select CPU_TLB_V4WBI if MMU
         select IO_36
 
+# Marvell PJ1 (Mohawk)
+config CPU_MOHAWK
+        bool
+        select CPU_32v5
+        select CPU_ABRT_EV5T
+        select CPU_PABRT_NOIFAR
+        select CPU_CACHE_VIVT
+        select CPU_CP15_MMU
+        select CPU_TLB_V4WBI if MMU
+        select CPU_COPY_V4WB if MMU
+
 # Feroceon
 config CPU_FEROCEON
         bool
@@ -484,6 +513,9 @@ config CPU_CACHE_VIVT
 config CPU_CACHE_VIPT
         bool
 
+config CPU_CACHE_FA
+        bool
+
 if MMU
 # The copy-page model
 config CPU_COPY_V3
@@ -498,6 +530,9 @@ config CPU_COPY_V4WB
 config CPU_COPY_FEROCEON
         bool
 
+config CPU_COPY_FA
+        bool
+
 config CPU_COPY_V6
         bool
 
@@ -528,6 +563,13 @@ config CPU_TLB_FEROCEON
         help
           Feroceon TLB (v4wbi with non-outer-cachable page table walks).
 
+config CPU_TLB_FA
+        bool
+        help
+          Faraday ARM FA526 architecture, unified TLB with writeback cache
+          and invalidate instruction cache entry. Branch target buffer is
+          also supported.
+
 config CPU_TLB_V6
         bool
 
@@ -569,7 +611,7 @@ comment "Processor Features"
 
 config ARM_THUMB
         bool "Support Thumb user binaries"
-        depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON
+        depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V7 || CPU_FEROCEON
         default y
         help
           Say Y if you want to include kernel support for running user space
@@ -638,7 +680,7 @@ config CPU_DCACHE_SIZE
 
 config CPU_DCACHE_WRITETHROUGH
         bool "Force write through D-cache"
-        depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE
+        depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
         default y if CPU_ARM925T
         help
           Say Y here to use the data cache in writethrough mode. Unless you
@@ -653,7 +695,7 @@ config CPU_CACHE_ROUND_ROBIN
 
 config CPU_BPREDICT_DISABLE
         bool "Disable branch prediction"
-        depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
+        depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
         help
           Say Y here to disable branch prediction.  If unsure, say N.
 
@@ -704,7 +746,8 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
 
 config CACHE_L2X0
         bool "Enable the L2x0 outer cache controller"
-        depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || REALVIEW_EB_A9MP
+        depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
+                   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31
         default y
         select OUTER_CACHE
         help
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 480f78a3611a..63e3f6dd0e21 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_MODULES)		+= proc-syms.o
 
 obj-$(CONFIG_ALIGNMENT_TRAP)    += alignment.o
 obj-$(CONFIG_DISCONTIGMEM)      += discontig.o
+obj-$(CONFIG_HIGHMEM)           += highmem.o
 
 obj-$(CONFIG_CPU_ABRT_NOMMU)    += abort-nommu.o
 obj-$(CONFIG_CPU_ABRT_EV4)      += abort-ev4.o
@@ -32,6 +33,7 @@ obj-$(CONFIG_CPU_CACHE_V4WT)	+= cache-v4wt.o
 obj-$(CONFIG_CPU_CACHE_V4WB)    += cache-v4wb.o
 obj-$(CONFIG_CPU_CACHE_V6)      += cache-v6.o
 obj-$(CONFIG_CPU_CACHE_V7)      += cache-v7.o
+obj-$(CONFIG_CPU_CACHE_FA)      += cache-fa.o
 
 obj-$(CONFIG_CPU_COPY_V3)       += copypage-v3.o
 obj-$(CONFIG_CPU_COPY_V4WT)     += copypage-v4wt.o
@@ -41,6 +43,7 @@ obj-$(CONFIG_CPU_COPY_V6)	+= copypage-v6.o context.o
 obj-$(CONFIG_CPU_SA1100)        += copypage-v4mc.o
 obj-$(CONFIG_CPU_XSCALE)        += copypage-xscale.o
 obj-$(CONFIG_CPU_XSC3)          += copypage-xsc3.o
+obj-$(CONFIG_CPU_COPY_FA)       += copypage-fa.o
 
 obj-$(CONFIG_CPU_TLB_V3)        += tlb-v3.o
 obj-$(CONFIG_CPU_TLB_V4WT)      += tlb-v4.o
@@ -49,6 +52,7 @@ obj-$(CONFIG_CPU_TLB_V4WBI)	+= tlb-v4wbi.o
 obj-$(CONFIG_CPU_TLB_FEROCEON)  += tlb-v4wbi.o  # reuse v4wbi TLB functions
 obj-$(CONFIG_CPU_TLB_V6)        += tlb-v6.o
 obj-$(CONFIG_CPU_TLB_V7)        += tlb-v7.o
+obj-$(CONFIG_CPU_TLB_FA)        += tlb-fa.o
 
 obj-$(CONFIG_CPU_ARM610)        += proc-arm6_7.o
 obj-$(CONFIG_CPU_ARM710)        += proc-arm6_7.o
@@ -62,6 +66,7 @@ obj-$(CONFIG_CPU_ARM925T)	+= proc-arm925.o
 obj-$(CONFIG_CPU_ARM926T)       += proc-arm926.o
 obj-$(CONFIG_CPU_ARM940T)       += proc-arm940.o
 obj-$(CONFIG_CPU_ARM946E)       += proc-arm946.o
+obj-$(CONFIG_CPU_FA526)         += proc-fa526.o
 obj-$(CONFIG_CPU_ARM1020)       += proc-arm1020.o
 obj-$(CONFIG_CPU_ARM1020E)      += proc-arm1020e.o
 obj-$(CONFIG_CPU_ARM1022)       += proc-arm1022.o
@@ -70,6 +75,7 @@ obj-$(CONFIG_CPU_SA110)		+= proc-sa110.o
 obj-$(CONFIG_CPU_SA1100)        += proc-sa1100.o
 obj-$(CONFIG_CPU_XSCALE)        += proc-xscale.o
 obj-$(CONFIG_CPU_XSC3)          += proc-xsc3.o
+obj-$(CONFIG_CPU_MOHAWK)        += proc-mohawk.o
 obj-$(CONFIG_CPU_FEROCEON)      += proc-feroceon.o
 obj-$(CONFIG_CPU_V6)            += proc-v6.o
 obj-$(CONFIG_CPU_V7)            += proc-v7.o
diff --git a/arch/arm/mm/cache-fa.S b/arch/arm/mm/cache-fa.S
new file mode 100644
index 000000000000..b63a8f7b95cf
--- /dev/null
+++ b/arch/arm/mm/cache-fa.S
@@ -0,0 +1,220 @@
+/*
+ *  linux/arch/arm/mm/cache-fa.S
+ *
+ *  Copyright (C) 2005 Faraday Corp.
+ *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * Based on cache-v4wb.S:
+ *  Copyright (C) 1997-2002 Russell king
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Processors: FA520 FA526 FA626       
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/memory.h>
+#include <asm/page.h>
+
+#include "proc-macros.S"
+
+/*
+ * The size of one data cache line.
+ */
+#define CACHE_DLINESIZE 16
+
+/*
+ * The total size of the data cache.
+ */
+#ifdef CONFIG_ARCH_GEMINI
+#define CACHE_DSIZE     8192
+#else
+#define CACHE_DSIZE     16384 
+#endif 
+
+/* FIXME: put optimal value here. Current one is just estimation */
+#define CACHE_DLIMIT    (CACHE_DSIZE * 2)
+
+/*
+ *      flush_user_cache_all()
+ *
+ *      Clean and invalidate all cache entries in a particular address
+ *      space.
+ */
+ENTRY(fa_flush_user_cache_all)
+        /* FALLTHROUGH */
+/*
+ *      flush_kern_cache_all()
+ *
+ *      Clean and invalidate the entire cache.
+ */
+ENTRY(fa_flush_kern_cache_all)
+        mov     ip, #0
+        mov     r2, #VM_EXEC
+__flush_whole_cache:
+        mcr     p15, 0, ip, c7, c14, 0          @ clean/invalidate D cache
+        tst     r2, #VM_EXEC
+        mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
+        mcrne   p15, 0, ip, c7, c5, 6           @ invalidate BTB
+        mcrne   p15, 0, ip, c7, c10, 4          @ drain write buffer
+        mcrne   p15, 0, ip, c7, c5, 4           @ prefetch flush
+        mov     pc, lr
+
+/*
+ *      flush_user_cache_range(start, end, flags)
+ *
+ *      Invalidate a range of cache entries in the specified
+ *      address space.
+ *
+ *      - start - start address (inclusive, page aligned)
+ *      - end   - end address (exclusive, page aligned)
+ *      - flags - vma_area_struct flags describing address space
+ */
+ENTRY(fa_flush_user_cache_range)
+        mov     ip, #0
+        sub     r3, r1, r0                      @ calculate total size
+        cmp     r3, #CACHE_DLIMIT               @ total size >= limit?
+        bhs     __flush_whole_cache             @ flush whole D cache
+
+1:      tst     r2, #VM_EXEC
+        mcrne   p15, 0, r0, c7, c5, 1           @ invalidate I line
+        mcr     p15, 0, r0, c7, c14, 1          @ clean and invalidate D entry
+        add     r0, r0, #CACHE_DLINESIZE
+        cmp     r0, r1
+        blo     1b
+        tst     r2, #VM_EXEC
+        mcrne   p15, 0, ip, c7, c5, 6           @ invalidate BTB
+        mcrne   p15, 0, ip, c7, c10, 4          @ data write barrier
+        mcrne   p15, 0, ip, c7, c5, 4           @ prefetch flush
+        mov     pc, lr
+
+/*
+ *      coherent_kern_range(start, end)
+ *
+ *      Ensure coherency between the Icache and the Dcache in the
+ *      region described by start.  If you have non-snooping
+ *      Harvard caches, you need to implement this function.
+ *
+ *      - start  - virtual start address
+ *      - end    - virtual end address
+ */
+ENTRY(fa_coherent_kern_range)
+        /* fall through */
+
+/*
+ *      coherent_user_range(start, end)
+ *
+ *      Ensure coherency between the Icache and the Dcache in the
+ *      region described by start.  If you have non-snooping
+ *      Harvard caches, you need to implement this function.
+ *
+ *      - start  - virtual start address
+ *      - end    - virtual end address
+ */
+ENTRY(fa_coherent_user_range)
+        bic     r0, r0, #CACHE_DLINESIZE - 1
+1:      mcr     p15, 0, r0, c7, c14, 1          @ clean and invalidate D entry
+        mcr     p15, 0, r0, c7, c5, 1           @ invalidate I entry
+        add     r0, r0, #CACHE_DLINESIZE
+        cmp     r0, r1
+        blo     1b
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 6           @ invalidate BTB
+        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
+        mcr     p15, 0, r0, c7, c5, 4           @ prefetch flush
+        mov     pc, lr
+
+/*
+ *      flush_kern_dcache_page(kaddr)
+ *
+ *      Ensure that the data held in the page kaddr is written back
+ *      to the page in question.
+ *
+ *      - kaddr   - kernel address (guaranteed to be page aligned)
+ */
+ENTRY(fa_flush_kern_dcache_page)
+        add     r1, r0, #PAGE_SZ
+1:      mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D line
+        add     r0, r0, #CACHE_DLINESIZE
+        cmp     r0, r1
+        blo     1b
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
+        mov     pc, lr
+
+/*
+ *      dma_inv_range(start, end)
+ *
+ *      Invalidate (discard) the specified virtual address range.
+ *      May not write back any entries.  If 'start' or 'end'
+ *      are not cache line aligned, those lines must be written
+ *      back.
+ *
+ *      - start  - virtual start address
+ *      - end    - virtual end address
+ */
+ENTRY(fa_dma_inv_range)
+        tst     r0, #CACHE_DLINESIZE - 1
+        bic     r0, r0, #CACHE_DLINESIZE - 1
+        mcrne   p15, 0, r0, c7, c14, 1          @ clean & invalidate D entry
+        tst     r1, #CACHE_DLINESIZE - 1
+        bic     r1, r1, #CACHE_DLINESIZE - 1
+        mcrne   p15, 0, r1, c7, c14, 1          @ clean & invalidate D entry
+1:      mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
+        add     r0, r0, #CACHE_DLINESIZE
+        cmp     r0, r1
+        blo     1b
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
+        mov     pc, lr
+
+/*
+ *      dma_clean_range(start, end)
+ *
+ *      Clean (write back) the specified virtual address range.
+ *
+ *      - start  - virtual start address
+ *      - end    - virtual end address
+ */
+ENTRY(fa_dma_clean_range)
+        bic     r0, r0, #CACHE_DLINESIZE - 1
+1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
+        add     r0, r0, #CACHE_DLINESIZE
+        cmp     r0, r1
+        blo     1b
+        mov     r0, #0  
+        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
+        mov     pc, lr
+
+/*
+ *      dma_flush_range(start,end)
+ *      - start   - virtual start address of region
+ *      - end     - virtual end address of region
+ */
+ENTRY(fa_dma_flush_range)
+        bic     r0, r0, #CACHE_DLINESIZE - 1
+1:      mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D entry
+        add     r0, r0, #CACHE_DLINESIZE
+        cmp     r0, r1
+        blo     1b
+        mov     r0, #0  
+        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
+        mov     pc, lr
+
+        __INITDATA
+
+        .type   fa_cache_fns, #object
+ENTRY(fa_cache_fns)
+        .long   fa_flush_kern_cache_all
+        .long   fa_flush_user_cache_all
+        .long   fa_flush_user_cache_range
+        .long   fa_coherent_kern_range
+        .long   fa_coherent_user_range
+        .long   fa_flush_kern_dcache_page
+        .long   fa_dma_inv_range
+        .long   fa_dma_clean_range
+        .long   fa_dma_flush_range
+        .size   fa_cache_fns, . - fa_cache_fns
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
index 80cd207cbaea..d6dd83826f8a 100644
--- a/arch/arm/mm/cache-feroceon-l2.c
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -14,8 +14,12 @@
 
 #include <linux/init.h>
 #include <asm/cacheflush.h>
+#include <asm/kmap_types.h>
+#include <asm/fixmap.h>
+#include <asm/pgtable.h>
+#include <asm/tlbflush.h>
 #include <plat/cache-feroceon-l2.h>
-
+#include "mm.h"
 
 /*
  * Low-level cache maintenance operations.
@@ -34,14 +38,36 @@
  * The range operations require two successive cp15 writes, in
  * between which we don't want to be preempted.
  */
+
+static inline unsigned long l2_start_va(unsigned long paddr)
+{
+#ifdef CONFIG_HIGHMEM
+        /*
+         * Let's do our own fixmap stuff in a minimal way here.
+         * Because range ops can't be done on physical addresses,
+         * we simply install a virtual mapping for it only for the
+         * TLB lookup to occur, hence no need to flush the untouched
+         * memory mapping.  This is protected with the disabling of
+         * interrupts by the caller.
+         */
+        unsigned long idx = KM_L2_CACHE + KM_TYPE_NR * smp_processor_id();
+        unsigned long vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
+        set_pte_ext(TOP_PTE(vaddr), pfn_pte(paddr >> PAGE_SHIFT, PAGE_KERNEL), 0);
+        local_flush_tlb_kernel_page(vaddr);
+        return vaddr + (paddr & ~PAGE_MASK);
+#else
+        return __phys_to_virt(paddr);
+#endif
+}
+
 static inline void l2_clean_pa(unsigned long addr)
 {
         __asm__("mcr p15, 1, %0, c15, c9, 3" : : "r" (addr));
 }
 
-static inline void l2_clean_mva_range(unsigned long start, unsigned long end)
+static inline void l2_clean_pa_range(unsigned long start, unsigned long end)
 {
-        unsigned long flags;
+        unsigned long va_start, va_end, flags;
 
         /*
          * Make sure 'start' and 'end' reference the same page, as
@@ -51,17 +77,14 @@ static inline void l2_clean_mva_range(unsigned long start, unsigned long end)
         BUG_ON((start ^ end) >> PAGE_SHIFT);
 
         raw_local_irq_save(flags);
+        va_start = l2_start_va(start);
+        va_end = va_start + (end - start);
         __asm__("mcr p15, 1, %0, c15, c9, 4\n\t"
                 "mcr p15, 1, %1, c15, c9, 5"
-                : : "r" (start), "r" (end));
+                : : "r" (va_start), "r" (va_end));
         raw_local_irq_restore(flags);
 }
 
-static inline void l2_clean_pa_range(unsigned long start, unsigned long end)
-{
-        l2_clean_mva_range(__phys_to_virt(start), __phys_to_virt(end));
-}
-
 static inline void l2_clean_inv_pa(unsigned long addr)
 {
         __asm__("mcr p15, 1, %0, c15, c10, 3" : : "r" (addr));
@@ -72,9 +95,9 @@ static inline void l2_inv_pa(unsigned long addr)
         __asm__("mcr p15, 1, %0, c15, c11, 3" : : "r" (addr));
 }
 
-static inline void l2_inv_mva_range(unsigned long start, unsigned long end)
+static inline void l2_inv_pa_range(unsigned long start, unsigned long end)
 {
-        unsigned long flags;
+        unsigned long va_start, va_end, flags;
 
         /*
          * Make sure 'start' and 'end' reference the same page, as
@@ -84,17 +107,14 @@ static inline void l2_inv_mva_range(unsigned long start, unsigned long end)
         BUG_ON((start ^ end) >> PAGE_SHIFT);
 
         raw_local_irq_save(flags);
+        va_start = l2_start_va(start);
+        va_end = va_start + (end - start);
         __asm__("mcr p15, 1, %0, c15, c11, 4\n\t"
                 "mcr p15, 1, %1, c15, c11, 5"
-                : : "r" (start), "r" (end));
+                : : "r" (va_start), "r" (va_end));
         raw_local_irq_restore(flags);
 }
 
-static inline void l2_inv_pa_range(unsigned long start, unsigned long end)
-{
-        l2_inv_mva_range(__phys_to_virt(start), __phys_to_virt(end));
-}
-
 
 /*
  * Linux primitives.
diff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c
index 464de893a988..5d180cb0bd94 100644
--- a/arch/arm/mm/cache-xsc3l2.c
+++ b/arch/arm/mm/cache-xsc3l2.c
@@ -17,12 +17,14 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  */
 #include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-
 #include <asm/system.h>
 #include <asm/cputype.h>
 #include <asm/cacheflush.h>
+#include <asm/kmap_types.h>
+#include <asm/fixmap.h>
+#include <asm/pgtable.h>
+#include <asm/tlbflush.h>
+#include "mm.h"
 
 #define CR_L2   (1 << 26)
 
@@ -47,21 +49,11 @@ static inline void xsc3_l2_clean_mva(unsigned long addr)
         __asm__("mcr p15, 1, %0, c7, c11, 1" : : "r" (addr));
 }
 
-static inline void xsc3_l2_clean_pa(unsigned long addr)
-{
-        xsc3_l2_clean_mva(__phys_to_virt(addr));
-}
-
 static inline void xsc3_l2_inv_mva(unsigned long addr)
 {
         __asm__("mcr p15, 1, %0, c7, c7, 1" : : "r" (addr));
 }
 
-static inline void xsc3_l2_inv_pa(unsigned long addr)
-{
-        xsc3_l2_inv_mva(__phys_to_virt(addr));
-}
-
 static inline void xsc3_l2_inv_all(void)
 {
         unsigned long l2ctype, set_way;
@@ -79,50 +71,103 @@ static inline void xsc3_l2_inv_all(void)
         dsb();
 }
 
+#ifdef CONFIG_HIGHMEM
+#define l2_map_save_flags(x)            raw_local_save_flags(x)
+#define l2_map_restore_flags(x)         raw_local_irq_restore(x)
+#else
+#define l2_map_save_flags(x)            ((x) = 0)
+#define l2_map_restore_flags(x)         ((void)(x))
+#endif
+
+static inline unsigned long l2_map_va(unsigned long pa, unsigned long prev_va,
+                                      unsigned long flags)
+{
+#ifdef CONFIG_HIGHMEM
+        unsigned long va = prev_va & PAGE_MASK;
+        unsigned long pa_offset = pa << (32 - PAGE_SHIFT);
+        if (unlikely(pa_offset < (prev_va << (32 - PAGE_SHIFT)))) {
+                /*
+                 * Switching to a new page.  Because cache ops are
+                 * using virtual addresses only, we must put a mapping
+                 * in place for it.  We also enable interrupts for a
+                 * short while and disable them again to protect this
+                 * mapping.
+                 */
+                unsigned long idx;
+                raw_local_irq_restore(flags);
+                idx = KM_L2_CACHE + KM_TYPE_NR * smp_processor_id();
+                va = __fix_to_virt(FIX_KMAP_BEGIN + idx);
+                raw_local_irq_restore(flags | PSR_I_BIT);
+                set_pte_ext(TOP_PTE(va), pfn_pte(pa >> PAGE_SHIFT, PAGE_KERNEL), 0);
+                local_flush_tlb_kernel_page(va);
+        }
+        return va + (pa_offset >> (32 - PAGE_SHIFT));
+#else
+        return __phys_to_virt(pa);
+#endif
+}
+
 static void xsc3_l2_inv_range(unsigned long start, unsigned long end)
 {
+        unsigned long vaddr, flags;
+
         if (start == 0 && end == -1ul) {
                 xsc3_l2_inv_all();
                 return;
         }
 
+        vaddr = -1;  /* to force the first mapping */
+        l2_map_save_flags(flags);
+
         /*
          * Clean and invalidate partial first cache line.
          */
         if (start & (CACHE_LINE_SIZE - 1)) {
-                xsc3_l2_clean_pa(start & ~(CACHE_LINE_SIZE - 1));
-                xsc3_l2_inv_pa(start & ~(CACHE_LINE_SIZE - 1));
+                vaddr = l2_map_va(start & ~(CACHE_LINE_SIZE - 1), vaddr, flags);
+                xsc3_l2_clean_mva(vaddr);
+                xsc3_l2_inv_mva(vaddr);
                 start = (start | (CACHE_LINE_SIZE - 1)) + 1;
         }
 
         /*
-         * Clean and invalidate partial last cache line.
+         * Invalidate all full cache lines between 'start' and 'end'.
          */
-        if (start < end && (end & (CACHE_LINE_SIZE - 1))) {
-                xsc3_l2_clean_pa(end & ~(CACHE_LINE_SIZE - 1));
-                xsc3_l2_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
-                end &= ~(CACHE_LINE_SIZE - 1);
+        while (start < (end & ~(CACHE_LINE_SIZE - 1))) {
+                vaddr = l2_map_va(start, vaddr, flags);
+                xsc3_l2_inv_mva(vaddr);
+                start += CACHE_LINE_SIZE;
         }
 
         /*
-         * Invalidate all full cache lines between 'start' and 'end'.
+         * Clean and invalidate partial last cache line.
          */
-        while (start < end) {
-                xsc3_l2_inv_pa(start);
-                start += CACHE_LINE_SIZE;
+        if (start < end) {
+                vaddr = l2_map_va(start, vaddr, flags);
+                xsc3_l2_clean_mva(vaddr);
+                xsc3_l2_inv_mva(vaddr);
         }
 
+        l2_map_restore_flags(flags);
+
         dsb();
 }
 
 static void xsc3_l2_clean_range(unsigned long start, unsigned long end)
 {
+        unsigned long vaddr, flags;
+
+        vaddr = -1;  /* to force the first mapping */
+        l2_map_save_flags(flags);
+
         start &= ~(CACHE_LINE_SIZE - 1);
         while (start < end) {
-                xsc3_l2_clean_pa(start);
+                vaddr = l2_map_va(start, vaddr, flags);
+                xsc3_l2_clean_mva(vaddr);
                 start += CACHE_LINE_SIZE;
         }
 
+        l2_map_restore_flags(flags);
+
         dsb();
 }
 
@@ -148,18 +193,26 @@ static inline void xsc3_l2_flush_all(void)
 
 static void xsc3_l2_flush_range(unsigned long start, unsigned long end)
 {
+        unsigned long vaddr, flags;
+
         if (start == 0 && end == -1ul) {
                 xsc3_l2_flush_all();
                 return;
         }
 
+        vaddr = -1;  /* to force the first mapping */
+        l2_map_save_flags(flags);
+
         start &= ~(CACHE_LINE_SIZE - 1);
         while (start < end) {
-                xsc3_l2_clean_pa(start);
-                xsc3_l2_inv_pa(start);
+                vaddr = l2_map_va(start, vaddr, flags);
+                xsc3_l2_clean_mva(vaddr);
+                xsc3_l2_inv_mva(vaddr);
                 start += CACHE_LINE_SIZE;
         }
 
+        l2_map_restore_flags(flags);
+
         dsb();
 }
 
diff --git a/arch/arm/mm/copypage-fa.c b/arch/arm/mm/copypage-fa.c
new file mode 100644
index 000000000000..b2a6008b0111
--- /dev/null
+++ b/arch/arm/mm/copypage-fa.c
@@ -0,0 +1,86 @@
+/*
+ *  linux/arch/arm/lib/copypage-fa.S
+ *
+ *  Copyright (C) 2005 Faraday Corp.
+ *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * Based on copypage-v4wb.S:
+ *  Copyright (C) 1995-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/highmem.h>
+
+/*
+ * Faraday optimised copy_user_page
+ */
+static void __naked
+fa_copy_user_page(void *kto, const void *kfrom)
+{
+        asm("\
+        stmfd   sp!, {r4, lr}                   @ 2\n\
+        mov     r2, %0                          @ 1\n\
+1:      ldmia   r1!, {r3, r4, ip, lr}           @ 4\n\
+        stmia   r0, {r3, r4, ip, lr}            @ 4\n\
+        mcr     p15, 0, r0, c7, c14, 1          @ 1   clean and invalidate D line\n\
+        add     r0, r0, #16                     @ 1\n\
+        ldmia   r1!, {r3, r4, ip, lr}           @ 4\n\
+        stmia   r0, {r3, r4, ip, lr}            @ 4\n\
+        mcr     p15, 0, r0, c7, c14, 1          @ 1   clean and invalidate D line\n\
+        add     r0, r0, #16                     @ 1\n\
+        subs    r2, r2, #1                      @ 1\n\
+        bne     1b                              @ 1\n\
+        mcr     p15, 0, r2, c7, c10, 4          @ 1   drain WB\n\
+        ldmfd   sp!, {r4, pc}                   @ 3"
+        :
+        : "I" (PAGE_SIZE / 32));
+}
+
+void fa_copy_user_highpage(struct page *to, struct page *from,
+        unsigned long vaddr)
+{
+        void *kto, *kfrom;
+
+        kto = kmap_atomic(to, KM_USER0);
+        kfrom = kmap_atomic(from, KM_USER1);
+        fa_copy_user_page(kto, kfrom);
+        kunmap_atomic(kfrom, KM_USER1);
+        kunmap_atomic(kto, KM_USER0);
+}
+
+/*
+ * Faraday optimised clear_user_page
+ *
+ * Same story as above.
+ */
+void fa_clear_user_highpage(struct page *page, unsigned long vaddr)
+{
+        void *ptr, *kaddr = kmap_atomic(page, KM_USER0);
+        asm volatile("\
+        mov     r1, %2                          @ 1\n\
+        mov     r2, #0                          @ 1\n\
+        mov     r3, #0                          @ 1\n\
+        mov     ip, #0                          @ 1\n\
+        mov     lr, #0                          @ 1\n\
+1:      stmia   %0, {r2, r3, ip, lr}            @ 4\n\
+        mcr     p15, 0, %0, c7, c14, 1          @ 1   clean and invalidate D line\n\
+        add     %0, %0, #16                     @ 1\n\
+        stmia   %0, {r2, r3, ip, lr}            @ 4\n\
+        mcr     p15, 0, %0, c7, c14, 1          @ 1   clean and invalidate D line\n\
+        add     %0, %0, #16                     @ 1\n\
+        subs    r1, r1, #1                      @ 1\n\
+        bne     1b                              @ 1\n\
+        mcr     p15, 0, r1, c7, c10, 4          @ 1   drain WB"
+        : "=r" (ptr)
+        : "0" (kaddr), "I" (PAGE_SIZE / 32)
+        : "r1", "r2", "r3", "ip", "lr");
+        kunmap_atomic(kaddr, KM_USER0);
+}
+
+struct cpu_user_fns fa_user_fns __initdata = {
+        .cpu_clear_user_highpage = fa_clear_user_highpage,
+        .cpu_copy_user_highpage = fa_copy_user_highpage,
+};
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index f1ef5613ccd4..510c179b0ac8 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -19,6 +19,7 @@
 #include <linux/dma-mapping.h>
 
 #include <asm/memory.h>
+#include <asm/highmem.h>
 #include <asm/cacheflush.h>
 #include <asm/tlbflush.h>
 #include <asm/sizes.h>
@@ -517,6 +518,74 @@ void dma_cache_maint(const void *start, size_t size, int direction)
 }
 EXPORT_SYMBOL(dma_cache_maint);
 
+static void dma_cache_maint_contiguous(struct page *page, unsigned long offset,
+                                       size_t size, int direction)
+{
+        void *vaddr;
+        unsigned long paddr;
+        void (*inner_op)(const void *, const void *);
+        void (*outer_op)(unsigned long, unsigned long);
+
+        switch (direction) {
+        case DMA_FROM_DEVICE:           /* invalidate only */
+                inner_op = dmac_inv_range;
+                outer_op = outer_inv_range;
+                break;
+        case DMA_TO_DEVICE:             /* writeback only */
+                inner_op = dmac_clean_range;
+                outer_op = outer_clean_range;
+                break;
+        case DMA_BIDIRECTIONAL:         /* writeback and invalidate */
+                inner_op = dmac_flush_range;
+                outer_op = outer_flush_range;
+                break;
+        default:
+                BUG();
+        }
+
+        if (!PageHighMem(page)) {
+                vaddr = page_address(page) + offset;
+                inner_op(vaddr, vaddr + size);
+        } else {
+                vaddr = kmap_high_get(page);
+                if (vaddr) {
+                        vaddr += offset;
+                        inner_op(vaddr, vaddr + size);
+                        kunmap_high(page);
+                }
+        }
+
+        paddr = page_to_phys(page) + offset;
+        outer_op(paddr, paddr + size);
+}
+
+void dma_cache_maint_page(struct page *page, unsigned long offset,
+                          size_t size, int dir)
+{
+        /*
+         * A single sg entry may refer to multiple physically contiguous
+         * pages.  But we still need to process highmem pages individually.
+         * If highmem is not configured then the bulk of this loop gets
+         * optimized out.
+         */
+        size_t left = size;
+        do {
+                size_t len = left;
+                if (PageHighMem(page) && len + offset > PAGE_SIZE) {
+                        if (offset >= PAGE_SIZE) {
+                                page += offset / PAGE_SIZE;
+                                offset %= PAGE_SIZE;
+                        }
+                        len = PAGE_SIZE - offset;
+                }
+                dma_cache_maint_contiguous(page, offset, len, dir);
+                offset = 0;
+                page++;
+                left -= len;
+        } while (left);
+}
+EXPORT_SYMBOL(dma_cache_maint_page);
+
 /**
  * dma_map_sg - map a set of SG buffers for streaming mode DMA
  * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
@@ -614,7 +683,8 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
                         continue;
 
                 if (!arch_is_coherent())
-                        dma_cache_maint(sg_virt(s), s->length, dir);
+                        dma_cache_maint_page(sg_page(s), s->offset,
+                                             s->length, dir);
         }
 }
 EXPORT_SYMBOL(dma_sync_sg_for_device);
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 0fa9bf388f0b..4e283481cee1 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -192,7 +192,7 @@ void flush_dcache_page(struct page *page)
         struct address_space *mapping = page_mapping(page);
 
 #ifndef CONFIG_SMP
-        if (mapping && !mapping_mapped(mapping))
+        if (!PageHighMem(page) && mapping && !mapping_mapped(mapping))
                 set_bit(PG_dcache_dirty, &page->flags);
         else
 #endif
diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c
new file mode 100644
index 000000000000..a34954d9df7d
--- /dev/null
+++ b/arch/arm/mm/highmem.c
@@ -0,0 +1,116 @@
+/*
+ * arch/arm/mm/highmem.c -- ARM highmem support
+ *
+ * Author:      Nicolas Pitre
+ * Created:     september 8, 2008
+ * Copyright:   Marvell Semiconductors Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/highmem.h>
+#include <linux/interrupt.h>
+#include <asm/fixmap.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include "mm.h"
+
+void *kmap(struct page *page)
+{
+        might_sleep();
+        if (!PageHighMem(page))
+                return page_address(page);
+        return kmap_high(page);
+}
+EXPORT_SYMBOL(kmap);
+
+void kunmap(struct page *page)
+{
+        BUG_ON(in_interrupt());
+        if (!PageHighMem(page))
+                return;
+        kunmap_high(page);
+}
+EXPORT_SYMBOL(kunmap);
+
+void *kmap_atomic(struct page *page, enum km_type type)
+{
+        unsigned int idx;
+        unsigned long vaddr;
+
+        pagefault_disable();
+        if (!PageHighMem(page))
+                return page_address(page);
+
+        idx = type + KM_TYPE_NR * smp_processor_id();
+        vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
+#ifdef CONFIG_DEBUG_HIGHMEM
+        /*
+         * With debugging enabled, kunmap_atomic forces that entry to 0.
+         * Make sure it was indeed properly unmapped.
+         */
+        BUG_ON(!pte_none(*(TOP_PTE(vaddr))));
+#endif
+        set_pte_ext(TOP_PTE(vaddr), mk_pte(page, kmap_prot), 0);
+        /*
+         * When debugging is off, kunmap_atomic leaves the previous mapping
+         * in place, so this TLB flush ensures the TLB is updated with the
+         * new mapping.
+         */
+        local_flush_tlb_kernel_page(vaddr);
+
+        return (void *)vaddr;
+}
+EXPORT_SYMBOL(kmap_atomic);
+
+void kunmap_atomic(void *kvaddr, enum km_type type)
+{
+        unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
+        unsigned int idx = type + KM_TYPE_NR * smp_processor_id();
+
+        if (kvaddr >= (void *)FIXADDR_START) {
+                __cpuc_flush_dcache_page((void *)vaddr);
+#ifdef CONFIG_DEBUG_HIGHMEM
+                BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx));
+                set_pte_ext(TOP_PTE(vaddr), __pte(0), 0);
+                local_flush_tlb_kernel_page(vaddr);
+#else
+                (void) idx;  /* to kill a warning */
+#endif
+        }
+        pagefault_enable();
+}
+EXPORT_SYMBOL(kunmap_atomic);
+
+void *kmap_atomic_pfn(unsigned long pfn, enum km_type type)
+{
+        unsigned int idx;
+        unsigned long vaddr;
+
+        pagefault_disable();
+
+        idx = type + KM_TYPE_NR * smp_processor_id();
+        vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
+#ifdef CONFIG_DEBUG_HIGHMEM
+        BUG_ON(!pte_none(*(TOP_PTE(vaddr))));
+#endif
+        set_pte_ext(TOP_PTE(vaddr), pfn_pte(pfn, kmap_prot), 0);
+        local_flush_tlb_kernel_page(vaddr);
+
+        return (void *)vaddr;
+}
+
+struct page *kmap_atomic_to_page(const void *ptr)
+{
+        unsigned long vaddr = (unsigned long)ptr;
+        pte_t *pte;
+
+        if (vaddr < FIXADDR_START)
+                return virt_to_page(ptr);
+
+        pte = TOP_PTE(vaddr);
+        return pte_page(*pte);
+}
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 80fd3b69ae1f..8277802ec859 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -15,6 +15,7 @@
 #include <linux/mman.h>
 #include <linux/nodemask.h>
 #include <linux/initrd.h>
+#include <linux/highmem.h>
 
 #include <asm/mach-types.h>
 #include <asm/sections.h>
@@ -485,7 +486,7 @@ void __init mem_init(void)
         int i, node;
 
 #ifndef CONFIG_DISCONTIGMEM
-        max_mapnr   = virt_to_page(high_memory) - mem_map;
+        max_mapnr   = pfn_to_page(max_pfn + PHYS_PFN_OFFSET) - mem_map;
 #endif
 
         /* this will put all unused low memory onto the freelists */
@@ -504,6 +505,19 @@ void __init mem_init(void)
                                     __phys_to_pfn(__pa(swapper_pg_dir)), NULL);
 #endif
 
+#ifdef CONFIG_HIGHMEM
+        /* set highmem page free */
+        for_each_online_node(node) {
+                for_each_nodebank (i, &meminfo, node) {
+                        unsigned long start = bank_pfn_start(&meminfo.bank[i]);
+                        unsigned long end = bank_pfn_end(&meminfo.bank[i]);
+                        if (start >= max_low_pfn + PHYS_PFN_OFFSET)
+                                totalhigh_pages += free_area(start, end, NULL);
+                }
+        }
+        totalram_pages += totalhigh_pages;
+#endif
+
         /*
          * Since our memory may not be contiguous, calculate the
          * real number of pages we have in this system
@@ -521,9 +535,10 @@ void __init mem_init(void)
         initsize = __init_end - __init_begin;
 
         printk(KERN_NOTICE "Memory: %luKB available (%dK code, "
-                "%dK data, %dK init)\n",
+                "%dK data, %dK init, %luK highmem)\n",
                 (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
-                codesize >> 10, datasize >> 10, initsize >> 10);
+                codesize >> 10, datasize >> 10, initsize >> 10,
+                (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10)));
 
         if (PAGE_SIZE >= 16384 && num_physpages <= 128) {
                 extern int sysctl_overcommit_memory;
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index 95bbe112965e..c4f6f05198e0 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -1,7 +1,6 @@
-/* the upper-most page table pointer */
-
 #ifdef CONFIG_MMU
 
+/* the upper-most page table pointer */
 extern pmd_t *top_pmd;
 
 #define TOP_PTE(x)      pte_offset_kernel(top_pmd, x)
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index d4d082c5c2d4..b438fc4fb77b 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -18,9 +18,11 @@
 #include <asm/cputype.h>
 #include <asm/mach-types.h>
 #include <asm/sections.h>
+#include <asm/cachetype.h>
 #include <asm/setup.h>
 #include <asm/sizes.h>
 #include <asm/tlb.h>
+#include <asm/highmem.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -243,6 +245,10 @@ static struct mem_type mem_types[] = {
                 .prot_sect = PMD_TYPE_SECT,
                 .domain    = DOMAIN_KERNEL,
         },
+        [MT_MEMORY_NONCACHED] = {
+                .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
+                .domain    = DOMAIN_KERNEL,
+        },
 };
 
 const struct mem_type *get_mem_type(unsigned int type)
@@ -406,9 +412,28 @@ static void __init build_mem_type_table(void)
                 kern_pgprot |= L_PTE_SHARED;
                 vecs_pgprot |= L_PTE_SHARED;
                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
+                mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
 #endif
         }
 
+        /*
+         * Non-cacheable Normal - intended for memory areas that must
+         * not cause dirty cache line writebacks when used
+         */
+        if (cpu_arch >= CPU_ARCH_ARMv6) {
+                if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
+                        /* Non-cacheable Normal is XCB = 001 */
+                        mem_types[MT_MEMORY_NONCACHED].prot_sect |=
+                                PMD_SECT_BUFFERED;
+                } else {
+                        /* For both ARMv6 and non-TEX-remapping ARMv7 */
+                        mem_types[MT_MEMORY_NONCACHED].prot_sect |=
+                                PMD_SECT_TEX(1);
+                }
+        } else {
+                mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
+        }
+
         for (i = 0; i < 16; i++) {
                 unsigned long v = pgprot_val(protection_map[i]);
                 protection_map[i] = __pgprot(v | user_pgprot);
@@ -677,6 +702,10 @@ static void __init sanity_check_meminfo(void)
                         if (meminfo.nr_banks >= NR_BANKS) {
                                 printk(KERN_CRIT "NR_BANKS too low, "
                                                  "ignoring high memory\n");
+                        } else if (cache_is_vipt_aliasing()) {
+                                printk(KERN_CRIT "HIGHMEM is not yet supported "
+                                                 "with VIPT aliasing cache, "
+                                                 "ignoring high memory\n");
                         } else {
                                 memmove(bank + 1, bank,
                                         (meminfo.nr_banks - i) * sizeof(*bank));
@@ -694,7 +723,7 @@ static void __init sanity_check_meminfo(void)
                  * the vmalloc area.
                  */
                 if (__va(bank->start) >= VMALLOC_MIN ||
-                    __va(bank->start) < PAGE_OFFSET) {
+                    __va(bank->start) < (void *)PAGE_OFFSET) {
                         printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
                                "(vmalloc region overlap).\n",
                                bank->start, bank->start + bank->size - 1);
@@ -895,6 +924,17 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
         flush_cache_all();
 }
 
+static void __init kmap_init(void)
+{
+#ifdef CONFIG_HIGHMEM
+        pmd_t *pmd = pmd_off_k(PKMAP_BASE);
+        pte_t *pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t));
+        BUG_ON(!pmd_none(*pmd) || !pte);
+        __pmd_populate(pmd, __pa(pte) | _PAGE_KERNEL_TABLE);
+        pkmap_page_table = pte + PTRS_PER_PTE;
+#endif
+}
+
 /*
  * paging_init() sets up the page tables, initialises the zone memory
  * maps, and sets up the zero page, bad page and bad page tables.
@@ -908,6 +948,7 @@ void __init paging_init(struct machine_desc *mdesc)
         prepare_page_table();
         bootmem_init();
         devicemaps_init(mdesc);
+        kmap_init();
 
         top_pmd = pmd_off_k(0xffff0000);
 
diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S
new file mode 100644
index 000000000000..08b8a955d5d7
--- /dev/null
+++ b/arch/arm/mm/proc-fa526.S
@@ -0,0 +1,248 @@
+/*
+ *  linux/arch/arm/mm/proc-fa526.S: MMU functions for FA526
+ *
+ *  Written by : Luke Lee
+ *  Copyright (C) 2005 Faraday Corp.
+ *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ *
+ * These are the low level assembler for performing cache and TLB
+ * functions on the fa526.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/assembler.h>
+#include <asm/hwcap.h>
+#include <asm/pgtable-hwdef.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+
+#include "proc-macros.S"
+
+#define CACHE_DLINESIZE 16
+
+        .text
+/*
+ * cpu_fa526_proc_init()
+ */
+ENTRY(cpu_fa526_proc_init)
+        mov     pc, lr
+
+/*
+ * cpu_fa526_proc_fin()
+ */
+ENTRY(cpu_fa526_proc_fin)
+        stmfd   sp!, {lr}
+        mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
+        msr     cpsr_c, ip
+        bl      fa_flush_kern_cache_all
+        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
+        bic     r0, r0, #0x1000                 @ ...i............
+        bic     r0, r0, #0x000e                 @ ............wca.
+        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
+        nop
+        nop
+        ldmfd   sp!, {pc}
+
+/*
+ * cpu_fa526_reset(loc)
+ *
+ * Perform a soft reset of the system.  Put the CPU into the
+ * same state as it would be if it had been reset, and branch
+ * to what would be the reset vector.
+ *
+ * loc: location to jump to for soft reset
+ */
+        .align  4
+ENTRY(cpu_fa526_reset)
+/* TODO: Use CP8 if possible... */
+        mov     ip, #0
+        mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
+        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
+#ifdef CONFIG_MMU
+        mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
+#endif
+        mrc     p15, 0, ip, c1, c0, 0           @ ctrl register
+        bic     ip, ip, #0x000f                 @ ............wcam
+        bic     ip, ip, #0x1100                 @ ...i...s........
+        bic     ip, ip, #0x0800                 @ BTB off
+        mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
+        nop
+        nop
+        mov     pc, r0
+
+/*
+ * cpu_fa526_do_idle()
+ */
+        .align  4
+ENTRY(cpu_fa526_do_idle)
+        mcr     p15, 0, r0, c7, c0, 4           @ Wait for interrupt
+        mov     pc, lr
+
+
+ENTRY(cpu_fa526_dcache_clean_area)
+1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
+        add     r0, r0, #CACHE_DLINESIZE
+        subs    r1, r1, #CACHE_DLINESIZE
+        bhi     1b
+        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+        mov     pc, lr
+
+/* =============================== PageTable ============================== */
+
+/*
+ * cpu_fa526_switch_mm(pgd)
+ *
+ * Set the translation base pointer to be as described by pgd.
+ *
+ * pgd: new page tables
+ */
+        .align  4
+ENTRY(cpu_fa526_switch_mm)
+#ifdef CONFIG_MMU
+        mov     ip, #0
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+        mcr     p15, 0, ip, c7, c6, 0           @ invalidate D cache
+#else
+        mcr     p15, 0, ip, c7, c14, 0          @ clean and invalidate whole D cache
+#endif
+        mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache
+        mcr     p15, 0, ip, c7, c5, 6           @ invalidate BTB since mm changed
+        mcr     p15, 0, ip, c7, c10, 4          @ data write barrier
+        mcr     p15, 0, ip, c7, c5, 4           @ prefetch flush
+        mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
+        mcr     p15, 0, ip, c8, c7, 0           @ invalidate UTLB
+#endif
+        mov     pc, lr
+
+/*
+ * cpu_fa526_set_pte_ext(ptep, pte, ext)
+ *
+ * Set a PTE and flush it out
+ */
+        .align  4
+ENTRY(cpu_fa526_set_pte_ext)
+#ifdef CONFIG_MMU
+        armv3_set_pte_ext
+        mov     r0, r0
+        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+#endif
+        mov     pc, lr
+
+        __INIT
+
+        .type   __fa526_setup, #function
+__fa526_setup:
+        /* On return of this routine, r0 must carry correct flags for CFG register */
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c7              @ invalidate I,D caches on v4
+        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer on v4
+#ifdef CONFIG_MMU
+        mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
+#endif
+        mcr     p15, 0, r0, c7, c5, 5           @ invalidate IScratchpad RAM
+
+        mov     r0, #1
+        mcr     p15, 0, r0, c1, c1, 0           @ turn-on ECR
+
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 6           @ invalidate BTB All
+        mcr     p15, 0, r0, c7, c10, 4          @ data write barrier
+        mcr     p15, 0, r0, c7, c5, 4           @ prefetch flush
+
+        mov     r0, #0x1f                       @ Domains 0, 1 = manager, 2 = client
+        mcr     p15, 0, r0, c3, c0              @ load domain access register
+
+        mrc     p15, 0, r0, c1, c0              @ get control register v4
+        ldr     r5, fa526_cr1_clear
+        bic     r0, r0, r5
+        ldr     r5, fa526_cr1_set
+        orr     r0, r0, r5
+        mov     pc, lr
+        .size   __fa526_setup, . - __fa526_setup
+
+        /*
+         * .RVI ZFRS BLDP WCAM
+         * ..11 1001 .111 1101
+         *
+         */
+        .type   fa526_cr1_clear, #object
+        .type   fa526_cr1_set, #object
+fa526_cr1_clear:
+        .word   0x3f3f
+fa526_cr1_set:
+        .word   0x397D
+
+        __INITDATA
+
+/*
+ * Purpose : Function pointers used to access above functions - all calls
+ *           come through these
+ */
+        .type   fa526_processor_functions, #object
+fa526_processor_functions:
+        .word   v4_early_abort
+        .word   pabort_noifar
+        .word   cpu_fa526_proc_init
+        .word   cpu_fa526_proc_fin
+        .word   cpu_fa526_reset
+        .word   cpu_fa526_do_idle
+        .word   cpu_fa526_dcache_clean_area
+        .word   cpu_fa526_switch_mm
+        .word   cpu_fa526_set_pte_ext
+        .size   fa526_processor_functions, . - fa526_processor_functions
+
+        .section ".rodata"
+
+        .type   cpu_arch_name, #object
+cpu_arch_name:
+        .asciz  "armv4"
+        .size   cpu_arch_name, . - cpu_arch_name
+
+        .type   cpu_elf_name, #object
+cpu_elf_name:
+        .asciz  "v4"
+        .size   cpu_elf_name, . - cpu_elf_name
+
+        .type   cpu_fa526_name, #object
+cpu_fa526_name:
+        .asciz  "FA526"
+        .size   cpu_fa526_name, . - cpu_fa526_name
+
+        .align
+
+        .section ".proc.info.init", #alloc, #execinstr
+
+        .type   __fa526_proc_info,#object
+__fa526_proc_info:
+        .long   0x66015261
+        .long   0xff01fff1
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_BUFFERABLE | \
+                PMD_SECT_CACHEABLE | \
+                PMD_BIT4 | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        .long   PMD_TYPE_SECT | \
+                PMD_BIT4 | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        b       __fa526_setup
+        .long   cpu_arch_name
+        .long   cpu_elf_name
+        .long   HWCAP_SWP | HWCAP_HALF
+        .long   cpu_fa526_name
+        .long   fa526_processor_functions
+        .long   fa_tlb_fns
+        .long   fa_user_fns
+        .long   fa_cache_fns
+        .size   __fa526_proc_info, . - __fa526_proc_info
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
new file mode 100644
index 000000000000..540f5078496b
--- /dev/null
+++ b/arch/arm/mm/proc-mohawk.S
@@ -0,0 +1,416 @@
+/*
+ *  linux/arch/arm/mm/proc-mohawk.S: MMU functions for Marvell PJ1 core
+ *
+ *  PJ1 (codename Mohawk) is a hybrid of the xscale3 and Marvell's own core.
+ *
+ *  Heavily based on proc-arm926.S and proc-xsc3.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/assembler.h>
+#include <asm/hwcap.h>
+#include <asm/pgtable-hwdef.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/ptrace.h>
+#include "proc-macros.S"
+
+/*
+ * This is the maximum size of an area which will be flushed.  If the
+ * area is larger than this, then we flush the whole cache.
+ */
+#define CACHE_DLIMIT    32768
+
+/*
+ * The cache line size of the L1 D cache.
+ */
+#define CACHE_DLINESIZE 32
+
+/*
+ * cpu_mohawk_proc_init()
+ */
+ENTRY(cpu_mohawk_proc_init)
+        mov     pc, lr
+
+/*
+ * cpu_mohawk_proc_fin()
+ */
+ENTRY(cpu_mohawk_proc_fin)
+        stmfd   sp!, {lr}
+        mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
+        msr     cpsr_c, ip
+        bl      mohawk_flush_kern_cache_all
+        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
+        bic     r0, r0, #0x1800                 @ ...iz...........
+        bic     r0, r0, #0x0006                 @ .............ca.
+        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
+        ldmfd   sp!, {pc}
+
+/*
+ * cpu_mohawk_reset(loc)
+ *
+ * Perform a soft reset of the system.  Put the CPU into the
+ * same state as it would be if it had been reset, and branch
+ * to what would be the reset vector.
+ *
+ * loc: location to jump to for soft reset
+ *
+ * (same as arm926)
+ */
+        .align  5
+ENTRY(cpu_mohawk_reset)
+        mov     ip, #0
+        mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
+        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
+        mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
+        mrc     p15, 0, ip, c1, c0, 0           @ ctrl register
+        bic     ip, ip, #0x0007                 @ .............cam
+        bic     ip, ip, #0x1100                 @ ...i...s........
+        mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
+        mov     pc, r0
+
+/*
+ * cpu_mohawk_do_idle()
+ *
+ * Called with IRQs disabled
+ */
+        .align  5
+ENTRY(cpu_mohawk_do_idle)
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
+        mcr     p15, 0, r0, c7, c0, 4           @ wait for interrupt
+        mov     pc, lr
+
+/*
+ *      flush_user_cache_all()
+ *
+ *      Clean and invalidate all cache entries in a particular
+ *      address space.
+ */
+ENTRY(mohawk_flush_user_cache_all)
+        /* FALLTHROUGH */
+
+/*
+ *      flush_kern_cache_all()
+ *
+ *      Clean and invalidate the entire cache.
+ */
+ENTRY(mohawk_flush_kern_cache_all)
+        mov     r2, #VM_EXEC
+        mov     ip, #0
+__flush_whole_cache:
+        mcr     p15, 0, ip, c7, c14, 0          @ clean & invalidate all D cache
+        tst     r2, #VM_EXEC
+        mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
+        mcrne   p15, 0, ip, c7, c10, 0          @ drain write buffer
+        mov     pc, lr
+
+/*
+ *      flush_user_cache_range(start, end, flags)
+ *
+ *      Clean and invalidate a range of cache entries in the
+ *      specified address range.
+ *
+ *      - start - start address (inclusive)
+ *      - end   - end address (exclusive)
+ *      - flags - vm_flags describing address space
+ *
+ * (same as arm926)
+ */
+ENTRY(mohawk_flush_user_cache_range)
+        mov     ip, #0
+        sub     r3, r1, r0                      @ calculate total size
+        cmp     r3, #CACHE_DLIMIT
+        bgt     __flush_whole_cache
+1:      tst     r2, #VM_EXEC
+        mcr     p15, 0, r0, c7, c14, 1          @ clean and invalidate D entry
+        mcrne   p15, 0, r0, c7, c5, 1           @ invalidate I entry
+        add     r0, r0, #CACHE_DLINESIZE
+        mcr     p15, 0, r0, c7, c14, 1          @ clean and invalidate D entry
+        mcrne   p15, 0, r0, c7, c5, 1           @ invalidate I entry
+        add     r0, r0, #CACHE_DLINESIZE
+        cmp     r0, r1
+        blo     1b
+        tst     r2, #VM_EXEC
+        mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
+        mov     pc, lr
+
+/*
+ *      coherent_kern_range(start, end)
+ *
+ *      Ensure coherency between the Icache and the Dcache in the
+ *      region described by start, end.  If you have non-snooping
+ *      Harvard caches, you need to implement this function.
+ *
+ *      - start - virtual start address
+ *      - end   - virtual end address
+ */
+ENTRY(mohawk_coherent_kern_range)
+        /* FALLTHROUGH */
+
+/*
+ *      coherent_user_range(start, end)
+ *
+ *      Ensure coherency between the Icache and the Dcache in the
+ *      region described by start, end.  If you have non-snooping
+ *      Harvard caches, you need to implement this function.
+ *
+ *      - start - virtual start address
+ *      - end   - virtual end address
+ *
+ * (same as arm926)
+ */
+ENTRY(mohawk_coherent_user_range)
+        bic     r0, r0, #CACHE_DLINESIZE - 1
+1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
+        mcr     p15, 0, r0, c7, c5, 1           @ invalidate I entry
+        add     r0, r0, #CACHE_DLINESIZE
+        cmp     r0, r1
+        blo     1b
+        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+        mov     pc, lr
+
+/*
+ *      flush_kern_dcache_page(void *page)
+ *
+ *      Ensure no D cache aliasing occurs, either with itself or
+ *      the I cache
+ *
+ *      - addr  - page aligned address
+ */
+ENTRY(mohawk_flush_kern_dcache_page)
+        add     r1, r0, #PAGE_SZ
+1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
+        add     r0, r0, #CACHE_DLINESIZE
+        cmp     r0, r1
+        blo     1b
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+        mov     pc, lr
+
+/*
+ *      dma_inv_range(start, end)
+ *
+ *      Invalidate (discard) the specified virtual address range.
+ *      May not write back any entries.  If 'start' or 'end'
+ *      are not cache line aligned, those lines must be written
+ *      back.
+ *
+ *      - start - virtual start address
+ *      - end   - virtual end address
+ *
+ * (same as v4wb)
+ */
+ENTRY(mohawk_dma_inv_range)
+        tst     r0, #CACHE_DLINESIZE - 1
+        mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
+        tst     r1, #CACHE_DLINESIZE - 1
+        mcrne   p15, 0, r1, c7, c10, 1          @ clean D entry
+        bic     r0, r0, #CACHE_DLINESIZE - 1
+1:      mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
+        add     r0, r0, #CACHE_DLINESIZE
+        cmp     r0, r1
+        blo     1b
+        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+        mov     pc, lr
+
+/*
+ *      dma_clean_range(start, end)
+ *
+ *      Clean the specified virtual address range.
+ *
+ *      - start - virtual start address
+ *      - end   - virtual end address
+ *
+ * (same as v4wb)
+ */
+ENTRY(mohawk_dma_clean_range)
+        bic     r0, r0, #CACHE_DLINESIZE - 1
+1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
+        add     r0, r0, #CACHE_DLINESIZE
+        cmp     r0, r1
+        blo     1b
+        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+        mov     pc, lr
+
+/*
+ *      dma_flush_range(start, end)
+ *
+ *      Clean and invalidate the specified virtual address range.
+ *
+ *      - start - virtual start address
+ *      - end   - virtual end address
+ */
+ENTRY(mohawk_dma_flush_range)
+        bic     r0, r0, #CACHE_DLINESIZE - 1
+1:
+        mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
+        add     r0, r0, #CACHE_DLINESIZE
+        cmp     r0, r1
+        blo     1b
+        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+        mov     pc, lr
+
+ENTRY(mohawk_cache_fns)
+        .long   mohawk_flush_kern_cache_all
+        .long   mohawk_flush_user_cache_all
+        .long   mohawk_flush_user_cache_range
+        .long   mohawk_coherent_kern_range
+        .long   mohawk_coherent_user_range
+        .long   mohawk_flush_kern_dcache_page
+        .long   mohawk_dma_inv_range
+        .long   mohawk_dma_clean_range
+        .long   mohawk_dma_flush_range
+
+ENTRY(cpu_mohawk_dcache_clean_area)
+1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
+        add     r0, r0, #CACHE_DLINESIZE
+        subs    r1, r1, #CACHE_DLINESIZE
+        bhi     1b
+        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+        mov     pc, lr
+
+/*
+ * cpu_mohawk_switch_mm(pgd)
+ *
+ * Set the translation base pointer to be as described by pgd.
+ *
+ * pgd: new page tables
+ */
+        .align  5
+ENTRY(cpu_mohawk_switch_mm)
+        mov     ip, #0
+        mcr     p15, 0, ip, c7, c14, 0          @ clean & invalidate all D cache
+        mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache
+        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
+        orr     r0, r0, #0x18                   @ cache the page table in L2
+        mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
+        mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
+        mov     pc, lr
+
+/*
+ * cpu_mohawk_set_pte_ext(ptep, pte, ext)
+ *
+ * Set a PTE and flush it out
+ */
+        .align  5
+ENTRY(cpu_mohawk_set_pte_ext)
+        armv3_set_pte_ext
+        mov     r0, r0
+        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
+        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+        mov     pc, lr
+
+        __INIT
+
+        .type   __mohawk_setup, #function
+__mohawk_setup:
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c7              @ invalidate I,D caches
+        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
+        mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs
+        orr     r4, r4, #0x18                   @ cache the page table in L2
+        mcr     p15, 0, r4, c2, c0, 0           @ load page table pointer
+
+        mov     r0, #0                          @ don't allow CP access
+        mcr     p15, 0, r0, c15, c1, 0          @ write CP access register
+
+        adr     r5, mohawk_crval
+        ldmia   r5, {r5, r6}
+        mrc     p15, 0, r0, c1, c0              @ get control register
+        bic     r0, r0, r5
+        orr     r0, r0, r6
+        mov     pc, lr
+
+        .size   __mohawk_setup, . - __mohawk_setup
+
+        /*
+         *  R
+         * .RVI ZFRS BLDP WCAM
+         * .011 1001 ..00 0101
+         *
+         */
+        .type   mohawk_crval, #object
+mohawk_crval:
+        crval   clear=0x00007f3f, mmuset=0x00003905, ucset=0x00001134
+
+        __INITDATA
+
+/*
+ * Purpose : Function pointers used to access above functions - all calls
+ *           come through these
+ */
+        .type   mohawk_processor_functions, #object
+mohawk_processor_functions:
+        .word   v5t_early_abort
+        .word   pabort_noifar
+        .word   cpu_mohawk_proc_init
+        .word   cpu_mohawk_proc_fin
+        .word   cpu_mohawk_reset
+        .word   cpu_mohawk_do_idle
+        .word   cpu_mohawk_dcache_clean_area
+        .word   cpu_mohawk_switch_mm
+        .word   cpu_mohawk_set_pte_ext
+        .size   mohawk_processor_functions, . - mohawk_processor_functions
+
+        .section ".rodata"
+
+        .type   cpu_arch_name, #object
+cpu_arch_name:
+        .asciz  "armv5te"
+        .size   cpu_arch_name, . - cpu_arch_name
+
+        .type   cpu_elf_name, #object
+cpu_elf_name:
+        .asciz  "v5"
+        .size   cpu_elf_name, . - cpu_elf_name
+
+        .type   cpu_mohawk_name, #object
+cpu_mohawk_name:
+        .asciz  "Marvell 88SV331x"
+        .size   cpu_mohawk_name, . - cpu_mohawk_name
+
+        .align
+
+        .section ".proc.info.init", #alloc, #execinstr
+
+        .type   __88sv331x_proc_info,#object
+__88sv331x_proc_info:
+        .long   0x56158000                      @ Marvell 88SV331x (MOHAWK)
+        .long   0xfffff000
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_BUFFERABLE | \
+                PMD_SECT_CACHEABLE | \
+                PMD_BIT4 | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        .long   PMD_TYPE_SECT | \
+                PMD_BIT4 | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        b       __mohawk_setup
+        .long   cpu_arch_name
+        .long   cpu_elf_name
+        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+        .long   cpu_mohawk_name
+        .long   mohawk_processor_functions
+        .long   v4wbi_tlb_fns
+        .long   v4wb_user_fns
+        .long   mohawk_cache_fns
+        .size   __88sv331x_proc_info, . - __88sv331x_proc_info
diff --git a/arch/arm/mm/tlb-fa.S b/arch/arm/mm/tlb-fa.S
new file mode 100644
index 000000000000..9694f1f6f485
--- /dev/null
+++ b/arch/arm/mm/tlb-fa.S
@@ -0,0 +1,75 @@
+/*
+ *  linux/arch/arm/mm/tlb-fa.S
+ *
+ *  Copyright (C) 2005 Faraday Corp.
+ *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * Based on tlb-v4wbi.S:
+ *  Copyright (C) 1997-2002 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  ARM architecture version 4, Faraday variation.
+ *  This assume an unified TLBs, with a write buffer, and branch target buffer (BTB)
+ *
+ *  Processors: FA520 FA526 FA626
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/asm-offsets.h>
+#include <asm/tlbflush.h>
+#include "proc-macros.S"
+
+
+/*
+ *      flush_user_tlb_range(start, end, mm)
+ *
+ *      Invalidate a range of TLB entries in the specified address space.
+ *
+ *      - start - range start address
+ *      - end   - range end address
+ *      - mm    - mm_struct describing address space
+ */
+        .align  4
+ENTRY(fa_flush_user_tlb_range)
+        vma_vm_mm ip, r2
+        act_mm  r3                              @ get current->active_mm
+        eors    r3, ip, r3                      @ == mm ?
+        movne   pc, lr                          @ no, we dont do anything
+        mov     r3, #0
+        mcr     p15, 0, r3, c7, c10, 4          @ drain WB
+        bic     r0, r0, #0x0ff
+        bic     r0, r0, #0xf00
+1:      mcr     p15, 0, r0, c8, c7, 1           @ invalidate UTLB entry
+        add     r0, r0, #PAGE_SZ
+        cmp     r0, r1
+        blo     1b
+        mcr     p15, 0, r3, c7, c5, 6           @ invalidate BTB
+        mcr     p15, 0, r3, c7, c10, 4          @ data write barrier
+        mov     pc, lr
+
+
+ENTRY(fa_flush_kern_tlb_range)
+        mov     r3, #0
+        mcr     p15, 0, r3, c7, c10, 4          @ drain WB
+        bic     r0, r0, #0x0ff
+        bic     r0, r0, #0xf00
+1:      mcr     p15, 0, r0, c8, c7, 1           @ invalidate UTLB entry
+        add     r0, r0, #PAGE_SZ
+        cmp     r0, r1
+        blo     1b
+        mcr     p15, 0, r3, c7, c5, 6           @ invalidate BTB
+        mcr     p15, 0, r3, c7, c10, 4          @ data write barrier
+        mcr     p15, 0, r3, c7, c5, 4           @ prefetch flush
+        mov     pc, lr
+
+        __INITDATA
+
+        .type   fa_tlb_fns, #object
+ENTRY(fa_tlb_fns)
+        .long   fa_flush_user_tlb_range
+        .long   fa_flush_kern_tlb_range
+        .long   fa_tlb_flags
+        .size   fa_tlb_fns, . - fa_tlb_fns
diff --git a/arch/arm/oprofile/backtrace.c b/arch/arm/oprofile/backtrace.c
index cefc21c2eee4..d805a52b5032 100644
--- a/arch/arm/oprofile/backtrace.c
+++ b/arch/arm/oprofile/backtrace.c
@@ -18,15 +18,14 @@
 #include <linux/mm.h>
 #include <linux/uaccess.h>
 #include <asm/ptrace.h>
-
-#include "../kernel/stacktrace.h"
+#include <asm/stacktrace.h>
 
 static int report_trace(struct stackframe *frame, void *d)
 {
         unsigned int *depth = d;
 
         if (*depth) {
-                oprofile_add_trace(frame->lr);
+                oprofile_add_trace(frame->pc);
                 (*depth)--;
         }
 
@@ -70,9 +69,12 @@ void arm_backtrace(struct pt_regs * const regs, unsigned int depth)
         struct frame_tail *tail = ((struct frame_tail *) regs->ARM_fp) - 1;
 
         if (!user_mode(regs)) {
-                unsigned long base = ((unsigned long)regs) & ~(THREAD_SIZE - 1);
-                walk_stackframe(regs->ARM_fp, base, base + THREAD_SIZE,
-                                report_trace, &depth);
+                struct stackframe frame;
+                frame.fp = regs->ARM_fp;
+                frame.sp = regs->ARM_sp;
+                frame.lr = regs->ARM_lr;
+                frame.pc = regs->ARM_pc;
+                walk_stackframe(&frame, report_trace, &depth);
                 return;
         }
 
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 9cc2b16fdf79..17d0e9906d5f 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -3,7 +3,7 @@ if ARCH_MXC
 menu "Freescale MXC Implementations"
 
 choice
-        prompt "MXC/iMX Base Type"
+        prompt "Freescale CPU family:"
         default ARCH_MX3
 
 config ARCH_MX1
@@ -15,12 +15,14 @@ config ARCH_MX1
 config ARCH_MX2
         bool "MX2-based"
         select CPU_ARM926T
+        select COMMON_CLKDEV
         help
           This enables support for systems based on the Freescale i.MX2 family
 
 config ARCH_MX3
         bool "MX3-based"
         select CPU_V6
+        select COMMON_CLKDEV
         help
           This enables support for systems based on the Freescale i.MX3 family
 
@@ -43,4 +45,10 @@ config MXC_IRQ_PRIOR
           requirements for timing.
           Say N here, unless you have a specialized requirement.
 
+config MXC_PWM
+        tristate "Enable PWM driver"
+        depends on ARCH_MXC
+        help
+          Enable support for the i.MX PWM controller(s).
+
 endif
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index db74a929179d..055406312b69 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -3,7 +3,8 @@
 #
 
 # Common support
-obj-y := irq.o clock.o gpio.o time.o devices.o
+obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o
 
 obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o
 obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o
+obj-$(CONFIG_MXC_PWM)  += pwm.o
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 0a38f0b396eb..92e13566cd4f 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -48,6 +48,11 @@ static DEFINE_MUTEX(clocks_mutex);
  *-------------------------------------------------------------------------*/
 
 /*
+ * All the code inside #ifndef CONFIG_COMMON_CLKDEV can be removed once all
+ * MXC architectures have switched to using clkdev.
+ */
+#ifndef CONFIG_COMMON_CLKDEV
+/*
  * Retrieve a clock by name.
  *
  * Note that we first try to use device id on the bus
@@ -110,6 +115,7 @@ found:
         return clk;
 }
 EXPORT_SYMBOL(clk_get);
+#endif
 
 static void __clk_disable(struct clk *clk)
 {
@@ -187,6 +193,7 @@ unsigned long clk_get_rate(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_rate);
 
+#ifndef CONFIG_COMMON_CLKDEV
 /* Decrement the clock's module reference count */
 void clk_put(struct clk *clk)
 {
@@ -194,6 +201,7 @@ void clk_put(struct clk *clk)
                 module_put(clk->owner);
 }
 EXPORT_SYMBOL(clk_put);
+#endif
 
 /* Round the requested clock rate to the nearest supported
  * rate that is less than or equal to the requested rate.
@@ -257,6 +265,7 @@ struct clk *clk_get_parent(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_parent);
 
+#ifndef CONFIG_COMMON_CLKDEV
 /*
  * Add a new clock to the clock tree.
  */
@@ -327,4 +336,49 @@ static int __init mxc_setup_proc_entry(void)
 }
 
 late_initcall(mxc_setup_proc_entry);
+#endif /* CONFIG_PROC_FS */
+#endif
+
+/*
+ * Get the resulting clock rate from a PLL register value and the input
+ * frequency. PLLs with this register layout can at least be found on
+ * MX1, MX21, MX27 and MX31
+ *
+ *                  mfi + mfn / (mfd + 1)
+ *  f = 2 * f_ref * --------------------
+ *                        pd + 1
+ */
+unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
+{
+        long long ll;
+        int mfn_abs;
+        unsigned int mfi, mfn, mfd, pd;
+
+        mfi = (reg_val >> 10) & 0xf;
+        mfn = reg_val & 0x3ff;
+        mfd = (reg_val >> 16) & 0x3ff;
+        pd =  (reg_val >> 26) & 0xf;
+
+        mfi = mfi <= 5 ? 5 : mfi;
+
+        mfn_abs = mfn;
+
+#if !defined CONFIG_ARCH_MX1 && !defined CONFIG_ARCH_MX21
+        if (mfn >= 0x200) {
+                mfn |= 0xFFFFFE00;
+                mfn_abs = -mfn;
+        }
 #endif
+
+        freq *= 2;
+        freq /= pd + 1;
+
+        ll = (unsigned long long)freq * mfn_abs;
+
+        do_div(ll, mfd + 1);
+        if (mfn < 0)
+                ll = -ll;
+        ll = (freq * mfi) + ll;
+
+        return ll;
+}
diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/plat-mxc/cpu.c
new file mode 100644
index 000000000000..386e0d52cf58
--- /dev/null
+++ b/arch/arm/plat-mxc/cpu.c
@@ -0,0 +1,11 @@
+
+#include <linux/module.h>
+
+unsigned int __mxc_cpu_type;
+EXPORT_SYMBOL(__mxc_cpu_type);
+
+void mxc_set_cpu_type(unsigned int type)
+{
+        __mxc_cpu_type = type;
+}
+
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
index c66748267c45..56f2fb5cc456 100644
--- a/arch/arm/plat-mxc/devices.c
+++ b/arch/arm/plat-mxc/devices.c
@@ -19,6 +19,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <mach/common.h>
 
 int __init mxc_register_device(struct platform_device *pdev, void *data)
 {
diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c
index 2905ec758758..e364a5ed10f1 100644
--- a/arch/arm/plat-mxc/dma-mx1-mx2.c
+++ b/arch/arm/plat-mxc/dma-mx1-mx2.c
@@ -113,7 +113,7 @@ struct imx_dma_channel {
         void (*err_handler) (int, void *, int errcode);
         void (*prog_handler) (int, void *, struct scatterlist *);
         void *data;
-        unsigned int  dma_mode;
+        unsigned int dma_mode;
         struct scatterlist *sg;
         unsigned int resbytes;
         int dma_num;
@@ -802,7 +802,7 @@ static int __init imx_dma_init(void)
         int ret = 0;
         int i;
 
-        dma_clk = clk_get(NULL, "dma_clk");
+        dma_clk = clk_get(NULL, "dma");
         clk_enable(dma_clk);
 
         /* reset DMA module */
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index ccbd94adc668..c6483bad8a26 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -200,8 +200,8 @@ static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 static int mxc_gpio_direction_output(struct gpio_chip *chip,
                                      unsigned offset, int value)
 {
-        _set_gpio_direction(chip, offset, 1);
         mxc_gpio_set(chip, offset, value);
+        _set_gpio_direction(chip, offset, 1);
         return 0;
 }
 
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
index 8f34a05afc87..1cac9d1135cd 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
@@ -48,7 +48,8 @@
  * Base address of PBC controller, CS4
  */
 #define PBC_BASE_ADDRESS        0xEB000000
-#define PBC_REG_ADDR(offset)    (PBC_BASE_ADDRESS + (offset))
+#define PBC_REG_ADDR(offset)    (void __force __iomem *) \
+                (PBC_BASE_ADDRESS + (offset))
 
 /*
  * PBC Interupt name definitions
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
index 451d510d08c3..318c72ada13d 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
 #define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
 
+#include <mach/hardware.h>
+
 /* Base address of PBC controller */
 #define PBC_BASE_ADDRESS        IO_ADDRESS(CS4_BASE_ADDR)
 /* Offsets for the PBC Controller register */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
new file mode 100644
index 000000000000..f8aef1babb75
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
+#define __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
+
+/* mandatory for CONFIG_LL_DEBUG */
+
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       (AIPI_BASE_ADDR_VIRT + 0x0A000)
+
+#ifndef __ASSEMBLY__
+
+enum mx31moboard_boards {
+        MX31NOBOARD     = 0,
+        MX31DEVBOARD    = 1,
+        MX31MARXBOT     = 2,
+};
+
+/*
+ * This CPU module needs a baseboard to work. After basic initializing
+ * its own devices, it calls baseboard's init function.
+ */
+
+extern void mx31moboard_devboard_init(void);
+extern void mx31moboard_marxbot_init(void);
+
+#endif
+
+#endif /* __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-qong.h b/arch/arm/plat-mxc/include/mach/board-qong.h
new file mode 100644
index 000000000000..4ff762dd45cf
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-qong.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_QONG_H__
+#define __ASM_ARCH_MXC_BOARD_QONG_H__
+
+/* mandatory for CONFIG_LL_DEBUG */
+
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+
+/* NOR FLASH */
+#define QONG_NOR_SIZE           (128*1024*1024)
+
+#endif /* __ASM_ARCH_MXC_BOARD_QONG_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/clkdev.h b/arch/arm/plat-mxc/include/mach/clkdev.h
new file mode 100644
index 000000000000..04b37a89801c
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
index d21f78e78819..43a82d0c534d 100644
--- a/arch/arm/plat-mxc/include/mach/clock.h
+++ b/arch/arm/plat-mxc/include/mach/clock.h
@@ -26,9 +26,13 @@
 struct module;
 
 struct clk {
+#ifndef CONFIG_COMMON_CLKDEV
+        /* As soon as i.MX1 and i.MX31 switched to clkdev, this
+         * block can go away */
         struct list_head node;
         struct module *owner;
         const char *name;
+#endif
         int id;
         /* Source clock this clk depends on */
         struct clk *parent;
@@ -63,5 +67,7 @@ struct clk {
 int clk_register(struct clk *clk);
 void clk_unregister(struct clk *clk);
 
+unsigned long mxc_decode_pll(unsigned int pll, u32 f_ref);
+
 #endif /* __ASSEMBLY__ */
 #endif /* __ASM_ARCH_MXC_CLOCK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 6350287a59b9..b2f9b72644db 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -12,12 +12,18 @@
 #define __ASM_ARCH_MXC_COMMON_H__
 
 struct platform_device;
+struct clk;
 
 extern void mxc_map_io(void);
 extern void mxc_init_irq(void);
-extern void mxc_timer_init(const char *clk_timer);
-extern int mxc_clocks_init(unsigned long fref);
+extern void mxc_timer_init(struct clk *timer_clk);
+extern int mx1_clocks_init(unsigned long fref);
+extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
+extern int mx27_clocks_init(unsigned long fref);
+extern int mx31_clocks_init(unsigned long fref);
+extern int mx35_clocks_init(void);
 extern int mxc_register_gpios(void);
 extern int mxc_register_device(struct platform_device *pdev, void *data);
+extern void mxc_set_cpu_type(unsigned int type);
 
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 602768b427e2..4f773148bc20 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -31,6 +31,9 @@
 #ifdef CONFIG_MACH_MX31_3DS
 #include <mach/board-mx31pdk.h>
 #endif
+#ifdef CONFIG_MACH_QONG
+#include <mach/board-qong.h>
+#endif
                 .macro  addruart,rx
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index a612d8bb73c8..42e4ee37ca1f 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -23,10 +23,16 @@
 #include <asm/sizes.h>
 
 #ifdef CONFIG_ARCH_MX3
-# include <mach/mx31.h>
+#include <mach/mx3x.h>
+#include <mach/mx31.h>
+#include <mach/mx35.h>
 #endif
 
 #ifdef CONFIG_ARCH_MX2
+# include <mach/mx2x.h>
+# ifdef CONFIG_MACH_MX21
+#  include <mach/mx21.h>
+# endif
 # ifdef CONFIG_MACH_MX27
 #  include <mach/mx27.h>
 # endif
diff --git a/arch/arm/mach-imx/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h
index 870d0d939616..762a7b0430e2 100644
--- a/arch/arm/mach-imx/include/mach/imxfb.h
+++ b/arch/arm/plat-mxc/include/mach/imxfb.h
@@ -76,6 +76,9 @@ struct imx_fb_platform_data {
         u_char * fixed_screen_cpu;
         dma_addr_t fixed_screen_dma;
 
+        int (*init)(struct platform_device*);
+        int (*exit)(struct platform_device*);
+
         void (*lcd_power)(int);
         void (*backlight_power)(int);
 };
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
deleted file mode 100644
index 95a383be628e..000000000000
--- a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
+++ /dev/null
@@ -1,416 +0,0 @@
-/*
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef _MXC_GPIO_MX1_MX2_H
-#define _MXC_GPIO_MX1_MX2_H
-
-#include <linux/io.h>
-
-/*
- *  GPIO Module and I/O Multiplexer
- *  x = 0..3 for reg_A, reg_B, reg_C, reg_D
- */
-#define VA_GPIO_BASE    IO_ADDRESS(GPIO_BASE_ADDR)
-#define MXC_DDIR(x)    (0x00 + ((x) << 8))
-#define MXC_OCR1(x)    (0x04 + ((x) << 8))
-#define MXC_OCR2(x)    (0x08 + ((x) << 8))
-#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
-#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
-#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
-#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
-#define MXC_DR(x)      (0x1c + ((x) << 8))
-#define MXC_GIUS(x)    (0x20 + ((x) << 8))
-#define MXC_SSR(x)     (0x24 + ((x) << 8))
-#define MXC_ICR1(x)    (0x28 + ((x) << 8))
-#define MXC_ICR2(x)    (0x2c + ((x) << 8))
-#define MXC_IMR(x)     (0x30 + ((x) << 8))
-#define MXC_ISR(x)     (0x34 + ((x) << 8))
-#define MXC_GPR(x)     (0x38 + ((x) << 8))
-#define MXC_SWR(x)     (0x3c + ((x) << 8))
-#define MXC_PUEN(x)    (0x40 + ((x) << 8))
-
-#ifdef CONFIG_ARCH_MX1
-# define GPIO_PORT_MAX  3
-#endif
-#ifdef CONFIG_ARCH_MX2
-# define GPIO_PORT_MAX  5
-#endif
-
-#ifndef GPIO_PORT_MAX
-# error "GPIO config port count unknown!"
-#endif
-
-#define GPIO_PIN_MASK 0x1f
-
-#define GPIO_PORT_SHIFT 5
-#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
-
-#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
-#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
-#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
-#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
-#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
-#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
-
-#define GPIO_OUT   (1 << 8)
-#define GPIO_IN    (0 << 8)
-#define GPIO_PUEN  (1 << 9)
-
-#define GPIO_PF    (1 << 10)
-#define GPIO_AF    (1 << 11)
-
-#define GPIO_OCR_SHIFT 12
-#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
-#define GPIO_AIN   (0 << GPIO_OCR_SHIFT)
-#define GPIO_BIN   (1 << GPIO_OCR_SHIFT)
-#define GPIO_CIN   (2 << GPIO_OCR_SHIFT)
-#define GPIO_GPIO  (3 << GPIO_OCR_SHIFT)
-
-#define GPIO_AOUT_SHIFT 14
-#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT     (0 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT_0   (2 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT_1   (3 << GPIO_AOUT_SHIFT)
-
-#define GPIO_BOUT_SHIFT 16
-#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT      (0 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT_ISR  (1 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT_0    (2 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT_1    (3 << GPIO_BOUT_SHIFT)
-
-extern void mxc_gpio_mode(int gpio_mode);
-extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
-                                        const char *label);
-extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
-
-/*-------------------------------------------------------------------------*/
-
-/* assignements for GPIO alternate/primary functions */
-
-/* FIXME: This list is not completed. The correct directions are
- * missing on some (many) pins
- */
-#ifdef CONFIG_ARCH_MX1
-#define PA0_AIN_SPI2_CLK     (GPIO_PORTA | GPIO_OUT | 0)
-#define PA0_AF_ETMTRACESYNC  (GPIO_PORTA | GPIO_AF | 0)
-#define PA1_AOUT_SPI2_RXD    (GPIO_PORTA | GPIO_IN | 1)
-#define PA1_PF_TIN           (GPIO_PORTA | GPIO_PF | 1)
-#define PA2_PF_PWM0          (GPIO_PORTA | GPIO_OUT | GPIO_PF | 2)
-#define PA3_PF_CSI_MCLK      (GPIO_PORTA | GPIO_PF | 3)
-#define PA4_PF_CSI_D0        (GPIO_PORTA | GPIO_PF | 4)
-#define PA5_PF_CSI_D1        (GPIO_PORTA | GPIO_PF | 5)
-#define PA6_PF_CSI_D2        (GPIO_PORTA | GPIO_PF | 6)
-#define PA7_PF_CSI_D3        (GPIO_PORTA | GPIO_PF | 7)
-#define PA8_PF_CSI_D4        (GPIO_PORTA | GPIO_PF | 8)
-#define PA9_PF_CSI_D5        (GPIO_PORTA | GPIO_PF | 9)
-#define PA10_PF_CSI_D6       (GPIO_PORTA | GPIO_PF | 10)
-#define PA11_PF_CSI_D7       (GPIO_PORTA | GPIO_PF | 11)
-#define PA12_PF_CSI_VSYNC    (GPIO_PORTA | GPIO_PF | 12)
-#define PA13_PF_CSI_HSYNC    (GPIO_PORTA | GPIO_PF | 13)
-#define PA14_PF_CSI_PIXCLK   (GPIO_PORTA | GPIO_PF | 14)
-#define PA15_PF_I2C_SDA      (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15)
-#define PA16_PF_I2C_SCL      (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16)
-#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17)
-#define PA17_AIN_SPI2_SS     (GPIO_PORTA | GPIO_OUT | 17)
-#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18)
-#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19)
-#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20)
-#define PA21_PF_A0           (GPIO_PORTA | GPIO_PF | 21)
-#define PA22_PF_CS4          (GPIO_PORTA | GPIO_PF | 22)
-#define PA23_PF_CS5          (GPIO_PORTA | GPIO_PF | 23)
-#define PA24_PF_A16          (GPIO_PORTA | GPIO_PF | 24)
-#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24)
-#define PA25_PF_A17          (GPIO_PORTA | GPIO_PF | 25)
-#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25)
-#define PA26_PF_A18          (GPIO_PORTA | GPIO_PF | 26)
-#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26)
-#define PA27_PF_A19          (GPIO_PORTA | GPIO_PF | 27)
-#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27)
-#define PA28_PF_A20          (GPIO_PORTA | GPIO_PF | 28)
-#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28)
-#define PA29_PF_A21          (GPIO_PORTA | GPIO_PF | 29)
-#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29)
-#define PA30_PF_A22          (GPIO_PORTA | GPIO_PF | 30)
-#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30)
-#define PA31_PF_A23          (GPIO_PORTA | GPIO_PF | 31)
-#define PA31_AF_ETMTRACECLK  (GPIO_PORTA | GPIO_AF | 31)
-#define PB8_PF_SD_DAT0       (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8)
-#define PB8_AF_MS_PIO        (GPIO_PORTB | GPIO_AF | 8)
-#define PB9_PF_SD_DAT1       (GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 9)
-#define PB9_AF_MS_PI1        (GPIO_PORTB | GPIO_AF | 9)
-#define PB10_PF_SD_DAT2      (GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 10)
-#define PB10_AF_MS_SCLKI     (GPIO_PORTB | GPIO_AF | 10)
-#define PB11_PF_SD_DAT3      (GPIO_PORTB | GPIO_PF | 11)
-#define PB11_AF_MS_SDIO      (GPIO_PORTB | GPIO_AF | 11)
-#define PB12_PF_SD_CLK       (GPIO_PORTB | GPIO_PF | 12)
-#define PB12_AF_MS_SCLK0     (GPIO_PORTB | GPIO_AF | 12)
-#define PB13_PF_SD_CMD       (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13)
-#define PB13_AF_MS_BS        (GPIO_PORTB | GPIO_AF | 13)
-#define PB14_AF_SSI_RXFS     (GPIO_PORTB | GPIO_AF | 14)
-#define PB15_AF_SSI_RXCLK    (GPIO_PORTB | GPIO_AF | 15)
-#define PB16_AF_SSI_RXDAT    (GPIO_PORTB | GPIO_IN | GPIO_AF | 16)
-#define PB17_AF_SSI_TXDAT    (GPIO_PORTB | GPIO_OUT | GPIO_AF | 17)
-#define PB18_AF_SSI_TXFS     (GPIO_PORTB | GPIO_AF | 18)
-#define PB19_AF_SSI_TXCLK    (GPIO_PORTB | GPIO_AF | 19)
-#define PB20_PF_USBD_AFE     (GPIO_PORTB | GPIO_PF | 20)
-#define PB21_PF_USBD_OE      (GPIO_PORTB | GPIO_PF | 21)
-#define PB22_PFUSBD_RCV      (GPIO_PORTB | GPIO_PF | 22)
-#define PB23_PF_USBD_SUSPND  (GPIO_PORTB | GPIO_PF | 23)
-#define PB24_PF_USBD_VP      (GPIO_PORTB | GPIO_PF | 24)
-#define PB25_PF_USBD_VM      (GPIO_PORTB | GPIO_PF | 25)
-#define PB26_PF_USBD_VPO     (GPIO_PORTB | GPIO_PF | 26)
-#define PB27_PF_USBD_VMO     (GPIO_PORTB | GPIO_PF | 27)
-#define PB28_PF_UART2_CTS    (GPIO_PORTB | GPIO_OUT | GPIO_PF | 28)
-#define PB29_PF_UART2_RTS    (GPIO_PORTB | GPIO_IN | GPIO_PF | 29)
-#define PB30_PF_UART2_TXD    (GPIO_PORTB | GPIO_OUT | GPIO_PF | 30)
-#define PB31_PF_UART2_RXD    (GPIO_PORTB | GPIO_IN | GPIO_PF | 31)
-#define PC3_PF_SSI_RXFS      (GPIO_PORTC | GPIO_PF | 3)
-#define PC4_PF_SSI_RXCLK     (GPIO_PORTC | GPIO_PF | 4)
-#define PC5_PF_SSI_RXDAT     (GPIO_PORTC | GPIO_IN | GPIO_PF | 5)
-#define PC6_PF_SSI_TXDAT     (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
-#define PC7_PF_SSI_TXFS      (GPIO_PORTC | GPIO_PF | 7)
-#define PC8_PF_SSI_TXCLK     (GPIO_PORTC | GPIO_PF | 8)
-#define PC9_PF_UART1_CTS     (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
-#define PC10_PF_UART1_RTS    (GPIO_PORTC | GPIO_IN | GPIO_PF | 10)
-#define PC11_PF_UART1_TXD    (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
-#define PC12_PF_UART1_RXD    (GPIO_PORTC | GPIO_IN | GPIO_PF | 12)
-#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13)
-#define PC14_PF_SPI1_SCLK    (GPIO_PORTC | GPIO_PF | 14)
-#define PC15_PF_SPI1_SS      (GPIO_PORTC | GPIO_PF | 15)
-#define PC16_PF_SPI1_MISO    (GPIO_PORTC | GPIO_PF | 16)
-#define PC17_PF_SPI1_MOSI    (GPIO_PORTC | GPIO_PF | 17)
-#define PC24_BIN_UART3_RI    (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24)
-#define PC25_BIN_UART3_DSR   (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25)
-#define PC26_AOUT_UART3_DTR  (GPIO_PORTC | GPIO_IN | 26)
-#define PC27_BIN_UART3_DCD   (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27)
-#define PC28_BIN_UART3_CTS   (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28)
-#define PC29_AOUT_UART3_RTS  (GPIO_PORTC | GPIO_IN | 29)
-#define PC30_BIN_UART3_TX    (GPIO_PORTC | GPIO_BIN | 30)
-#define PC31_AOUT_UART3_RX   (GPIO_PORTC | GPIO_IN | 31)
-#define PD6_PF_LSCLK         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 6)
-#define PD7_PF_REV           (GPIO_PORTD | GPIO_PF | 7)
-#define PD7_AF_UART2_DTR     (GPIO_PORTD | GPIO_IN | GPIO_AF | 7)
-#define PD7_AIN_SPI2_SCLK    (GPIO_PORTD | GPIO_AIN | 7)
-#define PD8_PF_CLS           (GPIO_PORTD | GPIO_PF | 8)
-#define PD8_AF_UART2_DCD     (GPIO_PORTD | GPIO_OUT | GPIO_AF | 8)
-#define PD8_AIN_SPI2_SS      (GPIO_PORTD | GPIO_AIN | 8)
-#define PD9_PF_PS            (GPIO_PORTD | GPIO_PF | 9)
-#define PD9_AF_UART2_RI      (GPIO_PORTD | GPIO_OUT | GPIO_AF | 9)
-#define PD9_AOUT_SPI2_RXD    (GPIO_PORTD | GPIO_IN | 9)
-#define PD10_PF_SPL_SPR      (GPIO_PORTD | GPIO_OUT | GPIO_PF | 10)
-#define PD10_AF_UART2_DSR    (GPIO_PORTD | GPIO_OUT | GPIO_AF | 10)
-#define PD10_AIN_SPI2_TXD    (GPIO_PORTD | GPIO_OUT | 10)
-#define PD11_PF_CONTRAST     (GPIO_PORTD | GPIO_OUT | GPIO_PF | 11)
-#define PD12_PF_ACD_OE       (GPIO_PORTD | GPIO_OUT | GPIO_PF | 12)
-#define PD13_PF_LP_HSYNC     (GPIO_PORTD | GPIO_OUT | GPIO_PF | 13)
-#define PD14_PF_FLM_VSYNC    (GPIO_PORTD | GPIO_OUT | GPIO_PF | 14)
-#define PD15_PF_LD0          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 15)
-#define PD16_PF_LD1          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 16)
-#define PD17_PF_LD2          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
-#define PD18_PF_LD3          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
-#define PD19_PF_LD4          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 19)
-#define PD20_PF_LD5          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 20)
-#define PD21_PF_LD6          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 21)
-#define PD22_PF_LD7          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 22)
-#define PD23_PF_LD8          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 23)
-#define PD24_PF_LD9          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 24)
-#define PD25_PF_LD10         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25)
-#define PD26_PF_LD11         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26)
-#define PD27_PF_LD12         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27)
-#define PD28_PF_LD13         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28)
-#define PD29_PF_LD14         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29)
-#define PD30_PF_LD15         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 30)
-#define PD31_PF_TMR2OUT      (GPIO_PORTD | GPIO_PF | 31)
-#define PD31_BIN_SPI2_TXD    (GPIO_PORTD | GPIO_BIN | 31)
-#endif
-
-#ifdef CONFIG_ARCH_MX2
-#define PA0_PF_USBH2_CLK        (GPIO_PORTA | GPIO_PF | 0)
-#define PA1_PF_USBH2_DIR        (GPIO_PORTA | GPIO_PF | 1)
-#define PA2_PF_USBH2_DATA7      (GPIO_PORTA | GPIO_PF | 2)
-#define PA3_PF_USBH2_NXT        (GPIO_PORTA | GPIO_PF | 3)
-#define PA4_PF_USBH2_STP        (GPIO_PORTA | GPIO_PF | 4)
-#define PA5_PF_LSCLK            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 5)
-#define PA6_PF_LD0              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 6)
-#define PA7_PF_LD1              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 7)
-#define PA8_PF_LD2              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 8)
-#define PA9_PF_LD3              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 9)
-#define PA10_PF_LD4             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 10)
-#define PA11_PF_LD5             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 11)
-#define PA12_PF_LD6             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 12)
-#define PA13_PF_LD7             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 13)
-#define PA14_PF_LD8             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 14)
-#define PA15_PF_LD9             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15)
-#define PA16_PF_LD10            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16)
-#define PA17_PF_LD11            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 17)
-#define PA18_PF_LD12            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 18)
-#define PA19_PF_LD13            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 19)
-#define PA20_PF_LD14            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 20)
-#define PA21_PF_LD15            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 21)
-#define PA22_PF_LD16            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 22)
-#define PA23_PF_LD17            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 23)
-#define PA24_PF_REV             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 24)
-#define PA25_PF_CLS             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 25)
-#define PA26_PF_PS              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 26)
-#define PA27_PF_SPL_SPR         (GPIO_PORTA | GPIO_OUT | GPIO_PF | 27)
-#define PA28_PF_HSYNC           (GPIO_PORTA | GPIO_OUT | GPIO_PF | 28)
-#define PA29_PF_VSYNC           (GPIO_PORTA | GPIO_OUT | GPIO_PF | 29)
-#define PA30_PF_CONTRAST        (GPIO_PORTA | GPIO_OUT | GPIO_PF | 30)
-#define PA31_PF_OE_ACD          (GPIO_PORTA | GPIO_OUT | GPIO_PF | 31)
-#define PB4_PF_SD2_D0           (GPIO_PORTB | GPIO_PF |  4)
-#define PB5_PF_SD2_D1           (GPIO_PORTB | GPIO_PF |  5)
-#define PB6_PF_SD2_D2           (GPIO_PORTB | GPIO_PF |  6)
-#define PB7_PF_SD2_D3           (GPIO_PORTB | GPIO_PF |  7)
-#define PB8_PF_SD2_CMD          (GPIO_PORTB | GPIO_PF |  8)
-#define PB9_PF_SD2_CLK          (GPIO_PORTB | GPIO_PF |  9)
-#define PB10_PF_CSI_D0          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 10)
-#define PB10_AF_UART6_TXD       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 10)
-#define PB11_PF_CSI_D1          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 11)
-#define PB11_AF_UART6_RXD       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 11)
-#define PB12_PF_CSI_D2          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 12)
-#define PB12_AF_UART6_CTS       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 12)
-#define PB13_PF_CSI_D3          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 13)
-#define PB13_AF_UART6_RTS       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 13)
-#define PB14_PF_CSI_D4          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 14)
-#define PB15_PF_CSI_MCLK        (GPIO_PORTB | GPIO_OUT | GPIO_PF | 15)
-#define PB16_PF_CSI_PIXCLK      (GPIO_PORTB | GPIO_OUT | GPIO_PF | 16)
-#define PB17_PF_CSI_D5          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 17)
-#define PB18_PF_CSI_D6          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 18)
-#define PB18_AF_UART5_TXD       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 18)
-#define PB19_PF_CSI_D7          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 19)
-#define PB19_AF_UART5_RXD       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 19)
-#define PB20_PF_CSI_VSYNC       (GPIO_PORTB | GPIO_OUT | GPIO_PF | 20)
-#define PB20_AF_UART5_CTS       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 20)
-#define PB21_PF_CSI_HSYNC       (GPIO_PORTB | GPIO_OUT | GPIO_PF | 21)
-#define PB21_AF_UART5_RTS       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 21)
-#define PB22_PF_USBH1_SUSP      (GPIO_PORTB | GPIO_PF | 22)
-#define PB23_PF_USB_PWR         (GPIO_PORTB | GPIO_PF | 23)
-#define PB24_PF_USB_OC_B        (GPIO_PORTB | GPIO_PF | 24)
-#define PB25_PF_USBH1_RCV       (GPIO_PORTB | GPIO_PF | 25)
-#define PB26_PF_USBH1_FS        (GPIO_PORTB | GPIO_PF | 26)
-#define PB27_PF_USBH1_OE_B      (GPIO_PORTB | GPIO_PF | 27)
-#define PB28_PF_USBH1_TXDM      (GPIO_PORTB | GPIO_PF | 28)
-#define PB29_PF_USBH1_TXDP      (GPIO_PORTB | GPIO_PF | 29)
-#define PB30_PF_USBH1_RXDM      (GPIO_PORTB | GPIO_PF | 30)
-#define PB31_PF_USBH1_RXDP      (GPIO_PORTB | GPIO_PF | 31)
-#define PB26_AF_UART4_RTS       (GPIO_PORTB | GPIO_IN  | GPIO_PF | 26)
-#define PB28_AF_UART4_TXD       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 28)
-#define PB29_AF_UART4_CTS       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 29)
-#define PB31_AF_UART4_RXD       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 31)
-#define PC5_PF_I2C2_SDA         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 5)
-#define PC6_PF_I2C2_SCL         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 6)
-#define PC7_PF_USBOTG_DATA5     (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7)
-#define PC8_PF_USBOTG_DATA6     (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8)
-#define PC9_PF_USBOTG_DATA0     (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
-#define PC10_PF_USBOTG_DATA2    (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10)
-#define PC11_PF_USBOTG_DATA1    (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
-#define PC12_PF_USBOTG_DATA4    (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12)
-#define PC13_PF_USBOTG_DATA3    (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13)
-#define PC16_PF_SSI4_FS         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 16)
-#define PC17_PF_SSI4_RXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 17)
-#define PC18_PF_SSI4_TXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 18)
-#define PC19_PF_SSI4_CLK        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 19)
-#define PC20_PF_SSI1_FS         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 20)
-#define PC21_PF_SSI1_RXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 21)
-#define PC22_PF_SSI1_TXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 22)
-#define PC23_PF_SSI1_CLK        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 23)
-#define PC24_PF_SSI2_FS         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 24)
-#define PC25_PF_SSI2_RXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 25)
-#define PC26_PF_SSI2_TXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 26)
-#define PC27_PF_SSI2_CLK        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 27)
-#define PC28_PF_SSI3_FS         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 28)
-#define PC29_PF_SSI3_RXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 29)
-#define PC30_PF_SSI3_TXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 30)
-#define PC31_PF_SSI3_CLK        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 31)
-#define PD0_AIN_FEC_TXD0        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
-#define PD1_AIN_FEC_TXD1        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
-#define PD2_AIN_FEC_TXD2        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
-#define PD3_AIN_FEC_TXD3        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
-#define PD4_AOUT_FEC_RX_ER      (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
-#define PD5_AOUT_FEC_RXD1       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
-#define PD6_AOUT_FEC_RXD2       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
-#define PD7_AOUT_FEC_RXD3       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
-#define PD8_AF_FEC_MDIO         (GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
-#define PD9_AIN_FEC_MDC         (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
-#define PD10_AOUT_FEC_CRS       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
-#define PD11_AOUT_FEC_TX_CLK    (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
-#define PD12_AOUT_FEC_RXD0      (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
-#define PD13_AOUT_FEC_RX_DV     (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
-#define PD14_AOUT_FEC_CLR       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
-#define PD15_AOUT_FEC_COL       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
-#define PD16_AIN_FEC_TX_ER      (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
-#define PD17_PF_I2C_DATA        (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
-#define PD18_PF_I2C_CLK         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
-#define PD19_AF_USBH2_DATA4     (GPIO_PORTD | GPIO_AF | 19)
-#define PD20_AF_USBH2_DATA3     (GPIO_PORTD | GPIO_AF | 20)
-#define PD21_AF_USBH2_DATA6     (GPIO_PORTD | GPIO_AF | 21)
-#define PD22_AF_USBH2_DATA0     (GPIO_PORTD | GPIO_AF | 22)
-#define PD23_AF_USBH2_DATA2     (GPIO_PORTD | GPIO_AF | 23)
-#define PD24_AF_USBH2_DATA1     (GPIO_PORTD | GPIO_AF | 24)
-#define PD25_PF_CSPI1_RDY       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 25)
-#define PD26_PF_CSPI1_SS2       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 26)
-#define PD26_AF_USBH2_DATA5     (GPIO_PORTD | GPIO_AF | 26)
-#define PD27_PF_CSPI1_SS1       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 27)
-#define PD28_PF_CSPI1_SS0       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 28)
-#define PD29_PF_CSPI1_SCLK      (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 29)
-#define PD30_PF_CSPI1_MISO      (GPIO_PORTD | GPIO_IN | GPIO_PF  | 30)
-#define PD31_PF_CSPI1_MOSI      (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 31)
-#define PF23_AIN_FEC_TX_EN      (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
-#define PE0_PF_USBOTG_NXT       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0)
-#define PE1_PF_USBOTG_STP       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1)
-#define PE2_PF_USBOTG_DIR       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2)
-#define PE3_PF_UART2_CTS        (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
-#define PE4_PF_UART2_RTS        (GPIO_PORTE | GPIO_IN  | GPIO_PF | 4)
-#define PE6_PF_UART2_TXD        (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
-#define PE7_PF_UART2_RXD        (GPIO_PORTE | GPIO_IN  | GPIO_PF | 7)
-#define PE8_PF_UART3_TXD        (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
-#define PE9_PF_UART3_RXD        (GPIO_PORTE | GPIO_IN  | GPIO_PF | 9)
-#define PE10_PF_UART3_CTS       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
-#define PE11_PF_UART3_RTS       (GPIO_PORTE | GPIO_IN  | GPIO_PF | 11)
-#define PE12_PF_UART1_TXD       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
-#define PE13_PF_UART1_RXD       (GPIO_PORTE | GPIO_IN  | GPIO_PF | 13)
-#define PE14_PF_UART1_CTS       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
-#define PE15_PF_UART1_RTS       (GPIO_PORTE | GPIO_IN  | GPIO_PF | 15)
-#define PE16_AF_RTCK            (GPIO_PORTE | GPIO_OUT | GPIO_AF | 16)
-#define PE16_PF_RTCK            (GPIO_PORTE | GPIO_OUT | GPIO_PF | 16)
-#define PE18_PF_SDHC1_D0        (GPIO_PORTE | GPIO_PF | 18)
-#define PE18_AF_CSPI3_MISO      (GPIO_PORTE | GPIO_IN  | GPIO_AF | 18)
-#define PE19_PF_SDHC1_D1        (GPIO_PORTE | GPIO_PF | 19)
-#define PE20_PF_SDHC1_D2        (GPIO_PORTE | GPIO_PF | 20)
-#define PE21_PF_SDHC1_D3        (GPIO_PORTE | GPIO_PF | 21)
-#define PE21_AF_CSPI3_SS        (GPIO_PORTE | GPIO_OUT | GPIO_AF | 21)
-#define PE22_PF_SDHC1_CMD       (GPIO_PORTE | GPIO_PF | 22)
-#define PE22_AF_CSPI3_MOSI      (GPIO_PORTE | GPIO_OUT | GPIO_AF | 22)
-#define PE22_PF_SDHC1_CLK       (GPIO_PORTE | GPIO_PF | 23)
-#define PE23_AF_CSPI3_SCLK      (GPIO_PORTE | GPIO_OUT | GPIO_AF | 23)
-#define PE24_PF_USBOTG_CLK      (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24)
-#define PE25_PF_USBOTG_DATA7    (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25)
-#endif
-
-/* decode irq number to use with IMR(x), ISR(x) and friends */
-#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5)
-
-#define IRQ_GPIOA(x)  (MXC_GPIO_IRQ_START + x)
-#define IRQ_GPIOB(x)  (IRQ_GPIOA(32) + x)
-#define IRQ_GPIOC(x)  (IRQ_GPIOB(32) + x)
-#define IRQ_GPIOD(x)  (IRQ_GPIOC(32) + x)
-#define IRQ_GPIOE(x)  (IRQ_GPIOD(32) + x)
-
-#endif /* _MXC_GPIO_MX1_MX2_H */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1.h b/arch/arm/plat-mxc/include/mach/iomux-mx1.h
new file mode 100644
index 000000000000..bf23305c19cc
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx1.h
@@ -0,0 +1,166 @@
+/*
+* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License
+* as published by the Free Software Foundation; either version 2
+* of the License, or (at your option) any later version.
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+* MA 02110-1301, USA.
+*/
+
+#ifndef _MXC_IOMUX_MX1_H
+#define _MXC_IOMUX_MX1_H
+
+#ifndef GPIO_PORTA
+#error Please include mach/iomux.h
+#endif
+
+/* FIXME: This list is not completed. The correct directions are
+* missing on some (many) pins
+*/
+
+
+/* Primary GPIO pin functions */
+
+#define PA0_AIN_SPI2_CLK        (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
+#define PA0_AF_ETMTRACESYNC     (GPIO_PORTA | GPIO_AF | 0)
+#define PA1_AOUT_SPI2_RXD       (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 1)
+#define PA1_PF_TIN              (GPIO_PORTA | GPIO_PF | 1)
+#define PA2_PF_PWM0             (GPIO_PORTA | GPIO_PF | GPIO_OUT | 2)
+#define PA3_PF_CSI_MCLK         (GPIO_PORTA | GPIO_PF | 3)
+#define PA4_PF_CSI_D0           (GPIO_PORTA | GPIO_PF | 4)
+#define PA5_PF_CSI_D1           (GPIO_PORTA | GPIO_PF | 5)
+#define PA6_PF_CSI_D2           (GPIO_PORTA | GPIO_PF | 6)
+#define PA7_PF_CSI_D3           (GPIO_PORTA | GPIO_PF | 7)
+#define PA8_PF_CSI_D4           (GPIO_PORTA | GPIO_PF | 8)
+#define PA9_PF_CSI_D5           (GPIO_PORTA | GPIO_PF | 9)
+#define PA10_PF_CSI_D6          (GPIO_PORTA | GPIO_PF | 10)
+#define PA11_PF_CSI_D7          (GPIO_PORTA | GPIO_PF | 11)
+#define PA12_PF_CSI_VSYNC       (GPIO_PORTA | GPIO_PF | 12)
+#define PA13_PF_CSI_HSYNC       (GPIO_PORTA | GPIO_PF | 13)
+#define PA14_PF_CSI_PIXCLK      (GPIO_PORTA | GPIO_PF | 14)
+#define PA15_PF_I2C_SDA         (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
+#define PA16_PF_I2C_SCL         (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
+#define PA17_AF_ETMTRACEPKT4    (GPIO_PORTA | GPIO_AF | 17)
+#define PA17_AIN_SPI2_SS        (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17)
+#define PA18_AF_ETMTRACEPKT5    (GPIO_PORTA | GPIO_AF | 18)
+#define PA19_AF_ETMTRACEPKT6    (GPIO_PORTA | GPIO_AF | 19)
+#define PA20_AF_ETMTRACEPKT7    (GPIO_PORTA | GPIO_AF | 20)
+#define PA21_PF_A0              (GPIO_PORTA | GPIO_PF | 21)
+#define PA22_PF_CS4             (GPIO_PORTA | GPIO_PF | 22)
+#define PA23_PF_CS5             (GPIO_PORTA | GPIO_PF | 23)
+#define PA24_PF_A16             (GPIO_PORTA | GPIO_PF | 24)
+#define PA24_AF_ETMTRACEPKT0    (GPIO_PORTA | GPIO_AF | 24)
+#define PA25_PF_A17             (GPIO_PORTA | GPIO_PF | 25)
+#define PA25_AF_ETMTRACEPKT1    (GPIO_PORTA | GPIO_AF | 25)
+#define PA26_PF_A18             (GPIO_PORTA | GPIO_PF | 26)
+#define PA26_AF_ETMTRACEPKT2    (GPIO_PORTA | GPIO_AF | 26)
+#define PA27_PF_A19             (GPIO_PORTA | GPIO_PF | 27)
+#define PA27_AF_ETMTRACEPKT3    (GPIO_PORTA | GPIO_AF | 27)
+#define PA28_PF_A20             (GPIO_PORTA | GPIO_PF | 28)
+#define PA28_AF_ETMPIPESTAT0    (GPIO_PORTA | GPIO_AF | 28)
+#define PA29_PF_A21             (GPIO_PORTA | GPIO_PF | 29)
+#define PA29_AF_ETMPIPESTAT1    (GPIO_PORTA | GPIO_AF | 29)
+#define PA30_PF_A22             (GPIO_PORTA | GPIO_PF | 30)
+#define PA30_AF_ETMPIPESTAT2    (GPIO_PORTA | GPIO_AF | 30)
+#define PA31_PF_A23             (GPIO_PORTA | GPIO_PF | 31)
+#define PA31_AF_ETMTRACECLK     (GPIO_PORTA | GPIO_AF | 31)
+#define PB8_PF_SD_DAT0          (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8)
+#define PB8_AF_MS_PIO           (GPIO_PORTB | GPIO_AF | 8)
+#define PB9_PF_SD_DAT1          (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9)
+#define PB9_AF_MS_PI1           (GPIO_PORTB | GPIO_AF | 9)
+#define PB10_PF_SD_DAT2         (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10)
+#define PB10_AF_MS_SCLKI        (GPIO_PORTB | GPIO_AF | 10)
+#define PB11_PF_SD_DAT3         (GPIO_PORTB | GPIO_PF | 11)
+#define PB11_AF_MS_SDIO         (GPIO_PORTB | GPIO_AF | 11)
+#define PB12_PF_SD_CLK          (GPIO_PORTB | GPIO_PF | 12)
+#define PB12_AF_MS_SCLK0        (GPIO_PORTB | GPIO_AF | 12)
+#define PB13_PF_SD_CMD          (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13)
+#define PB13_AF_MS_BS           (GPIO_PORTB | GPIO_AF | 13)
+#define PB14_AF_SSI_RXFS        (GPIO_PORTB | GPIO_AF | 14)
+#define PB15_AF_SSI_RXCLK       (GPIO_PORTB | GPIO_AF | 15)
+#define PB16_AF_SSI_RXDAT       (GPIO_PORTB | GPIO_AF | GPIO_IN | 16)
+#define PB17_AF_SSI_TXDAT       (GPIO_PORTB | GPIO_AF | GPIO_OUT | 17)
+#define PB18_AF_SSI_TXFS        (GPIO_PORTB | GPIO_AF | 18)
+#define PB19_AF_SSI_TXCLK       (GPIO_PORTB | GPIO_AF | 19)
+#define PB20_PF_USBD_AFE        (GPIO_PORTB | GPIO_PF | 20)
+#define PB21_PF_USBD_OE         (GPIO_PORTB | GPIO_PF | 21)
+#define PB22_PF_USBD_RCV        (GPIO_PORTB | GPIO_PF | 22)
+#define PB23_PF_USBD_SUSPND     (GPIO_PORTB | GPIO_PF | 23)
+#define PB24_PF_USBD_VP         (GPIO_PORTB | GPIO_PF | 24)
+#define PB25_PF_USBD_VM         (GPIO_PORTB | GPIO_PF | 25)
+#define PB26_PF_USBD_VPO        (GPIO_PORTB | GPIO_PF | 26)
+#define PB27_PF_USBD_VMO        (GPIO_PORTB | GPIO_PF | 27)
+#define PB28_PF_UART2_CTS       (GPIO_PORTB | GPIO_PF | GPIO_OUT | 28)
+#define PB29_PF_UART2_RTS       (GPIO_PORTB | GPIO_PF | GPIO_IN | 29)
+#define PB30_PF_UART2_TXD       (GPIO_PORTB | GPIO_PF | GPIO_OUT | 30)
+#define PB31_PF_UART2_RXD       (GPIO_PORTB | GPIO_PF | GPIO_IN | 31)
+#define PC3_PF_SSI_RXFS         (GPIO_PORTC | GPIO_PF | 3)
+#define PC4_PF_SSI_RXCLK        (GPIO_PORTC | GPIO_PF | 4)
+#define PC5_PF_SSI_RXDAT        (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
+#define PC6_PF_SSI_TXDAT        (GPIO_PORTC | GPIO_PF | GPIO_OUT | 6)
+#define PC7_PF_SSI_TXFS         (GPIO_PORTC | GPIO_PF | 7)
+#define PC8_PF_SSI_TXCLK        (GPIO_PORTC | GPIO_PF | 8)
+#define PC9_PF_UART1_CTS        (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
+#define PC10_PF_UART1_RTS       (GPIO_PORTC | GPIO_PF | GPIO_IN | 10)
+#define PC11_PF_UART1_TXD       (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
+#define PC12_PF_UART1_RXD       (GPIO_PORTC | GPIO_PF | GPIO_IN | 12)
+#define PC13_PF_SPI1_SPI_RDY    (GPIO_PORTC | GPIO_PF | 13)
+#define PC14_PF_SPI1_SCLK       (GPIO_PORTC | GPIO_PF | 14)
+#define PC15_PF_SPI1_SS         (GPIO_PORTC | GPIO_PF | 15)
+#define PC16_PF_SPI1_MISO       (GPIO_PORTC | GPIO_PF | 16)
+#define PC17_PF_SPI1_MOSI       (GPIO_PORTC | GPIO_PF | 17)
+#define PC24_BIN_UART3_RI       (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 24)
+#define PC25_BIN_UART3_DSR      (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 25)
+#define PC26_AOUT_UART3_DTR     (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 26)
+#define PC27_BIN_UART3_DCD      (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 27)
+#define PC28_BIN_UART3_CTS      (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 28)
+#define PC29_AOUT_UART3_RTS     (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 29)
+#define PC30_BIN_UART3_TX       (GPIO_PORTC | GPIO_BIN | 30)
+#define PC31_AOUT_UART3_RX      (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 31)
+#define PD6_PF_LSCLK            (GPIO_PORTD | GPIO_PF | GPIO_OUT | 6)
+#define PD7_PF_REV              (GPIO_PORTD | GPIO_PF | 7)
+#define PD7_AF_UART2_DTR        (GPIO_PORTD | GPIO_AF | GPIO_IN | 7)
+#define PD7_AIN_SPI2_SCLK       (GPIO_PORTD | GPIO_AIN | 7)
+#define PD8_PF_CLS              (GPIO_PORTD | GPIO_PF | 8)
+#define PD8_AF_UART2_DCD        (GPIO_PORTD | GPIO_AF | GPIO_OUT | 8)
+#define PD8_AIN_SPI2_SS         (GPIO_PORTD | GPIO_AIN | 8)
+#define PD9_PF_PS               (GPIO_PORTD | GPIO_PF | 9)
+#define PD9_AF_UART2_RI         (GPIO_PORTD | GPIO_AF | GPIO_OUT | 9)
+#define PD9_AOUT_SPI2_RXD       (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 9)
+#define PD10_PF_SPL_SPR         (GPIO_PORTD | GPIO_PF | GPIO_OUT | 10)
+#define PD10_AF_UART2_DSR       (GPIO_PORTD | GPIO_AF | GPIO_OUT | 10)
+#define PD10_AIN_SPI2_TXD       (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 10)
+#define PD11_PF_CONTRAST        (GPIO_PORTD | GPIO_PF | GPIO_OUT | 11)
+#define PD12_PF_ACD_OE          (GPIO_PORTD | GPIO_PF | GPIO_OUT | 12)
+#define PD13_PF_LP_HSYNC        (GPIO_PORTD | GPIO_PF | GPIO_OUT | 13)
+#define PD14_PF_FLM_VSYNC       (GPIO_PORTD | GPIO_PF | GPIO_OUT | 14)
+#define PD15_PF_LD0             (GPIO_PORTD | GPIO_PF | GPIO_OUT | 15)
+#define PD16_PF_LD1             (GPIO_PORTD | GPIO_PF | GPIO_OUT | 16)
+#define PD17_PF_LD2             (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
+#define PD18_PF_LD3             (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
+#define PD19_PF_LD4             (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19)
+#define PD20_PF_LD5             (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20)
+#define PD21_PF_LD6             (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21)
+#define PD22_PF_LD7             (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22)
+#define PD23_PF_LD8             (GPIO_PORTD | GPIO_PF | GPIO_OUT | 23)
+#define PD24_PF_LD9             (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24)
+#define PD25_PF_LD10            (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
+#define PD26_PF_LD11            (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
+#define PD27_PF_LD12            (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
+#define PD28_PF_LD13            (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28)
+#define PD29_PF_LD14            (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29)
+#define PD30_PF_LD15            (GPIO_PORTD | GPIO_PF | GPIO_OUT | 30)
+#define PD31_PF_TMR2OUT         (GPIO_PORTD | GPIO_PF | 31)
+#define PD31_BIN_SPI2_TXD       (GPIO_PORTD | GPIO_BIN | 31)
+
+
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx21.h b/arch/arm/plat-mxc/include/mach/iomux-mx21.h
new file mode 100644
index 000000000000..63aaa972e275
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx21.h
@@ -0,0 +1,126 @@
+/*
+* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License
+* as published by the Free Software Foundation; either version 2
+* of the License, or (at your option) any later version.
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+* MA 02110-1301, USA.
+*/
+
+#ifndef _MXC_IOMUX_MX21_H
+#define _MXC_IOMUX_MX21_H
+
+#ifndef GPIO_PORTA
+#error Please include mach/iomux.h
+#endif
+
+
+/* Primary GPIO pin functions */
+
+#define PB22_PF_USBH1_BYP       (GPIO_PORTB | GPIO_PF | 22)
+#define PB25_PF_USBH1_ON        (GPIO_PORTB | GPIO_PF | 25)
+#define PC5_PF_USBOTG_SDA       (GPIO_PORTC | GPIO_PF | 5)
+#define PC6_PF_USBOTG_SCL       (GPIO_PORTC | GPIO_PF | 6)
+#define PC7_PF_USBOTG_ON        (GPIO_PORTC | GPIO_PF | 7)
+#define PC8_PF_USBOTG_FS        (GPIO_PORTC | GPIO_PF | 8)
+#define PC9_PF_USBOTG_OE        (GPIO_PORTC | GPIO_PF | 9)
+#define PC10_PF_USBOTG_TXDM     (GPIO_PORTC | GPIO_PF | 10)
+#define PC11_PF_USBOTG_TXDP     (GPIO_PORTC | GPIO_PF | 11)
+#define PC12_PF_USBOTG_RXDM     (GPIO_PORTC | GPIO_PF | 12)
+#define PC13_PF_USBOTG_RXDP     (GPIO_PORTC | GPIO_PF | 13)
+#define PC16_PF_SAP_FS          (GPIO_PORTC | GPIO_PF | 16)
+#define PC17_PF_SAP_RXD         (GPIO_PORTC | GPIO_PF | 17)
+#define PC18_PF_SAP_TXD         (GPIO_PORTC | GPIO_PF | 18)
+#define PC19_PF_SAP_CLK         (GPIO_PORTC | GPIO_PF | 19)
+#define PE0_PF_TEST_WB2         (GPIO_PORTE | GPIO_PF | 0)
+#define PE1_PF_TEST_WB1         (GPIO_PORTE | GPIO_PF | 1)
+#define PE2_PF_TEST_WB0         (GPIO_PORTE | GPIO_PF | 2)
+#define PF1_PF_NFCE             (GPIO_PORTF | GPIO_PF | 1)
+#define PF3_PF_NFCLE            (GPIO_PORTF | GPIO_PF | 3)
+#define PF7_PF_NFIO0            (GPIO_PORTF | GPIO_PF | 7)
+#define PF8_PF_NFIO1            (GPIO_PORTF | GPIO_PF | 8)
+#define PF9_PF_NFIO2            (GPIO_PORTF | GPIO_PF | 9)
+#define PF10_PF_NFIO3           (GPIO_PORTF | GPIO_PF | 10)
+#define PF11_PF_NFIO4           (GPIO_PORTF | GPIO_PF | 11)
+#define PF12_PF_NFIO5           (GPIO_PORTF | GPIO_PF | 12)
+#define PF13_PF_NFIO6           (GPIO_PORTF | GPIO_PF | 13)
+#define PF14_PF_NFIO7           (GPIO_PORTF | GPIO_PF | 14)
+#define PF16_PF_RES             (GPIO_PORTF | GPIO_PF | 16)
+
+/* Alternate GPIO pin functions */
+
+#define PA5_AF_BMI_CLK_CS       (GPIO_PORTA | GPIO_AF | 5)
+#define PA6_AF_BMI_D0           (GPIO_PORTA | GPIO_AF | 6)
+#define PA7_AF_BMI_D1           (GPIO_PORTA | GPIO_AF | 7)
+#define PA8_AF_BMI_D2           (GPIO_PORTA | GPIO_AF | 8)
+#define PA9_AF_BMI_D3           (GPIO_PORTA | GPIO_AF | 9)
+#define PA10_AF_BMI_D4          (GPIO_PORTA | GPIO_AF | 10)
+#define PA11_AF_BMI_D5          (GPIO_PORTA | GPIO_AF | 11)
+#define PA12_AF_BMI_D6          (GPIO_PORTA | GPIO_AF | 12)
+#define PA13_AF_BMI_D7          (GPIO_PORTA | GPIO_AF | 13)
+#define PA14_AF_BMI_D8          (GPIO_PORTA | GPIO_AF | 14)
+#define PA15_AF_BMI_D9          (GPIO_PORTA | GPIO_AF | 15)
+#define PA16_AF_BMI_D10         (GPIO_PORTA | GPIO_AF | 16)
+#define PA17_AF_BMI_D11         (GPIO_PORTA | GPIO_AF | 17)
+#define PA18_AF_BMI_D12         (GPIO_PORTA | GPIO_AF | 18)
+#define PA19_AF_BMI_D13         (GPIO_PORTA | GPIO_AF | 19)
+#define PA20_AF_BMI_D14         (GPIO_PORTA | GPIO_AF | 20)
+#define PA21_AF_BMI_D15         (GPIO_PORTA | GPIO_AF | 21)
+#define PA22_AF_BMI_READ_REQ    (GPIO_PORTA | GPIO_AF | 22)
+#define PA23_AF_BMI_WRITE       (GPIO_PORTA | GPIO_AF | 23)
+#define PA29_AF_BMI_RX_FULL     (GPIO_PORTA | GPIO_AF | 29)
+#define PA30_AF_BMI_READ        (GPIO_PORTA | GPIO_AF | 30)
+
+/* AIN GPIO pin functions */
+
+#define PC14_AIN_SYS_CLK        (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14)
+#define PD21_AIN_USBH2_FS       (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21)
+#define PD22_AIN_USBH2_OE       (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22)
+#define PD23_AIN_USBH2_TXDM     (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23)
+#define PD24_AIN_USBH2_TXDP     (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24)
+#define PE8_AIN_IR_TXD          (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8)
+#define PF0_AIN_PC_RST          (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0)
+#define PF1_AIN_PC_CE1          (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1)
+#define PF2_AIN_PC_CE2          (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2)
+#define PF3_AIN_PC_POE          (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3)
+#define PF4_AIN_PC_OE           (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4)
+#define PF5_AIN_PC_RW           (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5)
+
+/* BIN GPIO pin functions */
+
+#define PC14_BIN_SYS_CLK        (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14)
+#define PD27_BIN_EXT_DMA_GRANT  (GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27)
+
+/* CIN GPIO pin functions */
+
+#define PB26_CIN_USBH1_RXDAT    (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26)
+
+/* AOUT GPIO pin functions */
+
+#define PA29_AOUT_BMI_WAIT      (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29)
+#define PD19_AOUT_USBH2_RXDM    (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19)
+#define PD20_AOUT_USBH2_RXDP    (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20)
+#define PD25_AOUT_EXT_DMAREQ    (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25)
+#define PD26_AOUT_USBOTG_RXDAT  (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26)
+#define PE9_AOUT_IR_RXD         (GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9)
+#define PF6_AOUT_PC_BVD2        (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6)
+#define PF7_AOUT_PC_BVD1        (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7)
+#define PF8_AOUT_PC_VS2         (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8)
+#define PF9_AOUT_PC_VS1         (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9)
+#define PF10_AOUT_PC_WP         (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10)
+#define PF11_AOUT_PC_READY      (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11)
+#define PF12_AOUT_PC_WAIT       (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12)
+#define PF13_AOUT_PC_CD2        (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13)
+#define PF14_AOUT_PC_CD1        (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14)
+
+
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx27.h b/arch/arm/plat-mxc/include/mach/iomux-mx27.h
new file mode 100644
index 000000000000..5ac158b70f61
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx27.h
@@ -0,0 +1,207 @@
+/*
+* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License
+* as published by the Free Software Foundation; either version 2
+* of the License, or (at your option) any later version.
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+* MA 02110-1301, USA.
+*/
+
+#ifndef _MXC_IOMUX_MX27_H
+#define _MXC_IOMUX_MX27_H
+
+#ifndef GPIO_PORTA
+#error Please include mach/iomux.h
+#endif
+
+
+/* Primary GPIO pin functions */
+
+#define PA0_PF_USBH2_CLK        (GPIO_PORTA | GPIO_PF | 0)
+#define PA1_PF_USBH2_DIR        (GPIO_PORTA | GPIO_PF | 1)
+#define PA2_PF_USBH2_DATA7      (GPIO_PORTA | GPIO_PF | 2)
+#define PA3_PF_USBH2_NXT        (GPIO_PORTA | GPIO_PF | 3)
+#define PA4_PF_USBH2_STP        (GPIO_PORTA | GPIO_PF | 4)
+#define PB22_PF_USBH1_SUSP      (GPIO_PORTB | GPIO_PF | 22)
+#define PB25_PF_USBH1_RCV       (GPIO_PORTB | GPIO_PF | 25)
+#define PC5_PF_I2C2_SDA         (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
+#define PC6_PF_I2C2_SCL         (GPIO_PORTC | GPIO_PF | GPIO_IN | 6)
+#define PC7_PF_USBOTG_DATA5     (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7)
+#define PC8_PF_USBOTG_DATA6     (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8)
+#define PC9_PF_USBOTG_DATA0     (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
+#define PC10_PF_USBOTG_DATA2    (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10)
+#define PC11_PF_USBOTG_DATA1    (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
+#define PC12_PF_USBOTG_DATA4    (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12)
+#define PC13_PF_USBOTG_DATA3    (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13)
+#define PC16_PF_SSI4_FS         (GPIO_PORTC | GPIO_PF | GPIO_IN | 16)
+#define PC17_PF_SSI4_RXD        (GPIO_PORTC | GPIO_PF | GPIO_IN | 17)
+#define PC18_PF_SSI4_TXD        (GPIO_PORTC | GPIO_PF | GPIO_IN | 18)
+#define PC19_PF_SSI4_CLK        (GPIO_PORTC | GPIO_PF | GPIO_IN | 19)
+#define PC25_AF_GPT5_TIN        (GPIO_PORTC | GPIO_AF | 25)
+#define PC27_AF_GPT4_TIN        (GPIO_PORTC | GPIO_AF | 27)
+#define PD0_PF_SD3_CMD          (GPIO_PORTD | GPIO_PF | 0)
+#define PD1_PF_SD3_CLK          (GPIO_PORTD | GPIO_PF | 1)
+#define PD2_PF_ATA_DATA0        (GPIO_PORTD | GPIO_PF | 2)
+#define PD3_PF_ATA_DATA1        (GPIO_PORTD | GPIO_PF | 3)
+#define PD4_PF_ATA_DATA2        (GPIO_PORTD | GPIO_PF | 4)
+#define PD5_PF_ATA_DATA3        (GPIO_PORTD | GPIO_PF | 5)
+#define PD6_PF_ATA_DATA4        (GPIO_PORTD | GPIO_PF | 6)
+#define PD7_PF_ATA_DATA5        (GPIO_PORTD | GPIO_PF | 7)
+#define PD8_PF_ATA_DATA6        (GPIO_PORTD | GPIO_PF | 8)
+#define PD9_PF_ATA_DATA7        (GPIO_PORTD | GPIO_PF | 9)
+#define PD10_PF_ATA_DATA8       (GPIO_PORTD | GPIO_PF | 10)
+#define PD11_PF_ATA_DATA9       (GPIO_PORTD | GPIO_PF | 11)
+#define PD12_PF_ATA_DATA10      (GPIO_PORTD | GPIO_PF | 12)
+#define PD13_PF_ATA_DATA11      (GPIO_PORTD | GPIO_PF | 13)
+#define PD14_PF_ATA_DATA12      (GPIO_PORTD | GPIO_PF | 14)
+#define PD15_PF_ATA_DATA13      (GPIO_PORTD | GPIO_PF | 15)
+#define PD16_PF_ATA_DATA14      (GPIO_PORTD | GPIO_PF | 16)
+#define PE0_PF_USBOTG_NXT       (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0)
+#define PE1_PF_USBOTG_STP       (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1)
+#define PE2_PF_USBOTG_DIR       (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2)
+#define PE24_PF_USBOTG_CLK      (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24)
+#define PE25_PF_USBOTG_DATA7    (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25)
+#define PF1_PF_NFCLE            (GPIO_PORTF | GPIO_PF | 1)
+#define PF3_PF_NFCE             (GPIO_PORTF | GPIO_PF | 3)
+#define PF7_PF_PC_POE           (GPIO_PORTF | GPIO_PF | 7)
+#define PF8_PF_PC_RW            (GPIO_PORTF | GPIO_PF | 8)
+#define PF9_PF_PC_IOIS16        (GPIO_PORTF | GPIO_PF | 9)
+#define PF10_PF_PC_RST          (GPIO_PORTF | GPIO_PF | 10)
+#define PF11_PF_PC_BVD2         (GPIO_PORTF | GPIO_PF | 11)
+#define PF12_PF_PC_BVD1         (GPIO_PORTF | GPIO_PF | 12)
+#define PF13_PF_PC_VS2          (GPIO_PORTF | GPIO_PF | 13)
+#define PF14_PF_PC_VS1          (GPIO_PORTF | GPIO_PF | 14)
+#define PF16_PF_PC_PWRON        (GPIO_PORTF | GPIO_PF | 16)
+#define PF17_PF_PC_READY        (GPIO_PORTF | GPIO_PF | 17)
+#define PF18_PF_PC_WAIT         (GPIO_PORTF | GPIO_PF | 18)
+#define PF19_PF_PC_CD2          (GPIO_PORTF | GPIO_PF | 19)
+#define PF20_PF_PC_CD1          (GPIO_PORTF | GPIO_PF | 20)
+#define PF23_PF_ATA_DATA15      (GPIO_PORTF | GPIO_PF | 23)
+
+/* Alternate GPIO pin functions */
+
+#define PB4_AF_MSHC_DATA0       (GPIO_PORTB | GPIO_AF | GPIO_OUT | 4)
+#define PB5_AF_MSHC_DATA1       (GPIO_PORTB | GPIO_AF | GPIO_OUT | 5)
+#define PB6_AF_MSHC_DATA2       (GPIO_PORTB | GPIO_AF | GPIO_OUT | 6)
+#define PB7_AF_MSHC_DATA4       (GPIO_PORTB | GPIO_AF | GPIO_OUT | 7)
+#define PB8_AF_MSHC_BS          (GPIO_PORTB | GPIO_AF | GPIO_OUT | 8)
+#define PB9_AF_MSHC_SCLK        (GPIO_PORTB | GPIO_AF | GPIO_OUT | 9)
+#define PB10_AF_UART6_TXD       (GPIO_PORTB | GPIO_AF | GPIO_OUT | 10)
+#define PB11_AF_UART6_RXD       (GPIO_PORTB | GPIO_AF | GPIO_IN | 11)
+#define PB12_AF_UART6_CTS       (GPIO_PORTB | GPIO_AF | GPIO_OUT | 12)
+#define PB13_AF_UART6_RTS       (GPIO_PORTB | GPIO_AF | GPIO_IN | 13)
+#define PB18_AF_UART5_TXD       (GPIO_PORTB | GPIO_AF | GPIO_OUT | 18)
+#define PB19_AF_UART5_RXD       (GPIO_PORTB | GPIO_AF | GPIO_IN | 19)
+#define PB20_AF_UART5_CTS       (GPIO_PORTB | GPIO_AF | GPIO_OUT | 20)
+#define PB21_AF_UART5_RTS       (GPIO_PORTB | GPIO_AF | GPIO_IN | 21)
+#define PC8_AF_FEC_MDIO         (GPIO_PORTC | GPIO_AF | GPIO_IN | 8)
+#define PC24_AF_GPT5_TOUT       (GPIO_PORTC | GPIO_AF | 24)
+#define PC26_AF_GPT4_TOUT       (GPIO_PORTC | GPIO_AF | 26)
+#define PD1_AF_ETMTRACE_PKT15   (GPIO_PORTD | GPIO_AF | 1)
+#define PD6_AF_ETMTRACE_PKT14   (GPIO_PORTD | GPIO_AF | 6)
+#define PD7_AF_ETMTRACE_PKT13   (GPIO_PORTD | GPIO_AF | 7)
+#define PD9_AF_ETMTRACE_PKT12   (GPIO_PORTD | GPIO_AF | 9)
+#define PD2_AF_SD3_D0           (GPIO_PORTD | GPIO_AF | 2)
+#define PD3_AF_SD3_D1           (GPIO_PORTD | GPIO_AF | 3)
+#define PD4_AF_SD3_D2           (GPIO_PORTD | GPIO_AF | 4)
+#define PD5_AF_SD3_D3           (GPIO_PORTD | GPIO_AF | 5)
+#define PD8_AF_FEC_MDIO         (GPIO_PORTD | GPIO_AF | GPIO_IN | 8)
+#define PD10_AF_ETMTRACE_PKT11  (GPIO_PORTD | GPIO_AF | 10)
+#define PD11_AF_ETMTRACE_PKT10  (GPIO_PORTD | GPIO_AF | 11)
+#define PD12_AF_ETMTRACE_PKT9   (GPIO_PORTD | GPIO_AF | 12)
+#define PD13_AF_ETMTRACE_PKT8   (GPIO_PORTD | GPIO_AF | 13)
+#define PD14_AF_ETMTRACE_PKT7   (GPIO_PORTD | GPIO_AF | 14)
+#define PD15_AF_ETMTRACE_PKT6   (GPIO_PORTD | GPIO_AF | 15)
+#define PD16_AF_ETMTRACE_PKT5   (GPIO_PORTD | GPIO_AF | 16)
+#define PF1_AF_ETMTRACE_PKT0    (GPIO_PORTF | GPIO_AF | 1)
+#define PF3_AF_ETMTRACE_PKT2    (GPIO_PORTF | GPIO_AF | 3)
+#define PF5_AF_ETMPIPESTAT11    (GPIO_PORTF | GPIO_AF | 5)
+#define PF7_AF_ATA_BUFFER_EN    (GPIO_PORTF | GPIO_AF | 7)
+#define PF8_AF_ATA_IORDY        (GPIO_PORTF | GPIO_AF | 8)
+#define PF9_AF_ATA_INTRQ        (GPIO_PORTF | GPIO_AF | 9)
+#define PF10_AF_ATA_RESET       (GPIO_PORTF | GPIO_AF | 10)
+#define PF11_AF_ATA_DMACK       (GPIO_PORTF | GPIO_AF | 11)
+#define PF12_AF_ATA_DMAREQ      (GPIO_PORTF | GPIO_AF | 12)
+#define PF13_AF_ATA_DA0         (GPIO_PORTF | GPIO_AF | 13)
+#define PF14_AF_ATA_DA1         (GPIO_PORTF | GPIO_AF | 14)
+#define PF15_AF_ETMTRACE_SYNC   (GPIO_PORTF | GPIO_AF | 15)
+#define PF16_AF_ATA_DA2         (GPIO_PORTF | GPIO_AF | 16)
+#define PF17_AF_ATA_CS0         (GPIO_PORTF | GPIO_AF | 17)
+#define PF18_AF_ATA_CS1         (GPIO_PORTF | GPIO_AF | 18)
+#define PF19_AF_ATA_DIOW        (GPIO_PORTF | GPIO_AF | 19)
+#define PF20_AF_ATA_DIOR        (GPIO_PORTF | GPIO_AF | 20)
+#define PF22_AF_ETMTRACE_CLK    (GPIO_PORTF | GPIO_AF | 22)
+#define PF23_AF_ETMTRACE_PKT4   (GPIO_PORTF | GPIO_AF | 23)
+
+/* AIN GPIO pin functions */
+
+#define PC14_AIN_SSI1_MCLK      (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14)
+#define PC15_AIN_GPT6_TOUT      (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 15)
+#define PD0_AIN_FEC_TXD0        (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 0)
+#define PD1_AIN_FEC_TXD1        (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 1)
+#define PD2_AIN_FEC_TXD2        (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 2)
+#define PD3_AIN_FEC_TXD3        (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 3)
+#define PD9_AIN_FEC_MDC         (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 9)
+#define PD16_AIN_FEC_TX_ER      (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 16)
+#define PD27_AIN_EXT_DMA_GRANT  (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 27)
+#define PF23_AIN_FEC_TX_EN      (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 23)
+
+/* BIN GPIO pin functions */
+
+#define PC14_BIN_SSI2_MCLK      (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14)
+
+/* CIN GPIO pin functions */
+
+#define PD2_CIN_SLCDC1_DAT0     (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 2)
+#define PD3_CIN_SLCDC1_DAT1     (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 3)
+#define PD4_CIN_SLCDC1_DAT2     (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 4)
+#define PD5_CIN_SLCDC1_DAT3     (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 5)
+#define PD6_CIN_SLCDC1_DAT4     (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 6)
+#define PD7_CIN_SLCDC1_DAT5     (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 7)
+#define PD8_CIN_SLCDC1_DAT6     (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 8)
+#define PD9_CIN_SLCDC1_DAT7     (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 9)
+#define PD10_CIN_SLCDC1_DAT8    (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 10)
+#define PD11_CIN_SLCDC1_DAT9    (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 11)
+#define PD12_CIN_SLCDC1_DAT10   (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 12)
+#define PD13_CIN_SLCDC1_DAT11   (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 13)
+#define PD14_CIN_SLCDC1_DAT12   (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 14)
+#define PD15_CIN_SLCDC1_DAT13   (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 15)
+#define PD16_CIN_SLCDC1_DAT14   (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 16)
+#define PD23_CIN_SLCDC1_DAT15   (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 23)
+#define PF27_CIN_EXT_DMA_GRANT  (GPIO_PORTF | GPIO_CIN | GPIO_OUT | 27)
+/* LCDC_TESTx on PBxx omitted, because it's not clear what they do */
+
+/* AOUT GPIO pin functions */
+
+#define PC14_AOUT_GPT6_TIN      (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 14)
+#define PD4_AOUT_FEC_RX_ER      (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 4)
+#define PD5_AOUT_FEC_RXD1       (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 5)
+#define PD6_AOUT_FEC_RXD2       (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 6)
+#define PD7_AOUT_FEC_RXD3       (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 7)
+#define PD10_AOUT_FEC_CRS       (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 10)
+#define PD11_AOUT_FEC_TX_CLK    (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 11)
+#define PD12_AOUT_FEC_RXD0      (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 12)
+#define PD13_AOUT_FEC_RX_DV     (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 13)
+#define PD14_AOUT_FEC_RX_CLK    (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14)
+#define PD15_AOUT_FEC_COL       (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15)
+
+#define PC17_BOUT_PC_IOIS16     (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17)
+#define PC18_BOUT_PC_BVD2       (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18)
+#define PC19_BOUT_PC_BVD1       (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19)
+#define PC28_BOUT_PC_BVD2       (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 28)
+#define PC29_BOUT_PC_VS1        (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 29)
+#define PC30_BOUT_PC_READY      (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30)
+#define PC31_BOUT_PC_WAIT       (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31)
+
+
+#endif /* _MXC_GPIO_MX1_MX2_H */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h
new file mode 100644
index 000000000000..fb5ae638e79f
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h
@@ -0,0 +1,237 @@
+/*
+* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License
+* as published by the Free Software Foundation; either version 2
+* of the License, or (at your option) any later version.
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+* MA 02110-1301, USA.
+*/
+
+#ifndef _MXC_IOMUX_MX2x_H
+#define _MXC_IOMUX_MX2x_H
+
+#ifndef GPIO_PORTA
+#error Please include mach/iomux.h
+#endif
+
+
+/* Primary GPIO pin functions */
+
+#define PA5_PF_LSCLK            (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5)
+#define PA6_PF_LD0              (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6)
+#define PA7_PF_LD1              (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7)
+#define PA8_PF_LD2              (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8)
+#define PA9_PF_LD3              (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9)
+#define PA10_PF_LD4             (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10)
+#define PA11_PF_LD5             (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11)
+#define PA12_PF_LD6             (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12)
+#define PA13_PF_LD7             (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13)
+#define PA14_PF_LD8             (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14)
+#define PA15_PF_LD9             (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
+#define PA16_PF_LD10            (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
+#define PA17_PF_LD11            (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17)
+#define PA18_PF_LD12            (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18)
+#define PA19_PF_LD13            (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19)
+#define PA20_PF_LD14            (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20)
+#define PA21_PF_LD15            (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21)
+#define PA22_PF_LD16            (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22)
+#define PA23_PF_LD17            (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23)
+#define PA24_PF_REV             (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24)
+#define PA25_PF_CLS             (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25)
+#define PA26_PF_PS              (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26)
+#define PA27_PF_SPL_SPR         (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27)
+#define PA28_PF_HSYNC           (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28)
+#define PA29_PF_VSYNC           (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29)
+#define PA30_PF_CONTRAST        (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30)
+#define PA31_PF_OE_ACD          (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31)
+#define PB4_PF_SD2_D0           (GPIO_PORTB | GPIO_PF | 4)
+#define PB5_PF_SD2_D1           (GPIO_PORTB | GPIO_PF | 5)
+#define PB6_PF_SD2_D2           (GPIO_PORTB | GPIO_PF | 6)
+#define PB7_PF_SD2_D3           (GPIO_PORTB | GPIO_PF | 7)
+#define PB8_PF_SD2_CMD          (GPIO_PORTB | GPIO_PF | 8)
+#define PB9_PF_SD2_CLK          (GPIO_PORTB | GPIO_PF | 9)
+#define PB10_PF_CSI_D0          (GPIO_PORTB | GPIO_PF | GPIO_OUT | 10)
+#define PB11_PF_CSI_D1          (GPIO_PORTB | GPIO_PF | GPIO_OUT | 11)
+#define PB12_PF_CSI_D2          (GPIO_PORTB | GPIO_PF | GPIO_OUT | 12)
+#define PB13_PF_CSI_D3          (GPIO_PORTB | GPIO_PF | GPIO_OUT | 13)
+#define PB14_PF_CSI_D4          (GPIO_PORTB | GPIO_PF | GPIO_OUT | 14)
+#define PB15_PF_CSI_MCLK        (GPIO_PORTB | GPIO_PF | GPIO_OUT | 15)
+#define PB16_PF_CSI_PIXCLK      (GPIO_PORTB | GPIO_PF | GPIO_OUT | 16)
+#define PB17_PF_CSI_D5          (GPIO_PORTB | GPIO_PF | GPIO_OUT | 17)
+#define PB18_PF_CSI_D6          (GPIO_PORTB | GPIO_PF | GPIO_OUT | 18)
+#define PB19_PF_CSI_D7          (GPIO_PORTB | GPIO_PF | GPIO_OUT | 19)
+#define PB20_PF_CSI_VSYNC       (GPIO_PORTB | GPIO_PF | GPIO_OUT | 20)
+#define PB21_PF_CSI_HSYNC       (GPIO_PORTB | GPIO_PF | GPIO_OUT | 21)
+#define PB23_PF_USB_PWR         (GPIO_PORTB | GPIO_PF | 23)
+#define PB24_PF_USB_OC          (GPIO_PORTB | GPIO_PF | 24)
+#define PB26_PF_USBH1_FS        (GPIO_PORTB | GPIO_PF | 26)
+#define PB27_PF_USBH1_OE        (GPIO_PORTB | GPIO_PF | 27)
+#define PB28_PF_USBH1_TXDM      (GPIO_PORTB | GPIO_PF | 28)
+#define PB29_PF_USBH1_TXDP      (GPIO_PORTB | GPIO_PF | 29)
+#define PB30_PF_USBH1_RXDM      (GPIO_PORTB | GPIO_PF | 30)
+#define PB31_PF_USBH1_RXDP      (GPIO_PORTB | GPIO_PF | 31)
+#define PC14_PF_TOUT            (GPIO_PORTC | GPIO_PF | 14)
+#define PC15_PF_TIN             (GPIO_PORTC | GPIO_PF | 15)
+#define PC20_PF_SSI1_FS         (GPIO_PORTC | GPIO_PF | GPIO_IN | 20)
+#define PC21_PF_SSI1_RXD        (GPIO_PORTC | GPIO_PF | GPIO_IN | 21)
+#define PC22_PF_SSI1_TXD        (GPIO_PORTC | GPIO_PF | GPIO_IN | 22)
+#define PC23_PF_SSI1_CLK        (GPIO_PORTC | GPIO_PF | GPIO_IN | 23)
+#define PC24_PF_SSI2_FS         (GPIO_PORTC | GPIO_PF | GPIO_IN | 24)
+#define PC25_PF_SSI2_RXD        (GPIO_PORTC | GPIO_PF | GPIO_IN | 25)
+#define PC26_PF_SSI2_TXD        (GPIO_PORTC | GPIO_PF | GPIO_IN | 26)
+#define PC27_PF_SSI2_CLK        (GPIO_PORTC | GPIO_PF | GPIO_IN | 27)
+#define PC28_PF_SSI3_FS         (GPIO_PORTC | GPIO_PF | GPIO_IN | 28)
+#define PC29_PF_SSI3_RXD        (GPIO_PORTC | GPIO_PF | GPIO_IN | 29)
+#define PC30_PF_SSI3_TXD        (GPIO_PORTC | GPIO_PF | GPIO_IN | 30)
+#define PC31_PF_SSI3_CLK        (GPIO_PORTC | GPIO_PF | GPIO_IN | 31)
+#define PD17_PF_I2C_DATA        (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
+#define PD18_PF_I2C_CLK         (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
+#define PD19_PF_CSPI2_SS2       (GPIO_PORTD | GPIO_PF | 19)
+#define PD20_PF_CSPI2_SS1       (GPIO_PORTD | GPIO_PF | 20)
+#define PD21_PF_CSPI2_SS0       (GPIO_PORTD | GPIO_PF | 21)
+#define PD22_PF_CSPI2_SCLK      (GPIO_PORTD | GPIO_PF | 22)
+#define PD23_PF_CSPI2_MISO      (GPIO_PORTD | GPIO_PF | 23)
+#define PD24_PF_CSPI2_MOSI      (GPIO_PORTD | GPIO_PF | 24)
+#define PD25_PF_CSPI1_RDY       (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
+#define PD26_PF_CSPI1_SS2       (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
+#define PD27_PF_CSPI1_SS1       (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
+#define PD28_PF_CSPI1_SS0       (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28)
+#define PD29_PF_CSPI1_SCLK      (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29)
+#define PD30_PF_CSPI1_MISO      (GPIO_PORTD | GPIO_PF | GPIO_IN | 30)
+#define PD31_PF_CSPI1_MOSI      (GPIO_PORTD | GPIO_PF | GPIO_OUT | 31)
+#define PE3_PF_UART2_CTS        (GPIO_PORTE | GPIO_PF | GPIO_OUT | 3)
+#define PE4_PF_UART2_RTS        (GPIO_PORTE | GPIO_PF | GPIO_IN | 4)
+#define PE5_PF_PWMO             (GPIO_PORTE | GPIO_PF | 5)
+#define PE6_PF_UART2_TXD        (GPIO_PORTE | GPIO_PF | GPIO_OUT | 6)
+#define PE7_PF_UART2_RXD        (GPIO_PORTE | GPIO_PF | GPIO_IN | 7)
+#define PE8_PF_UART3_TXD        (GPIO_PORTE | GPIO_PF | GPIO_OUT | 8)
+#define PE9_PF_UART3_RXD        (GPIO_PORTE | GPIO_PF | GPIO_IN | 9)
+#define PE10_PF_UART3_CTS       (GPIO_PORTE | GPIO_PF | GPIO_OUT | 10)
+#define PE11_PF_UART3_RTS       (GPIO_PORTE | GPIO_PF | GPIO_IN | 11)
+#define PE12_PF_UART1_TXD       (GPIO_PORTE | GPIO_PF | GPIO_OUT | 12)
+#define PE13_PF_UART1_RXD       (GPIO_PORTE | GPIO_PF | GPIO_IN | 13)
+#define PE14_PF_UART1_CTS       (GPIO_PORTE | GPIO_PF | GPIO_OUT | 14)
+#define PE15_PF_UART1_RTS       (GPIO_PORTE | GPIO_PF | GPIO_IN | 15)
+#define PE16_PF_RTCK            (GPIO_PORTE | GPIO_PF | GPIO_OUT | 16)
+#define PE17_PF_RESET_OUT       (GPIO_PORTE | GPIO_PF | 17)
+#define PE18_PF_SD1_D0          (GPIO_PORTE | GPIO_PF | 18)
+#define PE19_PF_SD1_D1          (GPIO_PORTE | GPIO_PF | 19)
+#define PE20_PF_SD1_D2          (GPIO_PORTE | GPIO_PF | 20)
+#define PE21_PF_SD1_D3          (GPIO_PORTE | GPIO_PF | 21)
+#define PE22_PF_SD1_CMD         (GPIO_PORTE | GPIO_PF | 22)
+#define PE23_PF_SD1_CLK         (GPIO_PORTE | GPIO_PF | 23)
+#define PF0_PF_NRFB             (GPIO_PORTF | GPIO_PF | 0)
+#define PF2_PF_NFWP             (GPIO_PORTF | GPIO_PF | 2)
+#define PF4_PF_NFALE            (GPIO_PORTF | GPIO_PF | 4)
+#define PF5_PF_NFRE             (GPIO_PORTF | GPIO_PF | 5)
+#define PF6_PF_NFWE             (GPIO_PORTF | GPIO_PF | 6)
+#define PF15_PF_CLKO            (GPIO_PORTF | GPIO_PF | 15)
+#define PF21_PF_CS4             (GPIO_PORTF | GPIO_PF | 21)
+#define PF22_PF_CS5             (GPIO_PORTF | GPIO_PF | 22)
+
+/* Alternate GPIO pin functions */
+
+#define PB26_AF_UART4_RTS       (GPIO_PORTB | GPIO_AF | GPIO_IN | 26)
+#define PB28_AF_UART4_TXD       (GPIO_PORTB | GPIO_AF | GPIO_OUT | 28)
+#define PB29_AF_UART4_CTS       (GPIO_PORTB | GPIO_AF | GPIO_OUT | 29)
+#define PB31_AF_UART4_RXD       (GPIO_PORTB | GPIO_AF | GPIO_IN | 31)
+#define PC28_AF_SLCDC2_D0       (GPIO_PORTC | GPIO_AF | 28)
+#define PC29_AF_SLCDC2_RS       (GPIO_PORTC | GPIO_AF | 29)
+#define PC30_AF_SLCDC2_CS       (GPIO_PORTC | GPIO_AF | 30)
+#define PC31_AF_SLCDC2_CLK      (GPIO_PORTC | GPIO_AF | 31)
+#define PD19_AF_USBH2_DATA4     (GPIO_PORTD | GPIO_AF | 19)
+#define PD20_AF_USBH2_DATA3     (GPIO_PORTD | GPIO_AF | 20)
+#define PD21_AF_USBH2_DATA6     (GPIO_PORTD | GPIO_AF | 21)
+#define PD22_AF_USBH2_DATA0     (GPIO_PORTD | GPIO_AF | 22)
+#define PD23_AF_USBH2_DATA2     (GPIO_PORTD | GPIO_AF | 23)
+#define PD24_AF_USBH2_DATA1     (GPIO_PORTD | GPIO_AF | 24)
+#define PD26_AF_USBH2_DATA5     (GPIO_PORTD | GPIO_AF | 26)
+#define PE0_AF_KP_COL6          (GPIO_PORTE | GPIO_AF | 0)
+#define PE1_AF_KP_ROW6          (GPIO_PORTE | GPIO_AF | 1)
+#define PE2_AF_KP_ROW7          (GPIO_PORTE | GPIO_AF | 2)
+#define PE3_AF_KP_COL7          (GPIO_PORTE | GPIO_AF | 3)
+#define PE4_AF_KP_ROW7          (GPIO_PORTE | GPIO_AF | 4)
+#define PE6_AF_KP_COL6          (GPIO_PORTE | GPIO_AF | 6)
+#define PE7_AF_KP_ROW6          (GPIO_PORTE | GPIO_AF | 7)
+#define PE16_AF_OWIRE           (GPIO_PORTE | GPIO_AF | 16)
+#define PE18_AF_CSPI3_MISO      (GPIO_PORTE | GPIO_AF | GPIO_IN | 18)
+#define PE21_AF_CSPI3_SS        (GPIO_PORTE | GPIO_AF | GPIO_OUT | 21)
+#define PE22_AF_CSPI3_MOSI      (GPIO_PORTE | GPIO_AF | GPIO_OUT | 22)
+#define PE23_AF_CSPI3_SCLK      (GPIO_PORTE | GPIO_AF | GPIO_OUT | 23)
+
+/* AIN GPIO pin functions */
+
+#define PA6_AIN_SLCDC1_DAT0     (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 6)
+#define PA7_AIN_SLCDC1_DAT1     (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 7)
+#define PA8_AIN_SLCDC1_DAT2     (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 8)
+#define PA0_AIN_SLCDC1_DAT3     (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
+#define PA11_AIN_SLCDC1_DAT5    (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 11)
+#define PA13_AIN_SLCDC1_DAT7    (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 13)
+#define PA15_AIN_SLCDC1_DAT9    (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 15)
+#define PA17_AIN_SLCDC1_DAT11   (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17)
+#define PA19_AIN_SLCDC1_DAT13   (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 19)
+#define PA21_AIN_SLCDC1_DAT15   (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 21)
+#define PA22_AIN_EXT_DMAGRANT   (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 22)
+#define PA24_AIN_SLCDC1_D0      (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 24)
+#define PA25_AIN_SLCDC1_RS      (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 25)
+#define PA26_AIN_SLCDC1_CS      (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 26)
+#define PA27_AIN_SLCDC1_CLK     (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 27)
+#define PB6_AIN_SLCDC1_D0       (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 6)
+#define PB7_AIN_SLCDC1_RS       (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 7)
+#define PB8_AIN_SLCDC1_CS       (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 8)
+#define PB9_AIN_SLCDC1_CLK      (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 9)
+#define PB25_AIN_SLCDC1_DAT0    (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 25)
+#define PB26_AIN_SLCDC1_DAT1    (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 26)
+#define PB27_AIN_SLCDC1_DAT2    (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 27)
+#define PB28_AIN_SLCDC1_DAT3    (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 28)
+#define PB29_AIN_SLCDC1_DAT4    (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 29)
+#define PB30_AIN_SLCDC1_DAT5    (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 30)
+#define PB31_AIN_SLCDC1_DAT6    (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 31)
+#define PC5_AIN_SLCDC1_DAT7     (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 5)
+#define PC6_AIN_SLCDC1_DAT8     (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 6)
+#define PC7_AIN_SLCDC1_DAT9     (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 7)
+#define PC8_AIN_SLCDC1_DAT10    (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 8)
+#define PC9_AIN_SLCDC1_DAT11    (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 9)
+#define PC10_AIN_SLCDC1_DAT12   (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 10)
+#define PC11_AIN_SLCDC1_DAT13   (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 11)
+#define PC12_AIN_SLCDC1_DAT14   (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 12)
+#define PC13_AIN_SLCDC1_DAT15   (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 13)
+#define PE5_AIN_PC_SPKOUT       (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 5)
+
+/* BIN GPIO pin functions */
+
+#define PE5_BIN_TOUT2           (GPIO_PORTE | GPIO_BIN | GPIO_OUT | 5)
+
+/* CIN GPIO pin functions */
+
+#define PA14_CIN_SLCDC1_DAT0    (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 14)
+#define PA15_CIN_SLCDC1_DAT1    (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 15)
+#define PA16_CIN_SLCDC1_DAT2    (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 16)
+#define PA17_CIN_SLCDC1_DAT3    (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 17)
+#define PA18_CIN_SLCDC1_DAT4    (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 18)
+#define PA19_CIN_SLCDC1_DAT5    (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 19)
+#define PA20_CIN_SLCDC1_DAT6    (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 20)
+#define PA21_CIN_SLCDC1_DAT7    (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 21)
+#define PB30_CIN_UART4_CTS      (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 30)
+#define PE5_CIN_TOUT3           (GPIO_PORTE | GPIO_CIN | GPIO_OUT | 5)
+
+/* AOUT GPIO pin functions */
+
+#define PB29_AOUT_UART4_RXD     (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 29)
+#define PB31_AOUT_UART4_RTS     (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 31)
+#define PC8_AOUT_USBOTG_TXR_INT (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 8)
+#define PC15_AOUT_WKGD          (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15)
+#define PF21_AOUT_DTACK         (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21)
+
+
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index c9198c0aea18..ab838cfe94f9 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -92,7 +92,7 @@ enum iomux_gp_func {
         MUX_EXTDMAREQ2_MBX_SEL          = 1 << 15,
         MUX_TAMPER_DETECT_EN            = 1 << 16,
         MUX_PGP_USB_4WIRE               = 1 << 17,
-        MUX_PGB_USB_COMMON              = 1 << 18,
+        MUX_PGP_USB_COMMON              = 1 << 18,
         MUX_SDHC_MEMSTICK1              = 1 << 19,
         MUX_SDHC_MEMSTICK2              = 1 << 20,
         MUX_PGP_SPLL_BYP                = 1 << 21,
@@ -109,21 +109,44 @@ enum iomux_gp_func {
 };
 
 /*
- * This function enables/disables the general purpose function for a particular
- * signal.
+ * setups a single pin:
+ *      - reserves the pin so that it is not claimed by another driver
+ *      - setups the iomux according to the configuration
+ *      - if the pin is configured as a GPIO, we claim it throug kernel gpiolib
+ */
+int mxc_iomux_setup_pin(const unsigned int pin, const char *label);
+/*
+ * setups mutliple pins
+ * convenient way to call the above function with tables
  */
-void iomux_config_gpr(enum iomux_gp_func , bool);
+int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
+                const char *label);
 
 /*
- * set the mode for a IOMUX pin.
+ * releases a single pin:
+ *      - make it available for a future use by another driver
+ *      - frees the GPIO if the pin was configured as GPIO
+ *      - DOES NOT reconfigure the IOMUX in its reset state
  */
-int mxc_iomux_mode(unsigned int);
+void mxc_iomux_release_pin(const unsigned int pin);
+/*
+ * releases multiple pins
+ * convenvient way to call the above function with tables
+ */
+void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count);
 
 /*
  * This function enables/disables the general purpose function for a particular
  * signal.
  */
-void mxc_iomux_set_gpr(enum iomux_gp_func, bool);
+void mxc_iomux_set_gpr(enum iomux_gp_func, bool en);
+
+/*
+ * This function only configures the iomux hardware.
+ * It is called by the setup functions and should not be called directly anymore.
+ * It is here visible for backward compatibility
+ */
+int mxc_iomux_mode(unsigned int pin_mode);
 
 #define IOMUX_PADNUM_MASK       0x1ff
 #define IOMUX_GPIONUM_SHIFT     9
@@ -144,6 +167,11 @@ void mxc_iomux_set_gpr(enum iomux_gp_func, bool);
         MXC_GPIO_IRQ_START)
 
 /*
+ * The number of gpio devices among the pads
+ */
+#define GPIO_PORT_MAX 3
+
+/*
  * This enumeration is constructed based on the Section
  * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
  * value is constructed based on the rules described above.
@@ -480,6 +508,9 @@ enum iomux_pins {
         MX31_PIN_CAPTURE        = IOMUX_PIN( 7,   327),
 };
 
+#define PIN_MAX 327
+#define NB_PORTS 12 /* NB_PINS/32, we chose 32 pins per "PORT" */
+
 /*
  * Convenience values for use with mxc_iomux_mode()
  *
@@ -507,7 +538,9 @@ enum iomux_pins {
 #define MX31_PIN_CSPI1_SS1__SS1         IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_CSPI1_SS2__SS2         IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_CSPI2_MOSI__MOSI       IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI2_MOSI__SCL        IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1)
 #define MX31_PIN_CSPI2_MISO__MISO       IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI2_MISO__SDA        IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1)
 #define MX31_PIN_CSPI2_SCLK__SCLK       IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_CSPI2_SS0__SS0         IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC)
@@ -525,6 +558,33 @@ enum iomux_pins {
 #define MX31_PIN_SD1_DATA0__SD1_DATA0   IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_SD1_CLK__SD1_CLK       IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_SD1_CMD__SD1_CMD       IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD0__LD0               IOMUX_MODE(MX31_PIN_LD0, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD1__LD1               IOMUX_MODE(MX31_PIN_LD1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD2__LD2               IOMUX_MODE(MX31_PIN_LD2, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD3__LD3               IOMUX_MODE(MX31_PIN_LD3, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD4__LD4               IOMUX_MODE(MX31_PIN_LD4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD5__LD5               IOMUX_MODE(MX31_PIN_LD5, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD6__LD6               IOMUX_MODE(MX31_PIN_LD6, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD7__LD7               IOMUX_MODE(MX31_PIN_LD7, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD8__LD8               IOMUX_MODE(MX31_PIN_LD8, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD9__LD9               IOMUX_MODE(MX31_PIN_LD9, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD10__LD10             IOMUX_MODE(MX31_PIN_LD10, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD11__LD11             IOMUX_MODE(MX31_PIN_LD11, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD12__LD12             IOMUX_MODE(MX31_PIN_LD12, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD13__LD13             IOMUX_MODE(MX31_PIN_LD13, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD14__LD14             IOMUX_MODE(MX31_PIN_LD14, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD15__LD15             IOMUX_MODE(MX31_PIN_LD15, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD16__LD16             IOMUX_MODE(MX31_PIN_LD16, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LD17__LD17             IOMUX_MODE(MX31_PIN_LD17, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_VSYNC3__VSYNC3         IOMUX_MODE(MX31_PIN_VSYNC3, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_HSYNC__HSYNC           IOMUX_MODE(MX31_PIN_HSYNC, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_FPSHIFT__FPSHIFT       IOMUX_MODE(MX31_PIN_FPSHIFT, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_DRDY0__DRDY0           IOMUX_MODE(MX31_PIN_DRDY0, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_D3_REV__D3_REV         IOMUX_MODE(MX31_PIN_D3_REV, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CONTRAST__CONTRAST     IOMUX_MODE(MX31_PIN_CONTRAST, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_D3_SPL__D3_SPL         IOMUX_MODE(MX31_PIN_D3_SPL, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_D3_CLS__D3_CLS         IOMUX_MODE(MX31_PIN_D3_CLS, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_LCS0__GPI03_23         IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO)
 
 /*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0
  * cspi1_ss1*/
diff --git a/arch/arm/plat-mxc/include/mach/iomux.h b/arch/arm/plat-mxc/include/mach/iomux.h
new file mode 100644
index 000000000000..171f8adc1109
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux.h
@@ -0,0 +1,127 @@
+/*
+* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License
+* as published by the Free Software Foundation; either version 2
+* of the License, or (at your option) any later version.
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+* MA 02110-1301, USA.
+*/
+
+#ifndef _MXC_IOMUX_H
+#define _MXC_IOMUX_H
+
+/*
+*  GPIO Module and I/O Multiplexer
+*  x = 0..3 for reg_A, reg_B, reg_C, reg_D
+*/
+#define VA_GPIO_BASE    IO_ADDRESS(GPIO_BASE_ADDR)
+#define MXC_DDIR(x)    (0x00 + ((x) << 8))
+#define MXC_OCR1(x)    (0x04 + ((x) << 8))
+#define MXC_OCR2(x)    (0x08 + ((x) << 8))
+#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
+#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
+#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
+#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
+#define MXC_DR(x)      (0x1c + ((x) << 8))
+#define MXC_GIUS(x)    (0x20 + ((x) << 8))
+#define MXC_SSR(x)     (0x24 + ((x) << 8))
+#define MXC_ICR1(x)    (0x28 + ((x) << 8))
+#define MXC_ICR2(x)    (0x2c + ((x) << 8))
+#define MXC_IMR(x)     (0x30 + ((x) << 8))
+#define MXC_ISR(x)     (0x34 + ((x) << 8))
+#define MXC_GPR(x)     (0x38 + ((x) << 8))
+#define MXC_SWR(x)     (0x3c + ((x) << 8))
+#define MXC_PUEN(x)    (0x40 + ((x) << 8))
+
+#ifdef CONFIG_ARCH_MX1
+# define GPIO_PORT_MAX  3
+#endif
+#ifdef CONFIG_ARCH_MX2
+# define GPIO_PORT_MAX  5
+#endif
+
+#ifndef GPIO_PORT_MAX
+# error "GPIO config port count unknown!"
+#endif
+
+#define GPIO_PIN_MASK 0x1f
+
+#define GPIO_PORT_SHIFT 5
+#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
+
+#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
+#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
+#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
+#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
+#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
+#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
+
+#define GPIO_OUT   (1 << 8)
+#define GPIO_IN    (0 << 8)
+#define GPIO_PUEN  (1 << 9)
+
+#define GPIO_PF    (1 << 10)
+#define GPIO_AF    (1 << 11)
+
+#define GPIO_OCR_SHIFT 12
+#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
+#define GPIO_AIN   (0 << GPIO_OCR_SHIFT)
+#define GPIO_BIN   (1 << GPIO_OCR_SHIFT)
+#define GPIO_CIN   (2 << GPIO_OCR_SHIFT)
+#define GPIO_GPIO  (3 << GPIO_OCR_SHIFT)
+
+#define GPIO_AOUT_SHIFT 14
+#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT     (0 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_0   (2 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_1   (3 << GPIO_AOUT_SHIFT)
+
+#define GPIO_BOUT_SHIFT 16
+#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT      (0 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_ISR  (1 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_0    (2 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_1    (3 << GPIO_BOUT_SHIFT)
+
+
+#ifdef CONFIG_ARCH_MX1
+#include <mach/iomux-mx1.h>
+#endif
+#ifdef CONFIG_ARCH_MX2
+#include <mach/iomux-mx2x.h>
+#ifdef CONFIG_MACH_MX21
+#include <mach/iomux-mx21.h>
+#endif
+#ifdef CONFIG_MACH_MX27
+#include <mach/iomux-mx27.h>
+#endif
+#endif
+
+
+/* decode irq number to use with IMR(x), ISR(x) and friends */
+#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5)
+
+#define IRQ_GPIOA(x)  (MXC_GPIO_IRQ_START + x)
+#define IRQ_GPIOB(x)  (IRQ_GPIOA(32) + x)
+#define IRQ_GPIOC(x)  (IRQ_GPIOB(32) + x)
+#define IRQ_GPIOD(x)  (IRQ_GPIOC(32) + x)
+#define IRQ_GPIOE(x)  (IRQ_GPIOD(32) + x)
+
+
+extern void mxc_gpio_mode(int gpio_mode);
+extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
+        const char *label);
+extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
+
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index 0b808399097f..e0783e619580 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -14,7 +14,12 @@
 #if defined CONFIG_ARCH_MX1
 #define PHYS_OFFSET             UL(0x08000000)
 #elif defined CONFIG_ARCH_MX2
+#ifdef CONFIG_MACH_MX21
+#define PHYS_OFFSET             UL(0xC0000000)
+#endif
+#ifdef CONFIG_MACH_MX27
 #define PHYS_OFFSET             UL(0xA0000000)
+#endif
 #elif defined CONFIG_ARCH_MX3
 #define PHYS_OFFSET             UL(0x80000000)
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
new file mode 100644
index 000000000000..e8c4cf56c24e
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2009 Holger Schurig, hs4233@mail.mn-solutions.de
+ *
+ * This contains i.MX21-specific hardware definitions. For those
+ * hardware pieces that are common between i.MX21 and i.MX27, have a
+ * look at mx2x.h.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_MX21_H__
+#define __ASM_ARCH_MXC_MX21_H__
+
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#error "Do not include directly."
+#endif
+
+
+/* Memory regions and CS */
+#define SDRAM_BASE_ADDR         0xC0000000
+#define CSD1_BASE_ADDR          0xC4000000
+
+#define CS0_BASE_ADDR           0xC8000000
+#define CS1_BASE_ADDR           0xCC000000
+#define CS2_BASE_ADDR           0xD0000000
+#define CS3_BASE_ADDR           0xD1000000
+#define CS4_BASE_ADDR           0xD2000000
+#define CS5_BASE_ADDR           0xDD000000
+#define PCMCIA_MEM_BASE_ADDR    0xD4000000
+
+/* NAND, SDRAM, WEIM etc controllers */
+#define X_MEMC_BASE_ADDR        0xDF000000
+#define X_MEMC_BASE_ADDR_VIRT   0xF4200000
+#define X_MEMC_SIZE             SZ_256K
+
+#define SDRAMC_BASE_ADDR        (X_MEMC_BASE_ADDR + 0x0000)
+#define EIM_BASE_ADDR           (X_MEMC_BASE_ADDR + 0x1000)
+#define PCMCIA_CTL_BASE_ADDR    (X_MEMC_BASE_ADDR + 0x2000)
+#define NFC_BASE_ADDR           (X_MEMC_BASE_ADDR + 0x3000)
+
+#define IRAM_BASE_ADDR          0xFFFFE800      /* internal ram */
+
+/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
+#define ARCH_NR_GPIOS           (6*32 + 16)
+
+/* fixed interrupt numbers */
+#define MXC_INT_USBCTRL         58
+#define MXC_INT_USBCTRL         58
+#define MXC_INT_USBMNP          57
+#define MXC_INT_USBFUNC         56
+#define MXC_INT_USBHOST         55
+#define MXC_INT_USBDMA          54
+#define MXC_INT_USBWKUP         53
+#define MXC_INT_EMMADEC         50
+#define MXC_INT_EMMAENC         49
+#define MXC_INT_BMI             30
+#define MXC_INT_FIRI            9
+
+/* fixed DMA request numbers */
+#define DMA_REQ_BMI_RX          29
+#define DMA_REQ_BMI_TX          28
+#define DMA_REQ_FIRI_RX         4
+
+#endif /* __ASM_ARCH_MXC_MX21_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index 0313be720552..6e93f2c0b7bb 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -2,6 +2,10 @@
  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  *
+ * This contains i.MX27-specific hardware definitions. For those
+ * hardware pieces that are common between i.MX21 and i.MX27, have a
+ * look at mx2x.h.
+ *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version 2
@@ -27,35 +31,6 @@
 /* IRAM */
 #define IRAM_BASE_ADDR          0xFFFF4C00      /* internal ram */
 
-/* Register offests */
-#define AIPI_BASE_ADDR          0x10000000
-#define AIPI_BASE_ADDR_VIRT     0xF4000000
-#define AIPI_SIZE               SZ_1M
-
-#define DMA_BASE_ADDR           (AIPI_BASE_ADDR + 0x01000)
-#define WDOG_BASE_ADDR          (AIPI_BASE_ADDR + 0x02000)
-#define GPT1_BASE_ADDR          (AIPI_BASE_ADDR + 0x03000)
-#define GPT2_BASE_ADDR          (AIPI_BASE_ADDR + 0x04000)
-#define GPT3_BASE_ADDR          (AIPI_BASE_ADDR + 0x05000)
-#define PWM_BASE_ADDR           (AIPI_BASE_ADDR + 0x06000)
-#define RTC_BASE_ADDR           (AIPI_BASE_ADDR + 0x07000)
-#define KPP_BASE_ADDR           (AIPI_BASE_ADDR + 0x08000)
-#define OWIRE_BASE_ADDR         (AIPI_BASE_ADDR + 0x09000)
-#define UART1_BASE_ADDR         (AIPI_BASE_ADDR + 0x0A000)
-#define UART2_BASE_ADDR         (AIPI_BASE_ADDR + 0x0B000)
-#define UART3_BASE_ADDR         (AIPI_BASE_ADDR + 0x0C000)
-#define UART4_BASE_ADDR         (AIPI_BASE_ADDR + 0x0D000)
-#define CSPI1_BASE_ADDR         (AIPI_BASE_ADDR + 0x0E000)
-#define CSPI2_BASE_ADDR         (AIPI_BASE_ADDR + 0x0F000)
-#define SSI1_BASE_ADDR          (AIPI_BASE_ADDR + 0x10000)
-#define SSI2_BASE_ADDR          (AIPI_BASE_ADDR + 0x11000)
-#define I2C_BASE_ADDR           (AIPI_BASE_ADDR + 0x12000)
-#define SDHC1_BASE_ADDR         (AIPI_BASE_ADDR + 0x13000)
-#define SDHC2_BASE_ADDR         (AIPI_BASE_ADDR + 0x14000)
-#define GPIO_BASE_ADDR          (AIPI_BASE_ADDR + 0x15000)
-#define AUDMUX_BASE_ADDR        (AIPI_BASE_ADDR + 0x16000)
-
-#define CSPI3_BASE_ADDR         (AIPI_BASE_ADDR + 0x17000)
 #define MSHC_BASE_ADDR          (AIPI_BASE_ADDR + 0x18000)
 #define GPT5_BASE_ADDR          (AIPI_BASE_ADDR + 0x19000)
 #define GPT4_BASE_ADDR          (AIPI_BASE_ADDR + 0x1A000)
@@ -64,55 +39,24 @@
 #define I2C2_BASE_ADDR          (AIPI_BASE_ADDR + 0x1D000)
 #define SDHC3_BASE_ADDR         (AIPI_BASE_ADDR + 0x1E000)
 #define GPT6_BASE_ADDR          (AIPI_BASE_ADDR + 0x1F000)
-
-#define LCDC_BASE_ADDR          (AIPI_BASE_ADDR + 0x21000)
-#define SLCDC_BASE_ADDR         (AIPI_BASE_ADDR + 0x22000)
 #define VPU_BASE_ADDR           (AIPI_BASE_ADDR + 0x23000)
-#define USBOTG_BASE_ADDR        (AIPI_BASE_ADDR + 0x24000)
-/* for mx27*/
 #define OTG_BASE_ADDR           USBOTG_BASE_ADDR
 #define SAHARA_BASE_ADDR        (AIPI_BASE_ADDR + 0x25000)
-#define EMMA_PP_BASE_ADDR       (AIPI_BASE_ADDR + 0x26000)
-#define EMMA_PRP_BASE_ADDR      (AIPI_BASE_ADDR + 0x26400)
-#define CCM_BASE_ADDR           (AIPI_BASE_ADDR + 0x27000)
-#define SYSCTRL_BASE_ADDR       (AIPI_BASE_ADDR + 0x27800)
 #define IIM_BASE_ADDR           (AIPI_BASE_ADDR + 0x28000)
-
 #define RTIC_BASE_ADDR          (AIPI_BASE_ADDR + 0x2A000)
 #define FEC_BASE_ADDR           (AIPI_BASE_ADDR + 0x2B000)
 #define SCC_BASE_ADDR           (AIPI_BASE_ADDR + 0x2C000)
 #define ETB_BASE_ADDR           (AIPI_BASE_ADDR + 0x3B000)
 #define ETB_RAM_BASE_ADDR       (AIPI_BASE_ADDR + 0x3C000)
 
-#define JAM_BASE_ADDR           (AIPI_BASE_ADDR + 0x3E000)
-#define MAX_BASE_ADDR           (AIPI_BASE_ADDR + 0x3F000)
-
-/* ROMP and AVIC */
+/* ROM patch */
 #define ROMP_BASE_ADDR          0x10041000
 
-#define AVIC_BASE_ADDR          0x10040000
-
-#define SAHB1_BASE_ADDR         0x80000000
-#define SAHB1_BASE_ADDR_VIRT    0xF4100000
-#define SAHB1_SIZE              SZ_1M
-
-#define CSI_BASE_ADDR           (SAHB1_BASE_ADDR + 0x0000)
 #define ATA_BASE_ADDR           (SAHB1_BASE_ADDR + 0x1000)
 
-/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
-#define X_MEMC_BASE_ADDR        0xD8000000
-#define X_MEMC_BASE_ADDR_VIRT   0xF4200000
-#define X_MEMC_SIZE             SZ_1M
-
-#define NFC_BASE_ADDR           (X_MEMC_BASE_ADDR)
-#define SDRAMC_BASE_ADDR        (X_MEMC_BASE_ADDR + 0x1000)
-#define WEIM_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x2000)
-#define M3IF_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x3000)
-#define PCMCIA_CTL_BASE_ADDR    (X_MEMC_BASE_ADDR + 0x4000)
-
 /* Memory regions and CS */
-#define SDRAM_BASE_ADDR         0xA0000000
-#define CSD1_BASE_ADDR          0xB0000000
+#define SDRAM_BASE_ADDR         0xA0000000
+#define CSD1_BASE_ADDR          0xB0000000
 
 #define CS0_BASE_ADDR           0xC0000000
 #define CS1_BASE_ADDR           0xC8000000
@@ -122,44 +66,20 @@
 #define CS5_BASE_ADDR           0xD6000000
 #define PCMCIA_MEM_BASE_ADDR    0xDC000000
 
-/*
- * This macro defines the physical to virtual address mapping for all the
- * peripheral modules. It is used by passing in the physical address as x
- * and returning the virtual address. If the physical address is not mapped,
- * it returns 0xDEADBEEF
- */
-#define IO_ADDRESS(x)   \
-        (void __iomem *) \
-        (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
-                AIPI_IO_ADDRESS(x) : \
-        ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
-                SAHB1_IO_ADDRESS(x) : \
-        ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
-                X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
-
-/* define the address mapping macros: in physical address order */
-#define AIPI_IO_ADDRESS(x)  \
-        (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
-
-#define AVIC_IO_ADDRESS(x)      AIPI_IO_ADDRESS(x)
-
-#define SAHB1_IO_ADDRESS(x)  \
-        (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
-
-#define CS4_IO_ADDRESS(x)  \
-        (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
-
-#define X_MEMC_IO_ADDRESS(x)  \
-        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
+#define X_MEMC_BASE_ADDR        0xD8000000
+#define X_MEMC_BASE_ADDR_VIRT   0xF4200000
+#define X_MEMC_SIZE             SZ_1M
 
-#define PCMCIA_IO_ADDRESS(x) \
-        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+#define NFC_BASE_ADDR           (X_MEMC_BASE_ADDR)
+#define SDRAMC_BASE_ADDR        (X_MEMC_BASE_ADDR + 0x1000)
+#define WEIM_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x2000)
+#define M3IF_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x3000)
+#define PCMCIA_CTL_BASE_ADDR    (X_MEMC_BASE_ADDR + 0x4000)
 
-/* fixed interrput numbers */
+/* fixed interrupt numbers */
 #define MXC_INT_CCM             63
 #define MXC_INT_IIM             62
-#define MXC_INT_LCDC            61
-#define MXC_INT_SLCDC           60
 #define MXC_INT_SAHARA          59
 #define MXC_INT_SCC_SCM         58
 #define MXC_INT_SCC_SMN         57
@@ -167,54 +87,12 @@
 #define MXC_INT_USB2            55
 #define MXC_INT_USB1            54
 #define MXC_INT_VPU             53
-#define MXC_INT_EMMAPP          52
-#define MXC_INT_EMMAPRP         51
 #define MXC_INT_FEC             50
 #define MXC_INT_UART5           49
 #define MXC_INT_UART6           48
-#define MXC_INT_DMACH15         47
-#define MXC_INT_DMACH14         46
-#define MXC_INT_DMACH13         45
-#define MXC_INT_DMACH12         44
-#define MXC_INT_DMACH11         43
-#define MXC_INT_DMACH10         42
-#define MXC_INT_DMACH9          41
-#define MXC_INT_DMACH8          40
-#define MXC_INT_DMACH7          39
-#define MXC_INT_DMACH6          38
-#define MXC_INT_DMACH5          37
-#define MXC_INT_DMACH4          36
-#define MXC_INT_DMACH3          35
-#define MXC_INT_DMACH2          34
-#define MXC_INT_DMACH1          33
-#define MXC_INT_DMACH0          32
-#define MXC_INT_CSI             31
 #define MXC_INT_ATA             30
-#define MXC_INT_NANDFC          29
-#define MXC_INT_PCMCIA          28
-#define MXC_INT_WDOG            27
-#define MXC_INT_GPT1            26
-#define MXC_INT_GPT2            25
-#define MXC_INT_GPT3            24
-#define MXC_INT_GPT             INT_GPT1
-#define MXC_INT_PWM             23
-#define MXC_INT_RTC             22
-#define MXC_INT_KPP             21
-#define MXC_INT_UART1           20
-#define MXC_INT_UART2           19
-#define MXC_INT_UART3           18
-#define MXC_INT_UART4           17
-#define MXC_INT_CSPI1           16
-#define MXC_INT_CSPI2           15
-#define MXC_INT_SSI1            14
-#define MXC_INT_SSI2            13
-#define MXC_INT_I2C             12
-#define MXC_INT_SDHC1           11
-#define MXC_INT_SDHC2           10
 #define MXC_INT_SDHC3           9
-#define MXC_INT_GPIO            8
 #define MXC_INT_SDHC            7
-#define MXC_INT_CSPI3           6
 #define MXC_INT_RTIC            5
 #define MXC_INT_GPT4            4
 #define MXC_INT_GPT5            3
@@ -228,36 +106,9 @@
 #define DMA_REQ_UART6_TX        34
 #define DMA_REQ_UART5_RX        33
 #define DMA_REQ_UART5_TX        32
-#define DMA_REQ_CSI_RX          31
-#define DMA_REQ_CSI_STAT        30
 #define DMA_REQ_ATA_RCV         29
 #define DMA_REQ_ATA_TX          28
-#define DMA_REQ_UART1_TX        27
-#define DMA_REQ_UART1_RX        26
-#define DMA_REQ_UART2_TX        25
-#define DMA_REQ_UART2_RX        24
-#define DMA_REQ_UART3_TX        23
-#define DMA_REQ_UART3_RX        22
-#define DMA_REQ_UART4_TX        21
-#define DMA_REQ_UART4_RX        20
-#define DMA_REQ_CSPI1_TX        19
-#define DMA_REQ_CSPI1_RX        18
-#define DMA_REQ_CSPI2_TX        17
-#define DMA_REQ_CSPI2_RX        16
-#define DMA_REQ_SSI1_TX1        15
-#define DMA_REQ_SSI1_RX1        14
-#define DMA_REQ_SSI1_TX0        13
-#define DMA_REQ_SSI1_RX0        12
-#define DMA_REQ_SSI2_TX1        11
-#define DMA_REQ_SSI2_RX1        10
-#define DMA_REQ_SSI2_TX0        9
-#define DMA_REQ_SSI2_RX0        8
-#define DMA_REQ_SDHC1           7
-#define DMA_REQ_SDHC2           6
 #define DMA_REQ_MSHC            4
-#define DMA_REQ_EXT             3
-#define DMA_REQ_CSPI3_TX        2
-#define DMA_REQ_CSPI3_RX        1
 
 /* silicon revisions specific to i.MX27 */
 #define CHIP_REV_1_0            0x00
@@ -267,25 +118,8 @@
 extern int mx27_revision(void);
 #endif
 
-/* gpio and gpio based interrupt handling */
-#define GPIO_DR                 0x1C
-#define GPIO_GDIR               0x00
-#define GPIO_PSR                0x24
-#define GPIO_ICR1               0x28
-#define GPIO_ICR2               0x2C
-#define GPIO_IMR                0x30
-#define GPIO_ISR                0x34
-#define GPIO_INT_LOW_LEV        0x3
-#define GPIO_INT_HIGH_LEV       0x2
-#define GPIO_INT_RISE_EDGE      0x0
-#define GPIO_INT_FALL_EDGE      0x1
-#define GPIO_INT_NONE           0x4
-
 /* Mandatory defines used globally */
 
-/* this is an i.MX27 CPU */
-#define cpu_is_mx27()           (1)
-
 /* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
 #define ARCH_NR_GPIOS           (192 + 16)
 
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
new file mode 100644
index 000000000000..fc40d3ab8c5b
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -0,0 +1,200 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This contains hardware definitions that are common between i.MX21 and
+ * i.MX27.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_MX2x_H__
+#define __ASM_ARCH_MXC_MX2x_H__
+
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#error "Do not include directly."
+#endif
+
+/* The following addresses are common between i.MX21 and i.MX27 */
+
+/* Register offests */
+#define AIPI_BASE_ADDR          0x10000000
+#define AIPI_BASE_ADDR_VIRT     0xF4000000
+#define AIPI_SIZE               SZ_1M
+
+#define DMA_BASE_ADDR           (AIPI_BASE_ADDR + 0x01000)
+#define WDOG_BASE_ADDR          (AIPI_BASE_ADDR + 0x02000)
+#define GPT1_BASE_ADDR          (AIPI_BASE_ADDR + 0x03000)
+#define GPT2_BASE_ADDR          (AIPI_BASE_ADDR + 0x04000)
+#define GPT3_BASE_ADDR          (AIPI_BASE_ADDR + 0x05000)
+#define PWM_BASE_ADDR           (AIPI_BASE_ADDR + 0x06000)
+#define RTC_BASE_ADDR           (AIPI_BASE_ADDR + 0x07000)
+#define KPP_BASE_ADDR           (AIPI_BASE_ADDR + 0x08000)
+#define OWIRE_BASE_ADDR         (AIPI_BASE_ADDR + 0x09000)
+#define UART1_BASE_ADDR         (AIPI_BASE_ADDR + 0x0A000)
+#define UART2_BASE_ADDR         (AIPI_BASE_ADDR + 0x0B000)
+#define UART3_BASE_ADDR         (AIPI_BASE_ADDR + 0x0C000)
+#define UART4_BASE_ADDR         (AIPI_BASE_ADDR + 0x0D000)
+#define CSPI1_BASE_ADDR         (AIPI_BASE_ADDR + 0x0E000)
+#define CSPI2_BASE_ADDR         (AIPI_BASE_ADDR + 0x0F000)
+#define SSI1_BASE_ADDR          (AIPI_BASE_ADDR + 0x10000)
+#define SSI2_BASE_ADDR          (AIPI_BASE_ADDR + 0x11000)
+#define I2C_BASE_ADDR           (AIPI_BASE_ADDR + 0x12000)
+#define SDHC1_BASE_ADDR         (AIPI_BASE_ADDR + 0x13000)
+#define SDHC2_BASE_ADDR         (AIPI_BASE_ADDR + 0x14000)
+#define GPIO_BASE_ADDR          (AIPI_BASE_ADDR + 0x15000)
+#define AUDMUX_BASE_ADDR        (AIPI_BASE_ADDR + 0x16000)
+#define CSPI3_BASE_ADDR         (AIPI_BASE_ADDR + 0x17000)
+#define LCDC_BASE_ADDR          (AIPI_BASE_ADDR + 0x21000)
+#define SLCDC_BASE_ADDR         (AIPI_BASE_ADDR + 0x22000)
+#define USBOTG_BASE_ADDR        (AIPI_BASE_ADDR + 0x24000)
+#define EMMA_PP_BASE_ADDR       (AIPI_BASE_ADDR + 0x26000)
+#define EMMA_PRP_BASE_ADDR      (AIPI_BASE_ADDR + 0x26400)
+#define CCM_BASE_ADDR           (AIPI_BASE_ADDR + 0x27000)
+#define SYSCTRL_BASE_ADDR       (AIPI_BASE_ADDR + 0x27800)
+#define JAM_BASE_ADDR           (AIPI_BASE_ADDR + 0x3E000)
+#define MAX_BASE_ADDR           (AIPI_BASE_ADDR + 0x3F000)
+
+#define AVIC_BASE_ADDR          0x10040000
+
+#define SAHB1_BASE_ADDR         0x80000000
+#define SAHB1_BASE_ADDR_VIRT    0xF4100000
+#define SAHB1_SIZE              SZ_1M
+
+#define CSI_BASE_ADDR           (SAHB1_BASE_ADDR + 0x0000)
+
+/*
+ * This macro defines the physical to virtual address mapping for all the
+ * peripheral modules. It is used by passing in the physical address as x
+ * and returning the virtual address. If the physical address is not mapped,
+ * it returns 0xDEADBEEF
+ */
+#define IO_ADDRESS(x)   \
+        (void __force __iomem *) \
+        (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
+                AIPI_IO_ADDRESS(x) : \
+        ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
+                SAHB1_IO_ADDRESS(x) : \
+        ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
+                X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
+
+/* define the address mapping macros: in physical address order */
+#define AIPI_IO_ADDRESS(x)  \
+        (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
+
+#define AVIC_IO_ADDRESS(x)      AIPI_IO_ADDRESS(x)
+
+#define SAHB1_IO_ADDRESS(x)  \
+        (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
+
+#define CS4_IO_ADDRESS(x)  \
+        (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
+
+#define X_MEMC_IO_ADDRESS(x)  \
+        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+
+#define PCMCIA_IO_ADDRESS(x) \
+        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+
+/* fixed interrupt numbers */
+#define MXC_INT_LCDC            61
+#define MXC_INT_SLCDC           60
+#define MXC_INT_EMMAPP          52
+#define MXC_INT_EMMAPRP         51
+#define MXC_INT_DMACH15         47
+#define MXC_INT_DMACH14         46
+#define MXC_INT_DMACH13         45
+#define MXC_INT_DMACH12         44
+#define MXC_INT_DMACH11         43
+#define MXC_INT_DMACH10         42
+#define MXC_INT_DMACH9          41
+#define MXC_INT_DMACH8          40
+#define MXC_INT_DMACH7          39
+#define MXC_INT_DMACH6          38
+#define MXC_INT_DMACH5          37
+#define MXC_INT_DMACH4          36
+#define MXC_INT_DMACH3          35
+#define MXC_INT_DMACH2          34
+#define MXC_INT_DMACH1          33
+#define MXC_INT_DMACH0          32
+#define MXC_INT_CSI             31
+#define MXC_INT_NANDFC          29
+#define MXC_INT_PCMCIA          28
+#define MXC_INT_WDOG            27
+#define MXC_INT_GPT1            26
+#define MXC_INT_GPT2            25
+#define MXC_INT_GPT3            24
+#define MXC_INT_GPT             INT_GPT1
+#define MXC_INT_PWM             23
+#define MXC_INT_RTC             22
+#define MXC_INT_KPP             21
+#define MXC_INT_UART1           20
+#define MXC_INT_UART2           19
+#define MXC_INT_UART3           18
+#define MXC_INT_UART4           17
+#define MXC_INT_CSPI1           16
+#define MXC_INT_CSPI2           15
+#define MXC_INT_SSI1            14
+#define MXC_INT_SSI2            13
+#define MXC_INT_I2C             12
+#define MXC_INT_SDHC1           11
+#define MXC_INT_SDHC2           10
+#define MXC_INT_GPIO            8
+#define MXC_INT_CSPI3           6
+
+/* gpio and gpio based interrupt handling */
+#define GPIO_DR                 0x1C
+#define GPIO_GDIR               0x00
+#define GPIO_PSR                0x24
+#define GPIO_ICR1               0x28
+#define GPIO_ICR2               0x2C
+#define GPIO_IMR                0x30
+#define GPIO_ISR                0x34
+#define GPIO_INT_LOW_LEV        0x3
+#define GPIO_INT_HIGH_LEV       0x2
+#define GPIO_INT_RISE_EDGE      0x0
+#define GPIO_INT_FALL_EDGE      0x1
+#define GPIO_INT_NONE           0x4
+
+/* fixed DMA request numbers */
+#define DMA_REQ_CSI_RX          31
+#define DMA_REQ_CSI_STAT        30
+#define DMA_REQ_UART1_TX        27
+#define DMA_REQ_UART1_RX        26
+#define DMA_REQ_UART2_TX        25
+#define DMA_REQ_UART2_RX        24
+#define DMA_REQ_UART3_TX        23
+#define DMA_REQ_UART3_RX        22
+#define DMA_REQ_UART4_TX        21
+#define DMA_REQ_UART4_RX        20
+#define DMA_REQ_CSPI1_TX        19
+#define DMA_REQ_CSPI1_RX        18
+#define DMA_REQ_CSPI2_TX        17
+#define DMA_REQ_CSPI2_RX        16
+#define DMA_REQ_SSI1_TX1        15
+#define DMA_REQ_SSI1_RX1        14
+#define DMA_REQ_SSI1_TX0        13
+#define DMA_REQ_SSI1_RX0        12
+#define DMA_REQ_SSI2_TX1        11
+#define DMA_REQ_SSI2_RX1        10
+#define DMA_REQ_SSI2_TX0        9
+#define DMA_REQ_SSI2_RX0        8
+#define DMA_REQ_SDHC1           7
+#define DMA_REQ_SDHC2           6
+#define DMA_REQ_EXT             3
+#define DMA_REQ_CSPI3_TX        2
+#define DMA_REQ_CSPI3_RX        1
+
+#endif /* __ASM_ARCH_MXC_MX2x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index de026654b00e..0b06941b6139 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -1,360 +1,45 @@
 /*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_MX31_H__
-#define __ASM_ARCH_MXC_MX31_H__
-
-#ifndef __ASM_ARCH_MXC_HARDWARE_H__
-#error "Do not include directly."
-#endif
-
-/*
- * MX31 memory map:
- *
- * Virt         Phys            Size    What
- * ---------------------------------------------------------------------------
- * F8000000     1FFC0000        16K     IRAM
- * F9000000     30000000        256M    L2CC
- * FC000000     43F00000        1M      AIPS 1
- * FC100000     50000000        1M      SPBA
- * FC200000     53F00000        1M      AIPS 2
- * FC500000     60000000        128M    ROMPATCH
- * FC400000     68000000        128M    AVIC
- *              70000000        256M    IPU (MAX M2)
- *              80000000        256M    CSD0 SDRAM/DDR
- *              90000000        256M    CSD1 SDRAM/DDR
- *              A0000000        128M    CS0 Flash
- *              A8000000        128M    CS1 Flash
- *              B0000000        32M     CS2
- *              B2000000        32M     CS3
- * F4000000     B4000000        32M     CS4
- *              B6000000        32M     CS5
- * FC320000     B8000000        64K     NAND, SDRAM, WEIM, M3IF, EMI controllers
- *              C0000000        64M     PCMCIA/CF
- */
-
-#define CS0_BASE_ADDR           0xA0000000
-#define CS1_BASE_ADDR           0xA8000000
-#define CS2_BASE_ADDR           0xB0000000
-#define CS3_BASE_ADDR           0xB2000000
-
-#define CS4_BASE_ADDR           0xB4000000
-#define CS4_BASE_ADDR_VIRT      0xF4000000
-#define CS4_SIZE                SZ_32M
-
-#define CS5_BASE_ADDR           0xB6000000
-#define PCMCIA_MEM_BASE_ADDR    0xBC000000
-
-/*
  * IRAM
  */
-#define IRAM_BASE_ADDR          0x1FFC0000      /* internal ram */
-#define IRAM_BASE_ADDR_VIRT     0xF8000000
-#define IRAM_SIZE               SZ_16K
-
-/*
- * L2CC
- */
-#define L2CC_BASE_ADDR          0x30000000
-#define L2CC_BASE_ADDR_VIRT     0xF9000000
-#define L2CC_SIZE               SZ_1M
-
-/*
- * AIPS 1
- */
-#define AIPS1_BASE_ADDR         0x43F00000
-#define AIPS1_BASE_ADDR_VIRT    0xFC000000
-#define AIPS1_SIZE              SZ_1M
+#define MX31_IRAM_BASE_ADDR             0x1FFC0000      /* internal ram */
+#define MX31_IRAM_SIZE                  SZ_16K
 
-#define MAX_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00004000)
-#define EVTMON_BASE_ADDR        (AIPS1_BASE_ADDR + 0x00008000)
-#define CLKCTL_BASE_ADDR        (AIPS1_BASE_ADDR + 0x0000C000)
-#define ETB_SLOT4_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00010000)
-#define ETB_SLOT5_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00014000)
-#define ECT_CTIO_BASE_ADDR      (AIPS1_BASE_ADDR + 0x00018000)
-#define I2C_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00080000)
-#define I2C3_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00084000)
 #define OTG_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00088000)
 #define ATA_BASE_ADDR           (AIPS1_BASE_ADDR + 0x0008C000)
-#define UART1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00090000)
-#define UART2_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00094000)
-#define I2C2_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00098000)
-#define OWIRE_BASE_ADDR         (AIPS1_BASE_ADDR + 0x0009C000)
-#define SSI1_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000A0000)
-#define CSPI1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000A4000)
-#define KPP_BASE_ADDR           (AIPS1_BASE_ADDR + 0x000A8000)
-#define IOMUXC_BASE_ADDR        (AIPS1_BASE_ADDR + 0x000AC000)
 #define UART4_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B0000)
 #define UART5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B4000)
-#define ECT_IP1_BASE_ADDR       (AIPS1_BASE_ADDR + 0x000B8000)
-#define ECT_IP2_BASE_ADDR       (AIPS1_BASE_ADDR + 0x000BC000)
-
-/*
- * SPBA global module enabled #0
- */
-#define SPBA0_BASE_ADDR         0x50000000
-#define SPBA0_BASE_ADDR_VIRT    0xFC100000
-#define SPBA0_SIZE              SZ_1M
 
 #define MMC_SDHC1_BASE_ADDR     (SPBA0_BASE_ADDR + 0x00004000)
 #define MMC_SDHC2_BASE_ADDR     (SPBA0_BASE_ADDR + 0x00008000)
-#define UART3_BASE_ADDR         (SPBA0_BASE_ADDR + 0x0000C000)
-#define CSPI2_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00010000)
-#define SSI2_BASE_ADDR          (SPBA0_BASE_ADDR + 0x00014000)
 #define SIM1_BASE_ADDR          (SPBA0_BASE_ADDR + 0x00018000)
 #define IIM_BASE_ADDR           (SPBA0_BASE_ADDR + 0x0001C000)
-#define ATA_DMA_BASE_ADDR       (SPBA0_BASE_ADDR + 0x00020000)
-#define MSHC1_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00024000)
-#define MSHC2_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00024000)
-#define SPBA_CTRL_BASE_ADDR     (SPBA0_BASE_ADDR + 0x0003C000)
 
-/*
- * AIPS 2
- */
-#define AIPS2_BASE_ADDR         0x53F00000
-#define AIPS2_BASE_ADDR_VIRT    0xFC200000
-#define AIPS2_SIZE              SZ_1M
-#define CCM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x00080000)
 #define CSPI3_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00084000)
 #define FIRI_BASE_ADDR          (AIPS2_BASE_ADDR + 0x0008C000)
-#define GPT1_BASE_ADDR          (AIPS2_BASE_ADDR + 0x00090000)
-#define EPIT1_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00094000)
-#define EPIT2_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00098000)
-#define GPIO3_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000A4000)
-#define SCC_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000AC000)
 #define SCM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000AE000)
 #define SMN_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000AF000)
-#define RNGA_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000B0000)
-#define IPU_CTRL_BASE_ADDR      (AIPS2_BASE_ADDR + 0x000C0000)
-#define AUDMUX_BASE_ADDR        (AIPS2_BASE_ADDR + 0x000C4000)
 #define MPEG4_ENC_BASE_ADDR     (AIPS2_BASE_ADDR + 0x000C8000)
-#define GPIO1_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000CC000)
-#define GPIO2_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000D0000)
-#define SDMA_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000D4000)
-#define RTC_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000D8000)
-#define WDOG_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000DC000)
-#define PWM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000E0000)
-#define RTIC_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000EC000)
-
-/*
- * ROMP and AVIC
- */
-#define ROMP_BASE_ADDR          0x60000000
-#define ROMP_BASE_ADDR_VIRT     0xFC500000
-#define ROMP_SIZE               SZ_1M
-
-#define AVIC_BASE_ADDR          0x68000000
-#define AVIC_BASE_ADDR_VIRT     0xFC400000
-#define AVIC_SIZE               SZ_1M
-
-/*
- * NAND, SDRAM, WEIM, M3IF, EMI controllers
- */
-#define X_MEMC_BASE_ADDR        0xB8000000
-#define X_MEMC_BASE_ADDR_VIRT   0xFC320000
-#define X_MEMC_SIZE             SZ_64K
 
-#define NFC_BASE_ADDR           (X_MEMC_BASE_ADDR + 0x0000)
-#define ESDCTL_BASE_ADDR        (X_MEMC_BASE_ADDR + 0x1000)
-#define WEIM_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x2000)
-#define M3IF_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x3000)
-#define EMI_CTL_BASE_ADDR       (X_MEMC_BASE_ADDR + 0x4000)
-#define PCMCIA_CTL_BASE_ADDR    EMI_CTL_BASE_ADDR
+#define MX31_NFC_BASE_ADDR      (X_MEMC_BASE_ADDR + 0x0000)
 
-/*
- * Memory regions and CS
- */
-#define IPU_MEM_BASE_ADDR       0x70000000
-#define CSD0_BASE_ADDR          0x80000000
-#define CSD1_BASE_ADDR          0x90000000
-#define CS0_BASE_ADDR           0xA0000000
-#define CS1_BASE_ADDR           0xA8000000
-#define CS2_BASE_ADDR           0xB0000000
-#define CS3_BASE_ADDR           0xB2000000
-
-#define CS4_BASE_ADDR           0xB4000000
-#define CS4_BASE_ADDR_VIRT      0xF4000000
-#define CS4_SIZE                SZ_32M
-
-#define CS5_BASE_ADDR           0xB6000000
-#define PCMCIA_MEM_BASE_ADDR    0xBC000000
-
-/*!
- * This macro defines the physical to virtual address mapping for all the
- * peripheral modules. It is used by passing in the physical address as x
- * and returning the virtual address. If the physical address is not mapped,
- * it returns 0xDEADBEEF
- */
-#define IO_ADDRESS(x)   \
-        (void __iomem *) \
-        (((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\
-        ((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\
-        ((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
-        ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
-        ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
-        ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
-        ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
-        ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
-        ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
-        0xDEADBEEF)
-
-/*
- * define the address mapping macros: in physical address order
- */
-
-#define IRAM_IO_ADDRESS(x)  \
-        (((x) - IRAM_BASE_ADDR) + IRAM_BASE_ADDR_VIRT)
-
-#define L2CC_IO_ADDRESS(x)  \
-        (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
-
-#define AIPS1_IO_ADDRESS(x)  \
-        (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
-
-#define SPBA0_IO_ADDRESS(x)  \
-        (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
-
-#define AIPS2_IO_ADDRESS(x)  \
-        (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
-
-#define ROMP_IO_ADDRESS(x)  \
-        (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
-
-#define AVIC_IO_ADDRESS(x)  \
-        (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
-
-#define CS4_IO_ADDRESS(x)  \
-        (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
-
-#define X_MEMC_IO_ADDRESS(x)  \
-        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
-
-#define PCMCIA_IO_ADDRESS(x) \
-        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
-
-/*
- * Interrupt numbers
- */
-#define MXC_INT_PEN_ADS7843     0
-#define MXC_INT_RESV1           1
-#define MXC_INT_CS8900A         2
-#define MXC_INT_I2C3            3
-#define MXC_INT_I2C2            4
 #define MXC_INT_MPEG4_ENCODER   5
-#define MXC_INT_RTIC            6
 #define MXC_INT_FIRI            7
-#define MXC_INT_MMC_SDHC2       8
+#define MX31_INT_MMC_SDHC2      8
 #define MXC_INT_MMC_SDHC1       9
-#define MXC_INT_I2C             10
-#define MXC_INT_SSI2            11
-#define MXC_INT_SSI1            12
-#define MXC_INT_CSPI2           13
-#define MXC_INT_CSPI1           14
-#define MXC_INT_ATA             15
+#define MX31_INT_SSI2           11
+#define MX31_INT_SSI1           12
 #define MXC_INT_MBX             16
 #define MXC_INT_CSPI3           17
-#define MXC_INT_UART3           18
-#define MXC_INT_IIM             19
 #define MXC_INT_SIM2            20
 #define MXC_INT_SIM1            21
-#define MXC_INT_RNGA            22
-#define MXC_INT_EVTMON          23
-#define MXC_INT_KPP             24
-#define MXC_INT_RTC             25
-#define MXC_INT_PWM             26
-#define MXC_INT_EPIT2           27
-#define MXC_INT_EPIT1           28
-#define MXC_INT_GPT             29
-#define MXC_INT_RESV30          30
-#define MXC_INT_RESV31          31
-#define MXC_INT_UART2           32
-#define MXC_INT_NANDFC          33
-#define MXC_INT_SDMA            34
+#define MXC_INT_CCM_DVFS        31
 #define MXC_INT_USB1            35
 #define MXC_INT_USB2            36
 #define MXC_INT_USB3            37
 #define MXC_INT_USB4            38
-#define MXC_INT_MSHC1           39
 #define MXC_INT_MSHC2           40
-#define MXC_INT_IPU_ERR         41
-#define MXC_INT_IPU_SYN         42
-#define MXC_INT_RESV43          43
-#define MXC_INT_RESV44          44
-#define MXC_INT_UART1           45
 #define MXC_INT_UART4           46
 #define MXC_INT_UART5           47
-#define MXC_INT_ECT             48
-#define MXC_INT_SCC_SCM         49
-#define MXC_INT_SCC_SMN         50
-#define MXC_INT_GPIO2           51
-#define MXC_INT_GPIO1           52
 #define MXC_INT_CCM             53
 #define MXC_INT_PCMCIA          54
-#define MXC_INT_WDOG            55
-#define MXC_INT_GPIO3           56
-#define MXC_INT_RESV57          57
-#define MXC_INT_EXT_POWER       58
-#define MXC_INT_EXT_TEMPER      59
-#define MXC_INT_EXT_SENSOR60    60
-#define MXC_INT_EXT_SENSOR61    61
-#define MXC_INT_EXT_WDOG        62
-#define MXC_INT_EXT_TV          63
-
-#define PROD_SIGNATURE          0x1     /* For MX31 */
-
-/* silicon revisions specific to i.MX31 */
-#define CHIP_REV_1_0            0x10
-#define CHIP_REV_1_1            0x11
-#define CHIP_REV_1_2            0x12
-#define CHIP_REV_1_3            0x13
-#define CHIP_REV_2_0            0x20
-#define CHIP_REV_2_1            0x21
-#define CHIP_REV_2_2            0x22
-#define CHIP_REV_2_3            0x23
-#define CHIP_REV_3_0            0x30
-#define CHIP_REV_3_1            0x31
-#define CHIP_REV_3_2            0x32
-
-#define SYSTEM_REV_MIN          CHIP_REV_1_0
-#define SYSTEM_REV_NUM          3
-
-/* gpio and gpio based interrupt handling */
-#define GPIO_DR                 0x00
-#define GPIO_GDIR               0x04
-#define GPIO_PSR                0x08
-#define GPIO_ICR1               0x0C
-#define GPIO_ICR2               0x10
-#define GPIO_IMR                0x14
-#define GPIO_ISR                0x18
-#define GPIO_INT_LOW_LEV        0x0
-#define GPIO_INT_HIGH_LEV       0x1
-#define GPIO_INT_RISE_EDGE      0x2
-#define GPIO_INT_FALL_EDGE      0x3
-#define GPIO_INT_NONE           0x4
-
-/* Mandatory defines used globally */
-
-/* this CPU supports up to 96 GPIOs */
-#define ARCH_NR_GPIOS           96
-
-#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
-
-/* this is a i.MX31 CPU */
-#define cpu_is_mx31()           (1)
-
-extern unsigned int system_rev;
-
-static inline int mx31_revision(void)
-{
-        return system_rev;
-}
-#endif
 
-#endif /*  __ASM_ARCH_MXC_MX31_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
new file mode 100644
index 000000000000..6465fefb42e3
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -0,0 +1,29 @@
+/*
+ * IRAM
+ */
+#define MX35_IRAM_BASE_ADDR             0x10000000      /* internal ram */
+#define MX35_IRAM_SIZE          SZ_128K
+
+#define MXC_FEC_BASE_ADDR       0x50038000
+#define MX35_NFC_BASE_ADDR      0xBB000000
+
+/*
+ * Interrupt numbers
+ */
+#define MXC_INT_OWIRE           2
+#define MX35_INT_MMC_SDHC1      7
+#define MXC_INT_MMC_SDHC2       8
+#define MXC_INT_MMC_SDHC3       9
+#define MX35_INT_SSI1           11
+#define MX35_INT_SSI2           12
+#define MXC_INT_GPU2D           16
+#define MXC_INT_ASRC            17
+#define MXC_INT_USBHS           35
+#define MXC_INT_USBOTG          37
+#define MXC_INT_ESAI            40
+#define MXC_INT_CAN1            43
+#define MXC_INT_CAN2            44
+#define MXC_INT_MLB             46
+#define MXC_INT_SPDIF           47
+#define MXC_INT_FEC             57
+
diff --git a/arch/arm/plat-mxc/include/mach/mx3fb.h b/arch/arm/plat-mxc/include/mach/mx3fb.h
index e391a76ca87d..ac24c5c4bc83 100644
--- a/arch/arm/plat-mxc/include/mach/mx3fb.h
+++ b/arch/arm/plat-mxc/include/mach/mx3fb.h
@@ -14,25 +14,25 @@
 #include <linux/fb.h>
 
 /* Proprietary FB_SYNC_ flags */
-#define FB_SYNC_OE_ACT_HIGH    0x80000000
-#define FB_SYNC_CLK_INVERT     0x40000000
-#define FB_SYNC_DATA_INVERT    0x20000000
-#define FB_SYNC_CLK_IDLE_EN    0x10000000
-#define FB_SYNC_SHARP_MODE     0x08000000
-#define FB_SYNC_SWAP_RGB       0x04000000
-#define FB_SYNC_CLK_SEL_EN     0x02000000
+#define FB_SYNC_OE_ACT_HIGH     0x80000000
+#define FB_SYNC_CLK_INVERT      0x40000000
+#define FB_SYNC_DATA_INVERT     0x20000000
+#define FB_SYNC_CLK_IDLE_EN     0x10000000
+#define FB_SYNC_SHARP_MODE      0x08000000
+#define FB_SYNC_SWAP_RGB        0x04000000
+#define FB_SYNC_CLK_SEL_EN      0x02000000
 
 /**
  * struct mx3fb_platform_data - mx3fb platform data
  *
- * @dma_dev:   pointer to the dma-device, used for dma-slave connection
- * @mode:      pointer to a platform-provided per mxc_register_fb() videomode
+ * @dma_dev:    pointer to the dma-device, used for dma-slave connection
+ * @mode:       pointer to a platform-provided per mxc_register_fb() videomode
  */
 struct mx3fb_platform_data {
-       struct device                   *dma_dev;
-       const char                      *name;
-       const struct fb_videomode       *mode;
-       int                             num_modes;
+        struct device                   *dma_dev;
+        const char                      *name;
+        const struct fb_videomode       *mode;
+        int                             num_modes;
 };
 
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
new file mode 100644
index 000000000000..3878c6085d5c
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -0,0 +1,290 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_MX31_H__
+#define __ASM_ARCH_MXC_MX31_H__
+
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#error "Do not include directly."
+#endif
+
+/*
+ * MX31 memory map:
+ *
+ * Virt         Phys            Size    What
+ * ---------------------------------------------------------------------------
+ * FC000000     43F00000        1M      AIPS 1
+ * FC100000     50000000        1M      SPBA
+ * FC200000     53F00000        1M      AIPS 2
+ * FC500000     60000000        128M    ROMPATCH
+ * FC400000     68000000        128M    AVIC
+ *              70000000        256M    IPU (MAX M2)
+ *              80000000        256M    CSD0 SDRAM/DDR
+ *              90000000        256M    CSD1 SDRAM/DDR
+ *              A0000000        128M    CS0 Flash
+ *              A8000000        128M    CS1 Flash
+ *              B0000000        32M     CS2
+ *              B2000000        32M     CS3
+ * F4000000     B4000000        32M     CS4
+ *              B6000000        32M     CS5
+ * FC320000     B8000000        64K     NAND, SDRAM, WEIM, M3IF, EMI controllers
+ *              C0000000        64M     PCMCIA/CF
+ */
+
+#define CS0_BASE_ADDR           0xA0000000
+#define CS1_BASE_ADDR           0xA8000000
+#define CS2_BASE_ADDR           0xB0000000
+#define CS3_BASE_ADDR           0xB2000000
+
+#define CS4_BASE_ADDR           0xB4000000
+#define CS4_BASE_ADDR_VIRT      0xF4000000
+#define CS4_SIZE                SZ_32M
+
+#define CS5_BASE_ADDR           0xB6000000
+#define PCMCIA_MEM_BASE_ADDR    0xBC000000
+
+/*
+ * L2CC
+ */
+#define L2CC_BASE_ADDR          0x30000000
+#define L2CC_SIZE               SZ_1M
+
+/*
+ * AIPS 1
+ */
+#define AIPS1_BASE_ADDR         0x43F00000
+#define AIPS1_BASE_ADDR_VIRT    0xFC000000
+#define AIPS1_SIZE              SZ_1M
+
+#define MAX_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00004000)
+#define EVTMON_BASE_ADDR        (AIPS1_BASE_ADDR + 0x00008000)
+#define CLKCTL_BASE_ADDR        (AIPS1_BASE_ADDR + 0x0000C000)
+#define ETB_SLOT4_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00010000)
+#define ETB_SLOT5_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00014000)
+#define ECT_CTIO_BASE_ADDR      (AIPS1_BASE_ADDR + 0x00018000)
+#define I2C_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00080000)
+#define I2C3_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00084000)
+#define UART1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00090000)
+#define UART2_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00094000)
+#define I2C2_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00098000)
+#define OWIRE_BASE_ADDR         (AIPS1_BASE_ADDR + 0x0009C000)
+#define SSI1_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000A0000)
+#define CSPI1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000A4000)
+#define KPP_BASE_ADDR           (AIPS1_BASE_ADDR + 0x000A8000)
+#define IOMUXC_BASE_ADDR        (AIPS1_BASE_ADDR + 0x000AC000)
+#define ECT_IP1_BASE_ADDR       (AIPS1_BASE_ADDR + 0x000B8000)
+#define ECT_IP2_BASE_ADDR       (AIPS1_BASE_ADDR + 0x000BC000)
+
+/*
+ * SPBA global module enabled #0
+ */
+#define SPBA0_BASE_ADDR         0x50000000
+#define SPBA0_BASE_ADDR_VIRT    0xFC100000
+#define SPBA0_SIZE              SZ_1M
+
+#define UART3_BASE_ADDR         (SPBA0_BASE_ADDR + 0x0000C000)
+#define CSPI2_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00010000)
+#define SSI2_BASE_ADDR          (SPBA0_BASE_ADDR + 0x00014000)
+#define ATA_DMA_BASE_ADDR       (SPBA0_BASE_ADDR + 0x00020000)
+#define MSHC1_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00024000)
+#define SPBA_CTRL_BASE_ADDR     (SPBA0_BASE_ADDR + 0x0003C000)
+
+/*
+ * AIPS 2
+ */
+#define AIPS2_BASE_ADDR         0x53F00000
+#define AIPS2_BASE_ADDR_VIRT    0xFC200000
+#define AIPS2_SIZE              SZ_1M
+#define CCM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x00080000)
+#define GPT1_BASE_ADDR          (AIPS2_BASE_ADDR + 0x00090000)
+#define EPIT1_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00094000)
+#define EPIT2_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00098000)
+#define GPIO3_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000A4000)
+#define SCC_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000AC000)
+#define RNGA_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000B0000)
+#define IPU_CTRL_BASE_ADDR      (AIPS2_BASE_ADDR + 0x000C0000)
+#define AUDMUX_BASE_ADDR        (AIPS2_BASE_ADDR + 0x000C4000)
+#define GPIO1_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000CC000)
+#define GPIO2_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000D0000)
+#define SDMA_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000D4000)
+#define RTC_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000D8000)
+#define WDOG_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000DC000)
+#define PWM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000E0000)
+#define RTIC_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000EC000)
+
+/*
+ * ROMP and AVIC
+ */
+#define ROMP_BASE_ADDR          0x60000000
+#define ROMP_BASE_ADDR_VIRT     0xFC500000
+#define ROMP_SIZE               SZ_1M
+
+#define AVIC_BASE_ADDR          0x68000000
+#define AVIC_BASE_ADDR_VIRT     0xFC400000
+#define AVIC_SIZE               SZ_1M
+
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define X_MEMC_BASE_ADDR        0xB8000000
+#define X_MEMC_BASE_ADDR_VIRT   0xFC320000
+#define X_MEMC_SIZE             SZ_64K
+
+#define ESDCTL_BASE_ADDR        (X_MEMC_BASE_ADDR + 0x1000)
+#define WEIM_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x2000)
+#define M3IF_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x3000)
+#define EMI_CTL_BASE_ADDR       (X_MEMC_BASE_ADDR + 0x4000)
+#define PCMCIA_CTL_BASE_ADDR    EMI_CTL_BASE_ADDR
+
+/*
+ * Memory regions and CS
+ */
+#define IPU_MEM_BASE_ADDR       0x70000000
+#define CSD0_BASE_ADDR          0x80000000
+#define CSD1_BASE_ADDR          0x90000000
+
+/*!
+ * This macro defines the physical to virtual address mapping for all the
+ * peripheral modules. It is used by passing in the physical address as x
+ * and returning the virtual address. If the physical address is not mapped,
+ * it returns 0xDEADBEEF
+ */
+#define IO_ADDRESS(x)   \
+        (void __force __iomem *) \
+        (((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
+        ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
+        ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
+        ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
+        ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
+        ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
+        ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
+        0xDEADBEEF)
+
+/*
+ * define the address mapping macros: in physical address order
+ */
+#define L2CC_IO_ADDRESS(x)  \
+        (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
+
+#define AIPS1_IO_ADDRESS(x)  \
+        (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
+
+#define SPBA0_IO_ADDRESS(x)  \
+        (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
+
+#define AIPS2_IO_ADDRESS(x)  \
+        (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
+
+#define ROMP_IO_ADDRESS(x)  \
+        (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
+
+#define AVIC_IO_ADDRESS(x)  \
+        (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
+
+#define CS4_IO_ADDRESS(x)  \
+        (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
+
+#define X_MEMC_IO_ADDRESS(x)  \
+        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+
+#define PCMCIA_IO_ADDRESS(x) \
+        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+
+/*
+ * Interrupt numbers
+ */
+#define MXC_INT_I2C3            3
+#define MXC_INT_I2C2            4
+#define MXC_INT_RTIC            6
+#define MXC_INT_I2C             10
+#define MXC_INT_CSPI2           13
+#define MXC_INT_CSPI1           14
+#define MXC_INT_ATA             15
+#define MXC_INT_UART3           18
+#define MXC_INT_IIM             19
+#define MXC_INT_RNGA            22
+#define MXC_INT_EVTMON          23
+#define MXC_INT_KPP             24
+#define MXC_INT_RTC             25
+#define MXC_INT_PWM             26
+#define MXC_INT_EPIT2           27
+#define MXC_INT_EPIT1           28
+#define MXC_INT_GPT             29
+#define MXC_INT_POWER_FAIL      30
+#define MXC_INT_UART2           32
+#define MXC_INT_NANDFC          33
+#define MXC_INT_SDMA            34
+#define MXC_INT_MSHC1           39
+#define MXC_INT_IPU_ERR         41
+#define MXC_INT_IPU_SYN         42
+#define MXC_INT_UART1           45
+#define MXC_INT_ECT             48
+#define MXC_INT_SCC_SCM         49
+#define MXC_INT_SCC_SMN         50
+#define MXC_INT_GPIO2           51
+#define MXC_INT_GPIO1           52
+#define MXC_INT_WDOG            55
+#define MXC_INT_GPIO3           56
+#define MXC_INT_EXT_POWER       58
+#define MXC_INT_EXT_TEMPER      59
+#define MXC_INT_EXT_SENSOR60    60
+#define MXC_INT_EXT_SENSOR61    61
+#define MXC_INT_EXT_WDOG        62
+#define MXC_INT_EXT_TV          63
+
+#define PROD_SIGNATURE          0x1     /* For MX31 */
+
+/* silicon revisions specific to i.MX31 */
+#define CHIP_REV_1_0            0x10
+#define CHIP_REV_1_1            0x11
+#define CHIP_REV_1_2            0x12
+#define CHIP_REV_1_3            0x13
+#define CHIP_REV_2_0            0x20
+#define CHIP_REV_2_1            0x21
+#define CHIP_REV_2_2            0x22
+#define CHIP_REV_2_3            0x23
+#define CHIP_REV_3_0            0x30
+#define CHIP_REV_3_1            0x31
+#define CHIP_REV_3_2            0x32
+
+#define SYSTEM_REV_MIN          CHIP_REV_1_0
+#define SYSTEM_REV_NUM          3
+
+/* gpio and gpio based interrupt handling */
+#define GPIO_DR                 0x00
+#define GPIO_GDIR               0x04
+#define GPIO_PSR                0x08
+#define GPIO_ICR1               0x0C
+#define GPIO_ICR2               0x10
+#define GPIO_IMR                0x14
+#define GPIO_ISR                0x18
+#define GPIO_INT_LOW_LEV        0x0
+#define GPIO_INT_HIGH_LEV       0x1
+#define GPIO_INT_RISE_EDGE      0x2
+#define GPIO_INT_FALL_EDGE      0x3
+#define GPIO_INT_NONE           0x4
+
+/* Mandatory defines used globally */
+
+/* this CPU supports up to 96 GPIOs */
+#define ARCH_NR_GPIOS           96
+
+#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
+
+extern unsigned int system_rev;
+
+static inline int mx31_revision(void)
+{
+        return system_rev;
+}
+#endif
+
+#endif /*  __ASM_ARCH_MXC_MX31_H__ */
+
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index f6caab062131..5fa2a07f4eaf 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -24,13 +24,74 @@
 #error "Do not include directly."
 #endif
 
-/* clean up all things that are not used */
-#ifndef CONFIG_ARCH_MX3
-# define cpu_is_mx31() (0)
+#define MXC_CPU_MX1             1
+#define MXC_CPU_MX21            21
+#define MXC_CPU_MX27            27
+#define MXC_CPU_MX31            31
+#define MXC_CPU_MX35            35
+
+#ifndef __ASSEMBLY__
+extern unsigned int __mxc_cpu_type;
+#endif
+
+#ifdef CONFIG_ARCH_MX1
+# ifdef mxc_cpu_type
+#  undef mxc_cpu_type
+#  define mxc_cpu_type __mxc_cpu_type
+# else
+#  define mxc_cpu_type MXC_CPU_MX1
+# endif
+# define cpu_is_mx1()           (mxc_cpu_type == MXC_CPU_MX1)
+#else
+# define cpu_is_mx1()           (0)
+#endif
+
+#ifdef CONFIG_MACH_MX21
+# ifdef mxc_cpu_type
+#  undef mxc_cpu_type
+#  define mxc_cpu_type __mxc_cpu_type
+# else
+#  define mxc_cpu_type MXC_CPU_MX21
+# endif
+# define cpu_is_mx21()          (mxc_cpu_type == MXC_CPU_MX21)
+#else
+# define cpu_is_mx21()          (0)
 #endif
 
-#ifndef CONFIG_MACH_MX27
-# define cpu_is_mx27() (0)
+#ifdef CONFIG_MACH_MX27
+# ifdef mxc_cpu_type
+#  undef mxc_cpu_type
+#  define mxc_cpu_type __mxc_cpu_type
+# else
+#  define mxc_cpu_type MXC_CPU_MX27
+# endif
+# define cpu_is_mx27()          (mxc_cpu_type == MXC_CPU_MX27)
+#else
+# define cpu_is_mx27()          (0)
+#endif
+
+#ifdef CONFIG_ARCH_MX31
+# ifdef mxc_cpu_type
+#  undef mxc_cpu_type
+#  define mxc_cpu_type __mxc_cpu_type
+# else
+#  define mxc_cpu_type MXC_CPU_MX31
+# endif
+# define cpu_is_mx31()          (mxc_cpu_type == MXC_CPU_MX31)
+#else
+# define cpu_is_mx31()          (0)
+#endif
+
+#ifdef CONFIG_ARCH_MX35
+# ifdef mxc_cpu_type
+#  undef mxc_cpu_type
+#  define mxc_cpu_type __mxc_cpu_type
+# else
+#  define mxc_cpu_type MXC_CPU_MX35
+# endif
+# define cpu_is_mx35()          (mxc_cpu_type == MXC_CPU_MX35)
+#else
+# define cpu_is_mx35()          (0)
 #endif
 
 #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
@@ -39,4 +100,7 @@
 #define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8)
 #endif
 
+#define cpu_is_mx3()    (cpu_is_mx31() || cpu_is_mx35())
+#define cpu_is_mx2()    (cpu_is_mx21() || cpu_is_mx27())
+
 #endif /*  __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index bbfc37465fc5..e56241af870e 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -26,9 +26,6 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-static inline void arch_reset(char mode)
-{
-        cpu_reset(0);
-}
+void arch_reset(char mode, const char *cmd);
 
 #endif /* __ASM_ARCH_MXC_SYSTEM_H__ */
diff --git a/arch/arm/plat-mxc/iomux-mx1-mx2.c b/arch/arm/plat-mxc/iomux-mx1-mx2.c
index df6f18395686..a37163ce280b 100644
--- a/arch/arm/plat-mxc/iomux-mx1-mx2.c
+++ b/arch/arm/plat-mxc/iomux-mx1-mx2.c
@@ -32,7 +32,7 @@
 
 #include <mach/hardware.h>
 #include <asm/mach/map.h>
-#include <mach/iomux-mx1-mx2.h>
+#include <mach/iomux.h>
 
 void mxc_gpio_mode(int gpio_mode)
 {
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
new file mode 100644
index 000000000000..9bffbc507cc2
--- /dev/null
+++ b/arch/arm/plat-mxc/pwm.c
@@ -0,0 +1,300 @@
+/*
+ * simple driver for PWM (Pulse Width Modulator) controller
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/pwm.h>
+
+#if defined CONFIG_ARCH_MX1 || defined CONFIG_ARCH_MX21
+#define PWM_VER_1
+
+#define PWMCR   0x00    /* PWM Control Register         */
+#define PWMSR   0x04    /* PWM Sample Register          */
+#define PWMPR   0x08    /* PWM Period Register          */
+#define PWMCNR  0x0C    /* PWM Counter Register         */
+
+#define PWMCR_HCTR              (1 << 18)               /* Halfword FIFO Data Swapping  */
+#define PWMCR_BCTR              (1 << 17)               /* Byte FIFO Data Swapping      */
+#define PWMCR_SWR               (1 << 16)               /* Software Reset               */
+#define PWMCR_CLKSRC_PERCLK     (0 << 15)               /* PERCLK Clock Source          */
+#define PWMCR_CLKSRC_CLK32      (1 << 15)               /* 32KHz Clock Source           */
+#define PWMCR_PRESCALER(x)      (((x - 1) & 0x7F) << 8) /* PRESCALER                    */
+#define PWMCR_IRQ               (1 << 7)                /* Interrupt Request            */
+#define PWMCR_IRQEN             (1 << 6)                /* Interrupt Request Enable     */
+#define PWMCR_FIFOAV            (1 << 5)                /* FIFO Available               */
+#define PWMCR_EN                (1 << 4)                /* Enables/Disables the PWM     */
+#define PWMCR_REPEAT(x)         (((x) & 0x03) << 2)     /* Sample Repeats               */
+#define PWMCR_DIV(x)            (((x) & 0x03) << 0)     /* Clock divider 2/4/8/16       */
+
+#define MAX_DIV                 (128 * 16)
+#endif
+
+#if defined CONFIG_MACH_MX27 || defined CONFIG_ARCH_MX31
+#define PWM_VER_2
+
+#define PWMCR   0x00    /* PWM Control Register         */
+#define PWMSR   0x04    /* PWM Status Register          */
+#define PWMIR   0x08    /* PWM Interrupt Register       */
+#define PWMSAR  0x0C    /* PWM Sample Register          */
+#define PWMPR   0x10    /* PWM Period Register          */
+#define PWMCNR  0x14    /* PWM Counter Register         */
+
+#define PWMCR_EN                (1 << 0)                /* Enables/Disables the PWM     */
+#define PWMCR_REPEAT(x)         (((x) & 0x03) << 1)     /* Sample Repeats               */
+#define PWMCR_SWR               (1 << 3)                /* Software Reset               */
+#define PWMCR_PRESCALER(x)      (((x - 1) & 0xFFF) << 4)/* PRESCALER                    */
+#define PWMCR_CLKSRC(x)         (((x) & 0x3) << 16)
+#define PWMCR_CLKSRC_OFF        (0 << 16)
+#define PWMCR_CLKSRC_IPG        (1 << 16)
+#define PWMCR_CLKSRC_IPG_HIGH   (2 << 16)
+#define PWMCR_CLKSRC_CLK32      (3 << 16)
+#define PWMCR_POUTC
+#define PWMCR_HCTR              (1 << 20)               /* Halfword FIFO Data Swapping  */
+#define PWMCR_BCTR              (1 << 21)               /* Byte FIFO Data Swapping      */
+#define PWMCR_DBGEN             (1 << 22)               /* Debug Mode                   */
+#define PWMCR_WAITEN            (1 << 23)               /* Wait Mode                    */
+#define PWMCR_DOZEN             (1 << 24)               /* Doze Mode                    */
+#define PWMCR_STOPEN            (1 << 25)               /* Stop Mode                    */
+#define PWMCR_FWM(x)            (((x) & 0x3) << 26)     /* FIFO Water Mark              */
+
+#define MAX_DIV 4096
+#endif
+
+#define PWMS_SAMPLE(x)          ((x) & 0xFFFF)          /* Contains a two-sample word   */
+#define PWMP_PERIOD(x)          ((x) & 0xFFFF)          /* Represents the PWM's period  */
+#define PWMC_COUNTER(x)         ((x) & 0xFFFF)          /* Represents the current count value   */
+
+struct pwm_device {
+        struct list_head        node;
+        struct platform_device *pdev;
+
+        const char      *label;
+        struct clk      *clk;
+
+        int             clk_enabled;
+        void __iomem    *mmio_base;
+
+        unsigned int    use_count;
+        unsigned int    pwm_id;
+};
+
+int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+{
+        unsigned long long c;
+        unsigned long period_cycles, duty_cycles, prescale;
+
+        if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
+                return -EINVAL;
+
+        c = clk_get_rate(pwm->clk);
+        c = c * period_ns;
+        do_div(c, 1000000000);
+        period_cycles = c;
+
+        prescale = period_cycles / 0x10000 + 1;
+
+        period_cycles /= prescale;
+        c = (unsigned long long)period_cycles * duty_ns;
+        do_div(c, period_ns);
+        duty_cycles = c;
+
+#ifdef PWM_VER_2
+        writel(duty_cycles, pwm->mmio_base + PWMSAR);
+        writel(period_cycles, pwm->mmio_base + PWMPR);
+        writel(PWMCR_PRESCALER(prescale - 1) | PWMCR_CLKSRC_IPG_HIGH | PWMCR_EN,
+                        pwm->mmio_base + PWMCR);
+#elif defined PWM_VER_1
+#error PWM not yet working on MX1 / MX21
+#endif
+
+        return 0;
+}
+EXPORT_SYMBOL(pwm_config);
+
+int pwm_enable(struct pwm_device *pwm)
+{
+        int rc = 0;
+
+        if (!pwm->clk_enabled) {
+                rc = clk_enable(pwm->clk);
+                if (!rc)
+                        pwm->clk_enabled = 1;
+        }
+        return rc;
+}
+EXPORT_SYMBOL(pwm_enable);
+
+void pwm_disable(struct pwm_device *pwm)
+{
+        if (pwm->clk_enabled) {
+                clk_disable(pwm->clk);
+                pwm->clk_enabled = 0;
+        }
+}
+EXPORT_SYMBOL(pwm_disable);
+
+static DEFINE_MUTEX(pwm_lock);
+static LIST_HEAD(pwm_list);
+
+struct pwm_device *pwm_request(int pwm_id, const char *label)
+{
+        struct pwm_device *pwm;
+        int found = 0;
+
+        mutex_lock(&pwm_lock);
+
+        list_for_each_entry(pwm, &pwm_list, node) {
+                if (pwm->pwm_id == pwm_id) {
+                        found = 1;
+                        break;
+                }
+        }
+
+        if (found) {
+                if (pwm->use_count == 0) {
+                        pwm->use_count++;
+                        pwm->label = label;
+                } else
+                        pwm = ERR_PTR(-EBUSY);
+        } else
+                pwm = ERR_PTR(-ENOENT);
+
+        mutex_unlock(&pwm_lock);
+        return pwm;
+}
+EXPORT_SYMBOL(pwm_request);
+
+void pwm_free(struct pwm_device *pwm)
+{
+        mutex_lock(&pwm_lock);
+
+        if (pwm->use_count) {
+                pwm->use_count--;
+                pwm->label = NULL;
+        } else
+                pr_warning("PWM device already freed\n");
+
+        mutex_unlock(&pwm_lock);
+}
+EXPORT_SYMBOL(pwm_free);
+
+static int __devinit mxc_pwm_probe(struct platform_device *pdev)
+{
+        struct pwm_device *pwm;
+        struct resource *r;
+        int ret = 0;
+
+        pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
+        if (pwm == NULL) {
+                dev_err(&pdev->dev, "failed to allocate memory\n");
+                return -ENOMEM;
+        }
+
+        pwm->clk = clk_get(&pdev->dev, "pwm");
+
+        if (IS_ERR(pwm->clk)) {
+                ret = PTR_ERR(pwm->clk);
+                goto err_free;
+        }
+
+        pwm->clk_enabled = 0;
+
+        pwm->use_count = 0;
+        pwm->pwm_id = pdev->id;
+        pwm->pdev = pdev;
+
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (r == NULL) {
+                dev_err(&pdev->dev, "no memory resource defined\n");
+                ret = -ENODEV;
+                goto err_free_clk;
+        }
+
+        r = request_mem_region(r->start, r->end - r->start + 1, pdev->name);
+        if (r == NULL) {
+                dev_err(&pdev->dev, "failed to request memory resource\n");
+                ret = -EBUSY;
+                goto err_free_clk;
+        }
+
+        pwm->mmio_base = ioremap(r->start, r->end - r->start + 1);
+        if (pwm->mmio_base == NULL) {
+                dev_err(&pdev->dev, "failed to ioremap() registers\n");
+                ret = -ENODEV;
+                goto err_free_mem;
+        }
+
+        mutex_lock(&pwm_lock);
+        list_add_tail(&pwm->node, &pwm_list);
+        mutex_unlock(&pwm_lock);
+
+        platform_set_drvdata(pdev, pwm);
+        return 0;
+
+err_free_mem:
+        release_mem_region(r->start, r->end - r->start + 1);
+err_free_clk:
+        clk_put(pwm->clk);
+err_free:
+        kfree(pwm);
+        return ret;
+}
+
+static int __devexit mxc_pwm_remove(struct platform_device *pdev)
+{
+        struct pwm_device *pwm;
+        struct resource *r;
+
+        pwm = platform_get_drvdata(pdev);
+        if (pwm == NULL)
+                return -ENODEV;
+
+        mutex_lock(&pwm_lock);
+        list_del(&pwm->node);
+        mutex_unlock(&pwm_lock);
+
+        iounmap(pwm->mmio_base);
+
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        release_mem_region(r->start, r->end - r->start + 1);
+
+        clk_put(pwm->clk);
+
+        kfree(pwm);
+        return 0;
+}
+
+static struct platform_driver mxc_pwm_driver = {
+        .driver         = {
+                .name   = "mxc_pwm",
+        },
+        .probe          = mxc_pwm_probe,
+        .remove         = __devexit_p(mxc_pwm_remove),
+};
+
+static int __init mxc_pwm_init(void)
+{
+        return platform_driver_register(&mxc_pwm_driver);
+}
+arch_initcall(mxc_pwm_init);
+
+static void __exit mxc_pwm_exit(void)
+{
+        platform_driver_unregister(&mxc_pwm_driver);
+}
+module_exit(mxc_pwm_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
+
diff --git a/arch/arm/mach-mx2/system.c b/arch/arm/plat-mxc/system.c
index 7b8269719d11..79c37577c916 100644
--- a/arch/arm/mach-mx2/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -3,6 +3,7 @@
  * Copyright (C) 2000 Deep Blue Solutions Ltd
  * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -22,42 +23,45 @@
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/err.h>
+#include <linux/delay.h>
 
 #include <mach/hardware.h>
 #include <asm/proc-fns.h>
 #include <asm/system.h>
 
-/*
- * Put the CPU into idle mode. It is called by default_idle()
- * in process.c file.
- */
-void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks.
-         */
-        cpu_do_idle();
-}
-
-#define WDOG_WCR_REG                    IO_ADDRESS(WDOG_BASE_ADDR)
-#define WDOG_WCR_SRS                    (1 << 4)
+#ifdef CONFIG_ARCH_MX1
+#define WDOG_WCR_REG            IO_ADDRESS(WDT_BASE_ADDR)
+#define WDOG_WCR_ENABLE         (1 << 0)
+#else
+#define WDOG_WCR_REG            IO_ADDRESS(WDOG_BASE_ADDR)
+#define WDOG_WCR_ENABLE         (1 << 2)
+#endif
 
 /*
  * Reset the system. It is called by machine_restart().
  */
-void arch_reset(char mode)
+void arch_reset(char mode, const char *cmd)
 {
-        struct clk *clk;
+        if (!cpu_is_mx1()) {
+                struct clk *clk;
 
-        clk = clk_get(NULL, "wdog_clk");
-        if (!clk) {
-                printk(KERN_ERR"Cannot activate the watchdog. Giving up\n");
-                return;
+                clk = clk_get_sys("imx-wdt.0", NULL);
+                if (!IS_ERR(clk))
+                        clk_enable(clk);
         }
 
-        clk_enable(clk);
-
         /* Assert SRS signal */
-        __raw_writew(__raw_readw(WDOG_WCR_REG) & ~WDOG_WCR_SRS, WDOG_WCR_REG);
+        __raw_writew(WDOG_WCR_ENABLE, WDOG_WCR_REG);
+
+        /* wait for reset to assert... */
+        mdelay(500);
+
+        printk(KERN_ERR "Watchdog reset failed to assert reset\n");
+
+        /* delay to allow the serial port to show the message */
+        mdelay(50);
+
+        /* we'll take a jump through zero as a poor second */
+        cpu_reset(0);
 }
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 758a1293bcfa..ef1b3cd85bd3 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -34,9 +34,6 @@
 static struct clock_event_device clockevent_mxc;
 static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
 
-/* clock source for the timer */
-static struct clk *timer_clk;
-
 /* clock source */
 
 static cycle_t mxc_get_cycles(void)
@@ -53,13 +50,11 @@ static struct clocksource clocksource_mxc = {
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
-static int __init mxc_clocksource_init(void)
+static int __init mxc_clocksource_init(struct clk *timer_clk)
 {
-        unsigned int clock;
-
-        clock = clk_get_rate(timer_clk);
+        unsigned int c = clk_get_rate(timer_clk);
 
-        clocksource_mxc.mult = clocksource_hz2mult(clock,
+        clocksource_mxc.mult = clocksource_hz2mult(c,
                                         clocksource_mxc.shift);
         clocksource_register(&clocksource_mxc);
 
@@ -177,13 +172,11 @@ static struct clock_event_device clockevent_mxc = {
         .rating         = 200,
 };
 
-static int __init mxc_clockevent_init(void)
+static int __init mxc_clockevent_init(struct clk *timer_clk)
 {
-        unsigned int clock;
-
-        clock = clk_get_rate(timer_clk);
+        unsigned int c = clk_get_rate(timer_clk);
 
-        clockevent_mxc.mult = div_sc(clock, NSEC_PER_SEC,
+        clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
                                         clockevent_mxc.shift);
         clockevent_mxc.max_delta_ns =
                         clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
@@ -197,14 +190,8 @@ static int __init mxc_clockevent_init(void)
         return 0;
 }
 
-void __init mxc_timer_init(const char *clk_timer)
+void __init mxc_timer_init(struct clk *timer_clk)
 {
-        timer_clk = clk_get(NULL, clk_timer);
-        if (!timer_clk) {
-                printk(KERN_ERR"Cannot determine timer clock. Giving up.\n");
-                return;
-        }
-
         clk_enable(timer_clk);
 
         /*
@@ -219,10 +206,9 @@ void __init mxc_timer_init(const char *clk_timer)
                      TIMER_BASE + MXC_TCTL);
 
         /* init and register the timer to the framework */
-        mxc_clocksource_init();
-        mxc_clockevent_init();
+        mxc_clocksource_init(timer_clk);
+        mxc_clockevent_init(timer_clk);
 
         /* Make irqs happen */
         setup_irq(TIMER_INTERRUPT, &mxc_timer_irq);
 }
-
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 46d3b0b9ce69..9dd68fafb374 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -11,14 +11,17 @@ choice
 
 config ARCH_OMAP1
         bool "TI OMAP1"
+        select COMMON_CLKDEV
 
 config ARCH_OMAP2
         bool "TI OMAP2"
         select CPU_V6
+        select COMMON_CLKDEV
 
 config ARCH_OMAP3
         bool "TI OMAP3"
         select CPU_V7
+        select COMMON_CLKDEV
 
 endchoice
 
@@ -104,6 +107,14 @@ config OMAP_MCBSP
           Say Y here if you want support for the OMAP Multichannel
           Buffered Serial Port.
 
+config OMAP_MBOX_FWK
+        tristate "Mailbox framework support"
+        depends on ARCH_OMAP
+        default n
+        help
+          Say Y here if you want to use OMAP Mailbox framework support for
+          DSP, IVA1.0 and IVA2 in OMAP1/2/3.
+
 choice
         prompt "System timer"
         default OMAP_MPU_TIMER
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index be6aab9c6834..2e0614552ac8 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -36,44 +36,6 @@ static struct clk_functions *arch_clock;
  * Standard clock functions defined in include/linux/clk.h
  *-------------------------------------------------------------------------*/
 
-/*
- * Returns a clock. Note that we first try to use device id on the bus
- * and clock name. If this fails, we try to use clock name only.
- */
-struct clk * clk_get(struct device *dev, const char *id)
-{
-        struct clk *p, *clk = ERR_PTR(-ENOENT);
-        int idno;
-
-        if (dev == NULL || dev->bus != &platform_bus_type)
-                idno = -1;
-        else
-                idno = to_platform_device(dev)->id;
-
-        mutex_lock(&clocks_mutex);
-
-        list_for_each_entry(p, &clocks, node) {
-                if (p->id == idno &&
-                    strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
-                        clk = p;
-                        goto found;
-                }
-        }
-
-        list_for_each_entry(p, &clocks, node) {
-                if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
-                        clk = p;
-                        break;
-                }
-        }
-
-found:
-        mutex_unlock(&clocks_mutex);
-
-        return clk;
-}
-EXPORT_SYMBOL(clk_get);
-
 int clk_enable(struct clk *clk)
 {
         unsigned long flags;
@@ -114,22 +76,6 @@ out:
 }
 EXPORT_SYMBOL(clk_disable);
 
-int clk_get_usecount(struct clk *clk)
-{
-        unsigned long flags;
-        int ret = 0;
-
-        if (clk == NULL || IS_ERR(clk))
-                return 0;
-
-        spin_lock_irqsave(&clockfw_lock, flags);
-        ret = clk->usecount;
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL(clk_get_usecount);
-
 unsigned long clk_get_rate(struct clk *clk)
 {
         unsigned long flags;
@@ -146,13 +92,6 @@ unsigned long clk_get_rate(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_rate);
 
-void clk_put(struct clk *clk)
-{
-        if (clk && !IS_ERR(clk))
-                module_put(clk->owner);
-}
-EXPORT_SYMBOL(clk_put);
-
 /*-------------------------------------------------------------------------
  * Optional clock functions defined in include/linux/clk.h
  *-------------------------------------------------------------------------*/
@@ -185,6 +124,11 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
         spin_lock_irqsave(&clockfw_lock, flags);
         if (arch_clock->clk_set_rate)
                 ret = arch_clock->clk_set_rate(clk, rate);
+        if (ret == 0) {
+                if (clk->recalc)
+                        clk->rate = clk->recalc(clk);
+                propagate_rate(clk);
+        }
         spin_unlock_irqrestore(&clockfw_lock, flags);
 
         return ret;
@@ -200,8 +144,16 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
                 return ret;
 
         spin_lock_irqsave(&clockfw_lock, flags);
-        if (arch_clock->clk_set_parent)
-                ret =  arch_clock->clk_set_parent(clk, parent);
+        if (clk->usecount == 0) {
+                if (arch_clock->clk_set_parent)
+                        ret = arch_clock->clk_set_parent(clk, parent);
+                if (ret == 0) {
+                        if (clk->recalc)
+                                clk->rate = clk->recalc(clk);
+                        propagate_rate(clk);
+                }
+        } else
+                ret = -EBUSY;
         spin_unlock_irqrestore(&clockfw_lock, flags);
 
         return ret;
@@ -210,18 +162,7 @@ EXPORT_SYMBOL(clk_set_parent);
 
 struct clk *clk_get_parent(struct clk *clk)
 {
-        unsigned long flags;
-        struct clk * ret = NULL;
-
-        if (clk == NULL || IS_ERR(clk))
-                return ret;
-
-        spin_lock_irqsave(&clockfw_lock, flags);
-        if (arch_clock->clk_get_parent)
-                ret = arch_clock->clk_get_parent(clk);
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-
-        return ret;
+        return clk->parent;
 }
 EXPORT_SYMBOL(clk_get_parent);
 
@@ -250,14 +191,20 @@ static int __init omap_clk_setup(char *str)
 __setup("mpurate=", omap_clk_setup);
 
 /* Used for clocks that always have same value as the parent clock */
-void followparent_recalc(struct clk *clk)
+unsigned long followparent_recalc(struct clk *clk)
 {
-        if (clk == NULL || IS_ERR(clk))
-                return;
+        return clk->parent->rate;
+}
 
-        clk->rate = clk->parent->rate;
-        if (unlikely(clk->flags & RATE_PROPAGATES))
-                propagate_rate(clk);
+void clk_reparent(struct clk *child, struct clk *parent)
+{
+        list_del_init(&child->sibling);
+        if (parent)
+                list_add(&child->sibling, &parent->children);
+        child->parent = parent;
+
+        /* now do the debugfs renaming to reattach the child
+           to the proper parent */
 }
 
 /* Propagate rate to children */
@@ -265,17 +212,15 @@ void propagate_rate(struct clk * tclk)
 {
         struct clk *clkp;
 
-        if (tclk == NULL || IS_ERR(tclk))
-                return;
-
-        list_for_each_entry(clkp, &clocks, node) {
-                if (likely(clkp->parent != tclk))
-                        continue;
-                if (likely((u32)clkp->recalc))
-                        clkp->recalc(clkp);
+        list_for_each_entry(clkp, &tclk->children, sibling) {
+                if (clkp->recalc)
+                        clkp->rate = clkp->recalc(clkp);
+                propagate_rate(clkp);
         }
 }
 
+static LIST_HEAD(root_clks);
+
 /**
  * recalculate_root_clocks - recalculate and propagate all root clocks
  *
@@ -287,18 +232,35 @@ void recalculate_root_clocks(void)
 {
         struct clk *clkp;
 
-        list_for_each_entry(clkp, &clocks, node) {
-                if (unlikely(!clkp->parent) && likely((u32)clkp->recalc))
-                        clkp->recalc(clkp);
+        list_for_each_entry(clkp, &root_clks, sibling) {
+                if (clkp->recalc)
+                        clkp->rate = clkp->recalc(clkp);
+                propagate_rate(clkp);
         }
 }
 
+void clk_init_one(struct clk *clk)
+{
+        INIT_LIST_HEAD(&clk->children);
+}
+
 int clk_register(struct clk *clk)
 {
         if (clk == NULL || IS_ERR(clk))
                 return -EINVAL;
 
+        /*
+         * trap out already registered clocks
+         */
+        if (clk->node.next || clk->node.prev)
+                return 0;
+
         mutex_lock(&clocks_mutex);
+        if (clk->parent)
+                list_add(&clk->sibling, &clk->parent->children);
+        else
+                list_add(&clk->sibling, &root_clks);
+
         list_add(&clk->node, &clocks);
         if (clk->init)
                 clk->init(clk);
@@ -314,39 +276,12 @@ void clk_unregister(struct clk *clk)
                 return;
 
         mutex_lock(&clocks_mutex);
+        list_del(&clk->sibling);
         list_del(&clk->node);
         mutex_unlock(&clocks_mutex);
 }
 EXPORT_SYMBOL(clk_unregister);
 
-void clk_deny_idle(struct clk *clk)
-{
-        unsigned long flags;
-
-        if (clk == NULL || IS_ERR(clk))
-                return;
-
-        spin_lock_irqsave(&clockfw_lock, flags);
-        if (arch_clock->clk_deny_idle)
-                arch_clock->clk_deny_idle(clk);
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-}
-EXPORT_SYMBOL(clk_deny_idle);
-
-void clk_allow_idle(struct clk *clk)
-{
-        unsigned long flags;
-
-        if (clk == NULL || IS_ERR(clk))
-                return;
-
-        spin_lock_irqsave(&clockfw_lock, flags);
-        if (arch_clock->clk_allow_idle)
-                arch_clock->clk_allow_idle(clk);
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-}
-EXPORT_SYMBOL(clk_allow_idle);
-
 void clk_enable_init_clocks(void)
 {
         struct clk *clkp;
@@ -358,6 +293,23 @@ void clk_enable_init_clocks(void)
 }
 EXPORT_SYMBOL(clk_enable_init_clocks);
 
+/*
+ * Low level helpers
+ */
+static int clkll_enable_null(struct clk *clk)
+{
+        return 0;
+}
+
+static void clkll_disable_null(struct clk *clk)
+{
+}
+
+const struct clkops clkops_null = {
+        .enable         = clkll_enable_null,
+        .disable        = clkll_disable_null,
+};
+
 #ifdef CONFIG_CPU_FREQ
 void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
 {
@@ -383,8 +335,10 @@ static int __init clk_disable_unused(void)
         unsigned long flags;
 
         list_for_each_entry(ck, &clocks, node) {
-                if (ck->usecount > 0 || (ck->flags & ALWAYS_ENABLED) ||
-                        ck->enable_reg == 0)
+                if (ck->ops == &clkops_null)
+                        continue;
+
+                if (ck->usecount > 0 || ck->enable_reg == 0)
                         continue;
 
                 spin_lock_irqsave(&clockfw_lock, flags);
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 6825fbb5a056..d1797147732f 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -245,7 +245,7 @@ static struct omap_globals *omap2_globals;
 static void __init __omap2_set_globals(void)
 {
         omap2_set_globals_tap(omap2_globals);
-        omap2_set_globals_memory(omap2_globals);
+        omap2_set_globals_sdrc(omap2_globals);
         omap2_set_globals_control(omap2_globals);
         omap2_set_globals_prcm(omap2_globals);
 }
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
index b2690242a390..843e8af64066 100644
--- a/arch/arm/plat-omap/cpu-omap.c
+++ b/arch/arm/plat-omap/cpu-omap.c
@@ -23,10 +23,13 @@
 #include <linux/io.h>
 
 #include <mach/hardware.h>
+#include <mach/clock.h>
 #include <asm/system.h>
 
 #define VERY_HI_RATE    900000000
 
+static struct cpufreq_frequency_table *freq_table;
+
 #ifdef CONFIG_ARCH_OMAP1
 #define MPU_CLK         "mpu"
 #else
@@ -39,6 +42,9 @@ static struct clk *mpu_clk;
 
 int omap_verify_speed(struct cpufreq_policy *policy)
 {
+        if (freq_table)
+                return cpufreq_frequency_table_verify(policy, freq_table);
+
         if (policy->cpu)
                 return -EINVAL;
 
@@ -70,12 +76,26 @@ static int omap_target(struct cpufreq_policy *policy,
         struct cpufreq_freqs freqs;
         int ret = 0;
 
+        /* Ensure desired rate is within allowed range.  Some govenors
+         * (ondemand) will just pass target_freq=0 to get the minimum. */
+        if (target_freq < policy->cpuinfo.min_freq)
+                target_freq = policy->cpuinfo.min_freq;
+        if (target_freq > policy->cpuinfo.max_freq)
+                target_freq = policy->cpuinfo.max_freq;
+
         freqs.old = omap_getspeed(0);
         freqs.new = clk_round_rate(mpu_clk, target_freq * 1000) / 1000;
         freqs.cpu = 0;
 
+        if (freqs.old == freqs.new)
+                return ret;
+
         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-        ret = clk_set_rate(mpu_clk, target_freq * 1000);
+#ifdef CONFIG_CPU_FREQ_DEBUG
+        printk(KERN_DEBUG "cpufreq-omap: transition: %u --> %u\n",
+               freqs.old, freqs.new);
+#endif
+        ret = clk_set_rate(mpu_clk, freqs.new * 1000);
         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 
         return ret;
@@ -83,16 +103,31 @@ static int omap_target(struct cpufreq_policy *policy,
 
 static int __init omap_cpu_init(struct cpufreq_policy *policy)
 {
+        int result = 0;
+
         mpu_clk = clk_get(NULL, MPU_CLK);
         if (IS_ERR(mpu_clk))
                 return PTR_ERR(mpu_clk);
 
         if (policy->cpu != 0)
                 return -EINVAL;
+
         policy->cur = policy->min = policy->max = omap_getspeed(0);
-        policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / 1000;
-        policy->cpuinfo.max_freq = clk_round_rate(mpu_clk, VERY_HI_RATE) / 1000;
-        policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
+
+        clk_init_cpufreq_table(&freq_table);
+        if (freq_table) {
+                result = cpufreq_frequency_table_cpuinfo(policy, freq_table);
+                if (!result)
+                        cpufreq_frequency_table_get_attr(freq_table,
+                                                        policy->cpu);
+        } else {
+                policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / 1000;
+                policy->cpuinfo.max_freq = clk_round_rate(mpu_clk,
+                                                        VERY_HI_RATE) / 1000;
+        }
+
+        /* FIXME: what's the actual transition time? */
+        policy->cpuinfo.transition_latency = 10 * 1000 * 1000;
 
         return 0;
 }
@@ -103,6 +138,11 @@ static int omap_cpu_exit(struct cpufreq_policy *policy)
         return 0;
 }
 
+static struct freq_attr *omap_cpufreq_attr[] = {
+        &cpufreq_freq_attr_scaling_available_freqs,
+        NULL,
+};
+
 static struct cpufreq_driver omap_driver = {
         .flags          = CPUFREQ_STICKY,
         .verify         = omap_verify_speed,
@@ -111,6 +151,7 @@ static struct cpufreq_driver omap_driver = {
         .init           = omap_cpu_init,
         .exit           = omap_cpu_exit,
         .name           = "omap",
+        .attr           = omap_cpufreq_attr,
 };
 
 static int __init omap_cpufreq_init(void)
@@ -119,3 +160,11 @@ static int __init omap_cpufreq_init(void)
 }
 
 arch_initcall(omap_cpufreq_init);
+
+/*
+ * if ever we want to remove this, upon cleanup call:
+ *
+ * cpufreq_unregister_driver()
+ * cpufreq_frequency_table_put_attr()
+ */
+
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 208dbb121f47..87fb7ff41794 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -228,6 +228,9 @@ int __init omap_mmc_add(const char *name, int id, unsigned long base,
         ret = platform_device_add(pdev);
         if (ret)
                 goto fail;
+
+        /* return device handle to board setup code */
+        data->dev = &pdev->dev;
         return 0;
 
 fail:
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 47ec77af4ccb..21cc0142b97a 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -123,6 +123,7 @@ static struct dma_link_info *dma_linked_lch;
 
 static int dma_lch_count;
 static int dma_chan_count;
+static int omap_dma_reserve_channels;
 
 static spinlock_t dma_chan_lock;
 static struct omap_dma_lch *dma_chan;
@@ -737,7 +738,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
                  * id.
                  */
                 dma_write(dev_id | (1 << 10), CCR(free_ch));
-        } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
+        } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
                 dma_write(dev_id, CCR(free_ch));
         }
 
@@ -1900,7 +1901,7 @@ static int omap2_dma_handle_ch(int ch)
 /* STATUS register count is from 1-32 while our is 0-31 */
 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
 {
-        u32 val;
+        u32 val, enable_reg;
         int i;
 
         val = dma_read(IRQSTATUS_L0);
@@ -1909,6 +1910,8 @@ static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
                         printk(KERN_WARNING "Spurious DMA IRQ\n");
                 return IRQ_HANDLED;
         }
+        enable_reg = dma_read(IRQENABLE_L0);
+        val &= enable_reg; /* Dispatch only relevant interrupts */
         for (i = 0; i < dma_lch_count && val != 0; i++) {
                 if (val & 1)
                         omap2_dma_handle_ch(i);
@@ -2321,6 +2324,10 @@ static int __init omap_init_dma(void)
                 return -ENODEV;
         }
 
+        if (cpu_class_is_omap2() && omap_dma_reserve_channels
+                        && (omap_dma_reserve_channels <= dma_lch_count))
+                dma_lch_count = omap_dma_reserve_channels;
+
         dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
                                 GFP_KERNEL);
         if (!dma_chan)
@@ -2339,7 +2346,7 @@ static int __init omap_init_dma(void)
                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
                 dma_chan_count = 9;
                 enable_1510_mode = 1;
-        } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
+        } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
                        dma_read(HW_ID));
                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
@@ -2371,7 +2378,7 @@ static int __init omap_init_dma(void)
                 u8 revision = dma_read(REVISION) & 0xff;
                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
                        revision >> 4, revision & 0xf);
-                dma_chan_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
+                dma_chan_count = dma_lch_count;
         } else {
                 dma_chan_count = 0;
                 return 0;
@@ -2437,4 +2444,17 @@ static int __init omap_init_dma(void)
 
 arch_initcall(omap_init_dma);
 
+/*
+ * Reserve the omap SDMA channels using cmdline bootarg
+ * "omap_dma_reserve_ch=". The valid range is 1 to 32
+ */
+static int __init omap_dma_cmdline_reserve_ch(char *str)
+{
+        if (get_option(&str, &omap_dma_reserve_channels) != 1)
+                omap_dma_reserve_channels = 0;
+        return 1;
+}
+
+__setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
+
 
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index e4f0ce04ba92..bfd47570cc91 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -33,6 +33,7 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/io.h>
+#include <linux/module.h>
 #include <mach/hardware.h>
 #include <mach/dmtimer.h>
 #include <mach/irqs.h>
@@ -362,6 +363,7 @@ struct omap_dm_timer *omap_dm_timer_request(void)
 
         return timer;
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_request);
 
 struct omap_dm_timer *omap_dm_timer_request_specific(int id)
 {
@@ -385,6 +387,7 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
 
         return timer;
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
 
 void omap_dm_timer_free(struct omap_dm_timer *timer)
 {
@@ -395,6 +398,7 @@ void omap_dm_timer_free(struct omap_dm_timer *timer)
         WARN_ON(!timer->reserved);
         timer->reserved = 0;
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_free);
 
 void omap_dm_timer_enable(struct omap_dm_timer *timer)
 {
@@ -406,6 +410,7 @@ void omap_dm_timer_enable(struct omap_dm_timer *timer)
 
         timer->enabled = 1;
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
 
 void omap_dm_timer_disable(struct omap_dm_timer *timer)
 {
@@ -417,11 +422,13 @@ void omap_dm_timer_disable(struct omap_dm_timer *timer)
 
         timer->enabled = 0;
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
 
 int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
 {
         return timer->irq;
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
 
 #if defined(CONFIG_ARCH_OMAP1)
 
@@ -452,6 +459,7 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 
         return inputmask;
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
 
 #elif defined(CONFIG_ARCH_OMAP2) || defined (CONFIG_ARCH_OMAP3)
 
@@ -459,6 +467,7 @@ struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 {
         return timer->fclk;
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk);
 
 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 {
@@ -466,6 +475,7 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 
         return 0;
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
 
 #endif
 
@@ -473,6 +483,7 @@ void omap_dm_timer_trigger(struct omap_dm_timer *timer)
 {
         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_trigger);
 
 void omap_dm_timer_start(struct omap_dm_timer *timer)
 {
@@ -484,6 +495,7 @@ void omap_dm_timer_start(struct omap_dm_timer *timer)
                 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
         }
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_start);
 
 void omap_dm_timer_stop(struct omap_dm_timer *timer)
 {
@@ -495,6 +507,7 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer)
                 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
         }
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
 
 #ifdef CONFIG_ARCH_OMAP1
 
@@ -507,6 +520,7 @@ void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
         l |= source << n;
         omap_writel(l, MOD_CONF_CTRL_1);
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
 
 #else
 
@@ -523,6 +537,7 @@ void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
          * cause an abort. */
         __delay(150000);
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
 
 #endif
 
@@ -541,6 +556,7 @@ void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
 
         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_set_load);
 
 /* Optimized set_load which removes costly spin wait in timer_start */
 void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
@@ -560,6 +576,7 @@ void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
         omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load);
         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start);
 
 void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
                              unsigned int match)
@@ -574,6 +591,7 @@ void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
         omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_set_match);
 
 void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
                            int toggle, int trigger)
@@ -590,6 +608,7 @@ void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
         l |= trigger << 10;
         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm);
 
 void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
 {
@@ -603,6 +622,7 @@ void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
         }
         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
 
 void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
                                   unsigned int value)
@@ -610,6 +630,7 @@ void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
         omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
         omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
 
 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
 {
@@ -619,11 +640,13 @@ unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
 
         return l;
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
 
 void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
 {
         omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
 
 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
 {
@@ -633,11 +656,13 @@ unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
 
         return l;
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter);
 
 void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
 {
         omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
 }
+EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter);
 
 int omap_dm_timers_active(void)
 {
@@ -658,6 +683,7 @@ int omap_dm_timers_active(void)
         }
         return 0;
 }
+EXPORT_SYMBOL_GPL(omap_dm_timers_active);
 
 int __init omap_dm_timer_init(void)
 {
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index f856a90b264e..d3fa41e3d8c5 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -81,6 +81,22 @@
 #define OMAP730_GPIO_INT_STATUS         0x14
 
 /*
+ * OMAP850 specific GPIO registers
+ */
+#define OMAP850_GPIO1_BASE              IO_ADDRESS(0xfffbc000)
+#define OMAP850_GPIO2_BASE              IO_ADDRESS(0xfffbc800)
+#define OMAP850_GPIO3_BASE              IO_ADDRESS(0xfffbd000)
+#define OMAP850_GPIO4_BASE              IO_ADDRESS(0xfffbd800)
+#define OMAP850_GPIO5_BASE              IO_ADDRESS(0xfffbe000)
+#define OMAP850_GPIO6_BASE              IO_ADDRESS(0xfffbe800)
+#define OMAP850_GPIO_DATA_INPUT         0x00
+#define OMAP850_GPIO_DATA_OUTPUT        0x04
+#define OMAP850_GPIO_DIR_CONTROL        0x08
+#define OMAP850_GPIO_INT_CONTROL        0x0c
+#define OMAP850_GPIO_INT_MASK           0x10
+#define OMAP850_GPIO_INT_STATUS         0x14
+
+/*
  * omap24xx specific GPIO registers
  */
 #define OMAP242X_GPIO1_BASE             IO_ADDRESS(0x48018000)
@@ -159,7 +175,8 @@ struct gpio_bank {
 #define METHOD_GPIO_1510        1
 #define METHOD_GPIO_1610        2
 #define METHOD_GPIO_730         3
-#define METHOD_GPIO_24XX        4
+#define METHOD_GPIO_850         4
+#define METHOD_GPIO_24XX        5
 
 #ifdef CONFIG_ARCH_OMAP16XX
 static struct gpio_bank gpio_bank_1610[5] = {
@@ -190,6 +207,19 @@ static struct gpio_bank gpio_bank_730[7] = {
 };
 #endif
 
+#ifdef CONFIG_ARCH_OMAP850
+static struct gpio_bank gpio_bank_850[7] = {
+        { OMAP_MPUIO_BASE,     INT_850_MPUIO,       IH_MPUIO_BASE,      METHOD_MPUIO },
+        { OMAP850_GPIO1_BASE,  INT_850_GPIO_BANK1,  IH_GPIO_BASE,       METHOD_GPIO_850 },
+        { OMAP850_GPIO2_BASE,  INT_850_GPIO_BANK2,  IH_GPIO_BASE + 32,  METHOD_GPIO_850 },
+        { OMAP850_GPIO3_BASE,  INT_850_GPIO_BANK3,  IH_GPIO_BASE + 64,  METHOD_GPIO_850 },
+        { OMAP850_GPIO4_BASE,  INT_850_GPIO_BANK4,  IH_GPIO_BASE + 96,  METHOD_GPIO_850 },
+        { OMAP850_GPIO5_BASE,  INT_850_GPIO_BANK5,  IH_GPIO_BASE + 128, METHOD_GPIO_850 },
+        { OMAP850_GPIO6_BASE,  INT_850_GPIO_BANK6,  IH_GPIO_BASE + 160, METHOD_GPIO_850 },
+};
+#endif
+
+
 #ifdef CONFIG_ARCH_OMAP24XX
 
 static struct gpio_bank gpio_bank_242x[4] = {
@@ -236,7 +266,7 @@ static inline struct gpio_bank *get_gpio_bank(int gpio)
                         return &gpio_bank[0];
                 return &gpio_bank[1 + (gpio >> 4)];
         }
-        if (cpu_is_omap730()) {
+        if (cpu_is_omap7xx()) {
                 if (OMAP_GPIO_IS_MPUIO(gpio))
                         return &gpio_bank[0];
                 return &gpio_bank[1 + (gpio >> 5)];
@@ -251,7 +281,7 @@ static inline struct gpio_bank *get_gpio_bank(int gpio)
 
 static inline int get_gpio_index(int gpio)
 {
-        if (cpu_is_omap730())
+        if (cpu_is_omap7xx())
                 return gpio & 0x1f;
         if (cpu_is_omap24xx())
                 return gpio & 0x1f;
@@ -273,7 +303,7 @@ static inline int gpio_valid(int gpio)
                 return 0;
         if ((cpu_is_omap16xx()) && gpio < 64)
                 return 0;
-        if (cpu_is_omap730() && gpio < 192)
+        if (cpu_is_omap7xx() && gpio < 192)
                 return 0;
         if (cpu_is_omap24xx() && gpio < 128)
                 return 0;
@@ -318,6 +348,11 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
                 reg += OMAP730_GPIO_DIR_CONTROL;
                 break;
 #endif
+#ifdef CONFIG_ARCH_OMAP850
+        case METHOD_GPIO_850:
+                reg += OMAP850_GPIO_DIR_CONTROL;
+                break;
+#endif
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         case METHOD_GPIO_24XX:
                 reg += OMAP24XX_GPIO_OE;
@@ -380,6 +415,16 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
                         l &= ~(1 << gpio);
                 break;
 #endif
+#ifdef CONFIG_ARCH_OMAP850
+        case METHOD_GPIO_850:
+                reg += OMAP850_GPIO_DATA_OUTPUT;
+                l = __raw_readl(reg);
+                if (enable)
+                        l |= 1 << gpio;
+                else
+                        l &= ~(1 << gpio);
+                break;
+#endif
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         case METHOD_GPIO_24XX:
                 if (enable)
@@ -426,6 +471,11 @@ static int __omap_get_gpio_datain(int gpio)
                 reg += OMAP730_GPIO_DATA_INPUT;
                 break;
 #endif
+#ifdef CONFIG_ARCH_OMAP850
+        case METHOD_GPIO_850:
+                reg += OMAP850_GPIO_DATA_INPUT;
+                break;
+#endif
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         case METHOD_GPIO_24XX:
                 reg += OMAP24XX_GPIO_DATAIN;
@@ -598,6 +648,18 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
                         goto bad;
                 break;
 #endif
+#ifdef CONFIG_ARCH_OMAP850
+        case METHOD_GPIO_850:
+                reg += OMAP850_GPIO_INT_CONTROL;
+                l = __raw_readl(reg);
+                if (trigger & IRQ_TYPE_EDGE_RISING)
+                        l |= 1 << gpio;
+                else if (trigger & IRQ_TYPE_EDGE_FALLING)
+                        l &= ~(1 << gpio);
+                else
+                        goto bad;
+                break;
+#endif
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         case METHOD_GPIO_24XX:
                 set_24xx_gpio_triggering(bank, gpio, trigger);
@@ -678,6 +740,11 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
                 reg += OMAP730_GPIO_INT_STATUS;
                 break;
 #endif
+#ifdef CONFIG_ARCH_OMAP850
+        case METHOD_GPIO_850:
+                reg += OMAP850_GPIO_INT_STATUS;
+                break;
+#endif
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         case METHOD_GPIO_24XX:
                 reg += OMAP24XX_GPIO_IRQSTATUS1;
@@ -736,6 +803,13 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
                 inv = 1;
                 break;
 #endif
+#ifdef CONFIG_ARCH_OMAP850
+        case METHOD_GPIO_850:
+                reg += OMAP850_GPIO_INT_MASK;
+                mask = 0xffffffff;
+                inv = 1;
+                break;
+#endif
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         case METHOD_GPIO_24XX:
                 reg += OMAP24XX_GPIO_IRQENABLE1;
@@ -799,6 +873,16 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
                         l |= gpio_mask;
                 break;
 #endif
+#ifdef CONFIG_ARCH_OMAP850
+        case METHOD_GPIO_850:
+                reg += OMAP850_GPIO_INT_MASK;
+                l = __raw_readl(reg);
+                if (enable)
+                        l &= ~(gpio_mask);
+                else
+                        l |= gpio_mask;
+                break;
+#endif
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         case METHOD_GPIO_24XX:
                 if (enable)
@@ -983,6 +1067,10 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         if (bank->method == METHOD_GPIO_730)
                 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
 #endif
+#ifdef CONFIG_ARCH_OMAP850
+        if (bank->method == METHOD_GPIO_850)
+                isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
+#endif
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         if (bank->method == METHOD_GPIO_24XX)
                 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
@@ -1372,6 +1460,13 @@ static int __init _omap_gpio_init(void)
                 gpio_bank = gpio_bank_730;
         }
 #endif
+#ifdef CONFIG_ARCH_OMAP850
+        if (cpu_is_omap850()) {
+                printk(KERN_INFO "OMAP850 GPIO hardware\n");
+                gpio_bank_count = 7;
+                gpio_bank = gpio_bank_850;
+        }
+#endif
 
 #ifdef CONFIG_ARCH_OMAP24XX
         if (cpu_is_omap242x()) {
@@ -1420,7 +1515,7 @@ static int __init _omap_gpio_init(void)
                         __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
                         __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
                 }
-                if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
+                if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) {
                         __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
                         __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
 
@@ -1743,6 +1838,9 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
         case METHOD_GPIO_730:
                 reg += OMAP730_GPIO_DIR_CONTROL;
                 break;
+        case METHOD_GPIO_850:
+                reg += OMAP850_GPIO_DIR_CONTROL;
+                break;
         case METHOD_GPIO_24XX:
                 reg += OMAP24XX_GPIO_OE;
                 break;
@@ -1762,7 +1860,8 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
 
                 if (bank_is_mpuio(bank))
                         gpio = OMAP_MPUIO(0);
-                else if (cpu_class_is_omap2() || cpu_is_omap730())
+                else if (cpu_class_is_omap2() || cpu_is_omap730() ||
+                                cpu_is_omap850())
                         bankwidth = 32;
 
                 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index 467531edefd3..a303071d5e36 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -98,6 +98,8 @@ static const int omap34xx_pins[][2] = {
 static const int omap34xx_pins[][2] = {};
 #endif
 
+#define OMAP_I2C_CMDLINE_SETUP  (BIT(31))
+
 static void __init omap_i2c_mux_pins(int bus)
 {
         int scl, sda;
@@ -119,14 +121,9 @@ static void __init omap_i2c_mux_pins(int bus)
         omap_cfg_reg(scl);
 }
 
-int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
-                          struct i2c_board_info const *info,
-                          unsigned len)
+static int __init omap_i2c_nr_ports(void)
 {
-        int ports, err;
-        struct platform_device *pdev;
-        struct resource *res;
-        resource_size_t base, irq;
+        int ports = 0;
 
         if (cpu_class_is_omap1())
                 ports = 1;
@@ -135,17 +132,16 @@ int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
         else if (cpu_is_omap34xx())
                 ports = 3;
 
-        BUG_ON(bus_id < 1 || bus_id > ports);
+        return ports;
+}
 
-        if (info) {
-                err = i2c_register_board_info(bus_id, info, len);
-                if (err)
-                        return err;
-        }
+static int __init omap_i2c_add_bus(int bus_id)
+{
+        struct platform_device *pdev;
+        struct resource *res;
+        resource_size_t base, irq;
 
         pdev = &omap_i2c_devices[bus_id - 1];
-        *(u32 *)pdev->dev.platform_data = clkrate;
-
         if (bus_id == 1) {
                 res = pdev->resource;
                 if (cpu_class_is_omap1()) {
@@ -163,3 +159,81 @@ int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
         omap_i2c_mux_pins(bus_id - 1);
         return platform_device_register(pdev);
 }
+
+/**
+ * omap_i2c_bus_setup - Process command line options for the I2C bus speed
+ * @str: String of options
+ *
+ * This function allow to override the default I2C bus speed for given I2C
+ * bus with a command line option.
+ *
+ * Format: i2c_bus=bus_id,clkrate (in kHz)
+ *
+ * Returns 1 on success, 0 otherwise.
+ */
+static int __init omap_i2c_bus_setup(char *str)
+{
+        int ports;
+        int ints[3];
+
+        ports = omap_i2c_nr_ports();
+        get_options(str, 3, ints);
+        if (ints[0] < 2 || ints[1] < 1 || ints[1] > ports)
+                return 0;
+        i2c_rate[ints[1] - 1] = ints[2];
+        i2c_rate[ints[1] - 1] |= OMAP_I2C_CMDLINE_SETUP;
+
+        return 1;
+}
+__setup("i2c_bus=", omap_i2c_bus_setup);
+
+/*
+ * Register busses defined in command line but that are not registered with
+ * omap_register_i2c_bus from board initialization code.
+ */
+static int __init omap_register_i2c_bus_cmdline(void)
+{
+        int i, err = 0;
+
+        for (i = 0; i < ARRAY_SIZE(i2c_rate); i++)
+                if (i2c_rate[i] & OMAP_I2C_CMDLINE_SETUP) {
+                        i2c_rate[i] &= ~OMAP_I2C_CMDLINE_SETUP;
+                        err = omap_i2c_add_bus(i + 1);
+                        if (err)
+                                goto out;
+                }
+
+out:
+        return err;
+}
+subsys_initcall(omap_register_i2c_bus_cmdline);
+
+/**
+ * omap_register_i2c_bus - register I2C bus with device descriptors
+ * @bus_id: bus id counting from number 1
+ * @clkrate: clock rate of the bus in kHz
+ * @info: pointer into I2C device descriptor table or NULL
+ * @len: number of descriptors in the table
+ *
+ * Returns 0 on success or an error code.
+ */
+int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
+                          struct i2c_board_info const *info,
+                          unsigned len)
+{
+        int err;
+
+        BUG_ON(bus_id < 1 || bus_id > omap_i2c_nr_ports());
+
+        if (info) {
+                err = i2c_register_board_info(bus_id, info, len);
+                if (err)
+                        return err;
+        }
+
+        if (!i2c_rate[bus_id - 1])
+                i2c_rate[bus_id - 1] = clkrate;
+        i2c_rate[bus_id - 1] &= ~OMAP_I2C_CMDLINE_SETUP;
+
+        return omap_i2c_add_bus(bus_id);
+}
diff --git a/arch/arm/plat-omap/include/mach/board-2430sdp.h b/arch/arm/plat-omap/include/mach/board-2430sdp.h
deleted file mode 100644
index 10d449ea7ed0..000000000000
--- a/arch/arm/plat-omap/include/mach/board-2430sdp.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/board-2430sdp.h
- *
- * Hardware definitions for TI OMAP2430 SDP board.
- *
- * Based on board-h4.h by Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP_2430SDP_H
-#define __ASM_ARCH_OMAP_2430SDP_H
-
-/* Placeholder for 2430SDP specific defines */
-#define OMAP24XX_ETHR_START             0x08000300
-#define OMAP24XX_ETHR_GPIO_IRQ          149
-#define SDP2430_CS0_BASE                0x04000000
-
-/* Function prototypes */
-extern void sdp2430_flash_init(void);
-extern void sdp2430_usb_init(void);
-
-#endif /* __ASM_ARCH_OMAP_2430SDP_H */
diff --git a/arch/arm/plat-omap/include/mach/board-apollon.h b/arch/arm/plat-omap/include/mach/board-apollon.h
deleted file mode 100644
index 61bd5e8f09b1..000000000000
--- a/arch/arm/plat-omap/include/mach/board-apollon.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/board-apollon.h
- *
- * Hardware definitions for Samsung OMAP24XX Apollon board.
- *
- * Initial creation by Kyungmin Park <kyungmin.park@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP_APOLLON_H
-#define __ASM_ARCH_OMAP_APOLLON_H
-
-#include <mach/cpu.h>
-
-extern void apollon_mmc_init(void);
-
-static inline int apollon_plus(void)
-{
-        /* The apollon plus has IDCODE revision 5 */
-        return omap_rev() & 0xc0;
-}
-
-/* Placeholder for APOLLON specific defines */
-#define APOLLON_ETHR_GPIO_IRQ           74
-
-#endif /*  __ASM_ARCH_OMAP_APOLLON_H */
-
diff --git a/arch/arm/plat-omap/include/mach/board-fsample.h b/arch/arm/plat-omap/include/mach/board-fsample.h
deleted file mode 100644
index cb3c5ae12776..000000000000
--- a/arch/arm/plat-omap/include/mach/board-fsample.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/board-fsample.h
- *
- * Board-specific goodies for TI F-Sample.
- *
- * Copyright (C) 2006 Google, Inc.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_OMAP_FSAMPLE_H
-#define __ASM_ARCH_OMAP_FSAMPLE_H
-
-/* fsample is pretty close to p2-sample */
-#include <mach/board-perseus2.h>
-
-#define fsample_cpld_read(reg) __raw_readb(reg)
-#define fsample_cpld_write(val, reg) __raw_writeb(val, reg)
-
-#define FSAMPLE_CPLD_BASE    0xE8100000
-#define FSAMPLE_CPLD_SIZE    SZ_4K
-#define FSAMPLE_CPLD_START   0x05080000
-
-#define FSAMPLE_CPLD_REG_A   (FSAMPLE_CPLD_BASE + 0x00)
-#define FSAMPLE_CPLD_SWITCH  (FSAMPLE_CPLD_BASE + 0x02)
-#define FSAMPLE_CPLD_UART    (FSAMPLE_CPLD_BASE + 0x02)
-#define FSAMPLE_CPLD_REG_B   (FSAMPLE_CPLD_BASE + 0x04)
-#define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06)
-#define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06)
-
-#define FSAMPLE_CPLD_BIT_BT_RESET         0
-#define FSAMPLE_CPLD_BIT_LCD_RESET        1
-#define FSAMPLE_CPLD_BIT_CAM_PWDN         2
-#define FSAMPLE_CPLD_BIT_CHARGER_ENABLE   3
-#define FSAMPLE_CPLD_BIT_SD_MMC_EN        4
-#define FSAMPLE_CPLD_BIT_aGPS_PWREN       5
-#define FSAMPLE_CPLD_BIT_BACKLIGHT        6
-#define FSAMPLE_CPLD_BIT_aGPS_EN_RESET    7
-#define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N    8
-#define FSAMPLE_CPLD_BIT_OTG_RESET        9
-
-#define fsample_cpld_set(bit) \
-    fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR)
-
-#define fsample_cpld_clear(bit) \
-    fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR)
-
-#endif
diff --git a/arch/arm/plat-omap/include/mach/board-h4.h b/arch/arm/plat-omap/include/mach/board-h4.h
deleted file mode 100644
index 7c3fa0f0a65e..000000000000
--- a/arch/arm/plat-omap/include/mach/board-h4.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/board-h4.h
- *
- * Hardware definitions for TI OMAP2420 H4 board.
- *
- * Initial creation by Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP_H4_H
-#define __ASM_ARCH_OMAP_H4_H
-
-/* MMC Prototypes */
-extern void h4_mmc_init(void);
-
-/* Placeholder for H4 specific defines */
-#define OMAP24XX_ETHR_GPIO_IRQ          92
-#endif /*  __ASM_ARCH_OMAP_H4_H */
-
diff --git a/arch/arm/plat-omap/include/mach/board-innovator.h b/arch/arm/plat-omap/include/mach/board-innovator.h
deleted file mode 100644
index 5ae3e79b9f9c..000000000000
--- a/arch/arm/plat-omap/include/mach/board-innovator.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/board-innovator.h
- *
- * Copyright (C) 2001 RidgeRun, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef __ASM_ARCH_OMAP_INNOVATOR_H
-#define __ASM_ARCH_OMAP_INNOVATOR_H
-
-#if defined (CONFIG_ARCH_OMAP15XX)
-
-#ifndef OMAP_SDRAM_DEVICE
-#define OMAP_SDRAM_DEVICE                       D256M_1X16_4B
-#endif
-
-#define OMAP1510P1_IMIF_PRI_VALUE               0x00
-#define OMAP1510P1_EMIFS_PRI_VALUE              0x00
-#define OMAP1510P1_EMIFF_PRI_VALUE              0x00
-
-#ifndef __ASSEMBLY__
-void fpga_write(unsigned char val, int reg);
-unsigned char fpga_read(int reg);
-#endif
-
-#endif /* CONFIG_ARCH_OMAP15XX */
-
-#if defined (CONFIG_ARCH_OMAP16XX)
-
-/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
-#define INNOVATOR1610_ETHR_START        0x04000300
-
-#endif /* CONFIG_ARCH_OMAP1610 */
-#endif /* __ASM_ARCH_OMAP_INNOVATOR_H */
diff --git a/arch/arm/plat-omap/include/mach/board-ldp.h b/arch/arm/plat-omap/include/mach/board-ldp.h
deleted file mode 100644
index f23399665212..000000000000
--- a/arch/arm/plat-omap/include/mach/board-ldp.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/board-ldp.h
- *
- * Hardware definitions for TI OMAP3 LDP.
- *
- * Copyright (C) 2008 Texas Instruments Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP_LDP_H
-#define __ASM_ARCH_OMAP_LDP_H
-
-extern void twl4030_bci_battery_init(void);
-
-#define TWL4030_IRQNUM          INT_34XX_SYS_NIRQ
-#define LDP_SMC911X_CS         1
-#define LDP_SMC911X_GPIO       152
-#define DEBUG_BASE             0x08000000
-#define OMAP34XX_ETHR_START    DEBUG_BASE
-#endif /* __ASM_ARCH_OMAP_LDP_H */
diff --git a/arch/arm/plat-omap/include/mach/board-nokia.h b/arch/arm/plat-omap/include/mach/board-nokia.h
deleted file mode 100644
index 2abbe001af8c..000000000000
--- a/arch/arm/plat-omap/include/mach/board-nokia.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/board-nokia.h
- *
- *  Information structures for Nokia-specific board config data
- *
- *  Copyright (C) 2005  Nokia Corporation
- */
-
-#ifndef _OMAP_BOARD_NOKIA_H
-#define _OMAP_BOARD_NOKIA_H
-
-#include <linux/types.h>
-
-#define OMAP_TAG_NOKIA_BT       0x4e01
-#define OMAP_TAG_WLAN_CX3110X   0x4e02
-#define OMAP_TAG_CBUS           0x4e03
-#define OMAP_TAG_EM_ASIC_BB5    0x4e04
-
-
-#define BT_CHIP_CSR             1
-#define BT_CHIP_TI              2
-
-#define BT_SYSCLK_12            1
-#define BT_SYSCLK_38_4          2
-
-struct omap_bluetooth_config {
-        u8    chip_type;
-        u8    bt_wakeup_gpio;
-        u8    host_wakeup_gpio;
-        u8    reset_gpio;
-        u8    bt_uart;
-        u8    bd_addr[6];
-        u8    bt_sysclk;
-};
-
-struct omap_wlan_cx3110x_config {
-        u8  chip_type;
-        s16 power_gpio;
-        s16 irq_gpio;
-        s16 spi_cs_gpio;
-};
-
-struct omap_cbus_config {
-        s16 clk_gpio;
-        s16 dat_gpio;
-        s16 sel_gpio;
-};
-
-struct omap_em_asic_bb5_config {
-        s16 retu_irq_gpio;
-        s16 tahvo_irq_gpio;
-};
-
-#endif
diff --git a/arch/arm/plat-omap/include/mach/board-omap3beagle.h b/arch/arm/plat-omap/include/mach/board-omap3beagle.h
deleted file mode 100644
index 3080d52d877a..000000000000
--- a/arch/arm/plat-omap/include/mach/board-omap3beagle.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/board-omap3beagle.h
- *
- * Hardware definitions for TI OMAP3 BEAGLE.
- *
- * Initial creation by Syed Mohammed Khasim <khasim@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP3_BEAGLE_H
-#define __ASM_ARCH_OMAP3_BEAGLE_H
-
-#endif /* __ASM_ARCH_OMAP3_BEAGLE_H */
-
diff --git a/arch/arm/plat-omap/include/mach/board-osk.h b/arch/arm/plat-omap/include/mach/board-osk.h
deleted file mode 100644
index 3850cb1f220a..000000000000
--- a/arch/arm/plat-omap/include/mach/board-osk.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/board-osk.h
- *
- * Hardware definitions for TI OMAP5912 OSK board.
- *
- * Written by Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP_OSK_H
-#define __ASM_ARCH_OMAP_OSK_H
-
-/* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
-#define OMAP_OSK_ETHR_START             0x04800300
-
-/* TPS65010 has four GPIOs.  nPG and LED2 can be treated like GPIOs with
- * alternate pin configurations for hardware-controlled blinking.
- */
-#define OSK_TPS_GPIO_BASE               (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */)
-#       define OSK_TPS_GPIO_USB_PWR_EN  (OSK_TPS_GPIO_BASE + 0)
-#       define OSK_TPS_GPIO_LED_D3      (OSK_TPS_GPIO_BASE + 1)
-#       define OSK_TPS_GPIO_LAN_RESET   (OSK_TPS_GPIO_BASE + 2)
-#       define OSK_TPS_GPIO_DSP_PWR_EN  (OSK_TPS_GPIO_BASE + 3)
-#       define OSK_TPS_GPIO_LED_D9      (OSK_TPS_GPIO_BASE + 4)
-#       define OSK_TPS_GPIO_LED_D2      (OSK_TPS_GPIO_BASE + 5)
-
-#endif /*  __ASM_ARCH_OMAP_OSK_H */
-
diff --git a/arch/arm/plat-omap/include/mach/board-overo.h b/arch/arm/plat-omap/include/mach/board-overo.h
deleted file mode 100644
index 7ecae66966d1..000000000000
--- a/arch/arm/plat-omap/include/mach/board-overo.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * board-overo.h (Gumstix Overo)
- *
- * Initial code: Steve Sakoman <steve@sakoman.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OVERO_H
-#define __ASM_ARCH_OVERO_H
-
-#define OVERO_GPIO_BT_XGATE     15
-#define OVERO_GPIO_W2W_NRESET   16
-#define OVERO_GPIO_BT_NRESET    164
-#define OVERO_GPIO_USBH_CPEN    168
-#define OVERO_GPIO_USBH_NRESET  183
-
-#endif /* ____ASM_ARCH_OVERO_H */
-
diff --git a/arch/arm/plat-omap/include/mach/board-palmte.h b/arch/arm/plat-omap/include/mach/board-palmte.h
deleted file mode 100644
index 6906cdebbcfb..000000000000
--- a/arch/arm/plat-omap/include/mach/board-palmte.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/board-palmte.h
- *
- * Hardware definitions for the Palm Tungsten E device.
- *
- * Maintainters :       http://palmtelinux.sf.net
- *                      palmtelinux-developpers@lists.sf.net
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __OMAP_BOARD_PALMTE_H
-#define __OMAP_BOARD_PALMTE_H
-
-#define PALMTE_USBDETECT_GPIO   0
-#define PALMTE_USB_OR_DC_GPIO   1
-#define PALMTE_TSC_GPIO         4
-#define PALMTE_PINTDAV_GPIO     6
-#define PALMTE_MMC_WP_GPIO      8
-#define PALMTE_MMC_POWER_GPIO   9
-#define PALMTE_HDQ_GPIO         11
-#define PALMTE_HEADPHONES_GPIO  14
-#define PALMTE_SPEAKER_GPIO     15
-#define PALMTE_DC_GPIO          OMAP_MPUIO(2)
-#define PALMTE_MMC_SWITCH_GPIO  OMAP_MPUIO(4)
-#define PALMTE_MMC1_GPIO        OMAP_MPUIO(6)
-#define PALMTE_MMC2_GPIO        OMAP_MPUIO(7)
-#define PALMTE_MMC3_GPIO        OMAP_MPUIO(11)
-
-#endif  /* __OMAP_BOARD_PALMTE_H */
diff --git a/arch/arm/plat-omap/include/mach/board-palmtt.h b/arch/arm/plat-omap/include/mach/board-palmtt.h
deleted file mode 100644
index e79f382b5931..000000000000
--- a/arch/arm/plat-omap/include/mach/board-palmtt.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/board-palmte.h
- *
- * Hardware definitions for the Palm Tungsten|T device.
- *
- * Maintainters :       Marek Vasut <marek.vasut@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __OMAP_BOARD_PALMTT_H
-#define __OMAP_BOARD_PALMTT_H
-
-#define PALMTT_USBDETECT_GPIO   0
-#define PALMTT_CABLE_GPIO       1
-#define PALMTT_LED_GPIO         3
-#define PALMTT_PENIRQ_GPIO      6
-#define PALMTT_MMC_WP_GPIO      8
-#define PALMTT_HDQ_GPIO         11
-
-#endif  /* __OMAP_BOARD_PALMTT_H */
diff --git a/arch/arm/plat-omap/include/mach/board-palmz71.h b/arch/arm/plat-omap/include/mach/board-palmz71.h
deleted file mode 100644
index b1d7d579b313..000000000000
--- a/arch/arm/plat-omap/include/mach/board-palmz71.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/board-palmz71.h
- *
- * Hardware definitions for the Palm Zire71 device.
- *
- * Maintainters :       Marek Vasut <marek.vasut@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __OMAP_BOARD_PALMZ71_H
-#define __OMAP_BOARD_PALMZ71_H
-
-#define PALMZ71_USBDETECT_GPIO  0
-#define PALMZ71_PENIRQ_GPIO     6
-#define PALMZ71_MMC_WP_GPIO     8
-#define PALMZ71_HDQ_GPIO        11
-
-#define PALMZ71_HOTSYNC_GPIO    OMAP_MPUIO(1)
-#define PALMZ71_CABLE_GPIO      OMAP_MPUIO(2)
-#define PALMZ71_SLIDER_GPIO     OMAP_MPUIO(3)
-#define PALMZ71_MMC_IN_GPIO     OMAP_MPUIO(4)
-
-#endif  /* __OMAP_BOARD_PALMZ71_H */
diff --git a/arch/arm/plat-omap/include/mach/board-perseus2.h b/arch/arm/plat-omap/include/mach/board-perseus2.h
deleted file mode 100644
index c06c3d717d57..000000000000
--- a/arch/arm/plat-omap/include/mach/board-perseus2.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/board-perseus2.h
- *
- *  Copyright 2003 by Texas Instruments Incorporated
- *    OMAP730 / Perseus2 support by Jean Pihet
- *
- * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
- * Author: RidgeRun, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef __ASM_ARCH_OMAP_PERSEUS2_H
-#define __ASM_ARCH_OMAP_PERSEUS2_H
-
-#include <mach/fpga.h>
-
-#ifndef OMAP_SDRAM_DEVICE
-#define OMAP_SDRAM_DEVICE               D256M_1X16_4B
-#endif
-
-#endif
diff --git a/arch/arm/plat-omap/include/mach/board-voiceblue.h b/arch/arm/plat-omap/include/mach/board-voiceblue.h
index ed6d346ee123..27916b210f57 100644
--- a/arch/arm/plat-omap/include/mach/board-voiceblue.h
+++ b/arch/arm/plat-omap/include/mach/board-voiceblue.h
@@ -14,7 +14,6 @@
 extern void voiceblue_wdt_enable(void);
 extern void voiceblue_wdt_disable(void);
 extern void voiceblue_wdt_ping(void);
-extern void voiceblue_reset(void);
 
 #endif /*  __ASM_ARCH_VOICEBLUE_H */
 
diff --git a/arch/arm/plat-omap/include/mach/board.h b/arch/arm/plat-omap/include/mach/board.h
index 9466772fc7c8..50ea79a0efa2 100644
--- a/arch/arm/plat-omap/include/mach/board.h
+++ b/arch/arm/plat-omap/include/mach/board.h
@@ -17,7 +17,6 @@
 /* Different peripheral ids */
 #define OMAP_TAG_CLOCK          0x4f01
 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03
-#define OMAP_TAG_USB            0x4f04
 #define OMAP_TAG_LCD            0x4f05
 #define OMAP_TAG_GPIO_SWITCH    0x4f06
 #define OMAP_TAG_UART           0x4f07
@@ -133,9 +132,6 @@ struct omap_version_config {
         char version[12];
 };
 
-
-#include <mach/board-nokia.h>
-
 struct omap_board_config_entry {
         u16 tag;
         u16 len;
diff --git a/arch/arm/plat-omap/include/mach/clkdev.h b/arch/arm/plat-omap/include/mach/clkdev.h
new file mode 100644
index 000000000000..730c49d1ebd8
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/clkdev.h
@@ -0,0 +1,13 @@
+#ifndef __MACH_CLKDEV_H
+#define __MACH_CLKDEV_H
+
+static inline int __clk_get(struct clk *clk)
+{
+        return 1;
+}
+
+static inline void __clk_put(struct clk *clk)
+{
+}
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index 719298554ed7..073a2c5569f0 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -17,11 +17,16 @@ struct module;
 struct clk;
 struct clockdomain;
 
+struct clkops {
+        int                     (*enable)(struct clk *);
+        void                    (*disable)(struct clk *);
+};
+
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
 
 struct clksel_rate {
-        u8                      div;
         u32                     val;
+        u8                      div;
         u8                      flags;
 };
 
@@ -34,24 +39,28 @@ struct dpll_data {
         void __iomem            *mult_div1_reg;
         u32                     mult_mask;
         u32                     div1_mask;
+        struct clk              *clk_bypass;
+        struct clk              *clk_ref;
+        void __iomem            *control_reg;
+        u32                     enable_mask;
+        unsigned int            rate_tolerance;
+        unsigned long           last_rounded_rate;
         u16                     last_rounded_m;
         u8                      last_rounded_n;
-        unsigned long           last_rounded_rate;
-        unsigned int            rate_tolerance;
-        u16                     max_multiplier;
+        u8                      min_divider;
         u8                      max_divider;
         u32                     max_tolerance;
+        u16                     max_multiplier;
 #  if defined(CONFIG_ARCH_OMAP3)
         u8                      modes;
-        void __iomem            *control_reg;
-        u32                     enable_mask;
+        void __iomem            *autoidle_reg;
+        void __iomem            *idlest_reg;
+        u32                     autoidle_mask;
+        u32                     freqsel_mask;
+        u32                     idlest_mask;
         u8                      auto_recal_bit;
         u8                      recal_en_bit;
         u8                      recal_st_bit;
-        void __iomem            *autoidle_reg;
-        u32                     autoidle_mask;
-        void __iomem            *idlest_reg;
-        u8                      idlest_bit;
 #  endif
 };
 
@@ -59,21 +68,21 @@ struct dpll_data {
 
 struct clk {
         struct list_head        node;
-        struct module           *owner;
+        const struct clkops     *ops;
         const char              *name;
         int                     id;
         struct clk              *parent;
+        struct list_head        children;
+        struct list_head        sibling;        /* node for children */
         unsigned long           rate;
         __u32                   flags;
         void __iomem            *enable_reg;
-        __u8                    enable_bit;
-        __s8                    usecount;
-        void                    (*recalc)(struct clk *);
+        unsigned long           (*recalc)(struct clk *);
         int                     (*set_rate)(struct clk *, unsigned long);
         long                    (*round_rate)(struct clk *, unsigned long);
         void                    (*init)(struct clk *);
-        int                     (*enable)(struct clk *);
-        void                    (*disable)(struct clk *);
+        __u8                    enable_bit;
+        __s8                    usecount;
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
         u8                      fixed_div;
         void __iomem            *clksel_reg;
@@ -99,7 +108,6 @@ struct clk_functions {
         long            (*clk_round_rate)(struct clk *clk, unsigned long rate);
         int             (*clk_set_rate)(struct clk *clk, unsigned long rate);
         int             (*clk_set_parent)(struct clk *clk, struct clk *parent);
-        struct clk *    (*clk_get_parent)(struct clk *clk);
         void            (*clk_allow_idle)(struct clk *clk);
         void            (*clk_deny_idle)(struct clk *clk);
         void            (*clk_disable_unused)(struct clk *clk);
@@ -110,42 +118,33 @@ struct clk_functions {
 
 extern unsigned int mpurate;
 
-extern int clk_init(struct clk_functions * custom_clocks);
+extern int clk_init(struct clk_functions *custom_clocks);
+extern void clk_init_one(struct clk *clk);
 extern int clk_register(struct clk *clk);
+extern void clk_reparent(struct clk *child, struct clk *parent);
 extern void clk_unregister(struct clk *clk);
 extern void propagate_rate(struct clk *clk);
 extern void recalculate_root_clocks(void);
-extern void followparent_recalc(struct clk * clk);
-extern void clk_allow_idle(struct clk *clk);
-extern void clk_deny_idle(struct clk *clk);
-extern int clk_get_usecount(struct clk *clk);
+extern unsigned long followparent_recalc(struct clk *clk);
 extern void clk_enable_init_clocks(void);
+#ifdef CONFIG_CPU_FREQ
+extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
+#endif
+
+extern const struct clkops clkops_null;
 
 /* Clock flags */
-#define RATE_CKCTL              (1 << 0)        /* Main fixed ratio clocks */
+/* bit 0 is free */
 #define RATE_FIXED              (1 << 1)        /* Fixed clock rate */
-#define RATE_PROPAGATES         (1 << 2)        /* Program children too */
-#define VIRTUAL_CLOCK           (1 << 3)        /* Composite clock from table */
-#define ALWAYS_ENABLED          (1 << 4)        /* Clock cannot be disabled */
+/* bits 2-4 are free */
 #define ENABLE_REG_32BIT        (1 << 5)        /* Use 32-bit access */
-#define VIRTUAL_IO_ADDRESS      (1 << 6)        /* Clock in virtual address */
 #define CLOCK_IDLE_CONTROL      (1 << 7)
 #define CLOCK_NO_IDLE_PARENT    (1 << 8)
 #define DELAYED_APP             (1 << 9)        /* Delay application of clock */
 #define CONFIG_PARTICIPANT      (1 << 10)       /* Fundamental clock */
 #define ENABLE_ON_INIT          (1 << 11)       /* Enable upon framework init */
 #define INVERT_ENABLE           (1 << 12)       /* 0 enables, 1 disables */
-/* bits 13-20 are currently free */
-#define CLOCK_IN_OMAP310        (1 << 21)
-#define CLOCK_IN_OMAP730        (1 << 22)
-#define CLOCK_IN_OMAP1510       (1 << 23)
-#define CLOCK_IN_OMAP16XX       (1 << 24)
-#define CLOCK_IN_OMAP242X       (1 << 25)
-#define CLOCK_IN_OMAP243X       (1 << 26)
-#define CLOCK_IN_OMAP343X       (1 << 27)       /* clocks common to all 343X */
-#define PARENT_CONTROLS_CLOCK   (1 << 28)
-#define CLOCK_IN_OMAP3430ES1    (1 << 29)       /* 3430ES1 clocks only */
-#define CLOCK_IN_OMAP3430ES2    (1 << 30)       /* 3430ES2 clocks only */
+/* bits 13-31 are currently free */
 
 /* Clksel_rate flags */
 #define DEFAULT_RATE            (1 << 0)
@@ -157,9 +156,4 @@ extern void clk_enable_init_clocks(void);
 #define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
 
 
-/* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
-#define CORE_CLK_SRC_32K                0
-#define CORE_CLK_SRC_DPLL               1
-#define CORE_CLK_SRC_DPLL_X2            2
-
 #endif
diff --git a/arch/arm/plat-omap/include/mach/clockdomain.h b/arch/arm/plat-omap/include/mach/clockdomain.h
index 1f51f0173784..b9d0dd2da89b 100644
--- a/arch/arm/plat-omap/include/mach/clockdomain.h
+++ b/arch/arm/plat-omap/include/mach/clockdomain.h
@@ -1,5 +1,5 @@
 /*
- * linux/include/asm-arm/arch-omap/clockdomain.h
+ * arch/arm/plat-omap/include/mach/clockdomain.h
  *
  * OMAP2/3 clockdomain framework functions
  *
@@ -48,11 +48,13 @@
  */
 struct clkdm_pwrdm_autodep {
 
-        /* Name of the powerdomain to add a wkdep/sleepdep on */
-        const char *pwrdm_name;
+        union {
+                /* Name of the powerdomain to add a wkdep/sleepdep on */
+                const char *name;
 
-        /* Powerdomain pointer (looked up at clkdm_init() time) */
-        struct powerdomain *pwrdm;
+                /* Powerdomain pointer (looked up at clkdm_init() time) */
+                struct powerdomain *ptr;
+        } pwrdm;
 
         /* OMAP chip types that this clockdomain dep is valid on */
         const struct omap_chip_id omap_chip;
@@ -64,8 +66,13 @@ struct clockdomain {
         /* Clockdomain name */
         const char *name;
 
-        /* Powerdomain enclosing this clockdomain */
-        const char *pwrdm_name;
+        union {
+                /* Powerdomain enclosing this clockdomain */
+                const char *name;
+
+                /* Powerdomain pointer assigned at clkdm_register() */
+                struct powerdomain *ptr;
+        } pwrdm;
 
         /* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */
         const u16 clktrctrl_mask;
@@ -79,9 +86,6 @@ struct clockdomain {
         /* Usecount tracking */
         atomic_t usecount;
 
-        /* Powerdomain pointer assigned at clkdm_register() */
-        struct powerdomain *pwrdm;
-
         struct list_head node;
 
 };
diff --git a/arch/arm/plat-omap/include/mach/common.h b/arch/arm/plat-omap/include/mach/common.h
index e746ec7e785e..0ecf36deb17b 100644
--- a/arch/arm/plat-omap/include/mach/common.h
+++ b/arch/arm/plat-omap/include/mach/common.h
@@ -65,7 +65,7 @@ void omap2_set_globals_343x(void);
 
 /* These get called from omap2_set_globals_xxxx(), do not call these */
 void omap2_set_globals_tap(struct omap_globals *);
-void omap2_set_globals_memory(struct omap_globals *);
+void omap2_set_globals_sdrc(struct omap_globals *);
 void omap2_set_globals_control(struct omap_globals *);
 void omap2_set_globals_prcm(struct omap_globals *);
 
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h
index a8e1178a9468..98b144252364 100644
--- a/arch/arm/plat-omap/include/mach/cpu.h
+++ b/arch/arm/plat-omap/include/mach/cpu.h
@@ -56,6 +56,14 @@ unsigned int omap_rev(void);
 #  define OMAP_NAME omap730
 # endif
 #endif
+#ifdef CONFIG_ARCH_OMAP850
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP1
+#  define MULTI_OMAP1
+# else
+#  define OMAP_NAME omap850
+# endif
+#endif
 #ifdef CONFIG_ARCH_OMAP15XX
 # ifdef OMAP_NAME
 #  undef  MULTI_OMAP1
@@ -105,7 +113,7 @@ unsigned int omap_rev(void);
 /*
  * Macros to group OMAP into cpu classes.
  * These can be used in most places.
- * cpu_is_omap7xx():    True for OMAP730
+ * cpu_is_omap7xx():    True for OMAP730, OMAP850
  * cpu_is_omap15xx():   True for OMAP1510, OMAP5910 and OMAP310
  * cpu_is_omap16xx():   True for OMAP1610, OMAP5912 and OMAP1710
  * cpu_is_omap24xx():   True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
@@ -153,6 +161,10 @@ IS_OMAP_SUBCLASS(343x, 0x343)
 #  undef  cpu_is_omap7xx
 #  define cpu_is_omap7xx()              is_omap7xx()
 # endif
+# if defined(CONFIG_ARCH_OMAP850)
+#  undef  cpu_is_omap7xx
+#  define cpu_is_omap7xx()              is_omap7xx()
+# endif
 # if defined(CONFIG_ARCH_OMAP15XX)
 #  undef  cpu_is_omap15xx
 #  define cpu_is_omap15xx()             is_omap15xx()
@@ -166,6 +178,10 @@ IS_OMAP_SUBCLASS(343x, 0x343)
 #  undef  cpu_is_omap7xx
 #  define cpu_is_omap7xx()              1
 # endif
+# if defined(CONFIG_ARCH_OMAP850)
+#  undef  cpu_is_omap7xx
+#  define cpu_is_omap7xx()              1
+# endif
 # if defined(CONFIG_ARCH_OMAP15XX)
 #  undef  cpu_is_omap15xx
 #  define cpu_is_omap15xx()             1
@@ -219,6 +235,7 @@ IS_OMAP_SUBCLASS(343x, 0x343)
  * These are only rarely needed.
  * cpu_is_omap330():    True for OMAP330
  * cpu_is_omap730():    True for OMAP730
+ * cpu_is_omap850():    True for OMAP850
  * cpu_is_omap1510():   True for OMAP1510
  * cpu_is_omap1610():   True for OMAP1610
  * cpu_is_omap1611():   True for OMAP1611
@@ -241,6 +258,7 @@ static inline int is_omap ##type (void)			\
 
 IS_OMAP_TYPE(310, 0x0310)
 IS_OMAP_TYPE(730, 0x0730)
+IS_OMAP_TYPE(850, 0x0850)
 IS_OMAP_TYPE(1510, 0x1510)
 IS_OMAP_TYPE(1610, 0x1610)
 IS_OMAP_TYPE(1611, 0x1611)
@@ -255,6 +273,7 @@ IS_OMAP_TYPE(3430, 0x3430)
 
 #define cpu_is_omap310()                0
 #define cpu_is_omap730()                0
+#define cpu_is_omap850()                0
 #define cpu_is_omap1510()               0
 #define cpu_is_omap1610()               0
 #define cpu_is_omap5912()               0
@@ -272,12 +291,22 @@ IS_OMAP_TYPE(3430, 0x3430)
 #  undef  cpu_is_omap730
 #  define cpu_is_omap730()              is_omap730()
 # endif
+# if defined(CONFIG_ARCH_OMAP850)
+#  undef  cpu_is_omap850
+#  define cpu_is_omap850()              is_omap850()
+# endif
 #else
 # if defined(CONFIG_ARCH_OMAP730)
 #  undef  cpu_is_omap730
 #  define cpu_is_omap730()              1
 # endif
 #endif
+#else
+# if defined(CONFIG_ARCH_OMAP850)
+#  undef  cpu_is_omap850
+#  define cpu_is_omap850()              1
+# endif
+#endif
 
 /*
  * Whether we have MULTI_OMAP1 or not, we still need to distinguish
@@ -320,7 +349,7 @@ IS_OMAP_TYPE(3430, 0x3430)
 #endif
 
 /* Macros to detect if we have OMAP1 or OMAP2 */
-#define cpu_class_is_omap1()    (cpu_is_omap730() || cpu_is_omap15xx() || \
+#define cpu_class_is_omap1()    (cpu_is_omap7xx() || cpu_is_omap15xx() || \
                                 cpu_is_omap16xx())
 #define cpu_class_is_omap2()    (cpu_is_omap24xx() || cpu_is_omap34xx())
 
@@ -355,13 +384,27 @@ IS_OMAP_TYPE(3430, 0x3430)
  * use omap_chip_is().
  *
  */
-#define CHIP_IS_OMAP2420       (1 << 0)
-#define CHIP_IS_OMAP2430       (1 << 1)
-#define CHIP_IS_OMAP3430       (1 << 2)
-#define CHIP_IS_OMAP3430ES1    (1 << 3)
-#define CHIP_IS_OMAP3430ES2    (1 << 4)
+#define CHIP_IS_OMAP2420                (1 << 0)
+#define CHIP_IS_OMAP2430                (1 << 1)
+#define CHIP_IS_OMAP3430                (1 << 2)
+#define CHIP_IS_OMAP3430ES1             (1 << 3)
+#define CHIP_IS_OMAP3430ES2             (1 << 4)
+#define CHIP_IS_OMAP3430ES3_0           (1 << 5)
+#define CHIP_IS_OMAP3430ES3_1           (1 << 6)
+
+#define CHIP_IS_OMAP24XX                (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
+
+/*
+ * "GE" here represents "greater than or equal to" in terms of ES
+ * levels.  So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430
+ * chips at ES2 and beyond, but not, for example, any OMAP lines after
+ * OMAP3.
+ */
+#define CHIP_GE_OMAP3430ES2             (CHIP_IS_OMAP3430ES2 | \
+                                         CHIP_IS_OMAP3430ES3_0 | \
+                                         CHIP_IS_OMAP3430ES3_1)
+#define CHIP_GE_OMAP3430ES3_1           (CHIP_IS_OMAP3430ES3_1)
 
-#define CHIP_IS_OMAP24XX       (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
 
 int omap_chip_is(struct omap_chip_id oci);
 int omap_type(void);
@@ -378,5 +421,3 @@ int omap_type(void);
 void omap2_check_revision(void);
 
 #endif    /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */
-
-#endif
diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/mach/gpio.h
index 8d9dfe314387..2b22a8799bc6 100644
--- a/arch/arm/plat-omap/include/mach/gpio.h
+++ b/arch/arm/plat-omap/include/mach/gpio.h
@@ -31,7 +31,8 @@
 
 #define OMAP_MPUIO_BASE                 0xfffb5000
 
-#ifdef CONFIG_ARCH_OMAP730
+#if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850))
+
 #define OMAP_MPUIO_INPUT_LATCH          0x00
 #define OMAP_MPUIO_OUTPUT               0x02
 #define OMAP_MPUIO_IO_CNTL              0x04
diff --git a/arch/arm/plat-omap/include/mach/gpmc.h b/arch/arm/plat-omap/include/mach/gpmc.h
index 45b678439bb7..921b16532ff5 100644
--- a/arch/arm/plat-omap/include/mach/gpmc.h
+++ b/arch/arm/plat-omap/include/mach/gpmc.h
@@ -103,6 +103,6 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
 extern void gpmc_cs_free(int cs);
 extern int gpmc_cs_set_reserved(int cs, int reserved);
 extern int gpmc_cs_reserved(int cs);
-extern void gpmc_init(void);
+extern void __init gpmc_init(void);
 
 #endif
diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/mach/hardware.h
index 6589ddbb63b2..3dc423ed3e80 100644
--- a/arch/arm/plat-omap/include/mach/hardware.h
+++ b/arch/arm/plat-omap/include/mach/hardware.h
@@ -286,78 +286,4 @@
 #include "omap24xx.h"
 #include "omap34xx.h"
 
-#ifndef __ASSEMBLER__
-
-/*
- * ---------------------------------------------------------------------------
- * Board specific defines
- * ---------------------------------------------------------------------------
- */
-
-#ifdef CONFIG_MACH_OMAP_INNOVATOR
-#include "board-innovator.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP_H2
-#include "board-h2.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP_PERSEUS2
-#include "board-perseus2.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP_FSAMPLE
-#include "board-fsample.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP_H3
-#include "board-h3.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP_H4
-#include "board-h4.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP_2430SDP
-#include "board-2430sdp.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_BEAGLE
-#include "board-omap3beagle.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP_LDP
-#include "board-ldp.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP_APOLLON
-#include "board-apollon.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP_OSK
-#include "board-osk.h"
-#endif
-
-#ifdef CONFIG_MACH_VOICEBLUE
-#include "board-voiceblue.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP_PALMTE
-#include "board-palmte.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP_PALMZ71
-#include "board-palmz71.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP_PALMTT
-#include "board-palmtt.h"
-#endif
-
-#ifdef CONFIG_MACH_SX1
-#include "board-sx1.h"
-#endif
-
-#endif /* !__ASSEMBLER__ */
-
 #endif  /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h
index d92bf7964481..0610d7e2b3d7 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/mach/io.h
@@ -185,11 +185,13 @@
 #define omap_writew(v,a)        __raw_writew(v, IO_ADDRESS(a))
 #define omap_writel(v,a)        __raw_writel(v, IO_ADDRESS(a))
 
+struct omap_sdrc_params;
+
 extern void omap1_map_common_io(void);
 extern void omap1_init_common_hw(void);
 
 extern void omap2_map_common_io(void);
-extern void omap2_init_common_hw(void);
+extern void omap2_init_common_hw(struct omap_sdrc_params *sp);
 
 #define __arch_ioremap(p,s,t)   omap_ioremap(p,s,t)
 #define __arch_iounmap(v)       omap_iounmap(v)
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h
index bed5274c910a..7f57ee66f364 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/mach/irqs.h
@@ -105,6 +105,29 @@
 #define INT_730_SPGIO_WR        29
 
 /*
+ * OMAP-850 specific IRQ numbers for interrupt handler 1
+ */
+#define INT_850_IH2_FIQ         0
+#define INT_850_IH2_IRQ         1
+#define INT_850_USB_NON_ISO     2
+#define INT_850_USB_ISO         3
+#define INT_850_ICR             4
+#define INT_850_EAC             5
+#define INT_850_GPIO_BANK1      6
+#define INT_850_GPIO_BANK2      7
+#define INT_850_GPIO_BANK3      8
+#define INT_850_McBSP2TX        10
+#define INT_850_McBSP2RX        11
+#define INT_850_McBSP2RX_OVF    12
+#define INT_850_LCD_LINE        14
+#define INT_850_GSM_PROTECT     15
+#define INT_850_TIMER3          16
+#define INT_850_GPIO_BANK5      17
+#define INT_850_GPIO_BANK6      18
+#define INT_850_SPGIO_WR        29
+
+
+/*
  * IRQ numbers for interrupt handler 2
  *
  * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
@@ -237,6 +260,64 @@
 #define INT_730_DMA_CH15        (62 + IH2_BASE)
 #define INT_730_NAND            (63 + IH2_BASE)
 
+/*
+ * OMAP-850 specific IRQ numbers for interrupt handler 2
+ */
+#define INT_850_HW_ERRORS       (0 + IH2_BASE)
+#define INT_850_NFIQ_PWR_FAIL   (1 + IH2_BASE)
+#define INT_850_CFCD            (2 + IH2_BASE)
+#define INT_850_CFIREQ          (3 + IH2_BASE)
+#define INT_850_I2C             (4 + IH2_BASE)
+#define INT_850_PCC             (5 + IH2_BASE)
+#define INT_850_MPU_EXT_NIRQ    (6 + IH2_BASE)
+#define INT_850_SPI_100K_1      (7 + IH2_BASE)
+#define INT_850_SYREN_SPI       (8 + IH2_BASE)
+#define INT_850_VLYNQ           (9 + IH2_BASE)
+#define INT_850_GPIO_BANK4      (10 + IH2_BASE)
+#define INT_850_McBSP1TX        (11 + IH2_BASE)
+#define INT_850_McBSP1RX        (12 + IH2_BASE)
+#define INT_850_McBSP1RX_OF     (13 + IH2_BASE)
+#define INT_850_UART_MODEM_IRDA_2 (14 + IH2_BASE)
+#define INT_850_UART_MODEM_1    (15 + IH2_BASE)
+#define INT_850_MCSI            (16 + IH2_BASE)
+#define INT_850_uWireTX         (17 + IH2_BASE)
+#define INT_850_uWireRX         (18 + IH2_BASE)
+#define INT_850_SMC_CD          (19 + IH2_BASE)
+#define INT_850_SMC_IREQ        (20 + IH2_BASE)
+#define INT_850_HDQ_1WIRE       (21 + IH2_BASE)
+#define INT_850_TIMER32K        (22 + IH2_BASE)
+#define INT_850_MMC_SDIO        (23 + IH2_BASE)
+#define INT_850_UPLD            (24 + IH2_BASE)
+#define INT_850_USB_HHC_1       (27 + IH2_BASE)
+#define INT_850_USB_HHC_2       (28 + IH2_BASE)
+#define INT_850_USB_GENI        (29 + IH2_BASE)
+#define INT_850_USB_OTG         (30 + IH2_BASE)
+#define INT_850_CAMERA_IF       (31 + IH2_BASE)
+#define INT_850_RNG             (32 + IH2_BASE)
+#define INT_850_DUAL_MODE_TIMER (33 + IH2_BASE)
+#define INT_850_DBB_RF_EN       (34 + IH2_BASE)
+#define INT_850_MPUIO_KEYPAD    (35 + IH2_BASE)
+#define INT_850_SHA1_MD5        (36 + IH2_BASE)
+#define INT_850_SPI_100K_2      (37 + IH2_BASE)
+#define INT_850_RNG_IDLE        (38 + IH2_BASE)
+#define INT_850_MPUIO           (39 + IH2_BASE)
+#define INT_850_LLPC_LCD_CTRL_CAN_BE_OFF        (40 + IH2_BASE)
+#define INT_850_LLPC_OE_FALLING (41 + IH2_BASE)
+#define INT_850_LLPC_OE_RISING  (42 + IH2_BASE)
+#define INT_850_LLPC_VSYNC      (43 + IH2_BASE)
+#define INT_850_WAKE_UP_REQ     (46 + IH2_BASE)
+#define INT_850_DMA_CH6         (53 + IH2_BASE)
+#define INT_850_DMA_CH7         (54 + IH2_BASE)
+#define INT_850_DMA_CH8         (55 + IH2_BASE)
+#define INT_850_DMA_CH9         (56 + IH2_BASE)
+#define INT_850_DMA_CH10        (57 + IH2_BASE)
+#define INT_850_DMA_CH11        (58 + IH2_BASE)
+#define INT_850_DMA_CH12        (59 + IH2_BASE)
+#define INT_850_DMA_CH13        (60 + IH2_BASE)
+#define INT_850_DMA_CH14        (61 + IH2_BASE)
+#define INT_850_DMA_CH15        (62 + IH2_BASE)
+#define INT_850_NAND            (63 + IH2_BASE)
+
 #define INT_24XX_SYS_NIRQ       7
 #define INT_24XX_SDMA_IRQ0      12
 #define INT_24XX_SDMA_IRQ1      13
@@ -341,7 +422,7 @@
 
 #define INT_34XX_BENCH_MPU_EMUL 3
 
-/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
+/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
  * 16 MPUIO lines */
 #define OMAP_MAX_GPIO_LINES     192
 #define IH_GPIO_BASE            (128 + IH2_BASE)
diff --git a/arch/arm/plat-omap/include/mach/mailbox.h b/arch/arm/plat-omap/include/mach/mailbox.h
index 7cbed9332e16..b7a6991814ec 100644
--- a/arch/arm/plat-omap/include/mach/mailbox.h
+++ b/arch/arm/plat-omap/include/mach/mailbox.h
@@ -33,6 +33,9 @@ struct omap_mbox_ops {
         void            (*disable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
         void            (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
         int             (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
+        /* ctx */
+        void            (*save_ctx)(struct omap_mbox *mbox);
+        void            (*restore_ctx)(struct omap_mbox *mbox);
 };
 
 struct omap_mbox_queue {
@@ -53,7 +56,7 @@ struct omap_mbox {
 
         mbox_msg_t              seq_snd, seq_rcv;
 
-        struct device           dev;
+        struct device           *dev;
 
         struct omap_mbox        *next;
         void                    *priv;
@@ -67,7 +70,27 @@ void omap_mbox_init_seq(struct omap_mbox *);
 struct omap_mbox *omap_mbox_get(const char *);
 void omap_mbox_put(struct omap_mbox *);
 
-int omap_mbox_register(struct omap_mbox *);
+int omap_mbox_register(struct device *parent, struct omap_mbox *);
 int omap_mbox_unregister(struct omap_mbox *);
 
+static inline void omap_mbox_save_ctx(struct omap_mbox *mbox)
+{
+        if (!mbox->ops->save_ctx) {
+                dev_err(mbox->dev, "%s:\tno save\n", __func__);
+                return;
+        }
+
+        mbox->ops->save_ctx(mbox);
+}
+
+static inline void omap_mbox_restore_ctx(struct omap_mbox *mbox)
+{
+        if (!mbox->ops->restore_ctx) {
+                dev_err(mbox->dev, "%s:\tno restore\n", __func__);
+                return;
+        }
+
+        mbox->ops->restore_ctx(mbox);
+}
+
 #endif /* MAILBOX_H */
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h
index 113c2466c86a..bb154ea76769 100644
--- a/arch/arm/plat-omap/include/mach/mcbsp.h
+++ b/arch/arm/plat-omap/include/mach/mcbsp.h
@@ -344,8 +344,6 @@ struct omap_mcbsp_platform_data {
         u8 dma_rx_sync, dma_tx_sync;
         u16 rx_irq, tx_irq;
         struct omap_mcbsp_ops *ops;
-        char const **clk_names;
-        int num_clks;
 };
 
 struct omap_mcbsp {
@@ -377,8 +375,8 @@ struct omap_mcbsp {
         /* Protect the field .free, while checking if the mcbsp is in use */
         spinlock_t lock;
         struct omap_mcbsp_platform_data *pdata;
-        struct clk **clks;
-        int num_clks;
+        struct clk *iclk;
+        struct clk *fclk;
 };
 extern struct omap_mcbsp **mcbsp_ptr;
 extern int omap_mcbsp_count;
diff --git a/arch/arm/plat-omap/include/mach/memory.h b/arch/arm/plat-omap/include/mach/memory.h
index d6b5ca6c7da2..99ed564d9277 100644
--- a/arch/arm/plat-omap/include/mach/memory.h
+++ b/arch/arm/plat-omap/include/mach/memory.h
@@ -61,9 +61,11 @@
 #define lbus_to_virt(x)         ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
 #define is_lbus_device(dev)     (cpu_is_omap15xx() && dev && (strncmp(dev_name(dev), "ohci", 4) == 0))
 
-#define __arch_page_to_dma(dev, page)   ({is_lbus_device(dev) ? \
-                                        (dma_addr_t)virt_to_lbus(page_address(page)) : \
-                                        (dma_addr_t)__virt_to_phys(page_address(page));})
+#define __arch_page_to_dma(dev, page)   \
+        ({ dma_addr_t __dma = page_to_phys(page); \
+           if (is_lbus_device(dev)) \
+                __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \
+           __dma; })
 
 #define __arch_dma_to_virt(dev, addr)   ({ (void *) (is_lbus_device(dev) ? \
                                                 lbus_to_virt(addr) : \
diff --git a/arch/arm/plat-omap/include/mach/mmc.h b/arch/arm/plat-omap/include/mach/mmc.h
index 73a9e15031b1..4435bd434e17 100644
--- a/arch/arm/plat-omap/include/mach/mmc.h
+++ b/arch/arm/plat-omap/include/mach/mmc.h
@@ -37,6 +37,8 @@
 #define OMAP_MMC_MAX_SLOTS      2
 
 struct omap_mmc_platform_data {
+        /* back-link to device */
+        struct device *dev;
 
         /* number of slots per controller */
         unsigned nr_slots:2;
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h
index f4362b8682c7..85a621705766 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -61,6 +61,16 @@
                                         .pull_bit = bit, \
                                         .pull_val = status,
 
+#define MUX_REG_850(reg, mode_offset, mode) .mux_reg_name = "OMAP850_IO_CONF_"#reg, \
+                                        .mux_reg = OMAP850_IO_CONF_##reg, \
+                                        .mask_offset = mode_offset, \
+                                        .mask = mode,
+
+#define PULL_REG_850(reg, bit, status)  .pull_name = "OMAP850_IO_CONF_"#reg, \
+                                        .pull_reg = OMAP850_IO_CONF_##reg, \
+                                        .pull_bit = bit, \
+                                        .pull_val = status,
+
 #else
 
 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
@@ -83,6 +93,15 @@
                                         .pull_bit = bit, \
                                         .pull_val = status,
 
+#define MUX_REG_850(reg, mode_offset, mode) \
+                                        .mux_reg = OMAP850_IO_CONF_##reg, \
+                                        .mask_offset = mode_offset, \
+                                        .mask = mode,
+
+#define PULL_REG_850(reg, bit, status)  .pull_reg = OMAP850_IO_CONF_##reg, \
+                                        .pull_bit = bit, \
+                                        .pull_val = status,
+
 #endif /* CONFIG_OMAP_MUX_DEBUG */
 
 #define MUX_CFG(desc, mux_reg, mode_offset, mode,       \
@@ -98,7 +117,7 @@
 
 
 /*
- * OMAP730 has a slightly different config for the pin mux.
+ * OMAP730/850 has a slightly different config for the pin mux.
  * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and
  *   not the FUNC_MUX_CTRL_x regs from hardware.h
  * - for pull-up/down, only has one enable bit which is is in the same register
@@ -114,6 +133,17 @@
         PU_PD_REG(NA, 0)                \
 },
 
+#define MUX_CFG_850(desc, mux_reg, mode_offset, mode,   \
+                   pull_bit, pull_status, debug_status)\
+{                                                       \
+        .name =  desc,                                  \
+        .debug = debug_status,                          \
+        MUX_REG_850(mux_reg, mode_offset, mode)         \
+        PULL_REG_850(mux_reg, pull_bit, pull_status)    \
+        PU_PD_REG(NA, 0)                \
+},
+
+
 #define MUX_CFG_24XX(desc, reg_offset, mode,                    \
                                 pull_en, pull_mode, dbg)        \
 {                                                               \
@@ -221,6 +251,26 @@ enum omap730_index {
         W17_730_USB_VBUSI,
 };
 
+enum omap850_index {
+        /* OMAP 850 keyboard */
+        E2_850_KBR0,
+        J7_850_KBR1,
+        E1_850_KBR2,
+        F3_850_KBR3,
+        D2_850_KBR4,
+        C2_850_KBC0,
+        D3_850_KBC1,
+        E4_850_KBC2,
+        F4_850_KBC3,
+        E3_850_KBC4,
+
+        /* USB */
+        AA17_850_USB_DM,
+        W16_850_USB_PU_EN,
+        W17_850_USB_VBUSI,
+};
+
+
 enum omap1xxx_index {
         /* UART1 (BT_UART_GATING)*/
         UART1_TX = 0,
@@ -788,7 +838,20 @@ enum omap34xx_index {
          *  - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown
          *  - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx)
          */
+        AF26_34XX_GPIO0,
+        AF22_34XX_GPIO9,
         AH8_34XX_GPIO29,
+        U8_34XX_GPIO54_OUT,
+        U8_34XX_GPIO54_DOWN,
+        L8_34XX_GPIO63,
+        G25_34XX_GPIO86_OUT,
+        AG4_34XX_GPIO134_OUT,
+        AE4_34XX_GPIO136_OUT,
+        AF6_34XX_GPIO140_UP,
+        AE6_34XX_GPIO141,
+        AF5_34XX_GPIO142,
+        AE5_34XX_GPIO143,
+        H19_34XX_GPIO164_OUT,
         J25_34XX_GPIO170,
 };
 
diff --git a/arch/arm/plat-omap/include/mach/omap34xx.h b/arch/arm/plat-omap/include/mach/omap34xx.h
index 8e0479fff05a..ab640151d3ec 100644
--- a/arch/arm/plat-omap/include/mach/omap34xx.h
+++ b/arch/arm/plat-omap/include/mach/omap34xx.h
@@ -49,11 +49,39 @@
 #define OMAP343X_CTRL_BASE      OMAP343X_SCM_BASE
 
 #define OMAP34XX_IC_BASE        0x48200000
+
+#define OMAP3430_ISP_BASE               (L4_34XX_BASE + 0xBC000)
+#define OMAP3430_ISP_CBUFF_BASE         (OMAP3430_ISP_BASE + 0x0100)
+#define OMAP3430_ISP_CCP2_BASE          (OMAP3430_ISP_BASE + 0x0400)
+#define OMAP3430_ISP_CCDC_BASE          (OMAP3430_ISP_BASE + 0x0600)
+#define OMAP3430_ISP_HIST_BASE          (OMAP3430_ISP_BASE + 0x0A00)
+#define OMAP3430_ISP_H3A_BASE           (OMAP3430_ISP_BASE + 0x0C00)
+#define OMAP3430_ISP_PREV_BASE          (OMAP3430_ISP_BASE + 0x0E00)
+#define OMAP3430_ISP_RESZ_BASE          (OMAP3430_ISP_BASE + 0x1000)
+#define OMAP3430_ISP_SBL_BASE           (OMAP3430_ISP_BASE + 0x1200)
+#define OMAP3430_ISP_MMU_BASE           (OMAP3430_ISP_BASE + 0x1400)
+#define OMAP3430_ISP_CSI2A_BASE         (OMAP3430_ISP_BASE + 0x1800)
+#define OMAP3430_ISP_CSI2PHY_BASE       (OMAP3430_ISP_BASE + 0x1970)
+
+#define OMAP3430_ISP_END                (OMAP3430_ISP_BASE         + 0x06F)
+#define OMAP3430_ISP_CBUFF_END          (OMAP3430_ISP_CBUFF_BASE   + 0x077)
+#define OMAP3430_ISP_CCP2_END           (OMAP3430_ISP_CCP2_BASE    + 0x1EF)
+#define OMAP3430_ISP_CCDC_END           (OMAP3430_ISP_CCDC_BASE    + 0x0A7)
+#define OMAP3430_ISP_HIST_END           (OMAP3430_ISP_HIST_BASE    + 0x047)
+#define OMAP3430_ISP_H3A_END            (OMAP3430_ISP_H3A_BASE     + 0x05F)
+#define OMAP3430_ISP_PREV_END           (OMAP3430_ISP_PREV_BASE    + 0x09F)
+#define OMAP3430_ISP_RESZ_END           (OMAP3430_ISP_RESZ_BASE    + 0x0AB)
+#define OMAP3430_ISP_SBL_END            (OMAP3430_ISP_SBL_BASE     + 0x0FB)
+#define OMAP3430_ISP_MMU_END            (OMAP3430_ISP_MMU_BASE     + 0x06F)
+#define OMAP3430_ISP_CSI2A_END          (OMAP3430_ISP_CSI2A_BASE   + 0x16F)
+#define OMAP3430_ISP_CSI2PHY_END        (OMAP3430_ISP_CSI2PHY_BASE + 0x007)
+
 #define OMAP34XX_IVA_INTC_BASE  0x40000000
 #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
 #define OMAP34XX_HSUSB_HOST_BASE        (L4_34XX_BASE + 0x64000)
 #define OMAP34XX_USBTLL_BASE    (L4_34XX_BASE + 0x62000)
 
+#define OMAP34XX_MAILBOX_BASE           (L4_34XX_BASE + 0x94000)
 
 #if defined(CONFIG_ARCH_OMAP3430)
 
diff --git a/arch/arm/plat-omap/include/mach/omap850.h b/arch/arm/plat-omap/include/mach/omap850.h
new file mode 100644
index 000000000000..c33f67981712
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/omap850.h
@@ -0,0 +1,102 @@
+/* arch/arm/plat-omap/include/mach/omap850.h
+ *
+ * Hardware definitions for TI OMAP850 processor.
+ *
+ * Derived from omap730.h by Zebediah C. McClure <zmc@lurian.net>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP850_H
+#define __ASM_ARCH_OMAP850_H
+
+/*
+ * ----------------------------------------------------------------------------
+ * Base addresses
+ * ----------------------------------------------------------------------------
+ */
+
+/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
+
+#define OMAP850_DSP_BASE        0xE0000000
+#define OMAP850_DSP_SIZE        0x50000
+#define OMAP850_DSP_START       0xE0000000
+
+#define OMAP850_DSPREG_BASE     0xE1000000
+#define OMAP850_DSPREG_SIZE     SZ_128K
+#define OMAP850_DSPREG_START    0xE1000000
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP850 specific configuration registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP850_CONFIG_BASE     0xfffe1000
+#define OMAP850_IO_CONF_0       0xfffe1070
+#define OMAP850_IO_CONF_1       0xfffe1074
+#define OMAP850_IO_CONF_2       0xfffe1078
+#define OMAP850_IO_CONF_3       0xfffe107c
+#define OMAP850_IO_CONF_4       0xfffe1080
+#define OMAP850_IO_CONF_5       0xfffe1084
+#define OMAP850_IO_CONF_6       0xfffe1088
+#define OMAP850_IO_CONF_7       0xfffe108c
+#define OMAP850_IO_CONF_8       0xfffe1090
+#define OMAP850_IO_CONF_9       0xfffe1094
+#define OMAP850_IO_CONF_10      0xfffe1098
+#define OMAP850_IO_CONF_11      0xfffe109c
+#define OMAP850_IO_CONF_12      0xfffe10a0
+#define OMAP850_IO_CONF_13      0xfffe10a4
+
+#define OMAP850_MODE_1          0xfffe1010
+#define OMAP850_MODE_2          0xfffe1014
+
+/* CSMI specials: in terms of base + offset */
+#define OMAP850_MODE2_OFFSET    0x14
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP850 traffic controller configuration registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP850_FLASH_CFG_0     0xfffecc10
+#define OMAP850_FLASH_ACFG_0    0xfffecc50
+#define OMAP850_FLASH_CFG_1     0xfffecc14
+#define OMAP850_FLASH_ACFG_1    0xfffecc54
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP850 DSP control registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP850_ICR_BASE        0xfffbb800
+#define OMAP850_DSP_M_CTL       0xfffbb804
+#define OMAP850_DSP_MMU_BASE    0xfffed200
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP850 PCC_UPLD configuration registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP850_PCC_UPLD_CTRL_BASE      (0xfffe0900)
+#define OMAP850_PCC_UPLD_CTRL           (OMAP850_PCC_UPLD_CTRL_BASE + 0x00)
+
+#endif /*  __ASM_ARCH_OMAP850_H */
+
diff --git a/arch/arm/plat-omap/include/mach/pm.h b/arch/arm/plat-omap/include/mach/pm.h
index 37e2f0f38b46..ce6ee7927537 100644
--- a/arch/arm/plat-omap/include/mach/pm.h
+++ b/arch/arm/plat-omap/include/mach/pm.h
@@ -118,18 +118,6 @@
 extern void prevent_idle_sleep(void);
 extern void allow_idle_sleep(void);
 
-/**
- * clk_deny_idle - Prevents the clock from being idled during MPU idle
- * @clk: clock signal handle
- */
-void clk_deny_idle(struct clk *clk);
-
-/**
- * clk_allow_idle - Counters previous clk_deny_idle
- * @clk: clock signal handle
- */
-void clk_allow_idle(struct clk *clk);
-
 extern void omap_pm_idle(void);
 extern void omap_pm_suspend(void);
 extern void omap730_cpu_suspend(unsigned short, unsigned short);
diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h b/arch/arm/plat-omap/include/mach/powerdomain.h
index 2806a9c8e4d7..69c9e675d8ee 100644
--- a/arch/arm/plat-omap/include/mach/powerdomain.h
+++ b/arch/arm/plat-omap/include/mach/powerdomain.h
@@ -50,9 +50,9 @@
 
 /*
  * Maximum number of clockdomains that can be associated with a powerdomain.
- * CORE powerdomain is probably the worst case.
+ * CORE powerdomain on OMAP3 is the worst case
  */
-#define PWRDM_MAX_CLKDMS        3
+#define PWRDM_MAX_CLKDMS        4
 
 /* XXX A completely arbitrary number. What is reasonable here? */
 #define PWRDM_TRANSITION_BAILOUT 100000
@@ -145,6 +145,7 @@ int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
 
 int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
 int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
+int pwrdm_read_pwrst(struct powerdomain *pwrdm);
 int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
 int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
 
diff --git a/arch/arm/plat-omap/include/mach/prcm.h b/arch/arm/plat-omap/include/mach/prcm.h
index 56eba0fd6f6a..24ac3c715912 100644
--- a/arch/arm/plat-omap/include/mach/prcm.h
+++ b/arch/arm/plat-omap/include/mach/prcm.h
@@ -20,10 +20,11 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  */
 
-#ifndef __ASM_ARM_ARCH_DPM_PRCM_H
-#define __ASM_ARM_ARCH_DPM_PRCM_H
+#ifndef __ASM_ARM_ARCH_OMAP_PRCM_H
+#define __ASM_ARM_ARCH_OMAP_PRCM_H
 
 u32 omap_prcm_get_reset_sources(void);
+void omap_prcm_arch_reset(char mode);
 
 #endif
 
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h
index a98c6c3beb2c..adc73522491f 100644
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/mach/sdrc.h
@@ -4,10 +4,12 @@
 /*
  * OMAP2/3 SDRC/SMS register definitions
  *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Copyright (C) 2007 Nokia Corporation
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
  *
- * Written by Paul Walmsley
+ * Tony Lindgren
+ * Paul Walmsley
+ * Richard Woodruff
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -64,14 +66,62 @@
  * SMS register access
  */
 
-
-#define OMAP242X_SMS_REGADDR(reg)       IO_ADDRESS(OMAP2420_SMS_BASE + reg)
-#define OMAP243X_SMS_REGADDR(reg)       IO_ADDRESS(OMAP243X_SMS_BASE + reg)
-#define OMAP343X_SMS_REGADDR(reg)       IO_ADDRESS(OMAP343X_SMS_BASE + reg)
+#define OMAP242X_SMS_REGADDR(reg)                                       \
+                        (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg)
+#define OMAP243X_SMS_REGADDR(reg)                                       \
+                        (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg)
+#define OMAP343X_SMS_REGADDR(reg)                                       \
+                        (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg)
 
 /* SMS register offsets - read/write with sms_{read,write}_reg() */
 
 #define SMS_SYSCONFIG           0x010
 /* REVISIT: fill in other SMS registers here */
 
+
+#ifndef __ASSEMBLER__
+
+/**
+ * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
+ * @rate: SDRC clock rate (in Hz)
+ * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
+ * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
+ * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
+ * @mr: Value to program to SDRC_MR for this rate
+ *
+ * This structure holds a pre-computed set of register values for the
+ * SDRC for a given SDRC clock rate and SDRAM chip.  These are
+ * intended to be pre-computed and specified in an array in the board-*.c
+ * files.  The structure is keyed off the 'rate' field.
+ */
+struct omap_sdrc_params {
+        unsigned long rate;
+        u32 actim_ctrla;
+        u32 actim_ctrlb;
+        u32 rfr_ctrl;
+        u32 mr;
+};
+
+void __init omap2_sdrc_init(struct omap_sdrc_params *sp);
+struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r);
+
+#ifdef CONFIG_ARCH_OMAP2
+
+struct memory_timings {
+        u32 m_type;             /* ddr = 1, sdr = 0 */
+        u32 dll_mode;           /* use lock mode = 1, unlock mode = 0 */
+        u32 slow_dll_ctrl;      /* unlock mode, dll value for slow speed */
+        u32 fast_dll_ctrl;      /* unlock mode, dll value for fast speed */
+        u32 base_cs;            /* base chip select to use for calculations */
+};
+
+extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
+
+u32 omap2xxx_sdrc_dll_is_unlocked(void);
+u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
+
+#endif  /* CONFIG_ARCH_OMAP2 */
+
+#endif  /* __ASSEMBLER__ */
+
 #endif
diff --git a/arch/arm/plat-omap/include/mach/system.h b/arch/arm/plat-omap/include/mach/system.h
index 06923f261545..1060e345423b 100644
--- a/arch/arm/plat-omap/include/mach/system.h
+++ b/arch/arm/plat-omap/include/mach/system.h
@@ -9,12 +9,14 @@
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 
+#include <mach/prcm.h>
+
 #ifndef CONFIG_MACH_VOICEBLUE
 #define voiceblue_reset()               do {} while (0)
+#else
+extern void voiceblue_reset(void);
 #endif
 
-extern void omap_prcm_arch_reset(char mode);
-
 static inline void arch_idle(void)
 {
         cpu_do_idle();
@@ -38,7 +40,7 @@ static inline void omap1_arch_reset(char mode)
                 omap_writew(1, ARM_RSTCT1);
 }
 
-static inline void arch_reset(char mode)
+static inline void arch_reset(char mode, const char *cmd)
 {
         if (!cpu_class_is_omap2())
                 omap1_arch_reset(mode);
diff --git a/arch/arm/plat-omap/include/mach/usb.h b/arch/arm/plat-omap/include/mach/usb.h
index a56a610950c2..69f0ceed500b 100644
--- a/arch/arm/plat-omap/include/mach/usb.h
+++ b/arch/arm/plat-omap/include/mach/usb.h
@@ -27,8 +27,18 @@
 #define UDC_BASE                        OMAP2_UDC_BASE
 #define OMAP_OHCI_BASE                  OMAP2_OHCI_BASE
 
+#ifdef CONFIG_USB_MUSB_SOC
+extern void usb_musb_init(void);
+#else
+static inline void usb_musb_init(void)
+{
+}
+#endif
+
 #endif
 
+void omap_usb_init(struct omap_usb_config *pdata);
+
 /*-------------------------------------------------------------------------*/
 
 /*
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index b52ce053e6f2..0abfbaa59871 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -1,10 +1,9 @@
 /*
  * OMAP mailbox driver
  *
- * Copyright (C) 2006 Nokia Corporation. All rights reserved.
+ * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
  *
- * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
- *              Restructured by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+ * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -22,21 +21,98 @@
  *
  */
 
-#include <linux/init.h>
 #include <linux/module.h>
-#include <linux/sched.h>
 #include <linux/interrupt.h>
 #include <linux/device.h>
-#include <linux/blkdev.h>
-#include <linux/err.h>
 #include <linux/delay.h>
-#include <linux/io.h>
+
 #include <mach/mailbox.h>
-#include "mailbox.h"
+
+static int enable_seq_bit;
+module_param(enable_seq_bit, bool, 0);
+MODULE_PARM_DESC(enable_seq_bit, "Enable sequence bit checking.");
 
 static struct omap_mbox *mboxes;
 static DEFINE_RWLOCK(mboxes_lock);
 
+/*
+ * Mailbox sequence bit API
+ */
+
+/* seq_rcv should be initialized with any value other than
+ * 0 and 1 << 31, to allow either value for the first
+ * message.  */
+static inline void mbox_seq_init(struct omap_mbox *mbox)
+{
+        if (!enable_seq_bit)
+                return;
+
+        /* any value other than 0 and 1 << 31 */
+        mbox->seq_rcv = 0xffffffff;
+}
+
+static inline void mbox_seq_toggle(struct omap_mbox *mbox, mbox_msg_t * msg)
+{
+        if (!enable_seq_bit)
+                return;
+
+        /* add seq_snd to msg */
+        *msg = (*msg & 0x7fffffff) | mbox->seq_snd;
+        /* flip seq_snd */
+        mbox->seq_snd ^= 1 << 31;
+}
+
+static inline int mbox_seq_test(struct omap_mbox *mbox, mbox_msg_t msg)
+{
+        mbox_msg_t seq;
+
+        if (!enable_seq_bit)
+                return 0;
+
+        seq = msg & (1 << 31);
+        if (seq == mbox->seq_rcv)
+                return -1;
+        mbox->seq_rcv = seq;
+        return 0;
+}
+
+/* Mailbox FIFO handle functions */
+static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
+{
+        return mbox->ops->fifo_read(mbox);
+}
+static inline void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
+{
+        mbox->ops->fifo_write(mbox, msg);
+}
+static inline int mbox_fifo_empty(struct omap_mbox *mbox)
+{
+        return mbox->ops->fifo_empty(mbox);
+}
+static inline int mbox_fifo_full(struct omap_mbox *mbox)
+{
+        return mbox->ops->fifo_full(mbox);
+}
+
+/* Mailbox IRQ handle functions */
+static inline void enable_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
+{
+        mbox->ops->enable_irq(mbox, irq);
+}
+static inline void disable_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
+{
+        mbox->ops->disable_irq(mbox, irq);
+}
+static inline void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
+{
+        if (mbox->ops->ack_irq)
+                mbox->ops->ack_irq(mbox, irq);
+}
+static inline int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
+{
+        return mbox->ops->is_irq(mbox, irq);
+}
+
 /* Mailbox Sequence Bit function */
 void omap_mbox_init_seq(struct omap_mbox *mbox)
 {
@@ -136,7 +212,7 @@ static void mbox_rx_work(struct work_struct *work)
         unsigned long flags;
 
         if (mbox->rxq->callback == NULL) {
-                sysfs_notify(&mbox->dev.kobj, NULL, "mbox");
+                sysfs_notify(&mbox->dev->kobj, NULL, "mbox");
                 return;
         }
 
@@ -204,7 +280,7 @@ static void __mbox_rx_interrupt(struct omap_mbox *mbox)
         /* no more messages in the fifo. clear IRQ source. */
         ack_mbox_irq(mbox, IRQ_RX);
         enable_mbox_irq(mbox, IRQ_RX);
-        nomem:
+nomem:
         schedule_work(&mbox->rxq->work);
 }
 
@@ -286,7 +362,7 @@ static ssize_t mbox_show(struct class *class, char *buf)
 static CLASS_ATTR(mbox, S_IRUGO, mbox_show, NULL);
 
 static struct class omap_mbox_class = {
-        .name = "omap_mbox",
+        .name = "omap-mailbox",
 };
 
 static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
@@ -333,21 +409,6 @@ static int omap_mbox_init(struct omap_mbox *mbox)
                         return ret;
         }
 
-        mbox->dev.class = &omap_mbox_class;
-        dev_set_name(&mbox->dev, "%s", mbox->name);
-        dev_set_drvdata(&mbox->dev, mbox);
-
-        ret = device_register(&mbox->dev);
-        if (unlikely(ret))
-                goto fail_device_reg;
-
-        ret = device_create_file(&mbox->dev, &dev_attr_mbox);
-        if (unlikely(ret)) {
-                printk(KERN_ERR
-                        "device_create_file failed: %d\n", ret);
-                goto fail_create_mbox;
-        }
-
         ret = request_irq(mbox->irq, mbox_interrupt, IRQF_DISABLED,
                                 mbox->name, mbox);
         if (unlikely(ret)) {
@@ -377,10 +438,6 @@ static int omap_mbox_init(struct omap_mbox *mbox)
  fail_alloc_txq:
         free_irq(mbox->irq, mbox);
  fail_request_irq:
-        device_remove_file(&mbox->dev, &dev_attr_mbox);
- fail_create_mbox:
-        device_unregister(&mbox->dev);
- fail_device_reg:
         if (unlikely(mbox->ops->shutdown))
                 mbox->ops->shutdown(mbox);
 
@@ -393,8 +450,6 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
         mbox_queue_free(mbox->rxq);
 
         free_irq(mbox->irq, mbox);
-        device_remove_file(&mbox->dev, &dev_attr_mbox);
-        class_unregister(&omap_mbox_class);
 
         if (unlikely(mbox->ops->shutdown))
                 mbox->ops->shutdown(mbox);
@@ -440,7 +495,7 @@ void omap_mbox_put(struct omap_mbox *mbox)
 }
 EXPORT_SYMBOL(omap_mbox_put);
 
-int omap_mbox_register(struct omap_mbox *mbox)
+int omap_mbox_register(struct device *parent, struct omap_mbox *mbox)
 {
         int ret = 0;
         struct omap_mbox **tmp;
@@ -450,14 +505,31 @@ int omap_mbox_register(struct omap_mbox *mbox)
         if (mbox->next)
                 return -EBUSY;
 
+        mbox->dev = device_create(&omap_mbox_class,
+                                  parent, 0, mbox, "%s", mbox->name);
+        if (IS_ERR(mbox->dev))
+                return PTR_ERR(mbox->dev);
+
+        ret = device_create_file(mbox->dev, &dev_attr_mbox);
+        if (ret)
+                goto err_sysfs;
+
         write_lock(&mboxes_lock);
         tmp = find_mboxes(mbox->name);
-        if (*tmp)
+        if (*tmp) {
                 ret = -EBUSY;
-        else
-                *tmp = mbox;
+                write_unlock(&mboxes_lock);
+                goto err_find;
+        }
+        *tmp = mbox;
         write_unlock(&mboxes_lock);
 
+        return 0;
+
+err_find:
+        device_remove_file(mbox->dev, &dev_attr_mbox);
+err_sysfs:
+        device_unregister(mbox->dev);
         return ret;
 }
 EXPORT_SYMBOL(omap_mbox_register);
@@ -473,6 +545,8 @@ int omap_mbox_unregister(struct omap_mbox *mbox)
                         *tmp = mbox->next;
                         mbox->next = NULL;
                         write_unlock(&mboxes_lock);
+                        device_remove_file(mbox->dev, &dev_attr_mbox);
+                        device_unregister(mbox->dev);
                         return 0;
                 }
                 tmp = &(*tmp)->next;
@@ -501,4 +575,6 @@ static void __exit omap_mbox_class_exit(void)
 subsys_initcall(omap_mbox_class_init);
 module_exit(omap_mbox_class_exit);
 
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging");
+MODULE_AUTHOR("Toshihiro Kobayashi and Hiroshi DOYU");
diff --git a/arch/arm/plat-omap/mailbox.h b/arch/arm/plat-omap/mailbox.h
deleted file mode 100644
index 67c6740b8ad5..000000000000
--- a/arch/arm/plat-omap/mailbox.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Mailbox internal functions
- *
- * Copyright (C) 2006 Nokia Corporation
- * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#ifndef __ARCH_ARM_PLAT_MAILBOX_H
-#define __ARCH_ARM_PLAT_MAILBOX_H
-
-/*
- * Mailbox sequence bit API
- */
-#if defined(CONFIG_ARCH_OMAP1)
-#  define MBOX_USE_SEQ_BIT
-#elif defined(CONFIG_ARCH_OMAP2)
-#  define MBOX_USE_SEQ_BIT
-#endif
-
-#ifdef MBOX_USE_SEQ_BIT
-/* seq_rcv should be initialized with any value other than
- * 0 and 1 << 31, to allow either value for the first
- * message.  */
-static inline void mbox_seq_init(struct omap_mbox *mbox)
-{
-        /* any value other than 0 and 1 << 31 */
-        mbox->seq_rcv = 0xffffffff;
-}
-
-static inline void mbox_seq_toggle(struct omap_mbox *mbox, mbox_msg_t * msg)
-{
-        /* add seq_snd to msg */
-        *msg = (*msg & 0x7fffffff) | mbox->seq_snd;
-        /* flip seq_snd */
-        mbox->seq_snd ^= 1 << 31;
-}
-
-static inline int mbox_seq_test(struct omap_mbox *mbox, mbox_msg_t msg)
-{
-        mbox_msg_t seq = msg & (1 << 31);
-        if (seq == mbox->seq_rcv)
-                return -1;
-        mbox->seq_rcv = seq;
-        return 0;
-}
-#else
-static inline void mbox_seq_init(struct omap_mbox *mbox)
-{
-}
-static inline void mbox_seq_toggle(struct omap_mbox *mbox, mbox_msg_t * msg)
-{
-}
-static inline int mbox_seq_test(struct omap_mbox *mbox, mbox_msg_t msg)
-{
-        return 0;
-}
-#endif
-
-/* Mailbox FIFO handle functions */
-static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
-{
-        return mbox->ops->fifo_read(mbox);
-}
-static inline void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
-{
-        mbox->ops->fifo_write(mbox, msg);
-}
-static inline int mbox_fifo_empty(struct omap_mbox *mbox)
-{
-        return mbox->ops->fifo_empty(mbox);
-}
-static inline int mbox_fifo_full(struct omap_mbox *mbox)
-{
-        return mbox->ops->fifo_full(mbox);
-}
-
-/* Mailbox IRQ handle functions */
-static inline void enable_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
-{
-        mbox->ops->enable_irq(mbox, irq);
-}
-static inline void disable_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
-{
-        mbox->ops->disable_irq(mbox, irq);
-}
-static inline void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
-{
-        if (mbox->ops->ack_irq)
-                mbox->ops->ack_irq(mbox, irq);
-}
-static inline int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
-{
-        return mbox->ops->is_irq(mbox, irq);
-}
-
-#endif                          /* __ARCH_ARM_PLAT_MAILBOX_H */
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index e5842e30e534..28b0a824b8cf 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -214,7 +214,6 @@ EXPORT_SYMBOL(omap_mcbsp_set_io_type);
 int omap_mcbsp_request(unsigned int id)
 {
         struct omap_mcbsp *mcbsp;
-        int i;
         int err;
 
         if (!omap_mcbsp_check_valid_id(id)) {
@@ -223,23 +222,23 @@ int omap_mcbsp_request(unsigned int id)
         }
         mcbsp = id_to_mcbsp_ptr(id);
 
-        if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
-                mcbsp->pdata->ops->request(id);
-
-        for (i = 0; i < mcbsp->num_clks; i++)
-                clk_enable(mcbsp->clks[i]);
-
         spin_lock(&mcbsp->lock);
         if (!mcbsp->free) {
                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
                         mcbsp->id);
                 spin_unlock(&mcbsp->lock);
-                return -1;
+                return -EBUSY;
         }
 
         mcbsp->free = 0;
         spin_unlock(&mcbsp->lock);
 
+        if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
+                mcbsp->pdata->ops->request(id);
+
+        clk_enable(mcbsp->iclk);
+        clk_enable(mcbsp->fclk);
+
         /*
          * Make sure that transmitter, receiver and sample-rate generator are
          * not running before activating IRQs.
@@ -278,7 +277,6 @@ EXPORT_SYMBOL(omap_mcbsp_request);
 void omap_mcbsp_free(unsigned int id)
 {
         struct omap_mcbsp *mcbsp;
-        int i;
 
         if (!omap_mcbsp_check_valid_id(id)) {
                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
@@ -289,8 +287,14 @@ void omap_mcbsp_free(unsigned int id)
         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
                 mcbsp->pdata->ops->free(id);
 
-        for (i = mcbsp->num_clks - 1; i >= 0; i--)
-                clk_disable(mcbsp->clks[i]);
+        clk_disable(mcbsp->fclk);
+        clk_disable(mcbsp->iclk);
+
+        if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
+                /* Free IRQs */
+                free_irq(mcbsp->rx_irq, (void *)mcbsp);
+                free_irq(mcbsp->tx_irq, (void *)mcbsp);
+        }
 
         spin_lock(&mcbsp->lock);
         if (mcbsp->free) {
@@ -302,12 +306,6 @@ void omap_mcbsp_free(unsigned int id)
 
         mcbsp->free = 1;
         spin_unlock(&mcbsp->lock);
-
-        if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
-                /* Free IRQs */
-                free_irq(mcbsp->rx_irq, (void *)mcbsp);
-                free_irq(mcbsp->tx_irq, (void *)mcbsp);
-        }
 }
 EXPORT_SYMBOL(omap_mcbsp_free);
 
@@ -876,7 +874,6 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
         struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
         struct omap_mcbsp *mcbsp;
         int id = pdev->id - 1;
-        int i;
         int ret = 0;
 
         if (!pdata) {
@@ -899,7 +896,6 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
                 ret = -ENOMEM;
                 goto exit;
         }
-        mcbsp_ptr[id] = mcbsp;
 
         spin_lock_init(&mcbsp->lock);
         mcbsp->id = id + 1;
@@ -921,39 +917,32 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
         mcbsp->dma_rx_sync = pdata->dma_rx_sync;
         mcbsp->dma_tx_sync = pdata->dma_tx_sync;
 
-        if (pdata->num_clks) {
-                mcbsp->num_clks = pdata->num_clks;
-                mcbsp->clks = kzalloc(mcbsp->num_clks * sizeof(struct clk *),
-                                        GFP_KERNEL);
-                if (!mcbsp->clks) {
-                        ret = -ENOMEM;
-                        goto exit;
-                }
-                for (i = 0; i < mcbsp->num_clks; i++) {
-                        mcbsp->clks[i] = clk_get(&pdev->dev, pdata->clk_names[i]);
-                        if (IS_ERR(mcbsp->clks[i])) {
-                                dev_err(&pdev->dev,
-                                        "Invalid %s configuration for McBSP%d.\n",
-                                        pdata->clk_names[i], mcbsp->id);
-                                ret = PTR_ERR(mcbsp->clks[i]);
-                                goto err_clk;
-                        }
-                }
+        mcbsp->iclk = clk_get(&pdev->dev, "ick");
+        if (IS_ERR(mcbsp->iclk)) {
+                ret = PTR_ERR(mcbsp->iclk);
+                dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
+                goto err_iclk;
+        }
 
+        mcbsp->fclk = clk_get(&pdev->dev, "fck");
+        if (IS_ERR(mcbsp->fclk)) {
+                ret = PTR_ERR(mcbsp->fclk);
+                dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
+                goto err_fclk;
         }
 
         mcbsp->pdata = pdata;
         mcbsp->dev = &pdev->dev;
+        mcbsp_ptr[id] = mcbsp;
         platform_set_drvdata(pdev, mcbsp);
         return 0;
 
-err_clk:
-        while (i--)
-                clk_put(mcbsp->clks[i]);
-        kfree(mcbsp->clks);
+err_fclk:
+        clk_put(mcbsp->iclk);
+err_iclk:
         iounmap(mcbsp->io_base);
 err_ioremap:
-        mcbsp->free = 0;
+        kfree(mcbsp);
 exit:
         return ret;
 }
@@ -961,7 +950,6 @@ exit:
 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
 {
         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
-        int i;
 
         platform_set_drvdata(pdev, NULL);
         if (mcbsp) {
@@ -970,18 +958,15 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
                                 mcbsp->pdata->ops->free)
                         mcbsp->pdata->ops->free(mcbsp->id);
 
-                for (i = mcbsp->num_clks - 1; i >= 0; i--) {
-                        clk_disable(mcbsp->clks[i]);
-                        clk_put(mcbsp->clks[i]);
-                }
+                clk_disable(mcbsp->fclk);
+                clk_disable(mcbsp->iclk);
+                clk_put(mcbsp->fclk);
+                clk_put(mcbsp->iclk);
 
                 iounmap(mcbsp->io_base);
 
-                if (mcbsp->num_clks) {
-                        kfree(mcbsp->clks);
-                        mcbsp->clks = NULL;
-                        mcbsp->num_clks = 0;
-                }
+                mcbsp->fclk = NULL;
+                mcbsp->iclk = NULL;
                 mcbsp->free = 0;
                 mcbsp->dev = NULL;
         }
@@ -1002,4 +987,3 @@ int __init omap_mcbsp_init(void)
         /* Register the McBSP driver */
         return platform_driver_register(&omap_mcbsp_driver);
 }
-
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index be7bcaf2b832..fa5297d643d3 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -148,7 +148,7 @@ void __init omap_detect_sram(void)
                 omap_sram_base = OMAP1_SRAM_VA;
                 omap_sram_start = OMAP1_SRAM_PA;
 
-                if (cpu_is_omap730())
+                if (cpu_is_omap7xx())
                         omap_sram_size = 0x32000;       /* 200K */
                 else if (cpu_is_omap15xx())
                         omap_sram_size = 0x30000;       /* 192K */
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index e278de6862ae..509f2ed99e21 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -729,30 +729,13 @@ static inline void omap_1510_usb_init(struct omap_usb_config *config) {}
 
 /*-------------------------------------------------------------------------*/
 
-static struct omap_usb_config platform_data;
-
-static int __init
-omap_usb_init(void)
+void __init omap_usb_init(struct omap_usb_config *pdata)
 {
-        const struct omap_usb_config *config;
-
-        config = omap_get_config(OMAP_TAG_USB, struct omap_usb_config);
-        if (config == NULL) {
-                printk(KERN_ERR "USB: No board-specific "
-                                "platform config found\n");
-                return -ENODEV;
-        }
-        platform_data = *config;
-
         if (cpu_is_omap730() || cpu_is_omap16xx() || cpu_is_omap24xx())
-                omap_otg_init(&platform_data);
+                omap_otg_init(pdata);
         else if (cpu_is_omap15xx())
-                omap_1510_usb_init(&platform_data);
-        else {
+                omap_1510_usb_init(pdata);
+        else
                 printk(KERN_ERR "USB: No init for your chip yet\n");
-                return -ENODEV;
-        }
-        return 0;
 }
 
-subsys_initcall(omap_usb_init);
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index 0d12c2164766..32eb9e33bebb 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -19,7 +19,8 @@
 
 static DEFINE_SPINLOCK(gpio_lock);
 static const char *gpio_label[GPIO_MAX];  /* non null for allocated GPIOs */
-static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)];
+static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)];
+static unsigned long gpio_valid_output[BITS_TO_LONGS(GPIO_MAX)];
 
 static inline void __set_direction(unsigned pin, int input)
 {
@@ -53,7 +54,7 @@ int gpio_direction_input(unsigned pin)
 {
         unsigned long flags;
 
-        if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
+        if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid_input)) {
                 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
                 return -EINVAL;
         }
@@ -83,7 +84,7 @@ int gpio_direction_output(unsigned pin, int value)
         unsigned long flags;
         u32 u;
 
-        if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
+        if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid_output)) {
                 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
                 return -EINVAL;
         }
@@ -161,7 +162,9 @@ int gpio_request(unsigned pin, const char *label)
         unsigned long flags;
         int ret;
 
-        if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
+        if (pin >= GPIO_MAX ||
+            !(test_bit(pin, gpio_valid_input) ||
+              test_bit(pin, gpio_valid_output))) {
                 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
                 return -EINVAL;
         }
@@ -183,7 +186,9 @@ EXPORT_SYMBOL(gpio_request);
 
 void gpio_free(unsigned pin)
 {
-        if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
+        if (pin >= GPIO_MAX ||
+            !(test_bit(pin, gpio_valid_input) ||
+              test_bit(pin, gpio_valid_output))) {
                 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
                 return;
         }
@@ -208,12 +213,18 @@ void __init orion_gpio_set_unused(unsigned pin)
         __set_direction(pin, 0);
 }
 
-void __init orion_gpio_set_valid(unsigned pin, int valid)
+void __init orion_gpio_set_valid(unsigned pin, int mode)
 {
-        if (valid)
-                __set_bit(pin, gpio_valid);
+        if (mode == 1)
+                mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
+        if (mode & GPIO_INPUT_OK)
+                __set_bit(pin, gpio_valid_input);
         else
-                __clear_bit(pin, gpio_valid);
+                __clear_bit(pin, gpio_valid_input);
+        if (mode & GPIO_OUTPUT_OK)
+                __set_bit(pin, gpio_valid_output);
+        else
+                __clear_bit(pin, gpio_valid_output);
 }
 
 void orion_gpio_set_blink(unsigned pin, int blink)
diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h
index ec743e82c876..33f6c6aec185 100644
--- a/arch/arm/plat-orion/include/plat/gpio.h
+++ b/arch/arm/plat-orion/include/plat/gpio.h
@@ -25,9 +25,13 @@ void gpio_set_value(unsigned pin, int value);
  * Orion-specific GPIO API extensions.
  */
 void orion_gpio_set_unused(unsigned pin);
-void orion_gpio_set_valid(unsigned pin, int valid);
 void orion_gpio_set_blink(unsigned pin, int blink);
 
+#define GPIO_BIDI_OK            (1 << 0)
+#define GPIO_INPUT_OK           (1 << 1)
+#define GPIO_OUTPUT_OK          (1 << 2)
+void orion_gpio_set_valid(unsigned pin, int mode);
+
 /*
  * GPIO interrupt handling.
  */
diff --git a/arch/arm/plat-orion/include/plat/mvsdio.h b/arch/arm/plat-orion/include/plat/mvsdio.h
new file mode 100644
index 000000000000..14ca88676002
--- /dev/null
+++ b/arch/arm/plat-orion/include/plat/mvsdio.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/plat-orion/include/plat/mvsdio.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_MVSDIO_H
+#define __MACH_MVSDIO_H
+
+#include <linux/mbus.h>
+
+struct mvsdio_platform_data {
+        struct mbus_dram_target_info *dram;
+        unsigned int clock;
+        int gpio_card_detect;
+        int gpio_write_protect;
+};
+
+#endif
diff --git a/arch/arm/plat-pxa/Kconfig b/arch/arm/plat-pxa/Kconfig
new file mode 100644
index 000000000000..b158e98038ed
--- /dev/null
+++ b/arch/arm/plat-pxa/Kconfig
@@ -0,0 +1,3 @@
+if PLAT_PXA
+
+endif
diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile
new file mode 100644
index 000000000000..8f2c4c7fbd48
--- /dev/null
+++ b/arch/arm/plat-pxa/Makefile
@@ -0,0 +1,9 @@
+#
+# Makefile for code common across different PXA processor families
+#
+
+obj-y   := dma.o
+
+obj-$(CONFIG_GENERIC_GPIO)      += gpio.o
+obj-$(CONFIG_PXA3xx)            += mfp.o
+obj-$(CONFIG_ARCH_MMP)          += mfp.o
diff --git a/arch/arm/mach-pxa/dma.c b/arch/arm/plat-pxa/dma.c
index 7de17fc5d54b..70aeee407f7d 100644
--- a/arch/arm/mach-pxa/dma.c
+++ b/arch/arm/plat-pxa/dma.c
@@ -1,5 +1,5 @@
 /*
- *  linux/arch/arm/mach-pxa/dma.c
+ *  linux/arch/arm/plat-pxa/dma.c
  *
  *  PXA DMA registration and IRQ dispatching
  *
@@ -23,8 +23,6 @@
 #include <mach/hardware.h>
 #include <mach/dma.h>
 
-#include <mach/pxa-regs.h>
-
 struct dma_channel {
         char *name;
         pxa_dma_prio prio;
@@ -36,8 +34,8 @@ static struct dma_channel *dma_channels;
 static int num_dma_channels;
 
 int pxa_request_dma (char *name, pxa_dma_prio prio,
-                         void (*irq_handler)(int, void *),
-                         void *data)
+                        void (*irq_handler)(int, void *),
+                        void *data)
 {
         unsigned long flags;
         int i, found = 0;
@@ -113,7 +111,7 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-int __init pxa_init_dma(int num_ch)
+int __init pxa_init_dma(int irq, int num_ch)
 {
         int i, ret;
 
@@ -131,7 +129,7 @@ int __init pxa_init_dma(int num_ch)
                 dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW);
         }
 
-        ret = request_irq(IRQ_DMA, dma_irq_handler, IRQF_DISABLED, "DMA", NULL);
+        ret = request_irq(irq, dma_irq_handler, IRQF_DISABLED, "DMA", NULL);
         if (ret) {
                 printk (KERN_CRIT "Wow!  Can't register IRQ for DMA\n");
                 kfree(dma_channels);
diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c
new file mode 100644
index 000000000000..af819bf21b63
--- /dev/null
+++ b/arch/arm/plat-pxa/gpio.c
@@ -0,0 +1,337 @@
+/*
+ *  linux/arch/arm/plat-pxa/gpio.c
+ *
+ *  Generic PXA GPIO handling
+ *
+ *  Author:     Nicolas Pitre
+ *  Created:    Jun 15, 2001
+ *  Copyright:  MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+#include <linux/bootmem.h>
+
+#include <mach/gpio.h>
+
+int pxa_last_gpio;
+
+struct pxa_gpio_chip {
+        struct gpio_chip chip;
+        void __iomem    *regbase;
+        char label[10];
+
+        unsigned long   irq_mask;
+        unsigned long   irq_edge_rise;
+        unsigned long   irq_edge_fall;
+
+#ifdef CONFIG_PM
+        unsigned long   saved_gplr;
+        unsigned long   saved_gpdr;
+        unsigned long   saved_grer;
+        unsigned long   saved_gfer;
+#endif
+};
+
+static DEFINE_SPINLOCK(gpio_lock);
+static struct pxa_gpio_chip *pxa_gpio_chips;
+
+#define for_each_gpio_chip(i, c)                        \
+        for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
+
+static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
+{
+        return container_of(c, struct pxa_gpio_chip, chip)->regbase;
+}
+
+static inline struct pxa_gpio_chip *gpio_to_chip(unsigned gpio)
+{
+        return &pxa_gpio_chips[gpio_to_bank(gpio)];
+}
+
+static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        void __iomem *base = gpio_chip_base(chip);
+        uint32_t value, mask = 1 << offset;
+        unsigned long flags;
+
+        spin_lock_irqsave(&gpio_lock, flags);
+
+        value = __raw_readl(base + GPDR_OFFSET);
+        if (__gpio_is_inverted(chip->base + offset))
+                value |= mask;
+        else
+                value &= ~mask;
+        __raw_writel(value, base + GPDR_OFFSET);
+
+        spin_unlock_irqrestore(&gpio_lock, flags);
+        return 0;
+}
+
+static int pxa_gpio_direction_output(struct gpio_chip *chip,
+                                     unsigned offset, int value)
+{
+        void __iomem *base = gpio_chip_base(chip);
+        uint32_t tmp, mask = 1 << offset;
+        unsigned long flags;
+
+        __raw_writel(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
+
+        spin_lock_irqsave(&gpio_lock, flags);
+
+        tmp = __raw_readl(base + GPDR_OFFSET);
+        if (__gpio_is_inverted(chip->base + offset))
+                tmp &= ~mask;
+        else
+                tmp |= mask;
+        __raw_writel(tmp, base + GPDR_OFFSET);
+
+        spin_unlock_irqrestore(&gpio_lock, flags);
+        return 0;
+}
+
+static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        return __raw_readl(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
+}
+
+static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        __raw_writel(1 << offset, gpio_chip_base(chip) +
+                                (value ? GPSR_OFFSET : GPCR_OFFSET));
+}
+
+static int __init pxa_init_gpio_chip(int gpio_end)
+{
+        int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
+        struct pxa_gpio_chip *chips;
+
+        /* this is early, we have to use bootmem allocator, and we really
+         * want this to be allocated dynamically for different 'gpio_end'
+         */
+        chips = alloc_bootmem_low(nbanks * sizeof(struct pxa_gpio_chip));
+        if (chips == NULL) {
+                pr_err("%s: failed to allocate GPIO chips\n", __func__);
+                return -ENOMEM;
+        }
+
+        for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
+                struct gpio_chip *c = &chips[i].chip;
+
+                sprintf(chips[i].label, "gpio-%d", i);
+                chips[i].regbase = (void __iomem *)GPIO_BANK(i);
+
+                c->base  = gpio;
+                c->label = chips[i].label;
+
+                c->direction_input  = pxa_gpio_direction_input;
+                c->direction_output = pxa_gpio_direction_output;
+                c->get = pxa_gpio_get;
+                c->set = pxa_gpio_set;
+
+                /* number of GPIOs on last bank may be less than 32 */
+                c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
+                gpiochip_add(c);
+        }
+        pxa_gpio_chips = chips;
+        return 0;
+}
+
+static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
+{
+        struct pxa_gpio_chip *c;
+        int gpio = irq_to_gpio(irq);
+        unsigned long gpdr, mask = GPIO_bit(gpio);
+
+        c = gpio_to_chip(gpio);
+
+        if (type == IRQ_TYPE_PROBE) {
+                /* Don't mess with enabled GPIOs using preconfigured edges or
+                 * GPIOs set to alternate function or to output during probe
+                 */
+                if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
+                        return 0;
+
+                if (__gpio_is_occupied(gpio))
+                        return 0;
+
+                type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
+        }
+
+        gpdr = __raw_readl(c->regbase + GPDR_OFFSET);
+
+        if (__gpio_is_inverted(gpio))
+                __raw_writel(gpdr | mask,  c->regbase + GPDR_OFFSET);
+        else
+                __raw_writel(gpdr & ~mask, c->regbase + GPDR_OFFSET);
+
+        if (type & IRQ_TYPE_EDGE_RISING)
+                c->irq_edge_rise |= mask;
+        else
+                c->irq_edge_rise &= ~mask;
+
+        if (type & IRQ_TYPE_EDGE_FALLING)
+                c->irq_edge_fall |= mask;
+        else
+                c->irq_edge_fall &= ~mask;
+
+        __raw_writel(c->irq_edge_rise & c->irq_mask, c->regbase + GRER_OFFSET);
+        __raw_writel(c->irq_edge_fall & c->irq_mask, c->regbase + GFER_OFFSET);
+
+        pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio,
+                ((type & IRQ_TYPE_EDGE_RISING)  ? " rising"  : ""),
+                ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
+        return 0;
+}
+
+static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
+{
+        struct pxa_gpio_chip *c;
+        int loop, gpio, gpio_base, n;
+        unsigned long gedr;
+
+        do {
+                loop = 0;
+                for_each_gpio_chip(gpio, c) {
+                        gpio_base = c->chip.base;
+
+                        gedr = __raw_readl(c->regbase + GEDR_OFFSET);
+                        gedr = gedr & c->irq_mask;
+                        __raw_writel(gedr, c->regbase + GEDR_OFFSET);
+
+                        n = find_first_bit(&gedr, BITS_PER_LONG);
+                        while (n < BITS_PER_LONG) {
+                                loop = 1;
+
+                                generic_handle_irq(gpio_to_irq(gpio_base + n));
+                                n = find_next_bit(&gedr, BITS_PER_LONG, n + 1);
+                        }
+                }
+        } while (loop);
+}
+
+static void pxa_ack_muxed_gpio(unsigned int irq)
+{
+        int gpio = irq_to_gpio(irq);
+        struct pxa_gpio_chip *c = gpio_to_chip(gpio);
+
+        __raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
+}
+
+static void pxa_mask_muxed_gpio(unsigned int irq)
+{
+        int gpio = irq_to_gpio(irq);
+        struct pxa_gpio_chip *c = gpio_to_chip(gpio);
+        uint32_t grer, gfer;
+
+        c->irq_mask &= ~GPIO_bit(gpio);
+
+        grer = __raw_readl(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
+        gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
+        __raw_writel(grer, c->regbase + GRER_OFFSET);
+        __raw_writel(gfer, c->regbase + GFER_OFFSET);
+}
+
+static void pxa_unmask_muxed_gpio(unsigned int irq)
+{
+        int gpio = irq_to_gpio(irq);
+        struct pxa_gpio_chip *c = gpio_to_chip(gpio);
+
+        c->irq_mask |= GPIO_bit(gpio);
+        __raw_writel(c->irq_edge_rise & c->irq_mask, c->regbase + GRER_OFFSET);
+        __raw_writel(c->irq_edge_fall & c->irq_mask, c->regbase + GFER_OFFSET);
+}
+
+static struct irq_chip pxa_muxed_gpio_chip = {
+        .name           = "GPIO",
+        .ack            = pxa_ack_muxed_gpio,
+        .mask           = pxa_mask_muxed_gpio,
+        .unmask         = pxa_unmask_muxed_gpio,
+        .set_type       = pxa_gpio_irq_type,
+};
+
+void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn)
+{
+        struct pxa_gpio_chip *c;
+        int gpio, irq;
+
+        pxa_last_gpio = end;
+
+        /* Initialize GPIO chips */
+        pxa_init_gpio_chip(end);
+
+        /* clear all GPIO edge detects */
+        for_each_gpio_chip(gpio, c) {
+                __raw_writel(0, c->regbase + GFER_OFFSET);
+                __raw_writel(0, c->regbase + GRER_OFFSET);
+                __raw_writel(~0,c->regbase + GEDR_OFFSET);
+        }
+
+        for (irq  = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) {
+                set_irq_chip(irq, &pxa_muxed_gpio_chip);
+                set_irq_handler(irq, handle_edge_irq);
+                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+        }
+
+        /* Install handler for GPIO>=2 edge detect interrupts */
+        set_irq_chained_handler(mux_irq, pxa_gpio_demux_handler);
+        pxa_muxed_gpio_chip.set_wake = fn;
+}
+
+#ifdef CONFIG_PM
+static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state)
+{
+        struct pxa_gpio_chip *c;
+        int gpio;
+
+        for_each_gpio_chip(gpio, c) {
+                c->saved_gplr = __raw_readl(c->regbase + GPLR_OFFSET);
+                c->saved_gpdr = __raw_readl(c->regbase + GPDR_OFFSET);
+                c->saved_grer = __raw_readl(c->regbase + GRER_OFFSET);
+                c->saved_gfer = __raw_readl(c->regbase + GFER_OFFSET);
+
+                /* Clear GPIO transition detect bits */
+                __raw_writel(0xffffffff, c->regbase + GEDR_OFFSET);
+        }
+        return 0;
+}
+
+static int pxa_gpio_resume(struct sys_device *dev)
+{
+        struct pxa_gpio_chip *c;
+        int gpio;
+
+        for_each_gpio_chip(gpio, c) {
+                /* restore level with set/clear */
+                __raw_writel( c->saved_gplr, c->regbase + GPSR_OFFSET);
+                __raw_writel(~c->saved_gplr, c->regbase + GPCR_OFFSET);
+
+                __raw_writel(c->saved_grer, c->regbase + GRER_OFFSET);
+                __raw_writel(c->saved_gfer, c->regbase + GFER_OFFSET);
+                __raw_writel(c->saved_gpdr, c->regbase + GPDR_OFFSET);
+        }
+        return 0;
+}
+#else
+#define pxa_gpio_suspend        NULL
+#define pxa_gpio_resume         NULL
+#endif
+
+struct sysdev_class pxa_gpio_sysclass = {
+        .name           = "gpio",
+        .suspend        = pxa_gpio_suspend,
+        .resume         = pxa_gpio_resume,
+};
+
+static int __init pxa_gpio_init(void)
+{
+        return sysdev_class_register(&pxa_gpio_sysclass);
+}
+
+core_initcall(pxa_gpio_init);
diff --git a/arch/arm/plat-pxa/include/plat/dma.h b/arch/arm/plat-pxa/include/plat/dma.h
new file mode 100644
index 000000000000..a7b91dc06852
--- /dev/null
+++ b/arch/arm/plat-pxa/include/plat/dma.h
@@ -0,0 +1,85 @@
+#ifndef __PLAT_DMA_H
+#define __PLAT_DMA_H
+
+#define DMAC_REG(x)     (*((volatile u32 *)(DMAC_REGS_VIRT + (x))))
+
+#define DCSR(n)         DMAC_REG((n) << 2)
+#define DALGN           DMAC_REG(0x00a0)  /* DMA Alignment Register */
+#define DINT            DMAC_REG(0x00f0)  /* DMA Interrupt Register */
+#define DDADR(n)        DMAC_REG(0x0200 + ((n) << 4))
+#define DSADR(n)        DMAC_REG(0x0204 + ((n) << 4))
+#define DTADR(n)        DMAC_REG(0x0208 + ((n) << 4))
+#define DCMD(n)         DMAC_REG(0x020c + ((n) << 4))
+#define DRCMR(n)        DMAC_REG((((n) < 64) ? 0x0100 : 0x1100) + \
+                                 (((n) & 0x3f) << 2))
+
+#define DCSR_RUN        (1 << 31)       /* Run Bit (read / write) */
+#define DCSR_NODESC     (1 << 30)       /* No-Descriptor Fetch (read / write) */
+#define DCSR_STOPIRQEN  (1 << 29)       /* Stop Interrupt Enable (read / write) */
+#define DCSR_REQPEND    (1 << 8)        /* Request Pending (read-only) */
+#define DCSR_STOPSTATE  (1 << 3)        /* Stop State (read-only) */
+#define DCSR_ENDINTR    (1 << 2)        /* End Interrupt (read / write) */
+#define DCSR_STARTINTR  (1 << 1)        /* Start Interrupt (read / write) */
+#define DCSR_BUSERR     (1 << 0)        /* Bus Error Interrupt (read / write) */
+
+#define DCSR_EORIRQEN   (1 << 28)       /* End of Receive Interrupt Enable (R/W) */
+#define DCSR_EORJMPEN   (1 << 27)       /* Jump to next descriptor on EOR */
+#define DCSR_EORSTOPEN  (1 << 26)       /* STOP on an EOR */
+#define DCSR_SETCMPST   (1 << 25)       /* Set Descriptor Compare Status */
+#define DCSR_CLRCMPST   (1 << 24)       /* Clear Descriptor Compare Status */
+#define DCSR_CMPST      (1 << 10)       /* The Descriptor Compare Status */
+#define DCSR_EORINTR    (1 << 9)        /* The end of Receive */
+
+#define DRCMR_MAPVLD    (1 << 7)        /* Map Valid (read / write) */
+#define DRCMR_CHLNUM    0x1f            /* mask for Channel Number (read / write) */
+
+#define DDADR_DESCADDR  0xfffffff0      /* Address of next descriptor (mask) */
+#define DDADR_STOP      (1 << 0)        /* Stop (read / write) */
+
+#define DCMD_INCSRCADDR (1 << 31)       /* Source Address Increment Setting. */
+#define DCMD_INCTRGADDR (1 << 30)       /* Target Address Increment Setting. */
+#define DCMD_FLOWSRC    (1 << 29)       /* Flow Control by the source. */
+#define DCMD_FLOWTRG    (1 << 28)       /* Flow Control by the target. */
+#define DCMD_STARTIRQEN (1 << 22)       /* Start Interrupt Enable */
+#define DCMD_ENDIRQEN   (1 << 21)       /* End Interrupt Enable */
+#define DCMD_ENDIAN     (1 << 18)       /* Device Endian-ness. */
+#define DCMD_BURST8     (1 << 16)       /* 8 byte burst */
+#define DCMD_BURST16    (2 << 16)       /* 16 byte burst */
+#define DCMD_BURST32    (3 << 16)       /* 32 byte burst */
+#define DCMD_WIDTH1     (1 << 14)       /* 1 byte width */
+#define DCMD_WIDTH2     (2 << 14)       /* 2 byte width (HalfWord) */
+#define DCMD_WIDTH4     (3 << 14)       /* 4 byte width (Word) */
+#define DCMD_LENGTH     0x01fff         /* length mask (max = 8K - 1) */
+
+/*
+ * Descriptor structure for PXA's DMA engine
+ * Note: this structure must always be aligned to a 16-byte boundary.
+ */
+
+typedef struct pxa_dma_desc {
+        volatile u32 ddadr;     /* Points to the next descriptor + flags */
+        volatile u32 dsadr;     /* DSADR value for the current transfer */
+        volatile u32 dtadr;     /* DTADR value for the current transfer */
+        volatile u32 dcmd;      /* DCMD value for the current transfer */
+} pxa_dma_desc;
+
+typedef enum {
+        DMA_PRIO_HIGH = 0,
+        DMA_PRIO_MEDIUM = 1,
+        DMA_PRIO_LOW = 2
+} pxa_dma_prio;
+
+/*
+ * DMA registration
+ */
+
+int __init pxa_init_dma(int irq, int num_ch);
+
+int pxa_request_dma (char *name,
+                         pxa_dma_prio prio,
+                         void (*irq_handler)(int, void *),
+                         void *data);
+
+void pxa_free_dma (int dma_ch);
+
+#endif /* __PLAT_DMA_H */
diff --git a/arch/arm/plat-pxa/include/plat/gpio.h b/arch/arm/plat-pxa/include/plat/gpio.h
new file mode 100644
index 000000000000..44248cb926a5
--- /dev/null
+++ b/arch/arm/plat-pxa/include/plat/gpio.h
@@ -0,0 +1,62 @@
+#ifndef __PLAT_GPIO_H
+#define __PLAT_GPIO_H
+
+/*
+ * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
+ * one set of registers. The register offsets are organized below:
+ *
+ *           GPLR    GPDR    GPSR    GPCR    GRER    GFER    GEDR
+ * BANK 0 - 0x0000  0x000C  0x0018  0x0024  0x0030  0x003C  0x0048
+ * BANK 1 - 0x0004  0x0010  0x001C  0x0028  0x0034  0x0040  0x004C
+ * BANK 2 - 0x0008  0x0014  0x0020  0x002C  0x0038  0x0044  0x0050
+ *
+ * BANK 3 - 0x0100  0x010C  0x0118  0x0124  0x0130  0x013C  0x0148
+ * BANK 4 - 0x0104  0x0110  0x011C  0x0128  0x0134  0x0140  0x014C
+ * BANK 5 - 0x0108  0x0114  0x0120  0x012C  0x0138  0x0144  0x0150
+ *
+ * NOTE:
+ *   BANK 3 is only available on PXA27x and later processors.
+ *   BANK 4 and 5 are only available on PXA935
+ */
+
+#define GPIO_BANK(n)    (GPIO_REGS_VIRT + BANK_OFF(n))
+
+#define GPLR_OFFSET     0x00
+#define GPDR_OFFSET     0x0C
+#define GPSR_OFFSET     0x18
+#define GPCR_OFFSET     0x24
+#define GRER_OFFSET     0x30
+#define GFER_OFFSET     0x3C
+#define GEDR_OFFSET     0x48
+
+static inline int gpio_get_value(unsigned gpio)
+{
+        if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO))
+                return GPLR(gpio) & GPIO_bit(gpio);
+        else
+                return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) {
+                if (value)
+                        GPSR(gpio) = GPIO_bit(gpio);
+                else
+                        GPCR(gpio) = GPIO_bit(gpio);
+        } else
+                __gpio_set_value(gpio, value);
+}
+
+#define gpio_cansleep           __gpio_cansleep
+
+/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
+ * Those cases currently cause holes in the GPIO number space, the
+ * actual number of the last GPIO is recorded by 'pxa_last_gpio'.
+ */
+extern int pxa_last_gpio;
+
+typedef int (*set_wake_t)(unsigned int irq, unsigned int on);
+
+extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn);
+#endif /* __PLAT_GPIO_H */
diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h
new file mode 100644
index 000000000000..64019464c8db
--- /dev/null
+++ b/arch/arm/plat-pxa/include/plat/mfp.h
@@ -0,0 +1,399 @@
+/*
+ * arch/arm/plat-pxa/include/plat/mfp.h
+ *
+ *   Common Multi-Function Pin Definitions
+ *
+ * Copyright (C) 2007 Marvell International Ltd.
+ *
+ * 2007-8-21: eric miao <eric.miao@marvell.com>
+ *            initial version
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_PLAT_MFP_H
+#define __ASM_PLAT_MFP_H
+
+#define mfp_to_gpio(m)  ((m) % 128)
+
+/* list of all the configurable MFP pins */
+enum {
+        MFP_PIN_INVALID = -1,
+
+        MFP_PIN_GPIO0 = 0,
+        MFP_PIN_GPIO1,
+        MFP_PIN_GPIO2,
+        MFP_PIN_GPIO3,
+        MFP_PIN_GPIO4,
+        MFP_PIN_GPIO5,
+        MFP_PIN_GPIO6,
+        MFP_PIN_GPIO7,
+        MFP_PIN_GPIO8,
+        MFP_PIN_GPIO9,
+        MFP_PIN_GPIO10,
+        MFP_PIN_GPIO11,
+        MFP_PIN_GPIO12,
+        MFP_PIN_GPIO13,
+        MFP_PIN_GPIO14,
+        MFP_PIN_GPIO15,
+        MFP_PIN_GPIO16,
+        MFP_PIN_GPIO17,
+        MFP_PIN_GPIO18,
+        MFP_PIN_GPIO19,
+        MFP_PIN_GPIO20,
+        MFP_PIN_GPIO21,
+        MFP_PIN_GPIO22,
+        MFP_PIN_GPIO23,
+        MFP_PIN_GPIO24,
+        MFP_PIN_GPIO25,
+        MFP_PIN_GPIO26,
+        MFP_PIN_GPIO27,
+        MFP_PIN_GPIO28,
+        MFP_PIN_GPIO29,
+        MFP_PIN_GPIO30,
+        MFP_PIN_GPIO31,
+        MFP_PIN_GPIO32,
+        MFP_PIN_GPIO33,
+        MFP_PIN_GPIO34,
+        MFP_PIN_GPIO35,
+        MFP_PIN_GPIO36,
+        MFP_PIN_GPIO37,
+        MFP_PIN_GPIO38,
+        MFP_PIN_GPIO39,
+        MFP_PIN_GPIO40,
+        MFP_PIN_GPIO41,
+        MFP_PIN_GPIO42,
+        MFP_PIN_GPIO43,
+        MFP_PIN_GPIO44,
+        MFP_PIN_GPIO45,
+        MFP_PIN_GPIO46,
+        MFP_PIN_GPIO47,
+        MFP_PIN_GPIO48,
+        MFP_PIN_GPIO49,
+        MFP_PIN_GPIO50,
+        MFP_PIN_GPIO51,
+        MFP_PIN_GPIO52,
+        MFP_PIN_GPIO53,
+        MFP_PIN_GPIO54,
+        MFP_PIN_GPIO55,
+        MFP_PIN_GPIO56,
+        MFP_PIN_GPIO57,
+        MFP_PIN_GPIO58,
+        MFP_PIN_GPIO59,
+        MFP_PIN_GPIO60,
+        MFP_PIN_GPIO61,
+        MFP_PIN_GPIO62,
+        MFP_PIN_GPIO63,
+        MFP_PIN_GPIO64,
+        MFP_PIN_GPIO65,
+        MFP_PIN_GPIO66,
+        MFP_PIN_GPIO67,
+        MFP_PIN_GPIO68,
+        MFP_PIN_GPIO69,
+        MFP_PIN_GPIO70,
+        MFP_PIN_GPIO71,
+        MFP_PIN_GPIO72,
+        MFP_PIN_GPIO73,
+        MFP_PIN_GPIO74,
+        MFP_PIN_GPIO75,
+        MFP_PIN_GPIO76,
+        MFP_PIN_GPIO77,
+        MFP_PIN_GPIO78,
+        MFP_PIN_GPIO79,
+        MFP_PIN_GPIO80,
+        MFP_PIN_GPIO81,
+        MFP_PIN_GPIO82,
+        MFP_PIN_GPIO83,
+        MFP_PIN_GPIO84,
+        MFP_PIN_GPIO85,
+        MFP_PIN_GPIO86,
+        MFP_PIN_GPIO87,
+        MFP_PIN_GPIO88,
+        MFP_PIN_GPIO89,
+        MFP_PIN_GPIO90,
+        MFP_PIN_GPIO91,
+        MFP_PIN_GPIO92,
+        MFP_PIN_GPIO93,
+        MFP_PIN_GPIO94,
+        MFP_PIN_GPIO95,
+        MFP_PIN_GPIO96,
+        MFP_PIN_GPIO97,
+        MFP_PIN_GPIO98,
+        MFP_PIN_GPIO99,
+        MFP_PIN_GPIO100,
+        MFP_PIN_GPIO101,
+        MFP_PIN_GPIO102,
+        MFP_PIN_GPIO103,
+        MFP_PIN_GPIO104,
+        MFP_PIN_GPIO105,
+        MFP_PIN_GPIO106,
+        MFP_PIN_GPIO107,
+        MFP_PIN_GPIO108,
+        MFP_PIN_GPIO109,
+        MFP_PIN_GPIO110,
+        MFP_PIN_GPIO111,
+        MFP_PIN_GPIO112,
+        MFP_PIN_GPIO113,
+        MFP_PIN_GPIO114,
+        MFP_PIN_GPIO115,
+        MFP_PIN_GPIO116,
+        MFP_PIN_GPIO117,
+        MFP_PIN_GPIO118,
+        MFP_PIN_GPIO119,
+        MFP_PIN_GPIO120,
+        MFP_PIN_GPIO121,
+        MFP_PIN_GPIO122,
+        MFP_PIN_GPIO123,
+        MFP_PIN_GPIO124,
+        MFP_PIN_GPIO125,
+        MFP_PIN_GPIO126,
+        MFP_PIN_GPIO127,
+        MFP_PIN_GPIO0_2,
+        MFP_PIN_GPIO1_2,
+        MFP_PIN_GPIO2_2,
+        MFP_PIN_GPIO3_2,
+        MFP_PIN_GPIO4_2,
+        MFP_PIN_GPIO5_2,
+        MFP_PIN_GPIO6_2,
+        MFP_PIN_GPIO7_2,
+        MFP_PIN_GPIO8_2,
+        MFP_PIN_GPIO9_2,
+        MFP_PIN_GPIO10_2,
+        MFP_PIN_GPIO11_2,
+        MFP_PIN_GPIO12_2,
+        MFP_PIN_GPIO13_2,
+        MFP_PIN_GPIO14_2,
+        MFP_PIN_GPIO15_2,
+        MFP_PIN_GPIO16_2,
+        MFP_PIN_GPIO17_2,
+
+        MFP_PIN_ULPI_STP,
+        MFP_PIN_ULPI_NXT,
+        MFP_PIN_ULPI_DIR,
+
+        MFP_PIN_nXCVREN,
+        MFP_PIN_DF_CLE_nOE,
+        MFP_PIN_DF_nADV1_ALE,
+        MFP_PIN_DF_SCLK_E,
+        MFP_PIN_DF_SCLK_S,
+        MFP_PIN_nBE0,
+        MFP_PIN_nBE1,
+        MFP_PIN_DF_nADV2_ALE,
+        MFP_PIN_DF_INT_RnB,
+        MFP_PIN_DF_nCS0,
+        MFP_PIN_DF_nCS1,
+        MFP_PIN_nLUA,
+        MFP_PIN_nLLA,
+        MFP_PIN_DF_nWE,
+        MFP_PIN_DF_ALE_nWE,
+        MFP_PIN_DF_nRE_nOE,
+        MFP_PIN_DF_ADDR0,
+        MFP_PIN_DF_ADDR1,
+        MFP_PIN_DF_ADDR2,
+        MFP_PIN_DF_ADDR3,
+        MFP_PIN_DF_IO0,
+        MFP_PIN_DF_IO1,
+        MFP_PIN_DF_IO2,
+        MFP_PIN_DF_IO3,
+        MFP_PIN_DF_IO4,
+        MFP_PIN_DF_IO5,
+        MFP_PIN_DF_IO6,
+        MFP_PIN_DF_IO7,
+        MFP_PIN_DF_IO8,
+        MFP_PIN_DF_IO9,
+        MFP_PIN_DF_IO10,
+        MFP_PIN_DF_IO11,
+        MFP_PIN_DF_IO12,
+        MFP_PIN_DF_IO13,
+        MFP_PIN_DF_IO14,
+        MFP_PIN_DF_IO15,
+        MFP_PIN_DF_nCS0_SM_nCS2,
+        MFP_PIN_DF_nCS1_SM_nCS3,
+        MFP_PIN_SM_nCS0,
+        MFP_PIN_SM_nCS1,
+        MFP_PIN_DF_WEn,
+        MFP_PIN_DF_REn,
+        MFP_PIN_DF_CLE_SM_OEn,
+        MFP_PIN_DF_ALE_SM_WEn,
+        MFP_PIN_DF_RDY0,
+        MFP_PIN_DF_RDY1,
+
+        MFP_PIN_SM_SCLK,
+        MFP_PIN_SM_BE0,
+        MFP_PIN_SM_BE1,
+        MFP_PIN_SM_ADV,
+        MFP_PIN_SM_ADVMUX,
+        MFP_PIN_SM_RDY,
+
+        MFP_PIN_MMC1_DAT7,
+        MFP_PIN_MMC1_DAT6,
+        MFP_PIN_MMC1_DAT5,
+        MFP_PIN_MMC1_DAT4,
+        MFP_PIN_MMC1_DAT3,
+        MFP_PIN_MMC1_DAT2,
+        MFP_PIN_MMC1_DAT1,
+        MFP_PIN_MMC1_DAT0,
+        MFP_PIN_MMC1_CMD,
+        MFP_PIN_MMC1_CLK,
+        MFP_PIN_MMC1_CD,
+        MFP_PIN_MMC1_WP,
+
+        /* additional pins on PXA930 */
+        MFP_PIN_GSIM_UIO,
+        MFP_PIN_GSIM_UCLK,
+        MFP_PIN_GSIM_UDET,
+        MFP_PIN_GSIM_nURST,
+        MFP_PIN_PMIC_INT,
+        MFP_PIN_RDY,
+
+        MFP_PIN_MAX,
+};
+
+/*
+ * a possible MFP configuration is represented by a 32-bit integer
+ *
+ * bit  0.. 9 - MFP Pin Number (1024 Pins Maximum)
+ * bit 10..12 - Alternate Function Selection
+ * bit 13..15 - Drive Strength
+ * bit 16..18 - Low Power Mode State
+ * bit 19..20 - Low Power Mode Edge Detection
+ * bit 21..22 - Run Mode Pull State
+ *
+ * to facilitate the definition, the following macros are provided
+ *
+ * MFP_CFG_DEFAULT - default MFP configuration value, with
+ *                alternate function = 0,
+ *                drive strength = fast 3mA (MFP_DS03X)
+ *                low power mode = default
+ *                edge detection = none
+ *
+ * MFP_CFG      - default MFPR value with alternate function
+ * MFP_CFG_DRV  - default MFPR value with alternate function and
+ *                pin drive strength
+ * MFP_CFG_LPM  - default MFPR value with alternate function and
+ *                low power mode
+ * MFP_CFG_X    - default MFPR value with alternate function,
+ *                pin drive strength and low power mode
+ */
+
+typedef unsigned long mfp_cfg_t;
+
+#define MFP_PIN(x)              ((x) & 0x3ff)
+
+#define MFP_AF0                 (0x0 << 10)
+#define MFP_AF1                 (0x1 << 10)
+#define MFP_AF2                 (0x2 << 10)
+#define MFP_AF3                 (0x3 << 10)
+#define MFP_AF4                 (0x4 << 10)
+#define MFP_AF5                 (0x5 << 10)
+#define MFP_AF6                 (0x6 << 10)
+#define MFP_AF7                 (0x7 << 10)
+#define MFP_AF_MASK             (0x7 << 10)
+#define MFP_AF(x)               (((x) >> 10) & 0x7)
+
+#define MFP_DS01X               (0x0 << 13)
+#define MFP_DS02X               (0x1 << 13)
+#define MFP_DS03X               (0x2 << 13)
+#define MFP_DS04X               (0x3 << 13)
+#define MFP_DS06X               (0x4 << 13)
+#define MFP_DS08X               (0x5 << 13)
+#define MFP_DS10X               (0x6 << 13)
+#define MFP_DS13X               (0x7 << 13)
+#define MFP_DS_MASK             (0x7 << 13)
+#define MFP_DS(x)               (((x) >> 13) & 0x7)
+
+#define MFP_LPM_DEFAULT         (0x0 << 16)
+#define MFP_LPM_DRIVE_LOW       (0x1 << 16)
+#define MFP_LPM_DRIVE_HIGH      (0x2 << 16)
+#define MFP_LPM_PULL_LOW        (0x3 << 16)
+#define MFP_LPM_PULL_HIGH       (0x4 << 16)
+#define MFP_LPM_FLOAT           (0x5 << 16)
+#define MFP_LPM_INPUT           (0x6 << 16)
+#define MFP_LPM_STATE_MASK      (0x7 << 16)
+#define MFP_LPM_STATE(x)        (((x) >> 16) & 0x7)
+
+#define MFP_LPM_EDGE_NONE       (0x0 << 19)
+#define MFP_LPM_EDGE_RISE       (0x1 << 19)
+#define MFP_LPM_EDGE_FALL       (0x2 << 19)
+#define MFP_LPM_EDGE_BOTH       (0x3 << 19)
+#define MFP_LPM_EDGE_MASK       (0x3 << 19)
+#define MFP_LPM_EDGE(x)         (((x) >> 19) & 0x3)
+
+#define MFP_PULL_NONE           (0x0 << 21)
+#define MFP_PULL_LOW            (0x1 << 21)
+#define MFP_PULL_HIGH           (0x2 << 21)
+#define MFP_PULL_BOTH           (0x3 << 21)
+#define MFP_PULL_MASK           (0x3 << 21)
+#define MFP_PULL(x)             (((x) >> 21) & 0x3)
+
+#define MFP_CFG_DEFAULT         (MFP_AF0 | MFP_DS03X | MFP_LPM_DEFAULT |\
+                                 MFP_LPM_EDGE_NONE | MFP_PULL_NONE)
+
+#define MFP_CFG(pin, af)                \
+        ((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\
+         (MFP_PIN(MFP_PIN_##pin) | MFP_##af))
+
+#define MFP_CFG_DRV(pin, af, drv)       \
+        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\
+         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv))
+
+#define MFP_CFG_LPM(pin, af, lpm)       \
+        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\
+         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm))
+
+#define MFP_CFG_X(pin, af, drv, lpm)    \
+        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\
+         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
+
+#if defined(CONFIG_PXA3xx) || defined(CONFIG_ARCH_MMP)
+/*
+ * each MFP pin will have a MFPR register, since the offset of the
+ * register varies between processors, the processor specific code
+ * should initialize the pin offsets by mfp_init()
+ *
+ * mfp_init_base() - accepts a virtual base for all MFPR registers and
+ * initialize the MFP table to a default state
+ *
+ * mfp_init_addr() - accepts a table of "mfp_addr_map" structure, which
+ * represents a range of MFP pins from "start" to "end", with the offset
+ * begining at "offset", to define a single pin, let "end" = -1.
+ *
+ * use
+ *
+ * MFP_ADDR_X() to define a range of pins
+ * MFP_ADDR()   to define a single pin
+ * MFP_ADDR_END to signal the end of pin offset definitions
+ */
+struct mfp_addr_map {
+        unsigned int    start;
+        unsigned int    end;
+        unsigned long   offset;
+};
+
+#define MFP_ADDR_X(start, end, offset) \
+        { MFP_PIN_##start, MFP_PIN_##end, offset }
+
+#define MFP_ADDR(pin, offset) \
+        { MFP_PIN_##pin, -1, offset }
+
+#define MFP_ADDR_END    { MFP_PIN_INVALID, 0 }
+
+void __init mfp_init_base(unsigned long mfpr_base);
+void __init mfp_init_addr(struct mfp_addr_map *map);
+
+/*
+ * mfp_{read, write}()  - for direct read/write access to the MFPR register
+ * mfp_config()         - for configuring a group of MFPR registers
+ * mfp_config_lpm()     - configuring all low power MFPR registers for suspend
+ * mfp_config_run()     - configuring all run time  MFPR registers after resume
+ */
+unsigned long mfp_read(int mfp);
+void mfp_write(int mfp, unsigned long mfpr_val);
+void mfp_config(unsigned long *mfp_cfgs, int num);
+void mfp_config_run(void);
+void mfp_config_lpm(void);
+#endif /* CONFIG_PXA3xx || CONFIG_ARCH_MMP */
+
+#endif /* __ASM_PLAT_MFP_H */
diff --git a/arch/arm/plat-pxa/mfp.c b/arch/arm/plat-pxa/mfp.c
new file mode 100644
index 000000000000..e716c622a17c
--- /dev/null
+++ b/arch/arm/plat-pxa/mfp.c
@@ -0,0 +1,278 @@
+/*
+ * linux/arch/arm/plat-pxa/mfp.c
+ *
+ *   Multi-Function Pin Support
+ *
+ * Copyright (C) 2007 Marvell Internation Ltd.
+ *
+ * 2007-08-21: eric miao <eric.miao@marvell.com>
+ *             initial version
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+
+#include <plat/mfp.h>
+
+#define MFPR_SIZE       (PAGE_SIZE)
+
+/* MFPR register bit definitions */
+#define MFPR_PULL_SEL           (0x1 << 15)
+#define MFPR_PULLUP_EN          (0x1 << 14)
+#define MFPR_PULLDOWN_EN        (0x1 << 13)
+#define MFPR_SLEEP_SEL          (0x1 << 9)
+#define MFPR_SLEEP_OE_N         (0x1 << 7)
+#define MFPR_EDGE_CLEAR         (0x1 << 6)
+#define MFPR_EDGE_FALL_EN       (0x1 << 5)
+#define MFPR_EDGE_RISE_EN       (0x1 << 4)
+
+#define MFPR_SLEEP_DATA(x)      ((x) << 8)
+#define MFPR_DRIVE(x)           (((x) & 0x7) << 10)
+#define MFPR_AF_SEL(x)          (((x) & 0x7) << 0)
+
+#define MFPR_EDGE_NONE          (0)
+#define MFPR_EDGE_RISE          (MFPR_EDGE_RISE_EN)
+#define MFPR_EDGE_FALL          (MFPR_EDGE_FALL_EN)
+#define MFPR_EDGE_BOTH          (MFPR_EDGE_RISE | MFPR_EDGE_FALL)
+
+/*
+ * Table that determines the low power modes outputs, with actual settings
+ * used in parentheses for don't-care values. Except for the float output,
+ * the configured driven and pulled levels match, so if there is a need for
+ * non-LPM pulled output, the same configuration could probably be used.
+ *
+ * Output value  sleep_oe_n  sleep_data  pullup_en  pulldown_en  pull_sel
+ *                 (bit 7)    (bit 8)    (bit 14)     (bit 13)   (bit 15)
+ *
+ * Input            0          X(0)        X(0)        X(0)       0
+ * Drive 0          0          0           0           X(1)       0
+ * Drive 1          0          1           X(1)        0          0
+ * Pull hi (1)      1          X(1)        1           0          0
+ * Pull lo (0)      1          X(0)        0           1          0
+ * Z (float)        1          X(0)        0           0          0
+ */
+#define MFPR_LPM_INPUT          (0)
+#define MFPR_LPM_DRIVE_LOW      (MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN)
+#define MFPR_LPM_DRIVE_HIGH     (MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN)
+#define MFPR_LPM_PULL_LOW       (MFPR_LPM_DRIVE_LOW  | MFPR_SLEEP_OE_N)
+#define MFPR_LPM_PULL_HIGH      (MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N)
+#define MFPR_LPM_FLOAT          (MFPR_SLEEP_OE_N)
+#define MFPR_LPM_MASK           (0xe080)
+
+/*
+ * The pullup and pulldown state of the MFP pin at run mode is by default
+ * determined by the selected alternate function. In case that some buggy
+ * devices need to override this default behavior,  the definitions below
+ * indicates the setting of corresponding MFPR bits
+ *
+ * Definition       pull_sel  pullup_en  pulldown_en
+ * MFPR_PULL_NONE       0         0        0
+ * MFPR_PULL_LOW        1         0        1
+ * MFPR_PULL_HIGH       1         1        0
+ * MFPR_PULL_BOTH       1         1        1
+ */
+#define MFPR_PULL_NONE          (0)
+#define MFPR_PULL_LOW           (MFPR_PULL_SEL | MFPR_PULLDOWN_EN)
+#define MFPR_PULL_BOTH          (MFPR_PULL_LOW | MFPR_PULLUP_EN)
+#define MFPR_PULL_HIGH          (MFPR_PULL_SEL | MFPR_PULLUP_EN)
+
+/* mfp_spin_lock is used to ensure that MFP register configuration
+ * (most likely a read-modify-write operation) is atomic, and that
+ * mfp_table[] is consistent
+ */
+static DEFINE_SPINLOCK(mfp_spin_lock);
+
+static void __iomem *mfpr_mmio_base;
+
+struct mfp_pin {
+        unsigned long   config;         /* -1 for not configured */
+        unsigned long   mfpr_off;       /* MFPRxx Register offset */
+        unsigned long   mfpr_run;       /* Run-Mode Register Value */
+        unsigned long   mfpr_lpm;       /* Low Power Mode Register Value */
+};
+
+static struct mfp_pin mfp_table[MFP_PIN_MAX];
+
+/* mapping of MFP_LPM_* definitions to MFPR_LPM_* register bits */
+static const unsigned long mfpr_lpm[] = {
+        MFPR_LPM_INPUT,
+        MFPR_LPM_DRIVE_LOW,
+        MFPR_LPM_DRIVE_HIGH,
+        MFPR_LPM_PULL_LOW,
+        MFPR_LPM_PULL_HIGH,
+        MFPR_LPM_FLOAT,
+};
+
+/* mapping of MFP_PULL_* definitions to MFPR_PULL_* register bits */
+static const unsigned long mfpr_pull[] = {
+        MFPR_PULL_NONE,
+        MFPR_PULL_LOW,
+        MFPR_PULL_HIGH,
+        MFPR_PULL_BOTH,
+};
+
+/* mapping of MFP_LPM_EDGE_* definitions to MFPR_EDGE_* register bits */
+static const unsigned long mfpr_edge[] = {
+        MFPR_EDGE_NONE,
+        MFPR_EDGE_RISE,
+        MFPR_EDGE_FALL,
+        MFPR_EDGE_BOTH,
+};
+
+#define mfpr_readl(off)                 \
+        __raw_readl(mfpr_mmio_base + (off))
+
+#define mfpr_writel(off, val)           \
+        __raw_writel(val, mfpr_mmio_base + (off))
+
+#define mfp_configured(p)       ((p)->config != -1)
+
+/*
+ * perform a read-back of any MFPR register to make sure the
+ * previous writings are finished
+ */
+#define mfpr_sync()     (void)__raw_readl(mfpr_mmio_base + 0)
+
+static inline void __mfp_config_run(struct mfp_pin *p)
+{
+        if (mfp_configured(p))
+                mfpr_writel(p->mfpr_off, p->mfpr_run);
+}
+
+static inline void __mfp_config_lpm(struct mfp_pin *p)
+{
+        if (mfp_configured(p)) {
+                unsigned long mfpr_clr = (p->mfpr_run & ~MFPR_EDGE_BOTH) | MFPR_EDGE_CLEAR;
+                if (mfpr_clr != p->mfpr_run)
+                        mfpr_writel(p->mfpr_off, mfpr_clr);
+                if (p->mfpr_lpm != mfpr_clr)
+                        mfpr_writel(p->mfpr_off, p->mfpr_lpm);
+        }
+}
+
+void mfp_config(unsigned long *mfp_cfgs, int num)
+{
+        unsigned long flags;
+        int i;
+
+        spin_lock_irqsave(&mfp_spin_lock, flags);
+
+        for (i = 0; i < num; i++, mfp_cfgs++) {
+                unsigned long tmp, c = *mfp_cfgs;
+                struct mfp_pin *p;
+                int pin, af, drv, lpm, edge, pull;
+
+                pin = MFP_PIN(c);
+                BUG_ON(pin >= MFP_PIN_MAX);
+                p = &mfp_table[pin];
+
+                af  = MFP_AF(c);
+                drv = MFP_DS(c);
+                lpm = MFP_LPM_STATE(c);
+                edge = MFP_LPM_EDGE(c);
+                pull = MFP_PULL(c);
+
+                /* run-mode pull settings will conflict with MFPR bits of
+                 * low power mode state,  calculate mfpr_run and mfpr_lpm
+                 * individually if pull != MFP_PULL_NONE
+                 */
+                tmp = MFPR_AF_SEL(af) | MFPR_DRIVE(drv);
+
+                if (likely(pull == MFP_PULL_NONE)) {
+                        p->mfpr_run = tmp | mfpr_lpm[lpm] | mfpr_edge[edge];
+                        p->mfpr_lpm = p->mfpr_run;
+                } else {
+                        p->mfpr_lpm = tmp | mfpr_lpm[lpm] | mfpr_edge[edge];
+                        p->mfpr_run = tmp | mfpr_pull[pull];
+                }
+
+                p->config = c; __mfp_config_run(p);
+        }
+
+        mfpr_sync();
+        spin_unlock_irqrestore(&mfp_spin_lock, flags);
+}
+
+unsigned long mfp_read(int mfp)
+{
+        unsigned long val, flags;
+
+        BUG_ON(mfp >= MFP_PIN_MAX);
+
+        spin_lock_irqsave(&mfp_spin_lock, flags);
+        val = mfpr_readl(mfp_table[mfp].mfpr_off);
+        spin_unlock_irqrestore(&mfp_spin_lock, flags);
+
+        return val;
+}
+
+void mfp_write(int mfp, unsigned long val)
+{
+        unsigned long flags;
+
+        BUG_ON(mfp >= MFP_PIN_MAX);
+
+        spin_lock_irqsave(&mfp_spin_lock, flags);
+        mfpr_writel(mfp_table[mfp].mfpr_off, val);
+        mfpr_sync();
+        spin_unlock_irqrestore(&mfp_spin_lock, flags);
+}
+
+void __init mfp_init_base(unsigned long mfpr_base)
+{
+        int i;
+
+        /* initialize the table with default - unconfigured */
+        for (i = 0; i < ARRAY_SIZE(mfp_table); i++)
+                mfp_table[i].config = -1;
+
+        mfpr_mmio_base = (void __iomem *)mfpr_base;
+}
+
+void __init mfp_init_addr(struct mfp_addr_map *map)
+{
+        struct mfp_addr_map *p;
+        unsigned long offset, flags;
+        int i;
+
+        spin_lock_irqsave(&mfp_spin_lock, flags);
+
+        for (p = map; p->start != MFP_PIN_INVALID; p++) {
+                offset = p->offset;
+                i = p->start;
+
+                do {
+                        mfp_table[i].mfpr_off = offset;
+                        mfp_table[i].mfpr_run = 0;
+                        mfp_table[i].mfpr_lpm = 0;
+                        offset += 4; i++;
+                } while ((i <= p->end) && (p->end != -1));
+        }
+
+        spin_unlock_irqrestore(&mfp_spin_lock, flags);
+}
+
+void mfp_config_lpm(void)
+{
+        struct mfp_pin *p = &mfp_table[0];
+        int pin;
+
+        for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++)
+                __mfp_config_lpm(p);
+}
+
+void mfp_config_run(void)
+{
+        struct mfp_pin *p = &mfp_table[0];
+        int pin;
+
+        for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++)
+                __mfp_config_run(p);
+}
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile
index 39195f972d5e..8d7815d25a51 100644
--- a/arch/arm/plat-s3c/Makefile
+++ b/arch/arm/plat-s3c/Makefile
@@ -18,6 +18,11 @@ obj-y				+= pwm-clock.o
 obj-y                           += gpio.o
 obj-y                           += gpio-config.o
 
+# PM support
+
+obj-$(CONFIG_PM)                += pm.o
+obj-$(CONFIG_S3C2410_PM_CHECK)  += pm-check.o
+
 # devices
 
 obj-$(CONFIG_S3C_DEV_HSMMC)     += dev-hsmmc.o
diff --git a/arch/arm/plat-s3c/include/plat/pm.h b/arch/arm/plat-s3c/include/plat/pm.h
new file mode 100644
index 000000000000..3779775133a9
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/pm.h
@@ -0,0 +1,174 @@
+/* linux/include/asm-arm/plat-s3c24xx/pm.h
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Written by Ben Dooks, <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* s3c_pm_init
+ *
+ * called from board at initialisation time to setup the power
+ * management
+*/
+
+#ifdef CONFIG_PM
+
+extern __init int s3c_pm_init(void);
+
+#else
+
+static inline int s3c_pm_init(void)
+{
+        return 0;
+}
+#endif
+
+/* configuration for the IRQ mask over sleep */
+extern unsigned long s3c_irqwake_intmask;
+extern unsigned long s3c_irqwake_eintmask;
+
+/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */
+extern unsigned long s3c_irqwake_intallow;
+extern unsigned long s3c_irqwake_eintallow;
+
+/* per-cpu sleep functions */
+
+extern void (*pm_cpu_prep)(void);
+extern void (*pm_cpu_sleep)(void);
+
+/* Flags for PM Control */
+
+extern unsigned long s3c_pm_flags;
+
+/* from sleep.S */
+
+extern int  s3c_cpu_save(unsigned long *saveblk);
+extern void s3c_cpu_resume(void);
+
+extern void s3c2410_cpu_suspend(void);
+
+extern unsigned long s3c_sleep_save_phys;
+
+/* sleep save info */
+
+/**
+ * struct sleep_save - save information for shared peripherals.
+ * @reg: Pointer to the register to save.
+ * @val: Holder for the value saved from reg.
+ *
+ * This describes a list of registers which is used by the pm core and
+ * other subsystem to save and restore register values over suspend.
+ */
+struct sleep_save {
+        void __iomem    *reg;
+        unsigned long   val;
+};
+
+#define SAVE_ITEM(x) \
+        { .reg = (x) }
+
+/**
+ * struct pm_uart_save - save block for core UART
+ * @ulcon: Save value for S3C2410_ULCON
+ * @ucon: Save value for S3C2410_UCON
+ * @ufcon: Save value for S3C2410_UFCON
+ * @umcon: Save value for S3C2410_UMCON
+ * @ubrdiv: Save value for S3C2410_UBRDIV
+ *
+ * Save block for UART registers to be held over sleep and restored if they
+ * are needed (say by debug).
+*/
+struct pm_uart_save {
+        u32     ulcon;
+        u32     ucon;
+        u32     ufcon;
+        u32     umcon;
+        u32     ubrdiv;
+};
+
+/* helper functions to save/restore lists of registers. */
+
+extern void s3c_pm_do_save(struct sleep_save *ptr, int count);
+extern void s3c_pm_do_restore(struct sleep_save *ptr, int count);
+extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count);
+
+#ifdef CONFIG_PM
+extern int s3c_irqext_wake(unsigned int irqno, unsigned int state);
+extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state);
+extern int s3c24xx_irq_resume(struct sys_device *dev);
+#else
+#define s3c_irqext_wake NULL
+#define s3c24xx_irq_suspend NULL
+#define s3c24xx_irq_resume  NULL
+#endif
+
+/* PM debug functions */
+
+#ifdef CONFIG_S3C2410_PM_DEBUG
+/**
+ * s3c_pm_dbg() - low level debug function for use in suspend/resume.
+ * @msg: The message to print.
+ *
+ * This function is used mainly to debug the resume process before the system
+ * can rely on printk/console output. It uses the low-level debugging output
+ * routine printascii() to do its work.
+ */
+extern void s3c_pm_dbg(const char *msg, ...);
+
+#define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt)
+#else
+#define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt)
+#endif
+
+/* suspend memory checking */
+
+#ifdef CONFIG_S3C2410_PM_CHECK
+extern void s3c_pm_check_prepare(void);
+extern void s3c_pm_check_restore(void);
+extern void s3c_pm_check_cleanup(void);
+extern void s3c_pm_check_store(void);
+#else
+#define s3c_pm_check_prepare() do { } while(0)
+#define s3c_pm_check_restore() do { } while(0)
+#define s3c_pm_check_cleanup() do { } while(0)
+#define s3c_pm_check_store()   do { } while(0)
+#endif
+
+/**
+ * s3c_pm_configure_extint() - ensure pins are correctly set for IRQ
+ *
+ * Setup all the necessary GPIO pins for waking the system on external
+ * interrupt.
+ */
+extern void s3c_pm_configure_extint(void);
+
+/**
+ * s3c_pm_restore_gpios() - restore the state of the gpios after sleep.
+ *
+ * Restore the state of the GPIO pins after sleep, which may involve ensuring
+ * that we do not glitch the state of the pins from that the bootloader's
+ * resume code has done.
+*/
+extern void s3c_pm_restore_gpios(void);
+
+/**
+ * s3c_pm_save_gpios() - save the state of the GPIOs for restoring after sleep.
+ *
+ * Save the GPIO states for resotration on resume. See s3c_pm_restore_gpios().
+ */
+extern void s3c_pm_save_gpios(void);
+
+/**
+ * s3c_pm_cb_flushcache - callback for assembly code
+ *
+ * Callback to issue flush_cache_all() as this call is
+ * not a directly callable object.
+ */
+extern void s3c_pm_cb_flushcache(void);
+
+extern void s3c_pm_save_core(void);
+extern void s3c_pm_restore_core(void);
diff --git a/arch/arm/plat-s3c/include/plat/uncompress.h b/arch/arm/plat-s3c/include/plat/uncompress.h
index 6061de87f225..dc66a477f62e 100644
--- a/arch/arm/plat-s3c/include/plat/uncompress.h
+++ b/arch/arm/plat-s3c/include/plat/uncompress.h
@@ -90,7 +90,10 @@ static inline void flush(void)
 {
 }
 
-#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
+#define __raw_writel(d, ad)                     \
+        do {                                                    \
+                *((volatile unsigned int __force *)(ad)) = (d); \
+        } while (0)
 
 /* CONFIG_S3C_BOOT_WATCHDOG
  *
diff --git a/arch/arm/plat-s3c/pm-check.c b/arch/arm/plat-s3c/pm-check.c
new file mode 100644
index 000000000000..39f2555564da
--- /dev/null
+++ b/arch/arm/plat-s3c/pm-check.c
@@ -0,0 +1,242 @@
+/* linux/arch/arm/plat-s3c/pm-check.c
+ *  originally in linux/arch/arm/plat-s3c24xx/pm.c
+ *
+ * Copyright (c) 2004,2006,2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C Power Mangament - suspend/resume memory corruptiuon check.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+#include <linux/init.h>
+#include <linux/crc32.h>
+#include <linux/ioport.h>
+
+#include <plat/pm.h>
+
+#if CONFIG_S3C2410_PM_CHECK_CHUNKSIZE < 1
+#error CONFIG_S3C2410_PM_CHECK_CHUNKSIZE must be a positive non-zero value
+#endif
+
+/* suspend checking code...
+ *
+ * this next area does a set of crc checks over all the installed
+ * memory, so the system can verify if the resume was ok.
+ *
+ * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
+ * increasing it will mean that the area corrupted will be less easy to spot,
+ * and reducing the size will cause the CRC save area to grow
+*/
+
+#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024)
+
+static u32 crc_size;    /* size needed for the crc block */
+static u32 *crcs;       /* allocated over suspend/resume */
+
+typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);
+
+/* s3c_pm_run_res
+ *
+ * go through the given resource list, and look for system ram
+*/
+
+static void s3c_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
+{
+        while (ptr != NULL) {
+                if (ptr->child != NULL)
+                        s3c_pm_run_res(ptr->child, fn, arg);
+
+                if ((ptr->flags & IORESOURCE_MEM) &&
+                    strcmp(ptr->name, "System RAM") == 0) {
+                        S3C_PMDBG("Found system RAM at %08lx..%08lx\n",
+                                  (unsigned long)ptr->start,
+                                  (unsigned long)ptr->end);
+                        arg = (fn)(ptr, arg);
+                }
+
+                ptr = ptr->sibling;
+        }
+}
+
+static void s3c_pm_run_sysram(run_fn_t fn, u32 *arg)
+{
+        s3c_pm_run_res(&iomem_resource, fn, arg);
+}
+
+static u32 *s3c_pm_countram(struct resource *res, u32 *val)
+{
+        u32 size = (u32)(res->end - res->start)+1;
+
+        size += CHECK_CHUNKSIZE-1;
+        size /= CHECK_CHUNKSIZE;
+
+        S3C_PMDBG("Area %08lx..%08lx, %d blocks\n",
+                  (unsigned long)res->start, (unsigned long)res->end, size);
+
+        *val += size * sizeof(u32);
+        return val;
+}
+
+/* s3c_pm_prepare_check
+ *
+ * prepare the necessary information for creating the CRCs. This
+ * must be done before the final save, as it will require memory
+ * allocating, and thus touching bits of the kernel we do not
+ * know about.
+*/
+
+void s3c_pm_check_prepare(void)
+{
+        crc_size = 0;
+
+        s3c_pm_run_sysram(s3c_pm_countram, &crc_size);
+
+        S3C_PMDBG("s3c_pm_prepare_check: %u checks needed\n", crc_size);
+
+        crcs = kmalloc(crc_size+4, GFP_KERNEL);
+        if (crcs == NULL)
+                printk(KERN_ERR "Cannot allocated CRC save area\n");
+}
+
+static u32 *s3c_pm_makecheck(struct resource *res, u32 *val)
+{
+        unsigned long addr, left;
+
+        for (addr = res->start; addr < res->end;
+             addr += CHECK_CHUNKSIZE) {
+                left = res->end - addr;
+
+                if (left > CHECK_CHUNKSIZE)
+                        left = CHECK_CHUNKSIZE;
+
+                *val = crc32_le(~0, phys_to_virt(addr), left);
+                val++;
+        }
+
+        return val;
+}
+
+/* s3c_pm_check_store
+ *
+ * compute the CRC values for the memory blocks before the final
+ * sleep.
+*/
+
+void s3c_pm_check_store(void)
+{
+        if (crcs != NULL)
+                s3c_pm_run_sysram(s3c_pm_makecheck, crcs);
+}
+
+/* in_region
+ *
+ * return TRUE if the area defined by ptr..ptr+size contains the
+ * what..what+whatsz
+*/
+
+static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
+{
+        if ((what+whatsz) < ptr)
+                return 0;
+
+        if (what > (ptr+size))
+                return 0;
+
+        return 1;
+}
+
+/**
+ * s3c_pm_runcheck() - helper to check a resource on restore.
+ * @res: The resource to check
+ * @vak: Pointer to list of CRC32 values to check.
+ *
+ * Called from the s3c_pm_check_restore() via s3c_pm_run_sysram(), this
+ * function runs the given memory resource checking it against the stored
+ * CRC to ensure that memory is restored. The function tries to skip as
+ * many of the areas used during the suspend process.
+ */
+static u32 *s3c_pm_runcheck(struct resource *res, u32 *val)
+{
+        void *save_at = phys_to_virt(s3c_sleep_save_phys);
+        unsigned long addr;
+        unsigned long left;
+        void *stkpage;
+        void *ptr;
+        u32 calc;
+
+        stkpage = (void *)((u32)&calc & ~PAGE_MASK);
+
+        for (addr = res->start; addr < res->end;
+             addr += CHECK_CHUNKSIZE) {
+                left = res->end - addr;
+
+                if (left > CHECK_CHUNKSIZE)
+                        left = CHECK_CHUNKSIZE;
+
+                ptr = phys_to_virt(addr);
+
+                if (in_region(ptr, left, stkpage, 4096)) {
+                        S3C_PMDBG("skipping %08lx, has stack in\n", addr);
+                        goto skip_check;
+                }
+
+                if (in_region(ptr, left, crcs, crc_size)) {
+                        S3C_PMDBG("skipping %08lx, has crc block in\n", addr);
+                        goto skip_check;
+                }
+
+                if (in_region(ptr, left, save_at, 32*4 )) {
+                        S3C_PMDBG("skipping %08lx, has save block in\n", addr);
+                        goto skip_check;
+                }
+
+                /* calculate and check the checksum */
+
+                calc = crc32_le(~0, ptr, left);
+                if (calc != *val) {
+                        printk(KERN_ERR "Restore CRC error at "
+                               "%08lx (%08x vs %08x)\n", addr, calc, *val);
+
+                        S3C_PMDBG("Restore CRC error at %08lx (%08x vs %08x)\n",
+                            addr, calc, *val);
+                }
+
+        skip_check:
+                val++;
+        }
+
+        return val;
+}
+
+/**
+ * s3c_pm_check_restore() - memory check called on resume
+ *
+ * check the CRCs after the restore event and free the memory used
+ * to hold them
+*/
+void s3c_pm_check_restore(void)
+{
+        if (crcs != NULL)
+                s3c_pm_run_sysram(s3c_pm_runcheck, crcs);
+}
+
+/**
+ * s3c_pm_check_cleanup() - free memory resources
+ *
+ * Free the resources that where allocated by the suspend
+ * memory check code. We do this separately from the
+ * s3c_pm_check_restore() function as we cannot call any
+ * functions that might sleep during that resume.
+ */
+void s3c_pm_check_cleanup(void)
+{
+        kfree(crcs);
+        crcs = NULL;
+}
+
diff --git a/arch/arm/plat-s3c/pm.c b/arch/arm/plat-s3c/pm.c
new file mode 100644
index 000000000000..061182ca66e3
--- /dev/null
+++ b/arch/arm/plat-s3c/pm.c
@@ -0,0 +1,363 @@
+/* linux/arch/arm/plat-s3c/pm.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2004,2006,2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C common power management (suspend to ram) support.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/suspend.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/serial_core.h>
+#include <linux/io.h>
+
+#include <asm/cacheflush.h>
+#include <mach/hardware.h>
+
+#include <plat/regs-serial.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-mem.h>
+#include <mach/regs-irq.h>
+#include <asm/irq.h>
+
+#include <plat/pm.h>
+#include <plat/pm-core.h>
+
+/* for external use */
+
+unsigned long s3c_pm_flags;
+
+/* Debug code:
+ *
+ * This code supports debug output to the low level UARTs for use on
+ * resume before the console layer is available.
+*/
+
+#ifdef CONFIG_S3C2410_PM_DEBUG
+extern void printascii(const char *);
+
+void s3c_pm_dbg(const char *fmt, ...)
+{
+        va_list va;
+        char buff[256];
+
+        va_start(va, fmt);
+        vsprintf(buff, fmt, va);
+        va_end(va);
+
+        printascii(buff);
+}
+
+static inline void s3c_pm_debug_init(void)
+{
+        /* restart uart clocks so we can use them to output */
+        s3c_pm_debug_init_uart();
+}
+
+#else
+#define s3c_pm_debug_init() do { } while(0)
+
+#endif /* CONFIG_S3C2410_PM_DEBUG */
+
+/* Save the UART configurations if we are configured for debug. */
+
+#ifdef CONFIG_S3C2410_PM_DEBUG
+
+struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS];
+
+static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
+{
+        void __iomem *regs = S3C_VA_UARTx(uart);
+
+        save->ulcon = __raw_readl(regs + S3C2410_ULCON);
+        save->ucon = __raw_readl(regs + S3C2410_UCON);
+        save->ufcon = __raw_readl(regs + S3C2410_UFCON);
+        save->umcon = __raw_readl(regs + S3C2410_UMCON);
+        save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
+}
+
+static void s3c_pm_save_uarts(void)
+{
+        struct pm_uart_save *save = uart_save;
+        unsigned int uart;
+
+        for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++)
+                s3c_pm_save_uart(uart, save);
+}
+
+static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save)
+{
+        void __iomem *regs = S3C_VA_UARTx(uart);
+
+        __raw_writel(save->ulcon, regs + S3C2410_ULCON);
+        __raw_writel(save->ucon,  regs + S3C2410_UCON);
+        __raw_writel(save->ufcon, regs + S3C2410_UFCON);
+        __raw_writel(save->umcon, regs + S3C2410_UMCON);
+        __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
+}
+
+static void s3c_pm_restore_uarts(void)
+{
+        struct pm_uart_save *save = uart_save;
+        unsigned int uart;
+
+        for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++)
+                s3c_pm_restore_uart(uart, save);
+}
+#else
+static void s3c_pm_save_uarts(void) { }
+static void s3c_pm_restore_uarts(void) { }
+#endif
+
+/* The IRQ ext-int code goes here, it is too small to currently bother
+ * with its own file. */
+
+unsigned long s3c_irqwake_intmask       = 0xffffffffL;
+unsigned long s3c_irqwake_eintmask      = 0xffffffffL;
+
+int s3c_irqext_wake(unsigned int irqno, unsigned int state)
+{
+        unsigned long bit = 1L << IRQ_EINT_BIT(irqno);
+
+        if (!(s3c_irqwake_eintallow & bit))
+                return -ENOENT;
+
+        printk(KERN_INFO "wake %s for irq %d\n",
+               state ? "enabled" : "disabled", irqno);
+
+        if (!state)
+                s3c_irqwake_eintmask |= bit;
+        else
+                s3c_irqwake_eintmask &= ~bit;
+
+        return 0;
+}
+
+/* helper functions to save and restore register state */
+
+/**
+ * s3c_pm_do_save() - save a set of registers for restoration on resume.
+ * @ptr: Pointer to an array of registers.
+ * @count: Size of the ptr array.
+ *
+ * Run through the list of registers given, saving their contents in the
+ * array for later restoration when we wakeup.
+ */
+void s3c_pm_do_save(struct sleep_save *ptr, int count)
+{
+        for (; count > 0; count--, ptr++) {
+                ptr->val = __raw_readl(ptr->reg);
+                S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val);
+        }
+}
+
+/**
+ * s3c_pm_do_restore() - restore register values from the save list.
+ * @ptr: Pointer to an array of registers.
+ * @count: Size of the ptr array.
+ *
+ * Restore the register values saved from s3c_pm_do_save().
+ *
+ * Note, we do not use S3C_PMDBG() in here, as the system may not have
+ * restore the UARTs state yet
+*/
+
+void s3c_pm_do_restore(struct sleep_save *ptr, int count)
+{
+        for (; count > 0; count--, ptr++) {
+                printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
+                       ptr->reg, ptr->val, __raw_readl(ptr->reg));
+
+                __raw_writel(ptr->val, ptr->reg);
+        }
+}
+
+/**
+ * s3c_pm_do_restore_core() - early restore register values from save list.
+ *
+ * This is similar to s3c_pm_do_restore() except we try and minimise the
+ * side effects of the function in case registers that hardware might need
+ * to work has been restored.
+ *
+ * WARNING: Do not put any debug in here that may effect memory or use
+ * peripherals, as things may be changing!
+*/
+
+void s3c_pm_do_restore_core(struct sleep_save *ptr, int count)
+{
+        for (; count > 0; count--, ptr++)
+                __raw_writel(ptr->val, ptr->reg);
+}
+
+/* s3c2410_pm_show_resume_irqs
+ *
+ * print any IRQs asserted at resume time (ie, we woke from)
+*/
+static void s3c_pm_show_resume_irqs(int start, unsigned long which,
+                                    unsigned long mask)
+{
+        int i;
+
+        which &= ~mask;
+
+        for (i = 0; i <= 31; i++) {
+                if (which & (1L<<i)) {
+                        S3C_PMDBG("IRQ %d asserted at resume\n", start+i);
+                }
+        }
+}
+
+
+void (*pm_cpu_prep)(void);
+void (*pm_cpu_sleep)(void);
+
+#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
+
+/* s3c_pm_enter
+ *
+ * central control for sleep/resume process
+*/
+
+static int s3c_pm_enter(suspend_state_t state)
+{
+        static unsigned long regs_save[16];
+
+        /* ensure the debug is initialised (if enabled) */
+
+        s3c_pm_debug_init();
+
+        S3C_PMDBG("%s(%d)\n", __func__, state);
+
+        if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
+                printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
+                return -EINVAL;
+        }
+
+        /* check if we have anything to wake-up with... bad things seem
+         * to happen if you suspend with no wakeup (system will often
+         * require a full power-cycle)
+        */
+
+        if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
+            !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
+                printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
+                printk(KERN_ERR "%s: Aborting sleep\n", __func__);
+                return -EINVAL;
+        }
+
+        /* store the physical address of the register recovery block */
+
+        s3c_sleep_save_phys = virt_to_phys(regs_save);
+
+        S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);
+
+        /* save all necessary core registers not covered by the drivers */
+
+        s3c_pm_save_gpios();
+        s3c_pm_save_uarts();
+        s3c_pm_save_core();
+
+        /* set the irq configuration for wake */
+
+        s3c_pm_configure_extint();
+
+        S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
+            s3c_irqwake_intmask, s3c_irqwake_eintmask);
+
+        s3c_pm_arch_prepare_irqs();
+
+        /* call cpu specific preparation */
+
+        pm_cpu_prep();
+
+        /* flush cache back to ram */
+
+        flush_cache_all();
+
+        s3c_pm_check_store();
+
+        /* send the cpu to sleep... */
+
+        s3c_pm_arch_stop_clocks();
+
+        /* s3c_cpu_save will also act as our return point from when
+         * we resume as it saves its own register state and restores it
+         * during the resume.  */
+
+        s3c_cpu_save(regs_save);
+
+        /* restore the cpu state using the kernel's cpu init code. */
+
+        cpu_init();
+
+        /* restore the system state */
+
+        s3c_pm_restore_core();
+        s3c_pm_restore_uarts();
+        s3c_pm_restore_gpios();
+
+        s3c_pm_debug_init();
+
+        /* check what irq (if any) restored the system */
+
+        s3c_pm_arch_show_resume_irqs();
+
+        S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);
+
+        s3c_pm_check_restore();
+
+        /* ok, let's return from sleep */
+
+        S3C_PMDBG("S3C PM Resume (post-restore)\n");
+        return 0;
+}
+
+/* callback from assembly code */
+void s3c_pm_cb_flushcache(void)
+{
+        flush_cache_all();
+}
+
+static int s3c_pm_prepare(void)
+{
+        /* prepare check area if configured */
+
+        s3c_pm_check_prepare();
+        return 0;
+}
+
+static void s3c_pm_finish(void)
+{
+        s3c_pm_check_cleanup();
+}
+
+static struct platform_suspend_ops s3c_pm_ops = {
+        .enter          = s3c_pm_enter,
+        .prepare        = s3c_pm_prepare,
+        .finish         = s3c_pm_finish,
+        .valid          = suspend_valid_only_mem,
+};
+
+/* s3c_pm_init
+ *
+ * Attach the power management functions. This should be called
+ * from the board specific initialisation if the board supports
+ * it.
+*/
+
+int __init s3c_pm_init(void)
+{
+        printk("S3C Power Management, Copyright 2004 Simtec Electronics\n");
+
+        suspend_set_ops(&s3c_pm_ops);
+        return 0;
+}
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index 1e0767b266b8..636cb12711df 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_CPU_S3C244X)	+= s3c244x-irq.o
 obj-$(CONFIG_CPU_S3C244X)       += s3c244x-clock.o
 obj-$(CONFIG_PM_SIMTEC)         += pm-simtec.o
 obj-$(CONFIG_PM)                += pm.o
+obj-$(CONFIG_PM)                += irq-pm.o
 obj-$(CONFIG_PM)                += sleep.o
 obj-$(CONFIG_HAVE_PWM)          += pwm.o
 obj-$(CONFIG_S3C2410_CLOCK)     += s3c2410-clock.o
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
index 3d4837021ac7..1a8347cec20a 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -201,5 +201,5 @@ void __init smdk_machine_init(void)
 
         platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs));
 
-        s3c2410_pm_init();
+        s3c_pm_init();
 }
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 542062f8cbc1..1932b7e0da15 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -182,7 +182,7 @@ static unsigned long s3c24xx_read_idcode_v4(void)
  * with the caches enabled. It seems at least the S3C2440 has a problem
  * resetting if there is bus activity interrupted by the reset.
  */
-static void s3c24xx_pm_restart(char mode)
+static void s3c24xx_pm_restart(char mode, const char *cmd)
 {
         if (mode != 's') {
                 unsigned long flags;
@@ -191,12 +191,12 @@ static void s3c24xx_pm_restart(char mode)
                 __cpuc_flush_kern_all();
                 __cpuc_flush_user_all();
 
-                arch_reset(mode);
+                arch_reset(mode, cmd);
                 local_irq_restore(flags);
         }
 
         /* fallback, or unhandled */
-        arm_machine_restart(mode);
+        arm_machine_restart(mode, cmd);
 }
 
 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
diff --git a/arch/arm/plat-s3c24xx/include/plat/irq.h b/arch/arm/plat-s3c24xx/include/plat/irq.h
index 45746a995343..69e1be8bec35 100644
--- a/arch/arm/plat-s3c24xx/include/plat/irq.h
+++ b/arch/arm/plat-s3c24xx/include/plat/irq.h
@@ -10,6 +10,12 @@
  * published by the Free Software Foundation.
 */
 
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
+
 #define irqdbf(x...)
 #define irqdbf2(x...)
 
diff --git a/arch/arm/plat-s3c24xx/include/plat/map.h b/arch/arm/plat-s3c24xx/include/plat/map.h
index fef8ea8b8e1e..eed8f78e7593 100644
--- a/arch/arm/plat-s3c24xx/include/plat/map.h
+++ b/arch/arm/plat-s3c24xx/include/plat/map.h
@@ -31,6 +31,8 @@
 #define S3C24XX_SZ_UART    SZ_1M
 #define S3C_UART_OFFSET    (0x4000)
 
+#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET)))
+
 /* Timers */
 #define S3C24XX_VA_TIMER   S3C_VA_TIMER
 #define S3C2410_PA_TIMER   (0x51000000)
diff --git a/arch/arm/plat-s3c24xx/include/plat/pm-core.h b/arch/arm/plat-s3c24xx/include/plat/pm-core.h
new file mode 100644
index 000000000000..c75882113e04
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/pm-core.h
@@ -0,0 +1,59 @@
+/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h
+ *
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C24xx - PM core support for arch/arm/plat-s3c/pm.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+static inline void s3c_pm_debug_init_uart(void)
+{
+        unsigned long tmp = __raw_readl(S3C2410_CLKCON);
+
+        /* re-start uart clocks */
+        tmp |= S3C2410_CLKCON_UART0;
+        tmp |= S3C2410_CLKCON_UART1;
+        tmp |= S3C2410_CLKCON_UART2;
+
+        __raw_writel(tmp, S3C2410_CLKCON);
+        udelay(10);
+}
+
+static inline void s3c_pm_arch_prepare_irqs(void)
+{
+        __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
+        __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
+
+        /* ack any outstanding external interrupts before we go to sleep */
+
+        __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
+        __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
+        __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
+
+}
+
+static inline void s3c_pm_arch_stop_clocks(void)
+{
+        __raw_writel(0x00, S3C2410_CLKCON);  /* turn off clocks over sleep */
+}
+
+static void s3c_pm_show_resume_irqs(int start, unsigned long which,
+                                    unsigned long mask);
+
+static inline void s3c_pm_arch_show_resume_irqs(void)
+{
+        S3C_PMDBG("post sleep: IRQs 0x%08x, 0x%08x\n",
+                  __raw_readl(S3C2410_SRCPND),
+                  __raw_readl(S3C2410_EINTPEND));
+
+        s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
+                                s3c_irqwake_intmask);
+
+        s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
+                                s3c_irqwake_eintmask);
+}
diff --git a/arch/arm/plat-s3c24xx/include/plat/pm.h b/arch/arm/plat-s3c24xx/include/plat/pm.h
deleted file mode 100644
index cc623667e48a..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/pm.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/pm.h
- *
- * Copyright (c) 2004 Simtec Electronics
- *      Written by Ben Dooks, <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* s3c2410_pm_init
- *
- * called from board at initialisation time to setup the power
- * management
-*/
-
-#ifdef CONFIG_PM
-
-extern __init int s3c2410_pm_init(void);
-
-#else
-
-static inline int s3c2410_pm_init(void)
-{
-        return 0;
-}
-#endif
-
-/* configuration for the IRQ mask over sleep */
-extern unsigned long s3c_irqwake_intmask;
-extern unsigned long s3c_irqwake_eintmask;
-
-/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */
-extern unsigned long s3c_irqwake_intallow;
-extern unsigned long s3c_irqwake_eintallow;
-
-/* per-cpu sleep functions */
-
-extern void (*pm_cpu_prep)(void);
-extern void (*pm_cpu_sleep)(void);
-
-/* Flags for PM Control */
-
-extern unsigned long s3c_pm_flags;
-
-/* from sleep.S */
-
-extern int  s3c2410_cpu_save(unsigned long *saveblk);
-extern void s3c2410_cpu_suspend(void);
-extern void s3c2410_cpu_resume(void);
-
-extern unsigned long s3c2410_sleep_save_phys;
-
-/* sleep save info */
-
-struct sleep_save {
-        void __iomem    *reg;
-        unsigned long   val;
-};
-
-#define SAVE_ITEM(x) \
-        { .reg = (x) }
-
-extern void s3c2410_pm_do_save(struct sleep_save *ptr, int count);
-extern void s3c2410_pm_do_restore(struct sleep_save *ptr, int count);
-
-#ifdef CONFIG_PM
-extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state);
-extern int s3c24xx_irq_resume(struct sys_device *dev);
-#else
-#define s3c24xx_irq_suspend NULL
-#define s3c24xx_irq_resume  NULL
-#endif
diff --git a/arch/arm/plat-s3c24xx/irq-pm.c b/arch/arm/plat-s3c24xx/irq-pm.c
new file mode 100644
index 000000000000..b7acf1a8ecd2
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/irq-pm.c
@@ -0,0 +1,95 @@
+/* linux/arch/arm/plat-s3c24xx/irq-om.c
+ *
+ * Copyright (c) 2003,2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C24XX - IRQ PM code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/sysdev.h>
+
+#include <plat/cpu.h>
+#include <plat/pm.h>
+#include <plat/irq.h>
+
+/* state for IRQs over sleep */
+
+/* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
+ *
+ * set bit to 1 in allow bitfield to enable the wakeup settings on it
+*/
+
+unsigned long s3c_irqwake_intallow      = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
+unsigned long s3c_irqwake_eintallow     = 0x0000fff0L;
+
+int s3c_irq_wake(unsigned int irqno, unsigned int state)
+{
+        unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
+
+        if (!(s3c_irqwake_intallow & irqbit))
+                return -ENOENT;
+
+        printk(KERN_INFO "wake %s for irq %d\n",
+               state ? "enabled" : "disabled", irqno);
+
+        if (!state)
+                s3c_irqwake_intmask |= irqbit;
+        else
+                s3c_irqwake_intmask &= ~irqbit;
+
+        return 0;
+}
+
+static struct sleep_save irq_save[] = {
+        SAVE_ITEM(S3C2410_INTMSK),
+        SAVE_ITEM(S3C2410_INTSUBMSK),
+};
+
+/* the extint values move between the s3c2410/s3c2440 and the s3c2412
+ * so we use an array to hold them, and to calculate the address of
+ * the register at run-time
+*/
+
+static unsigned long save_extint[3];
+static unsigned long save_eintflt[4];
+static unsigned long save_eintmask;
+
+int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
+{
+        unsigned int i;
+
+        for (i = 0; i < ARRAY_SIZE(save_extint); i++)
+                save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4));
+
+        for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
+                save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4));
+
+        s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
+        save_eintmask = __raw_readl(S3C24XX_EINTMASK);
+
+        return 0;
+}
+
+int s3c24xx_irq_resume(struct sys_device *dev)
+{
+        unsigned int i;
+
+        for (i = 0; i < ARRAY_SIZE(save_extint); i++)
+                __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4));
+
+        for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
+                __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4));
+
+        s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
+        __raw_writel(save_eintmask, S3C24XX_EINTMASK);
+
+        return 0;
+}
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index 0192ecdc1442..958737775ad2 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/irq.c
  *
- * Copyright (c) 2003,2004 Simtec Electronics
+ * Copyright (c) 2003,2004 Simtec Electronics 
  *      Ben Dooks <ben@simtec.co.uk>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -16,38 +16,6 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- * Changelog:
- *
- *   22-Jul-2004  Ben Dooks <ben@simtec.co.uk>
- *                Fixed compile warnings
- *
- *   22-Jul-2004  Roc Wu <cooloney@yahoo.com.cn>
- *                Fixed s3c_extirq_type
- *
- *   21-Jul-2004  Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
- *                Addition of ADC/TC demux
- *
- *   04-Oct-2004  Klaus Fetscher <k.fetscher@fetron.de>
- *                Fix for set_irq_type() on low EINT numbers
- *
- *   05-Oct-2004  Ben Dooks <ben@simtec.co.uk>
- *                Tidy up KF's patch and sort out new release
- *
- *   05-Oct-2004  Ben Dooks <ben@simtec.co.uk>
- *                Add support for power management controls
- *
- *   04-Nov-2004  Ben Dooks
- *                Fix standard IRQ wake for EINT0..4 and RTC
- *
- *   22-Feb-2005  Ben Dooks
- *                Fixed edge-triggering on ADC IRQ
- *
- *   28-Jun-2005  Ben Dooks
- *                Mark IRQ_LCD valid
- *
- *   25-Jul-2005  Ben Dooks
- *                Split the S3C2440 IRQ code to separate file
 */
 
 #include <linux/init.h>
@@ -55,81 +23,16 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/sysdev.h>
-#include <linux/io.h>
 
-#include <mach/hardware.h>
 #include <asm/irq.h>
-
 #include <asm/mach/irq.h>
 
 #include <plat/regs-irqtype.h>
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
 #include <plat/irq.h>
 
-/* wakeup irq control */
-
-#ifdef CONFIG_PM
-
-/* state for IRQs over sleep */
-
-/* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
- *
- * set bit to 1 in allow bitfield to enable the wakeup settings on it
-*/
-
-unsigned long s3c_irqwake_intallow      = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
-unsigned long s3c_irqwake_intmask       = 0xffffffffL;
-unsigned long s3c_irqwake_eintallow     = 0x0000fff0L;
-unsigned long s3c_irqwake_eintmask      = 0xffffffffL;
-
-int
-s3c_irq_wake(unsigned int irqno, unsigned int state)
-{
-        unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
-
-        if (!(s3c_irqwake_intallow & irqbit))
-                return -ENOENT;
-
-        printk(KERN_INFO "wake %s for irq %d\n",
-               state ? "enabled" : "disabled", irqno);
-
-        if (!state)
-                s3c_irqwake_intmask |= irqbit;
-        else
-                s3c_irqwake_intmask &= ~irqbit;
-
-        return 0;
-}
-
-static int
-s3c_irqext_wake(unsigned int irqno, unsigned int state)
-{
-        unsigned long bit = 1L << (irqno - EXTINT_OFF);
-
-        if (!(s3c_irqwake_eintallow & bit))
-                return -ENOENT;
-
-        printk(KERN_INFO "wake %s for irq %d\n",
-               state ? "enabled" : "disabled", irqno);
-
-        if (!state)
-                s3c_irqwake_eintmask |= bit;
-        else
-                s3c_irqwake_eintmask &= ~bit;
-
-        return 0;
-}
-
-#else
-#define s3c_irqext_wake NULL
-#define s3c_irq_wake NULL
-#endif
-
-
 static void
 s3c_irq_mask(unsigned int irqno)
 {
@@ -590,59 +493,6 @@ s3c_irq_demux_extint4t7(unsigned int irq,
         }
 }
 
-#ifdef CONFIG_PM
-
-static struct sleep_save irq_save[] = {
-        SAVE_ITEM(S3C2410_INTMSK),
-        SAVE_ITEM(S3C2410_INTSUBMSK),
-};
-
-/* the extint values move between the s3c2410/s3c2440 and the s3c2412
- * so we use an array to hold them, and to calculate the address of
- * the register at run-time
-*/
-
-static unsigned long save_extint[3];
-static unsigned long save_eintflt[4];
-static unsigned long save_eintmask;
-
-int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
-{
-        unsigned int i;
-
-        for (i = 0; i < ARRAY_SIZE(save_extint); i++)
-                save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4));
-
-        for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
-                save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4));
-
-        s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
-        save_eintmask = __raw_readl(S3C24XX_EINTMASK);
-
-        return 0;
-}
-
-int s3c24xx_irq_resume(struct sys_device *dev)
-{
-        unsigned int i;
-
-        for (i = 0; i < ARRAY_SIZE(save_extint); i++)
-                __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4));
-
-        for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
-                __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4));
-
-        s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
-        __raw_writel(save_eintmask, S3C24XX_EINTMASK);
-
-        return 0;
-}
-
-#else
-#define s3c24xx_irq_suspend NULL
-#define s3c24xx_irq_resume  NULL
-#endif
-
 /* s3c24xx_init_irq
  *
  * Initialise S3C2410 IRQ system
diff --git a/arch/arm/plat-s3c24xx/pm-simtec.c b/arch/arm/plat-s3c24xx/pm-simtec.c
index 21dfa74773d1..da0d3217d3e3 100644
--- a/arch/arm/plat-s3c24xx/pm-simtec.c
+++ b/arch/arm/plat-s3c24xx/pm-simtec.c
@@ -61,7 +61,7 @@ static __init int pm_simtec_init(void)
 
         __raw_writel(gstatus4, S3C2410_GSTATUS4);
 
-        return s3c2410_pm_init();
+        return s3c_pm_init();
 }
 
 arch_initcall(pm_simtec_init);
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
index 34ef18e5b2a1..062a29339a91 100644
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -31,14 +31,9 @@
 #include <linux/errno.h>
 #include <linux/time.h>
 #include <linux/interrupt.h>
-#include <linux/crc32.h>
-#include <linux/ioport.h>
 #include <linux/serial_core.h>
 #include <linux/io.h>
 
-#include <asm/cacheflush.h>
-#include <mach/hardware.h>
-
 #include <plat/regs-serial.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
@@ -49,10 +44,6 @@
 
 #include <plat/pm.h>
 
-/* for external use */
-
-unsigned long s3c_pm_flags;
-
 #define PFX "s3c24xx-pm: "
 
 static struct sleep_save core_save[] = {
@@ -120,328 +111,14 @@ static struct sleep_save misc_save[] = {
         SAVE_ITEM(S3C2410_DCLKCON),
 };
 
-#ifdef CONFIG_S3C2410_PM_DEBUG
-
-#define SAVE_UART(va) \
-        SAVE_ITEM((va) + S3C2410_ULCON), \
-        SAVE_ITEM((va) + S3C2410_UCON), \
-        SAVE_ITEM((va) + S3C2410_UFCON), \
-        SAVE_ITEM((va) + S3C2410_UMCON), \
-        SAVE_ITEM((va) + S3C2410_UBRDIV)
-
-static struct sleep_save uart_save[] = {
-        SAVE_UART(S3C24XX_VA_UART0),
-        SAVE_UART(S3C24XX_VA_UART1),
-#ifndef CONFIG_CPU_S3C2400
-        SAVE_UART(S3C24XX_VA_UART2),
-#endif
-};
-
-/* debug
- *
- * we send the debug to printascii() to allow it to be seen if the
- * system never wakes up from the sleep
-*/
-
-extern void printascii(const char *);
-
-void pm_dbg(const char *fmt, ...)
-{
-        va_list va;
-        char buff[256];
-
-        va_start(va, fmt);
-        vsprintf(buff, fmt, va);
-        va_end(va);
-
-        printascii(buff);
-}
-
-static void s3c2410_pm_debug_init(void)
-{
-        unsigned long tmp = __raw_readl(S3C2410_CLKCON);
-
-        /* re-start uart clocks */
-        tmp |= S3C2410_CLKCON_UART0;
-        tmp |= S3C2410_CLKCON_UART1;
-        tmp |= S3C2410_CLKCON_UART2;
-
-        __raw_writel(tmp, S3C2410_CLKCON);
-        udelay(10);
-}
-
-#define DBG(fmt...) pm_dbg(fmt)
-#else
-#define DBG(fmt...) printk(KERN_DEBUG fmt)
-
-#define s3c2410_pm_debug_init() do { } while(0)
-
-static struct sleep_save uart_save[] = {};
-#endif
-
-#if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0
-
-/* suspend checking code...
- *
- * this next area does a set of crc checks over all the installed
- * memory, so the system can verify if the resume was ok.
- *
- * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
- * increasing it will mean that the area corrupted will be less easy to spot,
- * and reducing the size will cause the CRC save area to grow
-*/
-
-#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024)
-
-static u32 crc_size;    /* size needed for the crc block */
-static u32 *crcs;       /* allocated over suspend/resume */
-
-typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);
-
-/* s3c2410_pm_run_res
- *
- * go thorugh the given resource list, and look for system ram
-*/
-
-static void s3c2410_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
-{
-        while (ptr != NULL) {
-                if (ptr->child != NULL)
-                        s3c2410_pm_run_res(ptr->child, fn, arg);
-
-                if ((ptr->flags & IORESOURCE_MEM) &&
-                    strcmp(ptr->name, "System RAM") == 0) {
-                        DBG("Found system RAM at %08lx..%08lx\n",
-                            ptr->start, ptr->end);
-                        arg = (fn)(ptr, arg);
-                }
-
-                ptr = ptr->sibling;
-        }
-}
-
-static void s3c2410_pm_run_sysram(run_fn_t fn, u32 *arg)
-{
-        s3c2410_pm_run_res(&iomem_resource, fn, arg);
-}
-
-static u32 *s3c2410_pm_countram(struct resource *res, u32 *val)
-{
-        u32 size = (u32)(res->end - res->start)+1;
-
-        size += CHECK_CHUNKSIZE-1;
-        size /= CHECK_CHUNKSIZE;
-
-        DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size);
-
-        *val += size * sizeof(u32);
-        return val;
-}
-
-/* s3c2410_pm_prepare_check
- *
- * prepare the necessary information for creating the CRCs. This
- * must be done before the final save, as it will require memory
- * allocating, and thus touching bits of the kernel we do not
- * know about.
-*/
-
-static void s3c2410_pm_check_prepare(void)
-{
-        crc_size = 0;
-
-        s3c2410_pm_run_sysram(s3c2410_pm_countram, &crc_size);
-
-        DBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size);
-
-        crcs = kmalloc(crc_size+4, GFP_KERNEL);
-        if (crcs == NULL)
-                printk(KERN_ERR "Cannot allocated CRC save area\n");
-}
-
-static u32 *s3c2410_pm_makecheck(struct resource *res, u32 *val)
-{
-        unsigned long addr, left;
-
-        for (addr = res->start; addr < res->end;
-             addr += CHECK_CHUNKSIZE) {
-                left = res->end - addr;
-
-                if (left > CHECK_CHUNKSIZE)
-                        left = CHECK_CHUNKSIZE;
-
-                *val = crc32_le(~0, phys_to_virt(addr), left);
-                val++;
-        }
-
-        return val;
-}
-
-/* s3c2410_pm_check_store
- *
- * compute the CRC values for the memory blocks before the final
- * sleep.
-*/
-
-static void s3c2410_pm_check_store(void)
-{
-        if (crcs != NULL)
-                s3c2410_pm_run_sysram(s3c2410_pm_makecheck, crcs);
-}
-
-/* in_region
- *
- * return TRUE if the area defined by ptr..ptr+size contatins the
- * what..what+whatsz
-*/
-
-static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
-{
-        if ((what+whatsz) < ptr)
-                return 0;
-
-        if (what > (ptr+size))
-                return 0;
-
-        return 1;
-}
-
-static u32 *s3c2410_pm_runcheck(struct resource *res, u32 *val)
-{
-        void *save_at = phys_to_virt(s3c2410_sleep_save_phys);
-        unsigned long addr;
-        unsigned long left;
-        void *ptr;
-        u32 calc;
-
-        for (addr = res->start; addr < res->end;
-             addr += CHECK_CHUNKSIZE) {
-                left = res->end - addr;
-
-                if (left > CHECK_CHUNKSIZE)
-                        left = CHECK_CHUNKSIZE;
-
-                ptr = phys_to_virt(addr);
-
-                if (in_region(ptr, left, crcs, crc_size)) {
-                        DBG("skipping %08lx, has crc block in\n", addr);
-                        goto skip_check;
-                }
-
-                if (in_region(ptr, left, save_at, 32*4 )) {
-                        DBG("skipping %08lx, has save block in\n", addr);
-                        goto skip_check;
-                }
-
-                /* calculate and check the checksum */
-
-                calc = crc32_le(~0, ptr, left);
-                if (calc != *val) {
-                        printk(KERN_ERR PFX "Restore CRC error at "
-                               "%08lx (%08x vs %08x)\n", addr, calc, *val);
-
-                        DBG("Restore CRC error at %08lx (%08x vs %08x)\n",
-                            addr, calc, *val);
-                }
-
-        skip_check:
-                val++;
-        }
-
-        return val;
-}
-
-/* s3c2410_pm_check_restore
- *
- * check the CRCs after the restore event and free the memory used
- * to hold them
-*/
-
-static void s3c2410_pm_check_restore(void)
-{
-        if (crcs != NULL) {
-                s3c2410_pm_run_sysram(s3c2410_pm_runcheck, crcs);
-                kfree(crcs);
-                crcs = NULL;
-        }
-}
-
-#else
-
-#define s3c2410_pm_check_prepare() do { } while(0)
-#define s3c2410_pm_check_restore() do { } while(0)
-#define s3c2410_pm_check_store()   do { } while(0)
-#endif
-
-/* helper functions to save and restore register state */
-
-void s3c2410_pm_do_save(struct sleep_save *ptr, int count)
-{
-        for (; count > 0; count--, ptr++) {
-                ptr->val = __raw_readl(ptr->reg);
-                DBG("saved %p value %08lx\n", ptr->reg, ptr->val);
-        }
-}
-
-/* s3c2410_pm_do_restore
- *
- * restore the system from the given list of saved registers
- *
- * Note, we do not use DBG() in here, as the system may not have
- * restore the UARTs state yet
-*/
-
-void s3c2410_pm_do_restore(struct sleep_save *ptr, int count)
-{
-        for (; count > 0; count--, ptr++) {
-                printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
-                       ptr->reg, ptr->val, __raw_readl(ptr->reg));
-
-                __raw_writel(ptr->val, ptr->reg);
-        }
-}
-
-/* s3c2410_pm_do_restore_core
- *
- * similar to s3c2410_pm_do_restore_core
- *
- * WARNING: Do not put any debug in here that may effect memory or use
- * peripherals, as things may be changing!
-*/
-
-static void s3c2410_pm_do_restore_core(struct sleep_save *ptr, int count)
-{
-        for (; count > 0; count--, ptr++) {
-                __raw_writel(ptr->val, ptr->reg);
-        }
-}
 
-/* s3c2410_pm_show_resume_irqs
- *
- * print any IRQs asserted at resume time (ie, we woke from)
-*/
-
-static void s3c2410_pm_show_resume_irqs(int start, unsigned long which,
-                                        unsigned long mask)
-{
-        int i;
-
-        which &= ~mask;
-
-        for (i = 0; i <= 31; i++) {
-                if ((which) & (1L<<i)) {
-                        DBG("IRQ %d asserted at resume\n", start+i);
-                }
-        }
-}
-
-/* s3c2410_pm_check_resume_pin
+/* s3c_pm_check_resume_pin
  *
  * check to see if the pin is configured correctly for sleep mode, and
  * make any necessary adjustments if it is not
 */
 
-static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
+static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
 {
         unsigned long irqstate;
         unsigned long pinstate;
@@ -456,21 +133,21 @@ static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
 
         if (!irqstate) {
                 if (pinstate == S3C2410_GPIO_IRQ)
-                        DBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
+                        S3C_PMDBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
         } else {
                 if (pinstate == S3C2410_GPIO_IRQ) {
-                        DBG("Disabling IRQ %d (pin %d)\n", irq, pin);
+                        S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin);
                         s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
                 }
         }
 }
 
-/* s3c2410_pm_configure_extint
+/* s3c_pm_configure_extint
  *
  * configure all external interrupt pins
 */
 
-static void s3c2410_pm_configure_extint(void)
+void s3c_pm_configure_extint(void)
 {
         int pin;
 
@@ -480,11 +157,11 @@ static void s3c2410_pm_configure_extint(void)
         */
 
         for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) {
-                s3c2410_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
+                s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
         }
 
         for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
-                s3c2410_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
+                s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
         }
 }
 
@@ -494,12 +171,12 @@ static void s3c2410_pm_configure_extint(void)
 #define OFFS_DAT        (S3C2410_GPADAT - S3C2410_GPACON)
 #define OFFS_UP         (S3C2410_GPBUP  - S3C2410_GPBCON)
 
-/* s3c2410_pm_save_gpios()
+/* s3c_pm_save_gpios()
  *
  * Save the state of the GPIOs
  */
 
-static void s3c2410_pm_save_gpios(void)
+void s3c_pm_save_gpios(void)
 {
         struct gpio_sleep *gps = gpio_save;
         unsigned int gpio;
@@ -538,7 +215,10 @@ static inline int is_out(unsigned long con)
         return con == 1;
 }
 
-/* s3c2410_pm_restore_gpio()
+/**
+ * s3c2410_pm_restore_gpio() - restore the given GPIO bank
+ * @index: The number of the GPIO bank being resumed.
+ * @gps: The sleep confgiuration for the bank.
  *
  * Restore one of the GPIO banks that was saved during suspend. This is
  * not as simple as once thought, due to the possibility of glitches
@@ -646,8 +326,8 @@ static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps)
                 __raw_writel(gps->gpup, base + OFFS_UP);
         }
 
-        DBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n",
-            index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
+        S3C_PMDBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n",
+                  index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
 }
 
 
@@ -656,7 +336,7 @@ static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps)
  * Restore the state of the GPIOs
  */
 
-static void s3c2410_pm_restore_gpios(void)
+void s3c_pm_restore_gpios(void)
 {
         struct gpio_sleep *gps = gpio_save;
         int gpio;
@@ -666,150 +346,15 @@ static void s3c2410_pm_restore_gpios(void)
         }
 }
 
-void (*pm_cpu_prep)(void);
-void (*pm_cpu_sleep)(void);
-
-#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
-
-/* s3c2410_pm_enter
- *
- * central control for sleep/resume process
-*/
-
-static int s3c2410_pm_enter(suspend_state_t state)
+void s3c_pm_restore_core(void)
 {
-        unsigned long regs_save[16];
-
-        /* ensure the debug is initialised (if enabled) */
-
-        s3c2410_pm_debug_init();
-
-        DBG("s3c2410_pm_enter(%d)\n", state);
-
-        if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
-                printk(KERN_ERR PFX "error: no cpu sleep functions set\n");
-                return -EINVAL;
-        }
-
-        /* check if we have anything to wake-up with... bad things seem
-         * to happen if you suspend with no wakeup (system will often
-         * require a full power-cycle)
-        */
-
-        if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
-            !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
-                printk(KERN_ERR PFX "No sources enabled for wake-up!\n");
-                printk(KERN_ERR PFX "Aborting sleep\n");
-                return -EINVAL;
-        }
-
-        /* prepare check area if configured */
-
-        s3c2410_pm_check_prepare();
-
-        /* store the physical address of the register recovery block */
-
-        s3c2410_sleep_save_phys = virt_to_phys(regs_save);
-
-        DBG("s3c2410_sleep_save_phys=0x%08lx\n", s3c2410_sleep_save_phys);
-
-        /* save all necessary core registers not covered by the drivers */
-
-        s3c2410_pm_save_gpios();
-        s3c2410_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
-        s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save));
-        s3c2410_pm_do_save(uart_save, ARRAY_SIZE(uart_save));
-
-        /* set the irq configuration for wake */
-
-        s3c2410_pm_configure_extint();
-
-        DBG("sleep: irq wakeup masks: %08lx,%08lx\n",
-            s3c_irqwake_intmask, s3c_irqwake_eintmask);
-
-        __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
-        __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
-
-        /* ack any outstanding external interrupts before we go to sleep */
-
-        __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
-        __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
-        __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
-
-        /* call cpu specific preparation */
-
-        pm_cpu_prep();
-
-        /* flush cache back to ram */
-
-        flush_cache_all();
-
-        s3c2410_pm_check_store();
-
-        /* send the cpu to sleep... */
-
-        __raw_writel(0x00, S3C2410_CLKCON);  /* turn off clocks over sleep */
-
-        /* s3c2410_cpu_save will also act as our return point from when
-         * we resume as it saves its own register state, so use the return
-         * code to differentiate return from save and return from sleep */
-
-        if (s3c2410_cpu_save(regs_save) == 0) {
-                flush_cache_all();
-                pm_cpu_sleep();
-        }
-
-        /* restore the cpu state */
-
-        cpu_init();
-
-        /* restore the system state */
-
-        s3c2410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
-        s3c2410_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
-        s3c2410_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
-        s3c2410_pm_restore_gpios();
-
-        s3c2410_pm_debug_init();
-
-        /* check what irq (if any) restored the system */
-
-        DBG("post sleep: IRQs 0x%08x, 0x%08x\n",
-            __raw_readl(S3C2410_SRCPND),
-            __raw_readl(S3C2410_EINTPEND));
-
-        s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
-                                    s3c_irqwake_intmask);
-
-        s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
-                                    s3c_irqwake_eintmask);
-
-        DBG("post sleep, preparing to return\n");
-
-        s3c2410_pm_check_restore();
-
-        /* ok, let's return from sleep */
-
-        DBG("S3C2410 PM Resume (post-restore)\n");
-        return 0;
+        s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
+        s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
 }
 
-static struct platform_suspend_ops s3c2410_pm_ops = {
-        .enter          = s3c2410_pm_enter,
-        .valid          = suspend_valid_only_mem,
-};
-
-/* s3c2410_pm_init
- *
- * Attach the power management functions. This should be called
- * from the board specific initialisation if the board supports
- * it.
-*/
-
-int __init s3c2410_pm_init(void)
+void s3c_pm_save_core(void)
 {
-        printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n");
-
-        suspend_set_ops(&s3c2410_pm_ops);
-        return 0;
+        s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
+        s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
 }
+
diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c
index c1de6bb0101b..1364317d421e 100644
--- a/arch/arm/plat-s3c24xx/s3c244x.c
+++ b/arch/arm/plat-s3c24xx/s3c244x.c
@@ -145,13 +145,13 @@ static struct sleep_save s3c244x_sleep[] = {
 
 static int s3c244x_suspend(struct sys_device *dev, pm_message_t state)
 {
-        s3c2410_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
+        s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
         return 0;
 }
 
 static int s3c244x_resume(struct sys_device *dev)
 {
-        s3c2410_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
+        s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
         return 0;
 }
 
diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S
index 76594b212802..e73e3b6e88d2 100644
--- a/arch/arm/plat-s3c24xx/sleep.S
+++ b/arch/arm/plat-s3c24xx/sleep.S
@@ -41,25 +41,13 @@
 
         .text
 
-        /* s3c2410_cpu_save
-         *
-         * save enough of the CPU state to allow us to re-start
-         * pm.c code. as we store items like the sp/lr, we will
-         * end up returning from this function when the cpu resumes
-         * so the return value is set to mark this.
-         *
-         * This arangement means we avoid having to flush the cache
-         * from this code.
+        /* s3c_cpu_save
          *
          * entry:
-         *      r0 = pointer to save block
-         *
-         * exit:
-         *      r0 = 0 => we stored everything
-         *           1 => resumed from sleep
+         *      r0 = save address (virtual addr of s3c_sleep_save_phys)
         */
 
-ENTRY(s3c2410_cpu_save)
+ENTRY(s3c_cpu_save)
         stmfd   sp!, { r4 - r12, lr }
 
         @@ store co-processor registers
@@ -71,20 +59,25 @@ ENTRY(s3c2410_cpu_save)
 
         stmia   r0, { r4 - r13 }
 
-        mov     r0, #0
-        ldmfd   sp, { r4 - r12, pc }
+        @@ write our state back to RAM
+        bl      s3c_pm_cb_flushcache
 
+        @@ jump to final code to send system to sleep
+        ldr     r0, =pm_cpu_sleep
+        @@ldr   pc, [ r0 ]
+        ldr     r0, [ r0 ]
+        mov     pc, r0
+        
         @@ return to the caller, after having the MMU
         @@ turned on, this restores the last bits from the
         @@ stack
 resume_with_mmu:
-        mov     r0, #1
         ldmfd   sp!, { r4 - r12, pc }
 
         .ltorg
 
         @@ the next bits sit in the .data segment, even though they
-        @@ happen to be code... the s3c2410_sleep_save_phys needs to be
+        @@ happen to be code... the s3c_sleep_save_phys needs to be
         @@ accessed by the resume code before it can restore the MMU.
         @@ This means that the variable has to be close enough for the
         @@ code to read it... since the .text segment needs to be RO,
@@ -92,19 +85,19 @@ resume_with_mmu:
 
         .data
 
-        .global s3c2410_sleep_save_phys
-s3c2410_sleep_save_phys:
+        .global s3c_sleep_save_phys
+s3c_sleep_save_phys:
         .word   0
 
 
         /* sleep magic, to allow the bootloader to check for an valid
          * image to resume to. Must be the first word before the
-         * s3c2410_cpu_resume entry.
+         * s3c_cpu_resume entry.
         */
 
         .word   0x2bedf00d
 
-        /* s3c2410_cpu_resume
+        /* s3c_cpu_resume
          *
          * resume code entry for bootloader to call
          *
@@ -113,7 +106,7 @@ s3c2410_sleep_save_phys:
          * must not write to the code segment (code is read-only)
         */
 
-ENTRY(s3c2410_cpu_resume)
+ENTRY(s3c_cpu_resume)
         mov     r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
         msr     cpsr_c, r0
 
@@ -145,7 +138,7 @@ ENTRY(s3c2410_cpu_resume)
         mcr     p15, 0, r1, c8, c7, 0           @@ invalidate I & D TLBs
         mcr     p15, 0, r1, c7, c7, 0           @@ invalidate I & D caches
 
-        ldr     r0, s3c2410_sleep_save_phys     @ address of restore block
+        ldr     r0, s3c_sleep_save_phys         @ address of restore block
         ldmia   r0, { r4 - r13 }
 
         mcr     p15, 0, r4, c13, c0, 0          @ PID
diff --git a/arch/arm/plat-s3c64xx/cpu.c b/arch/arm/plat-s3c64xx/cpu.c
index fbde183a4560..91f49a3a665d 100644
--- a/arch/arm/plat-s3c64xx/cpu.c
+++ b/arch/arm/plat-s3c64xx/cpu.c
@@ -96,6 +96,11 @@ static struct map_desc s3c_iodesc[] __initdata = {
                 .pfn            = __phys_to_pfn(S3C64XX_PA_GPIO),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C64XX_VA_MODEM,
+                .pfn            = __phys_to_pfn(S3C64XX_PA_MODEM),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
         },
 };
 
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h b/arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h
new file mode 100644
index 000000000000..82342f6fd27d
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h
@@ -0,0 +1,25 @@
+/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio-memport.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX - GPIO memory port register definitions
+ */
+
+#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H
+#define __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H __FILE__
+
+#define S3C64XX_MEM0CONSTOP     S3C64XX_GPIOREG(0x1B0)
+#define S3C64XX_MEM1CONSTOP     S3C64XX_GPIOREG(0x1B4)
+
+#define S3C64XX_MEM0CONSLP0     S3C64XX_GPIOREG(0x1C0)
+#define S3C64XX_MEM0CONSLP1     S3C64XX_GPIOREG(0x1C4)
+#define S3C64XX_MEM1CONSLP      S3C64XX_GPIOREG(0x1C8)
+
+#define S3C64XX_MEM0DRVCON      S3C64XX_GPIOREG(0x1D0)
+#define S3C64XX_MEM1DRVCON      S3C64XX_GPIOREG(0x1D4)
+
+#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H */
+
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h
index 75b873d82808..81f7f6e6832e 100644
--- a/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h
@@ -13,23 +13,175 @@
 
 /* Base addresses for each of the banks */
 
-#define S3C64XX_GPA_BASE        (S3C64XX_VA_GPIO + 0x0000)
-#define S3C64XX_GPB_BASE        (S3C64XX_VA_GPIO + 0x0020)
-#define S3C64XX_GPC_BASE        (S3C64XX_VA_GPIO + 0x0040)
-#define S3C64XX_GPD_BASE        (S3C64XX_VA_GPIO + 0x0060)
-#define S3C64XX_GPE_BASE        (S3C64XX_VA_GPIO + 0x0080)
-#define S3C64XX_GPF_BASE        (S3C64XX_VA_GPIO + 0x00A0)
-#define S3C64XX_GPG_BASE        (S3C64XX_VA_GPIO + 0x00C0)
-#define S3C64XX_GPH_BASE        (S3C64XX_VA_GPIO + 0x00E0)
-#define S3C64XX_GPI_BASE        (S3C64XX_VA_GPIO + 0x0100)
-#define S3C64XX_GPJ_BASE        (S3C64XX_VA_GPIO + 0x0120)
-#define S3C64XX_GPK_BASE        (S3C64XX_VA_GPIO + 0x0800)
-#define S3C64XX_GPL_BASE        (S3C64XX_VA_GPIO + 0x0810)
-#define S3C64XX_GPM_BASE        (S3C64XX_VA_GPIO + 0x0820)
-#define S3C64XX_GPN_BASE        (S3C64XX_VA_GPIO + 0x0830)
-#define S3C64XX_GPO_BASE        (S3C64XX_VA_GPIO + 0x0140)
-#define S3C64XX_GPP_BASE        (S3C64XX_VA_GPIO + 0x0160)
-#define S3C64XX_GPQ_BASE        (S3C64XX_VA_GPIO + 0x0180)
+#define S3C64XX_GPIOREG(reg)    (S3C64XX_VA_GPIO + (reg))
+
+#define S3C64XX_GPA_BASE        S3C64XX_GPIOREG(0x0000)
+#define S3C64XX_GPB_BASE        S3C64XX_GPIOREG(0x0020)
+#define S3C64XX_GPC_BASE        S3C64XX_GPIOREG(0x0040)
+#define S3C64XX_GPD_BASE        S3C64XX_GPIOREG(0x0060)
+#define S3C64XX_GPE_BASE        S3C64XX_GPIOREG(0x0080)
+#define S3C64XX_GPF_BASE        S3C64XX_GPIOREG(0x00A0)
+#define S3C64XX_GPG_BASE        S3C64XX_GPIOREG(0x00C0)
+#define S3C64XX_GPH_BASE        S3C64XX_GPIOREG(0x00E0)
+#define S3C64XX_GPI_BASE        S3C64XX_GPIOREG(0x0100)
+#define S3C64XX_GPJ_BASE        S3C64XX_GPIOREG(0x0120)
+#define S3C64XX_GPK_BASE        S3C64XX_GPIOREG(0x0800)
+#define S3C64XX_GPL_BASE        S3C64XX_GPIOREG(0x0810)
+#define S3C64XX_GPM_BASE        S3C64XX_GPIOREG(0x0820)
+#define S3C64XX_GPN_BASE        S3C64XX_GPIOREG(0x0830)
+#define S3C64XX_GPO_BASE        S3C64XX_GPIOREG(0x0140)
+#define S3C64XX_GPP_BASE        S3C64XX_GPIOREG(0x0160)
+#define S3C64XX_GPQ_BASE        S3C64XX_GPIOREG(0x0180)
+
+/* SPCON */
+
+#define S3C64XX_SPCON           S3C64XX_GPIOREG(0x1A0)
+
+#define S3C64XX_SPCON_DRVCON_CAM_MASK           (0x3 << 30)
+#define S3C64XX_SPCON_DRVCON_CAM_SHIFT          (30)
+#define S3C64XX_SPCON_DRVCON_CAM_2mA            (0x0 << 30)
+#define S3C64XX_SPCON_DRVCON_CAM_4mA            (0x1 << 30)
+#define S3C64XX_SPCON_DRVCON_CAM_7mA            (0x2 << 30)
+#define S3C64XX_SPCON_DRVCON_CAM_9mA            (0x3 << 30)
+
+#define S3C64XX_SPCON_DRVCON_HSSPI_MASK         (0x3 << 28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT        (28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_2mA          (0x0 << 28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_4mA          (0x1 << 28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_7mA          (0x2 << 28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_9mA          (0x3 << 28)
+
+#define S3C64XX_SPCON_DRVCON_HSMMC_MASK         (0x3 << 26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT        (26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_2mA          (0x0 << 26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_4mA          (0x1 << 26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_7mA          (0x2 << 26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_9mA          (0x3 << 26)
+
+#define S3C64XX_SPCON_DRVCON_LCD_MASK           (0x3 << 24)
+#define S3C64XX_SPCON_DRVCON_LCD_SHIFT          (24)
+#define S3C64XX_SPCON_DRVCON_LCD_2mA            (0x0 << 24)
+#define S3C64XX_SPCON_DRVCON_LCD_4mA            (0x1 << 24)
+#define S3C64XX_SPCON_DRVCON_LCD_7mA            (0x2 << 24)
+#define S3C64XX_SPCON_DRVCON_LCD_9mA            (0x3 << 24)
+
+#define S3C64XX_SPCON_DRVCON_MODEM_MASK         (0x3 << 22)
+#define S3C64XX_SPCON_DRVCON_MODEM_SHIFT        (22)
+#define S3C64XX_SPCON_DRVCON_MODEM_2mA          (0x0 << 22)
+#define S3C64XX_SPCON_DRVCON_MODEM_4mA          (0x1 << 22)
+#define S3C64XX_SPCON_DRVCON_MODEM_7mA          (0x2 << 22)
+#define S3C64XX_SPCON_DRVCON_MODEM_9mA          (0x3 << 22)
+
+#define S3C64XX_SPCON_nRSTOUT_OEN               (1 << 21)
+
+#define S3C64XX_SPCON_DRVCON_SPICLK1_MASK       (0x3 << 18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT      (18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_2mA        (0x0 << 18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_4mA        (0x1 << 18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_7mA        (0x2 << 18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_9mA        (0x3 << 18)
+
+#define S3C64XX_SPCON_MEM1_DQS_PUD_MASK         (0x3 << 16)
+#define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT        (16)
+#define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED     (0x0 << 16)
+#define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN         (0x1 << 16)
+#define S3C64XX_SPCON_MEM1_DQS_PUD_UP           (0x2 << 16)
+
+#define S3C64XX_SPCON_MEM1_D_PUD1_MASK          (0x3 << 14)
+#define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT         (14)
+#define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED      (0x0 << 14)
+#define S3C64XX_SPCON_MEM1_D_PUD1_DOWN          (0x1 << 14)
+#define S3C64XX_SPCON_MEM1_D_PUD1_UP            (0x2 << 14)
+
+#define S3C64XX_SPCON_MEM1_D_PUD0_MASK          (0x3 << 12)
+#define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT         (12)
+#define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED      (0x0 << 12)
+#define S3C64XX_SPCON_MEM1_D_PUD0_DOWN          (0x1 << 12)
+#define S3C64XX_SPCON_MEM1_D_PUD0_UP            (0x2 << 12)
+
+#define S3C64XX_SPCON_MEM0_D_PUD_MASK           (0x3 << 8)
+#define S3C64XX_SPCON_MEM0_D_PUD_SHIFT          (8)
+#define S3C64XX_SPCON_MEM0_D_PUD_DISABLED       (0x0 << 8)
+#define S3C64XX_SPCON_MEM0_D_PUD_DOWN           (0x1 << 8)
+#define S3C64XX_SPCON_MEM0_D_PUD_UP             (0x2 << 8)
+
+#define S3C64XX_SPCON_USBH_DMPD                 (1 << 7)
+#define S3C64XX_SPCON_USBH_DPPD                 (1 << 6)
+#define S3C64XX_SPCON_USBH_PUSW2                (1 << 5)
+#define S3C64XX_SPCON_USBH_PUSW1                (1 << 4)
+#define S3C64XX_SPCON_USBH_SUSPND               (1 << 3)
+
+#define S3C64XX_SPCON_LCD_SEL_MASK              (0x3 << 0)
+#define S3C64XX_SPCON_LCD_SEL_SHIFT             (0)
+#define S3C64XX_SPCON_LCD_SEL_HOST              (0x0 << 0)
+#define S3C64XX_SPCON_LCD_SEL_RGB               (0x1 << 0)
+#define S3C64XX_SPCON_LCD_SEL_606_656           (0x2 << 0)
+
+
+/* External interrupt registers */
+
+#define S3C64XX_EINT12CON       S3C64XX_GPIOREG(0x200)
+#define S3C64XX_EINT34CON       S3C64XX_GPIOREG(0x204)
+#define S3C64XX_EINT56CON       S3C64XX_GPIOREG(0x208)
+#define S3C64XX_EINT78CON       S3C64XX_GPIOREG(0x20C)
+#define S3C64XX_EINT9CON        S3C64XX_GPIOREG(0x210)
+
+#define S3C64XX_EINT12FLTCON    S3C64XX_GPIOREG(0x220)
+#define S3C64XX_EINT34FLTCON    S3C64XX_GPIOREG(0x224)
+#define S3C64XX_EINT56FLTCON    S3C64XX_GPIOREG(0x228)
+#define S3C64XX_EINT78FLTCON    S3C64XX_GPIOREG(0x22C)
+#define S3C64XX_EINT9FLTCON     S3C64XX_GPIOREG(0x230)
+
+#define S3C64XX_EINT12MASK      S3C64XX_GPIOREG(0x240)
+#define S3C64XX_EINT34MASK      S3C64XX_GPIOREG(0x244)
+#define S3C64XX_EINT56MASK      S3C64XX_GPIOREG(0x248)
+#define S3C64XX_EINT78MASK      S3C64XX_GPIOREG(0x24C)
+#define S3C64XX_EINT9MASK       S3C64XX_GPIOREG(0x250)
+
+#define S3C64XX_EINT12PEND      S3C64XX_GPIOREG(0x260)
+#define S3C64XX_EINT34PEND      S3C64XX_GPIOREG(0x264)
+#define S3C64XX_EINT56PEND      S3C64XX_GPIOREG(0x268)
+#define S3C64XX_EINT78PEND      S3C64XX_GPIOREG(0x26C)
+#define S3C64XX_EINT9PEND       S3C64XX_GPIOREG(0x270)
+
+#define S3C64XX_PRIORITY        S3C64XX_GPIOREG(0x280)
+#define S3C64XX_PRIORITY_ARB(x) (1 << (x))
+
+#define S3C64XX_SERVICE         S3C64XX_GPIOREG(0x284)
+#define S3C64XX_SERVICEPEND     S3C64XX_GPIOREG(0x288)
+
+#define S3C64XX_EINT0CON0       S3C64XX_GPIOREG(0x900)
+#define S3C64XX_EINT0CON1       S3C64XX_GPIOREG(0x904)
+#define S3C64XX_EINT0FLTCON0    S3C64XX_GPIOREG(0x910)
+#define S3C64XX_EINT0FLTCON1    S3C64XX_GPIOREG(0x914)
+#define S3C64XX_EINT0FLTCON2    S3C64XX_GPIOREG(0x918)
+#define S3C64XX_EINT0FLTCON3    S3C64XX_GPIOREG(0x91C)
+
+#define S3C64XX_EINT0MASK       S3C64XX_GPIOREG(0x920)
+#define S3C64XX_EINT0PEND       S3C64XX_GPIOREG(0x924)
+
+/* GPIO sleep configuration */
+
+#define S3C64XX_SPCONSLP        S3C64XX_GPIOREG(0x880)
+
+#define S3C64XX_SPCONSLP_TDO_PULLDOWN   (1 << 14)
+#define S3C64XX_SPCONSLP_CKE1INIT       (1 << 5)
+
+#define S3C64XX_SPCONSLP_RSTOUT_MASK    (0x3 << 12)
+#define S3C64XX_SPCONSLP_RSTOUT_OUT0    (0x0 << 12)
+#define S3C64XX_SPCONSLP_RSTOUT_OUT1    (0x1 << 12)
+#define S3C64XX_SPCONSLP_RSTOUT_HIZ     (0x2 << 12)
+
+#define S3C64XX_SPCONSLP_KPCOL_MASK     (0x3 << 0)
+#define S3C64XX_SPCONSLP_KPCOL_OUT0     (0x0 << 0)
+#define S3C64XX_SPCONSLP_KPCOL_OUT1     (0x1 << 0)
+#define S3C64XX_SPCONSLP_KPCOL_INP      (0x2 << 0)
+
+
+#define S3C64XX_SLPEN           S3C64XX_GPIOREG(0x930)
+
+#define S3C64XX_SLPEN_USE_xSLP          (1 << 0)
+#define S3C64XX_SLPEN_CFG_BYSLPEN       (1 << 1)
 
 #endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */
 
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-modem.h b/arch/arm/plat-s3c64xx/include/plat/regs-modem.h
new file mode 100644
index 000000000000..49f7759dedfa
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-modem.h
@@ -0,0 +1,31 @@
+/* arch/arm/plat-s3c64xx/include/plat/regs-modem.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C64XX - modem block registers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_S3C64XX_REGS_MODEM_H
+#define __PLAT_S3C64XX_REGS_MODEM_H __FILE__
+
+#define S3C64XX_MODEMREG(x)     (S3C64XX_VA_MODEM + (x))
+
+#define S3C64XX_MODEM_INT2AP                    S3C64XX_MODEMREG(0x0)
+#define S3C64XX_MODEM_INT2MODEM                 S3C64XX_MODEMREG(0x4)
+#define S3C64XX_MODEM_MIFCON                    S3C64XX_MODEMREG(0x8)
+#define S3C64XX_MODEM_MIFPCON                   S3C64XX_MODEMREG(0xC)
+#define S3C64XX_MODEM_INTCLR                    S3C64XX_MODEMREG(0x10)
+#define S3C64XX_MODEM_DMA_TXADDR                S3C64XX_MODEMREG(0x14)
+#define S3C64XX_MODEM_DMA_RXADDR                S3C64XX_MODEMREG(0x18)
+
+#define MIFPCON_INT2M_LEVEL                     (1 << 4)
+#define MIFPCON_LCD_BYPASS                      (1 << 3)
+
+#endif /* __PLAT_S3C64XX_REGS_MODEM_H */
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-sys.h b/arch/arm/plat-s3c64xx/include/plat/regs-sys.h
index d8ed82917096..69b78d9f83b8 100644
--- a/arch/arm/plat-s3c64xx/include/plat/regs-sys.h
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-sys.h
@@ -17,6 +17,10 @@
 
 #define S3C_SYSREG(x)           (S3C_VA_SYS + (x))
 
+#define S3C64XX_AHB_CON0        S3C_SYSREG(0x100)
+#define S3C64XX_AHB_CON1        S3C_SYSREG(0x104)
+#define S3C64XX_AHB_CON2        S3C_SYSREG(0x108)
+
 #define S3C64XX_OTHERS          S3C_SYSREG(0x900)
 
 #define S3C64XX_OTHERS_USBMASK  (1 << 16)
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h b/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h
new file mode 100644
index 000000000000..270d96ac9705
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h
@@ -0,0 +1,116 @@
+/* arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C64XX - syscon power and sleep control registers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_S3C64XX_REGS_SYSCON_POWER_H
+#define __PLAT_S3C64XX_REGS_SYSCON_POWER_H __FILE__
+
+#define S3C64XX_PWR_CFG                         S3C_SYSREG(0x804)
+
+#define S3C64XX_PWRCFG_OSC_OTG_DISABLE          (1 << 17)
+#define S3C64XX_PWRCFG_MMC2_DISABLE             (1 << 16)
+#define S3C64XX_PWRCFG_MMC1_DISABLE             (1 << 15)
+#define S3C64XX_PWRCFG_MMC0_DISABLE             (1 << 14)
+#define S3C64XX_PWRCFG_HSI_DISABLE              (1 << 13)
+#define S3C64XX_PWRCFG_TS_DISABLE               (1 << 12)
+#define S3C64XX_PWRCFG_RTC_TICK_DISABLE         (1 << 11)
+#define S3C64XX_PWRCFG_RTC_ALARM_DISABLE        (1 << 10)
+#define S3C64XX_PWRCFG_MSM_DISABLE              (1 << 9)
+#define S3C64XX_PWRCFG_KEY_DISABLE              (1 << 8)
+#define S3C64XX_PWRCFG_BATF_DISABLE             (1 << 7)
+
+#define S3C64XX_PWRCFG_CFG_WFI_MASK             (0x3 << 5)
+#define S3C64XX_PWRCFG_CFG_WFI_SHIFT            (5)
+#define S3C64XX_PWRCFG_CFG_WFI_IGNORE           (0x0 << 5)
+#define S3C64XX_PWRCFG_CFG_WFI_IDLE             (0x1 << 5)
+#define S3C64XX_PWRCFG_CFG_WFI_STOP             (0x2 << 5)
+#define S3C64XX_PWRCFG_CFG_WFI_SLEEP            (0x3 << 5)
+
+#define S3C64XX_PWRCFG_CFG_BATFLT_MASK          (0x3 << 3)
+#define S3C64XX_PWRCFG_CFG_BATFLT_SHIFT         (3)
+#define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE        (0x0 << 3)
+#define S3C64XX_PWRCFG_CFG_BATFLT_IRQ           (0x1 << 3)
+#define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP         (0x3 << 3)
+
+#define S3C64XX_PWRCFG_CFG_BAT_WAKE             (1 << 2)
+#define S3C64XX_PWRCFG_OSC27_EN                 (1 << 0)
+
+#define S3C64XX_EINT_MASK                       S3C_SYSREG(0x808)
+
+#define S3C64XX_NORMAL_CFG                      S3C_SYSREG(0x810)
+
+#define S3C64XX_NORMALCFG_IROM_ON               (1 << 30)
+#define S3C64XX_NORMALCFG_DOMAIN_ETM_ON         (1 << 16)
+#define S3C64XX_NORMALCFG_DOMAIN_S_ON           (1 << 15)
+#define S3C64XX_NORMALCFG_DOMAIN_F_ON           (1 << 14)
+#define S3C64XX_NORMALCFG_DOMAIN_P_ON           (1 << 13)
+#define S3C64XX_NORMALCFG_DOMAIN_I_ON           (1 << 12)
+#define S3C64XX_NORMALCFG_DOMAIN_G_ON           (1 << 10)
+#define S3C64XX_NORMALCFG_DOMAIN_V_ON           (1 << 9)
+
+#define S3C64XX_STOP_CFG                        S3C_SYSREG(0x814)
+
+#define S3C64XX_STOPCFG_MEMORY_ARM_ON           (1 << 29)
+#define S3C64XX_STOPCFG_TOP_MEMORY_ON           (1 << 20)
+#define S3C64XX_STOPCFG_ARM_LOGIC_ON            (1 << 17)
+#define S3C64XX_STOPCFG_TOP_LOGIC_ON            (1 << 8)
+#define S3C64XX_STOPCFG_OSC_EN                  (1 << 0)
+
+#define S3C64XX_SLEEP_CFG                       S3C_SYSREG(0x818)
+
+#define S3C64XX_SLEEPCFG_OSC_EN                 (1 << 0)
+
+#define S3C64XX_STOP_MEM_CFG                    S3C_SYSREG(0x81c)
+
+#define S3C64XX_STOPMEMCFG_MODEMIF_RETAIN       (1 << 6)
+#define S3C64XX_STOPMEMCFG_HOSTIF_RETAIN        (1 << 5)
+#define S3C64XX_STOPMEMCFG_OTG_RETAIN           (1 << 4)
+#define S3C64XX_STOPMEMCFG_HSMCC_RETAIN         (1 << 3)
+#define S3C64XX_STOPMEMCFG_IROM_RETAIN          (1 << 2)
+#define S3C64XX_STOPMEMCFG_IRDA_RETAIN          (1 << 1)
+#define S3C64XX_STOPMEMCFG_NFCON_RETAIN         (1 << 0)
+
+#define S3C64XX_OSC_STABLE                      S3C_SYSREG(0x824)
+#define S3C64XX_PWR_STABLE                      S3C_SYSREG(0x828)
+
+#define S3C64XX_WAKEUP_STAT                     S3C_SYSREG(0x908)
+
+#define S3C64XX_WAKEUPSTAT_MMC2                 (1 << 11)
+#define S3C64XX_WAKEUPSTAT_MMC1                 (1 << 10)
+#define S3C64XX_WAKEUPSTAT_MMC0                 (1 << 9)
+#define S3C64XX_WAKEUPSTAT_HSI                  (1 << 8)
+#define S3C64XX_WAKEUPSTAT_BATFLT               (1 << 6)
+#define S3C64XX_WAKEUPSTAT_MSM                  (1 << 5)
+#define S3C64XX_WAKEUPSTAT_KEY                  (1 << 4)
+#define S3C64XX_WAKEUPSTAT_TS                   (1 << 3)
+#define S3C64XX_WAKEUPSTAT_RTC_TICK             (1 << 2)
+#define S3C64XX_WAKEUPSTAT_RTC_ALARM            (1 << 1)
+#define S3C64XX_WAKEUPSTAT_EINT                 (1 << 0)
+
+#define S3C64XX_BLK_PWR_STAT                    S3C_SYSREG(0x90c)
+
+#define S3C64XX_BLKPWRSTAT_G                    (1 << 7)
+#define S3C64XX_BLKPWRSTAT_ETM                  (1 << 6)
+#define S3C64XX_BLKPWRSTAT_S                    (1 << 5)
+#define S3C64XX_BLKPWRSTAT_F                    (1 << 4)
+#define S3C64XX_BLKPWRSTAT_P                    (1 << 3)
+#define S3C64XX_BLKPWRSTAT_I                    (1 << 2)
+#define S3C64XX_BLKPWRSTAT_V                    (1 << 1)
+#define S3C64XX_BLKPWRSTAT_TOP                  (1 << 0)
+
+#define S3C64XX_INFORM0                         S3C_SYSREG(0xA00)
+#define S3C64XX_INFORM1                         S3C_SYSREG(0xA04)
+#define S3C64XX_INFORM2                         S3C_SYSREG(0xA08)
+#define S3C64XX_INFORM3                         S3C_SYSREG(0xA0C)
+
+#endif /* __PLAT_S3C64XX_REGS_SYSCON_POWER_H */
diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/plat-s3c64xx/irq-eint.c
index cf524826c93a..47e5155bb13e 100644
--- a/arch/arm/plat-s3c64xx/irq-eint.c
+++ b/arch/arm/plat-s3c64xx/irq-eint.c
@@ -27,20 +27,6 @@
 #include <mach/map.h>
 #include <plat/cpu.h>
 
-/* GPIO is 0x7F008xxx, */
-#define S3C64XX_GPIOREG(x)      (S3C64XX_VA_GPIO + (x))
-
-#define S3C64XX_EINT0CON0       S3C64XX_GPIOREG(0x900)
-#define S3C64XX_EINT0CON1       S3C64XX_GPIOREG(0x904)
-#define S3C64XX_EINT0FLTCON0    S3C64XX_GPIOREG(0x910)
-#define S3C64XX_EINT0FLTCON1    S3C64XX_GPIOREG(0x914)
-#define S3C64XX_EINT0FLTCON2    S3C64XX_GPIOREG(0x918)
-#define S3C64XX_EINT0FLTCON3    S3C64XX_GPIOREG(0x91C)
-
-#define S3C64XX_EINT0MASK       S3C64XX_GPIOREG(0x920)
-#define S3C64XX_EINT0PEND       S3C64XX_GPIOREG(0x924)
-
-
 #define eint_offset(irq)        ((irq) - IRQ_EINT(0))
 #define eint_irq_to_bit(irq)    (1 << eint_offset(irq))
 
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index b4211d8b2ac7..945e0d237a1d 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
 #
 #   http://www.arm.linux.org.uk/developer/machines/?action=new
 #
-# Last update: Thu Mar 12 18:01:45 2009
+# Last update: Mon Mar 23 20:09:01 2009
 #
 # machine_is_xxx        CONFIG_xxxx             MACH_TYPE_xxx           number
 #
@@ -2124,3 +2124,11 @@ mx27wallace		MACH_MX27WALLACE	MX27WALLACE		2133
 fmzwebmodul             MACH_FMZWEBMODUL        FMZWEBMODUL             2134
 rd78x00_masa            MACH_RD78X00_MASA       RD78X00_MASA            2135
 smallogger              MACH_SMALLOGGER         SMALLOGGER              2136
+ccw9p9215               MACH_CCW9P9215          CCW9P9215               2137
+dm355_leopard           MACH_DM355_LEOPARD      DM355_LEOPARD           2138
+ts219                   MACH_TS219              TS219                   2139
+tny_a9263               MACH_TNY_A9263          TNY_A9263               2140
+apollo                  MACH_APOLLO             APOLLO                  2141
+at91cap9stk             MACH_AT91CAP9STK        AT91CAP9STK             2142
+spc300                  MACH_SPC300             SPC300                  2143
+eko                     MACH_EKO                EKO                     2144
diff --git a/arch/arm/vfp/vfp.h b/arch/arm/vfp/vfp.h
index 8de86e4feada..c8c98dd44ad4 100644
--- a/arch/arm/vfp/vfp.h
+++ b/arch/arm/vfp/vfp.h
@@ -377,6 +377,4 @@ struct op {
         u32 flags;
 };
 
-#if defined(CONFIG_SMP) || defined(CONFIG_PM)
 extern void vfp_save_state(void *location, u32 fpexc);
-#endif
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index c92a08bd6a86..a5a4e57763c3 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -172,7 +172,6 @@ process_exception:
                                         @ retry the faulted instruction
 ENDPROC(vfp_support_entry)
 
-#if defined(CONFIG_SMP) || defined(CONFIG_PM)
 ENTRY(vfp_save_state)
         @ Save the current VFP state
         @ r0 - save location
@@ -190,7 +189,6 @@ ENTRY(vfp_save_state)
         stmia   r0, {r1, r2, r3, r12}   @ save FPEXC, FPSCR, FPINST, FPINST2
         mov     pc, lr
 ENDPROC(vfp_save_state)
-#endif
 
 last_VFP_context_address:
         .word   last_VFP_context
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 9f476a1be2ca..75457b30d813 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -377,6 +377,55 @@ static void vfp_pm_init(void)
 static inline void vfp_pm_init(void) { }
 #endif /* CONFIG_PM */
 
+/*
+ * Synchronise the hardware VFP state of a thread other than current with the
+ * saved one. This function is used by the ptrace mechanism.
+ */
+#ifdef CONFIG_SMP
+void vfp_sync_state(struct thread_info *thread)
+{
+        /*
+         * On SMP systems, the VFP state is automatically saved at every
+         * context switch. We mark the thread VFP state as belonging to a
+         * non-existent CPU so that the saved one will be reloaded when
+         * needed.
+         */
+        thread->vfpstate.hard.cpu = NR_CPUS;
+}
+#else
+void vfp_sync_state(struct thread_info *thread)
+{
+        unsigned int cpu = get_cpu();
+        u32 fpexc = fmrx(FPEXC);
+
+        /*
+         * If VFP is enabled, the previous state was already saved and
+         * last_VFP_context updated.
+         */
+        if (fpexc & FPEXC_EN)
+                goto out;
+
+        if (!last_VFP_context[cpu])
+                goto out;
+
+        /*
+         * Save the last VFP state on this CPU.
+         */
+        fmxr(FPEXC, fpexc | FPEXC_EN);
+        vfp_save_state(last_VFP_context[cpu], fpexc);
+        fmxr(FPEXC, fpexc);
+
+        /*
+         * Set the context to NULL to force a reload the next time the thread
+         * uses the VFP.
+         */
+        last_VFP_context[cpu] = NULL;
+
+out:
+        put_cpu();
+}
+#endif
+
 #include <linux/smp.h>
 
 /*
@@ -427,6 +476,18 @@ static int __init vfp_init(void)
                  * in place; report VFP support to userspace.
                  */
                 elf_hwcap |= HWCAP_VFP;
+#ifdef CONFIG_VFPv3
+                if (VFP_arch >= 3) {
+                        elf_hwcap |= HWCAP_VFPv3;
+
+                        /*
+                         * Check for VFPv3 D16. CPUs in this configuration
+                         * only have 16 x 64bit registers.
+                         */
+                        if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK)) == 1)
+                                elf_hwcap |= HWCAP_VFPv3D16;
+                }
+#endif
 #ifdef CONFIG_NEON
                 /*
                  * Check for the presence of the Advanced SIMD