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-rw-r--r--arch/x86/kernel/cpu/common.c8
-rw-r--r--arch/x86/kernel/cpu/common_64.c17
2 files changed, 25 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 2c4bfa2e56ad..f9191207718b 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -285,6 +285,10 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
285 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", 285 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
286 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); 286 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
287 c->x86_cache_size = (ecx>>24) + (edx>>24); 287 c->x86_cache_size = (ecx>>24) + (edx>>24);
288#ifdef CONFIG_X86_64
289 /* On K8 L1 TLB is inclusive, so don't count it */
290 c->x86_tlbsize = 0;
291#endif
288 } 292 }
289 293
290 if (n < 0x80000006) /* Some chips just has a large L1. */ 294 if (n < 0x80000006) /* Some chips just has a large L1. */
@@ -293,6 +297,9 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
293 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 297 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
294 l2size = ecx >> 16; 298 l2size = ecx >> 16;
295 299
300#ifdef CONFIG_X86_64
301 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
302#else
296 /* do processor-specific cache resizing */ 303 /* do processor-specific cache resizing */
297 if (this_cpu->c_size_cache) 304 if (this_cpu->c_size_cache)
298 l2size = this_cpu->c_size_cache(c, l2size); 305 l2size = this_cpu->c_size_cache(c, l2size);
@@ -303,6 +310,7 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
303 310
304 if (l2size == 0) 311 if (l2size == 0)
305 return; /* Again, no L2 cache is possible */ 312 return; /* Again, no L2 cache is possible */
313#endif
306 314
307 c->x86_cache_size = l2size; 315 c->x86_cache_size = l2size;
308 316
diff --git a/arch/x86/kernel/cpu/common_64.c b/arch/x86/kernel/cpu/common_64.c
index 2fda10974813..f7a2d524b1e7 100644
--- a/arch/x86/kernel/cpu/common_64.c
+++ b/arch/x86/kernel/cpu/common_64.c
@@ -285,8 +285,10 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
285 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", 285 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
286 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); 286 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
287 c->x86_cache_size = (ecx>>24) + (edx>>24); 287 c->x86_cache_size = (ecx>>24) + (edx>>24);
288#ifdef CONFIG_X86_64
288 /* On K8 L1 TLB is inclusive, so don't count it */ 289 /* On K8 L1 TLB is inclusive, so don't count it */
289 c->x86_tlbsize = 0; 290 c->x86_tlbsize = 0;
291#endif
290 } 292 }
291 293
292 if (n < 0x80000006) /* Some chips just has a large L1. */ 294 if (n < 0x80000006) /* Some chips just has a large L1. */
@@ -294,7 +296,22 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
294 296
295 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 297 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
296 l2size = ecx >> 16; 298 l2size = ecx >> 16;
299
300#ifdef CONFIG_X86_64
297 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 301 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
302#else
303
304 /* do processor-specific cache resizing */
305 if (this_cpu->c_size_cache)
306 l2size = this_cpu->c_size_cache(c, l2size);
307
308 /* Allow user to override all this if necessary. */
309 if (cachesize_override != -1)
310 l2size = cachesize_override;
311
312 if (l2size == 0)
313 return; /* Again, no L2 cache is possible */
314#endif
298 315
299 c->x86_cache_size = l2size; 316 c->x86_cache_size = l2size;
300 317