diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-omap1/clock_data.c | 10 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock2xxx_data.c | 81 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock34xx_data.c | 88 | ||||
-rw-r--r-- | arch/arm/plat-omap/clock.c | 2 | ||||
-rw-r--r-- | arch/arm/plat-omap/include/plat/clock.h | 1 |
5 files changed, 61 insertions, 121 deletions
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index edefb3440d30..cea91cdf624d 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c | |||
@@ -530,7 +530,7 @@ static struct clk bclk_16xx = { | |||
530 | }; | 530 | }; |
531 | 531 | ||
532 | static struct clk mmc1_ck = { | 532 | static struct clk mmc1_ck = { |
533 | .name = "mmc_ck", | 533 | .name = "mmc1_ck", |
534 | .ops = &clkops_generic, | 534 | .ops = &clkops_generic, |
535 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | 535 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
536 | .parent = &armper_ck.clk, | 536 | .parent = &armper_ck.clk, |
@@ -541,8 +541,7 @@ static struct clk mmc1_ck = { | |||
541 | }; | 541 | }; |
542 | 542 | ||
543 | static struct clk mmc2_ck = { | 543 | static struct clk mmc2_ck = { |
544 | .name = "mmc_ck", | 544 | .name = "mmc2_ck", |
545 | .id = 1, | ||
546 | .ops = &clkops_generic, | 545 | .ops = &clkops_generic, |
547 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | 546 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
548 | .parent = &armper_ck.clk, | 547 | .parent = &armper_ck.clk, |
@@ -553,8 +552,7 @@ static struct clk mmc2_ck = { | |||
553 | }; | 552 | }; |
554 | 553 | ||
555 | static struct clk mmc3_ck = { | 554 | static struct clk mmc3_ck = { |
556 | .name = "mmc_ck", | 555 | .name = "mmc3_ck", |
557 | .id = 2, | ||
558 | .ops = &clkops_generic, | 556 | .ops = &clkops_generic, |
559 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | 557 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
560 | .parent = &armper_ck.clk, | 558 | .parent = &armper_ck.clk, |
@@ -577,7 +575,6 @@ static struct clk virtual_ck_mpu = { | |||
577 | remains active during MPU idle whenever this is enabled */ | 575 | remains active during MPU idle whenever this is enabled */ |
578 | static struct clk i2c_fck = { | 576 | static struct clk i2c_fck = { |
579 | .name = "i2c_fck", | 577 | .name = "i2c_fck", |
580 | .id = 1, | ||
581 | .ops = &clkops_null, | 578 | .ops = &clkops_null, |
582 | .flags = CLOCK_NO_IDLE_PARENT, | 579 | .flags = CLOCK_NO_IDLE_PARENT, |
583 | .parent = &armxor_ck.clk, | 580 | .parent = &armxor_ck.clk, |
@@ -586,7 +583,6 @@ static struct clk i2c_fck = { | |||
586 | 583 | ||
587 | static struct clk i2c_ick = { | 584 | static struct clk i2c_ick = { |
588 | .name = "i2c_ick", | 585 | .name = "i2c_ick", |
589 | .id = 1, | ||
590 | .ops = &clkops_null, | 586 | .ops = &clkops_null, |
591 | .flags = CLOCK_NO_IDLE_PARENT, | 587 | .flags = CLOCK_NO_IDLE_PARENT, |
592 | .parent = &armper_ck.clk, | 588 | .parent = &armper_ck.clk, |
diff --git a/arch/arm/mach-omap2/clock2xxx_data.c b/arch/arm/mach-omap2/clock2xxx_data.c index 9bcef44fb140..82ad8b439eb9 100644 --- a/arch/arm/mach-omap2/clock2xxx_data.c +++ b/arch/arm/mach-omap2/clock2xxx_data.c | |||
@@ -1224,9 +1224,8 @@ static struct clk gpt12_fck = { | |||
1224 | }; | 1224 | }; |
1225 | 1225 | ||
1226 | static struct clk mcbsp1_ick = { | 1226 | static struct clk mcbsp1_ick = { |
1227 | .name = "mcbsp_ick", | 1227 | .name = "mcbsp1_ick", |
1228 | .ops = &clkops_omap2_dflt_wait, | 1228 | .ops = &clkops_omap2_dflt_wait, |
1229 | .id = 1, | ||
1230 | .parent = &l4_ck, | 1229 | .parent = &l4_ck, |
1231 | .clkdm_name = "core_l4_clkdm", | 1230 | .clkdm_name = "core_l4_clkdm", |
1232 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1231 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
@@ -1235,9 +1234,8 @@ static struct clk mcbsp1_ick = { | |||
1235 | }; | 1234 | }; |
1236 | 1235 | ||
1237 | static struct clk mcbsp1_fck = { | 1236 | static struct clk mcbsp1_fck = { |
1238 | .name = "mcbsp_fck", | 1237 | .name = "mcbsp1_fck", |
1239 | .ops = &clkops_omap2_dflt_wait, | 1238 | .ops = &clkops_omap2_dflt_wait, |
1240 | .id = 1, | ||
1241 | .parent = &func_96m_ck, | 1239 | .parent = &func_96m_ck, |
1242 | .clkdm_name = "core_l4_clkdm", | 1240 | .clkdm_name = "core_l4_clkdm", |
1243 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1241 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
@@ -1246,9 +1244,8 @@ static struct clk mcbsp1_fck = { | |||
1246 | }; | 1244 | }; |
1247 | 1245 | ||
1248 | static struct clk mcbsp2_ick = { | 1246 | static struct clk mcbsp2_ick = { |
1249 | .name = "mcbsp_ick", | 1247 | .name = "mcbsp2_ick", |
1250 | .ops = &clkops_omap2_dflt_wait, | 1248 | .ops = &clkops_omap2_dflt_wait, |
1251 | .id = 2, | ||
1252 | .parent = &l4_ck, | 1249 | .parent = &l4_ck, |
1253 | .clkdm_name = "core_l4_clkdm", | 1250 | .clkdm_name = "core_l4_clkdm", |
1254 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1251 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
@@ -1257,9 +1254,8 @@ static struct clk mcbsp2_ick = { | |||
1257 | }; | 1254 | }; |
1258 | 1255 | ||
1259 | static struct clk mcbsp2_fck = { | 1256 | static struct clk mcbsp2_fck = { |
1260 | .name = "mcbsp_fck", | 1257 | .name = "mcbsp2_fck", |
1261 | .ops = &clkops_omap2_dflt_wait, | 1258 | .ops = &clkops_omap2_dflt_wait, |
1262 | .id = 2, | ||
1263 | .parent = &func_96m_ck, | 1259 | .parent = &func_96m_ck, |
1264 | .clkdm_name = "core_l4_clkdm", | 1260 | .clkdm_name = "core_l4_clkdm", |
1265 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1261 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
@@ -1268,9 +1264,8 @@ static struct clk mcbsp2_fck = { | |||
1268 | }; | 1264 | }; |
1269 | 1265 | ||
1270 | static struct clk mcbsp3_ick = { | 1266 | static struct clk mcbsp3_ick = { |
1271 | .name = "mcbsp_ick", | 1267 | .name = "mcbsp3_ick", |
1272 | .ops = &clkops_omap2_dflt_wait, | 1268 | .ops = &clkops_omap2_dflt_wait, |
1273 | .id = 3, | ||
1274 | .parent = &l4_ck, | 1269 | .parent = &l4_ck, |
1275 | .clkdm_name = "core_l4_clkdm", | 1270 | .clkdm_name = "core_l4_clkdm", |
1276 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1271 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
@@ -1279,9 +1274,8 @@ static struct clk mcbsp3_ick = { | |||
1279 | }; | 1274 | }; |
1280 | 1275 | ||
1281 | static struct clk mcbsp3_fck = { | 1276 | static struct clk mcbsp3_fck = { |
1282 | .name = "mcbsp_fck", | 1277 | .name = "mcbsp3_fck", |
1283 | .ops = &clkops_omap2_dflt_wait, | 1278 | .ops = &clkops_omap2_dflt_wait, |
1284 | .id = 3, | ||
1285 | .parent = &func_96m_ck, | 1279 | .parent = &func_96m_ck, |
1286 | .clkdm_name = "core_l4_clkdm", | 1280 | .clkdm_name = "core_l4_clkdm", |
1287 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1281 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
@@ -1290,9 +1284,8 @@ static struct clk mcbsp3_fck = { | |||
1290 | }; | 1284 | }; |
1291 | 1285 | ||
1292 | static struct clk mcbsp4_ick = { | 1286 | static struct clk mcbsp4_ick = { |
1293 | .name = "mcbsp_ick", | 1287 | .name = "mcbsp4_ick", |
1294 | .ops = &clkops_omap2_dflt_wait, | 1288 | .ops = &clkops_omap2_dflt_wait, |
1295 | .id = 4, | ||
1296 | .parent = &l4_ck, | 1289 | .parent = &l4_ck, |
1297 | .clkdm_name = "core_l4_clkdm", | 1290 | .clkdm_name = "core_l4_clkdm", |
1298 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1291 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
@@ -1301,9 +1294,8 @@ static struct clk mcbsp4_ick = { | |||
1301 | }; | 1294 | }; |
1302 | 1295 | ||
1303 | static struct clk mcbsp4_fck = { | 1296 | static struct clk mcbsp4_fck = { |
1304 | .name = "mcbsp_fck", | 1297 | .name = "mcbsp4_fck", |
1305 | .ops = &clkops_omap2_dflt_wait, | 1298 | .ops = &clkops_omap2_dflt_wait, |
1306 | .id = 4, | ||
1307 | .parent = &func_96m_ck, | 1299 | .parent = &func_96m_ck, |
1308 | .clkdm_name = "core_l4_clkdm", | 1300 | .clkdm_name = "core_l4_clkdm", |
1309 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1301 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
@@ -1312,9 +1304,8 @@ static struct clk mcbsp4_fck = { | |||
1312 | }; | 1304 | }; |
1313 | 1305 | ||
1314 | static struct clk mcbsp5_ick = { | 1306 | static struct clk mcbsp5_ick = { |
1315 | .name = "mcbsp_ick", | 1307 | .name = "mcbsp5_ick", |
1316 | .ops = &clkops_omap2_dflt_wait, | 1308 | .ops = &clkops_omap2_dflt_wait, |
1317 | .id = 5, | ||
1318 | .parent = &l4_ck, | 1309 | .parent = &l4_ck, |
1319 | .clkdm_name = "core_l4_clkdm", | 1310 | .clkdm_name = "core_l4_clkdm", |
1320 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1311 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
@@ -1323,9 +1314,8 @@ static struct clk mcbsp5_ick = { | |||
1323 | }; | 1314 | }; |
1324 | 1315 | ||
1325 | static struct clk mcbsp5_fck = { | 1316 | static struct clk mcbsp5_fck = { |
1326 | .name = "mcbsp_fck", | 1317 | .name = "mcbsp5_fck", |
1327 | .ops = &clkops_omap2_dflt_wait, | 1318 | .ops = &clkops_omap2_dflt_wait, |
1328 | .id = 5, | ||
1329 | .parent = &func_96m_ck, | 1319 | .parent = &func_96m_ck, |
1330 | .clkdm_name = "core_l4_clkdm", | 1320 | .clkdm_name = "core_l4_clkdm", |
1331 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1321 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
@@ -1334,9 +1324,8 @@ static struct clk mcbsp5_fck = { | |||
1334 | }; | 1324 | }; |
1335 | 1325 | ||
1336 | static struct clk mcspi1_ick = { | 1326 | static struct clk mcspi1_ick = { |
1337 | .name = "mcspi_ick", | 1327 | .name = "mcspi1_ick", |
1338 | .ops = &clkops_omap2_dflt_wait, | 1328 | .ops = &clkops_omap2_dflt_wait, |
1339 | .id = 1, | ||
1340 | .parent = &l4_ck, | 1329 | .parent = &l4_ck, |
1341 | .clkdm_name = "core_l4_clkdm", | 1330 | .clkdm_name = "core_l4_clkdm", |
1342 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1331 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
@@ -1345,9 +1334,8 @@ static struct clk mcspi1_ick = { | |||
1345 | }; | 1334 | }; |
1346 | 1335 | ||
1347 | static struct clk mcspi1_fck = { | 1336 | static struct clk mcspi1_fck = { |
1348 | .name = "mcspi_fck", | 1337 | .name = "mcspi1_fck", |
1349 | .ops = &clkops_omap2_dflt_wait, | 1338 | .ops = &clkops_omap2_dflt_wait, |
1350 | .id = 1, | ||
1351 | .parent = &func_48m_ck, | 1339 | .parent = &func_48m_ck, |
1352 | .clkdm_name = "core_l4_clkdm", | 1340 | .clkdm_name = "core_l4_clkdm", |
1353 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1341 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
@@ -1356,9 +1344,8 @@ static struct clk mcspi1_fck = { | |||
1356 | }; | 1344 | }; |
1357 | 1345 | ||
1358 | static struct clk mcspi2_ick = { | 1346 | static struct clk mcspi2_ick = { |
1359 | .name = "mcspi_ick", | 1347 | .name = "mcspi2_ick", |
1360 | .ops = &clkops_omap2_dflt_wait, | 1348 | .ops = &clkops_omap2_dflt_wait, |
1361 | .id = 2, | ||
1362 | .parent = &l4_ck, | 1349 | .parent = &l4_ck, |
1363 | .clkdm_name = "core_l4_clkdm", | 1350 | .clkdm_name = "core_l4_clkdm", |
1364 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1351 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
@@ -1367,9 +1354,8 @@ static struct clk mcspi2_ick = { | |||
1367 | }; | 1354 | }; |
1368 | 1355 | ||
1369 | static struct clk mcspi2_fck = { | 1356 | static struct clk mcspi2_fck = { |
1370 | .name = "mcspi_fck", | 1357 | .name = "mcspi2_fck", |
1371 | .ops = &clkops_omap2_dflt_wait, | 1358 | .ops = &clkops_omap2_dflt_wait, |
1372 | .id = 2, | ||
1373 | .parent = &func_48m_ck, | 1359 | .parent = &func_48m_ck, |
1374 | .clkdm_name = "core_l4_clkdm", | 1360 | .clkdm_name = "core_l4_clkdm", |
1375 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1361 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
@@ -1378,9 +1364,8 @@ static struct clk mcspi2_fck = { | |||
1378 | }; | 1364 | }; |
1379 | 1365 | ||
1380 | static struct clk mcspi3_ick = { | 1366 | static struct clk mcspi3_ick = { |
1381 | .name = "mcspi_ick", | 1367 | .name = "mcspi3_ick", |
1382 | .ops = &clkops_omap2_dflt_wait, | 1368 | .ops = &clkops_omap2_dflt_wait, |
1383 | .id = 3, | ||
1384 | .parent = &l4_ck, | 1369 | .parent = &l4_ck, |
1385 | .clkdm_name = "core_l4_clkdm", | 1370 | .clkdm_name = "core_l4_clkdm", |
1386 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1371 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
@@ -1389,9 +1374,8 @@ static struct clk mcspi3_ick = { | |||
1389 | }; | 1374 | }; |
1390 | 1375 | ||
1391 | static struct clk mcspi3_fck = { | 1376 | static struct clk mcspi3_fck = { |
1392 | .name = "mcspi_fck", | 1377 | .name = "mcspi3_fck", |
1393 | .ops = &clkops_omap2_dflt_wait, | 1378 | .ops = &clkops_omap2_dflt_wait, |
1394 | .id = 3, | ||
1395 | .parent = &func_48m_ck, | 1379 | .parent = &func_48m_ck, |
1396 | .clkdm_name = "core_l4_clkdm", | 1380 | .clkdm_name = "core_l4_clkdm", |
1397 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1381 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
@@ -1717,9 +1701,8 @@ static struct clk hdq_fck = { | |||
1717 | }; | 1701 | }; |
1718 | 1702 | ||
1719 | static struct clk i2c2_ick = { | 1703 | static struct clk i2c2_ick = { |
1720 | .name = "i2c_ick", | 1704 | .name = "i2c2_ick", |
1721 | .ops = &clkops_omap2_dflt_wait, | 1705 | .ops = &clkops_omap2_dflt_wait, |
1722 | .id = 2, | ||
1723 | .parent = &l4_ck, | 1706 | .parent = &l4_ck, |
1724 | .clkdm_name = "core_l4_clkdm", | 1707 | .clkdm_name = "core_l4_clkdm", |
1725 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1708 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
@@ -1728,9 +1711,8 @@ static struct clk i2c2_ick = { | |||
1728 | }; | 1711 | }; |
1729 | 1712 | ||
1730 | static struct clk i2c2_fck = { | 1713 | static struct clk i2c2_fck = { |
1731 | .name = "i2c_fck", | 1714 | .name = "i2c2_fck", |
1732 | .ops = &clkops_omap2_dflt_wait, | 1715 | .ops = &clkops_omap2_dflt_wait, |
1733 | .id = 2, | ||
1734 | .parent = &func_12m_ck, | 1716 | .parent = &func_12m_ck, |
1735 | .clkdm_name = "core_l4_clkdm", | 1717 | .clkdm_name = "core_l4_clkdm", |
1736 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1718 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
@@ -1739,9 +1721,8 @@ static struct clk i2c2_fck = { | |||
1739 | }; | 1721 | }; |
1740 | 1722 | ||
1741 | static struct clk i2chs2_fck = { | 1723 | static struct clk i2chs2_fck = { |
1742 | .name = "i2c_fck", | 1724 | .name = "i2chs2_fck", |
1743 | .ops = &clkops_omap2430_i2chs_wait, | 1725 | .ops = &clkops_omap2430_i2chs_wait, |
1744 | .id = 2, | ||
1745 | .parent = &func_96m_ck, | 1726 | .parent = &func_96m_ck, |
1746 | .clkdm_name = "core_l4_clkdm", | 1727 | .clkdm_name = "core_l4_clkdm", |
1747 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1728 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
@@ -1750,9 +1731,8 @@ static struct clk i2chs2_fck = { | |||
1750 | }; | 1731 | }; |
1751 | 1732 | ||
1752 | static struct clk i2c1_ick = { | 1733 | static struct clk i2c1_ick = { |
1753 | .name = "i2c_ick", | 1734 | .name = "i2c1_ick", |
1754 | .ops = &clkops_omap2_dflt_wait, | 1735 | .ops = &clkops_omap2_dflt_wait, |
1755 | .id = 1, | ||
1756 | .parent = &l4_ck, | 1736 | .parent = &l4_ck, |
1757 | .clkdm_name = "core_l4_clkdm", | 1737 | .clkdm_name = "core_l4_clkdm", |
1758 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1738 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
@@ -1761,9 +1741,8 @@ static struct clk i2c1_ick = { | |||
1761 | }; | 1741 | }; |
1762 | 1742 | ||
1763 | static struct clk i2c1_fck = { | 1743 | static struct clk i2c1_fck = { |
1764 | .name = "i2c_fck", | 1744 | .name = "i2c1_fck", |
1765 | .ops = &clkops_omap2_dflt_wait, | 1745 | .ops = &clkops_omap2_dflt_wait, |
1766 | .id = 1, | ||
1767 | .parent = &func_12m_ck, | 1746 | .parent = &func_12m_ck, |
1768 | .clkdm_name = "core_l4_clkdm", | 1747 | .clkdm_name = "core_l4_clkdm", |
1769 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1748 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
@@ -1772,9 +1751,8 @@ static struct clk i2c1_fck = { | |||
1772 | }; | 1751 | }; |
1773 | 1752 | ||
1774 | static struct clk i2chs1_fck = { | 1753 | static struct clk i2chs1_fck = { |
1775 | .name = "i2c_fck", | 1754 | .name = "i2chs1_fck", |
1776 | .ops = &clkops_omap2430_i2chs_wait, | 1755 | .ops = &clkops_omap2430_i2chs_wait, |
1777 | .id = 1, | ||
1778 | .parent = &func_96m_ck, | 1756 | .parent = &func_96m_ck, |
1779 | .clkdm_name = "core_l4_clkdm", | 1757 | .clkdm_name = "core_l4_clkdm", |
1780 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1758 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
@@ -1941,7 +1919,7 @@ static struct clk usbhs_ick = { | |||
1941 | }; | 1919 | }; |
1942 | 1920 | ||
1943 | static struct clk mmchs1_ick = { | 1921 | static struct clk mmchs1_ick = { |
1944 | .name = "mmchs_ick", | 1922 | .name = "mmchs1_ick", |
1945 | .ops = &clkops_omap2_dflt_wait, | 1923 | .ops = &clkops_omap2_dflt_wait, |
1946 | .parent = &l4_ck, | 1924 | .parent = &l4_ck, |
1947 | .clkdm_name = "core_l4_clkdm", | 1925 | .clkdm_name = "core_l4_clkdm", |
@@ -1951,7 +1929,7 @@ static struct clk mmchs1_ick = { | |||
1951 | }; | 1929 | }; |
1952 | 1930 | ||
1953 | static struct clk mmchs1_fck = { | 1931 | static struct clk mmchs1_fck = { |
1954 | .name = "mmchs_fck", | 1932 | .name = "mmchs1_fck", |
1955 | .ops = &clkops_omap2_dflt_wait, | 1933 | .ops = &clkops_omap2_dflt_wait, |
1956 | .parent = &func_96m_ck, | 1934 | .parent = &func_96m_ck, |
1957 | .clkdm_name = "core_l3_clkdm", | 1935 | .clkdm_name = "core_l3_clkdm", |
@@ -1961,9 +1939,8 @@ static struct clk mmchs1_fck = { | |||
1961 | }; | 1939 | }; |
1962 | 1940 | ||
1963 | static struct clk mmchs2_ick = { | 1941 | static struct clk mmchs2_ick = { |
1964 | .name = "mmchs_ick", | 1942 | .name = "mmchs2_ick", |
1965 | .ops = &clkops_omap2_dflt_wait, | 1943 | .ops = &clkops_omap2_dflt_wait, |
1966 | .id = 1, | ||
1967 | .parent = &l4_ck, | 1944 | .parent = &l4_ck, |
1968 | .clkdm_name = "core_l4_clkdm", | 1945 | .clkdm_name = "core_l4_clkdm", |
1969 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1946 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
@@ -1972,9 +1949,8 @@ static struct clk mmchs2_ick = { | |||
1972 | }; | 1949 | }; |
1973 | 1950 | ||
1974 | static struct clk mmchs2_fck = { | 1951 | static struct clk mmchs2_fck = { |
1975 | .name = "mmchs_fck", | 1952 | .name = "mmchs2_fck", |
1976 | .ops = &clkops_omap2_dflt_wait, | 1953 | .ops = &clkops_omap2_dflt_wait, |
1977 | .id = 1, | ||
1978 | .parent = &func_96m_ck, | 1954 | .parent = &func_96m_ck, |
1979 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1955 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1980 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, | 1956 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, |
@@ -2012,7 +1988,7 @@ static struct clk mdm_intc_ick = { | |||
2012 | }; | 1988 | }; |
2013 | 1989 | ||
2014 | static struct clk mmchsdb1_fck = { | 1990 | static struct clk mmchsdb1_fck = { |
2015 | .name = "mmchsdb_fck", | 1991 | .name = "mmchsdb1_fck", |
2016 | .ops = &clkops_omap2_dflt_wait, | 1992 | .ops = &clkops_omap2_dflt_wait, |
2017 | .parent = &func_32k_ck, | 1993 | .parent = &func_32k_ck, |
2018 | .clkdm_name = "core_l4_clkdm", | 1994 | .clkdm_name = "core_l4_clkdm", |
@@ -2022,9 +1998,8 @@ static struct clk mmchsdb1_fck = { | |||
2022 | }; | 1998 | }; |
2023 | 1999 | ||
2024 | static struct clk mmchsdb2_fck = { | 2000 | static struct clk mmchsdb2_fck = { |
2025 | .name = "mmchsdb_fck", | 2001 | .name = "mmchsdb2_fck", |
2026 | .ops = &clkops_omap2_dflt_wait, | 2002 | .ops = &clkops_omap2_dflt_wait, |
2027 | .id = 1, | ||
2028 | .parent = &func_32k_ck, | 2003 | .parent = &func_32k_ck, |
2029 | .clkdm_name = "core_l4_clkdm", | 2004 | .clkdm_name = "core_l4_clkdm", |
2030 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2005 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c index 94f603b16c5e..995d5d4c897d 100644 --- a/arch/arm/mach-omap2/clock34xx_data.c +++ b/arch/arm/mach-omap2/clock34xx_data.c | |||
@@ -1505,9 +1505,8 @@ static struct clk core_96m_fck = { | |||
1505 | }; | 1505 | }; |
1506 | 1506 | ||
1507 | static struct clk mmchs3_fck = { | 1507 | static struct clk mmchs3_fck = { |
1508 | .name = "mmchs_fck", | 1508 | .name = "mmchs3_fck", |
1509 | .ops = &clkops_omap2_dflt_wait, | 1509 | .ops = &clkops_omap2_dflt_wait, |
1510 | .id = 2, | ||
1511 | .parent = &core_96m_fck, | 1510 | .parent = &core_96m_fck, |
1512 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1511 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1513 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | 1512 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, |
@@ -1516,9 +1515,8 @@ static struct clk mmchs3_fck = { | |||
1516 | }; | 1515 | }; |
1517 | 1516 | ||
1518 | static struct clk mmchs2_fck = { | 1517 | static struct clk mmchs2_fck = { |
1519 | .name = "mmchs_fck", | 1518 | .name = "mmchs2_fck", |
1520 | .ops = &clkops_omap2_dflt_wait, | 1519 | .ops = &clkops_omap2_dflt_wait, |
1521 | .id = 1, | ||
1522 | .parent = &core_96m_fck, | 1520 | .parent = &core_96m_fck, |
1523 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1521 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1524 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | 1522 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, |
@@ -1537,7 +1535,7 @@ static struct clk mspro_fck = { | |||
1537 | }; | 1535 | }; |
1538 | 1536 | ||
1539 | static struct clk mmchs1_fck = { | 1537 | static struct clk mmchs1_fck = { |
1540 | .name = "mmchs_fck", | 1538 | .name = "mmchs1_fck", |
1541 | .ops = &clkops_omap2_dflt_wait, | 1539 | .ops = &clkops_omap2_dflt_wait, |
1542 | .parent = &core_96m_fck, | 1540 | .parent = &core_96m_fck, |
1543 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1541 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
@@ -1547,9 +1545,8 @@ static struct clk mmchs1_fck = { | |||
1547 | }; | 1545 | }; |
1548 | 1546 | ||
1549 | static struct clk i2c3_fck = { | 1547 | static struct clk i2c3_fck = { |
1550 | .name = "i2c_fck", | 1548 | .name = "i2c3_fck", |
1551 | .ops = &clkops_omap2_dflt_wait, | 1549 | .ops = &clkops_omap2_dflt_wait, |
1552 | .id = 3, | ||
1553 | .parent = &core_96m_fck, | 1550 | .parent = &core_96m_fck, |
1554 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1551 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1555 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | 1552 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, |
@@ -1558,9 +1555,8 @@ static struct clk i2c3_fck = { | |||
1558 | }; | 1555 | }; |
1559 | 1556 | ||
1560 | static struct clk i2c2_fck = { | 1557 | static struct clk i2c2_fck = { |
1561 | .name = "i2c_fck", | 1558 | .name = "i2c2_fck", |
1562 | .ops = &clkops_omap2_dflt_wait, | 1559 | .ops = &clkops_omap2_dflt_wait, |
1563 | .id = 2, | ||
1564 | .parent = &core_96m_fck, | 1560 | .parent = &core_96m_fck, |
1565 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1561 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1566 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | 1562 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, |
@@ -1569,9 +1565,8 @@ static struct clk i2c2_fck = { | |||
1569 | }; | 1565 | }; |
1570 | 1566 | ||
1571 | static struct clk i2c1_fck = { | 1567 | static struct clk i2c1_fck = { |
1572 | .name = "i2c_fck", | 1568 | .name = "i2c1_fck", |
1573 | .ops = &clkops_omap2_dflt_wait, | 1569 | .ops = &clkops_omap2_dflt_wait, |
1574 | .id = 1, | ||
1575 | .parent = &core_96m_fck, | 1570 | .parent = &core_96m_fck, |
1576 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1571 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1577 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | 1572 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, |
@@ -1600,9 +1595,8 @@ static const struct clksel mcbsp_15_clksel[] = { | |||
1600 | }; | 1595 | }; |
1601 | 1596 | ||
1602 | static struct clk mcbsp5_fck = { | 1597 | static struct clk mcbsp5_fck = { |
1603 | .name = "mcbsp_fck", | 1598 | .name = "mcbsp5_fck", |
1604 | .ops = &clkops_omap2_dflt_wait, | 1599 | .ops = &clkops_omap2_dflt_wait, |
1605 | .id = 5, | ||
1606 | .init = &omap2_init_clksel_parent, | 1600 | .init = &omap2_init_clksel_parent, |
1607 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1601 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1608 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | 1602 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, |
@@ -1614,9 +1608,8 @@ static struct clk mcbsp5_fck = { | |||
1614 | }; | 1608 | }; |
1615 | 1609 | ||
1616 | static struct clk mcbsp1_fck = { | 1610 | static struct clk mcbsp1_fck = { |
1617 | .name = "mcbsp_fck", | 1611 | .name = "mcbsp1_fck", |
1618 | .ops = &clkops_omap2_dflt_wait, | 1612 | .ops = &clkops_omap2_dflt_wait, |
1619 | .id = 1, | ||
1620 | .init = &omap2_init_clksel_parent, | 1613 | .init = &omap2_init_clksel_parent, |
1621 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1614 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1622 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | 1615 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, |
@@ -1638,9 +1631,8 @@ static struct clk core_48m_fck = { | |||
1638 | }; | 1631 | }; |
1639 | 1632 | ||
1640 | static struct clk mcspi4_fck = { | 1633 | static struct clk mcspi4_fck = { |
1641 | .name = "mcspi_fck", | 1634 | .name = "mcspi4_fck", |
1642 | .ops = &clkops_omap2_dflt_wait, | 1635 | .ops = &clkops_omap2_dflt_wait, |
1643 | .id = 4, | ||
1644 | .parent = &core_48m_fck, | 1636 | .parent = &core_48m_fck, |
1645 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1637 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1646 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | 1638 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, |
@@ -1648,9 +1640,8 @@ static struct clk mcspi4_fck = { | |||
1648 | }; | 1640 | }; |
1649 | 1641 | ||
1650 | static struct clk mcspi3_fck = { | 1642 | static struct clk mcspi3_fck = { |
1651 | .name = "mcspi_fck", | 1643 | .name = "mcspi3_fck", |
1652 | .ops = &clkops_omap2_dflt_wait, | 1644 | .ops = &clkops_omap2_dflt_wait, |
1653 | .id = 3, | ||
1654 | .parent = &core_48m_fck, | 1645 | .parent = &core_48m_fck, |
1655 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1646 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1656 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | 1647 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, |
@@ -1658,9 +1649,8 @@ static struct clk mcspi3_fck = { | |||
1658 | }; | 1649 | }; |
1659 | 1650 | ||
1660 | static struct clk mcspi2_fck = { | 1651 | static struct clk mcspi2_fck = { |
1661 | .name = "mcspi_fck", | 1652 | .name = "mcspi2_fck", |
1662 | .ops = &clkops_omap2_dflt_wait, | 1653 | .ops = &clkops_omap2_dflt_wait, |
1663 | .id = 2, | ||
1664 | .parent = &core_48m_fck, | 1654 | .parent = &core_48m_fck, |
1665 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1655 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1666 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | 1656 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, |
@@ -1668,9 +1658,8 @@ static struct clk mcspi2_fck = { | |||
1668 | }; | 1658 | }; |
1669 | 1659 | ||
1670 | static struct clk mcspi1_fck = { | 1660 | static struct clk mcspi1_fck = { |
1671 | .name = "mcspi_fck", | 1661 | .name = "mcspi1_fck", |
1672 | .ops = &clkops_omap2_dflt_wait, | 1662 | .ops = &clkops_omap2_dflt_wait, |
1673 | .id = 1, | ||
1674 | .parent = &core_48m_fck, | 1663 | .parent = &core_48m_fck, |
1675 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1664 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1676 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | 1665 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, |
@@ -1879,9 +1868,8 @@ static struct clk usbtll_ick = { | |||
1879 | }; | 1868 | }; |
1880 | 1869 | ||
1881 | static struct clk mmchs3_ick = { | 1870 | static struct clk mmchs3_ick = { |
1882 | .name = "mmchs_ick", | 1871 | .name = "mmchs3_ick", |
1883 | .ops = &clkops_omap2_dflt_wait, | 1872 | .ops = &clkops_omap2_dflt_wait, |
1884 | .id = 2, | ||
1885 | .parent = &core_l4_ick, | 1873 | .parent = &core_l4_ick, |
1886 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1874 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1887 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | 1875 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, |
@@ -1931,9 +1919,8 @@ static struct clk des2_ick = { | |||
1931 | }; | 1919 | }; |
1932 | 1920 | ||
1933 | static struct clk mmchs2_ick = { | 1921 | static struct clk mmchs2_ick = { |
1934 | .name = "mmchs_ick", | 1922 | .name = "mmchs2_ick", |
1935 | .ops = &clkops_omap2_dflt_wait, | 1923 | .ops = &clkops_omap2_dflt_wait, |
1936 | .id = 1, | ||
1937 | .parent = &core_l4_ick, | 1924 | .parent = &core_l4_ick, |
1938 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1925 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1939 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | 1926 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, |
@@ -1942,7 +1929,7 @@ static struct clk mmchs2_ick = { | |||
1942 | }; | 1929 | }; |
1943 | 1930 | ||
1944 | static struct clk mmchs1_ick = { | 1931 | static struct clk mmchs1_ick = { |
1945 | .name = "mmchs_ick", | 1932 | .name = "mmchs1_ick", |
1946 | .ops = &clkops_omap2_dflt_wait, | 1933 | .ops = &clkops_omap2_dflt_wait, |
1947 | .parent = &core_l4_ick, | 1934 | .parent = &core_l4_ick, |
1948 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1935 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
@@ -1972,9 +1959,8 @@ static struct clk hdq_ick = { | |||
1972 | }; | 1959 | }; |
1973 | 1960 | ||
1974 | static struct clk mcspi4_ick = { | 1961 | static struct clk mcspi4_ick = { |
1975 | .name = "mcspi_ick", | 1962 | .name = "mcspi4_ick", |
1976 | .ops = &clkops_omap2_dflt_wait, | 1963 | .ops = &clkops_omap2_dflt_wait, |
1977 | .id = 4, | ||
1978 | .parent = &core_l4_ick, | 1964 | .parent = &core_l4_ick, |
1979 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1965 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1980 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | 1966 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, |
@@ -1983,9 +1969,8 @@ static struct clk mcspi4_ick = { | |||
1983 | }; | 1969 | }; |
1984 | 1970 | ||
1985 | static struct clk mcspi3_ick = { | 1971 | static struct clk mcspi3_ick = { |
1986 | .name = "mcspi_ick", | 1972 | .name = "mcspi3_ick", |
1987 | .ops = &clkops_omap2_dflt_wait, | 1973 | .ops = &clkops_omap2_dflt_wait, |
1988 | .id = 3, | ||
1989 | .parent = &core_l4_ick, | 1974 | .parent = &core_l4_ick, |
1990 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1975 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1991 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | 1976 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, |
@@ -1994,9 +1979,8 @@ static struct clk mcspi3_ick = { | |||
1994 | }; | 1979 | }; |
1995 | 1980 | ||
1996 | static struct clk mcspi2_ick = { | 1981 | static struct clk mcspi2_ick = { |
1997 | .name = "mcspi_ick", | 1982 | .name = "mcspi2_ick", |
1998 | .ops = &clkops_omap2_dflt_wait, | 1983 | .ops = &clkops_omap2_dflt_wait, |
1999 | .id = 2, | ||
2000 | .parent = &core_l4_ick, | 1984 | .parent = &core_l4_ick, |
2001 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1985 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2002 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | 1986 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, |
@@ -2005,9 +1989,8 @@ static struct clk mcspi2_ick = { | |||
2005 | }; | 1989 | }; |
2006 | 1990 | ||
2007 | static struct clk mcspi1_ick = { | 1991 | static struct clk mcspi1_ick = { |
2008 | .name = "mcspi_ick", | 1992 | .name = "mcspi1_ick", |
2009 | .ops = &clkops_omap2_dflt_wait, | 1993 | .ops = &clkops_omap2_dflt_wait, |
2010 | .id = 1, | ||
2011 | .parent = &core_l4_ick, | 1994 | .parent = &core_l4_ick, |
2012 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1995 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2013 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | 1996 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, |
@@ -2016,9 +1999,8 @@ static struct clk mcspi1_ick = { | |||
2016 | }; | 1999 | }; |
2017 | 2000 | ||
2018 | static struct clk i2c3_ick = { | 2001 | static struct clk i2c3_ick = { |
2019 | .name = "i2c_ick", | 2002 | .name = "i2c3_ick", |
2020 | .ops = &clkops_omap2_dflt_wait, | 2003 | .ops = &clkops_omap2_dflt_wait, |
2021 | .id = 3, | ||
2022 | .parent = &core_l4_ick, | 2004 | .parent = &core_l4_ick, |
2023 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2005 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2024 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | 2006 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, |
@@ -2027,9 +2009,8 @@ static struct clk i2c3_ick = { | |||
2027 | }; | 2009 | }; |
2028 | 2010 | ||
2029 | static struct clk i2c2_ick = { | 2011 | static struct clk i2c2_ick = { |
2030 | .name = "i2c_ick", | 2012 | .name = "i2c2_ick", |
2031 | .ops = &clkops_omap2_dflt_wait, | 2013 | .ops = &clkops_omap2_dflt_wait, |
2032 | .id = 2, | ||
2033 | .parent = &core_l4_ick, | 2014 | .parent = &core_l4_ick, |
2034 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2015 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2035 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | 2016 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, |
@@ -2038,9 +2019,8 @@ static struct clk i2c2_ick = { | |||
2038 | }; | 2019 | }; |
2039 | 2020 | ||
2040 | static struct clk i2c1_ick = { | 2021 | static struct clk i2c1_ick = { |
2041 | .name = "i2c_ick", | 2022 | .name = "i2c1_ick", |
2042 | .ops = &clkops_omap2_dflt_wait, | 2023 | .ops = &clkops_omap2_dflt_wait, |
2043 | .id = 1, | ||
2044 | .parent = &core_l4_ick, | 2024 | .parent = &core_l4_ick, |
2045 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2025 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2046 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | 2026 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, |
@@ -2089,9 +2069,8 @@ static struct clk gpt10_ick = { | |||
2089 | }; | 2069 | }; |
2090 | 2070 | ||
2091 | static struct clk mcbsp5_ick = { | 2071 | static struct clk mcbsp5_ick = { |
2092 | .name = "mcbsp_ick", | 2072 | .name = "mcbsp5_ick", |
2093 | .ops = &clkops_omap2_dflt_wait, | 2073 | .ops = &clkops_omap2_dflt_wait, |
2094 | .id = 5, | ||
2095 | .parent = &core_l4_ick, | 2074 | .parent = &core_l4_ick, |
2096 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2075 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2097 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | 2076 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, |
@@ -2100,9 +2079,8 @@ static struct clk mcbsp5_ick = { | |||
2100 | }; | 2079 | }; |
2101 | 2080 | ||
2102 | static struct clk mcbsp1_ick = { | 2081 | static struct clk mcbsp1_ick = { |
2103 | .name = "mcbsp_ick", | 2082 | .name = "mcbsp1_ick", |
2104 | .ops = &clkops_omap2_dflt_wait, | 2083 | .ops = &clkops_omap2_dflt_wait, |
2105 | .id = 1, | ||
2106 | .parent = &core_l4_ick, | 2084 | .parent = &core_l4_ick, |
2107 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2085 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2108 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | 2086 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, |
@@ -2897,9 +2875,8 @@ static struct clk gpt2_ick = { | |||
2897 | }; | 2875 | }; |
2898 | 2876 | ||
2899 | static struct clk mcbsp2_ick = { | 2877 | static struct clk mcbsp2_ick = { |
2900 | .name = "mcbsp_ick", | 2878 | .name = "mcbsp2_ick", |
2901 | .ops = &clkops_omap2_dflt_wait, | 2879 | .ops = &clkops_omap2_dflt_wait, |
2902 | .id = 2, | ||
2903 | .parent = &per_l4_ick, | 2880 | .parent = &per_l4_ick, |
2904 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2881 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2905 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | 2882 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, |
@@ -2908,9 +2885,8 @@ static struct clk mcbsp2_ick = { | |||
2908 | }; | 2885 | }; |
2909 | 2886 | ||
2910 | static struct clk mcbsp3_ick = { | 2887 | static struct clk mcbsp3_ick = { |
2911 | .name = "mcbsp_ick", | 2888 | .name = "mcbsp3_ick", |
2912 | .ops = &clkops_omap2_dflt_wait, | 2889 | .ops = &clkops_omap2_dflt_wait, |
2913 | .id = 3, | ||
2914 | .parent = &per_l4_ick, | 2890 | .parent = &per_l4_ick, |
2915 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2891 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2916 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | 2892 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, |
@@ -2919,9 +2895,8 @@ static struct clk mcbsp3_ick = { | |||
2919 | }; | 2895 | }; |
2920 | 2896 | ||
2921 | static struct clk mcbsp4_ick = { | 2897 | static struct clk mcbsp4_ick = { |
2922 | .name = "mcbsp_ick", | 2898 | .name = "mcbsp4_ick", |
2923 | .ops = &clkops_omap2_dflt_wait, | 2899 | .ops = &clkops_omap2_dflt_wait, |
2924 | .id = 4, | ||
2925 | .parent = &per_l4_ick, | 2900 | .parent = &per_l4_ick, |
2926 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2901 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2927 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | 2902 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, |
@@ -2936,9 +2911,8 @@ static const struct clksel mcbsp_234_clksel[] = { | |||
2936 | }; | 2911 | }; |
2937 | 2912 | ||
2938 | static struct clk mcbsp2_fck = { | 2913 | static struct clk mcbsp2_fck = { |
2939 | .name = "mcbsp_fck", | 2914 | .name = "mcbsp2_fck", |
2940 | .ops = &clkops_omap2_dflt_wait, | 2915 | .ops = &clkops_omap2_dflt_wait, |
2941 | .id = 2, | ||
2942 | .init = &omap2_init_clksel_parent, | 2916 | .init = &omap2_init_clksel_parent, |
2943 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2917 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
2944 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | 2918 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, |
@@ -2950,9 +2924,8 @@ static struct clk mcbsp2_fck = { | |||
2950 | }; | 2924 | }; |
2951 | 2925 | ||
2952 | static struct clk mcbsp3_fck = { | 2926 | static struct clk mcbsp3_fck = { |
2953 | .name = "mcbsp_fck", | 2927 | .name = "mcbsp3_fck", |
2954 | .ops = &clkops_omap2_dflt_wait, | 2928 | .ops = &clkops_omap2_dflt_wait, |
2955 | .id = 3, | ||
2956 | .init = &omap2_init_clksel_parent, | 2929 | .init = &omap2_init_clksel_parent, |
2957 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2930 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
2958 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | 2931 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, |
@@ -2964,9 +2937,8 @@ static struct clk mcbsp3_fck = { | |||
2964 | }; | 2937 | }; |
2965 | 2938 | ||
2966 | static struct clk mcbsp4_fck = { | 2939 | static struct clk mcbsp4_fck = { |
2967 | .name = "mcbsp_fck", | 2940 | .name = "mcbsp4_fck", |
2968 | .ops = &clkops_omap2_dflt_wait, | 2941 | .ops = &clkops_omap2_dflt_wait, |
2969 | .id = 4, | ||
2970 | .init = &omap2_init_clksel_parent, | 2942 | .init = &omap2_init_clksel_parent, |
2971 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2943 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
2972 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | 2944 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, |
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index e3b58afa5dcf..f244b172f9e1 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c | |||
@@ -408,8 +408,6 @@ static int clk_debugfs_register_one(struct clk *c) | |||
408 | char *p = s; | 408 | char *p = s; |
409 | 409 | ||
410 | p += sprintf(p, "%s", c->name); | 410 | p += sprintf(p, "%s", c->name); |
411 | if (c->id != 0) | ||
412 | sprintf(p, ":%d", c->id); | ||
413 | d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root); | 411 | d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root); |
414 | if (!d) | 412 | if (!d) |
415 | return -ENOMEM; | 413 | return -ENOMEM; |
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index 474c21e40eab..bbaba1b64a8a 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h | |||
@@ -120,7 +120,6 @@ struct clk { | |||
120 | struct list_head node; | 120 | struct list_head node; |
121 | const struct clkops *ops; | 121 | const struct clkops *ops; |
122 | const char *name; | 122 | const char *name; |
123 | int id; | ||
124 | struct clk *parent; | 123 | struct clk *parent; |
125 | struct list_head children; | 124 | struct list_head children; |
126 | struct list_head sibling; /* node for children */ | 125 | struct list_head sibling; /* node for children */ |