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-rw-r--r--arch/mips/dec/ecc-berr.c14
-rw-r--r--arch/mips/dec/int-handler.S18
-rw-r--r--arch/mips/dec/kn01-berr.c9
-rw-r--r--arch/mips/dec/kn02-irq.c9
-rw-r--r--arch/mips/dec/kn02xa-berr.c11
-rw-r--r--arch/mips/dec/prom/identify.c28
-rw-r--r--arch/mips/dec/setup.c16
7 files changed, 66 insertions, 39 deletions
diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c
index 8f3498aa43ab..cc24c5ed0c05 100644
--- a/arch/mips/dec/ecc-berr.c
+++ b/arch/mips/dec/ecc-berr.c
@@ -227,11 +227,11 @@ irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs)
227 */ 227 */
228static inline void dec_kn02_be_init(void) 228static inline void dec_kn02_be_init(void)
229{ 229{
230 volatile u32 *csr = (void *)KN02_CSR_BASE; 230 volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);
231 unsigned long flags; 231 unsigned long flags;
232 232
233 kn0x_erraddr = (void *)(KN02_SLOT_BASE + KN02_ERRADDR); 233 kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR);
234 kn0x_chksyn = (void *)(KN02_SLOT_BASE + KN02_CHKSYN); 234 kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN);
235 235
236 spin_lock_irqsave(&kn02_lock, flags); 236 spin_lock_irqsave(&kn02_lock, flags);
237 237
@@ -250,11 +250,11 @@ static inline void dec_kn02_be_init(void)
250 250
251static inline void dec_kn03_be_init(void) 251static inline void dec_kn03_be_init(void)
252{ 252{
253 volatile u32 *mcr = (void *)(KN03_SLOT_BASE + IOASIC_MCR); 253 volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR);
254 volatile u32 *mbcs = (void *)(KN4K_SLOT_BASE + KN4K_MB_CSR); 254 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
255 255
256 kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR); 256 kn0x_erraddr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_ERRADDR);
257 kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN); 257 kn0x_chksyn = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_CHKSYN);
258 258
259 /* 259 /*
260 * Set normal ECC detection and generation, enable ECC correction. 260 * Set normal ECC detection and generation, enable ECC correction.
diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S
index c89768d5c4e5..41fa372007bf 100644
--- a/arch/mips/dec/int-handler.S
+++ b/arch/mips/dec/int-handler.S
@@ -2,9 +2,9 @@
2 * arch/mips/dec/int-handler.S 2 * arch/mips/dec/int-handler.S
3 * 3 *
4 * Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen 4 * Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen
5 * Copyright (C) 2000, 2001, 2002, 2003 Maciej W. Rozycki 5 * Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki
6 * 6 *
7 * Written by Ralf Baechle and Andreas Busse, modified for DECStation 7 * Written by Ralf Baechle and Andreas Busse, modified for DECstation
8 * support by Paul Antoine and Harald Koerfgen. 8 * support by Paul Antoine and Harald Koerfgen.
9 * 9 *
10 * completly rewritten: 10 * completly rewritten:
@@ -14,11 +14,12 @@
14 * by Maciej W. Rozycki. 14 * by Maciej W. Rozycki.
15 */ 15 */
16#include <linux/config.h> 16#include <linux/config.h>
17
18#include <asm/addrspace.h>
17#include <asm/asm.h> 19#include <asm/asm.h>
18#include <asm/regdef.h>
19#include <asm/mipsregs.h> 20#include <asm/mipsregs.h>
21#include <asm/regdef.h>
20#include <asm/stackframe.h> 22#include <asm/stackframe.h>
21#include <asm/addrspace.h>
22 23
23#include <asm/dec/interrupts.h> 24#include <asm/dec/interrupts.h>
24#include <asm/dec/ioasic_addrs.h> 25#include <asm/dec/ioasic_addrs.h>
@@ -28,11 +29,14 @@
28#include <asm/dec/kn02xa.h> 29#include <asm/dec/kn02xa.h>
29#include <asm/dec/kn03.h> 30#include <asm/dec/kn03.h>
30 31
32#define KN02_CSR_BASE CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR)
33#define KN02XA_IOASIC_BASE CKSEG1ADDR(KN02XA_SLOT_BASE + IOASIC_IOCTL)
34#define KN03_IOASIC_BASE CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_IOCTL)
31 35
32 .text 36 .text
33 .set noreorder 37 .set noreorder
34/* 38/*
35 * decstation_handle_int: Interrupt handler for DECStations 39 * decstation_handle_int: Interrupt handler for DECstations
36 * 40 *
37 * We follow the model in the Indy interrupt code by David Miller, where he 41 * We follow the model in the Indy interrupt code by David Miller, where he
38 * says: a lot of complication here is taken away because: 42 * says: a lot of complication here is taken away because:
@@ -48,7 +52,7 @@
48 * 3) Linux only thinks in terms of all IRQs on or all IRQs 52 * 3) Linux only thinks in terms of all IRQs on or all IRQs
49 * off, nothing in between like BSD spl() brain-damage. 53 * off, nothing in between like BSD spl() brain-damage.
50 * 54 *
51 * Furthermore, the IRQs on the DECStations look basically (barring 55 * Furthermore, the IRQs on the DECstations look basically (barring
52 * software IRQs which we don't use at all) like... 56 * software IRQs which we don't use at all) like...
53 * 57 *
54 * DS2100/3100's, aka kn01, aka Pmax: 58 * DS2100/3100's, aka kn01, aka Pmax:
@@ -61,7 +65,7 @@
61 * 3 Lance Ethernet 65 * 3 Lance Ethernet
62 * 4 DZ11 serial 66 * 4 DZ11 serial
63 * 5 RTC 67 * 5 RTC
64 * 6 Memory Controller 68 * 6 Memory Controller & Video
65 * 7 FPU 69 * 7 FPU
66 * 70 *
67 * DS5000/200, aka kn02, aka 3max: 71 * DS5000/200, aka kn02, aka 3max:
diff --git a/arch/mips/dec/kn01-berr.c b/arch/mips/dec/kn01-berr.c
index 8ec7b30a90c1..b9271db9bc76 100644
--- a/arch/mips/dec/kn01-berr.c
+++ b/arch/mips/dec/kn01-berr.c
@@ -51,7 +51,7 @@ DEFINE_SPINLOCK(kn01_lock);
51 51
52static inline void dec_kn01_be_ack(void) 52static inline void dec_kn01_be_ack(void)
53{ 53{
54 volatile u16 *csr = (void *)(KN01_SLOT_BASE + KN01_CSR); 54 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
55 unsigned long flags; 55 unsigned long flags;
56 56
57 spin_lock_irqsave(&kn01_lock, flags); 57 spin_lock_irqsave(&kn01_lock, flags);
@@ -64,7 +64,8 @@ static inline void dec_kn01_be_ack(void)
64 64
65static int dec_kn01_be_backend(struct pt_regs *regs, int is_fixup, int invoker) 65static int dec_kn01_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
66{ 66{
67 volatile u32 *kn01_erraddr = (void *)(KN01_SLOT_BASE + KN01_ERRADDR); 67 volatile u32 *kn01_erraddr = (void *)CKSEG1ADDR(KN01_SLOT_BASE +
68 KN01_ERRADDR);
68 69
69 static const char excstr[] = "exception"; 70 static const char excstr[] = "exception";
70 static const char intstr[] = "interrupt"; 71 static const char intstr[] = "interrupt";
@@ -152,7 +153,7 @@ int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup)
152irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id, 153irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id,
153 struct pt_regs *regs) 154 struct pt_regs *regs)
154{ 155{
155 volatile u16 *csr = (void *)(KN01_SLOT_BASE + KN01_CSR); 156 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
156 int action; 157 int action;
157 158
158 if (!(*csr & KN01_CSR_MEMERR)) 159 if (!(*csr & KN01_CSR_MEMERR))
@@ -178,7 +179,7 @@ irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id,
178 179
179void __init dec_kn01_be_init(void) 180void __init dec_kn01_be_init(void)
180{ 181{
181 volatile u16 *csr = (void *)(KN01_SLOT_BASE + KN01_CSR); 182 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
182 unsigned long flags; 183 unsigned long flags;
183 184
184 spin_lock_irqsave(&kn01_lock, flags); 185 spin_lock_irqsave(&kn01_lock, flags);
diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c
index 644085e10403..898bed502a34 100644
--- a/arch/mips/dec/kn02-irq.c
+++ b/arch/mips/dec/kn02-irq.c
@@ -37,7 +37,8 @@ static int kn02_irq_base;
37 37
38static inline void unmask_kn02_irq(unsigned int irq) 38static inline void unmask_kn02_irq(unsigned int irq)
39{ 39{
40 volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; 40 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
41 KN02_CSR);
41 42
42 cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16)); 43 cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16));
43 *csr = cached_kn02_csr; 44 *csr = cached_kn02_csr;
@@ -45,7 +46,8 @@ static inline void unmask_kn02_irq(unsigned int irq)
45 46
46static inline void mask_kn02_irq(unsigned int irq) 47static inline void mask_kn02_irq(unsigned int irq)
47{ 48{
48 volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; 49 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
50 KN02_CSR);
49 51
50 cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16)); 52 cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16));
51 *csr = cached_kn02_csr; 53 *csr = cached_kn02_csr;
@@ -105,7 +107,8 @@ static struct hw_interrupt_type kn02_irq_type = {
105 107
106void __init init_kn02_irqs(int base) 108void __init init_kn02_irqs(int base)
107{ 109{
108 volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; 110 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
111 KN02_CSR);
109 unsigned long flags; 112 unsigned long flags;
110 int i; 113 int i;
111 114
diff --git a/arch/mips/dec/kn02xa-berr.c b/arch/mips/dec/kn02xa-berr.c
index c29909566628..6cd3f94f79fe 100644
--- a/arch/mips/dec/kn02xa-berr.c
+++ b/arch/mips/dec/kn02xa-berr.c
@@ -20,6 +20,7 @@
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/types.h> 21#include <linux/types.h>
22 22
23#include <asm/addrspace.h>
23#include <asm/system.h> 24#include <asm/system.h>
24#include <asm/traps.h> 25#include <asm/traps.h>
25 26
@@ -29,8 +30,8 @@
29 30
30static inline void dec_kn02xa_be_ack(void) 31static inline void dec_kn02xa_be_ack(void)
31{ 32{
32 volatile u32 *mer = (void *)KN02XA_MER; 33 volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER);
33 volatile u32 *mem_intr = (void *)KN02XA_MEM_INTR; 34 volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR);
34 35
35 *mer = KN02CA_MER_INTR; /* Clear errors; keep the ARC IRQ. */ 36 *mer = KN02CA_MER_INTR; /* Clear errors; keep the ARC IRQ. */
36 *mem_intr = 0; /* Any write clears the bus IRQ. */ 37 *mem_intr = 0; /* Any write clears the bus IRQ. */
@@ -40,8 +41,8 @@ static inline void dec_kn02xa_be_ack(void)
40static int dec_kn02xa_be_backend(struct pt_regs *regs, int is_fixup, 41static int dec_kn02xa_be_backend(struct pt_regs *regs, int is_fixup,
41 int invoker) 42 int invoker)
42{ 43{
43 volatile u32 *kn02xa_mer = (void *)KN02XA_MER; 44 volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER);
44 volatile u32 *kn02xa_ear = (void *)KN02XA_EAR; 45 volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR);
45 46
46 static const char excstr[] = "exception"; 47 static const char excstr[] = "exception";
47 static const char intstr[] = "interrupt"; 48 static const char intstr[] = "interrupt";
@@ -126,7 +127,7 @@ irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id,
126 127
127void __init dec_kn02xa_be_init(void) 128void __init dec_kn02xa_be_init(void)
128{ 129{
129 volatile u32 *mbcs = (void *)(KN4K_SLOT_BASE + KN4K_MB_CSR); 130 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
130 131
131 /* For KN04 we need to make sure EE (?) is enabled in the MB. */ 132 /* For KN04 we need to make sure EE (?) is enabled in the MB. */
132 if (current_cpu_data.cputype == CPU_R4000SC) 133 if (current_cpu_data.cputype == CPU_R4000SC)
diff --git a/arch/mips/dec/prom/identify.c b/arch/mips/dec/prom/identify.c
index 9380588cb15c..81d5e878ddce 100644
--- a/arch/mips/dec/prom/identify.c
+++ b/arch/mips/dec/prom/identify.c
@@ -2,7 +2,7 @@
2 * identify.c: machine identification code. 2 * identify.c: machine identification code.
3 * 3 *
4 * Copyright (C) 1998 Harald Koerfgen and Paul M. Antoine 4 * Copyright (C) 1998 Harald Koerfgen and Paul M. Antoine
5 * Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki 5 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
6 */ 6 */
7#include <linux/init.h> 7#include <linux/init.h>
8#include <linux/kernel.h> 8#include <linux/kernel.h>
@@ -12,6 +12,7 @@
12#include <linux/types.h> 12#include <linux/types.h>
13 13
14#include <asm/bootinfo.h> 14#include <asm/bootinfo.h>
15
15#include <asm/dec/ioasic.h> 16#include <asm/dec/ioasic.h>
16#include <asm/dec/ioasic_addrs.h> 17#include <asm/dec/ioasic_addrs.h>
17#include <asm/dec/kn01.h> 18#include <asm/dec/kn01.h>
@@ -21,6 +22,7 @@
21#include <asm/dec/kn03.h> 22#include <asm/dec/kn03.h>
22#include <asm/dec/kn230.h> 23#include <asm/dec/kn230.h>
23#include <asm/dec/prom.h> 24#include <asm/dec/prom.h>
25#include <asm/dec/system.h>
24 26
25#include "dectypes.h" 27#include "dectypes.h"
26 28
@@ -68,34 +70,44 @@ EXPORT_SYMBOL(dec_rtc_base);
68 70
69static inline void prom_init_kn01(void) 71static inline void prom_init_kn01(void)
70{ 72{
71 dec_rtc_base = (void *)KN01_RTC_BASE; 73 dec_kn_slot_base = KN01_SLOT_BASE;
72 dec_kn_slot_size = KN01_SLOT_SIZE; 74 dec_kn_slot_size = KN01_SLOT_SIZE;
75
76 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC);
73} 77}
74 78
75static inline void prom_init_kn230(void) 79static inline void prom_init_kn230(void)
76{ 80{
77 dec_rtc_base = (void *)KN01_RTC_BASE; 81 dec_kn_slot_base = KN01_SLOT_BASE;
78 dec_kn_slot_size = KN01_SLOT_SIZE; 82 dec_kn_slot_size = KN01_SLOT_SIZE;
83
84 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC);
79} 85}
80 86
81static inline void prom_init_kn02(void) 87static inline void prom_init_kn02(void)
82{ 88{
83 dec_rtc_base = (void *)KN02_RTC_BASE; 89 dec_kn_slot_base = KN02_SLOT_BASE;
84 dec_kn_slot_size = KN02_SLOT_SIZE; 90 dec_kn_slot_size = KN02_SLOT_SIZE;
91
92 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN02_RTC);
85} 93}
86 94
87static inline void prom_init_kn02xa(void) 95static inline void prom_init_kn02xa(void)
88{ 96{
89 ioasic_base = (void *)KN02XA_IOASIC_BASE; 97 dec_kn_slot_base = KN02XA_SLOT_BASE;
90 dec_rtc_base = (void *)KN02XA_RTC_BASE;
91 dec_kn_slot_size = IOASIC_SLOT_SIZE; 98 dec_kn_slot_size = IOASIC_SLOT_SIZE;
99
100 ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL);
101 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY);
92} 102}
93 103
94static inline void prom_init_kn03(void) 104static inline void prom_init_kn03(void)
95{ 105{
96 ioasic_base = (void *)KN03_IOASIC_BASE; 106 dec_kn_slot_base = KN03_SLOT_BASE;
97 dec_rtc_base = (void *)KN03_RTC_BASE;
98 dec_kn_slot_size = IOASIC_SLOT_SIZE; 107 dec_kn_slot_size = IOASIC_SLOT_SIZE;
108
109 ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL);
110 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY);
99} 111}
100 112
101 113
diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c
index f63fb9cd43c6..8861c3b22e4b 100644
--- a/arch/mips/dec/setup.c
+++ b/arch/mips/dec/setup.c
@@ -39,6 +39,7 @@
39#include <asm/dec/kn02ca.h> 39#include <asm/dec/kn02ca.h>
40#include <asm/dec/kn03.h> 40#include <asm/dec/kn03.h>
41#include <asm/dec/kn230.h> 41#include <asm/dec/kn230.h>
42#include <asm/dec/system.h>
42 43
43 44
44extern void dec_machine_restart(char *command); 45extern void dec_machine_restart(char *command);
@@ -48,10 +49,16 @@ extern irqreturn_t dec_intr_halt(int irq, void *dev_id, struct pt_regs *regs);
48 49
49extern asmlinkage void decstation_handle_int(void); 50extern asmlinkage void decstation_handle_int(void);
50 51
52unsigned long dec_kn_slot_base, dec_kn_slot_size;
53
54EXPORT_SYMBOL(dec_kn_slot_base);
55EXPORT_SYMBOL(dec_kn_slot_size);
56
51spinlock_t ioasic_ssr_lock; 57spinlock_t ioasic_ssr_lock;
52 58
53volatile u32 *ioasic_base; 59volatile u32 *ioasic_base;
54unsigned long dec_kn_slot_size; 60
61EXPORT_SYMBOL(ioasic_base);
55 62
56/* 63/*
57 * IRQ routing and priority tables. Priorites are set as follows: 64 * IRQ routing and priority tables. Priorites are set as follows:
@@ -78,6 +85,9 @@ unsigned long dec_kn_slot_size;
78int dec_interrupt[DEC_NR_INTS] = { 85int dec_interrupt[DEC_NR_INTS] = {
79 [0 ... DEC_NR_INTS - 1] = -1 86 [0 ... DEC_NR_INTS - 1] = -1
80}; 87};
88
89EXPORT_SYMBOL(dec_interrupt);
90
81int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = { 91int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
82 { { .i = ~0 }, { .p = dec_intr_unimplemented } }, 92 { { .i = ~0 }, { .p = dec_intr_unimplemented } },
83}; 93};
@@ -755,7 +765,3 @@ void __init arch_init_irq(void)
755 if (dec_interrupt[DEC_IRQ_HALT] >= 0) 765 if (dec_interrupt[DEC_IRQ_HALT] >= 0)
756 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq); 766 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
757} 767}
758
759EXPORT_SYMBOL(ioasic_base);
760EXPORT_SYMBOL(dec_kn_slot_size);
761EXPORT_SYMBOL(dec_interrupt);