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-rw-r--r--arch/x86/include/asm/uv/uv_mmrs.h153
1 files changed, 153 insertions, 0 deletions
diff --git a/arch/x86/include/asm/uv/uv_mmrs.h b/arch/x86/include/asm/uv/uv_mmrs.h
index dd627793a234..db68ac8a5ac2 100644
--- a/arch/x86/include/asm/uv/uv_mmrs.h
+++ b/arch/x86/include/asm/uv/uv_mmrs.h
@@ -1,3 +1,4 @@
1
1/* 2/*
2 * This file is subject to the terms and conditions of the GNU General Public 3 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive 4 * License. See the file "COPYING" in the main directory of this archive
@@ -243,6 +244,158 @@ union uvh_event_occurred0_u {
243#define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0 244#define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0
244 245
245/* ========================================================================= */ 246/* ========================================================================= */
247/* UVH_GR0_TLB_INT0_CONFIG */
248/* ========================================================================= */
249#define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL
250
251#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
252#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
253#define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8
254#define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
255#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11
256#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
257#define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12
258#define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
259#define UVH_GR0_TLB_INT0_CONFIG_P_SHFT 13
260#define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
261#define UVH_GR0_TLB_INT0_CONFIG_T_SHFT 15
262#define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
263#define UVH_GR0_TLB_INT0_CONFIG_M_SHFT 16
264#define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
265#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32
266#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
267
268union uvh_gr0_tlb_int0_config_u {
269 unsigned long v;
270 struct uvh_gr0_tlb_int0_config_s {
271 unsigned long vector_ : 8; /* RW */
272 unsigned long dm : 3; /* RW */
273 unsigned long destmode : 1; /* RW */
274 unsigned long status : 1; /* RO */
275 unsigned long p : 1; /* RO */
276 unsigned long rsvd_14 : 1; /* */
277 unsigned long t : 1; /* RO */
278 unsigned long m : 1; /* RW */
279 unsigned long rsvd_17_31: 15; /* */
280 unsigned long apic_id : 32; /* RW */
281 } s;
282};
283
284/* ========================================================================= */
285/* UVH_GR0_TLB_INT1_CONFIG */
286/* ========================================================================= */
287#define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL
288
289#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0
290#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
291#define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8
292#define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
293#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11
294#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
295#define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12
296#define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
297#define UVH_GR0_TLB_INT1_CONFIG_P_SHFT 13
298#define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
299#define UVH_GR0_TLB_INT1_CONFIG_T_SHFT 15
300#define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
301#define UVH_GR0_TLB_INT1_CONFIG_M_SHFT 16
302#define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
303#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32
304#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
305
306union uvh_gr0_tlb_int1_config_u {
307 unsigned long v;
308 struct uvh_gr0_tlb_int1_config_s {
309 unsigned long vector_ : 8; /* RW */
310 unsigned long dm : 3; /* RW */
311 unsigned long destmode : 1; /* RW */
312 unsigned long status : 1; /* RO */
313 unsigned long p : 1; /* RO */
314 unsigned long rsvd_14 : 1; /* */
315 unsigned long t : 1; /* RO */
316 unsigned long m : 1; /* RW */
317 unsigned long rsvd_17_31: 15; /* */
318 unsigned long apic_id : 32; /* RW */
319 } s;
320};
321
322/* ========================================================================= */
323/* UVH_GR1_TLB_INT0_CONFIG */
324/* ========================================================================= */
325#define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL
326
327#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0
328#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
329#define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8
330#define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
331#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11
332#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
333#define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12
334#define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
335#define UVH_GR1_TLB_INT0_CONFIG_P_SHFT 13
336#define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
337#define UVH_GR1_TLB_INT0_CONFIG_T_SHFT 15
338#define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
339#define UVH_GR1_TLB_INT0_CONFIG_M_SHFT 16
340#define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
341#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32
342#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
343
344union uvh_gr1_tlb_int0_config_u {
345 unsigned long v;
346 struct uvh_gr1_tlb_int0_config_s {
347 unsigned long vector_ : 8; /* RW */
348 unsigned long dm : 3; /* RW */
349 unsigned long destmode : 1; /* RW */
350 unsigned long status : 1; /* RO */
351 unsigned long p : 1; /* RO */
352 unsigned long rsvd_14 : 1; /* */
353 unsigned long t : 1; /* RO */
354 unsigned long m : 1; /* RW */
355 unsigned long rsvd_17_31: 15; /* */
356 unsigned long apic_id : 32; /* RW */
357 } s;
358};
359
360/* ========================================================================= */
361/* UVH_GR1_TLB_INT1_CONFIG */
362/* ========================================================================= */
363#define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL
364
365#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0
366#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
367#define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8
368#define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
369#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11
370#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
371#define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12
372#define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
373#define UVH_GR1_TLB_INT1_CONFIG_P_SHFT 13
374#define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
375#define UVH_GR1_TLB_INT1_CONFIG_T_SHFT 15
376#define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
377#define UVH_GR1_TLB_INT1_CONFIG_M_SHFT 16
378#define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
379#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32
380#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
381
382union uvh_gr1_tlb_int1_config_u {
383 unsigned long v;
384 struct uvh_gr1_tlb_int1_config_s {
385 unsigned long vector_ : 8; /* RW */
386 unsigned long dm : 3; /* RW */
387 unsigned long destmode : 1; /* RW */
388 unsigned long status : 1; /* RO */
389 unsigned long p : 1; /* RO */
390 unsigned long rsvd_14 : 1; /* */
391 unsigned long t : 1; /* RO */
392 unsigned long m : 1; /* RW */
393 unsigned long rsvd_17_31: 15; /* */
394 unsigned long apic_id : 32; /* RW */
395 } s;
396};
397
398/* ========================================================================= */
246/* UVH_INT_CMPB */ 399/* UVH_INT_CMPB */
247/* ========================================================================= */ 400/* ========================================================================= */
248#define UVH_INT_CMPB 0x22080UL 401#define UVH_INT_CMPB 0x22080UL