diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/cris/arch-v32/drivers/mach-a3/nandflash.c | 22 | ||||
-rw-r--r-- | arch/cris/arch-v32/drivers/mach-fs/nandflash.c | 22 |
2 files changed, 24 insertions, 20 deletions
diff --git a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c index 2fda3db0249d..01ed0be2d0d1 100644 --- a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c +++ b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c | |||
@@ -35,6 +35,11 @@ | |||
35 | #define ALE_BIT 11 | 35 | #define ALE_BIT 11 |
36 | #define CE_BIT 12 | 36 | #define CE_BIT 12 |
37 | 37 | ||
38 | struct mtd_info_wrapper { | ||
39 | struct mtd_info info; | ||
40 | struct nand_chip chip; | ||
41 | }; | ||
42 | |||
38 | /* Bitmask for control pins */ | 43 | /* Bitmask for control pins */ |
39 | #define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT)) | 44 | #define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT)) |
40 | 45 | ||
@@ -88,7 +93,7 @@ static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd, | |||
88 | /* | 93 | /* |
89 | * read device ready pin | 94 | * read device ready pin |
90 | */ | 95 | */ |
91 | int crisv32_device_ready(struct mtd_info *mtd) | 96 | static int crisv32_device_ready(struct mtd_info *mtd) |
92 | { | 97 | { |
93 | reg_pio_r_din din = REG_RD(pio, regi_pio, r_din); | 98 | reg_pio_r_din din = REG_RD(pio, regi_pio, r_din); |
94 | return din.rdy; | 99 | return din.rdy; |
@@ -102,6 +107,7 @@ struct mtd_info *__init crisv32_nand_flash_probe(void) | |||
102 | void __iomem *read_cs; | 107 | void __iomem *read_cs; |
103 | void __iomem *write_cs; | 108 | void __iomem *write_cs; |
104 | 109 | ||
110 | struct mtd_info_wrapper *wrapper; | ||
105 | struct nand_chip *this; | 111 | struct nand_chip *this; |
106 | int err = 0; | 112 | int err = 0; |
107 | 113 | ||
@@ -129,9 +135,8 @@ struct mtd_info *__init crisv32_nand_flash_probe(void) | |||
129 | REG_WR(pio, regi_pio, rw_oe, oe); | 135 | REG_WR(pio, regi_pio, rw_oe, oe); |
130 | 136 | ||
131 | /* Allocate memory for MTD device structure and private data */ | 137 | /* Allocate memory for MTD device structure and private data */ |
132 | crisv32_mtd = kmalloc(sizeof(struct mtd_info) + | 138 | wrapper = kzalloc(sizeof(struct mtd_info_wrapper), GFP_KERNEL); |
133 | sizeof(struct nand_chip), GFP_KERNEL); | 139 | if (!wrapper) { |
134 | if (!crisv32_mtd) { | ||
135 | printk(KERN_ERR "Unable to allocate CRISv32 NAND MTD " | 140 | printk(KERN_ERR "Unable to allocate CRISv32 NAND MTD " |
136 | "device structure.\n"); | 141 | "device structure.\n"); |
137 | err = -ENOMEM; | 142 | err = -ENOMEM; |
@@ -142,11 +147,8 @@ struct mtd_info *__init crisv32_nand_flash_probe(void) | |||
142 | rw_io_access0); | 147 | rw_io_access0); |
143 | 148 | ||
144 | /* Get pointer to private data */ | 149 | /* Get pointer to private data */ |
145 | this = (struct nand_chip *) (&crisv32_mtd[1]); | 150 | this = &wrapper->chip; |
146 | 151 | crisv32_mtd = &wrapper->info; | |
147 | /* Initialize structures */ | ||
148 | memset((char *) crisv32_mtd, 0, sizeof(struct mtd_info)); | ||
149 | memset((char *) this, 0, sizeof(struct nand_chip)); | ||
150 | 152 | ||
151 | /* Link the private data with the MTD structure */ | 153 | /* Link the private data with the MTD structure */ |
152 | crisv32_mtd->priv = this; | 154 | crisv32_mtd->priv = this; |
@@ -172,7 +174,7 @@ struct mtd_info *__init crisv32_nand_flash_probe(void) | |||
172 | return crisv32_mtd; | 174 | return crisv32_mtd; |
173 | 175 | ||
174 | out_mtd: | 176 | out_mtd: |
175 | kfree(crisv32_mtd); | 177 | kfree(wrapper); |
176 | return NULL; | 178 | return NULL; |
177 | } | 179 | } |
178 | 180 | ||
diff --git a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c b/arch/cris/arch-v32/drivers/mach-fs/nandflash.c index 5898ac71175d..aa01b134458a 100644 --- a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c +++ b/arch/cris/arch-v32/drivers/mach-fs/nandflash.c | |||
@@ -30,6 +30,11 @@ | |||
30 | #define ALE_BIT 6 | 30 | #define ALE_BIT 6 |
31 | #define BY_BIT 7 | 31 | #define BY_BIT 7 |
32 | 32 | ||
33 | struct mtd_info_wrapper { | ||
34 | struct mtd_info info; | ||
35 | struct nand_chip chip; | ||
36 | }; | ||
37 | |||
33 | /* Bitmask for control pins */ | 38 | /* Bitmask for control pins */ |
34 | #define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT)) | 39 | #define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT)) |
35 | 40 | ||
@@ -83,7 +88,7 @@ static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd, | |||
83 | /* | 88 | /* |
84 | * read device ready pin | 89 | * read device ready pin |
85 | */ | 90 | */ |
86 | int crisv32_device_ready(struct mtd_info *mtd) | 91 | static int crisv32_device_ready(struct mtd_info *mtd) |
87 | { | 92 | { |
88 | reg_gio_r_pa_din din = REG_RD(gio, regi_gio, r_pa_din); | 93 | reg_gio_r_pa_din din = REG_RD(gio, regi_gio, r_pa_din); |
89 | return ((din.data & (1 << BY_BIT)) >> BY_BIT); | 94 | return ((din.data & (1 << BY_BIT)) >> BY_BIT); |
@@ -100,13 +105,13 @@ struct mtd_info *__init crisv32_nand_flash_probe(void) | |||
100 | reg_bif_core_rw_grp3_cfg bif_cfg = REG_RD(bif_core, regi_bif_core, | 105 | reg_bif_core_rw_grp3_cfg bif_cfg = REG_RD(bif_core, regi_bif_core, |
101 | rw_grp3_cfg); | 106 | rw_grp3_cfg); |
102 | reg_gio_rw_pa_oe pa_oe = REG_RD(gio, regi_gio, rw_pa_oe); | 107 | reg_gio_rw_pa_oe pa_oe = REG_RD(gio, regi_gio, rw_pa_oe); |
108 | struct mtd_info_wrapper *wrapper; | ||
103 | struct nand_chip *this; | 109 | struct nand_chip *this; |
104 | int err = 0; | 110 | int err = 0; |
105 | 111 | ||
106 | /* Allocate memory for MTD device structure and private data */ | 112 | /* Allocate memory for MTD device structure and private data */ |
107 | crisv32_mtd = kmalloc(sizeof(struct mtd_info) + | 113 | wrapper = kzalloc(sizeof(struct mtd_info_wrapper), GFP_KERNEL); |
108 | sizeof(struct nand_chip), GFP_KERNEL); | 114 | if (!wrapper) { |
109 | if (!crisv32_mtd) { | ||
110 | printk(KERN_ERR "Unable to allocate CRISv32 NAND MTD " | 115 | printk(KERN_ERR "Unable to allocate CRISv32 NAND MTD " |
111 | "device structure.\n"); | 116 | "device structure.\n"); |
112 | err = -ENOMEM; | 117 | err = -ENOMEM; |
@@ -123,7 +128,8 @@ struct mtd_info *__init crisv32_nand_flash_probe(void) | |||
123 | } | 128 | } |
124 | 129 | ||
125 | /* Get pointer to private data */ | 130 | /* Get pointer to private data */ |
126 | this = (struct nand_chip *) (&crisv32_mtd[1]); | 131 | this = &wrapper->chip; |
132 | crisv32_mtd = &wrapper->info; | ||
127 | 133 | ||
128 | pa_oe.oe |= 1 << CE_BIT; | 134 | pa_oe.oe |= 1 << CE_BIT; |
129 | pa_oe.oe |= 1 << ALE_BIT; | 135 | pa_oe.oe |= 1 << ALE_BIT; |
@@ -135,10 +141,6 @@ struct mtd_info *__init crisv32_nand_flash_probe(void) | |||
135 | bif_cfg.gated_csp1 = regk_bif_core_wr; | 141 | bif_cfg.gated_csp1 = regk_bif_core_wr; |
136 | REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, bif_cfg); | 142 | REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, bif_cfg); |
137 | 143 | ||
138 | /* Initialize structures */ | ||
139 | memset((char *) crisv32_mtd, 0, sizeof(struct mtd_info)); | ||
140 | memset((char *) this, 0, sizeof(struct nand_chip)); | ||
141 | |||
142 | /* Link the private data with the MTD structure */ | 144 | /* Link the private data with the MTD structure */ |
143 | crisv32_mtd->priv = this; | 145 | crisv32_mtd->priv = this; |
144 | 146 | ||
@@ -166,7 +168,7 @@ out_ior: | |||
166 | iounmap((void *)read_cs); | 168 | iounmap((void *)read_cs); |
167 | iounmap((void *)write_cs); | 169 | iounmap((void *)write_cs); |
168 | out_mtd: | 170 | out_mtd: |
169 | kfree(crisv32_mtd); | 171 | kfree(wrapper); |
170 | return NULL; | 172 | return NULL; |
171 | } | 173 | } |
172 | 174 | ||