diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/x86/oprofile/op_model_ppro.c | 52 |
1 files changed, 26 insertions, 26 deletions
diff --git a/arch/x86/oprofile/op_model_ppro.c b/arch/x86/oprofile/op_model_ppro.c index c554f52cb808..eff431f6c57b 100644 --- a/arch/x86/oprofile/op_model_ppro.c +++ b/arch/x86/oprofile/op_model_ppro.c | |||
@@ -1,4 +1,4 @@ | |||
1 | /** | 1 | /* |
2 | * @file op_model_ppro.h | 2 | * @file op_model_ppro.h |
3 | * pentium pro / P6 model-specific MSR operations | 3 | * pentium pro / P6 model-specific MSR operations |
4 | * | 4 | * |
@@ -15,45 +15,45 @@ | |||
15 | #include <asm/msr.h> | 15 | #include <asm/msr.h> |
16 | #include <asm/apic.h> | 16 | #include <asm/apic.h> |
17 | #include <asm/nmi.h> | 17 | #include <asm/nmi.h> |
18 | 18 | ||
19 | #include "op_x86_model.h" | 19 | #include "op_x86_model.h" |
20 | #include "op_counter.h" | 20 | #include "op_counter.h" |
21 | 21 | ||
22 | #define NUM_COUNTERS 2 | 22 | #define NUM_COUNTERS 2 |
23 | #define NUM_CONTROLS 2 | 23 | #define NUM_CONTROLS 2 |
24 | 24 | ||
25 | #define CTR_IS_RESERVED(msrs,c) (msrs->counters[(c)].addr ? 1 : 0) | 25 | #define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0) |
26 | #define CTR_READ(l,h,msrs,c) do {rdmsr(msrs->counters[(c)].addr, (l), (h));} while (0) | 26 | #define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0) |
27 | #define CTR_32BIT_WRITE(l,msrs,c) \ | 27 | #define CTR_32BIT_WRITE(l, msrs, c) \ |
28 | do {wrmsr(msrs->counters[(c)].addr, -(u32)(l), 0);} while (0) | 28 | do {wrmsr(msrs->counters[(c)].addr, -(u32)(l), 0); } while (0) |
29 | #define CTR_OVERFLOWED(n) (!((n) & (1U<<31))) | 29 | #define CTR_OVERFLOWED(n) (!((n) & (1U<<31))) |
30 | 30 | ||
31 | #define CTRL_IS_RESERVED(msrs,c) (msrs->controls[(c)].addr ? 1 : 0) | 31 | #define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0) |
32 | #define CTRL_READ(l,h,msrs,c) do {rdmsr((msrs->controls[(c)].addr), (l), (h));} while (0) | 32 | #define CTRL_READ(l, h, msrs, c) do {rdmsr((msrs->controls[(c)].addr), (l), (h)); } while (0) |
33 | #define CTRL_WRITE(l,h,msrs,c) do {wrmsr((msrs->controls[(c)].addr), (l), (h));} while (0) | 33 | #define CTRL_WRITE(l, h, msrs, c) do {wrmsr((msrs->controls[(c)].addr), (l), (h)); } while (0) |
34 | #define CTRL_SET_ACTIVE(n) (n |= (1<<22)) | 34 | #define CTRL_SET_ACTIVE(n) (n |= (1<<22)) |
35 | #define CTRL_SET_INACTIVE(n) (n &= ~(1<<22)) | 35 | #define CTRL_SET_INACTIVE(n) (n &= ~(1<<22)) |
36 | #define CTRL_CLEAR(x) (x &= (1<<21)) | 36 | #define CTRL_CLEAR(x) (x &= (1<<21)) |
37 | #define CTRL_SET_ENABLE(val) (val |= 1<<20) | 37 | #define CTRL_SET_ENABLE(val) (val |= 1<<20) |
38 | #define CTRL_SET_USR(val,u) (val |= ((u & 1) << 16)) | 38 | #define CTRL_SET_USR(val, u) (val |= ((u & 1) << 16)) |
39 | #define CTRL_SET_KERN(val,k) (val |= ((k & 1) << 17)) | 39 | #define CTRL_SET_KERN(val, k) (val |= ((k & 1) << 17)) |
40 | #define CTRL_SET_UM(val, m) (val |= (m << 8)) | 40 | #define CTRL_SET_UM(val, m) (val |= (m << 8)) |
41 | #define CTRL_SET_EVENT(val, e) (val |= e) | 41 | #define CTRL_SET_EVENT(val, e) (val |= e) |
42 | 42 | ||
43 | static unsigned long reset_value[NUM_COUNTERS]; | 43 | static unsigned long reset_value[NUM_COUNTERS]; |
44 | 44 | ||
45 | static void ppro_fill_in_addresses(struct op_msrs * const msrs) | 45 | static void ppro_fill_in_addresses(struct op_msrs * const msrs) |
46 | { | 46 | { |
47 | int i; | 47 | int i; |
48 | 48 | ||
49 | for (i=0; i < NUM_COUNTERS; i++) { | 49 | for (i = 0; i < NUM_COUNTERS; i++) { |
50 | if (reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i)) | 50 | if (reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i)) |
51 | msrs->counters[i].addr = MSR_P6_PERFCTR0 + i; | 51 | msrs->counters[i].addr = MSR_P6_PERFCTR0 + i; |
52 | else | 52 | else |
53 | msrs->counters[i].addr = 0; | 53 | msrs->counters[i].addr = 0; |
54 | } | 54 | } |
55 | 55 | ||
56 | for (i=0; i < NUM_CONTROLS; i++) { | 56 | for (i = 0; i < NUM_CONTROLS; i++) { |
57 | if (reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i)) | 57 | if (reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i)) |
58 | msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i; | 58 | msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i; |
59 | else | 59 | else |
@@ -69,23 +69,23 @@ static void ppro_setup_ctrs(struct op_msrs const * const msrs) | |||
69 | 69 | ||
70 | /* clear all counters */ | 70 | /* clear all counters */ |
71 | for (i = 0 ; i < NUM_CONTROLS; ++i) { | 71 | for (i = 0 ; i < NUM_CONTROLS; ++i) { |
72 | if (unlikely(!CTRL_IS_RESERVED(msrs,i))) | 72 | if (unlikely(!CTRL_IS_RESERVED(msrs, i))) |
73 | continue; | 73 | continue; |
74 | CTRL_READ(low, high, msrs, i); | 74 | CTRL_READ(low, high, msrs, i); |
75 | CTRL_CLEAR(low); | 75 | CTRL_CLEAR(low); |
76 | CTRL_WRITE(low, high, msrs, i); | 76 | CTRL_WRITE(low, high, msrs, i); |
77 | } | 77 | } |
78 | 78 | ||
79 | /* avoid a false detection of ctr overflows in NMI handler */ | 79 | /* avoid a false detection of ctr overflows in NMI handler */ |
80 | for (i = 0; i < NUM_COUNTERS; ++i) { | 80 | for (i = 0; i < NUM_COUNTERS; ++i) { |
81 | if (unlikely(!CTR_IS_RESERVED(msrs,i))) | 81 | if (unlikely(!CTR_IS_RESERVED(msrs, i))) |
82 | continue; | 82 | continue; |
83 | CTR_32BIT_WRITE(1, msrs, i); | 83 | CTR_32BIT_WRITE(1, msrs, i); |
84 | } | 84 | } |
85 | 85 | ||
86 | /* enable active counters */ | 86 | /* enable active counters */ |
87 | for (i = 0; i < NUM_COUNTERS; ++i) { | 87 | for (i = 0; i < NUM_COUNTERS; ++i) { |
88 | if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs,i))) { | 88 | if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) { |
89 | reset_value[i] = counter_config[i].count; | 89 | reset_value[i] = counter_config[i].count; |
90 | 90 | ||
91 | CTR_32BIT_WRITE(counter_config[i].count, msrs, i); | 91 | CTR_32BIT_WRITE(counter_config[i].count, msrs, i); |
@@ -104,13 +104,13 @@ static void ppro_setup_ctrs(struct op_msrs const * const msrs) | |||
104 | } | 104 | } |
105 | } | 105 | } |
106 | 106 | ||
107 | 107 | ||
108 | static int ppro_check_ctrs(struct pt_regs * const regs, | 108 | static int ppro_check_ctrs(struct pt_regs * const regs, |
109 | struct op_msrs const * const msrs) | 109 | struct op_msrs const * const msrs) |
110 | { | 110 | { |
111 | unsigned int low, high; | 111 | unsigned int low, high; |
112 | int i; | 112 | int i; |
113 | 113 | ||
114 | for (i = 0 ; i < NUM_COUNTERS; ++i) { | 114 | for (i = 0 ; i < NUM_COUNTERS; ++i) { |
115 | if (!reset_value[i]) | 115 | if (!reset_value[i]) |
116 | continue; | 116 | continue; |
@@ -135,10 +135,10 @@ static int ppro_check_ctrs(struct pt_regs * const regs, | |||
135 | return 1; | 135 | return 1; |
136 | } | 136 | } |
137 | 137 | ||
138 | 138 | ||
139 | static void ppro_start(struct op_msrs const * const msrs) | 139 | static void ppro_start(struct op_msrs const * const msrs) |
140 | { | 140 | { |
141 | unsigned int low,high; | 141 | unsigned int low, high; |
142 | int i; | 142 | int i; |
143 | 143 | ||
144 | for (i = 0; i < NUM_COUNTERS; ++i) { | 144 | for (i = 0; i < NUM_COUNTERS; ++i) { |
@@ -153,7 +153,7 @@ static void ppro_start(struct op_msrs const * const msrs) | |||
153 | 153 | ||
154 | static void ppro_stop(struct op_msrs const * const msrs) | 154 | static void ppro_stop(struct op_msrs const * const msrs) |
155 | { | 155 | { |
156 | unsigned int low,high; | 156 | unsigned int low, high; |
157 | int i; | 157 | int i; |
158 | 158 | ||
159 | for (i = 0; i < NUM_COUNTERS; ++i) { | 159 | for (i = 0; i < NUM_COUNTERS; ++i) { |
@@ -170,11 +170,11 @@ static void ppro_shutdown(struct op_msrs const * const msrs) | |||
170 | int i; | 170 | int i; |
171 | 171 | ||
172 | for (i = 0 ; i < NUM_COUNTERS ; ++i) { | 172 | for (i = 0 ; i < NUM_COUNTERS ; ++i) { |
173 | if (CTR_IS_RESERVED(msrs,i)) | 173 | if (CTR_IS_RESERVED(msrs, i)) |
174 | release_perfctr_nmi(MSR_P6_PERFCTR0 + i); | 174 | release_perfctr_nmi(MSR_P6_PERFCTR0 + i); |
175 | } | 175 | } |
176 | for (i = 0 ; i < NUM_CONTROLS ; ++i) { | 176 | for (i = 0 ; i < NUM_CONTROLS ; ++i) { |
177 | if (CTRL_IS_RESERVED(msrs,i)) | 177 | if (CTRL_IS_RESERVED(msrs, i)) |
178 | release_evntsel_nmi(MSR_P6_EVNTSEL0 + i); | 178 | release_evntsel_nmi(MSR_P6_EVNTSEL0 + i); |
179 | } | 179 | } |
180 | } | 180 | } |