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-rw-r--r--arch/arm/mach-davinci/Kconfig9
-rw-r--r--arch/arm/mach-davinci/Makefile5
-rw-r--r--arch/arm/mach-davinci/board-dm644x-evm.c292
-rw-r--r--arch/arm/mach-davinci/dm644x.c461
-rw-r--r--arch/arm/mach-davinci/include/mach/board-dm6446evm.h20
-rw-r--r--arch/arm/mach-davinci/include/mach/common.h6
-rw-r--r--arch/arm/mach-davinci/include/mach/dm644x.h37
7 files changed, 791 insertions, 39 deletions
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index f18090e78e30..a9c78bc72b84 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -4,19 +4,18 @@ menu "TI DaVinci Implementations"
4 4
5comment "DaVinci Core Type" 5comment "DaVinci Core Type"
6 6
7config ARCH_DAVINCI644x 7config ARCH_DAVINCI_DM644x
8 default y
9 bool "DaVinci 644x based system" 8 bool "DaVinci 644x based system"
10 9
11comment "DaVinci Board Type" 10comment "DaVinci Board Type"
12 11
13config MACH_DAVINCI_EVM 12config MACH_DAVINCI_EVM
14 bool "TI DaVinci EVM" 13 bool "TI DM644x EVM"
15 default y 14 default y
16 depends on ARCH_DAVINCI644x 15 depends on ARCH_DAVINCI_DM644x
17 help 16 help
18 Configure this option to specify the whether the board used 17 Configure this option to specify the whether the board used
19 for development is a DaVinci EVM 18 for development is a DM644x EVM
20 19
21 20
22config DAVINCI_MUX 21config DAVINCI_MUX
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index b27871af4fcf..1674661942f3 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -9,5 +9,8 @@ obj-y := time.o irq.o clock.o serial.o io.o id.o psc.o \
9 9
10obj-$(CONFIG_DAVINCI_MUX) += mux.o 10obj-$(CONFIG_DAVINCI_MUX) += mux.o
11 11
12# Chip specific
13obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o
14
12# Board specific 15# Board specific
13obj-$(CONFIG_MACH_DAVINCI_EVM) += board-evm.o 16obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index c2701d740a1d..5387e6b20405 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -15,15 +15,19 @@
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/gpio.h> 16#include <linux/gpio.h>
17#include <linux/leds.h> 17#include <linux/leds.h>
18#include <linux/memory.h>
18 19
19#include <linux/i2c.h> 20#include <linux/i2c.h>
20#include <linux/i2c/pcf857x.h> 21#include <linux/i2c/pcf857x.h>
21#include <linux/i2c/at24.h> 22#include <linux/i2c/at24.h>
22 23#include <linux/etherdevice.h>
23#include <linux/mtd/mtd.h> 24#include <linux/mtd/mtd.h>
25#include <linux/mtd/nand.h>
24#include <linux/mtd/partitions.h> 26#include <linux/mtd/partitions.h>
25#include <linux/mtd/physmap.h> 27#include <linux/mtd/physmap.h>
26#include <linux/io.h> 28#include <linux/io.h>
29#include <linux/phy.h>
30#include <linux/clk.h>
27 31
28#include <asm/setup.h> 32#include <asm/setup.h>
29#include <asm/mach-types.h> 33#include <asm/mach-types.h>
@@ -32,28 +36,34 @@
32#include <asm/mach/map.h> 36#include <asm/mach/map.h>
33#include <asm/mach/flash.h> 37#include <asm/mach/flash.h>
34 38
35#include <mach/hardware.h> 39#include <mach/dm644x.h>
36#include <mach/common.h> 40#include <mach/common.h>
37#include <mach/i2c.h> 41#include <mach/i2c.h>
42#include <mach/serial.h>
43#include <mach/mux.h>
44#include <mach/psc.h>
45#include <mach/nand.h>
46
47#define DM644X_EVM_PHY_MASK (0x2)
48#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
38 49
39#define DAVINCI_CFC_ATA_BASE 0x01C66000 50#define DAVINCI_CFC_ATA_BASE 0x01C66000
40#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
41 51
42/* other misc. init functions */ 52#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
43void __init davinci_psc_init(void); 53#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
44void __init davinci_irq_init(void); 54#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
45void __init davinci_map_common_io(void); 55#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
46void __init davinci_init_common_hw(void); 56#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
47 57
48#if defined(CONFIG_MTD_PHYSMAP) || \ 58#define LXT971_PHY_ID (0x001378e2)
49 defined(CONFIG_MTD_PHYSMAP_MODULE) 59#define LXT971_PHY_MASK (0xfffffff0)
50 60
51static struct mtd_partition davinci_evm_norflash_partitions[] = { 61static struct mtd_partition davinci_evm_norflash_partitions[] = {
52 /* bootloader (U-Boot, etc) in first 4 sectors */ 62 /* bootloader (UBL, U-Boot, etc) in first 5 sectors */
53 { 63 {
54 .name = "bootloader", 64 .name = "bootloader",
55 .offset = 0, 65 .offset = 0,
56 .size = 4 * SZ_64K, 66 .size = 5 * SZ_64K,
57 .mask_flags = MTD_WRITEABLE, /* force read-only */ 67 .mask_flags = MTD_WRITEABLE, /* force read-only */
58 }, 68 },
59 /* bootloader params in the next 1 sectors */ 69 /* bootloader params in the next 1 sectors */
@@ -103,10 +113,60 @@ static struct platform_device davinci_evm_norflash_device = {
103 .resource = &davinci_evm_norflash_resource, 113 .resource = &davinci_evm_norflash_resource,
104}; 114};
105 115
106#endif 116struct mtd_partition davinci_evm_nandflash_partition[] = {
117 /* 5 MB space at the beginning for bootloader and kernel */
118 {
119 .name = "NAND filesystem",
120 .offset = 5 * SZ_1M,
121 .size = MTDPART_SIZ_FULL,
122 .mask_flags = 0,
123 }
124};
107 125
108#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ 126static struct davinci_nand_pdata davinci_evm_nandflash_data = {
109 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) 127 .parts = davinci_evm_nandflash_partition,
128 .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition),
129 .ecc_mode = NAND_ECC_HW,
130};
131
132static struct resource davinci_evm_nandflash_resource[] = {
133 {
134 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
135 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
136 .flags = IORESOURCE_MEM,
137 }, {
138 .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
139 .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
140 .flags = IORESOURCE_MEM,
141 },
142};
143
144static struct platform_device davinci_evm_nandflash_device = {
145 .name = "davinci_nand",
146 .id = 0,
147 .dev = {
148 .platform_data = &davinci_evm_nandflash_data,
149 },
150 .num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource),
151 .resource = davinci_evm_nandflash_resource,
152};
153
154static u64 davinci_fb_dma_mask = DMA_32BIT_MASK;
155
156static struct platform_device davinci_fb_device = {
157 .name = "davincifb",
158 .id = -1,
159 .dev = {
160 .dma_mask = &davinci_fb_dma_mask,
161 .coherent_dma_mask = DMA_32BIT_MASK,
162 },
163 .num_resources = 0,
164};
165
166static struct platform_device rtc_dev = {
167 .name = "rtc_davinci_evm",
168 .id = -1,
169};
110 170
111static struct resource ide_resources[] = { 171static struct resource ide_resources[] = {
112 { 172 {
@@ -121,7 +181,7 @@ static struct resource ide_resources[] = {
121 }, 181 },
122}; 182};
123 183
124static u64 ide_dma_mask = DMA_BIT_MASK(32); 184static u64 ide_dma_mask = DMA_32BIT_MASK;
125 185
126static struct platform_device ide_dev = { 186static struct platform_device ide_dev = {
127 .name = "palm_bk3710", 187 .name = "palm_bk3710",
@@ -130,12 +190,10 @@ static struct platform_device ide_dev = {
130 .num_resources = ARRAY_SIZE(ide_resources), 190 .num_resources = ARRAY_SIZE(ide_resources),
131 .dev = { 191 .dev = {
132 .dma_mask = &ide_dma_mask, 192 .dma_mask = &ide_dma_mask,
133 .coherent_dma_mask = DMA_BIT_MASK(32), 193 .coherent_dma_mask = DMA_32BIT_MASK,
134 }, 194 },
135}; 195};
136 196
137#endif
138
139/*----------------------------------------------------------------------*/ 197/*----------------------------------------------------------------------*/
140 198
141/* 199/*
@@ -314,7 +372,9 @@ evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
314 gpio_request(gpio + 7, "nCF_SEL"); 372 gpio_request(gpio + 7, "nCF_SEL");
315 gpio_direction_output(gpio + 7, 1); 373 gpio_direction_output(gpio + 7, 1);
316 374
317 /* irlml6401 sustains over 3A, switches 5V in under 8 msec */ 375 /* irlml6401 switches over 1A, in under 8 msec;
376 * now it can be managed by nDRV_VBUS ...
377 */
318 setup_usb(500, 8); 378 setup_usb(500, 8);
319 379
320 return 0; 380 return 0;
@@ -346,14 +406,120 @@ static struct pcf857x_platform_data pcf_data_u35 = {
346 * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL) 406 * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL)
347 * - ... newer boards may have more 407 * - ... newer boards may have more
348 */ 408 */
409static struct memory_accessor *at24_mem_acc;
410
411static void at24_setup(struct memory_accessor *mem_acc, void *context)
412{
413 DECLARE_MAC_BUF(mac_str);
414 char mac_addr[6];
415
416 at24_mem_acc = mem_acc;
417
418 /* Read MAC addr from EEPROM */
419 if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x7f00, 6) == 6) {
420 printk(KERN_INFO "Read MAC addr from EEPROM: %s\n",
421 print_mac(mac_str, mac_addr));
422 }
423}
424
349static struct at24_platform_data eeprom_info = { 425static struct at24_platform_data eeprom_info = {
350 .byte_len = (256*1024) / 8, 426 .byte_len = (256*1024) / 8,
351 .page_size = 64, 427 .page_size = 64,
352 .flags = AT24_FLAG_ADDR16, 428 .flags = AT24_FLAG_ADDR16,
429 .setup = at24_setup,
430};
431
432int dm6446evm_eeprom_read(void *buf, off_t off, size_t count)
433{
434 if (at24_mem_acc)
435 return at24_mem_acc->read(at24_mem_acc, buf, off, count);
436 return -ENODEV;
437}
438EXPORT_SYMBOL(dm6446evm_eeprom_read);
439
440int dm6446evm_eeprom_write(void *buf, off_t off, size_t count)
441{
442 if (at24_mem_acc)
443 return at24_mem_acc->write(at24_mem_acc, buf, off, count);
444 return -ENODEV;
445}
446EXPORT_SYMBOL(dm6446evm_eeprom_write);
447
448/*
449 * MSP430 supports RTC, card detection, input from IR remote, and
450 * a bit more. It triggers interrupts on GPIO(7) from pressing
451 * buttons on the IR remote, and for card detect switches.
452 */
453static struct i2c_client *dm6446evm_msp;
454
455static int dm6446evm_msp_probe(struct i2c_client *client,
456 const struct i2c_device_id *id)
457{
458 dm6446evm_msp = client;
459 return 0;
460}
461
462static int dm6446evm_msp_remove(struct i2c_client *client)
463{
464 dm6446evm_msp = NULL;
465 return 0;
466}
467
468static const struct i2c_device_id dm6446evm_msp_ids[] = {
469 { "dm6446evm_msp", 0, },
470 { /* end of list */ },
471};
472
473static struct i2c_driver dm6446evm_msp_driver = {
474 .driver.name = "dm6446evm_msp",
475 .id_table = dm6446evm_msp_ids,
476 .probe = dm6446evm_msp_probe,
477 .remove = dm6446evm_msp_remove,
353}; 478};
354 479
480static int dm6444evm_msp430_get_pins(void)
481{
482 static const char txbuf[2] = { 2, 4, };
483 char buf[4];
484 struct i2c_msg msg[2] = {
485 {
486 .addr = dm6446evm_msp->addr,
487 .flags = 0,
488 .len = 2,
489 .buf = (void __force *)txbuf,
490 },
491 {
492 .addr = dm6446evm_msp->addr,
493 .flags = I2C_M_RD,
494 .len = 4,
495 .buf = buf,
496 },
497 };
498 int status;
499
500 if (!dm6446evm_msp)
501 return -ENXIO;
502
503 /* Command 4 == get input state, returns port 2 and port3 data
504 * S Addr W [A] len=2 [A] cmd=4 [A]
505 * RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P
506 */
507 status = i2c_transfer(dm6446evm_msp->adapter, msg, 2);
508 if (status < 0)
509 return status;
510
511 dev_dbg(&dm6446evm_msp->dev,
512 "PINS: %02x %02x %02x %02x\n",
513 buf[0], buf[1], buf[2], buf[3]);
514
515 return (buf[3] << 8) | buf[2];
516}
517
355static struct i2c_board_info __initdata i2c_info[] = { 518static struct i2c_board_info __initdata i2c_info[] = {
356 { 519 {
520 I2C_BOARD_INFO("dm6446evm_msp", 0x23),
521 },
522 {
357 I2C_BOARD_INFO("pcf8574", 0x38), 523 I2C_BOARD_INFO("pcf8574", 0x38),
358 .platform_data = &pcf_data_u2, 524 .platform_data = &pcf_data_u2,
359 }, 525 },
@@ -371,7 +537,6 @@ static struct i2c_board_info __initdata i2c_info[] = {
371 }, 537 },
372 /* ALSO: 538 /* ALSO:
373 * - tvl320aic33 audio codec (0x1b) 539 * - tvl320aic33 audio codec (0x1b)
374 * - msp430 microcontroller (0x23)
375 * - tvp5146 video decoder (0x5d) 540 * - tvp5146 video decoder (0x5d)
376 */ 541 */
377}; 542};
@@ -387,40 +552,101 @@ static struct davinci_i2c_platform_data i2c_pdata = {
387static void __init evm_init_i2c(void) 552static void __init evm_init_i2c(void)
388{ 553{
389 davinci_init_i2c(&i2c_pdata); 554 davinci_init_i2c(&i2c_pdata);
555 i2c_add_driver(&dm6446evm_msp_driver);
390 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); 556 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
391} 557}
392 558
393static struct platform_device *davinci_evm_devices[] __initdata = { 559static struct platform_device *davinci_evm_devices[] __initdata = {
394#if defined(CONFIG_MTD_PHYSMAP) || \ 560 &davinci_fb_device,
395 defined(CONFIG_MTD_PHYSMAP_MODULE) 561 &rtc_dev,
396 &davinci_evm_norflash_device, 562};
397#endif 563
398#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ 564static struct davinci_uart_config uart_config __initdata = {
399 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) 565 .enabled_uarts = (1 << 0),
400 &ide_dev,
401#endif
402}; 566};
403 567
404static void __init 568static void __init
405davinci_evm_map_io(void) 569davinci_evm_map_io(void)
406{ 570{
407 davinci_map_common_io(); 571 davinci_map_common_io();
572 dm644x_init();
408} 573}
409 574
410static __init void davinci_evm_init(void) 575static int davinci_phy_fixup(struct phy_device *phydev)
411{ 576{
577 unsigned int control;
578 /* CRITICAL: Fix for increasing PHY signal drive strength for
579 * TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY
580 * signal strength was low causing TX to fail randomly. The
581 * fix is to Set bit 11 (Increased MII drive strength) of PHY
582 * register 26 (Digital Config register) on this phy. */
583 control = phy_read(phydev, 26);
584 phy_write(phydev, 26, (control | 0x800));
585 return 0;
586}
587
412#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ 588#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
413 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) 589 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
590#define HAS_ATA 1
591#else
592#define HAS_ATA 0
593#endif
594
414#if defined(CONFIG_MTD_PHYSMAP) || \ 595#if defined(CONFIG_MTD_PHYSMAP) || \
415 defined(CONFIG_MTD_PHYSMAP_MODULE) 596 defined(CONFIG_MTD_PHYSMAP_MODULE)
416 printk(KERN_WARNING "WARNING: both IDE and NOR flash are enabled, " 597#define HAS_NOR 1
417 "but share pins.\n\t Disable IDE for NOR support.\n"); 598#else
599#define HAS_NOR 0
418#endif 600#endif
601
602#if defined(CONFIG_MTD_NAND_DAVINCI) || \
603 defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
604#define HAS_NAND 1
605#else
606#define HAS_NAND 0
419#endif 607#endif
420 608
609static __init void davinci_evm_init(void)
610{
611 struct clk *aemif_clk;
612
613 aemif_clk = clk_get(NULL, "aemif");
614 clk_enable(aemif_clk);
615
616 if (HAS_ATA) {
617 if (HAS_NAND || HAS_NOR)
618 pr_warning("WARNING: both IDE and Flash are "
619 "enabled, but they share AEMIF pins.\n"
620 "\tDisable IDE for NAND/NOR support.\n");
621 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
622 davinci_cfg_reg(DM644X_ATAEN);
623 davinci_cfg_reg(DM644X_HDIREN);
624 platform_device_register(&ide_dev);
625 } else if (HAS_NAND || HAS_NOR) {
626 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
627 davinci_cfg_reg(DM644X_ATAEN_DISABLE);
628
629 /* only one device will be jumpered and detected */
630 if (HAS_NAND) {
631 platform_device_register(&davinci_evm_nandflash_device);
632 evm_leds[7].default_trigger = "nand-disk";
633 if (HAS_NOR)
634 pr_warning("WARNING: both NAND and NOR flash "
635 "are enabled; disable one of them.\n");
636 } else if (HAS_NOR)
637 platform_device_register(&davinci_evm_norflash_device);
638 }
639
421 platform_add_devices(davinci_evm_devices, 640 platform_add_devices(davinci_evm_devices,
422 ARRAY_SIZE(davinci_evm_devices)); 641 ARRAY_SIZE(davinci_evm_devices));
423 evm_init_i2c(); 642 evm_init_i2c();
643
644 davinci_serial_init(&uart_config);
645
646 /* Register the fixup for PHY on DaVinci */
647 phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
648 davinci_phy_fixup);
649
424} 650}
425 651
426static __init void davinci_evm_irq_init(void) 652static __init void davinci_evm_irq_init(void)
@@ -428,7 +654,7 @@ static __init void davinci_evm_irq_init(void)
428 davinci_irq_init(); 654 davinci_irq_init();
429} 655}
430 656
431MACHINE_START(DAVINCI_EVM, "DaVinci EVM") 657MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
432 /* Maintainer: MontaVista Software <source@mvista.com> */ 658 /* Maintainer: MontaVista Software <source@mvista.com> */
433 .phys_io = IO_PHYS, 659 .phys_io = IO_PHYS,
434 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, 660 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
new file mode 100644
index 000000000000..d428ef192eac
--- /dev/null
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -0,0 +1,461 @@
1/*
2 * TI DaVinci DM644x chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/clk.h>
14#include <linux/platform_device.h>
15
16#include <mach/dm644x.h>
17#include <mach/clock.h>
18#include <mach/cputype.h>
19#include <mach/edma.h>
20#include <mach/irqs.h>
21#include <mach/psc.h>
22#include <mach/mux.h>
23
24#include "clock.h"
25#include "mux.h"
26
27/*
28 * Device specific clocks
29 */
30#define DM644X_REF_FREQ 27000000
31
32static struct pll_data pll1_data = {
33 .num = 1,
34 .phys_base = DAVINCI_PLL1_BASE,
35};
36
37static struct pll_data pll2_data = {
38 .num = 2,
39 .phys_base = DAVINCI_PLL2_BASE,
40};
41
42static struct clk ref_clk = {
43 .name = "ref_clk",
44 .rate = DM644X_REF_FREQ,
45};
46
47static struct clk pll1_clk = {
48 .name = "pll1",
49 .parent = &ref_clk,
50 .pll_data = &pll1_data,
51 .flags = CLK_PLL,
52};
53
54static struct clk pll1_sysclk1 = {
55 .name = "pll1_sysclk1",
56 .parent = &pll1_clk,
57 .flags = CLK_PLL,
58 .div_reg = PLLDIV1,
59};
60
61static struct clk pll1_sysclk2 = {
62 .name = "pll1_sysclk2",
63 .parent = &pll1_clk,
64 .flags = CLK_PLL,
65 .div_reg = PLLDIV2,
66};
67
68static struct clk pll1_sysclk3 = {
69 .name = "pll1_sysclk3",
70 .parent = &pll1_clk,
71 .flags = CLK_PLL,
72 .div_reg = PLLDIV3,
73};
74
75static struct clk pll1_sysclk5 = {
76 .name = "pll1_sysclk5",
77 .parent = &pll1_clk,
78 .flags = CLK_PLL,
79 .div_reg = PLLDIV5,
80};
81
82static struct clk pll1_aux_clk = {
83 .name = "pll1_aux_clk",
84 .parent = &pll1_clk,
85 .flags = CLK_PLL | PRE_PLL,
86};
87
88static struct clk pll1_sysclkbp = {
89 .name = "pll1_sysclkbp",
90 .parent = &pll1_clk,
91 .flags = CLK_PLL | PRE_PLL,
92 .div_reg = BPDIV
93};
94
95static struct clk pll2_clk = {
96 .name = "pll2",
97 .parent = &ref_clk,
98 .pll_data = &pll2_data,
99 .flags = CLK_PLL,
100};
101
102static struct clk pll2_sysclk1 = {
103 .name = "pll2_sysclk1",
104 .parent = &pll2_clk,
105 .flags = CLK_PLL,
106 .div_reg = PLLDIV1,
107};
108
109static struct clk pll2_sysclk2 = {
110 .name = "pll2_sysclk2",
111 .parent = &pll2_clk,
112 .flags = CLK_PLL,
113 .div_reg = PLLDIV2,
114};
115
116static struct clk pll2_sysclkbp = {
117 .name = "pll2_sysclkbp",
118 .parent = &pll2_clk,
119 .flags = CLK_PLL | PRE_PLL,
120 .div_reg = BPDIV
121};
122
123static struct clk dsp_clk = {
124 .name = "dsp",
125 .parent = &pll1_sysclk1,
126 .lpsc = DAVINCI_LPSC_GEM,
127 .flags = PSC_DSP,
128 .usecount = 1, /* REVISIT how to disable? */
129};
130
131static struct clk arm_clk = {
132 .name = "arm",
133 .parent = &pll1_sysclk2,
134 .lpsc = DAVINCI_LPSC_ARM,
135 .flags = ALWAYS_ENABLED,
136};
137
138static struct clk vicp_clk = {
139 .name = "vicp",
140 .parent = &pll1_sysclk2,
141 .lpsc = DAVINCI_LPSC_IMCOP,
142 .flags = PSC_DSP,
143 .usecount = 1, /* REVISIT how to disable? */
144};
145
146static struct clk vpss_master_clk = {
147 .name = "vpss_master",
148 .parent = &pll1_sysclk3,
149 .lpsc = DAVINCI_LPSC_VPSSMSTR,
150 .flags = CLK_PSC,
151};
152
153static struct clk vpss_slave_clk = {
154 .name = "vpss_slave",
155 .parent = &pll1_sysclk3,
156 .lpsc = DAVINCI_LPSC_VPSSSLV,
157};
158
159static struct clk uart0_clk = {
160 .name = "uart0",
161 .parent = &pll1_aux_clk,
162 .lpsc = DAVINCI_LPSC_UART0,
163};
164
165static struct clk uart1_clk = {
166 .name = "uart1",
167 .parent = &pll1_aux_clk,
168 .lpsc = DAVINCI_LPSC_UART1,
169};
170
171static struct clk uart2_clk = {
172 .name = "uart2",
173 .parent = &pll1_aux_clk,
174 .lpsc = DAVINCI_LPSC_UART2,
175};
176
177static struct clk emac_clk = {
178 .name = "emac",
179 .parent = &pll1_sysclk5,
180 .lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
181};
182
183static struct clk i2c_clk = {
184 .name = "i2c",
185 .parent = &pll1_aux_clk,
186 .lpsc = DAVINCI_LPSC_I2C,
187};
188
189static struct clk ide_clk = {
190 .name = "ide",
191 .parent = &pll1_sysclk5,
192 .lpsc = DAVINCI_LPSC_ATA,
193};
194
195static struct clk asp_clk = {
196 .name = "asp0",
197 .parent = &pll1_sysclk5,
198 .lpsc = DAVINCI_LPSC_McBSP,
199};
200
201static struct clk mmcsd_clk = {
202 .name = "mmcsd",
203 .parent = &pll1_sysclk5,
204 .lpsc = DAVINCI_LPSC_MMC_SD,
205};
206
207static struct clk spi_clk = {
208 .name = "spi",
209 .parent = &pll1_sysclk5,
210 .lpsc = DAVINCI_LPSC_SPI,
211};
212
213static struct clk gpio_clk = {
214 .name = "gpio",
215 .parent = &pll1_sysclk5,
216 .lpsc = DAVINCI_LPSC_GPIO,
217};
218
219static struct clk usb_clk = {
220 .name = "usb",
221 .parent = &pll1_sysclk5,
222 .lpsc = DAVINCI_LPSC_USB,
223};
224
225static struct clk vlynq_clk = {
226 .name = "vlynq",
227 .parent = &pll1_sysclk5,
228 .lpsc = DAVINCI_LPSC_VLYNQ,
229};
230
231static struct clk aemif_clk = {
232 .name = "aemif",
233 .parent = &pll1_sysclk5,
234 .lpsc = DAVINCI_LPSC_AEMIF,
235};
236
237static struct clk pwm0_clk = {
238 .name = "pwm0",
239 .parent = &pll1_aux_clk,
240 .lpsc = DAVINCI_LPSC_PWM0,
241};
242
243static struct clk pwm1_clk = {
244 .name = "pwm1",
245 .parent = &pll1_aux_clk,
246 .lpsc = DAVINCI_LPSC_PWM1,
247};
248
249static struct clk pwm2_clk = {
250 .name = "pwm2",
251 .parent = &pll1_aux_clk,
252 .lpsc = DAVINCI_LPSC_PWM2,
253};
254
255static struct clk timer0_clk = {
256 .name = "timer0",
257 .parent = &pll1_aux_clk,
258 .lpsc = DAVINCI_LPSC_TIMER0,
259};
260
261static struct clk timer1_clk = {
262 .name = "timer1",
263 .parent = &pll1_aux_clk,
264 .lpsc = DAVINCI_LPSC_TIMER1,
265};
266
267static struct clk timer2_clk = {
268 .name = "timer2",
269 .parent = &pll1_aux_clk,
270 .lpsc = DAVINCI_LPSC_TIMER2,
271 .usecount = 1, /* REVISIT: why cant' this be disabled? */
272};
273
274struct davinci_clk dm644x_clks[] = {
275 CLK(NULL, "ref", &ref_clk),
276 CLK(NULL, "pll1", &pll1_clk),
277 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
278 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
279 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
280 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
281 CLK(NULL, "pll1_aux", &pll1_aux_clk),
282 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
283 CLK(NULL, "pll2", &pll2_clk),
284 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
285 CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
286 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
287 CLK(NULL, "dsp", &dsp_clk),
288 CLK(NULL, "arm", &arm_clk),
289 CLK(NULL, "vicp", &vicp_clk),
290 CLK(NULL, "vpss_master", &vpss_master_clk),
291 CLK(NULL, "vpss_slave", &vpss_slave_clk),
292 CLK(NULL, "arm", &arm_clk),
293 CLK(NULL, "uart0", &uart0_clk),
294 CLK(NULL, "uart1", &uart1_clk),
295 CLK(NULL, "uart2", &uart2_clk),
296 CLK("davinci_emac.1", NULL, &emac_clk),
297 CLK("i2c_davinci.1", NULL, &i2c_clk),
298 CLK("palm_bk3710", NULL, &ide_clk),
299 CLK("soc-audio.0", NULL, &asp_clk),
300 CLK("davinci_mmc.0", NULL, &mmcsd_clk),
301 CLK(NULL, "spi", &spi_clk),
302 CLK(NULL, "gpio", &gpio_clk),
303 CLK(NULL, "usb", &usb_clk),
304 CLK(NULL, "vlynq", &vlynq_clk),
305 CLK(NULL, "aemif", &aemif_clk),
306 CLK(NULL, "pwm0", &pwm0_clk),
307 CLK(NULL, "pwm1", &pwm1_clk),
308 CLK(NULL, "pwm2", &pwm2_clk),
309 CLK(NULL, "timer0", &timer0_clk),
310 CLK(NULL, "timer1", &timer1_clk),
311 CLK("watchdog", NULL, &timer2_clk),
312 CLK(NULL, NULL, NULL),
313};
314
315#if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
316
317static struct resource dm644x_emac_resources[] = {
318 {
319 .start = DM644X_EMAC_BASE,
320 .end = DM644X_EMAC_BASE + 0x47ff,
321 .flags = IORESOURCE_MEM,
322 },
323 {
324 .start = IRQ_EMACINT,
325 .end = IRQ_EMACINT,
326 .flags = IORESOURCE_IRQ,
327 },
328};
329
330static struct platform_device dm644x_emac_device = {
331 .name = "davinci_emac",
332 .id = 1,
333 .num_resources = ARRAY_SIZE(dm644x_emac_resources),
334 .resource = dm644x_emac_resources,
335};
336
337#endif
338
339/*
340 * Device specific mux setup
341 *
342 * soc description mux mode mode mux dbg
343 * reg offset mask mode
344 */
345static const struct mux_config dm644x_pins[] = {
346MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
347MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
348MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
349
350MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
351
352MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
353
354MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
355
356MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false)
357
358MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false)
359
360MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true)
361MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true)
362
363MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false)
364
365MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false)
366
367MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false)
368
369MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false)
370MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false)
371MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false)
372
373MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true)
374
375MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true)
376
377MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true)
378MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false)
379MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false)
380MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true)
381
382MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
383
384MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
385MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
386};
387
388
389/*----------------------------------------------------------------------*/
390
391static const s8 dma_chan_dm644x_no_event[] = {
392 0, 1, 12, 13, 14,
393 15, 25, 30, 31, 45,
394 46, 47, 55, 56, 57,
395 58, 59, 60, 61, 62,
396 63,
397 -1
398};
399
400static struct edma_soc_info dm644x_edma_info = {
401 .n_channel = 64,
402 .n_region = 4,
403 .n_slot = 128,
404 .n_tc = 2,
405 .noevent = dma_chan_dm644x_no_event,
406};
407
408static struct resource edma_resources[] = {
409 {
410 .name = "edma_cc",
411 .start = 0x01c00000,
412 .end = 0x01c00000 + SZ_64K - 1,
413 .flags = IORESOURCE_MEM,
414 },
415 {
416 .name = "edma_tc0",
417 .start = 0x01c10000,
418 .end = 0x01c10000 + SZ_1K - 1,
419 .flags = IORESOURCE_MEM,
420 },
421 {
422 .name = "edma_tc1",
423 .start = 0x01c10400,
424 .end = 0x01c10400 + SZ_1K - 1,
425 .flags = IORESOURCE_MEM,
426 },
427 {
428 .start = IRQ_CCINT0,
429 .flags = IORESOURCE_IRQ,
430 },
431 {
432 .start = IRQ_CCERRINT,
433 .flags = IORESOURCE_IRQ,
434 },
435 /* not using TC*_ERR */
436};
437
438static struct platform_device dm644x_edma_device = {
439 .name = "edma",
440 .id = -1,
441 .dev.platform_data = &dm644x_edma_info,
442 .num_resources = ARRAY_SIZE(edma_resources),
443 .resource = edma_resources,
444};
445
446/*----------------------------------------------------------------------*/
447void __init dm644x_init(void)
448{
449 davinci_clk_init(dm644x_clks);
450 davinci_mux_register(dm644x_pins, ARRAY_SIZE(dm644x_pins));
451}
452
453static int __init dm644x_init_devices(void)
454{
455 if (!cpu_is_davinci_dm644x())
456 return 0;
457
458 platform_device_register(&dm644x_edma_device);
459 return 0;
460}
461postcore_initcall(dm644x_init_devices);
diff --git a/arch/arm/mach-davinci/include/mach/board-dm6446evm.h b/arch/arm/mach-davinci/include/mach/board-dm6446evm.h
new file mode 100644
index 000000000000..3216f21c1238
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/board-dm6446evm.h
@@ -0,0 +1,20 @@
1/*
2 * DaVinci DM6446 EVM board specific headers
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or ifndef.
10 */
11
12#ifndef _MACH_DAVINCI_DM6446EVM_H
13#define _MACH_DAVINCI_DM6446EVM_H
14
15#include <linux/types.h>
16
17int dm6446evm_eeprom_read(char *buf, off_t off, size_t count);
18int dm6446evm_eeprom_write(char *buf, off_t off, size_t count);
19
20#endif
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 4b522e5c70ec..191770976250 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -16,6 +16,12 @@ struct sys_timer;
16 16
17extern struct sys_timer davinci_timer; 17extern struct sys_timer davinci_timer;
18 18
19extern void davinci_irq_init(void);
20extern void davinci_map_common_io(void);
21
22/* parameters describe VBUS sourcing for host mode */
23extern void setup_usb(unsigned mA, unsigned potpgt_msec);
24
19/* parameters describe VBUS sourcing for host mode */ 25/* parameters describe VBUS sourcing for host mode */
20extern void setup_usb(unsigned mA, unsigned potpgt_msec); 26extern void setup_usb(unsigned mA, unsigned potpgt_msec);
21 27
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
new file mode 100644
index 000000000000..3dcb9f4e58b4
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
@@ -0,0 +1,37 @@
1/*
2 * This file contains the processor specific definitions
3 * of the TI DM644x.
4 *
5 * Copyright (C) 2008 Texas Instruments.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22#ifndef __ASM_ARCH_DM644X_H
23#define __ASM_ARCH_DM644X_H
24
25#include <linux/platform_device.h>
26#include <mach/hardware.h>
27
28#define DM644X_EMAC_BASE (0x01C80000)
29#define DM644X_EMAC_CNTRL_OFFSET (0x0000)
30#define DM644X_EMAC_CNTRL_MOD_OFFSET (0x1000)
31#define DM644X_EMAC_CNTRL_RAM_OFFSET (0x2000)
32#define DM644X_EMAC_MDIO_OFFSET (0x4000)
33#define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000)
34
35void __init dm644x_init(void);
36
37#endif /* __ASM_ARCH_DM644X_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 21:27:36 -0500