448 files changed, 15812 insertions, 3997 deletions

diff --git a/arch/Kconfig b/arch/Kconfig
index 4877a8c8ee16..fe48fc7a3eba 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -32,8 +32,9 @@ config HAVE_OPROFILE
 
 config KPROBES
         bool "Kprobes"
-        depends on KALLSYMS && MODULES
+        depends on MODULES
         depends on HAVE_KPROBES
+        select KALLSYMS
         help
           Kprobes allows you to trap at almost any kernel address and
           execute a callback function.  register_kprobe() establishes
@@ -45,7 +46,6 @@ config OPTPROBES
         def_bool y
         depends on KPROBES && HAVE_OPTPROBES
         depends on !PREEMPT
-        select KALLSYMS_ALL
 
 config HAVE_EFFICIENT_UNALIGNED_ACCESS
         bool
diff --git a/arch/alpha/include/asm/cacheflush.h b/arch/alpha/include/asm/cacheflush.h
index 01d71e1c8a9e..012f1243b1c1 100644
--- a/arch/alpha/include/asm/cacheflush.h
+++ b/arch/alpha/include/asm/cacheflush.h
@@ -43,6 +43,8 @@ extern void smp_imb(void);
 /* ??? Ought to use this in arch/alpha/kernel/signal.c too.  */
 
 #ifndef CONFIG_SMP
+#include <linux/sched.h>
+
 extern void __load_new_mm_context(struct mm_struct *);
 static inline void
 flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
diff --git a/arch/alpha/include/asm/unistd.h b/arch/alpha/include/asm/unistd.h
index 804e5311c841..058937bf5a77 100644
--- a/arch/alpha/include/asm/unistd.h
+++ b/arch/alpha/include/asm/unistd.h
@@ -449,10 +449,13 @@
 #define __NR_pwritev                    491
 #define __NR_rt_tgsigqueueinfo          492
 #define __NR_perf_event_open            493
+#define __NR_fanotify_init              494
+#define __NR_fanotify_mark              495
+#define __NR_prlimit64                  496
 
 #ifdef __KERNEL__
 
-#define NR_SYSCALLS                     494
+#define NR_SYSCALLS                     497
 
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
@@ -463,6 +466,7 @@
 #define __ARCH_WANT_SYS_OLD_GETRLIMIT
 #define __ARCH_WANT_SYS_OLDUMOUNT
 #define __ARCH_WANT_SYS_SIGPENDING
+#define __ARCH_WANT_SYS_RT_SIGSUSPEND
 
 /* "Conditional" syscalls.  What we want is
 
diff --git a/arch/alpha/kernel/entry.S b/arch/alpha/kernel/entry.S
index b45d913a51c3..6d159cee5f2f 100644
--- a/arch/alpha/kernel/entry.S
+++ b/arch/alpha/kernel/entry.S
@@ -73,8 +73,6 @@
         ldq     $20, HAE_REG($19);      \
         stq     $21, HAE_CACHE($19);    \
         stq     $21, 0($20);            \
-        ldq     $0, 0($sp);             \
-        ldq     $1, 8($sp);             \
 99:;                                    \
         ldq     $19, 72($sp);           \
         ldq     $20, 80($sp);           \
@@ -316,19 +314,24 @@ ret_from_sys_call:
         cmovne  $26, 0, $19             /* $19 = 0 => non-restartable */
         ldq     $0, SP_OFF($sp)
         and     $0, 8, $0
-        beq     $0, restore_all
-ret_from_reschedule:
+        beq     $0, ret_to_kernel
+ret_to_user:
         /* Make sure need_resched and sigpending don't change between
                 sampling and the rti.  */
         lda     $16, 7
         call_pal PAL_swpipl
         ldl     $5, TI_FLAGS($8)
         and     $5, _TIF_WORK_MASK, $2
-        bne     $5, work_pending
+        bne     $2, work_pending
 restore_all:
         RESTORE_ALL
         call_pal PAL_rti
 
+ret_to_kernel:
+        lda     $16, 7
+        call_pal PAL_swpipl
+        br restore_all
+
         .align 3
 $syscall_error:
         /*
@@ -363,7 +366,7 @@ $ret_success:
  *       $8: current.
  *      $19: The old syscall number, or zero if this is not a return
  *           from a syscall that errored and is possibly restartable.
- *      $20: Error indication.
+ *      $20: The old a3 value
  */
 
         .align  4
@@ -392,12 +395,18 @@ $work_resched:
 
 $work_notifysig:
         mov     $sp, $16
-        br      $1, do_switch_stack
+        bsr     $1, do_switch_stack
         mov     $sp, $17
         mov     $5, $18
+        mov     $19, $9         /* save old syscall number */
+        mov     $20, $10        /* save old a3 */
+        and     $5, _TIF_SIGPENDING, $2
+        cmovne  $2, 0, $9       /* we don't want double syscall restarts */
         jsr     $26, do_notify_resume
+        mov     $9, $19
+        mov     $10, $20
         bsr     $1, undo_switch_stack
-        br      restore_all
+        br      ret_to_user
 .end work_pending
 
 /*
@@ -430,6 +439,7 @@ strace:
         beq     $1, 1f
         ldq     $27, 0($2)
 1:      jsr     $26, ($27), sys_gettimeofday
+ret_from_straced:
         ldgp    $gp, 0($26)
 
         /* check return.. */
@@ -650,7 +660,7 @@ kernel_thread:
         /* We don't actually care for a3 success widgetry in the kernel.
            Not for positive errno values.  */
         stq     $0, 0($sp)              /* $0 */
-        br      restore_all
+        br      ret_to_kernel
 .end kernel_thread
 
 /*
@@ -757,11 +767,15 @@ sys_vfork:
         .ent    sys_sigreturn
 sys_sigreturn:
         .prologue 0
+        lda     $9, ret_from_straced
+        cmpult  $26, $9, $9
         mov     $sp, $17
         lda     $18, -SWITCH_STACK_SIZE($sp)
         lda     $sp, -SWITCH_STACK_SIZE($sp)
         jsr     $26, do_sigreturn
-        br      $1, undo_switch_stack
+        bne     $9, 1f
+        jsr     $26, syscall_trace
+1:      br      $1, undo_switch_stack
         br      ret_from_sys_call
 .end sys_sigreturn
 
@@ -770,47 +784,19 @@ sys_sigreturn:
         .ent    sys_rt_sigreturn
 sys_rt_sigreturn:
         .prologue 0
+        lda     $9, ret_from_straced
+        cmpult  $26, $9, $9
         mov     $sp, $17
         lda     $18, -SWITCH_STACK_SIZE($sp)
         lda     $sp, -SWITCH_STACK_SIZE($sp)
         jsr     $26, do_rt_sigreturn
-        br      $1, undo_switch_stack
+        bne     $9, 1f
+        jsr     $26, syscall_trace
+1:      br      $1, undo_switch_stack
         br      ret_from_sys_call
 .end sys_rt_sigreturn
 
         .align  4
-        .globl  sys_sigsuspend
-        .ent    sys_sigsuspend
-sys_sigsuspend:
-        .prologue 0
-        mov     $sp, $17
-        br      $1, do_switch_stack
-        mov     $sp, $18
-        subq    $sp, 16, $sp
-        stq     $26, 0($sp)
-        jsr     $26, do_sigsuspend
-        ldq     $26, 0($sp)
-        lda     $sp, SWITCH_STACK_SIZE+16($sp)
-        ret
-.end sys_sigsuspend
-
-        .align  4
-        .globl  sys_rt_sigsuspend
-        .ent    sys_rt_sigsuspend
-sys_rt_sigsuspend:
-        .prologue 0
-        mov     $sp, $18
-        br      $1, do_switch_stack
-        mov     $sp, $19
-        subq    $sp, 16, $sp
-        stq     $26, 0($sp)
-        jsr     $26, do_rt_sigsuspend
-        ldq     $26, 0($sp)
-        lda     $sp, SWITCH_STACK_SIZE+16($sp)
-        ret
-.end sys_rt_sigsuspend
-
-        .align  4
         .globl  sys_sethae
         .ent    sys_sethae
 sys_sethae:
@@ -929,15 +915,6 @@ sys_execve:
 .end sys_execve
 
         .align  4
-        .globl  osf_sigprocmask
-        .ent    osf_sigprocmask
-osf_sigprocmask:
-        .prologue 0
-        mov     $sp, $18
-        jmp     $31, sys_osf_sigprocmask
-.end osf_sigprocmask
-
-        .align  4
         .globl  alpha_ni_syscall
         .ent    alpha_ni_syscall
 alpha_ni_syscall:
diff --git a/arch/alpha/kernel/err_ev6.c b/arch/alpha/kernel/err_ev6.c
index 8ca6345bf131..253cf1a87481 100644
--- a/arch/alpha/kernel/err_ev6.c
+++ b/arch/alpha/kernel/err_ev6.c
@@ -90,11 +90,13 @@ static int
 ev6_parse_cbox(u64 c_addr, u64 c1_syn, u64 c2_syn, 
                u64 c_stat, u64 c_sts, int print)
 {
-        char *sourcename[] = { "UNKNOWN", "UNKNOWN", "UNKNOWN",
-                               "MEMORY", "BCACHE", "DCACHE", 
-                               "BCACHE PROBE", "BCACHE PROBE" };
-        char *streamname[] = { "D", "I" };
-        char *bitsname[] = { "SINGLE", "DOUBLE" };
+        static const char * const sourcename[] = {
+                "UNKNOWN", "UNKNOWN", "UNKNOWN",
+                "MEMORY", "BCACHE", "DCACHE",
+                "BCACHE PROBE", "BCACHE PROBE"
+        };
+        static const char * const streamname[] = { "D", "I" };
+        static const char * const bitsname[] = { "SINGLE", "DOUBLE" };
         int status = MCHK_DISPOSITION_REPORT;
         int source = -1, stream = -1, bits = -1;
 
diff --git a/arch/alpha/kernel/err_marvel.c b/arch/alpha/kernel/err_marvel.c
index 5c905aaaeccd..648ae88aeb8a 100644
--- a/arch/alpha/kernel/err_marvel.c
+++ b/arch/alpha/kernel/err_marvel.c
@@ -589,22 +589,23 @@ marvel_print_pox_spl_cmplt(u64 spl_cmplt)
 static void
 marvel_print_pox_trans_sum(u64 trans_sum)
 {
-        char *pcix_cmd[] = { "Interrupt Acknowledge",
-                             "Special Cycle",
-                             "I/O Read",
-                             "I/O Write",
-                             "Reserved",
-                             "Reserved / Device ID Message",
-                             "Memory Read",
-                             "Memory Write",
-                             "Reserved / Alias to Memory Read Block",
-                             "Reserved / Alias to Memory Write Block",
-                             "Configuration Read",
-                             "Configuration Write",
-                             "Memory Read Multiple / Split Completion",
-                             "Dual Address Cycle",
-                             "Memory Read Line / Memory Read Block",
-                             "Memory Write and Invalidate / Memory Write Block"
+        static const char * const pcix_cmd[] = {
+                "Interrupt Acknowledge",
+                "Special Cycle",
+                "I/O Read",
+                "I/O Write",
+                "Reserved",
+                "Reserved / Device ID Message",
+                "Memory Read",
+                "Memory Write",
+                "Reserved / Alias to Memory Read Block",
+                "Reserved / Alias to Memory Write Block",
+                "Configuration Read",
+                "Configuration Write",
+                "Memory Read Multiple / Split Completion",
+                "Dual Address Cycle",
+                "Memory Read Line / Memory Read Block",
+                "Memory Write and Invalidate / Memory Write Block"
         };
 
 #define IO7__POX_TRANSUM__PCI_ADDR__S           (0)
diff --git a/arch/alpha/kernel/err_titan.c b/arch/alpha/kernel/err_titan.c
index f7ed97ce0dfd..c3b3781a03de 100644
--- a/arch/alpha/kernel/err_titan.c
+++ b/arch/alpha/kernel/err_titan.c
@@ -75,8 +75,12 @@ titan_parse_p_serror(int which, u64 serror, int print)
         int status = MCHK_DISPOSITION_REPORT;
 
 #ifdef CONFIG_VERBOSE_MCHECK
-        char *serror_src[] = {"GPCI", "APCI", "AGP HP", "AGP LP"};
-        char *serror_cmd[] = {"DMA Read", "DMA RMW", "SGTE Read", "Reserved"};
+        static const char * const serror_src[] = {
+                "GPCI", "APCI", "AGP HP", "AGP LP"
+        };
+        static const char * const serror_cmd[] = {
+                "DMA Read", "DMA RMW", "SGTE Read", "Reserved"
+        };
 #endif /* CONFIG_VERBOSE_MCHECK */
 
 #define TITAN__PCHIP_SERROR__LOST_UECC  (1UL << 0)
@@ -140,14 +144,15 @@ titan_parse_p_perror(int which, int port, u64 perror, int print)
         int status = MCHK_DISPOSITION_REPORT;
 
 #ifdef CONFIG_VERBOSE_MCHECK
-        char *perror_cmd[] = { "Interrupt Acknowledge", "Special Cycle",
-                               "I/O Read",              "I/O Write",
-                               "Reserved",              "Reserved",
-                               "Memory Read",           "Memory Write",
-                               "Reserved",              "Reserved",
-                               "Configuration Read",    "Configuration Write",
-                               "Memory Read Multiple",  "Dual Address Cycle",
-                               "Memory Read Line","Memory Write and Invalidate"
+        static const char * const perror_cmd[] = {
+                "Interrupt Acknowledge", "Special Cycle",
+                "I/O Read",             "I/O Write",
+                "Reserved",             "Reserved",
+                "Memory Read",          "Memory Write",
+                "Reserved",             "Reserved",
+                "Configuration Read",   "Configuration Write",
+                "Memory Read Multiple", "Dual Address Cycle",
+                "Memory Read Line",     "Memory Write and Invalidate"
         };
 #endif /* CONFIG_VERBOSE_MCHECK */
 
@@ -273,11 +278,11 @@ titan_parse_p_agperror(int which, u64 agperror, int print)
         int cmd, len;
         unsigned long addr;
 
-        char *agperror_cmd[] = { "Read (low-priority)", "Read (high-priority)",
-                                 "Write (low-priority)",
-                                 "Write (high-priority)",
-                                 "Reserved",            "Reserved",
-                                 "Flush",               "Fence"
+        static const char * const agperror_cmd[] = {
+                "Read (low-priority)",  "Read (high-priority)",
+                "Write (low-priority)", "Write (high-priority)",
+                "Reserved",             "Reserved",
+                "Flush",                "Fence"
         };
 #endif /* CONFIG_VERBOSE_MCHECK */
 
diff --git a/arch/alpha/kernel/osf_sys.c b/arch/alpha/kernel/osf_sys.c
index 5d1e6d6ce684..547e8b84b2f7 100644
--- a/arch/alpha/kernel/osf_sys.c
+++ b/arch/alpha/kernel/osf_sys.c
@@ -15,7 +15,6 @@
 #include <linux/kernel.h>
 #include <linux/mm.h>
 #include <linux/smp.h>
-#include <linux/smp_lock.h>
 #include <linux/stddef.h>
 #include <linux/syscalls.h>
 #include <linux/unistd.h>
@@ -69,7 +68,6 @@ SYSCALL_DEFINE4(osf_set_program_attributes, unsigned long, text_start,
 {
         struct mm_struct *mm;
 
-        lock_kernel();
         mm = current->mm;
         mm->end_code = bss_start + bss_len;
         mm->start_brk = bss_start + bss_len;
@@ -78,7 +76,6 @@ SYSCALL_DEFINE4(osf_set_program_attributes, unsigned long, text_start,
         printk("set_program_attributes(%lx %lx %lx %lx)\n",
                 text_start, text_len, bss_start, bss_len);
 #endif
-        unlock_kernel();
         return 0;
 }
 
@@ -517,7 +514,6 @@ SYSCALL_DEFINE2(osf_proplist_syscall, enum pl_code, code,
         long error;
         int __user *min_buf_size_ptr;
 
-        lock_kernel();
         switch (code) {
         case PL_SET:
                 if (get_user(error, &args->set.nbytes))
@@ -547,7 +543,6 @@ SYSCALL_DEFINE2(osf_proplist_syscall, enum pl_code, code,
                 error = -EOPNOTSUPP;
                 break;
         };
-        unlock_kernel();
         return error;
 }
 
@@ -594,7 +589,7 @@ SYSCALL_DEFINE2(osf_sigstack, struct sigstack __user *, uss,
 
 SYSCALL_DEFINE3(osf_sysinfo, int, command, char __user *, buf, long, count)
 {
-        char *sysinfo_table[] = {
+        const char *sysinfo_table[] = {
                 utsname()->sysname,
                 utsname()->nodename,
                 utsname()->release,
@@ -606,7 +601,7 @@ SYSCALL_DEFINE3(osf_sysinfo, int, command, char __user *, buf, long, count)
                 "dummy",        /* secure RPC domain */
         };
         unsigned long offset;
-        char *res;
+        const char *res;
         long len, err = -EINVAL;
 
         offset = command-1;
diff --git a/arch/alpha/kernel/pci-sysfs.c b/arch/alpha/kernel/pci-sysfs.c
index 738fc824e2ea..b899e95f79fd 100644
--- a/arch/alpha/kernel/pci-sysfs.c
+++ b/arch/alpha/kernel/pci-sysfs.c
@@ -66,7 +66,7 @@ static int pci_mmap_resource(struct kobject *kobj,
 {
         struct pci_dev *pdev = to_pci_dev(container_of(kobj,
                                                        struct device, kobj));
-        struct resource *res = (struct resource *)attr->private;
+        struct resource *res = attr->private;
         enum pci_mmap_state mmap_type;
         struct pci_bus_region bar;
         int i;
diff --git a/arch/alpha/kernel/process.c b/arch/alpha/kernel/process.c
index 842dba308eab..3ec35066f1dc 100644
--- a/arch/alpha/kernel/process.c
+++ b/arch/alpha/kernel/process.c
@@ -356,7 +356,7 @@ dump_elf_thread(elf_greg_t *dest, struct pt_regs *pt, struct thread_info *ti)
         dest[27] = pt->r27;
         dest[28] = pt->r28;
         dest[29] = pt->gp;
-        dest[30] = rdusp();
+        dest[30] = ti == current_thread_info() ? rdusp() : ti->pcb.usp;
         dest[31] = pt->pc;
 
         /* Once upon a time this was the PS value.  Which is stupid
diff --git a/arch/alpha/kernel/signal.c b/arch/alpha/kernel/signal.c
index 0932dbb1ef8e..6f7feb5db271 100644
--- a/arch/alpha/kernel/signal.c
+++ b/arch/alpha/kernel/signal.c
@@ -41,46 +41,20 @@ static void do_signal(struct pt_regs *, struct switch_stack *,
 /*
  * The OSF/1 sigprocmask calling sequence is different from the
  * C sigprocmask() sequence..
- *
- * how:
- * 1 - SIG_BLOCK
- * 2 - SIG_UNBLOCK
- * 3 - SIG_SETMASK
- *
- * We change the range to -1 .. 1 in order to let gcc easily
- * use the conditional move instructions.
- *
- * Note that we don't need to acquire the kernel lock for SMP
- * operation, as all of this is local to this thread.
  */
-SYSCALL_DEFINE3(osf_sigprocmask, int, how, unsigned long, newmask,
-                struct pt_regs *, regs)
+SYSCALL_DEFINE2(osf_sigprocmask, int, how, unsigned long, newmask)
 {
-        unsigned long oldmask = -EINVAL;
-
-        if ((unsigned long)how-1 <= 2) {
-                long sign = how-2;              /* -1 .. 1 */
-                unsigned long block, unblock;
-
-                newmask &= _BLOCKABLE;
-                spin_lock_irq(&current->sighand->siglock);
-                oldmask = current->blocked.sig[0];
-
-                unblock = oldmask & ~newmask;
-                block = oldmask | newmask;
-                if (!sign)
-                        block = unblock;
-                if (sign <= 0)
-                        newmask = block;
-                if (_NSIG_WORDS > 1 && sign > 0)
-                        sigemptyset(&current->blocked);
-                current->blocked.sig[0] = newmask;
-                recalc_sigpending();
-                spin_unlock_irq(&current->sighand->siglock);
-
-                regs->r0 = 0;           /* special no error return */
+        sigset_t oldmask;
+        sigset_t mask;
+        unsigned long res;
+
+        siginitset(&mask, newmask & _BLOCKABLE);
+        res = sigprocmask(how, &mask, &oldmask);
+        if (!res) {
+                force_successful_syscall_return();
+                res = oldmask.sig[0];
         }
-        return oldmask;
+        return res;
 }
 
 SYSCALL_DEFINE3(osf_sigaction, int, sig,
@@ -94,9 +68,9 @@ SYSCALL_DEFINE3(osf_sigaction, int, sig,
                 old_sigset_t mask;
                 if (!access_ok(VERIFY_READ, act, sizeof(*act)) ||
                     __get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
-                    __get_user(new_ka.sa.sa_flags, &act->sa_flags))
+                    __get_user(new_ka.sa.sa_flags, &act->sa_flags) ||
+                    __get_user(mask, &act->sa_mask))
                         return -EFAULT;
-                __get_user(mask, &act->sa_mask);
                 siginitset(&new_ka.sa.sa_mask, mask);
                 new_ka.ka_restorer = NULL;
         }
@@ -106,9 +80,9 @@ SYSCALL_DEFINE3(osf_sigaction, int, sig,
         if (!ret && oact) {
                 if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) ||
                     __put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
-                    __put_user(old_ka.sa.sa_flags, &oact->sa_flags))
+                    __put_user(old_ka.sa.sa_flags, &oact->sa_flags) ||
+                    __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask))
                         return -EFAULT;
-                __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask);
         }
 
         return ret;
@@ -144,8 +118,7 @@ SYSCALL_DEFINE5(rt_sigaction, int, sig, const struct sigaction __user *, act,
 /*
  * Atomically swap in the new signal mask, and wait for a signal.
  */
-asmlinkage int
-do_sigsuspend(old_sigset_t mask, struct pt_regs *regs, struct switch_stack *sw)
+SYSCALL_DEFINE1(sigsuspend, old_sigset_t, mask)
 {
         mask &= _BLOCKABLE;
         spin_lock_irq(&current->sighand->siglock);
@@ -154,41 +127,6 @@ do_sigsuspend(old_sigset_t mask, struct pt_regs *regs, struct switch_stack *sw)
         recalc_sigpending();
         spin_unlock_irq(&current->sighand->siglock);
 
-        /* Indicate EINTR on return from any possible signal handler,
-           which will not come back through here, but via sigreturn.  */
-        regs->r0 = EINTR;
-        regs->r19 = 1;
-
-        current->state = TASK_INTERRUPTIBLE;
-        schedule();
-        set_thread_flag(TIF_RESTORE_SIGMASK);
-        return -ERESTARTNOHAND;
-}
-
-asmlinkage int
-do_rt_sigsuspend(sigset_t __user *uset, size_t sigsetsize,
-                 struct pt_regs *regs, struct switch_stack *sw)
-{
-        sigset_t set;
-
-        /* XXX: Don't preclude handling different sized sigset_t's.  */
-        if (sigsetsize != sizeof(sigset_t))
-                return -EINVAL;
-        if (copy_from_user(&set, uset, sizeof(set)))
-                return -EFAULT;
-
-        sigdelsetmask(&set, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->saved_sigmask = current->blocked;
-        current->blocked = set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
-
-        /* Indicate EINTR on return from any possible signal handler,
-           which will not come back through here, but via sigreturn.  */
-        regs->r0 = EINTR;
-        regs->r19 = 1;
-
         current->state = TASK_INTERRUPTIBLE;
         schedule();
         set_thread_flag(TIF_RESTORE_SIGMASK);
@@ -239,6 +177,8 @@ restore_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs,
         unsigned long usp;
         long i, err = __get_user(regs->pc, &sc->sc_pc);
 
+        current_thread_info()->restart_block.fn = do_no_restart_syscall;
+
         sw->r26 = (unsigned long) ret_from_sys_call;
 
         err |= __get_user(regs->r0, sc->sc_regs+0);
@@ -591,7 +531,6 @@ syscall_restart(unsigned long r0, unsigned long r19,
                 regs->pc -= 4;
                 break;
         case ERESTART_RESTARTBLOCK:
-                current_thread_info()->restart_block.fn = do_no_restart_syscall;
                 regs->r0 = EINTR;
                 break;
         }
diff --git a/arch/alpha/kernel/srm_env.c b/arch/alpha/kernel/srm_env.c
index 4afc1a1e2e5a..f0df3fbd8402 100644
--- a/arch/alpha/kernel/srm_env.c
+++ b/arch/alpha/kernel/srm_env.c
@@ -87,7 +87,7 @@ static int srm_env_proc_show(struct seq_file *m, void *v)
         srm_env_t       *entry;
         char            *page;
 
-        entry = (srm_env_t *)m->private;
+        entry = m->private;
         page = (char *)__get_free_page(GFP_USER);
         if (!page)
                 return -ENOMEM;
diff --git a/arch/alpha/kernel/systbls.S b/arch/alpha/kernel/systbls.S
index 09acb786e72b..a6a1de9db16f 100644
--- a/arch/alpha/kernel/systbls.S
+++ b/arch/alpha/kernel/systbls.S
@@ -58,7 +58,7 @@ sys_call_table:
         .quad sys_open                          /* 45 */
         .quad alpha_ni_syscall
         .quad sys_getxgid
-        .quad osf_sigprocmask
+        .quad sys_osf_sigprocmask
         .quad alpha_ni_syscall
         .quad alpha_ni_syscall                  /* 50 */
         .quad sys_acct
@@ -512,6 +512,9 @@ sys_call_table:
         .quad sys_pwritev
         .quad sys_rt_tgsigqueueinfo
         .quad sys_perf_event_open
+        .quad sys_fanotify_init
+        .quad sys_fanotify_mark                         /* 495 */
+        .quad sys_prlimit64
 
         .size sys_call_table, . - sys_call_table
         .type sys_call_table, @object
diff --git a/arch/alpha/kernel/time.c b/arch/alpha/kernel/time.c
index eacceb26d9c8..396af1799ea4 100644
--- a/arch/alpha/kernel/time.c
+++ b/arch/alpha/kernel/time.c
@@ -191,16 +191,16 @@ irqreturn_t timer_interrupt(int irq, void *dev)
 
         write_sequnlock(&xtime_lock);
 
-#ifndef CONFIG_SMP
-        while (nticks--)
-                update_process_times(user_mode(get_irq_regs()));
-#endif
-
         if (test_perf_event_pending()) {
                 clear_perf_event_pending();
                 perf_event_do_pending();
         }
 
+#ifndef CONFIG_SMP
+        while (nticks--)
+                update_process_times(user_mode(get_irq_regs()));
+#endif
+
         return IRQ_HANDLED;
 }
 
diff --git a/arch/alpha/kernel/traps.c b/arch/alpha/kernel/traps.c
index b14f015008ad..0414e021a91c 100644
--- a/arch/alpha/kernel/traps.c
+++ b/arch/alpha/kernel/traps.c
@@ -13,7 +13,6 @@
 #include <linux/sched.h>
 #include <linux/tty.h>
 #include <linux/delay.h>
-#include <linux/smp_lock.h>
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/kallsyms.h>
@@ -623,7 +622,6 @@ do_entUna(void * va, unsigned long opcode, unsigned long reg,
                 return;
         }
 
-        lock_kernel();
         printk("Bad unaligned kernel access at %016lx: %p %lx %lu\n",
                 pc, va, opcode, reg);
         do_exit(SIGSEGV);
@@ -646,7 +644,6 @@ got_exception:
          * Yikes!  No one to forward the exception to.
          * Since the registers are in a weird format, dump them ourselves.
          */
-        lock_kernel();
 
         printk("%s(%d): unhandled unaligned exception\n",
                current->comm, task_pid_nr(current));
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 553b7cf17bfb..b27f8abf163c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -271,7 +271,6 @@ config ARCH_AT91
         bool "Atmel AT91"
         select ARCH_REQUIRE_GPIOLIB
         select HAVE_CLK
-        select ARCH_USES_GETTIMEOFFSET
         help
           This enables support for systems based on the Atmel AT91RM9200,
           AT91SAM9 and AT91CAP9 processors.
@@ -511,6 +510,7 @@ config ARCH_MMP
         select GENERIC_CLOCKEVENTS
         select TICK_ONESHOT
         select PLAT_PXA
+        select SPARSE_IRQ
         help
           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 
@@ -588,6 +588,7 @@ config ARCH_PXA
         select GENERIC_CLOCKEVENTS
         select TICK_ONESHOT
         select PLAT_PXA
+        select SPARSE_IRQ
         help
           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 
@@ -679,8 +680,8 @@ config ARCH_S3C64XX
         help
           Samsung S3C64XX series based systems
 
-config ARCH_S5P6440
-        bool "Samsung S5P6440"
+config ARCH_S5P64X0
+        bool "Samsung S5P6440 S5P6450"
         select CPU_V6
         select GENERIC_GPIO
         select HAVE_CLK
@@ -689,7 +690,8 @@ config ARCH_S5P6440
         select HAVE_S3C2410_I2C
         select HAVE_S3C_RTC
         help
-          Samsung S5P6440 CPU based systems
+          Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
+          SMDK6450.
 
 config ARCH_S5P6442
         bool "Samsung S5P6442"
@@ -748,6 +750,15 @@ config ARCH_SHARK
           Support for the StrongARM based Digital DNARD machine, also known
           as "Shark" (<http://www.shark-linux.de/shark.html>).
 
+config ARCH_TCC_926
+        bool "Telechips TCC ARM926-based systems"
+        select CPU_ARM926T
+        select HAVE_CLK
+        select COMMON_CLKDEV
+        select GENERIC_CLOCKEVENTS
+        help
+          Support for Telechips TCC ARM926-based systems.
+
 config ARCH_LH7A40X
         bool "Sharp LH7A40X"
         select CPU_ARM922T
@@ -916,6 +927,8 @@ source "arch/arm/plat-s5p/Kconfig"
 
 source "arch/arm/plat-spear/Kconfig"
 
+source "arch/arm/plat-tcc/Kconfig"
+
 if ARCH_S3C2410
 source "arch/arm/mach-s3c2400/Kconfig"
 source "arch/arm/mach-s3c2410/Kconfig"
@@ -929,7 +942,7 @@ if ARCH_S3C64XX
 source "arch/arm/mach-s3c64xx/Kconfig"
 endif
 
-source "arch/arm/mach-s5p6440/Kconfig"
+source "arch/arm/mach-s5p64x0/Kconfig"
 
 source "arch/arm/mach-s5p6442/Kconfig"
 
@@ -1051,6 +1064,32 @@ config ARM_ERRATA_460075
           ACTLR register. Note that setting specific bits in the ACTLR register
           may not be available in non-secure mode.
 
+config ARM_ERRATA_742230
+        bool "ARM errata: DMB operation may be faulty"
+        depends on CPU_V7 && SMP
+        help
+          This option enables the workaround for the 742230 Cortex-A9
+          (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
+          between two write operations may not ensure the correct visibility
+          ordering of the two writes. This workaround sets a specific bit in
+          the diagnostic register of the Cortex-A9 which causes the DMB
+          instruction to behave as a DSB, ensuring the correct behaviour of
+          the two writes.
+
+config ARM_ERRATA_742231
+        bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
+        depends on CPU_V7 && SMP
+        help
+          This option enables the workaround for the 742231 Cortex-A9
+          (r2p0..r2p2) erratum. Under certain conditions, specific to the
+          Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
+          accessing some data located in the same cache line, may get corrupted
+          data due to bad handling of the address hazard when the line gets
+          replaced from one of the CPUs at the same time as another CPU is
+          accessing it. This workaround sets specific bits in the diagnostic
+          register of the Cortex-A9 which reduces the linefill issuing
+          capabilities of the processor.
+
 config PL310_ERRATA_588369
         bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
         depends on CACHE_L2X0 && ARCH_OMAP4
@@ -1076,6 +1115,20 @@ config ARM_ERRATA_720789
           invalidated are not, resulting in an incoherency in the system page
           tables. The workaround changes the TLB flushing routines to invalidate
           entries regardless of the ASID.
+
+config ARM_ERRATA_743622
+        bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
+        depends on CPU_V7
+        help
+          This option enables the workaround for the 743622 Cortex-A9
+          (r2p0..r2p2) erratum. Under very rare conditions, a faulty
+          optimisation in the Cortex-A9 Store Buffer may lead to data
+          corruption. This workaround sets a specific bit in the diagnostic
+          register of the Cortex-A9 which disables the Store Buffer
+          optimisation, preventing the defect from occurring. This has no
+          visible impact on the overall performance or power consumption of the
+          processor.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
@@ -1232,7 +1285,7 @@ source kernel/Kconfig.preempt
 
 config HZ
         int
-        default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || \
+        default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
                 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
         default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
         default AT91_TIMER_HZ if ARCH_AT91
@@ -1438,6 +1491,20 @@ config UACCESS_WITH_MEMCPY
           However, if the CPU data cache is using a write-allocate mode,
           this option is unlikely to provide any performance gain.
 
+config SECCOMP
+        bool
+        prompt "Enable seccomp to safely compute untrusted bytecode"
+        ---help---
+          This kernel feature is useful for number crunching applications
+          that may need to compute untrusted bytecode during their
+          execution. By using pipes or other transports made available to
+          the process as file descriptors supporting the read/write
+          syscalls, it's possible to isolate those applications in
+          their own address space using seccomp. Once seccomp is
+          enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
+          and the task is only allowed to execute a few safe syscalls
+          defined by each seccomp mode.
+
 config CC_STACKPROTECTOR
         bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
         help
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 91344af75f39..c29fb382aeee 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -2,6 +2,20 @@ menu "Kernel hacking"
 
 source "lib/Kconfig.debug"
 
+config STRICT_DEVMEM
+        bool "Filter access to /dev/mem"
+        depends on MMU
+        ---help---
+          If this option is disabled, you allow userspace (root) access to all
+          of memory, including kernel and userspace memory. Accidental
+          access to this is obviously disastrous, but specific access can
+          be used by people debugging the kernel.
+
+          If this option is switched on, the /dev/mem file only allows
+          userspace access to memory mapped peripherals.
+
+          If in doubt, say Y.
+
 # RMK wants arm kernels compiled with frame pointers or stack unwinding.
 # If you know what you are doing and are willing to live without stack
 # traces, you can get a slightly smaller kernel by setting this option to
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 59c1ce858fc8..b87aed028eef 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -173,7 +173,7 @@ machine-$(CONFIG_ARCH_RPC)		:= rpc
 machine-$(CONFIG_ARCH_S3C2410)          := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c2443
 machine-$(CONFIG_ARCH_S3C24A0)          := s3c24a0
 machine-$(CONFIG_ARCH_S3C64XX)          := s3c64xx
-machine-$(CONFIG_ARCH_S5P6440)          := s5p6440
+machine-$(CONFIG_ARCH_S5P64X0)          := s5p64x0
 machine-$(CONFIG_ARCH_S5P6442)          := s5p6442
 machine-$(CONFIG_ARCH_S5PC100)          := s5pc100
 machine-$(CONFIG_ARCH_S5PV210)          := s5pv210
@@ -183,6 +183,7 @@ machine-$(CONFIG_ARCH_SHARK)		:= shark
 machine-$(CONFIG_ARCH_SHMOBILE)         := shmobile
 machine-$(CONFIG_ARCH_STMP378X)         := stmp378x
 machine-$(CONFIG_ARCH_STMP37XX)         := stmp37xx
+machine-$(CONFIG_ARCH_TCC8K)            := tcc8k
 machine-$(CONFIG_ARCH_TEGRA)            := tegra
 machine-$(CONFIG_ARCH_U300)             := u300
 machine-$(CONFIG_ARCH_U8500)            := ux500
@@ -202,6 +203,7 @@ plat-$(CONFIG_ARCH_MXC)		:= mxc
 plat-$(CONFIG_ARCH_OMAP)        := omap
 plat-$(CONFIG_ARCH_S3C64XX)     := samsung
 plat-$(CONFIG_ARCH_STMP3XXX)    := stmp3xxx
+plat-$(CONFIG_ARCH_TCC_926)     := tcc
 plat-$(CONFIG_PLAT_IOP)         := iop
 plat-$(CONFIG_PLAT_NOMADIK)     := nomadik
 plat-$(CONFIG_PLAT_ORION)       := orion
@@ -245,13 +247,14 @@ ifeq ($(FASTFPE),$(wildcard $(FASTFPE)))
 FASTFPE_OBJ     :=$(FASTFPE)/
 endif
 
-# If we have a machine-specific directory, then include it in the build.
-core-y                          += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
-core-y                          += $(machdirs) $(platdirs)
 core-$(CONFIG_FPE_NWFPE)        += arch/arm/nwfpe/
 core-$(CONFIG_FPE_FASTFPE)      += $(FASTFPE_OBJ)
 core-$(CONFIG_VFP)              += arch/arm/vfp/
 
+# If we have a machine-specific directory, then include it in the build.
+core-y                          += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
+core-y                          += $(machdirs) $(platdirs)
+
 drivers-$(CONFIG_OPROFILE)      += arch/arm/oprofile/
 
 libs-y                          := arch/arm/lib/ $(libs-y)
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index b23f6bc46cfa..65a7c1c588a9 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -116,5 +116,5 @@ CFLAGS_font.o := -Dstatic=
 $(obj)/font.c: $(FONTC)
         $(call cmd,shipped)
 
-$(obj)/vmlinux.lds: $(obj)/vmlinux.lds.in arch/arm/boot/Makefile .config
+$(obj)/vmlinux.lds: $(obj)/vmlinux.lds.in arch/arm/boot/Makefile $(KCONFIG_CONFIG)
         @sed "$(SEDFLAGS)" < $< > $@
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 7dfa9a85bc0c..ada6359160eb 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -67,25 +67,11 @@ static inline unsigned int gic_irq(unsigned int irq)
 
 /*
  * Routines to acknowledge, disable and enable interrupts
- *
- * Linux assumes that when we're done with an interrupt we need to
- * unmask it, in the same way we need to unmask an interrupt when
- * we first enable it.
- *
- * The GIC has a separate notion of "end of interrupt" to re-enable
- * an interrupt after handling, in order to support hardware
- * prioritisation.
- *
- * We can make the GIC behave in the way that Linux expects by making
- * our "acknowledge" routine disable the interrupt, then mark it as
- * complete.
  */
 static void gic_ack_irq(unsigned int irq)
 {
-        u32 mask = 1 << (irq % 32);
 
         spin_lock(&irq_controller_lock);
-        writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
         writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI);
         spin_unlock(&irq_controller_lock);
 }
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index 7974baacafce..1bec96e85196 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -271,6 +271,14 @@ int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
                 ((dma_addr + size - PHYS_OFFSET) >= SZ_64M);
 }
 
+int dma_set_coherent_mask(struct device *dev, u64 mask)
+{
+        if (mask >= PHYS_OFFSET + SZ_64M - 1)
+                return 0;
+
+        return -EIO;
+}
+
 int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
 {
         it8152_io.start = IT8152_IO_BASE + 0x12000;
diff --git a/arch/arm/configs/at91sam9g20ek_defconfig b/arch/arm/configs/at91sam9g20ek_defconfig
index f1bac70d6ce9..9e90e6d79297 100644
--- a/arch/arm/configs/at91sam9g20ek_defconfig
+++ b/arch/arm/configs/at91sam9g20ek_defconfig
@@ -13,6 +13,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9G20=y
 CONFIG_MACH_AT91SAM9G20EK=y
+CONFIG_MACH_AT91SAM9G20EK_2MMC=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index ccc9c9959b82..2f7042813765 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -15,6 +15,7 @@ CONFIG_MACH_MV88F6281GTW_GE=y
 CONFIG_MACH_SHEEVAPLUG=y
 CONFIG_MACH_ESATA_SHEEVAPLUG=y
 CONFIG_MACH_GURUPLUG=y
+CONFIG_MACH_DOCKSTAR=y
 CONFIG_MACH_TS219=y
 CONFIG_MACH_TS41X=y
 CONFIG_MACH_OPENRD_BASE=y
diff --git a/arch/arm/configs/s5p6440_defconfig b/arch/arm/configs/s5p64x0_defconfig
index 0b0266c6d326..2993ecd35145 100644
--- a/arch/arm/configs/s5p6440_defconfig
+++ b/arch/arm/configs/s5p64x0_defconfig
@@ -5,10 +5,11 @@ CONFIG_KALLSYMS_ALL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_S5P6440=y
+CONFIG_ARCH_S5P64X0=y
 CONFIG_S3C_BOOT_ERROR_RESET=y
 CONFIG_S3C_LOWLEVEL_UART_PORT=1
 CONFIG_MACH_SMDK6440=y
+CONFIG_MACH_SMDK6450=y
 CONFIG_CPU_32v6K=y
 CONFIG_AEABI=y
 CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc"
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 5747a8baa413..8bb66bca2e3e 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -127,4 +127,8 @@ struct mm_struct;
 extern unsigned long arch_randomize_brk(struct mm_struct *mm);
 #define arch_randomize_brk arch_randomize_brk
 
+extern int vectors_user_mapping(void);
+#define arch_setup_additional_pages(bprm, uses_interp) vectors_user_mapping()
+#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
+
 #endif
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 1261b1f928d9..815efa2d4e07 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -294,6 +294,7 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
 extern int valid_phys_addr_range(unsigned long addr, size_t size);
 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
+extern int devmem_is_allowed(unsigned long pfn);
 #endif
 
 /*
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index a0b3cac0547c..71605d9f8e42 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -18,7 +18,6 @@
 #include <asm/cacheflush.h>
 #include <asm/cachetype.h>
 #include <asm/proc-fns.h>
-#include <asm-generic/mm_hooks.h>
 
 void __check_kvm_seq(struct mm_struct *mm);
 
@@ -134,4 +133,32 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
 #define deactivate_mm(tsk,mm)   do { } while (0)
 #define activate_mm(prev,next)  switch_mm(prev, next, NULL)
 
+/*
+ * We are inserting a "fake" vma for the user-accessible vector page so
+ * gdb and friends can get to it through ptrace and /proc/<pid>/mem.
+ * But we also want to remove it before the generic code gets to see it
+ * during process exit or the unmapping of it would  cause total havoc.
+ * (the macro is used as remove_vma() is static to mm/mmap.c)
+ */
+#define arch_exit_mmap(mm) \
+do { \
+        struct vm_area_struct *high_vma = find_vma(mm, 0xffff0000); \
+        if (high_vma) { \
+                BUG_ON(high_vma->vm_next);  /* it should be last */ \
+                if (high_vma->vm_prev) \
+                        high_vma->vm_prev->vm_next = NULL; \
+                else \
+                        mm->mmap = NULL; \
+                rb_erase(&high_vma->vm_rb, &mm->mm_rb); \
+                mm->mmap_cache = NULL; \
+                mm->map_count--; \
+                remove_vma(high_vma); \
+        } \
+} while (0)
+
+static inline void arch_dup_mmap(struct mm_struct *oldmm,
+                                 struct mm_struct *mm)
+{
+}
+
 #endif
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index ab68cf1ef80f..e90b167ea848 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -317,6 +317,10 @@ static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
 #define pgprot_dmacoherent(prot) \
         __pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_BUFFERABLE)
+#define __HAVE_PHYS_MEM_ACCESS_PROT
+struct file;
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+                                     unsigned long size, pgprot_t vma_prot);
 #else
 #define pgprot_dmacoherent(prot) \
         __pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_UNCACHED)
diff --git a/arch/arm/include/asm/seccomp.h b/arch/arm/include/asm/seccomp.h
new file mode 100644
index 000000000000..52b156b341f5
--- /dev/null
+++ b/arch/arm/include/asm/seccomp.h
@@ -0,0 +1,11 @@
+#ifndef _ASM_ARM_SECCOMP_H
+#define _ASM_ARM_SECCOMP_H
+
+#include <linux/unistd.h>
+
+#define __NR_seccomp_read __NR_read
+#define __NR_seccomp_write __NR_write
+#define __NR_seccomp_exit __NR_exit
+#define __NR_seccomp_sigreturn __NR_rt_sigreturn
+
+#endif /* _ASM_ARM_SECCOMP_H */
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index 763e29fa8530..7b5cc8dae06e 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -144,6 +144,7 @@ extern void vfp_flush_hwstate(struct thread_info *);
 #define TIF_MEMDIE              18      /* is terminating due to OOM killer */
 #define TIF_FREEZE              19
 #define TIF_RESTORE_SIGMASK     20
+#define TIF_SECCOMP             21
 
 #define _TIF_SIGPENDING         (1 << TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1 << TIF_NEED_RESCHED)
@@ -153,6 +154,7 @@ extern void vfp_flush_hwstate(struct thread_info *);
 #define _TIF_USING_IWMMXT       (1 << TIF_USING_IWMMXT)
 #define _TIF_FREEZE             (1 << TIF_FREEZE)
 #define _TIF_RESTORE_SIGMASK    (1 << TIF_RESTORE_SIGMASK)
+#define _TIF_SECCOMP            (1 << TIF_SECCOMP)
 
 /*
  * Change these and you break ASM code in entry-common.S
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index f05a35a59694..0385a8207b67 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -48,6 +48,8 @@ work_pending:
         beq     no_work_pending
         mov     r0, sp                          @ 'regs'
         mov     r2, why                         @ 'syscall'
+        tst     r1, #_TIF_SIGPENDING            @ delivering a signal?
+        movne   why, #0                         @ prevent further restarts
         bl      do_notify_resume
         b       ret_slow_syscall                @ Check work again
 
@@ -293,7 +295,6 @@ ENTRY(vector_swi)
 
         get_thread_info tsk
         adr     tbl, sys_call_table             @ load syscall table pointer
-        ldr     ip, [tsk, #TI_FLAGS]            @ check for syscall tracing
 
 #if defined(CONFIG_OABI_COMPAT)
         /*
@@ -310,8 +311,20 @@ ENTRY(vector_swi)
         eor     scno, scno, #__NR_SYSCALL_BASE  @ check OS number
 #endif
 
+        ldr     r10, [tsk, #TI_FLAGS]           @ check for syscall tracing
         stmdb   sp!, {r4, r5}                   @ push fifth and sixth args
-        tst     ip, #_TIF_SYSCALL_TRACE         @ are we tracing syscalls?
+
+#ifdef CONFIG_SECCOMP
+        tst     r10, #_TIF_SECCOMP
+        beq     1f
+        mov     r0, scno
+        bl      __secure_computing      
+        add     r0, sp, #S_R0 + S_OFF           @ pointer to regs
+        ldmia   r0, {r0 - r3}                   @ have to reload r0 - r3
+1:
+#endif
+
+        tst     r10, #_TIF_SYSCALL_TRACE                @ are we tracing syscalls?
         bne     __sys_trace
 
         cmp     scno, #NR_syscalls              @ check upper syscall limit
@@ -418,11 +431,13 @@ ENDPROC(sys_clone_wrapper)
 
 sys_sigreturn_wrapper:
                 add     r0, sp, #S_OFF
+                mov     why, #0         @ prevent syscall restart handling
                 b       sys_sigreturn
 ENDPROC(sys_sigreturn_wrapper)
 
 sys_rt_sigreturn_wrapper:
                 add     r0, sp, #S_OFF
+                mov     why, #0         @ prevent syscall restart handling
                 b       sys_rt_sigreturn
 ENDPROC(sys_rt_sigreturn_wrapper)
 
diff --git a/arch/arm/kernel/kprobes-decode.c b/arch/arm/kernel/kprobes-decode.c
index 8bccbfa693ff..2c1f0050c9c4 100644
--- a/arch/arm/kernel/kprobes-decode.c
+++ b/arch/arm/kernel/kprobes-decode.c
@@ -1162,11 +1162,12 @@ space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
 {
         /*
          * MSR   : cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx
-         * Undef : cccc 0011 0x00 xxxx xxxx xxxx xxxx xxxx
+         * Undef : cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx
          * ALU op with S bit and Rd == 15 :
          *         cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx
          */
-        if ((insn & 0x0f900000) == 0x03200000 ||        /* MSR & Undef */
+        if ((insn & 0x0fb00000) == 0x03200000 ||        /* MSR */
+            (insn & 0x0ff00000) == 0x03400000 ||        /* Undef */
             (insn & 0x0e10f000) == 0x0210f000)          /* ALU s-bit, R15  */
                 return INSN_REJECTED;
 
@@ -1177,7 +1178,7 @@ space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
          * *S (bit 20) updates condition codes
          * ADC/SBC/RSC reads the C flag
          */
-        insn &= 0xfff00fff;     /* Rn = r0, Rd = r0 */
+        insn &= 0xffff0fff;     /* Rd = r0 */
         asi->insn[0] = insn;
         asi->insn_handler = (insn & (1 << 20)) ?  /* S-bit */
                         emulate_alu_imm_rwflags : emulate_alu_imm_rflags;
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 401e38be1f78..66ac9c926200 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -458,3 +458,24 @@ unsigned long arch_randomize_brk(struct mm_struct *mm)
         unsigned long range_end = mm->brk + 0x02000000;
         return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
 }
+
+/*
+ * The vectors page is always readable from user space for the
+ * atomic helpers and the signal restart code.  Let's declare a mapping
+ * for it so it is visible through ptrace and /proc/<pid>/mem.
+ */
+
+int vectors_user_mapping(void)
+{
+        struct mm_struct *mm = current->mm;
+        return install_special_mapping(mm, 0xffff0000, PAGE_SIZE,
+                                       VM_READ | VM_EXEC |
+                                       VM_MAYREAD | VM_MAYEXEC |
+                                       VM_ALWAYSDUMP | VM_RESERVED,
+                                       NULL);
+}
+
+const char *arch_vma_name(struct vm_area_struct *vma)
+{
+        return (vma->vm_start == 0xffff0000) ? "[vectors]" : NULL;
+}
diff --git a/arch/arm/mach-aaec2000/include/mach/vmalloc.h b/arch/arm/mach-aaec2000/include/mach/vmalloc.h
index 551f68f666bf..cff4e0a996ce 100644
--- a/arch/arm/mach-aaec2000/include/mach/vmalloc.h
+++ b/arch/arm/mach-aaec2000/include/mach/vmalloc.h
@@ -11,6 +11,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END             (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END             0xd0000000
 
 #endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 939bccd70569..bbd5efa65099 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -33,6 +33,7 @@ config ARCH_AT91SAM9260
         select HAVE_AT91_USART3
         select HAVE_AT91_USART4
         select HAVE_AT91_USART5
+        select HAVE_NET_MACB
 
 config ARCH_AT91SAM9261
         bool "AT91SAM9261"
@@ -51,6 +52,7 @@ config ARCH_AT91SAM9263
         select CPU_ARM926T
         select GENERIC_CLOCKEVENTS
         select HAVE_FB_ATMEL
+        select HAVE_NET_MACB
 
 config ARCH_AT91SAM9RL
         bool "AT91SAM9RL"
@@ -66,6 +68,7 @@ config ARCH_AT91SAM9G20
         select HAVE_AT91_USART3
         select HAVE_AT91_USART4
         select HAVE_AT91_USART5
+        select HAVE_NET_MACB
 
 config ARCH_AT91SAM9G45
         bool "AT91SAM9G45"
@@ -73,6 +76,7 @@ config ARCH_AT91SAM9G45
         select GENERIC_CLOCKEVENTS
         select HAVE_AT91_USART3
         select HAVE_FB_ATMEL
+        select HAVE_NET_MACB
 
 config ARCH_AT91CAP9
         bool "AT91CAP9"
@@ -338,6 +342,7 @@ config MACH_AT91SAM9G20EK
           that embeds only one SD/MMC slot.
 
 config MACH_AT91SAM9G20EK_2MMC
+        depends on MACH_AT91SAM9G20EK
         bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots"
         select HAVE_NAND_ATMEL_BUSWIDTH_16
         help
@@ -383,8 +388,8 @@ if ARCH_AT91SAM9G45
 
 comment "AT91SAM9G45 Board Type"
 
-config MACH_AT91SAM9G45EKES
-        bool "Atmel AT91SAM9G45-EKES Evaluation Kit"
+config MACH_AT91SAM9M10G45EK
+        bool "Atmel AT91SAM9M10G45-EK Evaluation Kits"
         select HAVE_NAND_ATMEL_BUSWIDTH_16
         help
           Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit.
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index ca2ac003f41f..3a07a3696441 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -61,7 +61,6 @@ obj-$(CONFIG_MACH_AT91SAM9RLEK)	+= board-sam9rlek.o
 
 # AT91SAM9G20 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
-obj-$(CONFIG_MACH_AT91SAM9G20EK_2MMC) += board-sam9g20ek-2slot-mmc.o
 obj-$(CONFIG_MACH_CPU9G20)      += board-cpu9krea.o
 obj-$(CONFIG_MACH_STAMP9G20)    += board-stamp9g20.o
 obj-$(CONFIG_MACH_PORTUXG20)    += board-stamp9g20.o
@@ -70,7 +69,7 @@ obj-$(CONFIG_MACH_PORTUXG20)	+= board-stamp9g20.o
 obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
 
 # AT91SAM9G45 board-specific support
-obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o
+obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
 
 # AT91CAP9 board-specific support
 obj-$(CONFIG_MACH_AT91CAP9ADK)  += board-cap9adk.o
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 5e71ccd5e7d3..1276babf84d5 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -426,7 +426,7 @@ static struct i2c_gpio_platform_data pdata_i2c0 = {
         .sda_is_open_drain      = 1,
         .scl_pin                = AT91_PIN_PA21,
         .scl_is_open_drain      = 1,
-        .udelay                 = 2,            /* ~100 kHz */
+        .udelay                 = 5,            /* ~100 kHz */
 };
 
 static struct platform_device at91sam9g45_twi0_device = {
@@ -440,7 +440,7 @@ static struct i2c_gpio_platform_data pdata_i2c1 = {
         .sda_is_open_drain      = 1,
         .scl_pin                = AT91_PIN_PB11,
         .scl_is_open_drain      = 1,
-        .udelay                 = 2,            /* ~100 kHz */
+        .udelay                 = 5,            /* ~100 kHz */
 };
 
 static struct platform_device at91sam9g45_twi1_device = {
diff --git a/arch/arm/mach-at91/board-at572d940hf_ek.c b/arch/arm/mach-at91/board-at572d940hf_ek.c
index 5daff277f53e..46651623f208 100644
--- a/arch/arm/mach-at91/board-at572d940hf_ek.c
+++ b/arch/arm/mach-at91/board-at572d940hf_ek.c
@@ -216,7 +216,7 @@ static struct atmel_nand_data __initdata eb_nand_data = {
 /*      .rdy_pin        = AT91_PIN_PC16, */
         .enable_pin     = AT91_PIN_PA15,
         .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
         .bus_width_16   = 1,
 #else
         .bus_width_16   = 0,
diff --git a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c b/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
deleted file mode 100644
index c49f5c003ee1..000000000000
--- a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2008 Atmel
- *  Copyright (C) 2009 Rob Emanuele
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/at73c213.h>
-#include <linux/clk.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/consumer.h>
-
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <mach/board.h>
-#include <mach/gpio.h>
-#include <mach/at91sam9_smc.h>
-
-#include "sam9_smc.h"
-#include "generic.h"
-
-
-static void __init ek_map_io(void)
-{
-        /* Initialize processor: 18.432 MHz crystal */
-        at91sam9260_initialize(18432000);
-
-        /* DGBU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                           | ATMEL_UART_RI);
-
-        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
-
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
-}
-
-static void __init ek_init_irq(void)
-{
-        at91sam9260_init_interrupts(NULL);
-}
-
-
-/*
- * USB Host port
- */
-static struct at91_usbh_data __initdata ek_usbh_data = {
-        .ports          = 2,
-};
-
-/*
- * USB Device port
- */
-static struct at91_udc_data __initdata ek_udc_data = {
-        .vbus_pin       = AT91_PIN_PC5,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
-};
-
-
-/*
- * SPI devices.
- */
-static struct spi_board_info ek_spi_devices[] = {
-#if !(defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_AT91))
-        {       /* DataFlash chip */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 1,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
-        {       /* DataFlash card */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-#endif
-#endif
-};
-
-
-/*
- * MACB Ethernet device
- */
-static struct at91_eth_data __initdata ek_macb_data = {
-        .phy_irq_pin    = AT91_PIN_PB0,
-        .is_rmii        = 1,
-};
-
-
-/*
- * NAND flash
- */
-static struct mtd_partition __initdata ek_nand_partition[] = {
-        {
-                .name   = "Bootstrap",
-                .offset = 0,
-                .size   = 4 * SZ_1M,
-        },
-        {
-                .name   = "Partition 1",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = 60 * SZ_1M,
-        },
-        {
-                .name   = "Partition 2",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = MTDPART_SIZ_FULL,
-        },
-};
-
-static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
-{
-        *num_partitions = ARRAY_SIZE(ek_nand_partition);
-        return ek_nand_partition;
-}
-
-/* det_pin is not connected */
-static struct atmel_nand_data __initdata ek_nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .rdy_pin        = AT91_PIN_PC13,
-        .enable_pin     = AT91_PIN_PC14,
-        .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
-        .bus_width_16   = 1,
-#else
-        .bus_width_16   = 0,
-#endif
-};
-
-static struct sam9_smc_config __initdata ek_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 2,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 2,
-
-        .ncs_read_pulse         = 4,
-        .nrd_pulse              = 4,
-        .ncs_write_pulse        = 4,
-        .nwe_pulse              = 4,
-
-        .read_cycle             = 7,
-        .write_cycle            = 7,
-
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
-        .tdf_cycles             = 3,
-};
-
-static void __init ek_add_device_nand(void)
-{
-        /* setup bus-width (8 or 16) */
-        if (ek_nand_data.bus_width_16)
-                ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
-        else
-                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
-
-        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &ek_nand_smc_config);
-
-        at91_add_device_nand(&ek_nand_data);
-}
-
-
-/*
- * MCI (SD/MMC)
- * wp_pin is not connected
- */
-#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
-static struct mci_platform_data __initdata ek_mmc_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PC2,
-                .wp_pin         = -ENODEV,
-        },
-        .slot[1] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PC9,
-                .wp_pin         = -ENODEV,
-        },
-
-};
-#else
-static struct at91_mmc_data __initdata ek_mmc_data = {
-        .slot_b         = 1,    /* Only one slot so use slot B */
-        .wire4          = 1,
-        .det_pin        = AT91_PIN_PC9,
-};
-#endif
-
-/*
- * LEDs
- */
-static struct gpio_led ek_leds[] = {
-        {       /* "bottom" led, green, userled1 to be defined */
-                .name                   = "ds5",
-                .gpio                   = AT91_PIN_PB8,
-                .active_low             = 1,
-                .default_trigger        = "none",
-        },
-        {       /* "power" led, yellow */
-                .name                   = "ds1",
-                .gpio                   = AT91_PIN_PB9,
-                .default_trigger        = "heartbeat",
-        }
-};
-
-#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
-static struct regulator_consumer_supply ek_audio_consumer_supplies[] = {
-        REGULATOR_SUPPLY("AVDD", "0-001b"),
-        REGULATOR_SUPPLY("HPVDD", "0-001b"),
-        REGULATOR_SUPPLY("DBVDD", "0-001b"),
-        REGULATOR_SUPPLY("DCVDD", "0-001b"),
-};
-
-static struct regulator_init_data ek_avdd_reg_init_data = {
-        .constraints    = {
-                .name   = "3V3",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .consumer_supplies = ek_audio_consumer_supplies,
-        .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies),
-};
-
-static struct fixed_voltage_config ek_vdd_pdata = {
-        .supply_name    = "board-3V3",
-        .microvolts     = 3300000,
-        .gpio           = -EINVAL,
-        .enabled_at_boot = 0,
-        .init_data      = &ek_avdd_reg_init_data,
-};
-static struct platform_device ek_voltage_regulator = {
-        .name           = "reg-fixed-voltage",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &ek_vdd_pdata,
-        },
-};
-static void __init ek_add_regulators(void)
-{
-        platform_device_register(&ek_voltage_regulator);
-}
-#else
-static void __init ek_add_regulators(void) {}
-#endif
-
-static struct i2c_board_info __initdata ek_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("24c512", 0x50),
-        },
-};
-
-
-static void __init ek_board_init(void)
-{
-        /* Serial */
-        at91_add_device_serial();
-        /* USB Host */
-        at91_add_device_usbh(&ek_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&ek_udc_data);
-        /* SPI */
-        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
-        /* NAND */
-        ek_add_device_nand();
-        /* Ethernet */
-        at91_add_device_eth(&ek_macb_data);
-        /* Regulators */
-        ek_add_regulators();
-        /* MMC */
-#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
-        at91_add_device_mci(0, &ek_mmc_data);
-#else
-        at91_add_device_mmc(0, &ek_mmc_data);
-#endif
-        /* I2C */
-        at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
-        /* LEDs */
-        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
-        /* PCK0 provides MCLK to the WM8731 */
-        at91_set_B_periph(AT91_PIN_PC1, 0);
-        /* SSC (for WM8731) */
-        at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
-}
-
-MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
-        /* Maintainer: Rob Emanuele */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
-        .timer          = &at91sam926x_timer,
-        .map_io         = ek_map_io,
-        .init_irq       = ek_init_irq,
-        .init_machine   = ek_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 6ea9808b8868..b463e340c4a0 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -47,6 +47,18 @@
 #include "sam9_smc.h"
 #include "generic.h"
 
+/*
+ * board revision encoding
+ * bit 0:
+ *      0 => 1 sd/mmc slot
+ *      1 => 2 sd/mmc slots connectors (board from revision C)
+ */
+#define HAVE_2MMC       (1 << 0)
+static int inline ek_have_2mmc(void)
+{
+        return machine_is_at91sam9g20ek_2mmc() || (system_rev & HAVE_2MMC);
+}
+
 
 static void __init ek_map_io(void)
 {
@@ -94,7 +106,7 @@ static struct at91_udc_data __initdata ek_udc_data = {
  * SPI devices.
  */
 static struct spi_board_info ek_spi_devices[] = {
-#if !defined(CONFIG_MMC_AT91)
+#if !(defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_AT91))
         {       /* DataFlash chip */
                 .modalias       = "mtd_dataflash",
                 .chip_select    = 1,
@@ -121,6 +133,13 @@ static struct at91_eth_data __initdata ek_macb_data = {
         .is_rmii        = 1,
 };
 
+static void __init ek_add_device_macb(void)
+{
+        if (ek_have_2mmc())
+                ek_macb_data.phy_irq_pin = AT91_PIN_PB0;
+
+        at91_add_device_eth(&ek_macb_data);
+}
 
 /*
  * NAND flash
@@ -198,13 +217,36 @@ static void __init ek_add_device_nand(void)
 
 /*
  * MCI (SD/MMC)
- * det_pin, wp_pin and vcc_pin are not connected
+ * wp_pin and vcc_pin are not connected
  */
+#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
+static struct mci_platform_data __initdata ek_mmc_data = {
+        .slot[1] = {
+                .bus_width      = 4,
+                .detect_pin     = AT91_PIN_PC9,
+        },
+
+};
+#else
 static struct at91_mmc_data __initdata ek_mmc_data = {
-        .slot_b         = 1,
+        .slot_b         = 1,    /* Only one slot so use slot B */
         .wire4          = 1,
+        .det_pin        = AT91_PIN_PC9,
 };
+#endif
 
+static void __init ek_add_device_mmc(void)
+{
+#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
+        if (ek_have_2mmc()) {
+                ek_mmc_data.slot[0].bus_width = 4;
+                ek_mmc_data.slot[0].detect_pin = AT91_PIN_PC2;
+        }
+        at91_add_device_mci(0, &ek_mmc_data);
+#else
+        at91_add_device_mmc(0, &ek_mmc_data);
+#endif
+}
 
 /*
  * LEDs
@@ -223,6 +265,15 @@ static struct gpio_led ek_leds[] = {
         }
 };
 
+static void __init ek_add_device_gpio_leds(void)
+{
+        if (ek_have_2mmc()) {
+                ek_leds[0].gpio = AT91_PIN_PB8;
+                ek_leds[1].gpio = AT91_PIN_PB9;
+        }
+
+        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+}
 
 /*
  * GPIO Buttons
@@ -336,15 +387,15 @@ static void __init ek_board_init(void)
         /* NAND */
         ek_add_device_nand();
         /* Ethernet */
-        at91_add_device_eth(&ek_macb_data);
+        ek_add_device_macb();
         /* Regulators */
         ek_add_regulators();
         /* MMC */
-        at91_add_device_mmc(0, &ek_mmc_data);
+        ek_add_device_mmc();
         /* I2C */
         at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
         /* LEDs */
-        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+        ek_add_device_gpio_leds();
         /* Push Buttons */
         ek_add_device_buttons();
         /* PCK0 provides MCLK to the WM8731 */
@@ -363,3 +414,14 @@ MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
         .init_irq       = ek_init_irq,
         .init_machine   = ek_board_init,
 MACHINE_END
+
+MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
+        /* Maintainer: Atmel */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = ek_map_io,
+        .init_irq       = ek_init_irq,
+        .init_machine   = ek_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index ee800595594d..ae0e0843e5f5 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -135,7 +135,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .rdy_pin        = AT91_PIN_PC8,
         .enable_pin     = AT91_PIN_PC14,
         .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
         .bus_width_16   = 1,
 #else
         .bus_width_16   = 0,
@@ -399,7 +399,7 @@ static void __init ek_board_init(void)
         at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led));
 }
 
-MACHINE_START(AT91SAM9G45EKES, "Atmel AT91SAM9G45-EKES")
+MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
         /* Maintainer: Atmel */
         .phys_io        = AT91_BASE_SYS,
         .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h
index d34cdb8abdca..063ac44a0204 100644
--- a/arch/arm/mach-at91/include/mach/at91x40.h
+++ b/arch/arm/mach-at91/include/mach/at91x40.h
@@ -52,4 +52,10 @@
 #define AT91_DBGU_CIDR  (AT91_SF + 0)   /* CIDR in PS segment */
 #define AT91_DBGU_EXID  (AT91_SF + 4)   /* EXID in PS segment */
 
+/*
+ * Support defines for the simple Power Controller module.
+ */
+#define AT91_PS_CR      (AT91_PS + 0)   /* PS Control register */
+#define AT91_PS_CR_CPU  (1 << 0)        /* CPU clock disable bit */
+
 #endif /* AT91X40_H */
diff --git a/arch/arm/mach-at91/include/mach/system.h b/arch/arm/mach-at91/include/mach/system.h
index c80e090b3670..36af14bc13bb 100644
--- a/arch/arm/mach-at91/include/mach/system.h
+++ b/arch/arm/mach-at91/include/mach/system.h
@@ -28,17 +28,20 @@
 
 static inline void arch_idle(void)
 {
-#ifndef CONFIG_DEBUG_KERNEL
         /*
          * Disable the processor clock.  The processor will be automatically
          * re-enabled by an interrupt or by a reset.
          */
-        at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+#ifdef AT91_PS
+        at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
 #else
+        at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+#endif
+#ifndef CONFIG_CPU_ARM920T
         /*
          * Set the processor (CP15) into 'Wait for Interrupt' mode.
-         * Unlike disabling the processor clock via the PMC (above)
-         *  this allows the processor to be woken via JTAG.
+         * Post-RM9200 processors need this in conjunction with the above
+         * to save power when idle.
          */
         cpu_do_idle();
 #endif
diff --git a/arch/arm/mach-bcmring/include/mach/vmalloc.h b/arch/arm/mach-bcmring/include/mach/vmalloc.h
index 35e2ead8395c..3db3a09fd398 100644
--- a/arch/arm/mach-bcmring/include/mach/vmalloc.h
+++ b/arch/arm/mach-bcmring/include/mach/vmalloc.h
@@ -22,4 +22,4 @@
  * 0xe0000000 to 0xefffffff. This gives us 256 MB of vm space and handles
  * larger physical memory designs better.
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x30000000)
+#define VMALLOC_END       0xf0000000
diff --git a/arch/arm/mach-clps711x/include/mach/vmalloc.h b/arch/arm/mach-clps711x/include/mach/vmalloc.h
index ea6cc7beff28..30b3a287ed88 100644
--- a/arch/arm/mach-clps711x/include/mach/vmalloc.h
+++ b/arch/arm/mach-clps711x/include/mach/vmalloc.h
@@ -17,4 +17,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END       0xd0000000
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 3d996b659ff4..9be261beae7d 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -769,8 +769,7 @@ static struct map_desc dm355_io_desc[] = {
                 .virtual        = SRAM_VIRT,
                 .pfn            = __phys_to_pfn(0x00010000),
                 .length         = SZ_32K,
-                /* MT_MEMORY_NONCACHED requires supersection alignment */
-                .type           = MT_DEVICE,
+                .type           = MT_MEMORY_NONCACHED,
         },
 };
 
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 6b6f4c643709..7781e35daec3 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -969,8 +969,7 @@ static struct map_desc dm365_io_desc[] = {
                 .virtual        = SRAM_VIRT,
                 .pfn            = __phys_to_pfn(0x00010000),
                 .length         = SZ_32K,
-                /* MT_MEMORY_NONCACHED requires supersection alignment */
-                .type           = MT_DEVICE,
+                .type           = MT_MEMORY_NONCACHED,
         },
 };
 
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 40fec315c99a..5e5b0a7831fb 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -653,8 +653,7 @@ static struct map_desc dm644x_io_desc[] = {
                 .virtual        = SRAM_VIRT,
                 .pfn            = __phys_to_pfn(0x00008000),
                 .length         = SZ_16K,
-                /* MT_MEMORY_NONCACHED requires supersection alignment */
-                .type           = MT_DEVICE,
+                .type           = MT_MEMORY_NONCACHED,
         },
 };
 
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index e4a3df1872ac..26e8a9c7f50b 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -737,8 +737,7 @@ static struct map_desc dm646x_io_desc[] = {
                 .virtual        = SRAM_VIRT,
                 .pfn            = __phys_to_pfn(0x00010000),
                 .length         = SZ_32K,
-                /* MT_MEMORY_NONCACHED requires supersection alignment */
-                .type           = MT_DEVICE,
+                .type           = MT_MEMORY_NONCACHED,
         },
 };
 
diff --git a/arch/arm/mach-dove/include/mach/io.h b/arch/arm/mach-dove/include/mach/io.h
index 3b3e4721ce2e..eb4936ff90ad 100644
--- a/arch/arm/mach-dove/include/mach/io.h
+++ b/arch/arm/mach-dove/include/mach/io.h
@@ -13,8 +13,8 @@
 
 #define IO_SPACE_LIMIT          0xffffffff
 
-#define __io(a)  ((void __iomem *)(((a) - DOVE_PCIE0_IO_PHYS_BASE) +\
-                                   DOVE_PCIE0_IO_VIRT_BASE))
-#define __mem_pci(a)            (a)
+#define __io(a)         ((void __iomem *)(((a) - DOVE_PCIE0_IO_BUS_BASE) + \
+                                                 DOVE_PCIE0_IO_VIRT_BASE))
+#define __mem_pci(a)    (a)
 
 #endif
diff --git a/arch/arm/mach-ebsa110/include/mach/vmalloc.h b/arch/arm/mach-ebsa110/include/mach/vmalloc.h
index 9b44c19e95ec..60bde56fba4c 100644
--- a/arch/arm/mach-ebsa110/include/mach/vmalloc.h
+++ b/arch/arm/mach-ebsa110/include/mach/vmalloc.h
@@ -7,4 +7,4 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x1f000000)
+#define VMALLOC_END       0xdf000000
diff --git a/arch/arm/mach-ep93xx/dma-m2p.c b/arch/arm/mach-ep93xx/dma-m2p.c
index 8904ca4e2e24..a696d354b1f8 100644
--- a/arch/arm/mach-ep93xx/dma-m2p.c
+++ b/arch/arm/mach-ep93xx/dma-m2p.c
@@ -276,7 +276,7 @@ static void channel_disable(struct m2p_channel *ch)
         v &= ~(M2P_CONTROL_STALL_IRQ_EN | M2P_CONTROL_NFB_IRQ_EN);
         m2p_set_control(ch, v);
 
-        while (m2p_channel_state(ch) == STATE_ON)
+        while (m2p_channel_state(ch) >= STATE_ON)
                 cpu_relax();
 
         m2p_set_control(ch, 0x0);
diff --git a/arch/arm/mach-footbridge/include/mach/vmalloc.h b/arch/arm/mach-footbridge/include/mach/vmalloc.h
index d0958d860a3c..0ffbb7c85e59 100644
--- a/arch/arm/mach-footbridge/include/mach/vmalloc.h
+++ b/arch/arm/mach-footbridge/include/mach/vmalloc.h
@@ -7,4 +7,4 @@
  */
 
 
-#define VMALLOC_END       (PAGE_OFFSET + 0x30000000)
+#define VMALLOC_END       0xf0000000
diff --git a/arch/arm/mach-h720x/include/mach/vmalloc.h b/arch/arm/mach-h720x/include/mach/vmalloc.h
index ff1460d6841b..a45915b88756 100644
--- a/arch/arm/mach-h720x/include/mach/vmalloc.h
+++ b/arch/arm/mach-h720x/include/mach/vmalloc.h
@@ -5,6 +5,6 @@
 #ifndef __ARCH_ARM_VMALLOC_H
 #define __ARCH_ARM_VMALLOC_H
 
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END       0xd0000000
 
 #endif
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 28f73a1c79f7..a1681fc9d9b0 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -258,7 +258,7 @@ static void __init eukrea_cpuimx27_init(void)
         i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
                                 ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
 
-        imx27_add_imx_i2c(1, &cpuimx27_i2c1_data);
+        imx27_add_imx_i2c(0, &cpuimx27_i2c1_data);
 
         imx27_add_fec(NULL);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
diff --git a/arch/arm/mach-integrator/include/mach/vmalloc.h b/arch/arm/mach-integrator/include/mach/vmalloc.h
index e87ab0b37bdd..e056e7cf5645 100644
--- a/arch/arm/mach-integrator/include/mach/vmalloc.h
+++ b/arch/arm/mach-integrator/include/mach/vmalloc.h
@@ -17,4 +17,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END       0xd0000000
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 61cd4d64b985..24498a932ba6 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -503,6 +503,14 @@ struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys)
         return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys);
 }
 
+int dma_set_coherent_mask(struct device *dev, u64 mask)
+{
+        if (mask >= SZ_64M - 1)
+                return 0;
+
+        return -EIO;
+}
+
 EXPORT_SYMBOL(ixp4xx_pci_read);
 EXPORT_SYMBOL(ixp4xx_pci_write);
 
diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h
index f91ca6d4fbe8..8138371c406e 100644
--- a/arch/arm/mach-ixp4xx/include/mach/hardware.h
+++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h
@@ -26,6 +26,8 @@
 #define PCIBIOS_MAX_MEM         0x4BFFFFFF
 #endif
 
+#define ARCH_HAS_DMA_SET_COHERENT_MASK
+
 #define pcibios_assign_all_busses()     1
 
 /* Register locations and bits */
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index cc25501b57fa..34106335c728 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -58,6 +58,12 @@ config MACH_TS41X
           QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS
           devices.
 
+config MACH_DOCKSTAR
+        bool "Seagate FreeAgent DockStar"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Seagate FreeAgent DockStar.
+
 config MACH_OPENRD
         bool
 
@@ -100,6 +106,12 @@ config MACH_NETSPACE_MAX_V2
           Say 'Y' here if you want your kernel to support the
           LaCie Network Space Max v2 NAS.
 
+config MACH_D2NET_V2
+        bool "LaCie d2 Network v2 NAS Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie d2 Network v2 NAS.
+
 config MACH_NET2BIG_V2
         bool "LaCie 2Big Network v2 NAS Board"
         help
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 295d7baa6ae1..5dcaa81a2ec3 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -7,14 +7,16 @@ obj-$(CONFIG_MACH_MV88F6281GTW_GE)	+= mv88f6281gtw_ge-setup.o
 obj-$(CONFIG_MACH_SHEEVAPLUG)           += sheevaplug-setup.o
 obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG)     += sheevaplug-setup.o
 obj-$(CONFIG_MACH_GURUPLUG)             += guruplug-setup.o
+obj-$(CONFIG_MACH_DOCKSTAR)             += dockstar-setup.o
 obj-$(CONFIG_MACH_TS219)                += ts219-setup.o tsx1x-common.o
 obj-$(CONFIG_MACH_TS41X)                += ts41x-setup.o tsx1x-common.o
 obj-$(CONFIG_MACH_OPENRD)               += openrd-setup.o
-obj-$(CONFIG_MACH_NETSPACE_V2)          += netspace_v2-setup.o
-obj-$(CONFIG_MACH_INETSPACE_V2)         += netspace_v2-setup.o
-obj-$(CONFIG_MACH_NETSPACE_MAX_V2)      += netspace_v2-setup.o
-obj-$(CONFIG_MACH_NET2BIG_V2)           += netxbig_v2-setup.o
-obj-$(CONFIG_MACH_NET5BIG_V2)           += netxbig_v2-setup.o
+obj-$(CONFIG_MACH_NETSPACE_V2)          += netspace_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_INETSPACE_V2)         += netspace_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_NETSPACE_MAX_V2)      += netspace_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_D2NET_V2)             += d2net_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_NET2BIG_V2)           += netxbig_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_NET5BIG_V2)           += netxbig_v2-setup.o lacie_v2-common.o
 obj-$(CONFIG_MACH_T5325)                += t5325-setup.o
 
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
diff --git a/arch/arm/mach-kirkwood/d2net_v2-setup.c b/arch/arm/mach-kirkwood/d2net_v2-setup.c
new file mode 100644
index 000000000000..cd62d0f82a73
--- /dev/null
+++ b/arch/arm/mach-kirkwood/d2net_v2-setup.c
@@ -0,0 +1,231 @@
+/*
+ * arch/arm/mach-kirkwood/d2net_v2-setup.c
+ *
+ * LaCie d2 Network Space v2 Board Setup
+ *
+ * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/input.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/leds.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include <mach/leds-ns2.h>
+#include "common.h"
+#include "mpp.h"
+#include "lacie_v2-common.h"
+
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+
+static struct mv643xx_eth_platform_data d2net_v2_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+
+static struct mv_sata_platform_data d2net_v2_sata_data = {
+        .n_ports        = 2,
+};
+
+/*****************************************************************************
+ * GPIO keys
+ ****************************************************************************/
+
+#define D2NET_V2_GPIO_PUSH_BUTTON          34
+#define D2NET_V2_GPIO_POWER_SWITCH_ON      13
+#define D2NET_V2_GPIO_POWER_SWITCH_OFF     15
+
+#define D2NET_V2_SWITCH_POWER_ON           0x1
+#define D2NET_V2_SWITCH_POWER_OFF          0x2
+
+static struct gpio_keys_button d2net_v2_buttons[] = {
+        [0] = {
+                .type           = EV_SW,
+                .code           = D2NET_V2_SWITCH_POWER_ON,
+                .gpio           = D2NET_V2_GPIO_POWER_SWITCH_ON,
+                .desc           = "Back power switch (on|auto)",
+                .active_low     = 0,
+        },
+        [1] = {
+                .type           = EV_SW,
+                .code           = D2NET_V2_SWITCH_POWER_OFF,
+                .gpio           = D2NET_V2_GPIO_POWER_SWITCH_OFF,
+                .desc           = "Back power switch (auto|off)",
+                .active_low     = 0,
+        },
+        [2] = {
+                .code           = KEY_POWER,
+                .gpio           = D2NET_V2_GPIO_PUSH_BUTTON,
+                .desc           = "Front Push Button",
+                .active_low     = 1,
+        },
+};
+
+static struct gpio_keys_platform_data d2net_v2_button_data = {
+        .buttons        = d2net_v2_buttons,
+        .nbuttons       = ARRAY_SIZE(d2net_v2_buttons),
+};
+
+static struct platform_device d2net_v2_gpio_buttons = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &d2net_v2_button_data,
+        },
+};
+
+/*****************************************************************************
+ * GPIO LEDs
+ ****************************************************************************/
+
+#define D2NET_V2_GPIO_RED_LED           12
+
+static struct gpio_led d2net_v2_gpio_led_pins[] = {
+        {
+                .name   = "d2net_v2:red:fail",
+                .gpio   = D2NET_V2_GPIO_RED_LED,
+        },
+};
+
+static struct gpio_led_platform_data d2net_v2_gpio_leds_data = {
+        .num_leds       = ARRAY_SIZE(d2net_v2_gpio_led_pins),
+        .leds           = d2net_v2_gpio_led_pins,
+};
+
+static struct platform_device d2net_v2_gpio_leds = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &d2net_v2_gpio_leds_data,
+        },
+};
+
+/*****************************************************************************
+ * Dual-GPIO CPLD LEDs
+ ****************************************************************************/
+
+#define D2NET_V2_GPIO_BLUE_LED_SLOW     29
+#define D2NET_V2_GPIO_BLUE_LED_CMD      30
+
+static struct ns2_led d2net_v2_led_pins[] = {
+        {
+                .name   = "d2net_v2:blue:sata",
+                .cmd    = D2NET_V2_GPIO_BLUE_LED_CMD,
+                .slow   = D2NET_V2_GPIO_BLUE_LED_SLOW,
+        },
+};
+
+static struct ns2_led_platform_data d2net_v2_leds_data = {
+        .num_leds       = ARRAY_SIZE(d2net_v2_led_pins),
+        .leds           = d2net_v2_led_pins,
+};
+
+static struct platform_device d2net_v2_leds = {
+        .name           = "leds-ns2",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &d2net_v2_leds_data,
+        },
+};
+
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+
+static unsigned int d2net_v2_mpp_config[] __initdata = {
+        MPP0_SPI_SCn,
+        MPP1_SPI_MOSI,
+        MPP2_SPI_SCK,
+        MPP3_SPI_MISO,
+        MPP6_SYSRST_OUTn,
+        MPP7_GPO,               /* Request power-off */
+        MPP8_TW0_SDA,
+        MPP9_TW0_SCK,
+        MPP10_UART0_TXD,
+        MPP11_UART0_RXD,
+        MPP12_GPO,              /* Red led */
+        MPP13_GPIO,             /* Rear power switch (on|auto) */
+        MPP14_GPIO,             /* USB fuse */
+        MPP15_GPIO,             /* Rear power switch (auto|off) */
+        MPP16_GPIO,             /* SATA 0 power */
+        MPP21_SATA0_ACTn,
+        MPP24_GPIO,             /* USB mode select */
+        MPP26_GPIO,             /* USB device vbus */
+        MPP28_GPIO,             /* USB enable host vbus */
+        MPP29_GPIO,             /* Blue led (slow register) */
+        MPP30_GPIO,             /* Blue led (command register) */
+        MPP34_GPIO,             /* Power button (1 = Released, 0 = Pushed) */
+        MPP35_GPIO,             /* Inhibit power-off */
+        0
+};
+
+#define D2NET_V2_GPIO_POWER_OFF         7
+
+static void d2net_v2_power_off(void)
+{
+        gpio_set_value(D2NET_V2_GPIO_POWER_OFF, 1);
+}
+
+static void __init d2net_v2_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+        kirkwood_mpp_conf(d2net_v2_mpp_config);
+
+        lacie_v2_hdd_power_init(1);
+
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&d2net_v2_ge00_data);
+        kirkwood_sata_init(&d2net_v2_sata_data);
+        kirkwood_uart0_init();
+        lacie_v2_register_flash();
+        lacie_v2_register_i2c_devices();
+
+        platform_device_register(&d2net_v2_leds);
+        platform_device_register(&d2net_v2_gpio_leds);
+        platform_device_register(&d2net_v2_gpio_buttons);
+
+        if (gpio_request(D2NET_V2_GPIO_POWER_OFF, "power-off") == 0 &&
+            gpio_direction_output(D2NET_V2_GPIO_POWER_OFF, 0) == 0)
+                pm_power_off = d2net_v2_power_off;
+        else
+                pr_err("d2net_v2: failed to configure power-off GPIO\n");
+}
+
+MACHINE_START(D2NET_V2, "LaCie d2 Network v2")
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = d2net_v2_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &lacie_v2_timer,
+MACHINE_END
diff --git a/arch/arm/mach-kirkwood/dockstar-setup.c b/arch/arm/mach-kirkwood/dockstar-setup.c
new file mode 100644
index 000000000000..a90475d5059c
--- /dev/null
+++ b/arch/arm/mach-kirkwood/dockstar-setup.c
@@ -0,0 +1,112 @@
+/*
+ * arch/arm/mach-kirkwood/dockstar-setup.c
+ *
+ * Seagate FreeAgent DockStar Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include <plat/mvsdio.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mtd_partition dockstar_nand_parts[] = {
+        {
+                .name = "u-boot",
+                .offset = 0,
+                .size = SZ_1M
+        }, {
+                .name = "uImage",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size = SZ_4M
+        }, {
+                .name = "root",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size = MTDPART_SIZ_FULL
+        },
+};
+
+static struct mv643xx_eth_platform_data dockstar_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+
+static struct gpio_led dockstar_led_pins[] = {
+        {
+                .name                   = "dockstar:green:health",
+                .default_trigger        = "default-on",
+                .gpio                   = 46,
+                .active_low             = 1,
+        },
+        {
+                .name                   = "dockstar:orange:misc",
+                .default_trigger        = "none",
+                .gpio                   = 47,
+                .active_low             = 1,
+        },
+};
+
+static struct gpio_led_platform_data dockstar_led_data = {
+        .leds           = dockstar_led_pins,
+        .num_leds       = ARRAY_SIZE(dockstar_led_pins),
+};
+
+static struct platform_device dockstar_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &dockstar_led_data,
+        }
+};
+
+static unsigned int dockstar_mpp_config[] __initdata = {
+        MPP29_GPIO,     /* USB Power Enable */
+        MPP46_GPIO,     /* LED green */
+        MPP47_GPIO,     /* LED orange */
+        0
+};
+
+static void __init dockstar_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+
+        /* setup gpio pin select */
+        kirkwood_mpp_conf(dockstar_mpp_config);
+
+        kirkwood_uart0_init();
+        kirkwood_nand_init(ARRAY_AND_SIZE(dockstar_nand_parts), 25);
+
+        if (gpio_request(29, "USB Power Enable") != 0 ||
+            gpio_direction_output(29, 1) != 0)
+                printk(KERN_ERR "can't set up GPIO 29 (USB Power Enable)\n");
+        kirkwood_ehci_init();
+
+        kirkwood_ge00_init(&dockstar_ge00_data);
+
+        platform_device_register(&dockstar_leds);
+}
+
+MACHINE_START(DOCKSTAR, "Seagate FreeAgent DockStar")
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = dockstar_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+MACHINE_END
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index 93fc2ec95e76..6e924b398919 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -38,7 +38,7 @@
 
 #define KIRKWOOD_PCIE1_IO_PHYS_BASE     0xf3000000
 #define KIRKWOOD_PCIE1_IO_VIRT_BASE     0xfef00000
-#define KIRKWOOD_PCIE1_IO_BUS_BASE      0x00000000
+#define KIRKWOOD_PCIE1_IO_BUS_BASE      0x00100000
 #define KIRKWOOD_PCIE1_IO_SIZE          SZ_1M
 
 #define KIRKWOOD_PCIE_IO_PHYS_BASE      0xf2000000
diff --git a/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h b/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h
new file mode 100644
index 000000000000..24b536ebdf13
--- /dev/null
+++ b/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h
@@ -0,0 +1,55 @@
+/*
+ * arch/arm/mach-kirkwood/include/mach/leds-netxbig.h
+ *
+ * Platform data structure for netxbig LED driver
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_LEDS_NETXBIG_H
+#define __MACH_LEDS_NETXBIG_H
+
+struct netxbig_gpio_ext {
+        unsigned        *addr;
+        int             num_addr;
+        unsigned        *data;
+        int             num_data;
+        unsigned        enable;
+};
+
+enum netxbig_led_mode {
+        NETXBIG_LED_OFF,
+        NETXBIG_LED_ON,
+        NETXBIG_LED_SATA,
+        NETXBIG_LED_TIMER1,
+        NETXBIG_LED_TIMER2,
+        NETXBIG_LED_MODE_NUM,
+};
+
+#define NETXBIG_LED_INVALID_MODE NETXBIG_LED_MODE_NUM
+
+struct netxbig_led_timer {
+        unsigned long           delay_on;
+        unsigned long           delay_off;
+        enum netxbig_led_mode   mode;
+};
+
+struct netxbig_led {
+        const char      *name;
+        const char      *default_trigger;
+        int             mode_addr;
+        int             *mode_val;
+        int             bright_addr;
+};
+
+struct netxbig_led_platform_data {
+        struct netxbig_gpio_ext *gpio_ext;
+        struct netxbig_led_timer *timer;
+        int                     num_timer;
+        struct netxbig_led      *leds;
+        int                     num_leds;
+};
+
+#endif /* __MACH_LEDS_NETXBIG_H */
diff --git a/arch/arm/mach-kirkwood/lacie_v2-common.c b/arch/arm/mach-kirkwood/lacie_v2-common.c
new file mode 100644
index 000000000000..d3ea1b6c8a02
--- /dev/null
+++ b/arch/arm/mach-kirkwood/lacie_v2-common.c
@@ -0,0 +1,127 @@
+/*
+ * arch/arm/mach-kirkwood/lacie_v2-common.c
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <linux/gpio.h>
+#include <asm/mach/time.h>
+#include <mach/kirkwood.h>
+#include <mach/irqs.h>
+#include <plat/time.h>
+#include "common.h"
+
+/*****************************************************************************
+ * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005)
+ ****************************************************************************/
+
+static struct mtd_partition lacie_v2_flash_parts[] = {
+        {
+                .name = "u-boot",
+                .size = MTDPART_SIZ_FULL,
+                .offset = 0,
+                .mask_flags = MTD_WRITEABLE, /* force read-only */
+        },
+};
+
+static const struct flash_platform_data lacie_v2_flash = {
+        .type           = "mx25l4005a",
+        .name           = "spi_flash",
+        .parts          = lacie_v2_flash_parts,
+        .nr_parts       = ARRAY_SIZE(lacie_v2_flash_parts),
+};
+
+static struct spi_board_info __initdata lacie_v2_spi_slave_info[] = {
+        {
+                .modalias       = "m25p80",
+                .platform_data  = &lacie_v2_flash,
+                .irq            = -1,
+                .max_speed_hz   = 20000000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+        },
+};
+
+void __init lacie_v2_register_flash(void)
+{
+        spi_register_board_info(lacie_v2_spi_slave_info,
+                                ARRAY_SIZE(lacie_v2_spi_slave_info));
+        kirkwood_spi_init();
+}
+
+/*****************************************************************************
+ * I2C devices
+ ****************************************************************************/
+
+static struct at24_platform_data at24c04 = {
+        .byte_len       = SZ_4K / 8,
+        .page_size      = 16,
+};
+
+/*
+ * i2c addr | chip         | description
+ * 0x50     | HT24LC04     | eeprom (512B)
+ */
+
+static struct i2c_board_info __initdata lacie_v2_i2c_info[] = {
+        {
+                I2C_BOARD_INFO("24c04", 0x50),
+                .platform_data  = &at24c04,
+        }
+};
+
+void __init lacie_v2_register_i2c_devices(void)
+{
+        kirkwood_i2c_init();
+        i2c_register_board_info(0, lacie_v2_i2c_info,
+                                ARRAY_SIZE(lacie_v2_i2c_info));
+}
+
+/*****************************************************************************
+ * Hard Disk power
+ ****************************************************************************/
+
+static int __initdata lacie_v2_gpio_hdd_power[] = { 16, 17, 41, 42, 43 };
+
+void __init lacie_v2_hdd_power_init(int hdd_num)
+{
+        int i;
+        int err;
+
+        /* Power up all hard disks. */
+        for (i = 0; i < hdd_num; i++) {
+                err = gpio_request(lacie_v2_gpio_hdd_power[i], NULL);
+                if (err == 0) {
+                        err = gpio_direction_output(
+                                        lacie_v2_gpio_hdd_power[i], 1);
+                        /* Free the HDD power GPIOs. This allow user-space to
+                         * configure them via the gpiolib sysfs interface. */
+                        gpio_free(lacie_v2_gpio_hdd_power[i]);
+                }
+                if (err)
+                        pr_err("Failed to power up HDD%d\n", i + 1);
+        }
+}
+
+/*****************************************************************************
+ * Timer
+ ****************************************************************************/
+
+static void lacie_v2_timer_init(void)
+{
+        kirkwood_tclk = 166666667;
+        orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
+}
+
+struct sys_timer lacie_v2_timer = {
+        .init = lacie_v2_timer_init,
+};
diff --git a/arch/arm/mach-kirkwood/lacie_v2-common.h b/arch/arm/mach-kirkwood/lacie_v2-common.h
new file mode 100644
index 000000000000..af521315b87b
--- /dev/null
+++ b/arch/arm/mach-kirkwood/lacie_v2-common.h
@@ -0,0 +1,18 @@
+/*
+ * arch/arm/mach-kirkwood/lacie_v2-common.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ARCH_KIRKWOOD_LACIE_V2_COMMON_H
+#define __ARCH_KIRKWOOD_LACIE_V2_COMMON_H
+
+void lacie_v2_register_flash(void);
+void lacie_v2_register_i2c_devices(void);
+void lacie_v2_hdd_power_init(int hdd_num);
+
+extern struct sys_timer lacie_v2_timer;
+
+#endif
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index d26bf324738b..fed264d28f4a 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -24,56 +24,19 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/i2c.h>
-#include <linux/i2c/at24.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/leds.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/time.h>
 #include <mach/kirkwood.h>
 #include <mach/leds-ns2.h>
-#include <plat/time.h>
 #include "common.h"
 #include "mpp.h"
-
-/*****************************************************************************
- * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005)
- ****************************************************************************/
-
-static struct mtd_partition netspace_v2_flash_parts[] = {
-        {
-                .name = "u-boot",
-                .size = MTDPART_SIZ_FULL,
-                .offset = 0,
-                .mask_flags = MTD_WRITEABLE, /* force read-only */
-        },
-};
-
-static const struct flash_platform_data netspace_v2_flash = {
-        .type           = "mx25l4005a",
-        .name           = "spi_flash",
-        .parts          = netspace_v2_flash_parts,
-        .nr_parts       = ARRAY_SIZE(netspace_v2_flash_parts),
-};
-
-static struct spi_board_info __initdata netspace_v2_spi_slave_info[] = {
-        {
-                .modalias       = "m25p80",
-                .platform_data  = &netspace_v2_flash,
-                .irq            = -1,
-                .max_speed_hz   = 20000000,
-                .bus_num        = 0,
-                .chip_select    = 0,
-        },
-};
+#include "lacie_v2-common.h"
 
 /*****************************************************************************
  * Ethernet
@@ -84,27 +47,6 @@ static struct mv643xx_eth_platform_data netspace_v2_ge00_data = {
 };
 
 /*****************************************************************************
- * I2C devices
- ****************************************************************************/
-
-static struct at24_platform_data at24c04 = {
-        .byte_len       = SZ_4K / 8,
-        .page_size      = 16,
-};
-
-/*
- * i2c addr | chip         | description
- * 0x50     | HT24LC04     | eeprom (512B)
- */
-
-static struct i2c_board_info __initdata netspace_v2_i2c_info[] = {
-        {
-                I2C_BOARD_INFO("24c04", 0x50),
-                .platform_data  = &at24c04,
-        }
-};
-
-/*****************************************************************************
  * SATA
  ****************************************************************************/
 
@@ -112,35 +54,6 @@ static struct mv_sata_platform_data netspace_v2_sata_data = {
         .n_ports        = 2,
 };
 
-#define NETSPACE_V2_GPIO_SATA0_POWER    16
-#define NETSPACE_V2_GPIO_SATA1_POWER    17
-
-static void __init netspace_v2_sata_power_init(void)
-{
-        int err;
-
-        err = gpio_request(NETSPACE_V2_GPIO_SATA0_POWER, "SATA0 power");
-        if (err == 0) {
-                err = gpio_direction_output(NETSPACE_V2_GPIO_SATA0_POWER, 1);
-                if (err)
-                        gpio_free(NETSPACE_V2_GPIO_SATA0_POWER);
-        }
-        if (err)
-                pr_err("netspace_v2: failed to setup SATA0 power\n");
-
-        if (machine_is_netspace_max_v2()) {
-                err = gpio_request(NETSPACE_V2_GPIO_SATA1_POWER, "SATA1 power");
-                if (err == 0) {
-                        err = gpio_direction_output(
-                                        NETSPACE_V2_GPIO_SATA1_POWER, 1);
-                        if (err)
-                                gpio_free(NETSPACE_V2_GPIO_SATA1_POWER);
-                }
-                if (err)
-                        pr_err("netspace_v2: failed to setup SATA1 power\n");
-        }
-}
-
 /*****************************************************************************
  * GPIO keys
  ****************************************************************************/
@@ -224,20 +137,6 @@ static struct platform_device netspace_v2_leds = {
 };
 
 /*****************************************************************************
- * Timer
- ****************************************************************************/
-
-static void netspace_v2_timer_init(void)
-{
-        kirkwood_tclk = 166666667;
-        orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
-}
-
-struct sys_timer netspace_v2_timer = {
-        .init = netspace_v2_timer_init,
-};
-
-/*****************************************************************************
  * General Setup
  ****************************************************************************/
 
@@ -291,18 +190,17 @@ static void __init netspace_v2_init(void)
         kirkwood_init();
         kirkwood_mpp_conf(netspace_v2_mpp_config);
 
-        netspace_v2_sata_power_init();
+        if (machine_is_netspace_max_v2())
+                lacie_v2_hdd_power_init(2);
+        else
+                lacie_v2_hdd_power_init(1);
 
         kirkwood_ehci_init();
         kirkwood_ge00_init(&netspace_v2_ge00_data);
         kirkwood_sata_init(&netspace_v2_sata_data);
         kirkwood_uart0_init();
-        spi_register_board_info(netspace_v2_spi_slave_info,
-                                ARRAY_SIZE(netspace_v2_spi_slave_info));
-        kirkwood_spi_init();
-        kirkwood_i2c_init();
-        i2c_register_board_info(0, netspace_v2_i2c_info,
-                                ARRAY_SIZE(netspace_v2_i2c_info));
+        lacie_v2_register_flash();
+        lacie_v2_register_i2c_devices();
 
         platform_device_register(&netspace_v2_leds);
         platform_device_register(&netspace_v2_gpio_leds);
@@ -323,7 +221,7 @@ MACHINE_START(NETSPACE_V2, "LaCie Network Space v2")
         .init_machine   = netspace_v2_init,
         .map_io         = kirkwood_map_io,
         .init_irq       = kirkwood_init_irq,
-        .timer          = &netspace_v2_timer,
+        .timer          = &lacie_v2_timer,
 MACHINE_END
 #endif
 
@@ -335,7 +233,7 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
         .init_machine   = netspace_v2_init,
         .map_io         = kirkwood_map_io,
         .init_irq       = kirkwood_init_irq,
-        .timer          = &netspace_v2_timer,
+        .timer          = &lacie_v2_timer,
 MACHINE_END
 #endif
 
@@ -347,6 +245,6 @@ MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
         .init_machine   = netspace_v2_init,
         .map_io         = kirkwood_map_io,
         .init_irq       = kirkwood_init_irq,
-        .timer          = &netspace_v2_timer,
+        .timer          = &lacie_v2_timer,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index 2bd14c5079de..d970e1eee37d 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -23,55 +23,19 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/i2c.h>
-#include <linux/i2c/at24.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/leds.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/time.h>
 #include <mach/kirkwood.h>
-#include <plat/time.h>
+#include <mach/leds-netxbig.h>
 #include "common.h"
 #include "mpp.h"
-
-/*****************************************************************************
- * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005)
- ****************************************************************************/
-
-static struct mtd_partition netxbig_v2_flash_parts[] = {
-        {
-                .name = "u-boot",
-                .size = MTDPART_SIZ_FULL,
-                .offset = 0,
-                .mask_flags = MTD_WRITEABLE, /* force read-only */
-        },
-};
-
-static const struct flash_platform_data netxbig_v2_flash = {
-        .type           = "mx25l4005a",
-        .name           = "spi_flash",
-        .parts          = netxbig_v2_flash_parts,
-        .nr_parts       = ARRAY_SIZE(netxbig_v2_flash_parts),
-};
-
-static struct spi_board_info __initdata netxbig_v2_spi_slave_info[] = {
-        {
-                .modalias       = "m25p80",
-                .platform_data  = &netxbig_v2_flash,
-                .irq            = -1,
-                .max_speed_hz   = 20000000,
-                .bus_num        = 0,
-                .chip_select    = 0,
-        },
-};
+#include "lacie_v2-common.h"
 
 /*****************************************************************************
  * Ethernet
@@ -86,27 +50,6 @@ static struct mv643xx_eth_platform_data netxbig_v2_ge01_data = {
 };
 
 /*****************************************************************************
- * I2C devices
- ****************************************************************************/
-
-static struct at24_platform_data at24c04 = {
-        .byte_len       = SZ_4K / 8,
-        .page_size      = 16,
-};
-
-/*
- * i2c addr | chip         | description
- * 0x50     | HT24LC04     | eeprom (512B)
- */
-
-static struct i2c_board_info __initdata netxbig_v2_i2c_info[] = {
-        {
-                I2C_BOARD_INFO("24c04", 0x50),
-                .platform_data  = &at24c04,
-        }
-};
-
-/*****************************************************************************
  * SATA
  ****************************************************************************/
 
@@ -114,34 +57,6 @@ static struct mv_sata_platform_data netxbig_v2_sata_data = {
         .n_ports        = 2,
 };
 
-static int __initdata netxbig_v2_gpio_hdd_power[] = { 16, 17, 41, 42, 43 };
-
-static void __init netxbig_v2_sata_power_init(void)
-{
-        int i;
-        int err;
-        int hdd_nb;
-
-        if (machine_is_net2big_v2())
-                hdd_nb = 2;
-        else
-                hdd_nb = 5;
-
-        /* Power up all hard disks. */
-        for (i = 0; i < hdd_nb; i++) {
-                err = gpio_request(netxbig_v2_gpio_hdd_power[i], NULL);
-                if (err == 0) {
-                        err = gpio_direction_output(
-                                        netxbig_v2_gpio_hdd_power[i], 1);
-                        /* Free the HDD power GPIOs. This allow user-space to
-                         * configure them via the gpiolib sysfs interface. */
-                        gpio_free(netxbig_v2_gpio_hdd_power[i]);
-                }
-                if (err)
-                        pr_err("netxbig_v2: failed to power up HDD%d\n", i + 1);
-        }
-}
-
 /*****************************************************************************
  * GPIO keys
  ****************************************************************************/
@@ -190,7 +105,7 @@ static struct platform_device netxbig_v2_gpio_buttons = {
 };
 
 /*****************************************************************************
- * GPIO LEDs
+ * GPIO extension LEDs
  ****************************************************************************/
 
 /*
@@ -200,19 +115,32 @@ static struct platform_device netxbig_v2_gpio_buttons = {
  * - address register : bit [0-2] -> GPIO [47-49]
  * - data register    : bit [0-2] -> GPIO [44-46]
  * - enable register  : GPIO 29
- *
+ */
+
+static int netxbig_v2_gpio_ext_addr[] = { 47, 48, 49 };
+static int netxbig_v2_gpio_ext_data[] = { 44, 45, 46 };
+
+static struct netxbig_gpio_ext netxbig_v2_gpio_ext = {
+        .addr           = netxbig_v2_gpio_ext_addr,
+        .num_addr       = ARRAY_SIZE(netxbig_v2_gpio_ext_addr),
+        .data           = netxbig_v2_gpio_ext_data,
+        .num_data       = ARRAY_SIZE(netxbig_v2_gpio_ext_data),
+        .enable         = 29,
+};
+
+/*
  * Address register selection:
  *
  * addr | register
  * ----------------------------
  *   0  | front LED
  *   1  | front LED brightness
- *   2  | HDD LED brightness
- *   3  | HDD1 LED
- *   4  | HDD2 LED
- *   5  | HDD3 LED
- *   6  | HDD4 LED
- *   7  | HDD5 LED
+ *   2  | SATA LED brightness
+ *   3  | SATA0 LED
+ *   4  | SATA1 LED
+ *   5  | SATA2 LED
+ *   6  | SATA3 LED
+ *   7  | SATA4 LED
  *
  * Data register configuration:
  *
@@ -233,30 +161,107 @@ static struct platform_device netxbig_v2_gpio_buttons = {
  *   6  | blink blue on=1 sec and red on=1 sec
  *   7  | blink blue on=0.5 sec and blue off=2.5 sec
  *
- * data | HDD LED mode
+ * data | SATA LED mode
  * -------------------------------------------------
- *   0  | fix blue on
+ *   0  | fix off
  *   1  | SATA activity blink
  *   2  | fix red on
  *   3  | blink blue on=1 sec and blue off=1 sec
  *   4  | blink red on=1 sec and red off=1 sec
  *   5  | blink blue on=2.5 sec and red on=0.5 sec
  *   6  | blink blue on=1 sec and red on=1 sec
- *   7  | blink blue on=0.5 sec and blue off=2.5 sec
+ *   7  | fix blue on
  */
 
-/*****************************************************************************
- * Timer
- ****************************************************************************/
+static int netxbig_v2_red_mled[NETXBIG_LED_MODE_NUM] = {
+        [NETXBIG_LED_OFF]       = 0,
+        [NETXBIG_LED_ON]        = 2,
+        [NETXBIG_LED_SATA]      = NETXBIG_LED_INVALID_MODE,
+        [NETXBIG_LED_TIMER1]    = 4,
+        [NETXBIG_LED_TIMER2]    = NETXBIG_LED_INVALID_MODE,
+};
 
-static void netxbig_v2_timer_init(void)
-{
-        kirkwood_tclk = 166666667;
-        orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
-}
+static int netxbig_v2_blue_pwr_mled[NETXBIG_LED_MODE_NUM] = {
+        [NETXBIG_LED_OFF]       = 0,
+        [NETXBIG_LED_ON]        = 1,
+        [NETXBIG_LED_SATA]      = NETXBIG_LED_INVALID_MODE,
+        [NETXBIG_LED_TIMER1]    = 3,
+        [NETXBIG_LED_TIMER2]    = 7,
+};
+
+static int netxbig_v2_blue_sata_mled[NETXBIG_LED_MODE_NUM] = {
+        [NETXBIG_LED_OFF]       = 0,
+        [NETXBIG_LED_ON]        = 7,
+        [NETXBIG_LED_SATA]      = 1,
+        [NETXBIG_LED_TIMER1]    = 3,
+        [NETXBIG_LED_TIMER2]    = NETXBIG_LED_INVALID_MODE,
+};
+
+static struct netxbig_led_timer netxbig_v2_led_timer[] = {
+        [0] = {
+                .delay_on       = 500,
+                .delay_off      = 500,
+                .mode           = NETXBIG_LED_TIMER1,
+        },
+        [1] = {
+                .delay_on       = 500,
+                .delay_off      = 1000,
+                .mode           = NETXBIG_LED_TIMER2,
+        },
+};
+
+#define NETXBIG_LED(_name, maddr, mval, baddr)                  \
+        { .name         = _name,                                \
+          .mode_addr    = maddr,                                \
+          .mode_val     = mval,                                 \
+          .bright_addr  = baddr }
+
+static struct netxbig_led net2big_v2_leds_ctrl[] = {
+        NETXBIG_LED("net2big-v2:blue:power", 0, netxbig_v2_blue_pwr_mled,  1),
+        NETXBIG_LED("net2big-v2:red:power",  0, netxbig_v2_red_mled,       1),
+        NETXBIG_LED("net2big-v2:blue:sata0", 3, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net2big-v2:red:sata0",  3, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net2big-v2:blue:sata1", 4, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net2big-v2:red:sata1",  4, netxbig_v2_red_mled,       2),
+};
+
+static struct netxbig_led_platform_data net2big_v2_leds_data = {
+        .gpio_ext       = &netxbig_v2_gpio_ext,
+        .timer          = netxbig_v2_led_timer,
+        .num_timer      = ARRAY_SIZE(netxbig_v2_led_timer),
+        .leds           = net2big_v2_leds_ctrl,
+        .num_leds       = ARRAY_SIZE(net2big_v2_leds_ctrl),
+};
+
+static struct netxbig_led net5big_v2_leds_ctrl[] = {
+        NETXBIG_LED("net5big-v2:blue:power", 0, netxbig_v2_blue_pwr_mled,  1),
+        NETXBIG_LED("net5big-v2:red:power",  0, netxbig_v2_red_mled,       1),
+        NETXBIG_LED("net5big-v2:blue:sata0", 3, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata0",  3, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net5big-v2:blue:sata1", 4, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata1",  4, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net5big-v2:blue:sata2", 5, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata2",  5, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net5big-v2:blue:sata3", 6, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata3",  6, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net5big-v2:blue:sata4", 7, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata5",  7, netxbig_v2_red_mled,       2),
+};
 
-struct sys_timer netxbig_v2_timer = {
-        .init = netxbig_v2_timer_init,
+static struct netxbig_led_platform_data net5big_v2_leds_data = {
+        .gpio_ext       = &netxbig_v2_gpio_ext,
+        .timer          = netxbig_v2_led_timer,
+        .num_timer      = ARRAY_SIZE(netxbig_v2_led_timer),
+        .leds           = net5big_v2_leds_ctrl,
+        .num_leds       = ARRAY_SIZE(net5big_v2_leds_ctrl),
+};
+
+static struct platform_device netxbig_v2_leds = {
+        .name           = "leds-netxbig",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &net2big_v2_leds_data,
+        },
 };
 
 /*****************************************************************************
@@ -284,18 +289,18 @@ static unsigned int net2big_v2_mpp_config[] __initdata = {
         MPP24_GPIO,             /* USB mode select */
         MPP26_GPIO,             /* USB device vbus */
         MPP28_GPIO,             /* USB enable host vbus */
-        MPP29_GPIO,             /* CPLD extension ALE */
+        MPP29_GPIO,             /* GPIO extension ALE */
         MPP34_GPIO,             /* Rear Push button */
         MPP35_GPIO,             /* Inhibit switch power-off */
         MPP36_GPIO,             /* SATA HDD1 presence */
         MPP37_GPIO,             /* SATA HDD2 presence */
         MPP40_GPIO,             /* eSATA presence */
-        MPP44_GPIO,             /* CPLD extension (data 0) */
-        MPP45_GPIO,             /* CPLD extension (data 1) */
-        MPP46_GPIO,             /* CPLD extension (data 2) */
-        MPP47_GPIO,             /* CPLD extension (addr 0) */
-        MPP48_GPIO,             /* CPLD extension (addr 1) */
-        MPP49_GPIO,             /* CPLD extension (addr 2) */
+        MPP44_GPIO,             /* GPIO extension (data 0) */
+        MPP45_GPIO,             /* GPIO extension (data 1) */
+        MPP46_GPIO,             /* GPIO extension (data 2) */
+        MPP47_GPIO,             /* GPIO extension (addr 0) */
+        MPP48_GPIO,             /* GPIO extension (addr 1) */
+        MPP49_GPIO,             /* GPIO extension (addr 2) */
         0
 };
 
@@ -324,7 +329,7 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
         MPP26_GE1_RXD2,
         MPP27_GE1_RXD3,
         MPP28_GPIO,             /* USB enable host vbus */
-        MPP29_GPIO,             /* CPLD extension ALE */
+        MPP29_GPIO,             /* GPIO extension ALE */
         MPP30_GE1_RXCTL,
         MPP31_GE1_RXCLK,
         MPP32_GE1_TCLKOUT,
@@ -339,12 +344,12 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
         MPP41_GPIO,             /* SATA HDD3 power */
         MPP42_GPIO,             /* SATA HDD4 power */
         MPP43_GPIO,             /* SATA HDD5 power */
-        MPP44_GPIO,             /* CPLD extension (data 0) */
-        MPP45_GPIO,             /* CPLD extension (data 1) */
-        MPP46_GPIO,             /* CPLD extension (data 2) */
-        MPP47_GPIO,             /* CPLD extension (addr 0) */
-        MPP48_GPIO,             /* CPLD extension (addr 1) */
-        MPP49_GPIO,             /* CPLD extension (addr 2) */
+        MPP44_GPIO,             /* GPIO extension (data 0) */
+        MPP45_GPIO,             /* GPIO extension (data 1) */
+        MPP46_GPIO,             /* GPIO extension (data 2) */
+        MPP47_GPIO,             /* GPIO extension (addr 0) */
+        MPP48_GPIO,             /* GPIO extension (addr 1) */
+        MPP49_GPIO,             /* GPIO extension (addr 2) */
         0
 };
 
@@ -366,7 +371,10 @@ static void __init netxbig_v2_init(void)
         else
                 kirkwood_mpp_conf(net5big_v2_mpp_config);
 
-        netxbig_v2_sata_power_init();
+        if (machine_is_net2big_v2())
+                lacie_v2_hdd_power_init(2);
+        else
+                lacie_v2_hdd_power_init(5);
 
         kirkwood_ehci_init();
         kirkwood_ge00_init(&netxbig_v2_ge00_data);
@@ -374,13 +382,12 @@ static void __init netxbig_v2_init(void)
                 kirkwood_ge01_init(&netxbig_v2_ge01_data);
         kirkwood_sata_init(&netxbig_v2_sata_data);
         kirkwood_uart0_init();
-        spi_register_board_info(netxbig_v2_spi_slave_info,
-                                ARRAY_SIZE(netxbig_v2_spi_slave_info));
-        kirkwood_spi_init();
-        kirkwood_i2c_init();
-        i2c_register_board_info(0, netxbig_v2_i2c_info,
-                                ARRAY_SIZE(netxbig_v2_i2c_info));
+        lacie_v2_register_flash();
+        lacie_v2_register_i2c_devices();
 
+        if (machine_is_net5big_v2())
+                netxbig_v2_leds.dev.platform_data = &net5big_v2_leds_data;
+        platform_device_register(&netxbig_v2_leds);
         platform_device_register(&netxbig_v2_gpio_buttons);
 
         if (gpio_request(NETXBIG_V2_GPIO_POWER_OFF, "power-off") == 0 &&
@@ -398,7 +405,7 @@ MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2")
         .init_machine   = netxbig_v2_init,
         .map_io         = kirkwood_map_io,
         .init_irq       = kirkwood_init_irq,
-        .timer          = &netxbig_v2_timer,
+        .timer          = &lacie_v2_timer,
 MACHINE_END
 #endif
 
@@ -410,6 +417,6 @@ MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2")
         .init_machine   = netxbig_v2_init,
         .map_io         = kirkwood_map_io,
         .init_irq       = kirkwood_init_irq,
-        .timer          = &netxbig_v2_timer,
+        .timer          = &lacie_v2_timer,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index fd06be618815..38017c8ac43f 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -16,6 +16,7 @@
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/i2c.h>
+#include <linux/gpio.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
@@ -57,7 +58,22 @@ static struct mvsdio_platform_data openrd_mvsdio_data = {
 };
 
 static unsigned int openrd_mpp_config[] __initdata = {
+        MPP12_SD_CLK,
+        MPP13_SD_CMD,
+        MPP14_SD_D0,
+        MPP15_SD_D1,
+        MPP16_SD_D2,
+        MPP17_SD_D3,
+        MPP28_GPIO,
         MPP29_GPIO,
+        MPP34_GPIO,
+        0
+};
+
+/* Configure MPP for UART1 */
+static unsigned int openrd_uart1_mpp_config[] __initdata = {
+        MPP13_UART1_TXD,
+        MPP14_UART1_RXD,
         0
 };
 
@@ -67,6 +83,68 @@ static struct i2c_board_info i2c_board_info[] __initdata = {
         },
 };
 
+static int __initdata uart1;
+
+static int __init sd_uart_selection(char *str)
+{
+        uart1 = -EINVAL;
+
+        /* Default is SD. Change if required, for UART */
+        if (!str)
+                return 0;
+
+        if (!strncmp(str, "232", 3)) {
+                uart1 = 232;
+        } else if (!strncmp(str, "485", 3)) {
+                /* OpenRD-Base doesn't have RS485. Treat is as an
+                 * unknown argument & just have default setting -
+                 * which is SD */
+                if (machine_is_openrd_base()) {
+                        uart1 = -ENODEV;
+                        return 1;
+                }
+
+                uart1 = 485;
+        }
+        return 1;
+}
+/* Parse boot_command_line string kw_openrd_init_uart1=232/485 */
+__setup("kw_openrd_init_uart1=", sd_uart_selection);
+
+static int __init uart1_mpp_config(void)
+{
+        kirkwood_mpp_conf(openrd_uart1_mpp_config);
+
+        if (gpio_request(34, "SD_UART1_SEL")) {
+                printk(KERN_ERR "GPIO request failed for SD/UART1 selection"
+                                ", gpio: 34\n");
+                return -EIO;
+        }
+
+        if (gpio_request(28, "RS232_RS485_SEL")) {
+                printk(KERN_ERR "GPIO request failed for RS232/RS485 selection"
+                                ", gpio# 28\n");
+                gpio_free(34);
+                return -EIO;
+        }
+
+        /* Select UART1
+         * Pin # 34: 0 => UART1, 1 => SD */
+        gpio_direction_output(34, 0);
+
+        /* Select RS232 OR RS485
+         * Pin # 28: 0 => RS232, 1 => RS485 */
+        if (uart1 == 232)
+                gpio_direction_output(28, 0);
+        else
+                gpio_direction_output(28, 1);
+
+        gpio_free(34);
+        gpio_free(28);
+
+        return 0;
+}
+
 static void __init openrd_init(void)
 {
         /*
@@ -90,7 +168,6 @@ static void __init openrd_init(void)
                 kirkwood_ge01_init(&openrd_ge01_data);
 
         kirkwood_sata_init(&openrd_sata_data);
-        kirkwood_sdio_init(&openrd_mvsdio_data);
 
         kirkwood_i2c_init();
 
@@ -99,6 +176,28 @@ static void __init openrd_init(void)
                         ARRAY_SIZE(i2c_board_info));
                 kirkwood_audio_init();
         }
+
+        if (uart1 <= 0) {
+                if (uart1 < 0)
+                        printk(KERN_ERR "Invalid kernel parameter to select "
+                                "UART1. Defaulting to SD. ERROR CODE: %d\n",
+                                uart1);
+
+                /* Select SD
+                 * Pin # 34: 0 => UART1, 1 => SD */
+                if (gpio_request(34, "SD_UART1_SEL")) {
+                        printk(KERN_ERR "GPIO request failed for SD/UART1 "
+                                        "selection, gpio: 34\n");
+                } else {
+
+                        gpio_direction_output(34, 1);
+                        gpio_free(34);
+                        kirkwood_sdio_init(&openrd_mvsdio_data);
+                }
+        } else {
+                if (!uart1_mpp_config())
+                        kirkwood_uart1_init();
+        }
 }
 
 static int __init openrd_pci_init(void)
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 55e7f00836b7..513ad3102d7c 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -117,7 +117,7 @@ static void __init pcie0_ioresources_init(struct pcie_port *pp)
          * IORESOURCE_IO
          */
         pp->res[0].name = "PCIe 0 I/O Space";
-        pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
+        pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
         pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
         pp->res[0].flags = IORESOURCE_IO;
 
@@ -139,7 +139,7 @@ static void __init pcie1_ioresources_init(struct pcie_port *pp)
          * IORESOURCE_IO
          */
         pp->res[0].name = "PCIe 1 I/O Space";
-        pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
+        pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE;
         pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
         pp->res[0].flags = IORESOURCE_IO;
 
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 6ab843eaa35b..0711d3b620ad 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -57,6 +57,13 @@ config MACH_MARVELL_JASPER
           PXA910-based development board. Since MMP2 is compatible to
           ARMv6 architecture.
 
+config MACH_TETON_BGA
+        bool "Marvell's PXA168 Teton BGA Development Board"
+        select CPU_PXA168
+        help
+          Say 'Y' here if you want to support the Marvell PXA168-based
+          Teton BGA Development Board.
+
 endmenu
 
 config CPU_PXA168
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 8b66d06739c4..751cdbf733c8 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_MACH_TAVOREVB)	+= tavorevb.o
 obj-$(CONFIG_MACH_TTC_DKB)      += ttc_dkb.o
 obj-$(CONFIG_MACH_FLINT)        += flint.o
 obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
+obj-$(CONFIG_MACH_TETON_BGA)    += teton_bga.o
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 0629394a5fb9..4681bedbe788 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -16,6 +16,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
+#include <linux/interrupt.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -23,6 +24,9 @@
 #include <mach/mfp-pxa168.h>
 #include <mach/pxa168.h>
 #include <mach/gpio.h>
+#include <video/pxa168fb.h>
+#include <linux/input.h>
+#include <plat/pxa27x_keypad.h>
 
 #include "common.h"
 
@@ -66,6 +70,43 @@ static unsigned long common_pin_config[] __initdata = {
         GPIO115_I2S_BCLK,
         GPIO116_I2S_RXD,
         GPIO117_I2S_TXD,
+
+        /* LCD */
+        GPIO56_LCD_FCLK_RD,
+        GPIO57_LCD_LCLK_A0,
+        GPIO58_LCD_PCLK_WR,
+        GPIO59_LCD_DENA_BIAS,
+        GPIO60_LCD_DD0,
+        GPIO61_LCD_DD1,
+        GPIO62_LCD_DD2,
+        GPIO63_LCD_DD3,
+        GPIO64_LCD_DD4,
+        GPIO65_LCD_DD5,
+        GPIO66_LCD_DD6,
+        GPIO67_LCD_DD7,
+        GPIO68_LCD_DD8,
+        GPIO69_LCD_DD9,
+        GPIO70_LCD_DD10,
+        GPIO71_LCD_DD11,
+        GPIO72_LCD_DD12,
+        GPIO73_LCD_DD13,
+        GPIO74_LCD_DD14,
+        GPIO75_LCD_DD15,
+        GPIO76_LCD_DD16,
+        GPIO77_LCD_DD17,
+        GPIO78_LCD_DD18,
+        GPIO79_LCD_DD19,
+        GPIO80_LCD_DD20,
+        GPIO81_LCD_DD21,
+        GPIO82_LCD_DD22,
+        GPIO83_LCD_DD23,
+
+        /* Keypad */
+        GPIO109_KP_MKIN1,
+        GPIO110_KP_MKIN0,
+        GPIO111_KP_MKOUT7,
+        GPIO112_KP_MKOUT6,
+        GPIO121_KP_MKIN4,
 };
 
 static struct smc91x_platdata smc91x_info = {
@@ -134,6 +175,51 @@ static struct i2c_board_info aspenite_i2c_info[] __initdata = {
         { I2C_BOARD_INFO("wm8753", 0x1b), },
 };
 
+static struct fb_videomode video_modes[] = {
+        [0] = {
+                .pixclock       = 30120,
+                .refresh        = 60,
+                .xres           = 800,
+                .yres           = 480,
+                .hsync_len      = 1,
+                .left_margin    = 215,
+                .right_margin   = 40,
+                .vsync_len      = 1,
+                .upper_margin   = 34,
+                .lower_margin   = 10,
+                .sync           = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
+        },
+};
+
+struct pxa168fb_mach_info aspenite_lcd_info = {
+        .id                     = "Graphic Frame",
+        .modes                  = video_modes,
+        .num_modes              = ARRAY_SIZE(video_modes),
+        .pix_fmt                = PIX_FMT_RGB565,
+        .io_pin_allocation_mode = PIN_MODE_DUMB_24,
+        .dumb_mode              = DUMB_MODE_RGB888,
+        .active                 = 1,
+        .panel_rbswap           = 0,
+        .invert_pixclock        = 0,
+};
+
+static unsigned int aspenite_matrix_key_map[] = {
+        KEY(0, 6, KEY_UP),      /* SW 4 */
+        KEY(0, 7, KEY_DOWN),    /* SW 5 */
+        KEY(1, 6, KEY_LEFT),    /* SW 6 */
+        KEY(1, 7, KEY_RIGHT),   /* SW 7 */
+        KEY(4, 6, KEY_ENTER),   /* SW 8 */
+        KEY(4, 7, KEY_ESC),     /* SW 9 */
+};
+
+static struct pxa27x_keypad_platform_data aspenite_keypad_info __initdata = {
+        .matrix_key_rows        = 5,
+        .matrix_key_cols        = 8,
+        .matrix_key_map         = aspenite_matrix_key_map,
+        .matrix_key_map_size    = ARRAY_SIZE(aspenite_matrix_key_map),
+        .debounce_interval      = 30,
+};
+
 static void __init common_init(void)
 {
         mfp_config(ARRAY_AND_SIZE(common_pin_config));
@@ -143,6 +229,8 @@ static void __init common_init(void)
         pxa168_add_twsi(1, NULL, ARRAY_AND_SIZE(aspenite_i2c_info));
         pxa168_add_ssp(1);
         pxa168_add_nand(&aspenite_nand_info);
+        pxa168_add_fb(&aspenite_lcd_info);
+        pxa168_add_keypad(&aspenite_keypad_info);
 
         /* off-chip devices */
         platform_device_register(&smc91x_device);
@@ -152,6 +240,7 @@ MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform")
         .phys_io        = APB_PHYS_BASE,
         .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
         .map_io         = mmp_map_io,
+        .nr_irqs        = IRQ_BOARD_START,
         .init_irq       = pxa168_init_irq,
         .timer          = &pxa168_timer,
         .init_machine   = common_init,
@@ -161,6 +250,7 @@ MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform")
         .phys_io        = APB_PHYS_BASE,
         .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
         .map_io         = mmp_map_io,
+        .nr_irqs        = IRQ_BOARD_START,
         .init_irq       = pxa168_init_irq,
         .timer          = &pxa168_timer,
         .init_machine   = common_init,
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index 3b29fa7e9b08..0ec0ca80bb3e 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -10,13 +10,20 @@
 
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/module.h>
 
 #include <asm/page.h>
 #include <asm/mach/map.h>
 #include <mach/addr-map.h>
+#include <mach/cputype.h>
 
 #include "common.h"
 
+#define MMP_CHIPID      (AXI_VIRT_BASE + 0x82c00)
+
+unsigned int mmp_chip_id;
+EXPORT_SYMBOL(mmp_chip_id);
+
 static struct map_desc standard_io_desc[] __initdata = {
         {
                 .pfn            = __phys_to_pfn(APB_PHYS_BASE),
@@ -34,4 +41,7 @@ static struct map_desc standard_io_desc[] __initdata = {
 void __init mmp_map_io(void)
 {
         iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
+
+        /* this is early, initialize mmp_chip_id here */
+        mmp_chip_id = __raw_readl(MMP_CHIPID);
 }
diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c
index e4312d238eae..c558425c3613 100644
--- a/arch/arm/mach-mmp/flint.c
+++ b/arch/arm/mach-mmp/flint.c
@@ -16,6 +16,7 @@
 #include <linux/smc91x.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/interrupt.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -25,6 +26,8 @@
 
 #include "common.h"
 
+#define FLINT_NR_IRQS   (IRQ_BOARD_START + 48)
+
 static unsigned long flint_pin_config[] __initdata = {
         /* UART1 */
         GPIO45_UART1_RXD,
@@ -116,6 +119,7 @@ MACHINE_START(FLINT, "Flint Development Platform")
         .phys_io        = APB_PHYS_BASE,
         .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
         .map_io         = mmp_map_io,
+        .nr_irqs        = FLINT_NR_IRQS,
         .init_irq       = mmp2_init_irq,
         .timer          = &mmp2_timer,
         .init_machine   = flint_init,
diff --git a/arch/arm/mach-mmp/include/mach/cputype.h b/arch/arm/mach-mmp/include/mach/cputype.h
index 83b18721d933..f43a68b213f1 100644
--- a/arch/arm/mach-mmp/include/mach/cputype.h
+++ b/arch/arm/mach-mmp/include/mach/cputype.h
@@ -4,36 +4,51 @@
 #include <asm/cputype.h>
 
 /*
- *  CPU   Stepping   OLD_ID       CPU_ID      CHIP_ID
+ *  CPU   Stepping   CPU_ID      CHIP_ID
  *
- * PXA168    A0    0x41159263   0x56158400   0x00A0A333
- * PXA910    Y0    0x41159262   0x56158000   0x00F0C910
- * MMP2      Z0                 0x560f5811
+ * PXA168    S0    0x56158400   0x0000C910
+ * PXA168    A0    0x56158400   0x00A0A168
+ * PXA910    Y1    0x56158400   0x00F2C920
+ * PXA910    A0    0x56158400   0x00F2C910
+ * PXA910    A1    0x56158400   0x00A0C910
+ * PXA920    Y0    0x56158400   0x00F2C920
+ * PXA920    A0    0x56158400   0x00A0C920
+ * PXA920    A1    0x56158400   0x00A1C920
+ * MMP2      Z0    0x560f5811   0x00F00410
+ * MMP2      Z1    0x560f5811   0x00E00410
+ * MMP2      A0    0x560f5811   0x00A0A610
  */
 
+extern unsigned int mmp_chip_id;
+
 #ifdef CONFIG_CPU_PXA168
-#  define __cpu_is_pxa168(id)   \
-        ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x84; })
+static inline int cpu_is_pxa168(void)
+{
+        return (((read_cpuid_id() >> 8) & 0xff) == 0x84) &&
+                ((mmp_chip_id & 0xfff) == 0x168);
+}
 #else
-#  define __cpu_is_pxa168(id)   (0)
+#define cpu_is_pxa168() (0)
 #endif
 
+/* cpu_is_pxa910() is shared on both pxa910 and pxa920 */
 #ifdef CONFIG_CPU_PXA910
-#  define __cpu_is_pxa910(id)   \
-        ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x80; })
+static inline int cpu_is_pxa910(void)
+{
+        return (((read_cpuid_id() >> 8) & 0xff) == 0x84) &&
+                (((mmp_chip_id & 0xfff) == 0x910) ||
+                 ((mmp_chip_id & 0xfff) == 0x920));
+}
 #else
-#  define __cpu_is_pxa910(id)   (0)
+#define cpu_is_pxa910() (0)
 #endif
 
 #ifdef CONFIG_CPU_MMP2
-#  define __cpu_is_mmp2(id)     \
-        ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x58; })
+static inline int cpu_is_mmp2(void)
+{
+        return (((cpu_readid_id() >> 8) & 0xff) == 0x58);
 #else
-#  define __cpu_is_mmp2(id)     (0)
+#define cpu_is_mmp2()   (0)
 #endif
 
-#define cpu_is_pxa168()         ({ __cpu_is_pxa168(read_cpuid_id()); })
-#define cpu_is_pxa910()         ({ __cpu_is_pxa910(read_cpuid_id()); })
-#define cpu_is_mmp2()           ({ __cpu_is_mmp2(read_cpuid_id()); })
-
 #endif /* __ASM_MACH_CPUTYPE_H */
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h
index b379cdec4d38..a09d328e2ddd 100644
--- a/arch/arm/mach-mmp/include/mach/irqs.h
+++ b/arch/arm/mach-mmp/include/mach/irqs.h
@@ -222,10 +222,8 @@
 #define IRQ_GPIO_NUM                    192
 #define IRQ_GPIO(x)                     (IRQ_GPIO_START + (x))
 
-/* Board IRQ - 64 by default, increase if not enough */
 #define IRQ_BOARD_START                 (IRQ_GPIO_START + IRQ_GPIO_NUM)
-#define IRQ_BOARD_END                   (IRQ_BOARD_START + 64)
 
-#define NR_IRQS                         (IRQ_BOARD_END)
+#define NR_IRQS                         (IRQ_BOARD_START)
 
 #endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
index ded43c455ec3..4621067c7720 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
@@ -289,4 +289,11 @@
 #define GPIO86_PWM1_OUT         MFP_CFG(GPIO86, AF2)
 #define GPIO86_PWM2_OUT         MFP_CFG(GPIO86, AF3)
 
+/* Keypad */
+#define GPIO109_KP_MKIN1        MFP_CFG(GPIO109, AF7)
+#define GPIO110_KP_MKIN0        MFP_CFG(GPIO110, AF7)
+#define GPIO111_KP_MKOUT7       MFP_CFG(GPIO111, AF7)
+#define GPIO112_KP_MKOUT6       MFP_CFG(GPIO112, AF7)
+#define GPIO121_KP_MKIN4        MFP_CFG(GPIO121, AF7)
+
 #endif /* __ASM_MACH_MFP_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 27e1bc758623..1801e4206232 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -5,11 +5,15 @@ struct sys_timer;
 
 extern struct sys_timer pxa168_timer;
 extern void __init pxa168_init_irq(void);
+extern void pxa168_clear_keypad_wakeup(void);
 
 #include <linux/i2c.h>
 #include <mach/devices.h>
 #include <plat/i2c.h>
 #include <plat/pxa3xx_nand.h>
+#include <video/pxa168fb.h>
+#include <plat/pxa27x_keypad.h>
+#include <mach/cputype.h>
 
 extern struct pxa_device_desc pxa168_device_uart1;
 extern struct pxa_device_desc pxa168_device_uart2;
@@ -25,6 +29,8 @@ extern struct pxa_device_desc pxa168_device_ssp3;
 extern struct pxa_device_desc pxa168_device_ssp4;
 extern struct pxa_device_desc pxa168_device_ssp5;
 extern struct pxa_device_desc pxa168_device_nand;
+extern struct pxa_device_desc pxa168_device_fb;
+extern struct pxa_device_desc pxa168_device_keypad;
 
 static inline int pxa168_add_uart(int id)
 {
@@ -97,4 +103,18 @@ static inline int pxa168_add_nand(struct pxa3xx_nand_platform_data *info)
 {
         return pxa_register_device(&pxa168_device_nand, info, sizeof(*info));
 }
+
+static inline int pxa168_add_fb(struct pxa168fb_mach_info *mi)
+{
+        return pxa_register_device(&pxa168_device_fb, mi, sizeof(*mi));
+}
+
+static inline int pxa168_add_keypad(struct pxa27x_keypad_platform_data *data)
+{
+        if (cpu_is_pxa168())
+                data->clear_wakeup_event = pxa168_clear_keypad_wakeup;
+
+        return pxa_register_device(&pxa168_device_keypad, data, sizeof(*data));
+}
+
 #endif /* __ASM_MACH_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h
index 919030514120..ac4702357a6e 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -33,4 +33,16 @@
 #define APMU_FNRST_DIS  (1 << 1)
 #define APMU_AXIRST_DIS (1 << 0)
 
+/* Wake Clear Register */
+#define APMU_WAKE_CLR   APMU_REG(0x07c)
+
+#define APMU_PXA168_KP_WAKE_CLR         (1 << 7)
+#define APMU_PXA168_CFI_WAKE_CLR        (1 << 6)
+#define APMU_PXA168_XD_WAKE_CLR         (1 << 5)
+#define APMU_PXA168_MSP_WAKE_CLR        (1 << 4)
+#define APMU_PXA168_SD4_WAKE_CLR        (1 << 3)
+#define APMU_PXA168_SD3_WAKE_CLR        (1 << 2)
+#define APMU_PXA168_SD2_WAKE_CLR        (1 << 1)
+#define APMU_PXA168_SD1_WAKE_CLR        (1 << 0)
+
 #endif /* __ASM_MACH_REGS_APMU_H */
diff --git a/arch/arm/mach-mmp/include/mach/system.h b/arch/arm/mach-mmp/include/mach/system.h
index 4f5b0e0ce6cf..1a8a25edb1b4 100644
--- a/arch/arm/mach-mmp/include/mach/system.h
+++ b/arch/arm/mach-mmp/include/mach/system.h
@@ -9,6 +9,8 @@
 #ifndef __ASM_MACH_SYSTEM_H
 #define __ASM_MACH_SYSTEM_H
 
+#include <mach/cputype.h>
+
 static inline void arch_idle(void)
 {
         cpu_do_idle();
@@ -16,6 +18,9 @@ static inline void arch_idle(void)
 
 static inline void arch_reset(char mode, const char *cmd)
 {
-        cpu_reset(0);
+        if (cpu_is_pxa168())
+                cpu_reset(0xffff0000);
+        else
+                cpu_reset(0);
 }
 #endif /* __ASM_MACH_SYSTEM_H */
diff --git a/arch/arm/mach-mmp/include/mach/teton_bga.h b/arch/arm/mach-mmp/include/mach/teton_bga.h
new file mode 100644
index 000000000000..61a539b2cc98
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/teton_bga.h
@@ -0,0 +1,27 @@
+/*
+ *  linux/arch/arm/mach-mmp/include/mach/teton_bga.h
+ *
+ *  Support for the Marvell PXA168 Teton BGA Development Platform.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+#ifndef __ASM_MACH_TETON_BGA_H
+#define __ASM_MACH_TETON_BGA_H
+
+/* GPIOs */
+#define MMC_PWENA_GPIO          27
+#define USBHPENB_GPIO           55
+#define RTC_INT_GPIO            78
+#define LCD_VBLK_EN_GPIO        79
+#define LCD_DVDD_EN_GPIO        80
+#define RST_WIFI_GPIO           81
+#define CF_PWEN_GPIO            82
+#define USB_OC_GPIO             83
+#define PWM_GPIO                84
+#define USBHPENA_GPIO           85
+#define TS_INT_GPIO             86
+#define CIR_GPIO                108
+
+#endif /* __ASM_MACH_TETON_BGA_H */
diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c
index 80c3e7ab1e17..940ee03e3682 100644
--- a/arch/arm/mach-mmp/jasper.c
+++ b/arch/arm/mach-mmp/jasper.c
@@ -18,16 +18,18 @@
 #include <linux/regulator/machine.h>
 #include <linux/regulator/max8649.h>
 #include <linux/mfd/max8925.h>
+#include <linux/interrupt.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/addr-map.h>
 #include <mach/mfp-mmp2.h>
 #include <mach/mmp2.h>
-#include <mach/irqs.h>
 
 #include "common.h"
 
+#define JASPER_NR_IRQS          (IRQ_BOARD_START + 48)
+
 static unsigned long jasper_pin_config[] __initdata = {
         /* UART1 */
         GPIO29_UART1_RXD,
@@ -137,6 +139,7 @@ MACHINE_START(MARVELL_JASPER, "Jasper Development Platform")
         .phys_io        = APB_PHYS_BASE,
         .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
         .map_io         = mmp_map_io,
+        .nr_irqs        = JASPER_NR_IRQS,
         .init_irq       = mmp2_init_irq,
         .timer          = &mmp2_timer,
         .init_machine   = jasper_init,
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 652ae660634c..72b4e7631583 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -77,8 +77,10 @@ static APBC_CLK(ssp2, PXA168_SSP2, 4, 0);
 static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
 static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
 static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
+static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
 
 static APMU_CLK(nand, NAND, 0x01db, 208000000);
+static APMU_CLK(lcd, LCD, 0x7f, 312000000);
 
 /* device and clock bindings */
 static struct clk_lookup pxa168_clkregs[] = {
@@ -96,6 +98,8 @@ static struct clk_lookup pxa168_clkregs[] = {
         INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
         INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
         INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+        INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
+        INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
 };
 
 static int __init pxa168_init(void)
@@ -132,6 +136,16 @@ struct sys_timer pxa168_timer = {
         .init   = pxa168_timer_init,
 };
 
+void pxa168_clear_keypad_wakeup(void)
+{
+        uint32_t val;
+        uint32_t mask = APMU_PXA168_KP_WAKE_CLR;
+
+        /* wake event clear is needed in order to clear keypad interrupt */
+        val = __raw_readl(APMU_WAKE_CLR);
+        __raw_writel(val |  mask, APMU_WAKE_CLR);
+}
+
 /* on-chip devices */
 PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22);
 PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24);
@@ -147,3 +161,5 @@ PXA168_DEVICE(ssp2, "pxa168-ssp", 1, SSP2, 0xd401c000, 0x40, 54, 55);
 PXA168_DEVICE(ssp3, "pxa168-ssp", 2, SSP3, 0xd401f000, 0x40, 56, 57);
 PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000, 0x40, 58, 59);
 PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61);
+PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8);
+PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c);
diff --git a/arch/arm/mach-mmp/teton_bga.c b/arch/arm/mach-mmp/teton_bga.c
new file mode 100644
index 000000000000..a4a375c58e0c
--- /dev/null
+++ b/arch/arm/mach-mmp/teton_bga.c
@@ -0,0 +1,91 @@
+/*
+ *  linux/arch/arm/mach-mmp/teton_bga.c
+ *
+ *  Support for the Marvell PXA168 Teton BGA Development Platform.
+ *
+ *  Author: Mark F. Brown <mark.brown314@gmail.com>
+ *
+ *  This code is based on aspenite.c
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <plat/pxa27x_keypad.h>
+#include <linux/i2c.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/addr-map.h>
+#include <mach/mfp-pxa168.h>
+#include <mach/pxa168.h>
+#include <mach/teton_bga.h>
+
+#include "common.h"
+
+static unsigned long teton_bga_pin_config[] __initdata = {
+        /* UART1 */
+        GPIO107_UART1_TXD,
+        GPIO108_UART1_RXD,
+
+        /* Keypad */
+        GPIO109_KP_MKIN1,
+        GPIO110_KP_MKIN0,
+        GPIO111_KP_MKOUT7,
+        GPIO112_KP_MKOUT6,
+
+        /* I2C Bus */
+        GPIO105_CI2C_SDA,
+        GPIO106_CI2C_SCL,
+
+        /* RTC */
+        GPIO78_GPIO,
+};
+
+static unsigned int teton_bga_matrix_key_map[] = {
+        KEY(0, 6, KEY_ESC),
+        KEY(0, 7, KEY_ENTER),
+        KEY(1, 6, KEY_LEFT),
+        KEY(1, 7, KEY_RIGHT),
+};
+
+static struct pxa27x_keypad_platform_data teton_bga_keypad_info __initdata = {
+        .matrix_key_rows        = 2,
+        .matrix_key_cols        = 8,
+        .matrix_key_map         = teton_bga_matrix_key_map,
+        .matrix_key_map_size    = ARRAY_SIZE(teton_bga_matrix_key_map),
+        .debounce_interval      = 30,
+};
+
+static struct i2c_board_info teton_bga_i2c_info[] __initdata = {
+        {
+                I2C_BOARD_INFO("ds1337", 0x68),
+                .irq = gpio_to_irq(RTC_INT_GPIO)
+        },
+};
+
+static void __init teton_bga_init(void)
+{
+        mfp_config(ARRAY_AND_SIZE(teton_bga_pin_config));
+
+        /* on-chip devices */
+        pxa168_add_uart(1);
+        pxa168_add_keypad(&teton_bga_keypad_info);
+        pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(teton_bga_i2c_info));
+}
+
+MACHINE_START(TETON_BGA, "PXA168-based Teton BGA Development Platform")
+        .phys_io        = APB_PHYS_BASE,
+        .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
+        .map_io         = mmp_map_io,
+        .nr_irqs        = IRQ_BOARD_START,
+        .init_irq       = pxa168_init_irq,
+        .timer          = &pxa168_timer,
+        .init_machine   = teton_bga_init,
+MACHINE_END
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index ee65e05f0cf1..54571139dc4b 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -14,6 +14,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/onenand.h>
+#include <linux/interrupt.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -24,6 +25,8 @@
 
 #include "common.h"
 
+#define TTCDKB_NR_IRQS          (IRQ_BOARD_START + 24)
+
 static unsigned long ttc_dkb_pin_config[] __initdata = {
         /* UART2 */
         GPIO47_UART2_RXD,
@@ -125,6 +128,7 @@ MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform")
         .phys_io        = APB_PHYS_BASE,
         .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
         .map_io         = mmp_map_io,
+        .nr_irqs        = TTCDKB_NR_IRQS,
         .init_irq       = pxa910_init_irq,
         .timer          = &pxa910_timer,
         .init_machine   = ttc_dkb_init,
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 47264a76eeb3..3115a29dec4e 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -10,6 +10,8 @@ config ARCH_MSM7X00A
         select MSM_SMD
         select MSM_SMD_PKG3
         select CPU_V6
+        select MSM_PROC_COMM
+        select HAS_MSM_DEBUG_UART_PHYS
 
 config ARCH_MSM7X30
         bool "MSM7x30"
@@ -18,6 +20,9 @@ config ARCH_MSM7X30
         select MSM_VIC
         select CPU_V7
         select MSM_REMOTE_SPINLOCK_DEKKERS
+        select MSM_GPIOMUX
+        select MSM_PROC_COMM
+        select HAS_MSM_DEBUG_UART_PHYS
 
 config ARCH_QSD8X50
         bool "QSD8X50"
@@ -26,6 +31,19 @@ config ARCH_QSD8X50
         select MSM_VIC
         select CPU_V7
         select MSM_REMOTE_SPINLOCK_LDREX
+        select MSM_GPIOMUX
+        select MSM_PROC_COMM
+        select HAS_MSM_DEBUG_UART_PHYS
+
+config ARCH_MSM8X60
+        bool "MSM8X60"
+        select ARM_GIC
+        select CPU_V7
+        select MSM_V2_TLMM
+        select MSM_GPIOMUX
+        select MACH_MSM8X60_SURF if (!MACH_MSM8X60_RUMI3 && !MACH_MSM8X60_SIM \
+                                  && !MACH_MSM8X60_FFA)
+
 endchoice
 
 config MSM_SOC_REV_A
@@ -36,6 +54,9 @@ config  ARCH_MSM_ARM11
 config  ARCH_MSM_SCORPION
         bool
 
+config HAS_MSM_DEBUG_UART_PHYS
+        bool
+
 config  MSM_VIC
         bool
 
@@ -74,6 +95,30 @@ config MACH_QSD8X50A_ST1_5
         help
           Support for the Qualcomm ST1.5.
 
+config MACH_MSM8X60_RUMI3
+        depends on ARCH_MSM8X60
+        bool "MSM8x60 RUMI3"
+        help
+          Support for the Qualcomm MSM8x60 RUMI3 emulator.
+
+config MACH_MSM8X60_SURF
+        depends on ARCH_MSM8X60
+        bool "MSM8x60 SURF"
+        help
+          Support for the Qualcomm MSM8x60 SURF eval board.
+
+config MACH_MSM8X60_SIM
+        depends on ARCH_MSM8X60
+        bool "MSM8x60 Simulator"
+        help
+          Support for the Qualcomm MSM8x60 simulator.
+
+config MACH_MSM8X60_FFA
+        depends on ARCH_MSM8X60
+        bool "MSM8x60 FFA"
+        help
+          Support for the Qualcomm MSM8x60 FFA eval board.
+
 endmenu
 
 config MSM_DEBUG_UART
@@ -82,6 +127,7 @@ config MSM_DEBUG_UART
         default 2 if MSM_DEBUG_UART2
         default 3 if MSM_DEBUG_UART3
 
+if HAS_MSM_DEBUG_UART_PHYS
 choice
         prompt "Debug UART"
 
@@ -99,11 +145,20 @@ choice
         config MSM_DEBUG_UART3
                 bool "UART3"
 endchoice
+endif
 
 config MSM_SMD_PKG3
         bool
 
+config MSM_PROC_COMM
+        bool
+
 config MSM_SMD
         bool
 
+config MSM_GPIOMUX
+        bool
+
+config MSM_V2_TLMM
+        bool
 endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 704610648a25..b5a7b07a44f5 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,16 +1,20 @@
-obj-y += proc_comm.o
-obj-y += io.o idle.o timer.o dma.o
-obj-y += vreg.o
+obj-y += io.o idle.o timer.o
+ifndef CONFIG_ARCH_MSM8X60
 obj-y += acpuclock-arm11.o
-obj-y += clock.o clock-pcom.o
-obj-y += gpio.o
+obj-y += dma.o
+endif
 
 ifdef CONFIG_MSM_VIC
 obj-y += irq-vic.o
 else
+ifndef CONFIG_ARCH_MSM8X60
 obj-y += irq.o
 endif
+endif
 
+obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o iommu.o iommu_dev.o devices-msm8x60-iommu.o
+obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
+obj-$(CONFIG_MSM_PROC_COMM) += clock.o
 obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
 obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
 obj-$(CONFIG_MSM_SMD) += last_radio_log.o
@@ -19,4 +23,11 @@ obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o d
 obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
 obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
 obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
+obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o
 
+obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o
+obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
+obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o
+ifndef CONFIG_MSM_V2_TLMM
+obj-y   += gpio.o
+endif
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index e32981928c77..76d5a22a6984 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -39,27 +39,11 @@
 
 extern struct sys_timer msm_timer;
 
-#ifdef CONFIG_SERIAL_MSM_CONSOLE
-static struct msm_gpio uart2_config_data[] = {
-        { GPIO_CFG(49, 2, GPIO_OUTPUT,  GPIO_PULL_DOWN, GPIO_2MA), "UART2_RFR"},
-        { GPIO_CFG(50, 2, GPIO_INPUT,   GPIO_PULL_DOWN, GPIO_2MA), "UART2_CTS"},
-        { GPIO_CFG(51, 2, GPIO_INPUT,   GPIO_PULL_DOWN, GPIO_2MA), "UART2_Rx"},
-        { GPIO_CFG(52, 2, GPIO_OUTPUT,  GPIO_PULL_DOWN, GPIO_2MA), "UART2_Tx"},
-};
-
-static void msm7x30_init_uart2(void)
-{
-        msm_gpios_request_enable(uart2_config_data,
-                        ARRAY_SIZE(uart2_config_data));
-
-}
-#endif
-
 static struct platform_device *devices[] __initdata = {
 #if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
         &msm_device_uart2,
 #endif
-
+        &msm_device_smd,
 };
 
 static void __init msm7x30_init_irq(void)
@@ -70,10 +54,6 @@ static void __init msm7x30_init_irq(void)
 static void __init msm7x30_init(void)
 {
         platform_add_devices(devices, ARRAY_SIZE(devices));
-#ifdef CONFIG_SERIAL_MSM_CONSOLE
-        msm7x30_init_uart2();
-#endif
-
 }
 
 static void __init msm7x30_map_io(void)
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
new file mode 100644
index 000000000000..7486a681cc71
--- /dev/null
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -0,0 +1,100 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+
+#include <mach/board.h>
+#include <mach/msm_iomap.h>
+
+void __iomem *gic_cpu_base_addr;
+
+unsigned long clk_get_max_axi_khz(void)
+{
+        return 0;
+}
+
+static void __init msm8x60_map_io(void)
+{
+        msm_map_msm8x60_io();
+}
+
+static void __init msm8x60_init_irq(void)
+{
+        unsigned int i;
+
+        gic_dist_init(0, MSM_QGIC_DIST_BASE, GIC_PPI_START);
+        gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE;
+        gic_cpu_init(0, MSM_QGIC_CPU_BASE);
+
+        /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
+        writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
+
+        /* RUMI does not adhere to GIC spec by enabling STIs by default.
+         * Enable/clear is supposed to be RO for STIs, but is RW on RUMI.
+         */
+        if (!machine_is_msm8x60_sim())
+                writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
+
+        /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
+         * as they are configured as level, which does not play nice with
+         * handle_percpu_irq.
+         */
+        for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
+                if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
+                        set_irq_handler(i, handle_percpu_irq);
+        }
+}
+
+static void __init msm8x60_init(void)
+{
+}
+
+MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
+        .map_io = msm8x60_map_io,
+        .init_irq = msm8x60_init_irq,
+        .init_machine = msm8x60_init,
+        .timer = &msm_timer,
+MACHINE_END
+
+MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
+        .map_io = msm8x60_map_io,
+        .init_irq = msm8x60_init_irq,
+        .init_machine = msm8x60_init,
+        .timer = &msm_timer,
+MACHINE_END
+
+MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
+        .map_io = msm8x60_map_io,
+        .init_irq = msm8x60_init_irq,
+        .init_machine = msm8x60_init,
+        .timer = &msm_timer,
+MACHINE_END
+
+MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
+        .map_io = msm8x60_map_io,
+        .init_irq = msm8x60_init_irq,
+        .init_machine = msm8x60_init,
+        .timer = &msm_timer,
+MACHINE_END
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index e3cc80792d6c..d5d5e441a52d 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -35,20 +35,49 @@
 
 extern struct sys_timer msm_timer;
 
-static struct msm_gpio uart3_config_data[] = {
-        { GPIO_CFG(86, 1, GPIO_INPUT,   GPIO_PULL_DOWN, GPIO_2MA), "UART2_Rx"},
-        { GPIO_CFG(87, 1, GPIO_OUTPUT,  GPIO_PULL_DOWN, GPIO_2MA), "UART2_Tx"},
+static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300;
+static const unsigned        qsd8x50_surf_smc91x_gpio __initdata = 156;
+
+/* Leave smc91x resources empty here, as we'll fill them in
+ * at run-time: they vary from board to board, and the true
+ * configuration won't be known until boot.
+ */
+static struct resource smc91x_resources[] __initdata = {
+        [0] = {
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .flags = IORESOURCE_IRQ,
+        },
 };
 
-static struct platform_device *devices[] __initdata = {
-        &msm_device_uart3,
+static struct platform_device smc91x_device __initdata = {
+        .name           = "smc91x",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(smc91x_resources),
+        .resource       = smc91x_resources,
 };
 
-static void msm8x50_init_uart3(void)
+static int __init msm_init_smc91x(void)
 {
-        msm_gpios_request_enable(uart3_config_data,
-                                ARRAY_SIZE(uart3_config_data));
+        if (machine_is_qsd8x50_surf()) {
+                smc91x_resources[0].start = qsd8x50_surf_smc91x_base;
+                smc91x_resources[0].end   = qsd8x50_surf_smc91x_base + 0xff;
+                smc91x_resources[1].start =
+                        gpio_to_irq(qsd8x50_surf_smc91x_gpio);
+                smc91x_resources[1].end   =
+                        gpio_to_irq(qsd8x50_surf_smc91x_gpio);
+                platform_device_register(&smc91x_device);
+        }
+
+        return 0;
 }
+module_init(msm_init_smc91x);
+
+static struct platform_device *devices[] __initdata = {
+        &msm_device_uart3,
+        &msm_device_smd,
+};
 
 static void __init qsd8x50_map_io(void)
 {
@@ -64,7 +93,6 @@ static void __init qsd8x50_init_irq(void)
 
 static void __init qsd8x50_init(void)
 {
-        msm8x50_init_uart3();
         platform_add_devices(devices, ARRAY_SIZE(devices));
 }
 
diff --git a/arch/arm/mach-msm/clock-dummy.c b/arch/arm/mach-msm/clock-dummy.c
new file mode 100644
index 000000000000..1250d22082ee
--- /dev/null
+++ b/arch/arm/mach-msm/clock-dummy.c
@@ -0,0 +1,54 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/module.h>
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+        return ERR_PTR(-ENOENT);
+}
+EXPORT_SYMBOL(clk_get);
+
+int clk_enable(struct clk *clk)
+{
+        return -ENOENT;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+        return 0;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        return -ENOENT;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+void clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_put);
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index b449e8ad2904..7fcf2e3b7698 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -51,6 +51,11 @@ struct platform_device msm_device_uart2 = {
         .resource       = resources_uart2,
 };
 
+struct platform_device msm_device_smd = {
+        .name   = "msm_smd",
+        .id     = -1,
+};
+
 struct clk msm_clocks_7x30[] = {
         CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
         CLK_PCOM("adsp_clk",    ADSP_CLK,       NULL, 0),
diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c b/arch/arm/mach-msm/devices-msm8x60-iommu.c
new file mode 100644
index 000000000000..89b9d4437e92
--- /dev/null
+++ b/arch/arm/mach-msm/devices-msm8x60-iommu.c
@@ -0,0 +1,883 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/bootmem.h>
+
+#include <mach/msm_iomap-8x60.h>
+#include <mach/irqs-8x60.h>
+#include <mach/iommu.h>
+
+static struct resource msm_iommu_jpegd_resources[] = {
+        {
+                .start = MSM_IOMMU_JPEGD_PHYS,
+                .end   = MSM_IOMMU_JPEGD_PHYS + MSM_IOMMU_JPEGD_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_JPEGD_CB_SC_SECURE_IRQ,
+                .end   = SMMU_JPEGD_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource msm_iommu_vpe_resources[] = {
+        {
+                .start = MSM_IOMMU_VPE_PHYS,
+                .end   = MSM_IOMMU_VPE_PHYS + MSM_IOMMU_VPE_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_VPE_CB_SC_SECURE_IRQ,
+                .end   = SMMU_VPE_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource msm_iommu_mdp0_resources[] = {
+        {
+                .start = MSM_IOMMU_MDP0_PHYS,
+                .end   = MSM_IOMMU_MDP0_PHYS + MSM_IOMMU_MDP0_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_MDP0_CB_SC_SECURE_IRQ,
+                .end   = SMMU_MDP0_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource msm_iommu_mdp1_resources[] = {
+        {
+                .start = MSM_IOMMU_MDP1_PHYS,
+                .end   = MSM_IOMMU_MDP1_PHYS + MSM_IOMMU_MDP1_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_MDP1_CB_SC_SECURE_IRQ,
+                .end   = SMMU_MDP1_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource msm_iommu_rot_resources[] = {
+        {
+                .start = MSM_IOMMU_ROT_PHYS,
+                .end   = MSM_IOMMU_ROT_PHYS + MSM_IOMMU_ROT_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_ROT_CB_SC_SECURE_IRQ,
+                .end   = SMMU_ROT_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource msm_iommu_ijpeg_resources[] = {
+        {
+                .start = MSM_IOMMU_IJPEG_PHYS,
+                .end   = MSM_IOMMU_IJPEG_PHYS + MSM_IOMMU_IJPEG_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_IJPEG_CB_SC_SECURE_IRQ,
+                .end   = SMMU_IJPEG_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource msm_iommu_vfe_resources[] = {
+        {
+                .start = MSM_IOMMU_VFE_PHYS,
+                .end   = MSM_IOMMU_VFE_PHYS + MSM_IOMMU_VFE_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_VFE_CB_SC_SECURE_IRQ,
+                .end   = SMMU_VFE_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource msm_iommu_vcodec_a_resources[] = {
+        {
+                .start = MSM_IOMMU_VCODEC_A_PHYS,
+                .end   = MSM_IOMMU_VCODEC_A_PHYS + MSM_IOMMU_VCODEC_A_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
+                .end   = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource msm_iommu_vcodec_b_resources[] = {
+        {
+                .start = MSM_IOMMU_VCODEC_B_PHYS,
+                .end   = MSM_IOMMU_VCODEC_B_PHYS + MSM_IOMMU_VCODEC_B_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
+                .end   = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource msm_iommu_gfx3d_resources[] = {
+        {
+                .start = MSM_IOMMU_GFX3D_PHYS,
+                .end   = MSM_IOMMU_GFX3D_PHYS + MSM_IOMMU_GFX3D_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_GFX3D_CB_SC_SECURE_IRQ,
+                .end   = SMMU_GFX3D_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource msm_iommu_gfx2d0_resources[] = {
+        {
+                .start = MSM_IOMMU_GFX2D0_PHYS,
+                .end   = MSM_IOMMU_GFX2D0_PHYS + MSM_IOMMU_GFX2D0_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
+                .end   = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device msm_root_iommu_dev = {
+        .name = "msm_iommu",
+        .id = -1,
+};
+
+static struct msm_iommu_dev jpegd_smmu = {
+        .name = "jpegd",
+        .clk_rate = -1
+};
+
+static struct msm_iommu_dev vpe_smmu = {
+        .name = "vpe"
+};
+
+static struct msm_iommu_dev mdp0_smmu = {
+        .name = "mdp0"
+};
+
+static struct msm_iommu_dev mdp1_smmu = {
+        .name = "mdp1"
+};
+
+static struct msm_iommu_dev rot_smmu = {
+        .name = "rot"
+};
+
+static struct msm_iommu_dev ijpeg_smmu = {
+        .name = "ijpeg"
+};
+
+static struct msm_iommu_dev vfe_smmu = {
+        .name = "vfe",
+        .clk_rate = -1
+};
+
+static struct msm_iommu_dev vcodec_a_smmu = {
+        .name = "vcodec_a"
+};
+
+static struct msm_iommu_dev vcodec_b_smmu = {
+        .name = "vcodec_b"
+};
+
+static struct msm_iommu_dev gfx3d_smmu = {
+        .name = "gfx3d",
+        .clk_rate = 27000000
+};
+
+static struct msm_iommu_dev gfx2d0_smmu = {
+        .name = "gfx2d0",
+        .clk_rate = 27000000
+};
+
+static struct platform_device msm_device_smmu_jpegd = {
+        .name = "msm_iommu",
+        .id = 0,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_jpegd_resources),
+        .resource = msm_iommu_jpegd_resources,
+};
+
+static struct platform_device msm_device_smmu_vpe = {
+        .name = "msm_iommu",
+        .id = 1,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_vpe_resources),
+        .resource = msm_iommu_vpe_resources,
+};
+
+static struct platform_device msm_device_smmu_mdp0 = {
+        .name = "msm_iommu",
+        .id = 2,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_mdp0_resources),
+        .resource = msm_iommu_mdp0_resources,
+};
+
+static struct platform_device msm_device_smmu_mdp1 = {
+        .name = "msm_iommu",
+        .id = 3,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_mdp1_resources),
+        .resource = msm_iommu_mdp1_resources,
+};
+
+static struct platform_device msm_device_smmu_rot = {
+        .name = "msm_iommu",
+        .id = 4,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_rot_resources),
+        .resource = msm_iommu_rot_resources,
+};
+
+static struct platform_device msm_device_smmu_ijpeg = {
+        .name = "msm_iommu",
+        .id = 5,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_ijpeg_resources),
+        .resource = msm_iommu_ijpeg_resources,
+};
+
+static struct platform_device msm_device_smmu_vfe = {
+        .name = "msm_iommu",
+        .id = 6,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_vfe_resources),
+        .resource = msm_iommu_vfe_resources,
+};
+
+static struct platform_device msm_device_smmu_vcodec_a = {
+        .name = "msm_iommu",
+        .id = 7,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_vcodec_a_resources),
+        .resource = msm_iommu_vcodec_a_resources,
+};
+
+static struct platform_device msm_device_smmu_vcodec_b = {
+        .name = "msm_iommu",
+        .id = 8,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_vcodec_b_resources),
+        .resource = msm_iommu_vcodec_b_resources,
+};
+
+static struct platform_device msm_device_smmu_gfx3d = {
+        .name = "msm_iommu",
+        .id = 9,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_gfx3d_resources),
+        .resource = msm_iommu_gfx3d_resources,
+};
+
+static struct platform_device msm_device_smmu_gfx2d0 = {
+        .name = "msm_iommu",
+        .id = 10,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_gfx2d0_resources),
+        .resource = msm_iommu_gfx2d0_resources,
+};
+
+static struct msm_iommu_ctx_dev jpegd_src_ctx = {
+        .name = "jpegd_src",
+        .num = 0,
+        .mids = {0, -1}
+};
+
+static struct msm_iommu_ctx_dev jpegd_dst_ctx = {
+        .name = "jpegd_dst",
+        .num = 1,
+        .mids = {1, -1}
+};
+
+static struct msm_iommu_ctx_dev vpe_src_ctx = {
+        .name = "vpe_src",
+        .num = 0,
+        .mids = {0, -1}
+};
+
+static struct msm_iommu_ctx_dev vpe_dst_ctx = {
+        .name = "vpe_dst",
+        .num = 1,
+        .mids = {1, -1}
+};
+
+static struct msm_iommu_ctx_dev mdp_vg1_ctx = {
+        .name = "mdp_vg1",
+        .num = 0,
+        .mids = {0, 2, -1}
+};
+
+static struct msm_iommu_ctx_dev mdp_rgb1_ctx = {
+        .name = "mdp_rgb1",
+        .num = 1,
+        .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
+};
+
+static struct msm_iommu_ctx_dev mdp_vg2_ctx = {
+        .name = "mdp_vg2",
+        .num = 0,
+        .mids = {0, 2, -1}
+};
+
+static struct msm_iommu_ctx_dev mdp_rgb2_ctx = {
+        .name = "mdp_rgb2",
+        .num = 1,
+        .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
+};
+
+static struct msm_iommu_ctx_dev rot_src_ctx = {
+        .name = "rot_src",
+        .num = 0,
+        .mids = {0, -1}
+};
+
+static struct msm_iommu_ctx_dev rot_dst_ctx = {
+        .name = "rot_dst",
+        .num = 1,
+        .mids = {1, -1}
+};
+
+static struct msm_iommu_ctx_dev ijpeg_src_ctx = {
+        .name = "ijpeg_src",
+        .num = 0,
+        .mids = {0, -1}
+};
+
+static struct msm_iommu_ctx_dev ijpeg_dst_ctx = {
+        .name = "ijpeg_dst",
+        .num = 1,
+        .mids = {1, -1}
+};
+
+static struct msm_iommu_ctx_dev vfe_imgwr_ctx = {
+        .name = "vfe_imgwr",
+        .num = 0,
+        .mids = {2, 3, 4, 5, 6, 7, 8, -1}
+};
+
+static struct msm_iommu_ctx_dev vfe_misc_ctx = {
+        .name = "vfe_misc",
+        .num = 1,
+        .mids = {0, 1, 9, -1}
+};
+
+static struct msm_iommu_ctx_dev vcodec_a_stream_ctx = {
+        .name = "vcodec_a_stream",
+        .num = 0,
+        .mids = {2, 5, -1}
+};
+
+static struct msm_iommu_ctx_dev vcodec_a_mm1_ctx = {
+        .name = "vcodec_a_mm1",
+        .num = 1,
+        .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
+};
+
+static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = {
+        .name = "vcodec_b_mm2",
+        .num = 0,
+        .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
+};
+
+static struct msm_iommu_ctx_dev gfx3d_rbpa_ctx = {
+        .name = "gfx3d_rbpa",
+        .num = 0,
+        .mids = {-1}
+};
+
+static struct msm_iommu_ctx_dev gfx3d_cpvgttc_ctx = {
+        .name = "gfx3d_cpvgttc",
+        .num = 1,
+        .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
+};
+
+static struct msm_iommu_ctx_dev gfx3d_smmu_ctx = {
+        .name = "gfx3d_smmu",
+        .num = 2,
+        .mids = {8, 9, 10, 11, 12, -1}
+};
+
+static struct msm_iommu_ctx_dev gfx2d0_pixv1_ctx = {
+        .name = "gfx2d0_pixv1_smmu",
+        .num = 0,
+        .mids = {0, 3, 4, -1}
+};
+
+static struct msm_iommu_ctx_dev gfx2d0_texv3_ctx = {
+        .name = "gfx2d0_texv3_smmu",
+        .num = 1,
+        .mids = {1, 6, 7, -1}
+};
+
+static struct platform_device msm_device_jpegd_src_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 0,
+        .dev = {
+                .parent = &msm_device_smmu_jpegd.dev,
+        },
+};
+
+static struct platform_device msm_device_jpegd_dst_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 1,
+        .dev = {
+                .parent = &msm_device_smmu_jpegd.dev,
+        },
+};
+
+static struct platform_device msm_device_vpe_src_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 2,
+        .dev = {
+                .parent = &msm_device_smmu_vpe.dev,
+        },
+};
+
+static struct platform_device msm_device_vpe_dst_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 3,
+        .dev = {
+                .parent = &msm_device_smmu_vpe.dev,
+        },
+};
+
+static struct platform_device msm_device_mdp_vg1_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 4,
+        .dev = {
+                .parent = &msm_device_smmu_mdp0.dev,
+        },
+};
+
+static struct platform_device msm_device_mdp_rgb1_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 5,
+        .dev = {
+                .parent = &msm_device_smmu_mdp0.dev,
+        },
+};
+
+static struct platform_device msm_device_mdp_vg2_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 6,
+        .dev = {
+                .parent = &msm_device_smmu_mdp1.dev,
+        },
+};
+
+static struct platform_device msm_device_mdp_rgb2_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 7,
+        .dev = {
+                .parent = &msm_device_smmu_mdp1.dev,
+        },
+};
+
+static struct platform_device msm_device_rot_src_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 8,
+        .dev = {
+                .parent = &msm_device_smmu_rot.dev,
+        },
+};
+
+static struct platform_device msm_device_rot_dst_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 9,
+        .dev = {
+                .parent = &msm_device_smmu_rot.dev,
+        },
+};
+
+static struct platform_device msm_device_ijpeg_src_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 10,
+        .dev = {
+                .parent = &msm_device_smmu_ijpeg.dev,
+        },
+};
+
+static struct platform_device msm_device_ijpeg_dst_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 11,
+        .dev = {
+                .parent = &msm_device_smmu_ijpeg.dev,
+        },
+};
+
+static struct platform_device msm_device_vfe_imgwr_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 12,
+        .dev = {
+                .parent = &msm_device_smmu_vfe.dev,
+        },
+};
+
+static struct platform_device msm_device_vfe_misc_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 13,
+        .dev = {
+                .parent = &msm_device_smmu_vfe.dev,
+        },
+};
+
+static struct platform_device msm_device_vcodec_a_stream_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 14,
+        .dev = {
+                .parent = &msm_device_smmu_vcodec_a.dev,
+        },
+};
+
+static struct platform_device msm_device_vcodec_a_mm1_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 15,
+        .dev = {
+                .parent = &msm_device_smmu_vcodec_a.dev,
+        },
+};
+
+static struct platform_device msm_device_vcodec_b_mm2_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 16,
+        .dev = {
+                .parent = &msm_device_smmu_vcodec_b.dev,
+        },
+};
+
+static struct platform_device msm_device_gfx3d_rbpa_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 17,
+        .dev = {
+                .parent = &msm_device_smmu_gfx3d.dev,
+        },
+};
+
+static struct platform_device msm_device_gfx3d_cpvgttc_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 18,
+        .dev = {
+                .parent = &msm_device_smmu_gfx3d.dev,
+        },
+};
+
+static struct platform_device msm_device_gfx3d_smmu_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 19,
+        .dev = {
+                .parent = &msm_device_smmu_gfx3d.dev,
+        },
+};
+
+static struct platform_device msm_device_gfx2d0_pixv1_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 20,
+        .dev = {
+                .parent = &msm_device_smmu_gfx2d0.dev,
+        },
+};
+
+static struct platform_device msm_device_gfx2d0_texv3_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 21,
+        .dev = {
+                .parent = &msm_device_smmu_gfx2d0.dev,
+        },
+};
+
+static struct platform_device *msm_iommu_devs[] = {
+        &msm_device_smmu_jpegd,
+        &msm_device_smmu_vpe,
+        &msm_device_smmu_mdp0,
+        &msm_device_smmu_mdp1,
+        &msm_device_smmu_rot,
+        &msm_device_smmu_ijpeg,
+        &msm_device_smmu_vfe,
+        &msm_device_smmu_vcodec_a,
+        &msm_device_smmu_vcodec_b,
+        &msm_device_smmu_gfx3d,
+        &msm_device_smmu_gfx2d0,
+};
+
+static struct msm_iommu_dev *msm_iommu_data[] = {
+        &jpegd_smmu,
+        &vpe_smmu,
+        &mdp0_smmu,
+        &mdp1_smmu,
+        &rot_smmu,
+        &ijpeg_smmu,
+        &vfe_smmu,
+        &vcodec_a_smmu,
+        &vcodec_b_smmu,
+        &gfx3d_smmu,
+        &gfx2d0_smmu,
+};
+
+static struct platform_device *msm_iommu_ctx_devs[] = {
+        &msm_device_jpegd_src_ctx,
+        &msm_device_jpegd_dst_ctx,
+        &msm_device_vpe_src_ctx,
+        &msm_device_vpe_dst_ctx,
+        &msm_device_mdp_vg1_ctx,
+        &msm_device_mdp_rgb1_ctx,
+        &msm_device_mdp_vg2_ctx,
+        &msm_device_mdp_rgb2_ctx,
+        &msm_device_rot_src_ctx,
+        &msm_device_rot_dst_ctx,
+        &msm_device_ijpeg_src_ctx,
+        &msm_device_ijpeg_dst_ctx,
+        &msm_device_vfe_imgwr_ctx,
+        &msm_device_vfe_misc_ctx,
+        &msm_device_vcodec_a_stream_ctx,
+        &msm_device_vcodec_a_mm1_ctx,
+        &msm_device_vcodec_b_mm2_ctx,
+        &msm_device_gfx3d_rbpa_ctx,
+        &msm_device_gfx3d_cpvgttc_ctx,
+        &msm_device_gfx3d_smmu_ctx,
+        &msm_device_gfx2d0_pixv1_ctx,
+        &msm_device_gfx2d0_texv3_ctx,
+};
+
+static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
+        &jpegd_src_ctx,
+        &jpegd_dst_ctx,
+        &vpe_src_ctx,
+        &vpe_dst_ctx,
+        &mdp_vg1_ctx,
+        &mdp_rgb1_ctx,
+        &mdp_vg2_ctx,
+        &mdp_rgb2_ctx,
+        &rot_src_ctx,
+        &rot_dst_ctx,
+        &ijpeg_src_ctx,
+        &ijpeg_dst_ctx,
+        &vfe_imgwr_ctx,
+        &vfe_misc_ctx,
+        &vcodec_a_stream_ctx,
+        &vcodec_a_mm1_ctx,
+        &vcodec_b_mm2_ctx,
+        &gfx3d_rbpa_ctx,
+        &gfx3d_cpvgttc_ctx,
+        &gfx3d_smmu_ctx,
+        &gfx2d0_pixv1_ctx,
+        &gfx2d0_texv3_ctx,
+};
+
+static int msm8x60_iommu_init(void)
+{
+        int ret, i;
+
+        ret = platform_device_register(&msm_root_iommu_dev);
+        if (ret != 0) {
+                pr_err("Failed to register root IOMMU device!\n");
+                goto failure;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); i++) {
+                ret = platform_device_add_data(msm_iommu_devs[i],
+                                               msm_iommu_data[i],
+                                               sizeof(struct msm_iommu_dev));
+                if (ret != 0) {
+                        pr_err("platform_device_add_data failed, "
+                               "i = %d\n", i);
+                        goto failure_unwind;
+                }
+
+                ret = platform_device_register(msm_iommu_devs[i]);
+
+                if (ret != 0) {
+                        pr_err("platform_device_register smmu failed, "
+                               "i = %d\n", i);
+                        goto failure_unwind;
+                }
+        }
+
+        for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) {
+                ret = platform_device_add_data(msm_iommu_ctx_devs[i],
+                                               msm_iommu_ctx_data[i],
+                                               sizeof(*msm_iommu_ctx_devs[i]));
+                if (ret != 0) {
+                        pr_err("platform_device_add_data smmu failed, "
+                               "i = %d\n", i);
+                        goto failure_unwind2;
+                }
+
+                ret = platform_device_register(msm_iommu_ctx_devs[i]);
+                if (ret != 0) {
+                        pr_err("platform_device_register ctx failed, "
+                               "i = %d\n", i);
+                        goto failure_unwind2;
+                }
+        }
+        return 0;
+
+failure_unwind2:
+        while (--i >= 0)
+                platform_device_unregister(msm_iommu_ctx_devs[i]);
+failure_unwind:
+        while (--i >= 0)
+                platform_device_unregister(msm_iommu_devs[i]);
+
+        platform_device_unregister(&msm_root_iommu_dev);
+failure:
+        return ret;
+}
+
+static void msm8x60_iommu_exit(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++)
+                platform_device_unregister(msm_iommu_ctx_devs[i]);
+
+        for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); ++i)
+                platform_device_unregister(msm_iommu_devs[i]);
+
+        platform_device_unregister(&msm_root_iommu_dev);
+}
+
+subsys_initcall(msm8x60_iommu_init);
+module_exit(msm8x60_iommu_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 4d4a50785e34..6fe67c5d1ae0 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -48,6 +48,11 @@ struct platform_device msm_device_uart3 = {
         .resource       = resources_uart3,
 };
 
+struct platform_device msm_device_smd = {
+        .name   = "msm_smd",
+        .id     = -1,
+};
+
 struct clk msm_clocks_8x50[] = {
         CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
         CLK_PCOM("ebi1_clk",    EBI1_CLK,       NULL, CLK_MIN),
diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c
index bc32c845c7b0..33051b509e88 100644
--- a/arch/arm/mach-msm/gpio.c
+++ b/arch/arm/mach-msm/gpio.c
@@ -1,7 +1,7 @@
 /* linux/arch/arm/mach-msm/gpio.c
  *
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2009, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -14,72 +14,363 @@
  *
  */
 
+#include <linux/bitops.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
 #include <linux/module.h>
-#include <mach/gpio.h>
-#include "proc_comm.h"
-
-int gpio_tlmm_config(unsigned config, unsigned disable)
-{
-        return msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, &disable);
-}
-EXPORT_SYMBOL(gpio_tlmm_config);
-
-int msm_gpios_enable(const struct msm_gpio *table, int size)
-{
-        int rc;
-        int i;
-        const struct msm_gpio *g;
-        for (i = 0; i < size; i++) {
-                g = table + i;
-                rc = gpio_tlmm_config(g->gpio_cfg, GPIO_ENABLE);
-                if (rc) {
-                        pr_err("gpio_tlmm_config(0x%08x, GPIO_ENABLE)"
-                               " <%s> failed: %d\n",
-                               g->gpio_cfg, g->label ?: "?", rc);
-                        pr_err("pin %d func %d dir %d pull %d drvstr %d\n",
-                               GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg),
-                               GPIO_DIR(g->gpio_cfg), GPIO_PULL(g->gpio_cfg),
-                               GPIO_DRVSTR(g->gpio_cfg));
-                        goto err;
-                }
+#include "gpio_hw.h"
+#include "gpiomux.h"
+
+#define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0)
+
+#define MSM_GPIO_BANK(bank, first, last)                                \
+        {                                                               \
+                .regs = {                                               \
+                        .out =         MSM_GPIO_OUT_##bank,             \
+                        .in =          MSM_GPIO_IN_##bank,              \
+                        .int_status =  MSM_GPIO_INT_STATUS_##bank,      \
+                        .int_clear =   MSM_GPIO_INT_CLEAR_##bank,       \
+                        .int_en =      MSM_GPIO_INT_EN_##bank,          \
+                        .int_edge =    MSM_GPIO_INT_EDGE_##bank,        \
+                        .int_pos =     MSM_GPIO_INT_POS_##bank,         \
+                        .oe =          MSM_GPIO_OE_##bank,              \
+                },                                                      \
+                .chip = {                                               \
+                        .base = (first),                                \
+                        .ngpio = (last) - (first) + 1,                  \
+                        .get = msm_gpio_get,                            \
+                        .set = msm_gpio_set,                            \
+                        .direction_input = msm_gpio_direction_input,    \
+                        .direction_output = msm_gpio_direction_output,  \
+                        .to_irq = msm_gpio_to_irq,                      \
+                        .request = msm_gpio_request,                    \
+                        .free = msm_gpio_free,                          \
+                }                                                       \
         }
+
+#define MSM_GPIO_BROKEN_INT_CLEAR 1
+
+struct msm_gpio_regs {
+        void __iomem *out;
+        void __iomem *in;
+        void __iomem *int_status;
+        void __iomem *int_clear;
+        void __iomem *int_en;
+        void __iomem *int_edge;
+        void __iomem *int_pos;
+        void __iomem *oe;
+};
+
+struct msm_gpio_chip {
+        spinlock_t              lock;
+        struct gpio_chip        chip;
+        struct msm_gpio_regs    regs;
+#if MSM_GPIO_BROKEN_INT_CLEAR
+        unsigned                int_status_copy;
+#endif
+        unsigned int            both_edge_detect;
+        unsigned int            int_enable[2]; /* 0: awake, 1: sleep */
+};
+
+static int msm_gpio_write(struct msm_gpio_chip *msm_chip,
+                          unsigned offset, unsigned on)
+{
+        unsigned mask = BIT(offset);
+        unsigned val;
+
+        val = readl(msm_chip->regs.out);
+        if (on)
+                writel(val | mask, msm_chip->regs.out);
+        else
+                writel(val & ~mask, msm_chip->regs.out);
         return 0;
-err:
-        msm_gpios_disable(table, i);
-        return rc;
-}
-EXPORT_SYMBOL(msm_gpios_enable);
-
-void msm_gpios_disable(const struct msm_gpio *table, int size)
-{
-        int rc;
-        int i;
-        const struct msm_gpio *g;
-        for (i = size-1; i >= 0; i--) {
-                g = table + i;
-                rc = gpio_tlmm_config(g->gpio_cfg, GPIO_DISABLE);
-                if (rc) {
-                        pr_err("gpio_tlmm_config(0x%08x, GPIO_DISABLE)"
-                               " <%s> failed: %d\n",
-                               g->gpio_cfg, g->label ?: "?", rc);
-                        pr_err("pin %d func %d dir %d pull %d drvstr %d\n",
-                               GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg),
-                               GPIO_DIR(g->gpio_cfg), GPIO_PULL(g->gpio_cfg),
-                               GPIO_DRVSTR(g->gpio_cfg));
-                }
+}
+
+static void msm_gpio_update_both_edge_detect(struct msm_gpio_chip *msm_chip)
+{
+        int loop_limit = 100;
+        unsigned pol, val, val2, intstat;
+        do {
+                val = readl(msm_chip->regs.in);
+                pol = readl(msm_chip->regs.int_pos);
+                pol = (pol & ~msm_chip->both_edge_detect) |
+                      (~val & msm_chip->both_edge_detect);
+                writel(pol, msm_chip->regs.int_pos);
+                intstat = readl(msm_chip->regs.int_status);
+                val2 = readl(msm_chip->regs.in);
+                if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0)
+                        return;
+        } while (loop_limit-- > 0);
+        printk(KERN_ERR "msm_gpio_update_both_edge_detect, "
+               "failed to reach stable state %x != %x\n", val, val2);
+}
+
+static int msm_gpio_clear_detect_status(struct msm_gpio_chip *msm_chip,
+                                        unsigned offset)
+{
+        unsigned bit = BIT(offset);
+
+#if MSM_GPIO_BROKEN_INT_CLEAR
+        /* Save interrupts that already triggered before we loose them. */
+        /* Any interrupt that triggers between the read of int_status */
+        /* and the write to int_clear will still be lost though. */
+        msm_chip->int_status_copy |= readl(msm_chip->regs.int_status);
+        msm_chip->int_status_copy &= ~bit;
+#endif
+        writel(bit, msm_chip->regs.int_clear);
+        msm_gpio_update_both_edge_detect(msm_chip);
+        return 0;
+}
+
+static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        struct msm_gpio_chip *msm_chip;
+        unsigned long irq_flags;
+
+        msm_chip = container_of(chip, struct msm_gpio_chip, chip);
+        spin_lock_irqsave(&msm_chip->lock, irq_flags);
+        writel(readl(msm_chip->regs.oe) & ~BIT(offset), msm_chip->regs.oe);
+        spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
+        return 0;
+}
+
+static int
+msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct msm_gpio_chip *msm_chip;
+        unsigned long irq_flags;
+
+        msm_chip = container_of(chip, struct msm_gpio_chip, chip);
+        spin_lock_irqsave(&msm_chip->lock, irq_flags);
+        msm_gpio_write(msm_chip, offset, value);
+        writel(readl(msm_chip->regs.oe) | BIT(offset), msm_chip->regs.oe);
+        spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
+        return 0;
+}
+
+static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct msm_gpio_chip *msm_chip;
+
+        msm_chip = container_of(chip, struct msm_gpio_chip, chip);
+        return (readl(msm_chip->regs.in) & (1U << offset)) ? 1 : 0;
+}
+
+static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct msm_gpio_chip *msm_chip;
+        unsigned long irq_flags;
+
+        msm_chip = container_of(chip, struct msm_gpio_chip, chip);
+        spin_lock_irqsave(&msm_chip->lock, irq_flags);
+        msm_gpio_write(msm_chip, offset, value);
+        spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
+}
+
+static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+        return MSM_GPIO_TO_INT(chip->base + offset);
+}
+
+#ifdef CONFIG_MSM_GPIOMUX
+static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+        return msm_gpiomux_get(chip->base + offset);
+}
+
+static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+        msm_gpiomux_put(chip->base + offset);
+}
+#else
+#define msm_gpio_request NULL
+#define msm_gpio_free NULL
+#endif
+
+struct msm_gpio_chip msm_gpio_chips[] = {
+#if defined(CONFIG_ARCH_MSM7X00A)
+        MSM_GPIO_BANK(0,   0,  15),
+        MSM_GPIO_BANK(1,  16,  42),
+        MSM_GPIO_BANK(2,  43,  67),
+        MSM_GPIO_BANK(3,  68,  94),
+        MSM_GPIO_BANK(4,  95, 106),
+        MSM_GPIO_BANK(5, 107, 121),
+#elif defined(CONFIG_ARCH_MSM7X25) || defined(CONFIG_ARCH_MSM7X27)
+        MSM_GPIO_BANK(0,   0,  15),
+        MSM_GPIO_BANK(1,  16,  42),
+        MSM_GPIO_BANK(2,  43,  67),
+        MSM_GPIO_BANK(3,  68,  94),
+        MSM_GPIO_BANK(4,  95, 106),
+        MSM_GPIO_BANK(5, 107, 132),
+#elif defined(CONFIG_ARCH_MSM7X30)
+        MSM_GPIO_BANK(0,   0,  15),
+        MSM_GPIO_BANK(1,  16,  43),
+        MSM_GPIO_BANK(2,  44,  67),
+        MSM_GPIO_BANK(3,  68,  94),
+        MSM_GPIO_BANK(4,  95, 106),
+        MSM_GPIO_BANK(5, 107, 133),
+        MSM_GPIO_BANK(6, 134, 150),
+        MSM_GPIO_BANK(7, 151, 181),
+#elif defined(CONFIG_ARCH_QSD8X50)
+        MSM_GPIO_BANK(0,   0,  15),
+        MSM_GPIO_BANK(1,  16,  42),
+        MSM_GPIO_BANK(2,  43,  67),
+        MSM_GPIO_BANK(3,  68,  94),
+        MSM_GPIO_BANK(4,  95, 103),
+        MSM_GPIO_BANK(5, 104, 121),
+        MSM_GPIO_BANK(6, 122, 152),
+        MSM_GPIO_BANK(7, 153, 164),
+#endif
+};
+
+static void msm_gpio_irq_ack(unsigned int irq)
+{
+        unsigned long irq_flags;
+        struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
+        spin_lock_irqsave(&msm_chip->lock, irq_flags);
+        msm_gpio_clear_detect_status(msm_chip,
+                                     irq - gpio_to_irq(msm_chip->chip.base));
+        spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
+}
+
+static void msm_gpio_irq_mask(unsigned int irq)
+{
+        unsigned long irq_flags;
+        struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
+        unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
+
+        spin_lock_irqsave(&msm_chip->lock, irq_flags);
+        /* level triggered interrupts are also latched */
+        if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
+                msm_gpio_clear_detect_status(msm_chip, offset);
+        msm_chip->int_enable[0] &= ~BIT(offset);
+        writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
+        spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
+}
+
+static void msm_gpio_irq_unmask(unsigned int irq)
+{
+        unsigned long irq_flags;
+        struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
+        unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
+
+        spin_lock_irqsave(&msm_chip->lock, irq_flags);
+        /* level triggered interrupts are also latched */
+        if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
+                msm_gpio_clear_detect_status(msm_chip, offset);
+        msm_chip->int_enable[0] |= BIT(offset);
+        writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
+        spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
+}
+
+static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
+{
+        unsigned long irq_flags;
+        struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
+        unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
+
+        spin_lock_irqsave(&msm_chip->lock, irq_flags);
+
+        if (on)
+                msm_chip->int_enable[1] |= BIT(offset);
+        else
+                msm_chip->int_enable[1] &= ~BIT(offset);
+
+        spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
+        return 0;
+}
+
+static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
+{
+        unsigned long irq_flags;
+        struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
+        unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
+        unsigned val, mask = BIT(offset);
+
+        spin_lock_irqsave(&msm_chip->lock, irq_flags);
+        val = readl(msm_chip->regs.int_edge);
+        if (flow_type & IRQ_TYPE_EDGE_BOTH) {
+                writel(val | mask, msm_chip->regs.int_edge);
+                irq_desc[irq].handle_irq = handle_edge_irq;
+        } else {
+                writel(val & ~mask, msm_chip->regs.int_edge);
+                irq_desc[irq].handle_irq = handle_level_irq;
+        }
+        if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
+                msm_chip->both_edge_detect |= mask;
+                msm_gpio_update_both_edge_detect(msm_chip);
+        } else {
+                msm_chip->both_edge_detect &= ~mask;
+                val = readl(msm_chip->regs.int_pos);
+                if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
+                        writel(val | mask, msm_chip->regs.int_pos);
+                else
+                        writel(val & ~mask, msm_chip->regs.int_pos);
         }
+        spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
+        return 0;
 }
-EXPORT_SYMBOL(msm_gpios_disable);
 
-int msm_gpios_request_enable(const struct msm_gpio *table, int size)
+static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
-        int rc = msm_gpios_enable(table, size);
-        return rc;
+        int i, j, mask;
+        unsigned val;
+
+        for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
+                struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i];
+                val = readl(msm_chip->regs.int_status);
+                val &= msm_chip->int_enable[0];
+                while (val) {
+                        mask = val & -val;
+                        j = fls(mask) - 1;
+                        /* printk("%s %08x %08x bit %d gpio %d irq %d\n",
+                                __func__, v, m, j, msm_chip->chip.start + j,
+                                FIRST_GPIO_IRQ + msm_chip->chip.start + j); */
+                        val &= ~mask;
+                        generic_handle_irq(FIRST_GPIO_IRQ +
+                                           msm_chip->chip.base + j);
+                }
+        }
+        desc->chip->ack(irq);
 }
-EXPORT_SYMBOL(msm_gpios_request_enable);
 
-void msm_gpios_disable_free(const struct msm_gpio *table, int size)
+static struct irq_chip msm_gpio_irq_chip = {
+        .name      = "msmgpio",
+        .ack       = msm_gpio_irq_ack,
+        .mask      = msm_gpio_irq_mask,
+        .unmask    = msm_gpio_irq_unmask,
+        .set_wake  = msm_gpio_irq_set_wake,
+        .set_type  = msm_gpio_irq_set_type,
+};
+
+static int __init msm_init_gpio(void)
 {
-        msm_gpios_disable(table, size);
+        int i, j = 0;
+
+        for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) {
+                if (i - FIRST_GPIO_IRQ >=
+                        msm_gpio_chips[j].chip.base +
+                        msm_gpio_chips[j].chip.ngpio)
+                        j++;
+                set_irq_chip_data(i, &msm_gpio_chips[j]);
+                set_irq_chip(i, &msm_gpio_irq_chip);
+                set_irq_handler(i, handle_edge_irq);
+                set_irq_flags(i, IRQF_VALID);
+        }
+
+        for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
+                spin_lock_init(&msm_gpio_chips[i].lock);
+                writel(0, msm_gpio_chips[i].regs.int_en);
+                gpiochip_add(&msm_gpio_chips[i].chip);
+        }
+
+        set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
+        set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
+        set_irq_wake(INT_GPIO_GROUP1, 1);
+        set_irq_wake(INT_GPIO_GROUP2, 2);
+        return 0;
 }
-EXPORT_SYMBOL(msm_gpios_disable_free);
+
+postcore_initcall(msm_init_gpio);
diff --git a/arch/arm/mach-msm/gpio_hw.h b/arch/arm/mach-msm/gpio_hw.h
new file mode 100644
index 000000000000..6b5066038baa
--- /dev/null
+++ b/arch/arm/mach-msm/gpio_hw.h
@@ -0,0 +1,278 @@
+/* arch/arm/mach-msm/gpio_hw.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_MSM_GPIO_HW_H
+#define __ARCH_ARM_MACH_MSM_GPIO_HW_H
+
+#include <mach/msm_iomap.h>
+
+/* see 80-VA736-2 Rev C pp 695-751
+**
+** These are actually the *shadow* gpio registers, since the
+** real ones (which allow full access) are only available to the
+** ARM9 side of the world.
+**
+** Since the _BASE need to be page-aligned when we're mapping them
+** to virtual addresses, adjust for the additional offset in these
+** macros.
+*/
+
+#if defined(CONFIG_ARCH_MSM7X30)
+#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off))
+#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off))
+#else
+#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
+#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
+#endif
+
+#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X25) ||\
+    defined(CONFIG_ARCH_MSM7X27)
+
+/* output value */
+#define MSM_GPIO_OUT_0         MSM_GPIO1_REG(0x00)  /* gpio  15-0  */
+#define MSM_GPIO_OUT_1         MSM_GPIO2_REG(0x00)  /* gpio  42-16 */
+#define MSM_GPIO_OUT_2         MSM_GPIO1_REG(0x04)  /* gpio  67-43 */
+#define MSM_GPIO_OUT_3         MSM_GPIO1_REG(0x08)  /* gpio  94-68 */
+#define MSM_GPIO_OUT_4         MSM_GPIO1_REG(0x0C)  /* gpio 106-95 */
+#define MSM_GPIO_OUT_5         MSM_GPIO1_REG(0x50)  /* gpio 107-121 */
+
+/* same pin map as above, output enable */
+#define MSM_GPIO_OE_0          MSM_GPIO1_REG(0x10)
+#define MSM_GPIO_OE_1          MSM_GPIO2_REG(0x08)
+#define MSM_GPIO_OE_2          MSM_GPIO1_REG(0x14)
+#define MSM_GPIO_OE_3          MSM_GPIO1_REG(0x18)
+#define MSM_GPIO_OE_4          MSM_GPIO1_REG(0x1C)
+#define MSM_GPIO_OE_5          MSM_GPIO1_REG(0x54)
+
+/* same pin map as above, input read */
+#define MSM_GPIO_IN_0          MSM_GPIO1_REG(0x34)
+#define MSM_GPIO_IN_1          MSM_GPIO2_REG(0x20)
+#define MSM_GPIO_IN_2          MSM_GPIO1_REG(0x38)
+#define MSM_GPIO_IN_3          MSM_GPIO1_REG(0x3C)
+#define MSM_GPIO_IN_4          MSM_GPIO1_REG(0x40)
+#define MSM_GPIO_IN_5          MSM_GPIO1_REG(0x44)
+
+/* same pin map as above, 1=edge 0=level interrup */
+#define MSM_GPIO_INT_EDGE_0    MSM_GPIO1_REG(0x60)
+#define MSM_GPIO_INT_EDGE_1    MSM_GPIO2_REG(0x50)
+#define MSM_GPIO_INT_EDGE_2    MSM_GPIO1_REG(0x64)
+#define MSM_GPIO_INT_EDGE_3    MSM_GPIO1_REG(0x68)
+#define MSM_GPIO_INT_EDGE_4    MSM_GPIO1_REG(0x6C)
+#define MSM_GPIO_INT_EDGE_5    MSM_GPIO1_REG(0xC0)
+
+/* same pin map as above, 1=positive 0=negative */
+#define MSM_GPIO_INT_POS_0     MSM_GPIO1_REG(0x70)
+#define MSM_GPIO_INT_POS_1     MSM_GPIO2_REG(0x58)
+#define MSM_GPIO_INT_POS_2     MSM_GPIO1_REG(0x74)
+#define MSM_GPIO_INT_POS_3     MSM_GPIO1_REG(0x78)
+#define MSM_GPIO_INT_POS_4     MSM_GPIO1_REG(0x7C)
+#define MSM_GPIO_INT_POS_5     MSM_GPIO1_REG(0xBC)
+
+/* same pin map as above, interrupt enable */
+#define MSM_GPIO_INT_EN_0      MSM_GPIO1_REG(0x80)
+#define MSM_GPIO_INT_EN_1      MSM_GPIO2_REG(0x60)
+#define MSM_GPIO_INT_EN_2      MSM_GPIO1_REG(0x84)
+#define MSM_GPIO_INT_EN_3      MSM_GPIO1_REG(0x88)
+#define MSM_GPIO_INT_EN_4      MSM_GPIO1_REG(0x8C)
+#define MSM_GPIO_INT_EN_5      MSM_GPIO1_REG(0xB8)
+
+/* same pin map as above, write 1 to clear interrupt */
+#define MSM_GPIO_INT_CLEAR_0   MSM_GPIO1_REG(0x90)
+#define MSM_GPIO_INT_CLEAR_1   MSM_GPIO2_REG(0x68)
+#define MSM_GPIO_INT_CLEAR_2   MSM_GPIO1_REG(0x94)
+#define MSM_GPIO_INT_CLEAR_3   MSM_GPIO1_REG(0x98)
+#define MSM_GPIO_INT_CLEAR_4   MSM_GPIO1_REG(0x9C)
+#define MSM_GPIO_INT_CLEAR_5   MSM_GPIO1_REG(0xB4)
+
+/* same pin map as above, 1=interrupt pending */
+#define MSM_GPIO_INT_STATUS_0  MSM_GPIO1_REG(0xA0)
+#define MSM_GPIO_INT_STATUS_1  MSM_GPIO2_REG(0x70)
+#define MSM_GPIO_INT_STATUS_2  MSM_GPIO1_REG(0xA4)
+#define MSM_GPIO_INT_STATUS_3  MSM_GPIO1_REG(0xA8)
+#define MSM_GPIO_INT_STATUS_4  MSM_GPIO1_REG(0xAC)
+#define MSM_GPIO_INT_STATUS_5  MSM_GPIO1_REG(0xB0)
+
+#endif
+
+#if defined(CONFIG_ARCH_QSD8X50)
+/* output value */
+#define MSM_GPIO_OUT_0         MSM_GPIO1_REG(0x00)  /* gpio  15-0   */
+#define MSM_GPIO_OUT_1         MSM_GPIO2_REG(0x00)  /* gpio  42-16  */
+#define MSM_GPIO_OUT_2         MSM_GPIO1_REG(0x04)  /* gpio  67-43  */
+#define MSM_GPIO_OUT_3         MSM_GPIO1_REG(0x08)  /* gpio  94-68  */
+#define MSM_GPIO_OUT_4         MSM_GPIO1_REG(0x0C)  /* gpio 103-95  */
+#define MSM_GPIO_OUT_5         MSM_GPIO1_REG(0x10)  /* gpio 121-104 */
+#define MSM_GPIO_OUT_6         MSM_GPIO1_REG(0x14)  /* gpio 152-122 */
+#define MSM_GPIO_OUT_7         MSM_GPIO1_REG(0x18)  /* gpio 164-153 */
+
+/* same pin map as above, output enable */
+#define MSM_GPIO_OE_0          MSM_GPIO1_REG(0x20)
+#define MSM_GPIO_OE_1          MSM_GPIO2_REG(0x08)
+#define MSM_GPIO_OE_2          MSM_GPIO1_REG(0x24)
+#define MSM_GPIO_OE_3          MSM_GPIO1_REG(0x28)
+#define MSM_GPIO_OE_4          MSM_GPIO1_REG(0x2C)
+#define MSM_GPIO_OE_5          MSM_GPIO1_REG(0x30)
+#define MSM_GPIO_OE_6          MSM_GPIO1_REG(0x34)
+#define MSM_GPIO_OE_7          MSM_GPIO1_REG(0x38)
+
+/* same pin map as above, input read */
+#define MSM_GPIO_IN_0          MSM_GPIO1_REG(0x50)
+#define MSM_GPIO_IN_1          MSM_GPIO2_REG(0x20)
+#define MSM_GPIO_IN_2          MSM_GPIO1_REG(0x54)
+#define MSM_GPIO_IN_3          MSM_GPIO1_REG(0x58)
+#define MSM_GPIO_IN_4          MSM_GPIO1_REG(0x5C)
+#define MSM_GPIO_IN_5          MSM_GPIO1_REG(0x60)
+#define MSM_GPIO_IN_6          MSM_GPIO1_REG(0x64)
+#define MSM_GPIO_IN_7          MSM_GPIO1_REG(0x68)
+
+/* same pin map as above, 1=edge 0=level interrup */
+#define MSM_GPIO_INT_EDGE_0    MSM_GPIO1_REG(0x70)
+#define MSM_GPIO_INT_EDGE_1    MSM_GPIO2_REG(0x50)
+#define MSM_GPIO_INT_EDGE_2    MSM_GPIO1_REG(0x74)
+#define MSM_GPIO_INT_EDGE_3    MSM_GPIO1_REG(0x78)
+#define MSM_GPIO_INT_EDGE_4    MSM_GPIO1_REG(0x7C)
+#define MSM_GPIO_INT_EDGE_5    MSM_GPIO1_REG(0x80)
+#define MSM_GPIO_INT_EDGE_6    MSM_GPIO1_REG(0x84)
+#define MSM_GPIO_INT_EDGE_7    MSM_GPIO1_REG(0x88)
+
+/* same pin map as above, 1=positive 0=negative */
+#define MSM_GPIO_INT_POS_0     MSM_GPIO1_REG(0x90)
+#define MSM_GPIO_INT_POS_1     MSM_GPIO2_REG(0x58)
+#define MSM_GPIO_INT_POS_2     MSM_GPIO1_REG(0x94)
+#define MSM_GPIO_INT_POS_3     MSM_GPIO1_REG(0x98)
+#define MSM_GPIO_INT_POS_4     MSM_GPIO1_REG(0x9C)
+#define MSM_GPIO_INT_POS_5     MSM_GPIO1_REG(0xA0)
+#define MSM_GPIO_INT_POS_6     MSM_GPIO1_REG(0xA4)
+#define MSM_GPIO_INT_POS_7     MSM_GPIO1_REG(0xA8)
+
+/* same pin map as above, interrupt enable */
+#define MSM_GPIO_INT_EN_0      MSM_GPIO1_REG(0xB0)
+#define MSM_GPIO_INT_EN_1      MSM_GPIO2_REG(0x60)
+#define MSM_GPIO_INT_EN_2      MSM_GPIO1_REG(0xB4)
+#define MSM_GPIO_INT_EN_3      MSM_GPIO1_REG(0xB8)
+#define MSM_GPIO_INT_EN_4      MSM_GPIO1_REG(0xBC)
+#define MSM_GPIO_INT_EN_5      MSM_GPIO1_REG(0xC0)
+#define MSM_GPIO_INT_EN_6      MSM_GPIO1_REG(0xC4)
+#define MSM_GPIO_INT_EN_7      MSM_GPIO1_REG(0xC8)
+
+/* same pin map as above, write 1 to clear interrupt */
+#define MSM_GPIO_INT_CLEAR_0   MSM_GPIO1_REG(0xD0)
+#define MSM_GPIO_INT_CLEAR_1   MSM_GPIO2_REG(0x68)
+#define MSM_GPIO_INT_CLEAR_2   MSM_GPIO1_REG(0xD4)
+#define MSM_GPIO_INT_CLEAR_3   MSM_GPIO1_REG(0xD8)
+#define MSM_GPIO_INT_CLEAR_4   MSM_GPIO1_REG(0xDC)
+#define MSM_GPIO_INT_CLEAR_5   MSM_GPIO1_REG(0xE0)
+#define MSM_GPIO_INT_CLEAR_6   MSM_GPIO1_REG(0xE4)
+#define MSM_GPIO_INT_CLEAR_7   MSM_GPIO1_REG(0xE8)
+
+/* same pin map as above, 1=interrupt pending */
+#define MSM_GPIO_INT_STATUS_0  MSM_GPIO1_REG(0xF0)
+#define MSM_GPIO_INT_STATUS_1  MSM_GPIO2_REG(0x70)
+#define MSM_GPIO_INT_STATUS_2  MSM_GPIO1_REG(0xF4)
+#define MSM_GPIO_INT_STATUS_3  MSM_GPIO1_REG(0xF8)
+#define MSM_GPIO_INT_STATUS_4  MSM_GPIO1_REG(0xFC)
+#define MSM_GPIO_INT_STATUS_5  MSM_GPIO1_REG(0x100)
+#define MSM_GPIO_INT_STATUS_6  MSM_GPIO1_REG(0x104)
+#define MSM_GPIO_INT_STATUS_7  MSM_GPIO1_REG(0x108)
+
+#endif
+
+#if defined(CONFIG_ARCH_MSM7X30)
+
+/* output value */
+#define MSM_GPIO_OUT_0         MSM_GPIO1_REG(0x00)   /* gpio  15-0   */
+#define MSM_GPIO_OUT_1         MSM_GPIO2_REG(0x00)   /* gpio  43-16  */
+#define MSM_GPIO_OUT_2         MSM_GPIO1_REG(0x04)   /* gpio  67-44  */
+#define MSM_GPIO_OUT_3         MSM_GPIO1_REG(0x08)   /* gpio  94-68  */
+#define MSM_GPIO_OUT_4         MSM_GPIO1_REG(0x0C)   /* gpio 106-95  */
+#define MSM_GPIO_OUT_5         MSM_GPIO1_REG(0x50)   /* gpio 133-107 */
+#define MSM_GPIO_OUT_6         MSM_GPIO1_REG(0xC4)   /* gpio 150-134 */
+#define MSM_GPIO_OUT_7         MSM_GPIO1_REG(0x214)  /* gpio 181-151 */
+
+/* same pin map as above, output enable */
+#define MSM_GPIO_OE_0          MSM_GPIO1_REG(0x10)
+#define MSM_GPIO_OE_1          MSM_GPIO2_REG(0x08)
+#define MSM_GPIO_OE_2          MSM_GPIO1_REG(0x14)
+#define MSM_GPIO_OE_3          MSM_GPIO1_REG(0x18)
+#define MSM_GPIO_OE_4          MSM_GPIO1_REG(0x1C)
+#define MSM_GPIO_OE_5          MSM_GPIO1_REG(0x54)
+#define MSM_GPIO_OE_6          MSM_GPIO1_REG(0xC8)
+#define MSM_GPIO_OE_7          MSM_GPIO1_REG(0x218)
+
+/* same pin map as above, input read */
+#define MSM_GPIO_IN_0          MSM_GPIO1_REG(0x34)
+#define MSM_GPIO_IN_1          MSM_GPIO2_REG(0x20)
+#define MSM_GPIO_IN_2          MSM_GPIO1_REG(0x38)
+#define MSM_GPIO_IN_3          MSM_GPIO1_REG(0x3C)
+#define MSM_GPIO_IN_4          MSM_GPIO1_REG(0x40)
+#define MSM_GPIO_IN_5          MSM_GPIO1_REG(0x44)
+#define MSM_GPIO_IN_6          MSM_GPIO1_REG(0xCC)
+#define MSM_GPIO_IN_7          MSM_GPIO1_REG(0x21C)
+
+/* same pin map as above, 1=edge 0=level interrup */
+#define MSM_GPIO_INT_EDGE_0    MSM_GPIO1_REG(0x60)
+#define MSM_GPIO_INT_EDGE_1    MSM_GPIO2_REG(0x50)
+#define MSM_GPIO_INT_EDGE_2    MSM_GPIO1_REG(0x64)
+#define MSM_GPIO_INT_EDGE_3    MSM_GPIO1_REG(0x68)
+#define MSM_GPIO_INT_EDGE_4    MSM_GPIO1_REG(0x6C)
+#define MSM_GPIO_INT_EDGE_5    MSM_GPIO1_REG(0xC0)
+#define MSM_GPIO_INT_EDGE_6    MSM_GPIO1_REG(0xD0)
+#define MSM_GPIO_INT_EDGE_7    MSM_GPIO1_REG(0x240)
+
+/* same pin map as above, 1=positive 0=negative */
+#define MSM_GPIO_INT_POS_0     MSM_GPIO1_REG(0x70)
+#define MSM_GPIO_INT_POS_1     MSM_GPIO2_REG(0x58)
+#define MSM_GPIO_INT_POS_2     MSM_GPIO1_REG(0x74)
+#define MSM_GPIO_INT_POS_3     MSM_GPIO1_REG(0x78)
+#define MSM_GPIO_INT_POS_4     MSM_GPIO1_REG(0x7C)
+#define MSM_GPIO_INT_POS_5     MSM_GPIO1_REG(0xBC)
+#define MSM_GPIO_INT_POS_6     MSM_GPIO1_REG(0xD4)
+#define MSM_GPIO_INT_POS_7     MSM_GPIO1_REG(0x228)
+
+/* same pin map as above, interrupt enable */
+#define MSM_GPIO_INT_EN_0      MSM_GPIO1_REG(0x80)
+#define MSM_GPIO_INT_EN_1      MSM_GPIO2_REG(0x60)
+#define MSM_GPIO_INT_EN_2      MSM_GPIO1_REG(0x84)
+#define MSM_GPIO_INT_EN_3      MSM_GPIO1_REG(0x88)
+#define MSM_GPIO_INT_EN_4      MSM_GPIO1_REG(0x8C)
+#define MSM_GPIO_INT_EN_5      MSM_GPIO1_REG(0xB8)
+#define MSM_GPIO_INT_EN_6      MSM_GPIO1_REG(0xD8)
+#define MSM_GPIO_INT_EN_7      MSM_GPIO1_REG(0x22C)
+
+/* same pin map as above, write 1 to clear interrupt */
+#define MSM_GPIO_INT_CLEAR_0   MSM_GPIO1_REG(0x90)
+#define MSM_GPIO_INT_CLEAR_1   MSM_GPIO2_REG(0x68)
+#define MSM_GPIO_INT_CLEAR_2   MSM_GPIO1_REG(0x94)
+#define MSM_GPIO_INT_CLEAR_3   MSM_GPIO1_REG(0x98)
+#define MSM_GPIO_INT_CLEAR_4   MSM_GPIO1_REG(0x9C)
+#define MSM_GPIO_INT_CLEAR_5   MSM_GPIO1_REG(0xB4)
+#define MSM_GPIO_INT_CLEAR_6   MSM_GPIO1_REG(0xDC)
+#define MSM_GPIO_INT_CLEAR_7   MSM_GPIO1_REG(0x230)
+
+/* same pin map as above, 1=interrupt pending */
+#define MSM_GPIO_INT_STATUS_0  MSM_GPIO1_REG(0xA0)
+#define MSM_GPIO_INT_STATUS_1  MSM_GPIO2_REG(0x70)
+#define MSM_GPIO_INT_STATUS_2  MSM_GPIO1_REG(0xA4)
+#define MSM_GPIO_INT_STATUS_3  MSM_GPIO1_REG(0xA8)
+#define MSM_GPIO_INT_STATUS_4  MSM_GPIO1_REG(0xAC)
+#define MSM_GPIO_INT_STATUS_5  MSM_GPIO1_REG(0xB0)
+#define MSM_GPIO_INT_STATUS_6  MSM_GPIO1_REG(0xE0)
+#define MSM_GPIO_INT_STATUS_7  MSM_GPIO1_REG(0x234)
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-msm/gpiomux-7x30.c b/arch/arm/mach-msm/gpiomux-7x30.c
new file mode 100644
index 000000000000..6ce41c5241a5
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux-7x30.c
@@ -0,0 +1,38 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#include "gpiomux.h"
+
+struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
+#ifdef CONFIG_SERIAL_MSM_CONSOLE
+        [49] = { /* UART2 RFR */
+                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
+                             GPIOMUX_FUNC_2 | GPIOMUX_VALID,
+        },
+        [50] = { /* UART2 CTS */
+                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
+                             GPIOMUX_FUNC_2 | GPIOMUX_VALID,
+        },
+        [51] = { /* UART2 RX */
+                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
+                             GPIOMUX_FUNC_2 | GPIOMUX_VALID,
+        },
+        [52] = { /* UART2 TX */
+                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
+                             GPIOMUX_FUNC_2 | GPIOMUX_VALID,
+        },
+#endif
+};
diff --git a/arch/arm/mach-msm/gpiomux-8x50.c b/arch/arm/mach-msm/gpiomux-8x50.c
new file mode 100644
index 000000000000..4406e0f4ae95
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux-8x50.c
@@ -0,0 +1,28 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#include "gpiomux.h"
+
+struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
+        [86] = { /* UART3 RX */
+                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
+                             GPIOMUX_FUNC_1 | GPIOMUX_VALID,
+        },
+        [87] = { /* UART3 TX */
+                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
+                             GPIOMUX_FUNC_1 | GPIOMUX_VALID,
+        },
+};
diff --git a/arch/arm/mach-msm/gpiomux-8x60.c b/arch/arm/mach-msm/gpiomux-8x60.c
new file mode 100644
index 000000000000..7b380b31bd0e
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux-8x60.c
@@ -0,0 +1,19 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#include "gpiomux.h"
+
+struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {};
diff --git a/arch/arm/mach-msm/gpiomux-v1.c b/arch/arm/mach-msm/gpiomux-v1.c
new file mode 100644
index 000000000000..27de2abd7144
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux-v1.c
@@ -0,0 +1,33 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#include <linux/kernel.h>
+#include "gpiomux.h"
+#include "proc_comm.h"
+
+void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val)
+{
+        unsigned tlmm_config  = (val & ~GPIOMUX_CTL_MASK) |
+                                ((gpio & 0x3ff) << 4);
+        unsigned tlmm_disable = 0;
+        int rc;
+
+        rc = msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX,
+                           &tlmm_config, &tlmm_disable);
+        if (rc)
+                pr_err("%s: unexpected proc_comm failure %d: %08x %08x\n",
+                       __func__, rc, tlmm_config, tlmm_disable);
+}
diff --git a/arch/arm/mach-msm/gpiomux-v1.h b/arch/arm/mach-msm/gpiomux-v1.h
new file mode 100644
index 000000000000..71d86feba450
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux-v1.h
@@ -0,0 +1,67 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_V1_H
+#define __ARCH_ARM_MACH_MSM_GPIOMUX_V1_H
+
+#if defined(CONFIG_ARCH_MSM7X30)
+#define GPIOMUX_NGPIOS 182
+#elif defined(CONFIG_ARCH_QSD8X50)
+#define GPIOMUX_NGPIOS 165
+#else
+#define GPIOMUX_NGPIOS 133
+#endif
+
+typedef u32 gpiomux_config_t;
+
+enum {
+        GPIOMUX_DRV_2MA  = 0UL << 17,
+        GPIOMUX_DRV_4MA  = 1UL << 17,
+        GPIOMUX_DRV_6MA  = 2UL << 17,
+        GPIOMUX_DRV_8MA  = 3UL << 17,
+        GPIOMUX_DRV_10MA = 4UL << 17,
+        GPIOMUX_DRV_12MA = 5UL << 17,
+        GPIOMUX_DRV_14MA = 6UL << 17,
+        GPIOMUX_DRV_16MA = 7UL << 17,
+};
+
+enum {
+        GPIOMUX_FUNC_GPIO = 0UL,
+        GPIOMUX_FUNC_1    = 1UL,
+        GPIOMUX_FUNC_2    = 2UL,
+        GPIOMUX_FUNC_3    = 3UL,
+        GPIOMUX_FUNC_4    = 4UL,
+        GPIOMUX_FUNC_5    = 5UL,
+        GPIOMUX_FUNC_6    = 6UL,
+        GPIOMUX_FUNC_7    = 7UL,
+        GPIOMUX_FUNC_8    = 8UL,
+        GPIOMUX_FUNC_9    = 9UL,
+        GPIOMUX_FUNC_A    = 10UL,
+        GPIOMUX_FUNC_B    = 11UL,
+        GPIOMUX_FUNC_C    = 12UL,
+        GPIOMUX_FUNC_D    = 13UL,
+        GPIOMUX_FUNC_E    = 14UL,
+        GPIOMUX_FUNC_F    = 15UL,
+};
+
+enum {
+        GPIOMUX_PULL_NONE   = 0UL << 15,
+        GPIOMUX_PULL_DOWN   = 1UL << 15,
+        GPIOMUX_PULL_KEEPER = 2UL << 15,
+        GPIOMUX_PULL_UP     = 3UL << 15,
+};
+
+#endif
diff --git a/arch/arm/mach-msm/gpiomux-v2.c b/arch/arm/mach-msm/gpiomux-v2.c
new file mode 100644
index 000000000000..273396d2b127
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux-v2.c
@@ -0,0 +1,25 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#include <linux/io.h>
+#include <mach/msm_iomap.h>
+#include "gpiomux.h"
+
+void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val)
+{
+        writel(val & ~GPIOMUX_CTL_MASK,
+               MSM_TLMM_BASE + 0x1000 + (0x10 * gpio));
+}
diff --git a/arch/arm/mach-msm/gpiomux-v2.h b/arch/arm/mach-msm/gpiomux-v2.h
new file mode 100644
index 000000000000..3bf10e7f0381
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux-v2.h
@@ -0,0 +1,61 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_V2_H
+#define __ARCH_ARM_MACH_MSM_GPIOMUX_V2_H
+
+#define GPIOMUX_NGPIOS 173
+
+typedef u16 gpiomux_config_t;
+
+enum {
+        GPIOMUX_DRV_2MA  = 0UL << 6,
+        GPIOMUX_DRV_4MA  = 1UL << 6,
+        GPIOMUX_DRV_6MA  = 2UL << 6,
+        GPIOMUX_DRV_8MA  = 3UL << 6,
+        GPIOMUX_DRV_10MA = 4UL << 6,
+        GPIOMUX_DRV_12MA = 5UL << 6,
+        GPIOMUX_DRV_14MA = 6UL << 6,
+        GPIOMUX_DRV_16MA = 7UL << 6,
+};
+
+enum {
+        GPIOMUX_FUNC_GPIO = 0UL  << 2,
+        GPIOMUX_FUNC_1    = 1UL  << 2,
+        GPIOMUX_FUNC_2    = 2UL  << 2,
+        GPIOMUX_FUNC_3    = 3UL  << 2,
+        GPIOMUX_FUNC_4    = 4UL  << 2,
+        GPIOMUX_FUNC_5    = 5UL  << 2,
+        GPIOMUX_FUNC_6    = 6UL  << 2,
+        GPIOMUX_FUNC_7    = 7UL  << 2,
+        GPIOMUX_FUNC_8    = 8UL  << 2,
+        GPIOMUX_FUNC_9    = 9UL  << 2,
+        GPIOMUX_FUNC_A    = 10UL << 2,
+        GPIOMUX_FUNC_B    = 11UL << 2,
+        GPIOMUX_FUNC_C    = 12UL << 2,
+        GPIOMUX_FUNC_D    = 13UL << 2,
+        GPIOMUX_FUNC_E    = 14UL << 2,
+        GPIOMUX_FUNC_F    = 15UL << 2,
+};
+
+enum {
+        GPIOMUX_PULL_NONE   = 0UL,
+        GPIOMUX_PULL_DOWN   = 1UL,
+        GPIOMUX_PULL_KEEPER = 2UL,
+        GPIOMUX_PULL_UP     = 3UL,
+};
+
+#endif
diff --git a/arch/arm/mach-msm/gpiomux.c b/arch/arm/mach-msm/gpiomux.c
new file mode 100644
index 000000000000..53af21abd155
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux.c
@@ -0,0 +1,96 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include "gpiomux.h"
+
+static DEFINE_SPINLOCK(gpiomux_lock);
+
+int msm_gpiomux_write(unsigned gpio,
+                      gpiomux_config_t active,
+                      gpiomux_config_t suspended)
+{
+        struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio;
+        unsigned long irq_flags;
+        gpiomux_config_t setting;
+
+        if (gpio >= GPIOMUX_NGPIOS)
+                return -EINVAL;
+
+        spin_lock_irqsave(&gpiomux_lock, irq_flags);
+
+        if (active & GPIOMUX_VALID)
+                cfg->active = active;
+
+        if (suspended & GPIOMUX_VALID)
+                cfg->suspended = suspended;
+
+        setting = cfg->ref ? active : suspended;
+        if (setting & GPIOMUX_VALID)
+                __msm_gpiomux_write(gpio, setting);
+
+        spin_unlock_irqrestore(&gpiomux_lock, irq_flags);
+        return 0;
+}
+EXPORT_SYMBOL(msm_gpiomux_write);
+
+int msm_gpiomux_get(unsigned gpio)
+{
+        struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio;
+        unsigned long irq_flags;
+
+        if (gpio >= GPIOMUX_NGPIOS)
+                return -EINVAL;
+
+        spin_lock_irqsave(&gpiomux_lock, irq_flags);
+        if (cfg->ref++ == 0 && cfg->active & GPIOMUX_VALID)
+                __msm_gpiomux_write(gpio, cfg->active);
+        spin_unlock_irqrestore(&gpiomux_lock, irq_flags);
+        return 0;
+}
+EXPORT_SYMBOL(msm_gpiomux_get);
+
+int msm_gpiomux_put(unsigned gpio)
+{
+        struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio;
+        unsigned long irq_flags;
+
+        if (gpio >= GPIOMUX_NGPIOS)
+                return -EINVAL;
+
+        spin_lock_irqsave(&gpiomux_lock, irq_flags);
+        BUG_ON(cfg->ref == 0);
+        if (--cfg->ref == 0 && cfg->suspended & GPIOMUX_VALID)
+                __msm_gpiomux_write(gpio, cfg->suspended);
+        spin_unlock_irqrestore(&gpiomux_lock, irq_flags);
+        return 0;
+}
+EXPORT_SYMBOL(msm_gpiomux_put);
+
+static int __init gpiomux_init(void)
+{
+        unsigned n;
+
+        for (n = 0; n < GPIOMUX_NGPIOS; ++n) {
+                msm_gpiomux_configs[n].ref = 0;
+                if (!(msm_gpiomux_configs[n].suspended & GPIOMUX_VALID))
+                        continue;
+                __msm_gpiomux_write(n, msm_gpiomux_configs[n].suspended);
+        }
+        return 0;
+}
+postcore_initcall(gpiomux_init);
diff --git a/arch/arm/mach-msm/gpiomux.h b/arch/arm/mach-msm/gpiomux.h
new file mode 100644
index 000000000000..b178d9cb742f
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux.h
@@ -0,0 +1,114 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_H
+#define __ARCH_ARM_MACH_MSM_GPIOMUX_H
+
+#include <linux/bitops.h>
+#include <linux/errno.h>
+
+#if defined(CONFIG_MSM_V2_TLMM)
+#include "gpiomux-v2.h"
+#else
+#include "gpiomux-v1.h"
+#endif
+
+/**
+ * struct msm_gpiomux_config: gpiomux settings for one gpio line.
+ *
+ * A complete gpiomux config is the bitwise-or of a drive-strength,
+ * function, and pull.  For functions other than GPIO, the OE
+ * is hard-wired according to the function.  For GPIO mode,
+ * OE is controlled by gpiolib.
+ *
+ * Available settings differ by target; see the gpiomux header
+ * specific to your target arch for available configurations.
+ *
+ * @active: The configuration to be installed when the line is
+ * active, or its reference count is > 0.
+ * @suspended: The configuration to be installed when the line
+ * is suspended, or its reference count is 0.
+ * @ref: The reference count of the line.  For internal use of
+ * the gpiomux framework only.
+ */
+struct msm_gpiomux_config {
+        gpiomux_config_t active;
+        gpiomux_config_t suspended;
+        unsigned         ref;
+};
+
+/**
+ * @GPIOMUX_VALID:      If set, the config field contains 'good data'.
+ *                      The absence of this bit will prevent the gpiomux
+ *                      system from applying the configuration under all
+ *                      circumstances.
+ */
+enum {
+        GPIOMUX_VALID    = BIT(sizeof(gpiomux_config_t) * BITS_PER_BYTE - 1),
+        GPIOMUX_CTL_MASK = GPIOMUX_VALID,
+};
+
+#ifdef CONFIG_MSM_GPIOMUX
+
+/* Each architecture must provide its own instance of this table.
+ * To avoid having gpiomux manage any given gpio, one or both of
+ * the entries can avoid setting GPIOMUX_VALID - the absence
+ * of that flag will prevent the configuration from being applied
+ * during state transitions.
+ */
+extern struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS];
+
+/* Increment a gpio's reference count, possibly activating the line. */
+int __must_check msm_gpiomux_get(unsigned gpio);
+
+/* Decrement a gpio's reference count, possibly suspending the line. */
+int msm_gpiomux_put(unsigned gpio);
+
+/* Install a new configuration to the gpio line.  To avoid overwriting
+ * a configuration, leave the VALID bit out.
+ */
+int msm_gpiomux_write(unsigned gpio,
+                      gpiomux_config_t active,
+                      gpiomux_config_t suspended);
+
+/* Architecture-internal function for use by the framework only.
+ * This function can assume the following:
+ * - the gpio value has passed a bounds-check
+ * - the gpiomux spinlock has been obtained
+ *
+ * This function is not for public consumption.  External users
+ * should use msm_gpiomux_write.
+ */
+void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val);
+#else
+static inline int __must_check msm_gpiomux_get(unsigned gpio)
+{
+        return -ENOSYS;
+}
+
+static inline int msm_gpiomux_put(unsigned gpio)
+{
+        return -ENOSYS;
+}
+
+static inline int msm_gpiomux_write(unsigned gpio,
+                                    gpiomux_config_t active,
+                                    gpiomux_config_t suspended)
+{
+        return -ENOSYS;
+}
+#endif
+#endif
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index 5a79bcf50413..6abf4a6eadc1 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -33,6 +33,8 @@ struct msm_acpu_clock_platform_data
 
 struct clk;
 
+extern struct sys_timer msm_timer;
+
 /* common init routines for use by arch/arm/mach-msm/board-*.c */
 
 void __init msm_add_devices(void);
diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S
index 528750f307e9..238c4f132cdb 100644
--- a/arch/arm/mach-msm/include/mach/debug-macro.S
+++ b/arch/arm/mach-msm/include/mach/debug-macro.S
@@ -19,7 +19,7 @@
 #include <mach/hardware.h>
 #include <mach/msm_iomap.h>
 
-#ifdef CONFIG_MSM_DEBUG_UART
+#ifdef CONFIG_HAS_MSM_DEBUG_UART_PHYS
         .macro  addruart, rx, tmp
         @ see if the MMU is enabled and select appropriate base address
         mrc     p15, 0, \rx, c1, c0
diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h
index 00f9bbfadbe6..05583f569524 100644
--- a/arch/arm/mach-msm/include/mach/dma.h
+++ b/arch/arm/mach-msm/include/mach/dma.h
@@ -32,10 +32,18 @@ struct msm_dmov_cmd {
         void *data;
 };
 
+#ifndef CONFIG_ARCH_MSM8X60
 void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
 void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful);
 int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr);
-
+#else
+static inline
+void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd) { }
+static inline
+void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful) { }
+static inline
+int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr) { return -EIO; }
+#endif
 
 
 #define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2))
diff --git a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
new file mode 100644
index 000000000000..4dc99aa65d07
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
@@ -0,0 +1,88 @@
+/*
+ * Low-level IRQ helper macros
+ *
+ * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/hardware.h>
+#include <asm/hardware/gic.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =gic_cpu_base_addr
+        ldr     \base, [\base]
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        /*
+         * The interrupt numbering scheme is defined in the
+         * interrupt controller spec.  To wit:
+         *
+         * Migrated the code from ARM MP port to be more consistant
+         * with interrupt processing , the following still holds true
+         * however, all interrupts are treated the same regardless of
+         * if they are local IPI or PPI
+         *
+         * Interrupts 0-15 are IPI
+         * 16-31 are PPI
+         *   (16-18 are the timers)
+         * 32-1020 are global
+         * 1021-1022 are reserved
+         * 1023 is "spurious" (no interrupt)
+         *
+         * A simple read from the controller will tell us the number of the
+         * highest priority enabled interrupt.  We then just need to check
+         * whether it is in the valid range for an IRQ (0-1020 inclusive).
+         *
+         * Base ARM code assumes that the local (private) peripheral interrupts
+         * are not valid, we treat them differently, in that the privates are
+         * handled like normal shared interrupts with the exception that only
+         * one processor can register the interrupt and the handler must be
+         * the same for all processors.
+         */
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+        ldr  \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 =srcCPU,
+                                                   9-0 =int # */
+
+        bic     \irqnr, \irqstat, #0x1c00       @mask src
+        cmp     \irqnr, #15
+        ldr             \tmp, =1021
+        cmpcc   \irqnr, \irqnr
+        cmpne   \irqnr, \tmp
+        cmpcs   \irqnr, \irqnr
+
+        .endm
+
+        /* We assume that irqstat (the raw value of the IRQ acknowledge
+         * register) is preserved from the macro above.
+         * If there is an IPI, we immediately signal end of interrupt on the
+         * controller, since this requires the original irqstat value which
+         * we won't easily be able to recreate later.
+         */
+        .macro test_for_ipi, irqnr, irqstat, base, tmp
+    bic \irqnr, \irqstat, #0x1c00
+    cmp \irqnr, #16
+    strcc   \irqstat, [\base, #GIC_CPU_EOI]
+    cmpcs   \irqnr, \irqnr
+        .endm
+
+        /* As above, this assumes that irqstat and base are preserved.. */
+
+        .macro test_for_ltirq, irqnr, irqstat, base, tmp
+    bic \irqnr, \irqstat, #0x1c00
+    mov     \tmp, #0
+    cmp \irqnr, #16
+    moveq   \tmp, #1
+    streq   \irqstat, [\base, #GIC_CPU_EOI]
+    cmp \tmp, #0
+        .endm
diff --git a/arch/arm/mach-msm/include/mach/entry-macro-vic.S b/arch/arm/mach-msm/include/mach/entry-macro-vic.S
new file mode 100644
index 000000000000..70563ed11b36
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/entry-macro-vic.S
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <mach/msm_iomap.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        @ enable imprecise aborts
+        cpsie   a
+        mov     \base, #MSM_VIC_BASE
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        @ 0xD0 has irq# or old irq# if the irq has been handled
+        @ 0xD4 has irq# or -1 if none pending *but* if you just
+        @ read 0xD4 you never get the first irq for some reason
+        ldr     \irqnr, [\base, #0xD0]
+        ldr     \irqnr, [\base, #0xD4]
+        cmp     \irqnr, #0xffffffff
+        .endm
diff --git a/arch/arm/mach-msm/include/mach/entry-macro.S b/arch/arm/mach-msm/include/mach/entry-macro.S
index d2259486bcb1..b16f082eeb6f 100644
--- a/arch/arm/mach-msm/include/mach/entry-macro.S
+++ b/arch/arm/mach-msm/include/mach/entry-macro.S
@@ -1,38 +1,23 @@
-/* arch/arm/mach-msm7200/include/mach/entry-macro.S
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
  *
- * Copyright (C) 2007 Google, Inc.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
  */
 
-#include <mach/msm_iomap.h>
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  get_irqnr_preamble, base, tmp
-        @ enable imprecise aborts
-        cpsie   a
-        mov     \base, #MSM_VIC_BASE
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        @ 0xD0 has irq# or old irq# if the irq has been handled
-        @ 0xD4 has irq# or -1 if none pending *but* if you just
-        @ read 0xD4 you never get the first irq for some reason
-        ldr     \irqnr, [\base, #0xD0]
-        ldr     \irqnr, [\base, #0xD4]
-        cmp     \irqnr, #0xffffffff
-        .endm
+#if defined(CONFIG_ARM_GIC)
+#include <mach/entry-macro-qgic.S>
+#else
+#include <mach/entry-macro-vic.S>
+#endif
diff --git a/arch/arm/mach-msm/include/mach/gpio.h b/arch/arm/mach-msm/include/mach/gpio.h
index 83e47c0d5c2e..36ad50d3bfaa 100644
--- a/arch/arm/mach-msm/include/mach/gpio.h
+++ b/arch/arm/mach-msm/include/mach/gpio.h
@@ -23,127 +23,4 @@
 #define gpio_cansleep   __gpio_cansleep
 #define gpio_to_irq     __gpio_to_irq
 
-/**
- * struct msm_gpio - GPIO pin description
- * @gpio_cfg - configuration bitmap, as per gpio_tlmm_config()
- * @label - textual label
- *
- * Usually, GPIO's are operated by sets.
- * This struct accumulate all GPIO information in single source
- * and facilitete group operations provided by msm_gpios_xxx()
- */
-struct msm_gpio {
-        u32 gpio_cfg;
-        const char *label;
-};
-
-/**
- * msm_gpios_request_enable() - request and enable set of GPIOs
- *
- * Request and configure set of GPIO's
- * In case of error, all operations rolled back.
- * Return error code.
- *
- * @table: GPIO table
- * @size:  number of entries in @table
- */
-int msm_gpios_request_enable(const struct msm_gpio *table, int size);
-
-/**
- * msm_gpios_disable_free() - disable and free set of GPIOs
- *
- * @table: GPIO table
- * @size:  number of entries in @table
- */
-void msm_gpios_disable_free(const struct msm_gpio *table, int size);
-
-/**
- * msm_gpios_request() - request set of GPIOs
- * In case of error, all operations rolled back.
- * Return error code.
- *
- * @table: GPIO table
- * @size:  number of entries in @table
- */
-int msm_gpios_request(const struct msm_gpio *table, int size);
-
-/**
- * msm_gpios_free() - free set of GPIOs
- *
- * @table: GPIO table
- * @size:  number of entries in @table
- */
-void msm_gpios_free(const struct msm_gpio *table, int size);
-
-/**
- * msm_gpios_enable() - enable set of GPIOs
- * In case of error, all operations rolled back.
- * Return error code.
- *
- * @table: GPIO table
- * @size:  number of entries in @table
- */
-int msm_gpios_enable(const struct msm_gpio *table, int size);
-
-/**
- * msm_gpios_disable() - disable set of GPIOs
- *
- * @table: GPIO table
- * @size:  number of entries in @table
- */
-void msm_gpios_disable(const struct msm_gpio *table, int size);
-
-/* GPIO TLMM (Top Level Multiplexing) Definitions */
-
-/* GPIO TLMM: Function -- GPIO specific */
-
-/* GPIO TLMM: Direction */
-enum {
-        GPIO_INPUT,
-        GPIO_OUTPUT,
-};
-
-/* GPIO TLMM: Pullup/Pulldown */
-enum {
-        GPIO_NO_PULL,
-        GPIO_PULL_DOWN,
-        GPIO_KEEPER,
-        GPIO_PULL_UP,
-};
-
-/* GPIO TLMM: Drive Strength */
-enum {
-        GPIO_2MA,
-        GPIO_4MA,
-        GPIO_6MA,
-        GPIO_8MA,
-        GPIO_10MA,
-        GPIO_12MA,
-        GPIO_14MA,
-        GPIO_16MA,
-};
-
-enum {
-        GPIO_ENABLE,
-        GPIO_DISABLE,
-};
-
-#define GPIO_CFG(gpio, func, dir, pull, drvstr) \
-        ((((gpio) & 0x3FF) << 4)        |         \
-         ((func) & 0xf)                  |        \
-         (((dir) & 0x1) << 14)           |        \
-         (((pull) & 0x3) << 15)          |        \
-         (((drvstr) & 0xF) << 17))
-
-/**
- * extract GPIO pin from bit-field used for gpio_tlmm_config
- */
-#define GPIO_PIN(gpio_cfg)    (((gpio_cfg) >>  4) & 0x3ff)
-#define GPIO_FUNC(gpio_cfg)   (((gpio_cfg) >>  0) & 0xf)
-#define GPIO_DIR(gpio_cfg)    (((gpio_cfg) >> 14) & 0x1)
-#define GPIO_PULL(gpio_cfg)   (((gpio_cfg) >> 15) & 0x3)
-#define GPIO_DRVSTR(gpio_cfg) (((gpio_cfg) >> 17) & 0xf)
-
-int gpio_tlmm_config(unsigned config, unsigned disable);
-
 #endif /* __ASM_ARCH_MSM_GPIO_H */
diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
index c35b29f9ac0f..7386e732baad 100644
--- a/arch/arm/mach-msm/include/mach/io.h
+++ b/arch/arm/mach-msm/include/mach/io.h
@@ -28,6 +28,7 @@ void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int m
 
 void msm_map_qsd8x50_io(void);
 void msm_map_msm7x30_io(void);
+void msm_map_msm8x60_io(void);
 
 extern unsigned int msm_shared_ram_phys;
 
diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h
new file mode 100644
index 000000000000..218ef5732a24
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/iommu.h
@@ -0,0 +1,103 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#ifndef MSM_IOMMU_H
+#define MSM_IOMMU_H
+
+#include <linux/interrupt.h>
+
+/* Maximum number of Machine IDs that we are allowing to be mapped to the same
+ * context bank. The number of MIDs mapped to the same CB does not affect
+ * performance, but there is a practical limit on how many distinct MIDs may
+ * be present. These mappings are typically determined at design time and are
+ * not expected to change at run time.
+ */
+#define MAX_NUM_MIDS    16
+
+/**
+ * struct msm_iommu_dev - a single IOMMU hardware instance
+ * name         Human-readable name given to this IOMMU HW instance
+ * clk_rate     Rate to set for this IOMMU's clock, if applicable to this
+ *              particular IOMMU. 0 means don't set a rate.
+ *              -1 means it is an AXI clock with no valid rate
+ *
+ */
+struct msm_iommu_dev {
+        const char *name;
+        int clk_rate;
+};
+
+/**
+ * struct msm_iommu_ctx_dev - an IOMMU context bank instance
+ * name         Human-readable name given to this context bank
+ * num          Index of this context bank within the hardware
+ * mids         List of Machine IDs that are to be mapped into this context
+ *              bank, terminated by -1. The MID is a set of signals on the
+ *              AXI bus that identifies the function associated with a specific
+ *              memory request. (See ARM spec).
+ */
+struct msm_iommu_ctx_dev {
+        const char *name;
+        int num;
+        int mids[MAX_NUM_MIDS];
+};
+
+
+/**
+ * struct msm_iommu_drvdata - A single IOMMU hardware instance
+ * @base:       IOMMU config port base address (VA)
+ * @irq:        Interrupt number
+  *
+ * A msm_iommu_drvdata holds the global driver data about a single piece
+ * of an IOMMU hardware instance.
+ */
+struct msm_iommu_drvdata {
+        void __iomem *base;
+        int irq;
+};
+
+/**
+ * struct msm_iommu_ctx_drvdata - an IOMMU context bank instance
+ * @num:                Hardware context number of this context
+ * @pdev:               Platform device associated wit this HW instance
+ * @attached_elm:       List element for domains to track which devices are
+ *                      attached to them
+ *
+ * A msm_iommu_ctx_drvdata holds the driver data for a single context bank
+ * within each IOMMU hardware instance
+ */
+struct msm_iommu_ctx_drvdata {
+        int num;
+        struct platform_device *pdev;
+        struct list_head attached_elm;
+};
+
+/*
+ * Look up an IOMMU context device by its context name. NULL if none found.
+ * Useful for testing and drivers that do not yet fully have IOMMU stuff in
+ * their platform devices.
+ */
+struct device *msm_iommu_get_ctx(const char *ctx_name);
+
+/*
+ * Interrupt handler for the IOMMU context fault interrupt. Hooking the
+ * interrupt is not supported in the API yet, but this will print an error
+ * message and dump useful IOMMU registers.
+ */
+irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
new file mode 100644
index 000000000000..f9386d3a2f77
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
@@ -0,0 +1,1871 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#ifndef __ARCH_ARM_MACH_MSM_IOMMU_HW_8XXX_H
+#define __ARCH_ARM_MACH_MSM_IOMMU_HW_8XXX_H
+
+#define CTX_SHIFT 12
+
+#define GET_GLOBAL_REG(reg, base) (readl((base) + (reg)))
+#define GET_CTX_REG(reg, base, ctx) \
+                                (readl((base) + (reg) + ((ctx) << CTX_SHIFT)))
+
+#define SET_GLOBAL_REG(reg, base, val)  writel((val), ((base) + (reg)))
+
+#define SET_CTX_REG(reg, base, ctx, val) \
+                        writel((val), ((base) + (reg) + ((ctx) << CTX_SHIFT)))
+
+/* Wrappers for numbered registers */
+#define SET_GLOBAL_REG_N(b, n, r, v) SET_GLOBAL_REG(b, ((r) + (n << 2)), (v))
+#define GET_GLOBAL_REG_N(b, n, r)    GET_GLOBAL_REG(b, ((r) + (n << 2)))
+
+/* Field wrappers */
+#define GET_GLOBAL_FIELD(b, r, F)    GET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT)
+#define GET_CONTEXT_FIELD(b, c, r, F)   \
+        GET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT)
+
+#define SET_GLOBAL_FIELD(b, r, F, v) \
+        SET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT, (v))
+#define SET_CONTEXT_FIELD(b, c, r, F, v)        \
+        SET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT, (v))
+
+#define GET_FIELD(addr, mask, shift)  ((readl(addr) >> (shift)) & (mask))
+
+#define SET_FIELD(addr, mask, shift, v) \
+do { \
+        int t = readl(addr); \
+        writel((t & ~((mask) << (shift))) + (((v) & (mask)) << (shift)), addr);\
+} while (0)
+
+
+#define NUM_FL_PTE      4096
+#define NUM_SL_PTE      256
+
+/* First-level page table bits */
+#define FL_BASE_MASK            0xFFFFFC00
+#define FL_TYPE_TABLE           (1 << 0)
+#define FL_TYPE_SECT            (2 << 0)
+#define FL_SUPERSECTION         (1 << 18)
+#define FL_AP_WRITE             (1 << 10)
+#define FL_AP_READ              (1 << 11)
+#define FL_SHARED               (1 << 16)
+#define FL_OFFSET(va)           (((va) & 0xFFF00000) >> 20)
+
+/* Second-level page table bits */
+#define SL_BASE_MASK_LARGE      0xFFFF0000
+#define SL_BASE_MASK_SMALL      0xFFFFF000
+#define SL_TYPE_LARGE           (1 << 0)
+#define SL_TYPE_SMALL           (2 << 0)
+#define SL_AP0                  (1 << 4)
+#define SL_AP1                  (2 << 4)
+#define SL_SHARED               (1 << 10)
+#define SL_OFFSET(va)           (((va) & 0xFF000) >> 12)
+
+/* Global register setters / getters */
+#define SET_M2VCBR_N(b, N, v)    SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v))
+#define SET_CBACR_N(b, N, v)     SET_GLOBAL_REG_N(CBACR_N, N, (b), (v))
+#define SET_TLBRSW(b, v)         SET_GLOBAL_REG(TLBRSW, (b), (v))
+#define SET_TLBTR0(b, v)         SET_GLOBAL_REG(TLBTR0, (b), (v))
+#define SET_TLBTR1(b, v)         SET_GLOBAL_REG(TLBTR1, (b), (v))
+#define SET_TLBTR2(b, v)         SET_GLOBAL_REG(TLBTR2, (b), (v))
+#define SET_TESTBUSCR(b, v)      SET_GLOBAL_REG(TESTBUSCR, (b), (v))
+#define SET_GLOBAL_TLBIALL(b, v) SET_GLOBAL_REG(GLOBAL_TLBIALL, (b), (v))
+#define SET_TLBIVMID(b, v)       SET_GLOBAL_REG(TLBIVMID, (b), (v))
+#define SET_CR(b, v)             SET_GLOBAL_REG(CR, (b), (v))
+#define SET_EAR(b, v)            SET_GLOBAL_REG(EAR, (b), (v))
+#define SET_ESR(b, v)            SET_GLOBAL_REG(ESR, (b), (v))
+#define SET_ESRRESTORE(b, v)     SET_GLOBAL_REG(ESRRESTORE, (b), (v))
+#define SET_ESYNR0(b, v)         SET_GLOBAL_REG(ESYNR0, (b), (v))
+#define SET_ESYNR1(b, v)         SET_GLOBAL_REG(ESYNR1, (b), (v))
+#define SET_RPU_ACR(b, v)        SET_GLOBAL_REG(RPU_ACR, (b), (v))
+
+#define GET_M2VCBR_N(b, N)       GET_GLOBAL_REG_N(M2VCBR_N, N, (b))
+#define GET_CBACR_N(b, N)        GET_GLOBAL_REG_N(CBACR_N, N, (b))
+#define GET_TLBTR0(b)            GET_GLOBAL_REG(TLBTR0, (b))
+#define GET_TLBTR1(b)            GET_GLOBAL_REG(TLBTR1, (b))
+#define GET_TLBTR2(b)            GET_GLOBAL_REG(TLBTR2, (b))
+#define GET_TESTBUSCR(b)         GET_GLOBAL_REG(TESTBUSCR, (b))
+#define GET_GLOBAL_TLBIALL(b)    GET_GLOBAL_REG(GLOBAL_TLBIALL, (b))
+#define GET_TLBIVMID(b)          GET_GLOBAL_REG(TLBIVMID, (b))
+#define GET_CR(b)                GET_GLOBAL_REG(CR, (b))
+#define GET_EAR(b)               GET_GLOBAL_REG(EAR, (b))
+#define GET_ESR(b)               GET_GLOBAL_REG(ESR, (b))
+#define GET_ESRRESTORE(b)        GET_GLOBAL_REG(ESRRESTORE, (b))
+#define GET_ESYNR0(b)            GET_GLOBAL_REG(ESYNR0, (b))
+#define GET_ESYNR1(b)            GET_GLOBAL_REG(ESYNR1, (b))
+#define GET_REV(b)               GET_GLOBAL_REG(REV, (b))
+#define GET_IDR(b)               GET_GLOBAL_REG(IDR, (b))
+#define GET_RPU_ACR(b)           GET_GLOBAL_REG(RPU_ACR, (b))
+
+
+/* Context register setters/getters */
+#define SET_SCTLR(b, c, v)       SET_CTX_REG(SCTLR, (b), (c), (v))
+#define SET_ACTLR(b, c, v)       SET_CTX_REG(ACTLR, (b), (c), (v))
+#define SET_CONTEXTIDR(b, c, v)  SET_CTX_REG(CONTEXTIDR, (b), (c), (v))
+#define SET_TTBR0(b, c, v)       SET_CTX_REG(TTBR0, (b), (c), (v))
+#define SET_TTBR1(b, c, v)       SET_CTX_REG(TTBR1, (b), (c), (v))
+#define SET_TTBCR(b, c, v)       SET_CTX_REG(TTBCR, (b), (c), (v))
+#define SET_PAR(b, c, v)         SET_CTX_REG(PAR, (b), (c), (v))
+#define SET_FSR(b, c, v)         SET_CTX_REG(FSR, (b), (c), (v))
+#define SET_FSRRESTORE(b, c, v)  SET_CTX_REG(FSRRESTORE, (b), (c), (v))
+#define SET_FAR(b, c, v)         SET_CTX_REG(FAR, (b), (c), (v))
+#define SET_FSYNR0(b, c, v)      SET_CTX_REG(FSYNR0, (b), (c), (v))
+#define SET_FSYNR1(b, c, v)      SET_CTX_REG(FSYNR1, (b), (c), (v))
+#define SET_PRRR(b, c, v)        SET_CTX_REG(PRRR, (b), (c), (v))
+#define SET_NMRR(b, c, v)        SET_CTX_REG(NMRR, (b), (c), (v))
+#define SET_TLBLKCR(b, c, v)     SET_CTX_REG(TLBLCKR, (b), (c), (v))
+#define SET_V2PSR(b, c, v)       SET_CTX_REG(V2PSR, (b), (c), (v))
+#define SET_TLBFLPTER(b, c, v)   SET_CTX_REG(TLBFLPTER, (b), (c), (v))
+#define SET_TLBSLPTER(b, c, v)   SET_CTX_REG(TLBSLPTER, (b), (c), (v))
+#define SET_BFBCR(b, c, v)       SET_CTX_REG(BFBCR, (b), (c), (v))
+#define SET_CTX_TLBIALL(b, c, v) SET_CTX_REG(CTX_TLBIALL, (b), (c), (v))
+#define SET_TLBIASID(b, c, v)    SET_CTX_REG(TLBIASID, (b), (c), (v))
+#define SET_TLBIVA(b, c, v)      SET_CTX_REG(TLBIVA, (b), (c), (v))
+#define SET_TLBIVAA(b, c, v)     SET_CTX_REG(TLBIVAA, (b), (c), (v))
+#define SET_V2PPR(b, c, v)       SET_CTX_REG(V2PPR, (b), (c), (v))
+#define SET_V2PPW(b, c, v)       SET_CTX_REG(V2PPW, (b), (c), (v))
+#define SET_V2PUR(b, c, v)       SET_CTX_REG(V2PUR, (b), (c), (v))
+#define SET_V2PUW(b, c, v)       SET_CTX_REG(V2PUW, (b), (c), (v))
+#define SET_RESUME(b, c, v)      SET_CTX_REG(RESUME, (b), (c), (v))
+
+#define GET_SCTLR(b, c)          GET_CTX_REG(SCTLR, (b), (c))
+#define GET_ACTLR(b, c)          GET_CTX_REG(ACTLR, (b), (c))
+#define GET_CONTEXTIDR(b, c)     GET_CTX_REG(CONTEXTIDR, (b), (c))
+#define GET_TTBR0(b, c)          GET_CTX_REG(TTBR0, (b), (c))
+#define GET_TTBR1(b, c)          GET_CTX_REG(TTBR1, (b), (c))
+#define GET_TTBCR(b, c)          GET_CTX_REG(TTBCR, (b), (c))
+#define GET_PAR(b, c)            GET_CTX_REG(PAR, (b), (c))
+#define GET_FSR(b, c)            GET_CTX_REG(FSR, (b), (c))
+#define GET_FSRRESTORE(b, c)     GET_CTX_REG(FSRRESTORE, (b), (c))
+#define GET_FAR(b, c)            GET_CTX_REG(FAR, (b), (c))
+#define GET_FSYNR0(b, c)         GET_CTX_REG(FSYNR0, (b), (c))
+#define GET_FSYNR1(b, c)         GET_CTX_REG(FSYNR1, (b), (c))
+#define GET_PRRR(b, c)           GET_CTX_REG(PRRR, (b), (c))
+#define GET_NMRR(b, c)           GET_CTX_REG(NMRR, (b), (c))
+#define GET_TLBLCKR(b, c)        GET_CTX_REG(TLBLCKR, (b), (c))
+#define GET_V2PSR(b, c)          GET_CTX_REG(V2PSR, (b), (c))
+#define GET_TLBFLPTER(b, c)      GET_CTX_REG(TLBFLPTER, (b), (c))
+#define GET_TLBSLPTER(b, c)      GET_CTX_REG(TLBSLPTER, (b), (c))
+#define GET_BFBCR(b, c)          GET_CTX_REG(BFBCR, (b), (c))
+#define GET_CTX_TLBIALL(b, c)    GET_CTX_REG(CTX_TLBIALL, (b), (c))
+#define GET_TLBIASID(b, c)       GET_CTX_REG(TLBIASID, (b), (c))
+#define GET_TLBIVA(b, c)         GET_CTX_REG(TLBIVA, (b), (c))
+#define GET_TLBIVAA(b, c)        GET_CTX_REG(TLBIVAA, (b), (c))
+#define GET_V2PPR(b, c)          GET_CTX_REG(V2PPR, (b), (c))
+#define GET_V2PPW(b, c)          GET_CTX_REG(V2PPW, (b), (c))
+#define GET_V2PUR(b, c)          GET_CTX_REG(V2PUR, (b), (c))
+#define GET_V2PUW(b, c)          GET_CTX_REG(V2PUW, (b), (c))
+#define GET_RESUME(b, c)         GET_CTX_REG(RESUME, (b), (c))
+
+
+/* Global field setters / getters */
+/* Global Field Setters: */
+/* CBACR_N */
+#define SET_RWVMID(b, n, v)   SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWVMID, v)
+#define SET_RWE(b, n, v)      SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWE, v)
+#define SET_RWGE(b, n, v)     SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWGE, v)
+#define SET_CBVMID(b, n, v)   SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), CBVMID, v)
+#define SET_IRPTNDX(b, n, v)  SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), IRPTNDX, v)
+
+
+/* M2VCBR_N */
+#define SET_VMID(b, n, v)     SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), VMID, v)
+#define SET_CBNDX(b, n, v)    SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), CBNDX, v)
+#define SET_BYPASSD(b, n, v)  SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BYPASSD, v)
+#define SET_BPRCOSH(b, n, v)  SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCOSH, v)
+#define SET_BPRCISH(b, n, v)  SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCISH, v)
+#define SET_BPRCNSH(b, n, v)  SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCNSH, v)
+#define SET_BPSHCFG(b, n, v)  SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPSHCFG, v)
+#define SET_NSCFG(b, n, v)    SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), NSCFG, v)
+#define SET_BPMTCFG(b, n, v)  SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMTCFG, v)
+#define SET_BPMEMTYPE(b, n, v) \
+        SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMEMTYPE, v)
+
+
+/* CR */
+#define SET_RPUE(b, v)           SET_GLOBAL_FIELD(b, CR, RPUE, v)
+#define SET_RPUERE(b, v)         SET_GLOBAL_FIELD(b, CR, RPUERE, v)
+#define SET_RPUEIE(b, v)         SET_GLOBAL_FIELD(b, CR, RPUEIE, v)
+#define SET_DCDEE(b, v)          SET_GLOBAL_FIELD(b, CR, DCDEE, v)
+#define SET_CLIENTPD(b, v)       SET_GLOBAL_FIELD(b, CR, CLIENTPD, v)
+#define SET_STALLD(b, v)         SET_GLOBAL_FIELD(b, CR, STALLD, v)
+#define SET_TLBLKCRWE(b, v)      SET_GLOBAL_FIELD(b, CR, TLBLKCRWE, v)
+#define SET_CR_TLBIALLCFG(b, v)  SET_GLOBAL_FIELD(b, CR, CR_TLBIALLCFG, v)
+#define SET_TLBIVMIDCFG(b, v)    SET_GLOBAL_FIELD(b, CR, TLBIVMIDCFG, v)
+#define SET_CR_HUME(b, v)        SET_GLOBAL_FIELD(b, CR, CR_HUME, v)
+
+
+/* ESR */
+#define SET_CFG(b, v)            SET_GLOBAL_FIELD(b, ESR, CFG, v)
+#define SET_BYPASS(b, v)         SET_GLOBAL_FIELD(b, ESR, BYPASS, v)
+#define SET_ESR_MULTI(b, v)      SET_GLOBAL_FIELD(b, ESR, ESR_MULTI, v)
+
+
+/* ESYNR0 */
+#define SET_ESYNR0_AMID(b, v)    SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AMID, v)
+#define SET_ESYNR0_APID(b, v)    SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_APID, v)
+#define SET_ESYNR0_ABID(b, v)    SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ABID, v)
+#define SET_ESYNR0_AVMID(b, v)   SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AVMID, v)
+#define SET_ESYNR0_ATID(b, v)    SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ATID, v)
+
+
+/* ESYNR1 */
+#define SET_ESYNR1_AMEMTYPE(b, v) \
+                        SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AMEMTYPE, v)
+#define SET_ESYNR1_ASHARED(b, v)  SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASHARED, v)
+#define SET_ESYNR1_AINNERSHARED(b, v) \
+                        SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINNERSHARED, v)
+#define SET_ESYNR1_APRIV(b, v)   SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APRIV, v)
+#define SET_ESYNR1_APROTNS(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APROTNS, v)
+#define SET_ESYNR1_AINST(b, v)   SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINST, v)
+#define SET_ESYNR1_AWRITE(b, v)  SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AWRITE, v)
+#define SET_ESYNR1_ABURST(b, v)  SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ABURST, v)
+#define SET_ESYNR1_ALEN(b, v)    SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALEN, v)
+#define SET_ESYNR1_ASIZE(b, v)   SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASIZE, v)
+#define SET_ESYNR1_ALOCK(b, v)   SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALOCK, v)
+#define SET_ESYNR1_AOOO(b, v)    SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AOOO, v)
+#define SET_ESYNR1_AFULL(b, v)   SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AFULL, v)
+#define SET_ESYNR1_AC(b, v)      SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AC, v)
+#define SET_ESYNR1_DCD(b, v)     SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_DCD, v)
+
+
+/* TESTBUSCR */
+#define SET_TBE(b, v)            SET_GLOBAL_FIELD(b, TESTBUSCR, TBE, v)
+#define SET_SPDMBE(b, v)         SET_GLOBAL_FIELD(b, TESTBUSCR, SPDMBE, v)
+#define SET_WGSEL(b, v)          SET_GLOBAL_FIELD(b, TESTBUSCR, WGSEL, v)
+#define SET_TBLSEL(b, v)         SET_GLOBAL_FIELD(b, TESTBUSCR, TBLSEL, v)
+#define SET_TBHSEL(b, v)         SET_GLOBAL_FIELD(b, TESTBUSCR, TBHSEL, v)
+#define SET_SPDM0SEL(b, v)       SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM0SEL, v)
+#define SET_SPDM1SEL(b, v)       SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM1SEL, v)
+#define SET_SPDM2SEL(b, v)       SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM2SEL, v)
+#define SET_SPDM3SEL(b, v)       SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM3SEL, v)
+
+
+/* TLBIVMID */
+#define SET_TLBIVMID_VMID(b, v)  SET_GLOBAL_FIELD(b, TLBIVMID, TLBIVMID_VMID, v)
+
+
+/* TLBRSW */
+#define SET_TLBRSW_INDEX(b, v)   SET_GLOBAL_FIELD(b, TLBRSW, TLBRSW_INDEX, v)
+#define SET_TLBBFBS(b, v)        SET_GLOBAL_FIELD(b, TLBRSW, TLBBFBS, v)
+
+
+/* TLBTR0 */
+#define SET_PR(b, v)             SET_GLOBAL_FIELD(b, TLBTR0, PR, v)
+#define SET_PW(b, v)             SET_GLOBAL_FIELD(b, TLBTR0, PW, v)
+#define SET_UR(b, v)             SET_GLOBAL_FIELD(b, TLBTR0, UR, v)
+#define SET_UW(b, v)             SET_GLOBAL_FIELD(b, TLBTR0, UW, v)
+#define SET_XN(b, v)             SET_GLOBAL_FIELD(b, TLBTR0, XN, v)
+#define SET_NSDESC(b, v)         SET_GLOBAL_FIELD(b, TLBTR0, NSDESC, v)
+#define SET_ISH(b, v)            SET_GLOBAL_FIELD(b, TLBTR0, ISH, v)
+#define SET_SH(b, v)             SET_GLOBAL_FIELD(b, TLBTR0, SH, v)
+#define SET_MT(b, v)             SET_GLOBAL_FIELD(b, TLBTR0, MT, v)
+#define SET_DPSIZR(b, v)         SET_GLOBAL_FIELD(b, TLBTR0, DPSIZR, v)
+#define SET_DPSIZC(b, v)         SET_GLOBAL_FIELD(b, TLBTR0, DPSIZC, v)
+
+
+/* TLBTR1 */
+#define SET_TLBTR1_VMID(b, v)    SET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_VMID, v)
+#define SET_TLBTR1_PA(b, v)      SET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_PA, v)
+
+
+/* TLBTR2 */
+#define SET_TLBTR2_ASID(b, v)    SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_ASID, v)
+#define SET_TLBTR2_V(b, v)       SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_V, v)
+#define SET_TLBTR2_NSTID(b, v)   SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NSTID, v)
+#define SET_TLBTR2_NV(b, v)      SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NV, v)
+#define SET_TLBTR2_VA(b, v)      SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_VA, v)
+
+
+/* Global Field Getters */
+/* CBACR_N */
+#define GET_RWVMID(b, n)         GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWVMID)
+#define GET_RWE(b, n)            GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWE)
+#define GET_RWGE(b, n)           GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWGE)
+#define GET_CBVMID(b, n)         GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), CBVMID)
+#define GET_IRPTNDX(b, n)        GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), IRPTNDX)
+
+
+/* M2VCBR_N */
+#define GET_VMID(b, n)       GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), VMID)
+#define GET_CBNDX(b, n)      GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), CBNDX)
+#define GET_BYPASSD(b, n)    GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BYPASSD)
+#define GET_BPRCOSH(b, n)    GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCOSH)
+#define GET_BPRCISH(b, n)    GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCISH)
+#define GET_BPRCNSH(b, n)    GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCNSH)
+#define GET_BPSHCFG(b, n)    GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPSHCFG)
+#define GET_NSCFG(b, n)      GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), NSCFG)
+#define GET_BPMTCFG(b, n)    GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMTCFG)
+#define GET_BPMEMTYPE(b, n)  GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMEMTYPE)
+
+
+/* CR */
+#define GET_RPUE(b)              GET_GLOBAL_FIELD(b, CR, RPUE)
+#define GET_RPUERE(b)            GET_GLOBAL_FIELD(b, CR, RPUERE)
+#define GET_RPUEIE(b)            GET_GLOBAL_FIELD(b, CR, RPUEIE)
+#define GET_DCDEE(b)             GET_GLOBAL_FIELD(b, CR, DCDEE)
+#define GET_CLIENTPD(b)          GET_GLOBAL_FIELD(b, CR, CLIENTPD)
+#define GET_STALLD(b)            GET_GLOBAL_FIELD(b, CR, STALLD)
+#define GET_TLBLKCRWE(b)         GET_GLOBAL_FIELD(b, CR, TLBLKCRWE)
+#define GET_CR_TLBIALLCFG(b)     GET_GLOBAL_FIELD(b, CR, CR_TLBIALLCFG)
+#define GET_TLBIVMIDCFG(b)       GET_GLOBAL_FIELD(b, CR, TLBIVMIDCFG)
+#define GET_CR_HUME(b)           GET_GLOBAL_FIELD(b, CR, CR_HUME)
+
+
+/* ESR */
+#define GET_CFG(b)               GET_GLOBAL_FIELD(b, ESR, CFG)
+#define GET_BYPASS(b)            GET_GLOBAL_FIELD(b, ESR, BYPASS)
+#define GET_ESR_MULTI(b)         GET_GLOBAL_FIELD(b, ESR, ESR_MULTI)
+
+
+/* ESYNR0 */
+#define GET_ESYNR0_AMID(b)       GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AMID)
+#define GET_ESYNR0_APID(b)       GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_APID)
+#define GET_ESYNR0_ABID(b)       GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ABID)
+#define GET_ESYNR0_AVMID(b)      GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AVMID)
+#define GET_ESYNR0_ATID(b)       GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ATID)
+
+
+/* ESYNR1 */
+#define GET_ESYNR1_AMEMTYPE(b)   GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AMEMTYPE)
+#define GET_ESYNR1_ASHARED(b)    GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASHARED)
+#define GET_ESYNR1_AINNERSHARED(b) \
+                        GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINNERSHARED)
+#define GET_ESYNR1_APRIV(b)      GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APRIV)
+#define GET_ESYNR1_APROTNS(b)    GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APROTNS)
+#define GET_ESYNR1_AINST(b)      GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINST)
+#define GET_ESYNR1_AWRITE(b)     GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AWRITE)
+#define GET_ESYNR1_ABURST(b)     GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ABURST)
+#define GET_ESYNR1_ALEN(b)       GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALEN)
+#define GET_ESYNR1_ASIZE(b)      GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASIZE)
+#define GET_ESYNR1_ALOCK(b)      GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALOCK)
+#define GET_ESYNR1_AOOO(b)       GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AOOO)
+#define GET_ESYNR1_AFULL(b)      GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AFULL)
+#define GET_ESYNR1_AC(b)         GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AC)
+#define GET_ESYNR1_DCD(b)        GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_DCD)
+
+
+/* IDR */
+#define GET_NM2VCBMT(b)          GET_GLOBAL_FIELD(b, IDR, NM2VCBMT)
+#define GET_HTW(b)               GET_GLOBAL_FIELD(b, IDR, HTW)
+#define GET_HUM(b)               GET_GLOBAL_FIELD(b, IDR, HUM)
+#define GET_TLBSIZE(b)           GET_GLOBAL_FIELD(b, IDR, TLBSIZE)
+#define GET_NCB(b)               GET_GLOBAL_FIELD(b, IDR, NCB)
+#define GET_NIRPT(b)             GET_GLOBAL_FIELD(b, IDR, NIRPT)
+
+
+/* REV */
+#define GET_MAJOR(b)             GET_GLOBAL_FIELD(b, REV, MAJOR)
+#define GET_MINOR(b)             GET_GLOBAL_FIELD(b, REV, MINOR)
+
+
+/* TESTBUSCR */
+#define GET_TBE(b)               GET_GLOBAL_FIELD(b, TESTBUSCR, TBE)
+#define GET_SPDMBE(b)            GET_GLOBAL_FIELD(b, TESTBUSCR, SPDMBE)
+#define GET_WGSEL(b)             GET_GLOBAL_FIELD(b, TESTBUSCR, WGSEL)
+#define GET_TBLSEL(b)            GET_GLOBAL_FIELD(b, TESTBUSCR, TBLSEL)
+#define GET_TBHSEL(b)            GET_GLOBAL_FIELD(b, TESTBUSCR, TBHSEL)
+#define GET_SPDM0SEL(b)          GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM0SEL)
+#define GET_SPDM1SEL(b)          GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM1SEL)
+#define GET_SPDM2SEL(b)          GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM2SEL)
+#define GET_SPDM3SEL(b)          GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM3SEL)
+
+
+/* TLBIVMID */
+#define GET_TLBIVMID_VMID(b)     GET_GLOBAL_FIELD(b, TLBIVMID, TLBIVMID_VMID)
+
+
+/* TLBTR0 */
+#define GET_PR(b)                GET_GLOBAL_FIELD(b, TLBTR0, PR)
+#define GET_PW(b)                GET_GLOBAL_FIELD(b, TLBTR0, PW)
+#define GET_UR(b)                GET_GLOBAL_FIELD(b, TLBTR0, UR)
+#define GET_UW(b)                GET_GLOBAL_FIELD(b, TLBTR0, UW)
+#define GET_XN(b)                GET_GLOBAL_FIELD(b, TLBTR0, XN)
+#define GET_NSDESC(b)            GET_GLOBAL_FIELD(b, TLBTR0, NSDESC)
+#define GET_ISH(b)               GET_GLOBAL_FIELD(b, TLBTR0, ISH)
+#define GET_SH(b)                GET_GLOBAL_FIELD(b, TLBTR0, SH)
+#define GET_MT(b)                GET_GLOBAL_FIELD(b, TLBTR0, MT)
+#define GET_DPSIZR(b)            GET_GLOBAL_FIELD(b, TLBTR0, DPSIZR)
+#define GET_DPSIZC(b)            GET_GLOBAL_FIELD(b, TLBTR0, DPSIZC)
+
+
+/* TLBTR1 */
+#define GET_TLBTR1_VMID(b)       GET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_VMID)
+#define GET_TLBTR1_PA(b)         GET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_PA)
+
+
+/* TLBTR2 */
+#define GET_TLBTR2_ASID(b)       GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_ASID)
+#define GET_TLBTR2_V(b)          GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_V)
+#define GET_TLBTR2_NSTID(b)      GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NSTID)
+#define GET_TLBTR2_NV(b)         GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NV)
+#define GET_TLBTR2_VA(b)         GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_VA)
+
+
+/* Context Register setters / getters */
+/* Context Register setters */
+/* ACTLR */
+#define SET_CFERE(b, c, v)       SET_CONTEXT_FIELD(b, c, ACTLR, CFERE, v)
+#define SET_CFEIE(b, c, v)       SET_CONTEXT_FIELD(b, c, ACTLR, CFEIE, v)
+#define SET_PTSHCFG(b, c, v)     SET_CONTEXT_FIELD(b, c, ACTLR, PTSHCFG, v)
+#define SET_RCOSH(b, c, v)       SET_CONTEXT_FIELD(b, c, ACTLR, RCOSH, v)
+#define SET_RCISH(b, c, v)       SET_CONTEXT_FIELD(b, c, ACTLR, RCISH, v)
+#define SET_RCNSH(b, c, v)       SET_CONTEXT_FIELD(b, c, ACTLR, RCNSH, v)
+#define SET_PRIVCFG(b, c, v)     SET_CONTEXT_FIELD(b, c, ACTLR, PRIVCFG, v)
+#define SET_DNA(b, c, v)         SET_CONTEXT_FIELD(b, c, ACTLR, DNA, v)
+#define SET_DNLV2PA(b, c, v)     SET_CONTEXT_FIELD(b, c, ACTLR, DNLV2PA, v)
+#define SET_TLBMCFG(b, c, v)     SET_CONTEXT_FIELD(b, c, ACTLR, TLBMCFG, v)
+#define SET_CFCFG(b, c, v)       SET_CONTEXT_FIELD(b, c, ACTLR, CFCFG, v)
+#define SET_TIPCF(b, c, v)       SET_CONTEXT_FIELD(b, c, ACTLR, TIPCF, v)
+#define SET_V2PCFG(b, c, v)      SET_CONTEXT_FIELD(b, c, ACTLR, V2PCFG, v)
+#define SET_HUME(b, c, v)        SET_CONTEXT_FIELD(b, c, ACTLR, HUME, v)
+#define SET_PTMTCFG(b, c, v)     SET_CONTEXT_FIELD(b, c, ACTLR, PTMTCFG, v)
+#define SET_PTMEMTYPE(b, c, v)   SET_CONTEXT_FIELD(b, c, ACTLR, PTMEMTYPE, v)
+
+
+/* BFBCR */
+#define SET_BFBDFE(b, c, v)      SET_CONTEXT_FIELD(b, c, BFBCR, BFBDFE, v)
+#define SET_BFBSFE(b, c, v)      SET_CONTEXT_FIELD(b, c, BFBCR, BFBSFE, v)
+#define SET_SFVS(b, c, v)        SET_CONTEXT_FIELD(b, c, BFBCR, SFVS, v)
+#define SET_FLVIC(b, c, v)       SET_CONTEXT_FIELD(b, c, BFBCR, FLVIC, v)
+#define SET_SLVIC(b, c, v)       SET_CONTEXT_FIELD(b, c, BFBCR, SLVIC, v)
+
+
+/* CONTEXTIDR */
+#define SET_CONTEXTIDR_ASID(b, c, v)   \
+                SET_CONTEXT_FIELD(b, c, CONTEXTIDR, CONTEXTIDR_ASID, v)
+#define SET_CONTEXTIDR_PROCID(b, c, v) \
+                SET_CONTEXT_FIELD(b, c, CONTEXTIDR, PROCID, v)
+
+
+/* FSR */
+#define SET_TF(b, c, v)          SET_CONTEXT_FIELD(b, c, FSR, TF, v)
+#define SET_AFF(b, c, v)         SET_CONTEXT_FIELD(b, c, FSR, AFF, v)
+#define SET_APF(b, c, v)         SET_CONTEXT_FIELD(b, c, FSR, APF, v)
+#define SET_TLBMF(b, c, v)       SET_CONTEXT_FIELD(b, c, FSR, TLBMF, v)
+#define SET_HTWDEEF(b, c, v)     SET_CONTEXT_FIELD(b, c, FSR, HTWDEEF, v)
+#define SET_HTWSEEF(b, c, v)     SET_CONTEXT_FIELD(b, c, FSR, HTWSEEF, v)
+#define SET_MHF(b, c, v)         SET_CONTEXT_FIELD(b, c, FSR, MHF, v)
+#define SET_SL(b, c, v)          SET_CONTEXT_FIELD(b, c, FSR, SL, v)
+#define SET_SS(b, c, v)          SET_CONTEXT_FIELD(b, c, FSR, SS, v)
+#define SET_MULTI(b, c, v)       SET_CONTEXT_FIELD(b, c, FSR, MULTI, v)
+
+
+/* FSYNR0 */
+#define SET_AMID(b, c, v)        SET_CONTEXT_FIELD(b, c, FSYNR0, AMID, v)
+#define SET_APID(b, c, v)        SET_CONTEXT_FIELD(b, c, FSYNR0, APID, v)
+#define SET_ABID(b, c, v)        SET_CONTEXT_FIELD(b, c, FSYNR0, ABID, v)
+#define SET_ATID(b, c, v)        SET_CONTEXT_FIELD(b, c, FSYNR0, ATID, v)
+
+
+/* FSYNR1 */
+#define SET_AMEMTYPE(b, c, v)    SET_CONTEXT_FIELD(b, c, FSYNR1, AMEMTYPE, v)
+#define SET_ASHARED(b, c, v)     SET_CONTEXT_FIELD(b, c, FSYNR1, ASHARED, v)
+#define SET_AINNERSHARED(b, c, v)  \
+                                SET_CONTEXT_FIELD(b, c, FSYNR1, AINNERSHARED, v)
+#define SET_APRIV(b, c, v)       SET_CONTEXT_FIELD(b, c, FSYNR1, APRIV, v)
+#define SET_APROTNS(b, c, v)     SET_CONTEXT_FIELD(b, c, FSYNR1, APROTNS, v)
+#define SET_AINST(b, c, v)       SET_CONTEXT_FIELD(b, c, FSYNR1, AINST, v)
+#define SET_AWRITE(b, c, v)      SET_CONTEXT_FIELD(b, c, FSYNR1, AWRITE, v)
+#define SET_ABURST(b, c, v)      SET_CONTEXT_FIELD(b, c, FSYNR1, ABURST, v)
+#define SET_ALEN(b, c, v)        SET_CONTEXT_FIELD(b, c, FSYNR1, ALEN, v)
+#define SET_FSYNR1_ASIZE(b, c, v) \
+                                SET_CONTEXT_FIELD(b, c, FSYNR1, FSYNR1_ASIZE, v)
+#define SET_ALOCK(b, c, v)       SET_CONTEXT_FIELD(b, c, FSYNR1, ALOCK, v)
+#define SET_AFULL(b, c, v)       SET_CONTEXT_FIELD(b, c, FSYNR1, AFULL, v)
+
+
+/* NMRR */
+#define SET_ICPC0(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC0, v)
+#define SET_ICPC1(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC1, v)
+#define SET_ICPC2(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC2, v)
+#define SET_ICPC3(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC3, v)
+#define SET_ICPC4(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC4, v)
+#define SET_ICPC5(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC5, v)
+#define SET_ICPC6(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC6, v)
+#define SET_ICPC7(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC7, v)
+#define SET_OCPC0(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC0, v)
+#define SET_OCPC1(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC1, v)
+#define SET_OCPC2(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC2, v)
+#define SET_OCPC3(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC3, v)
+#define SET_OCPC4(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC4, v)
+#define SET_OCPC5(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC5, v)
+#define SET_OCPC6(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC6, v)
+#define SET_OCPC7(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC7, v)
+
+
+/* PAR */
+#define SET_FAULT(b, c, v)       SET_CONTEXT_FIELD(b, c, PAR, FAULT, v)
+
+#define SET_FAULT_TF(b, c, v)    SET_CONTEXT_FIELD(b, c, PAR, FAULT_TF, v)
+#define SET_FAULT_AFF(b, c, v)   SET_CONTEXT_FIELD(b, c, PAR, FAULT_AFF, v)
+#define SET_FAULT_APF(b, c, v)   SET_CONTEXT_FIELD(b, c, PAR, FAULT_APF, v)
+#define SET_FAULT_TLBMF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_TLBMF, v)
+#define SET_FAULT_HTWDEEF(b, c, v) \
+                                SET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWDEEF, v)
+#define SET_FAULT_HTWSEEF(b, c, v) \
+                                SET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWSEEF, v)
+#define SET_FAULT_MHF(b, c, v)   SET_CONTEXT_FIELD(b, c, PAR, FAULT_MHF, v)
+#define SET_FAULT_SL(b, c, v)    SET_CONTEXT_FIELD(b, c, PAR, FAULT_SL, v)
+#define SET_FAULT_SS(b, c, v)    SET_CONTEXT_FIELD(b, c, PAR, FAULT_SS, v)
+
+#define SET_NOFAULT_SS(b, c, v)  SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_SS, v)
+#define SET_NOFAULT_MT(b, c, v)  SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_MT, v)
+#define SET_NOFAULT_SH(b, c, v)  SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_SH, v)
+#define SET_NOFAULT_NS(b, c, v)  SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_NS, v)
+#define SET_NOFAULT_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_NOS, v)
+#define SET_NPFAULT_PA(b, c, v)  SET_CONTEXT_FIELD(b, c, PAR, NPFAULT_PA, v)
+
+
+/* PRRR */
+#define SET_MTC0(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC0, v)
+#define SET_MTC1(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC1, v)
+#define SET_MTC2(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC2, v)
+#define SET_MTC3(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC3, v)
+#define SET_MTC4(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC4, v)
+#define SET_MTC5(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC5, v)
+#define SET_MTC6(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC6, v)
+#define SET_MTC7(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC7, v)
+#define SET_SHDSH0(b, c, v)      SET_CONTEXT_FIELD(b, c, PRRR, SHDSH0, v)
+#define SET_SHDSH1(b, c, v)      SET_CONTEXT_FIELD(b, c, PRRR, SHDSH1, v)
+#define SET_SHNMSH0(b, c, v)     SET_CONTEXT_FIELD(b, c, PRRR, SHNMSH0, v)
+#define SET_SHNMSH1(b, c, v)     SET_CONTEXT_FIELD(b, c, PRRR, SHNMSH1, v)
+#define SET_NOS0(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS0, v)
+#define SET_NOS1(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS1, v)
+#define SET_NOS2(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS2, v)
+#define SET_NOS3(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS3, v)
+#define SET_NOS4(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS4, v)
+#define SET_NOS5(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS5, v)
+#define SET_NOS6(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS6, v)
+#define SET_NOS7(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS7, v)
+
+
+/* RESUME */
+#define SET_TNR(b, c, v)         SET_CONTEXT_FIELD(b, c, RESUME, TNR, v)
+
+
+/* SCTLR */
+#define SET_M(b, c, v)           SET_CONTEXT_FIELD(b, c, SCTLR, M, v)
+#define SET_TRE(b, c, v)         SET_CONTEXT_FIELD(b, c, SCTLR, TRE, v)
+#define SET_AFE(b, c, v)         SET_CONTEXT_FIELD(b, c, SCTLR, AFE, v)
+#define SET_HAF(b, c, v)         SET_CONTEXT_FIELD(b, c, SCTLR, HAF, v)
+#define SET_BE(b, c, v)          SET_CONTEXT_FIELD(b, c, SCTLR, BE, v)
+#define SET_AFFD(b, c, v)        SET_CONTEXT_FIELD(b, c, SCTLR, AFFD, v)
+
+
+/* TLBLKCR */
+#define SET_LKE(b, c, v)           SET_CONTEXT_FIELD(b, c, TLBLKCR, LKE, v)
+#define SET_TLBLKCR_TLBIALLCFG(b, c, v) \
+                        SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBLCKR_TLBIALLCFG, v)
+#define SET_TLBIASIDCFG(b, c, v) \
+                        SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIASIDCFG, v)
+#define SET_TLBIVAACFG(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIVAACFG, v)
+#define SET_FLOOR(b, c, v)      SET_CONTEXT_FIELD(b, c, TLBLKCR, FLOOR, v)
+#define SET_VICTIM(b, c, v)     SET_CONTEXT_FIELD(b, c, TLBLKCR, VICTIM, v)
+
+
+/* TTBCR */
+#define SET_N(b, c, v)           SET_CONTEXT_FIELD(b, c, TTBCR, N, v)
+#define SET_PD0(b, c, v)         SET_CONTEXT_FIELD(b, c, TTBCR, PD0, v)
+#define SET_PD1(b, c, v)         SET_CONTEXT_FIELD(b, c, TTBCR, PD1, v)
+
+
+/* TTBR0 */
+#define SET_TTBR0_IRGNH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNH, v)
+#define SET_TTBR0_SH(b, c, v)    SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_SH, v)
+#define SET_TTBR0_ORGN(b, c, v)  SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_ORGN, v)
+#define SET_TTBR0_NOS(b, c, v)   SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_NOS, v)
+#define SET_TTBR0_IRGNL(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNL, v)
+#define SET_TTBR0_PA(b, c, v)    SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_PA, v)
+
+
+/* TTBR1 */
+#define SET_TTBR1_IRGNH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNH, v)
+#define SET_TTBR1_SH(b, c, v)    SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_SH, v)
+#define SET_TTBR1_ORGN(b, c, v)  SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_ORGN, v)
+#define SET_TTBR1_NOS(b, c, v)   SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_NOS, v)
+#define SET_TTBR1_IRGNL(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNL, v)
+#define SET_TTBR1_PA(b, c, v)    SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_PA, v)
+
+
+/* V2PSR */
+#define SET_HIT(b, c, v)         SET_CONTEXT_FIELD(b, c, V2PSR, HIT, v)
+#define SET_INDEX(b, c, v)       SET_CONTEXT_FIELD(b, c, V2PSR, INDEX, v)
+
+
+/* V2Pxx UW UR PW PR */
+#define SET_V2PUW_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_INDEX, v)
+#define SET_V2PUW_VA(b, c, v)    SET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_VA, v)
+
+#define SET_V2PUR_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_INDEX, v)
+#define SET_V2PUR_VA(b, c, v)    SET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_VA, v)
+
+#define SET_V2PPW_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_INDEX, v)
+#define SET_V2PPW_VA(b, c, v)    SET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_VA, v)
+
+#define SET_V2PPR_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_INDEX, v)
+#define SET_V2PPR_VA(b, c, v)    SET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_VA, v)
+
+
+/* Context Register getters */
+/* ACTLR */
+#define GET_CFERE(b, c)         GET_CONTEXT_FIELD(b, c, ACTLR, CFERE)
+#define GET_CFEIE(b, c)         GET_CONTEXT_FIELD(b, c, ACTLR, CFEIE)
+#define GET_PTSHCFG(b, c)       GET_CONTEXT_FIELD(b, c, ACTLR, PTSHCFG)
+#define GET_RCOSH(b, c)         GET_CONTEXT_FIELD(b, c, ACTLR, RCOSH)
+#define GET_RCISH(b, c)         GET_CONTEXT_FIELD(b, c, ACTLR, RCISH)
+#define GET_RCNSH(b, c)         GET_CONTEXT_FIELD(b, c, ACTLR, RCNSH)
+#define GET_PRIVCFG(b, c)       GET_CONTEXT_FIELD(b, c, ACTLR, PRIVCFG)
+#define GET_DNA(b, c)           GET_CONTEXT_FIELD(b, c, ACTLR, DNA)
+#define GET_DNLV2PA(b, c)       GET_CONTEXT_FIELD(b, c, ACTLR, DNLV2PA)
+#define GET_TLBMCFG(b, c)       GET_CONTEXT_FIELD(b, c, ACTLR, TLBMCFG)
+#define GET_CFCFG(b, c)         GET_CONTEXT_FIELD(b, c, ACTLR, CFCFG)
+#define GET_TIPCF(b, c)         GET_CONTEXT_FIELD(b, c, ACTLR, TIPCF)
+#define GET_V2PCFG(b, c)        GET_CONTEXT_FIELD(b, c, ACTLR, V2PCFG)
+#define GET_HUME(b, c)          GET_CONTEXT_FIELD(b, c, ACTLR, HUME)
+#define GET_PTMTCFG(b, c)       GET_CONTEXT_FIELD(b, c, ACTLR, PTMTCFG)
+#define GET_PTMEMTYPE(b, c)     GET_CONTEXT_FIELD(b, c, ACTLR, PTMEMTYPE)
+
+/* BFBCR */
+#define GET_BFBDFE(b, c)        GET_CONTEXT_FIELD(b, c, BFBCR, BFBDFE)
+#define GET_BFBSFE(b, c)        GET_CONTEXT_FIELD(b, c, BFBCR, BFBSFE)
+#define GET_SFVS(b, c)          GET_CONTEXT_FIELD(b, c, BFBCR, SFVS)
+#define GET_FLVIC(b, c)         GET_CONTEXT_FIELD(b, c, BFBCR, FLVIC)
+#define GET_SLVIC(b, c)         GET_CONTEXT_FIELD(b, c, BFBCR, SLVIC)
+
+
+/* CONTEXTIDR */
+#define GET_CONTEXTIDR_ASID(b, c) \
+                        GET_CONTEXT_FIELD(b, c, CONTEXTIDR, CONTEXTIDR_ASID)
+#define GET_CONTEXTIDR_PROCID(b, c) GET_CONTEXT_FIELD(b, c, CONTEXTIDR, PROCID)
+
+
+/* FSR */
+#define GET_TF(b, c)            GET_CONTEXT_FIELD(b, c, FSR, TF)
+#define GET_AFF(b, c)           GET_CONTEXT_FIELD(b, c, FSR, AFF)
+#define GET_APF(b, c)           GET_CONTEXT_FIELD(b, c, FSR, APF)
+#define GET_TLBMF(b, c)         GET_CONTEXT_FIELD(b, c, FSR, TLBMF)
+#define GET_HTWDEEF(b, c)       GET_CONTEXT_FIELD(b, c, FSR, HTWDEEF)
+#define GET_HTWSEEF(b, c)       GET_CONTEXT_FIELD(b, c, FSR, HTWSEEF)
+#define GET_MHF(b, c)           GET_CONTEXT_FIELD(b, c, FSR, MHF)
+#define GET_SL(b, c)            GET_CONTEXT_FIELD(b, c, FSR, SL)
+#define GET_SS(b, c)            GET_CONTEXT_FIELD(b, c, FSR, SS)
+#define GET_MULTI(b, c)         GET_CONTEXT_FIELD(b, c, FSR, MULTI)
+
+
+/* FSYNR0 */
+#define GET_AMID(b, c)          GET_CONTEXT_FIELD(b, c, FSYNR0, AMID)
+#define GET_APID(b, c)          GET_CONTEXT_FIELD(b, c, FSYNR0, APID)
+#define GET_ABID(b, c)          GET_CONTEXT_FIELD(b, c, FSYNR0, ABID)
+#define GET_ATID(b, c)          GET_CONTEXT_FIELD(b, c, FSYNR0, ATID)
+
+
+/* FSYNR1 */
+#define GET_AMEMTYPE(b, c)      GET_CONTEXT_FIELD(b, c, FSYNR1, AMEMTYPE)
+#define GET_ASHARED(b, c)       GET_CONTEXT_FIELD(b, c, FSYNR1, ASHARED)
+#define GET_AINNERSHARED(b, c)  GET_CONTEXT_FIELD(b, c, FSYNR1, AINNERSHARED)
+#define GET_APRIV(b, c)         GET_CONTEXT_FIELD(b, c, FSYNR1, APRIV)
+#define GET_APROTNS(b, c)       GET_CONTEXT_FIELD(b, c, FSYNR1, APROTNS)
+#define GET_AINST(b, c)         GET_CONTEXT_FIELD(b, c, FSYNR1, AINST)
+#define GET_AWRITE(b, c)        GET_CONTEXT_FIELD(b, c, FSYNR1, AWRITE)
+#define GET_ABURST(b, c)        GET_CONTEXT_FIELD(b, c, FSYNR1, ABURST)
+#define GET_ALEN(b, c)          GET_CONTEXT_FIELD(b, c, FSYNR1, ALEN)
+#define GET_FSYNR1_ASIZE(b, c)  GET_CONTEXT_FIELD(b, c, FSYNR1, FSYNR1_ASIZE)
+#define GET_ALOCK(b, c)         GET_CONTEXT_FIELD(b, c, FSYNR1, ALOCK)
+#define GET_AFULL(b, c)         GET_CONTEXT_FIELD(b, c, FSYNR1, AFULL)
+
+
+/* NMRR */
+#define GET_ICPC0(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC0)
+#define GET_ICPC1(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC1)
+#define GET_ICPC2(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC2)
+#define GET_ICPC3(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC3)
+#define GET_ICPC4(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC4)
+#define GET_ICPC5(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC5)
+#define GET_ICPC6(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC6)
+#define GET_ICPC7(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC7)
+#define GET_OCPC0(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC0)
+#define GET_OCPC1(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC1)
+#define GET_OCPC2(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC2)
+#define GET_OCPC3(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC3)
+#define GET_OCPC4(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC4)
+#define GET_OCPC5(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC5)
+#define GET_OCPC6(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC6)
+#define GET_OCPC7(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC7)
+
+
+/* PAR */
+#define GET_FAULT(b, c)         GET_CONTEXT_FIELD(b, c, PAR, FAULT)
+
+#define GET_FAULT_TF(b, c)      GET_CONTEXT_FIELD(b, c, PAR, FAULT_TF)
+#define GET_FAULT_AFF(b, c)     GET_CONTEXT_FIELD(b, c, PAR, FAULT_AFF)
+#define GET_FAULT_APF(b, c)     GET_CONTEXT_FIELD(b, c, PAR, FAULT_APF)
+#define GET_FAULT_TLBMF(b, c)   GET_CONTEXT_FIELD(b, c, PAR, FAULT_TLBMF)
+#define GET_FAULT_HTWDEEF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWDEEF)
+#define GET_FAULT_HTWSEEF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWSEEF)
+#define GET_FAULT_MHF(b, c)     GET_CONTEXT_FIELD(b, c, PAR, FAULT_MHF)
+#define GET_FAULT_SL(b, c)      GET_CONTEXT_FIELD(b, c, PAR, FAULT_SL)
+#define GET_FAULT_SS(b, c)      GET_CONTEXT_FIELD(b, c, PAR, FAULT_SS)
+
+#define GET_NOFAULT_SS(b, c)    GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_SS)
+#define GET_NOFAULT_MT(b, c)    GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_MT)
+#define GET_NOFAULT_SH(b, c)    GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_SH)
+#define GET_NOFAULT_NS(b, c)    GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_NS)
+#define GET_NOFAULT_NOS(b, c)   GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_NOS)
+#define GET_NPFAULT_PA(b, c)    GET_CONTEXT_FIELD(b, c, PAR, PAR_NPFAULT_PA)
+
+
+/* PRRR */
+#define GET_MTC0(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC0)
+#define GET_MTC1(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC1)
+#define GET_MTC2(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC2)
+#define GET_MTC3(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC3)
+#define GET_MTC4(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC4)
+#define GET_MTC5(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC5)
+#define GET_MTC6(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC6)
+#define GET_MTC7(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC7)
+#define GET_SHDSH0(b, c)        GET_CONTEXT_FIELD(b, c, PRRR, SHDSH0)
+#define GET_SHDSH1(b, c)        GET_CONTEXT_FIELD(b, c, PRRR, SHDSH1)
+#define GET_SHNMSH0(b, c)       GET_CONTEXT_FIELD(b, c, PRRR, SHNMSH0)
+#define GET_SHNMSH1(b, c)       GET_CONTEXT_FIELD(b, c, PRRR, SHNMSH1)
+#define GET_NOS0(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS0)
+#define GET_NOS1(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS1)
+#define GET_NOS2(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS2)
+#define GET_NOS3(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS3)
+#define GET_NOS4(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS4)
+#define GET_NOS5(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS5)
+#define GET_NOS6(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS6)
+#define GET_NOS7(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS7)
+
+
+/* RESUME */
+#define GET_TNR(b, c)           GET_CONTEXT_FIELD(b, c, RESUME, TNR)
+
+
+/* SCTLR */
+#define GET_M(b, c)             GET_CONTEXT_FIELD(b, c, SCTLR, M)
+#define GET_TRE(b, c)           GET_CONTEXT_FIELD(b, c, SCTLR, TRE)
+#define GET_AFE(b, c)           GET_CONTEXT_FIELD(b, c, SCTLR, AFE)
+#define GET_HAF(b, c)           GET_CONTEXT_FIELD(b, c, SCTLR, HAF)
+#define GET_BE(b, c)            GET_CONTEXT_FIELD(b, c, SCTLR, BE)
+#define GET_AFFD(b, c)          GET_CONTEXT_FIELD(b, c, SCTLR, AFFD)
+
+
+/* TLBLKCR */
+#define GET_LKE(b, c)           GET_CONTEXT_FIELD(b, c, TLBLKCR, LKE)
+#define GET_TLBLCKR_TLBIALLCFG(b, c) \
+                        GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBLCKR_TLBIALLCFG)
+#define GET_TLBIASIDCFG(b, c)   GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIASIDCFG)
+#define GET_TLBIVAACFG(b, c)    GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIVAACFG)
+#define GET_FLOOR(b, c)         GET_CONTEXT_FIELD(b, c, TLBLKCR, FLOOR)
+#define GET_VICTIM(b, c)        GET_CONTEXT_FIELD(b, c, TLBLKCR, VICTIM)
+
+
+/* TTBCR */
+#define GET_N(b, c)             GET_CONTEXT_FIELD(b, c, TTBCR, N)
+#define GET_PD0(b, c)           GET_CONTEXT_FIELD(b, c, TTBCR, PD0)
+#define GET_PD1(b, c)           GET_CONTEXT_FIELD(b, c, TTBCR, PD1)
+
+
+/* TTBR0 */
+#define GET_TTBR0_IRGNH(b, c)   GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNH)
+#define GET_TTBR0_SH(b, c)      GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_SH)
+#define GET_TTBR0_ORGN(b, c)    GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_ORGN)
+#define GET_TTBR0_NOS(b, c)     GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_NOS)
+#define GET_TTBR0_IRGNL(b, c)   GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNL)
+#define GET_TTBR0_PA(b, c)      GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_PA)
+
+
+/* TTBR1 */
+#define GET_TTBR1_IRGNH(b, c)   GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNH)
+#define GET_TTBR1_SH(b, c)      GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_SH)
+#define GET_TTBR1_ORGN(b, c)    GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_ORGN)
+#define GET_TTBR1_NOS(b, c)     GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_NOS)
+#define GET_TTBR1_IRGNL(b, c)   GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNL)
+#define GET_TTBR1_PA(b, c)      GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_PA)
+
+
+/* V2PSR */
+#define GET_HIT(b, c)           GET_CONTEXT_FIELD(b, c, V2PSR, HIT)
+#define GET_INDEX(b, c)         GET_CONTEXT_FIELD(b, c, V2PSR, INDEX)
+
+
+/* V2Pxx UW UR PW PR */
+#define GET_V2PUW_INDEX(b, c)   GET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_INDEX)
+#define GET_V2PUW_VA(b, c)      GET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_VA)
+
+#define GET_V2PUR_INDEX(b, c)   GET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_INDEX)
+#define GET_V2PUR_VA(b, c)      GET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_VA)
+
+#define GET_V2PPW_INDEX(b, c)   GET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_INDEX)
+#define GET_V2PPW_VA(b, c)      GET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_VA)
+
+#define GET_V2PPR_INDEX(b, c)   GET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_INDEX)
+#define GET_V2PPR_VA(b, c)      GET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_VA)
+
+
+/* Global Registers */
+#define M2VCBR_N        (0xFF000)
+#define CBACR_N         (0xFF800)
+#define TLBRSW          (0xFFE00)
+#define TLBTR0          (0xFFE80)
+#define TLBTR1          (0xFFE84)
+#define TLBTR2          (0xFFE88)
+#define TESTBUSCR       (0xFFE8C)
+#define GLOBAL_TLBIALL  (0xFFF00)
+#define TLBIVMID        (0xFFF04)
+#define CR              (0xFFF80)
+#define EAR             (0xFFF84)
+#define ESR             (0xFFF88)
+#define ESRRESTORE      (0xFFF8C)
+#define ESYNR0          (0xFFF90)
+#define ESYNR1          (0xFFF94)
+#define REV             (0xFFFF4)
+#define IDR             (0xFFFF8)
+#define RPU_ACR         (0xFFFFC)
+
+
+/* Context Bank Registers */
+#define SCTLR           (0x000)
+#define ACTLR           (0x004)
+#define CONTEXTIDR      (0x008)
+#define TTBR0           (0x010)
+#define TTBR1           (0x014)
+#define TTBCR           (0x018)
+#define PAR             (0x01C)
+#define FSR             (0x020)
+#define FSRRESTORE      (0x024)
+#define FAR             (0x028)
+#define FSYNR0          (0x02C)
+#define FSYNR1          (0x030)
+#define PRRR            (0x034)
+#define NMRR            (0x038)
+#define TLBLCKR         (0x03C)
+#define V2PSR           (0x040)
+#define TLBFLPTER       (0x044)
+#define TLBSLPTER       (0x048)
+#define BFBCR           (0x04C)
+#define CTX_TLBIALL     (0x800)
+#define TLBIASID        (0x804)
+#define TLBIVA          (0x808)
+#define TLBIVAA         (0x80C)
+#define V2PPR           (0x810)
+#define V2PPW           (0x814)
+#define V2PUR           (0x818)
+#define V2PUW           (0x81C)
+#define RESUME          (0x820)
+
+
+/* Global Register Fields */
+/* CBACRn */
+#define RWVMID        (RWVMID_MASK       << RWVMID_SHIFT)
+#define RWE           (RWE_MASK          << RWE_SHIFT)
+#define RWGE          (RWGE_MASK         << RWGE_SHIFT)
+#define CBVMID        (CBVMID_MASK       << CBVMID_SHIFT)
+#define IRPTNDX       (IRPTNDX_MASK      << IRPTNDX_SHIFT)
+
+
+/* CR */
+#define RPUE          (RPUE_MASK          << RPUE_SHIFT)
+#define RPUERE        (RPUERE_MASK        << RPUERE_SHIFT)
+#define RPUEIE        (RPUEIE_MASK        << RPUEIE_SHIFT)
+#define DCDEE         (DCDEE_MASK         << DCDEE_SHIFT)
+#define CLIENTPD      (CLIENTPD_MASK      << CLIENTPD_SHIFT)
+#define STALLD        (STALLD_MASK        << STALLD_SHIFT)
+#define TLBLKCRWE     (TLBLKCRWE_MASK     << TLBLKCRWE_SHIFT)
+#define CR_TLBIALLCFG (CR_TLBIALLCFG_MASK << CR_TLBIALLCFG_SHIFT)
+#define TLBIVMIDCFG   (TLBIVMIDCFG_MASK   << TLBIVMIDCFG_SHIFT)
+#define CR_HUME       (CR_HUME_MASK       << CR_HUME_SHIFT)
+
+
+/* ESR */
+#define CFG           (CFG_MASK          << CFG_SHIFT)
+#define BYPASS        (BYPASS_MASK       << BYPASS_SHIFT)
+#define ESR_MULTI     (ESR_MULTI_MASK    << ESR_MULTI_SHIFT)
+
+
+/* ESYNR0 */
+#define ESYNR0_AMID   (ESYNR0_AMID_MASK  << ESYNR0_AMID_SHIFT)
+#define ESYNR0_APID   (ESYNR0_APID_MASK  << ESYNR0_APID_SHIFT)
+#define ESYNR0_ABID   (ESYNR0_ABID_MASK  << ESYNR0_ABID_SHIFT)
+#define ESYNR0_AVMID  (ESYNR0_AVMID_MASK << ESYNR0_AVMID_SHIFT)
+#define ESYNR0_ATID   (ESYNR0_ATID_MASK  << ESYNR0_ATID_SHIFT)
+
+
+/* ESYNR1 */
+#define ESYNR1_AMEMTYPE      (ESYNR1_AMEMTYPE_MASK    << ESYNR1_AMEMTYPE_SHIFT)
+#define ESYNR1_ASHARED       (ESYNR1_ASHARED_MASK     << ESYNR1_ASHARED_SHIFT)
+#define ESYNR1_AINNERSHARED  (ESYNR1_AINNERSHARED_MASK<< \
+                                                ESYNR1_AINNERSHARED_SHIFT)
+#define ESYNR1_APRIV         (ESYNR1_APRIV_MASK       << ESYNR1_APRIV_SHIFT)
+#define ESYNR1_APROTNS       (ESYNR1_APROTNS_MASK     << ESYNR1_APROTNS_SHIFT)
+#define ESYNR1_AINST         (ESYNR1_AINST_MASK       << ESYNR1_AINST_SHIFT)
+#define ESYNR1_AWRITE        (ESYNR1_AWRITE_MASK      << ESYNR1_AWRITE_SHIFT)
+#define ESYNR1_ABURST        (ESYNR1_ABURST_MASK      << ESYNR1_ABURST_SHIFT)
+#define ESYNR1_ALEN          (ESYNR1_ALEN_MASK        << ESYNR1_ALEN_SHIFT)
+#define ESYNR1_ASIZE         (ESYNR1_ASIZE_MASK       << ESYNR1_ASIZE_SHIFT)
+#define ESYNR1_ALOCK         (ESYNR1_ALOCK_MASK       << ESYNR1_ALOCK_SHIFT)
+#define ESYNR1_AOOO          (ESYNR1_AOOO_MASK        << ESYNR1_AOOO_SHIFT)
+#define ESYNR1_AFULL         (ESYNR1_AFULL_MASK       << ESYNR1_AFULL_SHIFT)
+#define ESYNR1_AC            (ESYNR1_AC_MASK          << ESYNR1_AC_SHIFT)
+#define ESYNR1_DCD           (ESYNR1_DCD_MASK         << ESYNR1_DCD_SHIFT)
+
+
+/* IDR */
+#define NM2VCBMT      (NM2VCBMT_MASK     << NM2VCBMT_SHIFT)
+#define HTW           (HTW_MASK          << HTW_SHIFT)
+#define HUM           (HUM_MASK          << HUM_SHIFT)
+#define TLBSIZE       (TLBSIZE_MASK      << TLBSIZE_SHIFT)
+#define NCB           (NCB_MASK          << NCB_SHIFT)
+#define NIRPT         (NIRPT_MASK        << NIRPT_SHIFT)
+
+
+/* M2VCBRn */
+#define VMID          (VMID_MASK         << VMID_SHIFT)
+#define CBNDX         (CBNDX_MASK        << CBNDX_SHIFT)
+#define BYPASSD       (BYPASSD_MASK      << BYPASSD_SHIFT)
+#define BPRCOSH       (BPRCOSH_MASK      << BPRCOSH_SHIFT)
+#define BPRCISH       (BPRCISH_MASK      << BPRCISH_SHIFT)
+#define BPRCNSH       (BPRCNSH_MASK      << BPRCNSH_SHIFT)
+#define BPSHCFG       (BPSHCFG_MASK      << BPSHCFG_SHIFT)
+#define NSCFG         (NSCFG_MASK        << NSCFG_SHIFT)
+#define BPMTCFG       (BPMTCFG_MASK      << BPMTCFG_SHIFT)
+#define BPMEMTYPE     (BPMEMTYPE_MASK    << BPMEMTYPE_SHIFT)
+
+
+/* REV */
+#define IDR_MINOR     (MINOR_MASK        << MINOR_SHIFT)
+#define IDR_MAJOR     (MAJOR_MASK        << MAJOR_SHIFT)
+
+
+/* TESTBUSCR */
+#define TBE           (TBE_MASK          << TBE_SHIFT)
+#define SPDMBE        (SPDMBE_MASK       << SPDMBE_SHIFT)
+#define WGSEL         (WGSEL_MASK        << WGSEL_SHIFT)
+#define TBLSEL        (TBLSEL_MASK       << TBLSEL_SHIFT)
+#define TBHSEL        (TBHSEL_MASK       << TBHSEL_SHIFT)
+#define SPDM0SEL      (SPDM0SEL_MASK     << SPDM0SEL_SHIFT)
+#define SPDM1SEL      (SPDM1SEL_MASK     << SPDM1SEL_SHIFT)
+#define SPDM2SEL      (SPDM2SEL_MASK     << SPDM2SEL_SHIFT)
+#define SPDM3SEL      (SPDM3SEL_MASK     << SPDM3SEL_SHIFT)
+
+
+/* TLBIVMID */
+#define TLBIVMID_VMID (TLBIVMID_VMID_MASK << TLBIVMID_VMID_SHIFT)
+
+
+/* TLBRSW */
+#define TLBRSW_INDEX  (TLBRSW_INDEX_MASK << TLBRSW_INDEX_SHIFT)
+#define TLBBFBS       (TLBBFBS_MASK      << TLBBFBS_SHIFT)
+
+
+/* TLBTR0 */
+#define PR            (PR_MASK           << PR_SHIFT)
+#define PW            (PW_MASK           << PW_SHIFT)
+#define UR            (UR_MASK           << UR_SHIFT)
+#define UW            (UW_MASK           << UW_SHIFT)
+#define XN            (XN_MASK           << XN_SHIFT)
+#define NSDESC        (NSDESC_MASK       << NSDESC_SHIFT)
+#define ISH           (ISH_MASK          << ISH_SHIFT)
+#define SH            (SH_MASK           << SH_SHIFT)
+#define MT            (MT_MASK           << MT_SHIFT)
+#define DPSIZR        (DPSIZR_MASK       << DPSIZR_SHIFT)
+#define DPSIZC        (DPSIZC_MASK       << DPSIZC_SHIFT)
+
+
+/* TLBTR1 */
+#define TLBTR1_VMID   (TLBTR1_VMID_MASK  << TLBTR1_VMID_SHIFT)
+#define TLBTR1_PA     (TLBTR1_PA_MASK    << TLBTR1_PA_SHIFT)
+
+
+/* TLBTR2 */
+#define TLBTR2_ASID   (TLBTR2_ASID_MASK  << TLBTR2_ASID_SHIFT)
+#define TLBTR2_V      (TLBTR2_V_MASK     << TLBTR2_V_SHIFT)
+#define TLBTR2_NSTID  (TLBTR2_NSTID_MASK << TLBTR2_NSTID_SHIFT)
+#define TLBTR2_NV     (TLBTR2_NV_MASK    << TLBTR2_NV_SHIFT)
+#define TLBTR2_VA     (TLBTR2_VA_MASK    << TLBTR2_VA_SHIFT)
+
+
+/* Context Register Fields */
+/* ACTLR */
+#define CFERE              (CFERE_MASK              << CFERE_SHIFT)
+#define CFEIE              (CFEIE_MASK              << CFEIE_SHIFT)
+#define PTSHCFG            (PTSHCFG_MASK            << PTSHCFG_SHIFT)
+#define RCOSH              (RCOSH_MASK              << RCOSH_SHIFT)
+#define RCISH              (RCISH_MASK              << RCISH_SHIFT)
+#define RCNSH              (RCNSH_MASK              << RCNSH_SHIFT)
+#define PRIVCFG            (PRIVCFG_MASK            << PRIVCFG_SHIFT)
+#define DNA                (DNA_MASK                << DNA_SHIFT)
+#define DNLV2PA            (DNLV2PA_MASK            << DNLV2PA_SHIFT)
+#define TLBMCFG            (TLBMCFG_MASK            << TLBMCFG_SHIFT)
+#define CFCFG              (CFCFG_MASK              << CFCFG_SHIFT)
+#define TIPCF              (TIPCF_MASK              << TIPCF_SHIFT)
+#define V2PCFG             (V2PCFG_MASK             << V2PCFG_SHIFT)
+#define HUME               (HUME_MASK               << HUME_SHIFT)
+#define PTMTCFG            (PTMTCFG_MASK            << PTMTCFG_SHIFT)
+#define PTMEMTYPE          (PTMEMTYPE_MASK          << PTMEMTYPE_SHIFT)
+
+
+/* BFBCR */
+#define BFBDFE             (BFBDFE_MASK             << BFBDFE_SHIFT)
+#define BFBSFE             (BFBSFE_MASK             << BFBSFE_SHIFT)
+#define SFVS               (SFVS_MASK               << SFVS_SHIFT)
+#define FLVIC              (FLVIC_MASK              << FLVIC_SHIFT)
+#define SLVIC              (SLVIC_MASK              << SLVIC_SHIFT)
+
+
+/* CONTEXTIDR */
+#define CONTEXTIDR_ASID    (CONTEXTIDR_ASID_MASK    << CONTEXTIDR_ASID_SHIFT)
+#define PROCID             (PROCID_MASK             << PROCID_SHIFT)
+
+
+/* FSR */
+#define TF                 (TF_MASK                 << TF_SHIFT)
+#define AFF                (AFF_MASK                << AFF_SHIFT)
+#define APF                (APF_MASK                << APF_SHIFT)
+#define TLBMF              (TLBMF_MASK              << TLBMF_SHIFT)
+#define HTWDEEF            (HTWDEEF_MASK            << HTWDEEF_SHIFT)
+#define HTWSEEF            (HTWSEEF_MASK            << HTWSEEF_SHIFT)
+#define MHF                (MHF_MASK                << MHF_SHIFT)
+#define SL                 (SL_MASK                 << SL_SHIFT)
+#define SS                 (SS_MASK                 << SS_SHIFT)
+#define MULTI              (MULTI_MASK              << MULTI_SHIFT)
+
+
+/* FSYNR0 */
+#define AMID               (AMID_MASK               << AMID_SHIFT)
+#define APID               (APID_MASK               << APID_SHIFT)
+#define ABID               (ABID_MASK               << ABID_SHIFT)
+#define ATID               (ATID_MASK               << ATID_SHIFT)
+
+
+/* FSYNR1 */
+#define AMEMTYPE           (AMEMTYPE_MASK           << AMEMTYPE_SHIFT)
+#define ASHARED            (ASHARED_MASK            << ASHARED_SHIFT)
+#define AINNERSHARED       (AINNERSHARED_MASK       << AINNERSHARED_SHIFT)
+#define APRIV              (APRIV_MASK              << APRIV_SHIFT)
+#define APROTNS            (APROTNS_MASK            << APROTNS_SHIFT)
+#define AINST              (AINST_MASK              << AINST_SHIFT)
+#define AWRITE             (AWRITE_MASK             << AWRITE_SHIFT)
+#define ABURST             (ABURST_MASK             << ABURST_SHIFT)
+#define ALEN               (ALEN_MASK               << ALEN_SHIFT)
+#define FSYNR1_ASIZE       (FSYNR1_ASIZE_MASK       << FSYNR1_ASIZE_SHIFT)
+#define ALOCK              (ALOCK_MASK              << ALOCK_SHIFT)
+#define AFULL              (AFULL_MASK              << AFULL_SHIFT)
+
+
+/* NMRR */
+#define ICPC0              (ICPC0_MASK              << ICPC0_SHIFT)
+#define ICPC1              (ICPC1_MASK              << ICPC1_SHIFT)
+#define ICPC2              (ICPC2_MASK              << ICPC2_SHIFT)
+#define ICPC3              (ICPC3_MASK              << ICPC3_SHIFT)
+#define ICPC4              (ICPC4_MASK              << ICPC4_SHIFT)
+#define ICPC5              (ICPC5_MASK              << ICPC5_SHIFT)
+#define ICPC6              (ICPC6_MASK              << ICPC6_SHIFT)
+#define ICPC7              (ICPC7_MASK              << ICPC7_SHIFT)
+#define OCPC0              (OCPC0_MASK              << OCPC0_SHIFT)
+#define OCPC1              (OCPC1_MASK              << OCPC1_SHIFT)
+#define OCPC2              (OCPC2_MASK              << OCPC2_SHIFT)
+#define OCPC3              (OCPC3_MASK              << OCPC3_SHIFT)
+#define OCPC4              (OCPC4_MASK              << OCPC4_SHIFT)
+#define OCPC5              (OCPC5_MASK              << OCPC5_SHIFT)
+#define OCPC6              (OCPC6_MASK              << OCPC6_SHIFT)
+#define OCPC7              (OCPC7_MASK              << OCPC7_SHIFT)
+
+
+/* PAR */
+#define FAULT              (FAULT_MASK              << FAULT_SHIFT)
+/* If a fault is present, these are the
+same as the fault fields in the FAR */
+#define FAULT_TF           (FAULT_TF_MASK           << FAULT_TF_SHIFT)
+#define FAULT_AFF          (FAULT_AFF_MASK          << FAULT_AFF_SHIFT)
+#define FAULT_APF          (FAULT_APF_MASK          << FAULT_APF_SHIFT)
+#define FAULT_TLBMF        (FAULT_TLBMF_MASK        << FAULT_TLBMF_SHIFT)
+#define FAULT_HTWDEEF      (FAULT_HTWDEEF_MASK      << FAULT_HTWDEEF_SHIFT)
+#define FAULT_HTWSEEF      (FAULT_HTWSEEF_MASK      << FAULT_HTWSEEF_SHIFT)
+#define FAULT_MHF          (FAULT_MHF_MASK          << FAULT_MHF_SHIFT)
+#define FAULT_SL           (FAULT_SL_MASK           << FAULT_SL_SHIFT)
+#define FAULT_SS           (FAULT_SS_MASK           << FAULT_SS_SHIFT)
+
+/* If NO fault is present, the following fields are in effect */
+/* (FAULT remains as before) */
+#define PAR_NOFAULT_SS     (PAR_NOFAULT_SS_MASK     << PAR_NOFAULT_SS_SHIFT)
+#define PAR_NOFAULT_MT     (PAR_NOFAULT_MT_MASK     << PAR_NOFAULT_MT_SHIFT)
+#define PAR_NOFAULT_SH     (PAR_NOFAULT_SH_MASK     << PAR_NOFAULT_SH_SHIFT)
+#define PAR_NOFAULT_NS     (PAR_NOFAULT_NS_MASK     << PAR_NOFAULT_NS_SHIFT)
+#define PAR_NOFAULT_NOS    (PAR_NOFAULT_NOS_MASK    << PAR_NOFAULT_NOS_SHIFT)
+#define PAR_NPFAULT_PA     (PAR_NPFAULT_PA_MASK     << PAR_NPFAULT_PA_SHIFT)
+
+
+/* PRRR */
+#define MTC0               (MTC0_MASK               << MTC0_SHIFT)
+#define MTC1               (MTC1_MASK               << MTC1_SHIFT)
+#define MTC2               (MTC2_MASK               << MTC2_SHIFT)
+#define MTC3               (MTC3_MASK               << MTC3_SHIFT)
+#define MTC4               (MTC4_MASK               << MTC4_SHIFT)
+#define MTC5               (MTC5_MASK               << MTC5_SHIFT)
+#define MTC6               (MTC6_MASK               << MTC6_SHIFT)
+#define MTC7               (MTC7_MASK               << MTC7_SHIFT)
+#define SHDSH0             (SHDSH0_MASK             << SHDSH0_SHIFT)
+#define SHDSH1             (SHDSH1_MASK             << SHDSH1_SHIFT)
+#define SHNMSH0            (SHNMSH0_MASK            << SHNMSH0_SHIFT)
+#define SHNMSH1            (SHNMSH1_MASK            << SHNMSH1_SHIFT)
+#define NOS0               (NOS0_MASK               << NOS0_SHIFT)
+#define NOS1               (NOS1_MASK               << NOS1_SHIFT)
+#define NOS2               (NOS2_MASK               << NOS2_SHIFT)
+#define NOS3               (NOS3_MASK               << NOS3_SHIFT)
+#define NOS4               (NOS4_MASK               << NOS4_SHIFT)
+#define NOS5               (NOS5_MASK               << NOS5_SHIFT)
+#define NOS6               (NOS6_MASK               << NOS6_SHIFT)
+#define NOS7               (NOS7_MASK               << NOS7_SHIFT)
+
+
+/* RESUME */
+#define TNR                (TNR_MASK                << TNR_SHIFT)
+
+
+/* SCTLR */
+#define M                  (M_MASK                  << M_SHIFT)
+#define TRE                (TRE_MASK                << TRE_SHIFT)
+#define AFE                (AFE_MASK                << AFE_SHIFT)
+#define HAF                (HAF_MASK                << HAF_SHIFT)
+#define BE                 (BE_MASK                 << BE_SHIFT)
+#define AFFD               (AFFD_MASK               << AFFD_SHIFT)
+
+
+/* TLBIASID */
+#define TLBIASID_ASID      (TLBIASID_ASID_MASK      << TLBIASID_ASID_SHIFT)
+
+
+/* TLBIVA */
+#define TLBIVA_ASID        (TLBIVA_ASID_MASK        << TLBIVA_ASID_SHIFT)
+#define TLBIVA_VA          (TLBIVA_VA_MASK          << TLBIVA_VA_SHIFT)
+
+
+/* TLBIVAA */
+#define TLBIVAA_VA         (TLBIVAA_VA_MASK         << TLBIVAA_VA_SHIFT)
+
+
+/* TLBLCKR */
+#define LKE                (LKE_MASK                << LKE_SHIFT)
+#define TLBLCKR_TLBIALLCFG (TLBLCKR_TLBIALLCFG_MASK<<TLBLCKR_TLBIALLCFG_SHIFT)
+#define TLBIASIDCFG        (TLBIASIDCFG_MASK        << TLBIASIDCFG_SHIFT)
+#define TLBIVAACFG         (TLBIVAACFG_MASK         << TLBIVAACFG_SHIFT)
+#define FLOOR              (FLOOR_MASK              << FLOOR_SHIFT)
+#define VICTIM             (VICTIM_MASK             << VICTIM_SHIFT)
+
+
+/* TTBCR */
+#define N                  (N_MASK                  << N_SHIFT)
+#define PD0                (PD0_MASK                << PD0_SHIFT)
+#define PD1                (PD1_MASK                << PD1_SHIFT)
+
+
+/* TTBR0 */
+#define TTBR0_IRGNH        (TTBR0_IRGNH_MASK        << TTBR0_IRGNH_SHIFT)
+#define TTBR0_SH           (TTBR0_SH_MASK           << TTBR0_SH_SHIFT)
+#define TTBR0_ORGN         (TTBR0_ORGN_MASK         << TTBR0_ORGN_SHIFT)
+#define TTBR0_NOS          (TTBR0_NOS_MASK          << TTBR0_NOS_SHIFT)
+#define TTBR0_IRGNL        (TTBR0_IRGNL_MASK        << TTBR0_IRGNL_SHIFT)
+#define TTBR0_PA           (TTBR0_PA_MASK           << TTBR0_PA_SHIFT)
+
+
+/* TTBR1 */
+#define TTBR1_IRGNH        (TTBR1_IRGNH_MASK        << TTBR1_IRGNH_SHIFT)
+#define TTBR1_SH           (TTBR1_SH_MASK           << TTBR1_SH_SHIFT)
+#define TTBR1_ORGN         (TTBR1_ORGN_MASK         << TTBR1_ORGN_SHIFT)
+#define TTBR1_NOS          (TTBR1_NOS_MASK          << TTBR1_NOS_SHIFT)
+#define TTBR1_IRGNL        (TTBR1_IRGNL_MASK        << TTBR1_IRGNL_SHIFT)
+#define TTBR1_PA           (TTBR1_PA_MASK           << TTBR1_PA_SHIFT)
+
+
+/* V2PSR */
+#define HIT                (HIT_MASK                << HIT_SHIFT)
+#define INDEX              (INDEX_MASK              << INDEX_SHIFT)
+
+
+/* V2Pxx */
+#define V2Pxx_INDEX        (V2Pxx_INDEX_MASK        << V2Pxx_INDEX_SHIFT)
+#define V2Pxx_VA           (V2Pxx_VA_MASK           << V2Pxx_VA_SHIFT)
+
+
+/* Global Register Masks */
+/* CBACRn */
+#define RWVMID_MASK               0x1F
+#define RWE_MASK                  0x01
+#define RWGE_MASK                 0x01
+#define CBVMID_MASK               0x1F
+#define IRPTNDX_MASK              0xFF
+
+
+/* CR */
+#define RPUE_MASK                 0x01
+#define RPUERE_MASK               0x01
+#define RPUEIE_MASK               0x01
+#define DCDEE_MASK                0x01
+#define CLIENTPD_MASK             0x01
+#define STALLD_MASK               0x01
+#define TLBLKCRWE_MASK            0x01
+#define CR_TLBIALLCFG_MASK        0x01
+#define TLBIVMIDCFG_MASK          0x01
+#define CR_HUME_MASK              0x01
+
+
+/* ESR */
+#define CFG_MASK                  0x01
+#define BYPASS_MASK               0x01
+#define ESR_MULTI_MASK            0x01
+
+
+/* ESYNR0 */
+#define ESYNR0_AMID_MASK          0xFF
+#define ESYNR0_APID_MASK          0x1F
+#define ESYNR0_ABID_MASK          0x07
+#define ESYNR0_AVMID_MASK         0x1F
+#define ESYNR0_ATID_MASK          0xFF
+
+
+/* ESYNR1 */
+#define ESYNR1_AMEMTYPE_MASK             0x07
+#define ESYNR1_ASHARED_MASK              0x01
+#define ESYNR1_AINNERSHARED_MASK         0x01
+#define ESYNR1_APRIV_MASK                0x01
+#define ESYNR1_APROTNS_MASK              0x01
+#define ESYNR1_AINST_MASK                0x01
+#define ESYNR1_AWRITE_MASK               0x01
+#define ESYNR1_ABURST_MASK               0x01
+#define ESYNR1_ALEN_MASK                 0x0F
+#define ESYNR1_ASIZE_MASK                0x01
+#define ESYNR1_ALOCK_MASK                0x03
+#define ESYNR1_AOOO_MASK                 0x01
+#define ESYNR1_AFULL_MASK                0x01
+#define ESYNR1_AC_MASK                   0x01
+#define ESYNR1_DCD_MASK                  0x01
+
+
+/* IDR */
+#define NM2VCBMT_MASK             0x1FF
+#define HTW_MASK                  0x01
+#define HUM_MASK                  0x01
+#define TLBSIZE_MASK              0x0F
+#define NCB_MASK                  0xFF
+#define NIRPT_MASK                0xFF
+
+
+/* M2VCBRn */
+#define VMID_MASK                 0x1F
+#define CBNDX_MASK                0xFF
+#define BYPASSD_MASK              0x01
+#define BPRCOSH_MASK              0x01
+#define BPRCISH_MASK              0x01
+#define BPRCNSH_MASK              0x01
+#define BPSHCFG_MASK              0x03
+#define NSCFG_MASK                0x03
+#define BPMTCFG_MASK              0x01
+#define BPMEMTYPE_MASK            0x07
+
+
+/* REV */
+#define MINOR_MASK                0x0F
+#define MAJOR_MASK                0x0F
+
+
+/* TESTBUSCR */
+#define TBE_MASK                  0x01
+#define SPDMBE_MASK               0x01
+#define WGSEL_MASK                0x03
+#define TBLSEL_MASK               0x03
+#define TBHSEL_MASK               0x03
+#define SPDM0SEL_MASK             0x0F
+#define SPDM1SEL_MASK             0x0F
+#define SPDM2SEL_MASK             0x0F
+#define SPDM3SEL_MASK             0x0F
+
+
+/* TLBIMID */
+#define TLBIVMID_VMID_MASK        0x1F
+
+
+/* TLBRSW */
+#define TLBRSW_INDEX_MASK         0xFF
+#define TLBBFBS_MASK              0x03
+
+
+/* TLBTR0 */
+#define PR_MASK                   0x01
+#define PW_MASK                   0x01
+#define UR_MASK                   0x01
+#define UW_MASK                   0x01
+#define XN_MASK                   0x01
+#define NSDESC_MASK               0x01
+#define ISH_MASK                  0x01
+#define SH_MASK                   0x01
+#define MT_MASK                   0x07
+#define DPSIZR_MASK               0x07
+#define DPSIZC_MASK               0x07
+
+
+/* TLBTR1 */
+#define TLBTR1_VMID_MASK          0x1F
+#define TLBTR1_PA_MASK            0x000FFFFF
+
+
+/* TLBTR2 */
+#define TLBTR2_ASID_MASK          0xFF
+#define TLBTR2_V_MASK             0x01
+#define TLBTR2_NSTID_MASK         0x01
+#define TLBTR2_NV_MASK            0x01
+#define TLBTR2_VA_MASK            0x000FFFFF
+
+
+/* Global Register Shifts */
+/* CBACRn */
+#define RWVMID_SHIFT             0
+#define RWE_SHIFT                8
+#define RWGE_SHIFT               9
+#define CBVMID_SHIFT             16
+#define IRPTNDX_SHIFT            24
+
+
+/* CR */
+#define RPUE_SHIFT               0
+#define RPUERE_SHIFT             1
+#define RPUEIE_SHIFT             2
+#define DCDEE_SHIFT              3
+#define CLIENTPD_SHIFT           4
+#define STALLD_SHIFT             5
+#define TLBLKCRWE_SHIFT          6
+#define CR_TLBIALLCFG_SHIFT      7
+#define TLBIVMIDCFG_SHIFT        8
+#define CR_HUME_SHIFT            9
+
+
+/* ESR */
+#define CFG_SHIFT                0
+#define BYPASS_SHIFT             1
+#define ESR_MULTI_SHIFT          31
+
+
+/* ESYNR0 */
+#define ESYNR0_AMID_SHIFT        0
+#define ESYNR0_APID_SHIFT        8
+#define ESYNR0_ABID_SHIFT        13
+#define ESYNR0_AVMID_SHIFT       16
+#define ESYNR0_ATID_SHIFT        24
+
+
+/* ESYNR1 */
+#define ESYNR1_AMEMTYPE_SHIFT           0
+#define ESYNR1_ASHARED_SHIFT            3
+#define ESYNR1_AINNERSHARED_SHIFT       4
+#define ESYNR1_APRIV_SHIFT              5
+#define ESYNR1_APROTNS_SHIFT            6
+#define ESYNR1_AINST_SHIFT              7
+#define ESYNR1_AWRITE_SHIFT             8
+#define ESYNR1_ABURST_SHIFT             10
+#define ESYNR1_ALEN_SHIFT               12
+#define ESYNR1_ASIZE_SHIFT              16
+#define ESYNR1_ALOCK_SHIFT              20
+#define ESYNR1_AOOO_SHIFT               22
+#define ESYNR1_AFULL_SHIFT              24
+#define ESYNR1_AC_SHIFT                 30
+#define ESYNR1_DCD_SHIFT                31
+
+
+/* IDR */
+#define NM2VCBMT_SHIFT           0
+#define HTW_SHIFT                9
+#define HUM_SHIFT                10
+#define TLBSIZE_SHIFT            12
+#define NCB_SHIFT                16
+#define NIRPT_SHIFT              24
+
+
+/* M2VCBRn */
+#define VMID_SHIFT               0
+#define CBNDX_SHIFT              8
+#define BYPASSD_SHIFT            16
+#define BPRCOSH_SHIFT            17
+#define BPRCISH_SHIFT            18
+#define BPRCNSH_SHIFT            19
+#define BPSHCFG_SHIFT            20
+#define NSCFG_SHIFT              22
+#define BPMTCFG_SHIFT            24
+#define BPMEMTYPE_SHIFT          25
+
+
+/* REV */
+#define MINOR_SHIFT              0
+#define MAJOR_SHIFT              4
+
+
+/* TESTBUSCR */
+#define TBE_SHIFT                0
+#define SPDMBE_SHIFT             1
+#define WGSEL_SHIFT              8
+#define TBLSEL_SHIFT             12
+#define TBHSEL_SHIFT             14
+#define SPDM0SEL_SHIFT           16
+#define SPDM1SEL_SHIFT           20
+#define SPDM2SEL_SHIFT           24
+#define SPDM3SEL_SHIFT           28
+
+
+/* TLBIMID */
+#define TLBIVMID_VMID_SHIFT      0
+
+
+/* TLBRSW */
+#define TLBRSW_INDEX_SHIFT       0
+#define TLBBFBS_SHIFT            8
+
+
+/* TLBTR0 */
+#define PR_SHIFT                 0
+#define PW_SHIFT                 1
+#define UR_SHIFT                 2
+#define UW_SHIFT                 3
+#define XN_SHIFT                 4
+#define NSDESC_SHIFT             6
+#define ISH_SHIFT                7
+#define SH_SHIFT                 8
+#define MT_SHIFT                 9
+#define DPSIZR_SHIFT             16
+#define DPSIZC_SHIFT             20
+
+
+/* TLBTR1 */
+#define TLBTR1_VMID_SHIFT        0
+#define TLBTR1_PA_SHIFT          12
+
+
+/* TLBTR2 */
+#define TLBTR2_ASID_SHIFT        0
+#define TLBTR2_V_SHIFT           8
+#define TLBTR2_NSTID_SHIFT       9
+#define TLBTR2_NV_SHIFT          10
+#define TLBTR2_VA_SHIFT          12
+
+
+/* Context Register Masks */
+/* ACTLR */
+#define CFERE_MASK                       0x01
+#define CFEIE_MASK                       0x01
+#define PTSHCFG_MASK                     0x03
+#define RCOSH_MASK                       0x01
+#define RCISH_MASK                       0x01
+#define RCNSH_MASK                       0x01
+#define PRIVCFG_MASK                     0x03
+#define DNA_MASK                         0x01
+#define DNLV2PA_MASK                     0x01
+#define TLBMCFG_MASK                     0x03
+#define CFCFG_MASK                       0x01
+#define TIPCF_MASK                       0x01
+#define V2PCFG_MASK                      0x03
+#define HUME_MASK                        0x01
+#define PTMTCFG_MASK                     0x01
+#define PTMEMTYPE_MASK                   0x07
+
+
+/* BFBCR */
+#define BFBDFE_MASK                      0x01
+#define BFBSFE_MASK                      0x01
+#define SFVS_MASK                        0x01
+#define FLVIC_MASK                       0x0F
+#define SLVIC_MASK                       0x0F
+
+
+/* CONTEXTIDR */
+#define CONTEXTIDR_ASID_MASK             0xFF
+#define PROCID_MASK                      0x00FFFFFF
+
+
+/* FSR */
+#define TF_MASK                          0x01
+#define AFF_MASK                         0x01
+#define APF_MASK                         0x01
+#define TLBMF_MASK                       0x01
+#define HTWDEEF_MASK                     0x01
+#define HTWSEEF_MASK                     0x01
+#define MHF_MASK                         0x01
+#define SL_MASK                          0x01
+#define SS_MASK                          0x01
+#define MULTI_MASK                       0x01
+
+
+/* FSYNR0 */
+#define AMID_MASK                        0xFF
+#define APID_MASK                        0x1F
+#define ABID_MASK                        0x07
+#define ATID_MASK                        0xFF
+
+
+/* FSYNR1 */
+#define AMEMTYPE_MASK                    0x07
+#define ASHARED_MASK                     0x01
+#define AINNERSHARED_MASK                0x01
+#define APRIV_MASK                       0x01
+#define APROTNS_MASK                     0x01
+#define AINST_MASK                       0x01
+#define AWRITE_MASK                      0x01
+#define ABURST_MASK                      0x01
+#define ALEN_MASK                        0x0F
+#define FSYNR1_ASIZE_MASK                0x07
+#define ALOCK_MASK                       0x03
+#define AFULL_MASK                       0x01
+
+
+/* NMRR */
+#define ICPC0_MASK                       0x03
+#define ICPC1_MASK                       0x03
+#define ICPC2_MASK                       0x03
+#define ICPC3_MASK                       0x03
+#define ICPC4_MASK                       0x03
+#define ICPC5_MASK                       0x03
+#define ICPC6_MASK                       0x03
+#define ICPC7_MASK                       0x03
+#define OCPC0_MASK                       0x03
+#define OCPC1_MASK                       0x03
+#define OCPC2_MASK                       0x03
+#define OCPC3_MASK                       0x03
+#define OCPC4_MASK                       0x03
+#define OCPC5_MASK                       0x03
+#define OCPC6_MASK                       0x03
+#define OCPC7_MASK                       0x03
+
+
+/* PAR */
+#define FAULT_MASK                       0x01
+/* If a fault is present, these are the
+same as the fault fields in the FAR */
+#define FAULT_TF_MASK                    0x01
+#define FAULT_AFF_MASK                   0x01
+#define FAULT_APF_MASK                   0x01
+#define FAULT_TLBMF_MASK                 0x01
+#define FAULT_HTWDEEF_MASK               0x01
+#define FAULT_HTWSEEF_MASK               0x01
+#define FAULT_MHF_MASK                   0x01
+#define FAULT_SL_MASK                    0x01
+#define FAULT_SS_MASK                    0x01
+
+/* If NO fault is present, the following
+ * fields are in effect
+ * (FAULT remains as before) */
+#define PAR_NOFAULT_SS_MASK              0x01
+#define PAR_NOFAULT_MT_MASK              0x07
+#define PAR_NOFAULT_SH_MASK              0x01
+#define PAR_NOFAULT_NS_MASK              0x01
+#define PAR_NOFAULT_NOS_MASK             0x01
+#define PAR_NPFAULT_PA_MASK              0x000FFFFF
+
+
+/* PRRR */
+#define MTC0_MASK                        0x03
+#define MTC1_MASK                        0x03
+#define MTC2_MASK                        0x03
+#define MTC3_MASK                        0x03
+#define MTC4_MASK                        0x03
+#define MTC5_MASK                        0x03
+#define MTC6_MASK                        0x03
+#define MTC7_MASK                        0x03
+#define SHDSH0_MASK                      0x01
+#define SHDSH1_MASK                      0x01
+#define SHNMSH0_MASK                     0x01
+#define SHNMSH1_MASK                     0x01
+#define NOS0_MASK                        0x01
+#define NOS1_MASK                        0x01
+#define NOS2_MASK                        0x01
+#define NOS3_MASK                        0x01
+#define NOS4_MASK                        0x01
+#define NOS5_MASK                        0x01
+#define NOS6_MASK                        0x01
+#define NOS7_MASK                        0x01
+
+
+/* RESUME */
+#define TNR_MASK                         0x01
+
+
+/* SCTLR */
+#define M_MASK                           0x01
+#define TRE_MASK                         0x01
+#define AFE_MASK                         0x01
+#define HAF_MASK                         0x01
+#define BE_MASK                          0x01
+#define AFFD_MASK                        0x01
+
+
+/* TLBIASID */
+#define TLBIASID_ASID_MASK               0xFF
+
+
+/* TLBIVA */
+#define TLBIVA_ASID_MASK                 0xFF
+#define TLBIVA_VA_MASK                   0x000FFFFF
+
+
+/* TLBIVAA */
+#define TLBIVAA_VA_MASK                  0x000FFFFF
+
+
+/* TLBLCKR */
+#define LKE_MASK                         0x01
+#define TLBLCKR_TLBIALLCFG_MASK          0x01
+#define TLBIASIDCFG_MASK                 0x01
+#define TLBIVAACFG_MASK                  0x01
+#define FLOOR_MASK                       0xFF
+#define VICTIM_MASK                      0xFF
+
+
+/* TTBCR */
+#define N_MASK                           0x07
+#define PD0_MASK                         0x01
+#define PD1_MASK                         0x01
+
+
+/* TTBR0 */
+#define TTBR0_IRGNH_MASK                 0x01
+#define TTBR0_SH_MASK                    0x01
+#define TTBR0_ORGN_MASK                  0x03
+#define TTBR0_NOS_MASK                   0x01
+#define TTBR0_IRGNL_MASK                 0x01
+#define TTBR0_PA_MASK                    0x0003FFFF
+
+
+/* TTBR1 */
+#define TTBR1_IRGNH_MASK                 0x01
+#define TTBR1_SH_MASK                    0x01
+#define TTBR1_ORGN_MASK                  0x03
+#define TTBR1_NOS_MASK                   0x01
+#define TTBR1_IRGNL_MASK                 0x01
+#define TTBR1_PA_MASK                    0x0003FFFF
+
+
+/* V2PSR */
+#define HIT_MASK                         0x01
+#define INDEX_MASK                       0xFF
+
+
+/* V2Pxx */
+#define V2Pxx_INDEX_MASK                 0xFF
+#define V2Pxx_VA_MASK                    0x000FFFFF
+
+
+/* Context Register Shifts */
+/* ACTLR */
+#define CFERE_SHIFT                    0
+#define CFEIE_SHIFT                    1
+#define PTSHCFG_SHIFT                  2
+#define RCOSH_SHIFT                    4
+#define RCISH_SHIFT                    5
+#define RCNSH_SHIFT                    6
+#define PRIVCFG_SHIFT                  8
+#define DNA_SHIFT                      10
+#define DNLV2PA_SHIFT                  11
+#define TLBMCFG_SHIFT                  12
+#define CFCFG_SHIFT                    14
+#define TIPCF_SHIFT                    15
+#define V2PCFG_SHIFT                   16
+#define HUME_SHIFT                     18
+#define PTMTCFG_SHIFT                  20
+#define PTMEMTYPE_SHIFT                21
+
+
+/* BFBCR */
+#define BFBDFE_SHIFT                   0
+#define BFBSFE_SHIFT                   1
+#define SFVS_SHIFT                     2
+#define FLVIC_SHIFT                    4
+#define SLVIC_SHIFT                    8
+
+
+/* CONTEXTIDR */
+#define CONTEXTIDR_ASID_SHIFT          0
+#define PROCID_SHIFT                   8
+
+
+/* FSR */
+#define TF_SHIFT                       1
+#define AFF_SHIFT                      2
+#define APF_SHIFT                      3
+#define TLBMF_SHIFT                    4
+#define HTWDEEF_SHIFT                  5
+#define HTWSEEF_SHIFT                  6
+#define MHF_SHIFT                      7
+#define SL_SHIFT                       16
+#define SS_SHIFT                       30
+#define MULTI_SHIFT                    31
+
+
+/* FSYNR0 */
+#define AMID_SHIFT                     0
+#define APID_SHIFT                     8
+#define ABID_SHIFT                     13
+#define ATID_SHIFT                     24
+
+
+/* FSYNR1 */
+#define AMEMTYPE_SHIFT                 0
+#define ASHARED_SHIFT                  3
+#define AINNERSHARED_SHIFT             4
+#define APRIV_SHIFT                    5
+#define APROTNS_SHIFT                  6
+#define AINST_SHIFT                    7
+#define AWRITE_SHIFT                   8
+#define ABURST_SHIFT                   10
+#define ALEN_SHIFT                     12
+#define FSYNR1_ASIZE_SHIFT             16
+#define ALOCK_SHIFT                    20
+#define AFULL_SHIFT                    24
+
+
+/* NMRR */
+#define ICPC0_SHIFT                    0
+#define ICPC1_SHIFT                    2
+#define ICPC2_SHIFT                    4
+#define ICPC3_SHIFT                    6
+#define ICPC4_SHIFT                    8
+#define ICPC5_SHIFT                    10
+#define ICPC6_SHIFT                    12
+#define ICPC7_SHIFT                    14
+#define OCPC0_SHIFT                    16
+#define OCPC1_SHIFT                    18
+#define OCPC2_SHIFT                    20
+#define OCPC3_SHIFT                    22
+#define OCPC4_SHIFT                    24
+#define OCPC5_SHIFT                    26
+#define OCPC6_SHIFT                    28
+#define OCPC7_SHIFT                    30
+
+
+/* PAR */
+#define FAULT_SHIFT                    0
+/* If a fault is present, these are the
+same as the fault fields in the FAR */
+#define FAULT_TF_SHIFT                 1
+#define FAULT_AFF_SHIFT                2
+#define FAULT_APF_SHIFT                3
+#define FAULT_TLBMF_SHIFT              4
+#define FAULT_HTWDEEF_SHIFT            5
+#define FAULT_HTWSEEF_SHIFT            6
+#define FAULT_MHF_SHIFT                7
+#define FAULT_SL_SHIFT                 16
+#define FAULT_SS_SHIFT                 30
+
+/* If NO fault is present, the following
+ * fields are in effect
+ * (FAULT remains as before) */
+#define PAR_NOFAULT_SS_SHIFT           1
+#define PAR_NOFAULT_MT_SHIFT           4
+#define PAR_NOFAULT_SH_SHIFT           7
+#define PAR_NOFAULT_NS_SHIFT           9
+#define PAR_NOFAULT_NOS_SHIFT          10
+#define PAR_NPFAULT_PA_SHIFT           12
+
+
+/* PRRR */
+#define MTC0_SHIFT                     0
+#define MTC1_SHIFT                     2
+#define MTC2_SHIFT                     4
+#define MTC3_SHIFT                     6
+#define MTC4_SHIFT                     8
+#define MTC5_SHIFT                     10
+#define MTC6_SHIFT                     12
+#define MTC7_SHIFT                     14
+#define SHDSH0_SHIFT                   16
+#define SHDSH1_SHIFT                   17
+#define SHNMSH0_SHIFT                  18
+#define SHNMSH1_SHIFT                  19
+#define NOS0_SHIFT                     24
+#define NOS1_SHIFT                     25
+#define NOS2_SHIFT                     26
+#define NOS3_SHIFT                     27
+#define NOS4_SHIFT                     28
+#define NOS5_SHIFT                     29
+#define NOS6_SHIFT                     30
+#define NOS7_SHIFT                     31
+
+
+/* RESUME */
+#define TNR_SHIFT                      0
+
+
+/* SCTLR */
+#define M_SHIFT                        0
+#define TRE_SHIFT                      1
+#define AFE_SHIFT                      2
+#define HAF_SHIFT                      3
+#define BE_SHIFT                       4
+#define AFFD_SHIFT                     5
+
+
+/* TLBIASID */
+#define TLBIASID_ASID_SHIFT            0
+
+
+/* TLBIVA */
+#define TLBIVA_ASID_SHIFT              0
+#define TLBIVA_VA_SHIFT                12
+
+
+/* TLBIVAA */
+#define TLBIVAA_VA_SHIFT               12
+
+
+/* TLBLCKR */
+#define LKE_SHIFT                      0
+#define TLBLCKR_TLBIALLCFG_SHIFT       1
+#define TLBIASIDCFG_SHIFT              2
+#define TLBIVAACFG_SHIFT               3
+#define FLOOR_SHIFT                    8
+#define VICTIM_SHIFT                   8
+
+
+/* TTBCR */
+#define N_SHIFT                        3
+#define PD0_SHIFT                      4
+#define PD1_SHIFT                      5
+
+
+/* TTBR0 */
+#define TTBR0_IRGNH_SHIFT              0
+#define TTBR0_SH_SHIFT                 1
+#define TTBR0_ORGN_SHIFT               3
+#define TTBR0_NOS_SHIFT                5
+#define TTBR0_IRGNL_SHIFT              6
+#define TTBR0_PA_SHIFT                 14
+
+
+/* TTBR1 */
+#define TTBR1_IRGNH_SHIFT              0
+#define TTBR1_SH_SHIFT                 1
+#define TTBR1_ORGN_SHIFT               3
+#define TTBR1_NOS_SHIFT                5
+#define TTBR1_IRGNL_SHIFT              6
+#define TTBR1_PA_SHIFT                 14
+
+
+/* V2PSR */
+#define HIT_SHIFT                      0
+#define INDEX_SHIFT                    8
+
+
+/* V2Pxx */
+#define V2Pxx_INDEX_SHIFT              0
+#define V2Pxx_VA_SHIFT                 12
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs-8x60.h b/arch/arm/mach-msm/include/mach/irqs-8x60.h
new file mode 100644
index 000000000000..36074cfc9ad2
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/irqs-8x60.h
@@ -0,0 +1,253 @@
+/* Copyright (c) 2010 Code Aurora Forum. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_IRQS_8X60_H
+#define __ASM_ARCH_MSM_IRQS_8X60_H
+
+/* MSM ACPU Interrupt Numbers */
+
+/* 0-15:  STI/SGI (software triggered/generated interrupts)
+ * 16-31: PPI (private peripheral interrupts)
+ * 32+:   SPI (shared peripheral interrupts)
+ */
+
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+
+#define INT_DEBUG_TIMER_EXP                     (GIC_PPI_START + 0)
+#define INT_GP_TIMER_EXP                        (GIC_PPI_START + 1)
+#define INT_GP_TIMER2_EXP                       (GIC_PPI_START + 2)
+#define WDT0_ACCSCSSNBARK_INT                   (GIC_PPI_START + 3)
+#define WDT1_ACCSCSSNBARK_INT                   (GIC_PPI_START + 4)
+#define AVS_SVICINT                             (GIC_PPI_START + 5)
+#define AVS_SVICINTSWDONE                       (GIC_PPI_START + 6)
+#define CPU_DBGCPUXCOMMRXFULL                   (GIC_PPI_START + 7)
+#define CPU_DBGCPUXCOMMTXEMPTY                  (GIC_PPI_START + 8)
+#define CPU_SICCPUXPERFMONIRPTREQ               (GIC_PPI_START + 9)
+#define SC_AVSCPUXDOWN                          (GIC_PPI_START + 10)
+#define SC_AVSCPUXUP                            (GIC_PPI_START + 11)
+#define SC_SICCPUXACGIRPTREQ                    (GIC_PPI_START + 12)
+/* PPI 13 to 15 are unused */
+
+
+#define SC_SICMPUIRPTREQ                        (GIC_SPI_START + 0)
+#define SC_SICL2IRPTREQ                         (GIC_SPI_START + 1)
+#define SC_SICL2ACGIRPTREQ                      (GIC_SPI_START + 2)
+#define NC                                      (GIC_SPI_START + 3)
+#define TLMM_SCSS_DIR_CONN_IRQ_0                (GIC_SPI_START + 4)
+#define TLMM_SCSS_DIR_CONN_IRQ_1                (GIC_SPI_START + 5)
+#define TLMM_SCSS_DIR_CONN_IRQ_2                (GIC_SPI_START + 6)
+#define TLMM_SCSS_DIR_CONN_IRQ_3                (GIC_SPI_START + 7)
+#define TLMM_SCSS_DIR_CONN_IRQ_4                (GIC_SPI_START + 8)
+#define TLMM_SCSS_DIR_CONN_IRQ_5                (GIC_SPI_START + 9)
+#define TLMM_SCSS_DIR_CONN_IRQ_6                (GIC_SPI_START + 10)
+#define TLMM_SCSS_DIR_CONN_IRQ_7                (GIC_SPI_START + 11)
+#define TLMM_SCSS_DIR_CONN_IRQ_8                (GIC_SPI_START + 12)
+#define TLMM_SCSS_DIR_CONN_IRQ_9                (GIC_SPI_START + 13)
+#define PM8058_SEC_IRQ_N                        (GIC_SPI_START + 14)
+#define PM8901_SEC_IRQ_N                        (GIC_SPI_START + 15)
+#define TLMM_SCSS_SUMMARY_IRQ                   (GIC_SPI_START + 16)
+#define SPDM_RT_1_IRQ                           (GIC_SPI_START + 17)
+#define SPDM_DIAG_IRQ                           (GIC_SPI_START + 18)
+#define RPM_SCSS_CPU0_GP_HIGH_IRQ               (GIC_SPI_START + 19)
+#define RPM_SCSS_CPU0_GP_MEDIUM_IRQ             (GIC_SPI_START + 20)
+#define RPM_SCSS_CPU0_GP_LOW_IRQ                (GIC_SPI_START + 21)
+#define RPM_SCSS_CPU0_WAKE_UP_IRQ               (GIC_SPI_START + 22)
+#define RPM_SCSS_CPU1_GP_HIGH_IRQ               (GIC_SPI_START + 23)
+#define RPM_SCSS_CPU1_GP_MEDIUM_IRQ             (GIC_SPI_START + 24)
+#define RPM_SCSS_CPU1_GP_LOW_IRQ                (GIC_SPI_START + 25)
+#define RPM_SCSS_CPU1_WAKE_UP_IRQ               (GIC_SPI_START + 26)
+#define SSBI2_2_SC_CPU0_SECURE_INT              (GIC_SPI_START + 27)
+#define SSBI2_2_SC_CPU0_NON_SECURE_INT          (GIC_SPI_START + 28)
+#define SSBI2_1_SC_CPU0_SECURE_INT              (GIC_SPI_START + 29)
+#define SSBI2_1_SC_CPU0_NON_SECURE_INT          (GIC_SPI_START + 30)
+#define MSMC_SC_SEC_CE_IRQ                      (GIC_SPI_START + 31)
+#define MSMC_SC_PRI_CE_IRQ                      (GIC_SPI_START + 32)
+#define MARM_FIQ                                (GIC_SPI_START + 33)
+#define MARM_IRQ                                (GIC_SPI_START + 34)
+#define MARM_L2CC_IRQ                           (GIC_SPI_START + 35)
+#define MARM_WDOG_EXPIRED                       (GIC_SPI_START + 36)
+#define MARM_SCSS_GP_IRQ_0                      (GIC_SPI_START + 37)
+#define MARM_SCSS_GP_IRQ_1                      (GIC_SPI_START + 38)
+#define MARM_SCSS_GP_IRQ_2                      (GIC_SPI_START + 39)
+#define MARM_SCSS_GP_IRQ_3                      (GIC_SPI_START + 40)
+#define MARM_SCSS_GP_IRQ_4                      (GIC_SPI_START + 41)
+#define MARM_SCSS_GP_IRQ_5                      (GIC_SPI_START + 42)
+#define MARM_SCSS_GP_IRQ_6                      (GIC_SPI_START + 43)
+#define MARM_SCSS_GP_IRQ_7                      (GIC_SPI_START + 44)
+#define MARM_SCSS_GP_IRQ_8                      (GIC_SPI_START + 45)
+#define MARM_SCSS_GP_IRQ_9                      (GIC_SPI_START + 46)
+#define VPE_IRQ                                 (GIC_SPI_START + 47)
+#define VFE_IRQ                                 (GIC_SPI_START + 48)
+#define VCODEC_IRQ                              (GIC_SPI_START + 49)
+#define TV_ENC_IRQ                              (GIC_SPI_START + 50)
+#define SMMU_VPE_CB_SC_SECURE_IRQ               (GIC_SPI_START + 51)
+#define SMMU_VPE_CB_SC_NON_SECURE_IRQ           (GIC_SPI_START + 52)
+#define SMMU_VFE_CB_SC_SECURE_IRQ               (GIC_SPI_START + 53)
+#define SMMU_VFE_CB_SC_NON_SECURE_IRQ           (GIC_SPI_START + 54)
+#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ          (GIC_SPI_START + 55)
+#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ      (GIC_SPI_START + 56)
+#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ          (GIC_SPI_START + 57)
+#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ      (GIC_SPI_START + 58)
+#define SMMU_ROT_CB_SC_SECURE_IRQ               (GIC_SPI_START + 59)
+#define SMMU_ROT_CB_SC_NON_SECURE_IRQ           (GIC_SPI_START + 60)
+#define SMMU_MDP1_CB_SC_SECURE_IRQ              (GIC_SPI_START + 61)
+#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ          (GIC_SPI_START + 62)
+#define SMMU_MDP0_CB_SC_SECURE_IRQ              (GIC_SPI_START + 63)
+#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ          (GIC_SPI_START + 64)
+#define SMMU_JPEGD_CB_SC_SECURE_IRQ             (GIC_SPI_START + 65)
+#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ         (GIC_SPI_START + 66)
+#define SMMU_IJPEG_CB_SC_SECURE_IRQ             (GIC_SPI_START + 67)
+#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ         (GIC_SPI_START + 68)
+#define SMMU_GFX3D_CB_SC_SECURE_IRQ             (GIC_SPI_START + 69)
+#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ         (GIC_SPI_START + 70)
+#define SMMU_GFX2D0_CB_SC_SECURE_IRQ            (GIC_SPI_START + 71)
+#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ        (GIC_SPI_START + 72)
+#define ROT_IRQ                                 (GIC_SPI_START + 73)
+#define MMSS_FABRIC_IRQ                         (GIC_SPI_START + 74)
+#define MDP_IRQ                                 (GIC_SPI_START + 75)
+#define JPEGD_IRQ                               (GIC_SPI_START + 76)
+#define JPEG_IRQ                                (GIC_SPI_START + 77)
+#define MMSS_IMEM_IRQ                           (GIC_SPI_START + 78)
+#define HDMI_IRQ                                (GIC_SPI_START + 79)
+#define GFX3D_IRQ                               (GIC_SPI_START + 80)
+#define GFX2D0_IRQ                              (GIC_SPI_START + 81)
+#define DSI_IRQ                                 (GIC_SPI_START + 82)
+#define CSI_1_IRQ                               (GIC_SPI_START + 83)
+#define CSI_0_IRQ                               (GIC_SPI_START + 84)
+#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ            (GIC_SPI_START + 85)
+#define LPASS_SCSS_MIDI_IRQ                     (GIC_SPI_START + 86)
+#define LPASS_Q6SS_WDOG_EXPIRED                 (GIC_SPI_START + 87)
+#define LPASS_SCSS_GP_LOW_IRQ                   (GIC_SPI_START + 88)
+#define LPASS_SCSS_GP_MEDIUM_IRQ                (GIC_SPI_START + 89)
+#define LPASS_SCSS_GP_HIGH_IRQ                  (GIC_SPI_START + 90)
+#define TOP_IMEM_IRQ                            (GIC_SPI_START + 91)
+#define FABRIC_SYS_IRQ                          (GIC_SPI_START + 92)
+#define FABRIC_APPS_IRQ                         (GIC_SPI_START + 93)
+#define USB1_HS_BAM_IRQ                         (GIC_SPI_START + 94)
+#define SDC4_BAM_IRQ                            (GIC_SPI_START + 95)
+#define SDC3_BAM_IRQ                            (GIC_SPI_START + 96)
+#define SDC2_BAM_IRQ                            (GIC_SPI_START + 97)
+#define SDC1_BAM_IRQ                            (GIC_SPI_START + 98)
+#define FABRIC_SPS_IRQ                          (GIC_SPI_START + 99)
+#define USB1_HS_IRQ                             (GIC_SPI_START + 100)
+#define SDC4_IRQ_0                              (GIC_SPI_START + 101)
+#define SDC3_IRQ_0                              (GIC_SPI_START + 102)
+#define SDC2_IRQ_0                              (GIC_SPI_START + 103)
+#define SDC1_IRQ_0                              (GIC_SPI_START + 104)
+#define SPS_BAM_DMA_IRQ                         (GIC_SPI_START + 105)
+#define SPS_SEC_VIOL_IRQ                        (GIC_SPI_START + 106)
+#define SPS_MTI_0                               (GIC_SPI_START + 107)
+#define SPS_MTI_1                               (GIC_SPI_START + 108)
+#define SPS_MTI_2                               (GIC_SPI_START + 109)
+#define SPS_MTI_3                               (GIC_SPI_START + 110)
+#define SPS_MTI_4                               (GIC_SPI_START + 111)
+#define SPS_MTI_5                               (GIC_SPI_START + 112)
+#define SPS_MTI_6                               (GIC_SPI_START + 113)
+#define SPS_MTI_7                               (GIC_SPI_START + 114)
+#define SPS_MTI_8                               (GIC_SPI_START + 115)
+#define SPS_MTI_9                               (GIC_SPI_START + 116)
+#define SPS_MTI_10                              (GIC_SPI_START + 117)
+#define SPS_MTI_11                              (GIC_SPI_START + 118)
+#define SPS_MTI_12                              (GIC_SPI_START + 119)
+#define SPS_MTI_13                              (GIC_SPI_START + 120)
+#define SPS_MTI_14                              (GIC_SPI_START + 121)
+#define SPS_MTI_15                              (GIC_SPI_START + 122)
+#define SPS_MTI_16                              (GIC_SPI_START + 123)
+#define SPS_MTI_17                              (GIC_SPI_START + 124)
+#define SPS_MTI_18                              (GIC_SPI_START + 125)
+#define SPS_MTI_19                              (GIC_SPI_START + 126)
+#define SPS_MTI_20                              (GIC_SPI_START + 127)
+#define SPS_MTI_21                              (GIC_SPI_START + 128)
+#define SPS_MTI_22                              (GIC_SPI_START + 129)
+#define SPS_MTI_23                              (GIC_SPI_START + 130)
+#define SPS_MTI_24                              (GIC_SPI_START + 131)
+#define SPS_MTI_25                              (GIC_SPI_START + 132)
+#define SPS_MTI_26                              (GIC_SPI_START + 133)
+#define SPS_MTI_27                              (GIC_SPI_START + 134)
+#define SPS_MTI_28                              (GIC_SPI_START + 135)
+#define SPS_MTI_29                              (GIC_SPI_START + 136)
+#define SPS_MTI_30                              (GIC_SPI_START + 137)
+#define SPS_MTI_31                              (GIC_SPI_START + 138)
+#define UXMC_EBI2_WR_ER_DONE_IRQ                (GIC_SPI_START + 139)
+#define UXMC_EBI2_OP_DONE_IRQ                   (GIC_SPI_START + 140)
+#define USB2_IRQ                                (GIC_SPI_START + 141)
+#define USB1_IRQ                                (GIC_SPI_START + 142)
+#define TSSC_SSBI_IRQ                           (GIC_SPI_START + 143)
+#define TSSC_SAMPLE_IRQ                         (GIC_SPI_START + 144)
+#define TSSC_PENUP_IRQ                          (GIC_SPI_START + 145)
+#define INT_UART1DM_IRQ                         (GIC_SPI_START + 146)
+#define GSBI1_QUP_IRQ                           (GIC_SPI_START + 147)
+#define INT_UART2DM_IRQ                         (GIC_SPI_START + 148)
+#define GSBI2_QUP_IRQ                           (GIC_SPI_START + 149)
+#define INT_UART3DM_IRQ                         (GIC_SPI_START + 150)
+#define GSBI3_QUP_IRQ                           (GIC_SPI_START + 151)
+#define INT_UART4DM_IRQ                         (GIC_SPI_START + 152)
+#define GSBI4_QUP_IRQ                           (GIC_SPI_START + 153)
+#define INT_UART5DM_IRQ                         (GIC_SPI_START + 154)
+#define GSBI5_QUP_IRQ                           (GIC_SPI_START + 155)
+#define INT_UART6DM_IRQ                         (GIC_SPI_START + 156)
+#define GSBI6_QUP_IRQ                           (GIC_SPI_START + 157)
+#define INT_UART7DM_IRQ                         (GIC_SPI_START + 158)
+#define GSBI7_QUP_IRQ                           (GIC_SPI_START + 159)
+#define INT_UART8DM_IRQ                         (GIC_SPI_START + 160)
+#define GSBI8_QUP_IRQ                           (GIC_SPI_START + 161)
+#define TSIF_TSPP_IRQ                           (GIC_SPI_START + 162)
+#define TSIF_BAM_IRQ                            (GIC_SPI_START + 163)
+#define TSIF2_IRQ                               (GIC_SPI_START + 164)
+#define TSIF1_IRQ                               (GIC_SPI_START + 165)
+#define INT_ADM1_MASTER                         (GIC_SPI_START + 166)
+#define INT_ADM1_AARM                           (GIC_SPI_START + 167)
+#define INT_ADM1_SD2                            (GIC_SPI_START + 168)
+#define INT_ADM1_SD3                            (GIC_SPI_START + 169)
+#define INT_ADM0_MASTER                         (GIC_SPI_START + 170)
+#define INT_ADM0_AARM                           (GIC_SPI_START + 171)
+#define INT_ADM0_SD2                            (GIC_SPI_START + 172)
+#define INT_ADM0_SD3                            (GIC_SPI_START + 173)
+#define CC_SCSS_WDT1CPU1BITEEXPIRED             (GIC_SPI_START + 174)
+#define CC_SCSS_WDT1CPU0BITEEXPIRED             (GIC_SPI_START + 175)
+#define CC_SCSS_WDT0CPU1BITEEXPIRED             (GIC_SPI_START + 176)
+#define CC_SCSS_WDT0CPU0BITEEXPIRED             (GIC_SPI_START + 177)
+#define TSENS_UPPER_LOWER_INT                   (GIC_SPI_START + 178)
+#define SSBI2_2_SC_CPU1_SECURE_INT              (GIC_SPI_START + 179)
+#define SSBI2_2_SC_CPU1_NON_SECURE_INT          (GIC_SPI_START + 180)
+#define SSBI2_1_SC_CPU1_SECURE_INT              (GIC_SPI_START + 181)
+#define SSBI2_1_SC_CPU1_NON_SECURE_INT          (GIC_SPI_START + 182)
+#define XPU_SUMMARY_IRQ                         (GIC_SPI_START + 183)
+#define BUS_EXCEPTION_SUMMARY_IRQ               (GIC_SPI_START + 184)
+#define HSDDRX_SMICH0_IRQ                       (GIC_SPI_START + 185)
+#define HSDDRX_EBI1_IRQ                         (GIC_SPI_START + 186)
+#define SDC5_BAM_IRQ                            (GIC_SPI_START + 187)
+#define SDC5_IRQ_0                              (GIC_SPI_START + 188)
+#define INT_UART9DM_IRQ                         (GIC_SPI_START + 189)
+#define GSBI9_QUP_IRQ                           (GIC_SPI_START + 190)
+#define INT_UART10DM_IRQ                        (GIC_SPI_START + 191)
+#define GSBI10_QUP_IRQ                          (GIC_SPI_START + 192)
+#define INT_UART11DM_IRQ                        (GIC_SPI_START + 193)
+#define GSBI11_QUP_IRQ                          (GIC_SPI_START + 194)
+#define INT_UART12DM_IRQ                        (GIC_SPI_START + 195)
+#define GSBI12_QUP_IRQ                          (GIC_SPI_START + 196)
+/*SPI 197 to 216 arent used in 8x60*/
+#define SMPSS_SPARE_1                           (GIC_SPI_START + 217)
+#define SMPSS_SPARE_2                           (GIC_SPI_START + 218)
+#define SMPSS_SPARE_3                           (GIC_SPI_START + 219)
+#define SMPSS_SPARE_4                           (GIC_SPI_START + 220)
+#define SMPSS_SPARE_5                           (GIC_SPI_START + 221)
+#define SMPSS_SPARE_6                           (GIC_SPI_START + 222)
+#define SMPSS_SPARE_7                           (GIC_SPI_START + 223)
+
+#define NR_GPIO_IRQS 173
+#define NR_MSM_IRQS 256
+#define NR_BOARD_IRQS 0
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h
index 164d355c96ea..8679a4564744 100644
--- a/arch/arm/mach-msm/include/mach/irqs.h
+++ b/arch/arm/mach-msm/include/mach/irqs.h
@@ -24,6 +24,8 @@
 #elif defined(CONFIG_ARCH_QSD8X50)
 #include "irqs-8x50.h"
 #include "sirc.h"
+#elif defined(CONFIG_ARCH_MSM8X60)
+#include "irqs-8x60.h"
 #elif defined(CONFIG_ARCH_MSM_ARM11)
 #include "irqs-7x00.h"
 #else
diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
index 50c7847e6002..070e17d237f1 100644
--- a/arch/arm/mach-msm/include/mach/memory.h
+++ b/arch/arm/mach-msm/include/mach/memory.h
@@ -23,6 +23,8 @@
 #define PHYS_OFFSET             UL(0x20000000)
 #elif defined(CONFIG_ARCH_MSM7X30)
 #define PHYS_OFFSET             UL(0x00200000)
+#elif defined(CONFIG_ARCH_MSM8X60)
+#define PHYS_OFFSET             UL(0x40200000)
 #else
 #define PHYS_OFFSET             UL(0x10000000)
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
new file mode 100644
index 000000000000..45bab50e3ee6
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *
+ * The MSM peripherals are spread all over across 768MB of physical
+ * space, which makes just having a simple IO_ADDRESS macro to slide
+ * them into the right virtual location rough.  Instead, we will
+ * provide a master phys->virt mapping for peripherals here.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_IOMAP_8X60_H
+#define __ASM_ARCH_MSM_IOMAP_8X60_H
+
+/* Physical base address and size of peripherals.
+ * Ordered by the virtual base addresses they will be mapped at.
+ *
+ * MSM_VIC_BASE must be an value that can be loaded via a "mov"
+ * instruction, otherwise entry-macro.S will not compile.
+ *
+ * If you add or remove entries here, you'll want to edit the
+ * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
+ * changes.
+ *
+ */
+
+#define MSM_QGIC_DIST_BASE      IOMEM(0xF0000000)
+#define MSM_QGIC_DIST_PHYS      0x02080000
+#define MSM_QGIC_DIST_SIZE      SZ_4K
+
+#define MSM_QGIC_CPU_BASE       IOMEM(0xF0001000)
+#define MSM_QGIC_CPU_PHYS       0x02081000
+#define MSM_QGIC_CPU_SIZE       SZ_4K
+
+#define MSM_ACC_BASE            IOMEM(0xF0002000)
+#define MSM_ACC_PHYS            0x02001000
+#define MSM_ACC_SIZE            SZ_4K
+
+#define MSM_GCC_BASE            IOMEM(0xF0003000)
+#define MSM_GCC_PHYS            0x02082000
+#define MSM_GCC_SIZE            SZ_4K
+
+#define MSM_TLMM_BASE           IOMEM(0xF0004000)
+#define MSM_TLMM_PHYS           0x00800000
+#define MSM_TLMM_SIZE           SZ_16K
+
+#define MSM_SHARED_RAM_BASE     IOMEM(0xF0100000)
+#define MSM_SHARED_RAM_SIZE     SZ_1M
+
+#define MSM_TMR_BASE            IOMEM(0xF0200000)
+#define MSM_TMR_PHYS            0x02000000
+#define MSM_TMR_SIZE            (SZ_1M)
+
+#define MSM_GPT_BASE            (MSM_TMR_BASE + 0x4)
+#define MSM_DGT_BASE            (MSM_TMR_BASE + 0x24)
+
+#define MSM_IOMMU_JPEGD_PHYS    0x07300000
+#define MSM_IOMMU_JPEGD_SIZE    SZ_1M
+
+#define MSM_IOMMU_VPE_PHYS      0x07400000
+#define MSM_IOMMU_VPE_SIZE      SZ_1M
+
+#define MSM_IOMMU_MDP0_PHYS     0x07500000
+#define MSM_IOMMU_MDP0_SIZE     SZ_1M
+
+#define MSM_IOMMU_MDP1_PHYS     0x07600000
+#define MSM_IOMMU_MDP1_SIZE     SZ_1M
+
+#define MSM_IOMMU_ROT_PHYS      0x07700000
+#define MSM_IOMMU_ROT_SIZE      SZ_1M
+
+#define MSM_IOMMU_IJPEG_PHYS    0x07800000
+#define MSM_IOMMU_IJPEG_SIZE    SZ_1M
+
+#define MSM_IOMMU_VFE_PHYS      0x07900000
+#define MSM_IOMMU_VFE_SIZE      SZ_1M
+
+#define MSM_IOMMU_VCODEC_A_PHYS 0x07A00000
+#define MSM_IOMMU_VCODEC_A_SIZE SZ_1M
+
+#define MSM_IOMMU_VCODEC_B_PHYS 0x07B00000
+#define MSM_IOMMU_VCODEC_B_SIZE SZ_1M
+
+#define MSM_IOMMU_GFX3D_PHYS    0x07C00000
+#define MSM_IOMMU_GFX3D_SIZE    SZ_1M
+
+#define MSM_IOMMU_GFX2D0_PHYS   0x07D00000
+#define MSM_IOMMU_GFX2D0_SIZE   SZ_1M
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index e6b1821cc4ea..8e24dd812139 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -47,8 +47,12 @@
 #include "msm_iomap-7x30.h"
 #elif defined(CONFIG_ARCH_QSD8X50)
 #include "msm_iomap-8x50.h"
+#elif defined(CONFIG_ARCH_MSM8X60)
+#include "msm_iomap-8x60.h"
 #else
 #include "msm_iomap-7x00.h"
 #endif
 
+
+
 #endif
diff --git a/arch/arm/mach-msm/include/mach/smp.h b/arch/arm/mach-msm/include/mach/smp.h
new file mode 100644
index 000000000000..3ff7bf5e679e
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/smp.h
@@ -0,0 +1,39 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_SMP_H
+#define __ASM_ARCH_MSM_SMP_H
+
+#include <asm/hardware/gic.h>
+
+static inline void smp_cross_call(const struct cpumask *mask)
+{
+        gic_raise_softirq(mask, 1);
+}
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/vmalloc.h b/arch/arm/mach-msm/include/mach/vmalloc.h
index 05f81fd8623c..31a32ad062dc 100644
--- a/arch/arm/mach-msm/include/mach/vmalloc.h
+++ b/arch/arm/mach-msm/include/mach/vmalloc.h
@@ -16,7 +16,7 @@
 #ifndef __ASM_ARCH_MSM_VMALLOC_H
 #define __ASM_ARCH_MSM_VMALLOC_H
 
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END       0xd0000000
 
 #endif
 
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 1c05060b5f3b..d36b61074146 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -100,6 +100,21 @@ void __init msm_map_qsd8x50_io(void)
 }
 #endif /* CONFIG_ARCH_QSD8X50 */
 
+#ifdef CONFIG_ARCH_MSM8X60
+static struct map_desc msm8x60_io_desc[] __initdata = {
+        MSM_DEVICE(QGIC_DIST),
+        MSM_DEVICE(QGIC_CPU),
+        MSM_DEVICE(TMR),
+        MSM_DEVICE(ACC),
+        MSM_DEVICE(GCC),
+};
+
+void __init msm_map_msm8x60_io(void)
+{
+        iotable_init(msm8x60_io_desc, ARRAY_SIZE(msm8x60_io_desc));
+}
+#endif /* CONFIG_ARCH_MSM8X60 */
+
 #ifdef CONFIG_ARCH_MSM7X30
 static struct map_desc msm7x30_io_desc[] __initdata = {
         MSM_DEVICE(VIC),
diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c
new file mode 100644
index 000000000000..f71747db3bee
--- /dev/null
+++ b/arch/arm/mach-msm/iommu.c
@@ -0,0 +1,597 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#define pr_fmt(fmt)     KBUILD_MODNAME ": " fmt
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+#include <linux/iommu.h>
+
+#include <asm/cacheflush.h>
+#include <asm/sizes.h>
+
+#include <mach/iommu_hw-8xxx.h>
+#include <mach/iommu.h>
+
+DEFINE_SPINLOCK(msm_iommu_lock);
+
+struct msm_priv {
+        unsigned long *pgtable;
+        struct list_head list_attached;
+};
+
+static void __flush_iotlb(struct iommu_domain *domain)
+{
+        struct msm_priv *priv = domain->priv;
+        struct msm_iommu_drvdata *iommu_drvdata;
+        struct msm_iommu_ctx_drvdata *ctx_drvdata;
+
+#ifndef CONFIG_IOMMU_PGTABLES_L2
+        unsigned long *fl_table = priv->pgtable;
+        int i;
+
+        dmac_flush_range(fl_table, fl_table + SZ_16K);
+
+        for (i = 0; i < NUM_FL_PTE; i++)
+                if ((fl_table[i] & 0x03) == FL_TYPE_TABLE) {
+                        void *sl_table = __va(fl_table[i] & FL_BASE_MASK);
+                        dmac_flush_range(sl_table, sl_table + SZ_4K);
+                }
+#endif
+
+        list_for_each_entry(ctx_drvdata, &priv->list_attached, attached_elm) {
+                if (!ctx_drvdata->pdev || !ctx_drvdata->pdev->dev.parent)
+                        BUG();
+
+                iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
+                SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0);
+        }
+}
+
+static void __reset_context(void __iomem *base, int ctx)
+{
+        SET_BPRCOSH(base, ctx, 0);
+        SET_BPRCISH(base, ctx, 0);
+        SET_BPRCNSH(base, ctx, 0);
+        SET_BPSHCFG(base, ctx, 0);
+        SET_BPMTCFG(base, ctx, 0);
+        SET_ACTLR(base, ctx, 0);
+        SET_SCTLR(base, ctx, 0);
+        SET_FSRRESTORE(base, ctx, 0);
+        SET_TTBR0(base, ctx, 0);
+        SET_TTBR1(base, ctx, 0);
+        SET_TTBCR(base, ctx, 0);
+        SET_BFBCR(base, ctx, 0);
+        SET_PAR(base, ctx, 0);
+        SET_FAR(base, ctx, 0);
+        SET_CTX_TLBIALL(base, ctx, 0);
+        SET_TLBFLPTER(base, ctx, 0);
+        SET_TLBSLPTER(base, ctx, 0);
+        SET_TLBLKCR(base, ctx, 0);
+        SET_PRRR(base, ctx, 0);
+        SET_NMRR(base, ctx, 0);
+        SET_CONTEXTIDR(base, ctx, 0);
+}
+
+static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable)
+{
+        __reset_context(base, ctx);
+
+        /* Set up HTW mode */
+        /* TLB miss configuration: perform HTW on miss */
+        SET_TLBMCFG(base, ctx, 0x3);
+
+        /* V2P configuration: HTW for access */
+        SET_V2PCFG(base, ctx, 0x3);
+
+        SET_TTBCR(base, ctx, 0);
+        SET_TTBR0_PA(base, ctx, (pgtable >> 14));
+
+        /* Invalidate the TLB for this context */
+        SET_CTX_TLBIALL(base, ctx, 0);
+
+        /* Set interrupt number to "secure" interrupt */
+        SET_IRPTNDX(base, ctx, 0);
+
+        /* Enable context fault interrupt */
+        SET_CFEIE(base, ctx, 1);
+
+        /* Stall access on a context fault and let the handler deal with it */
+        SET_CFCFG(base, ctx, 1);
+
+        /* Redirect all cacheable requests to L2 slave port. */
+        SET_RCISH(base, ctx, 1);
+        SET_RCOSH(base, ctx, 1);
+        SET_RCNSH(base, ctx, 1);
+
+        /* Turn on TEX Remap */
+        SET_TRE(base, ctx, 1);
+
+        /* Do not configure PRRR / NMRR on the IOMMU for now. We will assume
+         * TEX class 0 for everything until attributes are properly worked out
+         */
+        SET_PRRR(base, ctx, 0);
+        SET_NMRR(base, ctx, 0);
+
+        /* Turn on BFB prefetch */
+        SET_BFBDFE(base, ctx, 1);
+
+#ifdef CONFIG_IOMMU_PGTABLES_L2
+        /* Configure page tables as inner-cacheable and shareable to reduce
+         * the TLB miss penalty.
+         */
+        SET_TTBR0_SH(base, ctx, 1);
+        SET_TTBR1_SH(base, ctx, 1);
+
+        SET_TTBR0_NOS(base, ctx, 1);
+        SET_TTBR1_NOS(base, ctx, 1);
+
+        SET_TTBR0_IRGNH(base, ctx, 0); /* WB, WA */
+        SET_TTBR0_IRGNL(base, ctx, 1);
+
+        SET_TTBR1_IRGNH(base, ctx, 0); /* WB, WA */
+        SET_TTBR1_IRGNL(base, ctx, 1);
+
+        SET_TTBR0_ORGN(base, ctx, 1); /* WB, WA */
+        SET_TTBR1_ORGN(base, ctx, 1); /* WB, WA */
+#endif
+
+        /* Enable the MMU */
+        SET_M(base, ctx, 1);
+}
+
+static int msm_iommu_domain_init(struct iommu_domain *domain)
+{
+        struct msm_priv *priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+
+        if (!priv)
+                goto fail_nomem;
+
+        INIT_LIST_HEAD(&priv->list_attached);
+        priv->pgtable = (unsigned long *)__get_free_pages(GFP_KERNEL,
+                                                          get_order(SZ_16K));
+
+        if (!priv->pgtable)
+                goto fail_nomem;
+
+        memset(priv->pgtable, 0, SZ_16K);
+        domain->priv = priv;
+        return 0;
+
+fail_nomem:
+        kfree(priv);
+        return -ENOMEM;
+}
+
+static void msm_iommu_domain_destroy(struct iommu_domain *domain)
+{
+        struct msm_priv *priv;
+        unsigned long flags;
+        unsigned long *fl_table;
+        int i;
+
+        spin_lock_irqsave(&msm_iommu_lock, flags);
+        priv = domain->priv;
+        domain->priv = NULL;
+
+        if (priv) {
+                fl_table = priv->pgtable;
+
+                for (i = 0; i < NUM_FL_PTE; i++)
+                        if ((fl_table[i] & 0x03) == FL_TYPE_TABLE)
+                                free_page((unsigned long) __va(((fl_table[i]) &
+                                                                FL_BASE_MASK)));
+
+                free_pages((unsigned long)priv->pgtable, get_order(SZ_16K));
+                priv->pgtable = NULL;
+        }
+
+        kfree(priv);
+        spin_unlock_irqrestore(&msm_iommu_lock, flags);
+}
+
+static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
+{
+        struct msm_priv *priv;
+        struct msm_iommu_ctx_dev *ctx_dev;
+        struct msm_iommu_drvdata *iommu_drvdata;
+        struct msm_iommu_ctx_drvdata *ctx_drvdata;
+        struct msm_iommu_ctx_drvdata *tmp_drvdata;
+        int ret = 0;
+        unsigned long flags;
+
+        spin_lock_irqsave(&msm_iommu_lock, flags);
+
+        priv = domain->priv;
+
+        if (!priv || !dev) {
+                ret = -EINVAL;
+                goto fail;
+        }
+
+        iommu_drvdata = dev_get_drvdata(dev->parent);
+        ctx_drvdata = dev_get_drvdata(dev);
+        ctx_dev = dev->platform_data;
+
+        if (!iommu_drvdata || !ctx_drvdata || !ctx_dev) {
+                ret = -EINVAL;
+                goto fail;
+        }
+
+        list_for_each_entry(tmp_drvdata, &priv->list_attached, attached_elm)
+                if (tmp_drvdata == ctx_drvdata) {
+                        ret = -EBUSY;
+                        goto fail;
+                }
+
+        __program_context(iommu_drvdata->base, ctx_dev->num,
+                          __pa(priv->pgtable));
+
+        list_add(&(ctx_drvdata->attached_elm), &priv->list_attached);
+        __flush_iotlb(domain);
+
+fail:
+        spin_unlock_irqrestore(&msm_iommu_lock, flags);
+        return ret;
+}
+
+static void msm_iommu_detach_dev(struct iommu_domain *domain,
+                                 struct device *dev)
+{
+        struct msm_priv *priv;
+        struct msm_iommu_ctx_dev *ctx_dev;
+        struct msm_iommu_drvdata *iommu_drvdata;
+        struct msm_iommu_ctx_drvdata *ctx_drvdata;
+        unsigned long flags;
+
+        spin_lock_irqsave(&msm_iommu_lock, flags);
+        priv = domain->priv;
+
+        if (!priv || !dev)
+                goto fail;
+
+        iommu_drvdata = dev_get_drvdata(dev->parent);
+        ctx_drvdata = dev_get_drvdata(dev);
+        ctx_dev = dev->platform_data;
+
+        if (!iommu_drvdata || !ctx_drvdata || !ctx_dev)
+                goto fail;
+
+        __flush_iotlb(domain);
+        __reset_context(iommu_drvdata->base, ctx_dev->num);
+        list_del_init(&ctx_drvdata->attached_elm);
+
+fail:
+        spin_unlock_irqrestore(&msm_iommu_lock, flags);
+}
+
+static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
+                         phys_addr_t pa, int order, int prot)
+{
+        struct msm_priv *priv;
+        unsigned long flags;
+        unsigned long *fl_table;
+        unsigned long *fl_pte;
+        unsigned long fl_offset;
+        unsigned long *sl_table;
+        unsigned long *sl_pte;
+        unsigned long sl_offset;
+        size_t len = 0x1000UL << order;
+        int ret = 0;
+
+        spin_lock_irqsave(&msm_iommu_lock, flags);
+        priv = domain->priv;
+
+        if (!priv) {
+                ret = -EINVAL;
+                goto fail;
+        }
+
+        fl_table = priv->pgtable;
+
+        if (len != SZ_16M && len != SZ_1M &&
+            len != SZ_64K && len != SZ_4K) {
+                pr_debug("Bad size: %d\n", len);
+                ret = -EINVAL;
+                goto fail;
+        }
+
+        if (!fl_table) {
+                pr_debug("Null page table\n");
+                ret = -EINVAL;
+                goto fail;
+        }
+
+        fl_offset = FL_OFFSET(va);      /* Upper 12 bits */
+        fl_pte = fl_table + fl_offset;  /* int pointers, 4 bytes */
+
+        if (len == SZ_16M) {
+                int i = 0;
+                for (i = 0; i < 16; i++)
+                        *(fl_pte+i) = (pa & 0xFF000000) | FL_SUPERSECTION |
+                                  FL_AP_READ | FL_AP_WRITE | FL_TYPE_SECT |
+                                  FL_SHARED;
+        }
+
+        if (len == SZ_1M)
+                *fl_pte = (pa & 0xFFF00000) | FL_AP_READ | FL_AP_WRITE |
+                                                FL_TYPE_SECT | FL_SHARED;
+
+        /* Need a 2nd level table */
+        if ((len == SZ_4K || len == SZ_64K) && (*fl_pte) == 0) {
+                unsigned long *sl;
+                sl = (unsigned long *) __get_free_pages(GFP_KERNEL,
+                                                        get_order(SZ_4K));
+
+                if (!sl) {
+                        pr_debug("Could not allocate second level table\n");
+                        ret = -ENOMEM;
+                        goto fail;
+                }
+
+                memset(sl, 0, SZ_4K);
+                *fl_pte = ((((int)__pa(sl)) & FL_BASE_MASK) | FL_TYPE_TABLE);
+        }
+
+        sl_table = (unsigned long *) __va(((*fl_pte) & FL_BASE_MASK));
+        sl_offset = SL_OFFSET(va);
+        sl_pte = sl_table + sl_offset;
+
+
+        if (len == SZ_4K)
+                *sl_pte = (pa & SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 |
+                                          SL_SHARED | SL_TYPE_SMALL;
+
+        if (len == SZ_64K) {
+                int i;
+
+                for (i = 0; i < 16; i++)
+                        *(sl_pte+i) = (pa & SL_BASE_MASK_LARGE) | SL_AP0 |
+                                            SL_AP1 | SL_SHARED | SL_TYPE_LARGE;
+        }
+
+        __flush_iotlb(domain);
+fail:
+        spin_unlock_irqrestore(&msm_iommu_lock, flags);
+        return ret;
+}
+
+static int msm_iommu_unmap(struct iommu_domain *domain, unsigned long va,
+                            int order)
+{
+        struct msm_priv *priv;
+        unsigned long flags;
+        unsigned long *fl_table;
+        unsigned long *fl_pte;
+        unsigned long fl_offset;
+        unsigned long *sl_table;
+        unsigned long *sl_pte;
+        unsigned long sl_offset;
+        size_t len = 0x1000UL << order;
+        int i, ret = 0;
+
+        spin_lock_irqsave(&msm_iommu_lock, flags);
+
+        priv = domain->priv;
+
+        if (!priv) {
+                ret = -ENODEV;
+                goto fail;
+        }
+
+        fl_table = priv->pgtable;
+
+        if (len != SZ_16M && len != SZ_1M &&
+            len != SZ_64K && len != SZ_4K) {
+                pr_debug("Bad length: %d\n", len);
+                ret = -EINVAL;
+                goto fail;
+        }
+
+        if (!fl_table) {
+                pr_debug("Null page table\n");
+                ret = -EINVAL;
+                goto fail;
+        }
+
+        fl_offset = FL_OFFSET(va);      /* Upper 12 bits */
+        fl_pte = fl_table + fl_offset;  /* int pointers, 4 bytes */
+
+        if (*fl_pte == 0) {
+                pr_debug("First level PTE is 0\n");
+                ret = -ENODEV;
+                goto fail;
+        }
+
+        /* Unmap supersection */
+        if (len == SZ_16M)
+                for (i = 0; i < 16; i++)
+                        *(fl_pte+i) = 0;
+
+        if (len == SZ_1M)
+                *fl_pte = 0;
+
+        sl_table = (unsigned long *) __va(((*fl_pte) & FL_BASE_MASK));
+        sl_offset = SL_OFFSET(va);
+        sl_pte = sl_table + sl_offset;
+
+        if (len == SZ_64K) {
+                for (i = 0; i < 16; i++)
+                        *(sl_pte+i) = 0;
+        }
+
+        if (len == SZ_4K)
+                *sl_pte = 0;
+
+        if (len == SZ_4K || len == SZ_64K) {
+                int used = 0;
+
+                for (i = 0; i < NUM_SL_PTE; i++)
+                        if (sl_table[i])
+                                used = 1;
+                if (!used) {
+                        free_page((unsigned long)sl_table);
+                        *fl_pte = 0;
+                }
+        }
+
+        __flush_iotlb(domain);
+fail:
+        spin_unlock_irqrestore(&msm_iommu_lock, flags);
+        return ret;
+}
+
+static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
+                                          unsigned long va)
+{
+        struct msm_priv *priv;
+        struct msm_iommu_drvdata *iommu_drvdata;
+        struct msm_iommu_ctx_drvdata *ctx_drvdata;
+        unsigned int par;
+        unsigned long flags;
+        void __iomem *base;
+        phys_addr_t ret = 0;
+        int ctx;
+
+        spin_lock_irqsave(&msm_iommu_lock, flags);
+
+        priv = domain->priv;
+        if (list_empty(&priv->list_attached))
+                goto fail;
+
+        ctx_drvdata = list_entry(priv->list_attached.next,
+                                 struct msm_iommu_ctx_drvdata, attached_elm);
+        iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
+
+        base = iommu_drvdata->base;
+        ctx = ctx_drvdata->num;
+
+        /* Invalidate context TLB */
+        SET_CTX_TLBIALL(base, ctx, 0);
+        SET_V2PPR_VA(base, ctx, va >> V2Pxx_VA_SHIFT);
+
+        if (GET_FAULT(base, ctx))
+                goto fail;
+
+        par = GET_PAR(base, ctx);
+
+        /* We are dealing with a supersection */
+        if (GET_NOFAULT_SS(base, ctx))
+                ret = (par & 0xFF000000) | (va & 0x00FFFFFF);
+        else    /* Upper 20 bits from PAR, lower 12 from VA */
+                ret = (par & 0xFFFFF000) | (va & 0x00000FFF);
+
+fail:
+        spin_unlock_irqrestore(&msm_iommu_lock, flags);
+        return ret;
+}
+
+static int msm_iommu_domain_has_cap(struct iommu_domain *domain,
+                                    unsigned long cap)
+{
+        return 0;
+}
+
+static void print_ctx_regs(void __iomem *base, int ctx)
+{
+        unsigned int fsr = GET_FSR(base, ctx);
+        pr_err("FAR    = %08x    PAR    = %08x\n",
+               GET_FAR(base, ctx), GET_PAR(base, ctx));
+        pr_err("FSR    = %08x [%s%s%s%s%s%s%s%s%s%s]\n", fsr,
+                        (fsr & 0x02) ? "TF " : "",
+                        (fsr & 0x04) ? "AFF " : "",
+                        (fsr & 0x08) ? "APF " : "",
+                        (fsr & 0x10) ? "TLBMF " : "",
+                        (fsr & 0x20) ? "HTWDEEF " : "",
+                        (fsr & 0x40) ? "HTWSEEF " : "",
+                        (fsr & 0x80) ? "MHF " : "",
+                        (fsr & 0x10000) ? "SL " : "",
+                        (fsr & 0x40000000) ? "SS " : "",
+                        (fsr & 0x80000000) ? "MULTI " : "");
+
+        pr_err("FSYNR0 = %08x    FSYNR1 = %08x\n",
+               GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx));
+        pr_err("TTBR0  = %08x    TTBR1  = %08x\n",
+               GET_TTBR0(base, ctx), GET_TTBR1(base, ctx));
+        pr_err("SCTLR  = %08x    ACTLR  = %08x\n",
+               GET_SCTLR(base, ctx), GET_ACTLR(base, ctx));
+        pr_err("PRRR   = %08x    NMRR   = %08x\n",
+               GET_PRRR(base, ctx), GET_NMRR(base, ctx));
+}
+
+irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
+{
+        struct msm_iommu_drvdata *drvdata = dev_id;
+        void __iomem *base;
+        unsigned int fsr = 0;
+        int ncb = 0, i = 0;
+
+        spin_lock(&msm_iommu_lock);
+
+        if (!drvdata) {
+                pr_err("Invalid device ID in context interrupt handler\n");
+                goto fail;
+        }
+
+        base = drvdata->base;
+
+        pr_err("===== WOAH! =====\n");
+        pr_err("Unexpected IOMMU page fault!\n");
+        pr_err("base = %08x\n", (unsigned int) base);
+
+        ncb = GET_NCB(base)+1;
+        for (i = 0; i < ncb; i++) {
+                fsr = GET_FSR(base, i);
+                if (fsr) {
+                        pr_err("Fault occurred in context %d.\n", i);
+                        pr_err("Interesting registers:\n");
+                        print_ctx_regs(base, i);
+                        SET_FSR(base, i, 0x4000000F);
+                }
+        }
+fail:
+        spin_unlock(&msm_iommu_lock);
+        return 0;
+}
+
+static struct iommu_ops msm_iommu_ops = {
+        .domain_init = msm_iommu_domain_init,
+        .domain_destroy = msm_iommu_domain_destroy,
+        .attach_dev = msm_iommu_attach_dev,
+        .detach_dev = msm_iommu_detach_dev,
+        .map = msm_iommu_map,
+        .unmap = msm_iommu_unmap,
+        .iova_to_phys = msm_iommu_iova_to_phys,
+        .domain_has_cap = msm_iommu_domain_has_cap
+};
+
+static int msm_iommu_init(void)
+{
+        register_iommu(&msm_iommu_ops);
+        return 0;
+}
+
+subsys_initcall(msm_iommu_init);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");
diff --git a/arch/arm/mach-msm/iommu_dev.c b/arch/arm/mach-msm/iommu_dev.c
new file mode 100644
index 000000000000..c33ae786c41f
--- /dev/null
+++ b/arch/arm/mach-msm/iommu_dev.c
@@ -0,0 +1,374 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#define pr_fmt(fmt)     KBUILD_MODNAME ": " fmt
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/iommu.h>
+#include <linux/interrupt.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+
+#include <mach/iommu_hw-8xxx.h>
+#include <mach/iommu.h>
+
+struct iommu_ctx_iter_data {
+        /* input */
+        const char *name;
+
+        /* output */
+        struct device *dev;
+};
+
+static struct platform_device *msm_iommu_root_dev;
+
+static int each_iommu_ctx(struct device *dev, void *data)
+{
+        struct iommu_ctx_iter_data *res = data;
+        struct msm_iommu_ctx_dev *c = dev->platform_data;
+
+        if (!res || !c || !c->name || !res->name)
+                return -EINVAL;
+
+        if (!strcmp(res->name, c->name)) {
+                res->dev = dev;
+                return 1;
+        }
+        return 0;
+}
+
+static int each_iommu(struct device *dev, void *data)
+{
+        return device_for_each_child(dev, data, each_iommu_ctx);
+}
+
+struct device *msm_iommu_get_ctx(const char *ctx_name)
+{
+        struct iommu_ctx_iter_data r;
+        int found;
+
+        if (!msm_iommu_root_dev) {
+                pr_err("No root IOMMU device.\n");
+                goto fail;
+        }
+
+        r.name = ctx_name;
+        found = device_for_each_child(&msm_iommu_root_dev->dev, &r, each_iommu);
+
+        if (!found) {
+                pr_err("Could not find context <%s>\n", ctx_name);
+                goto fail;
+        }
+
+        return r.dev;
+fail:
+        return NULL;
+}
+EXPORT_SYMBOL(msm_iommu_get_ctx);
+
+static void msm_iommu_reset(void __iomem *base)
+{
+        int ctx, ncb;
+
+        SET_RPUE(base, 0);
+        SET_RPUEIE(base, 0);
+        SET_ESRRESTORE(base, 0);
+        SET_TBE(base, 0);
+        SET_CR(base, 0);
+        SET_SPDMBE(base, 0);
+        SET_TESTBUSCR(base, 0);
+        SET_TLBRSW(base, 0);
+        SET_GLOBAL_TLBIALL(base, 0);
+        SET_RPU_ACR(base, 0);
+        SET_TLBLKCRWE(base, 1);
+        ncb = GET_NCB(base)+1;
+
+        for (ctx = 0; ctx < ncb; ctx++) {
+                SET_BPRCOSH(base, ctx, 0);
+                SET_BPRCISH(base, ctx, 0);
+                SET_BPRCNSH(base, ctx, 0);
+                SET_BPSHCFG(base, ctx, 0);
+                SET_BPMTCFG(base, ctx, 0);
+                SET_ACTLR(base, ctx, 0);
+                SET_SCTLR(base, ctx, 0);
+                SET_FSRRESTORE(base, ctx, 0);
+                SET_TTBR0(base, ctx, 0);
+                SET_TTBR1(base, ctx, 0);
+                SET_TTBCR(base, ctx, 0);
+                SET_BFBCR(base, ctx, 0);
+                SET_PAR(base, ctx, 0);
+                SET_FAR(base, ctx, 0);
+                SET_CTX_TLBIALL(base, ctx, 0);
+                SET_TLBFLPTER(base, ctx, 0);
+                SET_TLBSLPTER(base, ctx, 0);
+                SET_TLBLKCR(base, ctx, 0);
+                SET_PRRR(base, ctx, 0);
+                SET_NMRR(base, ctx, 0);
+                SET_CONTEXTIDR(base, ctx, 0);
+        }
+}
+
+static int msm_iommu_probe(struct platform_device *pdev)
+{
+        struct resource *r;
+        struct clk *iommu_clk;
+        struct msm_iommu_drvdata *drvdata;
+        struct msm_iommu_dev *iommu_dev = pdev->dev.platform_data;
+        void __iomem *regs_base;
+        resource_size_t len;
+        int ret = 0, ncb, nm2v, irq;
+
+        if (pdev->id != -1) {
+                drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
+
+                if (!drvdata) {
+                        ret = -ENOMEM;
+                        goto fail;
+                }
+
+                if (!iommu_dev) {
+                        ret = -ENODEV;
+                        goto fail;
+                }
+
+                if (iommu_dev->clk_rate != 0) {
+                        iommu_clk = clk_get(&pdev->dev, "iommu_clk");
+
+                        if (IS_ERR(iommu_clk)) {
+                                ret = -ENODEV;
+                                goto fail;
+                        }
+
+                        if (iommu_dev->clk_rate > 0) {
+                                ret = clk_set_rate(iommu_clk,
+                                                        iommu_dev->clk_rate);
+                                if (ret) {
+                                        clk_put(iommu_clk);
+                                        goto fail;
+                                }
+                        }
+
+                        ret = clk_enable(iommu_clk);
+                        if (ret) {
+                                clk_put(iommu_clk);
+                                goto fail;
+                        }
+                        clk_put(iommu_clk);
+                }
+
+                r = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+                                                 "physbase");
+                if (!r) {
+                        ret = -ENODEV;
+                        goto fail;
+                }
+
+                len = r->end - r->start + 1;
+
+                r = request_mem_region(r->start, len, r->name);
+                if (!r) {
+                        pr_err("Could not request memory region: "
+                        "start=%p, len=%d\n", (void *) r->start, len);
+                        ret = -EBUSY;
+                        goto fail;
+                }
+
+                regs_base = ioremap(r->start, len);
+
+                if (!regs_base) {
+                        pr_err("Could not ioremap: start=%p, len=%d\n",
+                                 (void *) r->start, len);
+                        ret = -EBUSY;
+                        goto fail;
+                }
+
+                irq = platform_get_irq_byname(pdev, "secure_irq");
+                if (irq < 0) {
+                        ret = -ENODEV;
+                        goto fail;
+                }
+
+                mb();
+
+                if (GET_IDR(regs_base) == 0) {
+                        pr_err("Invalid IDR value detected\n");
+                        ret = -ENODEV;
+                        goto fail;
+                }
+
+                ret = request_irq(irq, msm_iommu_fault_handler, 0,
+                                "msm_iommu_secure_irpt_handler", drvdata);
+                if (ret) {
+                        pr_err("Request IRQ %d failed with ret=%d\n", irq, ret);
+                        goto fail;
+                }
+
+                msm_iommu_reset(regs_base);
+                drvdata->base = regs_base;
+                drvdata->irq = irq;
+
+                nm2v = GET_NM2VCBMT((unsigned long) regs_base);
+                ncb = GET_NCB((unsigned long) regs_base);
+
+                pr_info("device %s mapped at %p, irq %d with %d ctx banks\n",
+                        iommu_dev->name, regs_base, irq, ncb+1);
+
+                platform_set_drvdata(pdev, drvdata);
+        } else
+                msm_iommu_root_dev = pdev;
+
+        return 0;
+
+fail:
+        kfree(drvdata);
+        return ret;
+}
+
+static int msm_iommu_remove(struct platform_device *pdev)
+{
+        struct msm_iommu_drvdata *drv = NULL;
+
+        drv = platform_get_drvdata(pdev);
+        if (drv) {
+                memset(drv, 0, sizeof(struct msm_iommu_drvdata));
+                kfree(drv);
+                platform_set_drvdata(pdev, NULL);
+        }
+        return 0;
+}
+
+static int msm_iommu_ctx_probe(struct platform_device *pdev)
+{
+        struct msm_iommu_ctx_dev *c = pdev->dev.platform_data;
+        struct msm_iommu_drvdata *drvdata;
+        struct msm_iommu_ctx_drvdata *ctx_drvdata = NULL;
+        int i, ret = 0;
+        if (!c || !pdev->dev.parent) {
+                ret = -EINVAL;
+                goto fail;
+        }
+
+        drvdata = dev_get_drvdata(pdev->dev.parent);
+
+        if (!drvdata) {
+                ret = -ENODEV;
+                goto fail;
+        }
+
+        ctx_drvdata = kzalloc(sizeof(*ctx_drvdata), GFP_KERNEL);
+        if (!ctx_drvdata) {
+                ret = -ENOMEM;
+                goto fail;
+        }
+        ctx_drvdata->num = c->num;
+        ctx_drvdata->pdev = pdev;
+
+        INIT_LIST_HEAD(&ctx_drvdata->attached_elm);
+        platform_set_drvdata(pdev, ctx_drvdata);
+
+        /* Program the M2V tables for this context */
+        for (i = 0; i < MAX_NUM_MIDS; i++) {
+                int mid = c->mids[i];
+                if (mid == -1)
+                        break;
+
+                SET_M2VCBR_N(drvdata->base, mid, 0);
+                SET_CBACR_N(drvdata->base, c->num, 0);
+
+                /* Set VMID = MID */
+                SET_VMID(drvdata->base, mid, mid);
+
+                /* Set the context number for that MID to this context */
+                SET_CBNDX(drvdata->base, mid, c->num);
+
+                /* Set MID associated with this context bank */
+                SET_CBVMID(drvdata->base, c->num, mid);
+
+                /* Set security bit override to be Non-secure */
+                SET_NSCFG(drvdata->base, mid, 3);
+        }
+
+        pr_info("context device %s with bank index %d\n", c->name, c->num);
+
+        return 0;
+fail:
+        kfree(ctx_drvdata);
+        return ret;
+}
+
+static int msm_iommu_ctx_remove(struct platform_device *pdev)
+{
+        struct msm_iommu_ctx_drvdata *drv = NULL;
+        drv = platform_get_drvdata(pdev);
+        if (drv) {
+                memset(drv, 0, sizeof(struct msm_iommu_ctx_drvdata));
+                kfree(drv);
+                platform_set_drvdata(pdev, NULL);
+        }
+        return 0;
+}
+
+static struct platform_driver msm_iommu_driver = {
+        .driver = {
+                .name   = "msm_iommu",
+        },
+        .probe          = msm_iommu_probe,
+        .remove         = msm_iommu_remove,
+};
+
+static struct platform_driver msm_iommu_ctx_driver = {
+        .driver = {
+                .name   = "msm_iommu_ctx",
+        },
+        .probe          = msm_iommu_ctx_probe,
+        .remove         = msm_iommu_ctx_remove,
+};
+
+static int msm_iommu_driver_init(void)
+{
+        int ret;
+        ret = platform_driver_register(&msm_iommu_driver);
+        if (ret != 0) {
+                pr_err("Failed to register IOMMU driver\n");
+                goto error;
+        }
+
+        ret = platform_driver_register(&msm_iommu_ctx_driver);
+        if (ret != 0) {
+                pr_err("Failed to register IOMMU context driver\n");
+                goto error;
+        }
+
+error:
+        return ret;
+}
+
+static void msm_iommu_driver_exit(void)
+{
+        platform_driver_unregister(&msm_iommu_ctx_driver);
+        platform_driver_unregister(&msm_iommu_driver);
+}
+
+subsys_initcall(msm_iommu_driver_init);
+module_exit(msm_iommu_driver_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index dec5ca622d7d..7689848ec680 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -28,7 +28,6 @@
 #ifndef MSM_DGT_BASE
 #define MSM_DGT_BASE (MSM_GPT_BASE + 0x10)
 #endif
-#define MSM_DGT_SHIFT (5)
 
 #define TIMER_MATCH_VAL         0x0000
 #define TIMER_COUNT_VAL         0x0004
@@ -36,12 +35,28 @@
 #define TIMER_ENABLE_CLR_ON_MATCH_EN    2
 #define TIMER_ENABLE_EN                 1
 #define TIMER_CLEAR             0x000C
-
+#define DGT_CLK_CTL             0x0034
+enum {
+        DGT_CLK_CTL_DIV_1 = 0,
+        DGT_CLK_CTL_DIV_2 = 1,
+        DGT_CLK_CTL_DIV_3 = 2,
+        DGT_CLK_CTL_DIV_4 = 3,
+};
 #define CSR_PROTECTION          0x0020
 #define CSR_PROTECTION_EN               1
 
 #define GPT_HZ 32768
+
+#if defined(CONFIG_ARCH_QSD8X50)
+#define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
+#define MSM_DGT_SHIFT (0)
+#elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60)
+#define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
+#define MSM_DGT_SHIFT (0)
+#else
 #define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */
+#define MSM_DGT_SHIFT (5)
+#endif
 
 struct msm_clock {
         struct clock_event_device   clockevent;
@@ -170,6 +185,10 @@ static void __init msm_timer_init(void)
         int i;
         int res;
 
+#ifdef CONFIG_ARCH_MSM8X60
+        writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
+#endif
+
         for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) {
                 struct msm_clock *clock = &msm_clocks[i];
                 struct clock_event_device *ce = &clock->clockevent;
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index 2d37785e3857..eaacb6e9b5d0 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -70,6 +70,25 @@ int mx51_revision(void)
 }
 EXPORT_SYMBOL(mx51_revision);
 
+#ifdef CONFIG_NEON
+
+/*
+ * All versions of the silicon before Rev. 3 have broken NEON implementations.
+ * Dependent on link order - so the assumption is that vfp_init is called
+ * before us.
+ */
+static int __init mx51_neon_fixup(void)
+{
+        if (mx51_revision() < MX51_CHIP_REV_3_0 && (elf_hwcap & HWCAP_NEON)) {
+                elf_hwcap &= ~HWCAP_NEON;
+                pr_info("Turning off NEON support, detected broken NEON implementation\n");
+        }
+        return 0;
+}
+
+late_initcall(mx51_neon_fixup);
+#endif
+
 static int __init post_cpu_init(void)
 {
         unsigned int reg;
diff --git a/arch/arm/mach-netx/include/mach/vmalloc.h b/arch/arm/mach-netx/include/mach/vmalloc.h
index 25d5cc676e0f..7cca3574308f 100644
--- a/arch/arm/mach-netx/include/mach/vmalloc.h
+++ b/arch/arm/mach-netx/include/mach/vmalloc.h
@@ -16,4 +16,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END       0xd0000000
diff --git a/arch/arm/mach-omap1/include/mach/vmalloc.h b/arch/arm/mach-omap1/include/mach/vmalloc.h
index 1b2af14df151..b001f67d695b 100644
--- a/arch/arm/mach-omap1/include/mach/vmalloc.h
+++ b/arch/arm/mach-omap1/include/mach/vmalloc.h
@@ -17,4 +17,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  */
-#define VMALLOC_END     (PAGE_OFFSET + 0x18000000)
+#define VMALLOC_END     0xd8000000
diff --git a/arch/arm/mach-omap2/include/mach/vmalloc.h b/arch/arm/mach-omap2/include/mach/vmalloc.h
index 9ce9b6e8ad23..4da31e997efe 100644
--- a/arch/arm/mach-omap2/include/mach/vmalloc.h
+++ b/arch/arm/mach-omap2/include/mach/vmalloc.h
@@ -17,4 +17,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x38000000)
+#define VMALLOC_END       0xf8000000
diff --git a/arch/arm/mach-pnx4008/include/mach/vmalloc.h b/arch/arm/mach-pnx4008/include/mach/vmalloc.h
index 2ad398378aed..31b65ee07b0b 100644
--- a/arch/arm/mach-pnx4008/include/mach/vmalloc.h
+++ b/arch/arm/mach-pnx4008/include/mach/vmalloc.h
@@ -17,4 +17,4 @@
  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
  * area for the same reason. ;)
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END       0xd0000000
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 7aefb9074852..dd235ecc9d6c 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -8,19 +8,16 @@ config ARCH_LUBBOCK
         bool "Intel DBPXA250 Development Platform (aka Lubbock)"
         select PXA25x
         select SA1111
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_MAINSTONE
         bool "Intel HCDDBBVA0 Development Platform (aka Mainstone)"
         select PXA27x
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_ZYLONITE
         bool
         select PXA3xx
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_ZYLONITE300
         bool "PXA3xx Development Platform (aka Zylonite) PXA300/310"
@@ -44,6 +41,10 @@ config MACH_TAVOREVB
         select PXA3xx
         select CPU_PXA930
 
+config MACH_TAVOREVB3
+        bool "PXA95x Development Platform (aka TavorEVB III)"
+        select CPU_PXA950
+
 config MACH_SAAR
         bool "PXA930 Handheld Platform (aka SAAR)"
         select PXA3xx
@@ -61,7 +62,6 @@ config ARCH_VIPER
         select ISA
         select I2C_GPIO
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
         select PXA_HAVE_ISA_IRQS
         select ARCOM_PCMCIA
 
@@ -69,7 +69,6 @@ config MACH_ARCOM_ZEUS
         bool "Arcom/Eurotech ZEUS SBC"
         select PXA27x
         select ISA
-        select PXA_HAVE_BOARD_IRQS
         select PXA_HAVE_ISA_IRQS
         select ARCOM_PCMCIA
 
@@ -77,7 +76,6 @@ config MACH_BALLOON3
         bool "Balloon 3 board"
         select PXA27x
         select IWMMXT
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_CSB726
         bool "Enable Cogent CSB726 System On a Module"
@@ -140,13 +138,11 @@ config MACH_INTELMOTE2
         bool "Intel Mote 2 Platform"
         select PXA27x
         select IWMMXT
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_STARGATE2
         bool "Intel Stargate 2 Platform"
         select PXA27x
         select IWMMXT
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_XCEP
         bool "Iskratel Electronics XCEP"
@@ -206,13 +202,11 @@ config MACH_LOGICPD_PXA270
         bool "LogicPD PXA270 Card Engine Development Platform"
         select PXA27x
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_PCM027
         bool "Phytec phyCORE-PXA270 CPU module (PCM-027)"
         select PXA27x
         select IWMMXT
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_PCM990_BASEBOARD
         bool "PHYTEC PCM-990 development board"
@@ -247,7 +241,6 @@ config MACH_COLIBRI_PXA270_INCOME
         depends on MACH_COLIBRI
         select PXA27x
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_COLIBRI300
         bool "Toradex Colibri PXA300/310"
@@ -274,7 +267,6 @@ config MACH_H4700
         select PXA27x
         select IWMMXT
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_H5000
         bool "HP iPAQ h5000"
@@ -289,7 +281,6 @@ config MACH_MAGICIAN
         select PXA27x
         select IWMMXT
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_MIOA701
         bool "Mitac Mio A701 Support"
@@ -307,7 +298,6 @@ config PXA_EZX
         select PXA27x
         select IWMMXT
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_EZX_A780
         bool "Motorola EZX A780"
@@ -478,7 +468,6 @@ config MACH_POODLE
         depends on PXA_SHARPSL
         select PXA25x
         select SHARP_LOCOMO
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_CORGI
         bool "Enable Sharp SL-C700 (Corgi) Support"
@@ -523,7 +512,6 @@ config MACH_TOSA
         bool "Enable Sharp SL-6000x (Tosa) Support"
         depends on PXA_SHARPSL
         select PXA25x
-        select PXA_HAVE_BOARD_IRQS
 
 config TOSA_BT
         tristate "Control the state of built-in bluetooth chip on Sharp SL-6000"
@@ -552,7 +540,6 @@ config MACH_ICONTROL
 config ARCH_PXA_ESERIES
         bool "PXA based Toshiba e-series PDAs"
         select PXA25x
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_E330
         bool "Toshiba e330"
@@ -606,7 +593,6 @@ config MACH_ZIPIT2
         bool "Zipit Z2 Handheld"
         select PXA27x
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 endmenu
 
@@ -643,6 +629,7 @@ config CPU_PXA300
 config CPU_PXA310
         bool
         select CPU_PXA300
+        select PXA310_ULPI if USB_ULPI
         help
           PXA310 (codename Monahans-LV)
 
@@ -692,10 +679,10 @@ config SHARPSL_PM_MAX1111
         select HWMON
         select SENSORS_MAX1111
 
-config PXA_HAVE_BOARD_IRQS
+config PXA_HAVE_ISA_IRQS
         bool
 
-config PXA_HAVE_ISA_IRQS
+config PXA310_ULPI
         bool
 
 endif
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 85c7fb324dbb..e2f89c2c6f49 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -18,7 +18,7 @@ endif
 # SoC-specific code
 obj-$(CONFIG_PXA25x)            += mfp-pxa2xx.o pxa2xx.o pxa25x.o
 obj-$(CONFIG_PXA27x)            += mfp-pxa2xx.o pxa2xx.o pxa27x.o
-obj-$(CONFIG_PXA3xx)            += mfp-pxa3xx.o pxa3xx.o smemc.o
+obj-$(CONFIG_PXA3xx)            += mfp-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
 obj-$(CONFIG_CPU_PXA300)        += pxa300.o
 obj-$(CONFIG_CPU_PXA320)        += pxa320.o
 obj-$(CONFIG_CPU_PXA930)        += pxa930.o
@@ -32,6 +32,7 @@ obj-$(CONFIG_MACH_ZYLONITE300)	+= zylonite.o zylonite_pxa300.o
 obj-$(CONFIG_MACH_ZYLONITE320)  += zylonite.o zylonite_pxa320.o
 obj-$(CONFIG_MACH_LITTLETON)    += littleton.o
 obj-$(CONFIG_MACH_TAVOREVB)     += tavorevb.o
+obj-$(CONFIG_MACH_TAVOREVB3)    += tavorevb3.o
 obj-$(CONFIG_MACH_SAAR)         += saar.o
 
 # 3rd Party Dev Platforms
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index 9041340fee1d..79d0f6cf53d7 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -68,42 +68,6 @@ static unsigned long balloon3_pin_config[] __initdata = {
 
         /* Reset, configured as GPIO wakeup source */
         GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
-
-        /* LEDs */
-        GPIO9_GPIO,     /* NAND activity LED */
-        GPIO10_GPIO,    /* Heartbeat LED */
-
-        /* AC97 */
-        GPIO28_AC97_BITCLK,
-        GPIO29_AC97_SDATA_IN_0,
-        GPIO30_AC97_SDATA_OUT,
-        GPIO31_AC97_SYNC,
-        GPIO113_AC97_nRESET,
-        GPIO95_GPIO,
-
-        /* MMC */
-        GPIO32_MMC_CLK,
-        GPIO92_MMC_DAT_0,
-        GPIO109_MMC_DAT_1,
-        GPIO110_MMC_DAT_2,
-        GPIO111_MMC_DAT_3,
-        GPIO112_MMC_CMD,
-
-        /* USB Host */
-        GPIO88_USBH1_PWR,
-        GPIO89_USBH1_PEN,
-
-        /* PC Card */
-        GPIO48_nPOE,
-        GPIO49_nPWE,
-        GPIO50_nPIOR,
-        GPIO51_nPIOW,
-        GPIO85_nPCE_1,
-        GPIO54_nPCE_2,
-        GPIO79_PSKTSEL,
-        GPIO55_nPREG,
-        GPIO56_nPWAIT,
-        GPIO57_nIOIS16,
 };
 
 /******************************************************************************
@@ -132,6 +96,34 @@ int __init parse_balloon3_features(char *arg)
 early_param("balloon3_features", parse_balloon3_features);
 
 /******************************************************************************
+ * Compact Flash slot
+ ******************************************************************************/
+#if     defined(CONFIG_PCMCIA_PXA2XX) || defined(CONFIG_PCMCIA_PXA2XX_MODULE)
+static unsigned long balloon3_cf_pin_config[] __initdata = {
+        GPIO48_nPOE,
+        GPIO49_nPWE,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO85_nPCE_1,
+        GPIO54_nPCE_2,
+        GPIO79_PSKTSEL,
+        GPIO55_nPREG,
+        GPIO56_nPWAIT,
+        GPIO57_nIOIS16,
+};
+
+static void __init balloon3_cf_init(void)
+{
+        if (!balloon3_has(BALLOON3_FEATURE_CF))
+                return;
+
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_cf_pin_config));
+}
+#else
+static inline void balloon3_cf_init(void) {}
+#endif
+
+/******************************************************************************
  * NOR Flash
  ******************************************************************************/
 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
@@ -179,6 +171,15 @@ static inline void balloon3_nor_init(void) {}
  ******************************************************************************/
 #if     defined(CONFIG_TOUCHSCREEN_UCB1400) || \
         defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE)
+static unsigned long balloon3_ac97_pin_config[] __initdata = {
+        GPIO28_AC97_BITCLK,
+        GPIO29_AC97_SDATA_IN_0,
+        GPIO30_AC97_SDATA_OUT,
+        GPIO31_AC97_SYNC,
+        GPIO113_AC97_nRESET,
+        GPIO95_GPIO,
+};
+
 static struct ucb1400_pdata vpac270_ucb1400_pdata = {
         .irq            = IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ),
 };
@@ -197,6 +198,7 @@ static void __init balloon3_ts_init(void)
         if (!balloon3_has(BALLOON3_FEATURE_AUDIO))
                 return;
 
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_ac97_pin_config));
         pxa_set_ac97_info(NULL);
         platform_device_register(&balloon3_ucb1400_device);
 }
@@ -208,6 +210,11 @@ static inline void balloon3_ts_init(void) {}
  * Framebuffer
  ******************************************************************************/
 #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
+static unsigned long balloon3_lcd_pin_config[] __initdata = {
+        GPIOxx_LCD_TFT_16BPP,
+        GPIO99_GPIO,
+};
+
 static struct pxafb_mode_info balloon3_lcd_modes[] = {
         {
                 .pixclock               = 38000,
@@ -242,6 +249,8 @@ static void __init balloon3_lcd_init(void)
         if (!balloon3_has(BALLOON3_FEATURE_TOPPOLY))
                 return;
 
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_lcd_pin_config));
+
         ret = gpio_request(BALLOON3_GPIO_RUN_BACKLIGHT, "BKL-ON");
         if (ret) {
                 pr_err("Requesting BKL-ON GPIO failed!\n");
@@ -271,6 +280,15 @@ static inline void balloon3_lcd_init(void) {}
  * SD/MMC card controller
  ******************************************************************************/
 #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
+static unsigned long balloon3_mmc_pin_config[] __initdata = {
+        GPIO32_MMC_CLK,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+        GPIO112_MMC_CMD,
+};
+
 static struct pxamci_platform_data balloon3_mci_platform_data = {
         .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
         .gpio_card_detect       = -1,
@@ -281,6 +299,7 @@ static struct pxamci_platform_data balloon3_mci_platform_data = {
 
 static void __init balloon3_mmc_init(void)
 {
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_mmc_pin_config));
         pxa_set_mci_info(&balloon3_mci_platform_data);
 }
 #else
@@ -339,6 +358,11 @@ static inline void balloon3_irda_init(void) {}
  * USB Host
  ******************************************************************************/
 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static unsigned long balloon3_uhc_pin_config[] __initdata = {
+        GPIO88_USBH1_PWR,
+        GPIO89_USBH1_PEN,
+};
+
 static struct pxaohci_platform_data balloon3_ohci_info = {
         .port_mode      = PMM_PERPORT_MODE,
         .flags          = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
@@ -348,6 +372,7 @@ static void __init balloon3_uhc_init(void)
 {
         if (!balloon3_has(BALLOON3_FEATURE_OHCI))
                 return;
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_uhc_pin_config));
         pxa_set_ohci_info(&balloon3_ohci_info);
 }
 #else
@@ -358,6 +383,11 @@ static inline void balloon3_uhc_init(void) {}
  * LEDs
  ******************************************************************************/
 #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+static unsigned long balloon3_led_pin_config[] __initdata = {
+        GPIO9_GPIO,     /* NAND activity LED */
+        GPIO10_GPIO,    /* Heartbeat LED */
+};
+
 struct gpio_led balloon3_gpio_leds[] = {
         {
                 .name                   = "balloon3:green:idle",
@@ -436,6 +466,7 @@ static struct platform_device balloon3_pcf_leds = {
 
 static void __init balloon3_leds_init(void)
 {
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_led_pin_config));
         platform_device_register(&balloon3_leds);
         platform_device_register(&balloon3_pcf_leds);
 }
@@ -757,6 +788,7 @@ static void __init balloon3_init(void)
         balloon3_ts_init();
         balloon3_udc_init();
         balloon3_uhc_init();
+        balloon3_cf_init();
 }
 
 static struct map_desc balloon3_io_desc[] __initdata = {
@@ -779,6 +811,7 @@ MACHINE_START(BALLOON3, "Balloon3")
         .phys_io        = 0x40000000,
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = balloon3_map_io,
+        .nr_irqs        = BALLOON3_NR_IRQS,
         .init_irq       = balloon3_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = balloon3_init,
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
index bff6e78f033d..ad40e7b141e0 100644
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -33,6 +33,9 @@
 extern void cmx255_init(void);
 extern void cmx270_init(void);
 
+/* reserve IRQs for IT8152 */
+#define CMX2XX_NR_IRQS          (IRQ_BOARD_START + 40)
+
 /* virtual addresses for statically mapped regions */
 #define CMX2XX_VIRT_BASE        (0xe8000000)
 #define CMX2XX_IT8152_VIRT      (CMX2XX_VIRT_BASE)
@@ -514,6 +517,7 @@ MACHINE_START(ARMCORE, "Compulab CM-X2XX")
         .phys_io        = 0x40000000,
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = cmx2xx_map_io,
+        .nr_irqs        = CMX2XX_NR_IRQS,
         .init_irq       = cmx2xx_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = cmx2xx_init,
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index c70e6c2f4e7c..8e0b5622b277 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -19,6 +19,7 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/platform_device.h>
+#include <linux/clk.h>
 
 #include <linux/gpio.h>
 #include <linux/dm9000.h>
@@ -50,6 +51,7 @@
 #include <plat/i2c.h>
 #include <plat/pxa3xx_nand.h>
 #include <mach/audio.h>
+#include <mach/pxa3xx-u2d.h>
 
 #include <asm/mach/map.h>
 
@@ -68,6 +70,8 @@
 #define GPIO97_RTC_RD           (97)
 #define GPIO98_RTC_IO           (98)
 
+#define GPIO_ULPI_PHY_RST       (127)
+
 static mfp_cfg_t cm_x3xx_mfp_cfg[] __initdata = {
         /* LCD */
         GPIO54_LCD_LDD_0,
@@ -472,6 +476,78 @@ static void __init cm_x300_init_mmc(void)
 static inline void cm_x300_init_mmc(void) {}
 #endif
 
+#if defined(CONFIG_PXA310_ULPI)
+static struct clk *pout_clk;
+
+static int cm_x300_ulpi_phy_reset(void)
+{
+        int err;
+
+        /* reset the PHY */
+        err = gpio_request(GPIO_ULPI_PHY_RST, "ulpi reset");
+        if (err) {
+                pr_err("%s: failed to request ULPI reset GPIO: %d\n",
+                       __func__, err);
+                return err;
+        }
+
+        gpio_direction_output(GPIO_ULPI_PHY_RST, 0);
+        msleep(10);
+        gpio_set_value(GPIO_ULPI_PHY_RST, 1);
+        msleep(10);
+
+        gpio_free(GPIO_ULPI_PHY_RST);
+
+        return 0;
+}
+
+static inline int cm_x300_u2d_init(struct device *dev)
+{
+        int err = 0;
+
+        if (cpu_is_pxa310()) {
+                /* CLK_POUT is connected to the ULPI PHY */
+                pout_clk = clk_get(NULL, "CLK_POUT");
+                if (IS_ERR(pout_clk)) {
+                        err = PTR_ERR(pout_clk);
+                        pr_err("%s: failed to get CLK_POUT: %d\n",
+                               __func__, err);
+                        return err;
+                }
+                clk_enable(pout_clk);
+
+                err = cm_x300_ulpi_phy_reset();
+                if (err) {
+                        clk_disable(pout_clk);
+                        clk_put(pout_clk);
+                }
+        }
+
+        return err;
+}
+
+static void cm_x300_u2d_exit(struct device *dev)
+{
+        if (cpu_is_pxa310()) {
+                clk_disable(pout_clk);
+                clk_put(pout_clk);
+        }
+}
+
+static struct pxa3xx_u2d_platform_data cm_x300_u2d_platform_data = {
+        .ulpi_mode      = ULPI_SER_6PIN,
+        .init           = cm_x300_u2d_init,
+        .exit           = cm_x300_u2d_exit,
+};
+
+static void cm_x300_init_u2d(void)
+{
+        pxa3xx_set_u2d_info(&cm_x300_u2d_platform_data);
+}
+#else
+static inline void cm_x300_init_u2d(void) {}
+#endif
+
 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
 static int cm_x300_ohci_init(struct device *dev)
 {
@@ -754,6 +830,7 @@ static void __init cm_x300_init(void)
         cm_x300_init_da9030();
         cm_x300_init_dm9000();
         cm_x300_init_lcd();
+        cm_x300_init_u2d();
         cm_x300_init_ohci();
         cm_x300_init_mmc();
         cm_x300_init_nand();
diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
index 50d5939a78f1..58093d9e07be 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
@@ -312,8 +312,7 @@ static int pxa_set_target(struct cpufreq_policy *policy,
         freqs.cpu = policy->cpu;
 
         if (freq_debug)
-                pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, "
-                         "(SDRAM %d Mhz)\n",
+                pr_debug("Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
                          freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
                          (new_freq_mem / 2000) : (new_freq_mem / 1000));
 
diff --git a/arch/arm/mach-pxa/cpufreq-pxa3xx.c b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
index 0a0d0fe99220..88fbec05ec50 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa3xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
@@ -159,7 +159,7 @@ static int pxa3xx_cpufreq_verify(struct cpufreq_policy *policy)
 
 static unsigned int pxa3xx_cpufreq_get(unsigned int cpu)
 {
-        return get_clk_frequency_khz(0);
+        return pxa3xx_get_clk_frequency_khz(0);
 }
 
 static int pxa3xx_cpufreq_set(struct cpufreq_policy *policy,
@@ -212,7 +212,8 @@ static int pxa3xx_cpufreq_init(struct cpufreq_policy *policy)
         policy->cpuinfo.min_freq = 104000;
         policy->cpuinfo.max_freq = (cpu_is_pxa320()) ? 806000 : 624000;
         policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
-        policy->cur = policy->min = policy->max = get_clk_frequency_khz(0);
+        policy->max = pxa3xx_get_clk_frequency_khz(0);
+        policy->cur = policy->min = policy->max;
 
         if (cpu_is_pxa300() || cpu_is_pxa310())
                 ret = setup_freqs_table(policy, ARRAY_AND_SIZE(pxa300_freqs));
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 65447dc736c2..08b410343870 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -6,11 +6,12 @@
 
 #include <asm/pmu.h>
 #include <mach/udc.h>
+#include <mach/pxa3xx-u2d.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
 #include <mach/irda.h>
 #include <mach/ohci.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/pxa2xx_spi.h>
 #include <mach/camera.h>
 #include <mach/audio.h>
@@ -134,6 +135,33 @@ struct platform_device pxa27x_device_udc = {
         }
 };
 
+#ifdef CONFIG_PXA3xx
+static struct resource pxa3xx_u2d_resources[] = {
+        [0] = {
+                .start  = 0x54100000,
+                .end    = 0x54100fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_USB2,
+                .end    = IRQ_USB2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device pxa3xx_device_u2d = {
+        .name           = "pxa3xx-u2d",
+        .id             = -1,
+        .resource       = pxa3xx_u2d_resources,
+        .num_resources  = ARRAY_SIZE(pxa3xx_u2d_resources),
+};
+
+void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
+{
+        pxa_register_device(&pxa3xx_device_u2d, info);
+}
+#endif /* CONFIG_PXA3xx */
+
 static struct resource pxafb_resources[] = {
         [0] = {
                 .start  = 0x44000000,
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index 50353ea49ba4..715e8bd02e24 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -4,6 +4,7 @@ extern struct platform_device pxa3xx_device_mci2;
 extern struct platform_device pxa3xx_device_mci3;
 extern struct platform_device pxa25x_device_udc;
 extern struct platform_device pxa27x_device_udc;
+extern struct platform_device pxa3xx_device_u2d;
 extern struct platform_device pxa_device_fb;
 extern struct platform_device pxa_device_ffuart;
 extern struct platform_device pxa_device_btuart;
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 0517c17978f3..51286a738a3b 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -43,7 +43,7 @@
 #include <mach/pxafb.h>
 #include <mach/ohci.h>
 #include <mach/mmc.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <plat/i2c.h>
 #include <mach/camera.h>
 #include <mach/pxa2xx_spi.h>
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index 349212a1cbd3..4971ce119501 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -29,6 +29,7 @@
 
 #include <mach/pxa25x.h>
 #include <mach/eseries-gpio.h>
+#include <mach/eseries-irq.h>
 #include <mach/audio.h>
 #include <mach/pxafb.h>
 #include <mach/udc.h>
@@ -183,6 +184,7 @@ MACHINE_START(E330, "Toshiba e330")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e330_init,
@@ -233,6 +235,7 @@ MACHINE_START(E350, "Toshiba e350")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e350_init,
@@ -356,6 +359,7 @@ MACHINE_START(E400, "Toshiba e400")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e400_init,
@@ -545,6 +549,7 @@ MACHINE_START(E740, "Toshiba e740")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e740_init,
@@ -737,6 +742,7 @@ MACHINE_START(E750, "Toshiba e750")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e750_init,
@@ -933,6 +939,7 @@ MACHINE_START(E800, "Toshiba e800")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e800_init,
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index 626c82b13970..f997e8455557 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -32,12 +32,14 @@
 #include <mach/ohci.h>
 #include <plat/i2c.h>
 #include <mach/hardware.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/camera.h>
 
 #include "devices.h"
 #include "generic.h"
 
+#define EZX_NR_IRQS                     (IRQ_BOARD_START + 24)
+
 #define GPIO12_A780_FLIP_LID            12
 #define GPIO15_A1200_FLIP_LID           15
 #define GPIO15_A910_FLIP_LID            15
@@ -800,6 +802,7 @@ MACHINE_START(EZX_A780, "Motorola EZX A780")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = a780_init,
@@ -866,6 +869,7 @@ MACHINE_START(EZX_E680, "Motorola EZX E680")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = e680_init,
@@ -932,6 +936,7 @@ MACHINE_START(EZX_A1200, "Motorola EZX A1200")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = a1200_init,
@@ -1124,6 +1129,7 @@ MACHINE_START(EZX_A910, "Motorola EZX A910")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = a910_init,
@@ -1190,6 +1196,7 @@ MACHINE_START(EZX_E6, "Motorola EZX E6")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = e6_init,
@@ -1230,6 +1237,7 @@ MACHINE_START(EZX_E2, "Motorola EZX E2")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = e2_init,
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index baabb3ce088e..6451e9c3a93f 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -66,8 +66,7 @@ unsigned int get_clk_frequency_khz(int info)
                 return pxa25x_get_clk_frequency_khz(info);
         else if (cpu_is_pxa27x())
                 return pxa27x_get_clk_frequency_khz(info);
-        else
-                return pxa3xx_get_clk_frequency_khz(info);
+        return 0;
 }
 EXPORT_SYMBOL(get_clk_frequency_khz);
 
@@ -80,8 +79,7 @@ unsigned int get_memclk_frequency_10khz(void)
                 return pxa25x_get_memclk_frequency_10khz();
         else if (cpu_is_pxa27x())
                 return pxa27x_get_memclk_frequency_10khz();
-        else
-                return pxa3xx_get_memclk_frequency_10khz();
+        return 0;
 }
 EXPORT_SYMBOL(get_memclk_frequency_10khz);
 
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index c6305c5b8a72..4b1ad2769ed7 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -54,11 +54,9 @@ static inline void pxa2xx_clear_reset_status(unsigned int mask) {}
 
 #ifdef CONFIG_PXA3xx
 extern unsigned pxa3xx_get_clk_frequency_khz(int);
-extern unsigned pxa3xx_get_memclk_frequency_10khz(void);
 extern void pxa3xx_clear_reset_status(unsigned int);
 #else
 #define pxa3xx_get_clk_frequency_khz(x)         (0)
-#define pxa3xx_get_memclk_frequency_10khz()     (0)
 static inline void pxa3xx_clear_reset_status(unsigned int mask) {}
 #endif
 
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index 848c861dd23f..10104f16e6e4 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -874,6 +874,7 @@ MACHINE_START(H4700, "HP iPAQ HX4700")
         .io_pg_offst  = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params  = 0xa0000100,
         .map_io       = pxa_map_io,
+        .nr_irqs      = HX4700_NR_IRQS,
         .init_irq     = pxa27x_init_irq,
         .init_machine = hx4700_init,
         .timer        = &pxa_timer,
diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h
index eec92e6fd7cf..561562b4360b 100644
--- a/arch/arm/mach-pxa/include/mach/balloon3.h
+++ b/arch/arm/mach-pxa/include/mach/balloon3.h
@@ -174,6 +174,8 @@ enum balloon3_features {
 #define BALLOON3_CODEC_IRQ      IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ)
 #define BALLOON3_S0_CD_IRQ      IRQ_GPIO(BALLOON3_GPIO_S0_CD)
 
+#define BALLOON3_NR_IRQS        (IRQ_BOARD_START + 4)
+
 extern int balloon3_has(enum balloon3_features feature);
 
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/eseries-irq.h b/arch/arm/mach-pxa/include/mach/eseries-irq.h
index f2a93d5e31d3..de292b269c63 100644
--- a/arch/arm/mach-pxa/include/mach/eseries-irq.h
+++ b/arch/arm/mach-pxa/include/mach/eseries-irq.h
@@ -25,3 +25,4 @@
 #define TMIO_SD_IRQ     IRQ_TMIO(1)
 #define TMIO_USB_IRQ    IRQ_TMIO(2)
 
+#define ESERIES_NR_IRQS (IRQ_BOARD_START + 16)
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index 7f64d24cd564..814f1458a06a 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -264,23 +264,35 @@
  * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
  * == 0x3 for pxa300/pxa310/pxa320
  */
+#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
 #define __cpu_is_pxa2xx(id)                             \
         ({                                              \
                 unsigned int _id = (id) >> 13 & 0x7;    \
                 _id <= 0x2;                             \
          })
+#else
+#define __cpu_is_pxa2xx(id)     (0)
+#endif
 
+#ifdef CONFIG_PXA3xx
 #define __cpu_is_pxa3xx(id)                             \
         ({                                              \
                 unsigned int _id = (id) >> 13 & 0x7;    \
                 _id == 0x3;                             \
          })
+#else
+#define __cpu_is_pxa3xx(id)     (0)
+#endif
 
+#if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935)
 #define __cpu_is_pxa93x(id)                             \
         ({                                              \
                 unsigned int _id = (id) >> 4 & 0xfff;   \
                 _id == 0x683 || _id == 0x693;           \
          })
+#else
+#define __cpu_is_pxa93x(id)     (0)
+#endif
 
 #define cpu_is_pxa2xx()                                 \
         ({                                              \
@@ -309,7 +321,7 @@ extern unsigned long get_clock_tick_rate(void);
 #define PCIBIOS_MIN_IO          0
 #define PCIBIOS_MIN_MEM         0
 #define pcibios_assign_all_busses()     1
+#define ARCH_HAS_DMA_SET_COHERENT_MASK
 #endif
 
-
 #endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-pxa/include/mach/hx4700.h b/arch/arm/mach-pxa/include/mach/hx4700.h
index 9eaeed1f87f1..37408449ec25 100644
--- a/arch/arm/mach-pxa/include/mach/hx4700.h
+++ b/arch/arm/mach-pxa/include/mach/hx4700.h
@@ -17,6 +17,7 @@
 
 #define HX4700_ASIC3_GPIO_BASE  NR_BUILTIN_GPIO
 #define HX4700_EGPIO_BASE       (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS)
+#define HX4700_NR_IRQS          (IRQ_BOARD_START + 70)
 
 /*
  * PXA GPIOs
diff --git a/arch/arm/mach-pxa/include/mach/io.h b/arch/arm/mach-pxa/include/mach/io.h
index 262691fb97d8..fdca3be47d9b 100644
--- a/arch/arm/mach-pxa/include/mach/io.h
+++ b/arch/arm/mach-pxa/include/mach/io.h
@@ -6,6 +6,8 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
+#include <mach/hardware.h>
+
 #define IO_SPACE_LIMIT 0xffffffff
 
 /*
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h
index ffc8314520f2..d372caa75dc7 100644
--- a/arch/arm/mach-pxa/include/mach/irqs.h
+++ b/arch/arm/mach-pxa/include/mach/irqs.h
@@ -117,48 +117,12 @@
 /*
  * The following interrupts are for board specific purposes. Since
  * the kernel can only run on one machine at a time, we can re-use
- * these.  There will be 16 IRQs by default.  If it is not enough,
- * IRQ_BOARD_END is allowed be customized for each board, but keep
- * the numbers within sensible limits and in descending order, so
- * when multiple config options are selected, the maximum will be
- * used.
+ * these.
+ * By default, no board IRQ is reserved. It should be finished in
+ * custom board since sparse IRQ is already enabled.
  */
 #define IRQ_BOARD_START         (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM)
 
-#if defined(CONFIG_MACH_H4700)
-#define IRQ_BOARD_END           (IRQ_BOARD_START + 70)
-#elif defined(CONFIG_MACH_ZYLONITE)
-#define IRQ_BOARD_END           (IRQ_BOARD_START + 32)
-#elif defined(CONFIG_PXA_EZX)
-#define IRQ_BOARD_END           (IRQ_BOARD_START + 23)
-#else
-#define IRQ_BOARD_END           (IRQ_BOARD_START + 16)
-#endif
-
-/*
- * Figure out the MAX IRQ number.
- *
- * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
- * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1
- * Otherwise, we have the standard IRQs only.
- */
-#ifdef CONFIG_SA1111
-#define NR_IRQS                 (IRQ_BOARD_END + 55)
-#elif defined(CONFIG_PXA_HAVE_BOARD_IRQS)
-#define NR_IRQS                 (IRQ_BOARD_END)
-#else
 #define NR_IRQS                 (IRQ_BOARD_START)
-#endif
-
-/* add IT8152 IRQs beyond BOARD_END */
-#ifdef CONFIG_PCI_HOST_ITE8152
-#define IT8152_LAST_IRQ         (IRQ_BOARD_END + 40)
-
-#if NR_IRQS < (IT8152_LAST_IRQ+1)
-#undef NR_IRQS
-#define NR_IRQS (IT8152_LAST_IRQ+1)
-#endif
-
-#endif /* CONFIG_PCI_HOST_ITE8152 */
 
 #endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-pxa/include/mach/littleton.h b/arch/arm/mach-pxa/include/mach/littleton.h
index 6c9b21c51322..2a5726c15e0e 100644
--- a/arch/arm/mach-pxa/include/mach/littleton.h
+++ b/arch/arm/mach-pxa/include/mach/littleton.h
@@ -10,4 +10,6 @@
 #define EXT0_GPIO_BASE  (NR_BUILTIN_GPIO)
 #define EXT0_GPIO(x)    (EXT0_GPIO_BASE + (x))
 
+#define LITTLETON_NR_IRQS       (IRQ_BOARD_START + 8)
+
 #endif /* __ASM_ARCH_LITTLETON_H */
diff --git a/arch/arm/mach-pxa/include/mach/lpd270.h b/arch/arm/mach-pxa/include/mach/lpd270.h
index 0e6440c81683..cd070092b6eb 100644
--- a/arch/arm/mach-pxa/include/mach/lpd270.h
+++ b/arch/arm/mach-pxa/include/mach/lpd270.h
@@ -38,5 +38,6 @@
 #define LPD270_USBC_IRQ         LPD270_IRQ(2)
 #define LPD270_ETHERNET_IRQ     LPD270_IRQ(3)
 #define LPD270_AC97_IRQ         LPD270_IRQ(4)
+#define LPD270_NR_IRQS          (IRQ_BOARD_START + 5)
 
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/lubbock.h b/arch/arm/mach-pxa/include/mach/lubbock.h
index a0d4247f08fc..2a086e8373eb 100644
--- a/arch/arm/mach-pxa/include/mach/lubbock.h
+++ b/arch/arm/mach-pxa/include/mach/lubbock.h
@@ -45,6 +45,9 @@
 #define LUBBOCK_USB_DISC_IRQ    LUBBOCK_IRQ(6)  /* usb disconnect */
 #define LUBBOCK_LAST_IRQ        LUBBOCK_IRQ(6)
 
+#define LUBBOCK_SA1111_IRQ_BASE (IRQ_BOARD_START + 16)
+#define LUBBOCK_NR_IRQS         (IRQ_BOARD_START + 16 + 55)
+
 #ifndef __ASSEMBLY__
 extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set);
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/magician.h b/arch/arm/mach-pxa/include/mach/magician.h
index 20ef37d4a9a7..0a2efcf7947c 100644
--- a/arch/arm/mach-pxa/include/mach/magician.h
+++ b/arch/arm/mach-pxa/include/mach/magician.h
@@ -71,6 +71,8 @@
 #define IRQ_MAGICIAN_BT         (IRQ_BOARD_START + 2)
 #define IRQ_MAGICIAN_VBUS       (IRQ_BOARD_START + 3)
 
+#define MAGICIAN_NR_IRQS        (IRQ_BOARD_START + 8)
+
 /*
  * CPLD EGPIOs
  */
diff --git a/arch/arm/mach-pxa/include/mach/mainstone.h b/arch/arm/mach-pxa/include/mach/mainstone.h
index 86e623abd64d..4c2d11cd824d 100644
--- a/arch/arm/mach-pxa/include/mach/mainstone.h
+++ b/arch/arm/mach-pxa/include/mach/mainstone.h
@@ -134,4 +134,6 @@
 #define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14)
 #define MAINSTONE_S1_IRQ        MAINSTONE_IRQ(15)
 
+#define MAINSTONE_NR_IRQS       (IRQ_BOARD_START + 16)
+
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
index 0d119d3b9221..04f7c97044f3 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
@@ -69,6 +69,7 @@
 #define nBE0_GPIO_60            MFP_CFG(nBE0, AF0)
 #define nBE1_GPIO_61            MFP_CFG(nBE1, AF0)
 #define RDY_GPIO_62             MFP_CFG(RDY, AF0)
+#define PMIC_INT_GPIO83         MFP_CFG_LPM(PMIC_INT, AF0, PULL_HIGH)
 
 /* Chip Select */
 #define DF_nCS0_nCS2            MFP_CFG_LPM(DF_nCS0, AF3, PULL_HIGH)
@@ -92,6 +93,9 @@
 #define GPIO63_CI2C_SCL         MFP_CFG_LPM(GPIO63, AF4, PULL_HIGH)
 #define GPIO64_CI2C_SDA         MFP_CFG_LPM(GPIO64, AF4, PULL_HIGH)
 
+#define GPIO73_CI2C_SCL         MFP_CFG_LPM(GPIO73, AF1, PULL_HIGH)
+#define GPIO74_CI2C_SDA         MFP_CFG_LPM(GPIO74, AF1, PULL_HIGH)
+
 #define GPIO77_CI2C_SCL         MFP_CFG_LPM(GPIO77, AF2, PULL_HIGH)
 #define GPIO78_CI2C_SDA         MFP_CFG_LPM(GPIO78, AF2, PULL_HIGH)
 
@@ -345,6 +349,9 @@
 #define GPIO69_UART1_CTS        MFP_CFG(GPIO69, AF2)
 #define GPIO70_UART1_RTS        MFP_CFG(GPIO70, AF2)
 
+#define GPIO53_UART1_TXD        MFP_CFG(GPIO53, AF2)
+#define GPIO54_UART1_RXD        MFP_CFG(GPIO54, AF2)
+
 /* UART2 - BTUART */
 #define GPIO91_UART2_RXD        MFP_CFG(GPIO91, AF1)
 #define GPIO92_UART2_TXD        MFP_CFG(GPIO92, AF1)
diff --git a/arch/arm/mach-pxa/include/mach/pcm027.h b/arch/arm/mach-pxa/include/mach/pcm027.h
index 04083263167e..4bac588478a8 100644
--- a/arch/arm/mach-pxa/include/mach/pcm027.h
+++ b/arch/arm/mach-pxa/include/mach/pcm027.h
@@ -30,6 +30,8 @@
 #define PCM027_MMCDET_IRQ      PCM027_IRQ(2)
 #define PCM027_PM_5V_IRQ       PCM027_IRQ(3)
 
+#define PCM027_NR_IRQS          (IRQ_BOARD_START + 32)
+
 /* I2C RTC */
 #define PCM027_RTC_IRQ_GPIO     0
 #define PCM027_RTC_IRQ          IRQ_GPIO(PCM027_RTC_IRQ_GPIO)
diff --git a/arch/arm/mach-pxa/include/mach/poodle.h b/arch/arm/mach-pxa/include/mach/poodle.h
index 0b3e6d051c64..83d1cfd00fc9 100644
--- a/arch/arm/mach-pxa/include/mach/poodle.h
+++ b/arch/arm/mach-pxa/include/mach/poodle.h
@@ -85,6 +85,8 @@
 #define POODLE_LOCOMO_GPIO_232VCC_ON   LOCOMO_GPIO(12)
 #define POODLE_LOCOMO_GPIO_JK_B        LOCOMO_GPIO(13)
 
+#define POODLE_NR_IRQS          (IRQ_BOARD_START + 4)   /* 4 for LoCoMo */
+
 extern struct platform_device poodle_locomo_device;
 
 #endif /* __ASM_ARCH_POODLE_H  */
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h b/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h
new file mode 100644
index 000000000000..9d82cb65ea56
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h
@@ -0,0 +1,35 @@
+/*
+ * PXA3xx U2D header
+ *
+ * Copyright (C) 2010 CompuLab Ltd.
+ *
+ * Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __PXA310_U2D__
+#define __PXA310_U2D__
+
+#include <linux/usb/ulpi.h>
+
+struct pxa3xx_u2d_platform_data {
+
+#define ULPI_SER_6PIN   (1 << 0)
+#define ULPI_SER_3PIN   (1 << 1)
+        unsigned int ulpi_mode;
+
+        int (*init)(struct device *);
+        void (*exit)(struct device *);
+};
+
+
+/* Start PXA3xx U2D host */
+int pxa3xx_u2d_start_hc(struct usb_bus *host);
+/* Stop PXA3xx U2D host */
+void pxa3xx_u2d_stop_hc(struct usb_bus *host);
+
+extern void pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info);
+
+#endif /* __PXA310_U2D__ */
diff --git a/arch/arm/mach-pxa/include/mach/tosa.h b/arch/arm/mach-pxa/include/mach/tosa.h
index 1bbd1f2e4beb..1272c4b56ceb 100644
--- a/arch/arm/mach-pxa/include/mach/tosa.h
+++ b/arch/arm/mach-pxa/include/mach/tosa.h
@@ -20,6 +20,7 @@
 /* Jacket Scoop */
 #define TOSA_SCOOP_PHYS         (PXA_CS5_PHYS + 0x00800000)
 
+#define TOSA_NR_IRQS            (IRQ_BOARD_START + TC6393XB_NR_IRQS)
 /*
  * SCOOP2 internal GPIOs
  */
diff --git a/arch/arm/mach-pxa/include/mach/zeus.h b/arch/arm/mach-pxa/include/mach/zeus.h
index 6e119976003e..faa408ab7ad7 100644
--- a/arch/arm/mach-pxa/include/mach/zeus.h
+++ b/arch/arm/mach-pxa/include/mach/zeus.h
@@ -15,6 +15,8 @@
 #ifndef _MACH_ZEUS_H
 #define _MACH_ZEUS_H
 
+#define ZEUS_NR_IRQS            (IRQ_BOARD_START + 48)
+
 /* Physical addresses */
 #define ZEUS_FLASH_PHYS         PXA_CS0_PHYS
 #define ZEUS_ETH0_PHYS          PXA_CS1_PHYS
diff --git a/arch/arm/mach-pxa/include/mach/zylonite.h b/arch/arm/mach-pxa/include/mach/zylonite.h
index 9edf645368d6..ea24998b923c 100644
--- a/arch/arm/mach-pxa/include/mach/zylonite.h
+++ b/arch/arm/mach-pxa/include/mach/zylonite.h
@@ -5,6 +5,8 @@
 
 #define EXT_GPIO(x)             (128 + (x))
 
+#define ZYLONITE_NR_IRQS        (IRQ_BOARD_START + 32)
+
 /* the following variables are processor specific and initialized
  * by the corresponding zylonite_pxa3xx_init()
  */
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 9b9046185b00..eb5850624c1d 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -43,7 +43,7 @@
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
 #include <mach/pxa2xx_spi.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/littleton.h>
 #include <plat/i2c.h>
 #include <plat/pxa3xx_nand.h>
@@ -441,6 +441,7 @@ MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleto
         .boot_params    = 0xa0000100,
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = pxa_map_io,
+        .nr_irqs        = LITTLETON_NR_IRQS,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = littleton_init,
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index d279507fc748..fc9502ef4024 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -509,6 +509,7 @@ MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = lpd270_map_io,
+        .nr_irqs        = LPD270_NR_IRQS,
         .init_irq       = lpd270_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = lpd270_init,
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 330c3282856e..1956c23093d1 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -229,7 +229,7 @@ static struct resource sa1111_resources[] = {
 };
 
 static struct sa1111_platform_data sa1111_info = {
-        .irq_base       = IRQ_BOARD_END,
+        .irq_base       = LUBBOCK_SA1111_IRQ_BASE,
 };
 
 static struct platform_device sa1111_device = {
@@ -560,6 +560,7 @@ MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform (aka Lubbock)")
         .phys_io        = 0x40000000,
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = lubbock_map_io,
+        .nr_irqs        = LUBBOCK_NR_IRQS,
         .init_irq       = lubbock_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = lubbock_init,
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index e81dd0c8e40d..42a0c2b41281 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -768,6 +768,7 @@ MACHINE_START(MAGICIAN, "HTC Magician")
         .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params = 0xa0000100,
         .map_io = pxa_map_io,
+        .nr_irqs = MAGICIAN_NR_IRQS,
         .init_irq = pxa27x_init_irq,
         .init_machine = magician_init,
         .timer = &pxa_timer,
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 5543c64da9ef..8b710024601c 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -50,7 +50,7 @@
 #include <mach/mmc.h>
 #include <mach/irda.h>
 #include <mach/ohci.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 
 #include "generic.h"
 #include "devices.h"
@@ -628,6 +628,7 @@ MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
         .boot_params    = 0xa0000100,   /* BLOB boot parameter setting */
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = mainstone_map_io,
+        .nr_irqs        = MAINSTONE_NR_IRQS,
         .init_irq       = mainstone_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = mainstone_init,
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index dc66942ef9ab..ffb3f5a8a086 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -45,7 +45,7 @@
 
 #include <mach/pxa27x.h>
 #include <mach/regs-rtc.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
 #include <mach/udc.h>
diff --git a/arch/arm/mach-pxa/palm27x.c b/arch/arm/mach-pxa/palm27x.c
index 77ad6d34ab5b..405b92a29793 100644
--- a/arch/arm/mach-pxa/palm27x.c
+++ b/arch/arm/mach-pxa/palm27x.c
@@ -469,9 +469,13 @@ static struct i2c_board_info __initdata palm27x_pi2c_board_info[] = {
         },
 };
 
+static struct i2c_pxa_platform_data palm27x_i2c_power_info = {
+        .use_pio        = 1,
+};
+
 void __init palm27x_pmic_init(void)
 {
         i2c_register_board_info(1, ARRAY_AND_SIZE(palm27x_pi2c_board_info));
-        pxa27x_set_i2c_power_info(NULL);
+        pxa27x_set_i2c_power_info(&palm27x_i2c_power_info);
 }
 #endif
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
index 91038eeafe44..3ff0c4a1ca4c 100644
--- a/arch/arm/mach-pxa/palmld.c
+++ b/arch/arm/mach-pxa/palmld.c
@@ -39,7 +39,7 @@
 #include <mach/mmc.h>
 #include <mach/pxafb.h>
 #include <mach/irda.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/palmasoc.h>
 #include <mach/palm27x.h>
 
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index 1c281995f658..5b9f766d1468 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -39,7 +39,7 @@
 #include <mach/mmc.h>
 #include <mach/pxafb.h>
 #include <mach/irda.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/udc.h>
 #include <mach/palmasoc.h>
 #include <mach/palm27x.h>
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index 52defd5e42e5..f685a600a181 100644
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -39,7 +39,7 @@
 #include <mach/mmc.h>
 #include <mach/pxafb.h>
 #include <mach/irda.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/udc.h>
 #include <mach/ohci.h>
 #include <mach/pxa2xx-regs.h>
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index 144dc2b6911f..89a37922b9d3 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -43,7 +43,7 @@
 #include <mach/mmc.h>
 #include <mach/pxafb.h>
 #include <mach/irda.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/udc.h>
 #include <mach/palmasoc.h>
 #include <mach/palm27x.h>
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index 87e4b1044e0b..38f4425bfc95 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -41,7 +41,7 @@
 #include <mach/mmc.h>
 #include <mach/pxafb.h>
 #include <mach/irda.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/udc.h>
 #include <mach/palmasoc.h>
 #include <mach/palm27x.h>
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
index 2190af066470..90b08ba8ad1a 100644
--- a/arch/arm/mach-pxa/pcm027.c
+++ b/arch/arm/mach-pxa/pcm027.c
@@ -262,6 +262,7 @@ MACHINE_START(PCM027, "Phytec Messtechnik GmbH phyCORE-PXA270")
         .phys_io        = 0x40000000,
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = pcm027_map_io,
+        .nr_irqs        = PCM027_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = pcm027_init,
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 55e8fcde0141..c04e025cd790 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -469,6 +469,7 @@ MACHINE_START(POODLE, "SHARP Poodle")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .fixup          = fixup_poodle,
         .map_io         = pxa_map_io,
+        .nr_irqs        = POODLE_NR_IRQS,       /* 4 for LoCoMo */
         .init_irq       = pxa25x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = poodle_init,
diff --git a/arch/arm/mach-pxa/pxa3xx-ulpi.c b/arch/arm/mach-pxa/pxa3xx-ulpi.c
new file mode 100644
index 000000000000..ce7168b233e2
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa3xx-ulpi.c
@@ -0,0 +1,400 @@
+/*
+ * linux/arch/arm/mach-pxa/pxa3xx-ulpi.c
+ *
+ * code specific to pxa3xx aka Monahans
+ *
+ * Copyright (C) 2010 CompuLab Ltd.
+ *
+ * 2010-13-07: Igor Grinberg <grinberg@compulab.co.il>
+ *             initial version: pxa310 USB Host mode support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/usb.h>
+#include <linux/usb/otg.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-u2d.h>
+#include <mach/pxa3xx-u2d.h>
+
+struct pxa3xx_u2d_ulpi {
+        struct clk              *clk;
+        void __iomem            *mmio_base;
+
+        struct otg_transceiver  *otg;
+        unsigned int            ulpi_mode;
+};
+
+static struct pxa3xx_u2d_ulpi *u2d;
+
+static inline u32 u2d_readl(u32 reg)
+{
+        return __raw_readl(u2d->mmio_base + reg);
+}
+
+static inline void u2d_writel(u32 reg, u32 val)
+{
+        __raw_writel(val, u2d->mmio_base + reg);
+}
+
+#if defined(CONFIG_PXA310_ULPI)
+enum u2d_ulpi_phy_mode {
+        SYNCH           = 0,
+        CARKIT          = (1 << 0),
+        SER_3PIN        = (1 << 1),
+        SER_6PIN        = (1 << 2),
+        LOWPOWER        = (1 << 3),
+};
+
+static inline enum u2d_ulpi_phy_mode pxa310_ulpi_get_phymode(void)
+{
+        return (u2d_readl(U2DOTGUSR) >> 28) & 0xF;
+}
+
+static int pxa310_ulpi_poll(void)
+{
+        int timeout = 50000;
+
+        while (timeout--) {
+                if (!(u2d_readl(U2DOTGUCR) & U2DOTGUCR_RUN))
+                        return 0;
+
+                cpu_relax();
+        }
+
+        pr_warning("%s: ULPI access timed out!\n", __func__);
+
+        return -ETIMEDOUT;
+}
+
+static int pxa310_ulpi_read(struct otg_transceiver *otg, u32 reg)
+{
+        int err;
+
+        if (pxa310_ulpi_get_phymode() != SYNCH) {
+                pr_warning("%s: PHY is not in SYNCH mode!\n", __func__);
+                return -EBUSY;
+        }
+
+        u2d_writel(U2DOTGUCR, U2DOTGUCR_RUN | U2DOTGUCR_RNW | (reg << 16));
+        msleep(5);
+
+        err = pxa310_ulpi_poll();
+        if (err)
+                return err;
+
+        return u2d_readl(U2DOTGUCR) & U2DOTGUCR_RDATA;
+}
+
+static int pxa310_ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg)
+{
+        if (pxa310_ulpi_get_phymode() != SYNCH) {
+                pr_warning("%s: PHY is not in SYNCH mode!\n", __func__);
+                return -EBUSY;
+        }
+
+        u2d_writel(U2DOTGUCR, U2DOTGUCR_RUN | (reg << 16) | (val << 8));
+        msleep(5);
+
+        return pxa310_ulpi_poll();
+}
+
+struct otg_io_access_ops pxa310_ulpi_access_ops = {
+        .read   = pxa310_ulpi_read,
+        .write  = pxa310_ulpi_write,
+};
+
+static void pxa310_otg_transceiver_rtsm(void)
+{
+        u32 u2dotgcr;
+
+        /* put PHY to sync mode */
+        u2dotgcr = u2d_readl(U2DOTGCR);
+        u2dotgcr |=  U2DOTGCR_RTSM | U2DOTGCR_UTMID;
+        u2d_writel(U2DOTGCR, u2dotgcr);
+        msleep(10);
+
+        /* setup OTG sync mode */
+        u2dotgcr = u2d_readl(U2DOTGCR);
+        u2dotgcr |= U2DOTGCR_ULAF;
+        u2dotgcr &= ~(U2DOTGCR_SMAF | U2DOTGCR_CKAF);
+        u2d_writel(U2DOTGCR, u2dotgcr);
+}
+
+static int pxa310_start_otg_host_transcvr(struct usb_bus *host)
+{
+        int err;
+
+        pxa310_otg_transceiver_rtsm();
+
+        err = otg_init(u2d->otg);
+        if (err) {
+                pr_err("OTG transceiver init failed");
+                return err;
+        }
+
+        err = otg_set_vbus(u2d->otg, 1);
+        if (err) {
+                pr_err("OTG transceiver VBUS set failed");
+                return err;
+        }
+
+        err = otg_set_host(u2d->otg, host);
+        if (err)
+                pr_err("OTG transceiver Host mode set failed");
+
+        return err;
+}
+
+static int pxa310_start_otg_hc(struct usb_bus *host)
+{
+        u32 u2dotgcr;
+        int err;
+
+        /* disable USB device controller */
+        u2d_writel(U2DCR, u2d_readl(U2DCR) & ~U2DCR_UDE);
+        u2d_writel(U2DOTGCR, u2d_readl(U2DOTGCR) | U2DOTGCR_UTMID);
+        u2d_writel(U2DOTGICR, u2d_readl(U2DOTGICR) & ~0x37F7F);
+
+        err = pxa310_start_otg_host_transcvr(host);
+        if (err)
+                return err;
+
+        /* set xceiver mode */
+        if (u2d->ulpi_mode & ULPI_IC_6PIN_SERIAL)
+                u2d_writel(U2DP3CR, u2d_readl(U2DP3CR) & ~U2DP3CR_P2SS);
+        else if (u2d->ulpi_mode & ULPI_IC_3PIN_SERIAL)
+                u2d_writel(U2DP3CR, u2d_readl(U2DP3CR) | U2DP3CR_P2SS);
+
+        /* start OTG host controller */
+        u2dotgcr = u2d_readl(U2DOTGCR) | U2DOTGCR_SMAF;
+        u2d_writel(U2DOTGCR, u2dotgcr & ~(U2DOTGCR_ULAF | U2DOTGCR_CKAF));
+
+        return 0;
+}
+
+static void pxa310_stop_otg_hc(void)
+{
+        pxa310_otg_transceiver_rtsm();
+
+        otg_set_host(u2d->otg, NULL);
+        otg_set_vbus(u2d->otg, 0);
+        otg_shutdown(u2d->otg);
+}
+
+static void pxa310_u2d_setup_otg_hc(void)
+{
+        u32 u2dotgcr;
+
+        u2dotgcr = u2d_readl(U2DOTGCR);
+        u2dotgcr |= U2DOTGCR_ULAF | U2DOTGCR_UTMID;
+        u2dotgcr &= ~(U2DOTGCR_SMAF | U2DOTGCR_CKAF);
+        u2d_writel(U2DOTGCR, u2dotgcr);
+        msleep(5);
+        u2d_writel(U2DOTGCR, u2dotgcr | U2DOTGCR_ULE);
+        msleep(5);
+        u2d_writel(U2DOTGICR, u2d_readl(U2DOTGICR) & ~0x37F7F);
+}
+
+static int pxa310_otg_init(struct pxa3xx_u2d_platform_data *pdata)
+{
+        unsigned int ulpi_mode = ULPI_OTG_DRVVBUS;
+
+        if (pdata) {
+                if (pdata->ulpi_mode & ULPI_SER_6PIN)
+                        ulpi_mode |= ULPI_IC_6PIN_SERIAL;
+                else if (pdata->ulpi_mode & ULPI_SER_3PIN)
+                        ulpi_mode |= ULPI_IC_3PIN_SERIAL;
+        }
+
+        u2d->ulpi_mode = ulpi_mode;
+
+        u2d->otg = otg_ulpi_create(&pxa310_ulpi_access_ops, ulpi_mode);
+        if (!u2d->otg)
+                return -ENOMEM;
+
+        u2d->otg->io_priv = u2d->mmio_base;
+
+        return 0;
+}
+
+static void pxa310_otg_exit(void)
+{
+        kfree(u2d->otg);
+}
+#else
+static inline void pxa310_u2d_setup_otg_hc(void) {}
+static inline int pxa310_start_otg_hc(struct usb_bus *host)
+{
+        return 0;
+}
+static inline void pxa310_stop_otg_hc(void) {}
+static inline int pxa310_otg_init(struct pxa3xx_u2d_platform_data *pdata)
+{
+        return 0;
+}
+static inline void pxa310_otg_exit(void) {}
+#endif /* CONFIG_PXA310_ULPI */
+
+int pxa3xx_u2d_start_hc(struct usb_bus *host)
+{
+        int err = 0;
+
+        /* In case the PXA3xx ULPI isn't used, do nothing. */
+        if (!u2d)
+                return 0;
+
+        clk_enable(u2d->clk);
+
+        if (cpu_is_pxa310()) {
+                pxa310_u2d_setup_otg_hc();
+                err = pxa310_start_otg_hc(host);
+        }
+
+        return err;
+}
+
+void pxa3xx_u2d_stop_hc(struct usb_bus *host)
+{
+        /* In case the PXA3xx ULPI isn't used, do nothing. */
+        if (!u2d)
+                return;
+
+        if (cpu_is_pxa310())
+                pxa310_stop_otg_hc();
+
+        clk_disable(u2d->clk);
+}
+
+static int pxa3xx_u2d_probe(struct platform_device *pdev)
+{
+        struct pxa3xx_u2d_platform_data *pdata = pdev->dev.platform_data;
+        struct resource *r;
+        int err;
+
+        u2d = kzalloc(sizeof(struct pxa3xx_u2d_ulpi), GFP_KERNEL);
+        if (!u2d) {
+                dev_err(&pdev->dev, "failed to allocate memory\n");
+                return -ENOMEM;
+        }
+
+        u2d->clk = clk_get(&pdev->dev, NULL);
+        if (IS_ERR(u2d->clk)) {
+                dev_err(&pdev->dev, "failed to get u2d clock\n");
+                err = PTR_ERR(u2d->clk);
+                goto err_free_mem;
+        }
+
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!r) {
+                dev_err(&pdev->dev, "no IO memory resource defined\n");
+                err = -ENODEV;
+                goto err_put_clk;
+        }
+
+        r = request_mem_region(r->start, resource_size(r), pdev->name);
+        if (!r) {
+                dev_err(&pdev->dev, "failed to request memory resource\n");
+                err = -EBUSY;
+                goto err_put_clk;
+        }
+
+        u2d->mmio_base = ioremap(r->start, resource_size(r));
+        if (!u2d->mmio_base) {
+                dev_err(&pdev->dev, "ioremap() failed\n");
+                err = -ENODEV;
+                goto err_free_res;
+        }
+
+        if (pdata->init) {
+                err = pdata->init(&pdev->dev);
+                if (err)
+                        goto err_free_io;
+        }
+
+        /* Only PXA310 U2D has OTG functionality */
+        if (cpu_is_pxa310()) {
+                err = pxa310_otg_init(pdata);
+                if (err)
+                        goto err_free_plat;
+        }
+
+        platform_set_drvdata(pdev, &u2d);
+
+        return 0;
+
+err_free_plat:
+        if (pdata->exit)
+                pdata->exit(&pdev->dev);
+err_free_io:
+        iounmap(u2d->mmio_base);
+err_free_res:
+        release_mem_region(r->start, resource_size(r));
+err_put_clk:
+        clk_put(u2d->clk);
+err_free_mem:
+        kfree(u2d);
+        return err;
+}
+
+static int pxa3xx_u2d_remove(struct platform_device *pdev)
+{
+        struct pxa3xx_u2d_platform_data *pdata = pdev->dev.platform_data;
+        struct resource *r;
+
+        if (cpu_is_pxa310()) {
+                pxa310_stop_otg_hc();
+                pxa310_otg_exit();
+        }
+
+        if (pdata->exit)
+                pdata->exit(&pdev->dev);
+
+        platform_set_drvdata(pdev, NULL);
+        iounmap(u2d->mmio_base);
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        release_mem_region(r->start, resource_size(r));
+
+        clk_put(u2d->clk);
+
+        kfree(u2d);
+
+        return 0;
+}
+
+static struct platform_driver pxa3xx_u2d_ulpi_driver = {
+        .driver         = {
+                .name   = "pxa3xx-u2d",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = pxa3xx_u2d_probe,
+        .remove         = pxa3xx_u2d_remove,
+};
+
+static int pxa3xx_u2d_ulpi_init(void)
+{
+        return platform_driver_register(&pxa3xx_u2d_ulpi_driver);
+}
+module_init(pxa3xx_u2d_ulpi_init);
+
+static void __exit pxa3xx_u2d_ulpi_exit(void)
+{
+        platform_driver_unregister(&pxa3xx_u2d_ulpi_driver);
+}
+module_exit(pxa3xx_u2d_ulpi_exit);
+
+MODULE_DESCRIPTION("PXA3xx U2D ULPI driver");
+MODULE_AUTHOR("Igor Grinberg");
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index fa0014847c71..c85c3a7abd31 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -98,23 +98,6 @@ unsigned int pxa3xx_get_clk_frequency_khz(int info)
         return CLK / 1000;
 }
 
-/*
- * Return the current static memory controller clock frequency
- * in units of 10kHz
- */
-unsigned int pxa3xx_get_memclk_frequency_10khz(void)
-{
-        unsigned long acsr;
-        unsigned int smcfs, clk = 0;
-
-        acsr = ACSR;
-
-        smcfs = (acsr >> 23) & 0x7;
-        clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
-
-        return (clk / 10000);
-}
-
 void pxa3xx_clear_reset_status(unsigned int mask)
 {
         /* RESET_STATUS_* has a 1:1 mapping with ARSR */
@@ -265,7 +248,7 @@ static struct clk_lookup pxa3xx_clkregs[] = {
         INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
         INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
         INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
-        INIT_CLKREG(&clk_pxa3xx_u2d, NULL, "U2DCLK"),
+        INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
         INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
         INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
         INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
diff --git a/arch/arm/mach-pxa/pxa930.c b/arch/arm/mach-pxa/pxa930.c
index 064292008288..7d29dd3af79d 100644
--- a/arch/arm/mach-pxa/pxa930.c
+++ b/arch/arm/mach-pxa/pxa930.c
@@ -192,7 +192,7 @@ static struct mfp_addr_map pxa935_mfp_addr_map[] __initdata = {
 
 static int __init pxa930_init(void)
 {
-        if (cpu_is_pxa930() || cpu_is_pxa935()) {
+        if (cpu_is_pxa930() || cpu_is_pxa935() || cpu_is_pxa950()) {
                 mfp_init_base(io_p2v(MFPR_BASE));
                 mfp_init_addr(pxa930_mfp_addr_map);
         }
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index a654d1e6b38a..62de07341cc6 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -56,6 +56,8 @@
 #include "devices.h"
 #include "generic.h"
 
+#define STARGATE_NR_IRQS        (IRQ_BOARD_START + 8)
+
 /* Bluetooth */
 #define SG2_BT_RESET            81
 
@@ -1011,6 +1013,7 @@ MACHINE_START(STARGATE2, "Stargate 2")
         .phys_io = 0x40000000,
         .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io = pxa_map_io,
+        .nr_irqs = STARGATE_NR_IRQS,
         .init_irq = pxa27x_init_irq,
         .timer = &pxa_timer,
         .init_machine = stargate2_init,
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index f02dcb5b4e97..0f440c9d7cbd 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -25,7 +25,7 @@
 
 #include <mach/pxa930.h>
 #include <mach/pxafb.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/tavorevb3.c b/arch/arm/mach-pxa/tavorevb3.c
new file mode 100644
index 000000000000..5eeba64515e4
--- /dev/null
+++ b/arch/arm/mach-pxa/tavorevb3.c
@@ -0,0 +1,136 @@
+/*
+ *  linux/arch/arm/mach-pxa/tavorevb3.c
+ *
+ *  Support for the Marvell EVB3 Development Platform.
+ *
+ *  Copyright:  (C) Copyright 2008-2010 Marvell International Ltd.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/mfd/88pm860x.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/pxa930.h>
+
+#include <plat/i2c.h>
+
+#include "devices.h"
+#include "generic.h"
+
+#define TAVOREVB3_NR_IRQS       (IRQ_BOARD_START + 24)
+
+static mfp_cfg_t evb3_mfp_cfg[] __initdata = {
+        /* UART */
+        GPIO53_UART1_TXD,
+        GPIO54_UART1_RXD,
+
+        /* PMIC */
+        PMIC_INT_GPIO83,
+};
+
+#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
+static struct pm860x_touch_pdata evb3_touch = {
+        .gpadc_prebias  = 1,
+        .slot_cycle     = 1,
+        .tsi_prebias    = 6,
+        .pen_prebias    = 16,
+        .pen_prechg     = 2,
+        .res_x          = 300,
+};
+
+static struct pm860x_backlight_pdata evb3_backlight[] = {
+        {
+                .id     = PM8606_ID_BACKLIGHT,
+                .iset   = PM8606_WLED_CURRENT(24),
+                .flags  = PM8606_BACKLIGHT1,
+        },
+        {},
+};
+
+static struct pm860x_led_pdata evb3_led[] = {
+        {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED1_RED,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED1_GREEN,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED1_BLUE,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED2_RED,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED2_GREEN,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED2_BLUE,
+        },
+};
+
+static struct pm860x_platform_data evb3_pm8607_info = {
+        .touch                          = &evb3_touch,
+        .backlight                      = &evb3_backlight[0],
+        .led                            = &evb3_led[0],
+        .companion_addr                 = 0x10,
+        .irq_mode                       = 0,
+        .irq_base                       = IRQ_BOARD_START,
+
+        .i2c_port                       = GI2C_PORT,
+};
+
+static struct i2c_board_info evb3_i2c_info[] = {
+        {
+                .type           = "88PM860x",
+                .addr           = 0x34,
+                .platform_data  = &evb3_pm8607_info,
+                .irq            = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)),
+        },
+};
+
+static void __init evb3_init_i2c(void)
+{
+        pxa_set_i2c_info(NULL);
+        i2c_register_board_info(0, ARRAY_AND_SIZE(evb3_i2c_info));
+}
+#else
+static inline void evb3_init_i2c(void) {}
+#endif
+
+static void __init evb3_init(void)
+{
+        /* initialize MFP configurations */
+        pxa3xx_mfp_config(ARRAY_AND_SIZE(evb3_mfp_cfg));
+
+        pxa_set_ffuart_info(NULL);
+
+        evb3_init_i2c();
+}
+
+MACHINE_START(TAVOREVB3, "PXA950 Evaluation Board (aka TavorEVB3)")
+        .phys_io        = 0x40000000,
+        .boot_params    = 0xa0000100,
+        .map_io         = pxa_map_io,
+        .nr_irqs        = TAVOREVB3_NR_IRQS,
+        .init_irq       = pxa3xx_init_irq,
+        .timer          = &pxa_timer,
+        .init_machine   = evb3_init,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 83cc3a18c2e9..3a06e98b4920 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -956,6 +956,7 @@ MACHINE_START(TOSA, "SHARP Tosa")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .fixup          = fixup_tosa,
         .map_io         = pxa_map_io,
+        .nr_irqs        = TOSA_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .init_machine   = tosa_init,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c
index c9b747cedea8..37d6173bbb66 100644
--- a/arch/arm/mach-pxa/vpac270.c
+++ b/arch/arm/mach-pxa/vpac270.c
@@ -240,6 +240,7 @@ static void __init vpac270_onenand_init(void) {}
 #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
 static struct pxamci_platform_data vpac270_mci_platform_data = {
         .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
+        .gpio_power             = -1,
         .gpio_card_detect       = GPIO53_VPAC270_SD_DETECT_N,
         .gpio_card_ro           = GPIO52_VPAC270_SD_READONLY,
         .detect_delay_ms        = 200,
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index f0d02288b4ca..8c44bc4381ba 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -37,7 +37,7 @@
 #include <mach/z2.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/pxa2xx_spi.h>
 
 #include <plat/i2c.h>
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index 03b9cb910e08..9da2b624ba20 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -904,6 +904,7 @@ MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
         .io_pg_offst    = ((io_p2v(0x40000000) >> 18) & 0xfffc),
         .boot_params    = 0xa0000100,
         .map_io         = zeus_map_io,
+        .nr_irqs        = ZEUS_NR_IRQS,
         .init_irq       = zeus_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = zeus_init,
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index c479cbecf784..69df3edcdd98 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -30,7 +30,7 @@
 #include <mach/zylonite.h>
 #include <mach/mmc.h>
 #include <mach/ohci.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <plat/pxa3xx_nand.h>
 
 #include "devices.h"
@@ -415,6 +415,7 @@ MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
         .boot_params    = 0xa0000100,
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = pxa_map_io,
+        .nr_irqs        = ZYLONITE_NR_IRQS,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = zylonite_init,
diff --git a/arch/arm/mach-rpc/include/mach/vmalloc.h b/arch/arm/mach-rpc/include/mach/vmalloc.h
index 9a96fd69e705..3bcd86fadb81 100644
--- a/arch/arm/mach-rpc/include/mach/vmalloc.h
+++ b/arch/arm/mach-rpc/include/mach/vmalloc.h
@@ -7,4 +7,4 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x1c000000)
+#define VMALLOC_END       0xdc000000
diff --git a/arch/arm/mach-s3c64xx/dev-spi.c b/arch/arm/mach-s3c64xx/dev-spi.c
index a492b982aa06..405e62128917 100644
--- a/arch/arm/mach-s3c64xx/dev-spi.c
+++ b/arch/arm/mach-s3c64xx/dev-spi.c
@@ -18,10 +18,11 @@
 #include <mach/map.h>
 #include <mach/gpio-bank-c.h>
 #include <mach/spi-clocks.h>
+#include <mach/irqs.h>
 
 #include <plat/s3c64xx-spi.h>
 #include <plat/gpio-cfg.h>
-#include <plat/irqs.h>
+#include <plat/devs.h>
 
 static char *spi_src_clks[] = {
         [S3C64XX_SPI_SRCCLK_PCLK] = "pclk",
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 5c07d013b23d..e130379ba0e8 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -30,73 +30,73 @@
 #include <plat/devs.h>
 #include <plat/regs-serial.h>
 
-#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
-#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
-#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
+#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
+#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
+#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
 
 static struct s3c2410_uartcfg real6410_uartcfgs[] __initdata = {
         [0] = {
-                .hwport      = 0,
-                .flags       = 0,
-                .ucon        = UCON,
-                .ulcon       = ULCON,
-                .ufcon       = UFCON,
+                .hwport = 0,
+                .flags  = 0,
+                .ucon   = UCON,
+                .ulcon  = ULCON,
+                .ufcon  = UFCON,
         },
         [1] = {
-                .hwport      = 1,
-                .flags       = 0,
-                .ucon        = UCON,
-                .ulcon       = ULCON,
-                .ufcon       = UFCON,
+                .hwport = 1,
+                .flags  = 0,
+                .ucon   = UCON,
+                .ulcon  = ULCON,
+                .ufcon  = UFCON,
         },
         [2] = {
-                .hwport      = 2,
-                .flags       = 0,
-                .ucon        = UCON,
-                .ulcon       = ULCON,
-                .ufcon       = UFCON,
+                .hwport = 2,
+                .flags  = 0,
+                .ucon   = UCON,
+                .ulcon  = ULCON,
+                .ufcon  = UFCON,
         },
         [3] = {
-                .hwport      = 3,
-                .flags       = 0,
-                .ucon        = UCON,
-                .ulcon       = ULCON,
-                .ufcon       = UFCON,
+                .hwport = 3,
+                .flags  = 0,
+                .ucon   = UCON,
+                .ulcon  = ULCON,
+                .ufcon  = UFCON,
         },
 };
 
 /* DM9000AEP 10/100 ethernet controller */
 
 static struct resource real6410_dm9k_resource[] = {
-        [0] = {
-                .start = S3C64XX_PA_XM0CSN1,
-                .end   = S3C64XX_PA_XM0CSN1 + 1,
-                .flags = IORESOURCE_MEM
-        },
-        [1] = {
-                .start = S3C64XX_PA_XM0CSN1 + 4,
-                .end   = S3C64XX_PA_XM0CSN1 + 5,
-                .flags = IORESOURCE_MEM
-        },
-        [2] = {
-                .start = S3C_EINT(7),
-                .end   = S3C_EINT(7),
-                .flags = IORESOURCE_IRQ,
-        }
+        [0] = {
+                .start  = S3C64XX_PA_XM0CSN1,
+                .end    = S3C64XX_PA_XM0CSN1 + 1,
+                .flags  = IORESOURCE_MEM
+        },
+        [1] = {
+                .start  = S3C64XX_PA_XM0CSN1 + 4,
+                .end    = S3C64XX_PA_XM0CSN1 + 5,
+                .flags  = IORESOURCE_MEM
+        },
+        [2] = {
+                .start  = S3C_EINT(7),
+                .end    = S3C_EINT(7),
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL
+        }
 };
 
 static struct dm9000_plat_data real6410_dm9k_pdata = {
-        .flags          = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
+        .flags          = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
 };
 
 static struct platform_device real6410_device_eth = {
-        .name           = "dm9000",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(real6410_dm9k_resource),
-        .resource       = real6410_dm9k_resource,
-        .dev            = {
-                .platform_data  = &real6410_dm9k_pdata,
-        },
+        .name           = "dm9000",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(real6410_dm9k_resource),
+        .resource       = real6410_dm9k_resource,
+        .dev            = {
+                .platform_data  = &real6410_dm9k_pdata,
+        },
 };
 
 static struct platform_device *real6410_devices[] __initdata = {
@@ -129,12 +129,12 @@ static void __init real6410_machine_init(void)
         /* set timing for nCS1 suitable for ethernet chip */
 
         __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
-                        (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
-                        (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
-                        (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
-                        (13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
-                        (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
-                        (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
+                (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
+                (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
+                (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
+                (13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
+                (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
+                (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
 
         platform_add_devices(real6410_devices, ARRAY_SIZE(real6410_devices));
 }
diff --git a/arch/arm/mach-s5p6440/Kconfig b/arch/arm/mach-s5p6440/Kconfig
deleted file mode 100644
index 6a4af7f57584..000000000000
--- a/arch/arm/mach-s5p6440/Kconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-# arch/arm/mach-s5p6440/Kconfig
-#
-# Copyright (c) 2009 Samsung Electronics Co., Ltd.
-#               http://www.samsung.com/
-#
-# Licensed under GPLv2
-
-if ARCH_S5P6440
-
-config CPU_S5P6440
-        bool
-        select S3C_PL330_DMA
-        help
-          Enable S5P6440 CPU support
-
-config S5P6440_SETUP_I2C1
-        bool
-        help
-          Common setup code for i2c bus 1.
-
-config MACH_SMDK6440
-        bool "SMDK6440"
-        select CPU_S5P6440
-        select S3C_DEV_I2C1
-        select S3C_DEV_RTC
-        select S3C_DEV_WDT
-        select SAMSUNG_DEV_ADC
-        select SAMSUNG_DEV_TS
-        select S5P6440_SETUP_I2C1
-        help
-          Machine support for the Samsung SMDK6440
-
-endif
diff --git a/arch/arm/mach-s5p6440/Makefile b/arch/arm/mach-s5p6440/Makefile
deleted file mode 100644
index c3fe4d3662a9..000000000000
--- a/arch/arm/mach-s5p6440/Makefile
+++ /dev/null
@@ -1,25 +0,0 @@
-# arch/arm/mach-s5p6440/Makefile
-#
-# Copyright (c) 2009 Samsung Electronics Co., Ltd.
-#               http://www.samsung.com/
-#
-# Licensed under GPLv2
-
-obj-y                           :=
-obj-m                           :=
-obj-n                           :=
-obj-                            :=
-
-# Core support for S5P6440 system
-
-obj-$(CONFIG_CPU_S5P6440)       += cpu.o init.o clock.o gpio.o dma.o
-obj-$(CONFIG_CPU_S5P6440)       += setup-i2c0.o
-
-# machine support
-
-obj-$(CONFIG_MACH_SMDK6440)     += mach-smdk6440.o
-
-# device support
-obj-y                           += dev-audio.o
-obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
-obj-$(CONFIG_S5P6440_SETUP_I2C1)        += setup-i2c1.o
diff --git a/arch/arm/mach-s5p6440/clock.c b/arch/arm/mach-s5p6440/clock.c
deleted file mode 100644
index ca6e48dce777..000000000000
--- a/arch/arm/mach-s5p6440/clock.c
+++ /dev/null
@@ -1,846 +0,0 @@
-/* linux/arch/arm/mach-s5p6440/clock.c
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P6440 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/sysdev.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-
-#include <plat/cpu-freq.h>
-#include <mach/regs-clock.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/clock-clksrc.h>
-#include <plat/s5p-clock.h>
-#include <plat/pll.h>
-#include <plat/s5p6440.h>
-
-/* APLL Mux output clock */
-static struct clksrc_clk clk_mout_apll = {
-        .clk    = {
-                .name           = "mout_apll",
-                .id             = -1,
-        },
-        .sources        = &clk_src_apll,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
-};
-
-static int s5p6440_epll_enable(struct clk *clk, int enable)
-{
-        unsigned int ctrlbit = clk->ctrlbit;
-        unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
-
-        if (enable)
-                __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
-        else
-                __raw_writel(epll_con, S5P_EPLL_CON);
-
-        return 0;
-}
-
-static unsigned long s5p6440_epll_get_rate(struct clk *clk)
-{
-        return clk->rate;
-}
-
-static u32 epll_div[][5] = {
-        { 36000000,     0,      48, 1, 4 },
-        { 48000000,     0,      32, 1, 3 },
-        { 60000000,     0,      40, 1, 3 },
-        { 72000000,     0,      48, 1, 3 },
-        { 84000000,     0,      28, 1, 2 },
-        { 96000000,     0,      32, 1, 2 },
-        { 32768000,     45264,  43, 1, 4 },
-        { 45158000,     6903,   30, 1, 3 },
-        { 49152000,     50332,  32, 1, 3 },
-        { 67738000,     10398,  45, 1, 3 },
-        { 73728000,     9961,   49, 1, 3 }
-};
-
-static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int epll_con, epll_con_k;
-        unsigned int i;
-
-        if (clk->rate == rate)  /* Return if nothing changed */
-                return 0;
-
-        epll_con = __raw_readl(S5P_EPLL_CON);
-        epll_con_k = __raw_readl(S5P_EPLL_CON_K);
-
-        epll_con_k &= ~(PLL90XX_KDIV_MASK);
-        epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
-
-        for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
-                 if (epll_div[i][0] == rate) {
-                        epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
-                        epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
-                                    (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
-                                    (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
-                        break;
-                }
-        }
-
-        if (i == ARRAY_SIZE(epll_div)) {
-                printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
-                return -EINVAL;
-        }
-
-        __raw_writel(epll_con, S5P_EPLL_CON);
-        __raw_writel(epll_con_k, S5P_EPLL_CON_K);
-
-        clk->rate = rate;
-
-        return 0;
-}
-
-static struct clk_ops s5p6440_epll_ops = {
-        .get_rate = s5p6440_epll_get_rate,
-        .set_rate = s5p6440_epll_set_rate,
-};
-
-static struct clksrc_clk clk_mout_epll = {
-        .clk    = {
-                .name           = "mout_epll",
-                .id             = -1,
-        },
-        .sources        = &clk_src_epll,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 2, .size = 1 },
-};
-
-static struct clksrc_clk clk_mout_mpll = {
-        .clk = {
-                .name           = "mout_mpll",
-                .id             = -1,
-        },
-        .sources        = &clk_src_mpll,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 },
-};
-
-enum perf_level {
-        L0 = 532*1000,
-        L1 = 266*1000,
-        L2 = 133*1000,
-};
-
-static const u32 clock_table[][3] = {
-        /*{ARM_CLK, DIVarm, DIVhclk}*/
-        {L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P_CLKDIV0_HCLK_SHIFT)},
-        {L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P_CLKDIV0_HCLK_SHIFT)},
-        {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P_CLKDIV0_HCLK_SHIFT)},
-};
-
-static unsigned long s5p6440_armclk_get_rate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        u32 clkdiv;
-
-        /* divisor mask starts at bit0, so no need to shift */
-        clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK;
-
-        return rate / (clkdiv + 1);
-}
-
-static unsigned long s5p6440_armclk_round_rate(struct clk *clk,
-                                                unsigned long rate)
-{
-        u32 iter;
-
-        for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
-                if (rate > clock_table[iter][0])
-                        return clock_table[iter-1][0];
-        }
-
-        return clock_table[ARRAY_SIZE(clock_table) - 1][0];
-}
-
-static int s5p6440_armclk_set_rate(struct clk *clk, unsigned long rate)
-{
-        u32 round_tmp;
-        u32 iter;
-        u32 clk_div0_tmp;
-        u32 cur_rate = clk->ops->get_rate(clk);
-        unsigned long flags;
-
-        round_tmp = clk->ops->round_rate(clk, rate);
-        if (round_tmp == cur_rate)
-                return 0;
-
-
-        for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
-                if (round_tmp == clock_table[iter][0])
-                        break;
-        }
-
-        if (iter >= ARRAY_SIZE(clock_table))
-                iter = ARRAY_SIZE(clock_table) - 1;
-
-        local_irq_save(flags);
-        if (cur_rate > round_tmp) {
-                /* Frequency Down */
-                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
-                clk_div0_tmp |= clock_table[iter][1];
-                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
-
-                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
-                                ~(S5P_CLKDIV0_HCLK_MASK);
-                clk_div0_tmp |= clock_table[iter][2];
-                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
-
-
-        } else {
-                /* Frequency Up */
-                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
-                                ~(S5P_CLKDIV0_HCLK_MASK);
-                clk_div0_tmp |= clock_table[iter][2];
-                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
-
-                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
-                clk_div0_tmp |= clock_table[iter][1];
-                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
-                }
-        local_irq_restore(flags);
-
-        clk->rate = clock_table[iter][0];
-
-        return 0;
-}
-
-static struct clk_ops s5p6440_clkarm_ops = {
-        .get_rate       = s5p6440_armclk_get_rate,
-        .set_rate       = s5p6440_armclk_set_rate,
-        .round_rate     = s5p6440_armclk_round_rate,
-};
-
-static struct clksrc_clk clk_armclk = {
-        .clk    = {
-                .name   = "armclk",
-                .id     = 1,
-                .parent = &clk_mout_apll.clk,
-                .ops    = &s5p6440_clkarm_ops,
-        },
-        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_dout_mpll = {
-        .clk    = {
-                .name   = "dout_mpll",
-                .id     = -1,
-                .parent = &clk_mout_mpll.clk,
-        },
-        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk clk_hclk = {
-        .clk    = {
-                .name   = "clk_hclk",
-                .id     = -1,
-                .parent = &clk_armclk.clk,
-        },
-        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk clk_pclk = {
-        .clk    = {
-                .name   = "clk_pclk",
-                .id     = -1,
-                .parent = &clk_hclk.clk,
-        },
-        .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 4 },
-};
-
-static struct clk *clkset_hclklow_list[] = {
-        &clk_mout_apll.clk,
-        &clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources clkset_hclklow = {
-        .sources        = clkset_hclklow_list,
-        .nr_sources     = ARRAY_SIZE(clkset_hclklow_list),
-};
-
-static struct clksrc_clk clk_hclk_low = {
-        .clk = {
-                .name   = "hclk_low",
-                .id     = -1,
-        },
-        .sources        = &clkset_hclklow,
-        .reg_src        = { .reg = S5P_SYS_OTHERS, .shift = 6, .size = 1 },
-        .reg_div        = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk clk_pclk_low = {
-        .clk    = {
-                .name   = "pclk_low",
-                .id     = -1,
-                .parent = &clk_hclk_low.clk,
-        },
-        .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
-};
-
-int s5p6440_clk48m_ctrl(struct clk *clk, int enable)
-{
-        unsigned long flags;
-        u32 val;
-
-        /* can't rely on clock lock, this register has other usages */
-        local_irq_save(flags);
-
-        val = __raw_readl(S5P_OTHERS);
-        if (enable)
-                val |= S5P_OTHERS_USB_SIG_MASK;
-        else
-                val &= ~S5P_OTHERS_USB_SIG_MASK;
-
-        __raw_writel(val, S5P_OTHERS);
-
-        local_irq_restore(flags);
-
-        return 0;
-}
-
-static int s5p6440_pclk_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLK_GATE_PCLK, clk, enable);
-}
-
-static int s5p6440_hclk0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLK_GATE_HCLK0, clk, enable);
-}
-
-static int s5p6440_hclk1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLK_GATE_HCLK1, clk, enable);
-}
-
-static int s5p6440_sclk_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable);
-}
-
-static int s5p6440_sclk1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLK_GATE_SCLK1, clk, enable);
-}
-
-static int s5p6440_mem_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable);
-}
-
-/*
- * The following clocks will be disabled during clock initialization. It is
- * recommended to keep the following clocks disabled until the driver requests
- * for enabling the clock.
- */
-static struct clk init_clocks_disable[] = {
-        {
-                .name           = "nand",
-                .id             = -1,
-                .parent         = &clk_hclk.clk,
-                .enable         = s5p6440_mem_ctrl,
-                .ctrlbit        = S5P_CLKCON_MEM0_HCLK_NFCON,
-        }, {
-                .name           = "adc",
-                .id             = -1,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_TSADC,
-        }, {
-                .name           = "i2c",
-                .id             = -1,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_IIC0,
-        }, {
-                .name           = "i2s_v40",
-                .id             = 0,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_IIS2,
-        }, {
-                .name           = "spi",
-                .id             = 0,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_SPI0,
-        }, {
-                .name           = "spi",
-                .id             = 1,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_SPI1,
-        }, {
-                .name           = "sclk_spi_48",
-                .id             = 0,
-                .parent         = &clk_48m,
-                .enable         = s5p6440_sclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_SCLK0_SPI0_48,
-        }, {
-                .name           = "sclk_spi_48",
-                .id             = 1,
-                .parent         = &clk_48m,
-                .enable         = s5p6440_sclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_SCLK0_SPI1_48,
-        }, {
-                .name           = "mmc_48m",
-                .id             = 0,
-                .parent         = &clk_48m,
-                .enable         = s5p6440_sclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_SCLK0_MMC0_48,
-        }, {
-                .name           = "mmc_48m",
-                .id             = 1,
-                .parent         = &clk_48m,
-                .enable         = s5p6440_sclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_SCLK0_MMC1_48,
-        }, {
-                .name           = "mmc_48m",
-                .id             = 2,
-                .parent         = &clk_48m,
-                .enable         = s5p6440_sclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_SCLK0_MMC2_48,
-        }, {
-                .name           = "otg",
-                .id             = -1,
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p6440_hclk0_ctrl,
-                .ctrlbit        = S5P_CLKCON_HCLK0_USB
-        }, {
-                .name           = "post",
-                .id             = -1,
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p6440_hclk0_ctrl,
-                .ctrlbit        = S5P_CLKCON_HCLK0_POST0
-        }, {
-                .name           = "lcd",
-                .id             = -1,
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p6440_hclk1_ctrl,
-                .ctrlbit        = S5P_CLKCON_HCLK1_DISPCON,
-        }, {
-                .name           = "hsmmc",
-                .id             = 0,
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p6440_hclk0_ctrl,
-                .ctrlbit        = S5P_CLKCON_HCLK0_HSMMC0,
-        }, {
-                .name           = "hsmmc",
-                .id             = 1,
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p6440_hclk0_ctrl,
-                .ctrlbit        = S5P_CLKCON_HCLK0_HSMMC1,
-        }, {
-                .name           = "hsmmc",
-                .id             = 2,
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p6440_hclk0_ctrl,
-                .ctrlbit        = S5P_CLKCON_HCLK0_HSMMC2,
-        }, {
-                .name           = "rtc",
-                .id             = -1,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_RTC,
-        }, {
-                .name           = "watchdog",
-                .id             = -1,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_WDT,
-        }, {
-                .name           = "timers",
-                .id             = -1,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_PWM,
-        }, {
-                .name           = "hclk_fimgvg",
-                .id             = -1,
-                .parent         = &clk_hclk.clk,
-                .enable         = s5p6440_hclk1_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "tsi",
-                .id             = -1,
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p6440_hclk1_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "pclk_fimgvg",
-                .id             = -1,
-                .parent         = &clk_pclk.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = (1 << 31),
-        }, {
-                .name           = "dmc0",
-                .id             = -1,
-                .parent         = &clk_pclk.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = (1 << 30),
-        }, {
-                .name           = "etm",
-                .id             = -1,
-                .parent         = &clk_pclk.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = (1 << 29),
-        }, {
-                .name           = "dsim",
-                .id             = -1,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = (1 << 28),
-        }, {
-                .name           = "gps",
-                .id             = -1,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = (1 << 25),
-        }, {
-                .name           = "pcm",
-                .id             = -1,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "irom",
-                .id             = -1,
-                .parent         = &clk_hclk.clk,
-                .enable         = s5p6440_hclk0_ctrl,
-                .ctrlbit        = (1 << 25),
-        }, {
-                .name           = "dma",
-                .id             = -1,
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p6440_hclk0_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "2d",
-                .id             = -1,
-                .parent         = &clk_hclk.clk,
-                .enable         = s5p6440_hclk0_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-};
-
-/*
- * The following clocks will be enabled during clock initialization.
- */
-static struct clk init_clocks[] = {
-        {
-                .name           = "gpio",
-                .id             = -1,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_GPIO,
-        }, {
-                .name           = "uart",
-                .id             = 0,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_UART0,
-        }, {
-                .name           = "uart",
-                .id             = 1,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_UART1,
-        }, {
-                .name           = "uart",
-                .id             = 2,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_UART2,
-        }, {
-                .name           = "uart",
-                .id             = 3,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_UART3,
-        }, {
-                .name           = "mem",
-                .id             = -1,
-                .parent         = &clk_hclk.clk,
-                .enable         = s5p6440_hclk0_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "intc",
-                .id             = -1,
-                .parent         = &clk_hclk.clk,
-                .enable         = s5p6440_hclk0_ctrl,
-                .ctrlbit        = (1 << 1),
-        },
-};
-
-static struct clk clk_iis_cd_v40 = {
-        .name           = "iis_cdclk_v40",
-        .id             = -1,
-};
-
-static struct clk clk_pcm_cd = {
-        .name           = "pcm_cdclk",
-        .id             = -1,
-};
-
-static struct clk *clkset_group1_list[] = {
-        &clk_mout_epll.clk,
-        &clk_dout_mpll.clk,
-        &clk_fin_epll,
-};
-
-static struct clksrc_sources clkset_group1 = {
-        .sources        = clkset_group1_list,
-        .nr_sources     = ARRAY_SIZE(clkset_group1_list),
-};
-
-static struct clk *clkset_uart_list[] = {
-        &clk_mout_epll.clk,
-        &clk_dout_mpll.clk,
-};
-
-static struct clksrc_sources clkset_uart = {
-        .sources        = clkset_uart_list,
-        .nr_sources     = ARRAY_SIZE(clkset_uart_list),
-};
-
-static struct clk *clkset_audio_list[] = {
-        &clk_mout_epll.clk,
-        &clk_dout_mpll.clk,
-        &clk_fin_epll,
-        &clk_iis_cd_v40,
-        &clk_pcm_cd,
-};
-
-static struct clksrc_sources clkset_audio = {
-        .sources        = clkset_audio_list,
-        .nr_sources     = ARRAY_SIZE(clkset_audio_list),
-};
-
-static struct clksrc_clk clksrcs[] = {
-        {
-                .clk    = {
-                        .name           = "mmc_bus",
-                        .id             = 0,
-                        .ctrlbit        = S5P_CLKCON_SCLK0_MMC0,
-                        .enable         = s5p6440_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "mmc_bus",
-                        .id             = 1,
-                        .ctrlbit        = S5P_CLKCON_SCLK0_MMC1,
-                        .enable         = s5p6440_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "mmc_bus",
-                        .id             = 2,
-                        .ctrlbit        = S5P_CLKCON_SCLK0_MMC2,
-                        .enable         = s5p6440_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "uclk1",
-                        .id             = -1,
-                        .ctrlbit        = S5P_CLKCON_SCLK0_UART,
-                        .enable         = s5p6440_sclk_ctrl,
-                },
-                .sources = &clkset_uart,
-                .reg_src = { .reg = S5P_CLK_SRC0, .shift = 13, .size = 1 },
-                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "spi_epll",
-                        .id             = 0,
-                        .ctrlbit        = S5P_CLKCON_SCLK0_SPI0,
-                        .enable         = s5p6440_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "spi_epll",
-                        .id             = 1,
-                        .ctrlbit        = S5P_CLKCON_SCLK0_SPI1,
-                        .enable         = s5p6440_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_post",
-                        .id             = -1,
-                        .ctrlbit        = (1 << 10),
-                        .enable         = s5p6440_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P_CLK_SRC0, .shift = 26, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_dispcon",
-                        .id             = -1,
-                        .ctrlbit        = (1 << 1),
-                        .enable         = s5p6440_sclk1_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimgvg",
-                        .id             = -1,
-                        .ctrlbit        = (1 << 2),
-                        .enable         = s5p6440_sclk1_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_audio2",
-                        .id             = -1,
-                        .ctrlbit        = (1 << 11),
-                        .enable         = s5p6440_sclk_ctrl,
-                },
-                .sources = &clkset_audio,
-                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 3 },
-                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 24, .size = 4 },
-        },
-};
-
-/* Clock initialisation code */
-static struct clksrc_clk *sysclks[] = {
-        &clk_mout_apll,
-        &clk_mout_epll,
-        &clk_mout_mpll,
-        &clk_dout_mpll,
-        &clk_armclk,
-        &clk_hclk,
-        &clk_pclk,
-        &clk_hclk_low,
-        &clk_pclk_low,
-};
-
-void __init_or_cpufreq s5p6440_setup_clocks(void)
-{
-        struct clk *xtal_clk;
-        unsigned long xtal;
-        unsigned long fclk;
-        unsigned long hclk;
-        unsigned long hclk_low;
-        unsigned long pclk;
-        unsigned long pclk_low;
-        unsigned long epll;
-        unsigned long apll;
-        unsigned long mpll;
-        unsigned int ptr;
-
-        /* Set S5P6440 functions for clk_fout_epll */
-        clk_fout_epll.enable = s5p6440_epll_enable;
-        clk_fout_epll.ops = &s5p6440_epll_ops;
-
-        clk_48m.enable = s5p6440_clk48m_ctrl;
-
-        xtal_clk = clk_get(NULL, "ext_xtal");
-        BUG_ON(IS_ERR(xtal_clk));
-
-        xtal = clk_get_rate(xtal_clk);
-        clk_put(xtal_clk);
-
-        epll = s5p_get_pll90xx(xtal, __raw_readl(S5P_EPLL_CON),
-                                __raw_readl(S5P_EPLL_CON_K));
-        mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
-        apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502);
-
-        clk_fout_mpll.rate = mpll;
-        clk_fout_epll.rate = epll;
-        clk_fout_apll.rate = apll;
-
-        printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
-                        " E=%ld.%ldMHz\n",
-                        print_mhz(apll), print_mhz(mpll), print_mhz(epll));
-
-        fclk = clk_get_rate(&clk_armclk.clk);
-        hclk = clk_get_rate(&clk_hclk.clk);
-        pclk = clk_get_rate(&clk_pclk.clk);
-        hclk_low = clk_get_rate(&clk_hclk_low.clk);
-        pclk_low = clk_get_rate(&clk_pclk_low.clk);
-
-        printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
-                        " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
-                        print_mhz(hclk), print_mhz(hclk_low),
-                        print_mhz(pclk), print_mhz(pclk_low));
-
-        clk_f.rate = fclk;
-        clk_h.rate = hclk;
-        clk_p.rate = pclk;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
-                s3c_set_clksrc(&clksrcs[ptr], true);
-}
-
-static struct clk *clks[] __initdata = {
-        &clk_ext,
-        &clk_iis_cd_v40,
-        &clk_pcm_cd,
-};
-
-void __init s5p6440_register_clocks(void)
-{
-        struct clk *clkp;
-        int ret;
-        int ptr;
-
-        ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
-        if (ret > 0)
-                printk(KERN_ERR "Failed to register %u clocks\n", ret);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-                s3c_register_clksrc(sysclks[ptr], 1);
-
-        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
-
-        clkp = init_clocks_disable;
-        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
-
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-                (clkp->enable)(clkp, 0);
-        }
-
-        s3c_pwmclk_init();
-}
diff --git a/arch/arm/mach-s5p6440/cpu.c b/arch/arm/mach-s5p6440/cpu.c
deleted file mode 100644
index 526f33adb31d..000000000000
--- a/arch/arm/mach-s5p6440/cpu.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/* linux/arch/arm/mach-s5p6440/cpu.c
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/sysdev.h>
-#include <linux/serial_core.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <asm/proc-fns.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <asm/irq.h>
-
-#include <plat/regs-serial.h>
-#include <mach/regs-clock.h>
-
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/clock.h>
-#include <plat/s5p6440.h>
-#include <plat/adc-core.h>
-
-static void s5p6440_idle(void)
-{
-        unsigned long val;
-
-        if (!need_resched()) {
-                val = __raw_readl(S5P_PWR_CFG);
-                val &= ~(0x3<<5);
-                val |= (0x1<<5);
-                __raw_writel(val, S5P_PWR_CFG);
-
-                cpu_do_idle();
-        }
-        local_irq_enable();
-}
-
-/* s5p6440_map_io
- *
- * register the standard cpu IO areas
-*/
-
-void __init s5p6440_map_io(void)
-{
-        /* initialize any device information early */
-        s3c_adc_setname("s3c64xx-adc");
-}
-
-void __init s5p6440_init_clocks(int xtal)
-{
-        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
-
-        s3c24xx_register_baseclocks(xtal);
-        s5p_register_clocks(xtal);
-        s5p6440_register_clocks();
-        s5p6440_setup_clocks();
-}
-
-void __init s5p6440_init_irq(void)
-{
-        /* S5P6440 supports only 2 VIC */
-        u32 vic[2];
-
-        /*
-         * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
-         * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
-         */
-        vic[0] = 0xff800ae7;
-        vic[1] = 0xffbf23e5;
-
-        s5p_init_irq(vic, ARRAY_SIZE(vic));
-}
-
-struct sysdev_class s5p6440_sysclass = {
-        .name   = "s5p6440-core",
-};
-
-static struct sys_device s5p6440_sysdev = {
-        .cls    = &s5p6440_sysclass,
-};
-
-static int __init s5p6440_core_init(void)
-{
-        return sysdev_class_register(&s5p6440_sysclass);
-}
-
-core_initcall(s5p6440_core_init);
-
-int __init s5p6440_init(void)
-{
-        printk(KERN_INFO "S5P6440: Initializing architecture\n");
-
-        /* set idle function */
-        pm_idle = s5p6440_idle;
-
-        return sysdev_register(&s5p6440_sysdev);
-}
diff --git a/arch/arm/mach-s5p6440/dev-audio.c b/arch/arm/mach-s5p6440/dev-audio.c
deleted file mode 100644
index 3ca0d2b8275d..000000000000
--- a/arch/arm/mach-s5p6440/dev-audio.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/* linux/arch/arm/mach-s5p6440/dev-audio.c
- *
- * Copyright (c) 2010 Samsung Electronics Co. Ltd
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-
-#include <plat/gpio-cfg.h>
-#include <plat/audio.h>
-
-#include <mach/map.h>
-#include <mach/dma.h>
-#include <mach/irqs.h>
-
-static int s5p6440_cfg_i2s(struct platform_device *pdev)
-{
-        /* configure GPIO for i2s port */
-        switch (pdev->id) {
-        case -1:
-                s3c_gpio_cfgpin(S5P6440_GPR(4), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6440_GPR(5), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(5));
-                break;
-
-        default:
-                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static struct s3c_audio_pdata s3c_i2s_pdata = {
-        .cfg_gpio = s5p6440_cfg_i2s,
-};
-
-static struct resource s5p6440_iis0_resource[] = {
-        [0] = {
-                .start = S5P6440_PA_I2S,
-                .end   = S5P6440_PA_I2S + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_I2S0_TX,
-                .end   = DMACH_I2S0_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_I2S0_RX,
-                .end   = DMACH_I2S0_RX,
-                .flags = IORESOURCE_DMA,
-        },
-};
-
-struct platform_device s5p6440_device_iis = {
-        .name             = "s3c64xx-iis-v4",
-        .id               = -1,
-        .num_resources    = ARRAY_SIZE(s5p6440_iis0_resource),
-        .resource         = s5p6440_iis0_resource,
-        .dev = {
-                .platform_data = &s3c_i2s_pdata,
-        },
-};
-
-/* PCM Controller platform_devices */
-
-static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev)
-{
-        switch (pdev->id) {
-        case 0:
-                s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(2));
-                break;
-
-        default:
-                printk(KERN_DEBUG "Invalid PCM Controller number!");
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static struct s3c_audio_pdata s3c_pcm_pdata = {
-        .cfg_gpio = s5p6440_pcm_cfg_gpio,
-};
-
-static struct resource s5p6440_pcm0_resource[] = {
-        [0] = {
-                .start = S5P6440_PA_PCM,
-                .end   = S5P6440_PA_PCM + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_PCM0_TX,
-                .end   = DMACH_PCM0_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_PCM0_RX,
-                .end   = DMACH_PCM0_RX,
-                .flags = IORESOURCE_DMA,
-        },
-};
-
-struct platform_device s5p6440_device_pcm = {
-        .name             = "samsung-pcm",
-        .id               = 0,
-        .num_resources    = ARRAY_SIZE(s5p6440_pcm0_resource),
-        .resource         = s5p6440_pcm0_resource,
-        .dev = {
-                .platform_data = &s3c_pcm_pdata,
-        },
-};
diff --git a/arch/arm/mach-s5p6440/dev-spi.c b/arch/arm/mach-s5p6440/dev-spi.c
deleted file mode 100644
index 510af44d180c..000000000000
--- a/arch/arm/mach-s5p6440/dev-spi.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/* linux/arch/arm/mach-s5p6440/dev-spi.c
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-
-#include <mach/dma.h>
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <mach/spi-clocks.h>
-
-#include <plat/s3c64xx-spi.h>
-#include <plat/gpio-cfg.h>
-
-static char *spi_src_clks[] = {
-        [S5P6440_SPI_SRCCLK_PCLK] = "pclk",
-        [S5P6440_SPI_SRCCLK_SCLK] = "spi_epll",
-};
-
-/* SPI Controller platform_devices */
-
-/* Since we emulate multi-cs capability, we do not touch the CS.
- * The emulated CS is toggled by board specific mechanism, as it can
- * be either some immediate GPIO or some signal out of some other
- * chip in between ... or some yet another way.
- * We simply do not assume anything about CS.
- */
-static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
-{
-        switch (pdev->id) {
-        case 0:
-                s3c_gpio_cfgpin(S5P6440_GPC(0), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPC(1), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPC(2), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(S5P6440_GPC(0), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5P6440_GPC(1), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5P6440_GPC(2), S3C_GPIO_PULL_UP);
-                break;
-
-        case 1:
-                s3c_gpio_cfgpin(S5P6440_GPC(4), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPC(5), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPC(6), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(S5P6440_GPC(4), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5P6440_GPC(5), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5P6440_GPC(6), S3C_GPIO_PULL_UP);
-                break;
-
-        default:
-                dev_err(&pdev->dev, "Invalid SPI Controller number!");
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static struct resource s5p6440_spi0_resource[] = {
-        [0] = {
-                .start = S5P6440_PA_SPI0,
-                .end   = S5P6440_PA_SPI0 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_SPI0_TX,
-                .end   = DMACH_SPI0_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_SPI0_RX,
-                .end   = DMACH_SPI0_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = IRQ_SPI0,
-                .end   = IRQ_SPI0,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
-        .cfg_gpio = s5p6440_spi_cfg_gpio,
-        .fifo_lvl_mask = 0x1ff,
-        .rx_lvl_offset = 15,
-};
-
-static u64 spi_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device s5p6440_device_spi0 = {
-        .name             = "s3c64xx-spi",
-        .id               = 0,
-        .num_resources    = ARRAY_SIZE(s5p6440_spi0_resource),
-        .resource         = s5p6440_spi0_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data = &s5p6440_spi0_pdata,
-        },
-};
-
-static struct resource s5p6440_spi1_resource[] = {
-        [0] = {
-                .start = S5P6440_PA_SPI1,
-                .end   = S5P6440_PA_SPI1 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_SPI1_TX,
-                .end   = DMACH_SPI1_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_SPI1_RX,
-                .end   = DMACH_SPI1_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = IRQ_SPI1,
-                .end   = IRQ_SPI1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
-        .cfg_gpio = s5p6440_spi_cfg_gpio,
-        .fifo_lvl_mask = 0x7f,
-        .rx_lvl_offset = 15,
-};
-
-struct platform_device s5p6440_device_spi1 = {
-        .name             = "s3c64xx-spi",
-        .id               = 1,
-        .num_resources    = ARRAY_SIZE(s5p6440_spi1_resource),
-        .resource         = s5p6440_spi1_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data = &s5p6440_spi1_pdata,
-        },
-};
-
-void __init s5p6440_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
-{
-        struct s3c64xx_spi_info *pd;
-
-        /* Reject invalid configuration */
-        if (!num_cs || src_clk_nr < 0
-                        || src_clk_nr > S5P6440_SPI_SRCCLK_SCLK) {
-                printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
-                return;
-        }
-
-        switch (cntrlr) {
-        case 0:
-                pd = &s5p6440_spi0_pdata;
-                break;
-        case 1:
-                pd = &s5p6440_spi1_pdata;
-                break;
-        default:
-                printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
-                                                        __func__, cntrlr);
-                return;
-        }
-
-        pd->num_cs = num_cs;
-        pd->src_clk_nr = src_clk_nr;
-        pd->src_clk_name = spi_src_clks[src_clk_nr];
-}
diff --git a/arch/arm/mach-s5p6440/include/mach/debug-macro.S b/arch/arm/mach-s5p6440/include/mach/debug-macro.S
deleted file mode 100644
index 1347d7f99079..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/debug-macro.S
+++ /dev/null
@@ -1,37 +0,0 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/debug-macro.S
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* pull in the relevant register and map files. */
-
-#include <mach/map.h>
-#include <plat/regs-serial.h>
-
-        /* note, for the boot process to work we have to keep the UART
-         * virtual address aligned to an 1MiB boundary for the L1
-         * mapping the head code makes. We keep the UART virtual address
-         * aligned and add in the offset when we load the value here.
-         */
-
-        .macro addruart, rx, rtmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1
-                ldreq   \rx, = S3C_PA_UART
-                ldrne   \rx, = S3C_VA_UART
-#if CONFIG_DEBUG_S3C_UART != 0
-                add     \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
-#endif
-        .endm
-
-/* include the reset of the code which will do the work, we're only
- * compiling for a single cpu processor type so the default of s3c2440
- * will be fine with us.
- */
-
-#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s5p6440/include/mach/gpio.h b/arch/arm/mach-s5p6440/include/mach/gpio.h
deleted file mode 100644
index 21783834f2a2..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/gpio.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/gpio.h
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P6440 - GPIO lib support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H __FILE__
-
-#define gpio_get_value  __gpio_get_value
-#define gpio_set_value  __gpio_set_value
-#define gpio_cansleep   __gpio_cansleep
-#define gpio_to_irq     __gpio_to_irq
-
-/* GPIO bank sizes */
-#define S5P6440_GPIO_A_NR       (6)
-#define S5P6440_GPIO_B_NR       (7)
-#define S5P6440_GPIO_C_NR       (8)
-#define S5P6440_GPIO_F_NR       (2)
-#define S5P6440_GPIO_G_NR       (7)
-#define S5P6440_GPIO_H_NR       (10)
-#define S5P6440_GPIO_I_NR       (16)
-#define S5P6440_GPIO_J_NR       (12)
-#define S5P6440_GPIO_N_NR       (16)
-#define S5P6440_GPIO_P_NR       (8)
-#define S5P6440_GPIO_R_NR       (15)
-
-/* GPIO bank numbers */
-
-/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
- * space for debugging purposes so that any accidental
- * change from one gpio bank to another can be caught.
-*/
-#define S5P6440_GPIO_NEXT(__gpio) \
-        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
-
-enum s5p_gpio_number {
-        S5P6440_GPIO_A_START = 0,
-        S5P6440_GPIO_B_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_A),
-        S5P6440_GPIO_C_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_B),
-        S5P6440_GPIO_F_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_C),
-        S5P6440_GPIO_G_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_F),
-        S5P6440_GPIO_H_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_G),
-        S5P6440_GPIO_I_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_H),
-        S5P6440_GPIO_J_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_I),
-        S5P6440_GPIO_N_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_J),
-        S5P6440_GPIO_P_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_N),
-        S5P6440_GPIO_R_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_P),
-};
-
-/* S5P6440 GPIO number definitions. */
-#define S5P6440_GPA(_nr)        (S5P6440_GPIO_A_START + (_nr))
-#define S5P6440_GPB(_nr)        (S5P6440_GPIO_B_START + (_nr))
-#define S5P6440_GPC(_nr)        (S5P6440_GPIO_C_START + (_nr))
-#define S5P6440_GPF(_nr)        (S5P6440_GPIO_F_START + (_nr))
-#define S5P6440_GPG(_nr)        (S5P6440_GPIO_G_START + (_nr))
-#define S5P6440_GPH(_nr)        (S5P6440_GPIO_H_START + (_nr))
-#define S5P6440_GPI(_nr)        (S5P6440_GPIO_I_START + (_nr))
-#define S5P6440_GPJ(_nr)        (S5P6440_GPIO_J_START + (_nr))
-#define S5P6440_GPN(_nr)        (S5P6440_GPIO_N_START + (_nr))
-#define S5P6440_GPP(_nr)        (S5P6440_GPIO_P_START + (_nr))
-#define S5P6440_GPR(_nr)        (S5P6440_GPIO_R_START + (_nr))
-
-/* the end of the S5P6440 specific gpios */
-#define S5P6440_GPIO_END        (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1)
-#define S3C_GPIO_END            S5P6440_GPIO_END
-
-/* define the number of gpios we need to the one after the GPR() range */
-#define ARCH_NR_GPIOS           (S5P6440_GPR(S5P6440_GPIO_R_NR) +       \
-                                 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
-
-#include <asm-generic/gpio.h>
-
-#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/io.h b/arch/arm/mach-s5p6440/include/mach/io.h
deleted file mode 100644
index fa2d69cb1ad7..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/io.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* arch/arm/mach-s5p6440/include/mach/io.h
- *
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben-linux@fluff.org>
- *
- * Default IO routines for S3C64XX based
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-/* No current ISA/PCI bus support. */
-#define __io(a)         __typesafe_io(a)
-#define __mem_pci(a)    (a)
-
-#define IO_SPACE_LIMIT (0xFFFFFFFF)
-
-#endif
diff --git a/arch/arm/mach-s5p6440/include/mach/map.h b/arch/arm/mach-s5p6440/include/mach/map.h
deleted file mode 100644
index 6cc5cbc88ffb..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/map.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/map.h
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P6440 - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_MAP_H
-#define __ASM_ARCH_MAP_H __FILE__
-
-#include <plat/map-base.h>
-#include <plat/map-s5p.h>
-
-#define S5P6440_PA_CHIPID       (0xE0000000)
-#define S5P_PA_CHIPID           S5P6440_PA_CHIPID
-
-#define S5P6440_PA_SYSCON       (0xE0100000)
-#define S5P6440_PA_CLK          (S5P6440_PA_SYSCON + 0x0)
-#define S5P_PA_SYSCON           S5P6440_PA_SYSCON
-
-#define S5P6440_PA_GPIO         (0xE0308000)
-#define S5P_PA_GPIO             S5P6440_PA_GPIO
-
-#define S5P6440_PA_VIC0         (0xE4000000)
-#define S5P_PA_VIC0             S5P6440_PA_VIC0
-
-#define S5P6440_PA_PDMA         0xE9000000
-
-#define S5P6440_PA_VIC1         (0xE4100000)
-#define S5P_PA_VIC1             S5P6440_PA_VIC1
-
-#define S5P6440_PA_TIMER        (0xEA000000)
-#define S5P_PA_TIMER            S5P6440_PA_TIMER
-
-#define S5P6440_PA_RTC          (0xEA100000)
-
-#define S5P6440_PA_WDT          (0xEA200000)
-#define S5P_PA_WDT              S5P6440_PA_WDT
-
-#define S5P6440_PA_UART         (0xEC000000)
-
-#define S5P_PA_UART0            (S5P6440_PA_UART + 0x0)
-#define S5P_PA_UART1            (S5P6440_PA_UART + 0x400)
-#define S5P_PA_UART2            (S5P6440_PA_UART + 0x800)
-#define S5P_PA_UART3            (S5P6440_PA_UART + 0xC00)
-
-#define S5P_SZ_UART             SZ_256
-
-#define S5P6440_PA_IIC0         (0xEC104000)
-#define S5P6440_PA_IIC1         (0xEC20F000)
-
-#define S5P6440_PA_SPI0         0xEC400000
-#define S5P6440_PA_SPI1         0xEC500000
-
-#define S5P6440_PA_HSOTG        (0xED100000)
-
-#define S5P6440_PA_HSMMC0       (0xED800000)
-#define S5P6440_PA_HSMMC1       (0xED900000)
-#define S5P6440_PA_HSMMC2       (0xEDA00000)
-
-#define S5P6440_PA_SDRAM        (0x20000000)
-#define S5P_PA_SDRAM            S5P6440_PA_SDRAM
-
-/* I2S */
-#define S5P6440_PA_I2S          0xF2000000
-
-/* PCM */
-#define S5P6440_PA_PCM          0xF2100000
-
-#define S5P6440_PA_ADC          (0xF3000000)
-
-/* compatibiltiy defines. */
-#define S3C_PA_UART             S5P6440_PA_UART
-#define S3C_PA_IIC              S5P6440_PA_IIC0
-#define S3C_PA_RTC              S5P6440_PA_RTC
-#define S3C_PA_IIC1             S5P6440_PA_IIC1
-#define S3C_PA_WDT              S5P6440_PA_WDT
-
-#define SAMSUNG_PA_ADC          S5P6440_PA_ADC
-
-#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/regs-clock.h b/arch/arm/mach-s5p6440/include/mach/regs-clock.h
deleted file mode 100644
index c783ecc9f193..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/regs-clock.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/regs-clock.h
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P6440 - Clock register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_CLOCK_H
-#define __ASM_ARCH_REGS_CLOCK_H __FILE__
-
-#include <mach/map.h>
-
-#define S5P_CLKREG(x)           (S3C_VA_SYS + (x))
-
-#define S5P_APLL_LOCK           S5P_CLKREG(0x00)
-#define S5P_MPLL_LOCK           S5P_CLKREG(0x04)
-#define S5P_EPLL_LOCK           S5P_CLKREG(0x08)
-#define S5P_APLL_CON            S5P_CLKREG(0x0C)
-#define S5P_MPLL_CON            S5P_CLKREG(0x10)
-#define S5P_EPLL_CON            S5P_CLKREG(0x14)
-#define S5P_EPLL_CON_K          S5P_CLKREG(0x18)
-#define S5P_CLK_SRC0            S5P_CLKREG(0x1C)
-#define S5P_CLK_DIV0            S5P_CLKREG(0x20)
-#define S5P_CLK_DIV1            S5P_CLKREG(0x24)
-#define S5P_CLK_DIV2            S5P_CLKREG(0x28)
-#define S5P_CLK_OUT             S5P_CLKREG(0x2C)
-#define S5P_CLK_GATE_HCLK0      S5P_CLKREG(0x30)
-#define S5P_CLK_GATE_PCLK       S5P_CLKREG(0x34)
-#define S5P_CLK_GATE_SCLK0      S5P_CLKREG(0x38)
-#define S5P_CLK_GATE_MEM0       S5P_CLKREG(0x3C)
-#define S5P_CLK_DIV3            S5P_CLKREG(0x40)
-#define S5P_CLK_GATE_HCLK1      S5P_CLKREG(0x44)
-#define S5P_CLK_GATE_SCLK1      S5P_CLKREG(0x48)
-#define S5P_AHB_CON0            S5P_CLKREG(0x100)
-#define S5P_CLK_SRC1            S5P_CLKREG(0x10C)
-#define S5P_SWRESET             S5P_CLKREG(0x114)
-#define S5P_SYS_ID              S5P_CLKREG(0x118)
-#define S5P_SYS_OTHERS          S5P_CLKREG(0x11C)
-#define S5P_MEM_CFG_STAT        S5P_CLKREG(0x12C)
-#define S5P_PWR_CFG             S5P_CLKREG(0x804)
-#define S5P_EINT_WAKEUP_MASK    S5P_CLKREG(0x808)
-#define S5P_NORMAL_CFG          S5P_CLKREG(0x810)
-#define S5P_STOP_CFG            S5P_CLKREG(0x814)
-#define S5P_SLEEP_CFG           S5P_CLKREG(0x818)
-#define S5P_OSC_FREQ            S5P_CLKREG(0x820)
-#define S5P_OSC_STABLE          S5P_CLKREG(0x824)
-#define S5P_PWR_STABLE          S5P_CLKREG(0x828)
-#define S5P_MTC_STABLE          S5P_CLKREG(0x830)
-#define S5P_OTHERS              S5P_CLKREG(0x900)
-#define S5P_RST_STAT            S5P_CLKREG(0x904)
-#define S5P_WAKEUP_STAT         S5P_CLKREG(0x908)
-#define S5P_SLPEN               S5P_CLKREG(0x930)
-#define S5P_INFORM0             S5P_CLKREG(0xA00)
-#define S5P_INFORM1             S5P_CLKREG(0xA04)
-#define S5P_INFORM2             S5P_CLKREG(0xA08)
-#define S5P_INFORM3             S5P_CLKREG(0xA0C)
-
-/* CLKDIV0 */
-#define S5P_CLKDIV0_PCLK_MASK           (0xf << 12)
-#define S5P_CLKDIV0_PCLK_SHIFT          (12)
-#define S5P_CLKDIV0_HCLK_MASK           (0xf << 8)
-#define S5P_CLKDIV0_HCLK_SHIFT          (8)
-#define S5P_CLKDIV0_MPLL_MASK           (0x1 << 4)
-#define S5P_CLKDIV0_ARM_MASK            (0xf << 0)
-#define S5P_CLKDIV0_ARM_SHIFT           (0)
-
-/* CLKDIV3 */
-#define S5P_CLKDIV3_PCLK_LOW_MASK       (0xf << 12)
-#define S5P_CLKDIV3_PCLK_LOW_SHIFT      (12)
-#define S5P_CLKDIV3_HCLK_LOW_MASK       (0xf << 8)
-#define S5P_CLKDIV3_HCLK_LOW_SHIFT      (8)
-
-/* HCLK0 GATE Registers */
-#define S5P_CLKCON_HCLK0_USB            (1<<20)
-#define S5P_CLKCON_HCLK0_HSMMC2         (1<<19)
-#define S5P_CLKCON_HCLK0_HSMMC1         (1<<18)
-#define S5P_CLKCON_HCLK0_HSMMC0         (1<<17)
-#define S5P_CLKCON_HCLK0_POST0          (1<<5)
-
-/* HCLK1 GATE Registers */
-#define S5P_CLKCON_HCLK1_DISPCON        (1<<1)
-
-/* PCLK GATE Registers */
-#define S5P_CLKCON_PCLK_IIS2            (1<<26)
-#define S5P_CLKCON_PCLK_SPI1            (1<<22)
-#define S5P_CLKCON_PCLK_SPI0            (1<<21)
-#define S5P_CLKCON_PCLK_GPIO            (1<<18)
-#define S5P_CLKCON_PCLK_IIC0            (1<<17)
-#define S5P_CLKCON_PCLK_TSADC           (1<<12)
-#define S5P_CLKCON_PCLK_PWM             (1<<7)
-#define S5P_CLKCON_PCLK_RTC             (1<<6)
-#define S5P_CLKCON_PCLK_WDT             (1<<5)
-#define S5P_CLKCON_PCLK_UART3           (1<<4)
-#define S5P_CLKCON_PCLK_UART2           (1<<3)
-#define S5P_CLKCON_PCLK_UART1           (1<<2)
-#define S5P_CLKCON_PCLK_UART0           (1<<1)
-
-/* SCLK0 GATE Registers */
-#define S5P_CLKCON_SCLK0_MMC2_48        (1<<29)
-#define S5P_CLKCON_SCLK0_MMC1_48        (1<<28)
-#define S5P_CLKCON_SCLK0_MMC0_48        (1<<27)
-#define S5P_CLKCON_SCLK0_MMC2           (1<<26)
-#define S5P_CLKCON_SCLK0_MMC1           (1<<25)
-#define S5P_CLKCON_SCLK0_MMC0           (1<<24)
-#define S5P_CLKCON_SCLK0_SPI1_48        (1<<23)
-#define S5P_CLKCON_SCLK0_SPI0_48        (1<<22)
-#define S5P_CLKCON_SCLK0_SPI1           (1<<21)
-#define S5P_CLKCON_SCLK0_SPI0           (1<<20)
-#define S5P_CLKCON_SCLK0_UART           (1<<5)
-
-/* SCLK1 GATE Registers */
-
-/* MEM0 GATE Registers */
-#define S5P_CLKCON_MEM0_HCLK_NFCON      (1<<2)
-
-/*OTHERS Resgister */
-#define S5P_OTHERS_USB_SIG_MASK         (1<<16)
-#define S5P_OTHERS_HCLK_LOW_SEL_MPLL    (1<<6)
-
-/* Compatibility defines */
-#define ARM_CLK_DIV                     S5P_CLK_DIV0
-#define ARM_DIV_RATIO_SHIFT             0
-#define ARM_DIV_MASK                    (0xf << ARM_DIV_RATIO_SHIFT)
-
-#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/spi-clocks.h b/arch/arm/mach-s5p6440/include/mach/spi-clocks.h
deleted file mode 100644
index 5fbca50d1cfb..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/spi-clocks.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/spi-clocks.h
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __S5P6440_PLAT_SPI_CLKS_H
-#define __S5P6440_PLAT_SPI_CLKS_H __FILE__
-
-#define S5P6440_SPI_SRCCLK_PCLK         0
-#define S5P6440_SPI_SRCCLK_SCLK         1
-
-#endif /* __S5P6440_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/uncompress.h b/arch/arm/mach-s5p6440/include/mach/uncompress.h
deleted file mode 100644
index 7c1f600d65c0..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/uncompress.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/uncompress.h
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P6440 - uncompress code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-
-#include <mach/map.h>
-#include <plat/uncompress.h>
-
-static void arch_detect_cpu(void)
-{
-        /* we do not need to do any cpu detection here at the moment. */
-}
-
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5p6440/init.c b/arch/arm/mach-s5p6440/init.c
deleted file mode 100644
index a1f3727e4021..000000000000
--- a/arch/arm/mach-s5p6440/init.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* linux/arch/arm/mach-s5p6440/init.c
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P6440 - Init support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/serial_core.h>
-
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/s5p6440.h>
-#include <plat/regs-serial.h>
-
-static struct s3c24xx_uart_clksrc s5p6440_serial_clocks[] = {
-        [0] = {
-                .name           = "pclk_low",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        },
-        [1] = {
-                .name           = "uclk1",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        },
-};
-
-/* uart registration process */
-void __init s5p6440_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
-        struct s3c2410_uartcfg *tcfg = cfg;
-        u32 ucnt;
-
-        for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
-                if (!tcfg->clocks) {
-                        tcfg->clocks = s5p6440_serial_clocks;
-                        tcfg->clocks_size = ARRAY_SIZE(s5p6440_serial_clocks);
-                }
-        }
-
-        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
-}
diff --git a/arch/arm/mach-s5p6442/cpu.c b/arch/arm/mach-s5p6442/cpu.c
index a48fb553fd01..842af86bda6d 100644
--- a/arch/arm/mach-s5p6442/cpu.c
+++ b/arch/arm/mach-s5p6442/cpu.c
@@ -1,7 +1,7 @@
 /* linux/arch/arm/mach-s5p6442/cpu.c
  *
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ *              http://www.samsung.com
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -19,6 +19,7 @@
 #include <linux/sysdev.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/sched.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -47,10 +48,30 @@ static struct map_desc s5p6442_iodesc[] __initdata = {
                 .length         = SZ_16K,
                 .type           = MT_DEVICE,
         }, {
+                .virtual        = (unsigned long)S5P_VA_GPIO,
+                .pfn            = __phys_to_pfn(S5P6442_PA_GPIO),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC0,
+                .pfn            = __phys_to_pfn(S5P6442_PA_VIC0),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC1,
+                .pfn            = __phys_to_pfn(S5P6442_PA_VIC1),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = (unsigned long)VA_VIC2,
                 .pfn            = __phys_to_pfn(S5P6442_PA_VIC2),
                 .length         = SZ_16K,
                 .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_UART,
+                .pfn            = __phys_to_pfn(S3C_PA_UART),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
         }
 };
 
@@ -62,10 +83,11 @@ static void s5p6442_idle(void)
         local_irq_enable();
 }
 
-/* s5p6442_map_io
+/*
+ * s5p6442_map_io
  *
  * register the standard cpu IO areas
-*/
+ */
 
 void __init s5p6442_map_io(void)
 {
diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h
index 281d256faafb..31fb2e68d527 100644
--- a/arch/arm/mach-s5p6442/include/mach/map.h
+++ b/arch/arm/mach-s5p6442/include/mach/map.h
@@ -23,16 +23,10 @@
 #define S5P_PA_SYSCON           S5P6442_PA_SYSCON
 
 #define S5P6442_PA_GPIO         (0xE0200000)
-#define S5P_PA_GPIO             S5P6442_PA_GPIO
 
 #define S5P6442_PA_VIC0         (0xE4000000)
-#define S5P_PA_VIC0             S5P6442_PA_VIC0
-
 #define S5P6442_PA_VIC1         (0xE4100000)
-#define S5P_PA_VIC1             S5P6442_PA_VIC1
-
 #define S5P6442_PA_VIC2         (0xE4200000)
-#define S5P_PA_VIC2             S5P6442_PA_VIC2
 
 #define S5P6442_PA_MDMA         0xE8000000
 #define S5P6442_PA_PDMA         0xE9000000
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
new file mode 100644
index 000000000000..fbcae9352022
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -0,0 +1,57 @@
+# arch/arm/mach-s5p64x0/Kconfig
+#
+# Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+#               http://www.samsung.com/
+#
+# Licensed under GPLv2
+
+if ARCH_S5P64X0
+
+config CPU_S5P6440
+        bool
+        select PLAT_S5P
+        select S3C_PL330_DMA
+        help
+          Enable S5P6440 CPU support
+
+config CPU_S5P6450
+        bool
+        select PLAT_S5P
+        select S3C_PL330_DMA
+        help
+          Enable S5P6450 CPU support
+
+config S5P64X0_SETUP_I2C1
+        bool
+        help
+          Common setup code for i2c bus 1.
+
+# machine support
+
+config MACH_SMDK6440
+        bool "SMDK6440"
+        select CPU_S5P6440
+        select S3C_DEV_I2C1
+        select S3C_DEV_RTC
+        select S3C_DEV_WDT
+        select S3C64XX_DEV_SPI
+        select SAMSUNG_DEV_ADC
+        select SAMSUNG_DEV_TS
+        select S5P64X0_SETUP_I2C1
+        help
+          Machine support for the Samsung SMDK6440
+
+config MACH_SMDK6450
+        bool "SMDK6450"
+        select CPU_S5P6450
+        select S3C_DEV_I2C1
+        select S3C_DEV_RTC
+        select S3C_DEV_WDT
+        select S3C64XX_DEV_SPI
+        select SAMSUNG_DEV_ADC
+        select SAMSUNG_DEV_TS
+        select S5P64X0_SETUP_I2C1
+        help
+          Machine support for the Samsung SMDK6450
+
+endif
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
new file mode 100644
index 000000000000..2655829e6bf8
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -0,0 +1,30 @@
+# arch/arm/mach-s5p64x0/Makefile
+#
+# Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+#               http://www.samsung.com
+#
+# Licensed under GPLv2
+
+obj-y                           :=
+obj-m                           :=
+obj-n                           :=
+obj-                            :=
+
+# Core support for S5P64X0 system
+
+obj-$(CONFIG_ARCH_S5P64X0)      += cpu.o init.o clock.o dma.o
+obj-$(CONFIG_ARCH_S5P64X0)      += setup-i2c0.o
+obj-$(CONFIG_CPU_S5P6440)       += clock-s5p6440.o gpio.o
+obj-$(CONFIG_CPU_S5P6450)       += clock-s5p6450.o
+
+# machine support
+
+obj-$(CONFIG_MACH_SMDK6440)     += mach-smdk6440.o
+obj-$(CONFIG_MACH_SMDK6450)     += mach-smdk6450.o
+
+# device support
+
+obj-y                           += dev-audio.o
+obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
+
+obj-$(CONFIG_S5P64X0_SETUP_I2C1)        += setup-i2c1.o
diff --git a/arch/arm/mach-s5p6440/Makefile.boot b/arch/arm/mach-s5p64x0/Makefile.boot
index ff90aa13bd67..ff90aa13bd67 100644
--- a/arch/arm/mach-s5p6440/Makefile.boot
+++ b/arch/arm/mach-s5p64x0/Makefile.boot
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
new file mode 100644
index 000000000000..f93dcd8b4d6a
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -0,0 +1,626 @@
+/* linux/arch/arm/mach-s5p64x0/clock-s5p6440.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P6440 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/s5p64x0-clock.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/s5p6440.h>
+
+static u32 epll_div[][5] = {
+        { 36000000,     0,      48, 1, 4 },
+        { 48000000,     0,      32, 1, 3 },
+        { 60000000,     0,      40, 1, 3 },
+        { 72000000,     0,      48, 1, 3 },
+        { 84000000,     0,      28, 1, 2 },
+        { 96000000,     0,      32, 1, 2 },
+        { 32768000,     45264,  43, 1, 4 },
+        { 45158000,     6903,   30, 1, 3 },
+        { 49152000,     50332,  32, 1, 3 },
+        { 67738000,     10398,  45, 1, 3 },
+        { 73728000,     9961,   49, 1, 3 }
+};
+
+static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int epll_con, epll_con_k;
+        unsigned int i;
+
+        if (clk->rate == rate)  /* Return if nothing changed */
+                return 0;
+
+        epll_con = __raw_readl(S5P64X0_EPLL_CON);
+        epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
+
+        epll_con_k &= ~(PLL90XX_KDIV_MASK);
+        epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
+
+        for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
+                 if (epll_div[i][0] == rate) {
+                        epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
+                        epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
+                                    (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
+                                    (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
+                        break;
+                }
+        }
+
+        if (i == ARRAY_SIZE(epll_div)) {
+                printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
+                return -EINVAL;
+        }
+
+        __raw_writel(epll_con, S5P64X0_EPLL_CON);
+        __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
+
+        clk->rate = rate;
+
+        return 0;
+}
+
+static struct clk_ops s5p6440_epll_ops = {
+        .get_rate = s5p64x0_epll_get_rate,
+        .set_rate = s5p6440_epll_set_rate,
+};
+
+static struct clksrc_clk clk_hclk = {
+        .clk    = {
+                .name           = "clk_hclk",
+                .id             = -1,
+                .parent         = &clk_armclk.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_pclk = {
+        .clk    = {
+                .name           = "clk_pclk",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
+};
+static struct clksrc_clk clk_hclk_low = {
+        .clk    = {
+                .name           = "clk_hclk_low",
+                .id             = -1,
+        },
+        .sources        = &clkset_hclk_low,
+        .reg_src        = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_pclk_low = {
+        .clk    = {
+                .name           = "clk_pclk_low",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
+};
+
+/*
+ * The following clocks will be disabled during clock initialization. It is
+ * recommended to keep the following clocks disabled until the driver requests
+ * for enabling the clock.
+ */
+static struct clk init_clocks_disable[] = {
+        {
+                .name           = "nand",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_mem_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "post",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 5)
+        }, {
+                .name           = "2d",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "hsmmc",
+                .id             = 0,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 17),
+        }, {
+                .name           = "hsmmc",
+                .id             = 1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 18),
+        }, {
+                .name           = "hsmmc",
+                .id             = 2,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 19),
+        }, {
+                .name           = "otg",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 20)
+        }, {
+                .name           = "irom",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 25),
+        }, {
+                .name           = "lcd",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk1_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "hclk_fimgvg",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_hclk1_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "tsi",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk1_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "watchdog",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "rtc",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 6),
+        }, {
+                .name           = "timers",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "pcm",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "adc",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "i2c",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 17),
+        }, {
+                .name           = "spi",
+                .id             = 0,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 21),
+        }, {
+                .name           = "spi",
+                .id             = 1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 22),
+        }, {
+                .name           = "gps",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 25),
+        }, {
+                .name           = "i2s_v40",
+                .id             = 0,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 26),
+        }, {
+                .name           = "dsim",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 28),
+        }, {
+                .name           = "etm",
+                .id             = -1,
+                .parent         = &clk_pclk.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 29),
+        }, {
+                .name           = "dmc0",
+                .id             = -1,
+                .parent         = &clk_pclk.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 30),
+        }, {
+                .name           = "pclk_fimgvg",
+                .id             = -1,
+                .parent         = &clk_pclk.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 31),
+        }, {
+                .name           = "sclk_spi_48",
+                .id             = 0,
+                .parent         = &clk_48m,
+                .enable         = s5p64x0_sclk_ctrl,
+                .ctrlbit        = (1 << 22),
+        }, {
+                .name           = "sclk_spi_48",
+                .id             = 1,
+                .parent         = &clk_48m,
+                .enable         = s5p64x0_sclk_ctrl,
+                .ctrlbit        = (1 << 23),
+        }, {
+                .name           = "mmc_48m",
+                .id             = 0,
+                .parent         = &clk_48m,
+                .enable         = s5p64x0_sclk_ctrl,
+                .ctrlbit        = (1 << 27),
+        }, {
+                .name           = "mmc_48m",
+                .id             = 1,
+                .parent         = &clk_48m,
+                .enable         = s5p64x0_sclk_ctrl,
+                .ctrlbit        = (1 << 28),
+        }, {
+                .name           = "mmc_48m",
+                .id             = 2,
+                .parent         = &clk_48m,
+                .enable         = s5p64x0_sclk_ctrl,
+                .ctrlbit        = (1 << 29),
+        },
+};
+
+/*
+ * The following clocks will be enabled during clock initialization.
+ */
+static struct clk init_clocks[] = {
+        {
+                .name           = "intc",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "mem",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 21),
+        }, {
+                .name           = "dma",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "uart",
+                .id             = 0,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "uart",
+                .id             = 1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "uart",
+                .id             = 2,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "uart",
+                .id             = 3,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "gpio",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 18),
+        },
+};
+
+static struct clk clk_iis_cd_v40 = {
+        .name           = "iis_cdclk_v40",
+        .id             = -1,
+};
+
+static struct clk clk_pcm_cd = {
+        .name           = "pcm_cdclk",
+        .id             = -1,
+};
+
+static struct clk *clkset_group1_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll.clk,
+        &clk_fin_epll,
+};
+
+static struct clksrc_sources clkset_group1 = {
+        .sources        = clkset_group1_list,
+        .nr_sources     = ARRAY_SIZE(clkset_group1_list),
+};
+
+static struct clk *clkset_uart_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll.clk,
+};
+
+static struct clksrc_sources clkset_uart = {
+        .sources        = clkset_uart_list,
+        .nr_sources     = ARRAY_SIZE(clkset_uart_list),
+};
+
+static struct clk *clkset_audio_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll.clk,
+        &clk_fin_epll,
+        &clk_iis_cd_v40,
+        &clk_pcm_cd,
+};
+
+static struct clksrc_sources clkset_audio = {
+        .sources        = clkset_audio_list,
+        .nr_sources     = ARRAY_SIZE(clkset_audio_list),
+};
+
+static struct clksrc_clk clksrcs[] = {
+        {
+                .clk    = {
+                        .name           = "mmc_bus",
+                        .id             = 0,
+                        .ctrlbit        = (1 << 24),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "mmc_bus",
+                        .id             = 1,
+                        .ctrlbit        = (1 << 25),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "mmc_bus",
+                        .id             = 2,
+                        .ctrlbit        = (1 << 26),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "uclk1",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 5),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_uart,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_spi",
+                        .id             = 0,
+                        .ctrlbit        = (1 << 20),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_spi",
+                        .id             = 1,
+                        .ctrlbit        = (1 << 21),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_post",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 10),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_dispcon",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 1),
+                        .enable         = s5p64x0_sclk1_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimgvg",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 2),
+                        .enable         = s5p64x0_sclk1_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_audio2",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 11),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_audio,
+                .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
+        },
+};
+
+/* Clock initialization code */
+static struct clksrc_clk *sysclks[] = {
+        &clk_mout_apll,
+        &clk_mout_epll,
+        &clk_mout_mpll,
+        &clk_dout_mpll,
+        &clk_armclk,
+        &clk_hclk,
+        &clk_pclk,
+        &clk_hclk_low,
+        &clk_pclk_low,
+};
+
+void __init_or_cpufreq s5p6440_setup_clocks(void)
+{
+        struct clk *xtal_clk;
+
+        unsigned long xtal;
+        unsigned long fclk;
+        unsigned long hclk;
+        unsigned long hclk_low;
+        unsigned long pclk;
+        unsigned long pclk_low;
+
+        unsigned long apll;
+        unsigned long mpll;
+        unsigned long epll;
+        unsigned int ptr;
+
+        /* Set S5P6440 functions for clk_fout_epll */
+
+        clk_fout_epll.enable = s5p64x0_epll_enable;
+        clk_fout_epll.ops = &s5p6440_epll_ops;
+
+        clk_48m.enable = s5p64x0_clk48m_ctrl;
+
+        xtal_clk = clk_get(NULL, "ext_xtal");
+        BUG_ON(IS_ERR(xtal_clk));
+
+        xtal = clk_get_rate(xtal_clk);
+        clk_put(xtal_clk);
+
+        apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
+        mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
+        epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
+                                __raw_readl(S5P64X0_EPLL_CON_K));
+
+        clk_fout_apll.rate = apll;
+        clk_fout_mpll.rate = mpll;
+        clk_fout_epll.rate = epll;
+
+        printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
+                        " E=%ld.%ldMHz\n",
+                        print_mhz(apll), print_mhz(mpll), print_mhz(epll));
+
+        fclk = clk_get_rate(&clk_armclk.clk);
+        hclk = clk_get_rate(&clk_hclk.clk);
+        pclk = clk_get_rate(&clk_pclk.clk);
+        hclk_low = clk_get_rate(&clk_hclk_low.clk);
+        pclk_low = clk_get_rate(&clk_pclk_low.clk);
+
+        printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
+                        " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
+                        print_mhz(hclk), print_mhz(hclk_low),
+                        print_mhz(pclk), print_mhz(pclk_low));
+
+        clk_f.rate = fclk;
+        clk_h.rate = hclk;
+        clk_p.rate = pclk;
+
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
+                s3c_set_clksrc(&clksrcs[ptr], true);
+}
+
+static struct clk *clks[] __initdata = {
+        &clk_ext,
+        &clk_iis_cd_v40,
+        &clk_pcm_cd,
+};
+
+void __init s5p6440_register_clocks(void)
+{
+        struct clk *clkp;
+        int ret;
+        int ptr;
+
+        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
+
+        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+                s3c_register_clksrc(sysclks[ptr], 1);
+
+        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+
+        clkp = init_clocks_disable;
+        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
+
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+                (clkp->enable)(clkp, 0);
+        }
+
+        s3c_pwmclk_init();
+}
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
new file mode 100644
index 000000000000..f9afb05b217c
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -0,0 +1,655 @@
+/* linux/arch/arm/mach-s5p64x0/clock-s5p6450.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P6450 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/s5p64x0-clock.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/s5p6450.h>
+
+static struct clksrc_clk clk_mout_dpll = {
+        .clk    = {
+                .name           = "mout_dpll",
+                .id             = -1,
+        },
+        .sources        = &clk_src_dpll,
+        .reg_src        = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
+};
+
+static u32 epll_div[][5] = {
+        { 133000000,    27307,  55, 2, 2 },
+        { 100000000,    43691,  41, 2, 2 },
+        { 480000000,    0,      80, 2, 0 },
+};
+
+static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int epll_con, epll_con_k;
+        unsigned int i;
+
+        if (clk->rate == rate)  /* Return if nothing changed */
+                return 0;
+
+        epll_con = __raw_readl(S5P64X0_EPLL_CON);
+        epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
+
+        epll_con_k &= ~(PLL90XX_KDIV_MASK);
+        epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
+
+        for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
+                 if (epll_div[i][0] == rate) {
+                        epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
+                        epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
+                                    (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
+                                    (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
+                        break;
+                }
+        }
+
+        if (i == ARRAY_SIZE(epll_div)) {
+                printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
+                return -EINVAL;
+        }
+
+        __raw_writel(epll_con, S5P64X0_EPLL_CON);
+        __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
+
+        clk->rate = rate;
+
+        return 0;
+}
+
+static struct clk_ops s5p6450_epll_ops = {
+        .get_rate = s5p64x0_epll_get_rate,
+        .set_rate = s5p6450_epll_set_rate,
+};
+
+static struct clksrc_clk clk_dout_epll = {
+        .clk    = {
+                .name           = "dout_epll",
+                .id             = -1,
+                .parent         = &clk_mout_epll.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
+};
+
+static struct clksrc_clk clk_mout_hclk_sel = {
+        .clk    = {
+                .name           = "mout_hclk_sel",
+                .id             = -1,
+        },
+        .sources        = &clkset_hclk_low,
+        .reg_src        = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
+};
+
+static struct clk *clkset_hclk_list[] = {
+        &clk_mout_hclk_sel.clk,
+        &clk_armclk.clk,
+};
+
+static struct clksrc_sources clkset_hclk = {
+        .sources        = clkset_hclk_list,
+        .nr_sources     = ARRAY_SIZE(clkset_hclk_list),
+};
+
+static struct clksrc_clk clk_hclk = {
+        .clk    = {
+                .name           = "clk_hclk",
+                .id             = -1,
+        },
+        .sources        = &clkset_hclk,
+        .reg_src        = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_pclk = {
+        .clk    = {
+                .name           = "clk_pclk",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+        },
+        .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
+};
+static struct clksrc_clk clk_dout_pwm_ratio0 = {
+        .clk    = {
+                .name           = "clk_dout_pwm_ratio0",
+                .id             = -1,
+                .parent         = &clk_mout_hclk_sel.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk clk_pclk_to_wdt_pwm = {
+        .clk    = {
+                .name           = "clk_pclk_to_wdt_pwm",
+                .id             = -1,
+                .parent         = &clk_dout_pwm_ratio0.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
+};
+
+static struct clksrc_clk clk_hclk_low = {
+        .clk    = {
+                .name           = "clk_hclk_low",
+                .id             = -1,
+        },
+        .sources        = &clkset_hclk_low,
+        .reg_src        = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_pclk_low = {
+        .clk    = {
+                .name           = "clk_pclk_low",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
+};
+
+/*
+ * The following clocks will be disabled during clock initialization. It is
+ * recommended to keep the following clocks disabled until the driver requests
+ * for enabling the clock.
+ */
+static struct clk init_clocks_disable[] = {
+        {
+                .name           = "usbhost",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "hsmmc",
+                .id             = 0,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 17),
+        }, {
+                .name           = "hsmmc",
+                .id             = 1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 18),
+        }, {
+                .name           = "hsmmc",
+                .id             = 2,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 19),
+        }, {
+                .name           = "usbotg",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 20),
+        }, {
+                .name           = "lcd",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5p64x0_hclk1_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "watchdog",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "adc",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "i2c",
+                .id             = 0,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 17),
+        }, {
+                .name           = "spi",
+                .id             = 0,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 21),
+        }, {
+                .name           = "spi",
+                .id             = 1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 22),
+        }, {
+                .name           = "iis",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 26),
+        }, {
+                .name           = "i2c",
+                .id             = 1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 27),
+        }, {
+                .name           = "dmc0",
+                .id             = -1,
+                .parent         = &clk_pclk.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 30),
+        }
+};
+
+/*
+ * The following clocks will be enabled during clock initialization.
+ */
+static struct clk init_clocks[] = {
+        {
+                .name           = "intc",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "mem",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 21),
+        }, {
+                .name           = "dma",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "uart",
+                .id             = 0,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "uart",
+                .id             = 1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "uart",
+                .id             = 2,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "uart",
+                .id             = 3,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "timers",
+                .id             = -1,
+                .parent         = &clk_pclk_to_wdt_pwm.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "gpio",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 18),
+        },
+};
+
+static struct clk *clkset_uart_list[] = {
+        &clk_dout_epll.clk,
+        &clk_dout_mpll.clk,
+};
+
+static struct clksrc_sources clkset_uart = {
+        .sources        = clkset_uart_list,
+        .nr_sources     = ARRAY_SIZE(clkset_uart_list),
+};
+
+static struct clk *clkset_mali_list[] = {
+        &clk_mout_epll.clk,
+        &clk_mout_apll.clk,
+        &clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources clkset_mali = {
+        .sources        = clkset_mali_list,
+        .nr_sources     = ARRAY_SIZE(clkset_mali_list),
+};
+
+static struct clk *clkset_group2_list[] = {
+        &clk_dout_epll.clk,
+        &clk_dout_mpll.clk,
+        &clk_ext_xtal_mux,
+};
+
+static struct clksrc_sources clkset_group2 = {
+        .sources        = clkset_group2_list,
+        .nr_sources     = ARRAY_SIZE(clkset_group2_list),
+};
+
+static struct clk *clkset_dispcon_list[] = {
+        &clk_dout_epll.clk,
+        &clk_dout_mpll.clk,
+        &clk_ext_xtal_mux,
+        &clk_mout_dpll.clk,
+};
+
+static struct clksrc_sources clkset_dispcon = {
+        .sources        = clkset_dispcon_list,
+        .nr_sources     = ARRAY_SIZE(clkset_dispcon_list),
+};
+
+static struct clk *clkset_hsmmc44_list[] = {
+        &clk_dout_epll.clk,
+        &clk_dout_mpll.clk,
+        &clk_ext_xtal_mux,
+        &s5p_clk_27m,
+        &clk_48m,
+};
+
+static struct clksrc_sources clkset_hsmmc44 = {
+        .sources        = clkset_hsmmc44_list,
+        .nr_sources     = ARRAY_SIZE(clkset_hsmmc44_list),
+};
+
+static struct clk *clkset_sclk_audio0_list[] = {
+        [0] = &clk_dout_epll.clk,
+        [1] = &clk_dout_mpll.clk,
+        [2] = &clk_ext_xtal_mux,
+        [3] = NULL,
+        [4] = NULL,
+};
+
+static struct clksrc_sources clkset_sclk_audio0 = {
+        .sources        = clkset_sclk_audio0_list,
+        .nr_sources     = ARRAY_SIZE(clkset_sclk_audio0_list),
+};
+
+static struct clksrc_clk clk_sclk_audio0 = {
+        .clk            = {
+                .name           = "audio-bus",
+                .id             = -1,
+                .enable         = s5p64x0_sclk_ctrl,
+                .ctrlbit        = (1 << 8),
+                .parent         = &clk_dout_epll.clk,
+        },
+        .sources        = &clkset_sclk_audio0,
+        .reg_src        = { .reg = S5P64X0_CLK_SRC1, .shift = 10, .size = 3 },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV2, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clksrcs[] = {
+        {
+                .clk    = {
+                        .name           = "sclk_mmc",
+                        .id             = 0,
+                        .ctrlbit        = (1 << 24),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_mmc",
+                        .id             = 1,
+                        .ctrlbit        = (1 << 25),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_mmc",
+                        .id             = 2,
+                        .ctrlbit        = (1 << 26),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "uclk1",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 5),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_uart,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_spi",
+                        .id             = 0,
+                        .ctrlbit        = (1 << 20),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_spi",
+                        .id             = 1,
+                        .ctrlbit        = (1 << 21),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimc",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 10),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "aclk_mali",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 2),
+                        .enable         = s5p64x0_sclk1_ctrl,
+                },
+                .sources = &clkset_mali,
+                .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_2d",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 12),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_mali,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 30, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 20, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_usi",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 7),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 10, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 16, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_camif",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 6),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 28, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 20, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_dispcon",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 1),
+                        .enable         = s5p64x0_sclk1_ctrl,
+                },
+                .sources = &clkset_dispcon,
+                .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_hsmmc44",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 30),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_hsmmc44,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 6, .size = 3 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 28, .size = 4 },
+        },
+};
+
+/* Clock initialization code */
+static struct clksrc_clk *sysclks[] = {
+        &clk_mout_apll,
+        &clk_mout_epll,
+        &clk_dout_epll,
+        &clk_mout_mpll,
+        &clk_dout_mpll,
+        &clk_armclk,
+        &clk_mout_hclk_sel,
+        &clk_dout_pwm_ratio0,
+        &clk_pclk_to_wdt_pwm,
+        &clk_hclk,
+        &clk_pclk,
+        &clk_hclk_low,
+        &clk_pclk_low,
+        &clk_sclk_audio0,
+};
+
+void __init_or_cpufreq s5p6450_setup_clocks(void)
+{
+        struct clk *xtal_clk;
+
+        unsigned long xtal;
+        unsigned long fclk;
+        unsigned long hclk;
+        unsigned long hclk_low;
+        unsigned long pclk;
+        unsigned long pclk_low;
+
+        unsigned long apll;
+        unsigned long mpll;
+        unsigned long epll;
+        unsigned long dpll;
+        unsigned int ptr;
+
+        /* Set S5P6450 functions for clk_fout_epll */
+
+        clk_fout_epll.enable = s5p64x0_epll_enable;
+        clk_fout_epll.ops = &s5p6450_epll_ops;
+
+        clk_48m.enable = s5p64x0_clk48m_ctrl;
+
+        xtal_clk = clk_get(NULL, "ext_xtal");
+        BUG_ON(IS_ERR(xtal_clk));
+
+        xtal = clk_get_rate(xtal_clk);
+        clk_put(xtal_clk);
+
+        apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
+        mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
+        epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
+                                __raw_readl(S5P64X0_EPLL_CON_K));
+        dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P6450_DPLL_CON),
+                                __raw_readl(S5P6450_DPLL_CON_K), pll_4650c);
+
+        clk_fout_apll.rate = apll;
+        clk_fout_mpll.rate = mpll;
+        clk_fout_epll.rate = epll;
+        clk_fout_dpll.rate = dpll;
+
+        printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
+                        " E=%ld.%ldMHz, D=%ld.%ldMHz\n",
+                        print_mhz(apll), print_mhz(mpll), print_mhz(epll),
+                        print_mhz(dpll));
+
+        fclk = clk_get_rate(&clk_armclk.clk);
+        hclk = clk_get_rate(&clk_hclk.clk);
+        pclk = clk_get_rate(&clk_pclk.clk);
+        hclk_low = clk_get_rate(&clk_hclk_low.clk);
+        pclk_low = clk_get_rate(&clk_pclk_low.clk);
+
+        printk(KERN_INFO "S5P6450: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
+                        " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
+                        print_mhz(hclk), print_mhz(hclk_low),
+                        print_mhz(pclk), print_mhz(pclk_low));
+
+        clk_f.rate = fclk;
+        clk_h.rate = hclk;
+        clk_p.rate = pclk;
+
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
+                s3c_set_clksrc(&clksrcs[ptr], true);
+}
+
+void __init s5p6450_register_clocks(void)
+{
+        struct clk *clkp;
+        int ret;
+        int ptr;
+
+        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+                s3c_register_clksrc(sysclks[ptr], 1);
+
+        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+
+        clkp = init_clocks_disable;
+        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
+
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+                (clkp->enable)(clkp, 0);
+        }
+
+        s3c_pwmclk_init();
+}
diff --git a/arch/arm/mach-s5p64x0/clock.c b/arch/arm/mach-s5p64x0/clock.c
new file mode 100644
index 000000000000..523ba8039ac2
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/clock.c
@@ -0,0 +1,253 @@
+/* linux/arch/arm/mach-s5p64x0/clock.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/s5p6440.h>
+#include <plat/s5p6450.h>
+
+struct clksrc_clk clk_mout_apll = {
+        .clk    = {
+                .name           = "mout_apll",
+                .id             = -1,
+        },
+        .sources        = &clk_src_apll,
+        .reg_src        = { .reg = S5P64X0_CLK_SRC0, .shift = 0, .size = 1 },
+};
+
+struct clksrc_clk clk_mout_mpll = {
+        .clk    = {
+                .name           = "mout_mpll",
+                .id             = -1,
+        },
+        .sources        = &clk_src_mpll,
+        .reg_src        = { .reg = S5P64X0_CLK_SRC0, .shift = 1, .size = 1 },
+};
+
+struct clksrc_clk clk_mout_epll = {
+        .clk    = {
+                .name           = "mout_epll",
+                .id             = -1,
+        },
+        .sources        = &clk_src_epll,
+        .reg_src        = { .reg = S5P64X0_CLK_SRC0, .shift = 2, .size = 1 },
+};
+
+enum perf_level {
+        L0 = 532*1000,
+        L1 = 266*1000,
+        L2 = 133*1000,
+};
+
+static const u32 clock_table[][3] = {
+        /*{ARM_CLK, DIVarm, DIVhclk}*/
+        {L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
+        {L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
+        {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
+};
+
+int s5p64x0_epll_enable(struct clk *clk, int enable)
+{
+        unsigned int ctrlbit = clk->ctrlbit;
+        unsigned int epll_con = __raw_readl(S5P64X0_EPLL_CON) & ~ctrlbit;
+
+        if (enable)
+                __raw_writel(epll_con | ctrlbit, S5P64X0_EPLL_CON);
+        else
+                __raw_writel(epll_con, S5P64X0_EPLL_CON);
+
+        return 0;
+}
+
+unsigned long s5p64x0_epll_get_rate(struct clk *clk)
+{
+        return clk->rate;
+}
+
+unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
+{
+        unsigned long rate = clk_get_rate(clk->parent);
+        u32 clkdiv;
+
+        /* divisor mask starts at bit0, so no need to shift */
+        clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK;
+
+        return rate / (clkdiv + 1);
+}
+
+unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate)
+{
+        u32 iter;
+
+        for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
+                if (rate > clock_table[iter][0])
+                        return clock_table[iter-1][0];
+        }
+
+        return clock_table[ARRAY_SIZE(clock_table) - 1][0];
+}
+
+int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 round_tmp;
+        u32 iter;
+        u32 clk_div0_tmp;
+        u32 cur_rate = clk->ops->get_rate(clk);
+        unsigned long flags;
+
+        round_tmp = clk->ops->round_rate(clk, rate);
+        if (round_tmp == cur_rate)
+                return 0;
+
+
+        for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
+                if (round_tmp == clock_table[iter][0])
+                        break;
+        }
+
+        if (iter >= ARRAY_SIZE(clock_table))
+                iter = ARRAY_SIZE(clock_table) - 1;
+
+        local_irq_save(flags);
+        if (cur_rate > round_tmp) {
+                /* Frequency Down */
+                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
+                clk_div0_tmp |= clock_table[iter][1];
+                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
+
+                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
+                                ~(S5P64X0_CLKDIV0_HCLK_MASK);
+                clk_div0_tmp |= clock_table[iter][2];
+                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
+
+
+        } else {
+                /* Frequency Up */
+                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
+                                ~(S5P64X0_CLKDIV0_HCLK_MASK);
+                clk_div0_tmp |= clock_table[iter][2];
+                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
+
+                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
+                clk_div0_tmp |= clock_table[iter][1];
+                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
+        }
+        local_irq_restore(flags);
+
+        clk->rate = clock_table[iter][0];
+
+        return 0;
+}
+
+struct clk_ops s5p64x0_clkarm_ops = {
+        .get_rate       = s5p64x0_armclk_get_rate,
+        .set_rate       = s5p64x0_armclk_set_rate,
+        .round_rate     = s5p64x0_armclk_round_rate,
+};
+
+struct clksrc_clk clk_armclk = {
+        .clk    = {
+                .name           = "armclk",
+                .id             = 1,
+                .parent         = &clk_mout_apll.clk,
+                .ops            = &s5p64x0_clkarm_ops,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 0, .size = 4 },
+};
+
+struct clksrc_clk clk_dout_mpll = {
+        .clk    = {
+                .name           = "dout_mpll",
+                .id             = -1,
+                .parent         = &clk_mout_mpll.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 },
+};
+
+struct clk *clkset_hclk_low_list[] = {
+        &clk_mout_apll.clk,
+        &clk_mout_mpll.clk,
+};
+
+struct clksrc_sources clkset_hclk_low = {
+        .sources        = clkset_hclk_low_list,
+        .nr_sources     = ARRAY_SIZE(clkset_hclk_low_list),
+};
+
+int s5p64x0_pclk_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P64X0_CLK_GATE_PCLK, clk, enable);
+}
+
+int s5p64x0_hclk0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK0, clk, enable);
+}
+
+int s5p64x0_hclk1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK1, clk, enable);
+}
+
+int s5p64x0_sclk_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK0, clk, enable);
+}
+
+int s5p64x0_sclk1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK1, clk, enable);
+}
+
+int s5p64x0_mem_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P64X0_CLK_GATE_MEM0, clk, enable);
+}
+
+int s5p64x0_clk48m_ctrl(struct clk *clk, int enable)
+{
+        unsigned long flags;
+        u32 val;
+
+        /* can't rely on clock lock, this register has other usages */
+        local_irq_save(flags);
+
+        val = __raw_readl(S5P64X0_OTHERS);
+        if (enable)
+                val |= S5P64X0_OTHERS_USB_SIG_MASK;
+        else
+                val &= ~S5P64X0_OTHERS_USB_SIG_MASK;
+
+        __raw_writel(val, S5P64X0_OTHERS);
+
+        local_irq_restore(flags);
+
+        return 0;
+}
diff --git a/arch/arm/mach-s5p64x0/cpu.c b/arch/arm/mach-s5p64x0/cpu.c
new file mode 100644
index 000000000000..b8d02eb4cf30
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/cpu.c
@@ -0,0 +1,209 @@
+/* linux/arch/arm/mach-s5p64x0/cpu.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/proc-fns.h>
+#include <asm/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+
+#include <plat/regs-serial.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/clock.h>
+#include <plat/s5p6440.h>
+#include <plat/s5p6450.h>
+#include <plat/adc-core.h>
+
+/* Initial IO mappings */
+
+static struct map_desc s5p64x0_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5P_VA_GPIO,
+                .pfn            = __phys_to_pfn(S5P64X0_PA_GPIO),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC0,
+                .pfn            = __phys_to_pfn(S5P64X0_PA_VIC0),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC1,
+                .pfn            = __phys_to_pfn(S5P64X0_PA_VIC1),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        },
+};
+
+static struct map_desc s5p6440_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S3C_VA_UART,
+                .pfn            = __phys_to_pfn(S5P6440_PA_UART(0)),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
+
+static struct map_desc s5p6450_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S3C_VA_UART,
+                .pfn            = __phys_to_pfn(S5P6450_PA_UART(0)),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_UART + SZ_512K,
+                .pfn            = __phys_to_pfn(S5P6450_PA_UART(5)),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
+
+static void s5p64x0_idle(void)
+{
+        unsigned long val;
+
+        if (!need_resched()) {
+                val = __raw_readl(S5P64X0_PWR_CFG);
+                val &= ~(0x3 << 5);
+                val |= (0x1 << 5);
+                __raw_writel(val, S5P64X0_PWR_CFG);
+
+                cpu_do_idle();
+        }
+        local_irq_enable();
+}
+
+/*
+ * s5p64x0_map_io
+ *
+ * register the standard CPU IO areas
+ */
+
+void __init s5p6440_map_io(void)
+{
+        /* initialize any device information early */
+        s3c_adc_setname("s3c64xx-adc");
+
+        iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
+        iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
+}
+
+void __init s5p6450_map_io(void)
+{
+        /* initialize any device information early */
+        s3c_adc_setname("s3c64xx-adc");
+
+        iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
+        iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6440_iodesc));
+}
+
+/*
+ * s5p64x0_init_clocks
+ *
+ * register and setup the CPU clocks
+ */
+
+void __init s5p6440_init_clocks(int xtal)
+{
+        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+
+        s3c24xx_register_baseclocks(xtal);
+        s5p_register_clocks(xtal);
+        s5p6440_register_clocks();
+        s5p6440_setup_clocks();
+}
+
+void __init s5p6450_init_clocks(int xtal)
+{
+        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+
+        s3c24xx_register_baseclocks(xtal);
+        s5p_register_clocks(xtal);
+        s5p6450_register_clocks();
+        s5p6450_setup_clocks();
+}
+
+/*
+ * s5p64x0_init_irq
+ *
+ * register the CPU interrupts
+ */
+
+void __init s5p6440_init_irq(void)
+{
+        /* S5P6440 supports 2 VIC */
+        u32 vic[2];
+
+        /*
+         * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
+         * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
+         */
+        vic[0] = 0xff800ae7;
+        vic[1] = 0xffbf23e5;
+
+        s5p_init_irq(vic, ARRAY_SIZE(vic));
+}
+
+void __init s5p6450_init_irq(void)
+{
+        /* S5P6450 supports only 2 VIC */
+        u32 vic[2];
+
+        /*
+         * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
+         * VIC1 is missing IRQ VIC1[12, 14, 23]
+         */
+        vic[0] = 0xff9f1fff;
+        vic[1] = 0xff7fafff;
+
+        s5p_init_irq(vic, ARRAY_SIZE(vic));
+}
+
+struct sysdev_class s5p64x0_sysclass = {
+        .name   = "s5p64x0-core",
+};
+
+static struct sys_device s5p64x0_sysdev = {
+        .cls    = &s5p64x0_sysclass,
+};
+
+static int __init s5p64x0_core_init(void)
+{
+        return sysdev_class_register(&s5p64x0_sysclass);
+}
+core_initcall(s5p64x0_core_init);
+
+int __init s5p64x0_init(void)
+{
+        printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
+
+        /* set idle function */
+        pm_idle = s5p64x0_idle;
+
+        return sysdev_register(&s5p64x0_sysdev);
+}
diff --git a/arch/arm/mach-s5p64x0/dev-audio.c b/arch/arm/mach-s5p64x0/dev-audio.c
new file mode 100644
index 000000000000..fa097bd68ca4
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/dev-audio.c
@@ -0,0 +1,164 @@
+/* linux/arch/arm/mach-s5p64x0/dev-audio.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co. Ltd
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/gpio.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/audio.h>
+
+#include <mach/map.h>
+#include <mach/dma.h>
+#include <mach/irqs.h>
+
+static int s5p6440_cfg_i2s(struct platform_device *pdev)
+{
+        /* configure GPIO for i2s port */
+        switch (pdev->id) {
+        case -1:
+                s3c_gpio_cfgpin(S5P6440_GPR(4), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(5), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(5));
+                break;
+
+        default:
+                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int s5p6450_cfg_i2s(struct platform_device *pdev)
+{
+        /* configure GPIO for i2s port */
+        switch (pdev->id) {
+        case -1:
+                s3c_gpio_cfgpin(S5P6450_GPB(4), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6450_GPR(4), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6450_GPR(5), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6450_GPR(6), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6450_GPR(7), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6450_GPR(8), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6450_GPR(13), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6450_GPR(14), S3C_GPIO_SFN(5));
+                break;
+
+        default:
+                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct s3c_audio_pdata s5p6440_i2s_pdata = {
+        .cfg_gpio = s5p6440_cfg_i2s,
+};
+
+static struct s3c_audio_pdata s5p6450_i2s_pdata = {
+        .cfg_gpio = s5p6450_cfg_i2s,
+};
+
+static struct resource s5p64x0_iis0_resource[] = {
+        [0] = {
+                .start  = S5P64X0_PA_I2S,
+                .end    = S5P64X0_PA_I2S + 0x100 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = DMACH_I2S0_TX,
+                .end    = DMACH_I2S0_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start  = DMACH_I2S0_RX,
+                .end    = DMACH_I2S0_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+struct platform_device s5p6440_device_iis = {
+        .name           = "s3c64xx-iis-v4",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(s5p64x0_iis0_resource),
+        .resource       = s5p64x0_iis0_resource,
+        .dev = {
+                .platform_data = &s5p6440_i2s_pdata,
+        },
+};
+
+struct platform_device s5p6450_device_iis0 = {
+        .name           = "s3c64xx-iis-v4",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(s5p64x0_iis0_resource),
+        .resource       = s5p64x0_iis0_resource,
+        .dev = {
+                .platform_data = &s5p6450_i2s_pdata,
+        },
+};
+
+/* PCM Controller platform_devices */
+
+static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev)
+{
+        switch (pdev->id) {
+        case 0:
+                s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(2));
+                break;
+
+        default:
+                printk(KERN_DEBUG "Invalid PCM Controller number!");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct s3c_audio_pdata s5p6440_pcm_pdata = {
+        .cfg_gpio = s5p6440_pcm_cfg_gpio,
+};
+
+static struct resource s5p6440_pcm0_resource[] = {
+        [0] = {
+                .start  = S5P64X0_PA_PCM,
+                .end    = S5P64X0_PA_PCM + 0x100 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = DMACH_PCM0_TX,
+                .end    = DMACH_PCM0_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start  = DMACH_PCM0_RX,
+                .end    = DMACH_PCM0_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+struct platform_device s5p6440_device_pcm = {
+        .name           = "samsung-pcm",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(s5p6440_pcm0_resource),
+        .resource       = s5p6440_pcm0_resource,
+        .dev = {
+                .platform_data = &s5p6440_pcm_pdata,
+        },
+};
diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c
new file mode 100644
index 000000000000..5b69ec4c8af3
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/dev-spi.c
@@ -0,0 +1,232 @@
+/* linux/arch/arm/mach-s5p64x0/dev-spi.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/gpio.h>
+
+#include <mach/dma.h>
+#include <mach/map.h>
+#include <mach/irqs.h>
+#include <mach/regs-clock.h>
+#include <mach/spi-clocks.h>
+
+#include <plat/s3c64xx-spi.h>
+#include <plat/gpio-cfg.h>
+
+static char *s5p64x0_spi_src_clks[] = {
+        [S5P64X0_SPI_SRCCLK_PCLK] = "pclk",
+        [S5P64X0_SPI_SRCCLK_SCLK] = "sclk_spi",
+};
+
+/* SPI Controller platform_devices */
+
+/* Since we emulate multi-cs capability, we do not touch the CS.
+ * The emulated CS is toggled by board specific mechanism, as it can
+ * be either some immediate GPIO or some signal out of some other
+ * chip in between ... or some yet another way.
+ * We simply do not assume anything about CS.
+ */
+static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
+{
+        switch (pdev->id) {
+        case 0:
+                s3c_gpio_cfgpin(S5P6440_GPC(0), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPC(1), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPC(2), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5P6440_GPC(0), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6440_GPC(1), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6440_GPC(2), S3C_GPIO_PULL_UP);
+                break;
+
+        case 1:
+                s3c_gpio_cfgpin(S5P6440_GPC(4), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPC(5), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPC(6), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5P6440_GPC(4), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6440_GPC(5), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6440_GPC(6), S3C_GPIO_PULL_UP);
+                break;
+
+        default:
+                dev_err(&pdev->dev, "Invalid SPI Controller number!");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
+{
+        switch (pdev->id) {
+        case 0:
+                s3c_gpio_cfgpin(S5P6450_GPC(0), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6450_GPC(1), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6450_GPC(2), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5P6450_GPC(0), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6450_GPC(1), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6450_GPC(2), S3C_GPIO_PULL_UP);
+                break;
+
+        case 1:
+                s3c_gpio_cfgpin(S5P6450_GPC(4), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6450_GPC(5), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6450_GPC(6), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5P6450_GPC(4), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6450_GPC(5), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6450_GPC(6), S3C_GPIO_PULL_UP);
+                break;
+
+        default:
+                dev_err(&pdev->dev, "Invalid SPI Controller number!");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct resource s5p64x0_spi0_resource[] = {
+        [0] = {
+                .start  = S5P64X0_PA_SPI0,
+                .end    = S5P64X0_PA_SPI0 + 0x100 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = DMACH_SPI0_TX,
+                .end    = DMACH_SPI0_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start  = DMACH_SPI0_RX,
+                .end    = DMACH_SPI0_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = IRQ_SPI0,
+                .end    = IRQ_SPI0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
+        .cfg_gpio       = s5p6440_spi_cfg_gpio,
+        .fifo_lvl_mask  = 0x1ff,
+        .rx_lvl_offset  = 15,
+};
+
+static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
+        .cfg_gpio       = s5p6450_spi_cfg_gpio,
+        .fifo_lvl_mask  = 0x1ff,
+        .rx_lvl_offset  = 15,
+};
+
+static u64 spi_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s5p64x0_device_spi0 = {
+        .name           = "s3c64xx-spi",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(s5p64x0_spi0_resource),
+        .resource       = s5p64x0_spi0_resource,
+        .dev = {
+                .dma_mask               = &spi_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+static struct resource s5p64x0_spi1_resource[] = {
+        [0] = {
+                .start  = S5P64X0_PA_SPI1,
+                .end    = S5P64X0_PA_SPI1 + 0x100 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = DMACH_SPI1_TX,
+                .end    = DMACH_SPI1_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start  = DMACH_SPI1_RX,
+                .end    = DMACH_SPI1_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = IRQ_SPI1,
+                .end    = IRQ_SPI1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
+        .cfg_gpio       = s5p6440_spi_cfg_gpio,
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 15,
+};
+
+static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
+        .cfg_gpio       = s5p6450_spi_cfg_gpio,
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 15,
+};
+
+struct platform_device s5p64x0_device_spi1 = {
+        .name           = "s3c64xx-spi",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(s5p64x0_spi1_resource),
+        .resource       = s5p64x0_spi1_resource,
+        .dev = {
+                .dma_mask               = &spi_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
+{
+        unsigned int id;
+        struct s3c64xx_spi_info *pd;
+
+        id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
+
+        /* Reject invalid configuration */
+        if (!num_cs || src_clk_nr < 0
+                        || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) {
+                printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
+                return;
+        }
+
+        switch (cntrlr) {
+        case 0:
+                if (id == 0x50000)
+                        pd = &s5p6450_spi0_pdata;
+                else
+                        pd = &s5p6440_spi0_pdata;
+
+                s5p64x0_device_spi0.dev.platform_data = pd;
+                break;
+        case 1:
+                if (id == 0x50000)
+                        pd = &s5p6450_spi1_pdata;
+                else
+                        pd = &s5p6440_spi1_pdata;
+
+                s5p64x0_device_spi1.dev.platform_data = pd;
+                break;
+        default:
+                printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
+                                                        __func__, cntrlr);
+                return;
+        }
+
+        pd->num_cs = num_cs;
+        pd->src_clk_nr = src_clk_nr;
+        pd->src_clk_name = s5p64x0_spi_src_clks[src_clk_nr];
+}
diff --git a/arch/arm/mach-s5p6440/dma.c b/arch/arm/mach-s5p64x0/dma.c
index 07606ad57519..29a8c2410049 100644
--- a/arch/arm/mach-s5p6440/dma.c
+++ b/arch/arm/mach-s5p64x0/dma.c
@@ -1,4 +1,8 @@
-/*
+/* linux/arch/arm/mach-s5p64x0/dma.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
  * Copyright (C) 2010 Samsung Electronics Co. Ltd.
  *      Jaswinder Singh <jassi.brar@samsung.com>
  *
@@ -15,26 +19,25 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
+*/
 
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 
-#include <plat/devs.h>
-#include <plat/irqs.h>
-
 #include <mach/map.h>
 #include <mach/irqs.h>
+#include <mach/regs-clock.h>
 
+#include <plat/devs.h>
 #include <plat/s3c-pl330-pdata.h>
 
 static u64 dma_dmamask = DMA_BIT_MASK(32);
 
-static struct resource s5p6440_pdma_resource[] = {
+static struct resource s5p64x0_pdma_resource[] = {
         [0] = {
-                .start  = S5P6440_PA_PDMA,
-                .end    = S5P6440_PA_PDMA + SZ_4K,
-                .flags = IORESOURCE_MEM,
+                .start  = S5P64X0_PA_PDMA,
+                .end    = S5P64X0_PA_PDMA + SZ_4K,
+                .flags  = IORESOURCE_MEM,
         },
         [1] = {
                 .start  = IRQ_DMA0,
@@ -80,26 +83,67 @@ static struct s3c_pl330_platdata s5p6440_pdma_pdata = {
         },
 };
 
-static struct platform_device s5p6440_device_pdma = {
+static struct s3c_pl330_platdata s5p6450_pdma_pdata = {
+        .peri = {
+                [0] = DMACH_UART0_RX,
+                [1] = DMACH_UART0_TX,
+                [2] = DMACH_UART1_RX,
+                [3] = DMACH_UART1_TX,
+                [4] = DMACH_UART2_RX,
+                [5] = DMACH_UART2_TX,
+                [6] = DMACH_UART3_RX,
+                [7] = DMACH_UART3_TX,
+                [8] = DMACH_UART4_RX,
+                [9] = DMACH_UART4_TX,
+                [10] = DMACH_PCM0_TX,
+                [11] = DMACH_PCM0_RX,
+                [12] = DMACH_I2S0_TX,
+                [13] = DMACH_I2S0_RX,
+                [14] = DMACH_SPI0_TX,
+                [15] = DMACH_SPI0_RX,
+                [16] = DMACH_PCM1_TX,
+                [17] = DMACH_PCM1_RX,
+                [18] = DMACH_PCM2_TX,
+                [19] = DMACH_PCM2_RX,
+                [20] = DMACH_SPI1_TX,
+                [21] = DMACH_SPI1_RX,
+                [22] = DMACH_USI_TX,
+                [23] = DMACH_USI_RX,
+                [24] = DMACH_MAX,
+                [25] = DMACH_I2S1_TX,
+                [26] = DMACH_I2S1_RX,
+                [27] = DMACH_I2S2_TX,
+                [28] = DMACH_I2S2_RX,
+                [29] = DMACH_PWM,
+                [30] = DMACH_UART5_RX,
+                [31] = DMACH_UART5_TX,
+        },
+};
+
+static struct platform_device s5p64x0_device_pdma = {
         .name           = "s3c-pl330",
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(s5p6440_pdma_resource),
-        .resource       = s5p6440_pdma_resource,
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(s5p64x0_pdma_resource),
+        .resource       = s5p64x0_pdma_resource,
         .dev            = {
                 .dma_mask = &dma_dmamask,
                 .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &s5p6440_pdma_pdata,
         },
 };
 
-static struct platform_device *s5p6440_dmacs[] __initdata = {
-        &s5p6440_device_pdma,
-};
-
-static int __init s5p6440_dma_init(void)
+static int __init s5p64x0_dma_init(void)
 {
-        platform_add_devices(s5p6440_dmacs, ARRAY_SIZE(s5p6440_dmacs));
+        unsigned int id;
+
+        id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
+
+        if (id == 0x50000)
+                s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata;
+        else
+                s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata;
+
+        platform_device_register(&s5p64x0_device_pdma);
 
         return 0;
 }
-arch_initcall(s5p6440_dma_init);
+arch_initcall(s5p64x0_dma_init);
diff --git a/arch/arm/mach-s5p6440/gpio.c b/arch/arm/mach-s5p64x0/gpio.c
index 8bf6e0ce51c9..39159dd5a29a 100644
--- a/arch/arm/mach-s5p6440/gpio.c
+++ b/arch/arm/mach-s5p64x0/gpio.c
@@ -1,14 +1,14 @@
-/* arch/arm/mach-s5p6440/gpio.c
+/* linux/arch/arm/mach-s5p64x0/gpio.c
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5P6440 - GPIOlib support
+ * S5P64X0 - GPIOlib support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
- */
+*/
 
 #include <linux/kernel.h>
 #include <linux/irq.h>
@@ -22,26 +22,29 @@
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
 
-/* GPIO bank summary:
-*
-* Bank  GPIOs   Style   SlpCon  ExtInt Group
-* A     6       4Bit    Yes     1
-* B     7       4Bit    Yes     1
-* C     8       4Bit    Yes     2
-* F     2       2Bit    Yes     4 [1]
-* G     7       4Bit    Yes     5
-* H     10      4Bit[2] Yes     6
-* I     16      2Bit    Yes     None
-* J     12      2Bit    Yes     None
-* N     16      2Bit    No      IRQ_EINT
-* P     8       2Bit    Yes     8
-* R     15      4Bit[2] Yes     8
-*
-* [1] BANKF pins 14,15 do not form part of the external interrupt sources
-* [2] BANK has two control registers, GPxCON0 and GPxCON1
-*/
+/* To be implemented S5P6450 GPIO */
+
+/*
+ * S5P6440 GPIO bank summary:
+ *
+ * Bank GPIOs   Style   SlpCon  ExtInt Group
+ * A    6       4Bit    Yes     1
+ * B    7       4Bit    Yes     1
+ * C    8       4Bit    Yes     2
+ * F    2       2Bit    Yes     4 [1]
+ * G    7       4Bit    Yes     5
+ * H    10      4Bit[2] Yes     6
+ * I    16      2Bit    Yes     None
+ * J    12      2Bit    Yes     None
+ * N    16      2Bit    No      IRQ_EINT
+ * P    8       2Bit    Yes     8
+ * R    15      4Bit[2] Yes     8
+ *
+ * [1] BANKF pins 14,15 do not form part of the external interrupt sources
+ * [2] BANK has two control registers, GPxCON0 and GPxCON1
+ */
 
-static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
+static int s5p64x0_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
                                              unsigned int offset)
 {
         struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
@@ -77,7 +80,7 @@ static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
         return 0;
 }
 
-static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
+static int s5p64x0_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
                                               unsigned int offset, int value)
 {
         struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
@@ -124,12 +127,11 @@ static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
         return 0;
 }
 
-int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
+int s5p64x0_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
                                    unsigned int off, unsigned int cfg)
 {
         void __iomem *reg = chip->base;
         unsigned int shift;
-        unsigned long flags;
         u32 con;
 
         switch (off) {
@@ -155,26 +157,22 @@ int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
                 cfg <<= shift;
         }
 
-        s3c_gpio_lock(chip, flags);
-
         con = __raw_readl(reg);
         con &= ~(0xf << shift);
         con |= cfg;
         __raw_writel(con, reg);
 
-        s3c_gpio_unlock(chip, flags);
-
         return 0;
 }
 
-static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = {
+static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = {
         {
                 .cfg_eint       = 0,
         }, {
                 .cfg_eint       = 7,
         }, {
                 .cfg_eint       = 3,
-                .set_config     = s5p6440_gpio_setcfg_4bit_rbank,
+                .set_config     = s5p64x0_gpio_setcfg_4bit_rbank,
         }, {
                 .cfg_eint       = 0,
                 .set_config     = s3c_gpio_setcfg_s3c24xx,
@@ -193,7 +191,7 @@ static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = {
 static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
         {
                 .base   = S5P6440_GPA_BASE,
-                .config = &s5p6440_gpio_cfgs[1],
+                .config = &s5p64x0_gpio_cfgs[1],
                 .chip   = {
                         .base   = S5P6440_GPA(0),
                         .ngpio  = S5P6440_GPIO_A_NR,
@@ -201,7 +199,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
                 },
         }, {
                 .base   = S5P6440_GPB_BASE,
-                .config = &s5p6440_gpio_cfgs[1],
+                .config = &s5p64x0_gpio_cfgs[1],
                 .chip   = {
                         .base   = S5P6440_GPB(0),
                         .ngpio  = S5P6440_GPIO_B_NR,
@@ -209,7 +207,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
                 },
         }, {
                 .base   = S5P6440_GPC_BASE,
-                .config = &s5p6440_gpio_cfgs[1],
+                .config = &s5p64x0_gpio_cfgs[1],
                 .chip   = {
                         .base   = S5P6440_GPC(0),
                         .ngpio  = S5P6440_GPIO_C_NR,
@@ -217,7 +215,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
                 },
         }, {
                 .base   = S5P6440_GPG_BASE,
-                .config = &s5p6440_gpio_cfgs[1],
+                .config = &s5p64x0_gpio_cfgs[1],
                 .chip   = {
                         .base   = S5P6440_GPG(0),
                         .ngpio  = S5P6440_GPIO_G_NR,
@@ -229,7 +227,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
 static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
         {
                 .base   = S5P6440_GPH_BASE + 0x4,
-                .config = &s5p6440_gpio_cfgs[1],
+                .config = &s5p64x0_gpio_cfgs[1],
                 .chip   = {
                         .base   = S5P6440_GPH(0),
                         .ngpio  = S5P6440_GPIO_H_NR,
@@ -238,10 +236,10 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
         },
 };
 
-static struct s3c_gpio_chip gpio_rbank_4bit2[] = {
+static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
         {
                 .base   = S5P6440_GPR_BASE + 0x4,
-                .config = &s5p6440_gpio_cfgs[2],
+                .config = &s5p64x0_gpio_cfgs[2],
                 .chip   = {
                         .base   = S5P6440_GPR(0),
                         .ngpio  = S5P6440_GPIO_R_NR,
@@ -253,7 +251,7 @@ static struct s3c_gpio_chip gpio_rbank_4bit2[] = {
 static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
         {
                 .base   = S5P6440_GPF_BASE,
-                .config = &s5p6440_gpio_cfgs[5],
+                .config = &s5p64x0_gpio_cfgs[5],
                 .chip   = {
                         .base   = S5P6440_GPF(0),
                         .ngpio  = S5P6440_GPIO_F_NR,
@@ -261,7 +259,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
                 },
         }, {
                 .base   = S5P6440_GPI_BASE,
-                .config = &s5p6440_gpio_cfgs[3],
+                .config = &s5p64x0_gpio_cfgs[3],
                 .chip   = {
                         .base   = S5P6440_GPI(0),
                         .ngpio  = S5P6440_GPIO_I_NR,
@@ -269,7 +267,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
                 },
         }, {
                 .base   = S5P6440_GPJ_BASE,
-                .config = &s5p6440_gpio_cfgs[3],
+                .config = &s5p64x0_gpio_cfgs[3],
                 .chip   = {
                         .base   = S5P6440_GPJ(0),
                         .ngpio  = S5P6440_GPIO_J_NR,
@@ -277,7 +275,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
                 },
         }, {
                 .base   = S5P6440_GPN_BASE,
-                .config = &s5p6440_gpio_cfgs[4],
+                .config = &s5p64x0_gpio_cfgs[4],
                 .chip   = {
                         .base   = S5P6440_GPN(0),
                         .ngpio  = S5P6440_GPIO_N_NR,
@@ -285,7 +283,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
                 },
         }, {
                 .base   = S5P6440_GPP_BASE,
-                .config = &s5p6440_gpio_cfgs[5],
+                .config = &s5p64x0_gpio_cfgs[5],
                 .chip   = {
                         .base   = S5P6440_GPP(0),
                         .ngpio  = S5P6440_GPIO_P_NR,
@@ -294,7 +292,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
         },
 };
 
-void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
+void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
 {
         for (; nr_chips > 0; nr_chips--, chipcfg++) {
                 if (!chipcfg->set_config)
@@ -308,13 +306,13 @@ void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
         }
 }
 
-static void __init s5p6440_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
+static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
                                                 int nr_chips)
 {
         for (; nr_chips > 0; nr_chips--, chip++) {
-                chip->chip.direction_input = s5p6440_gpiolib_rbank_4bit2_input;
+                chip->chip.direction_input = s5p64x0_gpiolib_rbank_4bit2_input;
                 chip->chip.direction_output =
-                                        s5p6440_gpiolib_rbank_4bit2_output;
+                                        s5p64x0_gpiolib_rbank_4bit2_output;
                 s3c_gpiolib_add(chip);
         }
 }
@@ -324,8 +322,8 @@ static int __init s5p6440_gpiolib_init(void)
         struct s3c_gpio_chip *chips = s5p6440_gpio_2bit;
         int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit);
 
-        s5p6440_gpiolib_set_cfg(s5p6440_gpio_cfgs,
-                                ARRAY_SIZE(s5p6440_gpio_cfgs));
+        s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
+                                ARRAY_SIZE(s5p64x0_gpio_cfgs));
 
         for (; nr_chips > 0; nr_chips--, chips++)
                 s3c_gpiolib_add(chips);
@@ -336,8 +334,8 @@ static int __init s5p6440_gpiolib_init(void)
         samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
                                 ARRAY_SIZE(s5p6440_gpio_4bit2));
 
-        s5p6440_gpio_add_rbank_4bit2(gpio_rbank_4bit2,
-                                ARRAY_SIZE(gpio_rbank_4bit2));
+        s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
+                                ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
 
         return 0;
 }
diff --git a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
new file mode 100644
index 000000000000..79b04e6a6f8e
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
@@ -0,0 +1,33 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* pull in the relevant register and map files. */
+
+#include <plat/map-base.h>
+#include <plat/map-s5p.h>
+
+#include <plat/regs-serial.h>
+
+        .macro addruart, rp, rv
+                mov     \rp, #0xE0000000
+                orr     \rp, \rp, #0x00100000
+                ldr     \rp, [\rp, #0x118 ]
+                and     \rp, \rp, #0xff000
+                teq     \rp, #0x50000           @@ S5P6450
+                ldreq   \rp, =0xEC800000
+                movne   \rp, #0xEC000000        @@ S5P6440
+                ldrne   \rv, = S3C_VA_UART
+#if CONFIG_DEBUG_S3C_UART != 0
+                add     \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
+                add     \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
+#endif
+        .endm
+
+#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s5p6440/include/mach/dma.h b/arch/arm/mach-s5p64x0/include/mach/dma.h
index 81209eb1409b..81209eb1409b 100644
--- a/arch/arm/mach-s5p6440/include/mach/dma.h
+++ b/arch/arm/mach-s5p64x0/include/mach/dma.h
diff --git a/arch/arm/mach-s5p6440/include/mach/entry-macro.S b/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
index e65f1b967262..10b62b4f8211 100644
--- a/arch/arm/mach-s5p6440/include/mach/entry-macro.S
+++ b/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/entry-macro.S
+/* linux/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * Low-level IRQ helper macros for the Samsung S5P6440
+ * Low-level IRQ helper macros for the Samsung S5P64X0
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p64x0/include/mach/gpio.h b/arch/arm/mach-s5p64x0/include/mach/gpio.h
new file mode 100644
index 000000000000..5486c8f01f1d
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/gpio.h
@@ -0,0 +1,139 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/gpio.h
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - GPIO lib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H __FILE__
+
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
+
+/* GPIO bank sizes */
+
+#define S5P6440_GPIO_A_NR       (6)
+#define S5P6440_GPIO_B_NR       (7)
+#define S5P6440_GPIO_C_NR       (8)
+#define S5P6440_GPIO_F_NR       (2)
+#define S5P6440_GPIO_G_NR       (7)
+#define S5P6440_GPIO_H_NR       (10)
+#define S5P6440_GPIO_I_NR       (16)
+#define S5P6440_GPIO_J_NR       (12)
+#define S5P6440_GPIO_N_NR       (16)
+#define S5P6440_GPIO_P_NR       (8)
+#define S5P6440_GPIO_R_NR       (15)
+
+#define S5P6450_GPIO_A_NR       (6)
+#define S5P6450_GPIO_B_NR       (7)
+#define S5P6450_GPIO_C_NR       (8)
+#define S5P6450_GPIO_D_NR       (8)
+#define S5P6450_GPIO_F_NR       (2)
+#define S5P6450_GPIO_G_NR       (14)
+#define S5P6450_GPIO_H_NR       (10)
+#define S5P6450_GPIO_I_NR       (16)
+#define S5P6450_GPIO_J_NR       (12)
+#define S5P6450_GPIO_K_NR       (5)
+#define S5P6450_GPIO_N_NR       (16)
+#define S5P6450_GPIO_P_NR       (11)
+#define S5P6450_GPIO_Q_NR       (14)
+#define S5P6450_GPIO_R_NR       (15)
+#define S5P6450_GPIO_S_NR       (8)
+
+/* GPIO bank numbers */
+
+/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
+ * space for debugging purposes so that any accidental
+ * change from one gpio bank to another can be caught.
+*/
+
+#define S5P64X0_GPIO_NEXT(__gpio) \
+        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
+
+enum s5p6440_gpio_number {
+        S5P6440_GPIO_A_START    = 0,
+        S5P6440_GPIO_B_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_A),
+        S5P6440_GPIO_C_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_B),
+        S5P6440_GPIO_F_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_C),
+        S5P6440_GPIO_G_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_F),
+        S5P6440_GPIO_H_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_G),
+        S5P6440_GPIO_I_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_H),
+        S5P6440_GPIO_J_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_I),
+        S5P6440_GPIO_N_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_J),
+        S5P6440_GPIO_P_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_N),
+        S5P6440_GPIO_R_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_P),
+};
+
+enum s5p6450_gpio_number {
+        S5P6450_GPIO_A_START    = 0,
+        S5P6450_GPIO_B_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_A),
+        S5P6450_GPIO_C_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_B),
+        S5P6450_GPIO_D_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_C),
+        S5P6450_GPIO_F_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_D),
+        S5P6450_GPIO_G_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_F),
+        S5P6450_GPIO_H_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_G),
+        S5P6450_GPIO_I_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_H),
+        S5P6450_GPIO_J_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_I),
+        S5P6450_GPIO_K_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_J),
+        S5P6450_GPIO_N_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_K),
+        S5P6450_GPIO_P_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_N),
+        S5P6450_GPIO_Q_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_P),
+        S5P6450_GPIO_R_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_Q),
+        S5P6450_GPIO_S_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_R),
+};
+
+/* GPIO number definitions */
+
+#define S5P6440_GPA(_nr)        (S5P6440_GPIO_A_START + (_nr))
+#define S5P6440_GPB(_nr)        (S5P6440_GPIO_B_START + (_nr))
+#define S5P6440_GPC(_nr)        (S5P6440_GPIO_C_START + (_nr))
+#define S5P6440_GPF(_nr)        (S5P6440_GPIO_F_START + (_nr))
+#define S5P6440_GPG(_nr)        (S5P6440_GPIO_G_START + (_nr))
+#define S5P6440_GPH(_nr)        (S5P6440_GPIO_H_START + (_nr))
+#define S5P6440_GPI(_nr)        (S5P6440_GPIO_I_START + (_nr))
+#define S5P6440_GPJ(_nr)        (S5P6440_GPIO_J_START + (_nr))
+#define S5P6440_GPN(_nr)        (S5P6440_GPIO_N_START + (_nr))
+#define S5P6440_GPP(_nr)        (S5P6440_GPIO_P_START + (_nr))
+#define S5P6440_GPR(_nr)        (S5P6440_GPIO_R_START + (_nr))
+
+#define S5P6450_GPA(_nr)        (S5P6450_GPIO_A_START + (_nr))
+#define S5P6450_GPB(_nr)        (S5P6450_GPIO_B_START + (_nr))
+#define S5P6450_GPC(_nr)        (S5P6450_GPIO_C_START + (_nr))
+#define S5P6450_GPD(_nr)        (S5P6450_GPIO_D_START + (_nr))
+#define S5P6450_GPF(_nr)        (S5P6450_GPIO_F_START + (_nr))
+#define S5P6450_GPG(_nr)        (S5P6450_GPIO_G_START + (_nr))
+#define S5P6450_GPH(_nr)        (S5P6450_GPIO_H_START + (_nr))
+#define S5P6450_GPI(_nr)        (S5P6450_GPIO_I_START + (_nr))
+#define S5P6450_GPJ(_nr)        (S5P6450_GPIO_J_START + (_nr))
+#define S5P6450_GPK(_nr)        (S5P6450_GPIO_K_START + (_nr))
+#define S5P6450_GPN(_nr)        (S5P6450_GPIO_N_START + (_nr))
+#define S5P6450_GPP(_nr)        (S5P6450_GPIO_P_START + (_nr))
+#define S5P6450_GPQ(_nr)        (S5P6450_GPIO_Q_START + (_nr))
+#define S5P6450_GPR(_nr)        (S5P6450_GPIO_R_START + (_nr))
+#define S5P6450_GPS(_nr)        (S5P6450_GPIO_S_START + (_nr))
+
+/* the end of the S5P64X0 specific gpios */
+
+#define S5P6440_GPIO_END        (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1)
+#define S5P6450_GPIO_END        (S5P6450_GPS(S5P6450_GPIO_S_NR) + 1)
+
+#define S5P64X0_GPIO_END        (S5P6440_GPIO_END > S5P6450_GPIO_END ?  \
+                                 S5P6440_GPIO_END : S5P6450_GPIO_END)
+
+#define S3C_GPIO_END            S5P64X0_GPIO_END
+
+/* define the number of gpios we need to the one after the last GPIO range */
+
+#define ARCH_NR_GPIOS           (S5P64X0_GPIO_END + CONFIG_SAMSUNG_GPIO_EXTRA)
+
+#include <asm-generic/gpio.h>
+
+#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/hardware.h b/arch/arm/mach-s5p64x0/include/mach/hardware.h
index be8b26e875db..d3e87996dd9a 100644
--- a/arch/arm/mach-s5p6440/include/mach/hardware.h
+++ b/arch/arm/mach-s5p64x0/include/mach/hardware.h
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/hardware.h
+/* linux/arch/arm/mach-s5p64x0/include/mach/hardware.h
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5P6440 - Hardware support
+ * S5P64X0 - Hardware support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p64x0/include/mach/i2c.h b/arch/arm/mach-s5p64x0/include/mach/i2c.h
new file mode 100644
index 000000000000..887d25209e8e
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/i2c.h
@@ -0,0 +1,17 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/i2c.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 I2C configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+extern void s5p6440_i2c0_cfg_gpio(struct platform_device *dev);
+extern void s5p6440_i2c1_cfg_gpio(struct platform_device *dev);
+
+extern void s5p6450_i2c0_cfg_gpio(struct platform_device *dev);
+extern void s5p6450_i2c1_cfg_gpio(struct platform_device *dev);
diff --git a/arch/arm/mach-s5p64x0/include/mach/io.h b/arch/arm/mach-s5p64x0/include/mach/io.h
new file mode 100644
index 000000000000..a3e095c02fb5
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/io.h
@@ -0,0 +1,25 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/io.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben-linux@fluff.org>
+ *
+ * Default IO routines for S5P64X0 based
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+/* No current ISA/PCI bus support. */
+#define __io(a)         __typesafe_io(a)
+#define __mem_pci(a)    (a)
+
+#define IO_SPACE_LIMIT (0xFFFFFFFF)
+
+#endif
diff --git a/arch/arm/mach-s5p6440/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h
index 16a761270de1..513abffc7604 100644
--- a/arch/arm/mach-s5p6440/include/mach/irqs.h
+++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h
@@ -1,17 +1,17 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/irqs.h
+/* linux/arch/arm/mach-s5p64x0/include/mach/irqs.h
  *
- * Copyright 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5P6440 - IRQ definitions
+ * S5P64X0 - IRQ definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
 */
 
-#ifndef __ASM_ARCH_S5P_IRQS_H
-#define __ASM_ARCH_S5P_IRQS_H __FILE__
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H __FILE__
 
 #include <plat/irqs.h>
 
@@ -20,10 +20,12 @@
 #define IRQ_EINT0_3             S5P_IRQ_VIC0(0)
 #define IRQ_EINT4_11            S5P_IRQ_VIC0(1)
 #define IRQ_RTC_TIC             S5P_IRQ_VIC0(2)
+#define IRQ_IIS1                S5P_IRQ_VIC0(3) /* for only S5P6450 */
+#define IRQ_IIS2                S5P_IRQ_VIC0(4) /* for only S5P6450 */
 #define IRQ_IIC1                S5P_IRQ_VIC0(5)
 #define IRQ_I2SV40              S5P_IRQ_VIC0(6)
-#define IRQ_GPS                 S5P_IRQ_VIC0(7)
-#define IRQ_POST0               S5P_IRQ_VIC0(9)
+#define IRQ_GPS                 S5P_IRQ_VIC0(7) /* for only S5P6450 */
+
 #define IRQ_2D                  S5P_IRQ_VIC0(11)
 #define IRQ_TIMER0_VIC          S5P_IRQ_VIC0(23)
 #define IRQ_TIMER1_VIC          S5P_IRQ_VIC0(24)
@@ -39,22 +41,26 @@
 
 #define IRQ_EINT12_15           S5P_IRQ_VIC1(0)
 #define IRQ_PCM0                S5P_IRQ_VIC1(2)
+#define IRQ_PCM1                S5P_IRQ_VIC1(3) /* for only S5P6450 */
+#define IRQ_PCM2                S5P_IRQ_VIC1(4) /* for only S5P6450 */
 #define IRQ_UART0               S5P_IRQ_VIC1(5)
 #define IRQ_UART1               S5P_IRQ_VIC1(6)
 #define IRQ_UART2               S5P_IRQ_VIC1(7)
 #define IRQ_UART3               S5P_IRQ_VIC1(8)
 #define IRQ_DMA0                S5P_IRQ_VIC1(9)
+#define IRQ_UART4               S5P_IRQ_VIC1(10)        /* S5P6450 */
+#define IRQ_UART5               S5P_IRQ_VIC1(11)        /* S5P6450 */
 #define IRQ_NFC                 S5P_IRQ_VIC1(13)
+#define IRQ_USI                 S5P_IRQ_VIC1(15)        /* S5P6450 */
 #define IRQ_SPI0                S5P_IRQ_VIC1(16)
 #define IRQ_SPI1                S5P_IRQ_VIC1(17)
+#define IRQ_HSMMC2              S5P_IRQ_VIC1(17)        /* Shared */
 #define IRQ_IIC                 S5P_IRQ_VIC1(18)
 #define IRQ_DISPCON3            S5P_IRQ_VIC1(19)
-#define IRQ_FIMGVG              S5P_IRQ_VIC1(20)
 #define IRQ_EINT_GROUPS         S5P_IRQ_VIC1(21)
-#define IRQ_PMU                 S5P_IRQ_VIC1(23)
+#define IRQ_PMU                 S5P_IRQ_VIC1(23)        /* S5P6440 */
 #define IRQ_HSMMC0              S5P_IRQ_VIC1(24)
 #define IRQ_HSMMC1              S5P_IRQ_VIC1(25)
-#define IRQ_HSMMC2              IRQ_SPI1        /* shared with SPI1 */
 #define IRQ_OTG                 S5P_IRQ_VIC1(26)
 #define IRQ_DSI                 S5P_IRQ_VIC1(27)
 #define IRQ_RTC_ALARM           S5P_IRQ_VIC1(28)
@@ -63,6 +69,24 @@
 #define IRQ_TC                  IRQ_PENDN
 #define IRQ_ADC                 S5P_IRQ_VIC1(31)
 
+/* UART interrupts, S5P6450 has 5 UARTs */
+#define IRQ_S5P_UART_BASE4      (96)
+#define IRQ_S5P_UART_BASE5      (100)
+
+#define IRQ_S5P_UART_RX4        (IRQ_S5P_UART_BASE4 + UART_IRQ_RXD)
+#define IRQ_S5P_UART_TX4        (IRQ_S5P_UART_BASE4 + UART_IRQ_TXD)
+#define IRQ_S5P_UART_ERR4       (IRQ_S5P_UART_BASE4 + UART_IRQ_ERR)
+
+#define IRQ_S5P_UART_RX5        (IRQ_S5P_UART_BASE5 + UART_IRQ_RXD)
+#define IRQ_S5P_UART_TX5        (IRQ_S5P_UART_BASE5 + UART_IRQ_TXD)
+#define IRQ_S5P_UART_ERR5       (IRQ_S5P_UART_BASE5 + UART_IRQ_ERR)
+
+/* S3C compatibilty defines */
+#define IRQ_S3CUART_RX4         IRQ_S5P_UART_RX4
+#define IRQ_S3CUART_RX5         IRQ_S5P_UART_RX5
+
+/* S5P6450 EINT feature will be added */
+
 /*
  * Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined
  * them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place
@@ -115,4 +139,4 @@
 
 #define NR_IRQS                 (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
 
-#endif /* __ASM_ARCH_S5P_IRQS_H */
+#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
new file mode 100644
index 000000000000..31e534156e06
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -0,0 +1,83 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/map.h
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MAP_H
+#define __ASM_ARCH_MAP_H __FILE__
+
+#include <plat/map-base.h>
+#include <plat/map-s5p.h>
+
+#define S5P64X0_PA_SDRAM        (0x20000000)
+
+#define S5P64X0_PA_CHIPID       (0xE0000000)
+#define S5P_PA_CHIPID           S5P64X0_PA_CHIPID
+
+#define S5P64X0_PA_SYSCON       (0xE0100000)
+#define S5P_PA_SYSCON           S5P64X0_PA_SYSCON
+
+#define S5P64X0_PA_GPIO         (0xE0308000)
+
+#define S5P64X0_PA_VIC0         (0xE4000000)
+#define S5P64X0_PA_VIC1         (0xE4100000)
+
+#define S5P64X0_PA_PDMA         (0xE9000000)
+
+#define S5P64X0_PA_TIMER        (0xEA000000)
+#define S5P_PA_TIMER            S5P64X0_PA_TIMER
+
+#define S5P64X0_PA_RTC          (0xEA100000)
+
+#define S5P64X0_PA_WDT          (0xEA200000)
+
+#define S5P6440_PA_UART(x)      (0xEC000000 + ((x) * S3C_UART_OFFSET))
+#define S5P6450_PA_UART(x)      ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
+
+#define S5P_PA_UART0            S5P6450_PA_UART(0)
+#define S5P_PA_UART1            S5P6450_PA_UART(1)
+#define S5P_PA_UART2            S5P6450_PA_UART(2)
+#define S5P_PA_UART3            S5P6450_PA_UART(3)
+#define S5P_PA_UART4            S5P6450_PA_UART(4)
+#define S5P_PA_UART5            S5P6450_PA_UART(5)
+
+#define S5P_SZ_UART             SZ_256
+
+#define S5P6440_PA_IIC0         (0xEC104000)
+#define S5P6440_PA_IIC1         (0xEC20F000)
+#define S5P6450_PA_IIC0         (0xEC100000)
+#define S5P6450_PA_IIC1         (0xEC200000)
+
+#define S5P64X0_PA_SPI0         (0xEC400000)
+#define S5P64X0_PA_SPI1         (0xEC500000)
+
+#define S5P64X0_PA_HSOTG        (0xED100000)
+
+#define S5P64X0_PA_HSMMC(x)     (0xED800000 + ((x) * 0x100000))
+
+#define S5P64X0_PA_I2S          (0xF2000000)
+
+#define S5P64X0_PA_PCM          (0xF2100000)
+
+#define S5P64X0_PA_ADC          (0xF3000000)
+
+/* compatibiltiy defines. */
+
+#define S3C_PA_HSMMC0           S5P64X0_PA_HSMMC(0)
+#define S3C_PA_HSMMC1           S5P64X0_PA_HSMMC(1)
+#define S3C_PA_HSMMC2           S5P64X0_PA_HSMMC(2)
+#define S3C_PA_IIC              S5P6440_PA_IIC0
+#define S3C_PA_IIC1             S5P6440_PA_IIC1
+#define S3C_PA_RTC              S5P64X0_PA_RTC
+#define S3C_PA_WDT              S5P64X0_PA_WDT
+
+#define SAMSUNG_PA_ADC          S5P64X0_PA_ADC
+
+#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/memory.h b/arch/arm/mach-s5p64x0/include/mach/memory.h
index d62910c71b56..1b036b0a24ce 100644
--- a/arch/arm/mach-s5p6440/include/mach/memory.h
+++ b/arch/arm/mach-s5p64x0/include/mach/memory.h
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/memory.h
+/* linux/arch/arm/mach-s5p64x0/include/mach/memory.h
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5P6440 - Memory definitions
+ * S5P64X0 - Memory definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -11,9 +11,9 @@
 */
 
 #ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H __FILE__
 
-#define PHYS_OFFSET             UL(0x20000000)
+#define PHYS_OFFSET             UL(0x20000000)
 #define CONSISTENT_DMA_SIZE     SZ_8M
 
 #endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/pwm-clock.h b/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
index 6a2a02fdf12a..19fff8b701c0 100644
--- a/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
+++ b/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
@@ -1,16 +1,14 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
+/* linux/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * Copyright 2008 Openmoko, Inc.
  * Copyright 2008 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
  *      http://armlinux.simtec.co.uk/
  *
- * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
- *
- * S5P6440 - pwm clock and timer support
+ * S5P64X0 - pwm clock and timer support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
new file mode 100644
index 000000000000..58e1bc813804
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
@@ -0,0 +1,63 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - Clock register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_CLOCK_H
+#define __ASM_ARCH_REGS_CLOCK_H __FILE__
+
+#include <mach/map.h>
+
+#define S5P_CLKREG(x)                   (S3C_VA_SYS + (x))
+
+#define S5P64X0_APLL_CON                S5P_CLKREG(0x0C)
+#define S5P64X0_MPLL_CON                S5P_CLKREG(0x10)
+#define S5P64X0_EPLL_CON                S5P_CLKREG(0x14)
+#define S5P64X0_EPLL_CON_K              S5P_CLKREG(0x18)
+
+#define S5P64X0_CLK_SRC0                S5P_CLKREG(0x1C)
+
+#define S5P64X0_CLK_DIV0                S5P_CLKREG(0x20)
+#define S5P64X0_CLK_DIV1                S5P_CLKREG(0x24)
+#define S5P64X0_CLK_DIV2                S5P_CLKREG(0x28)
+
+#define S5P64X0_CLK_GATE_HCLK0          S5P_CLKREG(0x30)
+#define S5P64X0_CLK_GATE_PCLK           S5P_CLKREG(0x34)
+#define S5P64X0_CLK_GATE_SCLK0          S5P_CLKREG(0x38)
+#define S5P64X0_CLK_GATE_MEM0           S5P_CLKREG(0x3C)
+
+#define S5P64X0_CLK_DIV3                S5P_CLKREG(0x40)
+
+#define S5P64X0_CLK_GATE_HCLK1          S5P_CLKREG(0x44)
+#define S5P64X0_CLK_GATE_SCLK1          S5P_CLKREG(0x48)
+
+#define S5P6450_DPLL_CON                S5P_CLKREG(0x50)
+#define S5P6450_DPLL_CON_K              S5P_CLKREG(0x54)
+
+#define S5P64X0_CLK_SRC1                S5P_CLKREG(0x10C)
+
+#define S5P64X0_SYS_ID                  S5P_CLKREG(0x118)
+#define S5P64X0_SYS_OTHERS              S5P_CLKREG(0x11C)
+
+#define S5P64X0_PWR_CFG                 S5P_CLKREG(0x804)
+#define S5P64X0_OTHERS                  S5P_CLKREG(0x900)
+
+#define S5P64X0_CLKDIV0_HCLK_SHIFT      (8)
+#define S5P64X0_CLKDIV0_HCLK_MASK       (0xF << S5P64X0_CLKDIV0_HCLK_SHIFT)
+
+#define S5P64X0_OTHERS_USB_SIG_MASK     (1 << 16)
+
+/* Compatibility defines */
+
+#define ARM_CLK_DIV                     S5P64X0_CLK_DIV0
+#define ARM_DIV_RATIO_SHIFT             0
+#define ARM_DIV_MASK                    (0xF << ARM_DIV_RATIO_SHIFT)
+
+#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
index 82ff753913da..85f448e20a8b 100644
--- a/arch/arm/mach-s5p6440/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
@@ -1,21 +1,24 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/regs-gpio.h
+/* linux/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5P6440 - GPIO register definitions
+ * S5P64X0 - GPIO register definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
- */
+*/
 
 #ifndef __ASM_ARCH_REGS_GPIO_H
 #define __ASM_ARCH_REGS_GPIO_H __FILE__
 
 #include <mach/map.h>
 
+/* Will be implemented S5P6442 GPIOlib */
+
 /* Base addresses for each of the banks */
+
 #define S5P6440_GPA_BASE                (S5P_VA_GPIO + 0x0000)
 #define S5P6440_GPB_BASE                (S5P_VA_GPIO + 0x0020)
 #define S5P6440_GPC_BASE                (S5P_VA_GPIO + 0x0040)
@@ -27,6 +30,7 @@
 #define S5P6440_GPN_BASE                (S5P_VA_GPIO + 0x0830)
 #define S5P6440_GPP_BASE                (S5P_VA_GPIO + 0x0160)
 #define S5P6440_GPR_BASE                (S5P_VA_GPIO + 0x0290)
+
 #define S5P6440_EINT0CON0               (S5P_VA_GPIO + 0x900)
 #define S5P6440_EINT0FLTCON0            (S5P_VA_GPIO + 0x910)
 #define S5P6440_EINT0FLTCON1            (S5P_VA_GPIO + 0x914)
@@ -34,19 +38,23 @@
 #define S5P6440_EINT0PEND               (S5P_VA_GPIO + 0x924)
 
 /* for LCD */
+
 #define S5P6440_SPCON_LCD_SEL_RGB       (1 << 0)
 #define S5P6440_SPCON_LCD_SEL_MASK      (3 << 0)
 
-/* These set of macros are not really useful for the
- * GPF/GPI/GPJ/GPN/GPP,
- * useful for others set of GPIO's (4 bit)
+/*
+ * These set of macros are not really useful for the
+ * GPF/GPI/GPJ/GPN/GPP, useful for others set of GPIO's (4 bit)
  */
+
 #define S5P6440_GPIO_CONMASK(__gpio)    (0xf << ((__gpio) * 4))
 #define S5P6440_GPIO_INPUT(__gpio)      (0x0 << ((__gpio) * 4))
 #define S5P6440_GPIO_OUTPUT(__gpio)     (0x1 << ((__gpio) * 4))
 
-/* Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit)
- * */
+/*
+ * Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit)
+ */
+
 #define S5P6440_GPIO2_CONMASK(__gpio)   (0x3 << ((__gpio) * 2))
 #define S5P6440_GPIO2_INPUT(__gpio)     (0x0 << ((__gpio) * 2))
 #define S5P6440_GPIO2_OUTPUT(__gpio)    (0x1 << ((__gpio) * 2))
diff --git a/arch/arm/mach-s5p6440/include/mach/regs-irq.h b/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
index a961f4beeb0c..4aaebdace55f 100644
--- a/arch/arm/mach-s5p6440/include/mach/regs-irq.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/regs-irq.h
+/* linux/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5P6440 - IRQ register definitions
+ * S5P64X0 - IRQ register definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h b/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
new file mode 100644
index 000000000000..ff85b4b6e8d9
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
@@ -0,0 +1,46 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Header file for s5p64x0 clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H __FILE__
+
+#include <linux/clk.h>
+
+extern struct clksrc_clk clk_mout_apll;
+extern struct clksrc_clk clk_mout_mpll;
+extern struct clksrc_clk clk_mout_epll;
+
+extern int s5p64x0_epll_enable(struct clk *clk, int enable);
+extern unsigned long s5p64x0_epll_get_rate(struct clk *clk);
+
+extern unsigned long s5p64x0_armclk_get_rate(struct clk *clk);
+extern unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate);
+extern int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate);
+
+extern struct clk_ops s5p64x0_clkarm_ops;
+
+extern struct clksrc_clk clk_armclk;
+extern struct clksrc_clk clk_dout_mpll;
+
+extern struct clk *clkset_hclk_low_list[];
+extern struct clksrc_sources clkset_hclk_low;
+
+extern int s5p64x0_pclk_ctrl(struct clk *clk, int enable);
+extern int s5p64x0_hclk0_ctrl(struct clk *clk, int enable);
+extern int s5p64x0_hclk1_ctrl(struct clk *clk, int enable);
+extern int s5p64x0_sclk_ctrl(struct clk *clk, int enable);
+extern int s5p64x0_sclk1_ctrl(struct clk *clk, int enable);
+extern int s5p64x0_mem_ctrl(struct clk *clk, int enable);
+
+extern int s5p64x0_clk48m_ctrl(struct clk *clk, int enable);
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h b/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h
new file mode 100644
index 000000000000..170a20a9643a
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h
@@ -0,0 +1,20 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_SPI_CLKS_H
+#define __ASM_ARCH_SPI_CLKS_H __FILE__
+
+#define S5P64X0_SPI_SRCCLK_PCLK         0
+#define S5P64X0_SPI_SRCCLK_SCLK         1
+
+#endif /* __ASM_ARCH_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/system.h b/arch/arm/mach-s5p64x0/include/mach/system.h
index a359ee3fa510..60f57532c970 100644
--- a/arch/arm/mach-s5p6440/include/mach/system.h
+++ b/arch/arm/mach-s5p64x0/include/mach/system.h
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/system.h
+/* linux/arch/arm/mach-s5p64x0/include/mach/system.h
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5P6440 - system support header
+ * S5P64X0 - system support header
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p6440/include/mach/tick.h b/arch/arm/mach-s5p64x0/include/mach/tick.h
index 2f25c7f07970..00aa7f1d8e51 100644
--- a/arch/arm/mach-s5p6440/include/mach/tick.h
+++ b/arch/arm/mach-s5p64x0/include/mach/tick.h
@@ -1,9 +1,14 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/tick.h
+/* linux/arch/arm/mach-s5p64x0/include/mach/tick.h
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5P6440 - Timer tick support definitions
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S5P64X0 - Timer tick support definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p6440/include/mach/timex.h b/arch/arm/mach-s5p64x0/include/mach/timex.h
index fb2e8cd40829..4b91faa195a8 100644
--- a/arch/arm/mach-s5p6440/include/mach/timex.h
+++ b/arch/arm/mach-s5p64x0/include/mach/timex.h
@@ -1,9 +1,12 @@
-/* arch/arm/mach-s3c64xx/include/mach/timex.h
+/* linux/arch/arm/mach-s5p64x0/include/mach/timex.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * Copyright (c) 2003-2005 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
  *
- * S3C6400 - time parameters
+ * S5P64X0 - time parameters
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
new file mode 100644
index 000000000000..c65b229aab23
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
@@ -0,0 +1,212 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/uncompress.h
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - uncompress code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include <mach/map.h>
+
+/*
+ * cannot use commonly <plat/uncompress.h>
+ * because uart base of S5P6440 and S5P6450 is different
+ */
+
+typedef unsigned int upf_t;     /* cannot include linux/serial_core.h */
+
+/* uart setup */
+
+static unsigned int fifo_mask;
+static unsigned int fifo_max;
+
+/* forward declerations */
+
+static void arch_detect_cpu(void);
+
+/* defines for UART registers */
+
+#include <plat/regs-serial.h>
+#include <plat/regs-watchdog.h>
+
+/* working in physical space... */
+#undef S3C2410_WDOGREG
+#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
+
+/* how many bytes we allow into the FIFO at a time in FIFO mode */
+#define FIFO_MAX         (14)
+
+static unsigned long uart_base;
+
+static __inline__ void get_uart_base(void)
+{
+        unsigned int chipid;
+
+        chipid = *(const volatile unsigned int __force *) 0xE0100118;
+
+        uart_base = S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT;
+
+        if ((chipid & 0xff000) == 0x50000)
+                uart_base += 0xEC800000;
+        else
+                uart_base += 0xEC000000;
+}
+
+static __inline__ void uart_wr(unsigned int reg, unsigned int val)
+{
+        volatile unsigned int *ptr;
+
+        get_uart_base();
+        ptr = (volatile unsigned int *)(reg + uart_base);
+        *ptr = val;
+}
+
+static __inline__ unsigned int uart_rd(unsigned int reg)
+{
+        volatile unsigned int *ptr;
+
+        get_uart_base();
+        ptr = (volatile unsigned int *)(reg + uart_base);
+        return *ptr;
+}
+
+/*
+ * we can deal with the case the UARTs are being run
+ * in FIFO mode, so that we don't hold up our execution
+ * waiting for tx to happen...
+ */
+
+static void putc(int ch)
+{
+        if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
+                int level;
+
+                while (1) {
+                        level = uart_rd(S3C2410_UFSTAT);
+                        level &= fifo_mask;
+
+                        if (level < fifo_max)
+                                break;
+                }
+
+        } else {
+                /* not using fifos */
+
+                while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
+                        barrier();
+        }
+
+        /* write byte to transmission register */
+        uart_wr(S3C2410_UTXH, ch);
+}
+
+static inline void flush(void)
+{
+}
+
+#define __raw_writel(d, ad)                     \
+        do {                                                    \
+                *((volatile unsigned int __force *)(ad)) = (d); \
+        } while (0)
+
+/*
+ * CONFIG_S3C_BOOT_WATCHDOG
+ *
+ * Simple boot-time watchdog setup, to reboot the system if there is
+ * any problem with the boot process
+ */
+
+#ifdef CONFIG_S3C_BOOT_WATCHDOG
+
+#define WDOG_COUNT (0xff00)
+
+static inline void arch_decomp_wdog(void)
+{
+        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
+}
+
+static void arch_decomp_wdog_start(void)
+{
+        __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
+        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
+        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
+}
+
+#else
+#define arch_decomp_wdog_start()
+#define arch_decomp_wdog()
+#endif
+
+#ifdef CONFIG_S3C_BOOT_ERROR_RESET
+
+static void arch_decomp_error(const char *x)
+{
+        putstr("\n\n");
+        putstr(x);
+        putstr("\n\n -- System resetting\n");
+
+        __raw_writel(0x4000, S3C2410_WTDAT);
+        __raw_writel(0x4000, S3C2410_WTCNT);
+        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
+
+        while(1);
+}
+
+#define arch_error arch_decomp_error
+#endif
+
+#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
+static inline void arch_enable_uart_fifo(void)
+{
+        u32 fifocon = uart_rd(S3C2410_UFCON);
+
+        if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
+                fifocon |= S3C2410_UFCON_RESETBOTH;
+                uart_wr(S3C2410_UFCON, fifocon);
+
+                /* wait for fifo reset to complete */
+                while (1) {
+                        fifocon = uart_rd(S3C2410_UFCON);
+                        if (!(fifocon & S3C2410_UFCON_RESETBOTH))
+                                break;
+                }
+        }
+}
+#else
+#define arch_enable_uart_fifo() do { } while(0)
+#endif
+
+static void arch_decomp_setup(void)
+{
+        /*
+         * we may need to setup the uart(s) here if we are not running
+         * on an BAST... the BAST will have left the uarts configured
+         * after calling linux.
+         */
+
+        arch_detect_cpu();
+        arch_decomp_wdog_start();
+
+        /*
+         * Enable the UART FIFOs if they where not enabled and our
+         * configuration says we should turn them on.
+         */
+
+        arch_enable_uart_fifo();
+}
+
+
+
+static void arch_detect_cpu(void)
+{
+        /* we do not need to do any cpu detection here at the moment. */
+}
+
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/vmalloc.h b/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
index e3f0eebf5205..97a9df38f1cf 100644
--- a/arch/arm/mach-s5p6440/include/mach/vmalloc.h
+++ b/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
@@ -1,4 +1,7 @@
-/* arch/arm/mach-s5p6440/include/mach/vmalloc.h
+/* linux/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
  *
diff --git a/arch/arm/mach-s5p64x0/init.c b/arch/arm/mach-s5p64x0/init.c
new file mode 100644
index 000000000000..79833caf8165
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/init.c
@@ -0,0 +1,73 @@
+/* linux/arch/arm/mach-s5p64x0/init.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - Init support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+
+#include <mach/map.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/s5p6440.h>
+#include <plat/s5p6450.h>
+#include <plat/regs-serial.h>
+
+static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = {
+        [0] = {
+                .name           = "pclk_low",
+                .divisor        = 1,
+                .min_baud       = 0,
+                .max_baud       = 0,
+        },
+        [1] = {
+                .name           = "uclk1",
+                .divisor        = 1,
+                .min_baud       = 0,
+                .max_baud       = 0,
+        },
+};
+
+/* uart registration process */
+
+void __init s5p64x0_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        struct s3c2410_uartcfg *tcfg = cfg;
+        u32 ucnt;
+
+        for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
+                if (!tcfg->clocks) {
+                        tcfg->clocks = s5p64x0_serial_clocks;
+                        tcfg->clocks_size = ARRAY_SIZE(s5p64x0_serial_clocks);
+                }
+        }
+}
+
+void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        int uart;
+
+        for (uart = 0; uart < no; uart++) {
+                s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
+                s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
+        }
+
+        s5p64x0_common_init_uarts(cfg, no);
+        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
+}
+
+void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        s5p64x0_common_init_uarts(cfg, no);
+        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
+}
diff --git a/arch/arm/mach-s5p6440/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 9202aaac3b56..28de0a57208c 100644
--- a/arch/arm/mach-s5p6440/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -1,7 +1,7 @@
-/* linux/arch/arm/mach-s5p6440/mach-smdk6440.c
+/* linux/arch/arm/mach-s5p64x0/mach-smdk6440.c
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -21,21 +21,22 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/clk.h>
+#include <linux/gpio.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
 
 #include <mach/hardware.h>
 #include <mach/map.h>
-
-#include <asm/irq.h>
-#include <asm/mach-types.h>
+#include <mach/regs-clock.h>
+#include <mach/i2c.h>
 
 #include <plat/regs-serial.h>
-
+#include <plat/gpio-cfg.h>
 #include <plat/s5p6440.h>
 #include <plat/clock.h>
-#include <mach/regs-clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/iic.h>
@@ -58,43 +59,60 @@
 
 static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
         [0] = {
-                .hwport      = 0,
-                .flags       = 0,
-                .ucon        = SMDK6440_UCON_DEFAULT,
-                .ulcon       = SMDK6440_ULCON_DEFAULT,
-                .ufcon       = SMDK6440_UFCON_DEFAULT,
+                .hwport         = 0,
+                .flags          = 0,
+                .ucon           = SMDK6440_UCON_DEFAULT,
+                .ulcon          = SMDK6440_ULCON_DEFAULT,
+                .ufcon          = SMDK6440_UFCON_DEFAULT,
         },
         [1] = {
-                .hwport      = 1,
-                .flags       = 0,
-                .ucon        = SMDK6440_UCON_DEFAULT,
-                .ulcon       = SMDK6440_ULCON_DEFAULT,
-                .ufcon       = SMDK6440_UFCON_DEFAULT,
+                .hwport         = 1,
+                .flags          = 0,
+                .ucon           = SMDK6440_UCON_DEFAULT,
+                .ulcon          = SMDK6440_ULCON_DEFAULT,
+                .ufcon          = SMDK6440_UFCON_DEFAULT,
         },
         [2] = {
-                .hwport      = 2,
-                .flags       = 0,
-                .ucon        = SMDK6440_UCON_DEFAULT,
-                .ulcon       = SMDK6440_ULCON_DEFAULT,
-                .ufcon       = SMDK6440_UFCON_DEFAULT,
+                .hwport         = 2,
+                .flags          = 0,
+                .ucon           = SMDK6440_UCON_DEFAULT,
+                .ulcon          = SMDK6440_ULCON_DEFAULT,
+                .ufcon          = SMDK6440_UFCON_DEFAULT,
         },
         [3] = {
-                .hwport      = 3,
-                .flags       = 0,
-                .ucon        = SMDK6440_UCON_DEFAULT,
-                .ulcon       = SMDK6440_ULCON_DEFAULT,
-                .ufcon       = SMDK6440_UFCON_DEFAULT,
+                .hwport         = 3,
+                .flags          = 0,
+                .ucon           = SMDK6440_UCON_DEFAULT,
+                .ulcon          = SMDK6440_ULCON_DEFAULT,
+                .ufcon          = SMDK6440_UFCON_DEFAULT,
         },
 };
 
 static struct platform_device *smdk6440_devices[] __initdata = {
-        &s5p6440_device_iis,
         &s3c_device_adc,
         &s3c_device_rtc,
         &s3c_device_i2c0,
         &s3c_device_i2c1,
         &s3c_device_ts,
         &s3c_device_wdt,
+        &s5p6440_device_iis,
+};
+
+static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
+        .flags          = 0,
+        .slave_addr     = 0x10,
+        .frequency      = 100*1000,
+        .sda_delay      = 100,
+        .cfg_gpio       = s5p6440_i2c0_cfg_gpio,
+};
+
+static struct s3c2410_platform_i2c s5p6440_i2c1_data __initdata = {
+        .flags          = 0,
+        .bus_num        = 1,
+        .slave_addr     = 0x10,
+        .frequency      = 100*1000,
+        .sda_delay      = 100,
+        .cfg_gpio       = s5p6440_i2c1_cfg_gpio,
 };
 
 static struct i2c_board_info smdk6440_i2c_devs0[] __initdata = {
@@ -113,7 +131,7 @@ static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
 
 static void __init smdk6440_map_io(void)
 {
-        s5p_init_io(NULL, 0, S5P_SYS_ID);
+        s5p_init_io(NULL, 0, S5P64X0_SYS_ID);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs));
 }
@@ -122,9 +140,8 @@ static void __init smdk6440_machine_init(void)
 {
         s3c24xx_ts_set_platdata(&s3c_ts_platform);
 
-        /* I2C */
-        s3c_i2c0_set_platdata(NULL);
-        s3c_i2c1_set_platdata(NULL);
+        s3c_i2c0_set_platdata(&s5p6440_i2c0_data);
+        s3c_i2c1_set_platdata(&s5p6440_i2c1_data);
         i2c_register_board_info(0, smdk6440_i2c_devs0,
                         ARRAY_SIZE(smdk6440_i2c_devs0));
         i2c_register_board_info(1, smdk6440_i2c_devs1,
@@ -135,9 +152,9 @@ static void __init smdk6440_machine_init(void)
 
 MACHINE_START(SMDK6440, "SMDK6440")
         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .phys_io        = S3C_PA_UART & 0xfff00000,
+        .phys_io        = S5P6440_PA_UART(0) & 0xfff00000,
         .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
-        .boot_params    = S5P_PA_SDRAM + 0x100,
+        .boot_params    = S5P64X0_PA_SDRAM + 0x100,
 
         .init_irq       = s5p6440_init_irq,
         .map_io         = smdk6440_map_io,
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
new file mode 100644
index 000000000000..8e982171418b
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -0,0 +1,182 @@
+/* linux/arch/arm/mach-s5p64x0/mach-smdk6450.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/gpio.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/i2c.h>
+
+#include <plat/regs-serial.h>
+#include <plat/gpio-cfg.h>
+#include <plat/s5p6450.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/iic.h>
+#include <plat/pll.h>
+#include <plat/adc.h>
+#include <plat/ts.h>
+
+#define SMDK6450_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
+                                S3C2410_UCON_RXILEVEL |         \
+                                S3C2410_UCON_TXIRQMODE |        \
+                                S3C2410_UCON_RXIRQMODE |        \
+                                S3C2410_UCON_RXFIFO_TOI |       \
+                                S3C2443_UCON_RXERR_IRQEN)
+
+#define SMDK6450_ULCON_DEFAULT  S3C2410_LCON_CS8
+
+#define SMDK6450_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
+                                S3C2440_UFCON_TXTRIG16 |        \
+                                S3C2410_UFCON_RXTRIG8)
+
+static struct s3c2410_uartcfg smdk6450_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport         = 0,
+                .flags          = 0,
+                .ucon           = SMDK6450_UCON_DEFAULT,
+                .ulcon          = SMDK6450_ULCON_DEFAULT,
+                .ufcon          = SMDK6450_UFCON_DEFAULT,
+        },
+        [1] = {
+                .hwport         = 1,
+                .flags          = 0,
+                .ucon           = SMDK6450_UCON_DEFAULT,
+                .ulcon          = SMDK6450_ULCON_DEFAULT,
+                .ufcon          = SMDK6450_UFCON_DEFAULT,
+        },
+        [2] = {
+                .hwport         = 2,
+                .flags          = 0,
+                .ucon           = SMDK6450_UCON_DEFAULT,
+                .ulcon          = SMDK6450_ULCON_DEFAULT,
+                .ufcon          = SMDK6450_UFCON_DEFAULT,
+        },
+        [3] = {
+                .hwport         = 3,
+                .flags          = 0,
+                .ucon           = SMDK6450_UCON_DEFAULT,
+                .ulcon          = SMDK6450_ULCON_DEFAULT,
+                .ufcon          = SMDK6450_UFCON_DEFAULT,
+        },
+#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
+        [4] = {
+                .hwport         = 4,
+                .flags          = 0,
+                .ucon           = SMDK6450_UCON_DEFAULT,
+                .ulcon          = SMDK6450_ULCON_DEFAULT,
+                .ufcon          = SMDK6450_UFCON_DEFAULT,
+        },
+#endif
+#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
+        [5] = {
+                .hwport         = 5,
+                .flags          = 0,
+                .ucon           = SMDK6450_UCON_DEFAULT,
+                .ulcon          = SMDK6450_ULCON_DEFAULT,
+                .ufcon          = SMDK6450_UFCON_DEFAULT,
+        },
+#endif
+};
+
+static struct platform_device *smdk6450_devices[] __initdata = {
+        &s3c_device_adc,
+        &s3c_device_rtc,
+        &s3c_device_i2c0,
+        &s3c_device_i2c1,
+        &s3c_device_ts,
+        &s3c_device_wdt,
+        &s5p6450_device_iis0,
+        /* s5p6450_device_spi0 will be added */
+};
+
+static struct s3c2410_platform_i2c s5p6450_i2c0_data __initdata = {
+        .flags          = 0,
+        .slave_addr     = 0x10,
+        .frequency      = 100*1000,
+        .sda_delay      = 100,
+        .cfg_gpio       = s5p6450_i2c0_cfg_gpio,
+};
+
+static struct s3c2410_platform_i2c s5p6450_i2c1_data __initdata = {
+        .flags          = 0,
+        .bus_num        = 1,
+        .slave_addr     = 0x10,
+        .frequency      = 100*1000,
+        .sda_delay      = 100,
+        .cfg_gpio       = s5p6450_i2c1_cfg_gpio,
+};
+
+static struct i2c_board_info smdk6450_i2c_devs0[] __initdata = {
+        { I2C_BOARD_INFO("24c08", 0x50), },     /* Samsung KS24C080C EEPROM */
+};
+
+static struct i2c_board_info smdk6450_i2c_devs1[] __initdata = {
+        { I2C_BOARD_INFO("24c128", 0x57), },/* Samsung S524AD0XD1 EEPROM */
+};
+
+static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
+        .delay                  = 10000,
+        .presc                  = 49,
+        .oversampling_shift     = 2,
+};
+
+static void __init smdk6450_map_io(void)
+{
+        s5p_init_io(NULL, 0, S5P64X0_SYS_ID);
+        s3c24xx_init_clocks(19200000);
+        s3c24xx_init_uarts(smdk6450_uartcfgs, ARRAY_SIZE(smdk6450_uartcfgs));
+}
+
+static void __init smdk6450_machine_init(void)
+{
+        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+
+        s3c_i2c0_set_platdata(&s5p6450_i2c0_data);
+        s3c_i2c1_set_platdata(&s5p6450_i2c1_data);
+        i2c_register_board_info(0, smdk6450_i2c_devs0,
+                        ARRAY_SIZE(smdk6450_i2c_devs0));
+        i2c_register_board_info(1, smdk6450_i2c_devs1,
+                        ARRAY_SIZE(smdk6450_i2c_devs1));
+
+        platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
+}
+
+MACHINE_START(SMDK6450, "SMDK6450")
+        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+        .phys_io        = S5P6450_PA_UART(0) & 0xfff00000,
+        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S5P64X0_PA_SDRAM + 0x100,
+
+        .init_irq       = s5p6450_init_irq,
+        .map_io         = smdk6450_map_io,
+        .init_machine   = smdk6450_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s5p6440/setup-i2c0.c b/arch/arm/mach-s5p64x0/setup-i2c0.c
index 2c99d14f7ac7..dc4cc65a5019 100644
--- a/arch/arm/mach-s5p6440/setup-i2c0.c
+++ b/arch/arm/mach-s5p64x0/setup-i2c0.c
@@ -1,11 +1,11 @@
-/* linux/arch/arm/mach-s5p6440/setup-i2c0.c
+/* linux/arch/arm/mach-s5p64x0/setup-i2c0.c
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * I2C0 GPIO configuration.
  *
- * Based on plat-s3c64xx/setup-i2c0.c
+ * Based on plat-s3c64x0/setup-i2c0.c
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -14,17 +14,29 @@
 
 #include <linux/kernel.h>
 #include <linux/types.h>
+#include <linux/gpio.h>
 
 struct platform_device; /* don't need the contents */
 
-#include <linux/gpio.h>
 #include <plat/gpio-cfg.h>
 #include <plat/iic.h>
 
-void s3c_i2c0_cfg_gpio(struct platform_device *dev)
+#include <mach/i2c.h>
+
+void s5p6440_i2c0_cfg_gpio(struct platform_device *dev)
 {
         s3c_gpio_cfgpin(S5P6440_GPB(5), S3C_GPIO_SFN(2));
         s3c_gpio_setpull(S5P6440_GPB(5), S3C_GPIO_PULL_UP);
         s3c_gpio_cfgpin(S5P6440_GPB(6), S3C_GPIO_SFN(2));
         s3c_gpio_setpull(S5P6440_GPB(6), S3C_GPIO_PULL_UP);
 }
+
+void s5p6450_i2c0_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(S5P6450_GPB(5), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5P6450_GPB(5), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5P6450_GPB(6), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5P6450_GPB(6), S3C_GPIO_PULL_UP);
+}
+
+void s3c_i2c0_cfg_gpio(struct platform_device *dev) { }
diff --git a/arch/arm/mach-s5p6440/setup-i2c1.c b/arch/arm/mach-s5p64x0/setup-i2c1.c
index 9a1537f786e0..2edd7912f8e4 100644
--- a/arch/arm/mach-s5p6440/setup-i2c1.c
+++ b/arch/arm/mach-s5p64x0/setup-i2c1.c
@@ -1,7 +1,7 @@
-/* linux/arch/arm/mach-s5p6440/setup-i2c1.c
+/* linux/arch/arm/mach-s5p64xx/setup-i2c1.c
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * I2C1 GPIO configuration.
  *
@@ -21,10 +21,22 @@ struct platform_device; /* don't need the contents */
 #include <plat/gpio-cfg.h>
 #include <plat/iic.h>
 
-void s3c_i2c1_cfg_gpio(struct platform_device *dev)
+#include <mach/i2c.h>
+
+void s5p6440_i2c1_cfg_gpio(struct platform_device *dev)
 {
         s3c_gpio_cfgpin(S5P6440_GPR(9), S3C_GPIO_SFN(6));
         s3c_gpio_setpull(S5P6440_GPR(9), S3C_GPIO_PULL_UP);
         s3c_gpio_cfgpin(S5P6440_GPR(10), S3C_GPIO_SFN(6));
         s3c_gpio_setpull(S5P6440_GPR(10), S3C_GPIO_PULL_UP);
 }
+
+void s5p6450_i2c1_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(S5P6450_GPR(9), S3C_GPIO_SFN(6));
+        s3c_gpio_setpull(S5P6450_GPR(9), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5P6450_GPR(10), S3C_GPIO_SFN(6));
+        s3c_gpio_setpull(S5P6450_GPR(10), S3C_GPIO_PULL_UP);
+}
+
+void s3c_i2c1_cfg_gpio(struct platform_device *dev) { }
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c
index 251c92ac5b22..fd2708e7d8a9 100644
--- a/arch/arm/mach-s5pc100/cpu.c
+++ b/arch/arm/mach-s5pc100/cpu.c
@@ -1,5 +1,8 @@
 /* linux/arch/arm/mach-s5pc100/cpu.c
  *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
  *
@@ -21,6 +24,7 @@
 #include <linux/sysdev.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/sched.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -56,11 +60,31 @@ static struct map_desc s5pc100_iodesc[] __initdata = {
                 .length         = SZ_16K,
                 .type           = MT_DEVICE,
         }, {
+                .virtual        = (unsigned long)S5P_VA_GPIO,
+                .pfn            = __phys_to_pfn(S5PC100_PA_GPIO),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC0,
+                .pfn            = __phys_to_pfn(S5PC100_PA_VIC0),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC1,
+                .pfn            = __phys_to_pfn(S5PC100_PA_VIC1),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = (unsigned long)VA_VIC2,
-                .pfn            = __phys_to_pfn(S5P_PA_VIC2),
+                .pfn            = __phys_to_pfn(S5PC100_PA_VIC2),
                 .length         = SZ_16K,
                 .type           = MT_DEVICE,
         }, {
+                .virtual        = (unsigned long)S3C_VA_UART,
+                .pfn            = __phys_to_pfn(S3C_PA_UART),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = (unsigned long)S5PC100_VA_OTHERS,
                 .pfn            = __phys_to_pfn(S5PC100_PA_OTHERS),
                 .length         = SZ_4K,
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 01b9134feff0..8751ef4a6804 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -44,19 +44,16 @@
 #define S5PC100_PA_OTHERS       (0xE0200000)
 #define S5PC100_VA_OTHERS       (S3C_VA_SYS + 0x10000)
 
-#define S5P_PA_GPIO             (0xE0300000)
+#define S5PC100_PA_GPIO         (0xE0300000)
 #define S5PC1XX_VA_GPIO         S3C_ADDR(0x00500000)
 
 /* Interrupt */
-#define S5PC100_PA_VIC          (0xE4000000)
+#define S5PC100_PA_VIC0         (0xE4000000)
+#define S5PC100_PA_VIC1         (0xE4100000)
+#define S5PC100_PA_VIC2         (0xE4200000)
 #define S5PC100_VA_VIC          S3C_VA_IRQ
-#define S5PC100_PA_VIC_OFFSET   0x100000
 #define S5PC100_VA_VIC_OFFSET   0x10000
-#define S5PC1XX_PA_VIC(x)       (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
 #define S5PC1XX_VA_VIC(x)       (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
-#define S5P_PA_VIC0             S5PC1XX_PA_VIC(0)
-#define S5P_PA_VIC1             S5PC1XX_PA_VIC(1)
-#define S5P_PA_VIC2             S5PC1XX_PA_VIC(2)
 
 
 #define S5PC100_PA_ONENAND      (0xE7100000)
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index d3a38955c741..5315fec3db86 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -53,11 +53,6 @@ config S5PV210_SETUP_SDHCI_GPIO
         help
           Common setup code for SDHCI gpio.
 
-config S5PC110_DEV_ONENAND
-        bool
-        help
-          Compile in platform device definition for OneNAND1 controller
-
 menu "S5PC110 Machines"
 
 config MACH_AQUILA
@@ -71,7 +66,7 @@ config MACH_AQUILA
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC1
         select S3C_DEV_HSMMC2
-        select S5PC110_DEV_ONENAND
+        select S5P_DEV_ONENAND
         select S5PV210_SETUP_FB_24BPP
         select S5PV210_SETUP_SDHCI
         help
@@ -88,7 +83,7 @@ config MACH_GONI
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC1
         select S3C_DEV_HSMMC2
-        select S5PC110_DEV_ONENAND
+        select S5P_DEV_ONENAND
         select S5PV210_SETUP_FB_24BPP
         select S5PV210_SETUP_SDHCI
         help
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 05048c5aa4c6..704548912408 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -26,7 +26,6 @@ obj-$(CONFIG_MACH_GONI)		+= mach-goni.o
 
 obj-y                           += dev-audio.o
 obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
-obj-$(CONFIG_S5PC110_DEV_ONENAND) += dev-onenand.o
 
 obj-$(CONFIG_S5PV210_SETUP_FB_24BPP)    += setup-fb-24bpp.o
 obj-$(CONFIG_S5PV210_SETUP_I2C1)        += setup-i2c1.o
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index af91fefef2c6..d562670e1b0b 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -173,11 +173,6 @@ static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
         return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
 }
 
-static int s5pv210_clk_ip4_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP4, clk, enable);
-}
-
 static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
@@ -281,6 +276,24 @@ static struct clk init_clocks_disable[] = {
                 .enable         = s5pv210_clk_ip0_ctrl,
                 .ctrlbit        = (1<<29),
         }, {
+                .name           = "fimc",
+                .id             = 0,
+                .parent         = &clk_hclk_dsys.clk,
+                .enable         = s5pv210_clk_ip0_ctrl,
+                .ctrlbit        = (1 << 24),
+        }, {
+                .name           = "fimc",
+                .id             = 1,
+                .parent         = &clk_hclk_dsys.clk,
+                .enable         = s5pv210_clk_ip0_ctrl,
+                .ctrlbit        = (1 << 25),
+        }, {
+                .name           = "fimc",
+                .id             = 2,
+                .parent         = &clk_hclk_dsys.clk,
+                .enable         = s5pv210_clk_ip0_ctrl,
+                .ctrlbit        = (1 << 26),
+        }, {
                 .name           = "otg",
                 .id             = -1,
                 .parent         = &clk_hclk_psys.clk,
@@ -357,7 +370,7 @@ static struct clk init_clocks_disable[] = {
                 .id             = 1,
                 .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
-                .ctrlbit        = (1<<8),
+                .ctrlbit        = (1 << 10),
         }, {
                 .name           = "i2c",
                 .id             = 2,
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index b9f4d677cf55..2f16bfc0a116 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -1,7 +1,7 @@
 /* linux/arch/arm/mach-s5pv210/cpu.c
  *
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ *              http://www.samsung.com
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -19,6 +19,7 @@
 #include <linux/io.h>
 #include <linux/sysdev.h>
 #include <linux/platform_device.h>
+#include <linux/sched.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -47,7 +48,22 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
         {
                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
                 .pfn            = __phys_to_pfn(S5PV210_PA_SYSTIMER),
-                .length         = SZ_1M,
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_GPIO,
+                .pfn            = __phys_to_pfn(S5PV210_PA_GPIO),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC0,
+                .pfn            = __phys_to_pfn(S5PV210_PA_VIC0),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC1,
+                .pfn            = __phys_to_pfn(S5PV210_PA_VIC1),
+                .length         = SZ_16K,
                 .type           = MT_DEVICE,
         }, {
                 .virtual        = (unsigned long)VA_VIC2,
@@ -60,6 +76,11 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
                 .length         = SZ_16K,
                 .type           = MT_DEVICE,
         }, {
+                .virtual        = (unsigned long)S3C_VA_UART,
+                .pfn            = __phys_to_pfn(S3C_PA_UART),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = (unsigned long)S5P_VA_SROMC,
                 .pfn            = __phys_to_pfn(S5PV210_PA_SROMC),
                 .length         = SZ_4K,
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index dd4fb6bf14b5..bd9afd52466a 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -17,7 +17,10 @@
 #include <plat/map-s5p.h>
 
 #define S5PC110_PA_ONENAND      (0xB0000000)
+#define S5P_PA_ONENAND          S5PC110_PA_ONENAND
+
 #define S5PC110_PA_ONENAND_DMA  (0xB0600000)
+#define S5P_PA_ONENAND_DMA      S5PC110_PA_ONENAND_DMA
 
 #define S5PV210_PA_CHIPID       (0xE0000000)
 #define S5P_PA_CHIPID           S5PV210_PA_CHIPID
@@ -26,7 +29,6 @@
 #define S5P_PA_SYSCON           S5PV210_PA_SYSCON
 
 #define S5PV210_PA_GPIO         (0xE0200000)
-#define S5P_PA_GPIO             S5PV210_PA_GPIO
 
 /* SPI */
 #define S5PV210_PA_SPI0         0xE1300000
@@ -72,16 +74,9 @@
 #define S5PV210_PA_HSMMC(x)     (0xEB000000 + ((x) * 0x100000))
 
 #define S5PV210_PA_VIC0         (0xF2000000)
-#define S5P_PA_VIC0             S5PV210_PA_VIC0
-
 #define S5PV210_PA_VIC1         (0xF2100000)
-#define S5P_PA_VIC1             S5PV210_PA_VIC1
-
 #define S5PV210_PA_VIC2         (0xF2200000)
-#define S5P_PA_VIC2             S5PV210_PA_VIC2
-
 #define S5PV210_PA_VIC3         (0xF2300000)
-#define S5P_PA_VIC3             S5PV210_PA_VIC3
 
 #define S5PV210_PA_SDRAM        (0x20000000)
 #define S5P_PA_SDRAM            S5PV210_PA_SDRAM
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 0dda8012d6b2..bf772de6b0c3 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -477,7 +477,7 @@ static struct platform_device *aquila_devices[] __initdata = {
         &aquila_i2c_gpio_pmic,
         &aquila_device_gpiokeys,
         &s3c_device_fb,
-        &s5pc110_device_onenand,
+        &s5p_device_onenand,
         &s3c_device_hsmmc0,
         &s3c_device_hsmmc1,
         &s3c_device_hsmmc2,
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 53754d7d364e..fdc5cca4eb41 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -456,7 +456,7 @@ static void goni_setup_sdhci(void)
 
 static struct platform_device *goni_devices[] __initdata = {
         &s3c_device_fb,
-        &s5pc110_device_onenand,
+        &s5p_device_onenand,
         &goni_i2c_gpio_pmic,
         &goni_device_gpiokeys,
         &s5p_device_fimc0,
diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c
index e5b261a99ab2..4add39853ff9 100644
--- a/arch/arm/mach-s5pv310/cpu.c
+++ b/arch/arm/mach-s5pv310/cpu.c
@@ -31,9 +31,14 @@ extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
 /* Initial IO mappings */
 static struct map_desc s5pv310_iodesc[] __initdata = {
         {
-                .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
-                .pfn            = __phys_to_pfn(S5PV310_PA_COREPERI),
-                .length         = SZ_8K,
+                .virtual        = (unsigned long)S5P_VA_SYSRAM,
+                .pfn            = __phys_to_pfn(S5PV310_PA_SYSRAM),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_CMU,
+                .pfn            = __phys_to_pfn(S5PV310_PA_CMU),
+                .length         = SZ_128K,
                 .type           = MT_DEVICE,
         }, {
                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
@@ -41,19 +46,24 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
+                .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
+                .pfn            = __phys_to_pfn(S5PV310_PA_COREPERI),
+                .length         = SZ_8K,
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = (unsigned long)S5P_VA_L2CC,
                 .pfn            = __phys_to_pfn(S5PV310_PA_L2CC),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = (unsigned long)S5P_VA_SYSRAM,
-                .pfn            = __phys_to_pfn(S5PV310_PA_SYSRAM),
+                .virtual        = (unsigned long)S5P_VA_GPIO,
+                .pfn            = __phys_to_pfn(S5PV310_PA_GPIO1),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = (unsigned long)S5P_VA_CMU,
-                .pfn            = __phys_to_pfn(S5PV310_PA_CMU),
-                .length         = SZ_128K,
+                .virtual        = (unsigned long)S3C_VA_UART,
+                .pfn            = __phys_to_pfn(S3C_PA_UART),
+                .length         = SZ_512K,
                 .type           = MT_DEVICE,
         },
 };
diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h
index 4cdedda6e652..471fc3bb199a 100644
--- a/arch/arm/mach-s5pv310/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv310/include/mach/irqs.h
@@ -68,6 +68,8 @@
 
 #define IRQ_IIC                 COMBINER_IRQ(27, 0)
 
+#define IRQ_ONENAND_AUDI        COMBINER_IRQ(34, 0)
+
 /* Set the default NR_IRQS */
 
 #define NR_IRQS                 COMBINER_IRQ(MAX_COMBINER_NR, 0)
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
index 213e1101a3b3..aff6d23624bb 100644
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ b/arch/arm/mach-s5pv310/include/mach/map.h
@@ -25,6 +25,12 @@
 
 #define S5PV310_PA_SYSRAM               (0x02025000)
 
+#define S5PC210_PA_ONENAND              (0x0C000000)
+#define S5P_PA_ONENAND                  S5PC210_PA_ONENAND
+
+#define S5PC210_PA_ONENAND_DMA          (0x0C600000)
+#define S5P_PA_ONENAND_DMA              S5PC210_PA_ONENAND_DMA
+
 #define S5PV310_PA_CHIPID               (0x10000000)
 #define S5P_PA_CHIPID                   S5PV310_PA_CHIPID
 
@@ -46,7 +52,6 @@
 #define S5PV310_PA_GPIO1                (0x11400000)
 #define S5PV310_PA_GPIO2                (0x11000000)
 #define S5PV310_PA_GPIO3                (0x03860000)
-#define S5P_PA_GPIO                     S5PV310_PA_GPIO1
 
 #define S5PV310_PA_HSMMC(x)             (0x12510000 + ((x) * 0x10000))
 
diff --git a/arch/arm/mach-shark/include/mach/vmalloc.h b/arch/arm/mach-shark/include/mach/vmalloc.h
index f6c6837c5451..8e845b6a7cb5 100644
--- a/arch/arm/mach-shark/include/mach/vmalloc.h
+++ b/arch/arm/mach-shark/include/mach/vmalloc.h
@@ -1,4 +1,4 @@
 /*
  * arch/arm/mach-shark/include/mach/vmalloc.h
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END       0xd0000000
diff --git a/arch/arm/mach-tcc8k/Kconfig b/arch/arm/mach-tcc8k/Kconfig
new file mode 100644
index 000000000000..ad86415d1577
--- /dev/null
+++ b/arch/arm/mach-tcc8k/Kconfig
@@ -0,0 +1,11 @@
+if ARCH_TCC8K
+
+comment "TCC8000 systems:"
+
+config MACH_TCC8000_SDK
+        bool "Telechips TCC8000-SDK development kit"
+        default y
+        help
+          Support for the Telechips TCC8000-SDK board.
+
+endif
diff --git a/arch/arm/mach-tcc8k/Makefile b/arch/arm/mach-tcc8k/Makefile
new file mode 100644
index 000000000000..9bacf31e49ba
--- /dev/null
+++ b/arch/arm/mach-tcc8k/Makefile
@@ -0,0 +1,9 @@
+#
+# Makefile for TCC8K boards and common files.
+#
+
+# Common support
+obj-y += clock.o irq.o time.o io.o devices.o
+
+# Board specific support
+obj-$(CONFIG_MACH_TCC8000_SDK) += board-tcc8000-sdk.o
diff --git a/arch/arm/mach-tcc8k/Makefile.boot b/arch/arm/mach-tcc8k/Makefile.boot
new file mode 100644
index 000000000000..f135c9deae10
--- /dev/null
+++ b/arch/arm/mach-tcc8k/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y           := 0x20008000
+params_phys-y           := 0x20000100
+initrd_phys-y           := 0x20800000
diff --git a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
new file mode 100644
index 000000000000..4e42555b2009
--- /dev/null
+++ b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-types.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+
+#include <mach/clock.h>
+
+#include "common.h"
+
+#define XI_FREQUENCY    12000000
+#define XTI_FREQUENCY   32768
+
+#ifdef CONFIG_MTD_NAND_TCC
+/* NAND */
+static struct tcc_nand_platform_data tcc8k_sdk_nand_data = {
+        .width = 1,
+        .hw_ecc = 0,
+};
+#endif
+
+static void __init tcc8k_init(void)
+{
+#ifdef CONFIG_MTD_NAND_TCC
+        tcc_nand_device.dev.platform_data = &tcc8k_sdk_nand_data;
+        platform_device_register(&tcc_nand_device);
+#endif
+}
+
+static void __init tcc8k_init_timer(void)
+{
+        tcc_clocks_init(XI_FREQUENCY, XTI_FREQUENCY);
+}
+
+static struct sys_timer tcc8k_timer = {
+        .init   = tcc8k_init_timer,
+};
+
+static void __init tcc8k_map_io(void)
+{
+        tcc8k_map_common_io();
+}
+
+MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board")
+        .phys_io        = 0x90000000,
+        .io_pg_offst    = ((0xf1000000) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x00000100,
+        .map_io         = tcc8k_map_io,
+        .init_irq       = tcc8k_init_irq,
+        .init_machine   = tcc8k_init,
+        .timer          = &tcc8k_timer,
+MACHINE_END
diff --git a/arch/arm/mach-tcc8k/clock.c b/arch/arm/mach-tcc8k/clock.c
new file mode 100644
index 000000000000..ba32a15127ab
--- /dev/null
+++ b/arch/arm/mach-tcc8k/clock.c
@@ -0,0 +1,567 @@
+/*
+ * Lowlevel clock handling for Telechips TCC8xxx SoCs
+ *
+ * Copyright (C) 2010 by Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GPL v2
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+
+#include <asm/clkdev.h>
+
+#include <mach/clock.h>
+#include <mach/irqs.h>
+#include <mach/tcc8k-regs.h>
+
+#include "common.h"
+
+#define BCLKCTR0        (CKC_BASE + BCLKCTR0_OFFS)
+#define BCLKCTR1        (CKC_BASE + BCLKCTR1_OFFS)
+
+#define ACLKREF         (CKC_BASE + ACLKREF_OFFS)
+#define ACLKUART0       (CKC_BASE + ACLKUART0_OFFS)
+#define ACLKUART1       (CKC_BASE + ACLKUART1_OFFS)
+#define ACLKUART2       (CKC_BASE + ACLKUART2_OFFS)
+#define ACLKUART3       (CKC_BASE + ACLKUART3_OFFS)
+#define ACLKUART4       (CKC_BASE + ACLKUART4_OFFS)
+#define ACLKI2C         (CKC_BASE + ACLKI2C_OFFS)
+#define ACLKADC         (CKC_BASE + ACLKADC_OFFS)
+#define ACLKUSBH        (CKC_BASE + ACLKUSBH_OFFS)
+#define ACLKLCD         (CKC_BASE + ACLKLCD_OFFS)
+#define ACLKSDH0        (CKC_BASE + ACLKSDH0_OFFS)
+#define ACLKSDH1        (CKC_BASE + ACLKSDH1_OFFS)
+#define ACLKSPI0        (CKC_BASE + ACLKSPI0_OFFS)
+#define ACLKSPI1        (CKC_BASE + ACLKSPI1_OFFS)
+#define ACLKSPDIF       (CKC_BASE + ACLKSPDIF_OFFS)
+#define ACLKC3DEC       (CKC_BASE + ACLKC3DEC_OFFS)
+#define ACLKCAN0        (CKC_BASE + ACLKCAN0_OFFS)
+#define ACLKCAN1        (CKC_BASE + ACLKCAN1_OFFS)
+#define ACLKGSB0        (CKC_BASE + ACLKGSB0_OFFS)
+#define ACLKGSB1        (CKC_BASE + ACLKGSB1_OFFS)
+#define ACLKGSB2        (CKC_BASE + ACLKGSB2_OFFS)
+#define ACLKGSB3        (CKC_BASE + ACLKGSB3_OFFS)
+#define ACLKUSBH        (CKC_BASE + ACLKUSBH_OFFS)
+#define ACLKTCT         (CKC_BASE + ACLKTCT_OFFS)
+#define ACLKTCX         (CKC_BASE + ACLKTCX_OFFS)
+#define ACLKTCZ         (CKC_BASE + ACLKTCZ_OFFS)
+
+/* Crystal frequencies */
+static unsigned long xi_rate, xti_rate;
+
+static void __iomem *pll_cfg_addr(int pll)
+{
+        switch (pll) {
+        case 0: return (CKC_BASE + PLL0CFG_OFFS);
+        case 1: return (CKC_BASE + PLL1CFG_OFFS);
+        case 2: return (CKC_BASE + PLL2CFG_OFFS);
+        default:
+                BUG();
+        }
+}
+
+static int pll_enable(int pll, int enable)
+{
+        u32 reg;
+        void __iomem *addr = pll_cfg_addr(pll);
+
+        reg = __raw_readl(addr);
+        if (enable)
+                reg &= ~PLLxCFG_PD;
+        else
+                reg |= PLLxCFG_PD;
+
+        __raw_writel(reg, addr);
+        return 0;
+}
+
+static int xi_enable(int enable)
+{
+        u32 reg;
+
+        reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
+        if (enable)
+                reg |= CLKCTRL_XE;
+        else
+                reg &= ~CLKCTRL_XE;
+
+        __raw_writel(reg, CKC_BASE + CLKCTRL_OFFS);
+        return 0;
+}
+
+static int root_clk_enable(enum root_clks src)
+{
+        switch (src) {
+        case CLK_SRC_PLL0: return pll_enable(0, 1);
+        case CLK_SRC_PLL1: return pll_enable(1, 1);
+        case CLK_SRC_PLL2: return pll_enable(2, 1);
+        case CLK_SRC_XI: return xi_enable(1);
+        default:
+                BUG();
+        }
+        return 0;
+}
+
+static int root_clk_disable(enum root_clks root_src)
+{
+        switch (root_src) {
+        case CLK_SRC_PLL0: return pll_enable(0, 0);
+        case CLK_SRC_PLL1: return pll_enable(1, 0);
+        case CLK_SRC_PLL2: return pll_enable(2, 0);
+        case CLK_SRC_XI: return xi_enable(0);
+        default:
+                BUG();
+        }
+        return 0;
+}
+
+static int enable_clk(struct clk *clk)
+{
+        u32 reg;
+
+        if (clk->root_id != CLK_SRC_NOROOT)
+                return root_clk_enable(clk->root_id);
+
+        if (clk->aclkreg) {
+                reg = __raw_readl(clk->aclkreg);
+                reg |= ACLK_EN;
+                __raw_writel(reg, clk->aclkreg);
+        }
+        if (clk->bclkctr) {
+                reg = __raw_readl(clk->bclkctr);
+                reg |= 1 << clk->bclk_shift;
+                __raw_writel(reg, clk->bclkctr);
+        }
+        return 0;
+}
+
+static void disable_clk(struct clk *clk)
+{
+        u32 reg;
+
+        if (clk->root_id != CLK_SRC_NOROOT) {
+                root_clk_disable(clk->root_id);
+                return;
+        }
+
+        if (clk->bclkctr) {
+                reg = __raw_readl(clk->bclkctr);
+                reg &= ~(1 << clk->bclk_shift);
+                __raw_writel(reg, clk->bclkctr);
+        }
+        if (clk->aclkreg) {
+                reg = __raw_readl(clk->aclkreg);
+                reg &= ~ACLK_EN;
+                __raw_writel(reg, clk->aclkreg);
+        }
+}
+
+static unsigned long get_rate_pll(int pll)
+{
+        u32 reg;
+        unsigned long s, m, p;
+        void __iomem *addr = pll_cfg_addr(pll);
+
+        reg = __raw_readl(addr);
+        s = (reg >> 16) & 0x07;
+        m = (reg >> 8) & 0xff;
+        p = reg & 0x3f;
+
+        return (m * xi_rate) / (p * (1 << s));
+}
+
+static unsigned long get_rate_pll_div(int pll)
+{
+        u32 reg;
+        unsigned long div = 0;
+        void __iomem *addr;
+
+        switch (pll) {
+        case 0:
+                addr = CKC_BASE + CLKDIVC0_OFFS;
+                reg = __raw_readl(addr);
+                if (reg & CLKDIVC0_P0E)
+                        div = (reg >> 24) & 0x3f;
+                break;
+        case 1:
+                addr = CKC_BASE + CLKDIVC0_OFFS;
+                reg = __raw_readl(addr);
+                if (reg & CLKDIVC0_P1E)
+                        div = (reg >> 16) & 0x3f;
+                break;
+        case 2:
+                addr = CKC_BASE + CLKDIVC1_OFFS;
+                reg = __raw_readl(addr);
+                if (reg & CLKDIVC1_P2E)
+                        div = __raw_readl(addr) & 0x3f;
+                break;
+        }
+        return get_rate_pll(pll) / (div + 1);
+}
+
+static unsigned long get_rate_xi_div(void)
+{
+        unsigned long div = 0;
+        u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
+
+        if (reg & CLKDIVC0_XE)
+                div = (reg >> 8) & 0x3f;
+
+        return xi_rate / (div + 1);
+}
+
+static unsigned long get_rate_xti_div(void)
+{
+        unsigned long div = 0;
+        u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
+
+        if (reg & CLKDIVC0_XTE)
+                div = reg & 0x3f;
+
+        return xti_rate / (div + 1);
+}
+
+static unsigned long root_clk_get_rate(enum root_clks src)
+{
+        switch (src) {
+        case CLK_SRC_PLL0: return get_rate_pll(0);
+        case CLK_SRC_PLL1: return get_rate_pll(1);
+        case CLK_SRC_PLL2: return get_rate_pll(2);
+        case CLK_SRC_PLL0DIV: return get_rate_pll_div(0);
+        case CLK_SRC_PLL1DIV: return get_rate_pll_div(1);
+        case CLK_SRC_PLL2DIV: return get_rate_pll_div(2);
+        case CLK_SRC_XI: return xi_rate;
+        case CLK_SRC_XTI: return xti_rate;
+        case CLK_SRC_XIDIV: return get_rate_xi_div();
+        case CLK_SRC_XTIDIV: return get_rate_xti_div();
+        default: return 0;
+        }
+}
+
+static unsigned long aclk_get_rate(struct clk *clk)
+{
+        u32 reg;
+        unsigned long div;
+        unsigned int src;
+
+        reg = __raw_readl(clk->aclkreg);
+        div = reg & 0x0fff;
+        src = (reg >> ACLK_SEL_SHIFT) & CLK_SRC_MASK;
+        return root_clk_get_rate(src) / (div + 1);
+}
+
+static unsigned long aclk_best_div(struct clk *clk, unsigned long rate)
+{
+        unsigned long div, src, freq, r1, r2;
+
+        src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
+        src &= CLK_SRC_MASK;
+        freq = root_clk_get_rate(src);
+        div = freq / rate + 1;
+        r1 = freq / div;
+        r2 = freq / (div + 1);
+        if (r2 >= rate)
+                return div + 1;
+        if ((rate - r2) < (r1 - rate))
+                return div + 1;
+
+        return div;
+}
+
+static unsigned long aclk_round_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int src;
+
+        src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
+        src &= CLK_SRC_MASK;
+
+        return root_clk_get_rate(src) / aclk_best_div(clk, rate);
+}
+
+static int aclk_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->aclkreg) & ~ACLK_DIV_MASK;
+        reg |= aclk_best_div(clk, rate);
+        return 0;
+}
+
+static unsigned long get_rate_sys(struct clk *clk)
+{
+        unsigned int src;
+
+        src = __raw_readl(CKC_BASE + CLKCTRL_OFFS) & CLK_SRC_MASK;
+                return root_clk_get_rate(src);
+}
+
+static unsigned long get_rate_bus(struct clk *clk)
+{
+        unsigned int div;
+
+        div = (__raw_readl(CKC_BASE + CLKCTRL_OFFS) >> 4) & 0xff;
+        return get_rate_sys(clk) / (div + 1);
+}
+
+static unsigned long get_rate_cpu(struct clk *clk)
+{
+        unsigned int reg, div, fsys, fbus;
+
+        fbus = get_rate_bus(clk);
+        reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
+        if (reg & (1 << 29))
+                return fbus;
+        fsys = get_rate_sys(clk);
+        div = (reg >> 16) & 0x0f;
+        return fbus + ((fsys - fbus) * (div + 1)) / 16;
+}
+
+static unsigned long get_rate_root(struct clk *clk)
+{
+        return root_clk_get_rate(clk->root_id);
+}
+
+static int aclk_set_parent(struct clk *clock, struct clk *parent)
+{
+        u32 reg;
+
+        if (clock->parent == parent)
+                return 0;
+
+        clock->parent = parent;
+
+        if (!parent)
+                return 0;
+
+        if (parent->root_id == CLK_SRC_NOROOT)
+                return 0;
+        reg = __raw_readl(clock->aclkreg);
+        reg &= ~ACLK_SEL_MASK;
+        reg |= (parent->root_id << ACLK_SEL_SHIFT) & ACLK_SEL_MASK;
+        __raw_writel(reg, clock->aclkreg);
+
+        return 0;
+}
+
+#define DEFINE_ROOT_CLOCK(name, ri, p)  \
+        static struct clk name = {              \
+                .root_id = ri,                  \
+                .get_rate = get_rate_root,                      \
+                .enable = enable_clk,           \
+                .disable = disable_clk,         \
+                .parent = p,                    \
+        };
+
+#define DEFINE_SPECIAL_CLOCK(name, gr, p)       \
+        static struct clk name = {              \
+                .root_id = CLK_SRC_NOROOT,      \
+                .get_rate = gr,                 \
+                .parent = p,                    \
+        };
+
+#define DEFINE_ACLOCK(name, bc, bs, ar)         \
+        static struct clk name = {              \
+                .root_id = CLK_SRC_NOROOT,      \
+                .bclkctr = bc,                  \
+                .bclk_shift = bs,               \
+                .aclkreg = ar,                  \
+                .get_rate = aclk_get_rate,      \
+                .set_rate = aclk_set_rate,      \
+                .round_rate = aclk_round_rate,  \
+                .enable = enable_clk,           \
+                .disable = disable_clk,         \
+                .set_parent = aclk_set_parent,  \
+        };
+
+#define DEFINE_BCLOCK(name, bc, bs, gr, p)      \
+        static struct clk name = {              \
+                .root_id = CLK_SRC_NOROOT,      \
+                .bclkctr = bc,                  \
+                .bclk_shift = bs,               \
+                .get_rate = gr,                 \
+                .enable = enable_clk,           \
+                .disable = disable_clk,         \
+                .parent = p,                    \
+        };
+
+DEFINE_ROOT_CLOCK(xi, CLK_SRC_XI, NULL)
+DEFINE_ROOT_CLOCK(xti, CLK_SRC_XTI, NULL)
+DEFINE_ROOT_CLOCK(xidiv, CLK_SRC_XIDIV, &xi)
+DEFINE_ROOT_CLOCK(xtidiv, CLK_SRC_XTIDIV, &xti)
+DEFINE_ROOT_CLOCK(pll0, CLK_SRC_PLL0, &xi)
+DEFINE_ROOT_CLOCK(pll1, CLK_SRC_PLL1, &xi)
+DEFINE_ROOT_CLOCK(pll2, CLK_SRC_PLL2, &xi)
+DEFINE_ROOT_CLOCK(pll0div, CLK_SRC_PLL0DIV, &pll0)
+DEFINE_ROOT_CLOCK(pll1div, CLK_SRC_PLL1DIV, &pll1)
+DEFINE_ROOT_CLOCK(pll2div, CLK_SRC_PLL2DIV, &pll2)
+
+/* The following 3 clocks are special and are initialized explicitly later */
+DEFINE_SPECIAL_CLOCK(sys, get_rate_sys, NULL)
+DEFINE_SPECIAL_CLOCK(bus, get_rate_bus, &sys)
+DEFINE_SPECIAL_CLOCK(cpu, get_rate_cpu, &sys)
+
+DEFINE_ACLOCK(tct, NULL, 0, ACLKTCT)
+DEFINE_ACLOCK(tcx, NULL, 0, ACLKTCX)
+DEFINE_ACLOCK(tcz, NULL, 0, ACLKTCZ)
+DEFINE_ACLOCK(ref, NULL, 0, ACLKREF)
+DEFINE_ACLOCK(uart0, BCLKCTR0, 5, ACLKUART0)
+DEFINE_ACLOCK(uart1, BCLKCTR0, 23, ACLKUART1)
+DEFINE_ACLOCK(uart2, BCLKCTR0, 6, ACLKUART2)
+DEFINE_ACLOCK(uart3, BCLKCTR0, 8, ACLKUART3)
+DEFINE_ACLOCK(uart4, BCLKCTR1, 6, ACLKUART4)
+DEFINE_ACLOCK(i2c, BCLKCTR0, 7, ACLKI2C)
+DEFINE_ACLOCK(adc, BCLKCTR0, 10, ACLKADC)
+DEFINE_ACLOCK(usbh0, BCLKCTR0, 11, ACLKUSBH)
+DEFINE_ACLOCK(lcd, BCLKCTR0, 13, ACLKLCD)
+DEFINE_ACLOCK(sd0, BCLKCTR0, 17, ACLKSDH0)
+DEFINE_ACLOCK(sd1, BCLKCTR1, 5, ACLKSDH1)
+DEFINE_ACLOCK(spi0, BCLKCTR0, 24, ACLKSPI0)
+DEFINE_ACLOCK(spi1, BCLKCTR0, 30, ACLKSPI1)
+DEFINE_ACLOCK(spdif, BCLKCTR1, 2, ACLKSPDIF)
+DEFINE_ACLOCK(c3dec, BCLKCTR1, 9, ACLKC3DEC)
+DEFINE_ACLOCK(can0, BCLKCTR1, 10, ACLKCAN0)
+DEFINE_ACLOCK(can1, BCLKCTR1, 11, ACLKCAN1)
+DEFINE_ACLOCK(gsb0, BCLKCTR1, 13, ACLKGSB0)
+DEFINE_ACLOCK(gsb1, BCLKCTR1, 14, ACLKGSB1)
+DEFINE_ACLOCK(gsb2, BCLKCTR1, 15, ACLKGSB2)
+DEFINE_ACLOCK(gsb3, BCLKCTR1, 16, ACLKGSB3)
+DEFINE_ACLOCK(usbh1, BCLKCTR1, 20, ACLKUSBH)
+
+DEFINE_BCLOCK(dai0, BCLKCTR0, 0, NULL, NULL)
+DEFINE_BCLOCK(pic, BCLKCTR0, 1, NULL, NULL)
+DEFINE_BCLOCK(tc, BCLKCTR0, 2, NULL, NULL)
+DEFINE_BCLOCK(gpio, BCLKCTR0, 3, NULL, NULL)
+DEFINE_BCLOCK(usbd, BCLKCTR0, 4, NULL, NULL)
+DEFINE_BCLOCK(ecc, BCLKCTR0, 9, NULL, NULL)
+DEFINE_BCLOCK(gdma0, BCLKCTR0, 12, NULL, NULL)
+DEFINE_BCLOCK(rtc, BCLKCTR0, 15, NULL, NULL)
+DEFINE_BCLOCK(nfc, BCLKCTR0, 16, NULL, NULL)
+DEFINE_BCLOCK(g2d, BCLKCTR0, 18, NULL, NULL)
+DEFINE_BCLOCK(gdma1, BCLKCTR0, 22, NULL, NULL)
+DEFINE_BCLOCK(mscl, BCLKCTR0, 25, NULL, NULL)
+DEFINE_BCLOCK(bdma, BCLKCTR1, 0, NULL, NULL)
+DEFINE_BCLOCK(adma0, BCLKCTR1, 1, NULL, NULL)
+DEFINE_BCLOCK(scfg, BCLKCTR1, 3, NULL, NULL)
+DEFINE_BCLOCK(cid, BCLKCTR1, 4, NULL, NULL)
+DEFINE_BCLOCK(dai1, BCLKCTR1, 7, NULL, NULL)
+DEFINE_BCLOCK(adma1, BCLKCTR1, 8, NULL, NULL)
+DEFINE_BCLOCK(gps, BCLKCTR1, 12, NULL, NULL)
+DEFINE_BCLOCK(gdma2, BCLKCTR1, 17, NULL, NULL)
+DEFINE_BCLOCK(gdma3, BCLKCTR1, 18, NULL, NULL)
+DEFINE_BCLOCK(ddrc, BCLKCTR1, 19, NULL, NULL)
+
+#define _REGISTER_CLOCK(d, n, c) \
+        { \
+                .dev_id = d, \
+                .con_id = n, \
+                .clk = &c, \
+        },
+
+static struct clk_lookup lookups[] = {
+        _REGISTER_CLOCK(NULL, "bus", bus)
+        _REGISTER_CLOCK(NULL, "cpu", cpu)
+        _REGISTER_CLOCK(NULL, "tct", tct)
+        _REGISTER_CLOCK(NULL, "tcx", tcx)
+        _REGISTER_CLOCK(NULL, "tcz", tcz)
+        _REGISTER_CLOCK(NULL, "ref", ref)
+        _REGISTER_CLOCK(NULL, "dai0", dai0)
+        _REGISTER_CLOCK(NULL, "pic", pic)
+        _REGISTER_CLOCK(NULL, "tc", tc)
+        _REGISTER_CLOCK(NULL, "gpio", gpio)
+        _REGISTER_CLOCK(NULL, "usbd", usbd)
+        _REGISTER_CLOCK("tcc-uart.0", NULL, uart0)
+        _REGISTER_CLOCK("tcc-uart.2", NULL, uart2)
+        _REGISTER_CLOCK("tcc-i2c", NULL, i2c)
+        _REGISTER_CLOCK("tcc-uart.3", NULL, uart3)
+        _REGISTER_CLOCK(NULL, "ecc", ecc)
+        _REGISTER_CLOCK(NULL, "adc", adc)
+        _REGISTER_CLOCK("tcc-usbh.0", "usb", usbh0)
+        _REGISTER_CLOCK(NULL, "gdma0", gdma0)
+        _REGISTER_CLOCK(NULL, "lcd", lcd)
+        _REGISTER_CLOCK(NULL, "rtc", rtc)
+        _REGISTER_CLOCK(NULL, "nfc", nfc)
+        _REGISTER_CLOCK("tcc-mmc.0", NULL, sd0)
+        _REGISTER_CLOCK(NULL, "g2d", g2d)
+        _REGISTER_CLOCK(NULL, "gdma1", gdma1)
+        _REGISTER_CLOCK("tcc-uart.1", NULL, uart1)
+        _REGISTER_CLOCK("tcc-spi.0", NULL, spi0)
+        _REGISTER_CLOCK(NULL, "mscl", mscl)
+        _REGISTER_CLOCK("tcc-spi.1", NULL, spi1)
+        _REGISTER_CLOCK(NULL, "bdma", bdma)
+        _REGISTER_CLOCK(NULL, "adma0", adma0)
+        _REGISTER_CLOCK(NULL, "spdif", spdif)
+        _REGISTER_CLOCK(NULL, "scfg", scfg)
+        _REGISTER_CLOCK(NULL, "cid", cid)
+        _REGISTER_CLOCK("tcc-mmc.1", NULL, sd1)
+        _REGISTER_CLOCK("tcc-uart.4", NULL, uart4)
+        _REGISTER_CLOCK(NULL, "dai1", dai1)
+        _REGISTER_CLOCK(NULL, "adma1", adma1)
+        _REGISTER_CLOCK(NULL, "c3dec", c3dec)
+        _REGISTER_CLOCK("tcc-can.0", NULL, can0)
+        _REGISTER_CLOCK("tcc-can.1", NULL, can1)
+        _REGISTER_CLOCK(NULL, "gps", gps)
+        _REGISTER_CLOCK("tcc-gsb.0", NULL, gsb0)
+        _REGISTER_CLOCK("tcc-gsb.1", NULL, gsb1)
+        _REGISTER_CLOCK("tcc-gsb.2", NULL, gsb2)
+        _REGISTER_CLOCK("tcc-gsb.3", NULL, gsb3)
+        _REGISTER_CLOCK(NULL, "gdma2", gdma2)
+        _REGISTER_CLOCK(NULL, "gdma3", gdma3)
+        _REGISTER_CLOCK(NULL, "ddrc", ddrc)
+        _REGISTER_CLOCK("tcc-usbh.1", "usb", usbh1)
+};
+
+static struct clk *root_clk_by_index(enum root_clks src)
+{
+        switch (src) {
+        case CLK_SRC_PLL0: return &pll0;
+        case CLK_SRC_PLL1: return &pll1;
+        case CLK_SRC_PLL2: return &pll2;
+        case CLK_SRC_PLL0DIV: return &pll0div;
+        case CLK_SRC_PLL1DIV: return &pll1div;
+        case CLK_SRC_PLL2DIV: return &pll2div;
+        case CLK_SRC_XI: return &xi;
+        case CLK_SRC_XTI: return &xti;
+        case CLK_SRC_XIDIV: return &xidiv;
+        case CLK_SRC_XTIDIV: return &xtidiv;
+        default: return NULL;
+        }
+}
+
+static void find_aclk_parent(struct clk *clk)
+{
+        unsigned int src;
+        struct clk *clock;
+
+        if (!clk->aclkreg)
+                return;
+
+        src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
+        src &= CLK_SRC_MASK;
+
+        clock = root_clk_by_index(src);
+        if (!clock)
+                return;
+
+        clk->parent = clock;
+        clk->set_parent = aclk_set_parent;
+}
+
+void __init tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq)
+{
+        int i;
+
+        xi_rate = xi_freq;
+        xti_rate = xti_freq;
+
+        /* fixup parents and add the clock */
+        for (i = 0; i < ARRAY_SIZE(lookups); i++) {
+                find_aclk_parent(lookups[i].clk);
+                clkdev_add(&lookups[i]);
+        }
+        tcc8k_timer_init(&tcz, (void __iomem *)TIMER_BASE, INT_TC32);
+}
diff --git a/arch/arm/mach-tcc8k/common.h b/arch/arm/mach-tcc8k/common.h
new file mode 100644
index 000000000000..705690add395
--- /dev/null
+++ b/arch/arm/mach-tcc8k/common.h
@@ -0,0 +1,15 @@
+#ifndef MACH_TCC8K_COMMON_H
+#define MACH_TCC8K_COMMON_H
+
+#include <linux/platform_device.h>
+
+extern struct platform_device tcc_nand_device;
+
+struct clk;
+
+extern void tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq);
+extern void tcc8k_timer_init(struct clk *clock, void __iomem *base, int irq);
+extern void tcc8k_init_irq(void);
+extern void tcc8k_map_common_io(void);
+
+#endif
diff --git a/arch/arm/mach-tcc8k/devices.c b/arch/arm/mach-tcc8k/devices.c
new file mode 100644
index 000000000000..6722ad7c2836
--- /dev/null
+++ b/arch/arm/mach-tcc8k/devices.c
@@ -0,0 +1,239 @@
+/*
+ * linux/arch/arm/mach-tcc8k/devices.c
+ *
+ * Copyright (C) Telechips, Inc.
+ * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of GPL v2.
+ *
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/tcc8k-regs.h>
+#include <mach/irqs.h>
+
+#include "common.h"
+
+static u64 tcc8k_dmamask = DMA_BIT_MASK(32);
+
+#ifdef CONFIG_MTD_NAND_TCC
+/* NAND controller */
+static struct resource tcc_nand_resources[] = {
+        {
+                .start  = (resource_size_t)NFC_BASE,
+                .end    = (resource_size_t)NFC_BASE + 0x7f,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = INT_NFC,
+                .end    = INT_NFC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device tcc_nand_device = {
+        .name = "tcc_nand",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(tcc_nand_resources),
+        .resource = tcc_nand_resources,
+};
+#endif
+
+#ifdef CONFIG_MMC_TCC8K
+/* MMC controller */
+static struct resource tcc8k_mmc0_resource[] = {
+        {
+                .start = INT_SD0,
+                .end   = INT_SD0,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource tcc8k_mmc1_resource[] = {
+        {
+                .start = INT_SD1,
+                .end   = INT_SD1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device tcc8k_mmc0_device = {
+        .name           = "tcc-mmc",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(tcc8k_mmc0_resource),
+        .resource       = tcc8k_mmc0_resource,
+        .dev            = {
+                .dma_mask               = &tcc8k_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        }
+};
+
+struct platform_device tcc8k_mmc1_device = {
+        .name           = "tcc-mmc",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(tcc8k_mmc1_resource),
+        .resource       = tcc8k_mmc1_resource,
+        .dev            = {
+                .dma_mask               = &tcc8k_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        }
+};
+
+static inline void tcc8k_init_mmc(void)
+{
+        u32 reg = __raw_readl(GPIOPS_BASE + GPIOPS_FS1_OFFS);
+
+        reg |= GPIOPS_FS1_SDH0_BITS | GPIOPS_FS1_SDH1_BITS;
+        __raw_writel(reg, GPIOPS_BASE + GPIOPS_FS1_OFFS);
+
+        platform_device_register(&tcc8k_mmc0_device);
+        platform_device_register(&tcc8k_mmc1_device);
+}
+#else
+static inline void tcc8k_init_mmc(void) { }
+#endif
+
+#ifdef CONFIG_USB_OHCI_HCD
+static int tcc8k_ohci_init(struct device *dev)
+{
+        u32 reg;
+
+        /* Use GPIO PK19 as VBUS control output */
+        reg = __raw_readl(GPIOPK_BASE + GPIOPK_FS0_OFFS);
+        reg &= ~(1 << 19);
+        __raw_writel(reg, GPIOPK_BASE + GPIOPK_FS0_OFFS);
+        reg = __raw_readl(GPIOPK_BASE + GPIOPK_FS1_OFFS);
+        reg &= ~(1 << 19);
+        __raw_writel(reg, GPIOPK_BASE + GPIOPK_FS1_OFFS);
+
+        reg = __raw_readl(GPIOPK_BASE + GPIOPK_DOE_OFFS);
+        reg |= (1 << 19);
+        __raw_writel(reg, GPIOPK_BASE + GPIOPK_DOE_OFFS);
+        /* Turn on VBUS */
+        reg = __raw_readl(GPIOPK_BASE + GPIOPK_DAT_OFFS);
+        reg |= (1 << 19);
+        __raw_writel(reg, GPIOPK_BASE + GPIOPK_DAT_OFFS);
+
+        return 0;
+}
+
+static struct resource tcc8k_ohci0_resources[] = {
+        [0] = {
+                .start = (resource_size_t)USBH0_BASE,
+                .end   = (resource_size_t)USBH0_BASE + 0x5c,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = INT_USBH0,
+                .end   = INT_USBH0,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+static struct resource tcc8k_ohci1_resources[] = {
+        [0] = {
+                .start = (resource_size_t)USBH1_BASE,
+                .end   = (resource_size_t)USBH1_BASE + 0x5c,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = INT_USBH1,
+                .end   = INT_USBH1,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+static struct tccohci_platform_data tcc8k_ohci0_platform_data = {
+        .controller     = 0,
+        .port_mode      = PMM_PERPORT_MODE,
+        .init           = tcc8k_ohci_init,
+};
+
+static struct tccohci_platform_data tcc8k_ohci1_platform_data = {
+        .controller     = 1,
+        .port_mode      = PMM_PERPORT_MODE,
+        .init           = tcc8k_ohci_init,
+};
+
+static struct platform_device ohci0_device = {
+        .name = "tcc-ohci",
+        .id = 0,
+        .dev = {
+                .dma_mask = &tcc8k_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+                .platform_data = &tcc8k_ohci0_platform_data,
+        },
+        .num_resources  = ARRAY_SIZE(tcc8k_ohci0_resources),
+        .resource       = tcc8k_ohci0_resources,
+};
+
+static struct platform_device ohci1_device = {
+        .name = "tcc-ohci",
+        .id = 1,
+        .dev = {
+                .dma_mask = &tcc8k_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+                .platform_data = &tcc8k_ohci1_platform_data,
+        },
+        .num_resources  = ARRAY_SIZE(tcc8k_ohci1_resources),
+        .resource       = tcc8k_ohci1_resources,
+};
+
+static void __init tcc8k_init_usbhost(void)
+{
+        platform_device_register(&ohci0_device);
+        platform_device_register(&ohci1_device);
+}
+#else
+static void __init tcc8k_init_usbhost(void) { }
+#endif
+
+/* USB device controller*/
+#ifdef CONFIG_USB_GADGET_TCC8K
+static struct resource udc_resources[] = {
+        [0] = {
+                .start = INT_USBD,
+                .end   = INT_USBD,
+                .flags = IORESOURCE_IRQ,
+        },
+        [1] = {
+                .start = INT_UDMA,
+                .end   = INT_UDMA,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tcc8k_udc_device = {
+        .name = "tcc-udc",
+        .id = 0,
+        .resource = udc_resources,
+        .num_resources = ARRAY_SIZE(udc_resources),
+        .dev = {
+                 .dma_mask = &tcc8k_dmamask,
+                 .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+
+static void __init tcc8k_init_usb_gadget(void)
+{
+        platform_device_register(&tcc8k_udc_device);
+}
+#else
+static void __init tcc8k_init_usb_gadget(void) { }
+#endif  /* CONFIG_USB_GADGET_TCC83X */
+
+static int __init tcc8k_init_devices(void)
+{
+        tcc8k_init_mmc();
+        tcc8k_init_usbhost();
+        tcc8k_init_usb_gadget();
+        return 0;
+}
+
+arch_initcall(tcc8k_init_devices);
diff --git a/arch/arm/mach-tcc8k/io.c b/arch/arm/mach-tcc8k/io.c
new file mode 100644
index 000000000000..9b39d7fa658f
--- /dev/null
+++ b/arch/arm/mach-tcc8k/io.c
@@ -0,0 +1,62 @@
+/*
+ * linux/arch/arm/mach-tcc8k/io.c
+ *
+ * (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * derived from TCC83xx io.c
+ * Copyright (C) Telechips, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/tcc8k-regs.h>
+
+/*
+ * The machine specific code may provide the extra mapping besides the
+ * default mapping provided here.
+ */
+static struct map_desc tcc8k_io_desc[] __initdata = {
+        {
+                .virtual        = (unsigned long)CS1_BASE_VIRT,
+                .pfn            = __phys_to_pfn(CS1_BASE),
+                .length         = CS1_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)AHB_PERI_BASE_VIRT,
+                .pfn            = __phys_to_pfn(AHB_PERI_BASE),
+                .length         = AHB_PERI_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)APB0_PERI_BASE_VIRT,
+                .pfn            = __phys_to_pfn(APB0_PERI_BASE),
+                .length         = APB0_PERI_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)APB1_PERI_BASE_VIRT,
+                .pfn            = __phys_to_pfn(APB1_PERI_BASE),
+                .length         = APB1_PERI_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)EXT_MEM_CTRL_BASE_VIRT,
+                .pfn            = __phys_to_pfn(EXT_MEM_CTRL_BASE),
+                .length         = EXT_MEM_CTRL_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
+/*
+ * Maps common IO regions for tcc8k.
+ *
+ */
+void __init tcc8k_map_common_io(void)
+{
+        iotable_init(tcc8k_io_desc, ARRAY_SIZE(tcc8k_io_desc));
+}
diff --git a/arch/arm/mach-tcc8k/irq.c b/arch/arm/mach-tcc8k/irq.c
new file mode 100644
index 000000000000..34575c4963f0
--- /dev/null
+++ b/arch/arm/mach-tcc8k/irq.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) Telechips, Inc.
+ * Copyright (C) 2009-2010 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GNU GPL version 2.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+
+#include <asm/irq.h>
+#include <asm/mach/irq.h>
+
+#include <mach/tcc8k-regs.h>
+#include <mach/irqs.h>
+
+#include "common.h"
+
+/* Disable IRQ */
+static void tcc8000_mask_ack_irq0(unsigned int irq)
+{
+        PIC0_IEN &= ~(1 << irq);
+        PIC0_CREQ |=  (1 << irq);
+}
+
+static void tcc8000_mask_ack_irq1(unsigned int irq)
+{
+        PIC1_IEN &= ~(1 << (irq - 32));
+        PIC1_CREQ |= (1 << (irq - 32));
+}
+
+static void tcc8000_mask_irq0(unsigned int irq)
+{
+        PIC0_IEN &= ~(1 << irq);
+}
+
+static void tcc8000_mask_irq1(unsigned int irq)
+{
+        PIC1_IEN &= ~(1 << (irq - 32));
+}
+
+static void tcc8000_ack_irq0(unsigned int irq)
+{
+        PIC0_CREQ |=  (1 << irq);
+}
+
+static void tcc8000_ack_irq1(unsigned int irq)
+{
+        PIC1_CREQ |= (1 << (irq - 32));
+}
+
+/* Enable IRQ */
+static void tcc8000_unmask_irq0(unsigned int irq)
+{
+        PIC0_IEN |= (1 << irq);
+        PIC0_INTOEN |= (1 << irq);
+}
+
+static void tcc8000_unmask_irq1(unsigned int irq)
+{
+        PIC1_IEN |= (1 << (irq - 32));
+        PIC1_INTOEN |= (1 << (irq - 32));
+}
+
+static struct irq_chip tcc8000_irq_chip0 = {
+        .name           = "tcc_irq0",
+        .mask           = tcc8000_mask_irq0,
+        .ack            = tcc8000_ack_irq0,
+        .mask_ack       = tcc8000_mask_ack_irq0,
+        .unmask         = tcc8000_unmask_irq0,
+};
+
+static struct irq_chip tcc8000_irq_chip1 = {
+        .name           = "tcc_irq1",
+        .mask           = tcc8000_mask_irq1,
+        .ack            = tcc8000_ack_irq1,
+        .mask_ack       = tcc8000_mask_ack_irq1,
+        .unmask         = tcc8000_unmask_irq1,
+};
+
+void __init tcc8k_init_irq(void)
+{
+        int irqno;
+
+        /* Mask and clear all interrupts */
+        PIC0_IEN = 0x00000000;
+        PIC0_CREQ = 0xffffffff;
+        PIC1_IEN = 0x00000000;
+        PIC1_CREQ = 0xffffffff;
+
+        PIC0_MEN0 = 0x00000003;
+        PIC1_MEN1 = 0x00000003;
+        PIC1_MEN = 0x00000003;
+
+        /* let all IRQs be level triggered */
+        PIC0_TMODE = 0xffffffff;
+        PIC1_TMODE = 0xffffffff;
+        /* all IRQs are IRQs (not FIQs) */
+        PIC0_IRQSEL = 0xffffffff;
+        PIC1_IRQSEL = 0xffffffff;
+
+        for (irqno = 0; irqno < NR_IRQS; irqno++) {
+                if (irqno < 32)
+                        set_irq_chip(irqno, &tcc8000_irq_chip0);
+                else
+                        set_irq_chip(irqno, &tcc8000_irq_chip1);
+                set_irq_handler(irqno, handle_level_irq);
+                set_irq_flags(irqno, IRQF_VALID);
+        }
+}
diff --git a/arch/arm/mach-tcc8k/time.c b/arch/arm/mach-tcc8k/time.c
new file mode 100644
index 000000000000..78d06008841d
--- /dev/null
+++ b/arch/arm/mach-tcc8k/time.c
@@ -0,0 +1,149 @@
+/*
+ * TCC8000 system timer setup
+ *
+ * (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GPL version 2.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+
+#include <asm/mach/time.h>
+
+#include <mach/tcc8k-regs.h>
+#include <mach/irqs.h>
+
+#include "common.h"
+
+static void __iomem *timer_base;
+
+static cycle_t tcc_get_cycles(struct clocksource *cs)
+{
+        return __raw_readl(timer_base + TC32MCNT_OFFS);
+}
+
+static struct clocksource clocksource_tcc = {
+        .name           = "tcc_tc32",
+        .rating         = 200,
+        .read           = tcc_get_cycles,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .shift          = 28,
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static int tcc_set_next_event(unsigned long evt,
+                              struct clock_event_device *unused)
+{
+        unsigned long reg = __raw_readl(timer_base + TC32MCNT_OFFS);
+
+        __raw_writel(reg + evt, timer_base + TC32CMP0_OFFS);
+        return 0;
+}
+
+static void tcc_set_mode(enum clock_event_mode mode,
+                                struct clock_event_device *evt)
+{
+        unsigned long tc32irq;
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_ONESHOT:
+                tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS);
+                tc32irq |= TC32IRQ_IRQEN0;
+                __raw_writel(tc32irq, timer_base + TC32IRQ_OFFS);
+                break;
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_UNUSED:
+                tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS);
+                tc32irq &= ~TC32IRQ_IRQEN0;
+                __raw_writel(tc32irq, timer_base + TC32IRQ_OFFS);
+                break;
+        case CLOCK_EVT_MODE_PERIODIC:
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        }
+}
+
+static irqreturn_t tcc8k_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = dev_id;
+
+        /* Acknowledge TC32 interrupt by reading TC32IRQ */
+        __raw_readl(timer_base + TC32IRQ_OFFS);
+
+        evt->event_handler(evt);
+
+        return IRQ_HANDLED;
+}
+
+static struct clock_event_device clockevent_tcc = {
+        .name           = "tcc_timer1",
+        .features       = CLOCK_EVT_FEAT_ONESHOT,
+        .shift          = 32,
+        .set_mode       = tcc_set_mode,
+        .set_next_event = tcc_set_next_event,
+        .rating         = 200,
+};
+
+static struct irqaction tcc8k_timer_irq = {
+        .name           = "TC32_timer",
+        .flags          = IRQF_DISABLED | IRQF_TIMER,
+        .handler        = tcc8k_timer_interrupt,
+        .dev_id         = &clockevent_tcc,
+};
+
+static int __init tcc_clockevent_init(struct clk *clock)
+{
+        unsigned int c = clk_get_rate(clock);
+
+        clocksource_tcc.mult = clocksource_hz2mult(c,
+                                        clocksource_tcc.shift);
+        clocksource_register(&clocksource_tcc);
+
+        clockevent_tcc.mult = div_sc(c, NSEC_PER_SEC,
+                                        clockevent_tcc.shift);
+        clockevent_tcc.max_delta_ns =
+                        clockevent_delta2ns(0xfffffffe, &clockevent_tcc);
+        clockevent_tcc.min_delta_ns =
+                        clockevent_delta2ns(0xff, &clockevent_tcc);
+
+        clockevent_tcc.cpumask = cpumask_of(0);
+
+        clockevents_register_device(&clockevent_tcc);
+
+        return 0;
+}
+
+void __init tcc8k_timer_init(struct clk *clock, void __iomem *base, int irq)
+{
+        u32 reg;
+
+        timer_base = base;
+        tcc8k_timer_irq.irq = irq;
+
+        /* Enable clocks */
+        clk_enable(clock);
+
+        /* Initialize 32-bit timer */
+        reg = __raw_readl(timer_base + TC32EN_OFFS);
+        reg &= ~TC32EN_ENABLE; /* Disable timer */
+        __raw_writel(reg, timer_base + TC32EN_OFFS);
+        /* Free running timer, counting from 0 to 0xffffffff */
+        __raw_writel(0, timer_base + TC32EN_OFFS);
+        __raw_writel(0, timer_base + TC32LDV_OFFS);
+        reg = __raw_readl(timer_base + TC32IRQ_OFFS);
+        reg |= TC32IRQ_IRQEN0; /* irq at match with CMP0 */
+        __raw_writel(reg, timer_base + TC32IRQ_OFFS);
+
+        __raw_writel(TC32EN_ENABLE, timer_base + TC32EN_OFFS);
+
+        tcc_clockevent_init(clock);
+        setup_irq(irq, &tcc8k_timer_irq);
+}
diff --git a/arch/arm/mach-u300/include/mach/gpio.h b/arch/arm/mach-u300/include/mach/gpio.h
index 7b1fc984abb6..d5a71abcbaea 100644
--- a/arch/arm/mach-u300/include/mach/gpio.h
+++ b/arch/arm/mach-u300/include/mach/gpio.h
@@ -273,6 +273,9 @@ extern void gpio_pullup(unsigned gpio, int value);
 extern int gpio_get_value(unsigned gpio);
 extern void gpio_set_value(unsigned gpio, int value);
 
+#define gpio_get_value_cansleep gpio_get_value
+#define gpio_set_value_cansleep gpio_set_value
+
 /* wrappers to sleep-enable the previous two functions */
 static inline unsigned gpio_to_irq(unsigned gpio)
 {
diff --git a/arch/arm/mach-versatile/include/mach/vmalloc.h b/arch/arm/mach-versatile/include/mach/vmalloc.h
index 427e3612db5d..ebd8a2543d3b 100644
--- a/arch/arm/mach-versatile/include/mach/vmalloc.h
+++ b/arch/arm/mach-versatile/include/mach/vmalloc.h
@@ -18,4 +18,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#define VMALLOC_END             (PAGE_OFFSET + 0x18000000)
+#define VMALLOC_END             0xd8000000
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 577df6cccb08..71fb17349520 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -68,7 +68,7 @@ static void __init ct_ca9x4_init_irq(void)
 }
 
 #if 0
-static void ct_ca9x4_timer_init(void)
+static void __init ct_ca9x4_timer_init(void)
 {
         writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
         writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
@@ -222,12 +222,18 @@ static struct platform_device pmu_device = {
         .resource       = pmu_resources,
 };
 
-static void ct_ca9x4_init(void)
+static void __init ct_ca9x4_init(void)
 {
         int i;
 
 #ifdef CONFIG_CACHE_L2X0
-        l2x0_init(MMIO_P2V(CT_CA9X4_L2CC), 0x00000000, 0xfe0fffff);
+        void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);
+
+        /* set RAM latencies to 1 cycle for this core tile. */
+        writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
+        writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
+
+        l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
 #endif
 
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 817f0ad38a0b..7eaa232180a5 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -48,7 +48,7 @@ void __init v2m_map_io(struct map_desc *tile, size_t num)
 }
 
 
-static void v2m_timer_init(void)
+static void __init v2m_timer_init(void)
 {
         writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
         writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index d073b64ae87e..724ba3bce72c 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -885,8 +885,23 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 
         if (ai_usermode & UM_SIGNAL)
                 force_sig(SIGBUS, current);
-        else
-                set_cr(cr_no_alignment);
+        else {
+                /*
+                 * We're about to disable the alignment trap and return to
+                 * user space.  But if an interrupt occurs before actually
+                 * reaching user space, then the IRQ vector entry code will
+                 * notice that we were still in kernel space and therefore
+                 * the alignment trap won't be re-enabled in that case as it
+                 * is presumed to be always on from kernel space.
+                 * Let's prevent that race by disabling interrupts here (they
+                 * are disabled on the way back to user space anyway in
+                 * entry-common.S) and disable the alignment trap only if
+                 * there is no work pending for this thread.
+                 */
+                raw_local_irq_disable();
+                if (!(current_thread_info()->flags & _TIF_WORK_MASK))
+                        set_cr(cr_no_alignment);
+        }
 
         return 0;
 }
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index ab506272b2d3..17e7b0b57e49 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -204,8 +204,12 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
         /*
          * Don't allow RAM to be mapped - this causes problems with ARMv6+
          */
-        if (WARN_ON(pfn_valid(pfn)))
-                return NULL;
+        if (pfn_valid(pfn)) {
+                printk(KERN_WARNING "BUG: Your driver calls ioremap() on system memory.  This leads\n"
+                       KERN_WARNING "to architecturally unpredictable behaviour on ARMv6+, and ioremap()\n"
+                       KERN_WARNING "will fail in the next kernel release.  Please fix your driver.\n");
+                WARN_ON(1);
+        }
 
         type = get_mem_type(mtype);
         if (!type)
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index 4f5b39687df5..b0a98305055c 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -144,3 +144,25 @@ int valid_mmap_phys_addr_range(unsigned long pfn, size_t size)
 {
         return !(pfn + (size >> PAGE_SHIFT) > 0x00100000);
 }
+
+#ifdef CONFIG_STRICT_DEVMEM
+
+#include <linux/ioport.h>
+
+/*
+ * devmem_is_allowed() checks to see if /dev/mem access to a certain
+ * address is valid. The argument is a physical page number.
+ * We mimic x86 here by disallowing access to system RAM as well as
+ * device-exclusive MMIO regions. This effectively disable read()/write()
+ * on /dev/mem.
+ */
+int devmem_is_allowed(unsigned long pfn)
+{
+        if (iomem_is_exclusive(pfn << PAGE_SHIFT))
+                return 0;
+        if (!page_is_ram(pfn))
+                return 1;
+        return 0;
+}
+
+#endif
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 6e1c4f6a2b3f..e8ed9dc461fe 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -15,6 +15,7 @@
 #include <linux/nodemask.h>
 #include <linux/memblock.h>
 #include <linux/sort.h>
+#include <linux/fs.h>
 
 #include <asm/cputype.h>
 #include <asm/sections.h>
@@ -246,6 +247,9 @@ static struct mem_type mem_types[] = {
                 .domain    = DOMAIN_USER,
         },
         [MT_MEMORY] = {
+                .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
+                                L_PTE_WRITE | L_PTE_EXEC,
+                .prot_l1   = PMD_TYPE_TABLE,
                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
                 .domain    = DOMAIN_KERNEL,
         },
@@ -254,6 +258,9 @@ static struct mem_type mem_types[] = {
                 .domain    = DOMAIN_KERNEL,
         },
         [MT_MEMORY_NONCACHED] = {
+                .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
+                                L_PTE_WRITE | L_PTE_EXEC | L_PTE_MT_BUFFERABLE,
+                .prot_l1   = PMD_TYPE_TABLE,
                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
                 .domain    = DOMAIN_KERNEL,
         },
@@ -411,9 +418,12 @@ static void __init build_mem_type_table(void)
          * Enable CPU-specific coherency if supported.
          * (Only available on XSC3 at the moment.)
          */
-        if (arch_is_coherent() && cpu_is_xsc3())
+        if (arch_is_coherent() && cpu_is_xsc3()) {
                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
-
+                mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
+                mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+                mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
+        }
         /*
          * ARMv6 and above have extended page tables.
          */
@@ -438,7 +448,9 @@ static void __init build_mem_type_table(void)
                 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
                 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
+                mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+                mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
 #endif
         }
 
@@ -475,6 +487,8 @@ static void __init build_mem_type_table(void)
         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
+        mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
+        mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
         mem_types[MT_ROM].prot_sect |= cp->pmd;
 
         switch (cp->pmd) {
@@ -498,6 +512,19 @@ static void __init build_mem_type_table(void)
         }
 }
 
+#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
+pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+                              unsigned long size, pgprot_t vma_prot)
+{
+        if (!pfn_valid(pfn))
+                return pgprot_noncached(vma_prot);
+        else if (file->f_flags & O_SYNC)
+                return pgprot_writecombine(vma_prot);
+        return vma_prot;
+}
+EXPORT_SYMBOL(phys_mem_access_prot);
+#endif
+
 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
 
 static void __init *early_alloc(unsigned long sz)
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 6a8506d99ee9..197f21bed5e9 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -186,13 +186,14 @@ cpu_v7_name:
  *      It is assumed that:
  *      - cache type register is implemented
  */
-__v7_setup:
+__v7_ca9mp_setup:
 #ifdef CONFIG_SMP
         mrc     p15, 0, r0, c1, c0, 1
         tst     r0, #(1 << 6)                   @ SMP/nAMP mode enabled?
         orreq   r0, r0, #(1 << 6) | (1 << 0)    @ Enable SMP/nAMP mode and
         mcreq   p15, 0, r0, c1, c0, 1           @ TLB ops broadcasting
 #endif
+__v7_setup:
         adr     r12, __v7_setup_stack           @ the local stack
         stmia   r12, {r0-r5, r7, r9, r11, lr}
         bl      v7_flush_dcache_all
@@ -201,11 +202,16 @@ __v7_setup:
         mrc     p15, 0, r0, c0, c0, 0           @ read main ID register
         and     r10, r0, #0xff000000            @ ARM?
         teq     r10, #0x41000000
-        bne     2f
+        bne     3f
         and     r5, r0, #0x00f00000             @ variant
         and     r6, r0, #0x0000000f             @ revision
-        orr     r0, r6, r5, lsr #20-4           @ combine variant and revision
+        orr     r6, r6, r5, lsr #20-4           @ combine variant and revision
+        ubfx    r0, r0, #4, #12                 @ primary part number
 
+        /* Cortex-A8 Errata */
+        ldr     r10, =0x00000c08                @ Cortex-A8 primary part number
+        teq     r0, r10
+        bne     2f
 #ifdef CONFIG_ARM_ERRATA_430973
         teq     r5, #0x00100000                 @ only present in r1p*
         mrceq   p15, 0, r10, c1, c0, 1          @ read aux control register
@@ -213,21 +219,50 @@ __v7_setup:
         mcreq   p15, 0, r10, c1, c0, 1          @ write aux control register
 #endif
 #ifdef CONFIG_ARM_ERRATA_458693
-        teq     r0, #0x20                       @ only present in r2p0
+        teq     r6, #0x20                       @ only present in r2p0
         mrceq   p15, 0, r10, c1, c0, 1          @ read aux control register
         orreq   r10, r10, #(1 << 5)             @ set L1NEON to 1
         orreq   r10, r10, #(1 << 9)             @ set PLDNOP to 1
         mcreq   p15, 0, r10, c1, c0, 1          @ write aux control register
 #endif
 #ifdef CONFIG_ARM_ERRATA_460075
-        teq     r0, #0x20                       @ only present in r2p0
+        teq     r6, #0x20                       @ only present in r2p0
         mrceq   p15, 1, r10, c9, c0, 2          @ read L2 cache aux ctrl register
         tsteq   r10, #1 << 22
         orreq   r10, r10, #(1 << 22)            @ set the Write Allocate disable bit
         mcreq   p15, 1, r10, c9, c0, 2          @ write the L2 cache aux ctrl register
 #endif
+        b       3f
 
-2:      mov     r10, #0
+        /* Cortex-A9 Errata */
+2:      ldr     r10, =0x00000c09                @ Cortex-A9 primary part number
+        teq     r0, r10
+        bne     3f
+#ifdef CONFIG_ARM_ERRATA_742230
+        cmp     r6, #0x22                       @ only present up to r2p2
+        mrcle   p15, 0, r10, c15, c0, 1         @ read diagnostic register
+        orrle   r10, r10, #1 << 4               @ set bit #4
+        mcrle   p15, 0, r10, c15, c0, 1         @ write diagnostic register
+#endif
+#ifdef CONFIG_ARM_ERRATA_742231
+        teq     r6, #0x20                       @ present in r2p0
+        teqne   r6, #0x21                       @ present in r2p1
+        teqne   r6, #0x22                       @ present in r2p2
+        mrceq   p15, 0, r10, c15, c0, 1         @ read diagnostic register
+        orreq   r10, r10, #1 << 12              @ set bit #12
+        orreq   r10, r10, #1 << 22              @ set bit #22
+        mcreq   p15, 0, r10, c15, c0, 1         @ write diagnostic register
+#endif
+#ifdef CONFIG_ARM_ERRATA_743622
+        teq     r6, #0x20                       @ present in r2p0
+        teqne   r6, #0x21                       @ present in r2p1
+        teqne   r6, #0x22                       @ present in r2p2
+        mrceq   p15, 0, r10, c15, c0, 1         @ read diagnostic register
+        orreq   r10, r10, #1 << 6               @ set bit #6
+        mcreq   p15, 0, r10, c15, c0, 1         @ write diagnostic register
+#endif
+
+3:      mov     r10, #0
 #ifdef HARVARD_CACHE
         mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
 #endif
@@ -323,6 +358,29 @@ cpu_elf_name:
 
         .section ".proc.info.init", #alloc, #execinstr
 
+        .type   __v7_ca9mp_proc_info, #object
+__v7_ca9mp_proc_info:
+        .long   0x410fc090              @ Required ID value
+        .long   0xff0ffff0              @ Mask for ID
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ | \
+                PMD_FLAGS
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_XN | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        b       __v7_ca9mp_setup
+        .long   cpu_arch_name
+        .long   cpu_elf_name
+        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
+        .long   cpu_v7_name
+        .long   v7_processor_functions
+        .long   v7wbi_tlb_fns
+        .long   v6_user_fns
+        .long   v7_cache_fns
+        .size   __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
+
         /*
          * Match any ARMv7 processor core.
          */
diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c
index 0691176899ff..72e09eb642dd 100644
--- a/arch/arm/oprofile/common.c
+++ b/arch/arm/oprofile/common.c
@@ -102,6 +102,7 @@ static int op_create_counter(int cpu, int event)
         if (IS_ERR(pevent)) {
                 ret = PTR_ERR(pevent);
         } else if (pevent->state != PERF_EVENT_STATE_ACTIVE) {
+                perf_event_release_kernel(pevent);
                 pr_warning("oprofile: failed to enable event %d "
                                 "on CPU %d\n", event, cpu);
                 ret = -EBUSY;
@@ -365,6 +366,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
         ret = init_driverfs();
         if (ret) {
                 kfree(counter_config);
+                counter_config = NULL;
                 return ret;
         }
 
@@ -402,7 +404,6 @@ void oprofile_arch_exit(void)
         struct perf_event *event;
 
         if (*perf_events) {
-                exit_driverfs();
                 for_each_possible_cpu(cpu) {
                         for (id = 0; id < perf_num_counters; ++id) {
                                 event = perf_events[cpu][id];
@@ -413,8 +414,10 @@ void oprofile_arch_exit(void)
                 }
         }
 
-        if (counter_config)
+        if (counter_config) {
                 kfree(counter_config);
+                exit_driverfs();
+        }
 }
 #else
 int __init oprofile_arch_init(struct oprofile_operations *ops)
diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c
index ea3ca86c5283..aedf9c1d645e 100644
--- a/arch/arm/plat-nomadik/timer.c
+++ b/arch/arm/plat-nomadik/timer.c
@@ -1,5 +1,5 @@
 /*
- *  linux/arch/arm/mach-nomadik/timer.c
+ *  linux/arch/arm/plat-nomadik/timer.c
  *
  * Copyright (C) 2008 STMicroelectronics
  * Copyright (C) 2010 Alessandro Rubini
@@ -75,7 +75,7 @@ static void nmdk_clkevt_mode(enum clock_event_mode mode,
                 cr = readl(mtu_base + MTU_CR(1));
                 writel(0, mtu_base + MTU_LR(1));
                 writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(1));
-                writel(0x2, mtu_base + MTU_IMSC);
+                writel(1 << 1, mtu_base + MTU_IMSC);
                 break;
         case CLOCK_EVT_MODE_SHUTDOWN:
         case CLOCK_EVT_MODE_UNUSED:
@@ -131,25 +131,23 @@ void __init nmdk_timer_init(void)
 {
         unsigned long rate;
         struct clk *clk0;
-        struct clk *clk1;
-        u32 cr;
+        u32 cr = MTU_CRn_32BITS;
 
         clk0 = clk_get_sys("mtu0", NULL);
         BUG_ON(IS_ERR(clk0));
 
-        clk1 = clk_get_sys("mtu1", NULL);
-        BUG_ON(IS_ERR(clk1));
-
         clk_enable(clk0);
-        clk_enable(clk1);
 
         /*
-         * Tick rate is 2.4MHz for Nomadik and 110MHz for ux500:
-         * use a divide-by-16 counter if it's more than 16MHz
+         * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
+         * for ux500.
+         * Use a divide-by-16 counter if the tick rate is more than 32MHz.
+         * At 32 MHz, the timer (with 32 bit counter) can be programmed
+         * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
+         * with 16 gives too low timer resolution.
          */
-        cr = MTU_CRn_32BITS;;
         rate = clk_get_rate(clk0);
-        if (rate > 16 << 20) {
+        if (rate > 32000000) {
                 rate /= 16;
                 cr |= MTU_CRn_PRESCALE_16;
         } else {
@@ -170,15 +168,8 @@ void __init nmdk_timer_init(void)
                 pr_err("timer: failed to initialize clock source %s\n",
                        nmdk_clksrc.name);
 
-        /* Timer 1 is used for events, fix according to rate */
-        cr = MTU_CRn_32BITS;
-        rate = clk_get_rate(clk1);
-        if (rate > 16 << 20) {
-                rate /= 16;
-                cr |= MTU_CRn_PRESCALE_16;
-        } else {
-                cr |= MTU_CRn_PRESCALE_1;
-        }
+        /* Timer 1 is used for events */
+
         clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);
 
         writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index e39a417a368d..a92cb499313f 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -33,7 +33,7 @@ config OMAP_DEBUG_DEVICES
 config OMAP_DEBUG_LEDS
         bool
         depends on OMAP_DEBUG_DEVICES
-        default y if LEDS
+        default y if LEDS_CLASS
 
 config OMAP_RESET_CLOCKS
         bool "Reset unused clocks during boot"
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index a202a2ce6e3d..6cd151b31bc5 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -320,6 +320,7 @@ void flush_iotlb_page(struct iommu *obj, u32 da)
                 if ((start <= da) && (da < start + bytes)) {
                         dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
                                 __func__, start, da, bytes);
+                        iotlb_load_cr(obj, &cr);
                         iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
                 }
         }
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index e31496e35b0f..0c8612fd8312 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -156,7 +156,7 @@ static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
                 /* Writing zero to RSYNC_ERR clears the IRQ */
                 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
         } else {
-                complete(&mcbsp_rx->tx_irq_completion);
+                complete(&mcbsp_rx->rx_irq_completion);
         }
 
         return IRQ_HANDLED;
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 226b2e858d6c..10b3b4c63372 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -220,20 +220,7 @@ void __init omap_map_sram(void)
         if (omap_sram_size == 0)
                 return;
 
-        if (cpu_is_omap24xx()) {
-                omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;
-
-                base = OMAP2_SRAM_PA;
-                base = ROUND_DOWN(base, PAGE_SIZE);
-                omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
-        }
-
         if (cpu_is_omap34xx()) {
-                omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA;
-                base = OMAP3_SRAM_PA;
-                base = ROUND_DOWN(base, PAGE_SIZE);
-                omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
-
                 /*
                  * SRAM must be marked as non-cached on OMAP3 since the
                  * CORE DPLL M2 divider change code (in SRAM) runs with the
@@ -244,13 +231,11 @@ void __init omap_map_sram(void)
                 omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
         }
 
-        if (cpu_is_omap44xx()) {
-                omap_sram_io_desc[0].virtual = OMAP4_SRAM_VA;
-                base = OMAP4_SRAM_PA;
-                base = ROUND_DOWN(base, PAGE_SIZE);
-                omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
-        }
-        omap_sram_io_desc[0].length = 1024 * 1024;      /* Use section desc */
+        omap_sram_io_desc[0].virtual = omap_sram_base;
+        base = omap_sram_start;
+        base = ROUND_DOWN(base, PAGE_SIZE);
+        omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
+        omap_sram_io_desc[0].length = ROUND_DOWN(omap_sram_size, PAGE_SIZE);
         iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
 
         printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
diff --git a/arch/arm/mach-pxa/include/mach/pxa27x_keypad.h b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
index 7b4eadc6df3a..abcc36eb1242 100644
--- a/arch/arm/mach-pxa/include/mach/pxa27x_keypad.h
+++ b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
@@ -25,6 +25,13 @@
  *
  * 4. matrix key and direct key will use the same debounce_interval by
  *    default, which should be sufficient in most cases
+ *
+ * pxa168 keypad platform specific parameter
+ *
+ * NOTE:
+ * clear_wakeup_event callback is a workaround required to clear the
+ * keypad interrupt. The keypad wake must be cleared in addition to
+ * reading the MI/DI bits in the KPC register.
  */
 struct pxa27x_keypad_platform_data {
 
@@ -52,6 +59,9 @@ struct pxa27x_keypad_platform_data {
 
         /* key debounce interval */
         unsigned int    debounce_interval;
+
+        /* clear wakeup event requirement for pxa168 */
+        void            (*clear_wakeup_event)(void);
 };
 
 extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info);
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index c6a855db2fb6..25960966af7c 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -7,7 +7,7 @@
 
 config PLAT_S5P
         bool
-        depends on (ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5PV310)
+        depends on (ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5PV310)
         default y
         select ARM_VIC if !ARCH_S5PV310
         select ARM_GIC if ARCH_S5PV310
@@ -30,7 +30,7 @@ config S5P_EXT_INT
         bool
         help
           Use the external interrupts (other than GPIO interrupts.)
-          Note: Do not choose this for S5P6440.
+          Note: Do not choose this for S5P6440 and S5P6450.
 
 config S5P_DEV_FIMC0
         bool
@@ -46,3 +46,8 @@ config S5P_DEV_FIMC2
         bool
         help
           Compile in platform device definitions for FIMC controller 2
+
+config S5P_DEV_ONENAND
+        bool
+        help
+          Compile in platform device definition for OneNAND controller
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index b2e029673950..f3e917e27da8 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_S5P_EXT_INT)	+= irq-eint.o
 obj-$(CONFIG_S5P_DEV_FIMC0)     += dev-fimc0.o
 obj-$(CONFIG_S5P_DEV_FIMC1)     += dev-fimc1.o
 obj-$(CONFIG_S5P_DEV_FIMC2)     += dev-fimc2.o
+obj-$(CONFIG_S5P_DEV_ONENAND)   += dev-onenand.o
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c
index b5e255265f20..8aaf4e6b60c3 100644
--- a/arch/arm/plat-s5p/clock.c
+++ b/arch/arm/plat-s5p/clock.c
@@ -74,6 +74,13 @@ struct clk clk_fout_epll = {
         .ctrlbit        = (1 << 31),
 };
 
+/* DPLL clock output */
+struct clk clk_fout_dpll = {
+        .name           = "fout_dpll",
+        .id             = -1,
+        .ctrlbit        = (1 << 31),
+};
+
 /* VPLL clock output */
 struct clk clk_fout_vpll = {
         .name           = "fout_vpll",
@@ -122,6 +129,17 @@ struct clksrc_sources clk_src_epll = {
         .nr_sources     = ARRAY_SIZE(clk_src_epll_list),
 };
 
+/* Possible clock sources for DPLL Mux */
+static struct clk *clk_src_dpll_list[] = {
+        [0] = &clk_fin_dpll,
+        [1] = &clk_fout_dpll,
+};
+
+struct clksrc_sources clk_src_dpll = {
+        .sources        = clk_src_dpll_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_dpll_list),
+};
+
 struct clk clk_vpll = {
         .name           = "vpll",
         .id             = -1,
@@ -145,6 +163,7 @@ static struct clk *s5p_clks[] __initdata = {
         &clk_fout_apll,
         &clk_fout_mpll,
         &clk_fout_epll,
+        &clk_fout_dpll,
         &clk_fout_vpll,
         &clk_arm,
         &clk_vpll,
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index b07a078fd284..74f7f5a5446c 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -19,6 +19,7 @@
 #include <plat/cpu.h>
 #include <plat/s5p6440.h>
 #include <plat/s5p6442.h>
+#include <plat/s5p6450.h>
 #include <plat/s5pc100.h>
 #include <plat/s5pv210.h>
 #include <plat/s5pv310.h>
@@ -27,6 +28,7 @@
 
 static const char name_s5p6440[] = "S5P6440";
 static const char name_s5p6442[] = "S5P6442";
+static const char name_s5p6450[] = "S5P6450";
 static const char name_s5pc100[] = "S5PC100";
 static const char name_s5pv210[] = "S5PV210/S5PC110";
 static const char name_s5pv310[] = "S5PV310";
@@ -38,7 +40,7 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .map_io         = s5p6440_map_io,
                 .init_clocks    = s5p6440_init_clocks,
                 .init_uarts     = s5p6440_init_uarts,
-                .init           = s5p6440_init,
+                .init           = s5p64x0_init,
                 .name           = name_s5p6440,
         }, {
                 .idcode         = 0x36442000,
@@ -49,6 +51,14 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .init           = s5p6442_init,
                 .name           = name_s5p6442,
         }, {
+                .idcode         = 0x36450000,
+                .idmask         = 0xffffff00,
+                .map_io         = s5p6450_map_io,
+                .init_clocks    = s5p6450_init_clocks,
+                .init_uarts     = s5p6450_init_uarts,
+                .init           = s5p64x0_init,
+                .name           = name_s5p6450,
+        }, {
                 .idcode         = 0x43100000,
                 .idmask         = 0xfffff000,
                 .map_io         = s5pc100_map_io,
@@ -89,33 +99,11 @@ static struct map_desc s5p_iodesc[] __initdata = {
                 .length         = SZ_64K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = (unsigned long)S3C_VA_UART,
-                .pfn            = __phys_to_pfn(S3C_PA_UART),
-                .length         = SZ_512K,
-                .type           = MT_DEVICE,
-#ifdef CONFIG_ARM_VIC
-        }, {
-                .virtual        = (unsigned long)VA_VIC0,
-                .pfn            = __phys_to_pfn(S5P_PA_VIC0),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC1,
-                .pfn            = __phys_to_pfn(S5P_PA_VIC1),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-#endif
-        }, {
                 .virtual        = (unsigned long)S3C_VA_TIMER,
                 .pfn            = __phys_to_pfn(S5P_PA_TIMER),
                 .length         = SZ_16K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = (unsigned long)S5P_VA_GPIO,
-                .pfn            = __phys_to_pfn(S5P_PA_GPIO),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
                 .pfn            = __phys_to_pfn(S3C_PA_WDT),
                 .length         = SZ_4K,
diff --git a/arch/arm/plat-s5p/dev-fimc0.c b/arch/arm/plat-s5p/dev-fimc0.c
index d3f1a9b5d2b5..608770fc1531 100644
--- a/arch/arm/plat-s5p/dev-fimc0.c
+++ b/arch/arm/plat-s5p/dev-fimc0.c
@@ -10,6 +10,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
@@ -18,7 +19,7 @@
 static struct resource s5p_fimc0_resource[] = {
         [0] = {
                 .start  = S5P_PA_FIMC0,
-                .end    = S5P_PA_FIMC0 + SZ_1M - 1,
+                .end    = S5P_PA_FIMC0 + SZ_4K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -28,9 +29,15 @@ static struct resource s5p_fimc0_resource[] = {
         },
 };
 
+static u64 s5p_fimc0_dma_mask = DMA_BIT_MASK(32);
+
 struct platform_device s5p_device_fimc0 = {
         .name           = "s5p-fimc",
         .id             = 0,
         .num_resources  = ARRAY_SIZE(s5p_fimc0_resource),
         .resource       = s5p_fimc0_resource,
+        .dev            = {
+                .dma_mask               = &s5p_fimc0_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
 };
diff --git a/arch/arm/plat-s5p/dev-fimc1.c b/arch/arm/plat-s5p/dev-fimc1.c
index 41bd6986d0ad..76e3a97a87d3 100644
--- a/arch/arm/plat-s5p/dev-fimc1.c
+++ b/arch/arm/plat-s5p/dev-fimc1.c
@@ -10,6 +10,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
@@ -18,7 +19,7 @@
 static struct resource s5p_fimc1_resource[] = {
         [0] = {
                 .start  = S5P_PA_FIMC1,
-                .end    = S5P_PA_FIMC1 + SZ_1M - 1,
+                .end    = S5P_PA_FIMC1 + SZ_4K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -28,9 +29,15 @@ static struct resource s5p_fimc1_resource[] = {
         },
 };
 
+static u64 s5p_fimc1_dma_mask = DMA_BIT_MASK(32);
+
 struct platform_device s5p_device_fimc1 = {
         .name           = "s5p-fimc",
         .id             = 1,
         .num_resources  = ARRAY_SIZE(s5p_fimc1_resource),
         .resource       = s5p_fimc1_resource,
+        .dev            = {
+                .dma_mask               = &s5p_fimc1_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
 };
diff --git a/arch/arm/plat-s5p/dev-fimc2.c b/arch/arm/plat-s5p/dev-fimc2.c
index dfddeda6d4a3..24d29816fa2c 100644
--- a/arch/arm/plat-s5p/dev-fimc2.c
+++ b/arch/arm/plat-s5p/dev-fimc2.c
@@ -10,6 +10,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
@@ -18,7 +19,7 @@
 static struct resource s5p_fimc2_resource[] = {
         [0] = {
                 .start  = S5P_PA_FIMC2,
-                .end    = S5P_PA_FIMC2 + SZ_1M - 1,
+                .end    = S5P_PA_FIMC2 + SZ_4K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -28,9 +29,15 @@ static struct resource s5p_fimc2_resource[] = {
         },
 };
 
+static u64 s5p_fimc2_dma_mask = DMA_BIT_MASK(32);
+
 struct platform_device s5p_device_fimc2 = {
         .name           = "s5p-fimc",
         .id             = 2,
         .num_resources  = ARRAY_SIZE(s5p_fimc2_resource),
         .resource       = s5p_fimc2_resource,
+        .dev            = {
+                .dma_mask               = &s5p_fimc2_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
 };
diff --git a/arch/arm/mach-s5pv210/dev-onenand.c b/arch/arm/plat-s5p/dev-onenand.c
index f8ede33ee82b..6db926202caa 100644
--- a/arch/arm/mach-s5pv210/dev-onenand.c
+++ b/arch/arm/plat-s5p/dev-onenand.c
@@ -1,10 +1,12 @@
-/*
- * linux/arch/arm/mach-s5pv210/dev-onenand.c
+/* linux/arch/arm/plat-s5p/dev-onenand.c
+ *
+ * Copyright 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  *  Copyright (c) 2008-2010 Samsung Electronics
  *  Kyungmin Park <kyungmin.park@samsung.com>
  *
- * S5PC110 series device definition for OneNAND devices
+ * S5P series device definition for OneNAND devices
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -19,15 +21,15 @@
 #include <mach/irqs.h>
 #include <mach/map.h>
 
-static struct resource s5pc110_onenand_resources[] = {
+static struct resource s5p_onenand_resources[] = {
         [0] = {
-                .start  = S5PC110_PA_ONENAND,
-                .end    = S5PC110_PA_ONENAND + SZ_128K - 1,
+                .start  = S5P_PA_ONENAND,
+                .end    = S5P_PA_ONENAND + SZ_128K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = S5PC110_PA_ONENAND_DMA,
-                .end    = S5PC110_PA_ONENAND_DMA + SZ_8K - 1,
+                .start  = S5P_PA_ONENAND_DMA,
+                .end    = S5P_PA_ONENAND_DMA + SZ_8K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [2] = {
@@ -37,19 +39,19 @@ static struct resource s5pc110_onenand_resources[] = {
         },
 };
 
-struct platform_device s5pc110_device_onenand = {
+struct platform_device s5p_device_onenand = {
         .name           = "s5pc110-onenand",
         .id             = -1,
-        .num_resources  = ARRAY_SIZE(s5pc110_onenand_resources),
-        .resource       = s5pc110_onenand_resources,
+        .num_resources  = ARRAY_SIZE(s5p_onenand_resources),
+        .resource       = s5p_onenand_resources,
 };
 
-void s5pc110_onenand_set_platdata(struct onenand_platform_data *pdata)
+void s5p_onenand_set_platdata(struct onenand_platform_data *pdata)
 {
         struct onenand_platform_data *pd;
 
         pd = kmemdup(pdata, sizeof(struct onenand_platform_data), GFP_KERNEL);
         if (!pd)
                 printk(KERN_ERR "%s: no memory for platform data\n", __func__);
-        s5pc110_device_onenand.dev.platform_data = pd;
+        s5p_device_onenand.dev.platform_data = pd;
 }
diff --git a/arch/arm/plat-s5p/dev-uart.c b/arch/arm/plat-s5p/dev-uart.c
index a89331ef4ae1..6a7342886171 100644
--- a/arch/arm/plat-s5p/dev-uart.c
+++ b/arch/arm/plat-s5p/dev-uart.c
@@ -119,6 +119,56 @@ static struct resource s5p_uart3_resource[] = {
 #endif
 };
 
+static struct resource s5p_uart4_resource[] = {
+#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
+        [0] = {
+                .start  = S5P_PA_UART4,
+                .end    = S5P_PA_UART4 + S5P_SZ_UART,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_S5P_UART_RX4,
+                .end    = IRQ_S5P_UART_RX4,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_S5P_UART_TX4,
+                .end    = IRQ_S5P_UART_TX4,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = IRQ_S5P_UART_ERR4,
+                .end    = IRQ_S5P_UART_ERR4,
+                .flags  = IORESOURCE_IRQ,
+        },
+#endif
+};
+
+static struct resource s5p_uart5_resource[] = {
+#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
+        [0] = {
+                .start  = S5P_PA_UART5,
+                .end    = S5P_PA_UART5 + S5P_SZ_UART,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_S5P_UART_RX5,
+                .end    = IRQ_S5P_UART_RX5,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_S5P_UART_TX5,
+                .end    = IRQ_S5P_UART_TX5,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = IRQ_S5P_UART_ERR5,
+                .end    = IRQ_S5P_UART_ERR5,
+                .flags  = IORESOURCE_IRQ,
+        },
+#endif
+};
+
 struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = {
         [0] = {
                 .resources      = s5p_uart0_resource,
@@ -136,4 +186,12 @@ struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = {
                 .resources      = s5p_uart3_resource,
                 .nr_resources   = ARRAY_SIZE(s5p_uart3_resource),
         },
+        [4] = {
+                .resources      = s5p_uart4_resource,
+                .nr_resources   = ARRAY_SIZE(s5p_uart4_resource),
+        },
+        [5] = {
+                .resources      = s5p_uart5_resource,
+                .nr_resources   = ARRAY_SIZE(s5p_uart5_resource),
+        },
 };
diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h
index 4e8fe08cb70d..bf28fadee7ae 100644
--- a/arch/arm/plat-s5p/include/plat/pll.h
+++ b/arch/arm/plat-s5p/include/plat/pll.h
@@ -47,6 +47,7 @@ static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
 }
 
 #define PLL46XX_KDIV_MASK       (0xFFFF)
+#define PLL4650C_KDIV_MASK      (0xFFF)
 #define PLL46XX_MDIV_MASK       (0x1FF)
 #define PLL46XX_PDIV_MASK       (0x3F)
 #define PLL46XX_SDIV_MASK       (0x7)
@@ -57,6 +58,7 @@ static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
 enum pll46xx_type_t {
         pll_4600,
         pll_4650,
+        pll_4650c,
 };
 
 static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
@@ -72,6 +74,11 @@ static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
         sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
         kdiv = pll_con1 & PLL46XX_KDIV_MASK;
 
+        if (pll_type == pll_4650c)
+                kdiv = pll_con1 & PLL4650C_KDIV_MASK;
+        else
+                kdiv = pll_con1 & PLL46XX_KDIV_MASK;
+
         tmp = baseclk;
 
         if (pll_type == pll_4600) {
diff --git a/arch/arm/plat-s5p/include/plat/s5p-clock.h b/arch/arm/plat-s5p/include/plat/s5p-clock.h
index 09418b1101fe..17036c898409 100644
--- a/arch/arm/plat-s5p/include/plat/s5p-clock.h
+++ b/arch/arm/plat-s5p/include/plat/s5p-clock.h
@@ -1,7 +1,7 @@
 /* linux/arch/arm/plat-s5p/include/plat/s5p-clock.h
  *
- * Copyright 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * Header file for s5p clock support
  *
@@ -20,6 +20,7 @@
 #define clk_fin_apll clk_ext_xtal_mux
 #define clk_fin_mpll clk_ext_xtal_mux
 #define clk_fin_epll clk_ext_xtal_mux
+#define clk_fin_dpll clk_ext_xtal_mux
 #define clk_fin_vpll clk_ext_xtal_mux
 #define clk_fin_hpll clk_ext_xtal_mux
 
@@ -30,6 +31,7 @@ extern struct clk s5p_clk_27m;
 extern struct clk clk_fout_apll;
 extern struct clk clk_fout_mpll;
 extern struct clk clk_fout_epll;
+extern struct clk clk_fout_dpll;
 extern struct clk clk_fout_vpll;
 extern struct clk clk_arm;
 extern struct clk clk_vpll;
@@ -37,8 +39,8 @@ extern struct clk clk_vpll;
 extern struct clksrc_sources clk_src_apll;
 extern struct clksrc_sources clk_src_mpll;
 extern struct clksrc_sources clk_src_epll;
+extern struct clksrc_sources clk_src_dpll;
 
-extern int s5p6440_clk48m_ctrl(struct clk *clk, int enable);
 extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable);
 
 #endif /* __ASM_PLAT_S5P_CLOCK_H */
diff --git a/arch/arm/plat-s5p/include/plat/s5p6440.h b/arch/arm/plat-s5p/include/plat/s5p6440.h
index a4cd75afeb3b..528585d2cafc 100644
--- a/arch/arm/plat-s5p/include/plat/s5p6440.h
+++ b/arch/arm/plat-s5p/include/plat/s5p6440.h
@@ -12,24 +12,23 @@
 
  /* Common init code for S5P6440 related SoCs */
 
-extern void s5p6440_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s5p6440_register_clocks(void);
 extern void s5p6440_setup_clocks(void);
 
 #ifdef CONFIG_CPU_S5P6440
 
-extern  int s5p6440_init(void);
+extern  int s5p64x0_init(void);
 extern void s5p6440_init_irq(void);
 extern void s5p6440_map_io(void);
 extern void s5p6440_init_clocks(int xtal);
 
-#define s5p6440_init_uarts s5p6440_common_init_uarts
+extern void s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 
 #else
 #define s5p6440_init_clocks NULL
 #define s5p6440_init_uarts NULL
 #define s5p6440_map_io NULL
-#define s5p6440_init NULL
+#define s5p64x0_init NULL
 #endif
 
 /* S5P6440 timer */
diff --git a/arch/arm/plat-s5p/include/plat/s5p6450.h b/arch/arm/plat-s5p/include/plat/s5p6450.h
new file mode 100644
index 000000000000..640a41c26be3
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/s5p6450.h
@@ -0,0 +1,36 @@
+/* arch/arm/plat-s5p/include/plat/s5p6450.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Header file for s5p6450 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Common init code for S5P6450 related SoCs */
+
+extern void s5p6450_register_clocks(void);
+extern void s5p6450_setup_clocks(void);
+
+#ifdef CONFIG_CPU_S5P6450
+
+extern  int s5p64x0_init(void);
+extern void s5p6450_init_irq(void);
+extern void s5p6450_map_io(void);
+extern void s5p6450_init_clocks(int xtal);
+
+extern void s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+
+#else
+#define s5p6450_init_clocks NULL
+#define s5p6450_init_uarts NULL
+#define s5p6450_map_io NULL
+#define s5p64x0_init NULL
+#endif
+
+/* S5P6450 timer */
+
+extern struct sys_timer s5p6450_timer;
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index 04d9521ddc9f..e8f2be2d67f2 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -435,7 +435,6 @@ static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state)
 static int s3c_adc_resume(struct platform_device *pdev)
 {
         struct adc_device *adc = platform_get_drvdata(pdev);
-        unsigned long flags;
 
         clk_enable(adc->clk);
         enable_irq(adc->irq);
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 90a20512d68d..e8d20b0bc50e 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -48,6 +48,9 @@
 #include <plat/clock.h>
 #include <plat/cpu.h>
 
+#include <linux/serial_core.h>
+#include <plat/regs-serial.h> /* for s3c24xx_uart_devs */
+
 /* clock information */
 
 static LIST_HEAD(clocks);
@@ -65,6 +68,28 @@ static int clk_null_enable(struct clk *clk, int enable)
         return 0;
 }
 
+static int dev_is_s3c_uart(struct device *dev)
+{
+        struct platform_device **pdev = s3c24xx_uart_devs;
+        int i;
+        for (i = 0; i < ARRAY_SIZE(s3c24xx_uart_devs); i++, pdev++)
+                if (*pdev && dev == &(*pdev)->dev)
+                        return 1;
+        return 0;
+}
+
+/*
+ * Serial drivers call get_clock() very early, before platform bus
+ * has been set up, this requires a special check to let them get
+ * a proper clock
+ */
+
+static int dev_is_platform_device(struct device *dev)
+{
+        return dev->bus == &platform_bus_type ||
+               (dev->bus == NULL && dev_is_s3c_uart(dev));
+}
+
 /* Clock API calls */
 
 struct clk *clk_get(struct device *dev, const char *id)
@@ -73,7 +98,7 @@ struct clk *clk_get(struct device *dev, const char *id)
         struct clk *clk = ERR_PTR(-ENOENT);
         int idno;
 
-        if (dev == NULL || dev->bus != &platform_bus_type)
+        if (dev == NULL || !dev_is_platform_device(dev))
                 idno = -1;
         else
                 idno = to_platform_device(dev)->id;
diff --git a/arch/arm/plat-samsung/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c
index 57b68a50f45e..e3d41eaed1ff 100644
--- a/arch/arm/plat-samsung/gpio-config.c
+++ b/arch/arm/plat-samsung/gpio-config.c
@@ -273,13 +273,13 @@ s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
         if (!chip)
                 return -EINVAL;
 
-        off = chip->chip.base - pin;
+        off = pin - chip->chip.base;
         shift = off * 2;
         reg = chip->base + 0x0C;
 
         drvstr = __raw_readl(reg);
-        drvstr = 0xffff & (0x3 << shift);
         drvstr = drvstr >> shift;
+        drvstr &= 0x3;
 
         return (__force s5p_gpio_drvstr_t)drvstr;
 }
@@ -296,11 +296,12 @@ int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
         if (!chip)
                 return -EINVAL;
 
-        off = chip->chip.base - pin;
+        off = pin - chip->chip.base;
         shift = off * 2;
         reg = chip->base + 0x0C;
 
         tmp = __raw_readl(reg);
+        tmp &= ~(0x3 << shift);
         tmp |= drvstr << shift;
 
         __raw_writel(tmp, reg);
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 6412933d6fbb..9addb3dfb4bc 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -79,7 +79,7 @@ extern struct sysdev_class s3c2442_sysclass;
 extern struct sysdev_class s3c2443_sysclass;
 extern struct sysdev_class s3c6410_sysclass;
 extern struct sysdev_class s3c64xx_sysclass;
-extern struct sysdev_class s5p6440_sysclass;
+extern struct sysdev_class s5p64x0_sysclass;
 extern struct sysdev_class s5p6442_sysclass;
 extern struct sysdev_class s5pv210_sysclass;
 
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 85f6f23a510f..7d448e138792 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -67,13 +67,15 @@ extern struct platform_device s5pv210_device_spi0;
 extern struct platform_device s5pv210_device_spi1;
 extern struct platform_device s5p6440_device_spi0;
 extern struct platform_device s5p6440_device_spi1;
+extern struct platform_device s5p6450_device_spi0;
+extern struct platform_device s5p6450_device_spi1;
 
 extern struct platform_device s3c_device_hwmon;
 
 extern struct platform_device s3c_device_nand;
 extern struct platform_device s3c_device_onenand;
 extern struct platform_device s3c64xx_device_onenand1;
-extern struct platform_device s5pc110_device_onenand;
+extern struct platform_device s5p_device_onenand;
 
 extern struct platform_device s3c_device_usbgadget;
 extern struct platform_device s3c_device_usb_hsotg;
@@ -95,6 +97,9 @@ extern struct platform_device s5p6442_device_spi;
 extern struct platform_device s5p6440_device_pcm;
 extern struct platform_device s5p6440_device_iis;
 
+extern struct platform_device s5p6450_device_iis0;
+extern struct platform_device s5p6450_device_pcm0;
+
 extern struct platform_device s5pc100_device_ac97;
 extern struct platform_device s5pc100_device_pcm0;
 extern struct platform_device s5pc100_device_pcm1;
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
index db4112c6f2be..1c6b92947c5d 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
@@ -143,12 +143,12 @@ extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
 /* Define values for the drvstr available for each gpio pin.
  *
  * These values control the value of the output signal driver strength,
- * configurable on most pins on the S5C series.
+ * configurable on most pins on the S5P series.
  */
-#define S5P_GPIO_DRVSTR_LV1     ((__force s5p_gpio_drvstr_t)0x00)
-#define S5P_GPIO_DRVSTR_LV2     ((__force s5p_gpio_drvstr_t)0x01)
-#define S5P_GPIO_DRVSTR_LV3     ((__force s5p_gpio_drvstr_t)0x10)
-#define S5P_GPIO_DRVSTR_LV4     ((__force s5p_gpio_drvstr_t)0x11)
+#define S5P_GPIO_DRVSTR_LV1     ((__force s5p_gpio_drvstr_t)0x0)
+#define S5P_GPIO_DRVSTR_LV2     ((__force s5p_gpio_drvstr_t)0x2)
+#define S5P_GPIO_DRVSTR_LV3     ((__force s5p_gpio_drvstr_t)0x1)
+#define S5P_GPIO_DRVSTR_LV4     ((__force s5p_gpio_drvstr_t)0x3)
 
 /**
  * s5c_gpio_get_drvstr() - get the driver streght value of a gpio pin
diff --git a/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h b/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h
index 5fe6721b57f7..810744213120 100644
--- a/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h
+++ b/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h
@@ -32,6 +32,12 @@ enum dma_ch {
         DMACH_UART2_TX,
         DMACH_UART3_RX,
         DMACH_UART3_TX,
+        DMACH_UART4_RX,
+        DMACH_UART4_TX,
+        DMACH_UART5_RX,
+        DMACH_UART5_TX,
+        DMACH_USI_RX,
+        DMACH_USI_TX,
         DMACH_IRDA,
         DMACH_I2S0_RX,
         DMACH_I2S0_TX,
@@ -64,6 +70,20 @@ enum dma_ch {
         DMACH_MSM_REQ2,
         DMACH_MSM_REQ1,
         DMACH_MSM_REQ0,
+        DMACH_SLIMBUS0_RX,
+        DMACH_SLIMBUS0_TX,
+        DMACH_SLIMBUS0AUX_RX,
+        DMACH_SLIMBUS0AUX_TX,
+        DMACH_SLIMBUS1_RX,
+        DMACH_SLIMBUS1_TX,
+        DMACH_SLIMBUS2_RX,
+        DMACH_SLIMBUS2_TX,
+        DMACH_SLIMBUS3_RX,
+        DMACH_SLIMBUS3_TX,
+        DMACH_SLIMBUS4_RX,
+        DMACH_SLIMBUS4_TX,
+        DMACH_SLIMBUS5_RX,
+        DMACH_SLIMBUS5_TX,
         /* END Marker, also used to denote a reserved channel */
         DMACH_MAX,
 };
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index e5aba8f95b79..ae8e802bdca8 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -65,7 +65,7 @@ struct s3c64xx_spi_info {
 extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
 extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
 extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
-extern void s5p6440_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
+extern void s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
 extern void s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
 
 #endif /* __S3C64XX_PLAT_SPI_H */
diff --git a/arch/arm/plat-tcc/Kconfig b/arch/arm/plat-tcc/Kconfig
new file mode 100644
index 000000000000..1bf499570f42
--- /dev/null
+++ b/arch/arm/plat-tcc/Kconfig
@@ -0,0 +1,20 @@
+if ARCH_TCC_926
+
+menu "Telechips ARM926-based CPUs"
+
+choice
+        prompt "Telechips CPU type:"
+        default ARCH_TCC8K
+
+config ARCH_TCC8K
+        bool TCC8000
+        select USB_ARCH_HAS_OHCI
+        help
+          Support for Telechips TCC8000 systems
+
+endchoice
+
+source "arch/arm/mach-tcc8k/Kconfig"
+
+endmenu
+endif
diff --git a/arch/arm/plat-tcc/Makefile b/arch/arm/plat-tcc/Makefile
new file mode 100644
index 000000000000..eceabc869b8f
--- /dev/null
+++ b/arch/arm/plat-tcc/Makefile
@@ -0,0 +1,3 @@
+# "Telechips Platform Common Modules"
+
+obj-y := clock.o system.o
diff --git a/arch/arm/plat-tcc/clock.c b/arch/arm/plat-tcc/clock.c
new file mode 100644
index 000000000000..f3ced10d5271
--- /dev/null
+++ b/arch/arm/plat-tcc/clock.c
@@ -0,0 +1,179 @@
+/*
+ * Clock framework for Telechips SoCs
+ * Based on arch/arm/plat-mxc/clock.c
+ *
+ * Copyright (C) 2004 - 2005 Nokia corporation
+ * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2010 Hans J. Koch, hjk@linutronix.de
+ *
+ * Licensed under the terms of the GPL v2.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/string.h>
+
+#include <mach/clock.h>
+#include <mach/hardware.h>
+
+static DEFINE_MUTEX(clocks_mutex);
+
+/*-------------------------------------------------------------------------
+ * Standard clock functions defined in include/linux/clk.h
+ *-------------------------------------------------------------------------*/
+
+static void __clk_disable(struct clk *clk)
+{
+        BUG_ON(clk->refcount == 0);
+
+        if (!(--clk->refcount) && clk->disable) {
+                /* Unconditionally disable the clock in hardware */
+                clk->disable(clk);
+                /* recursively disable parents */
+                if (clk->parent)
+                        __clk_disable(clk->parent);
+        }
+}
+
+static int __clk_enable(struct clk *clk)
+{
+        int ret = 0;
+
+        if (clk->refcount++ == 0 && clk->enable) {
+                if (clk->parent)
+                        ret = __clk_enable(clk->parent);
+                if (ret)
+                        return ret;
+                else
+                        return clk->enable(clk);
+        }
+
+        return 0;
+}
+
+/* This function increments the reference count on the clock and enables the
+ * clock if not already enabled. The parent clock tree is recursively enabled
+ */
+int clk_enable(struct clk *clk)
+{
+        int ret = 0;
+
+        if (!clk)
+                return -EINVAL;
+
+        mutex_lock(&clocks_mutex);
+        ret = __clk_enable(clk);
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(clk_enable);
+
+/* This function decrements the reference count on the clock and disables
+ * the clock when reference count is 0. The parent clock tree is
+ * recursively disabled
+ */
+void clk_disable(struct clk *clk)
+{
+        if (!clk)
+                return;
+
+        mutex_lock(&clocks_mutex);
+        __clk_disable(clk);
+        mutex_unlock(&clocks_mutex);
+}
+EXPORT_SYMBOL_GPL(clk_disable);
+
+/* Retrieve the *current* clock rate. If the clock itself
+ * does not provide a special calculation routine, ask
+ * its parent and so on, until one is able to return
+ * a valid clock rate
+ */
+unsigned long clk_get_rate(struct clk *clk)
+{
+        if (!clk)
+                return 0UL;
+
+        if (clk->get_rate)
+                return clk->get_rate(clk);
+
+        return clk_get_rate(clk->parent);
+}
+EXPORT_SYMBOL_GPL(clk_get_rate);
+
+/* Round the requested clock rate to the nearest supported
+ * rate that is less than or equal to the requested rate.
+ * This is dependent on the clock's current parent.
+ */
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        if (!clk)
+                return 0;
+        if (!clk->round_rate)
+                return 0;
+
+        return clk->round_rate(clk, rate);
+}
+EXPORT_SYMBOL_GPL(clk_round_rate);
+
+/* Set the clock to the requested clock rate. The rate must
+ * match a supported rate exactly based on what clk_round_rate returns
+ */
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        int ret = -EINVAL;
+
+        if (!clk)
+                return ret;
+        if (!clk->set_rate || !rate)
+                return ret;
+
+        mutex_lock(&clocks_mutex);
+        ret = clk->set_rate(clk, rate);
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_rate);
+
+/* Set the clock's parent to another clock source */
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        struct clk *old;
+        int ret = -EINVAL;
+
+        if (!clk)
+                return ret;
+        if (!clk->set_parent || !parent)
+                return ret;
+
+        mutex_lock(&clocks_mutex);
+        old = clk->parent;
+        if (clk->refcount)
+                __clk_enable(parent);
+        ret = clk->set_parent(clk, parent);
+        if (ret)
+                old = parent;
+        if (clk->refcount)
+                __clk_disable(old);
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_parent);
+
+/* Retrieve the clock's parent clock source */
+struct clk *clk_get_parent(struct clk *clk)
+{
+        if (!clk)
+                return NULL;
+
+        return clk->parent;
+}
+EXPORT_SYMBOL_GPL(clk_get_parent);
diff --git a/arch/arm/plat-tcc/include/mach/clkdev.h b/arch/arm/plat-tcc/include/mach/clkdev.h
new file mode 100644
index 000000000000..04b37a89801c
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/plat-tcc/include/mach/clock.h b/arch/arm/plat-tcc/include/mach/clock.h
new file mode 100644
index 000000000000..a12f58ad71a8
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/clock.h
@@ -0,0 +1,48 @@
+/*
+ * Low level clock header file for Telechips TCC architecture
+ * (C) 2010 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the GPL v2.
+ */
+
+#ifndef __ASM_ARCH_TCC_CLOCK_H__
+#define __ASM_ARCH_TCC_CLOCK_H__
+
+#ifndef __ASSEMBLY__
+
+struct clk {
+        struct clk *parent;
+        /* id number of a root clock, 0 for normal clocks */
+        int root_id;
+        /* Reference count of clock enable/disable */
+        int refcount;
+        /* Address of associated BCLKCTRx register. Must be set. */
+        void __iomem *bclkctr;
+        /* Bit position for BCLKCTRx. Must be set. */
+        int bclk_shift;
+        /* Address of ACLKxxx register, if any. */
+        void __iomem *aclkreg;
+        /* get the current clock rate (always a fresh value) */
+        unsigned long (*get_rate) (struct clk *);
+        /* Function ptr to set the clock to a new rate. The rate must match a
+           supported rate returned from round_rate. Leave blank if clock is not
+           programmable */
+        int (*set_rate) (struct clk *, unsigned long);
+        /* Function ptr to round the requested clock rate to the nearest
+           supported rate that is less than or equal to the requested rate. */
+        unsigned long (*round_rate) (struct clk *, unsigned long);
+        /* Function ptr to enable the clock. Leave blank if clock can not
+           be gated. */
+        int (*enable) (struct clk *);
+        /* Function ptr to disable the clock. Leave blank if clock can not
+           be gated. */
+        void (*disable) (struct clk *);
+        /* Function ptr to set the parent clock of the clock. */
+        int (*set_parent) (struct clk *, struct clk *);
+};
+
+int clk_register(struct clk *clk);
+void clk_unregister(struct clk *clk);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
diff --git a/arch/arm/plat-tcc/include/mach/debug-macro.S b/arch/arm/plat-tcc/include/mach/debug-macro.S
new file mode 100644
index 000000000000..97537845df64
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/debug-macro.S
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 1994-1999 Russell King
+ * Copyright (C) 2008-2009 Telechips
+ * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+                .macro  addruart,rx,tmp
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0x90000000        @ physical base address
+                movne   \rx, #0xF1000000        @ virtual base
+                orr     \rx, \rx, #0x00007000   @ UART0
+                .endm
+
+                .macro  senduart,rd,rx
+                strb    \rd, [\rx, #0x44]
+                .endm
+
+                .macro  waituart,rd,rx
+                .endm
+
+                .macro  busyuart,rd,rx
+1001:
+                ldr \rd, [\rx, #0x14]
+                tst \rd, #0x20
+
+                beq 1001b
+                .endm
diff --git a/arch/arm/plat-tcc/include/mach/entry-macro.S b/arch/arm/plat-tcc/include/mach/entry-macro.S
new file mode 100644
index 000000000000..748f401e4b6d
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/entry-macro.S
@@ -0,0 +1,68 @@
+/*
+ * include/asm-arm/arch-tcc83x/entry-macro.S
+ *
+ * Author : <linux@telechips.com>
+ * Created: June 10, 2008
+ * Description: Low-level IRQ helper macros for Telechips-based platforms
+ *
+ * Copyright (C) 2008-2009 Telechips
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+                ldr     \base, =0xF2003000 @ base address of PIC registers
+
+                @@ read MREQ register of PIC0
+
+                mov     \irqnr, #0
+                ldr     \irqstat, [\base, #0x00000014 ] @ lower 32 interrupts
+                cmp     \irqstat, #0
+                bne     1001f
+
+                @@ read MREQ register of PIC1
+
+                ldr     \irqstat, [\base, #0x00000094]  @ upper 32 interrupts
+                cmp     \irqstat, #0
+                beq     1002f
+                mov     \irqnr, #0x20
+
+1001:
+                movs    \tmp, \irqstat, lsl #16
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #16
+
+                movs    \tmp, \irqstat, lsl #8
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #8
+
+                movs    \tmp, \irqstat, lsl #4
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #4
+
+                movs    \tmp, \irqstat, lsl #2
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #2
+
+                movs    \tmp, \irqstat, lsl #1
+                addeq   \irqnr, \irqnr, #1
+                orrs    \base, \base, #1
+1002:
+                @@ exit here, Z flag unset if IRQ
+
+        .endm
diff --git a/arch/arm/plat-tcc/include/mach/hardware.h b/arch/arm/plat-tcc/include/mach/hardware.h
new file mode 100644
index 000000000000..e70d126ccaf3
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/hardware.h
@@ -0,0 +1,43 @@
+/*
+ * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
+ * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
+ *                          and Dirk Behme <dirk.behme@de.bosch.com>
+ * Rewritten by:    <linux@telechips.com>
+ * Description: Hardware definitions for TCC8300 processors and boards
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Copyright (C) 2008-2009 Telechips
+ *
+ * Modifications for mainline (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GNU Pulic License version 2.
+ */
+
+#ifndef __ASM_ARCH_TCC_HARDWARE_H
+#define __ASM_ARCH_TCC_HARDWARE_H
+
+#include <asm/sizes.h>
+#ifndef __ASSEMBLER__
+#include <asm/types.h>
+#endif
+#include <mach/io.h>
+
+/*
+ * ----------------------------------------------------------------------------
+ * Clocks
+ * ----------------------------------------------------------------------------
+ */
+#define CLKGEN_REG_BASE         0xfffece00
+#define ARM_CKCTL               (CLKGEN_REG_BASE + 0x0)
+#define ARM_IDLECT1             (CLKGEN_REG_BASE + 0x4)
+#define ARM_IDLECT2             (CLKGEN_REG_BASE + 0x8)
+#define ARM_EWUPCT              (CLKGEN_REG_BASE + 0xC)
+#define ARM_RSTCT1              (CLKGEN_REG_BASE + 0x10)
+#define ARM_RSTCT2              (CLKGEN_REG_BASE + 0x14)
+#define ARM_SYSST               (CLKGEN_REG_BASE + 0x18)
+#define ARM_IDLECT3             (CLKGEN_REG_BASE + 0x24)
+
+/* DPLL control registers */
+#define DPLL_CTL                0xfffecf00
+
+#endif  /* __ASM_ARCH_TCC_HARDWARE_H */
diff --git a/arch/arm/plat-tcc/include/mach/io.h b/arch/arm/plat-tcc/include/mach/io.h
new file mode 100644
index 000000000000..3e911d3ea0f1
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/io.h
@@ -0,0 +1,23 @@
+/*
+ * IO definitions for TCC8000 processors and boards
+ *
+ * Copyright (C) 1997-1999 Russell King
+ * Copyright (C) 2008-2009 Telechips
+ * Copyright (C) 2010 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GNU Public License version 2.
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a)                 __typesafe_io(a)
+#define __mem_pci(a)            (a)
+
+#endif
diff --git a/arch/arm/plat-tcc/include/mach/irqs.h b/arch/arm/plat-tcc/include/mach/irqs.h
new file mode 100644
index 000000000000..da863894d498
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/irqs.h
@@ -0,0 +1,83 @@
+/*
+ * IRQ definitions for TCC8xxx
+ *
+ * Copyright (C) 2008-2009 Telechips
+ * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GPL v2.
+ *
+ */
+
+#ifndef __ASM_ARCH_TCC_IRQS_H
+#define __ASM_ARCH_TCC_IRQS_H
+
+#define NR_IRQS 64
+
+/* PIC0 interrupts */
+#define INT_ADMA1       0
+#define INT_BDMA        1
+#define INT_ADMA0       2
+#define INT_GDMA1       3
+#define INT_I2S0RX      4
+#define INT_I2S0TX      5
+#define INT_TC          6
+#define INT_UART0       7
+#define INT_USBD        8
+#define INT_SPI0TX      9
+#define INT_UDMA        10
+#define INT_LIRQ        11
+#define INT_GDMA2       12
+#define INT_GDMA0       13
+#define INT_TC32        14
+#define INT_LCD         15
+#define INT_ADC         16
+#define INT_I2C         17
+#define INT_RTCP        18
+#define INT_RTCA        19
+#define INT_NFC         20
+#define INT_SD0         21
+#define INT_GSB0        22
+#define INT_PK          23
+#define INT_USBH0       24
+#define INT_USBH1       25
+#define INT_G2D         26
+#define INT_ECC         27
+#define INT_SPI0RX      28
+#define INT_UART1       29
+#define INT_MSCL        30
+#define INT_GSB1        31
+/* PIC1 interrupts */
+#define INT_E0          32
+#define INT_E1          33
+#define INT_E2          34
+#define INT_E3          35
+#define INT_E4          36
+#define INT_E5          37
+#define INT_E6          38
+#define INT_E7          39
+#define INT_UART2       40
+#define INT_UART3       41
+#define INT_SPI1TX      42
+#define INT_SPI1RX      43
+#define INT_GSB2        44
+#define INT_SPDIF       45
+#define INT_CDIF        46
+#define INT_VBON        47
+#define INT_VBOFF       48
+#define INT_SD1         49
+#define INT_UART4       50
+#define INT_GDMA3       51
+#define INT_I2S1RX      52
+#define INT_I2S1TX      53
+#define INT_CAN0        54
+#define INT_CAN1        55
+#define INT_GSB3        56
+#define INT_KRST        57
+#define INT_UNUSED      58
+#define INT_SD0D3       59
+#define INT_SD1D3       60
+#define INT_GPS0        61
+#define INT_GPS1        62
+#define INT_GPS2        63
+
+#endif  /* ASM_ARCH_TCC_IRQS_H */
diff --git a/arch/arm/plat-tcc/include/mach/memory.h b/arch/arm/plat-tcc/include/mach/memory.h
new file mode 100644
index 000000000000..cd91ba8a670b
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/memory.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Copyright (C) 2008-2009 Telechips
+ * Copyright (C) 2010 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GPL v2.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET             UL(0x20000000)
+
+#endif
diff --git a/arch/arm/plat-tcc/include/mach/system.h b/arch/arm/plat-tcc/include/mach/system.h
new file mode 100644
index 000000000000..909e6035d843
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/system.h
@@ -0,0 +1,31 @@
+/*
+ * Author: <linux@telechips.com>
+ * Created: June 10, 2008
+ * Description: LINUX SYSTEM FUNCTIONS for TCC83x
+ *
+ * Copyright (C) 2008-2009 Telechips
+ *
+ * Licensed under the terms of the GPL v2.
+ *
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+#include <linux/clk.h>
+
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+
+extern void plat_tcc_reboot(void);
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+        plat_tcc_reboot();
+}
+
+#endif
diff --git a/arch/arm/plat-tcc/include/mach/tcc8k-regs.h b/arch/arm/plat-tcc/include/mach/tcc8k-regs.h
new file mode 100644
index 000000000000..1d9428295332
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/tcc8k-regs.h
@@ -0,0 +1,807 @@
+/*
+ * Telechips TCC8000 register definitions
+ *
+ * (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GPLv2.
+ */
+
+#ifndef TCC8K_REGS_H
+#define TCC8K_REGS_H
+
+#include <linux/types.h>
+
+#define EXT_SDRAM_BASE          0x20000000
+#define INT_SRAM_BASE           0x30000000
+#define INT_SRAM_SIZE           SZ_32K
+#define CS0_BASE                0x40000000
+#define CS1_BASE                0x50000000
+#define CS1_SIZE                SZ_64K
+#define CS2_BASE                0x60000000
+#define CS3_BASE                0x70000000
+#define AHB_PERI_BASE           0x80000000
+#define AHB_PERI_SIZE           SZ_64K
+#define APB0_PERI_BASE          0x90000000
+#define APB0_PERI_SIZE          SZ_128K
+#define APB1_PERI_BASE          0x98000000
+#define APB1_PERI_SIZE          SZ_128K
+#define DATA_TCM_BASE           0xa0000000
+#define DATA_TCM_SIZE           SZ_8K
+#define EXT_MEM_CTRL_BASE       0xf0000000
+#define EXT_MEM_CTRL_SIZE       SZ_4K
+
+#define CS1_BASE_VIRT           (void __iomem *)0xf7000000
+#define AHB_PERI_BASE_VIRT      (void __iomem *)0xf4000000
+#define APB0_PERI_BASE_VIRT     (void __iomem *)0xf1000000
+#define APB1_PERI_BASE_VIRT     (void __iomem *)0xf2000000
+#define EXT_MEM_CTRL_BASE_VIRT  (void __iomem *)0xf3000000
+#define INT_SRAM_BASE_VIRT      (void __iomem *)0xf5000000
+#define DATA_TCM_BASE_VIRT      (void __iomem *)0xf6000000
+
+#define __REG(x)     (*((volatile u32 *)(x)))
+
+/* USB Device Controller Registers */
+#define UDC_BASE        (AHB_PERI_BASE_VIRT + 0x8000)
+#define UDC_BASE_PHYS   (AHB_PERI_BASE + 0x8000)
+
+#define UDC_IR_OFFS             0x00
+#define UDC_EIR_OFFS            0x04
+#define UDC_EIER_OFFS           0x08
+#define UDC_FAR_OFFS            0x0c
+#define UDC_FNR_OFFS            0x10
+#define UDC_EDR_OFFS            0x14
+#define UDC_RT_OFFS             0x18
+#define UDC_SSR_OFFS            0x1c
+#define UDC_SCR_OFFS            0x20
+#define UDC_EP0SR_OFFS          0x24
+#define UDC_EP0CR_OFFS          0x28
+
+#define UDC_ESR_OFFS            0x2c
+#define UDC_ECR_OFFS            0x30
+#define UDC_BRCR_OFFS           0x34
+#define UDC_BWCR_OFFS           0x38
+#define UDC_MPR_OFFS            0x3c
+#define UDC_DCR_OFFS            0x40
+#define UDC_DTCR_OFFS           0x44
+#define UDC_DFCR_OFFS           0x48
+#define UDC_DTTCR1_OFFS         0x4c
+#define UDC_DTTCR2_OFFS         0x50
+#define UDC_ESR2_OFFS           0x54
+
+#define UDC_SCR2_OFFS           0x58
+#define UDC_EP0BUF_OFFS         0x60
+#define UDC_EP1BUF_OFFS         0x64
+#define UDC_EP2BUF_OFFS         0x68
+#define UDC_EP3BUF_OFFS         0x6c
+#define UDC_PLICR_OFFS          0xa0
+#define UDC_PCR_OFFS            0xa4
+
+#define UDC_UPCR0_OFFS          0xc8
+#define UDC_UPCR1_OFFS          0xcc
+#define UDC_UPCR2_OFFS          0xd0
+#define UDC_UPCR3_OFFS          0xd4
+
+/* Bits in UDC_EIR */
+#define UDC_EIR_EP0I            (1 << 0)
+#define UDC_EIR_EP1I            (1 << 1)
+#define UDC_EIR_EP2I            (1 << 2)
+#define UDC_EIR_EP3I            (1 << 3)
+#define UDC_EIR_EPI_MASK        0x0f
+
+/* Bits in UDC_EIER */
+#define UDC_EIER_EP0IE          (1 << 0)
+#define UDC_EIER_EP1IE          (1 << 1)
+#define UDC_EIER_EP2IE          (1 << 2)
+#define UDC_EIER_EP3IE          (1 << 3)
+
+/* Bits in UDC_FNR */
+#define UDC_FNR_FN_MASK         0x7ff
+#define UDC_FNR_SM              (1 << 13)
+#define UDC_FNR_FTL             (1 << 14)
+
+/* Bits in UDC_SSR */
+#define UDC_SSR_HFRES           (1 << 0)
+#define UDC_SSR_HFSUSP          (1 << 1)
+#define UDC_SSR_HFRM            (1 << 2)
+#define UDC_SSR_SDE             (1 << 3)
+#define UDC_SSR_HSP             (1 << 4)
+#define UDC_SSR_DM              (1 << 5)
+#define UDC_SSR_DP              (1 << 6)
+#define UDC_SSR_TBM             (1 << 7)
+#define UDC_SSR_VBON            (1 << 8)
+#define UDC_SSR_VBOFF           (1 << 9)
+#define UDC_SSR_EOERR           (1 << 10)
+#define UDC_SSR_DCERR           (1 << 11)
+#define UDC_SSR_TCERR           (1 << 12)
+#define UDC_SSR_BSERR           (1 << 13)
+#define UDC_SSR_TMERR           (1 << 14)
+#define UDC_SSR_BAERR           (1 << 15)
+
+/* Bits in UDC_SCR */
+#define UDC_SCR_HRESE           (1 << 0)
+#define UDC_SCR_HSSPE           (1 << 1)
+#define UDC_SCR_RRDE            (1 << 5)
+#define UDC_SCR_SPDEN           (1 << 6)
+#define UDC_SCR_DIEN            (1 << 12)
+
+/* Bits in UDC_EP0SR */
+#define UDC_EP0SR_RSR           (1 << 0)
+#define UDC_EP0SR_TST           (1 << 1)
+#define UDC_EP0SR_SHT           (1 << 4)
+#define UDC_EP0SR_LWO           (1 << 6)
+
+/* Bits in UDC_EP0CR */
+#define UDC_EP0CR_ESS           (1 << 1)
+
+/* Bits in UDC_ESR */
+#define UDC_ESR_RPS             (1 << 0)
+#define UDC_ESR_TPS             (1 << 1)
+#define UDC_ESR_LWO             (1 << 4)
+#define UDC_ESR_FFS             (1 << 6)
+
+/* Bits in UDC_ECR */
+#define UDC_ECR_ESS             (1 << 1)
+#define UDC_ECR_CDP             (1 << 2)
+
+#define UDC_ECR_FLUSH           (1 << 6)
+#define UDC_ECR_DUEN            (1 << 7)
+
+/* Bits in UDC_UPCR0 */
+#define UDC_UPCR0_VBD           (1 << 1)
+#define UDC_UPCR0_VBDS          (1 << 6)
+#define UDC_UPCR0_RCD_12        (0x0 << 9)
+#define UDC_UPCR0_RCD_24        (0x1 << 9)
+#define UDC_UPCR0_RCD_48        (0x2 << 9)
+#define UDC_UPCR0_RCS_EXT       (0x1 << 11)
+#define UDC_UPCR0_RCS_XTAL      (0x0 << 11)
+
+/* Bits in UDC_UPCR1 */
+#define UDC_UPCR1_CDT(x)        ((x) << 0)
+#define UDC_UPCR1_OTGT(x)       ((x) << 3)
+#define UDC_UPCR1_SQRXT(x)      ((x) << 8)
+#define UDC_UPCR1_TXFSLST(x)    ((x) << 12)
+
+/* Bits in UDC_UPCR2 */
+#define UDC_UPCR2_TP            (1 << 0)
+#define UDC_UPCR2_TXRT(x)       ((x) << 2)
+#define UDC_UPCR2_TXVRT(x)      ((x) << 5)
+#define UDC_UPCR2_OPMODE(x)     ((x) << 9)
+#define UDC_UPCR2_XCVRSEL(x)    ((x) << 12)
+#define UDC_UPCR2_TM            (1 << 14)
+
+/* USB Host Controller registers */
+#define USBH0_BASE      (AHB_PERI_BASE_VIRT + 0xb000)
+#define USBH1_BASE      (AHB_PERI_BASE_VIRT + 0xb800)
+
+#define OHCI_INT_ENABLE_OFFS    0x10
+
+#define RH_DESCRIPTOR_A_OFFS    0x48
+#define RH_DESCRIPTOR_B_OFFS    0x4c
+
+#define USBHTCFG0_OFFS          0x100
+#define USBHHCFG0_OFFS          0x104
+#define USBHHCFG1_OFFS          0x104
+
+/* DMA controller registers */
+#define DMAC0_BASE      (AHB_PERI_BASE + 0x4000)
+#define DMAC1_BASE      (AHB_PERI_BASE + 0xa000)
+#define DMAC2_BASE      (AHB_PERI_BASE + 0x4800)
+#define DMAC3_BASE      (AHB_PERI_BASE + 0xa800)
+
+#define DMAC_CH_OFFSET(ch)      (ch * 0x30)
+
+#define ST_SADR_OFFS            0x00
+#define SPARAM_OFFS             0x04
+#define C_SADR_OFFS             0x0c
+#define ST_DADR_OFFS            0x10
+#define DPARAM_OFFS             0x14
+#define C_DADR_OFFS             0x1c
+#define HCOUNT_OFFS             0x20
+#define CHCTRL_OFFS             0x24
+#define RPTCTRL_OFFS            0x28
+#define EXTREQ_A_OFFS           0x2c
+
+/* Bits in CHCTRL register */
+#define CHCTRL_EN               (1 << 0)
+
+#define CHCTRL_IEN              (1 << 2)
+#define CHCTRL_FLAG             (1 << 3)
+#define CHCTRL_WSIZE8           (0 << 4)
+#define CHCTRL_WSIZE16          (1 << 4)
+#define CHCTRL_WSIZE32          (2 << 4)
+
+#define CHCTRL_BSIZE1           (0 << 6)
+#define CHCTRL_BSIZE2           (1 << 6)
+#define CHCTRL_BSIZE4           (2 << 6)
+#define CHCTRL_BSIZE8           (3 << 6)
+
+#define CHCTRL_TYPE_SINGLE_E    (0 << 8)
+#define CHCTRL_TYPE_HW          (1 << 8)
+#define CHCTRL_TYPE_SW          (2 << 8)
+#define CHCTRL_TYPE_SINGLE_L    (3 << 8)
+
+#define CHCTRL_BST              (1 << 10)
+
+/* Use DMA controller 0, channel 2 for USB */
+#define USB_DMA_BASE            (DMAC0_BASE + DMAC_CH_OFFSET(2))
+
+/* NAND flash controller registers */
+#define NFC_BASE        (AHB_PERI_BASE_VIRT + 0xd000)
+#define NFC_BASE_PHYS   (AHB_PERI_BASE + 0xd000)
+
+#define NFC_CMD_OFFS            0x00
+#define NFC_LADDR_OFFS          0x04
+#define NFC_BADDR_OFFS          0x08
+#define NFC_SADDR_OFFS          0x0c
+#define NFC_WDATA_OFFS          0x10
+#define NFC_LDATA_OFFS          0x20
+#define NFC_SDATA_OFFS          0x40
+#define NFC_CTRL_OFFS           0x50
+#define NFC_PSTART_OFFS         0x54
+#define NFC_RSTART_OFFS         0x58
+#define NFC_DSIZE_OFFS          0x5c
+#define NFC_IREQ_OFFS           0x60
+#define NFC_RST_OFFS            0x64
+#define NFC_CTRL1_OFFS          0x68
+#define NFC_MDATA_OFFS          0x70
+
+#define NFC_WDATA_PHYS_ADDR     (NFC_BASE_PHYS + NFC_WDATA_OFFS)
+
+/* Bits in NFC_CTRL */
+#define NFC_CTRL_BHLD_MASK      (0xf << 0)
+#define NFC_CTRL_BPW_MASK       (0xf << 4)
+#define NFC_CTRL_BSTP_MASK      (0xf << 8)
+#define NFC_CTRL_CADDR_MASK     (0x7 << 12)
+#define NFC_CTRL_CADDR_1        (0x0 << 12)
+#define NFC_CTRL_CADDR_2        (0x1 << 12)
+#define NFC_CTRL_CADDR_3        (0x2 << 12)
+#define NFC_CTRL_CADDR_4        (0x3 << 12)
+#define NFC_CTRL_CADDR_5        (0x4 << 12)
+#define NFC_CTRL_MSK            (1 << 15)
+#define NFC_CTRL_PSIZE256       (0 << 16)
+#define NFC_CTRL_PSIZE512       (1 << 16)
+#define NFC_CTRL_PSIZE1024      (2 << 16)
+#define NFC_CTRL_PSIZE2048      (3 << 16)
+#define NFC_CTRL_PSIZE4096      (4 << 16)
+#define NFC_CTRL_PSIZE_MASK     (7 << 16)
+#define NFC_CTRL_BSIZE1         (0 << 19)
+#define NFC_CTRL_BSIZE2         (1 << 19)
+#define NFC_CTRL_BSIZE4         (2 << 19)
+#define NFC_CTRL_BSIZE8         (3 << 19)
+#define NFC_CTRL_BSIZE_MASK     (3 << 19)
+#define NFC_CTRL_RDY            (1 << 21)
+#define NFC_CTRL_CS0SEL         (1 << 22)
+#define NFC_CTRL_CS1SEL         (1 << 23)
+#define NFC_CTRL_CS2SEL         (1 << 24)
+#define NFC_CTRL_CS3SEL         (1 << 25)
+#define NFC_CTRL_CSMASK         (0xf << 22)
+#define NFC_CTRL_BW             (1 << 26)
+#define NFC_CTRL_FS             (1 << 27)
+#define NFC_CTRL_DEN            (1 << 28)
+#define NFC_CTRL_READ_IEN       (1 << 29)
+#define NFC_CTRL_PROG_IEN       (1 << 30)
+#define NFC_CTRL_RDY_IEN        (1 << 31)
+
+/* Bits in NFC_IREQ */
+#define NFC_IREQ_IRQ0           (1 << 0)
+#define NFC_IREQ_IRQ1           (1 << 1)
+#define NFC_IREQ_IRQ2           (1 << 2)
+
+#define NFC_IREQ_FLAG0          (1 << 4)
+#define NFC_IREQ_FLAG1          (1 << 5)
+#define NFC_IREQ_FLAG2          (1 << 6)
+
+/* MMC controller registers */
+#define MMC0_BASE       (AHB_PERI_BASE_VIRT + 0xe000)
+#define MMC1_BASE       (AHB_PERI_BASE_VIRT + 0xe800)
+
+/* UART base addresses */
+
+#define UART0_BASE      (APB0_PERI_BASE_VIRT + 0x07000)
+#define UART0_BASE_PHYS (APB0_PERI_BASE + 0x07000)
+#define UART1_BASE      (APB0_PERI_BASE_VIRT + 0x08000)
+#define UART1_BASE_PHYS (APB0_PERI_BASE + 0x08000)
+#define UART2_BASE      (APB0_PERI_BASE_VIRT + 0x09000)
+#define UART2_BASE_PHYS (APB0_PERI_BASE + 0x09000)
+#define UART3_BASE      (APB0_PERI_BASE_VIRT + 0x0a000)
+#define UART3_BASE_PHYS (APB0_PERI_BASE + 0x0a000)
+#define UART4_BASE      (APB0_PERI_BASE_VIRT + 0x15000)
+#define UART4_BASE_PHYS (APB0_PERI_BASE + 0x15000)
+
+#define UART_BASE       UART0_BASE
+#define UART_BASE_PHYS  UART0_BASE_PHYS
+
+/* ECC controller */
+#define ECC_CTR_BASE    (APB0_PERI_BASE_VIRT + 0xd000)
+
+#define ECC_CTRL_OFFS           0x00
+#define ECC_BASE_OFFS           0x04
+#define ECC_MASK_OFFS           0x08
+#define ECC_CLEAR_OFFS          0x0c
+#define ECC4_0_OFFS             0x10
+#define ECC4_1_OFFS             0x14
+
+#define ECC_EADDR0_OFFS         0x50
+
+#define ECC_ERRNUM_OFFS         0x90
+#define ECC_IREQ_OFFS           0x94
+
+/* Bits in ECC_CTRL */
+#define ECC_CTRL_ECC4_DIEN      (1 << 28)
+#define ECC_CTRL_ECC8_DIEN      (1 << 29)
+#define ECC_CTRL_ECC12_DIEN     (1 << 30)
+#define ECC_CTRL_ECC_DISABLE    0x0
+#define ECC_CTRL_ECC_SLC_ENC    0x8
+#define ECC_CTRL_ECC_SLC_DEC    0x9
+#define ECC_CTRL_ECC4_ENC       0xa
+#define ECC_CTRL_ECC4_DEC       0xb
+#define ECC_CTRL_ECC8_ENC       0xc
+#define ECC_CTRL_ECC8_DEC       0xd
+#define ECC_CTRL_ECC12_ENC      0xe
+#define ECC_CTRL_ECC12_DEC      0xf
+
+/* Bits in ECC_IREQ */
+#define ECC_IREQ_E4DI           (1 << 4)
+
+#define ECC_IREQ_E4DF           (1 << 20)
+#define ECC_IREQ_E4EF           (1 << 21)
+
+/* Interrupt controller */
+
+#define PIC0_BASE       (APB1_PERI_BASE_VIRT + 0x3000)
+#define PIC0_BASE_PHYS  (APB1_PERI_BASE + 0x3000)
+
+#define PIC0_IEN_OFFS           0x00
+#define PIC0_CREQ_OFFS          0x04
+#define PIC0_IREQ_OFFS          0x08
+#define PIC0_IRQSEL_OFFS        0x0c
+#define PIC0_SRC_OFFS           0x10
+#define PIC0_MREQ_OFFS          0x14
+#define PIC0_TSTREQ_OFFS        0x18
+#define PIC0_POL_OFFS           0x1c
+#define PIC0_IRQ_OFFS           0x20
+#define PIC0_FIQ_OFFS           0x24
+#define PIC0_MIRQ_OFFS          0x28
+#define PIC0_MFIQ_OFFS          0x2c
+#define PIC0_TMODE_OFFS         0x30
+#define PIC0_SYNC_OFFS          0x34
+#define PIC0_WKUP_OFFS          0x38
+#define PIC0_TMODEA_OFFS        0x3c
+#define PIC0_INTOEN_OFFS        0x40
+#define PIC0_MEN0_OFFS          0x44
+#define PIC0_MEN_OFFS           0x48
+
+#define PIC0_IEN                __REG(PIC0_BASE + PIC0_IEN_OFFS)
+#define PIC0_IEN_PHYS           __REG(PIC0_BASE_PHYS + PIC0_IEN_OFFS)
+#define PIC0_CREQ               __REG(PIC0_BASE + PIC0_CREQ_OFFS)
+#define PIC0_CREQ_PHYS          __REG(PIC0_BASE_PHYS + PIC0_CREQ_OFFS)
+#define PIC0_IREQ               __REG(PIC0_BASE + PIC0_IREQ_OFFS)
+#define PIC0_IRQSEL             __REG(PIC0_BASE + PIC0_IRQSEL_OFFS)
+#define PIC0_IRQSEL_PHYS        __REG(PIC0_BASE_PHYS + PIC0_IRQSEL_OFFS)
+#define PIC0_SRC                __REG(PIC0_BASE + PIC0_SRC_OFFS)
+#define PIC0_MREQ               __REG(PIC0_BASE + PIC0_MREQ_OFFS)
+#define PIC0_TSTREQ             __REG(PIC0_BASE + PIC0_TSTREQ_OFFS)
+#define PIC0_POL                __REG(PIC0_BASE + PIC0_POL_OFFS)
+#define PIC0_IRQ                __REG(PIC0_BASE + PIC0_IRQ_OFFS)
+#define PIC0_FIQ                __REG(PIC0_BASE + PIC0_FIQ_OFFS)
+#define PIC0_MIRQ               __REG(PIC0_BASE + PIC0_MIRQ_OFFS)
+#define PIC0_MFIQ               __REG(PIC0_BASE + PIC0_MFIQ_OFFS)
+#define PIC0_TMODE              __REG(PIC0_BASE + PIC0_TMODE_OFFS)
+#define PIC0_TMODE_PHYS         __REG(PIC0_BASE_PHYS + PIC0_TMODE_OFFS)
+#define PIC0_SYNC               __REG(PIC0_BASE + PIC0_SYNC_OFFS)
+#define PIC0_WKUP               __REG(PIC0_BASE + PIC0_WKUP_OFFS)
+#define PIC0_TMODEA             __REG(PIC0_BASE + PIC0_TMODEA_OFFS)
+#define PIC0_INTOEN             __REG(PIC0_BASE + PIC0_INTOEN_OFFS)
+#define PIC0_MEN0               __REG(PIC0_BASE + PIC0_MEN0_OFFS)
+#define PIC0_MEN                __REG(PIC0_BASE + PIC0_MEN_OFFS)
+
+#define PIC1_BASE       (APB1_PERI_BASE_VIRT + 0x3080)
+
+#define PIC1_IEN_OFFS           0x00
+#define PIC1_CREQ_OFFS          0x04
+#define PIC1_IREQ_OFFS          0x08
+#define PIC1_IRQSEL_OFFS        0x0c
+#define PIC1_SRC_OFFS           0x10
+#define PIC1_MREQ_OFFS          0x14
+#define PIC1_TSTREQ_OFFS        0x18
+#define PIC1_POL_OFFS           0x1c
+#define PIC1_IRQ_OFFS           0x20
+#define PIC1_FIQ_OFFS           0x24
+#define PIC1_MIRQ_OFFS          0x28
+#define PIC1_MFIQ_OFFS          0x2c
+#define PIC1_TMODE_OFFS         0x30
+#define PIC1_SYNC_OFFS          0x34
+#define PIC1_WKUP_OFFS          0x38
+#define PIC1_TMODEA_OFFS        0x3c
+#define PIC1_INTOEN_OFFS        0x40
+#define PIC1_MEN1_OFFS          0x44
+#define PIC1_MEN_OFFS           0x48
+
+#define PIC1_IEN        __REG(PIC1_BASE + PIC1_IEN_OFFS)
+#define PIC1_CREQ       __REG(PIC1_BASE + PIC1_CREQ_OFFS)
+#define PIC1_IREQ       __REG(PIC1_BASE + PIC1_IREQ_OFFS)
+#define PIC1_IRQSEL     __REG(PIC1_BASE + PIC1_IRQSEL_OFFS)
+#define PIC1_SRC        __REG(PIC1_BASE + PIC1_SRC_OFFS)
+#define PIC1_MREQ       __REG(PIC1_BASE + PIC1_MREQ_OFFS)
+#define PIC1_TSTREQ     __REG(PIC1_BASE + PIC1_TSTREQ_OFFS)
+#define PIC1_POL        __REG(PIC1_BASE + PIC1_POL_OFFS)
+#define PIC1_IRQ        __REG(PIC1_BASE + PIC1_IRQ_OFFS)
+#define PIC1_FIQ        __REG(PIC1_BASE + PIC1_FIQ_OFFS)
+#define PIC1_MIRQ       __REG(PIC1_BASE + PIC1_MIRQ_OFFS)
+#define PIC1_MFIQ       __REG(PIC1_BASE + PIC1_MFIQ_OFFS)
+#define PIC1_TMODE      __REG(PIC1_BASE + PIC1_TMODE_OFFS)
+#define PIC1_SYNC       __REG(PIC1_BASE + PIC1_SYNC_OFFS)
+#define PIC1_WKUP       __REG(PIC1_BASE + PIC1_WKUP_OFFS)
+#define PIC1_TMODEA     __REG(PIC1_BASE + PIC1_TMODEA_OFFS)
+#define PIC1_INTOEN     __REG(PIC1_BASE + PIC1_INTOEN_OFFS)
+#define PIC1_MEN1       __REG(PIC1_BASE + PIC1_MEN1_OFFS)
+#define PIC1_MEN        __REG(PIC1_BASE + PIC1_MEN_OFFS)
+
+/* Timer registers */
+#define TIMER_BASE              (APB1_PERI_BASE_VIRT + 0x4000)
+#define TIMER_BASE_PHYS         (APB1_PERI_BASE + 0x4000)
+
+#define TWDCFG_OFFS             0x70
+
+#define TC32EN_OFFS             0x80
+#define TC32LDV_OFFS            0x84
+#define TC32CMP0_OFFS           0x88
+#define TC32CMP1_OFFS           0x8c
+#define TC32PCNT_OFFS           0x90
+#define TC32MCNT_OFFS           0x94
+#define TC32IRQ_OFFS            0x98
+
+/* Bits in TC32EN */
+#define TC32EN_PRESCALE_MASK    0x00ffffff
+#define TC32EN_ENABLE           (1 << 24)
+#define TC32EN_LOADZERO         (1 << 25)
+#define TC32EN_STOPMODE         (1 << 26)
+#define TC32EN_LDM0             (1 << 28)
+#define TC32EN_LDM1             (1 << 29)
+
+/* Bits in TC32IRQ */
+#define TC32IRQ_MSTAT_MASK      0x0000001f
+#define TC32IRQ_RSTAT_MASK      (0x1f << 8)
+#define TC32IRQ_IRQEN0          (1 << 16)
+#define TC32IRQ_IRQEN1          (1 << 17)
+#define TC32IRQ_IRQEN2          (1 << 18)
+#define TC32IRQ_IRQEN3          (1 << 19)
+#define TC32IRQ_IRQEN4          (1 << 20)
+#define TC32IRQ_RSYNC           (1 << 30)
+#define TC32IRQ_IRQCLR          (1 << 31)
+
+/* GPIO registers */
+#define GPIOPD_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOPD_DAT_OFFS         0x00
+#define GPIOPD_DOE_OFFS         0x04
+#define GPIOPD_FS0_OFFS         0x08
+#define GPIOPD_FS1_OFFS         0x0c
+#define GPIOPD_FS2_OFFS         0x10
+#define GPIOPD_RPU_OFFS         0x30
+#define GPIOPD_RPD_OFFS         0x34
+#define GPIOPD_DV0_OFFS         0x38
+#define GPIOPD_DV1_OFFS         0x3c
+
+#define GPIOPS_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOPS_DAT_OFFS         0x40
+#define GPIOPS_DOE_OFFS         0x44
+#define GPIOPS_FS0_OFFS         0x48
+#define GPIOPS_FS1_OFFS         0x4c
+#define GPIOPS_FS2_OFFS         0x50
+#define GPIOPS_FS3_OFFS         0x54
+#define GPIOPS_RPU_OFFS         0x70
+#define GPIOPS_RPD_OFFS         0x74
+#define GPIOPS_DV0_OFFS         0x78
+#define GPIOPS_DV1_OFFS         0x7c
+
+#define GPIOPS_FS1_SDH0_BITS    0x000000ff
+#define GPIOPS_FS1_SDH1_BITS    0x0000ff00
+
+#define GPIOPU_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOPU_DAT_OFFS         0x80
+#define GPIOPU_DOE_OFFS         0x84
+#define GPIOPU_FS0_OFFS         0x88
+#define GPIOPU_FS1_OFFS         0x8c
+#define GPIOPU_FS2_OFFS         0x90
+#define GPIOPU_RPU_OFFS         0xb0
+#define GPIOPU_RPD_OFFS         0xb4
+#define GPIOPU_DV0_OFFS         0xb8
+#define GPIOPU_DV1_OFFS         0xbc
+
+#define GPIOPU_FS0_TXD0         (1 << 0)
+#define GPIOPU_FS0_RXD0         (1 << 1)
+#define GPIOPU_FS0_CTS0         (1 << 2)
+#define GPIOPU_FS0_RTS0         (1 << 3)
+#define GPIOPU_FS0_TXD1         (1 << 4)
+#define GPIOPU_FS0_RXD1         (1 << 5)
+#define GPIOPU_FS0_CTS1         (1 << 6)
+#define GPIOPU_FS0_RTS1         (1 << 7)
+#define GPIOPU_FS0_TXD2         (1 << 8)
+#define GPIOPU_FS0_RXD2         (1 << 9)
+#define GPIOPU_FS0_CTS2         (1 << 10)
+#define GPIOPU_FS0_RTS2         (1 << 11)
+#define GPIOPU_FS0_TXD3         (1 << 12)
+#define GPIOPU_FS0_RXD3         (1 << 13)
+#define GPIOPU_FS0_CTS3         (1 << 14)
+#define GPIOPU_FS0_RTS3         (1 << 15)
+#define GPIOPU_FS0_TXD4         (1 << 16)
+#define GPIOPU_FS0_RXD4         (1 << 17)
+#define GPIOPU_FS0_CTS4         (1 << 18)
+#define GPIOPU_FS0_RTS4         (1 << 19)
+
+#define GPIOFC_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOFC_DAT_OFFS         0xc0
+#define GPIOFC_DOE_OFFS         0xc4
+#define GPIOFC_FS0_OFFS         0xc8
+#define GPIOFC_FS1_OFFS         0xcc
+#define GPIOFC_FS2_OFFS         0xd0
+#define GPIOFC_FS3_OFFS         0xd4
+#define GPIOFC_RPU_OFFS         0xf0
+#define GPIOFC_RPD_OFFS         0xf4
+#define GPIOFC_DV0_OFFS         0xf8
+#define GPIOFC_DV1_OFFS         0xfc
+
+#define GPIOFD_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOFD_DAT_OFFS         0x100
+#define GPIOFD_DOE_OFFS         0x104
+#define GPIOFD_FS0_OFFS         0x108
+#define GPIOFD_FS1_OFFS         0x10c
+#define GPIOFD_FS2_OFFS         0x110
+#define GPIOFD_RPU_OFFS         0x130
+#define GPIOFD_RPD_OFFS         0x134
+#define GPIOFD_DV0_OFFS         0x138
+#define GPIOFD_DV1_OFFS         0x13c
+
+#define GPIOLC_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOLC_DAT_OFFS         0x140
+#define GPIOLC_DOE_OFFS         0x144
+#define GPIOLC_FS0_OFFS         0x148
+#define GPIOLC_FS1_OFFS         0x14c
+#define GPIOLC_RPU_OFFS         0x170
+#define GPIOLC_RPD_OFFS         0x174
+#define GPIOLC_DV0_OFFS         0x178
+#define GPIOLC_DV1_OFFS         0x17c
+
+#define GPIOLD_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOLD_DAT_OFFS         0x180
+#define GPIOLD_DOE_OFFS         0x184
+#define GPIOLD_FS0_OFFS         0x188
+#define GPIOLD_FS1_OFFS         0x18c
+#define GPIOLD_FS2_OFFS         0x190
+#define GPIOLD_RPU_OFFS         0x1b0
+#define GPIOLD_RPD_OFFS         0x1b4
+#define GPIOLD_DV0_OFFS         0x1b8
+#define GPIOLD_DV1_OFFS         0x1bc
+
+#define GPIOAD_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOAD_DAT_OFFS         0x1c0
+#define GPIOAD_DOE_OFFS         0x1c4
+#define GPIOAD_FS0_OFFS         0x1c8
+#define GPIOAD_RPU_OFFS         0x1f0
+#define GPIOAD_RPD_OFFS         0x1f4
+#define GPIOAD_DV0_OFFS         0x1f8
+#define GPIOAD_DV1_OFFS         0x1fc
+
+#define GPIOXC_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOXC_DAT_OFFS         0x200
+#define GPIOXC_DOE_OFFS         0x204
+#define GPIOXC_FS0_OFFS         0x208
+#define GPIOXC_RPU_OFFS         0x230
+#define GPIOXC_RPD_OFFS         0x234
+#define GPIOXC_DV0_OFFS         0x238
+#define GPIOXC_DV1_OFFS         0x23c
+
+#define GPIOXC_FS0              __REG(GPIOXC_BASE + GPIOXC_FS0_OFFS)
+
+#define GPIOXC_FS0_CS0          (1 << 26)
+#define GPIOXC_FS0_CS1          (1 << 27)
+
+#define GPIOXD_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOXD_DAT_OFFS         0x240
+#define GPIOXD_FS0_OFFS         0x248
+#define GPIOXD_RPU_OFFS         0x270
+#define GPIOXD_RPD_OFFS         0x274
+#define GPIOXD_DV0_OFFS         0x278
+#define GPIOXD_DV1_OFFS         0x27c
+
+#define GPIOPK_BASE             (APB1_PERI_BASE_VIRT + 0x1c000)
+
+#define GPIOPK_RST_OFFS         0x008
+#define GPIOPK_DAT_OFFS         0x100
+#define GPIOPK_DOE_OFFS         0x104
+#define GPIOPK_FS0_OFFS         0x108
+#define GPIOPK_FS1_OFFS         0x10c
+#define GPIOPK_FS2_OFFS         0x110
+#define GPIOPK_IRQST_OFFS       0x210
+#define GPIOPK_IRQEN_OFFS       0x214
+#define GPIOPK_IRQPOL_OFFS      0x218
+#define GPIOPK_IRQTM0_OFFS      0x21c
+#define GPIOPK_IRQTM1_OFFS      0x220
+#define GPIOPK_CTL_OFFS         0x22c
+
+#define PMGPIO_BASE             (APB1_PERI_BASE_VIRT + 0x10000)
+#define BACKUP_RAM_BASE         PMGPIO_BASE
+
+#define PMGPIO_DAT_OFFS         0x800
+#define PMGPIO_DOE_OFFS         0x804
+#define PMGPIO_FS0_OFFS         0x808
+#define PMGPIO_RPU_OFFS         0x810
+#define PMGPIO_RPD_OFFS         0x814
+#define PMGPIO_DV0_OFFS         0x818
+#define PMGPIO_DV1_OFFS         0x81c
+#define PMGPIO_EE0_OFFS         0x820
+#define PMGPIO_EE1_OFFS         0x824
+#define PMGPIO_CTL_OFFS         0x828
+#define PMGPIO_DI_OFFS          0x82c
+#define PMGPIO_STR_OFFS         0x830
+#define PMGPIO_STF_OFFS         0x834
+#define PMGPIO_POL_OFFS         0x838
+#define PMGPIO_APB_OFFS         0x800
+
+/* Clock controller registers */
+#define CKC_BASE        ((void __iomem *)(APB1_PERI_BASE_VIRT + 0x6000))
+
+#define CLKCTRL_OFFS            0x00
+#define PLL0CFG_OFFS            0x04
+#define PLL1CFG_OFFS            0x08
+#define CLKDIVC0_OFFS           0x0c
+
+#define BCLKCTR0_OFFS           0x14
+#define SWRESET0_OFFS           0x18
+
+#define BCLKCTR1_OFFS           0x60
+#define SWRESET1_OFFS           0x64
+#define PWDCTL_OFFS             0x68
+#define PLL2CFG_OFFS            0x6c
+#define CLKDIVC1_OFFS           0x70
+
+#define ACLKREF_OFFS            0x80
+#define ACLKI2C_OFFS            0x84
+#define ACLKSPI0_OFFS           0x88
+#define ACLKSPI1_OFFS           0x8c
+#define ACLKUART0_OFFS          0x90
+#define ACLKUART1_OFFS          0x94
+#define ACLKUART2_OFFS          0x98
+#define ACLKUART3_OFFS          0x9c
+#define ACLKUART4_OFFS          0xa0
+#define ACLKTCT_OFFS            0xa4
+#define ACLKTCX_OFFS            0xa8
+#define ACLKTCZ_OFFS            0xac
+#define ACLKADC_OFFS            0xb0
+#define ACLKDAI0_OFFS           0xb4
+#define ACLKDAI1_OFFS           0xb8
+#define ACLKLCD_OFFS            0xbc
+#define ACLKSPDIF_OFFS          0xc0
+#define ACLKUSBH_OFFS           0xc4
+#define ACLKSDH0_OFFS           0xc8
+#define ACLKSDH1_OFFS           0xcc
+#define ACLKC3DEC_OFFS          0xd0
+#define ACLKEXT_OFFS            0xd4
+#define ACLKCAN0_OFFS           0xd8
+#define ACLKCAN1_OFFS           0xdc
+#define ACLKGSB0_OFFS           0xe0
+#define ACLKGSB1_OFFS           0xe4
+#define ACLKGSB2_OFFS           0xe8
+#define ACLKGSB3_OFFS           0xec
+
+#define PLLxCFG_PD              (1 << 31)
+
+/* CLKCTRL bits */
+#define CLKCTRL_XE              (1 << 31)
+
+/* CLKDIVCx bits */
+#define CLKDIVC0_XTE            (1 << 7)
+#define CLKDIVC0_XE             (1 << 15)
+#define CLKDIVC0_P1E            (1 << 23)
+#define CLKDIVC0_P0E            (1 << 31)
+
+#define CLKDIVC1_P2E            (1 << 7)
+
+/* BCLKCTR0 clock bits */
+#define BCLKCTR0_USBD           (1 << 4)
+#define BCLKCTR0_ECC            (1 << 9)
+#define BCLKCTR0_USBH0          (1 << 11)
+#define BCLKCTR0_NFC            (1 << 16)
+
+/* BCLKCTR1 clock bits */
+#define BCLKCTR1_USBH1          (1 << 20)
+
+/* SWRESET0 bits */
+#define SWRESET0_USBD           (1 << 4)
+#define SWRESET0_USBH0          (1 << 11)
+
+/* SWRESET1 bits */
+#define SWRESET1_USBH1          (1 << 20)
+
+/* System clock sources.
+ * Note: These are the clock sources that serve as parents for
+ * all other clocks. They have no parents themselves.
+ *
+ * These values are used for struct clk->root_id. All clocks
+ * that are not system clock sources have this value set to
+ * CLK_SRC_NOROOT.
+ * The values for system clocks start with CLK_SRC_PLL0 == 0
+ * because this gives us exactly the values needed for the lower
+ * 4 bits of ACLK_* registers. Therefore, CLK_SRC_NOROOT is
+ * defined as -1 to not disturb the order.
+ */
+enum root_clks {
+        CLK_SRC_NOROOT = -1,
+        CLK_SRC_PLL0 = 0,
+        CLK_SRC_PLL1,
+        CLK_SRC_PLL0DIV,
+        CLK_SRC_PLL1DIV,
+        CLK_SRC_XI,
+        CLK_SRC_XIDIV,
+        CLK_SRC_XTI,
+        CLK_SRC_XTIDIV,
+        CLK_SRC_PLL2,
+        CLK_SRC_PLL2DIV,
+        CLK_SRC_PK0,
+        CLK_SRC_PK1,
+        CLK_SRC_PK2,
+        CLK_SRC_PK3,
+        CLK_SRC_PK4,
+        CLK_SRC_48MHZ
+};
+
+#define CLK_SRC_MASK            0xf
+
+/* Bits in ACLK* registers */
+#define ACLK_EN         (1 << 28)
+#define ACLK_SEL_SHIFT          24
+#define ACLK_SEL_MASK           0x0f000000
+#define ACLK_DIV_MASK           0x00000fff
+
+/* System configuration registers */
+
+#define SCFG_BASE               (APB1_PERI_BASE_VIRT + 0x13000)
+
+#define BMI_OFFS                0x00
+#define AHBCON0_OFFS            0x04
+#define APBPWE_OFFS             0x08
+#define DTCMWAIT_OFFS           0x0c
+#define ECCSEL_OFFS             0x10
+#define AHBCON1_OFFS            0x14
+#define SDHCFG_OFFS             0x18
+#define REMAP_OFFS              0x20
+#define LCDSIAE_OFFS            0x24
+#define XMCCFG_OFFS             0xe0
+#define IMCCFG_OFFS             0xe4
+
+/* Values for ECCSEL */
+#define ECCSEL_EXTMEM           0x0
+#define ECCSEL_DTCM             0x1
+#define ECCSEL_INT_SRAM         0x2
+#define ECCSEL_AHB              0x3
+
+/* Bits in XMCCFG */
+#define XMCCFG_NFCE             (1 << 1)
+#define XMCCFG_FDXD             (1 << 2)
+
+/* External memory controller registers */
+
+#define EMC_BASE                EXT_MEM_CTRL_BASE
+
+#define SDCFG_OFFS              0x00
+#define SDFSM_OFFS              0x04
+#define MCFG_OFFS               0x08
+
+#define CSCFG0_OFFS             0x10
+#define CSCFG1_OFFS             0x14
+#define CSCFG2_OFFS             0x18
+#define CSCFG3_OFFS             0x1c
+
+#define MCFG_SDEN               (1 << 4)
+
+#endif /* TCC8K_REGS_H */
diff --git a/arch/arm/plat-tcc/include/mach/timex.h b/arch/arm/plat-tcc/include/mach/timex.h
new file mode 100644
index 000000000000..057acbe651d9
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/timex.h
@@ -0,0 +1,5 @@
+/*
+ * A definition needed by arch core code.
+ *
+ */
+#define CLOCK_TICK_RATE         (HZ * 100000UL)
diff --git a/arch/arm/plat-tcc/include/mach/uncompress.h b/arch/arm/plat-tcc/include/mach/uncompress.h
new file mode 100644
index 000000000000..7a3e33a27a30
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/uncompress.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * This file is licensed under the terms of the GPL version 2.
+ */
+
+#include <linux/serial_reg.h>
+#include <linux/types.h>
+
+#include <mach/tcc8k-regs.h>
+
+unsigned int system_rev;
+
+#define ID_MASK                 0x7fff
+
+static void putc(int c)
+{
+        u32 *uart_lsr = (u32 *)(UART_BASE_PHYS + (UART_LSR << 2));
+        u32 *uart_tx = (u32 *)(UART_BASE_PHYS + (UART_TX << 2));
+
+        while (!(*uart_lsr & UART_LSR_THRE))
+                barrier();
+        *uart_tx = c;
+}
+
+static inline void flush(void)
+{
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/plat-tcc/include/mach/vmalloc.h b/arch/arm/plat-tcc/include/mach/vmalloc.h
new file mode 100644
index 000000000000..99414d9c2b94
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/vmalloc.h
@@ -0,0 +1,10 @@
+/*
+ * Author: <linux@telechips.com>
+ * Created: June 10, 2008
+ *
+ * Copyright (C) 2000 Russell King.
+ * Copyright (C) 2008-2009 Telechips
+ *
+ * Licensed under the terms of the GPL v2.
+ */
+#define VMALLOC_END     0xf0000000UL
diff --git a/arch/arm/plat-tcc/system.c b/arch/arm/plat-tcc/system.c
new file mode 100644
index 000000000000..cc208fae3e7a
--- /dev/null
+++ b/arch/arm/plat-tcc/system.c
@@ -0,0 +1,25 @@
+/*
+ * System functions for Telechips TCCxxxx SoCs
+ *
+ * Copyright (C) Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GPL v2.
+ *
+ */
+
+#include <linux/io.h>
+
+#include <mach/tcc8k-regs.h>
+
+/* System reboot */
+void plat_tcc_reboot(void)
+{
+        /* Make sure clocks are on */
+        __raw_writel(0xffffffff, CKC_BASE + BCLKCTR0_OFFS);
+
+        /* Enable watchdog reset */
+        __raw_writel(0x49, TIMER_BASE + TWDCFG_OFFS);
+        /* Wait for reset */
+        while(1)
+                ;
+}
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index f51572772e21..9ac87255a03a 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -90,6 +90,7 @@ config PLATFORM_AT32AP
         select ARCH_REQUIRE_GPIOLIB
         select GENERIC_ALLOCATOR
         select HAVE_FB_ATMEL
+        select HAVE_NET_MACB
 
 #
 # CPU types
diff --git a/arch/avr32/kernel/module.c b/arch/avr32/kernel/module.c
index 98f94d041d9c..a727f54d64d6 100644
--- a/arch/avr32/kernel/module.c
+++ b/arch/avr32/kernel/module.c
@@ -314,10 +314,9 @@ int module_finalize(const Elf_Ehdr *hdr, const Elf_Shdr *sechdrs,
         vfree(module->arch.syminfo);
         module->arch.syminfo = NULL;
 
-        return module_bug_finalize(hdr, sechdrs, module);
+        return 0;
 }
 
 void module_arch_cleanup(struct module *module)
 {
-        module_bug_cleanup(module);
 }
diff --git a/arch/frv/kernel/signal.c b/arch/frv/kernel/signal.c
index 0974c0ecc594..bab01298b58e 100644
--- a/arch/frv/kernel/signal.c
+++ b/arch/frv/kernel/signal.c
@@ -121,6 +121,9 @@ static int restore_sigcontext(struct sigcontext __user *sc, int *_gr8)
         struct user_context *user = current->thread.user;
         unsigned long tbr, psr;
 
+        /* Always make any pending restarted system calls return -EINTR */
+        current_thread_info()->restart_block.fn = do_no_restart_syscall;
+
         tbr = user->i.tbr;
         psr = user->i.psr;
         if (copy_from_user(user, &sc->sc_context, sizeof(sc->sc_context)))
@@ -250,6 +253,8 @@ static int setup_frame(int sig, struct k_sigaction *ka, sigset_t *set)
         struct sigframe __user *frame;
         int rsig;
 
+        set_fs(USER_DS);
+
         frame = get_sigframe(ka, sizeof(*frame));
 
         if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
@@ -293,22 +298,23 @@ static int setup_frame(int sig, struct k_sigaction *ka, sigset_t *set)
                                    (unsigned long) (frame->retcode + 2));
         }
 
-        /* set up registers for signal handler */
-        __frame->sp   = (unsigned long) frame;
-        __frame->lr   = (unsigned long) &frame->retcode;
-        __frame->gr8  = sig;
-
+        /* Set up registers for the signal handler */
         if (current->personality & FDPIC_FUNCPTRS) {
                 struct fdpic_func_descriptor __user *funcptr =
                         (struct fdpic_func_descriptor __user *) ka->sa.sa_handler;
-                __get_user(__frame->pc, &funcptr->text);
-                __get_user(__frame->gr15, &funcptr->GOT);
+                struct fdpic_func_descriptor desc;
+                if (copy_from_user(&desc, funcptr, sizeof(desc)))
+                        goto give_sigsegv;
+                __frame->pc = desc.text;
+                __frame->gr15 = desc.GOT;
         } else {
                 __frame->pc   = (unsigned long) ka->sa.sa_handler;
                 __frame->gr15 = 0;
         }
 
-        set_fs(USER_DS);
+        __frame->sp   = (unsigned long) frame;
+        __frame->lr   = (unsigned long) &frame->retcode;
+        __frame->gr8  = sig;
 
         /* the tracer may want to single-step inside the handler */
         if (test_thread_flag(TIF_SINGLESTEP))
@@ -323,7 +329,7 @@ static int setup_frame(int sig, struct k_sigaction *ka, sigset_t *set)
         return 0;
 
 give_sigsegv:
-        force_sig(SIGSEGV, current);
+        force_sigsegv(sig, current);
         return -EFAULT;
 
 } /* end setup_frame() */
@@ -338,6 +344,8 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
         struct rt_sigframe __user *frame;
         int rsig;
 
+        set_fs(USER_DS);
+
         frame = get_sigframe(ka, sizeof(*frame));
 
         if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
@@ -392,22 +400,23 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
         }
 
         /* Set up registers for signal handler */
-        __frame->sp  = (unsigned long) frame;
-        __frame->lr   = (unsigned long) &frame->retcode;
-        __frame->gr8 = sig;
-        __frame->gr9 = (unsigned long) &frame->info;
-
         if (current->personality & FDPIC_FUNCPTRS) {
                 struct fdpic_func_descriptor __user *funcptr =
                         (struct fdpic_func_descriptor __user *) ka->sa.sa_handler;
-                __get_user(__frame->pc, &funcptr->text);
-                __get_user(__frame->gr15, &funcptr->GOT);
+                struct fdpic_func_descriptor desc;
+                if (copy_from_user(&desc, funcptr, sizeof(desc)))
+                        goto give_sigsegv;
+                __frame->pc = desc.text;
+                __frame->gr15 = desc.GOT;
         } else {
                 __frame->pc   = (unsigned long) ka->sa.sa_handler;
                 __frame->gr15 = 0;
         }
 
-        set_fs(USER_DS);
+        __frame->sp  = (unsigned long) frame;
+        __frame->lr  = (unsigned long) &frame->retcode;
+        __frame->gr8 = sig;
+        __frame->gr9 = (unsigned long) &frame->info;
 
         /* the tracer may want to single-step inside the handler */
         if (test_thread_flag(TIF_SINGLESTEP))
@@ -422,7 +431,7 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
         return 0;
 
 give_sigsegv:
-        force_sig(SIGSEGV, current);
+        force_sigsegv(sig, current);
         return -EFAULT;
 
 } /* end setup_rt_frame() */
@@ -437,7 +446,7 @@ static int handle_signal(unsigned long sig, siginfo_t *info,
         int ret;
 
         /* Are we from a system call? */
-        if (in_syscall(__frame)) {
+        if (__frame->syscallno != -1) {
                 /* If so, check system call restarting.. */
                 switch (__frame->gr8) {
                 case -ERESTART_RESTARTBLOCK:
@@ -456,6 +465,7 @@ static int handle_signal(unsigned long sig, siginfo_t *info,
                         __frame->gr8 = __frame->orig_gr8;
                         __frame->pc -= 4;
                 }
+                __frame->syscallno = -1;
         }
 
         /* Set up the stack frame */
@@ -538,10 +548,11 @@ no_signal:
                         break;
 
                 case -ERESTART_RESTARTBLOCK:
-                        __frame->gr8 = __NR_restart_syscall;
+                        __frame->gr7 = __NR_restart_syscall;
                         __frame->pc -= 4;
                         break;
                 }
+                __frame->syscallno = -1;
         }
 
         /* if there's no signal to deliver, we just put the saved sigmask
diff --git a/arch/h8300/kernel/module.c b/arch/h8300/kernel/module.c
index 0865e291c20d..db4953dc4e1b 100644
--- a/arch/h8300/kernel/module.c
+++ b/arch/h8300/kernel/module.c
@@ -112,10 +112,9 @@ int module_finalize(const Elf_Ehdr *hdr,
                     const Elf_Shdr *sechdrs,
                     struct module *me)
 {
-        return module_bug_finalize(hdr, sechdrs, me);
+        return 0;
 }
 
 void module_arch_cleanup(struct module *mod)
 {
-        module_bug_cleanup(mod);
 }
diff --git a/arch/ia64/include/asm/compat.h b/arch/ia64/include/asm/compat.h
index f90edc85b509..9301a2821615 100644
--- a/arch/ia64/include/asm/compat.h
+++ b/arch/ia64/include/asm/compat.h
@@ -199,7 +199,7 @@ ptr_to_compat(void __user *uptr)
 }
 
 static __inline__ void __user *
-compat_alloc_user_space (long len)
+arch_compat_alloc_user_space (long len)
 {
         struct pt_regs *regs = task_pt_regs(current);
         return (void __user *) (((regs->r12 & 0xffffffff) & -16) - len);
diff --git a/arch/ia64/kernel/fsys.S b/arch/ia64/kernel/fsys.S
index 3567d54f8cee..331d42bda77a 100644
--- a/arch/ia64/kernel/fsys.S
+++ b/arch/ia64/kernel/fsys.S
@@ -420,22 +420,31 @@ EX(.fail_efault, ld8 r14=[r33])			// r14 <- *set
         ;;
 
         RSM_PSR_I(p0, r18, r19)                 // mask interrupt delivery
-        mov ar.ccv=0
         andcm r14=r14,r17                       // filter out SIGKILL & SIGSTOP
+        mov r8=EINVAL                   // default to EINVAL
 
 #ifdef CONFIG_SMP
-        mov r17=1
+        // __ticket_spin_trylock(r31)
+        ld4 r17=[r31]
         ;;
-        cmpxchg4.acq r18=[r31],r17,ar.ccv       // try to acquire the lock
-        mov r8=EINVAL                   // default to EINVAL
+        mov.m ar.ccv=r17
+        extr.u r9=r17,17,15
+        adds r19=1,r17
+        extr.u r18=r17,0,15
+        ;;
+        cmp.eq p6,p7=r9,r18
         ;;
+(p6)    cmpxchg4.acq r9=[r31],r19,ar.ccv
+(p6)    dep.z r20=r19,1,15              // next serving ticket for unlock
+(p7)    br.cond.spnt.many .lock_contention
+        ;;
+        cmp4.eq p0,p7=r9,r17
+        adds r31=2,r31
+(p7)    br.cond.spnt.many .lock_contention
         ld8 r3=[r2]                     // re-read current->blocked now that we hold the lock
-        cmp4.ne p6,p0=r18,r0
-(p6)    br.cond.spnt.many .lock_contention
         ;;
 #else
         ld8 r3=[r2]                     // re-read current->blocked now that we hold the lock
-        mov r8=EINVAL                   // default to EINVAL
 #endif
         add r18=IA64_TASK_PENDING_OFFSET+IA64_SIGPENDING_SIGNAL_OFFSET,r16
         add r19=IA64_TASK_SIGNAL_OFFSET,r16
@@ -490,7 +499,9 @@ EX(.fail_efault, ld8 r14=[r33])			// r14 <- *set
 (p6)    br.cond.spnt.few 1b                     // yes -> retry
 
 #ifdef CONFIG_SMP
-        st4.rel [r31]=r0                        // release the lock
+        // __ticket_spin_unlock(r31)
+        st2.rel [r31]=r20
+        mov r20=0                                       // i must not leak kernel bits...
 #endif
         SSM_PSR_I(p0, p9, r31)
         ;;
@@ -512,7 +523,8 @@ EX(.fail_efault, (p15) st8 [r34]=r3)
 
 .sig_pending:
 #ifdef CONFIG_SMP
-        st4.rel [r31]=r0                        // release the lock
+        // __ticket_spin_unlock(r31)
+        st2.rel [r31]=r20                       // release the lock
 #endif
         SSM_PSR_I(p0, p9, r17)
         ;;
diff --git a/arch/m32r/include/asm/signal.h b/arch/m32r/include/asm/signal.h
index 9c1acb2b1a92..b2eeb0de1c8d 100644
--- a/arch/m32r/include/asm/signal.h
+++ b/arch/m32r/include/asm/signal.h
@@ -157,7 +157,6 @@ typedef struct sigaltstack {
 #undef __HAVE_ARCH_SIG_BITOPS
 
 struct pt_regs;
-extern int do_signal(struct pt_regs *regs, sigset_t *oldset);
 
 #define ptrace_signal_deliver(regs, cookie)     do { } while (0)
 
diff --git a/arch/m32r/include/asm/unistd.h b/arch/m32r/include/asm/unistd.h
index 76125777483c..c70545689da8 100644
--- a/arch/m32r/include/asm/unistd.h
+++ b/arch/m32r/include/asm/unistd.h
@@ -351,6 +351,7 @@
 #define __ARCH_WANT_SYS_OLD_GETRLIMIT /*will be unused*/
 #define __ARCH_WANT_SYS_OLDUMOUNT
 #define __ARCH_WANT_SYS_RT_SIGACTION
+#define __ARCH_WANT_SYS_RT_SIGSUSPEND
 
 #define __IGNORE_lchown
 #define __IGNORE_setuid
diff --git a/arch/m32r/kernel/entry.S b/arch/m32r/kernel/entry.S
index 403869833b98..225412bc227e 100644
--- a/arch/m32r/kernel/entry.S
+++ b/arch/m32r/kernel/entry.S
@@ -235,10 +235,9 @@ work_resched:
 work_notifysig:                         ; deal with pending signals and
                                         ; notify-resume requests
         mv      r0, sp                  ; arg1 : struct pt_regs *regs
-        ldi     r1, #0                  ; arg2 : sigset_t *oldset
-        mv      r2, r9                  ; arg3 : __u32 thread_info_flags
+        mv      r1, r9                  ; arg2 : __u32 thread_info_flags
         bl      do_notify_resume
-        bra     restore_all
+        bra     resume_userspace
 
         ; perform syscall exit tracing
         ALIGN
diff --git a/arch/m32r/kernel/ptrace.c b/arch/m32r/kernel/ptrace.c
index e555091eb97c..0021ade4cba8 100644
--- a/arch/m32r/kernel/ptrace.c
+++ b/arch/m32r/kernel/ptrace.c
@@ -592,16 +592,17 @@ void user_enable_single_step(struct task_struct *child)
 
         if (access_process_vm(child, pc&~3, &insn, sizeof(insn), 0)
             != sizeof(insn))
-                break;
+                return -EIO;
 
         compute_next_pc(insn, pc, &next_pc, child);
         if (next_pc & 0x80000000)
-                break;
+                return -EIO;
 
         if (embed_debug_trap(child, next_pc))
-                break;
+                return -EIO;
 
         invalidate_cache();
+        return 0;
 }
 
 void user_disable_single_step(struct task_struct *child)
diff --git a/arch/m32r/kernel/signal.c b/arch/m32r/kernel/signal.c
index 144b0f124fc7..7bbe38645ed5 100644
--- a/arch/m32r/kernel/signal.c
+++ b/arch/m32r/kernel/signal.c
@@ -28,37 +28,6 @@
 
 #define DEBUG_SIG 0
 
-#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
-
-int do_signal(struct pt_regs *, sigset_t *);
-
-asmlinkage int
-sys_rt_sigsuspend(sigset_t __user *unewset, size_t sigsetsize,
-                  unsigned long r2, unsigned long r3, unsigned long r4,
-                  unsigned long r5, unsigned long r6, struct pt_regs *regs)
-{
-        sigset_t newset;
-
-        /* XXX: Don't preclude handling different sized sigset_t's.  */
-        if (sigsetsize != sizeof(sigset_t))
-                return -EINVAL;
-
-        if (copy_from_user(&newset, unewset, sizeof(newset)))
-                return -EFAULT;
-        sigdelsetmask(&newset, sigmask(SIGKILL)|sigmask(SIGSTOP));
-
-        spin_lock_irq(&current->sighand->siglock);
-        current->saved_sigmask = current->blocked;
-        current->blocked = newset;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
-
-        current->state = TASK_INTERRUPTIBLE;
-        schedule();
-        set_thread_flag(TIF_RESTORE_SIGMASK);
-        return -ERESTARTNOHAND;
-}
-
 asmlinkage int
 sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss,
                 unsigned long r2, unsigned long r3, unsigned long r4,
@@ -218,7 +187,7 @@ get_sigframe(struct k_sigaction *ka, unsigned long sp, size_t frame_size)
         return (void __user *)((sp - frame_size) & -8ul);
 }
 
-static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
+static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
                            sigset_t *set, struct pt_regs *regs)
 {
         struct rt_sigframe __user *frame;
@@ -275,22 +244,34 @@ static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
                 current->comm, current->pid, frame, regs->pc);
 #endif
 
-        return;
+        return 0;
 
 give_sigsegv:
         force_sigsegv(sig, current);
+        return -EFAULT;
+}
+
+static int prev_insn(struct pt_regs *regs)
+{
+        u16 inst;
+        if (get_user(&inst, (u16 __user *)(regs->bpc - 2)))
+                return -EFAULT;
+        if ((inst & 0xfff0) == 0x10f0)  /* trap ? */
+                regs->bpc -= 2;
+        else
+                regs->bpc -= 4;
+        regs->syscall_nr = -1;
+        return 0;
 }
 
 /*
  * OK, we're invoking a handler
  */
 
-static void
+static int
 handle_signal(unsigned long sig, struct k_sigaction *ka, siginfo_t *info,
               sigset_t *oldset, struct pt_regs *regs)
 {
-        unsigned short inst;
-
         /* Are we from a system call? */
         if (regs->syscall_nr >= 0) {
                 /* If so, check system call restarting.. */
@@ -308,16 +289,14 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, siginfo_t *info,
                         /* fallthrough */
                         case -ERESTARTNOINTR:
                                 regs->r0 = regs->orig_r0;
-                                inst = *(unsigned short *)(regs->bpc - 2);
-                                if ((inst & 0xfff0) == 0x10f0)  /* trap ? */
-                                        regs->bpc -= 2;
-                                else
-                                        regs->bpc -= 4;
+                                if (prev_insn(regs) < 0)
+                                        return -EFAULT;
                 }
         }
 
         /* Set up the stack frame */
-        setup_rt_frame(sig, ka, info, oldset, regs);
+        if (setup_rt_frame(sig, ka, info, oldset, regs))
+                return -EFAULT;
 
         spin_lock_irq(&current->sighand->siglock);
         sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
@@ -325,6 +304,7 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, siginfo_t *info,
                 sigaddset(&current->blocked,sig);
         recalc_sigpending();
         spin_unlock_irq(&current->sighand->siglock);
+        return 0;
 }
 
 /*
@@ -332,12 +312,12 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, siginfo_t *info,
  * want to handle. Thus you cannot kill init even with a SIGKILL even by
  * mistake.
  */
-int do_signal(struct pt_regs *regs, sigset_t *oldset)
+static void do_signal(struct pt_regs *regs)
 {
         siginfo_t info;
         int signr;
         struct k_sigaction ka;
-        unsigned short inst;
+        sigset_t *oldset;
 
         /*
          * We want the common case to go fast, which
@@ -346,12 +326,14 @@ int do_signal(struct pt_regs *regs, sigset_t *oldset)
          * if so.
          */
         if (!user_mode(regs))
-                return 1;
+                return;
 
         if (try_to_freeze()) 
                 goto no_signal;
 
-        if (!oldset)
+        if (test_thread_flag(TIF_RESTORE_SIGMASK))
+                oldset = &current->saved_sigmask;
+        else
                 oldset = &current->blocked;
 
         signr = get_signal_to_deliver(&info, &ka, regs, NULL);
@@ -363,8 +345,10 @@ int do_signal(struct pt_regs *regs, sigset_t *oldset)
                  */
 
                 /* Whee!  Actually deliver the signal.  */
-                handle_signal(signr, &ka, &info, oldset, regs);
-                return 1;
+                if (handle_signal(signr, &ka, &info, oldset, regs) == 0)
+                        clear_thread_flag(TIF_RESTORE_SIGMASK);
+
+                return;
         }
 
  no_signal:
@@ -375,31 +359,24 @@ int do_signal(struct pt_regs *regs, sigset_t *oldset)
                     regs->r0 == -ERESTARTSYS ||
                     regs->r0 == -ERESTARTNOINTR) {
                         regs->r0 = regs->orig_r0;
-                        inst = *(unsigned short *)(regs->bpc - 2);
-                        if ((inst & 0xfff0) == 0x10f0)  /* trap ? */
-                                regs->bpc -= 2;
-                        else
-                                regs->bpc -= 4;
-                }
-                if (regs->r0 == -ERESTART_RESTARTBLOCK){
+                        prev_insn(regs);
+                } else if (regs->r0 == -ERESTART_RESTARTBLOCK){
                         regs->r0 = regs->orig_r0;
                         regs->r7 = __NR_restart_syscall;
-                        inst = *(unsigned short *)(regs->bpc - 2);
-                        if ((inst & 0xfff0) == 0x10f0)  /* trap ? */
-                                regs->bpc -= 2;
-                        else
-                                regs->bpc -= 4;
+                        prev_insn(regs);
                 }
         }
-        return 0;
+        if (test_thread_flag(TIF_RESTORE_SIGMASK)) {
+                clear_thread_flag(TIF_RESTORE_SIGMASK);
+                sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
+        }
 }
 
 /*
  * notification of userspace execution resumption
  * - triggered by current->work.notify_resume
  */
-void do_notify_resume(struct pt_regs *regs, sigset_t *oldset,
-                      __u32 thread_info_flags)
+void do_notify_resume(struct pt_regs *regs, __u32 thread_info_flags)
 {
         /* Pending single-step? */
         if (thread_info_flags & _TIF_SINGLESTEP)
@@ -407,7 +384,7 @@ void do_notify_resume(struct pt_regs *regs, sigset_t *oldset,
 
         /* deal with pending signal delivery */
         if (thread_info_flags & _TIF_SIGPENDING)
-                do_signal(regs,oldset);
+                do_signal(regs);
 
         if (thread_info_flags & _TIF_NOTIFY_RESUME) {
                 clear_thread_flag(TIF_NOTIFY_RESUME);
diff --git a/arch/m68k/include/asm/unistd.h b/arch/m68k/include/asm/unistd.h
index 60b15d0aa072..b43b36beafe3 100644
--- a/arch/m68k/include/asm/unistd.h
+++ b/arch/m68k/include/asm/unistd.h
@@ -340,10 +340,13 @@
 #define __NR_set_thread_area    334
 #define __NR_atomic_cmpxchg_32  335
 #define __NR_atomic_barrier     336
+#define __NR_fanotify_init      337
+#define __NR_fanotify_mark      338
+#define __NR_prlimit64          339
 
 #ifdef __KERNEL__
 
-#define NR_syscalls             337
+#define NR_syscalls             340
 
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
diff --git a/arch/m68k/kernel/entry.S b/arch/m68k/kernel/entry.S
index 2391bdff0996..6360c437dcf5 100644
--- a/arch/m68k/kernel/entry.S
+++ b/arch/m68k/kernel/entry.S
@@ -765,4 +765,7 @@ sys_call_table:
         .long sys_set_thread_area
         .long sys_atomic_cmpxchg_32     /* 335 */
         .long sys_atomic_barrier
+        .long sys_fanotify_init
+        .long sys_fanotify_mark
+        .long sys_prlimit64
 
diff --git a/arch/m68k/mac/macboing.c b/arch/m68k/mac/macboing.c
index 8f0640847ad2..05285d08e547 100644
--- a/arch/m68k/mac/macboing.c
+++ b/arch/m68k/mac/macboing.c
@@ -162,7 +162,7 @@ static void mac_init_asc( void )
 void mac_mksound( unsigned int freq, unsigned int length )
 {
         __u32 cfreq = ( freq << 5 ) / 468;
-        __u32 flags;
+        unsigned long flags;
         int i;
 
         if ( mac_special_bell == NULL )
@@ -224,7 +224,7 @@ static void mac_nosound( unsigned long ignored )
  */
 static void mac_quadra_start_bell( unsigned int freq, unsigned int length, unsigned int volume )
 {
-        __u32 flags;
+        unsigned long flags;
 
         /* if the bell is already ringing, ring longer */
         if ( mac_bell_duration > 0 )
@@ -271,7 +271,7 @@ static void mac_quadra_start_bell( unsigned int freq, unsigned int length, unsig
 static void mac_quadra_ring_bell( unsigned long ignored )
 {
         int     i, count = mac_asc_samplespersec / HZ;
-        __u32 flags;
+        unsigned long flags;
 
         /*
          * we neither want a sound buffer overflow nor underflow, so we need to match
diff --git a/arch/m68knommu/kernel/syscalltable.S b/arch/m68knommu/kernel/syscalltable.S
index b30b3eb197a5..79b1ed198c07 100644
--- a/arch/m68knommu/kernel/syscalltable.S
+++ b/arch/m68knommu/kernel/syscalltable.S
@@ -355,6 +355,9 @@ ENTRY(sys_call_table)
         .long sys_set_thread_area
         .long sys_atomic_cmpxchg_32     /* 335 */
         .long sys_atomic_barrier
+        .long sys_fanotify_init
+        .long sys_fanotify_mark
+        .long sys_prlimit64
 
         .rept NR_syscalls-(.-sys_call_table)/4
                 .long sys_ni_syscall
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 3ad59dde4852..5526faabfc21 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -13,6 +13,7 @@ config MIPS
         select HAVE_KPROBES
         select HAVE_KRETPROBES
         select RTC_LIB if !MACH_LOONGSON
+        select GENERIC_ATOMIC64 if !64BIT
 
 mainmenu "Linux/MIPS Kernel Configuration"
 
@@ -1646,8 +1647,16 @@ config MIPS_MT_SMP
         select SYS_SUPPORTS_SMP
         select SMP_UP
         help
-          This is a kernel model which is also known a VSMP or lately
-          has been marketesed into SMVP.
+          This is a kernel model which is known a VSMP but lately has been
+          marketesed into SMVP.
+          Virtual SMP uses the processor's VPEs  to implement virtual
+          processors. In currently available configuration of the 34K processor
+          this allows for a dual processor. Both processors will share the same
+          primary caches; each will obtain the half of the TLB for it's own
+          exclusive use. For a layman this model can be described as similar to
+          what Intel calls Hyperthreading.
+
+          For further information see http://www.linux-mips.org/wiki/34K#VSMP
 
 config MIPS_MT_SMTC
         bool "SMTC: Use all TCs on all VPEs for SMP"
@@ -1664,6 +1673,14 @@ config MIPS_MT_SMTC
         help
           This is a kernel model which is known a SMTC or lately has been
           marketesed into SMVP.
+          is presenting the available TC's of the core as processors to Linux.
+          On currently available 34K processors this means a Linux system will
+          see up to 5 processors. The implementation of the SMTC kernel differs
+          significantly from VSMP and cannot efficiently coexist in the same
+          kernel binary so the choice between VSMP and SMTC is a compile time
+          decision.
+
+          For further information see http://www.linux-mips.org/wiki/34K#SMTC
 
 endchoice
 
diff --git a/arch/mips/alchemy/common/prom.c b/arch/mips/alchemy/common/prom.c
index c29511b11d44..534021059629 100644
--- a/arch/mips/alchemy/common/prom.c
+++ b/arch/mips/alchemy/common/prom.c
@@ -43,7 +43,7 @@ int prom_argc;
 char **prom_argv;
 char **prom_envp;
 
-void prom_init_cmdline(void)
+void __init prom_init_cmdline(void)
 {
         int i;
 
@@ -104,7 +104,7 @@ static inline void str2eaddr(unsigned char *ea, unsigned char *str)
         }
 }
 
-int prom_get_ethernet_addr(char *ethernet_addr)
+int __init prom_get_ethernet_addr(char *ethernet_addr)
 {
         char *ethaddr_str;
 
@@ -123,7 +123,6 @@ int prom_get_ethernet_addr(char *ethernet_addr)
 
         return 0;
 }
-EXPORT_SYMBOL(prom_get_ethernet_addr);
 
 void __init prom_free_prom_memory(void)
 {
diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile
index ed9bb709c9a3..5fd7f7a58b7e 100644
--- a/arch/mips/boot/compressed/Makefile
+++ b/arch/mips/boot/compressed/Makefile
@@ -59,7 +59,7 @@ $(obj)/piggy.o: $(obj)/dummy.o $(obj)/vmlinux.bin.z FORCE
 hostprogs-y := calc_vmlinuz_load_addr
 
 VMLINUZ_LOAD_ADDRESS = $(shell $(obj)/calc_vmlinuz_load_addr \
-                $(objtree)/$(KBUILD_IMAGE) $(VMLINUX_LOAD_ADDRESS))
+                $(obj)/vmlinux.bin $(VMLINUX_LOAD_ADDRESS))
 
 vmlinuzobjs-y += $(obj)/piggy.o
 
diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index 094c17e38e16..47323ca452dc 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -83,3 +83,7 @@ config ARCH_SPARSEMEM_ENABLE
         def_bool y
         select SPARSEMEM_STATIC
         depends on CPU_CAVIUM_OCTEON
+
+config CAVIUM_OCTEON_HELPER
+        def_bool y
+        depends on OCTEON_ETHERNET || PCI
diff --git a/arch/mips/cavium-octeon/cpu.c b/arch/mips/cavium-octeon/cpu.c
index c664c8cc2b42..a5b427909b5c 100644
--- a/arch/mips/cavium-octeon/cpu.c
+++ b/arch/mips/cavium-octeon/cpu.c
@@ -41,7 +41,7 @@ static int cnmips_cu2_call(struct notifier_block *nfb, unsigned long action,
         return NOTIFY_OK;               /* Let default notifier send signals */
 }
 
-static int cnmips_cu2_setup(void)
+static int __init cnmips_cu2_setup(void)
 {
         return cu2_notifier(cnmips_cu2_call, 0);
 }
diff --git a/arch/mips/cavium-octeon/executive/Makefile b/arch/mips/cavium-octeon/executive/Makefile
index 2fd66db6939e..7f41c5be2190 100644
--- a/arch/mips/cavium-octeon/executive/Makefile
+++ b/arch/mips/cavium-octeon/executive/Makefile
@@ -11,4 +11,4 @@
 
 obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o
 
-obj-$(CONFIG_PCI) += cvmx-helper-errata.o cvmx-helper-jtag.o
+obj-$(CONFIG_CAVIUM_OCTEON_HELPER) += cvmx-helper-errata.o cvmx-helper-jtag.o
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index c63c56bfd184..47d87da379f9 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -782,6 +782,10 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
  */
 #define atomic64_add_negative(i, v) (atomic64_add_return(i, (v)) < 0)
 
+#else /* !CONFIG_64BIT */
+
+#include <asm-generic/atomic64.h>
+
 #endif /* CONFIG_64BIT */
 
 /*
diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h
index 613f6912dfc1..dbc51065df5b 100644
--- a/arch/mips/include/asm/compat.h
+++ b/arch/mips/include/asm/compat.h
@@ -145,7 +145,7 @@ static inline compat_uptr_t ptr_to_compat(void __user *uptr)
         return (u32)(unsigned long)uptr;
 }
 
-static inline void __user *compat_alloc_user_space(long len)
+static inline void __user *arch_compat_alloc_user_space(long len)
 {
         struct pt_regs *regs = (struct pt_regs *)
                 ((unsigned long) current_thread_info() + THREAD_SIZE - 32) - 1;
diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
index 2cb2f0c2c4f8..3532e2c5f098 100644
--- a/arch/mips/include/asm/cop2.h
+++ b/arch/mips/include/asm/cop2.h
@@ -24,7 +24,7 @@ extern int cu2_notifier_call_chain(unsigned long val, void *v);
 
 #define cu2_notifier(fn, pri)                                           \
 ({                                                                      \
-        static struct notifier_block fn##_nb __cpuinitdata = {          \
+        static struct notifier_block fn##_nb = {                        \
                 .notifier_call = fn,                                    \
                 .priority = pri                                         \
         };                                                              \
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
index 9b9436a4d816..86548da650e7 100644
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -321,6 +321,7 @@ struct gic_intrmask_regs {
  */
 struct gic_intr_map {
         unsigned int cpunum;    /* Directed to this CPU */
+#define GIC_UNUSED              0xdead                  /* Dummy data */
         unsigned int pin;       /* Directed to this Pin */
         unsigned int polarity;  /* Polarity : +/-       */
         unsigned int trigtype;  /* Trigger  : Edge/Levl */
diff --git a/arch/mips/include/asm/mach-tx49xx/kmalloc.h b/arch/mips/include/asm/mach-tx49xx/kmalloc.h
index b74caf65482b..ff9a8b86cb93 100644
--- a/arch/mips/include/asm/mach-tx49xx/kmalloc.h
+++ b/arch/mips/include/asm/mach-tx49xx/kmalloc.h
@@ -1,6 +1,6 @@
 #ifndef __ASM_MACH_TX49XX_KMALLOC_H
 #define __ASM_MACH_TX49XX_KMALLOC_H
 
-#define ARCH_KMALLOC_MINALIGN   L1_CACHE_BYTES
+#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
 
 #endif /* __ASM_MACH_TX49XX_KMALLOC_H */
diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h
index cea872fc6f5c..d11aa02a956a 100644
--- a/arch/mips/include/asm/mips-boards/maltaint.h
+++ b/arch/mips/include/asm/mips-boards/maltaint.h
@@ -88,9 +88,6 @@
 
 #define GIC_EXT_INTR(x)         x
 
-/* Dummy data */
-#define X                       0xdead
-
 /* External Interrupts used for IPI */
 #define GIC_IPI_EXT_INTR_RESCHED_VPE0   16
 #define GIC_IPI_EXT_INTR_CALLFNC_VPE0   17
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index a16beafcea91..e59cd1ac09c2 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -150,6 +150,20 @@ typedef struct { unsigned long pgprot; } pgprot_t;
     ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET)
 #endif
 #define __va(x)         ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET))
+
+/*
+ * RELOC_HIDE was originally added by 6007b903dfe5f1d13e0c711ac2894bdd4a61b1ad
+ * (lmo) rsp. 8431fd094d625b94d364fe393076ccef88e6ce18 (kernel.org).  The
+ * discussion can be found in lkml posting
+ * <a2ebde260608230500o3407b108hc03debb9da6e62c@mail.gmail.com> which is
+ * archived at http://lists.linuxcoding.com/kernel/2006-q3/msg17360.html
+ *
+ * It is unclear if the misscompilations mentioned in
+ * http://lkml.org/lkml/2010/8/8/138 also affect MIPS so we keep this one
+ * until GCC 3.x has been retired before we can apply
+ * https://patchwork.linux-mips.org/patch/1541/
+ */
+
 #define __pa_symbol(x)  __pa(RELOC_HIDE((unsigned long)(x), 0))
 
 #define pfn_to_kaddr(pfn)       __va((pfn) << PAGE_SHIFT)
diff --git a/arch/mips/include/asm/siginfo.h b/arch/mips/include/asm/siginfo.h
index 96e28f18dad1..1ca64b4d33d9 100644
--- a/arch/mips/include/asm/siginfo.h
+++ b/arch/mips/include/asm/siginfo.h
@@ -88,6 +88,7 @@ typedef struct siginfo {
 #ifdef __ARCH_SI_TRAPNO
                         int _trapno;    /* TRAP # which caused the signal */
 #endif
+                        short _addr_lsb;
                 } _sigfault;
 
                 /* SIGPOLL, SIGXFSZ (To do ...)  */
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 2376f2e06e47..70df9c0d3c5b 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -146,7 +146,8 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define _TIF_LOAD_WATCH         (1<<TIF_LOAD_WATCH)
 
 /* work to do on interrupt/exception return */
-#define _TIF_WORK_MASK          (0x0000ffef & ~_TIF_SECCOMP)
+#define _TIF_WORK_MASK          (0x0000ffef &                           \
+                                        ~(_TIF_SECCOMP | _TIF_SYSCALL_AUDIT))
 /* work to do on any return to u-space */
 #define _TIF_ALLWORK_MASK       (0x8000ffff & ~_TIF_SECCOMP)
 
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
index baa318a59c97..550725b881d5 100644
--- a/arch/mips/include/asm/unistd.h
+++ b/arch/mips/include/asm/unistd.h
@@ -356,16 +356,19 @@
 #define __NR_perf_event_open            (__NR_Linux + 333)
 #define __NR_accept4                    (__NR_Linux + 334)
 #define __NR_recvmmsg                   (__NR_Linux + 335)
+#define __NR_fanotify_init              (__NR_Linux + 336)
+#define __NR_fanotify_mark              (__NR_Linux + 337)
+#define __NR_prlimit64                  (__NR_Linux + 338)
 
 /*
  * Offset of the last Linux o32 flavoured syscall
  */
-#define __NR_Linux_syscalls             335
+#define __NR_Linux_syscalls             338
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
 
 #define __NR_O32_Linux                  4000
-#define __NR_O32_Linux_syscalls         335
+#define __NR_O32_Linux_syscalls         338
 
 #if _MIPS_SIM == _MIPS_SIM_ABI64
 
@@ -668,16 +671,19 @@
 #define __NR_perf_event_open            (__NR_Linux + 292)
 #define __NR_accept4                    (__NR_Linux + 293)
 #define __NR_recvmmsg                   (__NR_Linux + 294)
+#define __NR_fanotify_init              (__NR_Linux + 295)
+#define __NR_fanotify_mark              (__NR_Linux + 296)
+#define __NR_prlimit64                  (__NR_Linux + 297)
 
 /*
  * Offset of the last Linux 64-bit flavoured syscall
  */
-#define __NR_Linux_syscalls             294
+#define __NR_Linux_syscalls             297
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
 
 #define __NR_64_Linux                   5000
-#define __NR_64_Linux_syscalls          294
+#define __NR_64_Linux_syscalls          297
 
 #if _MIPS_SIM == _MIPS_SIM_NABI32
 
@@ -985,16 +991,19 @@
 #define __NR_accept4                    (__NR_Linux + 297)
 #define __NR_recvmmsg                   (__NR_Linux + 298)
 #define __NR_getdents64                 (__NR_Linux + 299)
+#define __NR_fanotify_init              (__NR_Linux + 300)
+#define __NR_fanotify_mark              (__NR_Linux + 301)
+#define __NR_prlimit64                  (__NR_Linux + 302)
 
 /*
  * Offset of the last N32 flavoured syscall
  */
-#define __NR_Linux_syscalls             299
+#define __NR_Linux_syscalls             302
 
 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
 
 #define __NR_N32_Linux                  6000
-#define __NR_N32_Linux_syscalls         299
+#define __NR_N32_Linux_syscalls         302
 
 #ifdef __KERNEL__
 
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c
index b181f2f0ea8e..82ba9f62f49e 100644
--- a/arch/mips/kernel/irq-gic.c
+++ b/arch/mips/kernel/irq-gic.c
@@ -7,7 +7,6 @@
 #include <asm/io.h>
 #include <asm/gic.h>
 #include <asm/gcmpregs.h>
-#include <asm/mips-boards/maltaint.h>
 #include <asm/irq.h>
 #include <linux/hardirq.h>
 #include <asm-generic/bitops/find.h>
@@ -131,7 +130,7 @@ static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
         int             i;
 
         irq -= _irqbase;
-        pr_debug(KERN_DEBUG "%s(%d) called\n", __func__, irq);
+        pr_debug("%s(%d) called\n", __func__, irq);
         cpumask_and(&tmp, cpumask, cpu_online_mask);
         if (cpus_empty(tmp))
                 return -1;
@@ -222,7 +221,7 @@ static void __init gic_basic_init(int numintrs, int numvpes,
         /* Setup specifics */
         for (i = 0; i < mapsize; i++) {
                 cpu = intrmap[i].cpunum;
-                if (cpu == X)
+                if (cpu == GIC_UNUSED)
                         continue;
                 if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
                         continue;
diff --git a/arch/mips/kernel/kgdb.c b/arch/mips/kernel/kgdb.c
index 1f4e2fa64140..f4546e97c60d 100644
--- a/arch/mips/kernel/kgdb.c
+++ b/arch/mips/kernel/kgdb.c
@@ -283,7 +283,7 @@ static int kgdb_mips_notify(struct notifier_block *self, unsigned long cmd,
         struct pt_regs *regs = args->regs;
         int trap = (regs->cp0_cause & 0x7c) >> 2;
 
-        /* Userpace events, ignore. */
+        /* Userspace events, ignore. */
         if (user_mode(regs))
                 return NOTIFY_DONE;
 
diff --git a/arch/mips/kernel/kspd.c b/arch/mips/kernel/kspd.c
index 80e2ba694bab..29811f043399 100644
--- a/arch/mips/kernel/kspd.c
+++ b/arch/mips/kernel/kspd.c
@@ -251,7 +251,7 @@ void sp_work_handle_request(void)
                 memset(&tz, 0, sizeof(tz));
                 if ((ret.retval = sp_syscall(__NR_gettimeofday, (int)&tv,
                                              (int)&tz, 0, 0)) == 0)
-                ret.retval = tv.tv_sec;
+                        ret.retval = tv.tv_sec;
                 break;
 
         case MTSP_SYSCALL_EXIT:
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index c2dab140dc98..6343b4a5b835 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -341,3 +341,10 @@ asmlinkage long sys32_lookup_dcookie(u32 a0, u32 a1, char __user *buf,
 {
         return sys_lookup_dcookie(merge_64(a0, a1), buf, len);
 }
+
+SYSCALL_DEFINE6(32_fanotify_mark, int, fanotify_fd, unsigned int, flags,
+                u64, a3, u64, a4, int, dfd, const char  __user *, pathname)
+{
+        return sys_fanotify_mark(fanotify_fd, flags, merge_64(a3, a4),
+                                 dfd, pathname);
+}
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index 17202bbe843f..584415eef8c9 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -583,7 +583,10 @@ einval:	li	v0, -ENOSYS
         sys     sys_rt_tgsigqueueinfo   4
         sys     sys_perf_event_open     5
         sys     sys_accept4             4
-        sys     sys_recvmmsg            5
+        sys     sys_recvmmsg            5       /* 4335 */
+        sys     sys_fanotify_init       2
+        sys     sys_fanotify_mark       6
+        sys     sys_prlimit64           4
         .endm
 
         /* We pre-compute the number of _instruction_ bytes needed to
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index a8a6c596eb04..5573f8e4e326 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -416,9 +416,12 @@ sys_call_table:
         PTR     sys_pipe2
         PTR     sys_inotify_init1
         PTR     sys_preadv
-        PTR     sys_pwritev                     /* 5390 */
+        PTR     sys_pwritev                     /* 5290 */
         PTR     sys_rt_tgsigqueueinfo
         PTR     sys_perf_event_open
         PTR     sys_accept4
-        PTR     sys_recvmmsg
+        PTR     sys_recvmmsg
+        PTR     sys_fanotify_init               /* 5295 */
+        PTR     sys_fanotify_mark
+        PTR     sys_prlimit64
         .size   sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index a3d66137731a..1e38ec97672e 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -419,5 +419,8 @@ EXPORT(sysn32_call_table)
         PTR     sys_perf_event_open
         PTR     sys_accept4
         PTR     compat_sys_recvmmsg
-        PTR     sys_getdents
+        PTR     sys_getdents64
+        PTR     sys_fanotify_init               /* 6300 */
+        PTR     sys_fanotify_mark
+        PTR     sys_prlimit64
         .size   sysn32_call_table,.-sysn32_call_table
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 813689ef2384..171979fc98e5 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -538,5 +538,8 @@ sys_call_table:
         PTR     compat_sys_rt_tgsigqueueinfo
         PTR     sys_perf_event_open
         PTR     sys_accept4
-        PTR     compat_sys_recvmmsg
+        PTR     compat_sys_recvmmsg             /* 4335 */
+        PTR     sys_fanotify_init
+        PTR     sys_32_fanotify_mark
+        PTR     sys_prlimit64
         .size   sys_call_table,.-sys_call_table
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 7ba890860d98..469d4019f795 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -44,27 +44,39 @@ static inline int cpu_is_noncoherent_r10000(struct device *dev)
 
 static gfp_t massage_gfp_flags(const struct device *dev, gfp_t gfp)
 {
+        gfp_t dma_flag;
+
         /* ignore region specifiers */
         gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM);
 
-#ifdef CONFIG_ZONE_DMA
+#ifdef CONFIG_ISA
         if (dev == NULL)
-                gfp |= __GFP_DMA;
-        else if (dev->coherent_dma_mask < DMA_BIT_MASK(24))
-                gfp |= __GFP_DMA;
+                dma_flag = __GFP_DMA;
         else
 #endif
-#ifdef CONFIG_ZONE_DMA32
+#if defined(CONFIG_ZONE_DMA32) && defined(CONFIG_ZONE_DMA)
              if (dev->coherent_dma_mask < DMA_BIT_MASK(32))
-                gfp |= __GFP_DMA32;
+                        dma_flag = __GFP_DMA;
+        else if (dev->coherent_dma_mask < DMA_BIT_MASK(64))
+                        dma_flag = __GFP_DMA32;
+        else
+#endif
+#if defined(CONFIG_ZONE_DMA32) && !defined(CONFIG_ZONE_DMA)
+             if (dev->coherent_dma_mask < DMA_BIT_MASK(64))
+                dma_flag = __GFP_DMA32;
+        else
+#endif
+#if defined(CONFIG_ZONE_DMA) && !defined(CONFIG_ZONE_DMA32)
+             if (dev->coherent_dma_mask < DMA_BIT_MASK(64))
+                dma_flag = __GFP_DMA;
         else
 #endif
-                ;
+                dma_flag = 0;
 
         /* Don't invoke OOM killer */
         gfp |= __GFP_NORETRY;
 
-        return gfp;
+        return gfp | dma_flag;
 }
 
 void *dma_alloc_noncoherent(struct device *dev, size_t size,
diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c
index 1ef75cd80a0d..274af3be1442 100644
--- a/arch/mips/mm/sc-rm7k.c
+++ b/arch/mips/mm/sc-rm7k.c
@@ -30,7 +30,7 @@
 #define tc_lsize        32
 
 extern unsigned long icache_way_size, dcache_way_size;
-unsigned long tcache_size;
+static unsigned long tcache_size;
 
 #include <asm/r4kcache.h>
 
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index 15949b0be811..b79b24afe3a2 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -385,6 +385,8 @@ static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
  */
 
 #define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK
+#define X GIC_UNUSED
+
 static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
         { X, X,            X,           X,              0 },
         { X, X,            X,           X,              0 },
@@ -404,6 +406,7 @@ static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
         { X, X,            X,           X,              0 },
         /* The remainder of this table is initialised by fill_ipi_map */
 };
+#undef X
 
 /*
  * GCMP needs to be detected before any SMP initialisation
diff --git a/arch/mips/pci/pci-rc32434.c b/arch/mips/pci/pci-rc32434.c
index 71f7d27b0d4c..f31218e17d3c 100644
--- a/arch/mips/pci/pci-rc32434.c
+++ b/arch/mips/pci/pci-rc32434.c
@@ -118,7 +118,7 @@ static int __init rc32434_pcibridge_init(void)
         if (!((pcicvalue == PCIM_H_EA) ||
               (pcicvalue == PCIM_H_IA_FIX) ||
               (pcicvalue == PCIM_H_IA_RR))) {
-                pr_err(KERN_ERR "PCI init error!!!\n");
+                pr_err("PCI init error!!!\n");
                 /* Not in Host Mode, return ERROR */
                 return -1;
         }
diff --git a/arch/mips/pnx8550/common/reset.c b/arch/mips/pnx8550/common/reset.c
index fadd8744a6bc..e7a12ff304b9 100644
--- a/arch/mips/pnx8550/common/reset.c
+++ b/arch/mips/pnx8550/common/reset.c
@@ -22,29 +22,19 @@
  */
 #include <linux/kernel.h>
 
+#include <asm/processor.h>
 #include <asm/reboot.h>
 #include <glb.h>
 
 void pnx8550_machine_restart(char *command)
 {
-        char head[] = "************* Machine restart *************";
-        char foot[] = "*******************************************";
-
-        printk("\n\n");
-        printk("%s\n", head);
-        if (command != NULL)
-                printk("* %s\n", command);
-        printk("%s\n", foot);
-
         PNX8550_RST_CTL = PNX8550_RST_DO_SW_RST;
 }
 
 void pnx8550_machine_halt(void)
 {
-        printk("*** Machine halt. (Not implemented) ***\n");
-}
-
-void pnx8550_machine_power_off(void)
-{
-        printk("*** Machine power off.  (Not implemented) ***\n");
+        while (1) {
+                if (cpu_wait)
+                        cpu_wait();
+        }
 }
diff --git a/arch/mips/pnx8550/common/setup.c b/arch/mips/pnx8550/common/setup.c
index 64246c9c875c..43cb3945fdbf 100644
--- a/arch/mips/pnx8550/common/setup.c
+++ b/arch/mips/pnx8550/common/setup.c
@@ -44,7 +44,6 @@
 extern void __init board_setup(void);
 extern void pnx8550_machine_restart(char *);
 extern void pnx8550_machine_halt(void);
-extern void pnx8550_machine_power_off(void);
 extern struct resource ioport_resource;
 extern struct resource iomem_resource;
 extern char *prom_getcmdline(void);
@@ -100,7 +99,7 @@ void __init plat_mem_setup(void)
 
         _machine_restart = pnx8550_machine_restart;
         _machine_halt = pnx8550_machine_halt;
-        pm_power_off = pnx8550_machine_power_off;
+        pm_power_off = pnx8550_machine_halt;
 
         /* Clear the Global 2 Register, PCI Inta Output Enable Registers
            Bit 1:Enable DAC Powerdown
diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig
index 444b9f918fdf..7c2a2f7f8dc1 100644
--- a/arch/mn10300/Kconfig
+++ b/arch/mn10300/Kconfig
@@ -8,7 +8,6 @@ mainmenu "Linux Kernel Configuration"
 config MN10300
         def_bool y
         select HAVE_OPROFILE
-        select HAVE_ARCH_TRACEHOOK
 
 config AM33
         def_bool y
diff --git a/arch/mn10300/Kconfig.debug b/arch/mn10300/Kconfig.debug
index ff80e86b9bd2..ce83c74b3fd7 100644
--- a/arch/mn10300/Kconfig.debug
+++ b/arch/mn10300/Kconfig.debug
@@ -101,7 +101,7 @@ config GDBSTUB_DEBUG_BREAKPOINT
 
 choice
         prompt "GDB stub port"
-        default GDBSTUB_TTYSM0
+        default GDBSTUB_ON_TTYSM0
         depends on GDBSTUB
         help
           Select the serial port used for GDB-stub.
diff --git a/arch/mn10300/include/asm/bitops.h b/arch/mn10300/include/asm/bitops.h
index f49ac49e09ad..3f50e9661076 100644
--- a/arch/mn10300/include/asm/bitops.h
+++ b/arch/mn10300/include/asm/bitops.h
@@ -229,9 +229,9 @@ int ffs(int x)
 #include <asm-generic/bitops/hweight.h>
 
 #define ext2_set_bit_atomic(lock, nr, addr) \
-        test_and_set_bit((nr) ^ 0x18, (addr))
+        test_and_set_bit((nr), (addr))
 #define ext2_clear_bit_atomic(lock, nr, addr) \
-        test_and_clear_bit((nr) ^ 0x18, (addr))
+        test_and_clear_bit((nr), (addr))
 
 #include <asm-generic/bitops/ext2-non-atomic.h>
 #include <asm-generic/bitops/minix-le.h>
diff --git a/arch/mn10300/include/asm/signal.h b/arch/mn10300/include/asm/signal.h
index 7e891fce2370..1865d72a86ff 100644
--- a/arch/mn10300/include/asm/signal.h
+++ b/arch/mn10300/include/asm/signal.h
@@ -78,7 +78,7 @@ typedef unsigned long sigset_t;
 
 /* These should not be considered constants from userland.  */
 #define SIGRTMIN        32
-#define SIGRTMAX        (_NSIG-1)
+#define SIGRTMAX        _NSIG
 
 /*
  * SA_FLAGS values:
diff --git a/arch/mn10300/kernel/mn10300-serial.c b/arch/mn10300/kernel/mn10300-serial.c
index 9d49073e827a..db509dd80565 100644
--- a/arch/mn10300/kernel/mn10300-serial.c
+++ b/arch/mn10300/kernel/mn10300-serial.c
@@ -156,17 +156,17 @@ struct mn10300_serial_port mn10300_serial_port_sif0 = {
         ._intr          = &SC0ICR,
         ._rxb           = &SC0RXB,
         ._txb           = &SC0TXB,
-        .rx_name        = "ttySM0/Rx",
-        .tx_name        = "ttySM0/Tx",
+        .rx_name        = "ttySM0:Rx",
+        .tx_name        = "ttySM0:Tx",
 #ifdef CONFIG_MN10300_TTYSM0_TIMER8
-        .tm_name        = "ttySM0/Timer8",
+        .tm_name        = "ttySM0:Timer8",
         ._tmxmd         = &TM8MD,
         ._tmxbr         = &TM8BR,
         ._tmicr         = &TM8ICR,
         .tm_irq         = TM8IRQ,
         .div_timer      = MNSCx_DIV_TIMER_16BIT,
 #else /* CONFIG_MN10300_TTYSM0_TIMER2 */
-        .tm_name        = "ttySM0/Timer2",
+        .tm_name        = "ttySM0:Timer2",
         ._tmxmd         = &TM2MD,
         ._tmxbr         = (volatile u16 *) &TM2BR,
         ._tmicr         = &TM2ICR,
@@ -209,17 +209,17 @@ struct mn10300_serial_port mn10300_serial_port_sif1 = {
         ._intr          = &SC1ICR,
         ._rxb           = &SC1RXB,
         ._txb           = &SC1TXB,
-        .rx_name        = "ttySM1/Rx",
-        .tx_name        = "ttySM1/Tx",
+        .rx_name        = "ttySM1:Rx",
+        .tx_name        = "ttySM1:Tx",
 #ifdef CONFIG_MN10300_TTYSM1_TIMER9
-        .tm_name        = "ttySM1/Timer9",
+        .tm_name        = "ttySM1:Timer9",
         ._tmxmd         = &TM9MD,
         ._tmxbr         = &TM9BR,
         ._tmicr         = &TM9ICR,
         .tm_irq         = TM9IRQ,
         .div_timer      = MNSCx_DIV_TIMER_16BIT,
 #else /* CONFIG_MN10300_TTYSM1_TIMER3 */
-        .tm_name        = "ttySM1/Timer3",
+        .tm_name        = "ttySM1:Timer3",
         ._tmxmd         = &TM3MD,
         ._tmxbr         = (volatile u16 *) &TM3BR,
         ._tmicr         = &TM3ICR,
@@ -260,9 +260,9 @@ struct mn10300_serial_port mn10300_serial_port_sif2 = {
         .uart.lock      =
         __SPIN_LOCK_UNLOCKED(mn10300_serial_port_sif2.uart.lock),
         .name           = "ttySM2",
-        .rx_name        = "ttySM2/Rx",
-        .tx_name        = "ttySM2/Tx",
-        .tm_name        = "ttySM2/Timer10",
+        .rx_name        = "ttySM2:Rx",
+        .tx_name        = "ttySM2:Tx",
+        .tm_name        = "ttySM2:Timer10",
         ._iobase        = &SC2CTR,
         ._control       = &SC2CTR,
         ._status        = &SC2STR,
diff --git a/arch/mn10300/kernel/module.c b/arch/mn10300/kernel/module.c
index 6aea7fd76993..196a111e2e29 100644
--- a/arch/mn10300/kernel/module.c
+++ b/arch/mn10300/kernel/module.c
@@ -206,7 +206,7 @@ int module_finalize(const Elf_Ehdr *hdr,
                     const Elf_Shdr *sechdrs,
                     struct module *me)
 {
-        return module_bug_finalize(hdr, sechdrs, me);
+        return 0;
 }
 
 /*
@@ -214,5 +214,4 @@ int module_finalize(const Elf_Ehdr *hdr,
  */
 void module_arch_cleanup(struct module *mod)
 {
-        module_bug_cleanup(mod);
 }
diff --git a/arch/mn10300/kernel/signal.c b/arch/mn10300/kernel/signal.c
index 717db14c2cc3..d4de05ab7864 100644
--- a/arch/mn10300/kernel/signal.c
+++ b/arch/mn10300/kernel/signal.c
@@ -65,10 +65,10 @@ asmlinkage long sys_sigaction(int sig,
                 old_sigset_t mask;
                 if (verify_area(VERIFY_READ, act, sizeof(*act)) ||
                     __get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
-                    __get_user(new_ka.sa.sa_restorer, &act->sa_restorer))
+                    __get_user(new_ka.sa.sa_restorer, &act->sa_restorer) ||
+                    __get_user(new_ka.sa.sa_flags, &act->sa_flags) ||
+                    __get_user(mask, &act->sa_mask))
                         return -EFAULT;
-                __get_user(new_ka.sa.sa_flags, &act->sa_flags);
-                __get_user(mask, &act->sa_mask);
                 siginitset(&new_ka.sa.sa_mask, mask);
         }
 
@@ -77,10 +77,10 @@ asmlinkage long sys_sigaction(int sig,
         if (!ret && oact) {
                 if (verify_area(VERIFY_WRITE, oact, sizeof(*oact)) ||
                     __put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
-                    __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer))
+                    __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer) ||
+                    __put_user(old_ka.sa.sa_flags, &oact->sa_flags) ||
+                    __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask))
                         return -EFAULT;
-                __put_user(old_ka.sa.sa_flags, &oact->sa_flags);
-                __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask);
         }
 
         return ret;
@@ -102,6 +102,9 @@ static int restore_sigcontext(struct pt_regs *regs,
 {
         unsigned int err = 0;
 
+        /* Always make any pending restarted system calls return -EINTR */
+        current_thread_info()->restart_block.fn = do_no_restart_syscall;
+
         if (is_using_fpu(current))
                 fpu_kill_state(current);
 
@@ -330,8 +333,6 @@ static int setup_frame(int sig, struct k_sigaction *ka, sigset_t *set,
         regs->d0 = sig;
         regs->d1 = (unsigned long) &frame->sc;
 
-        set_fs(USER_DS);
-
         /* the tracer may want to single-step inside the handler */
         if (test_thread_flag(TIF_SINGLESTEP))
                 ptrace_notify(SIGTRAP);
@@ -345,7 +346,7 @@ static int setup_frame(int sig, struct k_sigaction *ka, sigset_t *set,
         return 0;
 
 give_sigsegv:
-        force_sig(SIGSEGV, current);
+        force_sigsegv(sig, current);
         return -EFAULT;
 }
 
@@ -413,8 +414,6 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
         regs->d0 = sig;
         regs->d1 = (long) &frame->info;
 
-        set_fs(USER_DS);
-
         /* the tracer may want to single-step inside the handler */
         if (test_thread_flag(TIF_SINGLESTEP))
                 ptrace_notify(SIGTRAP);
@@ -428,10 +427,16 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
         return 0;
 
 give_sigsegv:
-        force_sig(SIGSEGV, current);
+        force_sigsegv(sig, current);
         return -EFAULT;
 }
 
+static inline void stepback(struct pt_regs *regs)
+{
+        regs->pc -= 2;
+        regs->orig_d0 = -1;
+}
+
 /*
  * handle the actual delivery of a signal to userspace
  */
@@ -459,7 +464,7 @@ static int handle_signal(int sig,
                         /* fallthrough */
                 case -ERESTARTNOINTR:
                         regs->d0 = regs->orig_d0;
-                        regs->pc -= 2;
+                        stepback(regs);
                 }
         }
 
@@ -527,12 +532,12 @@ static void do_signal(struct pt_regs *regs)
                 case -ERESTARTSYS:
                 case -ERESTARTNOINTR:
                         regs->d0 = regs->orig_d0;
-                        regs->pc -= 2;
+                        stepback(regs);
                         break;
 
                 case -ERESTART_RESTARTBLOCK:
                         regs->d0 = __NR_restart_syscall;
-                        regs->pc -= 2;
+                        stepback(regs);
                         break;
                 }
         }
diff --git a/arch/mn10300/mm/Makefile b/arch/mn10300/mm/Makefile
index 28b9d983db0c..1557277fbc5c 100644
--- a/arch/mn10300/mm/Makefile
+++ b/arch/mn10300/mm/Makefile
@@ -2,13 +2,11 @@
 # Makefile for the MN10300-specific memory management code
 #
 
+cacheflush-y    := cache.o cache-mn10300.o
+cacheflush-$(CONFIG_MN10300_CACHE_WBACK) += cache-flush-mn10300.o
+
+cacheflush-$(CONFIG_MN10300_CACHE_DISABLED) := cache-disabled.o
+
 obj-y := \
         init.o fault.o pgtable.o extable.o tlb-mn10300.o mmu-context.o \
-        misalignment.o dma-alloc.o
-
-ifneq ($(CONFIG_MN10300_CACHE_DISABLED),y)
-obj-y   += cache.o cache-mn10300.o
-ifeq ($(CONFIG_MN10300_CACHE_WBACK),y)
-obj-y   += cache-flush-mn10300.o
-endif
-endif
+        misalignment.o dma-alloc.o $(cacheflush-y)
diff --git a/arch/mn10300/mm/cache-disabled.c b/arch/mn10300/mm/cache-disabled.c
new file mode 100644
index 000000000000..f669ea42aba6
--- /dev/null
+++ b/arch/mn10300/mm/cache-disabled.c
@@ -0,0 +1,21 @@
+/* Handle the cache being disabled
+ *
+ * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/mm.h>
+
+/*
+ * allow userspace to flush the instruction cache
+ */
+asmlinkage long sys_cacheflush(unsigned long start, unsigned long end)
+{
+        if (end < start)
+                return -EINVAL;
+        return 0;
+}
diff --git a/arch/mn10300/mm/cache.c b/arch/mn10300/mm/cache.c
index 1b76719ec1c3..9261217e8d2c 100644
--- a/arch/mn10300/mm/cache.c
+++ b/arch/mn10300/mm/cache.c
@@ -54,13 +54,30 @@ EXPORT_SYMBOL(flush_icache_page);
 void flush_icache_range(unsigned long start, unsigned long end)
 {
 #ifdef CONFIG_MN10300_CACHE_WBACK
-        unsigned long addr, size, off;
+        unsigned long addr, size, base, off;
         struct page *page;
         pgd_t *pgd;
         pud_t *pud;
         pmd_t *pmd;
         pte_t *ppte, pte;
 
+        if (end > 0x80000000UL) {
+                /* addresses above 0xa0000000 do not go through the cache */
+                if (end > 0xa0000000UL) {
+                        end = 0xa0000000UL;
+                        if (start >= end)
+                                return;
+                }
+
+                /* kernel addresses between 0x80000000 and 0x9fffffff do not
+                 * require page tables, so we just map such addresses directly */
+                base = (start >= 0x80000000UL) ? start : 0x80000000UL;
+                mn10300_dcache_flush_range(base, end);
+                if (base == start)
+                        goto invalidate;
+                end = base;
+        }
+
         for (; start < end; start += size) {
                 /* work out how much of the page to flush */
                 off = start & (PAGE_SIZE - 1);
@@ -104,6 +121,7 @@ void flush_icache_range(unsigned long start, unsigned long end)
         }
 #endif
 
+invalidate:
         mn10300_icache_inv();
 }
 EXPORT_SYMBOL(flush_icache_range);
diff --git a/arch/parisc/include/asm/compat.h b/arch/parisc/include/asm/compat.h
index 02b77baa5da6..efa0b60c63fe 100644
--- a/arch/parisc/include/asm/compat.h
+++ b/arch/parisc/include/asm/compat.h
@@ -147,7 +147,7 @@ static inline compat_uptr_t ptr_to_compat(void __user *uptr)
         return (u32)(unsigned long)uptr;
 }
 
-static __inline__ void __user *compat_alloc_user_space(long len)
+static __inline__ void __user *arch_compat_alloc_user_space(long len)
 {
         struct pt_regs *regs = &current->thread.regs;
         return (void __user *)regs->gr[30];
diff --git a/arch/parisc/kernel/module.c b/arch/parisc/kernel/module.c
index 159a2b81e90c..6e81bb596e5b 100644
--- a/arch/parisc/kernel/module.c
+++ b/arch/parisc/kernel/module.c
@@ -941,11 +941,10 @@ int module_finalize(const Elf_Ehdr *hdr,
         nsyms = newptr - (Elf_Sym *)symhdr->sh_addr;
         DEBUGP("NEW num_symtab %lu\n", nsyms);
         symhdr->sh_size = nsyms * sizeof(Elf_Sym);
-        return module_bug_finalize(hdr, sechdrs, me);
+        return 0;
 }
 
 void module_arch_cleanup(struct module *mod)
 {
         deregister_unwind_table(mod);
-        module_bug_cleanup(mod);
 }
diff --git a/arch/powerpc/include/asm/compat.h b/arch/powerpc/include/asm/compat.h
index 396d21a80058..a11d4eac4f97 100644
--- a/arch/powerpc/include/asm/compat.h
+++ b/arch/powerpc/include/asm/compat.h
@@ -134,7 +134,7 @@ static inline compat_uptr_t ptr_to_compat(void __user *uptr)
         return (u32)(unsigned long)uptr;
 }
 
-static inline void __user *compat_alloc_user_space(long len)
+static inline void __user *arch_compat_alloc_user_space(long len)
 {
         struct pt_regs *regs = current->thread.regs;
         unsigned long usp = regs->gpr[1];
diff --git a/arch/powerpc/kernel/module.c b/arch/powerpc/kernel/module.c
index 477c663e0140..49cee9df225b 100644
--- a/arch/powerpc/kernel/module.c
+++ b/arch/powerpc/kernel/module.c
@@ -63,11 +63,6 @@ int module_finalize(const Elf_Ehdr *hdr,
                 const Elf_Shdr *sechdrs, struct module *me)
 {
         const Elf_Shdr *sect;
-        int err;
-
-        err = module_bug_finalize(hdr, sechdrs, me);
-        if (err)
-                return err;
 
         /* Apply feature fixups */
         sect = find_section(hdr, sechdrs, "__ftr_fixup");
@@ -101,5 +96,4 @@ int module_finalize(const Elf_Ehdr *hdr,
 
 void module_arch_cleanup(struct module *mod)
 {
-        module_bug_cleanup(mod);
 }
diff --git a/arch/powerpc/kernel/signal.c b/arch/powerpc/kernel/signal.c
index 7109f5b1baa8..2300426e531a 100644
--- a/arch/powerpc/kernel/signal.c
+++ b/arch/powerpc/kernel/signal.c
@@ -138,6 +138,7 @@ static int do_signal_pending(sigset_t *oldset, struct pt_regs *regs)
                         ti->local_flags &= ~_TLF_RESTORE_SIGMASK;
                         sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
                 }
+                regs->trap = 0;
                 return 0;               /* no signals delivered */
         }
 
@@ -164,6 +165,7 @@ static int do_signal_pending(sigset_t *oldset, struct pt_regs *regs)
                 ret = handle_rt_signal64(signr, &ka, &info, oldset, regs);
         }
 
+        regs->trap = 0;
         if (ret) {
                 spin_lock_irq(&current->sighand->siglock);
                 sigorsets(&current->blocked, &current->blocked,
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index 266610119f66..b96a3a010c26 100644
--- a/arch/powerpc/kernel/signal_32.c
+++ b/arch/powerpc/kernel/signal_32.c
@@ -511,6 +511,7 @@ static long restore_user_regs(struct pt_regs *regs,
         if (!sig)
                 save_r2 = (unsigned int)regs->gpr[2];
         err = restore_general_regs(regs, sr);
+        regs->trap = 0;
         err |= __get_user(msr, &sr->mc_gregs[PT_MSR]);
         if (!sig)
                 regs->gpr[2] = (unsigned long) save_r2;
@@ -884,7 +885,6 @@ int handle_rt_signal32(unsigned long sig, struct k_sigaction *ka,
         regs->nip = (unsigned long) ka->sa.sa_handler;
         /* enter the signal handler in big-endian mode */
         regs->msr &= ~MSR_LE;
-        regs->trap = 0;
         return 1;
 
 badframe:
@@ -1228,7 +1228,6 @@ int handle_signal32(unsigned long sig, struct k_sigaction *ka,
         regs->nip = (unsigned long) ka->sa.sa_handler;
         /* enter the signal handler in big-endian mode */
         regs->msr &= ~MSR_LE;
-        regs->trap = 0;
 
         return 1;
 
diff --git a/arch/powerpc/kernel/signal_64.c b/arch/powerpc/kernel/signal_64.c
index 2fe6fc64b614..27c4a4584f80 100644
--- a/arch/powerpc/kernel/signal_64.c
+++ b/arch/powerpc/kernel/signal_64.c
@@ -178,7 +178,7 @@ static long restore_sigcontext(struct pt_regs *regs, sigset_t *set, int sig,
         err |= __get_user(regs->xer, &sc->gp_regs[PT_XER]);
         err |= __get_user(regs->ccr, &sc->gp_regs[PT_CCR]);
         /* skip SOFTE */
-        err |= __get_user(regs->trap, &sc->gp_regs[PT_TRAP]);
+        regs->trap = 0;
         err |= __get_user(regs->dar, &sc->gp_regs[PT_DAR]);
         err |= __get_user(regs->dsisr, &sc->gp_regs[PT_DSISR]);
         err |= __get_user(regs->result, &sc->gp_regs[PT_RESULT]);
diff --git a/arch/powerpc/platforms/512x/clock.c b/arch/powerpc/platforms/512x/clock.c
index 5b243bd3eb3b..3dc2a8d262b8 100644
--- a/arch/powerpc/platforms/512x/clock.c
+++ b/arch/powerpc/platforms/512x/clock.c
@@ -57,7 +57,7 @@ static struct clk *mpc5121_clk_get(struct device *dev, const char *id)
         int id_match = 0;
 
         if (dev == NULL || id == NULL)
-                return NULL;
+                return clk;
 
         mutex_lock(&clocks_mutex);
         list_for_each_entry(p, &clocks, node) {
diff --git a/arch/powerpc/platforms/52xx/efika.c b/arch/powerpc/platforms/52xx/efika.c
index 45c0cb9b67e6..18c104820198 100644
--- a/arch/powerpc/platforms/52xx/efika.c
+++ b/arch/powerpc/platforms/52xx/efika.c
@@ -99,7 +99,7 @@ static void __init efika_pcisetup(void)
         if (bus_range == NULL || len < 2 * sizeof(int)) {
                 printk(KERN_WARNING EFIKA_PLATFORM_NAME
                        ": Can't get bus-range for %s\n", pcictrl->full_name);
-                return;
+                goto out_put;
         }
 
         if (bus_range[1] == bus_range[0])
@@ -111,12 +111,12 @@ static void __init efika_pcisetup(void)
         printk(" controlled by %s\n", pcictrl->full_name);
         printk("\n");
 
-        hose = pcibios_alloc_controller(of_node_get(pcictrl));
+        hose = pcibios_alloc_controller(pcictrl);
         if (!hose) {
                 printk(KERN_WARNING EFIKA_PLATFORM_NAME
                        ": Can't allocate PCI controller structure for %s\n",
                        pcictrl->full_name);
-                return;
+                goto out_put;
         }
 
         hose->first_busno = bus_range[0];
@@ -124,6 +124,9 @@ static void __init efika_pcisetup(void)
         hose->ops = &rtas_pci_ops;
 
         pci_process_bridge_OF_ranges(hose, pcictrl, 0);
+        return;
+out_put:
+        of_node_put(pcictrl);
 }
 
 #else
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c b/arch/powerpc/platforms/52xx/mpc52xx_common.c
index 6e905314ad5d..41f3a7eda1de 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_common.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_common.c
@@ -325,12 +325,16 @@ int mpc5200_psc_ac97_gpio_reset(int psc_number)
         clrbits32(&simple_gpio->simple_dvo, sync | out);
         clrbits8(&wkup_gpio->wkup_dvo, reset);
 
-        /* wait at lease 1 us */
-        udelay(2);
+        /* wait for 1 us */
+        udelay(1);
 
         /* Deassert reset */
         setbits8(&wkup_gpio->wkup_dvo, reset);
 
+        /* wait at least 200ns */
+        /* 7 ~= (200ns * timebase) / ns2sec */
+        __delay(7);
+
         /* Restore pin-muxing */
         out_be32(&simple_gpio->port_config, mux);
 
diff --git a/arch/s390/include/asm/compat.h b/arch/s390/include/asm/compat.h
index 104f2007f097..a875c2f542e1 100644
--- a/arch/s390/include/asm/compat.h
+++ b/arch/s390/include/asm/compat.h
@@ -181,7 +181,7 @@ static inline int is_compat_task(void)
 
 #endif
 
-static inline void __user *compat_alloc_user_space(long len)
+static inline void __user *arch_compat_alloc_user_space(long len)
 {
         unsigned long stack;
 
diff --git a/arch/s390/kernel/module.c b/arch/s390/kernel/module.c
index 22cfd634c355..f7167ee4604c 100644
--- a/arch/s390/kernel/module.c
+++ b/arch/s390/kernel/module.c
@@ -407,10 +407,9 @@ int module_finalize(const Elf_Ehdr *hdr,
 {
         vfree(me->arch.syminfo);
         me->arch.syminfo = NULL;
-        return module_bug_finalize(hdr, sechdrs, me);
+        return 0;
 }
 
 void module_arch_cleanup(struct module *mod)
 {
-        module_bug_cleanup(mod);
 }
diff --git a/arch/sh/kernel/module.c b/arch/sh/kernel/module.c
index 43adddfe4c04..ae0be697a89e 100644
--- a/arch/sh/kernel/module.c
+++ b/arch/sh/kernel/module.c
@@ -149,13 +149,11 @@ int module_finalize(const Elf_Ehdr *hdr,
         int ret = 0;
 
         ret |= module_dwarf_finalize(hdr, sechdrs, me);
-        ret |= module_bug_finalize(hdr, sechdrs, me);
 
         return ret;
 }
 
 void module_arch_cleanup(struct module *mod)
 {
-        module_bug_cleanup(mod);
         module_dwarf_cleanup(mod);
 }
diff --git a/arch/sparc/include/asm/compat.h b/arch/sparc/include/asm/compat.h
index 5016f76ea98a..6f57325bb883 100644
--- a/arch/sparc/include/asm/compat.h
+++ b/arch/sparc/include/asm/compat.h
@@ -167,7 +167,7 @@ static inline compat_uptr_t ptr_to_compat(void __user *uptr)
         return (u32)(unsigned long)uptr;
 }
 
-static inline void __user *compat_alloc_user_space(long len)
+static inline void __user *arch_compat_alloc_user_space(long len)
 {
         struct pt_regs *regs = current_thread_info()->kregs;
         unsigned long usp = regs->u_regs[UREG_I6];
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index 357ced3c33ff..6318e622cfb0 100644
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -1038,6 +1038,7 @@ static int __hw_perf_event_init(struct perf_event *event)
         if (atomic_read(&nmi_active) < 0)
                 return -ENODEV;
 
+        pmap = NULL;
         if (attr->type == PERF_TYPE_HARDWARE) {
                 if (attr->config >= sparc_pmu->max_events)
                         return -EINVAL;
@@ -1046,9 +1047,18 @@ static int __hw_perf_event_init(struct perf_event *event)
                 pmap = sparc_map_cache_event(attr->config);
                 if (IS_ERR(pmap))
                         return PTR_ERR(pmap);
-        } else
+        } else if (attr->type != PERF_TYPE_RAW)
                 return -EOPNOTSUPP;
 
+        if (pmap) {
+                hwc->event_base = perf_event_encode(pmap);
+        } else {
+                /* User gives us "(encoding << 16) | pic_mask" for
+                 * PERF_TYPE_RAW events.
+                 */
+                hwc->event_base = attr->config;
+        }
+
         /* We save the enable bits in the config_base.  */
         hwc->config_base = sparc_pmu->irq_bit;
         if (!attr->exclude_user)
@@ -1058,8 +1068,6 @@ static int __hw_perf_event_init(struct perf_event *event)
         if (!attr->exclude_hv)
                 hwc->config_base |= sparc_pmu->hv_bit;
 
-        hwc->event_base = perf_event_encode(pmap);
-
         n = 0;
         if (event->group_leader != event) {
                 n = collect_events(event->group_leader,
diff --git a/arch/sparc/kernel/signal32.c b/arch/sparc/kernel/signal32.c
index ea22cd373c64..75fad425e249 100644
--- a/arch/sparc/kernel/signal32.c
+++ b/arch/sparc/kernel/signal32.c
@@ -453,8 +453,66 @@ static int save_fpu_state32(struct pt_regs *regs, __siginfo_fpu_t __user *fpu)
         return err;
 }
 
-static void setup_frame32(struct k_sigaction *ka, struct pt_regs *regs,
-                          int signo, sigset_t *oldset)
+/* The I-cache flush instruction only works in the primary ASI, which
+ * right now is the nucleus, aka. kernel space.
+ *
+ * Therefore we have to kick the instructions out using the kernel
+ * side linear mapping of the physical address backing the user
+ * instructions.
+ */
+static void flush_signal_insns(unsigned long address)
+{
+        unsigned long pstate, paddr;
+        pte_t *ptep, pte;
+        pgd_t *pgdp;
+        pud_t *pudp;
+        pmd_t *pmdp;
+
+        /* Commit all stores of the instructions we are about to flush.  */
+        wmb();
+
+        /* Disable cross-call reception.  In this way even a very wide
+         * munmap() on another cpu can't tear down the page table
+         * hierarchy from underneath us, since that can't complete
+         * until the IPI tlb flush returns.
+         */
+
+        __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
+        __asm__ __volatile__("wrpr %0, %1, %%pstate"
+                                : : "r" (pstate), "i" (PSTATE_IE));
+
+        pgdp = pgd_offset(current->mm, address);
+        if (pgd_none(*pgdp))
+                goto out_irqs_on;
+        pudp = pud_offset(pgdp, address);
+        if (pud_none(*pudp))
+                goto out_irqs_on;
+        pmdp = pmd_offset(pudp, address);
+        if (pmd_none(*pmdp))
+                goto out_irqs_on;
+
+        ptep = pte_offset_map(pmdp, address);
+        pte = *ptep;
+        if (!pte_present(pte))
+                goto out_unmap;
+
+        paddr = (unsigned long) page_address(pte_page(pte));
+
+        __asm__ __volatile__("flush     %0 + %1"
+                             : /* no outputs */
+                             : "r" (paddr),
+                               "r" (address & (PAGE_SIZE - 1))
+                             : "memory");
+
+out_unmap:
+        pte_unmap(ptep);
+out_irqs_on:
+        __asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate));
+
+}
+
+static int setup_frame32(struct k_sigaction *ka, struct pt_regs *regs,
+                         int signo, sigset_t *oldset)
 {
         struct signal_frame32 __user *sf;
         int sigframe_size;
@@ -547,13 +605,7 @@ static void setup_frame32(struct k_sigaction *ka, struct pt_regs *regs,
         if (ka->ka_restorer) {
                 regs->u_regs[UREG_I7] = (unsigned long)ka->ka_restorer;
         } else {
-                /* Flush instruction space. */
                 unsigned long address = ((unsigned long)&(sf->insns[0]));
-                pgd_t *pgdp = pgd_offset(current->mm, address);
-                pud_t *pudp = pud_offset(pgdp, address);
-                pmd_t *pmdp = pmd_offset(pudp, address);
-                pte_t *ptep;
-                pte_t pte;
 
                 regs->u_regs[UREG_I7] = (unsigned long) (&(sf->insns[0]) - 2);
         
@@ -562,34 +614,22 @@ static void setup_frame32(struct k_sigaction *ka, struct pt_regs *regs,
                 if (err)
                         goto sigsegv;
 
-                preempt_disable();
-                ptep = pte_offset_map(pmdp, address);
-                pte = *ptep;
-                if (pte_present(pte)) {
-                        unsigned long page = (unsigned long)
-                                page_address(pte_page(pte));
-
-                        wmb();
-                        __asm__ __volatile__("flush     %0 + %1"
-                                             : /* no outputs */
-                                             : "r" (page),
-                                               "r" (address & (PAGE_SIZE - 1))
-                                             : "memory");
-                }
-                pte_unmap(ptep);
-                preempt_enable();
+                flush_signal_insns(address);
         }
-        return;
+        return 0;
 
 sigill:
         do_exit(SIGILL);
+        return -EINVAL;
+
 sigsegv:
         force_sigsegv(signo, current);
+        return -EFAULT;
 }
 
-static void setup_rt_frame32(struct k_sigaction *ka, struct pt_regs *regs,
-                             unsigned long signr, sigset_t *oldset,
-                             siginfo_t *info)
+static int setup_rt_frame32(struct k_sigaction *ka, struct pt_regs *regs,
+                            unsigned long signr, sigset_t *oldset,
+                            siginfo_t *info)
 {
         struct rt_signal_frame32 __user *sf;
         int sigframe_size;
@@ -687,12 +727,7 @@ static void setup_rt_frame32(struct k_sigaction *ka, struct pt_regs *regs,
         if (ka->ka_restorer)
                 regs->u_regs[UREG_I7] = (unsigned long)ka->ka_restorer;
         else {
-                /* Flush instruction space. */
                 unsigned long address = ((unsigned long)&(sf->insns[0]));
-                pgd_t *pgdp = pgd_offset(current->mm, address);
-                pud_t *pudp = pud_offset(pgdp, address);
-                pmd_t *pmdp = pmd_offset(pudp, address);
-                pte_t *ptep;
 
                 regs->u_regs[UREG_I7] = (unsigned long) (&(sf->insns[0]) - 2);
         
@@ -704,38 +739,32 @@ static void setup_rt_frame32(struct k_sigaction *ka, struct pt_regs *regs,
                 if (err)
                         goto sigsegv;
 
-                preempt_disable();
-                ptep = pte_offset_map(pmdp, address);
-                if (pte_present(*ptep)) {
-                        unsigned long page = (unsigned long)
-                                page_address(pte_page(*ptep));
-
-                        wmb();
-                        __asm__ __volatile__("flush     %0 + %1"
-                                             : /* no outputs */
-                                             : "r" (page),
-                                               "r" (address & (PAGE_SIZE - 1))
-                                             : "memory");
-                }
-                pte_unmap(ptep);
-                preempt_enable();
+                flush_signal_insns(address);
         }
-        return;
+        return 0;
 
 sigill:
         do_exit(SIGILL);
+        return -EINVAL;
+
 sigsegv:
         force_sigsegv(signr, current);
+        return -EFAULT;
 }
 
-static inline void handle_signal32(unsigned long signr, struct k_sigaction *ka,
-                                   siginfo_t *info,
-                                   sigset_t *oldset, struct pt_regs *regs)
+static inline int handle_signal32(unsigned long signr, struct k_sigaction *ka,
+                                  siginfo_t *info,
+                                  sigset_t *oldset, struct pt_regs *regs)
 {
+        int err;
+
         if (ka->sa.sa_flags & SA_SIGINFO)
-                setup_rt_frame32(ka, regs, signr, oldset, info);
+                err = setup_rt_frame32(ka, regs, signr, oldset, info);
         else
-                setup_frame32(ka, regs, signr, oldset);
+                err = setup_frame32(ka, regs, signr, oldset);
+
+        if (err)
+                return err;
 
         spin_lock_irq(&current->sighand->siglock);
         sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
@@ -743,6 +772,10 @@ static inline void handle_signal32(unsigned long signr, struct k_sigaction *ka,
                 sigaddset(&current->blocked,signr);
         recalc_sigpending();
         spin_unlock_irq(&current->sighand->siglock);
+
+        tracehook_signal_handler(signr, info, ka, regs, 0);
+
+        return 0;
 }
 
 static inline void syscall_restart32(unsigned long orig_i0, struct pt_regs *regs,
@@ -789,16 +822,14 @@ void do_signal32(sigset_t *oldset, struct pt_regs * regs,
         if (signr > 0) {
                 if (restart_syscall)
                         syscall_restart32(orig_i0, regs, &ka.sa);
-                handle_signal32(signr, &ka, &info, oldset, regs);
-
-                /* A signal was successfully delivered; the saved
-                 * sigmask will have been stored in the signal frame,
-                 * and will be restored by sigreturn, so we can simply
-                 * clear the TS_RESTORE_SIGMASK flag.
-                 */
-                current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
-
-                tracehook_signal_handler(signr, &info, &ka, regs, 0);
+                if (handle_signal32(signr, &ka, &info, oldset, regs) == 0) {
+                        /* A signal was successfully delivered; the saved
+                         * sigmask will have been stored in the signal frame,
+                         * and will be restored by sigreturn, so we can simply
+                         * clear the TS_RESTORE_SIGMASK flag.
+                         */
+                        current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
+                }
                 return;
         }
         if (restart_syscall &&
@@ -809,12 +840,14 @@ void do_signal32(sigset_t *oldset, struct pt_regs * regs,
                 regs->u_regs[UREG_I0] = orig_i0;
                 regs->tpc -= 4;
                 regs->tnpc -= 4;
+                pt_regs_clear_syscall(regs);
         }
         if (restart_syscall &&
             regs->u_regs[UREG_I0] == ERESTART_RESTARTBLOCK) {
                 regs->u_regs[UREG_G1] = __NR_restart_syscall;
                 regs->tpc -= 4;
                 regs->tnpc -= 4;
+                pt_regs_clear_syscall(regs);
         }
 
         /* If there's no signal to deliver, we just put the saved sigmask
diff --git a/arch/sparc/kernel/signal_32.c b/arch/sparc/kernel/signal_32.c
index 9882df92ba0a..5e5c5fd03783 100644
--- a/arch/sparc/kernel/signal_32.c
+++ b/arch/sparc/kernel/signal_32.c
@@ -315,8 +315,8 @@ save_fpu_state(struct pt_regs *regs, __siginfo_fpu_t __user *fpu)
         return err;
 }
 
-static void setup_frame(struct k_sigaction *ka, struct pt_regs *regs,
-                        int signo, sigset_t *oldset)
+static int setup_frame(struct k_sigaction *ka, struct pt_regs *regs,
+                       int signo, sigset_t *oldset)
 {
         struct signal_frame __user *sf;
         int sigframe_size, err;
@@ -384,16 +384,19 @@ static void setup_frame(struct k_sigaction *ka, struct pt_regs *regs,
                 /* Flush instruction space. */
                 flush_sig_insns(current->mm, (unsigned long) &(sf->insns[0]));
         }
-        return;
+        return 0;
 
 sigill_and_return:
         do_exit(SIGILL);
+        return -EINVAL;
+
 sigsegv:
         force_sigsegv(signo, current);
+        return -EFAULT;
 }
 
-static void setup_rt_frame(struct k_sigaction *ka, struct pt_regs *regs,
-                           int signo, sigset_t *oldset, siginfo_t *info)
+static int setup_rt_frame(struct k_sigaction *ka, struct pt_regs *regs,
+                          int signo, sigset_t *oldset, siginfo_t *info)
 {
         struct rt_signal_frame __user *sf;
         int sigframe_size;
@@ -466,22 +469,30 @@ static void setup_rt_frame(struct k_sigaction *ka, struct pt_regs *regs,
                 /* Flush instruction space. */
                 flush_sig_insns(current->mm, (unsigned long) &(sf->insns[0]));
         }
-        return;
+        return 0;
 
 sigill:
         do_exit(SIGILL);
+        return -EINVAL;
+
 sigsegv:
         force_sigsegv(signo, current);
+        return -EFAULT;
 }
 
-static inline void
+static inline int
 handle_signal(unsigned long signr, struct k_sigaction *ka,
               siginfo_t *info, sigset_t *oldset, struct pt_regs *regs)
 {
+        int err;
+
         if (ka->sa.sa_flags & SA_SIGINFO)
-                setup_rt_frame(ka, regs, signr, oldset, info);
+                err = setup_rt_frame(ka, regs, signr, oldset, info);
         else
-                setup_frame(ka, regs, signr, oldset);
+                err = setup_frame(ka, regs, signr, oldset);
+
+        if (err)
+                return err;
 
         spin_lock_irq(&current->sighand->siglock);
         sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
@@ -489,6 +500,10 @@ handle_signal(unsigned long signr, struct k_sigaction *ka,
                 sigaddset(&current->blocked, signr);
         recalc_sigpending();
         spin_unlock_irq(&current->sighand->siglock);
+
+        tracehook_signal_handler(signr, info, ka, regs, 0);
+
+        return 0;
 }
 
 static inline void syscall_restart(unsigned long orig_i0, struct pt_regs *regs,
@@ -546,17 +561,15 @@ static void do_signal(struct pt_regs *regs, unsigned long orig_i0)
         if (signr > 0) {
                 if (restart_syscall)
                         syscall_restart(orig_i0, regs, &ka.sa);
-                handle_signal(signr, &ka, &info, oldset, regs);
-
-                /* a signal was successfully delivered; the saved
-                 * sigmask will have been stored in the signal frame,
-                 * and will be restored by sigreturn, so we can simply
-                 * clear the TIF_RESTORE_SIGMASK flag.
-                 */
-                if (test_thread_flag(TIF_RESTORE_SIGMASK))
-                        clear_thread_flag(TIF_RESTORE_SIGMASK);
-
-                tracehook_signal_handler(signr, &info, &ka, regs, 0);
+                if (handle_signal(signr, &ka, &info, oldset, regs) == 0) {
+                        /* a signal was successfully delivered; the saved
+                         * sigmask will have been stored in the signal frame,
+                         * and will be restored by sigreturn, so we can simply
+                         * clear the TIF_RESTORE_SIGMASK flag.
+                         */
+                        if (test_thread_flag(TIF_RESTORE_SIGMASK))
+                                clear_thread_flag(TIF_RESTORE_SIGMASK);
+                }
                 return;
         }
         if (restart_syscall &&
@@ -567,12 +580,14 @@ static void do_signal(struct pt_regs *regs, unsigned long orig_i0)
                 regs->u_regs[UREG_I0] = orig_i0;
                 regs->pc -= 4;
                 regs->npc -= 4;
+                pt_regs_clear_syscall(regs);
         }
         if (restart_syscall &&
             regs->u_regs[UREG_I0] == ERESTART_RESTARTBLOCK) {
                 regs->u_regs[UREG_G1] = __NR_restart_syscall;
                 regs->pc -= 4;
                 regs->npc -= 4;
+                pt_regs_clear_syscall(regs);
         }
 
         /* if there's no signal to deliver, we just put the saved sigmask
diff --git a/arch/sparc/kernel/signal_64.c b/arch/sparc/kernel/signal_64.c
index 9fa48c30037e..006fe4515886 100644
--- a/arch/sparc/kernel/signal_64.c
+++ b/arch/sparc/kernel/signal_64.c
@@ -409,7 +409,7 @@ static inline void __user *get_sigframe(struct k_sigaction *ka, struct pt_regs *
         return (void __user *) sp;
 }
 
-static inline void
+static inline int
 setup_rt_frame(struct k_sigaction *ka, struct pt_regs *regs,
                int signo, sigset_t *oldset, siginfo_t *info)
 {
@@ -483,26 +483,37 @@ setup_rt_frame(struct k_sigaction *ka, struct pt_regs *regs,
         }
         /* 4. return to kernel instructions */
         regs->u_regs[UREG_I7] = (unsigned long)ka->ka_restorer;
-        return;
+        return 0;
 
 sigill:
         do_exit(SIGILL);
+        return -EINVAL;
+
 sigsegv:
         force_sigsegv(signo, current);
+        return -EFAULT;
 }
 
-static inline void handle_signal(unsigned long signr, struct k_sigaction *ka,
-                                 siginfo_t *info,
-                                 sigset_t *oldset, struct pt_regs *regs)
+static inline int handle_signal(unsigned long signr, struct k_sigaction *ka,
+                                siginfo_t *info,
+                                sigset_t *oldset, struct pt_regs *regs)
 {
-        setup_rt_frame(ka, regs, signr, oldset,
-                       (ka->sa.sa_flags & SA_SIGINFO) ? info : NULL);
+        int err;
+
+        err = setup_rt_frame(ka, regs, signr, oldset,
+                             (ka->sa.sa_flags & SA_SIGINFO) ? info : NULL);
+        if (err)
+                return err;
         spin_lock_irq(&current->sighand->siglock);
         sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
         if (!(ka->sa.sa_flags & SA_NOMASK))
                 sigaddset(&current->blocked,signr);
         recalc_sigpending();
         spin_unlock_irq(&current->sighand->siglock);
+
+        tracehook_signal_handler(signr, info, ka, regs, 0);
+
+        return 0;
 }
 
 static inline void syscall_restart(unsigned long orig_i0, struct pt_regs *regs,
@@ -571,16 +582,14 @@ static void do_signal(struct pt_regs *regs, unsigned long orig_i0)
         if (signr > 0) {
                 if (restart_syscall)
                         syscall_restart(orig_i0, regs, &ka.sa);
-                handle_signal(signr, &ka, &info, oldset, regs);
-
-                /* A signal was successfully delivered; the saved
-                 * sigmask will have been stored in the signal frame,
-                 * and will be restored by sigreturn, so we can simply
-                 * clear the TS_RESTORE_SIGMASK flag.
-                 */
-                current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
-
-                tracehook_signal_handler(signr, &info, &ka, regs, 0);
+                if (handle_signal(signr, &ka, &info, oldset, regs) == 0) {
+                        /* A signal was successfully delivered; the saved
+                         * sigmask will have been stored in the signal frame,
+                         * and will be restored by sigreturn, so we can simply
+                         * clear the TS_RESTORE_SIGMASK flag.
+                         */
+                        current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
+                }
                 return;
         }
         if (restart_syscall &&
@@ -591,12 +600,14 @@ static void do_signal(struct pt_regs *regs, unsigned long orig_i0)
                 regs->u_regs[UREG_I0] = orig_i0;
                 regs->tpc -= 4;
                 regs->tnpc -= 4;
+                pt_regs_clear_syscall(regs);
         }
         if (restart_syscall &&
             regs->u_regs[UREG_I0] == ERESTART_RESTARTBLOCK) {
                 regs->u_regs[UREG_G1] = __NR_restart_syscall;
                 regs->tpc -= 4;
                 regs->tnpc -= 4;
+                pt_regs_clear_syscall(regs);
         }
 
         /* If there's no signal to deliver, we just put the saved sigmask
diff --git a/arch/tile/include/arch/chip_tile64.h b/arch/tile/include/arch/chip_tile64.h
index 1246573be59e..261aaba092d4 100644
--- a/arch/tile/include/arch/chip_tile64.h
+++ b/arch/tile/include/arch/chip_tile64.h
@@ -150,6 +150,9 @@
 /** Is the PROC_STATUS SPR supported? */
 #define CHIP_HAS_PROC_STATUS_SPR() 0
 
+/** Is the DSTREAM_PF SPR supported? */
+#define CHIP_HAS_DSTREAM_PF() 0
+
 /** Log of the number of mshims we have. */
 #define CHIP_LOG_NUM_MSHIMS() 2
 
diff --git a/arch/tile/include/arch/chip_tilepro.h b/arch/tile/include/arch/chip_tilepro.h
index e864c47fc89c..70017699a74c 100644
--- a/arch/tile/include/arch/chip_tilepro.h
+++ b/arch/tile/include/arch/chip_tilepro.h
@@ -150,6 +150,9 @@
 /** Is the PROC_STATUS SPR supported? */
 #define CHIP_HAS_PROC_STATUS_SPR() 1
 
+/** Is the DSTREAM_PF SPR supported? */
+#define CHIP_HAS_DSTREAM_PF() 0
+
 /** Log of the number of mshims we have. */
 #define CHIP_LOG_NUM_MSHIMS() 2
 
diff --git a/arch/tile/include/asm/compat.h b/arch/tile/include/asm/compat.h
index 5a34da6cdd79..8b60ec8b2d19 100644
--- a/arch/tile/include/asm/compat.h
+++ b/arch/tile/include/asm/compat.h
@@ -195,7 +195,7 @@ static inline unsigned long ptr_to_compat_reg(void __user *uptr)
         return (long)(int)(long __force)uptr;
 }
 
-static inline void __user *compat_alloc_user_space(long len)
+static inline void __user *arch_compat_alloc_user_space(long len)
 {
         struct pt_regs *regs = task_pt_regs(current);
         return (void __user *)regs->sp - len;
@@ -214,8 +214,9 @@ extern int compat_setup_rt_frame(int sig, struct k_sigaction *ka,
 struct compat_sigaction;
 struct compat_siginfo;
 struct compat_sigaltstack;
-long compat_sys_execve(char __user *path, compat_uptr_t __user *argv,
-                       compat_uptr_t __user *envp);
+long compat_sys_execve(const char __user *path,
+                       const compat_uptr_t __user *argv,
+                       const compat_uptr_t __user *envp);
 long compat_sys_rt_sigaction(int sig, struct compat_sigaction __user *act,
                              struct compat_sigaction __user *oact,
                              size_t sigsetsize);
diff --git a/arch/tile/include/asm/io.h b/arch/tile/include/asm/io.h
index 8c95bef3fa45..ee43328713ab 100644
--- a/arch/tile/include/asm/io.h
+++ b/arch/tile/include/asm/io.h
@@ -164,22 +164,22 @@ static inline void _tile_writeq(u64 val, unsigned long addr)
 #define iowrite32 writel
 #define iowrite64 writeq
 
-static inline void *memcpy_fromio(void *dst, void *src, int len)
+static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
+                                 size_t len)
 {
         int x;
         BUG_ON((unsigned long)src & 0x3);
         for (x = 0; x < len; x += 4)
                 *(u32 *)(dst + x) = readl(src + x);
-        return dst;
 }
 
-static inline void *memcpy_toio(void *dst, void *src, int len)
+static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
+                                size_t len)
 {
         int x;
         BUG_ON((unsigned long)dst & 0x3);
         for (x = 0; x < len; x += 4)
                 writel(*(u32 *)(src + x), dst + x);
-        return dst;
 }
 
 /*
diff --git a/arch/tile/include/asm/processor.h b/arch/tile/include/asm/processor.h
index d942d09b252e..ccd5f8425688 100644
--- a/arch/tile/include/asm/processor.h
+++ b/arch/tile/include/asm/processor.h
@@ -103,6 +103,18 @@ struct thread_struct {
         /* Any other miscellaneous processor state bits */
         unsigned long proc_status;
 #endif
+#if !CHIP_HAS_FIXED_INTVEC_BASE()
+        /* Interrupt base for PL0 interrupts */
+        unsigned long interrupt_vector_base;
+#endif
+#if CHIP_HAS_TILE_RTF_HWM()
+        /* Tile cache retry fifo high-water mark */
+        unsigned long tile_rtf_hwm;
+#endif
+#if CHIP_HAS_DSTREAM_PF()
+        /* Data stream prefetch control */
+        unsigned long dstream_pf;
+#endif
 #ifdef CONFIG_HARDWALL
         /* Is this task tied to an activated hardwall? */
         struct hardwall_info *hardwall;
diff --git a/arch/tile/include/asm/ptrace.h b/arch/tile/include/asm/ptrace.h
index acdae814e016..4a02bb073979 100644
--- a/arch/tile/include/asm/ptrace.h
+++ b/arch/tile/include/asm/ptrace.h
@@ -51,10 +51,7 @@ typedef uint_reg_t pt_reg_t;
 
 /*
  * This struct defines the way the registers are stored on the stack during a
- * system call/exception.  It should be a multiple of 8 bytes to preserve
- * normal stack alignment rules.
- *
- * Must track <sys/ucontext.h> and <sys/procfs.h>
+ * system call or exception.  "struct sigcontext" has the same shape.
  */
 struct pt_regs {
         /* Saved main processor registers; 56..63 are special. */
@@ -80,11 +77,6 @@ struct pt_regs {
 
 #endif /* __ASSEMBLY__ */
 
-/* Flag bits in pt_regs.flags */
-#define PT_FLAGS_DISABLE_IRQ    1  /* on return to kernel, disable irqs */
-#define PT_FLAGS_CALLER_SAVES   2  /* caller-save registers are valid */
-#define PT_FLAGS_RESTORE_REGS   4  /* restore callee-save regs on return */
-
 #define PTRACE_GETREGS          12
 #define PTRACE_SETREGS          13
 #define PTRACE_GETFPREGS        14
@@ -101,6 +93,11 @@ struct pt_regs {
 
 #ifdef __KERNEL__
 
+/* Flag bits in pt_regs.flags */
+#define PT_FLAGS_DISABLE_IRQ    1  /* on return to kernel, disable irqs */
+#define PT_FLAGS_CALLER_SAVES   2  /* caller-save registers are valid */
+#define PT_FLAGS_RESTORE_REGS   4  /* restore callee-save regs on return */
+
 #ifndef __ASSEMBLY__
 
 #define instruction_pointer(regs) ((regs)->pc)
diff --git a/arch/tile/include/asm/sigcontext.h b/arch/tile/include/asm/sigcontext.h
index 7cd7672e3ad4..5e2d03336f53 100644
--- a/arch/tile/include/asm/sigcontext.h
+++ b/arch/tile/include/asm/sigcontext.h
@@ -15,13 +15,21 @@
 #ifndef _ASM_TILE_SIGCONTEXT_H
 #define _ASM_TILE_SIGCONTEXT_H
 
-/* NOTE: we can't include <linux/ptrace.h> due to #include dependencies. */
-#include <asm/ptrace.h>
-
-/* Must track <sys/ucontext.h> */
+#include <arch/abi.h>
 
+/*
+ * struct sigcontext has the same shape as struct pt_regs,
+ * but is simplified since we know the fault is from userspace.
+ */
 struct sigcontext {
-        struct pt_regs regs;
+        uint_reg_t gregs[53];   /* General-purpose registers.  */
+        uint_reg_t tp;          /* Aliases gregs[TREG_TP].  */
+        uint_reg_t sp;          /* Aliases gregs[TREG_SP].  */
+        uint_reg_t lr;          /* Aliases gregs[TREG_LR].  */
+        uint_reg_t pc;          /* Program counter.  */
+        uint_reg_t ics;         /* In Interrupt Critical Section?  */
+        uint_reg_t faultnum;    /* Fault number.  */
+        uint_reg_t pad[5];
 };
 
 #endif /* _ASM_TILE_SIGCONTEXT_H */
diff --git a/arch/tile/include/asm/signal.h b/arch/tile/include/asm/signal.h
index eb0253f32202..c1ee1d61d44c 100644
--- a/arch/tile/include/asm/signal.h
+++ b/arch/tile/include/asm/signal.h
@@ -24,6 +24,7 @@
 #include <asm-generic/signal.h>
 
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
+struct pt_regs;
 int restore_sigcontext(struct pt_regs *, struct sigcontext __user *, long *);
 int setup_sigcontext(struct sigcontext __user *, struct pt_regs *);
 void do_signal(struct pt_regs *regs);
diff --git a/arch/tile/include/asm/syscalls.h b/arch/tile/include/asm/syscalls.h
index af165a74537f..ce99ffefeacf 100644
--- a/arch/tile/include/asm/syscalls.h
+++ b/arch/tile/include/asm/syscalls.h
@@ -62,10 +62,12 @@ long sys_fork(void);
 long _sys_fork(struct pt_regs *regs);
 long sys_vfork(void);
 long _sys_vfork(struct pt_regs *regs);
-long sys_execve(char __user *filename, char __user * __user *argv,
-                char __user * __user *envp);
-long _sys_execve(char __user *filename, char __user * __user *argv,
-                 char __user * __user *envp, struct pt_regs *regs);
+long sys_execve(const char __user *filename,
+                const char __user *const __user *argv,
+                const char __user *const __user *envp);
+long _sys_execve(const char __user *filename,
+                 const char __user *const __user *argv,
+                 const char __user *const __user *envp, struct pt_regs *regs);
 
 /* kernel/signal.c */
 long sys_sigaltstack(const stack_t __user *, stack_t __user *);
@@ -86,10 +88,13 @@ int _sys_cmpxchg_badaddr(unsigned long address, struct pt_regs *);
 #endif
 
 #ifdef CONFIG_COMPAT
-long compat_sys_execve(char __user *path, compat_uptr_t __user *argv,
-                       compat_uptr_t __user *envp);
-long _compat_sys_execve(char __user *path, compat_uptr_t __user *argv,
-                        compat_uptr_t __user *envp, struct pt_regs *regs);
+long compat_sys_execve(const char __user *path,
+                       const compat_uptr_t __user *argv,
+                       const compat_uptr_t __user *envp);
+long _compat_sys_execve(const char __user *path,
+                        const compat_uptr_t __user *argv,
+                        const compat_uptr_t __user *envp,
+                        struct pt_regs *regs);
 long compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr,
                             struct compat_sigaltstack __user *uoss_ptr);
 long _compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr,
diff --git a/arch/tile/kernel/intvec_32.S b/arch/tile/kernel/intvec_32.S
index 84f296ca9e63..8f58bdff20d7 100644
--- a/arch/tile/kernel/intvec_32.S
+++ b/arch/tile/kernel/intvec_32.S
@@ -1506,13 +1506,6 @@ handle_ill:
         }
         STD_ENDPROC(handle_ill)
 
-        .pushsection .rodata, "a"
-        .align  8
-bpt_code:
-        bpt
-        ENDPROC(bpt_code)
-        .popsection
-
 /* Various stub interrupt handlers and syscall handlers */
 
 STD_ENTRY_LOCAL(_kernel_double_fault)
diff --git a/arch/tile/kernel/process.c b/arch/tile/kernel/process.c
index 985cc28c74c5..84c29111756c 100644
--- a/arch/tile/kernel/process.c
+++ b/arch/tile/kernel/process.c
@@ -408,6 +408,15 @@ static void save_arch_state(struct thread_struct *t)
 #if CHIP_HAS_PROC_STATUS_SPR()
         t->proc_status = __insn_mfspr(SPR_PROC_STATUS);
 #endif
+#if !CHIP_HAS_FIXED_INTVEC_BASE()
+        t->interrupt_vector_base = __insn_mfspr(SPR_INTERRUPT_VECTOR_BASE_0);
+#endif
+#if CHIP_HAS_TILE_RTF_HWM()
+        t->tile_rtf_hwm = __insn_mfspr(SPR_TILE_RTF_HWM);
+#endif
+#if CHIP_HAS_DSTREAM_PF()
+        t->dstream_pf = __insn_mfspr(SPR_DSTREAM_PF);
+#endif
 }
 
 static void restore_arch_state(const struct thread_struct *t)
@@ -428,14 +437,14 @@ static void restore_arch_state(const struct thread_struct *t)
 #if CHIP_HAS_PROC_STATUS_SPR()
         __insn_mtspr(SPR_PROC_STATUS, t->proc_status);
 #endif
+#if !CHIP_HAS_FIXED_INTVEC_BASE()
+        __insn_mtspr(SPR_INTERRUPT_VECTOR_BASE_0, t->interrupt_vector_base);
+#endif
 #if CHIP_HAS_TILE_RTF_HWM()
-        /*
-         * Clear this whenever we switch back to a process in case
-         * the previous process was monkeying with it.  Even if enabled
-         * in CBOX_MSR1 via TILE_RTF_HWM_MIN, it's still just a
-         * performance hint, so isn't worth a full save/restore.
-         */
-        __insn_mtspr(SPR_TILE_RTF_HWM, 0);
+        __insn_mtspr(SPR_TILE_RTF_HWM, t->tile_rtf_hwm);
+#endif
+#if CHIP_HAS_DSTREAM_PF()
+        __insn_mtspr(SPR_DSTREAM_PF, t->dstream_pf);
 #endif
 }
 
@@ -561,8 +570,9 @@ out:
 }
 
 #ifdef CONFIG_COMPAT
-long _compat_sys_execve(char __user *path, compat_uptr_t __user *argv,
-                        compat_uptr_t __user *envp, struct pt_regs *regs)
+long _compat_sys_execve(const char __user *path,
+                        const compat_uptr_t __user *argv,
+                        const compat_uptr_t __user *envp, struct pt_regs *regs)
 {
         long error;
         char *filename;
@@ -657,7 +667,7 @@ void show_regs(struct pt_regs *regs)
                regs->regs[51], regs->regs[52], regs->tp);
         pr_err(" sp : "REGFMT" lr : "REGFMT"\n", regs->sp, regs->lr);
 #else
-        for (i = 0; i < 52; i += 3)
+        for (i = 0; i < 52; i += 4)
                 pr_err(" r%-2d: "REGFMT" r%-2d: "REGFMT
                        " r%-2d: "REGFMT" r%-2d: "REGFMT"\n",
                        i, regs->regs[i], i+1, regs->regs[i+1],
diff --git a/arch/tile/kernel/signal.c b/arch/tile/kernel/signal.c
index 45b66a3c991f..ce183aa1492c 100644
--- a/arch/tile/kernel/signal.c
+++ b/arch/tile/kernel/signal.c
@@ -61,13 +61,19 @@ int restore_sigcontext(struct pt_regs *regs,
         /* Always make any pending restarted system calls return -EINTR */
         current_thread_info()->restart_block.fn = do_no_restart_syscall;
 
+        /*
+         * Enforce that sigcontext is like pt_regs, and doesn't mess
+         * up our stack alignment rules.
+         */
+        BUILD_BUG_ON(sizeof(struct sigcontext) != sizeof(struct pt_regs));
+        BUILD_BUG_ON(sizeof(struct sigcontext) % 8 != 0);
+
         for (i = 0; i < sizeof(struct pt_regs)/sizeof(long); ++i)
-                err |= __get_user(((long *)regs)[i],
-                                  &((long __user *)(&sc->regs))[i]);
+                err |= __get_user(regs->regs[i], &sc->gregs[i]);
 
         regs->faultnum = INT_SWINT_1_SIGRETURN;
 
-        err |= __get_user(*pr0, &sc->regs.regs[0]);
+        err |= __get_user(*pr0, &sc->gregs[0]);
         return err;
 }
 
@@ -112,8 +118,7 @@ int setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs)
         int i, err = 0;
 
         for (i = 0; i < sizeof(struct pt_regs)/sizeof(long); ++i)
-                err |= __put_user(((long *)regs)[i],
-                                  &((long __user *)(&sc->regs))[i]);
+                err |= __put_user(regs->regs[i], &sc->gregs[i]);
 
         return err;
 }
@@ -203,19 +208,17 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
          * Set up registers for signal handler.
          * Registers that we don't modify keep the value they had from
          * user-space at the time we took the signal.
+         * We always pass siginfo and mcontext, regardless of SA_SIGINFO,
+         * since some things rely on this (e.g. glibc's debug/segfault.c).
          */
         regs->pc = (unsigned long) ka->sa.sa_handler;
         regs->ex1 = PL_ICS_EX1(USER_PL, 1); /* set crit sec in handler */
         regs->sp = (unsigned long) frame;
         regs->lr = restorer;
         regs->regs[0] = (unsigned long) usig;
-
-        if (ka->sa.sa_flags & SA_SIGINFO) {
-                /* Need extra arguments, so mark to restore caller-saves. */
-                regs->regs[1] = (unsigned long) &frame->info;
-                regs->regs[2] = (unsigned long) &frame->uc;
-                regs->flags |= PT_FLAGS_CALLER_SAVES;
-        }
+        regs->regs[1] = (unsigned long) &frame->info;
+        regs->regs[2] = (unsigned long) &frame->uc;
+        regs->flags |= PT_FLAGS_CALLER_SAVES;
 
         /*
          * Notify any tracer that was single-stepping it.
diff --git a/arch/tile/kernel/stack.c b/arch/tile/kernel/stack.c
index 38a68b0b4581..ea2e0ce28380 100644
--- a/arch/tile/kernel/stack.c
+++ b/arch/tile/kernel/stack.c
@@ -175,7 +175,7 @@ static struct pt_regs *valid_sigframe(struct KBacktraceIterator* kbt)
                         pr_err("  <received signal %d>\n",
                                frame->info.si_signo);
                 }
-                return &frame->uc.uc_mcontext.regs;
+                return (struct pt_regs *)&frame->uc.uc_mcontext;
         }
         return NULL;
 }
diff --git a/arch/um/drivers/net_kern.c b/arch/um/drivers/net_kern.c
index 2ab233ba32c1..47d0c37897d5 100644
--- a/arch/um/drivers/net_kern.c
+++ b/arch/um/drivers/net_kern.c
@@ -255,18 +255,6 @@ static void uml_net_tx_timeout(struct net_device *dev)
         netif_wake_queue(dev);
 }
 
-static int uml_net_set_mac(struct net_device *dev, void *addr)
-{
-        struct uml_net_private *lp = netdev_priv(dev);
-        struct sockaddr *hwaddr = addr;
-
-        spin_lock_irq(&lp->lock);
-        eth_mac_addr(dev, hwaddr->sa_data);
-        spin_unlock_irq(&lp->lock);
-
-        return 0;
-}
-
 static int uml_net_change_mtu(struct net_device *dev, int new_mtu)
 {
         dev->mtu = new_mtu;
@@ -373,7 +361,7 @@ static const struct net_device_ops uml_netdev_ops = {
         .ndo_start_xmit         = uml_net_start_xmit,
         .ndo_set_multicast_list = uml_net_set_multicast_list,
         .ndo_tx_timeout         = uml_net_tx_timeout,
-        .ndo_set_mac_address    = uml_net_set_mac,
+        .ndo_set_mac_address    = eth_mac_addr,
         .ndo_change_mtu         = uml_net_change_mtu,
         .ndo_validate_addr      = eth_validate_addr,
 };
@@ -472,7 +460,8 @@ static void eth_configure(int n, void *init, char *mac,
             ((*transport->user->init)(&lp->user, dev) != 0))
                 goto out_unregister;
 
-        eth_mac_addr(dev, device->mac);
+        /* don't use eth_mac_addr, it will not work here */
+        memcpy(dev->dev_addr, device->mac, ETH_ALEN);
         dev->mtu = transport->user->mtu;
         dev->netdev_ops = &uml_netdev_ops;
         dev->ethtool_ops = &uml_net_ethtool_ops;
diff --git a/arch/um/kernel/exec.c b/arch/um/kernel/exec.c
index cd145eda3579..49b5e1eb3262 100644
--- a/arch/um/kernel/exec.c
+++ b/arch/um/kernel/exec.c
@@ -62,7 +62,7 @@ static long execve1(const char *file,
         return error;
 }
 
-long um_execve(const char *file, char __user *__user *argv, char __user *__user *env)
+long um_execve(const char *file, const char __user *const __user *argv, const char __user *const __user *env)
 {
         long err;
 
@@ -72,8 +72,8 @@ long um_execve(const char *file, char __user *__user *argv, char __user *__user
         return err;
 }
 
-long sys_execve(const char __user *file, char __user *__user *argv,
-                char __user *__user *env)
+long sys_execve(const char __user *file, const char __user *const __user *argv,
+                const char __user *const __user *env)
 {
         long error;
         char *filename;
diff --git a/arch/um/kernel/internal.h b/arch/um/kernel/internal.h
index 1303a105fe91..5bf97db24a04 100644
--- a/arch/um/kernel/internal.h
+++ b/arch/um/kernel/internal.h
@@ -1 +1 @@
-extern long um_execve(const char *file, char __user *__user *argv, char __user *__user *env);
+extern long um_execve(const char *file, const char __user *const __user *argv, const char __user *const __user *env);
diff --git a/arch/um/kernel/syscall.c b/arch/um/kernel/syscall.c
index 5ddb246626db..f958cb876ee3 100644
--- a/arch/um/kernel/syscall.c
+++ b/arch/um/kernel/syscall.c
@@ -60,8 +60,8 @@ int kernel_execve(const char *filename,
 
         fs = get_fs();
         set_fs(KERNEL_DS);
-        ret = um_execve(filename, (char __user *__user *)argv,
-                        (char __user *__user *) envp);
+        ret = um_execve(filename, (const char __user *const __user *)argv,
+                        (const char __user *const __user *) envp);
         set_fs(fs);
 
         return ret;
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index 8aa1b59b9074..e8c8881351b3 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -74,7 +74,7 @@ endif
 
 ifdef CONFIG_CC_STACKPROTECTOR
         cc_has_sp := $(srctree)/scripts/gcc-x86_$(BITS)-has-stack-protector.sh
-        ifeq ($(shell $(CONFIG_SHELL) $(cc_has_sp) $(CC) $(biarch)),y)
+        ifeq ($(shell $(CONFIG_SHELL) $(cc_has_sp) $(CC) $(KBUILD_CPPFLAGS) $(biarch)),y)
                 stackp-y := -fstack-protector
                 KBUILD_CFLAGS += $(stackp-y)
         else
diff --git a/arch/x86/boot/early_serial_console.c b/arch/x86/boot/early_serial_console.c
index 030f4b93e255..5df2869c874b 100644
--- a/arch/x86/boot/early_serial_console.c
+++ b/arch/x86/boot/early_serial_console.c
@@ -58,7 +58,19 @@ static void parse_earlyprintk(void)
                 if (arg[pos] == ',')
                         pos++;
 
-                if (!strncmp(arg, "ttyS", 4)) {
+                /*
+                 * make sure we have
+                 *      "serial,0x3f8,115200"
+                 *      "serial,ttyS0,115200"
+                 *      "ttyS0,115200"
+                 */
+                if (pos == 7 && !strncmp(arg + pos, "0x", 2)) {
+                        port = simple_strtoull(arg + pos, &e, 16);
+                        if (port == 0 || arg + pos == e)
+                                port = DEFAULT_SERIAL_PORT;
+                        else
+                                pos = e - arg;
+                } else if (!strncmp(arg + pos, "ttyS", 4)) {
                         static const int bases[] = { 0x3f8, 0x2f8 };
                         int idx = 0;
 
diff --git a/arch/x86/ia32/ia32_aout.c b/arch/x86/ia32/ia32_aout.c
index 0350311906ae..2d93bdbc9ac0 100644
--- a/arch/x86/ia32/ia32_aout.c
+++ b/arch/x86/ia32/ia32_aout.c
@@ -34,7 +34,7 @@
 #include <asm/ia32.h>
 
 #undef WARN_OLD
-#undef CORE_DUMP /* probably broken */
+#undef CORE_DUMP /* definitely broken */
 
 static int load_aout_binary(struct linux_binprm *, struct pt_regs *regs);
 static int load_aout_library(struct file *);
@@ -131,21 +131,15 @@ static void set_brk(unsigned long start, unsigned long end)
  * macros to write out all the necessary info.
  */
 
-static int dump_write(struct file *file, const void *addr, int nr)
-{
-        return file->f_op->write(file, addr, nr, &file->f_pos) == nr;
-}
+#include <linux/coredump.h>
 
 #define DUMP_WRITE(addr, nr)                         \
         if (!dump_write(file, (void *)(addr), (nr))) \
                 goto end_coredump;
 
-#define DUMP_SEEK(offset)                                               \
-        if (file->f_op->llseek) {                                       \
-                if (file->f_op->llseek(file, (offset), 0) != (offset))  \
-                        goto end_coredump;                              \
-        } else                                                          \
-                file->f_pos = (offset)
+#define DUMP_SEEK(offset)               \
+        if (!dump_seek(file, offset))   \
+                goto end_coredump;
 
 #define START_DATA()    (u.u_tsize << PAGE_SHIFT)
 #define START_STACK(u)  (u.start_stack)
@@ -217,12 +211,6 @@ static int aout_core_dump(long signr, struct pt_regs *regs, struct file *file,
                 dump_size = dump.u_ssize << PAGE_SHIFT;
                 DUMP_WRITE(dump_start, dump_size);
         }
-        /*
-         * Finally dump the task struct.  Not be used by gdb, but
-         * could be useful
-         */
-        set_fs(KERNEL_DS);
-        DUMP_WRITE(current, sizeof(*current));
 end_coredump:
         set_fs(fs);
         return has_dumped;
diff --git a/arch/x86/ia32/ia32entry.S b/arch/x86/ia32/ia32entry.S
index b86feabed69b..518bb99c3394 100644
--- a/arch/x86/ia32/ia32entry.S
+++ b/arch/x86/ia32/ia32entry.S
@@ -50,7 +50,12 @@
         /*
          * Reload arg registers from stack in case ptrace changed them.
          * We don't reload %eax because syscall_trace_enter() returned
-         * the value it wants us to use in the table lookup.
+         * the %rax value we should see.  Instead, we just truncate that
+         * value to 32 bits again as we did on entry from user mode.
+         * If it's a new value set by user_regset during entry tracing,
+         * this matches the normal truncation of the user-mode value.
+         * If it's -1 to make us punt the syscall, then (u32)-1 is still
+         * an appropriately invalid value.
          */
         .macro LOAD_ARGS32 offset, _r9=0
         .if \_r9
@@ -60,6 +65,7 @@
         movl \offset+48(%rsp),%edx
         movl \offset+56(%rsp),%esi
         movl \offset+64(%rsp),%edi
+        movl %eax,%eax                  /* zero extension */
         .endm
         
         .macro CFI_STARTPROC32 simple
@@ -153,7 +159,7 @@ ENTRY(ia32_sysenter_target)
         testl  $_TIF_WORK_SYSCALL_ENTRY,TI_flags(%r10)
         CFI_REMEMBER_STATE
         jnz  sysenter_tracesys
-        cmpl    $(IA32_NR_syscalls-1),%eax
+        cmpq    $(IA32_NR_syscalls-1),%rax
         ja      ia32_badsys
 sysenter_do_call:
         IA32_ARG_FIXUP
@@ -195,7 +201,7 @@ sysexit_from_sys_call:
         movl $AUDIT_ARCH_I386,%edi      /* 1st arg: audit arch */
         call audit_syscall_entry
         movl RAX-ARGOFFSET(%rsp),%eax   /* reload syscall number */
-        cmpl $(IA32_NR_syscalls-1),%eax
+        cmpq $(IA32_NR_syscalls-1),%rax
         ja ia32_badsys
         movl %ebx,%edi                  /* reload 1st syscall arg */
         movl RCX-ARGOFFSET(%rsp),%esi   /* reload 2nd syscall arg */
@@ -248,7 +254,7 @@ sysenter_tracesys:
         call    syscall_trace_enter
         LOAD_ARGS32 ARGOFFSET  /* reload args from stack in case ptrace changed it */
         RESTORE_REST
-        cmpl    $(IA32_NR_syscalls-1),%eax
+        cmpq    $(IA32_NR_syscalls-1),%rax
         ja      int_ret_from_sys_call /* sysenter_tracesys has set RAX(%rsp) */
         jmp     sysenter_do_call
         CFI_ENDPROC
@@ -314,7 +320,7 @@ ENTRY(ia32_cstar_target)
         testl $_TIF_WORK_SYSCALL_ENTRY,TI_flags(%r10)
         CFI_REMEMBER_STATE
         jnz   cstar_tracesys
-        cmpl $IA32_NR_syscalls-1,%eax
+        cmpq $IA32_NR_syscalls-1,%rax
         ja  ia32_badsys
 cstar_do_call:
         IA32_ARG_FIXUP 1
@@ -367,7 +373,7 @@ cstar_tracesys:
         LOAD_ARGS32 ARGOFFSET, 1  /* reload args from stack in case ptrace changed it */
         RESTORE_REST
         xchgl %ebp,%r9d
-        cmpl $(IA32_NR_syscalls-1),%eax
+        cmpq $(IA32_NR_syscalls-1),%rax
         ja int_ret_from_sys_call /* cstar_tracesys has set RAX(%rsp) */
         jmp cstar_do_call
 END(ia32_cstar_target)
@@ -425,7 +431,7 @@ ENTRY(ia32_syscall)
         orl   $TS_COMPAT,TI_status(%r10)
         testl $_TIF_WORK_SYSCALL_ENTRY,TI_flags(%r10)
         jnz ia32_tracesys
-        cmpl $(IA32_NR_syscalls-1),%eax
+        cmpq $(IA32_NR_syscalls-1),%rax
         ja ia32_badsys
 ia32_do_call:
         IA32_ARG_FIXUP
@@ -444,7 +450,7 @@ ia32_tracesys:
         call syscall_trace_enter
         LOAD_ARGS32 ARGOFFSET  /* reload args from stack in case ptrace changed it */
         RESTORE_REST
-        cmpl $(IA32_NR_syscalls-1),%eax
+        cmpq $(IA32_NR_syscalls-1),%rax
         ja  int_ret_from_sys_call       /* ia32_tracesys has set RAX(%rsp) */
         jmp ia32_do_call
 END(ia32_syscall)
diff --git a/arch/x86/include/asm/amd_iommu_proto.h b/arch/x86/include/asm/amd_iommu_proto.h
index d2544f1d705d..cb030374b90a 100644
--- a/arch/x86/include/asm/amd_iommu_proto.h
+++ b/arch/x86/include/asm/amd_iommu_proto.h
@@ -38,4 +38,10 @@ static inline void amd_iommu_stats_init(void) { }
 
 #endif /* !CONFIG_AMD_IOMMU_STATS */
 
+static inline bool is_rd890_iommu(struct pci_dev *pdev)
+{
+        return (pdev->vendor == PCI_VENDOR_ID_ATI) &&
+               (pdev->device == PCI_DEVICE_ID_RD890_IOMMU);
+}
+
 #endif /* _ASM_X86_AMD_IOMMU_PROTO_H  */
diff --git a/arch/x86/include/asm/amd_iommu_types.h b/arch/x86/include/asm/amd_iommu_types.h
index 7014e88bc779..08616180deaf 100644
--- a/arch/x86/include/asm/amd_iommu_types.h
+++ b/arch/x86/include/asm/amd_iommu_types.h
@@ -368,6 +368,9 @@ struct amd_iommu {
         /* capabilities of that IOMMU read from ACPI */
         u32 cap;
 
+        /* flags read from acpi table */
+        u8 acpi_flags;
+
         /*
          * Capability pointer. There could be more than one IOMMU per PCI
          * device function if there are more than one AMD IOMMU capability
@@ -411,6 +414,15 @@ struct amd_iommu {
 
         /* default dma_ops domain for that IOMMU */
         struct dma_ops_domain *default_dom;
+
+        /*
+         * This array is required to work around a potential BIOS bug.
+         * The BIOS may miss to restore parts of the PCI configuration
+         * space when the system resumes from S3. The result is that the
+         * IOMMU does not execute commands anymore which leads to system
+         * failure.
+         */
+        u32 cache_cfg[4];
 };
 
 /*
diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h
index 545776efeb16..bafd80defa43 100644
--- a/arch/x86/include/asm/bitops.h
+++ b/arch/x86/include/asm/bitops.h
@@ -309,7 +309,7 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
 static __always_inline int constant_test_bit(unsigned int nr, const volatile unsigned long *addr)
 {
         return ((1UL << (nr % BITS_PER_LONG)) &
-                (((unsigned long *)addr)[nr / BITS_PER_LONG])) != 0;
+                (addr[nr / BITS_PER_LONG])) != 0;
 }
 
 static inline int variable_test_bit(int nr, volatile const unsigned long *addr)
diff --git a/arch/x86/include/asm/compat.h b/arch/x86/include/asm/compat.h
index 306160e58b48..1d9cd27c2920 100644
--- a/arch/x86/include/asm/compat.h
+++ b/arch/x86/include/asm/compat.h
@@ -205,7 +205,7 @@ static inline compat_uptr_t ptr_to_compat(void __user *uptr)
         return (u32)(unsigned long)uptr;
 }
 
-static inline void __user *compat_alloc_user_space(long len)
+static inline void __user *arch_compat_alloc_user_space(long len)
 {
         struct pt_regs *regs = task_pt_regs(current);
         return (void __user *)regs->sp - len;
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 781a50b29a49..3f76523589af 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -168,6 +168,7 @@
 #define X86_FEATURE_XSAVEOPT    (7*32+ 4) /* Optimized Xsave */
 #define X86_FEATURE_PLN         (7*32+ 5) /* Intel Power Limit Notification */
 #define X86_FEATURE_PTS         (7*32+ 6) /* Intel Package Thermal Status */
+#define X86_FEATURE_DTS         (7*32+ 7) /* Digital Thermal Sensor */
 
 /* Virtualization flags: Linux defined, word 8 */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
@@ -296,6 +297,7 @@ extern const char * const x86_power_flags[32];
 
 #endif /* CONFIG_X86_64 */
 
+#if __GNUC__ >= 4
 /*
  * Static testing of CPU features.  Used the same as boot_cpu_has().
  * These are only valid after alternatives have run, but will statically
@@ -304,7 +306,7 @@ extern const char * const x86_power_flags[32];
  */
 static __always_inline __pure bool __static_cpu_has(u16 bit)
 {
-#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+#if __GNUC__ > 4 || __GNUC_MINOR__ >= 5
                 asm goto("1: jmp %l[t_no]\n"
                          "2:\n"
                          ".section .altinstructions,\"a\"\n"
@@ -345,7 +347,6 @@ static __always_inline __pure bool __static_cpu_has(u16 bit)
 #endif
 }
 
-#if __GNUC__ >= 4
 #define static_cpu_has(bit)                                     \
 (                                                               \
         __builtin_constant_p(boot_cpu_has(bit)) ?               \
diff --git a/arch/x86/include/asm/hpet.h b/arch/x86/include/asm/hpet.h
index 004e6e25e913..1d5c08a1bdfd 100644
--- a/arch/x86/include/asm/hpet.h
+++ b/arch/x86/include/asm/hpet.h
@@ -68,7 +68,6 @@ extern unsigned long force_hpet_address;
 extern u8 hpet_blockid;
 extern int hpet_force_user;
 extern u8 hpet_msi_disable;
-extern u8 hpet_readback_cmp;
 extern int is_hpet_enabled(void);
 extern int hpet_enable(void);
 extern void hpet_disable(void);
diff --git a/arch/x86/include/asm/hw_breakpoint.h b/arch/x86/include/asm/hw_breakpoint.h
index 528a11e8d3e3..824ca07860d0 100644
--- a/arch/x86/include/asm/hw_breakpoint.h
+++ b/arch/x86/include/asm/hw_breakpoint.h
@@ -20,7 +20,7 @@ struct arch_hw_breakpoint {
 #include <linux/list.h>
 
 /* Available HW breakpoint length encodings */
-#define X86_BREAKPOINT_LEN_X            0x00
+#define X86_BREAKPOINT_LEN_X            0x40
 #define X86_BREAKPOINT_LEN_1            0x40
 #define X86_BREAKPOINT_LEN_2            0x44
 #define X86_BREAKPOINT_LEN_4            0x4c
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 0925676266bd..fedf32a8c3ec 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -11,6 +11,8 @@ ifdef CONFIG_FUNCTION_TRACER
 CFLAGS_REMOVE_tsc.o = -pg
 CFLAGS_REMOVE_rtc.o = -pg
 CFLAGS_REMOVE_paravirt-spinlocks.o = -pg
+CFLAGS_REMOVE_pvclock.o = -pg
+CFLAGS_REMOVE_kvmclock.o = -pg
 CFLAGS_REMOVE_ftrace.o = -pg
 CFLAGS_REMOVE_early_printk.o = -pg
 endif
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index fb7a5f052e2b..fb16f17e59be 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -61,7 +61,7 @@ struct cstate_entry {
                 unsigned int ecx;
         } states[ACPI_PROCESSOR_MAX_POWER];
 };
-static struct cstate_entry *cpu_cstate_entry;   /* per CPU ptr */
+static struct cstate_entry __percpu *cpu_cstate_entry;  /* per CPU ptr */
 
 static short mwait_supported[ACPI_PROCESSOR_MAX_POWER];
 
diff --git a/arch/x86/kernel/amd_iommu.c b/arch/x86/kernel/amd_iommu.c
index fa044e1e30a2..679b6450382b 100644
--- a/arch/x86/kernel/amd_iommu.c
+++ b/arch/x86/kernel/amd_iommu.c
@@ -1953,6 +1953,7 @@ static void __unmap_single(struct dma_ops_domain *dma_dom,
                            size_t size,
                            int dir)
 {
+        dma_addr_t flush_addr;
         dma_addr_t i, start;
         unsigned int pages;
 
@@ -1960,6 +1961,7 @@ static void __unmap_single(struct dma_ops_domain *dma_dom,
             (dma_addr + size > dma_dom->aperture_size))
                 return;
 
+        flush_addr = dma_addr;
         pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
         dma_addr &= PAGE_MASK;
         start = dma_addr;
@@ -1974,7 +1976,7 @@ static void __unmap_single(struct dma_ops_domain *dma_dom,
         dma_ops_free_addresses(dma_dom, dma_addr, pages);
 
         if (amd_iommu_unmap_flush || dma_dom->need_flush) {
-                iommu_flush_pages(&dma_dom->domain, dma_addr, size);
+                iommu_flush_pages(&dma_dom->domain, flush_addr, size);
                 dma_dom->need_flush = false;
         }
 }
diff --git a/arch/x86/kernel/amd_iommu_init.c b/arch/x86/kernel/amd_iommu_init.c
index 3cc63e2b8dd4..5a170cbbbed8 100644
--- a/arch/x86/kernel/amd_iommu_init.c
+++ b/arch/x86/kernel/amd_iommu_init.c
@@ -632,6 +632,13 @@ static void __init init_iommu_from_pci(struct amd_iommu *iommu)
         iommu->last_device = calc_devid(MMIO_GET_BUS(range),
                                         MMIO_GET_LD(range));
         iommu->evt_msi_num = MMIO_MSI_NUM(misc);
+
+        if (is_rd890_iommu(iommu->dev)) {
+                pci_read_config_dword(iommu->dev, 0xf0, &iommu->cache_cfg[0]);
+                pci_read_config_dword(iommu->dev, 0xf4, &iommu->cache_cfg[1]);
+                pci_read_config_dword(iommu->dev, 0xf8, &iommu->cache_cfg[2]);
+                pci_read_config_dword(iommu->dev, 0xfc, &iommu->cache_cfg[3]);
+        }
 }
 
 /*
@@ -649,29 +656,9 @@ static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
         struct ivhd_entry *e;
 
         /*
-         * First set the recommended feature enable bits from ACPI
-         * into the IOMMU control registers
+         * First save the recommended feature enable bits from ACPI
          */
-        h->flags & IVHD_FLAG_HT_TUN_EN_MASK ?
-                iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
-                iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
-
-        h->flags & IVHD_FLAG_PASSPW_EN_MASK ?
-                iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
-                iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
-
-        h->flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
-                iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
-                iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
-
-        h->flags & IVHD_FLAG_ISOC_EN_MASK ?
-                iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
-                iommu_feature_disable(iommu, CONTROL_ISOC_EN);
-
-        /*
-         * make IOMMU memory accesses cache coherent
-         */
-        iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
+        iommu->acpi_flags = h->flags;
 
         /*
          * Done. Now parse the device entries
@@ -1116,6 +1103,40 @@ static void init_device_table(void)
         }
 }
 
+static void iommu_init_flags(struct amd_iommu *iommu)
+{
+        iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
+                iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
+                iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
+
+        iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
+                iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
+                iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
+
+        iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
+                iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
+                iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
+
+        iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
+                iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
+                iommu_feature_disable(iommu, CONTROL_ISOC_EN);
+
+        /*
+         * make IOMMU memory accesses cache coherent
+         */
+        iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
+}
+
+static void iommu_apply_quirks(struct amd_iommu *iommu)
+{
+        if (is_rd890_iommu(iommu->dev)) {
+                pci_write_config_dword(iommu->dev, 0xf0, iommu->cache_cfg[0]);
+                pci_write_config_dword(iommu->dev, 0xf4, iommu->cache_cfg[1]);
+                pci_write_config_dword(iommu->dev, 0xf8, iommu->cache_cfg[2]);
+                pci_write_config_dword(iommu->dev, 0xfc, iommu->cache_cfg[3]);
+        }
+}
+
 /*
  * This function finally enables all IOMMUs found in the system after
  * they have been initialized
@@ -1126,6 +1147,8 @@ static void enable_iommus(void)
 
         for_each_iommu(iommu) {
                 iommu_disable(iommu);
+                iommu_apply_quirks(iommu);
+                iommu_init_flags(iommu);
                 iommu_set_device_table(iommu);
                 iommu_enable_command_buffer(iommu);
                 iommu_enable_event_buffer(iommu);
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index f1efebaf5510..5c5b8f3dddb5 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -306,14 +306,19 @@ void arch_init_copy_chip_data(struct irq_desc *old_desc,
 
         old_cfg = old_desc->chip_data;
 
-        memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
+        cfg->vector = old_cfg->vector;
+        cfg->move_in_progress = old_cfg->move_in_progress;
+        cpumask_copy(cfg->domain, old_cfg->domain);
+        cpumask_copy(cfg->old_domain, old_cfg->old_domain);
 
         init_copy_irq_2_pin(old_cfg, cfg, node);
 }
 
-static void free_irq_cfg(struct irq_cfg *old_cfg)
+static void free_irq_cfg(struct irq_cfg *cfg)
 {
-        kfree(old_cfg);
+        free_cpumask_var(cfg->domain);
+        free_cpumask_var(cfg->old_domain);
+        kfree(cfg);
 }
 
 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 7b598b84c902..f744f54cb248 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -698,9 +698,11 @@ void __init uv_system_init(void)
                 for (j = 0; j < 64; j++) {
                         if (!test_bit(j, &present))
                                 continue;
-                        uv_blade_info[blade].pnode = (i * 64 + j);
+                        pnode = (i * 64 + j);
+                        uv_blade_info[blade].pnode = pnode;
                         uv_blade_info[blade].nr_possible_cpus = 0;
                         uv_blade_info[blade].nr_online_cpus = 0;
+                        max_pnode = max(pnode, max_pnode);
                         blade++;
                 }
         }
@@ -738,7 +740,6 @@ void __init uv_system_init(void)
                 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
                 uv_node_to_blade[nid] = blade;
                 uv_cpu_to_blade[cpu] = blade;
-                max_pnode = max(pnode, max_pnode);
         }
 
         /* Add blade/pnode info for nodes without cpus */
@@ -750,7 +751,6 @@ void __init uv_system_init(void)
                 pnode = (paddr >> m_val) & pnode_mask;
                 blade = boot_pnode_to_blade(pnode);
                 uv_node_to_blade[nid] = blade;
-                max_pnode = max(pnode, max_pnode);
         }
 
         map_gru_high(max_pnode);
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 490dac63c2d2..f2f9ac7da25c 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -545,7 +545,7 @@ void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
         }
 }
 
-static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
+void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
 {
         u32 tfms, xlvl;
         u32 ebx;
diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h
index 3624e8a0f71b..f668bb1f7d43 100644
--- a/arch/x86/kernel/cpu/cpu.h
+++ b/arch/x86/kernel/cpu/cpu.h
@@ -33,5 +33,6 @@ extern const struct cpu_dev *const __x86_cpu_dev_start[],
                             *const __x86_cpu_dev_end[];
 
 extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c);
+extern void get_cpu_cap(struct cpuinfo_x86 *c);
 
 #endif
diff --git a/arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c b/arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c
index 994230d4dc4e..4f6f679f2799 100644
--- a/arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c
+++ b/arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c
@@ -368,16 +368,22 @@ static int __init pcc_cpufreq_do_osc(acpi_handle *handle)
                 return -ENODEV;
 
         out_obj = output.pointer;
-        if (out_obj->type != ACPI_TYPE_BUFFER)
-                return -ENODEV;
+        if (out_obj->type != ACPI_TYPE_BUFFER) {
+                ret = -ENODEV;
+                goto out_free;
+        }
 
         errors = *((u32 *)out_obj->buffer.pointer) & ~(1 << 0);
-        if (errors)
-                return -ENODEV;
+        if (errors) {
+                ret = -ENODEV;
+                goto out_free;
+        }
 
         supported = *((u32 *)(out_obj->buffer.pointer + 4));
-        if (!(supported & 0x1))
-                return -ENODEV;
+        if (!(supported & 0x1)) {
+                ret = -ENODEV;
+                goto out_free;
+        }
 
 out_free:
         kfree(output.pointer);
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 85f69cdeae10..b4389441efbb 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -39,6 +39,7 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
                         misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
                         wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
                         c->cpuid_level = cpuid_eax(0);
+                        get_cpu_cap(c);
                 }
         }
 
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 5e975298fa81..39aaee5c1ab2 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -141,6 +141,7 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
                                 address = (low & MASK_BLKPTR_LO) >> 21;
                                 if (!address)
                                         break;
+
                                 address += MCG_XBLK_ADDR;
                         } else
                                 ++address;
@@ -148,12 +149,8 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
                         if (rdmsr_safe(address, &low, &high))
                                 break;
 
-                        if (!(high & MASK_VALID_HI)) {
-                                if (block)
-                                        continue;
-                                else
-                                        break;
-                        }
+                        if (!(high & MASK_VALID_HI))
+                                continue;
 
                         if (!(high & MASK_CNTP_HI)  ||
                              (high & MASK_LOCKED_HI))
diff --git a/arch/x86/kernel/cpu/mcheck/therm_throt.c b/arch/x86/kernel/cpu/mcheck/therm_throt.c
index d9368eeda309..169d8804a9f8 100644
--- a/arch/x86/kernel/cpu/mcheck/therm_throt.c
+++ b/arch/x86/kernel/cpu/mcheck/therm_throt.c
@@ -216,7 +216,7 @@ static __cpuinit int thermal_throttle_add_dev(struct sys_device *sys_dev,
                 err = sysfs_add_file_to_group(&sys_dev->kobj,
                                               &attr_core_power_limit_count.attr,
                                               thermal_attr_group.name);
-        if (cpu_has(c, X86_FEATURE_PTS))
+        if (cpu_has(c, X86_FEATURE_PTS)) {
                 err = sysfs_add_file_to_group(&sys_dev->kobj,
                                               &attr_package_throttle_count.attr,
                                               thermal_attr_group.name);
@@ -224,6 +224,7 @@ static __cpuinit int thermal_throttle_add_dev(struct sys_device *sys_dev,
                         err = sysfs_add_file_to_group(&sys_dev->kobj,
                                         &attr_package_power_limit_count.attr,
                                         thermal_attr_group.name);
+        }
 
         return err;
 }
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 3efdf2870a35..03a5b0385ad6 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -102,6 +102,7 @@ struct cpu_hw_events {
          */
         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
+        unsigned long           running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
         int                     enabled;
 
         int                     n_events;
@@ -1010,6 +1011,7 @@ static int x86_pmu_start(struct perf_event *event)
         x86_perf_event_set_period(event);
         cpuc->events[idx] = event;
         __set_bit(idx, cpuc->active_mask);
+        __set_bit(idx, cpuc->running);
         x86_pmu.enable(event);
         perf_event_update_userpage(event);
 
@@ -1141,8 +1143,16 @@ static int x86_pmu_handle_irq(struct pt_regs *regs)
         cpuc = &__get_cpu_var(cpu_hw_events);
 
         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
-                if (!test_bit(idx, cpuc->active_mask))
+                if (!test_bit(idx, cpuc->active_mask)) {
+                        /*
+                         * Though we deactivated the counter some cpus
+                         * might still deliver spurious interrupts still
+                         * in flight. Catch them:
+                         */
+                        if (__test_and_clear_bit(idx, cpuc->running))
+                                handled++;
                         continue;
+                }
 
                 event = cpuc->events[idx];
                 hwc = &event->hw;
diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c
index b560db3305be..249015173992 100644
--- a/arch/x86/kernel/cpu/perf_event_p4.c
+++ b/arch/x86/kernel/cpu/perf_event_p4.c
@@ -660,8 +660,12 @@ static int p4_pmu_handle_irq(struct pt_regs *regs)
         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
                 int overflow;
 
-                if (!test_bit(idx, cpuc->active_mask))
+                if (!test_bit(idx, cpuc->active_mask)) {
+                        /* catch in-flight IRQs */
+                        if (__test_and_clear_bit(idx, cpuc->running))
+                                handled++;
                         continue;
+                }
 
                 event = cpuc->events[idx];
                 hwc = &event->hw;
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 34b4dad6f0b8..d49079515122 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -31,6 +31,7 @@ void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
         const struct cpuid_bit *cb;
 
         static const struct cpuid_bit __cpuinitconst cpuid_bits[] = {
+                { X86_FEATURE_DTS,              CR_EAX, 0, 0x00000006, 0 },
                 { X86_FEATURE_IDA,              CR_EAX, 1, 0x00000006, 0 },
                 { X86_FEATURE_ARAT,             CR_EAX, 2, 0x00000006, 0 },
                 { X86_FEATURE_PLN,              CR_EAX, 4, 0x00000006, 0 },
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index e5cc7e82e60d..ebdb85cf2686 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -18,7 +18,6 @@
 #include <asm/apic.h>
 #include <asm/iommu.h>
 #include <asm/gart.h>
-#include <asm/hpet.h>
 
 static void __init fix_hypertransport_config(int num, int slot, int func)
 {
@@ -192,21 +191,6 @@ static void __init ati_bugs_contd(int num, int slot, int func)
 }
 #endif
 
-/*
- * Force the read back of the CMP register in hpet_next_event()
- * to work around the problem that the CMP register write seems to be
- * delayed. See hpet_next_event() for details.
- *
- * We do this on all SMBUS incarnations for now until we have more
- * information about the affected chipsets.
- */
-static void __init ati_hpet_bugs(int num, int slot, int func)
-{
-#ifdef CONFIG_HPET_TIMER
-        hpet_readback_cmp = 1;
-#endif
-}
-
 #define QFLAG_APPLY_ONCE        0x1
 #define QFLAG_APPLIED           0x2
 #define QFLAG_DONE              (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
@@ -236,8 +220,6 @@ static struct chipset early_qrk[] __initdata = {
           PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
           PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
-        { PCI_VENDOR_ID_ATI, PCI_ANY_ID,
-          PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_hpet_bugs },
         {}
 };
 
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index 351f9c0fea1f..7494999141b3 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -35,7 +35,6 @@
 unsigned long                           hpet_address;
 u8                                      hpet_blockid; /* OS timer block num */
 u8                                      hpet_msi_disable;
-u8                                      hpet_readback_cmp;
 
 #ifdef CONFIG_PCI_MSI
 static unsigned long                    hpet_num_timers;
@@ -395,23 +394,27 @@ static int hpet_next_event(unsigned long delta,
          * at that point and we would wait for the next hpet interrupt
          * forever. We found out that reading the CMP register back
          * forces the transfer so we can rely on the comparison with
-         * the counter register below.
+         * the counter register below. If the read back from the
+         * compare register does not match the value we programmed
+         * then we might have a real hardware problem. We can not do
+         * much about it here, but at least alert the user/admin with
+         * a prominent warning.
          *
-         * That works fine on those ATI chipsets, but on newer Intel
-         * chipsets (ICH9...) this triggers due to an erratum: Reading
-         * the comparator immediately following a write is returning
-         * the old value.
+         * An erratum on some chipsets (ICH9,..), results in
+         * comparator read immediately following a write returning old
+         * value. Workaround for this is to read this value second
+         * time, when first read returns old value.
          *
-         * We restrict the read back to the affected ATI chipsets (set
-         * by quirks) and also run it with hpet=verbose for debugging
-         * purposes.
+         * In fact the write to the comparator register is delayed up
+         * to two HPET cycles so the workaround we tried to restrict
+         * the readback to those known to be borked ATI chipsets
+         * failed miserably. So we give up on optimizations forever
+         * and penalize all HPET incarnations unconditionally.
          */
-        if (hpet_readback_cmp || hpet_verbose) {
-                u32 cmp = hpet_readl(HPET_Tn_CMP(timer));
-
-                if (cmp != cnt)
+        if (unlikely((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt)) {
+                if (hpet_readl(HPET_Tn_CMP(timer)) != cnt)
                         printk_once(KERN_WARNING
-                            "hpet: compare register read back failed.\n");
+                                "hpet: compare register read back failed.\n");
         }
 
         return (s32)(hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
@@ -503,7 +506,7 @@ static int hpet_assign_irq(struct hpet_dev *dev)
 {
         unsigned int irq;
 
-        irq = create_irq();
+        irq = create_irq_nr(0, -1);
         if (!irq)
                 return -EINVAL;
 
diff --git a/arch/x86/kernel/hw_breakpoint.c b/arch/x86/kernel/hw_breakpoint.c
index a474ec37c32f..ff15c9dcc25d 100644
--- a/arch/x86/kernel/hw_breakpoint.c
+++ b/arch/x86/kernel/hw_breakpoint.c
@@ -206,11 +206,27 @@ int arch_check_bp_in_kernelspace(struct perf_event *bp)
 int arch_bp_generic_fields(int x86_len, int x86_type,
                            int *gen_len, int *gen_type)
 {
-        /* Len */
-        switch (x86_len) {
-        case X86_BREAKPOINT_LEN_X:
+        /* Type */
+        switch (x86_type) {
+        case X86_BREAKPOINT_EXECUTE:
+                if (x86_len != X86_BREAKPOINT_LEN_X)
+                        return -EINVAL;
+
+                *gen_type = HW_BREAKPOINT_X;
                 *gen_len = sizeof(long);
+                return 0;
+        case X86_BREAKPOINT_WRITE:
+                *gen_type = HW_BREAKPOINT_W;
                 break;
+        case X86_BREAKPOINT_RW:
+                *gen_type = HW_BREAKPOINT_W | HW_BREAKPOINT_R;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /* Len */
+        switch (x86_len) {
         case X86_BREAKPOINT_LEN_1:
                 *gen_len = HW_BREAKPOINT_LEN_1;
                 break;
@@ -229,21 +245,6 @@ int arch_bp_generic_fields(int x86_len, int x86_type,
                 return -EINVAL;
         }
 
-        /* Type */
-        switch (x86_type) {
-        case X86_BREAKPOINT_EXECUTE:
-                *gen_type = HW_BREAKPOINT_X;
-                break;
-        case X86_BREAKPOINT_WRITE:
-                *gen_type = HW_BREAKPOINT_W;
-                break;
-        case X86_BREAKPOINT_RW:
-                *gen_type = HW_BREAKPOINT_W | HW_BREAKPOINT_R;
-                break;
-        default:
-                return -EINVAL;
-        }
-
         return 0;
 }
 
@@ -316,9 +317,6 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
         ret = -EINVAL;
 
         switch (info->len) {
-        case X86_BREAKPOINT_LEN_X:
-                align = sizeof(long) -1;
-                break;
         case X86_BREAKPOINT_LEN_1:
                 align = 0;
                 break;
diff --git a/arch/x86/kernel/module.c b/arch/x86/kernel/module.c
index e0bc186d7501..1c355c550960 100644
--- a/arch/x86/kernel/module.c
+++ b/arch/x86/kernel/module.c
@@ -239,11 +239,10 @@ int module_finalize(const Elf_Ehdr *hdr,
                 apply_paravirt(pseg, pseg + para->sh_size);
         }
 
-        return module_bug_finalize(hdr, sechdrs, me);
+        return 0;
 }
 
 void module_arch_cleanup(struct module *mod)
 {
         alternatives_smp_module_del(mod);
-        module_bug_cleanup(mod);
 }
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index bc5b9b8d4a33..81ed28cb36e6 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -766,7 +766,6 @@ static void init_vmcb(struct vcpu_svm *svm)
 
         control->iopm_base_pa = iopm_base;
         control->msrpm_base_pa = __pa(svm->msrpm);
-        control->tsc_offset = 0;
         control->int_ctl = V_INTR_MASKING_MASK;
 
         init_seg(&save->es);
@@ -902,6 +901,7 @@ static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
         svm->asid_generation = 0;
         init_vmcb(svm);
+        svm->vmcb->control.tsc_offset = 0-native_read_tsc();
 
         err = fx_init(&svm->vcpu);
         if (err)
diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c
index 9257510b4836..9d5f55848455 100644
--- a/arch/x86/lguest/boot.c
+++ b/arch/x86/lguest/boot.c
@@ -324,9 +324,8 @@ static void lguest_load_gdt(const struct desc_ptr *desc)
 }
 
 /*
- * For a single GDT entry which changes, we do the lazy thing: alter our GDT,
- * then tell the Host to reload the entire thing.  This operation is so rare
- * that this naive implementation is reasonable.
+ * For a single GDT entry which changes, we simply change our copy and
+ * then tell the host about it.
  */
 static void lguest_write_gdt_entry(struct desc_struct *dt, int entrynum,
                                    const void *desc, int type)
@@ -338,9 +337,13 @@ static void lguest_write_gdt_entry(struct desc_struct *dt, int entrynum,
 }
 
 /*
- * OK, I lied.  There are three "thread local storage" GDT entries which change
+ * There are three "thread local storage" GDT entries which change
  * on every context switch (these three entries are how glibc implements
- * __thread variables).  So we have a hypercall specifically for this case.
+ * __thread variables).  As an optimization, we have a hypercall
+ * specifically for this case.
+ *
+ * Wouldn't it be nicer to have a general LOAD_GDT_ENTRIES hypercall
+ * which took a range of entries?
  */
 static void lguest_load_tls(struct thread_struct *t, unsigned int cpu)
 {
diff --git a/arch/x86/mm/srat_64.c b/arch/x86/mm/srat_64.c
index f9897f7a9ef1..9c0d0d399c30 100644
--- a/arch/x86/mm/srat_64.c
+++ b/arch/x86/mm/srat_64.c
@@ -420,9 +420,11 @@ int __init acpi_scan_nodes(unsigned long start, unsigned long end)
                 return -1;
         }
 
-        for_each_node_mask(i, nodes_parsed)
-                e820_register_active_regions(i, nodes[i].start >> PAGE_SHIFT,
-                                                nodes[i].end >> PAGE_SHIFT);
+        for (i = 0; i < num_node_memblks; i++)
+                e820_register_active_regions(memblk_nodeid[i],
+                                node_memblk_range[i].start >> PAGE_SHIFT,
+                                node_memblk_range[i].end >> PAGE_SHIFT);
+
         /* for out of order entries in SRAT */
         sort_node_map();
         if (!nodes_cover_memory(nodes)) {
diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c
index cfe4faabb0f6..f1575c9a2572 100644
--- a/arch/x86/oprofile/nmi_int.c
+++ b/arch/x86/oprofile/nmi_int.c
@@ -671,7 +671,10 @@ static int __init ppro_init(char **cpu_type)
         case 14:
                 *cpu_type = "i386/core";
                 break;
-        case 15: case 23:
+        case 0x0f:
+        case 0x16:
+        case 0x17:
+        case 0x1d:
                 *cpu_type = "i386/core_2";
                 break;
         case 0x1a:
diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
index 1a5353a753fc..b2bb5aa3b054 100644
--- a/arch/x86/xen/time.c
+++ b/arch/x86/xen/time.c
@@ -489,8 +489,9 @@ static void xen_hvm_setup_cpu_clockevents(void)
 __init void xen_hvm_init_time_ops(void)
 {
         /* vector callback is needed otherwise we cannot receive interrupts
-         * on cpu > 0 */
-        if (!xen_have_vector_callback && num_present_cpus() > 1)
+         * on cpu > 0 and at this point we don't know how many cpus are
+         * available */
+        if (!xen_have_vector_callback)
                 return;
         if (!xen_feature(XENFEAT_hvm_safe_pvclock)) {
                 printk(KERN_INFO "Xen doesn't support pvclock on HVM,"