10 files changed, 402 insertions, 234 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bb57f35e7683..cfd99649ad85 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -586,6 +586,7 @@ config ARCH_DAVINCI
         select HAVE_CLK
         select ZONE_DMA
         select HAVE_IDE
+        select COMMON_CLKDEV
         help
           Support for TI's DaVinci platform.
 
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index bac988e7a4c3..af886734c73b 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -18,6 +18,18 @@ config MACH_DAVINCI_EVM
           Configure this option to specify the whether the board used
           for development is a DaVinci EVM
 
+config DAVINCI_RESET_CLOCKS
+        bool "Reset unused clocks during boot"
+        depends on ARCH_DAVINCI
+        help
+          Say Y if you want to reset unused clocks during boot.
+          This option saves power, but assumes all drivers are
+          using the clock framework. Broken drivers that do not
+          yet use clock framework may not work with this option.
+          If you are booting from another operating system, you
+          probably do not want this option enabled until your
+          device drivers work properly.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-davinci/board-evm.c b/arch/arm/mach-davinci/board-evm.c
index 0b97a528902b..1b745c39d891 100644
--- a/arch/arm/mach-davinci/board-evm.c
+++ b/arch/arm/mach-davinci/board-evm.c
@@ -406,8 +406,6 @@ davinci_evm_map_io(void)
 
 static __init void davinci_evm_init(void)
 {
-        davinci_psc_init();
-
 #if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
     defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
 #if defined(CONFIG_MTD_PHYSMAP) || \
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index abb92b7eca0c..f0baaa15a57e 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -1,7 +1,8 @@
 /*
- * TI DaVinci clock config file
+ * Clock and PLL control for DaVinci devices
  *
- * Copyright (C) 2006 Texas Instruments.
+ * Copyright (C) 2006-2007 Texas Instruments.
+ * Copyright (C) 2008-2009 Deep Root Systems, LLC
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -13,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/errno.h>
+#include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/mutex.h>
 #include <linux/platform_device.h>
@@ -21,98 +23,50 @@
 #include <mach/hardware.h>
 
 #include <mach/psc.h>
+#include <mach/cputype.h>
 #include "clock.h"
 
-/* PLL/Reset register offsets */
-#define PLLM            0x110
-
 static LIST_HEAD(clocks);
 static DEFINE_MUTEX(clocks_mutex);
 static DEFINE_SPINLOCK(clockfw_lock);
 
-static unsigned int commonrate;
-static unsigned int armrate;
-static unsigned int fixedrate = 27000000;       /* 27 MHZ */
-
-extern void davinci_psc_config(unsigned int domain, unsigned int id, char enable);
-
-/*
- * Returns a clock. Note that we first try to use device id on the bus
- * and clock name. If this fails, we try to use clock name only.
- */
-struct clk *clk_get(struct device *dev, const char *id)
+static unsigned psc_domain(struct clk *clk)
 {
-        struct clk *p, *clk = ERR_PTR(-ENOENT);
-        int idno;
-
-        if (dev == NULL || dev->bus != &platform_bus_type)
-                idno = -1;
-        else
-                idno = to_platform_device(dev)->id;
-
-        mutex_lock(&clocks_mutex);
-
-        list_for_each_entry(p, &clocks, node) {
-                if (p->id == idno &&
-                    strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
-                        clk = p;
-                        goto found;
-                }
-        }
-
-        list_for_each_entry(p, &clocks, node) {
-                if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
-                        clk = p;
-                        break;
-                }
-        }
-
-found:
-        mutex_unlock(&clocks_mutex);
-
-        return clk;
+        return (clk->flags & PSC_DSP)
+                ? DAVINCI_GPSC_DSPDOMAIN
+                : DAVINCI_GPSC_ARMDOMAIN;
 }
-EXPORT_SYMBOL(clk_get);
 
-void clk_put(struct clk *clk)
+static void __clk_enable(struct clk *clk)
 {
-        if (clk && !IS_ERR(clk))
-                module_put(clk->owner);
-}
-EXPORT_SYMBOL(clk_put);
-
-static int __clk_enable(struct clk *clk)
-{
-        if (clk->flags & ALWAYS_ENABLED)
-                return 0;
-
-        davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 1);
-        return 0;
+        if (clk->parent)
+                __clk_enable(clk->parent);
+        if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
+                davinci_psc_config(psc_domain(clk), clk->lpsc, 1);
 }
 
 static void __clk_disable(struct clk *clk)
 {
-        if (clk->usecount)
+        if (WARN_ON(clk->usecount == 0))
                 return;
-
-        davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 0);
+        if (--clk->usecount == 0 && !(clk->flags & CLK_PLL))
+                davinci_psc_config(psc_domain(clk), clk->lpsc, 0);
+        if (clk->parent)
+                __clk_disable(clk->parent);
 }
 
 int clk_enable(struct clk *clk)
 {
         unsigned long flags;
-        int ret = 0;
 
         if (clk == NULL || IS_ERR(clk))
                 return -EINVAL;
 
-        if (clk->usecount++ == 0) {
-                spin_lock_irqsave(&clockfw_lock, flags);
-                ret = __clk_enable(clk);
-                spin_unlock_irqrestore(&clockfw_lock, flags);
-        }
+        spin_lock_irqsave(&clockfw_lock, flags);
+        __clk_enable(clk);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
 
-        return ret;
+        return 0;
 }
 EXPORT_SYMBOL(clk_enable);
 
@@ -123,11 +77,9 @@ void clk_disable(struct clk *clk)
         if (clk == NULL || IS_ERR(clk))
                 return;
 
-        if (clk->usecount > 0 && !(--clk->usecount)) {
-                spin_lock_irqsave(&clockfw_lock, flags);
-                __clk_disable(clk);
-                spin_unlock_irqrestore(&clockfw_lock, flags);
-        }
+        spin_lock_irqsave(&clockfw_lock, flags);
+        __clk_disable(clk);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
 }
 EXPORT_SYMBOL(clk_disable);
 
@@ -136,7 +88,7 @@ unsigned long clk_get_rate(struct clk *clk)
         if (clk == NULL || IS_ERR(clk))
                 return -EINVAL;
 
-        return *(clk->rate);
+        return clk->rate;
 }
 EXPORT_SYMBOL(clk_get_rate);
 
@@ -145,7 +97,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
         if (clk == NULL || IS_ERR(clk))
                 return -EINVAL;
 
-        return *(clk->rate);
+        return clk->rate;
 }
 EXPORT_SYMBOL(clk_round_rate);
 
@@ -164,10 +116,23 @@ int clk_register(struct clk *clk)
         if (clk == NULL || IS_ERR(clk))
                 return -EINVAL;
 
+        if (WARN(clk->parent && !clk->parent->rate,
+                        "CLK: %s parent %s has no rate!\n",
+                        clk->name, clk->parent->name))
+                return -EINVAL;
+
         mutex_lock(&clocks_mutex);
-        list_add(&clk->node, &clocks);
+        list_add_tail(&clk->node, &clocks);
         mutex_unlock(&clocks_mutex);
 
+        /* If rate is already set, use it */
+        if (clk->rate)
+                return 0;
+
+        /* Otherwise, default to parent rate */
+        if (clk->parent)
+                clk->rate = clk->parent->rate;
+
         return 0;
 }
 EXPORT_SYMBOL(clk_register);
@@ -183,84 +148,150 @@ void clk_unregister(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_unregister);
 
-static struct clk davinci_clks[] = {
-        {
-                .name = "ARMCLK",
-                .rate = &armrate,
-                .lpsc = -1,
-                .flags = ALWAYS_ENABLED,
-        },
-        {
-                .name = "UART",
-                .rate = &fixedrate,
-                .lpsc = DAVINCI_LPSC_UART0,
-        },
-        {
-                .name = "EMACCLK",
-                .rate = &commonrate,
-                .lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
-        },
-        {
-                .name = "I2CCLK",
-                .rate = &fixedrate,
-                .lpsc = DAVINCI_LPSC_I2C,
-        },
-        {
-                .name = "IDECLK",
-                .rate = &commonrate,
-                .lpsc = DAVINCI_LPSC_ATA,
-        },
-        {
-                .name = "McBSPCLK",
-                .rate = &commonrate,
-                .lpsc = DAVINCI_LPSC_McBSP,
-        },
-        {
-                .name = "MMCSDCLK",
-                .rate = &commonrate,
-                .lpsc = DAVINCI_LPSC_MMC_SD,
-        },
-        {
-                .name = "SPICLK",
-                .rate = &commonrate,
-                .lpsc = DAVINCI_LPSC_SPI,
-        },
-        {
-                .name = "gpio",
-                .rate = &commonrate,
-                .lpsc = DAVINCI_LPSC_GPIO,
-        },
-        {
-                .name = "usb",
-                .rate = &commonrate,
-                .lpsc = DAVINCI_LPSC_USB,
-        },
-        {
-                .name = "AEMIFCLK",
-                .rate = &commonrate,
-                .lpsc = DAVINCI_LPSC_AEMIF,
-                .usecount = 1,
+#ifdef CONFIG_DAVINCI_RESET_CLOCKS
+/*
+ * Disable any unused clocks left on by the bootloader
+ */
+static int __init clk_disable_unused(void)
+{
+        struct clk *ck;
+
+        spin_lock_irq(&clockfw_lock);
+        list_for_each_entry(ck, &clocks, node) {
+                if (ck->usecount > 0)
+                        continue;
+                if (!(ck->flags & CLK_PSC))
+                        continue;
+
+                /* ignore if in Disabled or SwRstDisable states */
+                if (!davinci_psc_is_clk_active(ck->lpsc))
+                        continue;
+
+                pr_info("Clocks: disable unused %s\n", ck->name);
+                davinci_psc_config(psc_domain(ck), ck->lpsc, 0);
         }
-};
+        spin_unlock_irq(&clockfw_lock);
+
+        return 0;
+}
+late_initcall(clk_disable_unused);
+#endif
 
-int __init davinci_clk_init(void)
+static void clk_sysclk_recalc(struct clk *clk)
 {
-        struct clk *clkp;
-        int count = 0;
-        u32 pll_mult;
-
-        pll_mult = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLM);
-        commonrate = ((pll_mult + 1) * 27000000) / 6;
-        armrate = ((pll_mult + 1) * 27000000) / 2;
-
-        for (clkp = davinci_clks; count < ARRAY_SIZE(davinci_clks);
-             count++, clkp++) {
-                clk_register(clkp);
-
-                /* Turn on clocks that have been enabled in the
-                 * table above */
-                if (clkp->usecount)
-                        clk_enable(clkp);
+        u32 v, plldiv;
+        struct pll_data *pll;
+
+        /* If this is the PLL base clock, no more calculations needed */
+        if (clk->pll_data)
+                return;
+
+        if (WARN_ON(!clk->parent))
+                return;
+
+        clk->rate = clk->parent->rate;
+
+        /* Otherwise, the parent must be a PLL */
+        if (WARN_ON(!clk->parent->pll_data))
+                return;
+
+        pll = clk->parent->pll_data;
+
+        /* If pre-PLL, source clock is before the multiplier and divider(s) */
+        if (clk->flags & PRE_PLL)
+                clk->rate = pll->input_rate;
+
+        if (!clk->div_reg)
+                return;
+
+        v = __raw_readl(pll->base + clk->div_reg);
+        if (v & PLLDIV_EN) {
+                plldiv = (v & PLLDIV_RATIO_MASK) + 1;
+                if (plldiv)
+                        clk->rate /= plldiv;
+        }
+}
+
+static void __init clk_pll_init(struct clk *clk)
+{
+        u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
+        u8 bypass;
+        struct pll_data *pll = clk->pll_data;
+
+        pll->base = IO_ADDRESS(pll->phys_base);
+        ctrl = __raw_readl(pll->base + PLLCTL);
+        clk->rate = pll->input_rate = clk->parent->rate;
+
+        if (ctrl & PLLCTL_PLLEN) {
+                bypass = 0;
+                mult = __raw_readl(pll->base + PLLM);
+                mult = (mult & PLLM_PLLM_MASK) + 1;
+        } else
+                bypass = 1;
+
+        if (pll->flags & PLL_HAS_PREDIV) {
+                prediv = __raw_readl(pll->base + PREDIV);
+                if (prediv & PLLDIV_EN)
+                        prediv = (prediv & PLLDIV_RATIO_MASK) + 1;
+                else
+                        prediv = 1;
+        }
+
+        /* pre-divider is fixed, but (some?) chips won't report that */
+        if (cpu_is_davinci_dm355() && pll->num == 1)
+                prediv = 8;
+
+        if (pll->flags & PLL_HAS_POSTDIV) {
+                postdiv = __raw_readl(pll->base + POSTDIV);
+                if (postdiv & PLLDIV_EN)
+                        postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1;
+                else
+                        postdiv = 1;
+        }
+
+        if (!bypass) {
+                clk->rate /= prediv;
+                clk->rate *= mult;
+                clk->rate /= postdiv;
+        }
+
+        pr_debug("PLL%d: input = %lu MHz [ ",
+                 pll->num, clk->parent->rate / 1000000);
+        if (bypass)
+                pr_debug("bypass ");
+        if (prediv > 1)
+                pr_debug("/ %d ", prediv);
+        if (mult > 1)
+                pr_debug("* %d ", mult);
+        if (postdiv > 1)
+                pr_debug("/ %d ", postdiv);
+        pr_debug("] --> %lu MHz output.\n", clk->rate / 1000000);
+}
+
+int __init davinci_clk_init(struct davinci_clk *clocks)
+  {
+        struct davinci_clk *c;
+        struct clk *clk;
+
+        for (c = clocks; c->lk.clk; c++) {
+                clk = c->lk.clk;
+
+                if (clk->pll_data)
+                        clk_pll_init(clk);
+
+                /* Calculate rates for PLL-derived clocks */
+                else if (clk->flags & CLK_PLL)
+                        clk_sysclk_recalc(clk);
+
+                if (clk->lpsc)
+                        clk->flags |= CLK_PSC;
+
+                clkdev_add(&c->lk);
+                clk_register(clk);
+
+                /* Turn on clocks that Linux doesn't otherwise manage */
+                if (clk->flags & ALWAYS_ENABLED)
+                        clk_enable(clk);
         }
 
         return 0;
@@ -285,12 +316,52 @@ static void davinci_ck_stop(struct seq_file *m, void *v)
 {
 }
 
-static int davinci_ck_show(struct seq_file *m, void *v)
+#define CLKNAME_MAX     10              /* longest clock name */
+#define NEST_DELTA      2
+#define NEST_MAX        4
+
+static void
+dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
 {
-        struct clk *cp;
+        char            *state;
+        char            buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
+        struct clk      *clk;
+        unsigned        i;
+
+        if (parent->flags & CLK_PLL)
+                state = "pll";
+        else if (parent->flags & CLK_PSC)
+                state = "psc";
+        else
+                state = "";
+
+        /* <nest spaces> name <pad to end> */
+        memset(buf, ' ', sizeof(buf) - 1);
+        buf[sizeof(buf) - 1] = 0;
+        i = strlen(parent->name);
+        memcpy(buf + nest, parent->name,
+                        min(i, (unsigned)(sizeof(buf) - 1 - nest)));
+
+        seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
+                   buf, parent->usecount, state, clk_get_rate(parent));
+        /* REVISIT show device associations too */
+
+        /* cost is now small, but not linear... */
+        list_for_each_entry(clk, &clocks, node) {
+                if (clk->parent == parent)
+                        dump_clock(s, nest + NEST_DELTA, clk);
+        }
+}
 
-        list_for_each_entry(cp, &clocks, node)
-                seq_printf(m,"%s %d %d\n", cp->name, *(cp->rate), cp->usecount);
+static int davinci_ck_show(struct seq_file *m, void *v)
+{
+        /* Show clock tree; we know the main oscillator is first.
+         * We trust nonzero usecounts equate to PSC enables...
+         */
+        mutex_lock(&clocks_mutex);
+        if (!list_empty(&clocks))
+                dump_clock(m, 0, list_first_entry(&clocks, struct clk, node));
+        mutex_unlock(&clocks_mutex);
 
         return 0;
 }
@@ -321,4 +392,4 @@ static int __init davinci_ck_proc_init(void)
 
 }
 __initcall(davinci_ck_proc_init);
-#endif  /* CONFIG_DEBUG_PROC_FS */
+#endif /* CONFIG_DEBUG_PROC_FS */
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index ed47079a52e4..35736ec202f8 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -1,7 +1,8 @@
 /*
  * TI DaVinci clock definitions
  *
- * Copyright (C) 2006 Texas Instruments.
+ * Copyright (C) 2006-2007 Texas Instruments.
+ * Copyright (C) 2008-2009 Deep Root Systems, LLC
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -11,23 +12,85 @@
 #ifndef __ARCH_ARM_DAVINCI_CLOCK_H
 #define __ARCH_ARM_DAVINCI_CLOCK_H
 
+#include <linux/list.h>
+#include <asm/clkdev.h>
+
+#define DAVINCI_PLL1_BASE 0x01c40800
+#define DAVINCI_PLL2_BASE 0x01c40c00
+#define MAX_PLL 2
+
+/* PLL/Reset register offsets */
+#define PLLCTL          0x100
+#define PLLCTL_PLLEN    BIT(0)
+#define PLLCTL_CLKMODE  BIT(8)
+
+#define PLLM            0x110
+#define PLLM_PLLM_MASK  0xff
+
+#define PREDIV          0x114
+#define PLLDIV1         0x118
+#define PLLDIV2         0x11c
+#define PLLDIV3         0x120
+#define POSTDIV         0x128
+#define BPDIV           0x12c
+#define PLLCMD          0x138
+#define PLLSTAT         0x13c
+#define PLLALNCTL       0x140
+#define PLLDCHANGE      0x144
+#define PLLCKEN         0x148
+#define PLLCKSTAT       0x14c
+#define PLLSYSTAT       0x150
+#define PLLDIV4         0x160
+#define PLLDIV5         0x164
+#define PLLDIV6         0x168
+#define PLLDIV7         0x16c
+#define PLLDIV8         0x170
+#define PLLDIV9         0x174
+#define PLLDIV_EN       BIT(15)
+#define PLLDIV_RATIO_MASK 0x1f
+
+struct pll_data {
+        u32 phys_base;
+        void __iomem *base;
+        u32 num;
+        u32 flags;
+        u32 input_rate;
+};
+#define PLL_HAS_PREDIV          0x01
+#define PLL_HAS_POSTDIV         0x02
+
 struct clk {
         struct list_head        node;
         struct module           *owner;
         const char              *name;
-        unsigned int            *rate;
-        int                     id;
-        __s8                    usecount;
-        __u8                    flags;
-        __u8                    lpsc;
+        unsigned long           rate;
+        u8                      usecount;
+        u8                      flags;
+        u8                      lpsc;
+        struct clk              *parent;
+        struct pll_data         *pll_data;
+        u32                     div_reg;
 };
 
 /* Clock flags */
-#define RATE_CKCTL              1
-#define RATE_FIXED              2
-#define RATE_PROPAGATES         4
-#define VIRTUAL_CLOCK           8
-#define ALWAYS_ENABLED          16
-#define ENABLE_REG_32BIT        32
+#define ALWAYS_ENABLED          BIT(1)
+#define CLK_PSC                 BIT(2)
+#define PSC_DSP                 BIT(3) /* PSC uses DSP domain, not ARM */
+#define CLK_PLL                 BIT(4) /* PLL-derived clock */
+#define PRE_PLL                 BIT(5) /* source is before PLL mult/div */
+
+struct davinci_clk {
+        struct clk_lookup lk;
+};
+
+#define CLK(dev, con, ck)               \
+        {                               \
+                .lk = {                 \
+                        .dev_id = dev,  \
+                        .con_id = con,  \
+                        .clk = ck,      \
+                },                      \
+        }
 
+int davinci_clk_init(struct davinci_clk *clocks);
 #endif
diff --git a/arch/arm/mach-davinci/include/mach/clkdev.h b/arch/arm/mach-davinci/include/mach/clkdev.h
new file mode 100644
index 000000000000..730c49d1ebd8
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/clkdev.h
@@ -0,0 +1,13 @@
+#ifndef __MACH_CLKDEV_H
+#define __MACH_CLKDEV_H
+
+static inline int __clk_get(struct clk *clk)
+{
+        return 1;
+}
+
+static inline void __clk_put(struct clk *clk)
+{
+}
+
+#endif
diff --git a/arch/arm/mach-davinci/include/mach/clock.h b/arch/arm/mach-davinci/include/mach/clock.h
index 38bdd49bc181..a3b040219876 100644
--- a/arch/arm/mach-davinci/include/mach/clock.h
+++ b/arch/arm/mach-davinci/include/mach/clock.h
@@ -17,6 +17,5 @@ struct clk;
 
 extern int clk_register(struct clk *clk);
 extern void clk_unregister(struct clk *clk);
-extern int davinci_clk_init(void);
 
 #endif
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 4977aa071e1e..55a90d419fac 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -38,8 +38,6 @@
 #define DAVINCI_LPSC_TPTC1          4
 #define DAVINCI_LPSC_EMAC           5
 #define DAVINCI_LPSC_EMAC_WRAPPER   6
-#define DAVINCI_LPSC_MDIO           7
-#define DAVINCI_LPSC_IEEE1394       8
 #define DAVINCI_LPSC_USB            9
 #define DAVINCI_LPSC_ATA            10
 #define DAVINCI_LPSC_VLYNQ          11
@@ -47,7 +45,6 @@
 #define DAVINCI_LPSC_DDR_EMIF       13
 #define DAVINCI_LPSC_AEMIF          14
 #define DAVINCI_LPSC_MMC_SD         15
-#define DAVINCI_LPSC_MEMSTICK       16
 #define DAVINCI_LPSC_McBSP          17
 #define DAVINCI_LPSC_I2C            18
 #define DAVINCI_LPSC_UART0          19
@@ -73,4 +70,54 @@
 #define DAVINCI_LPSC_GEM            39
 #define DAVINCI_LPSC_IMCOP          40
 
+#define DM355_LPSC_TIMER3               5
+#define DM355_LPSC_SPI1                 6
+#define DM355_LPSC_MMC_SD1              7
+#define DM355_LPSC_McBSP1               8
+#define DM355_LPSC_PWM3                 10
+#define DM355_LPSC_SPI2                 11
+#define DM355_LPSC_RTO                  12
+#define DM355_LPSC_VPSS_DAC             41
+
+/*
+ * LPSC Assignments
+ */
+#define DM646X_LPSC_ARM            0
+#define DM646X_LPSC_C64X_CPU       1
+#define DM646X_LPSC_HDVICP0        2
+#define DM646X_LPSC_HDVICP1        3
+#define DM646X_LPSC_TPCC           4
+#define DM646X_LPSC_TPTC0          5
+#define DM646X_LPSC_TPTC1          6
+#define DM646X_LPSC_TPTC2          7
+#define DM646X_LPSC_TPTC3          8
+#define DM646X_LPSC_PCI            13
+#define DM646X_LPSC_EMAC           14
+#define DM646X_LPSC_VDCE           15
+#define DM646X_LPSC_VPSSMSTR       16
+#define DM646X_LPSC_VPSSSLV        17
+#define DM646X_LPSC_TSIF0          18
+#define DM646X_LPSC_TSIF1          19
+#define DM646X_LPSC_DDR_EMIF       20
+#define DM646X_LPSC_AEMIF          21
+#define DM646X_LPSC_McASP0         22
+#define DM646X_LPSC_McASP1         23
+#define DM646X_LPSC_CRGEN0         24
+#define DM646X_LPSC_CRGEN1         25
+#define DM646X_LPSC_UART0          26
+#define DM646X_LPSC_UART1          27
+#define DM646X_LPSC_UART2          28
+#define DM646X_LPSC_PWM0           29
+#define DM646X_LPSC_PWM1           30
+#define DM646X_LPSC_I2C            31
+#define DM646X_LPSC_SPI            32
+#define DM646X_LPSC_GPIO           33
+#define DM646X_LPSC_TIMER0         34
+#define DM646X_LPSC_TIMER1         35
+#define DM646X_LPSC_ARM_INTC       45
+
+extern int davinci_psc_is_clk_active(unsigned int id);
+extern void davinci_psc_config(unsigned int domain, unsigned int id,
+                               char enable);
+
 #endif /* __ASM_ARCH_PSC_H */
diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c
index 299515f70b8b..71a7ae342b91 100644
--- a/arch/arm/mach-davinci/io.c
+++ b/arch/arm/mach-davinci/io.c
@@ -53,5 +53,4 @@ void __init davinci_map_common_io(void)
 
 void __init davinci_init_common_hw(void)
 {
-        davinci_clk_init();
 }
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index 58754f066d5b..c5098831741f 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -23,6 +23,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 
+#include <mach/cputype.h>
 #include <mach/hardware.h>
 #include <mach/psc.h>
 #include <mach/mux.h>
@@ -36,76 +37,57 @@
 #define MDSTAT          0x800
 #define MDCTL           0xA00
 
-/* System control register offsets */
-#define VDD3P3V_PWDN    0x48
 
-static void davinci_psc_mux(unsigned int id)
+/* Return nonzero iff the domain's clock is active */
+int __init davinci_psc_is_clk_active(unsigned int id)
 {
-        switch (id) {
-        case DAVINCI_LPSC_ATA:
-                davinci_mux_peripheral(DAVINCI_MUX_HDIREN, 1);
-                davinci_mux_peripheral(DAVINCI_MUX_ATAEN, 1);
-                break;
-        case DAVINCI_LPSC_MMC_SD:
-                /* VDD power manupulations are done in U-Boot for CPMAC
-                 * so applies to MMC as well
-                 */
-                /*Set up the pull regiter for MMC */
-                davinci_writel(0, DAVINCI_SYSTEM_MODULE_BASE + VDD3P3V_PWDN);
-                davinci_mux_peripheral(DAVINCI_MUX_MSTK, 0);
-                break;
-        case DAVINCI_LPSC_I2C:
-                davinci_mux_peripheral(DAVINCI_MUX_I2C, 1);
-                break;
-        case DAVINCI_LPSC_McBSP:
-                davinci_mux_peripheral(DAVINCI_MUX_ASP, 1);
-                break;
-        default:
-                break;
-        }
+        void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE);
+        u32 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
+
+        /* if clocked, state can be "Enable" or "SyncReset" */
+        return mdstat & BIT(12);
 }
 
 /* Enable or disable a PSC domain */
 void davinci_psc_config(unsigned int domain, unsigned int id, char enable)
 {
         u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl, mdstat_mask;
+        void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE);
 
-        mdctl = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id);
+        mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
         if (enable)
                 mdctl |= 0x00000003;    /* Enable Module */
         else
-                mdctl &= 0xFFFFFFF2;    /* Disable Module */
-        davinci_writel(mdctl, DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id);
+                mdctl &= 0xFFFFFFE2;    /* Disable Module */
+        __raw_writel(mdctl, psc_base + MDCTL + 4 * id);
 
-        pdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDSTAT);
+        pdstat = __raw_readl(psc_base + PDSTAT);
         if ((pdstat & 0x00000001) == 0) {
-                pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
+                pdctl1 = __raw_readl(psc_base + PDCTL1);
                 pdctl1 |= 0x1;
-                davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
+                __raw_writel(pdctl1, psc_base + PDCTL1);
 
                 ptcmd = 1 << domain;
-                davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD);
+                __raw_writel(ptcmd, psc_base + PTCMD);
 
                 do {
-                        epcpr = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
-                                              EPCPR);
+                        epcpr = __raw_readl(psc_base + EPCPR);
                 } while ((((epcpr >> domain) & 1) == 0));
 
-                pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
+                pdctl1 = __raw_readl(psc_base + PDCTL1);
                 pdctl1 |= 0x100;
-                davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
+                __raw_writel(pdctl1, psc_base + PDCTL1);
 
                 do {
-                        ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
+                        ptstat = __raw_readl(psc_base +
                                                PTSTAT);
                 } while (!(((ptstat >> domain) & 1) == 0));
         } else {
                 ptcmd = 1 << domain;
-                davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD);
+                __raw_writel(ptcmd, psc_base + PTCMD);
 
                 do {
-                        ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
-                                               PTSTAT);
+                        ptstat = __raw_readl(psc_base + PTSTAT);
                 } while (!(((ptstat >> domain) & 1) == 0));
         }
 
@@ -115,23 +97,6 @@ void davinci_psc_config(unsigned int domain, unsigned int id, char enable)
                 mdstat_mask = 0x2;
 
         do {
-                mdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
-                                       MDSTAT + 4 * id);
+                mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
         } while (!((mdstat & 0x0000001F) == mdstat_mask));
-
-        if (enable)
-                davinci_psc_mux(id);
-}
-
-void __init davinci_psc_init(void)
-{
-        davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_VPSSMSTR, 1);
-        davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_VPSSSLV, 1);
-        davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPCC, 1);
-        davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPTC0, 1);
-        davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPTC1, 1);
-        davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_GPIO, 1);
-
-        /* Turn on WatchDog timer LPSC.  Needed for RESET to work */
-        davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TIMER2, 1);
 }