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-rw-r--r--arch/arm/mach-omap2/clock34xx.c268
-rw-r--r--arch/arm/mach-omap2/clock34xx.h513
-rw-r--r--arch/arm/plat-omap/Kconfig1
-rw-r--r--arch/arm/plat-omap/include/mach/clock.h5
4 files changed, 331 insertions, 456 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 52698fb4fd04..2c22750016cc 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -30,6 +30,7 @@
30#include <mach/clock.h> 30#include <mach/clock.h>
31#include <mach/sram.h> 31#include <mach/sram.h>
32#include <asm/div64.h> 32#include <asm/div64.h>
33#include <asm/clkdev.h>
33 34
34#include "memory.h" 35#include "memory.h"
35#include "clock.h" 36#include "clock.h"
@@ -42,6 +43,240 @@ static const struct clkops clkops_noncore_dpll_ops;
42 43
43#include "clock34xx.h" 44#include "clock34xx.h"
44 45
46struct omap_clk {
47 u32 cpu;
48 struct clk_lookup lk;
49};
50
51#define CLK(dev, con, ck, cp) \
52 { \
53 .cpu = cp, \
54 .lk = { \
55 .dev_id = dev, \
56 .con_id = con, \
57 .clk = ck, \
58 }, \
59 }
60
61#define CK_343X (1 << 0)
62#define CK_3430ES1 (1 << 1)
63#define CK_3430ES2 (1 << 2)
64
65static struct omap_clk omap34xx_clks[] = {
66 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X),
67 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X),
68 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X),
69 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
70 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
71 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X),
72 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
73 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X),
74 CLK(NULL, "sys_ck", &sys_ck, CK_343X),
75 CLK(NULL, "sys_altclk", &sys_altclk, CK_343X),
76 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X),
77 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X),
78 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X),
79 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X),
80 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
81 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
82 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
83 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X),
84 CLK(NULL, "core_ck", &core_ck, CK_343X),
85 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X),
86 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X),
87 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
88 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X),
89 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
90 CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
91 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X),
92 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X),
93 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
94 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X),
95 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X),
96 CLK(NULL, "virt_omap_54m_fck", &virt_omap_54m_fck, CK_343X),
97 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X),
98 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X),
99 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X),
100 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X),
101 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
102 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X),
103 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
104 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X),
105 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
106 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X),
107 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
108 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X),
109 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
110 CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
111 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2),
112 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2),
113 CLK(NULL, "omap_120m_fck", &omap_120m_fck, CK_3430ES2),
114 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X),
115 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X),
116 CLK(NULL, "corex2_fck", &corex2_fck, CK_343X),
117 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X),
118 CLK(NULL, "mpu_ck", &mpu_ck, CK_343X),
119 CLK(NULL, "arm_fck", &arm_fck, CK_343X),
120 CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
121 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
122 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
123 CLK(NULL, "l3_ick", &l3_ick, CK_343X),
124 CLK(NULL, "l4_ick", &l4_ick, CK_343X),
125 CLK(NULL, "rm_ick", &rm_ick, CK_343X),
126 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
127 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
128 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
129 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
130 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
131 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2),
132 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2),
133 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
134 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X),
135 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X),
136 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2),
137 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2),
138 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2),
139 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X),
140 CLK("mmci-omap-hs.2", "mmchs_fck", &mmchs3_fck, CK_3430ES2),
141 CLK("mmci-omap-hs.1", "mmchs_fck", &mmchs2_fck, CK_343X),
142 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
143 CLK("mmci-omap-hs.0", "mmchs_fck", &mmchs1_fck, CK_343X),
144 CLK("i2c_omap.3", "i2c_fck", &i2c3_fck, CK_343X),
145 CLK("i2c_omap.2", "i2c_fck", &i2c2_fck, CK_343X),
146 CLK("i2c_omap.1", "i2c_fck", &i2c1_fck, CK_343X),
147 CLK("omap-mcbsp.5", "mcbsp_fck", &mcbsp5_fck, CK_343X),
148 CLK("omap-mcbsp.1", "mcbsp_fck", &mcbsp1_fck, CK_343X),
149 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X),
150 CLK("omap2_mcspi.4", "mcspi_fck", &mcspi4_fck, CK_343X),
151 CLK("omap2_mcspi.3", "mcspi_fck", &mcspi3_fck, CK_343X),
152 CLK("omap2_mcspi.2", "mcspi_fck", &mcspi2_fck, CK_343X),
153 CLK("omap2_mcspi.1", "mcspi_fck", &mcspi1_fck, CK_343X),
154 CLK(NULL, "uart2_fck", &uart2_fck, CK_343X),
155 CLK(NULL, "uart1_fck", &uart1_fck, CK_343X),
156 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
157 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X),
158 CLK(NULL, "hdq_fck", &hdq_fck, CK_343X),
159 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X),
160 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X),
161 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
162 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick, CK_343X),
163 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
164 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
165 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
166 CLK(NULL, "pka_ick", &pka_ick, CK_343X),
167 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X),
168 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2),
169 CLK("mmci-omap-hs.2", "mmchs_ick", &mmchs3_ick, CK_3430ES2),
170 CLK(NULL, "icr_ick", &icr_ick, CK_343X),
171 CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
172 CLK(NULL, "sha12_ick", &sha12_ick, CK_343X),
173 CLK(NULL, "des2_ick", &des2_ick, CK_343X),
174 CLK("mmci-omap-hs.1", "mmchs_ick", &mmchs2_ick, CK_343X),
175 CLK("mmci-omap-hs.0", "mmchs_ick", &mmchs1_ick, CK_343X),
176 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
177 CLK(NULL, "hdq_ick", &hdq_ick, CK_343X),
178 CLK("omap2_mcspi.4", "mcspi_ick", &mcspi4_ick, CK_343X),
179 CLK("omap2_mcspi.3", "mcspi_ick", &mcspi3_ick, CK_343X),
180 CLK("omap2_mcspi.2", "mcspi_ick", &mcspi2_ick, CK_343X),
181 CLK("omap2_mcspi.1", "mcspi_ick", &mcspi1_ick, CK_343X),
182 CLK("i2c_omap.3", "i2c_ick", &i2c3_ick, CK_343X),
183 CLK("i2c_omap.2", "i2c_ick", &i2c2_ick, CK_343X),
184 CLK("i2c_omap.1", "i2c_ick", &i2c1_ick, CK_343X),
185 CLK(NULL, "uart2_ick", &uart2_ick, CK_343X),
186 CLK(NULL, "uart1_ick", &uart1_ick, CK_343X),
187 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X),
188 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X),
189 CLK("omap-mcbsp.5", "mcbsp_ick", &mcbsp5_ick, CK_343X),
190 CLK("omap-mcbsp.1", "mcbsp_ick", &mcbsp1_ick, CK_343X),
191 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
192 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
193 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X),
194 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
195 CLK(NULL, "ssi_ick", &ssi_ick, CK_343X),
196 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
197 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
198 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
199 CLK(NULL, "rng_ick", &rng_ick, CK_343X),
200 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
201 CLK(NULL, "des1_ick", &des1_ick, CK_343X),
202 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck, CK_343X),
203 CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_343X),
204 CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_343X),
205 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_343X),
206 CLK(NULL, "dss_ick", &dss_ick, CK_343X),
207 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
208 CLK(NULL, "cam_ick", &cam_ick, CK_343X),
209 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
210 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
211 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2),
212 CLK(NULL, "usbhost_sar_fck", &usbhost_sar_fck, CK_3430ES2),
213 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
214 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X),
215 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X),
216 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X),
217 CLK(NULL, "wdt2_fck", &wdt2_fck, CK_343X),
218 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
219 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
220 CLK(NULL, "wdt2_ick", &wdt2_ick, CK_343X),
221 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X),
222 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X),
223 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
224 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X),
225 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X),
226 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X),
227 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X),
228 CLK(NULL, "uart3_fck", &uart3_fck, CK_343X),
229 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X),
230 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X),
231 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X),
232 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X),
233 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X),
234 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X),
235 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X),
236 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X),
237 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
238 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X),
239 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X),
240 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X),
241 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X),
242 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X),
243 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X),
244 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X),
245 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X),
246 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X),
247 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X),
248 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X),
249 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X),
250 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X),
251 CLK(NULL, "uart3_ick", &uart3_ick, CK_343X),
252 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X),
253 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X),
254 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X),
255 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X),
256 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X),
257 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X),
258 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X),
259 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X),
260 CLK("omap-mcbsp.2", "mcbsp_ick", &mcbsp2_ick, CK_343X),
261 CLK("omap-mcbsp.3", "mcbsp_ick", &mcbsp3_ick, CK_343X),
262 CLK("omap-mcbsp.4", "mcbsp_ick", &mcbsp4_ick, CK_343X),
263 CLK("omap-mcbsp.2", "mcbsp_fck", &mcbsp2_fck, CK_343X),
264 CLK("omap-mcbsp.3", "mcbsp_fck", &mcbsp3_fck, CK_343X),
265 CLK("omap-mcbsp.4", "mcbsp_fck", &mcbsp4_fck, CK_343X),
266 CLK(NULL, "emu_src_ck", &emu_src_ck, CK_343X),
267 CLK(NULL, "pclk_fck", &pclk_fck, CK_343X),
268 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X),
269 CLK(NULL, "atclk_fck", &atclk_fck, CK_343X),
270 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X),
271 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X),
272 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
273 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
274 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
275 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X),
276 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X),
277 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X),
278};
279
45/* CM_AUTOIDLE_PLL*.AUTO_* bit values */ 280/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
46#define DPLL_AUTOIDLE_DISABLE 0x0 281#define DPLL_AUTOIDLE_DISABLE 0x0
47#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 282#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
@@ -453,26 +688,13 @@ arch_initcall(omap2_clk_arch_init);
453int __init omap2_clk_init(void) 688int __init omap2_clk_init(void)
454{ 689{
455 /* struct prcm_config *prcm; */ 690 /* struct prcm_config *prcm; */
456 struct clk **clkp; 691 struct omap_clk *c;
457 /* u32 clkrate; */ 692 /* u32 clkrate; */
458 u32 cpu_clkflg; 693 u32 cpu_clkflg;
459 694
460 /* REVISIT: Ultimately this will be used for multiboot */
461#if 0
462 if (cpu_is_omap242x()) {
463 cpu_mask = RATE_IN_242X;
464 cpu_clkflg = CLOCK_IN_OMAP242X;
465 clkp = onchip_24xx_clks;
466 } else if (cpu_is_omap2430()) {
467 cpu_mask = RATE_IN_243X;
468 cpu_clkflg = CLOCK_IN_OMAP243X;
469 clkp = onchip_24xx_clks;
470 }
471#endif
472 if (cpu_is_omap34xx()) { 695 if (cpu_is_omap34xx()) {
473 cpu_mask = RATE_IN_343X; 696 cpu_mask = RATE_IN_343X;
474 cpu_clkflg = CLOCK_IN_OMAP343X; 697 cpu_clkflg = CK_343X;
475 clkp = onchip_34xx_clks;
476 698
477 /* 699 /*
478 * Update this if there are further clock changes between ES2 700 * Update this if there are further clock changes between ES2
@@ -480,23 +702,21 @@ int __init omap2_clk_init(void)
480 */ 702 */
481 if (omap_rev() == OMAP3430_REV_ES1_0) { 703 if (omap_rev() == OMAP3430_REV_ES1_0) {
482 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ 704 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
483 cpu_clkflg |= CLOCK_IN_OMAP3430ES1; 705 cpu_clkflg |= CK_3430ES1;
484 } else { 706 } else {
485 cpu_mask |= RATE_IN_3430ES2; 707 cpu_mask |= RATE_IN_3430ES2;
486 cpu_clkflg |= CLOCK_IN_OMAP3430ES2; 708 cpu_clkflg |= CK_3430ES2;
487 } 709 }
488 } 710 }
489 711
490 clk_init(&omap2_clk_functions); 712 clk_init(&omap2_clk_functions);
491 713
492 for (clkp = onchip_34xx_clks; 714 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
493 clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks); 715 if (c->cpu & cpu_clkflg) {
494 clkp++) { 716 clkdev_add(&c->lk);
495 if ((*clkp)->flags & cpu_clkflg) { 717 clk_register(c->lk.clk);
496 clk_register(*clkp); 718 omap2_init_clk_clkdm(c->lk.clk);
497 omap2_init_clk_clkdm(*clkp);
498 } 719 }
499 }
500 720
501 /* REVISIT: Not yet ready for OMAP3 */ 721 /* REVISIT: Not yet ready for OMAP3 */
502#if 0 722#if 0
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index dcacec84f8ca..6bd8c6d5a4e7 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -57,14 +57,14 @@ static struct clk omap_32k_fck = {
57 .name = "omap_32k_fck", 57 .name = "omap_32k_fck",
58 .ops = &clkops_null, 58 .ops = &clkops_null,
59 .rate = 32768, 59 .rate = 32768,
60 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, 60 .flags = RATE_FIXED | RATE_PROPAGATES,
61}; 61};
62 62
63static struct clk secure_32k_fck = { 63static struct clk secure_32k_fck = {
64 .name = "secure_32k_fck", 64 .name = "secure_32k_fck",
65 .ops = &clkops_null, 65 .ops = &clkops_null,
66 .rate = 32768, 66 .rate = 32768,
67 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, 67 .flags = RATE_FIXED | RATE_PROPAGATES,
68}; 68};
69 69
70/* Virtual source clocks for osc_sys_ck */ 70/* Virtual source clocks for osc_sys_ck */
@@ -72,42 +72,42 @@ static struct clk virt_12m_ck = {
72 .name = "virt_12m_ck", 72 .name = "virt_12m_ck",
73 .ops = &clkops_null, 73 .ops = &clkops_null,
74 .rate = 12000000, 74 .rate = 12000000,
75 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, 75 .flags = RATE_FIXED | RATE_PROPAGATES,
76}; 76};
77 77
78static struct clk virt_13m_ck = { 78static struct clk virt_13m_ck = {
79 .name = "virt_13m_ck", 79 .name = "virt_13m_ck",
80 .ops = &clkops_null, 80 .ops = &clkops_null,
81 .rate = 13000000, 81 .rate = 13000000,
82 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, 82 .flags = RATE_FIXED | RATE_PROPAGATES,
83}; 83};
84 84
85static struct clk virt_16_8m_ck = { 85static struct clk virt_16_8m_ck = {
86 .name = "virt_16_8m_ck", 86 .name = "virt_16_8m_ck",
87 .ops = &clkops_null, 87 .ops = &clkops_null,
88 .rate = 16800000, 88 .rate = 16800000,
89 .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES, 89 .flags = RATE_FIXED | RATE_PROPAGATES,
90}; 90};
91 91
92static struct clk virt_19_2m_ck = { 92static struct clk virt_19_2m_ck = {
93 .name = "virt_19_2m_ck", 93 .name = "virt_19_2m_ck",
94 .ops = &clkops_null, 94 .ops = &clkops_null,
95 .rate = 19200000, 95 .rate = 19200000,
96 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, 96 .flags = RATE_FIXED | RATE_PROPAGATES,
97}; 97};
98 98
99static struct clk virt_26m_ck = { 99static struct clk virt_26m_ck = {
100 .name = "virt_26m_ck", 100 .name = "virt_26m_ck",
101 .ops = &clkops_null, 101 .ops = &clkops_null,
102 .rate = 26000000, 102 .rate = 26000000,
103 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, 103 .flags = RATE_FIXED | RATE_PROPAGATES,
104}; 104};
105 105
106static struct clk virt_38_4m_ck = { 106static struct clk virt_38_4m_ck = {
107 .name = "virt_38_4m_ck", 107 .name = "virt_38_4m_ck",
108 .ops = &clkops_null, 108 .ops = &clkops_null,
109 .rate = 38400000, 109 .rate = 38400000,
110 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, 110 .flags = RATE_FIXED | RATE_PROPAGATES,
111}; 111};
112 112
113static const struct clksel_rate osc_sys_12m_rates[] = { 113static const struct clksel_rate osc_sys_12m_rates[] = {
@@ -160,7 +160,7 @@ static struct clk osc_sys_ck = {
160 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, 160 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
161 .clksel = osc_sys_clksel, 161 .clksel = osc_sys_clksel,
162 /* REVISIT: deal with autoextclkmode? */ 162 /* REVISIT: deal with autoextclkmode? */
163 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, 163 .flags = RATE_FIXED | RATE_PROPAGATES,
164 .recalc = &omap2_clksel_recalc, 164 .recalc = &omap2_clksel_recalc,
165}; 165};
166 166
@@ -185,21 +185,21 @@ static struct clk sys_ck = {
185 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, 185 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
186 .clksel_mask = OMAP_SYSCLKDIV_MASK, 186 .clksel_mask = OMAP_SYSCLKDIV_MASK,
187 .clksel = sys_clksel, 187 .clksel = sys_clksel,
188 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 188 .flags = RATE_PROPAGATES,
189 .recalc = &omap2_clksel_recalc, 189 .recalc = &omap2_clksel_recalc,
190}; 190};
191 191
192static struct clk sys_altclk = { 192static struct clk sys_altclk = {
193 .name = "sys_altclk", 193 .name = "sys_altclk",
194 .ops = &clkops_null, 194 .ops = &clkops_null,
195 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 195 .flags = RATE_PROPAGATES,
196}; 196};
197 197
198/* Optional external clock input for some McBSPs */ 198/* Optional external clock input for some McBSPs */
199static struct clk mcbsp_clks = { 199static struct clk mcbsp_clks = {
200 .name = "mcbsp_clks", 200 .name = "mcbsp_clks",
201 .ops = &clkops_null, 201 .ops = &clkops_null,
202 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 202 .flags = RATE_PROPAGATES,
203}; 203};
204 204
205/* PRM EXTERNAL CLOCK OUTPUT */ 205/* PRM EXTERNAL CLOCK OUTPUT */
@@ -210,7 +210,6 @@ static struct clk sys_clkout1 = {
210 .parent = &osc_sys_ck, 210 .parent = &osc_sys_ck,
211 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, 211 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
212 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, 212 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
213 .flags = CLOCK_IN_OMAP343X,
214 .recalc = &followparent_recalc, 213 .recalc = &followparent_recalc,
215}; 214};
216 215
@@ -275,7 +274,7 @@ static struct clk dpll1_ck = {
275 .ops = &clkops_null, 274 .ops = &clkops_null,
276 .parent = &sys_ck, 275 .parent = &sys_ck,
277 .dpll_data = &dpll1_dd, 276 .dpll_data = &dpll1_dd,
278 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 277 .flags = RATE_PROPAGATES,
279 .round_rate = &omap2_dpll_round_rate, 278 .round_rate = &omap2_dpll_round_rate,
280 .recalc = &omap3_dpll_recalc, 279 .recalc = &omap3_dpll_recalc,
281}; 280};
@@ -288,7 +287,7 @@ static struct clk dpll1_x2_ck = {
288 .name = "dpll1_x2_ck", 287 .name = "dpll1_x2_ck",
289 .ops = &clkops_null, 288 .ops = &clkops_null,
290 .parent = &dpll1_ck, 289 .parent = &dpll1_ck,
291 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 290 .flags = RATE_PROPAGATES,
292 .recalc = &omap3_clkoutx2_recalc, 291 .recalc = &omap3_clkoutx2_recalc,
293}; 292};
294 293
@@ -310,7 +309,7 @@ static struct clk dpll1_x2m2_ck = {
310 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), 309 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
311 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, 310 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
312 .clksel = div16_dpll1_x2m2_clksel, 311 .clksel = div16_dpll1_x2m2_clksel,
313 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 312 .flags = RATE_PROPAGATES,
314 .recalc = &omap2_clksel_recalc, 313 .recalc = &omap2_clksel_recalc,
315}; 314};
316 315
@@ -343,7 +342,7 @@ static struct clk dpll2_ck = {
343 .ops = &clkops_noncore_dpll_ops, 342 .ops = &clkops_noncore_dpll_ops,
344 .parent = &sys_ck, 343 .parent = &sys_ck,
345 .dpll_data = &dpll2_dd, 344 .dpll_data = &dpll2_dd,
346 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 345 .flags = RATE_PROPAGATES,
347 .round_rate = &omap2_dpll_round_rate, 346 .round_rate = &omap2_dpll_round_rate,
348 .recalc = &omap3_dpll_recalc, 347 .recalc = &omap3_dpll_recalc,
349}; 348};
@@ -366,7 +365,7 @@ static struct clk dpll2_m2_ck = {
366 OMAP3430_CM_CLKSEL2_PLL), 365 OMAP3430_CM_CLKSEL2_PLL),
367 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, 366 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
368 .clksel = div16_dpll2_m2x2_clksel, 367 .clksel = div16_dpll2_m2x2_clksel,
369 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 368 .flags = RATE_PROPAGATES,
370 .recalc = &omap2_clksel_recalc, 369 .recalc = &omap2_clksel_recalc,
371}; 370};
372 371
@@ -396,7 +395,7 @@ static struct clk dpll3_ck = {
396 .ops = &clkops_null, 395 .ops = &clkops_null,
397 .parent = &sys_ck, 396 .parent = &sys_ck,
398 .dpll_data = &dpll3_dd, 397 .dpll_data = &dpll3_dd,
399 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 398 .flags = RATE_PROPAGATES,
400 .round_rate = &omap2_dpll_round_rate, 399 .round_rate = &omap2_dpll_round_rate,
401 .recalc = &omap3_dpll_recalc, 400 .recalc = &omap3_dpll_recalc,
402}; 401};
@@ -409,7 +408,7 @@ static struct clk dpll3_x2_ck = {
409 .name = "dpll3_x2_ck", 408 .name = "dpll3_x2_ck",
410 .ops = &clkops_null, 409 .ops = &clkops_null,
411 .parent = &dpll3_ck, 410 .parent = &dpll3_ck,
412 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 411 .flags = RATE_PROPAGATES,
413 .recalc = &omap3_clkoutx2_recalc, 412 .recalc = &omap3_clkoutx2_recalc,
414}; 413};
415 414
@@ -466,7 +465,7 @@ static struct clk dpll3_m2_ck = {
466 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 465 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
467 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, 466 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
468 .clksel = div31_dpll3m2_clksel, 467 .clksel = div31_dpll3m2_clksel,
469 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 468 .flags = RATE_PROPAGATES,
470 .recalc = &omap2_clksel_recalc, 469 .recalc = &omap2_clksel_recalc,
471}; 470};
472 471
@@ -483,7 +482,7 @@ static struct clk core_ck = {
483 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 482 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
484 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, 483 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
485 .clksel = core_ck_clksel, 484 .clksel = core_ck_clksel,
486 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 485 .flags = RATE_PROPAGATES,
487 .recalc = &omap2_clksel_recalc, 486 .recalc = &omap2_clksel_recalc,
488}; 487};
489 488
@@ -500,7 +499,7 @@ static struct clk dpll3_m2x2_ck = {
500 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 499 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
501 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, 500 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
502 .clksel = dpll3_m2x2_ck_clksel, 501 .clksel = dpll3_m2x2_ck_clksel,
503 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 502 .flags = RATE_PROPAGATES,
504 .recalc = &omap2_clksel_recalc, 503 .recalc = &omap2_clksel_recalc,
505}; 504};
506 505
@@ -519,7 +518,7 @@ static struct clk dpll3_m3_ck = {
519 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 518 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
520 .clksel_mask = OMAP3430_DIV_DPLL3_MASK, 519 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
521 .clksel = div16_dpll3_clksel, 520 .clksel = div16_dpll3_clksel,
522 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 521 .flags = RATE_PROPAGATES,
523 .recalc = &omap2_clksel_recalc, 522 .recalc = &omap2_clksel_recalc,
524}; 523};
525 524
@@ -530,7 +529,7 @@ static struct clk dpll3_m3x2_ck = {
530 .parent = &dpll3_m3_ck, 529 .parent = &dpll3_m3_ck,
531 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 530 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
532 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, 531 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
533 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 532 .flags = RATE_PROPAGATES | INVERT_ENABLE,
534 .recalc = &omap3_clkoutx2_recalc, 533 .recalc = &omap3_clkoutx2_recalc,
535}; 534};
536 535
@@ -548,7 +547,7 @@ static struct clk emu_core_alwon_ck = {
548 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 547 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
549 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, 548 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
550 .clksel = emu_core_alwon_ck_clksel, 549 .clksel = emu_core_alwon_ck_clksel,
551 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 550 .flags = RATE_PROPAGATES,
552 .recalc = &omap2_clksel_recalc, 551 .recalc = &omap2_clksel_recalc,
553}; 552};
554 553
@@ -579,7 +578,7 @@ static struct clk dpll4_ck = {
579 .ops = &clkops_noncore_dpll_ops, 578 .ops = &clkops_noncore_dpll_ops,
580 .parent = &sys_ck, 579 .parent = &sys_ck,
581 .dpll_data = &dpll4_dd, 580 .dpll_data = &dpll4_dd,
582 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 581 .flags = RATE_PROPAGATES,
583 .round_rate = &omap2_dpll_round_rate, 582 .round_rate = &omap2_dpll_round_rate,
584 .recalc = &omap3_dpll_recalc, 583 .recalc = &omap3_dpll_recalc,
585}; 584};
@@ -593,7 +592,7 @@ static struct clk dpll4_x2_ck = {
593 .name = "dpll4_x2_ck", 592 .name = "dpll4_x2_ck",
594 .ops = &clkops_null, 593 .ops = &clkops_null,
595 .parent = &dpll4_ck, 594 .parent = &dpll4_ck,
596 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 595 .flags = RATE_PROPAGATES,
597 .recalc = &omap3_clkoutx2_recalc, 596 .recalc = &omap3_clkoutx2_recalc,
598}; 597};
599 598
@@ -611,7 +610,7 @@ static struct clk dpll4_m2_ck = {
611 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), 610 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
612 .clksel_mask = OMAP3430_DIV_96M_MASK, 611 .clksel_mask = OMAP3430_DIV_96M_MASK,
613 .clksel = div16_dpll4_clksel, 612 .clksel = div16_dpll4_clksel,
614 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 613 .flags = RATE_PROPAGATES,
615 .recalc = &omap2_clksel_recalc, 614 .recalc = &omap2_clksel_recalc,
616}; 615};
617 616
@@ -622,7 +621,7 @@ static struct clk dpll4_m2x2_ck = {
622 .parent = &dpll4_m2_ck, 621 .parent = &dpll4_m2_ck,
623 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 622 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
624 .enable_bit = OMAP3430_PWRDN_96M_SHIFT, 623 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
625 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 624 .flags = RATE_PROPAGATES | INVERT_ENABLE,
626 .recalc = &omap3_clkoutx2_recalc, 625 .recalc = &omap3_clkoutx2_recalc,
627}; 626};
628 627
@@ -640,7 +639,7 @@ static struct clk omap_96m_alwon_fck = {
640 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 639 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
641 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, 640 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
642 .clksel = omap_96m_alwon_fck_clksel, 641 .clksel = omap_96m_alwon_fck_clksel,
643 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 642 .flags = RATE_PROPAGATES,
644 .recalc = &omap2_clksel_recalc, 643 .recalc = &omap2_clksel_recalc,
645}; 644};
646 645
@@ -648,7 +647,7 @@ static struct clk omap_96m_fck = {
648 .name = "omap_96m_fck", 647 .name = "omap_96m_fck",
649 .ops = &clkops_null, 648 .ops = &clkops_null,
650 .parent = &omap_96m_alwon_fck, 649 .parent = &omap_96m_alwon_fck,
651 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 650 .flags = RATE_PROPAGATES,
652 .recalc = &followparent_recalc, 651 .recalc = &followparent_recalc,
653}; 652};
654 653
@@ -666,7 +665,7 @@ static struct clk cm_96m_fck = {
666 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 665 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
667 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, 666 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
668 .clksel = cm_96m_fck_clksel, 667 .clksel = cm_96m_fck_clksel,
669 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 668 .flags = RATE_PROPAGATES,
670 .recalc = &omap2_clksel_recalc, 669 .recalc = &omap2_clksel_recalc,
671}; 670};
672 671
@@ -679,7 +678,7 @@ static struct clk dpll4_m3_ck = {
679 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), 678 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
680 .clksel_mask = OMAP3430_CLKSEL_TV_MASK, 679 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
681 .clksel = div16_dpll4_clksel, 680 .clksel = div16_dpll4_clksel,
682 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 681 .flags = RATE_PROPAGATES,
683 .recalc = &omap2_clksel_recalc, 682 .recalc = &omap2_clksel_recalc,
684}; 683};
685 684
@@ -691,7 +690,7 @@ static struct clk dpll4_m3x2_ck = {
691 .init = &omap2_init_clksel_parent, 690 .init = &omap2_init_clksel_parent,
692 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 691 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
693 .enable_bit = OMAP3430_PWRDN_TV_SHIFT, 692 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
694 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 693 .flags = RATE_PROPAGATES | INVERT_ENABLE,
695 .recalc = &omap3_clkoutx2_recalc, 694 .recalc = &omap3_clkoutx2_recalc,
696}; 695};
697 696
@@ -709,7 +708,7 @@ static struct clk virt_omap_54m_fck = {
709 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 708 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
710 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, 709 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
711 .clksel = virt_omap_54m_fck_clksel, 710 .clksel = virt_omap_54m_fck_clksel,
712 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 711 .flags = RATE_PROPAGATES,
713 .recalc = &omap2_clksel_recalc, 712 .recalc = &omap2_clksel_recalc,
714}; 713};
715 714
@@ -736,7 +735,7 @@ static struct clk omap_54m_fck = {
736 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 735 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
737 .clksel_mask = OMAP3430_SOURCE_54M, 736 .clksel_mask = OMAP3430_SOURCE_54M,
738 .clksel = omap_54m_clksel, 737 .clksel = omap_54m_clksel,
739 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 738 .flags = RATE_PROPAGATES,
740 .recalc = &omap2_clksel_recalc, 739 .recalc = &omap2_clksel_recalc,
741}; 740};
742 741
@@ -763,7 +762,7 @@ static struct clk omap_48m_fck = {
763 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 762 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
764 .clksel_mask = OMAP3430_SOURCE_48M, 763 .clksel_mask = OMAP3430_SOURCE_48M,
765 .clksel = omap_48m_clksel, 764 .clksel = omap_48m_clksel,
766 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 765 .flags = RATE_PROPAGATES,
767 .recalc = &omap2_clksel_recalc, 766 .recalc = &omap2_clksel_recalc,
768}; 767};
769 768
@@ -772,7 +771,7 @@ static struct clk omap_12m_fck = {
772 .ops = &clkops_null, 771 .ops = &clkops_null,
773 .parent = &omap_48m_fck, 772 .parent = &omap_48m_fck,
774 .fixed_div = 4, 773 .fixed_div = 4,
775 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 774 .flags = RATE_PROPAGATES,
776 .recalc = &omap2_fixed_divisor_recalc, 775 .recalc = &omap2_fixed_divisor_recalc,
777}; 776};
778 777
@@ -785,7 +784,7 @@ static struct clk dpll4_m4_ck = {
785 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), 784 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
786 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, 785 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
787 .clksel = div16_dpll4_clksel, 786 .clksel = div16_dpll4_clksel,
788 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 787 .flags = RATE_PROPAGATES,
789 .recalc = &omap2_clksel_recalc, 788 .recalc = &omap2_clksel_recalc,
790}; 789};
791 790
@@ -796,7 +795,7 @@ static struct clk dpll4_m4x2_ck = {
796 .parent = &dpll4_m4_ck, 795 .parent = &dpll4_m4_ck,
797 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 796 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
798 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, 797 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
799 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 798 .flags = RATE_PROPAGATES | INVERT_ENABLE,
800 .recalc = &omap3_clkoutx2_recalc, 799 .recalc = &omap3_clkoutx2_recalc,
801}; 800};
802 801
@@ -809,7 +808,7 @@ static struct clk dpll4_m5_ck = {
809 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), 808 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
810 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, 809 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
811 .clksel = div16_dpll4_clksel, 810 .clksel = div16_dpll4_clksel,
812 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 811 .flags = RATE_PROPAGATES,
813 .recalc = &omap2_clksel_recalc, 812 .recalc = &omap2_clksel_recalc,
814}; 813};
815 814
@@ -820,7 +819,7 @@ static struct clk dpll4_m5x2_ck = {
820 .parent = &dpll4_m5_ck, 819 .parent = &dpll4_m5_ck,
821 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 820 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
822 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, 821 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
823 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 822 .flags = RATE_PROPAGATES | INVERT_ENABLE,
824 .recalc = &omap3_clkoutx2_recalc, 823 .recalc = &omap3_clkoutx2_recalc,
825}; 824};
826 825
@@ -833,7 +832,7 @@ static struct clk dpll4_m6_ck = {
833 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 832 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
834 .clksel_mask = OMAP3430_DIV_DPLL4_MASK, 833 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
835 .clksel = div16_dpll4_clksel, 834 .clksel = div16_dpll4_clksel,
836 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 835 .flags = RATE_PROPAGATES,
837 .recalc = &omap2_clksel_recalc, 836 .recalc = &omap2_clksel_recalc,
838}; 837};
839 838
@@ -845,7 +844,7 @@ static struct clk dpll4_m6x2_ck = {
845 .init = &omap2_init_clksel_parent, 844 .init = &omap2_init_clksel_parent,
846 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 845 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
847 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, 846 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
848 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 847 .flags = RATE_PROPAGATES | INVERT_ENABLE,
849 .recalc = &omap3_clkoutx2_recalc, 848 .recalc = &omap3_clkoutx2_recalc,
850}; 849};
851 850
@@ -853,7 +852,7 @@ static struct clk emu_per_alwon_ck = {
853 .name = "emu_per_alwon_ck", 852 .name = "emu_per_alwon_ck",
854 .ops = &clkops_null, 853 .ops = &clkops_null,
855 .parent = &dpll4_m6x2_ck, 854 .parent = &dpll4_m6x2_ck,
856 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 855 .flags = RATE_PROPAGATES,
857 .recalc = &followparent_recalc, 856 .recalc = &followparent_recalc,
858}; 857};
859 858
@@ -885,7 +884,7 @@ static struct clk dpll5_ck = {
885 .ops = &clkops_noncore_dpll_ops, 884 .ops = &clkops_noncore_dpll_ops,
886 .parent = &sys_ck, 885 .parent = &sys_ck,
887 .dpll_data = &dpll5_dd, 886 .dpll_data = &dpll5_dd,
888 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, 887 .flags = RATE_PROPAGATES,
889 .round_rate = &omap2_dpll_round_rate, 888 .round_rate = &omap2_dpll_round_rate,
890 .recalc = &omap3_dpll_recalc, 889 .recalc = &omap3_dpll_recalc,
891}; 890};
@@ -903,7 +902,7 @@ static struct clk dpll5_m2_ck = {
903 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), 902 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
904 .clksel_mask = OMAP3430ES2_DIV_120M_MASK, 903 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
905 .clksel = div16_dpll5_clksel, 904 .clksel = div16_dpll5_clksel,
906 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, 905 .flags = RATE_PROPAGATES,
907 .recalc = &omap2_clksel_recalc, 906 .recalc = &omap2_clksel_recalc,
908}; 907};
909 908
@@ -921,7 +920,7 @@ static struct clk omap_120m_fck = {
921 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), 920 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
922 .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, 921 .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
923 .clksel = omap_120m_fck_clksel, 922 .clksel = omap_120m_fck_clksel,
924 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, 923 .flags = RATE_PROPAGATES,
925 .recalc = &omap2_clksel_recalc, 924 .recalc = &omap2_clksel_recalc,
926}; 925};
927 926
@@ -964,7 +963,7 @@ static struct clk clkout2_src_ck = {
964 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, 963 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
965 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, 964 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
966 .clksel = clkout2_src_clksel, 965 .clksel = clkout2_src_clksel,
967 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 966 .flags = RATE_PROPAGATES,
968 .recalc = &omap2_clksel_recalc, 967 .recalc = &omap2_clksel_recalc,
969}; 968};
970 969
@@ -989,7 +988,6 @@ static struct clk sys_clkout2 = {
989 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, 988 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
990 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, 989 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
991 .clksel = sys_clkout2_clksel, 990 .clksel = sys_clkout2_clksel,
992 .flags = CLOCK_IN_OMAP343X,
993 .recalc = &omap2_clksel_recalc, 991 .recalc = &omap2_clksel_recalc,
994}; 992};
995 993
@@ -999,7 +997,7 @@ static struct clk corex2_fck = {
999 .name = "corex2_fck", 997 .name = "corex2_fck",
1000 .ops = &clkops_null, 998 .ops = &clkops_null,
1001 .parent = &dpll3_m2x2_ck, 999 .parent = &dpll3_m2x2_ck,
1002 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1000 .flags = RATE_PROPAGATES,
1003 .recalc = &followparent_recalc, 1001 .recalc = &followparent_recalc,
1004}; 1002};
1005 1003
@@ -1022,7 +1020,7 @@ static struct clk dpll1_fck = {
1022 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), 1020 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1023 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, 1021 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1024 .clksel = div2_core_clksel, 1022 .clksel = div2_core_clksel,
1025 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1023 .flags = RATE_PROPAGATES,
1026 .recalc = &omap2_clksel_recalc, 1024 .recalc = &omap2_clksel_recalc,
1027}; 1025};
1028 1026
@@ -1046,7 +1044,7 @@ static struct clk mpu_ck = {
1046 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), 1044 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1047 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, 1045 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1048 .clksel = mpu_clksel, 1046 .clksel = mpu_clksel,
1049 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1047 .flags = RATE_PROPAGATES,
1050 .clkdm_name = "mpu_clkdm", 1048 .clkdm_name = "mpu_clkdm",
1051 .recalc = &omap2_clksel_recalc, 1049 .recalc = &omap2_clksel_recalc,
1052}; 1050};
@@ -1071,7 +1069,7 @@ static struct clk arm_fck = {
1071 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), 1069 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1072 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, 1070 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1073 .clksel = arm_fck_clksel, 1071 .clksel = arm_fck_clksel,
1074 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1072 .flags = RATE_PROPAGATES,
1075 .recalc = &omap2_clksel_recalc, 1073 .recalc = &omap2_clksel_recalc,
1076}; 1074};
1077 1075
@@ -1085,7 +1083,7 @@ static struct clk emu_mpu_alwon_ck = {
1085 .name = "emu_mpu_alwon_ck", 1083 .name = "emu_mpu_alwon_ck",
1086 .ops = &clkops_null, 1084 .ops = &clkops_null,
1087 .parent = &mpu_ck, 1085 .parent = &mpu_ck,
1088 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1086 .flags = RATE_PROPAGATES,
1089 .recalc = &followparent_recalc, 1087 .recalc = &followparent_recalc,
1090}; 1088};
1091 1089
@@ -1097,7 +1095,7 @@ static struct clk dpll2_fck = {
1097 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), 1095 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1098 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, 1096 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1099 .clksel = div2_core_clksel, 1097 .clksel = div2_core_clksel,
1100 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1098 .flags = RATE_PROPAGATES,
1101 .recalc = &omap2_clksel_recalc, 1099 .recalc = &omap2_clksel_recalc,
1102}; 1100};
1103 1101
@@ -1125,7 +1123,7 @@ static struct clk iva2_ck = {
1125 OMAP3430_CM_IDLEST_PLL), 1123 OMAP3430_CM_IDLEST_PLL),
1126 .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK, 1124 .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK,
1127 .clksel = iva2_clksel, 1125 .clksel = iva2_clksel,
1128 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1126 .flags = RATE_PROPAGATES,
1129 .clkdm_name = "iva2_clkdm", 1127 .clkdm_name = "iva2_clkdm",
1130 .recalc = &omap2_clksel_recalc, 1128 .recalc = &omap2_clksel_recalc,
1131}; 1129};
@@ -1140,7 +1138,7 @@ static struct clk l3_ick = {
1140 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1138 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1141 .clksel_mask = OMAP3430_CLKSEL_L3_MASK, 1139 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1142 .clksel = div2_core_clksel, 1140 .clksel = div2_core_clksel,
1143 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1141 .flags = RATE_PROPAGATES,
1144 .clkdm_name = "core_l3_clkdm", 1142 .clkdm_name = "core_l3_clkdm",
1145 .recalc = &omap2_clksel_recalc, 1143 .recalc = &omap2_clksel_recalc,
1146}; 1144};
@@ -1158,7 +1156,7 @@ static struct clk l4_ick = {
1158 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1156 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1159 .clksel_mask = OMAP3430_CLKSEL_L4_MASK, 1157 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1160 .clksel = div2_l3_clksel, 1158 .clksel = div2_l3_clksel,
1161 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1159 .flags = RATE_PROPAGATES,
1162 .clkdm_name = "core_l4_clkdm", 1160 .clkdm_name = "core_l4_clkdm",
1163 .recalc = &omap2_clksel_recalc, 1161 .recalc = &omap2_clksel_recalc,
1164 1162
@@ -1177,7 +1175,6 @@ static struct clk rm_ick = {
1177 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), 1175 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1178 .clksel_mask = OMAP3430_CLKSEL_RM_MASK, 1176 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1179 .clksel = div2_l4_clksel, 1177 .clksel = div2_l4_clksel,
1180 .flags = CLOCK_IN_OMAP343X,
1181 .recalc = &omap2_clksel_recalc, 1178 .recalc = &omap2_clksel_recalc,
1182}; 1179};
1183 1180
@@ -1198,7 +1195,6 @@ static struct clk gfx_l3_ck = {
1198 .init = &omap2_init_clksel_parent, 1195 .init = &omap2_init_clksel_parent,
1199 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), 1196 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1200 .enable_bit = OMAP_EN_GFX_SHIFT, 1197 .enable_bit = OMAP_EN_GFX_SHIFT,
1201 .flags = CLOCK_IN_OMAP3430ES1,
1202 .recalc = &followparent_recalc, 1198 .recalc = &followparent_recalc,
1203}; 1199};
1204 1200
@@ -1210,7 +1206,7 @@ static struct clk gfx_l3_fck = {
1210 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), 1206 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1211 .clksel_mask = OMAP_CLKSEL_GFX_MASK, 1207 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1212 .clksel = gfx_l3_clksel, 1208 .clksel = gfx_l3_clksel,
1213 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES, 1209 .flags = RATE_PROPAGATES,
1214 .clkdm_name = "gfx_3430es1_clkdm", 1210 .clkdm_name = "gfx_3430es1_clkdm",
1215 .recalc = &omap2_clksel_recalc, 1211 .recalc = &omap2_clksel_recalc,
1216}; 1212};
@@ -1219,7 +1215,6 @@ static struct clk gfx_l3_ick = {
1219 .name = "gfx_l3_ick", 1215 .name = "gfx_l3_ick",
1220 .ops = &clkops_null, 1216 .ops = &clkops_null,
1221 .parent = &gfx_l3_ck, 1217 .parent = &gfx_l3_ck,
1222 .flags = CLOCK_IN_OMAP3430ES1,
1223 .clkdm_name = "gfx_3430es1_clkdm", 1218 .clkdm_name = "gfx_3430es1_clkdm",
1224 .recalc = &followparent_recalc, 1219 .recalc = &followparent_recalc,
1225}; 1220};
@@ -1231,7 +1226,6 @@ static struct clk gfx_cg1_ck = {
1231 .init = &omap2_init_clk_clkdm, 1226 .init = &omap2_init_clk_clkdm,
1232 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1227 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1233 .enable_bit = OMAP3430ES1_EN_2D_SHIFT, 1228 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1234 .flags = CLOCK_IN_OMAP3430ES1,
1235 .clkdm_name = "gfx_3430es1_clkdm", 1229 .clkdm_name = "gfx_3430es1_clkdm",
1236 .recalc = &followparent_recalc, 1230 .recalc = &followparent_recalc,
1237}; 1231};
@@ -1243,7 +1237,6 @@ static struct clk gfx_cg2_ck = {
1243 .init = &omap2_init_clk_clkdm, 1237 .init = &omap2_init_clk_clkdm,
1244 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1238 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1245 .enable_bit = OMAP3430ES1_EN_3D_SHIFT, 1239 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1246 .flags = CLOCK_IN_OMAP3430ES1,
1247 .clkdm_name = "gfx_3430es1_clkdm", 1240 .clkdm_name = "gfx_3430es1_clkdm",
1248 .recalc = &followparent_recalc, 1241 .recalc = &followparent_recalc,
1249}; 1242};
@@ -1277,7 +1270,6 @@ static struct clk sgx_fck = {
1277 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), 1270 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1278 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, 1271 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1279 .clksel = sgx_clksel, 1272 .clksel = sgx_clksel,
1280 .flags = CLOCK_IN_OMAP3430ES2,
1281 .clkdm_name = "sgx_clkdm", 1273 .clkdm_name = "sgx_clkdm",
1282 .recalc = &omap2_clksel_recalc, 1274 .recalc = &omap2_clksel_recalc,
1283}; 1275};
@@ -1289,7 +1281,6 @@ static struct clk sgx_ick = {
1289 .init = &omap2_init_clk_clkdm, 1281 .init = &omap2_init_clk_clkdm,
1290 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), 1282 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1291 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, 1283 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
1292 .flags = CLOCK_IN_OMAP3430ES2,
1293 .clkdm_name = "sgx_clkdm", 1284 .clkdm_name = "sgx_clkdm",
1294 .recalc = &followparent_recalc, 1285 .recalc = &followparent_recalc,
1295}; 1286};
@@ -1303,7 +1294,6 @@ static struct clk d2d_26m_fck = {
1303 .init = &omap2_init_clk_clkdm, 1294 .init = &omap2_init_clk_clkdm,
1304 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1295 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1305 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, 1296 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1306 .flags = CLOCK_IN_OMAP3430ES1,
1307 .clkdm_name = "d2d_clkdm", 1297 .clkdm_name = "d2d_clkdm",
1308 .recalc = &followparent_recalc, 1298 .recalc = &followparent_recalc,
1309}; 1299};
@@ -1324,7 +1314,6 @@ static struct clk gpt10_fck = {
1324 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1314 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1325 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, 1315 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1326 .clksel = omap343x_gpt_clksel, 1316 .clksel = omap343x_gpt_clksel,
1327 .flags = CLOCK_IN_OMAP343X,
1328 .clkdm_name = "core_l4_clkdm", 1317 .clkdm_name = "core_l4_clkdm",
1329 .recalc = &omap2_clksel_recalc, 1318 .recalc = &omap2_clksel_recalc,
1330}; 1319};
@@ -1339,7 +1328,6 @@ static struct clk gpt11_fck = {
1339 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1328 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1340 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, 1329 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1341 .clksel = omap343x_gpt_clksel, 1330 .clksel = omap343x_gpt_clksel,
1342 .flags = CLOCK_IN_OMAP343X,
1343 .clkdm_name = "core_l4_clkdm", 1331 .clkdm_name = "core_l4_clkdm",
1344 .recalc = &omap2_clksel_recalc, 1332 .recalc = &omap2_clksel_recalc,
1345}; 1333};
@@ -1350,7 +1338,6 @@ static struct clk cpefuse_fck = {
1350 .parent = &sys_ck, 1338 .parent = &sys_ck,
1351 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), 1339 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1352 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, 1340 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1353 .flags = CLOCK_IN_OMAP3430ES2,
1354 .recalc = &followparent_recalc, 1341 .recalc = &followparent_recalc,
1355}; 1342};
1356 1343
@@ -1360,7 +1347,6 @@ static struct clk ts_fck = {
1360 .parent = &omap_32k_fck, 1347 .parent = &omap_32k_fck,
1361 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), 1348 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1362 .enable_bit = OMAP3430ES2_EN_TS_SHIFT, 1349 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1363 .flags = CLOCK_IN_OMAP3430ES2,
1364 .recalc = &followparent_recalc, 1350 .recalc = &followparent_recalc,
1365}; 1351};
1366 1352
@@ -1370,7 +1356,6 @@ static struct clk usbtll_fck = {
1370 .parent = &omap_120m_fck, 1356 .parent = &omap_120m_fck,
1371 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), 1357 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1372 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, 1358 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1373 .flags = CLOCK_IN_OMAP3430ES2,
1374 .recalc = &followparent_recalc, 1359 .recalc = &followparent_recalc,
1375}; 1360};
1376 1361
@@ -1380,7 +1365,7 @@ static struct clk core_96m_fck = {
1380 .name = "core_96m_fck", 1365 .name = "core_96m_fck",
1381 .ops = &clkops_null, 1366 .ops = &clkops_null,
1382 .parent = &omap_96m_fck, 1367 .parent = &omap_96m_fck,
1383 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1368 .flags = RATE_PROPAGATES,
1384 .clkdm_name = "core_l4_clkdm", 1369 .clkdm_name = "core_l4_clkdm",
1385 .recalc = &followparent_recalc, 1370 .recalc = &followparent_recalc,
1386}; 1371};
@@ -1392,7 +1377,6 @@ static struct clk mmchs3_fck = {
1392 .parent = &core_96m_fck, 1377 .parent = &core_96m_fck,
1393 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1378 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1394 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, 1379 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1395 .flags = CLOCK_IN_OMAP3430ES2,
1396 .clkdm_name = "core_l4_clkdm", 1380 .clkdm_name = "core_l4_clkdm",
1397 .recalc = &followparent_recalc, 1381 .recalc = &followparent_recalc,
1398}; 1382};
@@ -1404,7 +1388,6 @@ static struct clk mmchs2_fck = {
1404 .parent = &core_96m_fck, 1388 .parent = &core_96m_fck,
1405 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1389 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1406 .enable_bit = OMAP3430_EN_MMC2_SHIFT, 1390 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1407 .flags = CLOCK_IN_OMAP343X,
1408 .clkdm_name = "core_l4_clkdm", 1391 .clkdm_name = "core_l4_clkdm",
1409 .recalc = &followparent_recalc, 1392 .recalc = &followparent_recalc,
1410}; 1393};
@@ -1415,7 +1398,6 @@ static struct clk mspro_fck = {
1415 .parent = &core_96m_fck, 1398 .parent = &core_96m_fck,
1416 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1399 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1417 .enable_bit = OMAP3430_EN_MSPRO_SHIFT, 1400 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1418 .flags = CLOCK_IN_OMAP343X,
1419 .clkdm_name = "core_l4_clkdm", 1401 .clkdm_name = "core_l4_clkdm",
1420 .recalc = &followparent_recalc, 1402 .recalc = &followparent_recalc,
1421}; 1403};
@@ -1426,7 +1408,6 @@ static struct clk mmchs1_fck = {
1426 .parent = &core_96m_fck, 1408 .parent = &core_96m_fck,
1427 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1409 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1428 .enable_bit = OMAP3430_EN_MMC1_SHIFT, 1410 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1429 .flags = CLOCK_IN_OMAP343X,
1430 .clkdm_name = "core_l4_clkdm", 1411 .clkdm_name = "core_l4_clkdm",
1431 .recalc = &followparent_recalc, 1412 .recalc = &followparent_recalc,
1432}; 1413};
@@ -1438,7 +1419,6 @@ static struct clk i2c3_fck = {
1438 .parent = &core_96m_fck, 1419 .parent = &core_96m_fck,
1439 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1420 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1440 .enable_bit = OMAP3430_EN_I2C3_SHIFT, 1421 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1441 .flags = CLOCK_IN_OMAP343X,
1442 .clkdm_name = "core_l4_clkdm", 1422 .clkdm_name = "core_l4_clkdm",
1443 .recalc = &followparent_recalc, 1423 .recalc = &followparent_recalc,
1444}; 1424};
@@ -1450,7 +1430,6 @@ static struct clk i2c2_fck = {
1450 .parent = &core_96m_fck, 1430 .parent = &core_96m_fck,
1451 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1431 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1452 .enable_bit = OMAP3430_EN_I2C2_SHIFT, 1432 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1453 .flags = CLOCK_IN_OMAP343X,
1454 .clkdm_name = "core_l4_clkdm", 1433 .clkdm_name = "core_l4_clkdm",
1455 .recalc = &followparent_recalc, 1434 .recalc = &followparent_recalc,
1456}; 1435};
@@ -1462,7 +1441,6 @@ static struct clk i2c1_fck = {
1462 .parent = &core_96m_fck, 1441 .parent = &core_96m_fck,
1463 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1442 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1464 .enable_bit = OMAP3430_EN_I2C1_SHIFT, 1443 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1465 .flags = CLOCK_IN_OMAP343X,
1466 .clkdm_name = "core_l4_clkdm", 1444 .clkdm_name = "core_l4_clkdm",
1467 .recalc = &followparent_recalc, 1445 .recalc = &followparent_recalc,
1468}; 1446};
@@ -1497,7 +1475,6 @@ static struct clk mcbsp5_fck = {
1497 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), 1475 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1498 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, 1476 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1499 .clksel = mcbsp_15_clksel, 1477 .clksel = mcbsp_15_clksel,
1500 .flags = CLOCK_IN_OMAP343X,
1501 .clkdm_name = "core_l4_clkdm", 1478 .clkdm_name = "core_l4_clkdm",
1502 .recalc = &omap2_clksel_recalc, 1479 .recalc = &omap2_clksel_recalc,
1503}; 1480};
@@ -1512,7 +1489,6 @@ static struct clk mcbsp1_fck = {
1512 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), 1489 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1513 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, 1490 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1514 .clksel = mcbsp_15_clksel, 1491 .clksel = mcbsp_15_clksel,
1515 .flags = CLOCK_IN_OMAP343X,
1516 .clkdm_name = "core_l4_clkdm", 1492 .clkdm_name = "core_l4_clkdm",
1517 .recalc = &omap2_clksel_recalc, 1493 .recalc = &omap2_clksel_recalc,
1518}; 1494};
@@ -1523,7 +1499,7 @@ static struct clk core_48m_fck = {
1523 .name = "core_48m_fck", 1499 .name = "core_48m_fck",
1524 .ops = &clkops_null, 1500 .ops = &clkops_null,
1525 .parent = &omap_48m_fck, 1501 .parent = &omap_48m_fck,
1526 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1502 .flags = RATE_PROPAGATES,
1527 .clkdm_name = "core_l4_clkdm", 1503 .clkdm_name = "core_l4_clkdm",
1528 .recalc = &followparent_recalc, 1504 .recalc = &followparent_recalc,
1529}; 1505};
@@ -1535,7 +1511,6 @@ static struct clk mcspi4_fck = {
1535 .parent = &core_48m_fck, 1511 .parent = &core_48m_fck,
1536 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1512 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1537 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, 1513 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1538 .flags = CLOCK_IN_OMAP343X,
1539 .recalc = &followparent_recalc, 1514 .recalc = &followparent_recalc,
1540}; 1515};
1541 1516
@@ -1546,7 +1521,6 @@ static struct clk mcspi3_fck = {
1546 .parent = &core_48m_fck, 1521 .parent = &core_48m_fck,
1547 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1522 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1548 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, 1523 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1549 .flags = CLOCK_IN_OMAP343X,
1550 .recalc = &followparent_recalc, 1524 .recalc = &followparent_recalc,
1551}; 1525};
1552 1526
@@ -1557,7 +1531,6 @@ static struct clk mcspi2_fck = {
1557 .parent = &core_48m_fck, 1531 .parent = &core_48m_fck,
1558 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1532 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1559 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, 1533 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1560 .flags = CLOCK_IN_OMAP343X,
1561 .recalc = &followparent_recalc, 1534 .recalc = &followparent_recalc,
1562}; 1535};
1563 1536
@@ -1568,7 +1541,6 @@ static struct clk mcspi1_fck = {
1568 .parent = &core_48m_fck, 1541 .parent = &core_48m_fck,
1569 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1542 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1570 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, 1543 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1571 .flags = CLOCK_IN_OMAP343X,
1572 .recalc = &followparent_recalc, 1544 .recalc = &followparent_recalc,
1573}; 1545};
1574 1546
@@ -1578,7 +1550,6 @@ static struct clk uart2_fck = {
1578 .parent = &core_48m_fck, 1550 .parent = &core_48m_fck,
1579 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1551 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1580 .enable_bit = OMAP3430_EN_UART2_SHIFT, 1552 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1581 .flags = CLOCK_IN_OMAP343X,
1582 .recalc = &followparent_recalc, 1553 .recalc = &followparent_recalc,
1583}; 1554};
1584 1555
@@ -1588,7 +1559,6 @@ static struct clk uart1_fck = {
1588 .parent = &core_48m_fck, 1559 .parent = &core_48m_fck,
1589 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1560 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1590 .enable_bit = OMAP3430_EN_UART1_SHIFT, 1561 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1591 .flags = CLOCK_IN_OMAP343X,
1592 .recalc = &followparent_recalc, 1562 .recalc = &followparent_recalc,
1593}; 1563};
1594 1564
@@ -1598,7 +1568,6 @@ static struct clk fshostusb_fck = {
1598 .parent = &core_48m_fck, 1568 .parent = &core_48m_fck,
1599 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1569 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1600 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, 1570 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1601 .flags = CLOCK_IN_OMAP3430ES1,
1602 .recalc = &followparent_recalc, 1571 .recalc = &followparent_recalc,
1603}; 1572};
1604 1573
@@ -1608,7 +1577,7 @@ static struct clk core_12m_fck = {
1608 .name = "core_12m_fck", 1577 .name = "core_12m_fck",
1609 .ops = &clkops_null, 1578 .ops = &clkops_null,
1610 .parent = &omap_12m_fck, 1579 .parent = &omap_12m_fck,
1611 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1580 .flags = RATE_PROPAGATES,
1612 .clkdm_name = "core_l4_clkdm", 1581 .clkdm_name = "core_l4_clkdm",
1613 .recalc = &followparent_recalc, 1582 .recalc = &followparent_recalc,
1614}; 1583};
@@ -1619,7 +1588,6 @@ static struct clk hdq_fck = {
1619 .parent = &core_12m_fck, 1588 .parent = &core_12m_fck,
1620 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1589 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1621 .enable_bit = OMAP3430_EN_HDQ_SHIFT, 1590 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1622 .flags = CLOCK_IN_OMAP343X,
1623 .recalc = &followparent_recalc, 1591 .recalc = &followparent_recalc,
1624}; 1592};
1625 1593
@@ -1649,7 +1617,7 @@ static struct clk ssi_ssr_fck = {
1649 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1617 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1650 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, 1618 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1651 .clksel = ssi_ssr_clksel, 1619 .clksel = ssi_ssr_clksel,
1652 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1620 .flags = RATE_PROPAGATES,
1653 .clkdm_name = "core_l4_clkdm", 1621 .clkdm_name = "core_l4_clkdm",
1654 .recalc = &omap2_clksel_recalc, 1622 .recalc = &omap2_clksel_recalc,
1655}; 1623};
@@ -1659,7 +1627,6 @@ static struct clk ssi_sst_fck = {
1659 .ops = &clkops_null, 1627 .ops = &clkops_null,
1660 .parent = &ssi_ssr_fck, 1628 .parent = &ssi_ssr_fck,
1661 .fixed_div = 2, 1629 .fixed_div = 2,
1662 .flags = CLOCK_IN_OMAP343X,
1663 .recalc = &omap2_fixed_divisor_recalc, 1630 .recalc = &omap2_fixed_divisor_recalc,
1664}; 1631};
1665 1632
@@ -1676,7 +1643,7 @@ static struct clk core_l3_ick = {
1676 .ops = &clkops_null, 1643 .ops = &clkops_null,
1677 .parent = &l3_ick, 1644 .parent = &l3_ick,
1678 .init = &omap2_init_clk_clkdm, 1645 .init = &omap2_init_clk_clkdm,
1679 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1646 .flags = RATE_PROPAGATES,
1680 .clkdm_name = "core_l3_clkdm", 1647 .clkdm_name = "core_l3_clkdm",
1681 .recalc = &followparent_recalc, 1648 .recalc = &followparent_recalc,
1682}; 1649};
@@ -1687,7 +1654,6 @@ static struct clk hsotgusb_ick = {
1687 .parent = &core_l3_ick, 1654 .parent = &core_l3_ick,
1688 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1655 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1689 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, 1656 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1690 .flags = CLOCK_IN_OMAP343X,
1691 .clkdm_name = "core_l3_clkdm", 1657 .clkdm_name = "core_l3_clkdm",
1692 .recalc = &followparent_recalc, 1658 .recalc = &followparent_recalc,
1693}; 1659};
@@ -1698,7 +1664,7 @@ static struct clk sdrc_ick = {
1698 .parent = &core_l3_ick, 1664 .parent = &core_l3_ick,
1699 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1665 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1700 .enable_bit = OMAP3430_EN_SDRC_SHIFT, 1666 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1701 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, 1667 .flags = ENABLE_ON_INIT,
1702 .clkdm_name = "core_l3_clkdm", 1668 .clkdm_name = "core_l3_clkdm",
1703 .recalc = &followparent_recalc, 1669 .recalc = &followparent_recalc,
1704}; 1670};
@@ -1707,7 +1673,7 @@ static struct clk gpmc_fck = {
1707 .name = "gpmc_fck", 1673 .name = "gpmc_fck",
1708 .ops = &clkops_null, 1674 .ops = &clkops_null,
1709 .parent = &core_l3_ick, 1675 .parent = &core_l3_ick,
1710 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, /* huh? */ 1676 .flags = ENABLE_ON_INIT, /* huh? */
1711 .clkdm_name = "core_l3_clkdm", 1677 .clkdm_name = "core_l3_clkdm",
1712 .recalc = &followparent_recalc, 1678 .recalc = &followparent_recalc,
1713}; 1679};
@@ -1718,7 +1684,7 @@ static struct clk security_l3_ick = {
1718 .name = "security_l3_ick", 1684 .name = "security_l3_ick",
1719 .ops = &clkops_null, 1685 .ops = &clkops_null,
1720 .parent = &l3_ick, 1686 .parent = &l3_ick,
1721 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1687 .flags = RATE_PROPAGATES,
1722 .recalc = &followparent_recalc, 1688 .recalc = &followparent_recalc,
1723}; 1689};
1724 1690
@@ -1728,7 +1694,6 @@ static struct clk pka_ick = {
1728 .parent = &security_l3_ick, 1694 .parent = &security_l3_ick,
1729 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1695 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1730 .enable_bit = OMAP3430_EN_PKA_SHIFT, 1696 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1731 .flags = CLOCK_IN_OMAP343X,
1732 .recalc = &followparent_recalc, 1697 .recalc = &followparent_recalc,
1733}; 1698};
1734 1699
@@ -1739,7 +1704,7 @@ static struct clk core_l4_ick = {
1739 .ops = &clkops_null, 1704 .ops = &clkops_null,
1740 .parent = &l4_ick, 1705 .parent = &l4_ick,
1741 .init = &omap2_init_clk_clkdm, 1706 .init = &omap2_init_clk_clkdm,
1742 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1707 .flags = RATE_PROPAGATES,
1743 .clkdm_name = "core_l4_clkdm", 1708 .clkdm_name = "core_l4_clkdm",
1744 .recalc = &followparent_recalc, 1709 .recalc = &followparent_recalc,
1745}; 1710};
@@ -1750,7 +1715,6 @@ static struct clk usbtll_ick = {
1750 .parent = &core_l4_ick, 1715 .parent = &core_l4_ick,
1751 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 1716 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1752 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, 1717 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1753 .flags = CLOCK_IN_OMAP3430ES2,
1754 .clkdm_name = "core_l4_clkdm", 1718 .clkdm_name = "core_l4_clkdm",
1755 .recalc = &followparent_recalc, 1719 .recalc = &followparent_recalc,
1756}; 1720};
@@ -1762,7 +1726,6 @@ static struct clk mmchs3_ick = {
1762 .parent = &core_l4_ick, 1726 .parent = &core_l4_ick,
1763 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1727 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1764 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, 1728 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1765 .flags = CLOCK_IN_OMAP3430ES2,
1766 .clkdm_name = "core_l4_clkdm", 1729 .clkdm_name = "core_l4_clkdm",
1767 .recalc = &followparent_recalc, 1730 .recalc = &followparent_recalc,
1768}; 1731};
@@ -1774,7 +1737,6 @@ static struct clk icr_ick = {
1774 .parent = &core_l4_ick, 1737 .parent = &core_l4_ick,
1775 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1738 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1776 .enable_bit = OMAP3430_EN_ICR_SHIFT, 1739 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1777 .flags = CLOCK_IN_OMAP343X,
1778 .clkdm_name = "core_l4_clkdm", 1740 .clkdm_name = "core_l4_clkdm",
1779 .recalc = &followparent_recalc, 1741 .recalc = &followparent_recalc,
1780}; 1742};
@@ -1785,7 +1747,6 @@ static struct clk aes2_ick = {
1785 .parent = &core_l4_ick, 1747 .parent = &core_l4_ick,
1786 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1748 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1787 .enable_bit = OMAP3430_EN_AES2_SHIFT, 1749 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1788 .flags = CLOCK_IN_OMAP343X,
1789 .clkdm_name = "core_l4_clkdm", 1750 .clkdm_name = "core_l4_clkdm",
1790 .recalc = &followparent_recalc, 1751 .recalc = &followparent_recalc,
1791}; 1752};
@@ -1796,7 +1757,6 @@ static struct clk sha12_ick = {
1796 .parent = &core_l4_ick, 1757 .parent = &core_l4_ick,
1797 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1758 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1798 .enable_bit = OMAP3430_EN_SHA12_SHIFT, 1759 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1799 .flags = CLOCK_IN_OMAP343X,
1800 .clkdm_name = "core_l4_clkdm", 1760 .clkdm_name = "core_l4_clkdm",
1801 .recalc = &followparent_recalc, 1761 .recalc = &followparent_recalc,
1802}; 1762};
@@ -1807,7 +1767,6 @@ static struct clk des2_ick = {
1807 .parent = &core_l4_ick, 1767 .parent = &core_l4_ick,
1808 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1768 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1809 .enable_bit = OMAP3430_EN_DES2_SHIFT, 1769 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1810 .flags = CLOCK_IN_OMAP343X,
1811 .clkdm_name = "core_l4_clkdm", 1770 .clkdm_name = "core_l4_clkdm",
1812 .recalc = &followparent_recalc, 1771 .recalc = &followparent_recalc,
1813}; 1772};
@@ -1819,7 +1778,6 @@ static struct clk mmchs2_ick = {
1819 .parent = &core_l4_ick, 1778 .parent = &core_l4_ick,
1820 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1779 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1821 .enable_bit = OMAP3430_EN_MMC2_SHIFT, 1780 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1822 .flags = CLOCK_IN_OMAP343X,
1823 .clkdm_name = "core_l4_clkdm", 1781 .clkdm_name = "core_l4_clkdm",
1824 .recalc = &followparent_recalc, 1782 .recalc = &followparent_recalc,
1825}; 1783};
@@ -1830,7 +1788,6 @@ static struct clk mmchs1_ick = {
1830 .parent = &core_l4_ick, 1788 .parent = &core_l4_ick,
1831 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1789 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1832 .enable_bit = OMAP3430_EN_MMC1_SHIFT, 1790 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1833 .flags = CLOCK_IN_OMAP343X,
1834 .clkdm_name = "core_l4_clkdm", 1791 .clkdm_name = "core_l4_clkdm",
1835 .recalc = &followparent_recalc, 1792 .recalc = &followparent_recalc,
1836}; 1793};
@@ -1841,7 +1798,6 @@ static struct clk mspro_ick = {
1841 .parent = &core_l4_ick, 1798 .parent = &core_l4_ick,
1842 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1799 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1843 .enable_bit = OMAP3430_EN_MSPRO_SHIFT, 1800 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1844 .flags = CLOCK_IN_OMAP343X,
1845 .clkdm_name = "core_l4_clkdm", 1801 .clkdm_name = "core_l4_clkdm",
1846 .recalc = &followparent_recalc, 1802 .recalc = &followparent_recalc,
1847}; 1803};
@@ -1852,7 +1808,6 @@ static struct clk hdq_ick = {
1852 .parent = &core_l4_ick, 1808 .parent = &core_l4_ick,
1853 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1809 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1854 .enable_bit = OMAP3430_EN_HDQ_SHIFT, 1810 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1855 .flags = CLOCK_IN_OMAP343X,
1856 .clkdm_name = "core_l4_clkdm", 1811 .clkdm_name = "core_l4_clkdm",
1857 .recalc = &followparent_recalc, 1812 .recalc = &followparent_recalc,
1858}; 1813};
@@ -1864,7 +1819,6 @@ static struct clk mcspi4_ick = {
1864 .parent = &core_l4_ick, 1819 .parent = &core_l4_ick,
1865 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1820 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1866 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, 1821 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1867 .flags = CLOCK_IN_OMAP343X,
1868 .clkdm_name = "core_l4_clkdm", 1822 .clkdm_name = "core_l4_clkdm",
1869 .recalc = &followparent_recalc, 1823 .recalc = &followparent_recalc,
1870}; 1824};
@@ -1876,7 +1830,6 @@ static struct clk mcspi3_ick = {
1876 .parent = &core_l4_ick, 1830 .parent = &core_l4_ick,
1877 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1831 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1878 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, 1832 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1879 .flags = CLOCK_IN_OMAP343X,
1880 .clkdm_name = "core_l4_clkdm", 1833 .clkdm_name = "core_l4_clkdm",
1881 .recalc = &followparent_recalc, 1834 .recalc = &followparent_recalc,
1882}; 1835};
@@ -1888,7 +1841,6 @@ static struct clk mcspi2_ick = {
1888 .parent = &core_l4_ick, 1841 .parent = &core_l4_ick,
1889 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1842 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1890 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, 1843 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1891 .flags = CLOCK_IN_OMAP343X,
1892 .clkdm_name = "core_l4_clkdm", 1844 .clkdm_name = "core_l4_clkdm",
1893 .recalc = &followparent_recalc, 1845 .recalc = &followparent_recalc,
1894}; 1846};
@@ -1900,7 +1852,6 @@ static struct clk mcspi1_ick = {
1900 .parent = &core_l4_ick, 1852 .parent = &core_l4_ick,
1901 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1853 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1902 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, 1854 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1903 .flags = CLOCK_IN_OMAP343X,
1904 .clkdm_name = "core_l4_clkdm", 1855 .clkdm_name = "core_l4_clkdm",
1905 .recalc = &followparent_recalc, 1856 .recalc = &followparent_recalc,
1906}; 1857};
@@ -1912,7 +1863,6 @@ static struct clk i2c3_ick = {
1912 .parent = &core_l4_ick, 1863 .parent = &core_l4_ick,
1913 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1864 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1914 .enable_bit = OMAP3430_EN_I2C3_SHIFT, 1865 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1915 .flags = CLOCK_IN_OMAP343X,
1916 .clkdm_name = "core_l4_clkdm", 1866 .clkdm_name = "core_l4_clkdm",
1917 .recalc = &followparent_recalc, 1867 .recalc = &followparent_recalc,
1918}; 1868};
@@ -1924,7 +1874,6 @@ static struct clk i2c2_ick = {
1924 .parent = &core_l4_ick, 1874 .parent = &core_l4_ick,
1925 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1875 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1926 .enable_bit = OMAP3430_EN_I2C2_SHIFT, 1876 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1927 .flags = CLOCK_IN_OMAP343X,
1928 .clkdm_name = "core_l4_clkdm", 1877 .clkdm_name = "core_l4_clkdm",
1929 .recalc = &followparent_recalc, 1878 .recalc = &followparent_recalc,
1930}; 1879};
@@ -1936,7 +1885,6 @@ static struct clk i2c1_ick = {
1936 .parent = &core_l4_ick, 1885 .parent = &core_l4_ick,
1937 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1886 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1938 .enable_bit = OMAP3430_EN_I2C1_SHIFT, 1887 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1939 .flags = CLOCK_IN_OMAP343X,
1940 .clkdm_name = "core_l4_clkdm", 1888 .clkdm_name = "core_l4_clkdm",
1941 .recalc = &followparent_recalc, 1889 .recalc = &followparent_recalc,
1942}; 1890};
@@ -1947,7 +1895,6 @@ static struct clk uart2_ick = {
1947 .parent = &core_l4_ick, 1895 .parent = &core_l4_ick,
1948 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1896 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1949 .enable_bit = OMAP3430_EN_UART2_SHIFT, 1897 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1950 .flags = CLOCK_IN_OMAP343X,
1951 .clkdm_name = "core_l4_clkdm", 1898 .clkdm_name = "core_l4_clkdm",
1952 .recalc = &followparent_recalc, 1899 .recalc = &followparent_recalc,
1953}; 1900};
@@ -1958,7 +1905,6 @@ static struct clk uart1_ick = {
1958 .parent = &core_l4_ick, 1905 .parent = &core_l4_ick,
1959 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1906 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1960 .enable_bit = OMAP3430_EN_UART1_SHIFT, 1907 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1961 .flags = CLOCK_IN_OMAP343X,
1962 .clkdm_name = "core_l4_clkdm", 1908 .clkdm_name = "core_l4_clkdm",
1963 .recalc = &followparent_recalc, 1909 .recalc = &followparent_recalc,
1964}; 1910};
@@ -1969,7 +1915,6 @@ static struct clk gpt11_ick = {
1969 .parent = &core_l4_ick, 1915 .parent = &core_l4_ick,
1970 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1916 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1971 .enable_bit = OMAP3430_EN_GPT11_SHIFT, 1917 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1972 .flags = CLOCK_IN_OMAP343X,
1973 .clkdm_name = "core_l4_clkdm", 1918 .clkdm_name = "core_l4_clkdm",
1974 .recalc = &followparent_recalc, 1919 .recalc = &followparent_recalc,
1975}; 1920};
@@ -1980,7 +1925,6 @@ static struct clk gpt10_ick = {
1980 .parent = &core_l4_ick, 1925 .parent = &core_l4_ick,
1981 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1926 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1982 .enable_bit = OMAP3430_EN_GPT10_SHIFT, 1927 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1983 .flags = CLOCK_IN_OMAP343X,
1984 .clkdm_name = "core_l4_clkdm", 1928 .clkdm_name = "core_l4_clkdm",
1985 .recalc = &followparent_recalc, 1929 .recalc = &followparent_recalc,
1986}; 1930};
@@ -1992,7 +1936,6 @@ static struct clk mcbsp5_ick = {
1992 .parent = &core_l4_ick, 1936 .parent = &core_l4_ick,
1993 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1937 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1994 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, 1938 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1995 .flags = CLOCK_IN_OMAP343X,
1996 .clkdm_name = "core_l4_clkdm", 1939 .clkdm_name = "core_l4_clkdm",
1997 .recalc = &followparent_recalc, 1940 .recalc = &followparent_recalc,
1998}; 1941};
@@ -2004,7 +1947,6 @@ static struct clk mcbsp1_ick = {
2004 .parent = &core_l4_ick, 1947 .parent = &core_l4_ick,
2005 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1948 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2006 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, 1949 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2007 .flags = CLOCK_IN_OMAP343X,
2008 .clkdm_name = "core_l4_clkdm", 1950 .clkdm_name = "core_l4_clkdm",
2009 .recalc = &followparent_recalc, 1951 .recalc = &followparent_recalc,
2010}; 1952};
@@ -2015,7 +1957,6 @@ static struct clk fac_ick = {
2015 .parent = &core_l4_ick, 1957 .parent = &core_l4_ick,
2016 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1958 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2017 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, 1959 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
2018 .flags = CLOCK_IN_OMAP3430ES1,
2019 .clkdm_name = "core_l4_clkdm", 1960 .clkdm_name = "core_l4_clkdm",
2020 .recalc = &followparent_recalc, 1961 .recalc = &followparent_recalc,
2021}; 1962};
@@ -2026,7 +1967,6 @@ static struct clk mailboxes_ick = {
2026 .parent = &core_l4_ick, 1967 .parent = &core_l4_ick,
2027 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1968 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2028 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, 1969 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2029 .flags = CLOCK_IN_OMAP343X,
2030 .clkdm_name = "core_l4_clkdm", 1970 .clkdm_name = "core_l4_clkdm",
2031 .recalc = &followparent_recalc, 1971 .recalc = &followparent_recalc,
2032}; 1972};
@@ -2037,7 +1977,7 @@ static struct clk omapctrl_ick = {
2037 .parent = &core_l4_ick, 1977 .parent = &core_l4_ick,
2038 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1978 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2039 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, 1979 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2040 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, 1980 .flags = ENABLE_ON_INIT,
2041 .recalc = &followparent_recalc, 1981 .recalc = &followparent_recalc,
2042}; 1982};
2043 1983
@@ -2047,7 +1987,7 @@ static struct clk ssi_l4_ick = {
2047 .name = "ssi_l4_ick", 1987 .name = "ssi_l4_ick",
2048 .ops = &clkops_null, 1988 .ops = &clkops_null,
2049 .parent = &l4_ick, 1989 .parent = &l4_ick,
2050 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1990 .flags = RATE_PROPAGATES,
2051 .clkdm_name = "core_l4_clkdm", 1991 .clkdm_name = "core_l4_clkdm",
2052 .recalc = &followparent_recalc, 1992 .recalc = &followparent_recalc,
2053}; 1993};
@@ -2058,7 +1998,6 @@ static struct clk ssi_ick = {
2058 .parent = &ssi_l4_ick, 1998 .parent = &ssi_l4_ick,
2059 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1999 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2060 .enable_bit = OMAP3430_EN_SSI_SHIFT, 2000 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2061 .flags = CLOCK_IN_OMAP343X,
2062 .clkdm_name = "core_l4_clkdm", 2001 .clkdm_name = "core_l4_clkdm",
2063 .recalc = &followparent_recalc, 2002 .recalc = &followparent_recalc,
2064}; 2003};
@@ -2081,7 +2020,6 @@ static struct clk usb_l4_ick = {
2081 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 2020 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2082 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, 2021 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2083 .clksel = usb_l4_clksel, 2022 .clksel = usb_l4_clksel,
2084 .flags = CLOCK_IN_OMAP3430ES1,
2085 .recalc = &omap2_clksel_recalc, 2023 .recalc = &omap2_clksel_recalc,
2086}; 2024};
2087 2025
@@ -2093,7 +2031,7 @@ static struct clk security_l4_ick2 = {
2093 .name = "security_l4_ick2", 2031 .name = "security_l4_ick2",
2094 .ops = &clkops_null, 2032 .ops = &clkops_null,
2095 .parent = &l4_ick, 2033 .parent = &l4_ick,
2096 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 2034 .flags = RATE_PROPAGATES,
2097 .recalc = &followparent_recalc, 2035 .recalc = &followparent_recalc,
2098}; 2036};
2099 2037
@@ -2103,7 +2041,6 @@ static struct clk aes1_ick = {
2103 .parent = &security_l4_ick2, 2041 .parent = &security_l4_ick2,
2104 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2042 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2105 .enable_bit = OMAP3430_EN_AES1_SHIFT, 2043 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2106 .flags = CLOCK_IN_OMAP343X,
2107 .recalc = &followparent_recalc, 2044 .recalc = &followparent_recalc,
2108}; 2045};
2109 2046
@@ -2113,7 +2050,6 @@ static struct clk rng_ick = {
2113 .parent = &security_l4_ick2, 2050 .parent = &security_l4_ick2,
2114 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2051 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2115 .enable_bit = OMAP3430_EN_RNG_SHIFT, 2052 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2116 .flags = CLOCK_IN_OMAP343X,
2117 .recalc = &followparent_recalc, 2053 .recalc = &followparent_recalc,
2118}; 2054};
2119 2055
@@ -2123,7 +2059,6 @@ static struct clk sha11_ick = {
2123 .parent = &security_l4_ick2, 2059 .parent = &security_l4_ick2,
2124 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2060 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2125 .enable_bit = OMAP3430_EN_SHA11_SHIFT, 2061 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2126 .flags = CLOCK_IN_OMAP343X,
2127 .recalc = &followparent_recalc, 2062 .recalc = &followparent_recalc,
2128}; 2063};
2129 2064
@@ -2133,7 +2068,6 @@ static struct clk des1_ick = {
2133 .parent = &security_l4_ick2, 2068 .parent = &security_l4_ick2,
2134 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2069 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2135 .enable_bit = OMAP3430_EN_DES1_SHIFT, 2070 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2136 .flags = CLOCK_IN_OMAP343X,
2137 .recalc = &followparent_recalc, 2071 .recalc = &followparent_recalc,
2138}; 2072};
2139 2073
@@ -2154,7 +2088,6 @@ static struct clk dss1_alwon_fck = {
2154 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 2088 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2155 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, 2089 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
2156 .clksel = dss1_alwon_fck_clksel, 2090 .clksel = dss1_alwon_fck_clksel,
2157 .flags = CLOCK_IN_OMAP343X,
2158 .clkdm_name = "dss_clkdm", 2091 .clkdm_name = "dss_clkdm",
2159 .recalc = &omap2_clksel_recalc, 2092 .recalc = &omap2_clksel_recalc,
2160}; 2093};
@@ -2166,7 +2099,6 @@ static struct clk dss_tv_fck = {
2166 .init = &omap2_init_clk_clkdm, 2099 .init = &omap2_init_clk_clkdm,
2167 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2100 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2168 .enable_bit = OMAP3430_EN_TV_SHIFT, 2101 .enable_bit = OMAP3430_EN_TV_SHIFT,
2169 .flags = CLOCK_IN_OMAP343X,
2170 .clkdm_name = "dss_clkdm", 2102 .clkdm_name = "dss_clkdm",
2171 .recalc = &followparent_recalc, 2103 .recalc = &followparent_recalc,
2172}; 2104};
@@ -2178,7 +2110,6 @@ static struct clk dss_96m_fck = {
2178 .init = &omap2_init_clk_clkdm, 2110 .init = &omap2_init_clk_clkdm,
2179 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2111 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2180 .enable_bit = OMAP3430_EN_TV_SHIFT, 2112 .enable_bit = OMAP3430_EN_TV_SHIFT,
2181 .flags = CLOCK_IN_OMAP343X,
2182 .clkdm_name = "dss_clkdm", 2113 .clkdm_name = "dss_clkdm",
2183 .recalc = &followparent_recalc, 2114 .recalc = &followparent_recalc,
2184}; 2115};
@@ -2190,7 +2121,6 @@ static struct clk dss2_alwon_fck = {
2190 .init = &omap2_init_clk_clkdm, 2121 .init = &omap2_init_clk_clkdm,
2191 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2122 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2192 .enable_bit = OMAP3430_EN_DSS2_SHIFT, 2123 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2193 .flags = CLOCK_IN_OMAP343X,
2194 .clkdm_name = "dss_clkdm", 2124 .clkdm_name = "dss_clkdm",
2195 .recalc = &followparent_recalc, 2125 .recalc = &followparent_recalc,
2196}; 2126};
@@ -2203,7 +2133,6 @@ static struct clk dss_ick = {
2203 .init = &omap2_init_clk_clkdm, 2133 .init = &omap2_init_clk_clkdm,
2204 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), 2134 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2205 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, 2135 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2206 .flags = CLOCK_IN_OMAP343X,
2207 .clkdm_name = "dss_clkdm", 2136 .clkdm_name = "dss_clkdm",
2208 .recalc = &followparent_recalc, 2137 .recalc = &followparent_recalc,
2209}; 2138};
@@ -2226,7 +2155,6 @@ static struct clk cam_mclk = {
2226 .clksel = cam_mclk_clksel, 2155 .clksel = cam_mclk_clksel,
2227 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), 2156 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2228 .enable_bit = OMAP3430_EN_CAM_SHIFT, 2157 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2229 .flags = CLOCK_IN_OMAP343X,
2230 .clkdm_name = "cam_clkdm", 2158 .clkdm_name = "cam_clkdm",
2231 .recalc = &omap2_clksel_recalc, 2159 .recalc = &omap2_clksel_recalc,
2232}; 2160};
@@ -2239,7 +2167,6 @@ static struct clk cam_ick = {
2239 .init = &omap2_init_clk_clkdm, 2167 .init = &omap2_init_clk_clkdm,
2240 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), 2168 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2241 .enable_bit = OMAP3430_EN_CAM_SHIFT, 2169 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2242 .flags = CLOCK_IN_OMAP343X,
2243 .clkdm_name = "cam_clkdm", 2170 .clkdm_name = "cam_clkdm",
2244 .recalc = &followparent_recalc, 2171 .recalc = &followparent_recalc,
2245}; 2172};
@@ -2253,7 +2180,6 @@ static struct clk usbhost_120m_fck = {
2253 .init = &omap2_init_clk_clkdm, 2180 .init = &omap2_init_clk_clkdm,
2254 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), 2181 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2255 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, 2182 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2256 .flags = CLOCK_IN_OMAP3430ES2,
2257 .clkdm_name = "usbhost_clkdm", 2183 .clkdm_name = "usbhost_clkdm",
2258 .recalc = &followparent_recalc, 2184 .recalc = &followparent_recalc,
2259}; 2185};
@@ -2265,7 +2191,6 @@ static struct clk usbhost_48m_fck = {
2265 .init = &omap2_init_clk_clkdm, 2191 .init = &omap2_init_clk_clkdm,
2266 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), 2192 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2267 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, 2193 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2268 .flags = CLOCK_IN_OMAP3430ES2,
2269 .clkdm_name = "usbhost_clkdm", 2194 .clkdm_name = "usbhost_clkdm",
2270 .recalc = &followparent_recalc, 2195 .recalc = &followparent_recalc,
2271}; 2196};
@@ -2278,7 +2203,6 @@ static struct clk usbhost_ick = {
2278 .init = &omap2_init_clk_clkdm, 2203 .init = &omap2_init_clk_clkdm,
2279 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), 2204 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2280 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, 2205 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2281 .flags = CLOCK_IN_OMAP3430ES2,
2282 .clkdm_name = "usbhost_clkdm", 2206 .clkdm_name = "usbhost_clkdm",
2283 .recalc = &followparent_recalc, 2207 .recalc = &followparent_recalc,
2284}; 2208};
@@ -2290,7 +2214,6 @@ static struct clk usbhost_sar_fck = {
2290 .init = &omap2_init_clk_clkdm, 2214 .init = &omap2_init_clk_clkdm,
2291 .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL), 2215 .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2292 .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT, 2216 .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2293 .flags = CLOCK_IN_OMAP3430ES2,
2294 .clkdm_name = "usbhost_clkdm", 2217 .clkdm_name = "usbhost_clkdm",
2295 .recalc = &followparent_recalc, 2218 .recalc = &followparent_recalc,
2296}; 2219};
@@ -2330,7 +2253,6 @@ static struct clk usim_fck = {
2330 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), 2253 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2331 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, 2254 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2332 .clksel = usim_clksel, 2255 .clksel = usim_clksel,
2333 .flags = CLOCK_IN_OMAP3430ES2,
2334 .recalc = &omap2_clksel_recalc, 2256 .recalc = &omap2_clksel_recalc,
2335}; 2257};
2336 2258
@@ -2344,7 +2266,6 @@ static struct clk gpt1_fck = {
2344 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), 2266 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2345 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, 2267 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2346 .clksel = omap343x_gpt_clksel, 2268 .clksel = omap343x_gpt_clksel,
2347 .flags = CLOCK_IN_OMAP343X,
2348 .clkdm_name = "wkup_clkdm", 2269 .clkdm_name = "wkup_clkdm",
2349 .recalc = &omap2_clksel_recalc, 2270 .recalc = &omap2_clksel_recalc,
2350}; 2271};
@@ -2354,7 +2275,7 @@ static struct clk wkup_32k_fck = {
2354 .ops = &clkops_null, 2275 .ops = &clkops_null,
2355 .init = &omap2_init_clk_clkdm, 2276 .init = &omap2_init_clk_clkdm,
2356 .parent = &omap_32k_fck, 2277 .parent = &omap_32k_fck,
2357 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 2278 .flags = RATE_PROPAGATES,
2358 .clkdm_name = "wkup_clkdm", 2279 .clkdm_name = "wkup_clkdm",
2359 .recalc = &followparent_recalc, 2280 .recalc = &followparent_recalc,
2360}; 2281};
@@ -2365,7 +2286,6 @@ static struct clk gpio1_dbck = {
2365 .parent = &wkup_32k_fck, 2286 .parent = &wkup_32k_fck,
2366 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2287 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2367 .enable_bit = OMAP3430_EN_GPIO1_SHIFT, 2288 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2368 .flags = CLOCK_IN_OMAP343X,
2369 .clkdm_name = "wkup_clkdm", 2289 .clkdm_name = "wkup_clkdm",
2370 .recalc = &followparent_recalc, 2290 .recalc = &followparent_recalc,
2371}; 2291};
@@ -2376,7 +2296,6 @@ static struct clk wdt2_fck = {
2376 .parent = &wkup_32k_fck, 2296 .parent = &wkup_32k_fck,
2377 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2297 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2378 .enable_bit = OMAP3430_EN_WDT2_SHIFT, 2298 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2379 .flags = CLOCK_IN_OMAP343X,
2380 .clkdm_name = "wkup_clkdm", 2299 .clkdm_name = "wkup_clkdm",
2381 .recalc = &followparent_recalc, 2300 .recalc = &followparent_recalc,
2382}; 2301};
@@ -2385,7 +2304,7 @@ static struct clk wkup_l4_ick = {
2385 .name = "wkup_l4_ick", 2304 .name = "wkup_l4_ick",
2386 .ops = &clkops_null, 2305 .ops = &clkops_null,
2387 .parent = &sys_ck, 2306 .parent = &sys_ck,
2388 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 2307 .flags = RATE_PROPAGATES,
2389 .clkdm_name = "wkup_clkdm", 2308 .clkdm_name = "wkup_clkdm",
2390 .recalc = &followparent_recalc, 2309 .recalc = &followparent_recalc,
2391}; 2310};
@@ -2398,7 +2317,6 @@ static struct clk usim_ick = {
2398 .parent = &wkup_l4_ick, 2317 .parent = &wkup_l4_ick,
2399 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2318 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2400 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, 2319 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2401 .flags = CLOCK_IN_OMAP3430ES2,
2402 .clkdm_name = "wkup_clkdm", 2320 .clkdm_name = "wkup_clkdm",
2403 .recalc = &followparent_recalc, 2321 .recalc = &followparent_recalc,
2404}; 2322};
@@ -2409,7 +2327,6 @@ static struct clk wdt2_ick = {
2409 .parent = &wkup_l4_ick, 2327 .parent = &wkup_l4_ick,
2410 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2328 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2411 .enable_bit = OMAP3430_EN_WDT2_SHIFT, 2329 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2412 .flags = CLOCK_IN_OMAP343X,
2413 .clkdm_name = "wkup_clkdm", 2330 .clkdm_name = "wkup_clkdm",
2414 .recalc = &followparent_recalc, 2331 .recalc = &followparent_recalc,
2415}; 2332};
@@ -2420,7 +2337,6 @@ static struct clk wdt1_ick = {
2420 .parent = &wkup_l4_ick, 2337 .parent = &wkup_l4_ick,
2421 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2338 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2422 .enable_bit = OMAP3430_EN_WDT1_SHIFT, 2339 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2423 .flags = CLOCK_IN_OMAP343X,
2424 .clkdm_name = "wkup_clkdm", 2340 .clkdm_name = "wkup_clkdm",
2425 .recalc = &followparent_recalc, 2341 .recalc = &followparent_recalc,
2426}; 2342};
@@ -2431,7 +2347,6 @@ static struct clk gpio1_ick = {
2431 .parent = &wkup_l4_ick, 2347 .parent = &wkup_l4_ick,
2432 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2348 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2433 .enable_bit = OMAP3430_EN_GPIO1_SHIFT, 2349 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2434 .flags = CLOCK_IN_OMAP343X,
2435 .clkdm_name = "wkup_clkdm", 2350 .clkdm_name = "wkup_clkdm",
2436 .recalc = &followparent_recalc, 2351 .recalc = &followparent_recalc,
2437}; 2352};
@@ -2442,7 +2357,6 @@ static struct clk omap_32ksync_ick = {
2442 .parent = &wkup_l4_ick, 2357 .parent = &wkup_l4_ick,
2443 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2358 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2444 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, 2359 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2445 .flags = CLOCK_IN_OMAP343X,
2446 .clkdm_name = "wkup_clkdm", 2360 .clkdm_name = "wkup_clkdm",
2447 .recalc = &followparent_recalc, 2361 .recalc = &followparent_recalc,
2448}; 2362};
@@ -2454,7 +2368,6 @@ static struct clk gpt12_ick = {
2454 .parent = &wkup_l4_ick, 2368 .parent = &wkup_l4_ick,
2455 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2369 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2456 .enable_bit = OMAP3430_EN_GPT12_SHIFT, 2370 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2457 .flags = CLOCK_IN_OMAP343X,
2458 .clkdm_name = "wkup_clkdm", 2371 .clkdm_name = "wkup_clkdm",
2459 .recalc = &followparent_recalc, 2372 .recalc = &followparent_recalc,
2460}; 2373};
@@ -2465,7 +2378,6 @@ static struct clk gpt1_ick = {
2465 .parent = &wkup_l4_ick, 2378 .parent = &wkup_l4_ick,
2466 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2379 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2467 .enable_bit = OMAP3430_EN_GPT1_SHIFT, 2380 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2468 .flags = CLOCK_IN_OMAP343X,
2469 .clkdm_name = "wkup_clkdm", 2381 .clkdm_name = "wkup_clkdm",
2470 .recalc = &followparent_recalc, 2382 .recalc = &followparent_recalc,
2471}; 2383};
@@ -2479,7 +2391,7 @@ static struct clk per_96m_fck = {
2479 .ops = &clkops_null, 2391 .ops = &clkops_null,
2480 .parent = &omap_96m_alwon_fck, 2392 .parent = &omap_96m_alwon_fck,
2481 .init = &omap2_init_clk_clkdm, 2393 .init = &omap2_init_clk_clkdm,
2482 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 2394 .flags = RATE_PROPAGATES,
2483 .clkdm_name = "per_clkdm", 2395 .clkdm_name = "per_clkdm",
2484 .recalc = &followparent_recalc, 2396 .recalc = &followparent_recalc,
2485}; 2397};
@@ -2489,7 +2401,7 @@ static struct clk per_48m_fck = {
2489 .ops = &clkops_null, 2401 .ops = &clkops_null,
2490 .parent = &omap_48m_fck, 2402 .parent = &omap_48m_fck,
2491 .init = &omap2_init_clk_clkdm, 2403 .init = &omap2_init_clk_clkdm,
2492 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 2404 .flags = RATE_PROPAGATES,
2493 .clkdm_name = "per_clkdm", 2405 .clkdm_name = "per_clkdm",
2494 .recalc = &followparent_recalc, 2406 .recalc = &followparent_recalc,
2495}; 2407};
@@ -2500,7 +2412,6 @@ static struct clk uart3_fck = {
2500 .parent = &per_48m_fck, 2412 .parent = &per_48m_fck,
2501 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2413 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2502 .enable_bit = OMAP3430_EN_UART3_SHIFT, 2414 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2503 .flags = CLOCK_IN_OMAP343X,
2504 .clkdm_name = "per_clkdm", 2415 .clkdm_name = "per_clkdm",
2505 .recalc = &followparent_recalc, 2416 .recalc = &followparent_recalc,
2506}; 2417};
@@ -2514,7 +2425,6 @@ static struct clk gpt2_fck = {
2514 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2425 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2515 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, 2426 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2516 .clksel = omap343x_gpt_clksel, 2427 .clksel = omap343x_gpt_clksel,
2517 .flags = CLOCK_IN_OMAP343X,
2518 .clkdm_name = "per_clkdm", 2428 .clkdm_name = "per_clkdm",
2519 .recalc = &omap2_clksel_recalc, 2429 .recalc = &omap2_clksel_recalc,
2520}; 2430};
@@ -2528,7 +2438,6 @@ static struct clk gpt3_fck = {
2528 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2438 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2529 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, 2439 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2530 .clksel = omap343x_gpt_clksel, 2440 .clksel = omap343x_gpt_clksel,
2531 .flags = CLOCK_IN_OMAP343X,
2532 .clkdm_name = "per_clkdm", 2441 .clkdm_name = "per_clkdm",
2533 .recalc = &omap2_clksel_recalc, 2442 .recalc = &omap2_clksel_recalc,
2534}; 2443};
@@ -2542,7 +2451,6 @@ static struct clk gpt4_fck = {
2542 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2451 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2543 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, 2452 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2544 .clksel = omap343x_gpt_clksel, 2453 .clksel = omap343x_gpt_clksel,
2545 .flags = CLOCK_IN_OMAP343X,
2546 .clkdm_name = "per_clkdm", 2454 .clkdm_name = "per_clkdm",
2547 .recalc = &omap2_clksel_recalc, 2455 .recalc = &omap2_clksel_recalc,
2548}; 2456};
@@ -2556,7 +2464,6 @@ static struct clk gpt5_fck = {
2556 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2464 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2557 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, 2465 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2558 .clksel = omap343x_gpt_clksel, 2466 .clksel = omap343x_gpt_clksel,
2559 .flags = CLOCK_IN_OMAP343X,
2560 .clkdm_name = "per_clkdm", 2467 .clkdm_name = "per_clkdm",
2561 .recalc = &omap2_clksel_recalc, 2468 .recalc = &omap2_clksel_recalc,
2562}; 2469};
@@ -2570,7 +2477,6 @@ static struct clk gpt6_fck = {
2570 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2477 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2571 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, 2478 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2572 .clksel = omap343x_gpt_clksel, 2479 .clksel = omap343x_gpt_clksel,
2573 .flags = CLOCK_IN_OMAP343X,
2574 .clkdm_name = "per_clkdm", 2480 .clkdm_name = "per_clkdm",
2575 .recalc = &omap2_clksel_recalc, 2481 .recalc = &omap2_clksel_recalc,
2576}; 2482};
@@ -2584,7 +2490,6 @@ static struct clk gpt7_fck = {
2584 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2490 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2585 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, 2491 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2586 .clksel = omap343x_gpt_clksel, 2492 .clksel = omap343x_gpt_clksel,
2587 .flags = CLOCK_IN_OMAP343X,
2588 .clkdm_name = "per_clkdm", 2493 .clkdm_name = "per_clkdm",
2589 .recalc = &omap2_clksel_recalc, 2494 .recalc = &omap2_clksel_recalc,
2590}; 2495};
@@ -2598,7 +2503,6 @@ static struct clk gpt8_fck = {
2598 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2503 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2599 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, 2504 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2600 .clksel = omap343x_gpt_clksel, 2505 .clksel = omap343x_gpt_clksel,
2601 .flags = CLOCK_IN_OMAP343X,
2602 .clkdm_name = "per_clkdm", 2506 .clkdm_name = "per_clkdm",
2603 .recalc = &omap2_clksel_recalc, 2507 .recalc = &omap2_clksel_recalc,
2604}; 2508};
@@ -2612,7 +2516,6 @@ static struct clk gpt9_fck = {
2612 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2516 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2613 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, 2517 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2614 .clksel = omap343x_gpt_clksel, 2518 .clksel = omap343x_gpt_clksel,
2615 .flags = CLOCK_IN_OMAP343X,
2616 .clkdm_name = "per_clkdm", 2519 .clkdm_name = "per_clkdm",
2617 .recalc = &omap2_clksel_recalc, 2520 .recalc = &omap2_clksel_recalc,
2618}; 2521};
@@ -2622,7 +2525,7 @@ static struct clk per_32k_alwon_fck = {
2622 .ops = &clkops_null, 2525 .ops = &clkops_null,
2623 .parent = &omap_32k_fck, 2526 .parent = &omap_32k_fck,
2624 .clkdm_name = "per_clkdm", 2527 .clkdm_name = "per_clkdm",
2625 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 2528 .flags = RATE_PROPAGATES,
2626 .recalc = &followparent_recalc, 2529 .recalc = &followparent_recalc,
2627}; 2530};
2628 2531
@@ -2632,7 +2535,6 @@ static struct clk gpio6_dbck = {
2632 .parent = &per_32k_alwon_fck, 2535 .parent = &per_32k_alwon_fck,
2633 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2536 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2634 .enable_bit = OMAP3430_EN_GPIO6_SHIFT, 2537 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2635 .flags = CLOCK_IN_OMAP343X,
2636 .clkdm_name = "per_clkdm", 2538 .clkdm_name = "per_clkdm",
2637 .recalc = &followparent_recalc, 2539 .recalc = &followparent_recalc,
2638}; 2540};
@@ -2643,7 +2545,6 @@ static struct clk gpio5_dbck = {
2643 .parent = &per_32k_alwon_fck, 2545 .parent = &per_32k_alwon_fck,
2644 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2546 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2645 .enable_bit = OMAP3430_EN_GPIO5_SHIFT, 2547 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2646 .flags = CLOCK_IN_OMAP343X,
2647 .clkdm_name = "per_clkdm", 2548 .clkdm_name = "per_clkdm",
2648 .recalc = &followparent_recalc, 2549 .recalc = &followparent_recalc,
2649}; 2550};
@@ -2654,7 +2555,6 @@ static struct clk gpio4_dbck = {
2654 .parent = &per_32k_alwon_fck, 2555 .parent = &per_32k_alwon_fck,
2655 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2556 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2656 .enable_bit = OMAP3430_EN_GPIO4_SHIFT, 2557 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2657 .flags = CLOCK_IN_OMAP343X,
2658 .clkdm_name = "per_clkdm", 2558 .clkdm_name = "per_clkdm",
2659 .recalc = &followparent_recalc, 2559 .recalc = &followparent_recalc,
2660}; 2560};
@@ -2665,7 +2565,6 @@ static struct clk gpio3_dbck = {
2665 .parent = &per_32k_alwon_fck, 2565 .parent = &per_32k_alwon_fck,
2666 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2566 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2667 .enable_bit = OMAP3430_EN_GPIO3_SHIFT, 2567 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2668 .flags = CLOCK_IN_OMAP343X,
2669 .clkdm_name = "per_clkdm", 2568 .clkdm_name = "per_clkdm",
2670 .recalc = &followparent_recalc, 2569 .recalc = &followparent_recalc,
2671}; 2570};
@@ -2676,7 +2575,6 @@ static struct clk gpio2_dbck = {
2676 .parent = &per_32k_alwon_fck, 2575 .parent = &per_32k_alwon_fck,
2677 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2576 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2678 .enable_bit = OMAP3430_EN_GPIO2_SHIFT, 2577 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2679 .flags = CLOCK_IN_OMAP343X,
2680 .clkdm_name = "per_clkdm", 2578 .clkdm_name = "per_clkdm",
2681 .recalc = &followparent_recalc, 2579 .recalc = &followparent_recalc,
2682}; 2580};
@@ -2687,7 +2585,6 @@ static struct clk wdt3_fck = {
2687 .parent = &per_32k_alwon_fck, 2585 .parent = &per_32k_alwon_fck,
2688 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2586 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2689 .enable_bit = OMAP3430_EN_WDT3_SHIFT, 2587 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2690 .flags = CLOCK_IN_OMAP343X,
2691 .clkdm_name = "per_clkdm", 2588 .clkdm_name = "per_clkdm",
2692 .recalc = &followparent_recalc, 2589 .recalc = &followparent_recalc,
2693}; 2590};
@@ -2696,7 +2593,7 @@ static struct clk per_l4_ick = {
2696 .name = "per_l4_ick", 2593 .name = "per_l4_ick",
2697 .ops = &clkops_null, 2594 .ops = &clkops_null,
2698 .parent = &l4_ick, 2595 .parent = &l4_ick,
2699 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 2596 .flags = RATE_PROPAGATES,
2700 .clkdm_name = "per_clkdm", 2597 .clkdm_name = "per_clkdm",
2701 .recalc = &followparent_recalc, 2598 .recalc = &followparent_recalc,
2702}; 2599};
@@ -2707,7 +2604,6 @@ static struct clk gpio6_ick = {
2707 .parent = &per_l4_ick, 2604 .parent = &per_l4_ick,
2708 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2605 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2709 .enable_bit = OMAP3430_EN_GPIO6_SHIFT, 2606 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2710 .flags = CLOCK_IN_OMAP343X,
2711 .clkdm_name = "per_clkdm", 2607 .clkdm_name = "per_clkdm",
2712 .recalc = &followparent_recalc, 2608 .recalc = &followparent_recalc,
2713}; 2609};
@@ -2718,7 +2614,6 @@ static struct clk gpio5_ick = {
2718 .parent = &per_l4_ick, 2614 .parent = &per_l4_ick,
2719 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2615 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2720 .enable_bit = OMAP3430_EN_GPIO5_SHIFT, 2616 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2721 .flags = CLOCK_IN_OMAP343X,
2722 .clkdm_name = "per_clkdm", 2617 .clkdm_name = "per_clkdm",
2723 .recalc = &followparent_recalc, 2618 .recalc = &followparent_recalc,
2724}; 2619};
@@ -2729,7 +2624,6 @@ static struct clk gpio4_ick = {
2729 .parent = &per_l4_ick, 2624 .parent = &per_l4_ick,
2730 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2625 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2731 .enable_bit = OMAP3430_EN_GPIO4_SHIFT, 2626 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2732 .flags = CLOCK_IN_OMAP343X,
2733 .clkdm_name = "per_clkdm", 2627 .clkdm_name = "per_clkdm",
2734 .recalc = &followparent_recalc, 2628 .recalc = &followparent_recalc,
2735}; 2629};
@@ -2740,7 +2634,6 @@ static struct clk gpio3_ick = {
2740 .parent = &per_l4_ick, 2634 .parent = &per_l4_ick,
2741 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2635 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2742 .enable_bit = OMAP3430_EN_GPIO3_SHIFT, 2636 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2743 .flags = CLOCK_IN_OMAP343X,
2744 .clkdm_name = "per_clkdm", 2637 .clkdm_name = "per_clkdm",
2745 .recalc = &followparent_recalc, 2638 .recalc = &followparent_recalc,
2746}; 2639};
@@ -2751,7 +2644,6 @@ static struct clk gpio2_ick = {
2751 .parent = &per_l4_ick, 2644 .parent = &per_l4_ick,
2752 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2645 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2753 .enable_bit = OMAP3430_EN_GPIO2_SHIFT, 2646 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2754 .flags = CLOCK_IN_OMAP343X,
2755 .clkdm_name = "per_clkdm", 2647 .clkdm_name = "per_clkdm",
2756 .recalc = &followparent_recalc, 2648 .recalc = &followparent_recalc,
2757}; 2649};
@@ -2762,7 +2654,6 @@ static struct clk wdt3_ick = {
2762 .parent = &per_l4_ick, 2654 .parent = &per_l4_ick,
2763 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2655 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2764 .enable_bit = OMAP3430_EN_WDT3_SHIFT, 2656 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2765 .flags = CLOCK_IN_OMAP343X,
2766 .clkdm_name = "per_clkdm", 2657 .clkdm_name = "per_clkdm",
2767 .recalc = &followparent_recalc, 2658 .recalc = &followparent_recalc,
2768}; 2659};
@@ -2773,7 +2664,6 @@ static struct clk uart3_ick = {
2773 .parent = &per_l4_ick, 2664 .parent = &per_l4_ick,
2774 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2665 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2775 .enable_bit = OMAP3430_EN_UART3_SHIFT, 2666 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2776 .flags = CLOCK_IN_OMAP343X,
2777 .clkdm_name = "per_clkdm", 2667 .clkdm_name = "per_clkdm",
2778 .recalc = &followparent_recalc, 2668 .recalc = &followparent_recalc,
2779}; 2669};
@@ -2784,7 +2674,6 @@ static struct clk gpt9_ick = {
2784 .parent = &per_l4_ick, 2674 .parent = &per_l4_ick,
2785 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2675 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2786 .enable_bit = OMAP3430_EN_GPT9_SHIFT, 2676 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2787 .flags = CLOCK_IN_OMAP343X,
2788 .clkdm_name = "per_clkdm", 2677 .clkdm_name = "per_clkdm",
2789 .recalc = &followparent_recalc, 2678 .recalc = &followparent_recalc,
2790}; 2679};
@@ -2795,7 +2684,6 @@ static struct clk gpt8_ick = {
2795 .parent = &per_l4_ick, 2684 .parent = &per_l4_ick,
2796 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2685 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2797 .enable_bit = OMAP3430_EN_GPT8_SHIFT, 2686 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2798 .flags = CLOCK_IN_OMAP343X,
2799 .clkdm_name = "per_clkdm", 2687 .clkdm_name = "per_clkdm",
2800 .recalc = &followparent_recalc, 2688 .recalc = &followparent_recalc,
2801}; 2689};
@@ -2806,7 +2694,6 @@ static struct clk gpt7_ick = {
2806 .parent = &per_l4_ick, 2694 .parent = &per_l4_ick,
2807 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2695 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2808 .enable_bit = OMAP3430_EN_GPT7_SHIFT, 2696 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2809 .flags = CLOCK_IN_OMAP343X,
2810 .clkdm_name = "per_clkdm", 2697 .clkdm_name = "per_clkdm",
2811 .recalc = &followparent_recalc, 2698 .recalc = &followparent_recalc,
2812}; 2699};
@@ -2817,7 +2704,6 @@ static struct clk gpt6_ick = {
2817 .parent = &per_l4_ick, 2704 .parent = &per_l4_ick,
2818 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2705 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2819 .enable_bit = OMAP3430_EN_GPT6_SHIFT, 2706 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2820 .flags = CLOCK_IN_OMAP343X,
2821 .clkdm_name = "per_clkdm", 2707 .clkdm_name = "per_clkdm",
2822 .recalc = &followparent_recalc, 2708 .recalc = &followparent_recalc,
2823}; 2709};
@@ -2828,7 +2714,6 @@ static struct clk gpt5_ick = {
2828 .parent = &per_l4_ick, 2714 .parent = &per_l4_ick,
2829 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2715 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2830 .enable_bit = OMAP3430_EN_GPT5_SHIFT, 2716 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2831 .flags = CLOCK_IN_OMAP343X,
2832 .clkdm_name = "per_clkdm", 2717 .clkdm_name = "per_clkdm",
2833 .recalc = &followparent_recalc, 2718 .recalc = &followparent_recalc,
2834}; 2719};
@@ -2839,7 +2724,6 @@ static struct clk gpt4_ick = {
2839 .parent = &per_l4_ick, 2724 .parent = &per_l4_ick,
2840 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2725 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2841 .enable_bit = OMAP3430_EN_GPT4_SHIFT, 2726 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2842 .flags = CLOCK_IN_OMAP343X,
2843 .clkdm_name = "per_clkdm", 2727 .clkdm_name = "per_clkdm",
2844 .recalc = &followparent_recalc, 2728 .recalc = &followparent_recalc,
2845}; 2729};
@@ -2850,7 +2734,6 @@ static struct clk gpt3_ick = {
2850 .parent = &per_l4_ick, 2734 .parent = &per_l4_ick,
2851 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2735 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2852 .enable_bit = OMAP3430_EN_GPT3_SHIFT, 2736 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2853 .flags = CLOCK_IN_OMAP343X,
2854 .clkdm_name = "per_clkdm", 2737 .clkdm_name = "per_clkdm",
2855 .recalc = &followparent_recalc, 2738 .recalc = &followparent_recalc,
2856}; 2739};
@@ -2861,7 +2744,6 @@ static struct clk gpt2_ick = {
2861 .parent = &per_l4_ick, 2744 .parent = &per_l4_ick,
2862 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2745 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2863 .enable_bit = OMAP3430_EN_GPT2_SHIFT, 2746 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2864 .flags = CLOCK_IN_OMAP343X,
2865 .clkdm_name = "per_clkdm", 2747 .clkdm_name = "per_clkdm",
2866 .recalc = &followparent_recalc, 2748 .recalc = &followparent_recalc,
2867}; 2749};
@@ -2873,7 +2755,6 @@ static struct clk mcbsp2_ick = {
2873 .parent = &per_l4_ick, 2755 .parent = &per_l4_ick,
2874 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2756 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2875 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, 2757 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2876 .flags = CLOCK_IN_OMAP343X,
2877 .clkdm_name = "per_clkdm", 2758 .clkdm_name = "per_clkdm",
2878 .recalc = &followparent_recalc, 2759 .recalc = &followparent_recalc,
2879}; 2760};
@@ -2885,7 +2766,6 @@ static struct clk mcbsp3_ick = {
2885 .parent = &per_l4_ick, 2766 .parent = &per_l4_ick,
2886 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2767 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2887 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, 2768 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2888 .flags = CLOCK_IN_OMAP343X,
2889 .clkdm_name = "per_clkdm", 2769 .clkdm_name = "per_clkdm",
2890 .recalc = &followparent_recalc, 2770 .recalc = &followparent_recalc,
2891}; 2771};
@@ -2897,7 +2777,6 @@ static struct clk mcbsp4_ick = {
2897 .parent = &per_l4_ick, 2777 .parent = &per_l4_ick,
2898 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2778 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2899 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, 2779 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2900 .flags = CLOCK_IN_OMAP343X,
2901 .clkdm_name = "per_clkdm", 2780 .clkdm_name = "per_clkdm",
2902 .recalc = &followparent_recalc, 2781 .recalc = &followparent_recalc,
2903}; 2782};
@@ -2918,7 +2797,6 @@ static struct clk mcbsp2_fck = {
2918 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), 2797 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2919 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, 2798 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2920 .clksel = mcbsp_234_clksel, 2799 .clksel = mcbsp_234_clksel,
2921 .flags = CLOCK_IN_OMAP343X,
2922 .clkdm_name = "per_clkdm", 2800 .clkdm_name = "per_clkdm",
2923 .recalc = &omap2_clksel_recalc, 2801 .recalc = &omap2_clksel_recalc,
2924}; 2802};
@@ -2933,7 +2811,6 @@ static struct clk mcbsp3_fck = {
2933 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), 2811 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2934 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, 2812 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2935 .clksel = mcbsp_234_clksel, 2813 .clksel = mcbsp_234_clksel,
2936 .flags = CLOCK_IN_OMAP343X,
2937 .clkdm_name = "per_clkdm", 2814 .clkdm_name = "per_clkdm",
2938 .recalc = &omap2_clksel_recalc, 2815 .recalc = &omap2_clksel_recalc,
2939}; 2816};
@@ -2948,7 +2825,6 @@ static struct clk mcbsp4_fck = {
2948 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), 2825 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2949 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, 2826 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2950 .clksel = mcbsp_234_clksel, 2827 .clksel = mcbsp_234_clksel,
2951 .flags = CLOCK_IN_OMAP343X,
2952 .clkdm_name = "per_clkdm", 2828 .clkdm_name = "per_clkdm",
2953 .recalc = &omap2_clksel_recalc, 2829 .recalc = &omap2_clksel_recalc,
2954}; 2830};
@@ -2997,7 +2873,7 @@ static struct clk emu_src_ck = {
2997 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2873 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2998 .clksel_mask = OMAP3430_MUX_CTRL_MASK, 2874 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2999 .clksel = emu_src_clksel, 2875 .clksel = emu_src_clksel,
3000 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 2876 .flags = RATE_PROPAGATES,
3001 .clkdm_name = "emu_clkdm", 2877 .clkdm_name = "emu_clkdm",
3002 .recalc = &omap2_clksel_recalc, 2878 .recalc = &omap2_clksel_recalc,
3003}; 2879};
@@ -3022,7 +2898,7 @@ static struct clk pclk_fck = {
3022 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2898 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3023 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, 2899 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
3024 .clksel = pclk_emu_clksel, 2900 .clksel = pclk_emu_clksel,
3025 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 2901 .flags = RATE_PROPAGATES,
3026 .clkdm_name = "emu_clkdm", 2902 .clkdm_name = "emu_clkdm",
3027 .recalc = &omap2_clksel_recalc, 2903 .recalc = &omap2_clksel_recalc,
3028}; 2904};
@@ -3046,7 +2922,7 @@ static struct clk pclkx2_fck = {
3046 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2922 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3047 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, 2923 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
3048 .clksel = pclkx2_emu_clksel, 2924 .clksel = pclkx2_emu_clksel,
3049 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 2925 .flags = RATE_PROPAGATES,
3050 .clkdm_name = "emu_clkdm", 2926 .clkdm_name = "emu_clkdm",
3051 .recalc = &omap2_clksel_recalc, 2927 .recalc = &omap2_clksel_recalc,
3052}; 2928};
@@ -3063,7 +2939,7 @@ static struct clk atclk_fck = {
3063 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2939 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3064 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, 2940 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
3065 .clksel = atclk_emu_clksel, 2941 .clksel = atclk_emu_clksel,
3066 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 2942 .flags = RATE_PROPAGATES,
3067 .clkdm_name = "emu_clkdm", 2943 .clkdm_name = "emu_clkdm",
3068 .recalc = &omap2_clksel_recalc, 2944 .recalc = &omap2_clksel_recalc,
3069}; 2945};
@@ -3075,7 +2951,7 @@ static struct clk traceclk_src_fck = {
3075 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2951 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3076 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, 2952 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
3077 .clksel = emu_src_clksel, 2953 .clksel = emu_src_clksel,
3078 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 2954 .flags = RATE_PROPAGATES,
3079 .clkdm_name = "emu_clkdm", 2955 .clkdm_name = "emu_clkdm",
3080 .recalc = &omap2_clksel_recalc, 2956 .recalc = &omap2_clksel_recalc,
3081}; 2957};
@@ -3099,7 +2975,6 @@ static struct clk traceclk_fck = {
3099 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2975 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3100 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, 2976 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
3101 .clksel = traceclk_clksel, 2977 .clksel = traceclk_clksel,
3102 .flags = CLOCK_IN_OMAP343X,
3103 .clkdm_name = "emu_clkdm", 2978 .clkdm_name = "emu_clkdm",
3104 .recalc = &omap2_clksel_recalc, 2979 .recalc = &omap2_clksel_recalc,
3105}; 2980};
@@ -3113,7 +2988,7 @@ static struct clk sr1_fck = {
3113 .parent = &sys_ck, 2988 .parent = &sys_ck,
3114 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2989 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3115 .enable_bit = OMAP3430_EN_SR1_SHIFT, 2990 .enable_bit = OMAP3430_EN_SR1_SHIFT,
3116 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 2991 .flags = RATE_PROPAGATES,
3117 .recalc = &followparent_recalc, 2992 .recalc = &followparent_recalc,
3118}; 2993};
3119 2994
@@ -3124,7 +2999,7 @@ static struct clk sr2_fck = {
3124 .parent = &sys_ck, 2999 .parent = &sys_ck,
3125 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 3000 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3126 .enable_bit = OMAP3430_EN_SR2_SHIFT, 3001 .enable_bit = OMAP3430_EN_SR2_SHIFT,
3127 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 3002 .flags = RATE_PROPAGATES,
3128 .recalc = &followparent_recalc, 3003 .recalc = &followparent_recalc,
3129}; 3004};
3130 3005
@@ -3132,7 +3007,6 @@ static struct clk sr_l4_ick = {
3132 .name = "sr_l4_ick", 3007 .name = "sr_l4_ick",
3133 .ops = &clkops_null, /* RMK: missing? */ 3008 .ops = &clkops_null, /* RMK: missing? */
3134 .parent = &l4_ick, 3009 .parent = &l4_ick,
3135 .flags = CLOCK_IN_OMAP343X,
3136 .clkdm_name = "core_l4_clkdm", 3010 .clkdm_name = "core_l4_clkdm",
3137 .recalc = &followparent_recalc, 3011 .recalc = &followparent_recalc,
3138}; 3012};
@@ -3144,7 +3018,6 @@ static struct clk gpt12_fck = {
3144 .name = "gpt12_fck", 3018 .name = "gpt12_fck",
3145 .ops = &clkops_null, 3019 .ops = &clkops_null,
3146 .parent = &secure_32k_fck, 3020 .parent = &secure_32k_fck,
3147 .flags = CLOCK_IN_OMAP343X,
3148 .recalc = &followparent_recalc, 3021 .recalc = &followparent_recalc,
3149}; 3022};
3150 3023
@@ -3152,223 +3025,7 @@ static struct clk wdt1_fck = {
3152 .name = "wdt1_fck", 3025 .name = "wdt1_fck",
3153 .ops = &clkops_null, 3026 .ops = &clkops_null,
3154 .parent = &secure_32k_fck, 3027 .parent = &secure_32k_fck,
3155 .flags = CLOCK_IN_OMAP343X, 3028 .recalc = &followparent_recalc,
3156 .recalc = &followparent_recalc,
3157};
3158
3159static struct clk *onchip_34xx_clks[] __initdata = {
3160 &omap_32k_fck,
3161 &virt_12m_ck,
3162 &virt_13m_ck,
3163 &virt_16_8m_ck,
3164 &virt_19_2m_ck,
3165 &virt_26m_ck,
3166 &virt_38_4m_ck,
3167 &osc_sys_ck,
3168 &sys_ck,
3169 &sys_altclk,
3170 &mcbsp_clks,
3171 &sys_clkout1,
3172 &dpll1_ck,
3173 &dpll1_x2_ck,
3174 &dpll1_x2m2_ck,
3175 &dpll2_ck,
3176 &dpll2_m2_ck,
3177 &dpll3_ck,
3178 &core_ck,
3179 &dpll3_x2_ck,
3180 &dpll3_m2_ck,
3181 &dpll3_m2x2_ck,
3182 &dpll3_m3_ck,
3183 &dpll3_m3x2_ck,
3184 &emu_core_alwon_ck,
3185 &dpll4_ck,
3186 &dpll4_x2_ck,
3187 &omap_96m_alwon_fck,
3188 &omap_96m_fck,
3189 &cm_96m_fck,
3190 &virt_omap_54m_fck,
3191 &omap_54m_fck,
3192 &omap_48m_fck,
3193 &omap_12m_fck,
3194 &dpll4_m2_ck,
3195 &dpll4_m2x2_ck,
3196 &dpll4_m3_ck,
3197 &dpll4_m3x2_ck,
3198 &dpll4_m4_ck,
3199 &dpll4_m4x2_ck,
3200 &dpll4_m5_ck,
3201 &dpll4_m5x2_ck,
3202 &dpll4_m6_ck,
3203 &dpll4_m6x2_ck,
3204 &emu_per_alwon_ck,
3205 &dpll5_ck,
3206 &dpll5_m2_ck,
3207 &omap_120m_fck,
3208 &clkout2_src_ck,
3209 &sys_clkout2,
3210 &corex2_fck,
3211 &dpll1_fck,
3212 &mpu_ck,
3213 &arm_fck,
3214 &emu_mpu_alwon_ck,
3215 &dpll2_fck,
3216 &iva2_ck,
3217 &l3_ick,
3218 &l4_ick,
3219 &rm_ick,
3220 &gfx_l3_ck,
3221 &gfx_l3_fck,
3222 &gfx_l3_ick,
3223 &gfx_cg1_ck,
3224 &gfx_cg2_ck,
3225 &sgx_fck,
3226 &sgx_ick,
3227 &d2d_26m_fck,
3228 &gpt10_fck,
3229 &gpt11_fck,
3230 &cpefuse_fck,
3231 &ts_fck,
3232 &usbtll_fck,
3233 &core_96m_fck,
3234 &mmchs3_fck,
3235 &mmchs2_fck,
3236 &mspro_fck,
3237 &mmchs1_fck,
3238 &i2c3_fck,
3239 &i2c2_fck,
3240 &i2c1_fck,
3241 &mcbsp5_fck,
3242 &mcbsp1_fck,
3243 &core_48m_fck,
3244 &mcspi4_fck,
3245 &mcspi3_fck,
3246 &mcspi2_fck,
3247 &mcspi1_fck,
3248 &uart2_fck,
3249 &uart1_fck,
3250 &fshostusb_fck,
3251 &core_12m_fck,
3252 &hdq_fck,
3253 &ssi_ssr_fck,
3254 &ssi_sst_fck,
3255 &core_l3_ick,
3256 &hsotgusb_ick,
3257 &sdrc_ick,
3258 &gpmc_fck,
3259 &security_l3_ick,
3260 &pka_ick,
3261 &core_l4_ick,
3262 &usbtll_ick,
3263 &mmchs3_ick,
3264 &icr_ick,
3265 &aes2_ick,
3266 &sha12_ick,
3267 &des2_ick,
3268 &mmchs2_ick,
3269 &mmchs1_ick,
3270 &mspro_ick,
3271 &hdq_ick,
3272 &mcspi4_ick,
3273 &mcspi3_ick,
3274 &mcspi2_ick,
3275 &mcspi1_ick,
3276 &i2c3_ick,
3277 &i2c2_ick,
3278 &i2c1_ick,
3279 &uart2_ick,
3280 &uart1_ick,
3281 &gpt11_ick,
3282 &gpt10_ick,
3283 &mcbsp5_ick,
3284 &mcbsp1_ick,
3285 &fac_ick,
3286 &mailboxes_ick,
3287 &omapctrl_ick,
3288 &ssi_l4_ick,
3289 &ssi_ick,
3290 &usb_l4_ick,
3291 &security_l4_ick2,
3292 &aes1_ick,
3293 &rng_ick,
3294 &sha11_ick,
3295 &des1_ick,
3296 &dss1_alwon_fck,
3297 &dss_tv_fck,
3298 &dss_96m_fck,
3299 &dss2_alwon_fck,
3300 &dss_ick,
3301 &cam_mclk,
3302 &cam_ick,
3303 &usbhost_120m_fck,
3304 &usbhost_48m_fck,
3305 &usbhost_ick,
3306 &usbhost_sar_fck,
3307 &usim_fck,
3308 &gpt1_fck,
3309 &wkup_32k_fck,
3310 &gpio1_dbck,
3311 &wdt2_fck,
3312 &wkup_l4_ick,
3313 &usim_ick,
3314 &wdt2_ick,
3315 &wdt1_ick,
3316 &gpio1_ick,
3317 &omap_32ksync_ick,
3318 &gpt12_ick,
3319 &gpt1_ick,
3320 &per_96m_fck,
3321 &per_48m_fck,
3322 &uart3_fck,
3323 &gpt2_fck,
3324 &gpt3_fck,
3325 &gpt4_fck,
3326 &gpt5_fck,
3327 &gpt6_fck,
3328 &gpt7_fck,
3329 &gpt8_fck,
3330 &gpt9_fck,
3331 &per_32k_alwon_fck,
3332 &gpio6_dbck,
3333 &gpio5_dbck,
3334 &gpio4_dbck,
3335 &gpio3_dbck,
3336 &gpio2_dbck,
3337 &wdt3_fck,
3338 &per_l4_ick,
3339 &gpio6_ick,
3340 &gpio5_ick,
3341 &gpio4_ick,
3342 &gpio3_ick,
3343 &gpio2_ick,
3344 &wdt3_ick,
3345 &uart3_ick,
3346 &gpt9_ick,
3347 &gpt8_ick,
3348 &gpt7_ick,
3349 &gpt6_ick,
3350 &gpt5_ick,
3351 &gpt4_ick,
3352 &gpt3_ick,
3353 &gpt2_ick,
3354 &mcbsp2_ick,
3355 &mcbsp3_ick,
3356 &mcbsp4_ick,
3357 &mcbsp2_fck,
3358 &mcbsp3_fck,
3359 &mcbsp4_fck,
3360 &emu_src_ck,
3361 &pclk_fck,
3362 &pclkx2_fck,
3363 &atclk_fck,
3364 &traceclk_src_fck,
3365 &traceclk_fck,
3366 &sr1_fck,
3367 &sr2_fck,
3368 &sr_l4_ick,
3369 &secure_32k_fck,
3370 &gpt12_fck,
3371 &wdt1_fck,
3372}; 3029};
3373 3030
3374#endif 3031#endif
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 90372131055b..e25e1ac64fc1 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -21,6 +21,7 @@ config ARCH_OMAP2
21config ARCH_OMAP3 21config ARCH_OMAP3
22 bool "TI OMAP3" 22 bool "TI OMAP3"
23 select CPU_V7 23 select CPU_V7
24 select COMMON_CLKDEV
24 25
25endchoice 26endchoice
26 27
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index 214dc46d6ad1..3895ba729792 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -136,10 +136,7 @@ extern const struct clkops clkops_null;
136#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ 136#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
137#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ 137#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
138#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ 138#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
139/* bits 13-26 are currently free */ 139/* bits 13-31 are currently free */
140#define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */
141#define CLOCK_IN_OMAP3430ES1 (1 << 29) /* 3430ES1 clocks only */
142#define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2 clocks only */
143 140
144/* Clksel_rate flags */ 141/* Clksel_rate flags */
145#define DEFAULT_RATE (1 << 0) 142#define DEFAULT_RATE (1 << 0)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 17:00:47 -0500