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-rw-r--r--arch/arm/mach-ux500/devices-db8500.c12
-rw-r--r--arch/arm/plat-nomadik/include/plat/ste_dma40.h60
2 files changed, 22 insertions, 50 deletions
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 58b3e723b183..c04bf2b61dcd 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -132,35 +132,25 @@ static struct resource dma40_resources[] = {
132 132
133/* Default configuration for physcial memcpy */ 133/* Default configuration for physcial memcpy */
134struct stedma40_chan_cfg dma40_memcpy_conf_phy = { 134struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
135 .channel_type = (STEDMA40_CHANNEL_IN_PHY_MODE | 135 .mode = STEDMA40_MODE_PHYSICAL,
136 STEDMA40_LOW_PRIORITY_CHANNEL |
137 STEDMA40_PCHAN_BASIC_MODE),
138 .dir = STEDMA40_MEM_TO_MEM, 136 .dir = STEDMA40_MEM_TO_MEM,
139 137
140 .src_info.endianess = STEDMA40_LITTLE_ENDIAN,
141 .src_info.data_width = STEDMA40_BYTE_WIDTH, 138 .src_info.data_width = STEDMA40_BYTE_WIDTH,
142 .src_info.psize = STEDMA40_PSIZE_PHY_1, 139 .src_info.psize = STEDMA40_PSIZE_PHY_1,
143 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, 140 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
144 141
145 .dst_info.endianess = STEDMA40_LITTLE_ENDIAN,
146 .dst_info.data_width = STEDMA40_BYTE_WIDTH, 142 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
147 .dst_info.psize = STEDMA40_PSIZE_PHY_1, 143 .dst_info.psize = STEDMA40_PSIZE_PHY_1,
148 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, 144 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
149}; 145};
150/* Default configuration for logical memcpy */ 146/* Default configuration for logical memcpy */
151struct stedma40_chan_cfg dma40_memcpy_conf_log = { 147struct stedma40_chan_cfg dma40_memcpy_conf_log = {
152 .channel_type = (STEDMA40_CHANNEL_IN_LOG_MODE |
153 STEDMA40_LOW_PRIORITY_CHANNEL |
154 STEDMA40_LCHAN_SRC_LOG_DST_LOG |
155 STEDMA40_NO_TIM_FOR_LINK),
156 .dir = STEDMA40_MEM_TO_MEM, 148 .dir = STEDMA40_MEM_TO_MEM,
157 149
158 .src_info.endianess = STEDMA40_LITTLE_ENDIAN,
159 .src_info.data_width = STEDMA40_BYTE_WIDTH, 150 .src_info.data_width = STEDMA40_BYTE_WIDTH,
160 .src_info.psize = STEDMA40_PSIZE_LOG_1, 151 .src_info.psize = STEDMA40_PSIZE_LOG_1,
161 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, 152 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
162 153
163 .dst_info.endianess = STEDMA40_LITTLE_ENDIAN,
164 .dst_info.data_width = STEDMA40_BYTE_WIDTH, 154 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
165 .dst_info.psize = STEDMA40_PSIZE_LOG_1, 155 .dst_info.psize = STEDMA40_PSIZE_LOG_1,
166 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, 156 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
diff --git a/arch/arm/plat-nomadik/include/plat/ste_dma40.h b/arch/arm/plat-nomadik/include/plat/ste_dma40.h
index 3dd42551de04..da1f08ff9ee2 100644
--- a/arch/arm/plat-nomadik/include/plat/ste_dma40.h
+++ b/arch/arm/plat-nomadik/include/plat/ste_dma40.h
@@ -18,37 +18,20 @@
18#define STEDMA40_DEV_DST_MEMORY (-1) 18#define STEDMA40_DEV_DST_MEMORY (-1)
19#define STEDMA40_DEV_SRC_MEMORY (-1) 19#define STEDMA40_DEV_SRC_MEMORY (-1)
20 20
21/* 21enum stedma40_mode {
22 * Description of bitfields of channel_type variable is available in 22 STEDMA40_MODE_LOGICAL = 0,
23 * the info structure. 23 STEDMA40_MODE_PHYSICAL,
24 */ 24 STEDMA40_MODE_OPERATION,
25};
25 26
26/* Priority */ 27enum stedma40_mode_opt {
27#define STEDMA40_INFO_PRIO_TYPE_POS 2 28 STEDMA40_PCHAN_BASIC_MODE = 0,
28#define STEDMA40_HIGH_PRIORITY_CHANNEL (0x1 << STEDMA40_INFO_PRIO_TYPE_POS) 29 STEDMA40_LCHAN_SRC_LOG_DST_LOG = 0,
29#define STEDMA40_LOW_PRIORITY_CHANNEL (0x2 << STEDMA40_INFO_PRIO_TYPE_POS) 30 STEDMA40_PCHAN_MODULO_MODE,
30 31 STEDMA40_PCHAN_DOUBLE_DST_MODE,
31/* Mode */ 32 STEDMA40_LCHAN_SRC_PHY_DST_LOG,
32#define STEDMA40_INFO_CH_MODE_TYPE_POS 6 33 STEDMA40_LCHAN_SRC_LOG_DST_PHY,
33#define STEDMA40_CHANNEL_IN_PHY_MODE (0x1 << STEDMA40_INFO_CH_MODE_TYPE_POS) 34};
34#define STEDMA40_CHANNEL_IN_LOG_MODE (0x2 << STEDMA40_INFO_CH_MODE_TYPE_POS)
35#define STEDMA40_CHANNEL_IN_OPER_MODE (0x3 << STEDMA40_INFO_CH_MODE_TYPE_POS)
36
37/* Mode options */
38#define STEDMA40_INFO_CH_MODE_OPT_POS 8
39#define STEDMA40_PCHAN_BASIC_MODE (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS)
40#define STEDMA40_PCHAN_MODULO_MODE (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS)
41#define STEDMA40_PCHAN_DOUBLE_DST_MODE (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS)
42#define STEDMA40_LCHAN_SRC_PHY_DST_LOG (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS)
43#define STEDMA40_LCHAN_SRC_LOG_DST_PHS (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS)
44#define STEDMA40_LCHAN_SRC_LOG_DST_LOG (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS)
45
46/* Interrupt */
47#define STEDMA40_INFO_TIM_POS 10
48#define STEDMA40_NO_TIM_FOR_LINK (0x0 << STEDMA40_INFO_TIM_POS)
49#define STEDMA40_TIM_FOR_LINK (0x1 << STEDMA40_INFO_TIM_POS)
50
51/* End of channel_type configuration */
52 35
53#define STEDMA40_ESIZE_8_BIT 0x0 36#define STEDMA40_ESIZE_8_BIT 0x0
54#define STEDMA40_ESIZE_16_BIT 0x1 37#define STEDMA40_ESIZE_16_BIT 0x1
@@ -79,11 +62,6 @@ enum stedma40_flow_ctrl {
79 STEDMA40_FLOW_CTRL, 62 STEDMA40_FLOW_CTRL,
80}; 63};
81 64
82enum stedma40_endianess {
83 STEDMA40_LITTLE_ENDIAN,
84 STEDMA40_BIG_ENDIAN
85};
86
87enum stedma40_periph_data_width { 65enum stedma40_periph_data_width {
88 STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT, 66 STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
89 STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT, 67 STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
@@ -102,13 +80,13 @@ enum stedma40_xfer_dir {
102/** 80/**
103 * struct stedma40_chan_cfg - dst/src channel configuration 81 * struct stedma40_chan_cfg - dst/src channel configuration
104 * 82 *
105 * @endianess: Endianess of the src/dst hardware 83 * @big_endian: true if the src/dst should be read as big endian
106 * @data_width: Data width of the src/dst hardware 84 * @data_width: Data width of the src/dst hardware
107 * @p_size: Burst size 85 * @p_size: Burst size
108 * @flow_ctrl: Flow control on/off. 86 * @flow_ctrl: Flow control on/off.
109 */ 87 */
110struct stedma40_half_channel_info { 88struct stedma40_half_channel_info {
111 enum stedma40_endianess endianess; 89 bool big_endian;
112 enum stedma40_periph_data_width data_width; 90 enum stedma40_periph_data_width data_width;
113 int psize; 91 int psize;
114 enum stedma40_flow_ctrl flow_ctrl; 92 enum stedma40_flow_ctrl flow_ctrl;
@@ -118,7 +96,9 @@ struct stedma40_half_channel_info {
118 * struct stedma40_chan_cfg - Structure to be filled by client drivers. 96 * struct stedma40_chan_cfg - Structure to be filled by client drivers.
119 * 97 *
120 * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH 98 * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
121 * @channel_type: priority, mode, mode options and interrupt configuration. 99 * @high_priority: true if high-priority
100 * @mode: channel mode: physical, logical, or operation
101 * @mode_opt: options for the chosen channel mode
122 * @src_dev_type: Src device type 102 * @src_dev_type: Src device type
123 * @dst_dev_type: Dst device type 103 * @dst_dev_type: Dst device type
124 * @src_info: Parameters for dst half channel 104 * @src_info: Parameters for dst half channel
@@ -131,7 +111,9 @@ struct stedma40_half_channel_info {
131 */ 111 */
132struct stedma40_chan_cfg { 112struct stedma40_chan_cfg {
133 enum stedma40_xfer_dir dir; 113 enum stedma40_xfer_dir dir;
134 unsigned int channel_type; 114 bool high_priority;
115 enum stedma40_mode mode;
116 enum stedma40_mode_opt mode_opt;
135 int src_dev_type; 117 int src_dev_type;
136 int dst_dev_type; 118 int dst_dev_type;
137 struct stedma40_half_channel_info src_info; 119 struct stedma40_half_channel_info src_info;