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-rw-r--r--arch/arm/Kconfig.debug101
-rw-r--r--arch/arm/boot/compressed/head.S39
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi9
-rw-r--r--arch/arm/boot/dts/exynos4x12.dtsi14
-rw-r--r--arch/arm/configs/iop32x_defconfig1
-rw-r--r--arch/arm/configs/iop33x_defconfig1
-rw-r--r--arch/arm/configs/ixp4xx_defconfig1
-rw-r--r--arch/arm/configs/lpc32xx_defconfig1
-rw-r--r--arch/arm/configs/mv78xx0_defconfig1
-rw-r--r--arch/arm/configs/orion5x_defconfig1
-rw-r--r--arch/arm/configs/rpc_defconfig1
-rw-r--r--arch/arm/include/asm/outercache.h3
-rw-r--r--arch/arm/include/debug/ks8695.S (renamed from arch/arm/mach-ks8695/include/mach/debug-macro.S)10
-rw-r--r--arch/arm/include/debug/netx.S (renamed from arch/arm/mach-netx/include/mach/debug-macro.S)22
-rw-r--r--arch/arm/include/uapi/asm/unistd.h1
-rw-r--r--arch/arm/kernel/calls.S1
-rw-r--r--arch/arm/kernel/entry-header.S13
-rw-r--r--arch/arm/kernel/entry-v7m.S2
-rw-r--r--arch/arm/kernel/irq.c3
-rw-r--r--arch/arm/kernel/perf_event.c10
-rw-r--r--arch/arm/kernel/setup.c7
-rw-r--r--arch/arm/mach-exynos/firmware.c50
-rw-r--r--arch/arm/mach-exynos/sleep.S46
-rw-r--r--arch/arm/mach-omap1/include/mach/debug-macro.S101
-rw-r--r--arch/arm/mach-omap2/board-generic.c6
-rw-r--r--arch/arm/mach-omap2/common.h8
-rw-r--r--arch/arm/mach-omap2/omap4-common.c16
-rw-r--r--arch/arm/mach-sa1100/Makefile2
-rw-r--r--arch/arm/mach-sa1100/clock.c12
-rw-r--r--arch/arm/mach-sa1100/collie.c3
-rw-r--r--arch/arm/mach-sa1100/generic.c6
-rw-r--r--arch/arm/mach-sa1100/include/mach/irqs.h73
-rw-r--r--arch/arm/mach-sa1100/irq.c203
-rw-r--r--arch/arm/mach-sa1100/pm.c1
-rw-r--r--arch/arm/mach-sa1100/time.c139
-rw-r--r--arch/arm/mm/Kconfig1
-rw-r--r--arch/arm/mm/cache-l2x0.c439
-rw-r--r--arch/arm/mm/context.c26
-rw-r--r--arch/arm/mm/dma-mapping.c3
-rw-r--r--arch/arm/mm/dump.c9
-rw-r--r--arch/arm/mm/init.c4
-rw-r--r--arch/arm/mm/mmu.c4
42 files changed, 617 insertions, 777 deletions
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 5ddd4906f7a7..a324ecdfeb21 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -397,6 +397,13 @@ choice
397 Say Y here if you want the debug print routines to direct 397 Say Y here if you want the debug print routines to direct
398 their output to UART1 serial port on KEYSTONE2 devices. 398 their output to UART1 serial port on KEYSTONE2 devices.
399 399
400 config DEBUG_KS8695_UART
401 bool "KS8695 Debug UART"
402 depends on ARCH_KS8695
403 help
404 Say Y here if you want kernel low-level debugging support
405 on KS8695.
406
400 config DEBUG_MESON_UARTAO 407 config DEBUG_MESON_UARTAO
401 bool "Kernel low-level debugging via Meson6 UARTAO" 408 bool "Kernel low-level debugging via Meson6 UARTAO"
402 depends on ARCH_MESON 409 depends on ARCH_MESON
@@ -496,6 +503,13 @@ choice
496 Say Y here if you want kernel low-level debugging support 503 Say Y here if you want kernel low-level debugging support
497 on Vybrid based platforms. 504 on Vybrid based platforms.
498 505
506 config DEBUG_NETX_UART
507 bool "Kernel low-level debugging messages via NetX UART"
508 depends on ARCH_NETX
509 help
510 Say Y here if you want kernel low-level debugging support
511 on Hilscher NetX based platforms.
512
499 config DEBUG_NOMADIK_UART 513 config DEBUG_NOMADIK_UART
500 bool "Kernel low-level debugging messages via NOMADIK UART" 514 bool "Kernel low-level debugging messages via NOMADIK UART"
501 depends on ARCH_NOMADIK 515 depends on ARCH_NOMADIK
@@ -520,6 +534,30 @@ choice
520 Say Y here if you want kernel low-level debugging support 534 Say Y here if you want kernel low-level debugging support
521 on TI-NSPIRE CX models. 535 on TI-NSPIRE CX models.
522 536
537 config DEBUG_OMAP1UART1
538 bool "Kernel low-level debugging via OMAP1 UART1"
539 depends on ARCH_OMAP1
540 select DEBUG_UART_8250
541 help
542 Say Y here if you want kernel low-level debugging support
543 on OMAP1 based platforms (except OMAP730) on the UART1.
544
545 config DEBUG_OMAP1UART2
546 bool "Kernel low-level debugging via OMAP1 UART2"
547 depends on ARCH_OMAP1
548 select DEBUG_UART_8250
549 help
550 Say Y here if you want kernel low-level debugging support
551 on OMAP1 based platforms (except OMAP730) on the UART2.
552
553 config DEBUG_OMAP1UART3
554 bool "Kernel low-level debugging via OMAP1 UART3"
555 depends on ARCH_OMAP1
556 select DEBUG_UART_8250
557 help
558 Say Y here if you want kernel low-level debugging support
559 on OMAP1 based platforms (except OMAP730) on the UART3.
560
523 config DEBUG_OMAP2UART1 561 config DEBUG_OMAP2UART1
524 bool "OMAP2/3/4 UART1 (omap2/3 sdp boards and some omap3 boards)" 562 bool "OMAP2/3/4 UART1 (omap2/3 sdp boards and some omap3 boards)"
525 depends on ARCH_OMAP2PLUS 563 depends on ARCH_OMAP2PLUS
@@ -562,6 +600,30 @@ choice
562 depends on ARCH_OMAP2PLUS 600 depends on ARCH_OMAP2PLUS
563 select DEBUG_OMAP2PLUS_UART 601 select DEBUG_OMAP2PLUS_UART
564 602
603 config DEBUG_OMAP7XXUART1
604 bool "Kernel low-level debugging via OMAP730 UART1"
605 depends on ARCH_OMAP730
606 select DEBUG_UART_8250
607 help
608 Say Y here if you want kernel low-level debugging support
609 on OMAP730 based platforms on the UART1.
610
611 config DEBUG_OMAP7XXUART2
612 bool "Kernel low-level debugging via OMAP730 UART2"
613 depends on ARCH_OMAP730
614 select DEBUG_UART_8250
615 help
616 Say Y here if you want kernel low-level debugging support
617 on OMAP730 based platforms on the UART2.
618
619 config DEBUG_OMAP7XXUART3
620 bool "Kernel low-level debugging via OMAP730 UART3"
621 depends on ARCH_OMAP730
622 select DEBUG_UART_8250
623 help
624 Say Y here if you want kernel low-level debugging support
625 on OMAP730 based platforms on the UART3.
626
565 config DEBUG_TI81XXUART1 627 config DEBUG_TI81XXUART1
566 bool "Kernel low-level debugging messages via TI81XX UART1 (ti8148evm)" 628 bool "Kernel low-level debugging messages via TI81XX UART1 (ti8148evm)"
567 depends on ARCH_OMAP2PLUS 629 depends on ARCH_OMAP2PLUS
@@ -1031,15 +1093,6 @@ choice
1031 This option selects UART0 on VIA/Wondermedia System-on-a-chip 1093 This option selects UART0 on VIA/Wondermedia System-on-a-chip
1032 devices, including VT8500, WM8505, WM8650 and WM8850. 1094 devices, including VT8500, WM8505, WM8650 and WM8850.
1033 1095
1034 config DEBUG_LL_UART_NONE
1035 bool "No low-level debugging UART"
1036 depends on !ARCH_MULTIPLATFORM
1037 help
1038 Say Y here if your platform doesn't provide a UART option
1039 above. This relies on your platform choosing the right UART
1040 definition internally in order for low-level debugging to
1041 work.
1042
1043 config DEBUG_ICEDCC 1096 config DEBUG_ICEDCC
1044 bool "Kernel low-level debugging via EmbeddedICE DCC channel" 1097 bool "Kernel low-level debugging via EmbeddedICE DCC channel"
1045 help 1098 help
@@ -1183,7 +1236,9 @@ config DEBUG_LL_INCLUDE
1183 DEBUG_IMX6Q_UART || \ 1236 DEBUG_IMX6Q_UART || \
1184 DEBUG_IMX6SL_UART || \ 1237 DEBUG_IMX6SL_UART || \
1185 DEBUG_IMX6SX_UART 1238 DEBUG_IMX6SX_UART
1239 default "debug/ks8695.S" if DEBUG_KS8695_UART
1186 default "debug/msm.S" if DEBUG_MSM_UART || DEBUG_QCOM_UARTDM 1240 default "debug/msm.S" if DEBUG_MSM_UART || DEBUG_QCOM_UARTDM
1241 default "debug/netx.S" if DEBUG_NETX_UART
1187 default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART 1242 default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
1188 default "debug/renesas-scif.S" if DEBUG_R7S72100_SCIF2 1243 default "debug/renesas-scif.S" if DEBUG_R7S72100_SCIF2
1189 default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF0 1244 default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF0
@@ -1208,12 +1263,7 @@ config DEBUG_LL_INCLUDE
1208 1263
1209# Compatibility options for PL01x 1264# Compatibility options for PL01x
1210config DEBUG_UART_PL01X 1265config DEBUG_UART_PL01X
1211 def_bool ARCH_EP93XX || \ 1266 bool
1212 ARCH_INTEGRATOR || \
1213 ARCH_SPEAR3XX || \
1214 ARCH_SPEAR6XX || \
1215 ARCH_SPEAR13XX || \
1216 ARCH_VERSATILE
1217 1267
1218# Compatibility options for 8250 1268# Compatibility options for 8250
1219config DEBUG_UART_8250 1269config DEBUG_UART_8250
@@ -1229,6 +1279,7 @@ config DEBUG_UART_BCM63XX
1229 1279
1230config DEBUG_UART_PHYS 1280config DEBUG_UART_PHYS
1231 hex "Physical base address of debug UART" 1281 hex "Physical base address of debug UART"
1282 default 0x00100a00 if DEBUG_NETX_UART
1232 default 0x01c20000 if DEBUG_DAVINCI_DMx_UART0 1283 default 0x01c20000 if DEBUG_DAVINCI_DMx_UART0
1233 default 0x01c28000 if DEBUG_SUNXI_UART0 1284 default 0x01c28000 if DEBUG_SUNXI_UART0
1234 default 0x01c28400 if DEBUG_SUNXI_UART1 1285 default 0x01c28400 if DEBUG_SUNXI_UART1
@@ -1269,7 +1320,6 @@ config DEBUG_UART_PHYS
1269 DEBUG_S3C2410_UART2) 1320 DEBUG_S3C2410_UART2)
1270 default 0x78000000 if DEBUG_CNS3XXX 1321 default 0x78000000 if DEBUG_CNS3XXX
1271 default 0x7c0003f8 if FOOTBRIDGE 1322 default 0x7c0003f8 if FOOTBRIDGE
1272 default 0x78000000 if DEBUG_CNS3XXX
1273 default 0x80010000 if DEBUG_ASM9260_UART 1323 default 0x80010000 if DEBUG_ASM9260_UART
1274 default 0x80070000 if DEBUG_IMX23_UART 1324 default 0x80070000 if DEBUG_IMX23_UART
1275 default 0x80074000 if DEBUG_IMX28_UART 1325 default 0x80074000 if DEBUG_IMX28_UART
@@ -1310,12 +1360,17 @@ config DEBUG_UART_PHYS
1310 default 0xffe40000 if DEBUG_RCAR_GEN1_SCIF0 1360 default 0xffe40000 if DEBUG_RCAR_GEN1_SCIF0
1311 default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2 1361 default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2
1312 default 0xfff36000 if DEBUG_HIGHBANK_UART 1362 default 0xfff36000 if DEBUG_HIGHBANK_UART
1363 default 0xfffb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1
1364 default 0xfffb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2
1365 default 0xfffb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3
1313 default 0xfffe8600 if DEBUG_UART_BCM63XX 1366 default 0xfffe8600 if DEBUG_UART_BCM63XX
1314 default 0xfffff700 if ARCH_IOP33X 1367 default 0xfffff700 if ARCH_IOP33X
1315 depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ 1368 depends on ARCH_EP93XX || \
1369 DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
1316 DEBUG_LL_UART_EFM32 || \ 1370 DEBUG_LL_UART_EFM32 || \
1317 DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \ 1371 DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
1318 DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \ 1372 DEBUG_MSM_UART || DEBUG_NETX_UART || \
1373 DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \
1319 DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \ 1374 DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \
1320 DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF2 || \ 1375 DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF2 || \
1321 DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \ 1376 DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \
@@ -1324,6 +1379,7 @@ config DEBUG_UART_PHYS
1324 1379
1325config DEBUG_UART_VIRT 1380config DEBUG_UART_VIRT
1326 hex "Virtual base address of debug UART" 1381 hex "Virtual base address of debug UART"
1382 default 0xe0000a00 if DEBUG_NETX_UART
1327 default 0xe0010fe0 if ARCH_RPC 1383 default 0xe0010fe0 if ARCH_RPC
1328 default 0xe1000000 if DEBUG_MSM_UART 1384 default 0xe1000000 if DEBUG_MSM_UART
1329 default 0xf0000be0 if ARCH_EBSA110 1385 default 0xf0000be0 if ARCH_EBSA110
@@ -1392,18 +1448,23 @@ config DEBUG_UART_VIRT
1392 default 0xfef00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN 1448 default 0xfef00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
1393 default 0xfef00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN 1449 default 0xfef00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
1394 default 0xfef36000 if DEBUG_HIGHBANK_UART 1450 default 0xfef36000 if DEBUG_HIGHBANK_UART
1451 default 0xfefb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1
1452 default 0xfefb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2
1453 default 0xfefb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3
1395 default 0xfefff700 if ARCH_IOP33X 1454 default 0xfefff700 if ARCH_IOP33X
1396 default 0xff003000 if DEBUG_U300_UART 1455 default 0xff003000 if DEBUG_U300_UART
1397 default DEBUG_UART_PHYS if !MMU 1456 default DEBUG_UART_PHYS if !MMU
1398 depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ 1457 depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
1399 DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \ 1458 DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
1400 DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \ 1459 DEBUG_MSM_UART || DEBUG_NETX_UART || \
1460 DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
1401 DEBUG_UART_BCM63XX || DEBUG_ASM9260_UART 1461 DEBUG_UART_BCM63XX || DEBUG_ASM9260_UART
1402 1462
1403config DEBUG_UART_8250_SHIFT 1463config DEBUG_UART_8250_SHIFT
1404 int "Register offset shift for the 8250 debug UART" 1464 int "Register offset shift for the 8250 debug UART"
1405 depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 1465 depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
1406 default 0 if FOOTBRIDGE || ARCH_IOP32X || DEBUG_BCM_5301X 1466 default 0 if FOOTBRIDGE || ARCH_IOP32X || DEBUG_BCM_5301X || \
1467 DEBUG_OMAP7XXUART1 || DEBUG_OMAP7XXUART2 || DEBUG_OMAP7XXUART3
1407 default 2 1468 default 2
1408 1469
1409config DEBUG_UART_8250_WORD 1470config DEBUG_UART_8250_WORD
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 9dff61479dff..c41a793b519c 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -263,16 +263,37 @@ restart: adr r0, LC0
263 * OK... Let's do some funky business here. 263 * OK... Let's do some funky business here.
264 * If we do have a DTB appended to zImage, and we do have 264 * If we do have a DTB appended to zImage, and we do have
265 * an ATAG list around, we want the later to be translated 265 * an ATAG list around, we want the later to be translated
266 * and folded into the former here. To be on the safe side, 266 * and folded into the former here. No GOT fixup has occurred
267 * let's temporarily move the stack away into the malloc 267 * yet, but none of the code we're about to call uses any
268 * area. No GOT fixup has occurred yet, but none of the 268 * global variable.
269 * code we're about to call uses any global variable.
270 */ 269 */
271 add sp, sp, #0x10000 270
271 /* Get the initial DTB size */
272 ldr r5, [r6, #4]
273#ifndef __ARMEB__
274 /* convert to little endian */
275 eor r1, r5, r5, ror #16
276 bic r1, r1, #0x00ff0000
277 mov r5, r5, ror #8
278 eor r5, r5, r1, lsr #8
279#endif
280 /* 50% DTB growth should be good enough */
281 add r5, r5, r5, lsr #1
282 /* preserve 64-bit alignment */
283 add r5, r5, #7
284 bic r5, r5, #7
285 /* clamp to 32KB min and 1MB max */
286 cmp r5, #(1 << 15)
287 movlo r5, #(1 << 15)
288 cmp r5, #(1 << 20)
289 movhi r5, #(1 << 20)
290 /* temporarily relocate the stack past the DTB work space */
291 add sp, sp, r5
292
272 stmfd sp!, {r0-r3, ip, lr} 293 stmfd sp!, {r0-r3, ip, lr}
273 mov r0, r8 294 mov r0, r8
274 mov r1, r6 295 mov r1, r6
275 sub r2, sp, r6 296 mov r2, r5
276 bl atags_to_fdt 297 bl atags_to_fdt
277 298
278 /* 299 /*
@@ -285,11 +306,11 @@ restart: adr r0, LC0
285 bic r0, r0, #1 306 bic r0, r0, #1
286 add r0, r0, #0x100 307 add r0, r0, #0x100
287 mov r1, r6 308 mov r1, r6
288 sub r2, sp, r6 309 mov r2, r5
289 bleq atags_to_fdt 310 bleq atags_to_fdt
290 311
291 ldmfd sp!, {r0-r3, ip, lr} 312 ldmfd sp!, {r0-r3, ip, lr}
292 sub sp, sp, #0x10000 313 sub sp, sp, r5
293#endif 314#endif
294 315
295 mov r8, r6 @ use the appended device tree 316 mov r8, r6 @ use the appended device tree
@@ -306,7 +327,7 @@ restart: adr r0, LC0
306 subs r1, r5, r1 327 subs r1, r5, r1
307 addhi r9, r9, r1 328 addhi r9, r9, r1
308 329
309 /* Get the dtb's size */ 330 /* Get the current DTB size */
310 ldr r5, [r6, #4] 331 ldr r5, [r6, #4]
311#ifndef __ARMEB__ 332#ifndef __ARMEB__
312 /* convert r5 (dtb size) to little endian */ 333 /* convert r5 (dtb size) to little endian */
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index bcc9e63c8070..8e45ea44317e 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -81,6 +81,15 @@
81 reg = <0x10023CA0 0x20>; 81 reg = <0x10023CA0 0x20>;
82 }; 82 };
83 83
84 l2c: l2-cache-controller@10502000 {
85 compatible = "arm,pl310-cache";
86 reg = <0x10502000 0x1000>;
87 cache-unified;
88 cache-level = <2>;
89 arm,tag-latency = <2 2 1>;
90 arm,data-latency = <2 2 1>;
91 };
92
84 gic: interrupt-controller@10490000 { 93 gic: interrupt-controller@10490000 {
85 cpu-offset = <0x8000>; 94 cpu-offset = <0x8000>;
86 }; 95 };
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 93b70402e943..8bc97c415c9a 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -54,6 +54,20 @@
54 reg = <0x10023CA0 0x20>; 54 reg = <0x10023CA0 0x20>;
55 }; 55 };
56 56
57 l2c: l2-cache-controller@10502000 {
58 compatible = "arm,pl310-cache";
59 reg = <0x10502000 0x1000>;
60 cache-unified;
61 cache-level = <2>;
62 arm,tag-latency = <2 2 1>;
63 arm,data-latency = <3 2 1>;
64 arm,double-linefill = <1>;
65 arm,double-linefill-incr = <0>;
66 arm,double-linefill-wrap = <1>;
67 arm,prefetch-drop = <1>;
68 arm,prefetch-offset = <7>;
69 };
70
57 clock: clock-controller@10030000 { 71 clock: clock-controller@10030000 {
58 compatible = "samsung,exynos4412-clock"; 72 compatible = "samsung,exynos4412-clock";
59 reg = <0x10030000 0x20000>; 73 reg = <0x10030000 0x20000>;
diff --git a/arch/arm/configs/iop32x_defconfig b/arch/arm/configs/iop32x_defconfig
index 4f2ec3ac138e..c3058da631da 100644
--- a/arch/arm/configs/iop32x_defconfig
+++ b/arch/arm/configs/iop32x_defconfig
@@ -106,6 +106,7 @@ CONFIG_MAGIC_SYSRQ=y
106CONFIG_DEBUG_KERNEL=y 106CONFIG_DEBUG_KERNEL=y
107CONFIG_DEBUG_USER=y 107CONFIG_DEBUG_USER=y
108CONFIG_DEBUG_LL=y 108CONFIG_DEBUG_LL=y
109CONFIG_DEBUG_LL_UART_8250=y
109CONFIG_KEYS=y 110CONFIG_KEYS=y
110CONFIG_KEYS_DEBUG_PROC_KEYS=y 111CONFIG_KEYS_DEBUG_PROC_KEYS=y
111CONFIG_CRYPTO_NULL=y 112CONFIG_CRYPTO_NULL=y
diff --git a/arch/arm/configs/iop33x_defconfig b/arch/arm/configs/iop33x_defconfig
index aa36128abca2..713faeee8cf4 100644
--- a/arch/arm/configs/iop33x_defconfig
+++ b/arch/arm/configs/iop33x_defconfig
@@ -87,5 +87,6 @@ CONFIG_DEBUG_KERNEL=y
87# CONFIG_RCU_CPU_STALL_DETECTOR is not set 87# CONFIG_RCU_CPU_STALL_DETECTOR is not set
88CONFIG_DEBUG_USER=y 88CONFIG_DEBUG_USER=y
89CONFIG_DEBUG_LL=y 89CONFIG_DEBUG_LL=y
90CONFIG_DEBUG_LL_UART_8250=y
90# CONFIG_CRYPTO_ANSI_CPRNG is not set 91# CONFIG_CRYPTO_ANSI_CPRNG is not set
91# CONFIG_CRC32 is not set 92# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig
index 1af665e847d1..24636cfdf6df 100644
--- a/arch/arm/configs/ixp4xx_defconfig
+++ b/arch/arm/configs/ixp4xx_defconfig
@@ -202,3 +202,4 @@ CONFIG_MAGIC_SYSRQ=y
202CONFIG_DEBUG_KERNEL=y 202CONFIG_DEBUG_KERNEL=y
203CONFIG_DEBUG_ERRORS=y 203CONFIG_DEBUG_ERRORS=y
204CONFIG_DEBUG_LL=y 204CONFIG_DEBUG_LL=y
205CONFIG_DEBUG_LL_UART_8250=y
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
index 9f56ca3985ae..c100b7df5441 100644
--- a/arch/arm/configs/lpc32xx_defconfig
+++ b/arch/arm/configs/lpc32xx_defconfig
@@ -204,6 +204,7 @@ CONFIG_DEBUG_INFO=y
204# CONFIG_FTRACE is not set 204# CONFIG_FTRACE is not set
205# CONFIG_ARM_UNWIND is not set 205# CONFIG_ARM_UNWIND is not set
206CONFIG_DEBUG_LL=y 206CONFIG_DEBUG_LL=y
207CONFIG_DEBUG_LL_UART_8250=y
207CONFIG_EARLY_PRINTK=y 208CONFIG_EARLY_PRINTK=y
208CONFIG_CRYPTO_ANSI_CPRNG=y 209CONFIG_CRYPTO_ANSI_CPRNG=y
209# CONFIG_CRYPTO_HW is not set 210# CONFIG_CRYPTO_HW is not set
diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig
index 0dae1c1f007a..85d10d2e3d66 100644
--- a/arch/arm/configs/mv78xx0_defconfig
+++ b/arch/arm/configs/mv78xx0_defconfig
@@ -132,6 +132,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
132CONFIG_DEBUG_USER=y 132CONFIG_DEBUG_USER=y
133CONFIG_DEBUG_ERRORS=y 133CONFIG_DEBUG_ERRORS=y
134CONFIG_DEBUG_LL=y 134CONFIG_DEBUG_LL=y
135CONFIG_DEBUG_LL_UART_8250=y
135CONFIG_CRYPTO_CBC=m 136CONFIG_CRYPTO_CBC=m
136CONFIG_CRYPTO_ECB=m 137CONFIG_CRYPTO_ECB=m
137CONFIG_CRYPTO_PCBC=m 138CONFIG_CRYPTO_PCBC=m
diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig
index 952430d9e2d9..855143fac6bd 100644
--- a/arch/arm/configs/orion5x_defconfig
+++ b/arch/arm/configs/orion5x_defconfig
@@ -156,6 +156,7 @@ CONFIG_LATENCYTOP=y
156# CONFIG_FTRACE is not set 156# CONFIG_FTRACE is not set
157CONFIG_DEBUG_USER=y 157CONFIG_DEBUG_USER=y
158CONFIG_DEBUG_LL=y 158CONFIG_DEBUG_LL=y
159CONFIG_DEBUG_LL_UART_8250=y
159CONFIG_CRYPTO_CBC=m 160CONFIG_CRYPTO_CBC=m
160CONFIG_CRYPTO_ECB=m 161CONFIG_CRYPTO_ECB=m
161CONFIG_CRYPTO_PCBC=m 162CONFIG_CRYPTO_PCBC=m
diff --git a/arch/arm/configs/rpc_defconfig b/arch/arm/configs/rpc_defconfig
index 00515ef9782d..89631795a915 100644
--- a/arch/arm/configs/rpc_defconfig
+++ b/arch/arm/configs/rpc_defconfig
@@ -131,3 +131,4 @@ CONFIG_DEBUG_KERNEL=y
131CONFIG_DEBUG_USER=y 131CONFIG_DEBUG_USER=y
132CONFIG_DEBUG_ERRORS=y 132CONFIG_DEBUG_ERRORS=y
133CONFIG_DEBUG_LL=y 133CONFIG_DEBUG_LL=y
134CONFIG_DEBUG_LL_UART_8250=y
diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h
index 891a56b35bcf..563b92fc2f41 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -23,6 +23,8 @@
23 23
24#include <linux/types.h> 24#include <linux/types.h>
25 25
26struct l2x0_regs;
27
26struct outer_cache_fns { 28struct outer_cache_fns {
27 void (*inv_range)(unsigned long, unsigned long); 29 void (*inv_range)(unsigned long, unsigned long);
28 void (*clean_range)(unsigned long, unsigned long); 30 void (*clean_range)(unsigned long, unsigned long);
@@ -36,6 +38,7 @@ struct outer_cache_fns {
36 38
37 /* This is an ARM L2C thing */ 39 /* This is an ARM L2C thing */
38 void (*write_sec)(unsigned long, unsigned); 40 void (*write_sec)(unsigned long, unsigned);
41 void (*configure)(const struct l2x0_regs *);
39}; 42};
40 43
41extern struct outer_cache_fns outer_cache; 44extern struct outer_cache_fns outer_cache;
diff --git a/arch/arm/mach-ks8695/include/mach/debug-macro.S b/arch/arm/include/debug/ks8695.S
index a79e48981202..961da1f32ab3 100644
--- a/arch/arm/mach-ks8695/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/ks8695.S
@@ -1,5 +1,5 @@
1/* 1/*
2 * arch/arm/mach-ks8695/include/mach/debug-macro.S 2 * arch/arm/include/debug/ks8695.S
3 * 3 *
4 * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> 4 * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
5 * Copyright (C) 2006 Simtec Electronics 5 * Copyright (C) 2006 Simtec Electronics
@@ -11,8 +11,12 @@
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13 13
14#include <mach/hardware.h> 14#define KS8695_UART_PA 0x03ffe000
15#include <mach/regs-uart.h> 15#define KS8695_UART_VA 0xf00fe000
16#define KS8695_URTH (0x04)
17#define KS8695_URLS (0x14)
18#define URLS_URTE (1 << 6)
19#define URLS_URTHRE (1 << 5)
16 20
17 .macro addruart, rp, rv, tmp 21 .macro addruart, rp, rv, tmp
18 ldr \rp, =KS8695_UART_PA @ physical base address 22 ldr \rp, =KS8695_UART_PA @ physical base address
diff --git a/arch/arm/mach-netx/include/mach/debug-macro.S b/arch/arm/include/debug/netx.S
index 247781e096e2..81e1b2af70f7 100644
--- a/arch/arm/mach-netx/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/netx.S
@@ -1,5 +1,4 @@
1/* arch/arm/mach-netx/include/mach/debug-macro.S 1/*
2 *
3 * Debugging macro include header 2 * Debugging macro include header
4 * 3 *
5 * Copyright (C) 1994-1999 Russell King 4 * Copyright (C) 1994-1999 Russell King
@@ -11,26 +10,27 @@
11 * 10 *
12*/ 11*/
13 12
14#include "hardware.h" 13#define UART_DATA 0
14#define UART_FLAG 0x18
15#define UART_FLAG_BUSY (1 << 3)
15 16
16 .macro addruart, rp, rv, tmp 17 .macro addruart, rp, rv, tmp
17 mov \rp, #0x00000a00 18 ldr \rp, =CONFIG_DEBUG_UART_PHYS
18 orr \rv, \rp, #io_p2v(0x00100000) @ virtual 19 ldr \rv, =CONFIG_DEBUG_UART_VIRT
19 orr \rp, \rp, #0x00100000 @ physical
20 .endm 20 .endm
21 21
22 .macro senduart,rd,rx 22 .macro senduart,rd,rx
23 str \rd, [\rx, #0] 23 str \rd, [\rx, #UART_DATA]
24 .endm 24 .endm
25 25
26 .macro busyuart,rd,rx 26 .macro busyuart,rd,rx
271002: ldr \rd, [\rx, #0x18] 271002: ldr \rd, [\rx, #UART_FLAG]
28 tst \rd, #(1 << 3) 28 tst \rd, #UART_FLAG_BUSY
29 bne 1002b 29 bne 1002b
30 .endm 30 .endm
31 31
32 .macro waituart,rd,rx 32 .macro waituart,rd,rx
331001: ldr \rd, [\rx, #0x18] 331001: ldr \rd, [\rx, #UART_FLAG]
34 tst \rd, #(1 << 3) 34 tst \rd, #UART_FLAG_BUSY
35 bne 1001b 35 bne 1001b
36 .endm 36 .endm
diff --git a/arch/arm/include/uapi/asm/unistd.h b/arch/arm/include/uapi/asm/unistd.h
index 705bb7620673..0c3f5a0dafd3 100644
--- a/arch/arm/include/uapi/asm/unistd.h
+++ b/arch/arm/include/uapi/asm/unistd.h
@@ -413,6 +413,7 @@
413#define __NR_getrandom (__NR_SYSCALL_BASE+384) 413#define __NR_getrandom (__NR_SYSCALL_BASE+384)
414#define __NR_memfd_create (__NR_SYSCALL_BASE+385) 414#define __NR_memfd_create (__NR_SYSCALL_BASE+385)
415#define __NR_bpf (__NR_SYSCALL_BASE+386) 415#define __NR_bpf (__NR_SYSCALL_BASE+386)
416#define __NR_execveat (__NR_SYSCALL_BASE+387)
416 417
417/* 418/*
418 * The following SWIs are ARM private. 419 * The following SWIs are ARM private.
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index e51833f8cc38..05745eb838c5 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -396,6 +396,7 @@
396 CALL(sys_getrandom) 396 CALL(sys_getrandom)
397/* 385 */ CALL(sys_memfd_create) 397/* 385 */ CALL(sys_memfd_create)
398 CALL(sys_bpf) 398 CALL(sys_bpf)
399 CALL(sys_execveat)
399#ifndef syscalls_counted 400#ifndef syscalls_counted
400.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls 401.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
401#define syscalls_counted 402#define syscalls_counted
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 4176df721bf0..1a0045abead7 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -253,21 +253,22 @@
253 .endm 253 .endm
254 254
255 .macro restore_user_regs, fast = 0, offset = 0 255 .macro restore_user_regs, fast = 0, offset = 0
256 ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr 256 mov r2, sp
257 ldr lr, [sp, #\offset + S_PC]! @ get pc 257 ldr r1, [r2, #\offset + S_PSR] @ get calling cpsr
258 ldr lr, [r2, #\offset + S_PC]! @ get pc
258 msr spsr_cxsf, r1 @ save in spsr_svc 259 msr spsr_cxsf, r1 @ save in spsr_svc
259#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_32v6K) 260#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_32v6K)
260 @ We must avoid clrex due to Cortex-A15 erratum #830321 261 @ We must avoid clrex due to Cortex-A15 erratum #830321
261 strex r1, r2, [sp] @ clear the exclusive monitor 262 strex r1, r2, [r2] @ clear the exclusive monitor
262#endif 263#endif
263 .if \fast 264 .if \fast
264 ldmdb sp, {r1 - lr}^ @ get calling r1 - lr 265 ldmdb r2, {r1 - lr}^ @ get calling r1 - lr
265 .else 266 .else
266 ldmdb sp, {r0 - lr}^ @ get calling r0 - lr 267 ldmdb r2, {r0 - lr}^ @ get calling r0 - lr
267 .endif 268 .endif
268 mov r0, r0 @ ARMv5T and earlier require a nop 269 mov r0, r0 @ ARMv5T and earlier require a nop
269 @ after ldm {}^ 270 @ after ldm {}^
270 add sp, sp, #S_FRAME_SIZE - S_PC 271 add sp, sp, #\offset + S_FRAME_SIZE
271 movs pc, lr @ return & move spsr_svc into cpsr 272 movs pc, lr @ return & move spsr_svc into cpsr
272 .endm 273 .endm
273 274
diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S
index 2260f1855820..8944f4991c3c 100644
--- a/arch/arm/kernel/entry-v7m.S
+++ b/arch/arm/kernel/entry-v7m.S
@@ -22,10 +22,12 @@
22 22
23__invalid_entry: 23__invalid_entry:
24 v7m_exception_entry 24 v7m_exception_entry
25#ifdef CONFIG_PRINTK
25 adr r0, strerr 26 adr r0, strerr
26 mrs r1, ipsr 27 mrs r1, ipsr
27 mov r2, lr 28 mov r2, lr
28 bl printk 29 bl printk
30#endif
29 mov r0, sp 31 mov r0, sp
30 bl show_regs 32 bl show_regs
311: b 1b 331: b 1b
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index ad857bada96c..350f188c92d2 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -109,7 +109,8 @@ void __init init_IRQ(void)
109 109
110 if (IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_CACHE_L2X0) && 110 if (IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_CACHE_L2X0) &&
111 (machine_desc->l2c_aux_mask || machine_desc->l2c_aux_val)) { 111 (machine_desc->l2c_aux_mask || machine_desc->l2c_aux_val)) {
112 outer_cache.write_sec = machine_desc->l2c_write_sec; 112 if (!outer_cache.write_sec)
113 outer_cache.write_sec = machine_desc->l2c_write_sec;
113 ret = l2x0_of_init(machine_desc->l2c_aux_val, 114 ret = l2x0_of_init(machine_desc->l2c_aux_val,
114 machine_desc->l2c_aux_mask); 115 machine_desc->l2c_aux_mask);
115 if (ret) 116 if (ret)
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index f7c65adaa428..557e128e4df0 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -116,8 +116,14 @@ int armpmu_event_set_period(struct perf_event *event)
116 ret = 1; 116 ret = 1;
117 } 117 }
118 118
119 if (left > (s64)armpmu->max_period) 119 /*
120 left = armpmu->max_period; 120 * Limit the maximum period to prevent the counter value
121 * from overtaking the one we are about to program. In
122 * effect we are reducing max_period to account for
123 * interrupt latency (and we are being very conservative).
124 */
125 if (left > (armpmu->max_period >> 1))
126 left = armpmu->max_period >> 1;
121 127
122 local64_set(&hwc->prev_count, (u64)-left); 128 local64_set(&hwc->prev_count, (u64)-left);
123 129
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index f9c863911038..d13f185e7bd5 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -657,10 +657,13 @@ int __init arm_add_memory(u64 start, u64 size)
657 657
658 /* 658 /*
659 * Ensure that start/size are aligned to a page boundary. 659 * Ensure that start/size are aligned to a page boundary.
660 * Size is appropriately rounded down, start is rounded up. 660 * Size is rounded down, start is rounded up.
661 */ 661 */
662 size -= start & ~PAGE_MASK;
663 aligned_start = PAGE_ALIGN(start); 662 aligned_start = PAGE_ALIGN(start);
663 if (aligned_start > start + size)
664 size = 0;
665 else
666 size -= aligned_start - start;
664 667
665#ifndef CONFIG_ARCH_PHYS_ADDR_T_64BIT 668#ifndef CONFIG_ARCH_PHYS_ADDR_T_64BIT
666 if (aligned_start > ULONG_MAX) { 669 if (aligned_start > ULONG_MAX) {
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 766f57d2f029..4791a3cc00f9 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -17,6 +17,7 @@
17#include <asm/cacheflush.h> 17#include <asm/cacheflush.h>
18#include <asm/cputype.h> 18#include <asm/cputype.h>
19#include <asm/firmware.h> 19#include <asm/firmware.h>
20#include <asm/hardware/cache-l2x0.h>
20#include <asm/suspend.h> 21#include <asm/suspend.h>
21 22
22#include <mach/map.h> 23#include <mach/map.h>
@@ -136,6 +137,43 @@ static const struct firmware_ops exynos_firmware_ops = {
136 .resume = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_resume : NULL, 137 .resume = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_resume : NULL,
137}; 138};
138 139
140static void exynos_l2_write_sec(unsigned long val, unsigned reg)
141{
142 static int l2cache_enabled;
143
144 switch (reg) {
145 case L2X0_CTRL:
146 if (val & L2X0_CTRL_EN) {
147 /*
148 * Before the cache can be enabled, due to firmware
149 * design, SMC_CMD_L2X0INVALL must be called.
150 */
151 if (!l2cache_enabled) {
152 exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
153 l2cache_enabled = 1;
154 }
155 } else {
156 l2cache_enabled = 0;
157 }
158 exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0);
159 break;
160
161 case L2X0_DEBUG_CTRL:
162 exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0);
163 break;
164
165 default:
166 WARN_ONCE(1, "%s: ignoring write to reg 0x%x\n", __func__, reg);
167 }
168}
169
170static void exynos_l2_configure(const struct l2x0_regs *regs)
171{
172 exynos_smc(SMC_CMD_L2X0SETUP1, regs->tag_latency, regs->data_latency,
173 regs->prefetch_ctrl);
174 exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0);
175}
176
139void __init exynos_firmware_init(void) 177void __init exynos_firmware_init(void)
140{ 178{
141 struct device_node *nd; 179 struct device_node *nd;
@@ -155,4 +193,16 @@ void __init exynos_firmware_init(void)
155 pr_info("Running under secure firmware.\n"); 193 pr_info("Running under secure firmware.\n");
156 194
157 register_firmware_ops(&exynos_firmware_ops); 195 register_firmware_ops(&exynos_firmware_ops);
196
197 /*
198 * Exynos 4 SoCs (based on Cortex A9 and equipped with L2C-310),
199 * running under secure firmware, require certain registers of L2
200 * cache controller to be written in secure mode. Here .write_sec
201 * callback is provided to perform necessary SMC calls.
202 */
203 if (IS_ENABLED(CONFIG_CACHE_L2X0) &&
204 read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
205 outer_cache.write_sec = exynos_l2_write_sec;
206 outer_cache.configure = exynos_l2_configure;
207 }
158} 208}
diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S
index e3c373082bbe..31d25834b9c4 100644
--- a/arch/arm/mach-exynos/sleep.S
+++ b/arch/arm/mach-exynos/sleep.S
@@ -16,6 +16,8 @@
16 */ 16 */
17 17
18#include <linux/linkage.h> 18#include <linux/linkage.h>
19#include <asm/asm-offsets.h>
20#include <asm/hardware/cache-l2x0.h>
19#include "smc.h" 21#include "smc.h"
20 22
21#define CPU_MASK 0xff0ffff0 23#define CPU_MASK 0xff0ffff0
@@ -74,6 +76,45 @@ ENTRY(exynos_cpu_resume_ns)
74 mov r0, #SMC_CMD_C15RESUME 76 mov r0, #SMC_CMD_C15RESUME
75 dsb 77 dsb
76 smc #0 78 smc #0
79#ifdef CONFIG_CACHE_L2X0
80 adr r0, 1f
81 ldr r2, [r0]
82 add r0, r2, r0
83
84 /* Check that the address has been initialised. */
85 ldr r1, [r0, #L2X0_R_PHY_BASE]
86 teq r1, #0
87 beq skip_l2x0
88
89 /* Check if controller has been enabled. */
90 ldr r2, [r1, #L2X0_CTRL]
91 tst r2, #0x1
92 bne skip_l2x0
93
94 ldr r1, [r0, #L2X0_R_TAG_LATENCY]
95 ldr r2, [r0, #L2X0_R_DATA_LATENCY]
96 ldr r3, [r0, #L2X0_R_PREFETCH_CTRL]
97 mov r0, #SMC_CMD_L2X0SETUP1
98 smc #0
99
100 /* Reload saved regs pointer because smc corrupts registers. */
101 adr r0, 1f
102 ldr r2, [r0]
103 add r0, r2, r0
104
105 ldr r1, [r0, #L2X0_R_PWR_CTRL]
106 ldr r2, [r0, #L2X0_R_AUX_CTRL]
107 mov r0, #SMC_CMD_L2X0SETUP2
108 smc #0
109
110 mov r0, #SMC_CMD_L2X0INVALL
111 smc #0
112
113 mov r1, #1
114 mov r0, #SMC_CMD_L2X0CTRL
115 smc #0
116skip_l2x0:
117#endif /* CONFIG_CACHE_L2X0 */
77skip_cp15: 118skip_cp15:
78 b cpu_resume 119 b cpu_resume
79ENDPROC(exynos_cpu_resume_ns) 120ENDPROC(exynos_cpu_resume_ns)
@@ -83,3 +124,8 @@ cp15_save_diag:
83 .globl cp15_save_power 124 .globl cp15_save_power
84cp15_save_power: 125cp15_save_power:
85 .long 0 @ cp15 power control 126 .long 0 @ cp15 power control
127
128#ifdef CONFIG_CACHE_L2X0
129 .align
1301: .long l2x0_saved_regs - .
131#endif /* CONFIG_CACHE_L2X0 */
diff --git a/arch/arm/mach-omap1/include/mach/debug-macro.S b/arch/arm/mach-omap1/include/mach/debug-macro.S
deleted file mode 100644
index 5c1a26c9f490..000000000000
--- a/arch/arm/mach-omap1/include/mach/debug-macro.S
+++ /dev/null
@@ -1,101 +0,0 @@
1/* arch/arm/mach-omap1/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <linux/serial_reg.h>
15
16#include "serial.h"
17
18 .pushsection .data
19omap_uart_phys: .word 0x0
20omap_uart_virt: .word 0x0
21 .popsection
22
23 /*
24 * Note that this code won't work if the bootloader passes
25 * a wrong machine ID number in r1. To debug, just hardcode
26 * the desired UART phys and virt addresses temporarily into
27 * the omap_uart_phys and omap_uart_virt above.
28 */
29 .macro addruart, rp, rv, tmp
30
31 /* Use omap_uart_phys/virt if already configured */
329: adr \rp, 99f @ get effective addr of 99f
33 ldr \rv, [\rp] @ get absolute addr of 99f
34 sub \rv, \rv, \rp @ offset between the two
35 ldr \rp, [\rp, #4] @ abs addr of omap_uart_phys
36 sub \tmp, \rp, \rv @ make it effective
37 ldr \rp, [\tmp, #0] @ omap_uart_phys
38 ldr \rv, [\tmp, #4] @ omap_uart_virt
39 cmp \rp, #0 @ is port configured?
40 cmpne \rv, #0
41 bne 100f @ already configured
42
43 /* Check the debug UART configuration set in uncompress.h */
44 and \rp, pc, #0xff000000
45 ldr \rv, =OMAP_UART_INFO_OFS
46 ldr \rp, [\rp, \rv]
47
48 /* Select the UART to use based on the UART1 scratchpad value */
4910: cmp \rp, #0 @ no port configured?
50 beq 11f @ if none, try to use UART1
51 cmp \rp, #OMAP1UART1
52 beq 11f @ configure OMAP1UART1
53 cmp \rp, #OMAP1UART2
54 beq 12f @ configure OMAP1UART2
55 cmp \rp, #OMAP1UART3
56 beq 13f @ configure OMAP2UART3
57
58 /* Configure the UART offset from the phys/virt base */
5911: mov \rp, #0x00fb0000 @ OMAP1UART1
60 b 98f
6112: mov \rp, #0x00fb0000 @ OMAP1UART1
62 orr \rp, \rp, #0x00000800 @ OMAP1UART2
63 b 98f
6413: mov \rp, #0x00fb0000 @ OMAP1UART1
65 orr \rp, \rp, #0x00000800 @ OMAP1UART2
66 orr \rp, \rp, #0x00009000 @ OMAP1UART3
67
68 /* Store both phys and virt address for the uart */
6998: add \rp, \rp, #0xff000000 @ phys base
70 str \rp, [\tmp, #0] @ omap_uart_phys
71 sub \rp, \rp, #0xff000000 @ phys base
72 add \rp, \rp, #0xfe000000 @ virt base
73 str \rp, [\tmp, #4] @ omap_uart_virt
74 b 9b
75
76 .align
7799: .word .
78 .word omap_uart_phys
79 .ltorg
80
81100:
82 .endm
83
84 .macro senduart,rd,rx
85 strb \rd, [\rx]
86 .endm
87
88 .macro busyuart,rd,rx
891001: ldrb \rd, [\rx, #(UART_LSR << OMAP_PORT_SHIFT)]
90 and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
91 teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
92 beq 1002f
93 ldrb \rd, [\rx, #(UART_LSR << OMAP7XX_PORT_SHIFT)]
94 and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
95 teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
96 bne 1001b
971002:
98 .endm
99
100 .macro waituart,rd,rx
101 .endm
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 608079a1aba6..c5c480b76da5 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -171,6 +171,9 @@ static const char *const omap4_boards_compat[] __initconst = {
171}; 171};
172 172
173DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)") 173DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
174 .l2c_aux_val = OMAP_L2C_AUX_CTRL,
175 .l2c_aux_mask = 0xcf9fffff,
176 .l2c_write_sec = omap4_l2c310_write_sec,
174 .reserve = omap_reserve, 177 .reserve = omap_reserve,
175 .smp = smp_ops(omap4_smp_ops), 178 .smp = smp_ops(omap4_smp_ops),
176 .map_io = omap4_map_io, 179 .map_io = omap4_map_io,
@@ -214,6 +217,9 @@ static const char *const am43_boards_compat[] __initconst = {
214}; 217};
215 218
216DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)") 219DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)")
220 .l2c_aux_val = OMAP_L2C_AUX_CTRL,
221 .l2c_aux_mask = 0xcf9fffff,
222 .l2c_write_sec = omap4_l2c310_write_sec,
217 .map_io = am33xx_map_io, 223 .map_io = am33xx_map_io,
218 .init_early = am43xx_init_early, 224 .init_early = am43xx_init_early,
219 .init_late = am43xx_init_late, 225 .init_late = am43xx_init_late,
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 377eea849e7b..2610c9f8d29f 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -35,6 +35,7 @@
35#include <linux/irqchip/irq-omap-intc.h> 35#include <linux/irqchip/irq-omap-intc.h>
36 36
37#include <asm/proc-fns.h> 37#include <asm/proc-fns.h>
38#include <asm/hardware/cache-l2x0.h>
38 39
39#include "i2c.h" 40#include "i2c.h"
40#include "serial.h" 41#include "serial.h"
@@ -94,11 +95,18 @@ extern void omap3_gptimer_timer_init(void);
94extern void omap4_local_timer_init(void); 95extern void omap4_local_timer_init(void);
95#ifdef CONFIG_CACHE_L2X0 96#ifdef CONFIG_CACHE_L2X0
96int omap_l2_cache_init(void); 97int omap_l2_cache_init(void);
98#define OMAP_L2C_AUX_CTRL (L2C_AUX_CTRL_SHARED_OVERRIDE | \
99 L310_AUX_CTRL_DATA_PREFETCH | \
100 L310_AUX_CTRL_INSTR_PREFETCH)
101void omap4_l2c310_write_sec(unsigned long val, unsigned reg);
97#else 102#else
98static inline int omap_l2_cache_init(void) 103static inline int omap_l2_cache_init(void)
99{ 104{
100 return 0; 105 return 0;
101} 106}
107
108#define OMAP_L2C_AUX_CTRL 0
109#define omap4_l2c310_write_sec NULL
102#endif 110#endif
103extern void omap5_realtime_timer_init(void); 111extern void omap5_realtime_timer_init(void);
104 112
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index b7cb44abe49b..fe99ceff2e2d 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -166,7 +166,7 @@ void __iomem *omap4_get_l2cache_base(void)
166 return l2cache_base; 166 return l2cache_base;
167} 167}
168 168
169static void omap4_l2c310_write_sec(unsigned long val, unsigned reg) 169void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
170{ 170{
171 unsigned smc_op; 171 unsigned smc_op;
172 172
@@ -201,24 +201,10 @@ static void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
201 201
202int __init omap_l2_cache_init(void) 202int __init omap_l2_cache_init(void)
203{ 203{
204 u32 aux_ctrl;
205
206 /* Static mapping, never released */ 204 /* Static mapping, never released */
207 l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K); 205 l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
208 if (WARN_ON(!l2cache_base)) 206 if (WARN_ON(!l2cache_base))
209 return -ENOMEM; 207 return -ENOMEM;
210
211 /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */
212 aux_ctrl = L2C_AUX_CTRL_SHARED_OVERRIDE |
213 L310_AUX_CTRL_DATA_PREFETCH |
214 L310_AUX_CTRL_INSTR_PREFETCH;
215
216 outer_cache.write_sec = omap4_l2c310_write_sec;
217 if (of_have_populated_dt())
218 l2x0_of_init(aux_ctrl, 0xcf9fffff);
219 else
220 l2x0_init(l2cache_base, aux_ctrl, 0xcf9fffff);
221
222 return 0; 208 return 0;
223} 209}
224#endif 210#endif
diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile
index f1114d11fe13..61ff91e76e0a 100644
--- a/arch/arm/mach-sa1100/Makefile
+++ b/arch/arm/mach-sa1100/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := clock.o generic.o irq.o time.o #nmi-oopser.o 6obj-y := clock.o generic.o irq.o #nmi-oopser.o
7 7
8# Specific board support 8# Specific board support
9obj-$(CONFIG_SA1100_ASSABET) += assabet.o 9obj-$(CONFIG_SA1100_ASSABET) += assabet.o
diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c
index 03c75a811cb0..cbf53bb9c814 100644
--- a/arch/arm/mach-sa1100/clock.c
+++ b/arch/arm/mach-sa1100/clock.c
@@ -119,6 +119,17 @@ static DEFINE_CLK(gpio27, &clk_gpio27_ops);
119 119
120static DEFINE_CLK(cpu, &clk_cpu_ops); 120static DEFINE_CLK(cpu, &clk_cpu_ops);
121 121
122static unsigned long clk_36864_get_rate(struct clk *clk)
123{
124 return 3686400;
125}
126
127static struct clkops clk_36864_ops = {
128 .get_rate = clk_36864_get_rate,
129};
130
131static DEFINE_CLK(36864, &clk_36864_ops);
132
122static struct clk_lookup sa11xx_clkregs[] = { 133static struct clk_lookup sa11xx_clkregs[] = {
123 CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27), 134 CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27),
124 CLKDEV_INIT("sa1100-rtc", NULL, NULL), 135 CLKDEV_INIT("sa1100-rtc", NULL, NULL),
@@ -126,6 +137,7 @@ static struct clk_lookup sa11xx_clkregs[] = {
126 CLKDEV_INIT("sa11x0-pcmcia", NULL, &clk_cpu), 137 CLKDEV_INIT("sa11x0-pcmcia", NULL, &clk_cpu),
127 /* sa1111 names devices using internal offsets, PCMCIA is at 0x1800 */ 138 /* sa1111 names devices using internal offsets, PCMCIA is at 0x1800 */
128 CLKDEV_INIT("1800", NULL, &clk_cpu), 139 CLKDEV_INIT("1800", NULL, &clk_cpu),
140 CLKDEV_INIT(NULL, "OSTIMER0", &clk_36864),
129}; 141};
130 142
131static int __init sa11xx_clk_init(void) 143static int __init sa11xx_clk_init(void)
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index b90c7d828391..bd5155d04519 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -371,8 +371,7 @@ static void __init collie_init(void)
371 PPC_LDD6 | PPC_LDD7 | PPC_L_PCLK | PPC_L_LCLK | PPC_L_FCLK | PPC_L_BIAS | 371 PPC_LDD6 | PPC_LDD7 | PPC_L_PCLK | PPC_L_LCLK | PPC_L_FCLK | PPC_L_BIAS |
372 PPC_TXD1 | PPC_TXD2 | PPC_TXD3 | PPC_TXD4 | PPC_SCLK | PPC_SFRM; 372 PPC_TXD1 | PPC_TXD2 | PPC_TXD3 | PPC_TXD4 | PPC_SCLK | PPC_SFRM;
373 373
374 PWER = _COLLIE_GPIO_AC_IN | _COLLIE_GPIO_CO | _COLLIE_GPIO_ON_KEY | 374 PWER = 0;
375 _COLLIE_GPIO_WAKEUP | _COLLIE_GPIO_nREMOCON_INT | PWER_RTC;
376 375
377 PGSR = _COLLIE_GPIO_nREMOCON_ON; 376 PGSR = _COLLIE_GPIO_nREMOCON_ON;
378 377
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index d4ea142c4edd..40e0d8619a2d 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -33,6 +33,7 @@
33#include <mach/irqs.h> 33#include <mach/irqs.h>
34 34
35#include "generic.h" 35#include "generic.h"
36#include <clocksource/pxa.h>
36 37
37unsigned int reset_status; 38unsigned int reset_status;
38EXPORT_SYMBOL(reset_status); 39EXPORT_SYMBOL(reset_status);
@@ -369,6 +370,11 @@ void __init sa1100_map_io(void)
369 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); 370 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
370} 371}
371 372
373void __init sa1100_timer_init(void)
374{
375 pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x90000000), 3686400);
376}
377
372/* 378/*
373 * Disable the memory bus request/grant signals on the SA1110 to 379 * Disable the memory bus request/grant signals on the SA1110 to
374 * ensure that we don't receive spurious memory requests. We set 380 * ensure that we don't receive spurious memory requests. We set
diff --git a/arch/arm/mach-sa1100/include/mach/irqs.h b/arch/arm/mach-sa1100/include/mach/irqs.h
index de0983494c7e..734e30e406a3 100644
--- a/arch/arm/mach-sa1100/include/mach/irqs.h
+++ b/arch/arm/mach-sa1100/include/mach/irqs.h
@@ -8,17 +8,17 @@
8 * 2001/11/14 RMK Cleaned up and standardised a lot of the IRQs. 8 * 2001/11/14 RMK Cleaned up and standardised a lot of the IRQs.
9 */ 9 */
10 10
11#define IRQ_GPIO0 1 11#define IRQ_GPIO0_SC 1
12#define IRQ_GPIO1 2 12#define IRQ_GPIO1_SC 2
13#define IRQ_GPIO2 3 13#define IRQ_GPIO2_SC 3
14#define IRQ_GPIO3 4 14#define IRQ_GPIO3_SC 4
15#define IRQ_GPIO4 5 15#define IRQ_GPIO4_SC 5
16#define IRQ_GPIO5 6 16#define IRQ_GPIO5_SC 6
17#define IRQ_GPIO6 7 17#define IRQ_GPIO6_SC 7
18#define IRQ_GPIO7 8 18#define IRQ_GPIO7_SC 8
19#define IRQ_GPIO8 9 19#define IRQ_GPIO8_SC 9
20#define IRQ_GPIO9 10 20#define IRQ_GPIO9_SC 10
21#define IRQ_GPIO10 11 21#define IRQ_GPIO10_SC 11
22#define IRQ_GPIO11_27 12 22#define IRQ_GPIO11_27 12
23#define IRQ_LCD 13 /* LCD controller */ 23#define IRQ_LCD 13 /* LCD controller */
24#define IRQ_Ser0UDC 14 /* Ser. port 0 UDC */ 24#define IRQ_Ser0UDC 14 /* Ser. port 0 UDC */
@@ -41,32 +41,43 @@
41#define IRQ_RTC1Hz 31 /* RTC 1 Hz clock */ 41#define IRQ_RTC1Hz 31 /* RTC 1 Hz clock */
42#define IRQ_RTCAlrm 32 /* RTC Alarm */ 42#define IRQ_RTCAlrm 32 /* RTC Alarm */
43 43
44#define IRQ_GPIO11 33 44#define IRQ_GPIO0 33
45#define IRQ_GPIO12 34 45#define IRQ_GPIO1 34
46#define IRQ_GPIO13 35 46#define IRQ_GPIO2 35
47#define IRQ_GPIO14 36 47#define IRQ_GPIO3 36
48#define IRQ_GPIO15 37 48#define IRQ_GPIO4 37
49#define IRQ_GPIO16 38 49#define IRQ_GPIO5 38
50#define IRQ_GPIO17 39 50#define IRQ_GPIO6 39
51#define IRQ_GPIO18 40 51#define IRQ_GPIO7 40
52#define IRQ_GPIO19 41 52#define IRQ_GPIO8 41
53#define IRQ_GPIO20 42 53#define IRQ_GPIO9 42
54#define IRQ_GPIO21 43 54#define IRQ_GPIO10 43
55#define IRQ_GPIO22 44 55#define IRQ_GPIO11 44
56#define IRQ_GPIO23 45 56#define IRQ_GPIO12 45
57#define IRQ_GPIO24 46 57#define IRQ_GPIO13 46
58#define IRQ_GPIO25 47 58#define IRQ_GPIO14 47
59#define IRQ_GPIO26 48 59#define IRQ_GPIO15 48
60#define IRQ_GPIO27 49 60#define IRQ_GPIO16 49
61#define IRQ_GPIO17 50
62#define IRQ_GPIO18 51
63#define IRQ_GPIO19 52
64#define IRQ_GPIO20 53
65#define IRQ_GPIO21 54
66#define IRQ_GPIO22 55
67#define IRQ_GPIO23 56
68#define IRQ_GPIO24 57
69#define IRQ_GPIO25 58
70#define IRQ_GPIO26 59
71#define IRQ_GPIO27 60
61 72
62/* 73/*
63 * The next 16 interrupts are for board specific purposes. Since 74 * The next 16 interrupts are for board specific purposes. Since
64 * the kernel can only run on one machine at a time, we can re-use 75 * the kernel can only run on one machine at a time, we can re-use
65 * these. If you need more, increase IRQ_BOARD_END, but keep it 76 * these. If you need more, increase IRQ_BOARD_END, but keep it
66 * within sensible limits. IRQs 49 to 64 are available. 77 * within sensible limits. IRQs 61 to 76 are available.
67 */ 78 */
68#define IRQ_BOARD_START 50 79#define IRQ_BOARD_START 61
69#define IRQ_BOARD_END 66 80#define IRQ_BOARD_END 77
70 81
71/* 82/*
72 * Figure out the MAX IRQ number. 83 * Figure out the MAX IRQ number.
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 63e2901db416..65aebfa66fe5 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -80,170 +80,6 @@ static struct irq_domain_ops sa1100_normal_irqdomain_ops = {
80 80
81static struct irq_domain *sa1100_normal_irqdomain; 81static struct irq_domain *sa1100_normal_irqdomain;
82 82
83/*
84 * SA1100 GPIO edge detection for IRQs:
85 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
86 * Use this instead of directly setting GRER/GFER.
87 */
88static int GPIO_IRQ_rising_edge;
89static int GPIO_IRQ_falling_edge;
90static int GPIO_IRQ_mask = (1 << 11) - 1;
91
92static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
93{
94 unsigned int mask;
95
96 mask = BIT(d->hwirq);
97
98 if (type == IRQ_TYPE_PROBE) {
99 if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
100 return 0;
101 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
102 }
103
104 if (type & IRQ_TYPE_EDGE_RISING) {
105 GPIO_IRQ_rising_edge |= mask;
106 } else
107 GPIO_IRQ_rising_edge &= ~mask;
108 if (type & IRQ_TYPE_EDGE_FALLING) {
109 GPIO_IRQ_falling_edge |= mask;
110 } else
111 GPIO_IRQ_falling_edge &= ~mask;
112
113 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
114 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
115
116 return 0;
117}
118
119/*
120 * GPIO IRQs must be acknowledged.
121 */
122static void sa1100_gpio_ack(struct irq_data *d)
123{
124 GEDR = BIT(d->hwirq);
125}
126
127static int sa1100_gpio_wake(struct irq_data *d, unsigned int on)
128{
129 if (on)
130 PWER |= BIT(d->hwirq);
131 else
132 PWER &= ~BIT(d->hwirq);
133 return 0;
134}
135
136/*
137 * This is for IRQs from 0 to 10.
138 */
139static struct irq_chip sa1100_low_gpio_chip = {
140 .name = "GPIO-l",
141 .irq_ack = sa1100_gpio_ack,
142 .irq_mask = sa1100_mask_irq,
143 .irq_unmask = sa1100_unmask_irq,
144 .irq_set_type = sa1100_gpio_type,
145 .irq_set_wake = sa1100_gpio_wake,
146};
147
148static int sa1100_low_gpio_irqdomain_map(struct irq_domain *d,
149 unsigned int irq, irq_hw_number_t hwirq)
150{
151 irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
152 handle_edge_irq);
153 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
154
155 return 0;
156}
157
158static struct irq_domain_ops sa1100_low_gpio_irqdomain_ops = {
159 .map = sa1100_low_gpio_irqdomain_map,
160 .xlate = irq_domain_xlate_onetwocell,
161};
162
163static struct irq_domain *sa1100_low_gpio_irqdomain;
164
165/*
166 * IRQ11 (GPIO11 through 27) handler. We enter here with the
167 * irq_controller_lock held, and IRQs disabled. Decode the IRQ
168 * and call the handler.
169 */
170static void
171sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
172{
173 unsigned int mask;
174
175 mask = GEDR & 0xfffff800;
176 do {
177 /*
178 * clear down all currently active IRQ sources.
179 * We will be processing them all.
180 */
181 GEDR = mask;
182
183 irq = IRQ_GPIO11;
184 mask >>= 11;
185 do {
186 if (mask & 1)
187 generic_handle_irq(irq);
188 mask >>= 1;
189 irq++;
190 } while (mask);
191
192 mask = GEDR & 0xfffff800;
193 } while (mask);
194}
195
196/*
197 * Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially.
198 * In addition, the IRQs are all collected up into one bit in the
199 * interrupt controller registers.
200 */
201static void sa1100_high_gpio_mask(struct irq_data *d)
202{
203 unsigned int mask = BIT(d->hwirq);
204
205 GPIO_IRQ_mask &= ~mask;
206
207 GRER &= ~mask;
208 GFER &= ~mask;
209}
210
211static void sa1100_high_gpio_unmask(struct irq_data *d)
212{
213 unsigned int mask = BIT(d->hwirq);
214
215 GPIO_IRQ_mask |= mask;
216
217 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
218 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
219}
220
221static struct irq_chip sa1100_high_gpio_chip = {
222 .name = "GPIO-h",
223 .irq_ack = sa1100_gpio_ack,
224 .irq_mask = sa1100_high_gpio_mask,
225 .irq_unmask = sa1100_high_gpio_unmask,
226 .irq_set_type = sa1100_gpio_type,
227 .irq_set_wake = sa1100_gpio_wake,
228};
229
230static int sa1100_high_gpio_irqdomain_map(struct irq_domain *d,
231 unsigned int irq, irq_hw_number_t hwirq)
232{
233 irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
234 handle_edge_irq);
235 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
236
237 return 0;
238}
239
240static struct irq_domain_ops sa1100_high_gpio_irqdomain_ops = {
241 .map = sa1100_high_gpio_irqdomain_map,
242 .xlate = irq_domain_xlate_onetwocell,
243};
244
245static struct irq_domain *sa1100_high_gpio_irqdomain;
246
247static struct resource irq_resource = 83static struct resource irq_resource =
248 DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs"); 84 DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
249 85
@@ -270,17 +106,6 @@ static int sa1100irq_suspend(void)
270 IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2| 106 IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2|
271 IC_GPIO1|IC_GPIO0); 107 IC_GPIO1|IC_GPIO0);
272 108
273 /*
274 * Set the appropriate edges for wakeup.
275 */
276 GRER = PWER & GPIO_IRQ_rising_edge;
277 GFER = PWER & GPIO_IRQ_falling_edge;
278
279 /*
280 * Clear any pending GPIO interrupts.
281 */
282 GEDR = GEDR;
283
284 return 0; 109 return 0;
285} 110}
286 111
@@ -292,9 +117,6 @@ static void sa1100irq_resume(void)
292 ICCR = st->iccr; 117 ICCR = st->iccr;
293 ICLR = st->iclr; 118 ICLR = st->iclr;
294 119
295 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
296 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
297
298 ICMR = st->icmr; 120 ICMR = st->icmr;
299 } 121 }
300} 122}
@@ -325,7 +147,8 @@ sa1100_handle_irq(struct pt_regs *regs)
325 if (mask == 0) 147 if (mask == 0)
326 break; 148 break;
327 149
328 handle_IRQ(ffs(mask) - 1 + IRQ_GPIO0, regs); 150 handle_domain_irq(sa1100_normal_irqdomain,
151 ffs(mask) - 1, regs);
329 } while (1); 152 } while (1);
330} 153}
331 154
@@ -339,34 +162,16 @@ void __init sa1100_init_irq(void)
339 /* all IRQs are IRQ, not FIQ */ 162 /* all IRQs are IRQ, not FIQ */
340 ICLR = 0; 163 ICLR = 0;
341 164
342 /* clear all GPIO edge detects */
343 GFER = 0;
344 GRER = 0;
345 GEDR = -1;
346
347 /* 165 /*
348 * Whatever the doc says, this has to be set for the wait-on-irq 166 * Whatever the doc says, this has to be set for the wait-on-irq
349 * instruction to work... on a SA1100 rev 9 at least. 167 * instruction to work... on a SA1100 rev 9 at least.
350 */ 168 */
351 ICCR = 1; 169 ICCR = 1;
352 170
353 sa1100_low_gpio_irqdomain = irq_domain_add_legacy(NULL, 171 sa1100_normal_irqdomain = irq_domain_add_simple(NULL,
354 11, IRQ_GPIO0, 0, 172 32, IRQ_GPIO0_SC,
355 &sa1100_low_gpio_irqdomain_ops, NULL);
356
357 sa1100_normal_irqdomain = irq_domain_add_legacy(NULL,
358 21, IRQ_GPIO11_27, 11,
359 &sa1100_normal_irqdomain_ops, NULL); 173 &sa1100_normal_irqdomain_ops, NULL);
360 174
361 sa1100_high_gpio_irqdomain = irq_domain_add_legacy(NULL,
362 17, IRQ_GPIO11, 11,
363 &sa1100_high_gpio_irqdomain_ops, NULL);
364
365 /*
366 * Install handler for GPIO 11-27 edge detect interrupts
367 */
368 irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
369
370 set_handle_irq(sa1100_handle_irq); 175 set_handle_irq(sa1100_handle_irq);
371 176
372 sa1100_init_gpio(); 177 sa1100_init_gpio();
diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
index 6645d1e31f14..34853d5dfda2 100644
--- a/arch/arm/mach-sa1100/pm.c
+++ b/arch/arm/mach-sa1100/pm.c
@@ -81,6 +81,7 @@ static int sa11x0_pm_enter(suspend_state_t state)
81 /* 81 /*
82 * Ensure not to come back here if it wasn't intended 82 * Ensure not to come back here if it wasn't intended
83 */ 83 */
84 RCSR = RCSR_SMR;
84 PSPR = 0; 85 PSPR = 0;
85 86
86 /* 87 /*
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
deleted file mode 100644
index 1dea6cfafb31..000000000000
--- a/arch/arm/mach-sa1100/time.c
+++ /dev/null
@@ -1,139 +0,0 @@
1/*
2 * linux/arch/arm/mach-sa1100/time.c
3 *
4 * Copyright (C) 1998 Deborah Wallach.
5 * Twiddles (C) 1999 Hugo Fiennes <hugo@empeg.com>
6 *
7 * 2000/03/29 (C) Nicolas Pitre <nico@fluxnic.net>
8 * Rewritten: big cleanup, much simpler, better HZ accuracy.
9 *
10 */
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/errno.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/timex.h>
17#include <linux/clockchips.h>
18#include <linux/sched_clock.h>
19
20#include <asm/mach/time.h>
21#include <mach/hardware.h>
22#include <mach/irqs.h>
23
24#define SA1100_CLOCK_FREQ 3686400
25#define SA1100_LATCH DIV_ROUND_CLOSEST(SA1100_CLOCK_FREQ, HZ)
26
27static u64 notrace sa1100_read_sched_clock(void)
28{
29 return readl_relaxed(OSCR);
30}
31
32#define MIN_OSCR_DELTA 2
33
34static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id)
35{
36 struct clock_event_device *c = dev_id;
37
38 /* Disarm the compare/match, signal the event. */
39 writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
40 writel_relaxed(OSSR_M0, OSSR);
41 c->event_handler(c);
42
43 return IRQ_HANDLED;
44}
45
46static int
47sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c)
48{
49 unsigned long next, oscr;
50
51 writel_relaxed(readl_relaxed(OIER) | OIER_E0, OIER);
52 next = readl_relaxed(OSCR) + delta;
53 writel_relaxed(next, OSMR0);
54 oscr = readl_relaxed(OSCR);
55
56 return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
57}
58
59static void
60sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c)
61{
62 switch (mode) {
63 case CLOCK_EVT_MODE_ONESHOT:
64 case CLOCK_EVT_MODE_UNUSED:
65 case CLOCK_EVT_MODE_SHUTDOWN:
66 writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
67 writel_relaxed(OSSR_M0, OSSR);
68 break;
69
70 case CLOCK_EVT_MODE_RESUME:
71 case CLOCK_EVT_MODE_PERIODIC:
72 break;
73 }
74}
75
76#ifdef CONFIG_PM
77unsigned long osmr[4], oier;
78
79static void sa1100_timer_suspend(struct clock_event_device *cedev)
80{
81 osmr[0] = readl_relaxed(OSMR0);
82 osmr[1] = readl_relaxed(OSMR1);
83 osmr[2] = readl_relaxed(OSMR2);
84 osmr[3] = readl_relaxed(OSMR3);
85 oier = readl_relaxed(OIER);
86}
87
88static void sa1100_timer_resume(struct clock_event_device *cedev)
89{
90 writel_relaxed(0x0f, OSSR);
91 writel_relaxed(osmr[0], OSMR0);
92 writel_relaxed(osmr[1], OSMR1);
93 writel_relaxed(osmr[2], OSMR2);
94 writel_relaxed(osmr[3], OSMR3);
95 writel_relaxed(oier, OIER);
96
97 /*
98 * OSMR0 is the system timer: make sure OSCR is sufficiently behind
99 */
100 writel_relaxed(OSMR0 - SA1100_LATCH, OSCR);
101}
102#else
103#define sa1100_timer_suspend NULL
104#define sa1100_timer_resume NULL
105#endif
106
107static struct clock_event_device ckevt_sa1100_osmr0 = {
108 .name = "osmr0",
109 .features = CLOCK_EVT_FEAT_ONESHOT,
110 .rating = 200,
111 .set_next_event = sa1100_osmr0_set_next_event,
112 .set_mode = sa1100_osmr0_set_mode,
113 .suspend = sa1100_timer_suspend,
114 .resume = sa1100_timer_resume,
115};
116
117static struct irqaction sa1100_timer_irq = {
118 .name = "ost0",
119 .flags = IRQF_TIMER | IRQF_IRQPOLL,
120 .handler = sa1100_ost0_interrupt,
121 .dev_id = &ckevt_sa1100_osmr0,
122};
123
124void __init sa1100_timer_init(void)
125{
126 writel_relaxed(0, OIER);
127 writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
128
129 sched_clock_register(sa1100_read_sched_clock, 32, 3686400);
130
131 ckevt_sa1100_osmr0.cpumask = cpumask_of(0);
132
133 setup_irq(IRQ_OST0, &sa1100_timer_irq);
134
135 clocksource_mmio_init(OSCR, "oscr", SA1100_CLOCK_FREQ, 200, 32,
136 clocksource_mmio_readl_up);
137 clockevents_config_and_register(&ckevt_sa1100_osmr0, 3686400,
138 MIN_OSCR_DELTA * 2, 0x7fffffff);
139}
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 03823e784f63..c43c71455566 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -1012,6 +1012,7 @@ config ARCH_SUPPORTS_BIG_ENDIAN
1012 1012
1013config ARM_KERNMEM_PERMS 1013config ARM_KERNMEM_PERMS
1014 bool "Restrict kernel memory permissions" 1014 bool "Restrict kernel memory permissions"
1015 depends on MMU
1015 help 1016 help
1016 If this is set, kernel memory other than kernel text (and rodata) 1017 If this is set, kernel memory other than kernel text (and rodata)
1017 will be made non-executable. The tradeoff is that each region is 1018 will be made non-executable. The tradeoff is that each region is
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 5e65ca8dea62..5ea2d6d417f7 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -41,12 +41,14 @@ struct l2c_init_data {
41 void (*enable)(void __iomem *, u32, unsigned); 41 void (*enable)(void __iomem *, u32, unsigned);
42 void (*fixup)(void __iomem *, u32, struct outer_cache_fns *); 42 void (*fixup)(void __iomem *, u32, struct outer_cache_fns *);
43 void (*save)(void __iomem *); 43 void (*save)(void __iomem *);
44 void (*configure)(void __iomem *);
44 struct outer_cache_fns outer_cache; 45 struct outer_cache_fns outer_cache;
45}; 46};
46 47
47#define CACHE_LINE_SIZE 32 48#define CACHE_LINE_SIZE 32
48 49
49static void __iomem *l2x0_base; 50static void __iomem *l2x0_base;
51static const struct l2c_init_data *l2x0_data;
50static DEFINE_RAW_SPINLOCK(l2x0_lock); 52static DEFINE_RAW_SPINLOCK(l2x0_lock);
51static u32 l2x0_way_mask; /* Bitmask of active ways */ 53static u32 l2x0_way_mask; /* Bitmask of active ways */
52static u32 l2x0_size; 54static u32 l2x0_size;
@@ -106,6 +108,19 @@ static inline void l2c_unlock(void __iomem *base, unsigned num)
106 } 108 }
107} 109}
108 110
111static void l2c_configure(void __iomem *base)
112{
113 if (outer_cache.configure) {
114 outer_cache.configure(&l2x0_saved_regs);
115 return;
116 }
117
118 if (l2x0_data->configure)
119 l2x0_data->configure(base);
120
121 l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL);
122}
123
109/* 124/*
110 * Enable the L2 cache controller. This function must only be 125 * Enable the L2 cache controller. This function must only be
111 * called when the cache controller is known to be disabled. 126 * called when the cache controller is known to be disabled.
@@ -114,7 +129,12 @@ static void l2c_enable(void __iomem *base, u32 aux, unsigned num_lock)
114{ 129{
115 unsigned long flags; 130 unsigned long flags;
116 131
117 l2c_write_sec(aux, base, L2X0_AUX_CTRL); 132 /* Do not touch the controller if already enabled. */
133 if (readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)
134 return;
135
136 l2x0_saved_regs.aux_ctrl = aux;
137 l2c_configure(base);
118 138
119 l2c_unlock(base, num_lock); 139 l2c_unlock(base, num_lock);
120 140
@@ -136,76 +156,14 @@ static void l2c_disable(void)
136 dsb(st); 156 dsb(st);
137} 157}
138 158
139#ifdef CONFIG_CACHE_PL310 159static void l2c_save(void __iomem *base)
140static inline void cache_wait(void __iomem *reg, unsigned long mask)
141{
142 /* cache operations by line are atomic on PL310 */
143}
144#else
145#define cache_wait l2c_wait_mask
146#endif
147
148static inline void cache_sync(void)
149{
150 void __iomem *base = l2x0_base;
151
152 writel_relaxed(0, base + sync_reg_offset);
153 cache_wait(base + L2X0_CACHE_SYNC, 1);
154}
155
156#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
157static inline void debug_writel(unsigned long val)
158{
159 l2c_set_debug(l2x0_base, val);
160}
161#else
162/* Optimised out for non-errata case */
163static inline void debug_writel(unsigned long val)
164{
165}
166#endif
167
168static void l2x0_cache_sync(void)
169{
170 unsigned long flags;
171
172 raw_spin_lock_irqsave(&l2x0_lock, flags);
173 cache_sync();
174 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
175}
176
177static void __l2x0_flush_all(void)
178{
179 debug_writel(0x03);
180 __l2c_op_way(l2x0_base + L2X0_CLEAN_INV_WAY);
181 cache_sync();
182 debug_writel(0x00);
183}
184
185static void l2x0_flush_all(void)
186{
187 unsigned long flags;
188
189 /* clean all ways */
190 raw_spin_lock_irqsave(&l2x0_lock, flags);
191 __l2x0_flush_all();
192 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
193}
194
195static void l2x0_disable(void)
196{ 160{
197 unsigned long flags; 161 l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
198
199 raw_spin_lock_irqsave(&l2x0_lock, flags);
200 __l2x0_flush_all();
201 l2c_write_sec(0, l2x0_base, L2X0_CTRL);
202 dsb(st);
203 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
204} 162}
205 163
206static void l2c_save(void __iomem *base) 164static void l2c_resume(void)
207{ 165{
208 l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 166 l2c_enable(l2x0_base, l2x0_saved_regs.aux_ctrl, l2x0_data->num_lock);
209} 167}
210 168
211/* 169/*
@@ -288,14 +246,6 @@ static void l2c210_sync(void)
288 __l2c210_cache_sync(l2x0_base); 246 __l2c210_cache_sync(l2x0_base);
289} 247}
290 248
291static void l2c210_resume(void)
292{
293 void __iomem *base = l2x0_base;
294
295 if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN))
296 l2c_enable(base, l2x0_saved_regs.aux_ctrl, 1);
297}
298
299static const struct l2c_init_data l2c210_data __initconst = { 249static const struct l2c_init_data l2c210_data __initconst = {
300 .type = "L2C-210", 250 .type = "L2C-210",
301 .way_size_0 = SZ_8K, 251 .way_size_0 = SZ_8K,
@@ -309,7 +259,7 @@ static const struct l2c_init_data l2c210_data __initconst = {
309 .flush_all = l2c210_flush_all, 259 .flush_all = l2c210_flush_all,
310 .disable = l2c_disable, 260 .disable = l2c_disable,
311 .sync = l2c210_sync, 261 .sync = l2c210_sync,
312 .resume = l2c210_resume, 262 .resume = l2c_resume,
313 }, 263 },
314}; 264};
315 265
@@ -466,7 +416,7 @@ static const struct l2c_init_data l2c220_data = {
466 .flush_all = l2c220_flush_all, 416 .flush_all = l2c220_flush_all,
467 .disable = l2c_disable, 417 .disable = l2c_disable,
468 .sync = l2c220_sync, 418 .sync = l2c220_sync,
469 .resume = l2c210_resume, 419 .resume = l2c_resume,
470 }, 420 },
471}; 421};
472 422
@@ -615,39 +565,29 @@ static void __init l2c310_save(void __iomem *base)
615 L310_POWER_CTRL); 565 L310_POWER_CTRL);
616} 566}
617 567
618static void l2c310_resume(void) 568static void l2c310_configure(void __iomem *base)
619{ 569{
620 void __iomem *base = l2x0_base; 570 unsigned revision;
621 571
622 if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) { 572 /* restore pl310 setup */
623 unsigned revision; 573 l2c_write_sec(l2x0_saved_regs.tag_latency, base,
624 574 L310_TAG_LATENCY_CTRL);
625 /* restore pl310 setup */ 575 l2c_write_sec(l2x0_saved_regs.data_latency, base,
626 writel_relaxed(l2x0_saved_regs.tag_latency, 576 L310_DATA_LATENCY_CTRL);
627 base + L310_TAG_LATENCY_CTRL); 577 l2c_write_sec(l2x0_saved_regs.filter_end, base,
628 writel_relaxed(l2x0_saved_regs.data_latency, 578 L310_ADDR_FILTER_END);
629 base + L310_DATA_LATENCY_CTRL); 579 l2c_write_sec(l2x0_saved_regs.filter_start, base,
630 writel_relaxed(l2x0_saved_regs.filter_end, 580 L310_ADDR_FILTER_START);
631 base + L310_ADDR_FILTER_END); 581
632 writel_relaxed(l2x0_saved_regs.filter_start, 582 revision = readl_relaxed(base + L2X0_CACHE_ID) &
633 base + L310_ADDR_FILTER_START); 583 L2X0_CACHE_ID_RTL_MASK;
634 584
635 revision = readl_relaxed(base + L2X0_CACHE_ID) & 585 if (revision >= L310_CACHE_ID_RTL_R2P0)
636 L2X0_CACHE_ID_RTL_MASK; 586 l2c_write_sec(l2x0_saved_regs.prefetch_ctrl, base,
637 587 L310_PREFETCH_CTRL);
638 if (revision >= L310_CACHE_ID_RTL_R2P0) 588 if (revision >= L310_CACHE_ID_RTL_R3P0)
639 l2c_write_sec(l2x0_saved_regs.prefetch_ctrl, base, 589 l2c_write_sec(l2x0_saved_regs.pwr_ctrl, base,
640 L310_PREFETCH_CTRL); 590 L310_POWER_CTRL);
641 if (revision >= L310_CACHE_ID_RTL_R3P0)
642 l2c_write_sec(l2x0_saved_regs.pwr_ctrl, base,
643 L310_POWER_CTRL);
644
645 l2c_enable(base, l2x0_saved_regs.aux_ctrl, 8);
646
647 /* Re-enable full-line-of-zeros for Cortex-A9 */
648 if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_FULL_LINE_ZERO)
649 set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1));
650 }
651} 591}
652 592
653static int l2c310_cpu_enable_flz(struct notifier_block *nb, unsigned long act, void *data) 593static int l2c310_cpu_enable_flz(struct notifier_block *nb, unsigned long act, void *data)
@@ -699,6 +639,23 @@ static void __init l2c310_enable(void __iomem *base, u32 aux, unsigned num_lock)
699 aux &= ~(L310_AUX_CTRL_FULL_LINE_ZERO | L310_AUX_CTRL_EARLY_BRESP); 639 aux &= ~(L310_AUX_CTRL_FULL_LINE_ZERO | L310_AUX_CTRL_EARLY_BRESP);
700 } 640 }
701 641
642 /* r3p0 or later has power control register */
643 if (rev >= L310_CACHE_ID_RTL_R3P0)
644 l2x0_saved_regs.pwr_ctrl = L310_DYNAMIC_CLK_GATING_EN |
645 L310_STNDBY_MODE_EN;
646
647 /*
648 * Always enable non-secure access to the lockdown registers -
649 * we write to them as part of the L2C enable sequence so they
650 * need to be accessible.
651 */
652 aux |= L310_AUX_CTRL_NS_LOCKDOWN;
653
654 l2c_enable(base, aux, num_lock);
655
656 /* Read back resulting AUX_CTRL value as it could have been altered. */
657 aux = readl_relaxed(base + L2X0_AUX_CTRL);
658
702 if (aux & (L310_AUX_CTRL_DATA_PREFETCH | L310_AUX_CTRL_INSTR_PREFETCH)) { 659 if (aux & (L310_AUX_CTRL_DATA_PREFETCH | L310_AUX_CTRL_INSTR_PREFETCH)) {
703 u32 prefetch = readl_relaxed(base + L310_PREFETCH_CTRL); 660 u32 prefetch = readl_relaxed(base + L310_PREFETCH_CTRL);
704 661
@@ -712,23 +669,12 @@ static void __init l2c310_enable(void __iomem *base, u32 aux, unsigned num_lock)
712 if (rev >= L310_CACHE_ID_RTL_R3P0) { 669 if (rev >= L310_CACHE_ID_RTL_R3P0) {
713 u32 power_ctrl; 670 u32 power_ctrl;
714 671
715 l2c_write_sec(L310_DYNAMIC_CLK_GATING_EN | L310_STNDBY_MODE_EN,
716 base, L310_POWER_CTRL);
717 power_ctrl = readl_relaxed(base + L310_POWER_CTRL); 672 power_ctrl = readl_relaxed(base + L310_POWER_CTRL);
718 pr_info("L2C-310 dynamic clock gating %sabled, standby mode %sabled\n", 673 pr_info("L2C-310 dynamic clock gating %sabled, standby mode %sabled\n",
719 power_ctrl & L310_DYNAMIC_CLK_GATING_EN ? "en" : "dis", 674 power_ctrl & L310_DYNAMIC_CLK_GATING_EN ? "en" : "dis",
720 power_ctrl & L310_STNDBY_MODE_EN ? "en" : "dis"); 675 power_ctrl & L310_STNDBY_MODE_EN ? "en" : "dis");
721 } 676 }
722 677
723 /*
724 * Always enable non-secure access to the lockdown registers -
725 * we write to them as part of the L2C enable sequence so they
726 * need to be accessible.
727 */
728 aux |= L310_AUX_CTRL_NS_LOCKDOWN;
729
730 l2c_enable(base, aux, num_lock);
731
732 if (aux & L310_AUX_CTRL_FULL_LINE_ZERO) { 678 if (aux & L310_AUX_CTRL_FULL_LINE_ZERO) {
733 set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1)); 679 set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1));
734 cpu_notifier(l2c310_cpu_enable_flz, 0); 680 cpu_notifier(l2c310_cpu_enable_flz, 0);
@@ -760,11 +706,11 @@ static void __init l2c310_fixup(void __iomem *base, u32 cache_id,
760 706
761 if (revision >= L310_CACHE_ID_RTL_R3P0 && 707 if (revision >= L310_CACHE_ID_RTL_R3P0 &&
762 revision < L310_CACHE_ID_RTL_R3P2) { 708 revision < L310_CACHE_ID_RTL_R3P2) {
763 u32 val = readl_relaxed(base + L310_PREFETCH_CTRL); 709 u32 val = l2x0_saved_regs.prefetch_ctrl;
764 /* I don't think bit23 is required here... but iMX6 does so */ 710 /* I don't think bit23 is required here... but iMX6 does so */
765 if (val & (BIT(30) | BIT(23))) { 711 if (val & (BIT(30) | BIT(23))) {
766 val &= ~(BIT(30) | BIT(23)); 712 val &= ~(BIT(30) | BIT(23));
767 l2c_write_sec(val, base, L310_PREFETCH_CTRL); 713 l2x0_saved_regs.prefetch_ctrl = val;
768 errata[n++] = "752271"; 714 errata[n++] = "752271";
769 } 715 }
770 } 716 }
@@ -800,6 +746,15 @@ static void l2c310_disable(void)
800 l2c_disable(); 746 l2c_disable();
801} 747}
802 748
749static void l2c310_resume(void)
750{
751 l2c_resume();
752
753 /* Re-enable full-line-of-zeros for Cortex-A9 */
754 if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_FULL_LINE_ZERO)
755 set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1));
756}
757
803static const struct l2c_init_data l2c310_init_fns __initconst = { 758static const struct l2c_init_data l2c310_init_fns __initconst = {
804 .type = "L2C-310", 759 .type = "L2C-310",
805 .way_size_0 = SZ_8K, 760 .way_size_0 = SZ_8K,
@@ -807,6 +762,7 @@ static const struct l2c_init_data l2c310_init_fns __initconst = {
807 .enable = l2c310_enable, 762 .enable = l2c310_enable,
808 .fixup = l2c310_fixup, 763 .fixup = l2c310_fixup,
809 .save = l2c310_save, 764 .save = l2c310_save,
765 .configure = l2c310_configure,
810 .outer_cache = { 766 .outer_cache = {
811 .inv_range = l2c210_inv_range, 767 .inv_range = l2c210_inv_range,
812 .clean_range = l2c210_clean_range, 768 .clean_range = l2c210_clean_range,
@@ -818,14 +774,22 @@ static const struct l2c_init_data l2c310_init_fns __initconst = {
818 }, 774 },
819}; 775};
820 776
821static void __init __l2c_init(const struct l2c_init_data *data, 777static int __init __l2c_init(const struct l2c_init_data *data,
822 u32 aux_val, u32 aux_mask, u32 cache_id) 778 u32 aux_val, u32 aux_mask, u32 cache_id)
823{ 779{
824 struct outer_cache_fns fns; 780 struct outer_cache_fns fns;
825 unsigned way_size_bits, ways; 781 unsigned way_size_bits, ways;
826 u32 aux, old_aux; 782 u32 aux, old_aux;
827 783
828 /* 784 /*
785 * Save the pointer globally so that callbacks which do not receive
786 * context from callers can access the structure.
787 */
788 l2x0_data = kmemdup(data, sizeof(*data), GFP_KERNEL);
789 if (!l2x0_data)
790 return -ENOMEM;
791
792 /*
829 * Sanity check the aux values. aux_mask is the bits we preserve 793 * Sanity check the aux values. aux_mask is the bits we preserve
830 * from reading the hardware register, and aux_val is the bits we 794 * from reading the hardware register, and aux_val is the bits we
831 * set. 795 * set.
@@ -884,6 +848,7 @@ static void __init __l2c_init(const struct l2c_init_data *data,
884 848
885 fns = data->outer_cache; 849 fns = data->outer_cache;
886 fns.write_sec = outer_cache.write_sec; 850 fns.write_sec = outer_cache.write_sec;
851 fns.configure = outer_cache.configure;
887 if (data->fixup) 852 if (data->fixup)
888 data->fixup(l2x0_base, cache_id, &fns); 853 data->fixup(l2x0_base, cache_id, &fns);
889 854
@@ -910,6 +875,8 @@ static void __init __l2c_init(const struct l2c_init_data *data,
910 data->type, ways, l2x0_size >> 10); 875 data->type, ways, l2x0_size >> 10);
911 pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n", 876 pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
912 data->type, cache_id, aux); 877 data->type, cache_id, aux);
878
879 return 0;
913} 880}
914 881
915void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) 882void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
@@ -936,6 +903,10 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
936 break; 903 break;
937 } 904 }
938 905
906 /* Read back current (default) hardware configuration */
907 if (data->save)
908 data->save(l2x0_base);
909
939 __l2c_init(data, aux_val, aux_mask, cache_id); 910 __l2c_init(data, aux_val, aux_mask, cache_id);
940} 911}
941 912
@@ -1102,7 +1073,7 @@ static const struct l2c_init_data of_l2c210_data __initconst = {
1102 .flush_all = l2c210_flush_all, 1073 .flush_all = l2c210_flush_all,
1103 .disable = l2c_disable, 1074 .disable = l2c_disable,
1104 .sync = l2c210_sync, 1075 .sync = l2c210_sync,
1105 .resume = l2c210_resume, 1076 .resume = l2c_resume,
1106 }, 1077 },
1107}; 1078};
1108 1079
@@ -1120,7 +1091,7 @@ static const struct l2c_init_data of_l2c220_data __initconst = {
1120 .flush_all = l2c220_flush_all, 1091 .flush_all = l2c220_flush_all,
1121 .disable = l2c_disable, 1092 .disable = l2c_disable,
1122 .sync = l2c220_sync, 1093 .sync = l2c220_sync,
1123 .resume = l2c210_resume, 1094 .resume = l2c_resume,
1124 }, 1095 },
1125}; 1096};
1126 1097
@@ -1131,32 +1102,32 @@ static void __init l2c310_of_parse(const struct device_node *np,
1131 u32 tag[3] = { 0, 0, 0 }; 1102 u32 tag[3] = { 0, 0, 0 };
1132 u32 filter[2] = { 0, 0 }; 1103 u32 filter[2] = { 0, 0 };
1133 u32 assoc; 1104 u32 assoc;
1105 u32 prefetch;
1106 u32 val;
1134 int ret; 1107 int ret;
1135 1108
1136 of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag)); 1109 of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
1137 if (tag[0] && tag[1] && tag[2]) 1110 if (tag[0] && tag[1] && tag[2])
1138 writel_relaxed( 1111 l2x0_saved_regs.tag_latency =
1139 L310_LATENCY_CTRL_RD(tag[0] - 1) | 1112 L310_LATENCY_CTRL_RD(tag[0] - 1) |
1140 L310_LATENCY_CTRL_WR(tag[1] - 1) | 1113 L310_LATENCY_CTRL_WR(tag[1] - 1) |
1141 L310_LATENCY_CTRL_SETUP(tag[2] - 1), 1114 L310_LATENCY_CTRL_SETUP(tag[2] - 1);
1142 l2x0_base + L310_TAG_LATENCY_CTRL);
1143 1115
1144 of_property_read_u32_array(np, "arm,data-latency", 1116 of_property_read_u32_array(np, "arm,data-latency",
1145 data, ARRAY_SIZE(data)); 1117 data, ARRAY_SIZE(data));
1146 if (data[0] && data[1] && data[2]) 1118 if (data[0] && data[1] && data[2])
1147 writel_relaxed( 1119 l2x0_saved_regs.data_latency =
1148 L310_LATENCY_CTRL_RD(data[0] - 1) | 1120 L310_LATENCY_CTRL_RD(data[0] - 1) |
1149 L310_LATENCY_CTRL_WR(data[1] - 1) | 1121 L310_LATENCY_CTRL_WR(data[1] - 1) |
1150 L310_LATENCY_CTRL_SETUP(data[2] - 1), 1122 L310_LATENCY_CTRL_SETUP(data[2] - 1);
1151 l2x0_base + L310_DATA_LATENCY_CTRL);
1152 1123
1153 of_property_read_u32_array(np, "arm,filter-ranges", 1124 of_property_read_u32_array(np, "arm,filter-ranges",
1154 filter, ARRAY_SIZE(filter)); 1125 filter, ARRAY_SIZE(filter));
1155 if (filter[1]) { 1126 if (filter[1]) {
1156 writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M), 1127 l2x0_saved_regs.filter_end =
1157 l2x0_base + L310_ADDR_FILTER_END); 1128 ALIGN(filter[0] + filter[1], SZ_1M);
1158 writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L310_ADDR_FILTER_EN, 1129 l2x0_saved_regs.filter_start = (filter[0] & ~(SZ_1M - 1))
1159 l2x0_base + L310_ADDR_FILTER_START); 1130 | L310_ADDR_FILTER_EN;
1160 } 1131 }
1161 1132
1162 ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_512K); 1133 ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_512K);
@@ -1178,6 +1149,58 @@ static void __init l2c310_of_parse(const struct device_node *np,
1178 assoc); 1149 assoc);
1179 break; 1150 break;
1180 } 1151 }
1152
1153 prefetch = l2x0_saved_regs.prefetch_ctrl;
1154
1155 ret = of_property_read_u32(np, "arm,double-linefill", &val);
1156 if (ret == 0) {
1157 if (val)
1158 prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL;
1159 else
1160 prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL;
1161 } else if (ret != -EINVAL) {
1162 pr_err("L2C-310 OF arm,double-linefill property value is missing\n");
1163 }
1164
1165 ret = of_property_read_u32(np, "arm,double-linefill-incr", &val);
1166 if (ret == 0) {
1167 if (val)
1168 prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_INCR;
1169 else
1170 prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL_INCR;
1171 } else if (ret != -EINVAL) {
1172 pr_err("L2C-310 OF arm,double-linefill-incr property value is missing\n");
1173 }
1174
1175 ret = of_property_read_u32(np, "arm,double-linefill-wrap", &val);
1176 if (ret == 0) {
1177 if (!val)
1178 prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP;
1179 else
1180 prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP;
1181 } else if (ret != -EINVAL) {
1182 pr_err("L2C-310 OF arm,double-linefill-wrap property value is missing\n");
1183 }
1184
1185 ret = of_property_read_u32(np, "arm,prefetch-drop", &val);
1186 if (ret == 0) {
1187 if (val)
1188 prefetch |= L310_PREFETCH_CTRL_PREFETCH_DROP;
1189 else
1190 prefetch &= ~L310_PREFETCH_CTRL_PREFETCH_DROP;
1191 } else if (ret != -EINVAL) {
1192 pr_err("L2C-310 OF arm,prefetch-drop property value is missing\n");
1193 }
1194
1195 ret = of_property_read_u32(np, "arm,prefetch-offset", &val);
1196 if (ret == 0) {
1197 prefetch &= ~L310_PREFETCH_CTRL_OFFSET_MASK;
1198 prefetch |= val & L310_PREFETCH_CTRL_OFFSET_MASK;
1199 } else if (ret != -EINVAL) {
1200 pr_err("L2C-310 OF arm,prefetch-offset property value is missing\n");
1201 }
1202
1203 l2x0_saved_regs.prefetch_ctrl = prefetch;
1181} 1204}
1182 1205
1183static const struct l2c_init_data of_l2c310_data __initconst = { 1206static const struct l2c_init_data of_l2c310_data __initconst = {
@@ -1188,6 +1211,7 @@ static const struct l2c_init_data of_l2c310_data __initconst = {
1188 .enable = l2c310_enable, 1211 .enable = l2c310_enable,
1189 .fixup = l2c310_fixup, 1212 .fixup = l2c310_fixup,
1190 .save = l2c310_save, 1213 .save = l2c310_save,
1214 .configure = l2c310_configure,
1191 .outer_cache = { 1215 .outer_cache = {
1192 .inv_range = l2c210_inv_range, 1216 .inv_range = l2c210_inv_range,
1193 .clean_range = l2c210_clean_range, 1217 .clean_range = l2c210_clean_range,
@@ -1216,6 +1240,7 @@ static const struct l2c_init_data of_l2c310_coherent_data __initconst = {
1216 .enable = l2c310_enable, 1240 .enable = l2c310_enable,
1217 .fixup = l2c310_fixup, 1241 .fixup = l2c310_fixup,
1218 .save = l2c310_save, 1242 .save = l2c310_save,
1243 .configure = l2c310_configure,
1219 .outer_cache = { 1244 .outer_cache = {
1220 .inv_range = l2c210_inv_range, 1245 .inv_range = l2c210_inv_range,
1221 .clean_range = l2c210_clean_range, 1246 .clean_range = l2c210_clean_range,
@@ -1231,7 +1256,7 @@ static const struct l2c_init_data of_l2c310_coherent_data __initconst = {
1231 * noninclusive, while the hardware cache range operations use 1256 * noninclusive, while the hardware cache range operations use
1232 * inclusive start and end addresses. 1257 * inclusive start and end addresses.
1233 */ 1258 */
1234static unsigned long calc_range_end(unsigned long start, unsigned long end) 1259static unsigned long aurora_range_end(unsigned long start, unsigned long end)
1235{ 1260{
1236 /* 1261 /*
1237 * Limit the number of cache lines processed at once, 1262 * Limit the number of cache lines processed at once,
@@ -1250,25 +1275,13 @@ static unsigned long calc_range_end(unsigned long start, unsigned long end)
1250 return end; 1275 return end;
1251} 1276}
1252 1277
1253/*
1254 * Make sure 'start' and 'end' reference the same page, as L2 is PIPT
1255 * and range operations only do a TLB lookup on the start address.
1256 */
1257static void aurora_pa_range(unsigned long start, unsigned long end, 1278static void aurora_pa_range(unsigned long start, unsigned long end,
1258 unsigned long offset) 1279 unsigned long offset)
1259{ 1280{
1281 void __iomem *base = l2x0_base;
1282 unsigned long range_end;
1260 unsigned long flags; 1283 unsigned long flags;
1261 1284
1262 raw_spin_lock_irqsave(&l2x0_lock, flags);
1263 writel_relaxed(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
1264 writel_relaxed(end, l2x0_base + offset);
1265 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
1266
1267 cache_sync();
1268}
1269
1270static void aurora_inv_range(unsigned long start, unsigned long end)
1271{
1272 /* 1285 /*
1273 * round start and end adresses up to cache line size 1286 * round start and end adresses up to cache line size
1274 */ 1287 */
@@ -1276,15 +1289,24 @@ static void aurora_inv_range(unsigned long start, unsigned long end)
1276 end = ALIGN(end, CACHE_LINE_SIZE); 1289 end = ALIGN(end, CACHE_LINE_SIZE);
1277 1290
1278 /* 1291 /*
1279 * Invalidate all full cache lines between 'start' and 'end'. 1292 * perform operation on all full cache lines between 'start' and 'end'
1280 */ 1293 */
1281 while (start < end) { 1294 while (start < end) {
1282 unsigned long range_end = calc_range_end(start, end); 1295 range_end = aurora_range_end(start, end);
1283 aurora_pa_range(start, range_end - CACHE_LINE_SIZE, 1296
1284 AURORA_INVAL_RANGE_REG); 1297 raw_spin_lock_irqsave(&l2x0_lock, flags);
1298 writel_relaxed(start, base + AURORA_RANGE_BASE_ADDR_REG);
1299 writel_relaxed(range_end - CACHE_LINE_SIZE, base + offset);
1300 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
1301
1302 writel_relaxed(0, base + AURORA_SYNC_REG);
1285 start = range_end; 1303 start = range_end;
1286 } 1304 }
1287} 1305}
1306static void aurora_inv_range(unsigned long start, unsigned long end)
1307{
1308 aurora_pa_range(start, end, AURORA_INVAL_RANGE_REG);
1309}
1288 1310
1289static void aurora_clean_range(unsigned long start, unsigned long end) 1311static void aurora_clean_range(unsigned long start, unsigned long end)
1290{ 1312{
@@ -1292,52 +1314,53 @@ static void aurora_clean_range(unsigned long start, unsigned long end)
1292 * If L2 is forced to WT, the L2 will always be clean and we 1314 * If L2 is forced to WT, the L2 will always be clean and we
1293 * don't need to do anything here. 1315 * don't need to do anything here.
1294 */ 1316 */
1295 if (!l2_wt_override) { 1317 if (!l2_wt_override)
1296 start &= ~(CACHE_LINE_SIZE - 1); 1318 aurora_pa_range(start, end, AURORA_CLEAN_RANGE_REG);
1297 end = ALIGN(end, CACHE_LINE_SIZE);
1298 while (start != end) {
1299 unsigned long range_end = calc_range_end(start, end);
1300 aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
1301 AURORA_CLEAN_RANGE_REG);
1302 start = range_end;
1303 }
1304 }
1305} 1319}
1306 1320
1307static void aurora_flush_range(unsigned long start, unsigned long end) 1321static void aurora_flush_range(unsigned long start, unsigned long end)
1308{ 1322{
1309 start &= ~(CACHE_LINE_SIZE - 1); 1323 if (l2_wt_override)
1310 end = ALIGN(end, CACHE_LINE_SIZE); 1324 aurora_pa_range(start, end, AURORA_INVAL_RANGE_REG);
1311 while (start != end) { 1325 else
1312 unsigned long range_end = calc_range_end(start, end); 1326 aurora_pa_range(start, end, AURORA_FLUSH_RANGE_REG);
1313 /*
1314 * If L2 is forced to WT, the L2 will always be clean and we
1315 * just need to invalidate.
1316 */
1317 if (l2_wt_override)
1318 aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
1319 AURORA_INVAL_RANGE_REG);
1320 else
1321 aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
1322 AURORA_FLUSH_RANGE_REG);
1323 start = range_end;
1324 }
1325} 1327}
1326 1328
1327static void aurora_save(void __iomem *base) 1329static void aurora_flush_all(void)
1328{ 1330{
1329 l2x0_saved_regs.ctrl = readl_relaxed(base + L2X0_CTRL); 1331 void __iomem *base = l2x0_base;
1330 l2x0_saved_regs.aux_ctrl = readl_relaxed(base + L2X0_AUX_CTRL); 1332 unsigned long flags;
1333
1334 /* clean all ways */
1335 raw_spin_lock_irqsave(&l2x0_lock, flags);
1336 __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
1337 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
1338
1339 writel_relaxed(0, base + AURORA_SYNC_REG);
1331} 1340}
1332 1341
1333static void aurora_resume(void) 1342static void aurora_cache_sync(void)
1343{
1344 writel_relaxed(0, l2x0_base + AURORA_SYNC_REG);
1345}
1346
1347static void aurora_disable(void)
1334{ 1348{
1335 void __iomem *base = l2x0_base; 1349 void __iomem *base = l2x0_base;
1350 unsigned long flags;
1336 1351
1337 if (!(readl(base + L2X0_CTRL) & L2X0_CTRL_EN)) { 1352 raw_spin_lock_irqsave(&l2x0_lock, flags);
1338 writel_relaxed(l2x0_saved_regs.aux_ctrl, base + L2X0_AUX_CTRL); 1353 __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
1339 writel_relaxed(l2x0_saved_regs.ctrl, base + L2X0_CTRL); 1354 writel_relaxed(0, base + AURORA_SYNC_REG);
1340 } 1355 l2c_write_sec(0, base, L2X0_CTRL);
1356 dsb(st);
1357 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
1358}
1359
1360static void aurora_save(void __iomem *base)
1361{
1362 l2x0_saved_regs.ctrl = readl_relaxed(base + L2X0_CTRL);
1363 l2x0_saved_regs.aux_ctrl = readl_relaxed(base + L2X0_AUX_CTRL);
1341} 1364}
1342 1365
1343/* 1366/*
@@ -1398,10 +1421,10 @@ static const struct l2c_init_data of_aurora_with_outer_data __initconst = {
1398 .inv_range = aurora_inv_range, 1421 .inv_range = aurora_inv_range,
1399 .clean_range = aurora_clean_range, 1422 .clean_range = aurora_clean_range,
1400 .flush_range = aurora_flush_range, 1423 .flush_range = aurora_flush_range,
1401 .flush_all = l2x0_flush_all, 1424 .flush_all = aurora_flush_all,
1402 .disable = l2x0_disable, 1425 .disable = aurora_disable,
1403 .sync = l2x0_cache_sync, 1426 .sync = aurora_cache_sync,
1404 .resume = aurora_resume, 1427 .resume = l2c_resume,
1405 }, 1428 },
1406}; 1429};
1407 1430
@@ -1414,7 +1437,7 @@ static const struct l2c_init_data of_aurora_no_outer_data __initconst = {
1414 .fixup = aurora_fixup, 1437 .fixup = aurora_fixup,
1415 .save = aurora_save, 1438 .save = aurora_save,
1416 .outer_cache = { 1439 .outer_cache = {
1417 .resume = aurora_resume, 1440 .resume = l2c_resume,
1418 }, 1441 },
1419}; 1442};
1420 1443
@@ -1562,6 +1585,7 @@ static const struct l2c_init_data of_bcm_l2x0_data __initconst = {
1562 .of_parse = l2c310_of_parse, 1585 .of_parse = l2c310_of_parse,
1563 .enable = l2c310_enable, 1586 .enable = l2c310_enable,
1564 .save = l2c310_save, 1587 .save = l2c310_save,
1588 .configure = l2c310_configure,
1565 .outer_cache = { 1589 .outer_cache = {
1566 .inv_range = bcm_inv_range, 1590 .inv_range = bcm_inv_range,
1567 .clean_range = bcm_clean_range, 1591 .clean_range = bcm_clean_range,
@@ -1583,18 +1607,12 @@ static void __init tauros3_save(void __iomem *base)
1583 readl_relaxed(base + L310_PREFETCH_CTRL); 1607 readl_relaxed(base + L310_PREFETCH_CTRL);
1584} 1608}
1585 1609
1586static void tauros3_resume(void) 1610static void tauros3_configure(void __iomem *base)
1587{ 1611{
1588 void __iomem *base = l2x0_base; 1612 writel_relaxed(l2x0_saved_regs.aux2_ctrl,
1589 1613 base + TAUROS3_AUX2_CTRL);
1590 if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) { 1614 writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
1591 writel_relaxed(l2x0_saved_regs.aux2_ctrl, 1615 base + L310_PREFETCH_CTRL);
1592 base + TAUROS3_AUX2_CTRL);
1593 writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
1594 base + L310_PREFETCH_CTRL);
1595
1596 l2c_enable(base, l2x0_saved_regs.aux_ctrl, 8);
1597 }
1598} 1616}
1599 1617
1600static const struct l2c_init_data of_tauros3_data __initconst = { 1618static const struct l2c_init_data of_tauros3_data __initconst = {
@@ -1603,9 +1621,10 @@ static const struct l2c_init_data of_tauros3_data __initconst = {
1603 .num_lock = 8, 1621 .num_lock = 8,
1604 .enable = l2c_enable, 1622 .enable = l2c_enable,
1605 .save = tauros3_save, 1623 .save = tauros3_save,
1624 .configure = tauros3_configure,
1606 /* Tauros3 broadcasts L1 cache operations to L2 */ 1625 /* Tauros3 broadcasts L1 cache operations to L2 */
1607 .outer_cache = { 1626 .outer_cache = {
1608 .resume = tauros3_resume, 1627 .resume = l2c_resume,
1609 }, 1628 },
1610}; 1629};
1611 1630
@@ -1661,6 +1680,10 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
1661 if (!of_property_read_bool(np, "cache-unified")) 1680 if (!of_property_read_bool(np, "cache-unified"))
1662 pr_err("L2C: device tree omits to specify unified cache\n"); 1681 pr_err("L2C: device tree omits to specify unified cache\n");
1663 1682
1683 /* Read back current (default) hardware configuration */
1684 if (data->save)
1685 data->save(l2x0_base);
1686
1664 /* L2 configuration can only be changed if the cache is disabled */ 1687 /* L2 configuration can only be changed if the cache is disabled */
1665 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) 1688 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN))
1666 if (data->of_parse) 1689 if (data->of_parse)
@@ -1671,8 +1694,6 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
1671 else 1694 else
1672 cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); 1695 cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
1673 1696
1674 __l2c_init(data, aux_val, aux_mask, cache_id); 1697 return __l2c_init(data, aux_val, aux_mask, cache_id);
1675
1676 return 0;
1677} 1698}
1678#endif 1699#endif
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 91892569710f..845769e41332 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -144,21 +144,17 @@ static void flush_context(unsigned int cpu)
144 /* Update the list of reserved ASIDs and the ASID bitmap. */ 144 /* Update the list of reserved ASIDs and the ASID bitmap. */
145 bitmap_clear(asid_map, 0, NUM_USER_ASIDS); 145 bitmap_clear(asid_map, 0, NUM_USER_ASIDS);
146 for_each_possible_cpu(i) { 146 for_each_possible_cpu(i) {
147 if (i == cpu) { 147 asid = atomic64_xchg(&per_cpu(active_asids, i), 0);
148 asid = 0; 148 /*
149 } else { 149 * If this CPU has already been through a
150 asid = atomic64_xchg(&per_cpu(active_asids, i), 0); 150 * rollover, but hasn't run another task in
151 /* 151 * the meantime, we must preserve its reserved
152 * If this CPU has already been through a 152 * ASID, as this is the only trace we have of
153 * rollover, but hasn't run another task in 153 * the process it is still running.
154 * the meantime, we must preserve its reserved 154 */
155 * ASID, as this is the only trace we have of 155 if (asid == 0)
156 * the process it is still running. 156 asid = per_cpu(reserved_asids, i);
157 */ 157 __set_bit(asid & ~ASID_MASK, asid_map);
158 if (asid == 0)
159 asid = per_cpu(reserved_asids, i);
160 __set_bit(asid & ~ASID_MASK, asid_map);
161 }
162 per_cpu(reserved_asids, i) = asid; 158 per_cpu(reserved_asids, i) = asid;
163 } 159 }
164 160
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 7864797609b3..f142ddd6c40a 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -2025,6 +2025,9 @@ static void arm_teardown_iommu_dma_ops(struct device *dev)
2025{ 2025{
2026 struct dma_iommu_mapping *mapping = dev->archdata.mapping; 2026 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
2027 2027
2028 if (!mapping)
2029 return;
2030
2028 arm_iommu_detach_device(dev); 2031 arm_iommu_detach_device(dev);
2029 arm_iommu_release_mapping(mapping); 2032 arm_iommu_release_mapping(mapping);
2030} 2033}
diff --git a/arch/arm/mm/dump.c b/arch/arm/mm/dump.c
index 59424937e52b..9fe8e241335c 100644
--- a/arch/arm/mm/dump.c
+++ b/arch/arm/mm/dump.c
@@ -220,9 +220,6 @@ static void note_page(struct pg_state *st, unsigned long addr, unsigned level, u
220 static const char units[] = "KMGTPE"; 220 static const char units[] = "KMGTPE";
221 u64 prot = val & pg_level[level].mask; 221 u64 prot = val & pg_level[level].mask;
222 222
223 if (addr < USER_PGTABLES_CEILING)
224 return;
225
226 if (!st->level) { 223 if (!st->level) {
227 st->level = level; 224 st->level = level;
228 st->current_prot = prot; 225 st->current_prot = prot;
@@ -308,15 +305,13 @@ static void walk_pgd(struct seq_file *m)
308 pgd_t *pgd = swapper_pg_dir; 305 pgd_t *pgd = swapper_pg_dir;
309 struct pg_state st; 306 struct pg_state st;
310 unsigned long addr; 307 unsigned long addr;
311 unsigned i, pgdoff = USER_PGTABLES_CEILING / PGDIR_SIZE; 308 unsigned i;
312 309
313 memset(&st, 0, sizeof(st)); 310 memset(&st, 0, sizeof(st));
314 st.seq = m; 311 st.seq = m;
315 st.marker = address_markers; 312 st.marker = address_markers;
316 313
317 pgd += pgdoff; 314 for (i = 0; i < PTRS_PER_PGD; i++, pgd++) {
318
319 for (i = pgdoff; i < PTRS_PER_PGD; i++, pgd++) {
320 addr = i * PGDIR_SIZE; 315 addr = i * PGDIR_SIZE;
321 if (!pgd_none(*pgd)) { 316 if (!pgd_none(*pgd)) {
322 walk_pud(&st, pgd, addr); 317 walk_pud(&st, pgd, addr);
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index d538dc73fcb0..1609b022a72f 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -655,8 +655,8 @@ static struct section_perm ro_perms[] = {
655 .start = (unsigned long)_stext, 655 .start = (unsigned long)_stext,
656 .end = (unsigned long)__init_begin, 656 .end = (unsigned long)__init_begin,
657#ifdef CONFIG_ARM_LPAE 657#ifdef CONFIG_ARM_LPAE
658 .mask = ~PMD_SECT_RDONLY, 658 .mask = ~L_PMD_SECT_RDONLY,
659 .prot = PMD_SECT_RDONLY, 659 .prot = L_PMD_SECT_RDONLY,
660#else 660#else
661 .mask = ~(PMD_SECT_APX | PMD_SECT_AP_WRITE), 661 .mask = ~(PMD_SECT_APX | PMD_SECT_AP_WRITE),
662 .prot = PMD_SECT_APX | PMD_SECT_AP_WRITE, 662 .prot = PMD_SECT_APX | PMD_SECT_AP_WRITE,
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index cda7c40999b6..4e6ef896c619 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -1329,8 +1329,8 @@ static void __init kmap_init(void)
1329static void __init map_lowmem(void) 1329static void __init map_lowmem(void)
1330{ 1330{
1331 struct memblock_region *reg; 1331 struct memblock_region *reg;
1332 unsigned long kernel_x_start = round_down(__pa(_stext), SECTION_SIZE); 1332 phys_addr_t kernel_x_start = round_down(__pa(_stext), SECTION_SIZE);
1333 unsigned long kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE); 1333 phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
1334 1334
1335 /* Map all the lowmem memory banks. */ 1335 /* Map all the lowmem memory banks. */
1336 for_each_memblock(memory, reg) { 1336 for_each_memblock(memory, reg) {
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-03 03:11:13 -0500