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-rw-r--r--arch/mips/include/asm/mach-ar7/ar7.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/include/asm/mach-ar7/ar7.h b/arch/mips/include/asm/mach-ar7/ar7.h
index f1cf38943497..483ffea9ecb1 100644
--- a/arch/mips/include/asm/mach-ar7/ar7.h
+++ b/arch/mips/include/asm/mach-ar7/ar7.h
@@ -50,7 +50,7 @@
50#define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00) 50#define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00)
51#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00) 51#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
52 52
53#define AR7_RESET_PEREPHERIAL 0x0 53#define AR7_RESET_PERIPHERAL 0x0
54#define AR7_RESET_SOFTWARE 0x4 54#define AR7_RESET_SOFTWARE 0x4
55#define AR7_RESET_STATUS 0x8 55#define AR7_RESET_STATUS 0x8
56 56
@@ -128,7 +128,7 @@ static inline int ar7_has_high_cpmac(void)
128static inline void ar7_device_enable(u32 bit) 128static inline void ar7_device_enable(u32 bit)
129{ 129{
130 void *reset_reg = 130 void *reset_reg =
131 (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL); 131 (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL);
132 writel(readl(reset_reg) | (1 << bit), reset_reg); 132 writel(readl(reset_reg) | (1 << bit), reset_reg);
133 msleep(20); 133 msleep(20);
134} 134}
@@ -136,7 +136,7 @@ static inline void ar7_device_enable(u32 bit)
136static inline void ar7_device_disable(u32 bit) 136static inline void ar7_device_disable(u32 bit)
137{ 137{
138 void *reset_reg = 138 void *reset_reg =
139 (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL); 139 (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL);
140 writel(readl(reset_reg) & ~(1 << bit), reset_reg); 140 writel(readl(reset_reg) & ~(1 << bit), reset_reg);
141 msleep(20); 141 msleep(20);
142} 142}