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-rw-r--r--arch/arm/Kconfig13
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/compressed/head.S6
-rw-r--r--arch/arm/configs/dove_defconfig1620
-rw-r--r--arch/arm/include/asm/hardware/cache-tauros2.h11
-rw-r--r--arch/arm/mach-dove/Kconfig14
-rw-r--r--arch/arm/mach-dove/Makefile3
-rw-r--r--arch/arm/mach-dove/Makefile.boot3
-rw-r--r--arch/arm/mach-dove/addr-map.c149
-rw-r--r--arch/arm/mach-dove/common.c781
-rw-r--r--arch/arm/mach-dove/common.h40
-rw-r--r--arch/arm/mach-dove/dove-db-setup.c102
-rw-r--r--arch/arm/mach-dove/include/mach/bridge-regs.h58
-rw-r--r--arch/arm/mach-dove/include/mach/debug-macro.S20
-rw-r--r--arch/arm/mach-dove/include/mach/dove.h180
-rw-r--r--arch/arm/mach-dove/include/mach/entry-macro.S39
-rw-r--r--arch/arm/mach-dove/include/mach/gpio.h49
-rw-r--r--arch/arm/mach-dove/include/mach/hardware.h26
-rw-r--r--arch/arm/mach-dove/include/mach/io.h20
-rw-r--r--arch/arm/mach-dove/include/mach/irqs.h101
-rw-r--r--arch/arm/mach-dove/include/mach/memory.h10
-rw-r--r--arch/arm/mach-dove/include/mach/pm.h54
-rw-r--r--arch/arm/mach-dove/include/mach/system.h36
-rw-r--r--arch/arm/mach-dove/include/mach/timex.h9
-rw-r--r--arch/arm/mach-dove/include/mach/uncompress.h37
-rw-r--r--arch/arm/mach-dove/include/mach/vmalloc.h5
-rw-r--r--arch/arm/mach-dove/irq.c133
-rw-r--r--arch/arm/mach-dove/pcie.c238
-rw-r--r--arch/arm/mach-kirkwood/Kconfig12
-rw-r--r--arch/arm/mach-kirkwood/Makefile3
-rw-r--r--arch/arm/mach-kirkwood/ts219-setup.c108
-rw-r--r--arch/arm/mach-kirkwood/ts41x-setup.c154
-rw-r--r--arch/arm/mach-kirkwood/tsx1x-common.c113
-rw-r--r--arch/arm/mach-kirkwood/tsx1x-common.h7
-rw-r--r--arch/arm/mm/Kconfig11
-rw-r--r--arch/arm/mm/Makefile2
-rw-r--r--arch/arm/mm/cache-tauros2.c263
-rw-r--r--arch/arm/mm/proc-v6.S33
38 files changed, 4355 insertions, 109 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 455284edda25..62152ae34758 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -433,6 +433,17 @@ config ARCH_L7200
433 If you have any questions or comments about the Linux kernel port 433 If you have any questions or comments about the Linux kernel port
434 to this board, send e-mail to <sjhill@cotw.com>. 434 to this board, send e-mail to <sjhill@cotw.com>.
435 435
436config ARCH_DOVE
437 bool "Marvell Dove"
438 select PCI
439 select GENERIC_GPIO
440 select ARCH_REQUIRE_GPIOLIB
441 select GENERIC_TIME
442 select GENERIC_CLOCKEVENTS
443 select PLAT_ORION
444 help
445 Support for the Marvell Dove SoC 88AP510
446
436config ARCH_KIRKWOOD 447config ARCH_KIRKWOOD
437 bool "Marvell Kirkwood" 448 bool "Marvell Kirkwood"
438 select CPU_FEROCEON 449 select CPU_FEROCEON
@@ -747,6 +758,8 @@ source "arch/arm/mach-orion5x/Kconfig"
747 758
748source "arch/arm/mach-kirkwood/Kconfig" 759source "arch/arm/mach-kirkwood/Kconfig"
749 760
761source "arch/arm/mach-dove/Kconfig"
762
750source "arch/arm/plat-s3c24xx/Kconfig" 763source "arch/arm/plat-s3c24xx/Kconfig"
751source "arch/arm/plat-s3c64xx/Kconfig" 764source "arch/arm/plat-s3c64xx/Kconfig"
752source "arch/arm/plat-s3c/Kconfig" 765source "arch/arm/plat-s3c/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index a73caaf66763..2ddc323b1c6a 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -122,6 +122,7 @@ machine-$(CONFIG_ARCH_AT91) := at91
122machine-$(CONFIG_ARCH_BCMRING) := bcmring 122machine-$(CONFIG_ARCH_BCMRING) := bcmring
123machine-$(CONFIG_ARCH_CLPS711X) := clps711x 123machine-$(CONFIG_ARCH_CLPS711X) := clps711x
124machine-$(CONFIG_ARCH_DAVINCI) := davinci 124machine-$(CONFIG_ARCH_DAVINCI) := davinci
125machine-$(CONFIG_ARCH_DOVE) := dove
125machine-$(CONFIG_ARCH_EBSA110) := ebsa110 126machine-$(CONFIG_ARCH_EBSA110) := ebsa110
126machine-$(CONFIG_ARCH_EP93XX) := ep93xx 127machine-$(CONFIG_ARCH_EP93XX) := ep93xx
127machine-$(CONFIG_ARCH_GEMINI) := gemini 128machine-$(CONFIG_ARCH_GEMINI) := gemini
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index fa6fbf45cf3b..d356af7cef82 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -743,6 +743,12 @@ proc_types:
743 W(b) __armv4_mmu_cache_off 743 W(b) __armv4_mmu_cache_off
744 W(b) __armv6_mmu_cache_flush 744 W(b) __armv6_mmu_cache_flush
745 745
746 .word 0x560f5810 @ Marvell PJ4 ARMv6
747 .word 0xff0ffff0
748 W(b) __armv4_mmu_cache_on
749 W(b) __armv4_mmu_cache_off
750 W(b) __armv6_mmu_cache_flush
751
746 .word 0x000f0000 @ new CPU Id 752 .word 0x000f0000 @ new CPU Id
747 .word 0x000f0000 753 .word 0x000f0000
748 W(b) __armv7_mmu_cache_on 754 W(b) __armv7_mmu_cache_on
diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig
new file mode 100644
index 000000000000..b3a491675d59
--- /dev/null
+++ b/arch/arm/configs/dove_defconfig
@@ -0,0 +1,1620 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.32-rc6
4# Tue Nov 24 13:53:37 2009
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_GENERIC_HARDIRQS=y
12CONFIG_STACKTRACE_SUPPORT=y
13CONFIG_HAVE_LATENCYTOP_SUPPORT=y
14CONFIG_LOCKDEP_SUPPORT=y
15CONFIG_TRACE_IRQFLAGS_SUPPORT=y
16CONFIG_HARDIRQS_SW_RESEND=y
17CONFIG_GENERIC_IRQ_PROBE=y
18CONFIG_RWSEM_GENERIC_SPINLOCK=y
19CONFIG_GENERIC_HWEIGHT=y
20CONFIG_GENERIC_CALIBRATE_DELAY=y
21CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
22CONFIG_VECTORS_BASE=0xffff0000
23CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
24CONFIG_CONSTRUCTORS=y
25
26#
27# General setup
28#
29CONFIG_EXPERIMENTAL=y
30CONFIG_BROKEN_ON_SMP=y
31CONFIG_INIT_ENV_ARG_LIMIT=32
32CONFIG_LOCALVERSION=""
33CONFIG_LOCALVERSION_AUTO=y
34CONFIG_SWAP=y
35CONFIG_SYSVIPC=y
36CONFIG_SYSVIPC_SYSCTL=y
37# CONFIG_POSIX_MQUEUE is not set
38# CONFIG_BSD_PROCESS_ACCT is not set
39# CONFIG_TASKSTATS is not set
40# CONFIG_AUDIT is not set
41
42#
43# RCU Subsystem
44#
45CONFIG_TREE_RCU=y
46# CONFIG_TREE_PREEMPT_RCU is not set
47# CONFIG_RCU_TRACE is not set
48CONFIG_RCU_FANOUT=32
49# CONFIG_RCU_FANOUT_EXACT is not set
50# CONFIG_TREE_RCU_TRACE is not set
51# CONFIG_IKCONFIG is not set
52CONFIG_LOG_BUF_SHIFT=14
53# CONFIG_GROUP_SCHED is not set
54# CONFIG_CGROUPS is not set
55# CONFIG_SYSFS_DEPRECATED_V2 is not set
56# CONFIG_RELAY is not set
57# CONFIG_NAMESPACES is not set
58# CONFIG_BLK_DEV_INITRD is not set
59CONFIG_CC_OPTIMIZE_FOR_SIZE=y
60CONFIG_SYSCTL=y
61CONFIG_ANON_INODES=y
62CONFIG_EMBEDDED=y
63CONFIG_UID16=y
64CONFIG_SYSCTL_SYSCALL=y
65CONFIG_KALLSYMS=y
66# CONFIG_KALLSYMS_ALL is not set
67# CONFIG_KALLSYMS_EXTRA_PASS is not set
68CONFIG_HOTPLUG=y
69CONFIG_PRINTK=y
70CONFIG_BUG=y
71CONFIG_ELF_CORE=y
72CONFIG_BASE_FULL=y
73CONFIG_FUTEX=y
74CONFIG_EPOLL=y
75CONFIG_SIGNALFD=y
76CONFIG_TIMERFD=y
77CONFIG_EVENTFD=y
78CONFIG_SHMEM=y
79CONFIG_AIO=y
80
81#
82# Kernel Performance Events And Counters
83#
84CONFIG_VM_EVENT_COUNTERS=y
85CONFIG_PCI_QUIRKS=y
86CONFIG_COMPAT_BRK=y
87CONFIG_SLAB=y
88# CONFIG_SLUB is not set
89# CONFIG_SLOB is not set
90# CONFIG_PROFILING is not set
91CONFIG_HAVE_OPROFILE=y
92# CONFIG_KPROBES is not set
93CONFIG_HAVE_KPROBES=y
94CONFIG_HAVE_KRETPROBES=y
95
96#
97# GCOV-based kernel profiling
98#
99# CONFIG_GCOV_KERNEL is not set
100# CONFIG_SLOW_WORK is not set
101CONFIG_HAVE_GENERIC_DMA_COHERENT=y
102CONFIG_SLABINFO=y
103CONFIG_RT_MUTEXES=y
104CONFIG_BASE_SMALL=0
105CONFIG_MODULES=y
106# CONFIG_MODULE_FORCE_LOAD is not set
107CONFIG_MODULE_UNLOAD=y
108# CONFIG_MODULE_FORCE_UNLOAD is not set
109# CONFIG_MODVERSIONS is not set
110# CONFIG_MODULE_SRCVERSION_ALL is not set
111CONFIG_BLOCK=y
112CONFIG_LBDAF=y
113# CONFIG_BLK_DEV_BSG is not set
114# CONFIG_BLK_DEV_INTEGRITY is not set
115
116#
117# IO Schedulers
118#
119CONFIG_IOSCHED_NOOP=y
120CONFIG_IOSCHED_AS=y
121CONFIG_IOSCHED_DEADLINE=y
122CONFIG_IOSCHED_CFQ=y
123# CONFIG_DEFAULT_AS is not set
124# CONFIG_DEFAULT_DEADLINE is not set
125CONFIG_DEFAULT_CFQ=y
126# CONFIG_DEFAULT_NOOP is not set
127CONFIG_DEFAULT_IOSCHED="cfq"
128# CONFIG_FREEZER is not set
129
130#
131# System Type
132#
133CONFIG_MMU=y
134# CONFIG_ARCH_AAEC2000 is not set
135# CONFIG_ARCH_INTEGRATOR is not set
136# CONFIG_ARCH_REALVIEW is not set
137# CONFIG_ARCH_VERSATILE is not set
138# CONFIG_ARCH_AT91 is not set
139# CONFIG_ARCH_CLPS711X is not set
140# CONFIG_ARCH_GEMINI is not set
141# CONFIG_ARCH_EBSA110 is not set
142# CONFIG_ARCH_EP93XX is not set
143# CONFIG_ARCH_FOOTBRIDGE is not set
144# CONFIG_ARCH_MXC is not set
145# CONFIG_ARCH_STMP3XXX is not set
146# CONFIG_ARCH_NETX is not set
147# CONFIG_ARCH_H720X is not set
148# CONFIG_ARCH_NOMADIK is not set
149# CONFIG_ARCH_IOP13XX is not set
150# CONFIG_ARCH_IOP32X is not set
151# CONFIG_ARCH_IOP33X is not set
152# CONFIG_ARCH_IXP23XX is not set
153# CONFIG_ARCH_IXP2000 is not set
154# CONFIG_ARCH_IXP4XX is not set
155# CONFIG_ARCH_L7200 is not set
156CONFIG_ARCH_DOVE=y
157# CONFIG_ARCH_KIRKWOOD is not set
158# CONFIG_ARCH_LOKI is not set
159# CONFIG_ARCH_MV78XX0 is not set
160# CONFIG_ARCH_ORION5X is not set
161# CONFIG_ARCH_MMP is not set
162# CONFIG_ARCH_KS8695 is not set
163# CONFIG_ARCH_NS9XXX is not set
164# CONFIG_ARCH_W90X900 is not set
165# CONFIG_ARCH_PNX4008 is not set
166# CONFIG_ARCH_PXA is not set
167# CONFIG_ARCH_MSM is not set
168# CONFIG_ARCH_RPC is not set
169# CONFIG_ARCH_SA1100 is not set
170# CONFIG_ARCH_S3C2410 is not set
171# CONFIG_ARCH_S3C64XX is not set
172# CONFIG_ARCH_S5PC1XX is not set
173# CONFIG_ARCH_SHARK is not set
174# CONFIG_ARCH_LH7A40X is not set
175# CONFIG_ARCH_U300 is not set
176# CONFIG_ARCH_DAVINCI is not set
177# CONFIG_ARCH_OMAP is not set
178# CONFIG_ARCH_BCMRING is not set
179
180#
181# Marvell Dove Implementations
182#
183CONFIG_MACH_DOVE_DB=y
184CONFIG_PLAT_ORION=y
185
186#
187# Processor Type
188#
189CONFIG_CPU_32=y
190CONFIG_CPU_V6=y
191CONFIG_CPU_32v6K=y
192CONFIG_CPU_32v6=y
193CONFIG_CPU_ABRT_EV6=y
194CONFIG_CPU_PABRT_V6=y
195CONFIG_CPU_CACHE_V6=y
196CONFIG_CPU_CACHE_VIPT=y
197CONFIG_CPU_COPY_V6=y
198CONFIG_CPU_TLB_V6=y
199CONFIG_CPU_HAS_ASID=y
200CONFIG_CPU_CP15=y
201CONFIG_CPU_CP15_MMU=y
202
203#
204# Processor Features
205#
206CONFIG_ARM_THUMB=y
207# CONFIG_CPU_ICACHE_DISABLE is not set
208# CONFIG_CPU_DCACHE_DISABLE is not set
209# CONFIG_CPU_BPREDICT_DISABLE is not set
210CONFIG_OUTER_CACHE=y
211CONFIG_CACHE_TAUROS2=y
212CONFIG_ARM_L1_CACHE_SHIFT=5
213# CONFIG_ARM_ERRATA_411920 is not set
214
215#
216# Bus support
217#
218CONFIG_PCI=y
219CONFIG_PCI_SYSCALL=y
220# CONFIG_ARCH_SUPPORTS_MSI is not set
221CONFIG_PCI_LEGACY=y
222# CONFIG_PCI_DEBUG is not set
223# CONFIG_PCI_STUB is not set
224# CONFIG_PCI_IOV is not set
225# CONFIG_PCCARD is not set
226
227#
228# Kernel Features
229#
230CONFIG_TICK_ONESHOT=y
231CONFIG_NO_HZ=y
232CONFIG_HIGH_RES_TIMERS=y
233CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
234CONFIG_VMSPLIT_3G=y
235# CONFIG_VMSPLIT_2G is not set
236# CONFIG_VMSPLIT_1G is not set
237CONFIG_PAGE_OFFSET=0xC0000000
238CONFIG_PREEMPT_NONE=y
239# CONFIG_PREEMPT_VOLUNTARY is not set
240# CONFIG_PREEMPT is not set
241CONFIG_HZ=100
242CONFIG_AEABI=y
243CONFIG_OABI_COMPAT=y
244# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
245# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
246# CONFIG_HIGHMEM is not set
247CONFIG_SELECT_MEMORY_MODEL=y
248CONFIG_FLATMEM_MANUAL=y
249# CONFIG_DISCONTIGMEM_MANUAL is not set
250# CONFIG_SPARSEMEM_MANUAL is not set
251CONFIG_FLATMEM=y
252CONFIG_FLAT_NODE_MEM_MAP=y
253CONFIG_PAGEFLAGS_EXTENDED=y
254CONFIG_SPLIT_PTLOCK_CPUS=4
255# CONFIG_PHYS_ADDR_T_64BIT is not set
256CONFIG_ZONE_DMA_FLAG=0
257CONFIG_VIRT_TO_BUS=y
258CONFIG_HAVE_MLOCK=y
259CONFIG_HAVE_MLOCKED_PAGE_BIT=y
260# CONFIG_KSM is not set
261CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
262CONFIG_ALIGNMENT_TRAP=y
263# CONFIG_UACCESS_WITH_MEMCPY is not set
264
265#
266# Boot options
267#
268CONFIG_ZBOOT_ROM_TEXT=0x0
269CONFIG_ZBOOT_ROM_BSS=0x0
270CONFIG_CMDLINE=""
271# CONFIG_XIP_KERNEL is not set
272# CONFIG_KEXEC is not set
273
274#
275# CPU Power Management
276#
277# CONFIG_CPU_IDLE is not set
278
279#
280# Floating point emulation
281#
282
283#
284# At least one emulation must be selected
285#
286# CONFIG_FPE_NWFPE is not set
287# CONFIG_FPE_FASTFPE is not set
288CONFIG_VFP=y
289
290#
291# Userspace binary formats
292#
293CONFIG_BINFMT_ELF=y
294# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
295CONFIG_HAVE_AOUT=y
296# CONFIG_BINFMT_AOUT is not set
297# CONFIG_BINFMT_MISC is not set
298
299#
300# Power management options
301#
302# CONFIG_PM is not set
303CONFIG_ARCH_SUSPEND_POSSIBLE=y
304CONFIG_NET=y
305
306#
307# Networking options
308#
309CONFIG_PACKET=y
310CONFIG_PACKET_MMAP=y
311CONFIG_UNIX=y
312CONFIG_XFRM=y
313# CONFIG_XFRM_USER is not set
314# CONFIG_XFRM_SUB_POLICY is not set
315# CONFIG_XFRM_MIGRATE is not set
316# CONFIG_XFRM_STATISTICS is not set
317# CONFIG_NET_KEY is not set
318CONFIG_INET=y
319CONFIG_IP_MULTICAST=y
320# CONFIG_IP_ADVANCED_ROUTER is not set
321CONFIG_IP_FIB_HASH=y
322CONFIG_IP_PNP=y
323CONFIG_IP_PNP_DHCP=y
324CONFIG_IP_PNP_BOOTP=y
325# CONFIG_IP_PNP_RARP is not set
326# CONFIG_NET_IPIP is not set
327# CONFIG_NET_IPGRE is not set
328# CONFIG_IP_MROUTE is not set
329# CONFIG_ARPD is not set
330# CONFIG_SYN_COOKIES is not set
331# CONFIG_INET_AH is not set
332# CONFIG_INET_ESP is not set
333# CONFIG_INET_IPCOMP is not set
334# CONFIG_INET_XFRM_TUNNEL is not set
335# CONFIG_INET_TUNNEL is not set
336CONFIG_INET_XFRM_MODE_TRANSPORT=y
337CONFIG_INET_XFRM_MODE_TUNNEL=y
338CONFIG_INET_XFRM_MODE_BEET=y
339CONFIG_INET_LRO=y
340CONFIG_INET_DIAG=y
341CONFIG_INET_TCP_DIAG=y
342# CONFIG_TCP_CONG_ADVANCED is not set
343CONFIG_TCP_CONG_CUBIC=y
344CONFIG_DEFAULT_TCP_CONG="cubic"
345# CONFIG_TCP_MD5SIG is not set
346# CONFIG_IPV6 is not set
347# CONFIG_NETWORK_SECMARK is not set
348# CONFIG_NETFILTER is not set
349# CONFIG_IP_DCCP is not set
350# CONFIG_IP_SCTP is not set
351# CONFIG_RDS is not set
352# CONFIG_TIPC is not set
353# CONFIG_ATM is not set
354# CONFIG_BRIDGE is not set
355# CONFIG_NET_DSA is not set
356# CONFIG_VLAN_8021Q is not set
357# CONFIG_DECNET is not set
358# CONFIG_LLC2 is not set
359# CONFIG_IPX is not set
360# CONFIG_ATALK is not set
361# CONFIG_X25 is not set
362# CONFIG_LAPB is not set
363# CONFIG_ECONET is not set
364# CONFIG_WAN_ROUTER is not set
365# CONFIG_PHONET is not set
366# CONFIG_IEEE802154 is not set
367# CONFIG_NET_SCHED is not set
368# CONFIG_DCB is not set
369
370#
371# Network testing
372#
373# CONFIG_NET_PKTGEN is not set
374# CONFIG_HAMRADIO is not set
375# CONFIG_CAN is not set
376# CONFIG_IRDA is not set
377# CONFIG_BT is not set
378# CONFIG_AF_RXRPC is not set
379# CONFIG_WIRELESS is not set
380# CONFIG_WIMAX is not set
381# CONFIG_RFKILL is not set
382# CONFIG_NET_9P is not set
383
384#
385# Device Drivers
386#
387
388#
389# Generic Driver Options
390#
391CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
392# CONFIG_DEVTMPFS is not set
393CONFIG_STANDALONE=y
394CONFIG_PREVENT_FIRMWARE_BUILD=y
395CONFIG_FW_LOADER=y
396CONFIG_FIRMWARE_IN_KERNEL=y
397CONFIG_EXTRA_FIRMWARE=""
398# CONFIG_DEBUG_DRIVER is not set
399# CONFIG_DEBUG_DEVRES is not set
400# CONFIG_SYS_HYPERVISOR is not set
401# CONFIG_CONNECTOR is not set
402CONFIG_MTD=y
403# CONFIG_MTD_DEBUG is not set
404# CONFIG_MTD_TESTS is not set
405# CONFIG_MTD_CONCAT is not set
406CONFIG_MTD_PARTITIONS=y
407# CONFIG_MTD_REDBOOT_PARTS is not set
408CONFIG_MTD_CMDLINE_PARTS=y
409# CONFIG_MTD_AFS_PARTS is not set
410# CONFIG_MTD_AR7_PARTS is not set
411
412#
413# User Modules And Translation Layers
414#
415CONFIG_MTD_CHAR=y
416CONFIG_MTD_BLKDEVS=y
417CONFIG_MTD_BLOCK=y
418# CONFIG_FTL is not set
419# CONFIG_NFTL is not set
420# CONFIG_INFTL is not set
421# CONFIG_RFD_FTL is not set
422# CONFIG_SSFDC is not set
423# CONFIG_MTD_OOPS is not set
424
425#
426# RAM/ROM/Flash chip drivers
427#
428CONFIG_MTD_CFI=y
429CONFIG_MTD_JEDECPROBE=y
430CONFIG_MTD_GEN_PROBE=y
431CONFIG_MTD_CFI_ADV_OPTIONS=y
432CONFIG_MTD_CFI_NOSWAP=y
433# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
434# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
435CONFIG_MTD_CFI_GEOMETRY=y
436CONFIG_MTD_MAP_BANK_WIDTH_1=y
437CONFIG_MTD_MAP_BANK_WIDTH_2=y
438# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
439# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
440# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
441# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
442CONFIG_MTD_CFI_I1=y
443CONFIG_MTD_CFI_I2=y
444# CONFIG_MTD_CFI_I4 is not set
445# CONFIG_MTD_CFI_I8 is not set
446# CONFIG_MTD_OTP is not set
447CONFIG_MTD_CFI_INTELEXT=y
448# CONFIG_MTD_CFI_AMDSTD is not set
449CONFIG_MTD_CFI_STAA=y
450CONFIG_MTD_CFI_UTIL=y
451# CONFIG_MTD_RAM is not set
452# CONFIG_MTD_ROM is not set
453# CONFIG_MTD_ABSENT is not set
454
455#
456# Mapping drivers for chip access
457#
458# CONFIG_MTD_COMPLEX_MAPPINGS is not set
459CONFIG_MTD_PHYSMAP=y
460# CONFIG_MTD_PHYSMAP_COMPAT is not set
461# CONFIG_MTD_ARM_INTEGRATOR is not set
462# CONFIG_MTD_IMPA7 is not set
463# CONFIG_MTD_INTEL_VR_NOR is not set
464# CONFIG_MTD_PLATRAM is not set
465
466#
467# Self-contained MTD device drivers
468#
469# CONFIG_MTD_PMC551 is not set
470# CONFIG_MTD_DATAFLASH is not set
471CONFIG_MTD_M25P80=y
472CONFIG_M25PXX_USE_FAST_READ=y
473# CONFIG_MTD_SST25L is not set
474# CONFIG_MTD_SLRAM is not set
475# CONFIG_MTD_PHRAM is not set
476# CONFIG_MTD_MTDRAM is not set
477# CONFIG_MTD_BLOCK2MTD is not set
478
479#
480# Disk-On-Chip Device Drivers
481#
482# CONFIG_MTD_DOC2000 is not set
483# CONFIG_MTD_DOC2001 is not set
484# CONFIG_MTD_DOC2001PLUS is not set
485# CONFIG_MTD_NAND is not set
486# CONFIG_MTD_ONENAND is not set
487
488#
489# LPDDR flash memory drivers
490#
491# CONFIG_MTD_LPDDR is not set
492
493#
494# UBI - Unsorted block images
495#
496CONFIG_MTD_UBI=y
497CONFIG_MTD_UBI_WL_THRESHOLD=4096
498CONFIG_MTD_UBI_BEB_RESERVE=1
499# CONFIG_MTD_UBI_GLUEBI is not set
500
501#
502# UBI debugging options
503#
504# CONFIG_MTD_UBI_DEBUG is not set
505# CONFIG_PARPORT is not set
506CONFIG_BLK_DEV=y
507# CONFIG_BLK_CPQ_DA is not set
508# CONFIG_BLK_CPQ_CISS_DA is not set
509# CONFIG_BLK_DEV_DAC960 is not set
510# CONFIG_BLK_DEV_UMEM is not set
511# CONFIG_BLK_DEV_COW_COMMON is not set
512CONFIG_BLK_DEV_LOOP=y
513# CONFIG_BLK_DEV_CRYPTOLOOP is not set
514# CONFIG_BLK_DEV_NBD is not set
515# CONFIG_BLK_DEV_SX8 is not set
516# CONFIG_BLK_DEV_UB is not set
517CONFIG_BLK_DEV_RAM=y
518CONFIG_BLK_DEV_RAM_COUNT=1
519CONFIG_BLK_DEV_RAM_SIZE=4096
520# CONFIG_BLK_DEV_XIP is not set
521# CONFIG_CDROM_PKTCDVD is not set
522# CONFIG_ATA_OVER_ETH is not set
523# CONFIG_MG_DISK is not set
524# CONFIG_MISC_DEVICES is not set
525CONFIG_HAVE_IDE=y
526# CONFIG_IDE is not set
527
528#
529# SCSI device support
530#
531# CONFIG_RAID_ATTRS is not set
532CONFIG_SCSI=y
533CONFIG_SCSI_DMA=y
534# CONFIG_SCSI_TGT is not set
535# CONFIG_SCSI_NETLINK is not set
536# CONFIG_SCSI_PROC_FS is not set
537
538#
539# SCSI support type (disk, tape, CD-ROM)
540#
541CONFIG_BLK_DEV_SD=y
542# CONFIG_CHR_DEV_ST is not set
543# CONFIG_CHR_DEV_OSST is not set
544# CONFIG_BLK_DEV_SR is not set
545# CONFIG_CHR_DEV_SG is not set
546# CONFIG_CHR_DEV_SCH is not set
547# CONFIG_SCSI_MULTI_LUN is not set
548# CONFIG_SCSI_CONSTANTS is not set
549# CONFIG_SCSI_LOGGING is not set
550# CONFIG_SCSI_SCAN_ASYNC is not set
551CONFIG_SCSI_WAIT_SCAN=m
552
553#
554# SCSI Transports
555#
556# CONFIG_SCSI_SPI_ATTRS is not set
557# CONFIG_SCSI_FC_ATTRS is not set
558# CONFIG_SCSI_ISCSI_ATTRS is not set
559# CONFIG_SCSI_SAS_LIBSAS is not set
560# CONFIG_SCSI_SRP_ATTRS is not set
561# CONFIG_SCSI_LOWLEVEL is not set
562# CONFIG_SCSI_DH is not set
563# CONFIG_SCSI_OSD_INITIATOR is not set
564CONFIG_ATA=y
565# CONFIG_ATA_NONSTANDARD is not set
566CONFIG_ATA_VERBOSE_ERROR=y
567CONFIG_SATA_PMP=y
568# CONFIG_SATA_AHCI is not set
569# CONFIG_SATA_SIL24 is not set
570CONFIG_ATA_SFF=y
571# CONFIG_SATA_SVW is not set
572# CONFIG_ATA_PIIX is not set
573CONFIG_SATA_MV=y
574# CONFIG_SATA_NV is not set
575# CONFIG_PDC_ADMA is not set
576# CONFIG_SATA_QSTOR is not set
577# CONFIG_SATA_PROMISE is not set
578# CONFIG_SATA_SX4 is not set
579# CONFIG_SATA_SIL is not set
580# CONFIG_SATA_SIS is not set
581# CONFIG_SATA_ULI is not set
582# CONFIG_SATA_VIA is not set
583# CONFIG_SATA_VITESSE is not set
584# CONFIG_SATA_INIC162X is not set
585# CONFIG_PATA_ALI is not set
586# CONFIG_PATA_AMD is not set
587# CONFIG_PATA_ARTOP is not set
588# CONFIG_PATA_ATP867X is not set
589# CONFIG_PATA_ATIIXP is not set
590# CONFIG_PATA_CMD640_PCI is not set
591# CONFIG_PATA_CMD64X is not set
592# CONFIG_PATA_CS5520 is not set
593# CONFIG_PATA_CS5530 is not set
594# CONFIG_PATA_CYPRESS is not set
595# CONFIG_PATA_EFAR is not set
596# CONFIG_ATA_GENERIC is not set
597# CONFIG_PATA_HPT366 is not set
598# CONFIG_PATA_HPT37X is not set
599# CONFIG_PATA_HPT3X2N is not set
600# CONFIG_PATA_HPT3X3 is not set
601# CONFIG_PATA_IT821X is not set
602# CONFIG_PATA_IT8213 is not set
603# CONFIG_PATA_JMICRON is not set
604# CONFIG_PATA_TRIFLEX is not set
605# CONFIG_PATA_MARVELL is not set
606# CONFIG_PATA_MPIIX is not set
607# CONFIG_PATA_OLDPIIX is not set
608# CONFIG_PATA_NETCELL is not set
609# CONFIG_PATA_NINJA32 is not set
610# CONFIG_PATA_NS87410 is not set
611# CONFIG_PATA_NS87415 is not set
612# CONFIG_PATA_OPTI is not set
613# CONFIG_PATA_OPTIDMA is not set
614# CONFIG_PATA_PDC_OLD is not set
615# CONFIG_PATA_RADISYS is not set
616# CONFIG_PATA_RDC is not set
617# CONFIG_PATA_RZ1000 is not set
618# CONFIG_PATA_SC1200 is not set
619# CONFIG_PATA_SERVERWORKS is not set
620# CONFIG_PATA_PDC2027X is not set
621# CONFIG_PATA_SIL680 is not set
622# CONFIG_PATA_SIS is not set
623# CONFIG_PATA_VIA is not set
624# CONFIG_PATA_WINBOND is not set
625# CONFIG_PATA_PLATFORM is not set
626# CONFIG_PATA_SCH is not set
627# CONFIG_MD is not set
628# CONFIG_FUSION is not set
629
630#
631# IEEE 1394 (FireWire) support
632#
633
634#
635# You can enable one or both FireWire driver stacks.
636#
637
638#
639# See the help texts for more information.
640#
641# CONFIG_FIREWIRE is not set
642# CONFIG_IEEE1394 is not set
643# CONFIG_I2O is not set
644CONFIG_NETDEVICES=y
645# CONFIG_DUMMY is not set
646# CONFIG_BONDING is not set
647# CONFIG_MACVLAN is not set
648# CONFIG_EQUALIZER is not set
649# CONFIG_TUN is not set
650# CONFIG_VETH is not set
651# CONFIG_ARCNET is not set
652CONFIG_PHYLIB=y
653
654#
655# MII PHY device drivers
656#
657# CONFIG_MARVELL_PHY is not set
658# CONFIG_DAVICOM_PHY is not set
659# CONFIG_QSEMI_PHY is not set
660# CONFIG_LXT_PHY is not set
661# CONFIG_CICADA_PHY is not set
662# CONFIG_VITESSE_PHY is not set
663# CONFIG_SMSC_PHY is not set
664# CONFIG_BROADCOM_PHY is not set
665# CONFIG_ICPLUS_PHY is not set
666# CONFIG_REALTEK_PHY is not set
667# CONFIG_NATIONAL_PHY is not set
668# CONFIG_STE10XP is not set
669# CONFIG_LSI_ET1011C_PHY is not set
670# CONFIG_FIXED_PHY is not set
671# CONFIG_MDIO_BITBANG is not set
672# CONFIG_NET_ETHERNET is not set
673CONFIG_NETDEV_1000=y
674# CONFIG_ACENIC is not set
675# CONFIG_DL2K is not set
676# CONFIG_E1000 is not set
677# CONFIG_E1000E is not set
678# CONFIG_IP1000 is not set
679# CONFIG_IGB is not set
680# CONFIG_IGBVF is not set
681# CONFIG_NS83820 is not set
682# CONFIG_HAMACHI is not set
683# CONFIG_YELLOWFIN is not set
684# CONFIG_R8169 is not set
685# CONFIG_SIS190 is not set
686# CONFIG_SKGE is not set
687# CONFIG_SKY2 is not set
688# CONFIG_VIA_VELOCITY is not set
689# CONFIG_TIGON3 is not set
690# CONFIG_BNX2 is not set
691# CONFIG_CNIC is not set
692CONFIG_MV643XX_ETH=y
693# CONFIG_QLA3XXX is not set
694# CONFIG_ATL1 is not set
695# CONFIG_ATL1E is not set
696# CONFIG_ATL1C is not set
697# CONFIG_JME is not set
698# CONFIG_NETDEV_10000 is not set
699# CONFIG_TR is not set
700CONFIG_WLAN=y
701# CONFIG_WLAN_PRE80211 is not set
702# CONFIG_WLAN_80211 is not set
703
704#
705# Enable WiMAX (Networking options) to see the WiMAX drivers
706#
707
708#
709# USB Network Adapters
710#
711# CONFIG_USB_CATC is not set
712# CONFIG_USB_KAWETH is not set
713# CONFIG_USB_PEGASUS is not set
714# CONFIG_USB_RTL8150 is not set
715# CONFIG_USB_USBNET is not set
716# CONFIG_WAN is not set
717# CONFIG_FDDI is not set
718# CONFIG_HIPPI is not set
719# CONFIG_PPP is not set
720# CONFIG_SLIP is not set
721# CONFIG_NET_FC is not set
722# CONFIG_NETCONSOLE is not set
723# CONFIG_NETPOLL is not set
724# CONFIG_NET_POLL_CONTROLLER is not set
725# CONFIG_ISDN is not set
726# CONFIG_PHONE is not set
727
728#
729# Input device support
730#
731CONFIG_INPUT=y
732# CONFIG_INPUT_FF_MEMLESS is not set
733CONFIG_INPUT_POLLDEV=y
734
735#
736# Userland interfaces
737#
738# CONFIG_INPUT_MOUSEDEV is not set
739# CONFIG_INPUT_JOYDEV is not set
740CONFIG_INPUT_EVDEV=y
741# CONFIG_INPUT_EVBUG is not set
742
743#
744# Input Device Drivers
745#
746CONFIG_INPUT_KEYBOARD=y
747# CONFIG_KEYBOARD_ADP5588 is not set
748# CONFIG_KEYBOARD_ATKBD is not set
749# CONFIG_QT2160 is not set
750# CONFIG_KEYBOARD_LKKBD is not set
751# CONFIG_KEYBOARD_GPIO is not set
752# CONFIG_KEYBOARD_MATRIX is not set
753# CONFIG_KEYBOARD_MAX7359 is not set
754# CONFIG_KEYBOARD_NEWTON is not set
755# CONFIG_KEYBOARD_OPENCORES is not set
756# CONFIG_KEYBOARD_STOWAWAY is not set
757# CONFIG_KEYBOARD_SUNKBD is not set
758# CONFIG_KEYBOARD_XTKBD is not set
759CONFIG_INPUT_MOUSE=y
760# CONFIG_MOUSE_PS2 is not set
761# CONFIG_MOUSE_SERIAL is not set
762# CONFIG_MOUSE_APPLETOUCH is not set
763# CONFIG_MOUSE_BCM5974 is not set
764# CONFIG_MOUSE_VSXXXAA is not set
765# CONFIG_MOUSE_GPIO is not set
766# CONFIG_MOUSE_SYNAPTICS_I2C is not set
767# CONFIG_INPUT_JOYSTICK is not set
768# CONFIG_INPUT_TABLET is not set
769# CONFIG_INPUT_TOUCHSCREEN is not set
770# CONFIG_INPUT_MISC is not set
771
772#
773# Hardware I/O ports
774#
775# CONFIG_SERIO is not set
776# CONFIG_GAMEPORT is not set
777
778#
779# Character devices
780#
781CONFIG_VT=y
782CONFIG_CONSOLE_TRANSLATIONS=y
783CONFIG_VT_CONSOLE=y
784CONFIG_HW_CONSOLE=y
785# CONFIG_VT_HW_CONSOLE_BINDING is not set
786# CONFIG_DEVKMEM is not set
787# CONFIG_SERIAL_NONSTANDARD is not set
788# CONFIG_NOZOMI is not set
789
790#
791# Serial drivers
792#
793CONFIG_SERIAL_8250=y
794CONFIG_SERIAL_8250_CONSOLE=y
795# CONFIG_SERIAL_8250_PCI is not set
796CONFIG_SERIAL_8250_NR_UARTS=4
797CONFIG_SERIAL_8250_RUNTIME_UARTS=2
798# CONFIG_SERIAL_8250_EXTENDED is not set
799
800#
801# Non-8250 serial port support
802#
803# CONFIG_SERIAL_MAX3100 is not set
804CONFIG_SERIAL_CORE=y
805CONFIG_SERIAL_CORE_CONSOLE=y
806# CONFIG_SERIAL_JSM is not set
807CONFIG_UNIX98_PTYS=y
808# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
809CONFIG_LEGACY_PTYS=y
810CONFIG_LEGACY_PTY_COUNT=16
811# CONFIG_IPMI_HANDLER is not set
812# CONFIG_HW_RANDOM is not set
813# CONFIG_R3964 is not set
814# CONFIG_APPLICOM is not set
815# CONFIG_RAW_DRIVER is not set
816# CONFIG_TCG_TPM is not set
817CONFIG_DEVPORT=y
818CONFIG_I2C=y
819CONFIG_I2C_BOARDINFO=y
820CONFIG_I2C_COMPAT=y
821CONFIG_I2C_CHARDEV=y
822CONFIG_I2C_HELPER_AUTO=y
823
824#
825# I2C Hardware Bus support
826#
827
828#
829# PC SMBus host controller drivers
830#
831# CONFIG_I2C_ALI1535 is not set
832# CONFIG_I2C_ALI1563 is not set
833# CONFIG_I2C_ALI15X3 is not set
834# CONFIG_I2C_AMD756 is not set
835# CONFIG_I2C_AMD8111 is not set
836# CONFIG_I2C_I801 is not set
837# CONFIG_I2C_ISCH is not set
838# CONFIG_I2C_PIIX4 is not set
839# CONFIG_I2C_NFORCE2 is not set
840# CONFIG_I2C_SIS5595 is not set
841# CONFIG_I2C_SIS630 is not set
842# CONFIG_I2C_SIS96X is not set
843# CONFIG_I2C_VIA is not set
844# CONFIG_I2C_VIAPRO is not set
845
846#
847# I2C system bus drivers (mostly embedded / system-on-chip)
848#
849# CONFIG_I2C_GPIO is not set
850CONFIG_I2C_MV64XXX=y
851# CONFIG_I2C_OCORES is not set
852# CONFIG_I2C_SIMTEC is not set
853
854#
855# External I2C/SMBus adapter drivers
856#
857# CONFIG_I2C_PARPORT_LIGHT is not set
858# CONFIG_I2C_TAOS_EVM is not set
859# CONFIG_I2C_TINY_USB is not set
860
861#
862# Graphics adapter I2C/DDC channel drivers
863#
864# CONFIG_I2C_VOODOO3 is not set
865
866#
867# Other I2C/SMBus bus drivers
868#
869# CONFIG_I2C_PCA_PLATFORM is not set
870# CONFIG_I2C_STUB is not set
871
872#
873# Miscellaneous I2C Chip support
874#
875# CONFIG_DS1682 is not set
876# CONFIG_SENSORS_TSL2550 is not set
877# CONFIG_I2C_DEBUG_CORE is not set
878# CONFIG_I2C_DEBUG_ALGO is not set
879# CONFIG_I2C_DEBUG_BUS is not set
880# CONFIG_I2C_DEBUG_CHIP is not set
881CONFIG_SPI=y
882# CONFIG_SPI_DEBUG is not set
883CONFIG_SPI_MASTER=y
884
885#
886# SPI Master Controller Drivers
887#
888# CONFIG_SPI_BITBANG is not set
889# CONFIG_SPI_GPIO is not set
890CONFIG_SPI_ORION=y
891
892#
893# SPI Protocol Masters
894#
895# CONFIG_SPI_SPIDEV is not set
896# CONFIG_SPI_TLE62X0 is not set
897
898#
899# PPS support
900#
901# CONFIG_PPS is not set
902CONFIG_ARCH_REQUIRE_GPIOLIB=y
903CONFIG_GPIOLIB=y
904# CONFIG_DEBUG_GPIO is not set
905# CONFIG_GPIO_SYSFS is not set
906
907#
908# Memory mapped GPIO expanders:
909#
910
911#
912# I2C GPIO expanders:
913#
914# CONFIG_GPIO_MAX732X is not set
915# CONFIG_GPIO_PCA953X is not set
916# CONFIG_GPIO_PCF857X is not set
917
918#
919# PCI GPIO expanders:
920#
921# CONFIG_GPIO_BT8XX is not set
922# CONFIG_GPIO_LANGWELL is not set
923
924#
925# SPI GPIO expanders:
926#
927# CONFIG_GPIO_MAX7301 is not set
928# CONFIG_GPIO_MCP23S08 is not set
929# CONFIG_GPIO_MC33880 is not set
930
931#
932# AC97 GPIO expanders:
933#
934# CONFIG_W1 is not set
935# CONFIG_POWER_SUPPLY is not set
936# CONFIG_HWMON is not set
937# CONFIG_THERMAL is not set
938# CONFIG_WATCHDOG is not set
939CONFIG_SSB_POSSIBLE=y
940
941#
942# Sonics Silicon Backplane
943#
944# CONFIG_SSB is not set
945
946#
947# Multifunction device drivers
948#
949# CONFIG_MFD_CORE is not set
950# CONFIG_MFD_SM501 is not set
951# CONFIG_MFD_ASIC3 is not set
952# CONFIG_HTC_EGPIO is not set
953# CONFIG_HTC_PASIC3 is not set
954# CONFIG_TPS65010 is not set
955# CONFIG_TWL4030_CORE is not set
956# CONFIG_MFD_TMIO is not set
957# CONFIG_MFD_TC6393XB is not set
958# CONFIG_PMIC_DA903X is not set
959# CONFIG_MFD_WM8400 is not set
960# CONFIG_MFD_WM831X is not set
961# CONFIG_MFD_WM8350_I2C is not set
962# CONFIG_MFD_PCF50633 is not set
963# CONFIG_MFD_MC13783 is not set
964# CONFIG_AB3100_CORE is not set
965# CONFIG_EZX_PCAP is not set
966# CONFIG_REGULATOR is not set
967# CONFIG_MEDIA_SUPPORT is not set
968
969#
970# Graphics support
971#
972CONFIG_VGA_ARB=y
973# CONFIG_DRM is not set
974# CONFIG_VGASTATE is not set
975# CONFIG_VIDEO_OUTPUT_CONTROL is not set
976# CONFIG_FB is not set
977# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
978
979#
980# Display device support
981#
982# CONFIG_DISPLAY_SUPPORT is not set
983
984#
985# Console display driver support
986#
987# CONFIG_VGA_CONSOLE is not set
988CONFIG_DUMMY_CONSOLE=y
989# CONFIG_SOUND is not set
990CONFIG_HID_SUPPORT=y
991CONFIG_HID=y
992# CONFIG_HIDRAW is not set
993
994#
995# USB Input Devices
996#
997CONFIG_USB_HID=y
998# CONFIG_HID_PID is not set
999# CONFIG_USB_HIDDEV is not set
1000
1001#
1002# Special HID drivers
1003#
1004# CONFIG_HID_A4TECH is not set
1005# CONFIG_HID_APPLE is not set
1006# CONFIG_HID_BELKIN is not set
1007# CONFIG_HID_CHERRY is not set
1008# CONFIG_HID_CHICONY is not set
1009# CONFIG_HID_CYPRESS is not set
1010# CONFIG_HID_DRAGONRISE is not set
1011# CONFIG_HID_EZKEY is not set
1012# CONFIG_HID_KYE is not set
1013# CONFIG_HID_GYRATION is not set
1014# CONFIG_HID_TWINHAN is not set
1015# CONFIG_HID_KENSINGTON is not set
1016# CONFIG_HID_LOGITECH is not set
1017# CONFIG_HID_MICROSOFT is not set
1018# CONFIG_HID_MONTEREY is not set
1019# CONFIG_HID_NTRIG is not set
1020# CONFIG_HID_PANTHERLORD is not set
1021# CONFIG_HID_PETALYNX is not set
1022# CONFIG_HID_SAMSUNG is not set
1023# CONFIG_HID_SONY is not set
1024# CONFIG_HID_SUNPLUS is not set
1025# CONFIG_HID_GREENASIA is not set
1026# CONFIG_HID_SMARTJOYPLUS is not set
1027# CONFIG_HID_TOPSEED is not set
1028# CONFIG_HID_THRUSTMASTER is not set
1029# CONFIG_HID_ZEROPLUS is not set
1030CONFIG_USB_SUPPORT=y
1031CONFIG_USB_ARCH_HAS_HCD=y
1032CONFIG_USB_ARCH_HAS_OHCI=y
1033CONFIG_USB_ARCH_HAS_EHCI=y
1034CONFIG_USB=y
1035# CONFIG_USB_DEBUG is not set
1036# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
1037
1038#
1039# Miscellaneous USB options
1040#
1041CONFIG_USB_DEVICEFS=y
1042CONFIG_USB_DEVICE_CLASS=y
1043# CONFIG_USB_DYNAMIC_MINORS is not set
1044# CONFIG_USB_OTG is not set
1045# CONFIG_USB_OTG_WHITELIST is not set
1046# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1047# CONFIG_USB_MON is not set
1048# CONFIG_USB_WUSB is not set
1049# CONFIG_USB_WUSB_CBAF is not set
1050
1051#
1052# USB Host Controller Drivers
1053#
1054# CONFIG_USB_C67X00_HCD is not set
1055# CONFIG_USB_XHCI_HCD is not set
1056CONFIG_USB_EHCI_HCD=y
1057CONFIG_USB_EHCI_ROOT_HUB_TT=y
1058CONFIG_USB_EHCI_TT_NEWSCHED=y
1059# CONFIG_USB_OXU210HP_HCD is not set
1060# CONFIG_USB_ISP116X_HCD is not set
1061# CONFIG_USB_ISP1760_HCD is not set
1062# CONFIG_USB_ISP1362_HCD is not set
1063# CONFIG_USB_OHCI_HCD is not set
1064# CONFIG_USB_UHCI_HCD is not set
1065# CONFIG_USB_SL811_HCD is not set
1066# CONFIG_USB_R8A66597_HCD is not set
1067# CONFIG_USB_WHCI_HCD is not set
1068# CONFIG_USB_HWA_HCD is not set
1069# CONFIG_USB_MUSB_HDRC is not set
1070
1071#
1072# USB Device Class drivers
1073#
1074# CONFIG_USB_ACM is not set
1075# CONFIG_USB_PRINTER is not set
1076# CONFIG_USB_WDM is not set
1077# CONFIG_USB_TMC is not set
1078
1079#
1080# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
1081#
1082
1083#
1084# also be needed; see USB_STORAGE Help for more info
1085#
1086CONFIG_USB_STORAGE=y
1087# CONFIG_USB_STORAGE_DEBUG is not set
1088# CONFIG_USB_STORAGE_DATAFAB is not set
1089# CONFIG_USB_STORAGE_FREECOM is not set
1090# CONFIG_USB_STORAGE_ISD200 is not set
1091# CONFIG_USB_STORAGE_USBAT is not set
1092# CONFIG_USB_STORAGE_SDDR09 is not set
1093# CONFIG_USB_STORAGE_SDDR55 is not set
1094# CONFIG_USB_STORAGE_JUMPSHOT is not set
1095# CONFIG_USB_STORAGE_ALAUDA is not set
1096# CONFIG_USB_STORAGE_ONETOUCH is not set
1097# CONFIG_USB_STORAGE_KARMA is not set
1098# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1099# CONFIG_USB_LIBUSUAL is not set
1100
1101#
1102# USB Imaging devices
1103#
1104# CONFIG_USB_MDC800 is not set
1105# CONFIG_USB_MICROTEK is not set
1106
1107#
1108# USB port drivers
1109#
1110# CONFIG_USB_SERIAL is not set
1111
1112#
1113# USB Miscellaneous drivers
1114#
1115# CONFIG_USB_EMI62 is not set
1116# CONFIG_USB_EMI26 is not set
1117# CONFIG_USB_ADUTUX is not set
1118# CONFIG_USB_SEVSEG is not set
1119# CONFIG_USB_RIO500 is not set
1120# CONFIG_USB_LEGOTOWER is not set
1121# CONFIG_USB_LCD is not set
1122# CONFIG_USB_BERRY_CHARGE is not set
1123# CONFIG_USB_LED is not set
1124# CONFIG_USB_CYPRESS_CY7C63 is not set
1125# CONFIG_USB_CYTHERM is not set
1126# CONFIG_USB_IDMOUSE is not set
1127# CONFIG_USB_FTDI_ELAN is not set
1128# CONFIG_USB_APPLEDISPLAY is not set
1129# CONFIG_USB_SISUSBVGA is not set
1130# CONFIG_USB_LD is not set
1131# CONFIG_USB_TRANCEVIBRATOR is not set
1132# CONFIG_USB_IOWARRIOR is not set
1133# CONFIG_USB_TEST is not set
1134# CONFIG_USB_ISIGHTFW is not set
1135# CONFIG_USB_VST is not set
1136# CONFIG_USB_GADGET is not set
1137
1138#
1139# OTG and related infrastructure
1140#
1141# CONFIG_USB_GPIO_VBUS is not set
1142# CONFIG_NOP_USB_XCEIV is not set
1143# CONFIG_UWB is not set
1144# CONFIG_MMC is not set
1145# CONFIG_MEMSTICK is not set
1146# CONFIG_NEW_LEDS is not set
1147# CONFIG_ACCESSIBILITY is not set
1148# CONFIG_INFINIBAND is not set
1149CONFIG_RTC_LIB=y
1150CONFIG_RTC_CLASS=y
1151CONFIG_RTC_HCTOSYS=y
1152CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1153# CONFIG_RTC_DEBUG is not set
1154
1155#
1156# RTC interfaces
1157#
1158CONFIG_RTC_INTF_SYSFS=y
1159CONFIG_RTC_INTF_PROC=y
1160CONFIG_RTC_INTF_DEV=y
1161# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1162# CONFIG_RTC_DRV_TEST is not set
1163
1164#
1165# I2C RTC drivers
1166#
1167# CONFIG_RTC_DRV_DS1307 is not set
1168# CONFIG_RTC_DRV_DS1374 is not set
1169# CONFIG_RTC_DRV_DS1672 is not set
1170# CONFIG_RTC_DRV_MAX6900 is not set
1171# CONFIG_RTC_DRV_RS5C372 is not set
1172# CONFIG_RTC_DRV_ISL1208 is not set
1173# CONFIG_RTC_DRV_X1205 is not set
1174# CONFIG_RTC_DRV_PCF8563 is not set
1175# CONFIG_RTC_DRV_PCF8583 is not set
1176# CONFIG_RTC_DRV_M41T80 is not set
1177# CONFIG_RTC_DRV_S35390A is not set
1178# CONFIG_RTC_DRV_FM3130 is not set
1179# CONFIG_RTC_DRV_RX8581 is not set
1180# CONFIG_RTC_DRV_RX8025 is not set
1181
1182#
1183# SPI RTC drivers
1184#
1185# CONFIG_RTC_DRV_M41T94 is not set
1186# CONFIG_RTC_DRV_DS1305 is not set
1187# CONFIG_RTC_DRV_DS1390 is not set
1188# CONFIG_RTC_DRV_MAX6902 is not set
1189# CONFIG_RTC_DRV_R9701 is not set
1190# CONFIG_RTC_DRV_RS5C348 is not set
1191# CONFIG_RTC_DRV_DS3234 is not set
1192# CONFIG_RTC_DRV_PCF2123 is not set
1193
1194#
1195# Platform RTC drivers
1196#
1197# CONFIG_RTC_DRV_CMOS is not set
1198# CONFIG_RTC_DRV_DS1286 is not set
1199# CONFIG_RTC_DRV_DS1511 is not set
1200# CONFIG_RTC_DRV_DS1553 is not set
1201# CONFIG_RTC_DRV_DS1742 is not set
1202# CONFIG_RTC_DRV_STK17TA8 is not set
1203# CONFIG_RTC_DRV_M48T86 is not set
1204# CONFIG_RTC_DRV_M48T35 is not set
1205# CONFIG_RTC_DRV_M48T59 is not set
1206# CONFIG_RTC_DRV_BQ4802 is not set
1207# CONFIG_RTC_DRV_V3020 is not set
1208
1209#
1210# on-CPU RTC drivers
1211#
1212CONFIG_RTC_DRV_MV=y
1213CONFIG_DMADEVICES=y
1214
1215#
1216# DMA Devices
1217#
1218CONFIG_MV_XOR=y
1219CONFIG_DMA_ENGINE=y
1220
1221#
1222# DMA Clients
1223#
1224# CONFIG_NET_DMA is not set
1225# CONFIG_ASYNC_TX_DMA is not set
1226# CONFIG_DMATEST is not set
1227# CONFIG_AUXDISPLAY is not set
1228# CONFIG_UIO is not set
1229
1230#
1231# TI VLYNQ
1232#
1233# CONFIG_STAGING is not set
1234
1235#
1236# File systems
1237#
1238CONFIG_EXT2_FS=y
1239# CONFIG_EXT2_FS_XATTR is not set
1240# CONFIG_EXT2_FS_XIP is not set
1241CONFIG_EXT3_FS=y
1242# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1243# CONFIG_EXT3_FS_XATTR is not set
1244# CONFIG_EXT4_FS is not set
1245CONFIG_JBD=y
1246# CONFIG_JBD_DEBUG is not set
1247# CONFIG_REISERFS_FS is not set
1248# CONFIG_JFS_FS is not set
1249# CONFIG_FS_POSIX_ACL is not set
1250# CONFIG_XFS_FS is not set
1251# CONFIG_GFS2_FS is not set
1252# CONFIG_OCFS2_FS is not set
1253# CONFIG_BTRFS_FS is not set
1254# CONFIG_NILFS2_FS is not set
1255CONFIG_FILE_LOCKING=y
1256CONFIG_FSNOTIFY=y
1257CONFIG_DNOTIFY=y
1258CONFIG_INOTIFY=y
1259CONFIG_INOTIFY_USER=y
1260# CONFIG_QUOTA is not set
1261# CONFIG_AUTOFS_FS is not set
1262# CONFIG_AUTOFS4_FS is not set
1263# CONFIG_FUSE_FS is not set
1264
1265#
1266# Caches
1267#
1268# CONFIG_FSCACHE is not set
1269
1270#
1271# CD-ROM/DVD Filesystems
1272#
1273CONFIG_ISO9660_FS=y
1274CONFIG_JOLIET=y
1275# CONFIG_ZISOFS is not set
1276CONFIG_UDF_FS=m
1277CONFIG_UDF_NLS=y
1278
1279#
1280# DOS/FAT/NT Filesystems
1281#
1282CONFIG_FAT_FS=y
1283CONFIG_MSDOS_FS=y
1284CONFIG_VFAT_FS=y
1285CONFIG_FAT_DEFAULT_CODEPAGE=437
1286CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1287# CONFIG_NTFS_FS is not set
1288
1289#
1290# Pseudo filesystems
1291#
1292CONFIG_PROC_FS=y
1293CONFIG_PROC_SYSCTL=y
1294CONFIG_PROC_PAGE_MONITOR=y
1295CONFIG_SYSFS=y
1296CONFIG_TMPFS=y
1297# CONFIG_TMPFS_POSIX_ACL is not set
1298# CONFIG_HUGETLB_PAGE is not set
1299# CONFIG_CONFIGFS_FS is not set
1300CONFIG_MISC_FILESYSTEMS=y
1301# CONFIG_ADFS_FS is not set
1302# CONFIG_AFFS_FS is not set
1303# CONFIG_HFS_FS is not set
1304# CONFIG_HFSPLUS_FS is not set
1305# CONFIG_BEFS_FS is not set
1306# CONFIG_BFS_FS is not set
1307# CONFIG_EFS_FS is not set
1308CONFIG_JFFS2_FS=y
1309CONFIG_JFFS2_FS_DEBUG=0
1310CONFIG_JFFS2_FS_WRITEBUFFER=y
1311# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1312# CONFIG_JFFS2_SUMMARY is not set
1313# CONFIG_JFFS2_FS_XATTR is not set
1314# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1315CONFIG_JFFS2_ZLIB=y
1316# CONFIG_JFFS2_LZO is not set
1317CONFIG_JFFS2_RTIME=y
1318# CONFIG_JFFS2_RUBIN is not set
1319# CONFIG_UBIFS_FS is not set
1320# CONFIG_CRAMFS is not set
1321# CONFIG_SQUASHFS is not set
1322# CONFIG_VXFS_FS is not set
1323# CONFIG_MINIX_FS is not set
1324# CONFIG_OMFS_FS is not set
1325# CONFIG_HPFS_FS is not set
1326# CONFIG_QNX4FS_FS is not set
1327# CONFIG_ROMFS_FS is not set
1328# CONFIG_SYSV_FS is not set
1329# CONFIG_UFS_FS is not set
1330CONFIG_NETWORK_FILESYSTEMS=y
1331CONFIG_NFS_FS=y
1332CONFIG_NFS_V3=y
1333# CONFIG_NFS_V3_ACL is not set
1334# CONFIG_NFS_V4 is not set
1335CONFIG_ROOT_NFS=y
1336# CONFIG_NFSD is not set
1337CONFIG_LOCKD=y
1338CONFIG_LOCKD_V4=y
1339CONFIG_NFS_COMMON=y
1340CONFIG_SUNRPC=y
1341# CONFIG_RPCSEC_GSS_KRB5 is not set
1342# CONFIG_RPCSEC_GSS_SPKM3 is not set
1343# CONFIG_SMB_FS is not set
1344# CONFIG_CIFS is not set
1345# CONFIG_NCP_FS is not set
1346# CONFIG_CODA_FS is not set
1347# CONFIG_AFS_FS is not set
1348
1349#
1350# Partition Types
1351#
1352CONFIG_PARTITION_ADVANCED=y
1353# CONFIG_ACORN_PARTITION is not set
1354# CONFIG_OSF_PARTITION is not set
1355# CONFIG_AMIGA_PARTITION is not set
1356# CONFIG_ATARI_PARTITION is not set
1357# CONFIG_MAC_PARTITION is not set
1358CONFIG_MSDOS_PARTITION=y
1359# CONFIG_BSD_DISKLABEL is not set
1360# CONFIG_MINIX_SUBPARTITION is not set
1361# CONFIG_SOLARIS_X86_PARTITION is not set
1362# CONFIG_UNIXWARE_DISKLABEL is not set
1363# CONFIG_LDM_PARTITION is not set
1364# CONFIG_SGI_PARTITION is not set
1365# CONFIG_ULTRIX_PARTITION is not set
1366# CONFIG_SUN_PARTITION is not set
1367# CONFIG_KARMA_PARTITION is not set
1368# CONFIG_EFI_PARTITION is not set
1369# CONFIG_SYSV68_PARTITION is not set
1370CONFIG_NLS=y
1371CONFIG_NLS_DEFAULT="iso8859-1"
1372CONFIG_NLS_CODEPAGE_437=y
1373# CONFIG_NLS_CODEPAGE_737 is not set
1374# CONFIG_NLS_CODEPAGE_775 is not set
1375CONFIG_NLS_CODEPAGE_850=y
1376# CONFIG_NLS_CODEPAGE_852 is not set
1377# CONFIG_NLS_CODEPAGE_855 is not set
1378# CONFIG_NLS_CODEPAGE_857 is not set
1379# CONFIG_NLS_CODEPAGE_860 is not set
1380# CONFIG_NLS_CODEPAGE_861 is not set
1381# CONFIG_NLS_CODEPAGE_862 is not set
1382# CONFIG_NLS_CODEPAGE_863 is not set
1383# CONFIG_NLS_CODEPAGE_864 is not set
1384# CONFIG_NLS_CODEPAGE_865 is not set
1385# CONFIG_NLS_CODEPAGE_866 is not set
1386# CONFIG_NLS_CODEPAGE_869 is not set
1387# CONFIG_NLS_CODEPAGE_936 is not set
1388# CONFIG_NLS_CODEPAGE_950 is not set
1389# CONFIG_NLS_CODEPAGE_932 is not set
1390# CONFIG_NLS_CODEPAGE_949 is not set
1391# CONFIG_NLS_CODEPAGE_874 is not set
1392# CONFIG_NLS_ISO8859_8 is not set
1393# CONFIG_NLS_CODEPAGE_1250 is not set
1394# CONFIG_NLS_CODEPAGE_1251 is not set
1395# CONFIG_NLS_ASCII is not set
1396CONFIG_NLS_ISO8859_1=y
1397CONFIG_NLS_ISO8859_2=y
1398# CONFIG_NLS_ISO8859_3 is not set
1399# CONFIG_NLS_ISO8859_4 is not set
1400# CONFIG_NLS_ISO8859_5 is not set
1401# CONFIG_NLS_ISO8859_6 is not set
1402# CONFIG_NLS_ISO8859_7 is not set
1403# CONFIG_NLS_ISO8859_9 is not set
1404# CONFIG_NLS_ISO8859_13 is not set
1405# CONFIG_NLS_ISO8859_14 is not set
1406# CONFIG_NLS_ISO8859_15 is not set
1407# CONFIG_NLS_KOI8_R is not set
1408# CONFIG_NLS_KOI8_U is not set
1409CONFIG_NLS_UTF8=y
1410# CONFIG_DLM is not set
1411
1412#
1413# Kernel hacking
1414#
1415# CONFIG_PRINTK_TIME is not set
1416CONFIG_ENABLE_WARN_DEPRECATED=y
1417CONFIG_ENABLE_MUST_CHECK=y
1418CONFIG_FRAME_WARN=1024
1419CONFIG_MAGIC_SYSRQ=y
1420# CONFIG_STRIP_ASM_SYMS is not set
1421# CONFIG_UNUSED_SYMBOLS is not set
1422CONFIG_DEBUG_FS=y
1423# CONFIG_HEADERS_CHECK is not set
1424CONFIG_DEBUG_KERNEL=y
1425# CONFIG_DEBUG_SHIRQ is not set
1426CONFIG_DETECT_SOFTLOCKUP=y
1427# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1428CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1429CONFIG_DETECT_HUNG_TASK=y
1430# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
1431CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1432# CONFIG_SCHED_DEBUG is not set
1433# CONFIG_SCHEDSTATS is not set
1434CONFIG_TIMER_STATS=y
1435# CONFIG_DEBUG_OBJECTS is not set
1436# CONFIG_DEBUG_SLAB is not set
1437# CONFIG_DEBUG_KMEMLEAK is not set
1438# CONFIG_DEBUG_RT_MUTEXES is not set
1439# CONFIG_RT_MUTEX_TESTER is not set
1440# CONFIG_DEBUG_SPINLOCK is not set
1441# CONFIG_DEBUG_MUTEXES is not set
1442# CONFIG_DEBUG_LOCK_ALLOC is not set
1443# CONFIG_PROVE_LOCKING is not set
1444# CONFIG_LOCK_STAT is not set
1445# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1446# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1447# CONFIG_DEBUG_KOBJECT is not set
1448# CONFIG_DEBUG_BUGVERBOSE is not set
1449CONFIG_DEBUG_INFO=y
1450# CONFIG_DEBUG_VM is not set
1451# CONFIG_DEBUG_WRITECOUNT is not set
1452# CONFIG_DEBUG_MEMORY_INIT is not set
1453# CONFIG_DEBUG_LIST is not set
1454# CONFIG_DEBUG_SG is not set
1455# CONFIG_DEBUG_NOTIFIERS is not set
1456# CONFIG_DEBUG_CREDENTIALS is not set
1457# CONFIG_BOOT_PRINTK_DELAY is not set
1458# CONFIG_RCU_TORTURE_TEST is not set
1459# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1460# CONFIG_BACKTRACE_SELF_TEST is not set
1461# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1462# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
1463# CONFIG_FAULT_INJECTION is not set
1464# CONFIG_LATENCYTOP is not set
1465CONFIG_SYSCTL_SYSCALL_CHECK=y
1466# CONFIG_PAGE_POISONING is not set
1467CONFIG_HAVE_FUNCTION_TRACER=y
1468CONFIG_TRACING_SUPPORT=y
1469CONFIG_FTRACE=y
1470# CONFIG_FUNCTION_TRACER is not set
1471# CONFIG_IRQSOFF_TRACER is not set
1472# CONFIG_SCHED_TRACER is not set
1473# CONFIG_ENABLE_DEFAULT_TRACERS is not set
1474# CONFIG_BOOT_TRACER is not set
1475CONFIG_BRANCH_PROFILE_NONE=y
1476# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
1477# CONFIG_PROFILE_ALL_BRANCHES is not set
1478# CONFIG_STACK_TRACER is not set
1479# CONFIG_KMEMTRACE is not set
1480# CONFIG_WORKQUEUE_TRACER is not set
1481# CONFIG_BLK_DEV_IO_TRACE is not set
1482# CONFIG_DYNAMIC_DEBUG is not set
1483# CONFIG_SAMPLES is not set
1484CONFIG_HAVE_ARCH_KGDB=y
1485# CONFIG_KGDB is not set
1486CONFIG_ARM_UNWIND=y
1487CONFIG_DEBUG_USER=y
1488CONFIG_DEBUG_ERRORS=y
1489# CONFIG_DEBUG_STACK_USAGE is not set
1490# CONFIG_DEBUG_LL is not set
1491
1492#
1493# Security options
1494#
1495# CONFIG_KEYS is not set
1496# CONFIG_SECURITY is not set
1497# CONFIG_SECURITYFS is not set
1498# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1499CONFIG_CRYPTO=y
1500
1501#
1502# Crypto core or helper
1503#
1504CONFIG_CRYPTO_ALGAPI=y
1505CONFIG_CRYPTO_ALGAPI2=y
1506CONFIG_CRYPTO_AEAD2=y
1507CONFIG_CRYPTO_BLKCIPHER=y
1508CONFIG_CRYPTO_BLKCIPHER2=y
1509CONFIG_CRYPTO_HASH=y
1510CONFIG_CRYPTO_HASH2=y
1511CONFIG_CRYPTO_RNG2=y
1512CONFIG_CRYPTO_PCOMP=y
1513CONFIG_CRYPTO_MANAGER=y
1514CONFIG_CRYPTO_MANAGER2=y
1515# CONFIG_CRYPTO_GF128MUL is not set
1516CONFIG_CRYPTO_NULL=y
1517CONFIG_CRYPTO_WORKQUEUE=y
1518# CONFIG_CRYPTO_CRYPTD is not set
1519# CONFIG_CRYPTO_AUTHENC is not set
1520# CONFIG_CRYPTO_TEST is not set
1521
1522#
1523# Authenticated Encryption with Associated Data
1524#
1525# CONFIG_CRYPTO_CCM is not set
1526# CONFIG_CRYPTO_GCM is not set
1527# CONFIG_CRYPTO_SEQIV is not set
1528
1529#
1530# Block modes
1531#
1532CONFIG_CRYPTO_CBC=y
1533# CONFIG_CRYPTO_CTR is not set
1534# CONFIG_CRYPTO_CTS is not set
1535CONFIG_CRYPTO_ECB=m
1536# CONFIG_CRYPTO_LRW is not set
1537CONFIG_CRYPTO_PCBC=m
1538# CONFIG_CRYPTO_XTS is not set
1539
1540#
1541# Hash modes
1542#
1543CONFIG_CRYPTO_HMAC=y
1544# CONFIG_CRYPTO_XCBC is not set
1545# CONFIG_CRYPTO_VMAC is not set
1546
1547#
1548# Digest
1549#
1550CONFIG_CRYPTO_CRC32C=y
1551# CONFIG_CRYPTO_GHASH is not set
1552CONFIG_CRYPTO_MD4=y
1553CONFIG_CRYPTO_MD5=y
1554# CONFIG_CRYPTO_MICHAEL_MIC is not set
1555# CONFIG_CRYPTO_RMD128 is not set
1556# CONFIG_CRYPTO_RMD160 is not set
1557# CONFIG_CRYPTO_RMD256 is not set
1558# CONFIG_CRYPTO_RMD320 is not set
1559CONFIG_CRYPTO_SHA1=y
1560CONFIG_CRYPTO_SHA256=y
1561CONFIG_CRYPTO_SHA512=y
1562# CONFIG_CRYPTO_TGR192 is not set
1563# CONFIG_CRYPTO_WP512 is not set
1564
1565#
1566# Ciphers
1567#
1568CONFIG_CRYPTO_AES=y
1569# CONFIG_CRYPTO_ANUBIS is not set
1570# CONFIG_CRYPTO_ARC4 is not set
1571CONFIG_CRYPTO_BLOWFISH=y
1572# CONFIG_CRYPTO_CAMELLIA is not set
1573# CONFIG_CRYPTO_CAST5 is not set
1574# CONFIG_CRYPTO_CAST6 is not set
1575CONFIG_CRYPTO_DES=y
1576# CONFIG_CRYPTO_FCRYPT is not set
1577# CONFIG_CRYPTO_KHAZAD is not set
1578# CONFIG_CRYPTO_SALSA20 is not set
1579# CONFIG_CRYPTO_SEED is not set
1580# CONFIG_CRYPTO_SERPENT is not set
1581CONFIG_CRYPTO_TEA=y
1582CONFIG_CRYPTO_TWOFISH=y
1583CONFIG_CRYPTO_TWOFISH_COMMON=y
1584
1585#
1586# Compression
1587#
1588CONFIG_CRYPTO_DEFLATE=y
1589# CONFIG_CRYPTO_ZLIB is not set
1590CONFIG_CRYPTO_LZO=y
1591
1592#
1593# Random Number Generation
1594#
1595# CONFIG_CRYPTO_ANSI_CPRNG is not set
1596CONFIG_CRYPTO_HW=y
1597# CONFIG_CRYPTO_DEV_MV_CESA is not set
1598# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1599# CONFIG_BINARY_PRINTF is not set
1600
1601#
1602# Library routines
1603#
1604CONFIG_BITREVERSE=y
1605CONFIG_GENERIC_FIND_LAST_BIT=y
1606CONFIG_CRC_CCITT=y
1607CONFIG_CRC16=y
1608# CONFIG_CRC_T10DIF is not set
1609CONFIG_CRC_ITU_T=m
1610CONFIG_CRC32=y
1611# CONFIG_CRC7 is not set
1612CONFIG_LIBCRC32C=y
1613CONFIG_ZLIB_INFLATE=y
1614CONFIG_ZLIB_DEFLATE=y
1615CONFIG_LZO_COMPRESS=y
1616CONFIG_LZO_DECOMPRESS=y
1617CONFIG_HAS_IOMEM=y
1618CONFIG_HAS_IOPORT=y
1619CONFIG_HAS_DMA=y
1620CONFIG_NLATTR=y
diff --git a/arch/arm/include/asm/hardware/cache-tauros2.h b/arch/arm/include/asm/hardware/cache-tauros2.h
new file mode 100644
index 000000000000..538f17ca905b
--- /dev/null
+++ b/arch/arm/include/asm/hardware/cache-tauros2.h
@@ -0,0 +1,11 @@
1/*
2 * arch/arm/include/asm/hardware/cache-tauros2.h
3 *
4 * Copyright (C) 2008 Marvell Semiconductor
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11extern void __init tauros2_init(void);
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
new file mode 100644
index 000000000000..3b9a32ace909
--- /dev/null
+++ b/arch/arm/mach-dove/Kconfig
@@ -0,0 +1,14 @@
1if ARCH_DOVE
2
3menu "Marvell Dove Implementations"
4
5config MACH_DOVE_DB
6 bool "Marvell DB-MV88AP510 Development Board"
7 select I2C_BOARDINFO
8 help
9 Say 'Y' here if you want your kernel to support the
10 Marvell DB-MV88AP510 Development Board.
11
12endmenu
13
14endif
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
new file mode 100644
index 000000000000..7ab3be53f642
--- /dev/null
+++ b/arch/arm/mach-dove/Makefile
@@ -0,0 +1,3 @@
1obj-y += common.o addr-map.o irq.o pcie.o
2
3obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o
diff --git a/arch/arm/mach-dove/Makefile.boot b/arch/arm/mach-dove/Makefile.boot
new file mode 100644
index 000000000000..67039c3e0c48
--- /dev/null
+++ b/arch/arm/mach-dove/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c
new file mode 100644
index 000000000000..00be4fc26dd7
--- /dev/null
+++ b/arch/arm/mach-dove/addr-map.c
@@ -0,0 +1,149 @@
1/*
2 * arch/arm/mach-dove/addr-map.c
3 *
4 * Address map functions for Marvell Dove 88AP510 SoC
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/mbus.h>
14#include <linux/io.h>
15#include <asm/mach/arch.h>
16#include <asm/setup.h>
17#include "common.h"
18
19/*
20 * Generic Address Decode Windows bit settings
21 */
22#define TARGET_DDR 0x0
23#define TARGET_BOOTROM 0x1
24#define TARGET_CESA 0x3
25#define TARGET_PCIE0 0x4
26#define TARGET_PCIE1 0x8
27#define TARGET_SCRATCHPAD 0xd
28
29#define ATTR_CESA 0x01
30#define ATTR_BOOTROM 0xfd
31#define ATTR_DEV_SPI0_ROM 0xfe
32#define ATTR_DEV_SPI1_ROM 0xfb
33#define ATTR_PCIE_IO 0xe0
34#define ATTR_PCIE_MEM 0xe8
35#define ATTR_SCRATCHPAD 0x0
36
37/*
38 * CPU Address Decode Windows registers
39 */
40#define WIN_CTRL(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x0)
41#define WIN_BASE(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x4)
42#define WIN_REMAP_LO(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x8)
43#define WIN_REMAP_HI(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0xc)
44
45struct mbus_dram_target_info dove_mbus_dram_info;
46
47static inline void __iomem *ddr_map_sc(int i)
48{
49 return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4));
50}
51
52static int cpu_win_can_remap(int win)
53{
54 if (win < 4)
55 return 1;
56
57 return 0;
58}
59
60static void __init setup_cpu_win(int win, u32 base, u32 size,
61 u8 target, u8 attr, int remap)
62{
63 u32 ctrl;
64
65 base &= 0xffff0000;
66 ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
67
68 writel(base, WIN_BASE(win));
69 writel(ctrl, WIN_CTRL(win));
70 if (cpu_win_can_remap(win)) {
71 if (remap < 0)
72 remap = base;
73 writel(remap & 0xffff0000, WIN_REMAP_LO(win));
74 writel(0, WIN_REMAP_HI(win));
75 }
76}
77
78void __init dove_setup_cpu_mbus(void)
79{
80 int i;
81 int cs;
82
83 /*
84 * First, disable and clear windows.
85 */
86 for (i = 0; i < 8; i++) {
87 writel(0, WIN_BASE(i));
88 writel(0, WIN_CTRL(i));
89 if (cpu_win_can_remap(i)) {
90 writel(0, WIN_REMAP_LO(i));
91 writel(0, WIN_REMAP_HI(i));
92 }
93 }
94
95 /*
96 * Setup windows for PCIe IO+MEM space.
97 */
98 setup_cpu_win(0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE,
99 TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE);
100 setup_cpu_win(1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE,
101 TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE);
102 setup_cpu_win(2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE,
103 TARGET_PCIE0, ATTR_PCIE_MEM, -1);
104 setup_cpu_win(3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE,
105 TARGET_PCIE1, ATTR_PCIE_MEM, -1);
106
107 /*
108 * Setup window for CESA engine.
109 */
110 setup_cpu_win(4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE,
111 TARGET_CESA, ATTR_CESA, -1);
112
113 /*
114 * Setup the Window to the BootROM for Standby and Sleep Resume
115 */
116 setup_cpu_win(5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE,
117 TARGET_BOOTROM, ATTR_BOOTROM, -1);
118
119 /*
120 * Setup the Window to the PMU Scratch Pad space
121 */
122 setup_cpu_win(6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE,
123 TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1);
124
125 /*
126 * Setup MBUS dram target info.
127 */
128 dove_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
129
130 for (i = 0, cs = 0; i < 2; i++) {
131 u32 map = readl(ddr_map_sc(i));
132
133 /*
134 * Chip select enabled?
135 */
136 if (map & 1) {
137 struct mbus_dram_window *w;
138
139 w = &dove_mbus_dram_info.cs[cs++];
140 w->cs_index = i;
141 w->mbus_attr = 0; /* CS address decoding done inside */
142 /* the DDR controller, no need to */
143 /* provide attributes */
144 w->base = map & 0xff800000;
145 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
146 }
147 }
148 dove_mbus_dram_info.num_cs = cs;
149}
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
new file mode 100644
index 000000000000..806972a68c87
--- /dev/null
+++ b/arch/arm/mach-dove/common.c
@@ -0,0 +1,781 @@
1/*
2 * arch/arm/mach-dove/common.c
3 *
4 * Core functions for Marvell Dove 88AP510 System On Chip
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/delay.h>
13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/pci.h>
16#include <linux/serial_8250.h>
17#include <linux/clk.h>
18#include <linux/mbus.h>
19#include <linux/mv643xx_eth.h>
20#include <linux/mv643xx_i2c.h>
21#include <linux/ata_platform.h>
22#include <linux/spi/orion_spi.h>
23#include <linux/gpio.h>
24#include <asm/page.h>
25#include <asm/setup.h>
26#include <asm/timex.h>
27#include <asm/hardware/cache-tauros2.h>
28#include <asm/mach/map.h>
29#include <asm/mach/time.h>
30#include <asm/mach/pci.h>
31#include <mach/dove.h>
32#include <mach/bridge-regs.h>
33#include <asm/mach/arch.h>
34#include <linux/irq.h>
35#include <plat/mv_xor.h>
36#include <plat/ehci-orion.h>
37#include <plat/time.h>
38#include "common.h"
39
40/*****************************************************************************
41 * I/O Address Mapping
42 ****************************************************************************/
43static struct map_desc dove_io_desc[] __initdata = {
44 {
45 .virtual = DOVE_SB_REGS_VIRT_BASE,
46 .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
47 .length = DOVE_SB_REGS_SIZE,
48 .type = MT_DEVICE,
49 }, {
50 .virtual = DOVE_NB_REGS_VIRT_BASE,
51 .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
52 .length = DOVE_NB_REGS_SIZE,
53 .type = MT_DEVICE,
54 }, {
55 .virtual = DOVE_PCIE0_IO_VIRT_BASE,
56 .pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
57 .length = DOVE_PCIE0_IO_SIZE,
58 .type = MT_DEVICE,
59 }, {
60 .virtual = DOVE_PCIE1_IO_VIRT_BASE,
61 .pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
62 .length = DOVE_PCIE1_IO_SIZE,
63 .type = MT_DEVICE,
64 },
65};
66
67void __init dove_map_io(void)
68{
69 iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
70}
71
72/*****************************************************************************
73 * EHCI
74 ****************************************************************************/
75static struct orion_ehci_data dove_ehci_data = {
76 .dram = &dove_mbus_dram_info,
77 .phy_version = EHCI_PHY_NA,
78};
79
80static u64 ehci_dmamask = DMA_BIT_MASK(32);
81
82/*****************************************************************************
83 * EHCI0
84 ****************************************************************************/
85static struct resource dove_ehci0_resources[] = {
86 {
87 .start = DOVE_USB0_PHYS_BASE,
88 .end = DOVE_USB0_PHYS_BASE + SZ_4K - 1,
89 .flags = IORESOURCE_MEM,
90 }, {
91 .start = IRQ_DOVE_USB0,
92 .end = IRQ_DOVE_USB0,
93 .flags = IORESOURCE_IRQ,
94 },
95};
96
97static struct platform_device dove_ehci0 = {
98 .name = "orion-ehci",
99 .id = 0,
100 .dev = {
101 .dma_mask = &ehci_dmamask,
102 .coherent_dma_mask = DMA_BIT_MASK(32),
103 .platform_data = &dove_ehci_data,
104 },
105 .resource = dove_ehci0_resources,
106 .num_resources = ARRAY_SIZE(dove_ehci0_resources),
107};
108
109void __init dove_ehci0_init(void)
110{
111 platform_device_register(&dove_ehci0);
112}
113
114/*****************************************************************************
115 * EHCI1
116 ****************************************************************************/
117static struct resource dove_ehci1_resources[] = {
118 {
119 .start = DOVE_USB1_PHYS_BASE,
120 .end = DOVE_USB1_PHYS_BASE + SZ_4K - 1,
121 .flags = IORESOURCE_MEM,
122 }, {
123 .start = IRQ_DOVE_USB1,
124 .end = IRQ_DOVE_USB1,
125 .flags = IORESOURCE_IRQ,
126 },
127};
128
129static struct platform_device dove_ehci1 = {
130 .name = "orion-ehci",
131 .id = 1,
132 .dev = {
133 .dma_mask = &ehci_dmamask,
134 .coherent_dma_mask = DMA_BIT_MASK(32),
135 .platform_data = &dove_ehci_data,
136 },
137 .resource = dove_ehci1_resources,
138 .num_resources = ARRAY_SIZE(dove_ehci1_resources),
139};
140
141void __init dove_ehci1_init(void)
142{
143 platform_device_register(&dove_ehci1);
144}
145
146/*****************************************************************************
147 * GE00
148 ****************************************************************************/
149struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = {
150 .t_clk = 0,
151 .dram = &dove_mbus_dram_info,
152};
153
154static struct resource dove_ge00_shared_resources[] = {
155 {
156 .name = "ge00 base",
157 .start = DOVE_GE00_PHYS_BASE + 0x2000,
158 .end = DOVE_GE00_PHYS_BASE + SZ_16K - 1,
159 .flags = IORESOURCE_MEM,
160 },
161};
162
163static struct platform_device dove_ge00_shared = {
164 .name = MV643XX_ETH_SHARED_NAME,
165 .id = 0,
166 .dev = {
167 .platform_data = &dove_ge00_shared_data,
168 },
169 .num_resources = 1,
170 .resource = dove_ge00_shared_resources,
171};
172
173static struct resource dove_ge00_resources[] = {
174 {
175 .name = "ge00 irq",
176 .start = IRQ_DOVE_GE00_SUM,
177 .end = IRQ_DOVE_GE00_SUM,
178 .flags = IORESOURCE_IRQ,
179 },
180};
181
182static struct platform_device dove_ge00 = {
183 .name = MV643XX_ETH_NAME,
184 .id = 0,
185 .num_resources = 1,
186 .resource = dove_ge00_resources,
187 .dev = {
188 .coherent_dma_mask = 0xffffffff,
189 },
190};
191
192void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
193{
194 eth_data->shared = &dove_ge00_shared;
195 dove_ge00.dev.platform_data = eth_data;
196
197 platform_device_register(&dove_ge00_shared);
198 platform_device_register(&dove_ge00);
199}
200
201/*****************************************************************************
202 * SoC RTC
203 ****************************************************************************/
204static struct resource dove_rtc_resource[] = {
205 {
206 .start = DOVE_RTC_PHYS_BASE,
207 .end = DOVE_RTC_PHYS_BASE + 32 - 1,
208 .flags = IORESOURCE_MEM,
209 }, {
210 .start = IRQ_DOVE_RTC,
211 .flags = IORESOURCE_IRQ,
212 }
213};
214
215void __init dove_rtc_init(void)
216{
217 platform_device_register_simple("rtc-mv", -1, dove_rtc_resource, 2);
218}
219
220/*****************************************************************************
221 * SATA
222 ****************************************************************************/
223static struct resource dove_sata_resources[] = {
224 {
225 .name = "sata base",
226 .start = DOVE_SATA_PHYS_BASE,
227 .end = DOVE_SATA_PHYS_BASE + 0x5000 - 1,
228 .flags = IORESOURCE_MEM,
229 }, {
230 .name = "sata irq",
231 .start = IRQ_DOVE_SATA,
232 .end = IRQ_DOVE_SATA,
233 .flags = IORESOURCE_IRQ,
234 },
235};
236
237static struct platform_device dove_sata = {
238 .name = "sata_mv",
239 .id = 0,
240 .dev = {
241 .coherent_dma_mask = DMA_BIT_MASK(32),
242 },
243 .num_resources = ARRAY_SIZE(dove_sata_resources),
244 .resource = dove_sata_resources,
245};
246
247void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
248{
249 sata_data->dram = &dove_mbus_dram_info;
250 dove_sata.dev.platform_data = sata_data;
251 platform_device_register(&dove_sata);
252}
253
254/*****************************************************************************
255 * UART0
256 ****************************************************************************/
257static struct plat_serial8250_port dove_uart0_data[] = {
258 {
259 .mapbase = DOVE_UART0_PHYS_BASE,
260 .membase = (char *)DOVE_UART0_VIRT_BASE,
261 .irq = IRQ_DOVE_UART_0,
262 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
263 .iotype = UPIO_MEM,
264 .regshift = 2,
265 .uartclk = 0,
266 }, {
267 },
268};
269
270static struct resource dove_uart0_resources[] = {
271 {
272 .start = DOVE_UART0_PHYS_BASE,
273 .end = DOVE_UART0_PHYS_BASE + SZ_256 - 1,
274 .flags = IORESOURCE_MEM,
275 }, {
276 .start = IRQ_DOVE_UART_0,
277 .end = IRQ_DOVE_UART_0,
278 .flags = IORESOURCE_IRQ,
279 },
280};
281
282static struct platform_device dove_uart0 = {
283 .name = "serial8250",
284 .id = 0,
285 .dev = {
286 .platform_data = dove_uart0_data,
287 },
288 .resource = dove_uart0_resources,
289 .num_resources = ARRAY_SIZE(dove_uart0_resources),
290};
291
292void __init dove_uart0_init(void)
293{
294 platform_device_register(&dove_uart0);
295}
296
297/*****************************************************************************
298 * UART1
299 ****************************************************************************/
300static struct plat_serial8250_port dove_uart1_data[] = {
301 {
302 .mapbase = DOVE_UART1_PHYS_BASE,
303 .membase = (char *)DOVE_UART1_VIRT_BASE,
304 .irq = IRQ_DOVE_UART_1,
305 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
306 .iotype = UPIO_MEM,
307 .regshift = 2,
308 .uartclk = 0,
309 }, {
310 },
311};
312
313static struct resource dove_uart1_resources[] = {
314 {
315 .start = DOVE_UART1_PHYS_BASE,
316 .end = DOVE_UART1_PHYS_BASE + SZ_256 - 1,
317 .flags = IORESOURCE_MEM,
318 }, {
319 .start = IRQ_DOVE_UART_1,
320 .end = IRQ_DOVE_UART_1,
321 .flags = IORESOURCE_IRQ,
322 },
323};
324
325static struct platform_device dove_uart1 = {
326 .name = "serial8250",
327 .id = 1,
328 .dev = {
329 .platform_data = dove_uart1_data,
330 },
331 .resource = dove_uart1_resources,
332 .num_resources = ARRAY_SIZE(dove_uart1_resources),
333};
334
335void __init dove_uart1_init(void)
336{
337 platform_device_register(&dove_uart1);
338}
339
340/*****************************************************************************
341 * UART2
342 ****************************************************************************/
343static struct plat_serial8250_port dove_uart2_data[] = {
344 {
345 .mapbase = DOVE_UART2_PHYS_BASE,
346 .membase = (char *)DOVE_UART2_VIRT_BASE,
347 .irq = IRQ_DOVE_UART_2,
348 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
349 .iotype = UPIO_MEM,
350 .regshift = 2,
351 .uartclk = 0,
352 }, {
353 },
354};
355
356static struct resource dove_uart2_resources[] = {
357 {
358 .start = DOVE_UART2_PHYS_BASE,
359 .end = DOVE_UART2_PHYS_BASE + SZ_256 - 1,
360 .flags = IORESOURCE_MEM,
361 }, {
362 .start = IRQ_DOVE_UART_2,
363 .end = IRQ_DOVE_UART_2,
364 .flags = IORESOURCE_IRQ,
365 },
366};
367
368static struct platform_device dove_uart2 = {
369 .name = "serial8250",
370 .id = 2,
371 .dev = {
372 .platform_data = dove_uart2_data,
373 },
374 .resource = dove_uart2_resources,
375 .num_resources = ARRAY_SIZE(dove_uart2_resources),
376};
377
378void __init dove_uart2_init(void)
379{
380 platform_device_register(&dove_uart2);
381}
382
383/*****************************************************************************
384 * UART3
385 ****************************************************************************/
386static struct plat_serial8250_port dove_uart3_data[] = {
387 {
388 .mapbase = DOVE_UART3_PHYS_BASE,
389 .membase = (char *)DOVE_UART3_VIRT_BASE,
390 .irq = IRQ_DOVE_UART_3,
391 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
392 .iotype = UPIO_MEM,
393 .regshift = 2,
394 .uartclk = 0,
395 }, {
396 },
397};
398
399static struct resource dove_uart3_resources[] = {
400 {
401 .start = DOVE_UART3_PHYS_BASE,
402 .end = DOVE_UART3_PHYS_BASE + SZ_256 - 1,
403 .flags = IORESOURCE_MEM,
404 }, {
405 .start = IRQ_DOVE_UART_3,
406 .end = IRQ_DOVE_UART_3,
407 .flags = IORESOURCE_IRQ,
408 },
409};
410
411static struct platform_device dove_uart3 = {
412 .name = "serial8250",
413 .id = 3,
414 .dev = {
415 .platform_data = dove_uart3_data,
416 },
417 .resource = dove_uart3_resources,
418 .num_resources = ARRAY_SIZE(dove_uart3_resources),
419};
420
421void __init dove_uart3_init(void)
422{
423 platform_device_register(&dove_uart3);
424}
425
426/*****************************************************************************
427 * SPI0
428 ****************************************************************************/
429static struct orion_spi_info dove_spi0_data = {
430 .tclk = 0,
431};
432
433static struct resource dove_spi0_resources[] = {
434 {
435 .start = DOVE_SPI0_PHYS_BASE,
436 .end = DOVE_SPI0_PHYS_BASE + SZ_512 - 1,
437 .flags = IORESOURCE_MEM,
438 }, {
439 .start = IRQ_DOVE_SPI0,
440 .end = IRQ_DOVE_SPI0,
441 .flags = IORESOURCE_IRQ,
442 },
443};
444
445static struct platform_device dove_spi0 = {
446 .name = "orion_spi",
447 .id = 0,
448 .resource = dove_spi0_resources,
449 .dev = {
450 .platform_data = &dove_spi0_data,
451 },
452 .num_resources = ARRAY_SIZE(dove_spi0_resources),
453};
454
455void __init dove_spi0_init(void)
456{
457 platform_device_register(&dove_spi0);
458}
459
460/*****************************************************************************
461 * SPI1
462 ****************************************************************************/
463static struct orion_spi_info dove_spi1_data = {
464 .tclk = 0,
465};
466
467static struct resource dove_spi1_resources[] = {
468 {
469 .start = DOVE_SPI1_PHYS_BASE,
470 .end = DOVE_SPI1_PHYS_BASE + SZ_512 - 1,
471 .flags = IORESOURCE_MEM,
472 }, {
473 .start = IRQ_DOVE_SPI1,
474 .end = IRQ_DOVE_SPI1,
475 .flags = IORESOURCE_IRQ,
476 },
477};
478
479static struct platform_device dove_spi1 = {
480 .name = "orion_spi",
481 .id = 1,
482 .resource = dove_spi1_resources,
483 .dev = {
484 .platform_data = &dove_spi1_data,
485 },
486 .num_resources = ARRAY_SIZE(dove_spi1_resources),
487};
488
489void __init dove_spi1_init(void)
490{
491 platform_device_register(&dove_spi1);
492}
493
494/*****************************************************************************
495 * I2C
496 ****************************************************************************/
497static struct mv64xxx_i2c_pdata dove_i2c_data = {
498 .freq_m = 10, /* assumes 166 MHz TCLK gets 94.3kHz */
499 .freq_n = 3,
500 .timeout = 1000, /* Default timeout of 1 second */
501};
502
503static struct resource dove_i2c_resources[] = {
504 {
505 .name = "i2c base",
506 .start = DOVE_I2C_PHYS_BASE,
507 .end = DOVE_I2C_PHYS_BASE + 0x20 - 1,
508 .flags = IORESOURCE_MEM,
509 }, {
510 .name = "i2c irq",
511 .start = IRQ_DOVE_I2C,
512 .end = IRQ_DOVE_I2C,
513 .flags = IORESOURCE_IRQ,
514 },
515};
516
517static struct platform_device dove_i2c = {
518 .name = MV64XXX_I2C_CTLR_NAME,
519 .id = 0,
520 .num_resources = ARRAY_SIZE(dove_i2c_resources),
521 .resource = dove_i2c_resources,
522 .dev = {
523 .platform_data = &dove_i2c_data,
524 },
525};
526
527void __init dove_i2c_init(void)
528{
529 platform_device_register(&dove_i2c);
530}
531
532/*****************************************************************************
533 * Time handling
534 ****************************************************************************/
535static int get_tclk(void)
536{
537 /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
538 return 166666667;
539}
540
541static void dove_timer_init(void)
542{
543 orion_time_init(IRQ_DOVE_BRIDGE, get_tclk());
544}
545
546struct sys_timer dove_timer = {
547 .init = dove_timer_init,
548};
549
550/*****************************************************************************
551 * XOR
552 ****************************************************************************/
553static struct mv_xor_platform_shared_data dove_xor_shared_data = {
554 .dram = &dove_mbus_dram_info,
555};
556
557/*****************************************************************************
558 * XOR 0
559 ****************************************************************************/
560static u64 dove_xor0_dmamask = DMA_BIT_MASK(32);
561
562static struct resource dove_xor0_shared_resources[] = {
563 {
564 .name = "xor 0 low",
565 .start = DOVE_XOR0_PHYS_BASE,
566 .end = DOVE_XOR0_PHYS_BASE + 0xff,
567 .flags = IORESOURCE_MEM,
568 }, {
569 .name = "xor 0 high",
570 .start = DOVE_XOR0_HIGH_PHYS_BASE,
571 .end = DOVE_XOR0_HIGH_PHYS_BASE + 0xff,
572 .flags = IORESOURCE_MEM,
573 },
574};
575
576static struct platform_device dove_xor0_shared = {
577 .name = MV_XOR_SHARED_NAME,
578 .id = 0,
579 .dev = {
580 .platform_data = &dove_xor_shared_data,
581 },
582 .num_resources = ARRAY_SIZE(dove_xor0_shared_resources),
583 .resource = dove_xor0_shared_resources,
584};
585
586static struct resource dove_xor00_resources[] = {
587 [0] = {
588 .start = IRQ_DOVE_XOR_00,
589 .end = IRQ_DOVE_XOR_00,
590 .flags = IORESOURCE_IRQ,
591 },
592};
593
594static struct mv_xor_platform_data dove_xor00_data = {
595 .shared = &dove_xor0_shared,
596 .hw_id = 0,
597 .pool_size = PAGE_SIZE,
598};
599
600static struct platform_device dove_xor00_channel = {
601 .name = MV_XOR_NAME,
602 .id = 0,
603 .num_resources = ARRAY_SIZE(dove_xor00_resources),
604 .resource = dove_xor00_resources,
605 .dev = {
606 .dma_mask = &dove_xor0_dmamask,
607 .coherent_dma_mask = DMA_BIT_MASK(64),
608 .platform_data = (void *)&dove_xor00_data,
609 },
610};
611
612static struct resource dove_xor01_resources[] = {
613 [0] = {
614 .start = IRQ_DOVE_XOR_01,
615 .end = IRQ_DOVE_XOR_01,
616 .flags = IORESOURCE_IRQ,
617 },
618};
619
620static struct mv_xor_platform_data dove_xor01_data = {
621 .shared = &dove_xor0_shared,
622 .hw_id = 1,
623 .pool_size = PAGE_SIZE,
624};
625
626static struct platform_device dove_xor01_channel = {
627 .name = MV_XOR_NAME,
628 .id = 1,
629 .num_resources = ARRAY_SIZE(dove_xor01_resources),
630 .resource = dove_xor01_resources,
631 .dev = {
632 .dma_mask = &dove_xor0_dmamask,
633 .coherent_dma_mask = DMA_BIT_MASK(64),
634 .platform_data = (void *)&dove_xor01_data,
635 },
636};
637
638void __init dove_xor0_init(void)
639{
640 platform_device_register(&dove_xor0_shared);
641
642 /*
643 * two engines can't do memset simultaneously, this limitation
644 * satisfied by removing memset support from one of the engines.
645 */
646 dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask);
647 dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask);
648 platform_device_register(&dove_xor00_channel);
649
650 dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask);
651 dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask);
652 dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask);
653 platform_device_register(&dove_xor01_channel);
654}
655
656/*****************************************************************************
657 * XOR 1
658 ****************************************************************************/
659static u64 dove_xor1_dmamask = DMA_BIT_MASK(32);
660
661static struct resource dove_xor1_shared_resources[] = {
662 {
663 .name = "xor 0 low",
664 .start = DOVE_XOR1_PHYS_BASE,
665 .end = DOVE_XOR1_PHYS_BASE + 0xff,
666 .flags = IORESOURCE_MEM,
667 }, {
668 .name = "xor 0 high",
669 .start = DOVE_XOR1_HIGH_PHYS_BASE,
670 .end = DOVE_XOR1_HIGH_PHYS_BASE + 0xff,
671 .flags = IORESOURCE_MEM,
672 },
673};
674
675static struct platform_device dove_xor1_shared = {
676 .name = MV_XOR_SHARED_NAME,
677 .id = 1,
678 .dev = {
679 .platform_data = &dove_xor_shared_data,
680 },
681 .num_resources = ARRAY_SIZE(dove_xor1_shared_resources),
682 .resource = dove_xor1_shared_resources,
683};
684
685static struct resource dove_xor10_resources[] = {
686 [0] = {
687 .start = IRQ_DOVE_XOR_10,
688 .end = IRQ_DOVE_XOR_10,
689 .flags = IORESOURCE_IRQ,
690 },
691};
692
693static struct mv_xor_platform_data dove_xor10_data = {
694 .shared = &dove_xor1_shared,
695 .hw_id = 0,
696 .pool_size = PAGE_SIZE,
697};
698
699static struct platform_device dove_xor10_channel = {
700 .name = MV_XOR_NAME,
701 .id = 2,
702 .num_resources = ARRAY_SIZE(dove_xor10_resources),
703 .resource = dove_xor10_resources,
704 .dev = {
705 .dma_mask = &dove_xor1_dmamask,
706 .coherent_dma_mask = DMA_BIT_MASK(64),
707 .platform_data = (void *)&dove_xor10_data,
708 },
709};
710
711static struct resource dove_xor11_resources[] = {
712 [0] = {
713 .start = IRQ_DOVE_XOR_11,
714 .end = IRQ_DOVE_XOR_11,
715 .flags = IORESOURCE_IRQ,
716 },
717};
718
719static struct mv_xor_platform_data dove_xor11_data = {
720 .shared = &dove_xor1_shared,
721 .hw_id = 1,
722 .pool_size = PAGE_SIZE,
723};
724
725static struct platform_device dove_xor11_channel = {
726 .name = MV_XOR_NAME,
727 .id = 3,
728 .num_resources = ARRAY_SIZE(dove_xor11_resources),
729 .resource = dove_xor11_resources,
730 .dev = {
731 .dma_mask = &dove_xor1_dmamask,
732 .coherent_dma_mask = DMA_BIT_MASK(64),
733 .platform_data = (void *)&dove_xor11_data,
734 },
735};
736
737void __init dove_xor1_init(void)
738{
739 platform_device_register(&dove_xor1_shared);
740
741 /*
742 * two engines can't do memset simultaneously, this limitation
743 * satisfied by removing memset support from one of the engines.
744 */
745 dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask);
746 dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask);
747 platform_device_register(&dove_xor10_channel);
748
749 dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask);
750 dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask);
751 dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask);
752 platform_device_register(&dove_xor11_channel);
753}
754
755void __init dove_init(void)
756{
757 int tclk;
758
759 tclk = get_tclk();
760
761 printk(KERN_INFO "Dove 88AP510 SoC, ");
762 printk(KERN_INFO "TCLK = %dMHz\n", (tclk + 499999) / 1000000);
763
764#ifdef CONFIG_CACHE_TAUROS2
765 tauros2_init();
766#endif
767 dove_setup_cpu_mbus();
768
769 dove_ge00_shared_data.t_clk = tclk;
770 dove_uart0_data[0].uartclk = tclk;
771 dove_uart1_data[0].uartclk = tclk;
772 dove_uart2_data[0].uartclk = tclk;
773 dove_uart3_data[0].uartclk = tclk;
774 dove_spi0_data.tclk = tclk;
775 dove_spi1_data.tclk = tclk;
776
777 /* internal devices that every board has */
778 dove_rtc_init();
779 dove_xor0_init();
780 dove_xor1_init();
781}
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
new file mode 100644
index 000000000000..b29e8937de4f
--- /dev/null
+++ b/arch/arm/mach-dove/common.h
@@ -0,0 +1,40 @@
1/*
2 * arch/arm/mach-dove/common.h
3 *
4 * Core functions for Marvell Dove 88AP510 System On Chip
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ARCH_DOVE_COMMON_H
12#define __ARCH_DOVE_COMMON_H
13
14struct mv643xx_eth_platform_data;
15struct mv_sata_platform_data;
16
17extern struct sys_timer dove_timer;
18extern struct mbus_dram_target_info dove_mbus_dram_info;
19
20/*
21 * Basic Dove init functions used early by machine-setup.
22 */
23void dove_map_io(void);
24void dove_init(void);
25void dove_init_irq(void);
26void dove_setup_cpu_mbus(void);
27void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
28void dove_sata_init(struct mv_sata_platform_data *sata_data);
29void dove_pcie_init(int init_port0, int init_port1);
30void dove_ehci0_init(void);
31void dove_ehci1_init(void);
32void dove_uart0_init(void);
33void dove_uart1_init(void);
34void dove_uart2_init(void);
35void dove_uart3_init(void);
36void dove_spi0_init(void);
37void dove_spi1_init(void);
38void dove_i2c_init(void);
39
40#endif
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
new file mode 100644
index 000000000000..f2971b745224
--- /dev/null
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -0,0 +1,102 @@
1/*
2 * arch/arm/mach-dove/dove-db-setup.c
3 *
4 * Marvell DB-MV88AP510-BP Development Board Setup
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/irq.h>
15#include <linux/mtd/physmap.h>
16#include <linux/mtd/nand.h>
17#include <linux/timer.h>
18#include <linux/ata_platform.h>
19#include <linux/mv643xx_eth.h>
20#include <linux/i2c.h>
21#include <linux/pci.h>
22#include <linux/spi/spi.h>
23#include <linux/spi/orion_spi.h>
24#include <linux/spi/flash.h>
25#include <linux/gpio.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <mach/dove.h>
29#include "common.h"
30
31static struct mv643xx_eth_platform_data dove_db_ge00_data = {
32 .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
33};
34
35static struct mv_sata_platform_data dove_db_sata_data = {
36 .n_ports = 1,
37};
38
39/*****************************************************************************
40 * SPI Devices:
41 * SPI0: 4M Flash ST-M25P32-VMF6P
42 ****************************************************************************/
43static const struct flash_platform_data dove_db_spi_flash_data = {
44 .type = "m25p64",
45};
46
47static struct spi_board_info __initdata dove_db_spi_flash_info[] = {
48 {
49 .modalias = "m25p80",
50 .platform_data = &dove_db_spi_flash_data,
51 .irq = -1,
52 .max_speed_hz = 20000000,
53 .bus_num = 0,
54 .chip_select = 0,
55 },
56};
57
58/*****************************************************************************
59 * PCI
60 ****************************************************************************/
61static int __init dove_db_pci_init(void)
62{
63 if (machine_is_dove_db())
64 dove_pcie_init(1, 1);
65
66 return 0;
67}
68
69subsys_initcall(dove_db_pci_init);
70
71/*****************************************************************************
72 * Board Init
73 ****************************************************************************/
74static void __init dove_db_init(void)
75{
76 /*
77 * Basic Dove setup. Needs to be called early.
78 */
79 dove_init();
80
81 dove_ge00_init(&dove_db_ge00_data);
82 dove_ehci0_init();
83 dove_ehci1_init();
84 dove_sata_init(&dove_db_sata_data);
85 dove_spi0_init();
86 dove_spi1_init();
87 dove_uart0_init();
88 dove_uart1_init();
89 dove_i2c_init();
90 spi_register_board_info(dove_db_spi_flash_info,
91 ARRAY_SIZE(dove_db_spi_flash_info));
92}
93
94MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board")
95 .phys_io = DOVE_SB_REGS_PHYS_BASE,
96 .io_pg_offst = ((DOVE_SB_REGS_VIRT_BASE) >> 18) & 0xfffc,
97 .boot_params = 0x00000100,
98 .init_machine = dove_db_init,
99 .map_io = dove_map_io,
100 .init_irq = dove_init_irq,
101 .timer = &dove_timer,
102MACHINE_END
diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h
new file mode 100644
index 000000000000..214a4c31f069
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/bridge-regs.h
@@ -0,0 +1,58 @@
1/*
2 * arch/arm/mach-dove/include/mach/bridge-regs.h
3 *
4 * Mbus-L to Mbus Bridge Registers
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_BRIDGE_REGS_H
12#define __ASM_ARCH_BRIDGE_REGS_H
13
14#include <mach/dove.h>
15
16#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0000)
17
18#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
19#define CPU_CTRL_PCIE0_LINK 0x00000001
20#define CPU_RESET 0x00000002
21#define CPU_CTRL_PCIE1_LINK 0x00000008
22
23#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
24#define SOFT_RESET_OUT_EN 0x00000004
25
26#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
27#define SOFT_RESET 0x00000001
28
29#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
30#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
31#define BRIDGE_INT_TIMER0 0x0002
32#define BRIDGE_INT_TIMER1 0x0004
33#define BRIDGE_INT_TIMER1_CLR (~0x0004)
34
35#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
36#define IRQ_CAUSE_LOW_OFF 0x0000
37#define IRQ_MASK_LOW_OFF 0x0004
38#define FIQ_MASK_LOW_OFF 0x0008
39#define ENDPOINT_MASK_LOW_OFF 0x000c
40#define IRQ_CAUSE_HIGH_OFF 0x0010
41#define IRQ_MASK_HIGH_OFF 0x0014
42#define FIQ_MASK_HIGH_OFF 0x0018
43#define ENDPOINT_MASK_HIGH_OFF 0x001c
44#define PCIE_INTERRUPT_MASK_OFF 0x0020
45
46#define IRQ_MASK_LOW (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)
47#define FIQ_MASK_LOW (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF)
48#define ENDPOINT_MASK_LOW (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF)
49#define IRQ_MASK_HIGH (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)
50#define FIQ_MASK_HIGH (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF)
51#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
52#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
53
54#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE | 0x011c)
55
56#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
57
58#endif
diff --git a/arch/arm/mach-dove/include/mach/debug-macro.S b/arch/arm/mach-dove/include/mach/debug-macro.S
new file mode 100644
index 000000000000..9b89ec7d3040
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/debug-macro.S
@@ -0,0 +1,20 @@
1/*
2 * arch/arm/mach-dove/include/mach/debug-macro.S
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7*/
8
9#include <mach/bridge-regs.h>
10
11 .macro addruart,rx
12 mrc p15, 0, \rx, c1, c0
13 tst \rx, #1 @ MMU enabled?
14 ldreq \rx, =DOVE_SB_REGS_PHYS_BASE
15 ldrne \rx, =DOVE_SB_REGS_VIRT_BASE
16 orr \rx, \rx, #0x00012000
17 .endm
18
19#define UART_SHIFT 2
20#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
new file mode 100644
index 000000000000..f6a08397f046
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -0,0 +1,180 @@
1/*
2 * arch/arm/mach-dove/include/mach/dove.h
3 *
4 * Generic definitions for Marvell Dove 88AP510 SoC
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_DOVE_H
12#define __ASM_ARCH_DOVE_H
13
14#include <mach/vmalloc.h>
15
16/*
17 * Marvell Dove address maps.
18 *
19 * phys virt size
20 * c8000000 fdb00000 1M Cryptographic SRAM
21 * e0000000 @runtime 128M PCIe-0 Memory space
22 * e8000000 @runtime 128M PCIe-1 Memory space
23 * f1000000 fde00000 8M on-chip south-bridge registers
24 * f1800000 fe600000 8M on-chip north-bridge registers
25 * f2000000 fee00000 1M PCIe-0 I/O space
26 * f2100000 fef00000 1M PCIe-1 I/O space
27 */
28
29#define DOVE_CESA_PHYS_BASE 0xc8000000
30#define DOVE_CESA_VIRT_BASE 0xfdb00000
31#define DOVE_CESA_SIZE SZ_1M
32
33#define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
34#define DOVE_PCIE0_MEM_SIZE SZ_128M
35
36#define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000
37#define DOVE_PCIE1_MEM_SIZE SZ_128M
38
39#define DOVE_BOOTROM_PHYS_BASE 0xf8000000
40#define DOVE_BOOTROM_SIZE SZ_128M
41
42#define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
43#define DOVE_SCRATCHPAD_VIRT_BASE 0xfdd00000
44#define DOVE_SCRATCHPAD_SIZE SZ_1M
45
46#define DOVE_SB_REGS_PHYS_BASE 0xf1000000
47#define DOVE_SB_REGS_VIRT_BASE 0xfde00000
48#define DOVE_SB_REGS_SIZE SZ_8M
49
50#define DOVE_NB_REGS_PHYS_BASE 0xf1800000
51#define DOVE_NB_REGS_VIRT_BASE 0xfe600000
52#define DOVE_NB_REGS_SIZE SZ_8M
53
54#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000
55#define DOVE_PCIE0_IO_VIRT_BASE 0xfee00000
56#define DOVE_PCIE0_IO_BUS_BASE 0x00000000
57#define DOVE_PCIE0_IO_SIZE SZ_1M
58
59#define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000
60#define DOVE_PCIE1_IO_VIRT_BASE 0xfef00000
61#define DOVE_PCIE1_IO_BUS_BASE 0x00100000
62#define DOVE_PCIE1_IO_SIZE SZ_1M
63
64/*
65 * Dove Core Registers Map
66 */
67
68/* SPI, I2C, UART */
69#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x11000)
70#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12000)
71#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12000)
72#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12100)
73#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12100)
74#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12200)
75#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12200)
76#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12300)
77#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12300)
78#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x10600)
79#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x14600)
80
81/* North-South Bridge */
82#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x20000)
83
84/* Cryptographic Engine */
85#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x30000)
86
87/* PCIe 0 */
88#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x40000)
89
90/* USB */
91#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x50000)
92#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x51000)
93
94/* XOR 0 Engine */
95#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60800)
96#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60800)
97#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60A00)
98#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60A00)
99
100/* XOR 1 Engine */
101#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60900)
102#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60900)
103#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60B00)
104#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60B00)
105
106/* Gigabit Ethernet */
107#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x70000)
108
109/* PCIe 1 */
110#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x80000)
111
112/* CAFE */
113#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x92000)
114#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x90000)
115#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x94000)
116#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x98000)
117
118/* SATA */
119#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xa0000)
120
121/* I2S/SPDIF */
122#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb0000)
123#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb4000)
124
125/* NAND Flash Controller */
126#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xc0000)
127
128/* MPP, GPIO, Reset Sampling */
129#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0200)
130#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
131#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014)
132#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018)
133#define DOVE_GPIO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
134#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
135#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)
136#define DOVE_NAND_GPIO_EN (1 << 0)
137#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_VIRT_BASE + 0x40)
138
139
140/* Power Management */
141#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0000)
142
143/* Real Time Clock */
144#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xd8500)
145
146/* AC97 */
147#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe0000)
148#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe0000)
149
150/* Peripheral DMA */
151#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe4000)
152#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe4000)
153
154#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE | 0xe802C)
155#define DOVE_TWSI_ENABLE_OPTION1 (1 << 7)
156#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE | 0xe8030)
157#define DOVE_TWSI_ENABLE_OPTION2 (1 << 20)
158#define DOVE_TWSI_ENABLE_OPTION3 (1 << 21)
159#define DOVE_TWSI_OPTION3_GPIO (1 << 22)
160#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xec000)
161#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE | 0xe8034)
162#define DOVE_SSP_ON_AU1 (1 << 0)
163#define DOVE_SSP_CLOCK_ENABLE (1 << 1)
164#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11)
165/* Memory Controller */
166#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE | 0x00000)
167
168/* LCD Controller */
169#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000)
170#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x20000)
171#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000)
172#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x30000)
173
174/* Graphic Engine */
175#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x40000)
176
177/* Video Engine */
178#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x400000)
179
180#endif
diff --git a/arch/arm/mach-dove/include/mach/entry-macro.S b/arch/arm/mach-dove/include/mach/entry-macro.S
new file mode 100644
index 000000000000..e84c78c2a8b7
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/entry-macro.S
@@ -0,0 +1,39 @@
1/*
2 * arch/arm/mach-dove/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for Marvell Dove platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <mach/bridge-regs.h>
12
13 .macro disable_fiq
14 .endm
15
16 .macro arch_ret_to_user, tmp1, tmp2
17 .endm
18
19 .macro get_irqnr_preamble, base, tmp
20 ldr \base, =IRQ_VIRT_BASE
21 .endm
22
23 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
24 @ check low interrupts
25 ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
26 ldr \tmp, [\base, #IRQ_MASK_LOW_OFF]
27 mov \irqnr, #31
28 ands \irqstat, \irqstat, \tmp
29
30 @ if no low interrupts set, check high interrupts
31 ldreq \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
32 ldreq \tmp, [\base, #IRQ_MASK_HIGH_OFF]
33 moveq \irqnr, #63
34 andeqs \irqstat, \irqstat, \tmp
35
36 @ find first active interrupt source
37 clzne \irqstat, \irqstat
38 subne \irqnr, \irqnr, \irqstat
39 .endm
diff --git a/arch/arm/mach-dove/include/mach/gpio.h b/arch/arm/mach-dove/include/mach/gpio.h
new file mode 100644
index 000000000000..0ee70ff39e11
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/gpio.h
@@ -0,0 +1,49 @@
1/*
2 * arch/arm/mach-dove/include/mach/gpio.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_GPIO_H
10#define __ASM_ARCH_GPIO_H
11
12#include <asm/errno.h>
13#include <mach/irqs.h>
14#include <plat/gpio.h>
15#include <asm-generic/gpio.h> /* cansleep wrappers */
16
17#define GPIO_MAX 64
18
19#define GPIO_BASE_LO (DOVE_GPIO_VIRT_BASE + 0x00)
20#define GPIO_BASE_HI (DOVE_GPIO_VIRT_BASE + 0x20)
21
22#define GPIO_BASE(pin) ((pin < 32) ? GPIO_BASE_LO : GPIO_BASE_HI)
23
24#define GPIO_OUT(pin) (GPIO_BASE(pin) + 0x00)
25#define GPIO_IO_CONF(pin) (GPIO_BASE(pin) + 0x04)
26#define GPIO_BLINK_EN(pin) (GPIO_BASE(pin) + 0x08)
27#define GPIO_IN_POL(pin) (GPIO_BASE(pin) + 0x0c)
28#define GPIO_DATA_IN(pin) (GPIO_BASE(pin) + 0x10)
29#define GPIO_EDGE_CAUSE(pin) (GPIO_BASE(pin) + 0x14)
30#define GPIO_EDGE_MASK(pin) (GPIO_BASE(pin) + 0x18)
31#define GPIO_LEVEL_MASK(pin) (GPIO_BASE(pin) + 0x1c)
32
33static inline int gpio_to_irq(int pin)
34{
35 if (pin < NR_GPIO_IRQS)
36 return pin + IRQ_DOVE_GPIO_START;
37
38 return -EINVAL;
39}
40
41static inline int irq_to_gpio(int irq)
42{
43 if (IRQ_DOVE_GPIO_START < irq && irq < NR_IRQS)
44 return irq - IRQ_DOVE_GPIO_START;
45
46 return -EINVAL;
47}
48
49#endif
diff --git a/arch/arm/mach-dove/include/mach/hardware.h b/arch/arm/mach-dove/include/mach/hardware.h
new file mode 100644
index 000000000000..32b0826e7873
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/hardware.h
@@ -0,0 +1,26 @@
1/*
2 * arch/arm/mach-dove/include/mach/hardware.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_HARDWARE_H
10#define __ASM_ARCH_HARDWARE_H
11
12#include "dove.h"
13
14#define pcibios_assign_all_busses() 1
15
16#define PCIBIOS_MIN_IO 0x1000
17#define PCIBIOS_MIN_MEM 0x01000000
18#define PCIMEM_BASE DOVE_PCIE0_MEM_PHYS_BASE
19
20
21/* Macros below are required for compatibility with PXA AC'97 driver. */
22#define __REG(x) (*((volatile u32 *)((x) - DOVE_SB_REGS_PHYS_BASE + \
23 DOVE_SB_REGS_VIRT_BASE)))
24#define __PREG(x) (((u32)&(x)) - DOVE_SB_REGS_VIRT_BASE + \
25 DOVE_SB_REGS_PHYS_BASE)
26#endif
diff --git a/arch/arm/mach-dove/include/mach/io.h b/arch/arm/mach-dove/include/mach/io.h
new file mode 100644
index 000000000000..3b3e4721ce2e
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/io.h
@@ -0,0 +1,20 @@
1/*
2 * arch/arm/mach-dove/include/mach/io.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_IO_H
10#define __ASM_ARCH_IO_H
11
12#include "dove.h"
13
14#define IO_SPACE_LIMIT 0xffffffff
15
16#define __io(a) ((void __iomem *)(((a) - DOVE_PCIE0_IO_PHYS_BASE) +\
17 DOVE_PCIE0_IO_VIRT_BASE))
18#define __mem_pci(a) (a)
19
20#endif
diff --git a/arch/arm/mach-dove/include/mach/irqs.h b/arch/arm/mach-dove/include/mach/irqs.h
new file mode 100644
index 000000000000..46681466f92b
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/irqs.h
@@ -0,0 +1,101 @@
1/*
2 * arch/arm/mach-dove/include/mach/irqs.h
3 *
4 * IRQ definitions for Marvell Dove 88AP510 SoC
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_IRQS_H
12#define __ASM_ARCH_IRQS_H
13
14/*
15 * Dove Low Interrupt Controller
16 */
17#define IRQ_DOVE_BRIDGE 0
18#define IRQ_DOVE_H2C 1
19#define IRQ_DOVE_C2H 2
20#define IRQ_DOVE_NAND 3
21#define IRQ_DOVE_PDMA 4
22#define IRQ_DOVE_SPI1 5
23#define IRQ_DOVE_SPI0 6
24#define IRQ_DOVE_UART_0 7
25#define IRQ_DOVE_UART_1 8
26#define IRQ_DOVE_UART_2 9
27#define IRQ_DOVE_UART_3 10
28#define IRQ_DOVE_I2C 11
29#define IRQ_DOVE_GPIO_0_7 12
30#define IRQ_DOVE_GPIO_8_15 13
31#define IRQ_DOVE_GPIO_16_23 14
32#define IRQ_DOVE_PCIE0_ERR 15
33#define IRQ_DOVE_PCIE0 16
34#define IRQ_DOVE_PCIE1_ERR 17
35#define IRQ_DOVE_PCIE1 18
36#define IRQ_DOVE_I2S0 19
37#define IRQ_DOVE_I2S0_ERR 20
38#define IRQ_DOVE_I2S1 21
39#define IRQ_DOVE_I2S1_ERR 22
40#define IRQ_DOVE_USB_ERR 23
41#define IRQ_DOVE_USB0 24
42#define IRQ_DOVE_USB1 25
43#define IRQ_DOVE_GE00_RX 26
44#define IRQ_DOVE_GE00_TX 27
45#define IRQ_DOVE_GE00_MISC 28
46#define IRQ_DOVE_GE00_SUM 29
47#define IRQ_DOVE_GE00_ERR 30
48#define IRQ_DOVE_CRYPTO 31
49
50/*
51 * Dove High Interrupt Controller
52 */
53#define IRQ_DOVE_AC97 32
54#define IRQ_DOVE_PMU 33
55#define IRQ_DOVE_CAM 34
56#define IRQ_DOVE_SDIO0 35
57#define IRQ_DOVE_SDIO1 36
58#define IRQ_DOVE_SDIO0_WAKEUP 37
59#define IRQ_DOVE_SDIO1_WAKEUP 38
60#define IRQ_DOVE_XOR_00 39
61#define IRQ_DOVE_XOR_01 40
62#define IRQ_DOVE_XOR0_ERR 41
63#define IRQ_DOVE_XOR_10 42
64#define IRQ_DOVE_XOR_11 43
65#define IRQ_DOVE_XOR1_ERR 44
66#define IRQ_DOVE_LCD_DCON 45
67#define IRQ_DOVE_LCD1 46
68#define IRQ_DOVE_LCD0 47
69#define IRQ_DOVE_GPU 48
70#define IRQ_DOVE_PERFORM_MNTR 49
71#define IRQ_DOVE_VPRO_DMA1 51
72#define IRQ_DOVE_SSP_TIMER 54
73#define IRQ_DOVE_SSP 55
74#define IRQ_DOVE_MC_L2_ERR 56
75#define IRQ_DOVE_CRYPTO_ERR 59
76#define IRQ_DOVE_GPIO_24_31 60
77#define IRQ_DOVE_HIGH_GPIO 61
78#define IRQ_DOVE_SATA 62
79
80/*
81 * DOVE General Purpose Pins
82 */
83#define IRQ_DOVE_GPIO_START 64
84#define NR_GPIO_IRQS 64
85
86/*
87 * PMU interrupts
88 */
89#define IRQ_DOVE_PMU_START (IRQ_DOVE_GPIO_START + NR_GPIO_IRQS)
90#define NR_PMU_IRQS 7
91#define IRQ_DOVE_RTC (IRQ_DOVE_PMU_START + 5)
92
93#define NR_IRQS (IRQ_DOVE_PMU_START + NR_PMU_IRQS)
94
95/* Required for compatability with PXA AC97 driver. */
96#define IRQ_AC97 IRQ_DOVE_AC97
97/* Required for compatability with PXA DMA driver. */
98#define IRQ_DMA IRQ_DOVE_PDMA
99/* Required for compatability with PXA NAND driver */
100#define IRQ_NAND IRQ_DOVE_NAND
101#endif
diff --git a/arch/arm/mach-dove/include/mach/memory.h b/arch/arm/mach-dove/include/mach/memory.h
new file mode 100644
index 000000000000..d66872074946
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/memory.h
@@ -0,0 +1,10 @@
1/*
2 * arch/arm/mach-dove/include/mach/memory.h
3 */
4
5#ifndef __ASM_ARCH_MEMORY_H
6#define __ASM_ARCH_MEMORY_H
7
8#define PHYS_OFFSET UL(0x00000000)
9
10#endif
diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h
new file mode 100644
index 000000000000..3ad9f946a9e8
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/pm.h
@@ -0,0 +1,54 @@
1/*
2 * arch/arm/mach-dove/include/mach/pm.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_PM_H
10#define __ASM_ARCH_PM_H
11
12#include <asm/errno.h>
13#include <mach/irqs.h>
14
15#define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38)
16#define CLOCK_GATING_USB0_MASK (1 << 0)
17#define CLOCK_GATING_USB1_MASK (1 << 1)
18#define CLOCK_GATING_GBE_MASK (1 << 2)
19#define CLOCK_GATING_SATA_MASK (1 << 3)
20#define CLOCK_GATING_PCIE0_MASK (1 << 4)
21#define CLOCK_GATING_PCIE1_MASK (1 << 5)
22#define CLOCK_GATING_SDIO0_MASK (1 << 8)
23#define CLOCK_GATING_SDIO1_MASK (1 << 9)
24#define CLOCK_GATING_NAND_MASK (1 << 10)
25#define CLOCK_GATING_CAMERA_MASK (1 << 11)
26#define CLOCK_GATING_I2S0_MASK (1 << 12)
27#define CLOCK_GATING_I2S1_MASK (1 << 13)
28#define CLOCK_GATING_CRYPTO_MASK (1 << 15)
29#define CLOCK_GATING_AC97_MASK (1 << 21)
30#define CLOCK_GATING_PDMA_MASK (1 << 22)
31#define CLOCK_GATING_XOR0_MASK (1 << 23)
32#define CLOCK_GATING_XOR1_MASK (1 << 24)
33#define CLOCK_GATING_GIGA_PHY_MASK (1 << 30)
34
35#define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50)
36#define PMU_INTERRUPT_MASK (DOVE_PMU_VIRT_BASE + 0x54)
37
38static inline int pmu_to_irq(int pin)
39{
40 if (pin < NR_PMU_IRQS)
41 return pin + IRQ_DOVE_PMU_START;
42
43 return -EINVAL;
44}
45
46static inline int irq_to_pmu(int irq)
47{
48 if (IRQ_DOVE_PMU_START < irq && irq < NR_IRQS)
49 return irq - IRQ_DOVE_PMU_START;
50
51 return -EINVAL;
52}
53
54#endif
diff --git a/arch/arm/mach-dove/include/mach/system.h b/arch/arm/mach-dove/include/mach/system.h
new file mode 100644
index 000000000000..356afda56853
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/system.h
@@ -0,0 +1,36 @@
1/*
2 * arch/arm/mach-dove/include/mach/system.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_SYSTEM_H
10#define __ASM_ARCH_SYSTEM_H
11
12#include <mach/bridge-regs.h>
13
14static inline void arch_idle(void)
15{
16 cpu_do_idle();
17}
18
19static inline void arch_reset(char mode, const char *cmd)
20{
21 /*
22 * Enable soft reset to assert RSTOUTn.
23 */
24 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
25
26 /*
27 * Assert soft reset.
28 */
29 writel(SOFT_RESET, SYSTEM_SOFT_RESET);
30
31 while (1)
32 ;
33}
34
35
36#endif
diff --git a/arch/arm/mach-dove/include/mach/timex.h b/arch/arm/mach-dove/include/mach/timex.h
new file mode 100644
index 000000000000..251d538541db
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/timex.h
@@ -0,0 +1,9 @@
1/*
2 * arch/arm/mach-dove/include/mach/timex.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/arch/arm/mach-dove/include/mach/uncompress.h b/arch/arm/mach-dove/include/mach/uncompress.h
new file mode 100644
index 000000000000..2c5cdd7a3eed
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/uncompress.h
@@ -0,0 +1,37 @@
1/*
2 * arch/arm/mach-dove/include/mach/uncompress.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#include <mach/dove.h>
10
11#define UART_THR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x0))
12#define UART_LSR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x14))
13
14#define LSR_THRE 0x20
15
16static void putc(const char c)
17{
18 int i;
19
20 for (i = 0; i < 0x1000; i++) {
21 /* Transmit fifo not full? */
22 if (*UART_LSR & LSR_THRE)
23 break;
24 }
25
26 *UART_THR = c;
27}
28
29static void flush(void)
30{
31}
32
33/*
34 * nothing to do
35 */
36#define arch_decomp_setup()
37#define arch_decomp_wdog()
diff --git a/arch/arm/mach-dove/include/mach/vmalloc.h b/arch/arm/mach-dove/include/mach/vmalloc.h
new file mode 100644
index 000000000000..8b2c974755c6
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/vmalloc.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-dove/include/mach/vmalloc.h
3 */
4
5#define VMALLOC_END 0xfd800000
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
new file mode 100644
index 000000000000..61bfcb3b08c2
--- /dev/null
+++ b/arch/arm/mach-dove/irq.c
@@ -0,0 +1,133 @@
1/*
2 * arch/arm/mach-dove/irq.c
3 *
4 * Dove IRQ handling.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/irq.h>
14#include <linux/gpio.h>
15#include <linux/io.h>
16#include <asm/mach/arch.h>
17#include <plat/irq.h>
18#include <asm/mach/irq.h>
19#include <mach/pm.h>
20#include <mach/bridge-regs.h>
21#include "common.h"
22
23static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
24{
25 int irqoff;
26 BUG_ON(irq < IRQ_DOVE_GPIO_0_7 || irq > IRQ_DOVE_HIGH_GPIO);
27
28 irqoff = irq <= IRQ_DOVE_GPIO_16_23 ? irq - IRQ_DOVE_GPIO_0_7 :
29 3 + irq - IRQ_DOVE_GPIO_24_31;
30
31 orion_gpio_irq_handler(irqoff << 3);
32 if (irq == IRQ_DOVE_HIGH_GPIO) {
33 orion_gpio_irq_handler(40);
34 orion_gpio_irq_handler(48);
35 orion_gpio_irq_handler(56);
36 }
37}
38
39static void pmu_irq_mask(unsigned int irq)
40{
41 int pin = irq_to_pmu(irq);
42 u32 u;
43
44 u = readl(PMU_INTERRUPT_MASK);
45 u &= ~(1 << (pin & 31));
46 writel(u, PMU_INTERRUPT_MASK);
47}
48
49static void pmu_irq_unmask(unsigned int irq)
50{
51 int pin = irq_to_pmu(irq);
52 u32 u;
53
54 u = readl(PMU_INTERRUPT_MASK);
55 u |= 1 << (pin & 31);
56 writel(u, PMU_INTERRUPT_MASK);
57}
58
59static void pmu_irq_ack(unsigned int irq)
60{
61 int pin = irq_to_pmu(irq);
62 u32 u;
63
64 u = ~(1 << (pin & 31));
65 writel(u, PMU_INTERRUPT_CAUSE);
66}
67
68static struct irq_chip pmu_irq_chip = {
69 .name = "pmu_irq",
70 .mask = pmu_irq_mask,
71 .unmask = pmu_irq_unmask,
72 .ack = pmu_irq_ack,
73};
74
75static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
76{
77 unsigned long cause = readl(PMU_INTERRUPT_CAUSE);
78
79 cause &= readl(PMU_INTERRUPT_MASK);
80 if (cause == 0) {
81 do_bad_IRQ(irq, desc);
82 return;
83 }
84
85 for (irq = 0; irq < NR_PMU_IRQS; irq++) {
86 if (!(cause & (1 << irq)))
87 continue;
88 irq = pmu_to_irq(irq);
89 desc = irq_desc + irq;
90 desc_handle_irq(irq, desc);
91 }
92}
93
94void __init dove_init_irq(void)
95{
96 int i;
97
98 orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
99 orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
100
101 /*
102 * Mask and clear GPIO IRQ interrupts.
103 */
104 writel(0, GPIO_LEVEL_MASK(0));
105 writel(0, GPIO_EDGE_MASK(0));
106 writel(0, GPIO_EDGE_CAUSE(0));
107
108 /*
109 * Mask and clear PMU interrupts
110 */
111 writel(0, PMU_INTERRUPT_MASK);
112 writel(0, PMU_INTERRUPT_CAUSE);
113
114 for (i = IRQ_DOVE_GPIO_START; i < IRQ_DOVE_PMU_START; i++) {
115 set_irq_chip(i, &orion_gpio_irq_chip);
116 set_irq_handler(i, handle_level_irq);
117 irq_desc[i].status |= IRQ_LEVEL;
118 set_irq_flags(i, IRQF_VALID);
119 }
120 set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
121 set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
122 set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
123 set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
124 set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
125
126 for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
127 set_irq_chip(i, &pmu_irq_chip);
128 set_irq_handler(i, handle_level_irq);
129 irq_desc[i].status |= IRQ_LEVEL;
130 set_irq_flags(i, IRQF_VALID);
131 }
132 set_irq_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
133}
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
new file mode 100644
index 000000000000..502d1ca2f4b7
--- /dev/null
+++ b/arch/arm/mach-dove/pcie.c
@@ -0,0 +1,238 @@
1/*
2 * arch/arm/mach-dove/pcie.c
3 *
4 * PCIe functions for Marvell Dove 88AP510 SoC
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/pci.h>
13#include <linux/mbus.h>
14#include <asm/mach/pci.h>
15#include <asm/mach/arch.h>
16#include <asm/setup.h>
17#include <asm/delay.h>
18#include <plat/pcie.h>
19#include <mach/irqs.h>
20#include <mach/bridge-regs.h>
21#include "common.h"
22
23struct pcie_port {
24 u8 index;
25 u8 root_bus_nr;
26 void __iomem *base;
27 spinlock_t conf_lock;
28 char io_space_name[16];
29 char mem_space_name[16];
30 struct resource res[2];
31};
32
33static struct pcie_port pcie_port[2];
34static int num_pcie_ports;
35
36
37static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
38{
39 struct pcie_port *pp;
40
41 if (nr >= num_pcie_ports)
42 return 0;
43
44 pp = &pcie_port[nr];
45 pp->root_bus_nr = sys->busnr;
46
47 /*
48 * Generic PCIe unit setup.
49 */
50 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
51
52 orion_pcie_setup(pp->base, &dove_mbus_dram_info);
53
54 /*
55 * IORESOURCE_IO
56 */
57 snprintf(pp->io_space_name, sizeof(pp->io_space_name),
58 "PCIe %d I/O", pp->index);
59 pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
60 pp->res[0].name = pp->io_space_name;
61 if (pp->index == 0) {
62 pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE;
63 pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1;
64 } else {
65 pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE;
66 pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1;
67 }
68 pp->res[0].flags = IORESOURCE_IO;
69 if (request_resource(&ioport_resource, &pp->res[0]))
70 panic("Request PCIe IO resource failed\n");
71 sys->resource[0] = &pp->res[0];
72
73 /*
74 * IORESOURCE_MEM
75 */
76 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
77 "PCIe %d MEM", pp->index);
78 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
79 pp->res[1].name = pp->mem_space_name;
80 if (pp->index == 0) {
81 pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE;
82 pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1;
83 } else {
84 pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE;
85 pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1;
86 }
87 pp->res[1].flags = IORESOURCE_MEM;
88 if (request_resource(&iomem_resource, &pp->res[1]))
89 panic("Request PCIe Memory resource failed\n");
90 sys->resource[1] = &pp->res[1];
91
92 sys->resource[2] = NULL;
93
94 return 1;
95}
96
97static struct pcie_port *bus_to_port(int bus)
98{
99 int i;
100
101 for (i = num_pcie_ports - 1; i >= 0; i--) {
102 int rbus = pcie_port[i].root_bus_nr;
103 if (rbus != -1 && rbus <= bus)
104 break;
105 }
106
107 return i >= 0 ? pcie_port + i : NULL;
108}
109
110static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
111{
112 /*
113 * Don't go out when trying to access nonexisting devices
114 * on the local bus.
115 */
116 if (bus == pp->root_bus_nr && dev > 1)
117 return 0;
118
119 return 1;
120}
121
122static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
123 int size, u32 *val)
124{
125 struct pcie_port *pp = bus_to_port(bus->number);
126 unsigned long flags;
127 int ret;
128
129 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
130 *val = 0xffffffff;
131 return PCIBIOS_DEVICE_NOT_FOUND;
132 }
133
134 spin_lock_irqsave(&pp->conf_lock, flags);
135 ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
136 spin_unlock_irqrestore(&pp->conf_lock, flags);
137
138 return ret;
139}
140
141static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
142 int where, int size, u32 val)
143{
144 struct pcie_port *pp = bus_to_port(bus->number);
145 unsigned long flags;
146 int ret;
147
148 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
149 return PCIBIOS_DEVICE_NOT_FOUND;
150
151 spin_lock_irqsave(&pp->conf_lock, flags);
152 ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
153 spin_unlock_irqrestore(&pp->conf_lock, flags);
154
155 return ret;
156}
157
158static struct pci_ops pcie_ops = {
159 .read = pcie_rd_conf,
160 .write = pcie_wr_conf,
161};
162
163static void __devinit rc_pci_fixup(struct pci_dev *dev)
164{
165 /*
166 * Prevent enumeration of root complex.
167 */
168 if (dev->bus->parent == NULL && dev->devfn == 0) {
169 int i;
170
171 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
172 dev->resource[i].start = 0;
173 dev->resource[i].end = 0;
174 dev->resource[i].flags = 0;
175 }
176 }
177}
178DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
179
180static struct pci_bus __init *
181dove_pcie_scan_bus(int nr, struct pci_sys_data *sys)
182{
183 struct pci_bus *bus;
184
185 if (nr < num_pcie_ports) {
186 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
187 } else {
188 bus = NULL;
189 BUG();
190 }
191
192 return bus;
193}
194
195static int __init dove_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
196{
197 struct pcie_port *pp = bus_to_port(dev->bus->number);
198
199 return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
200}
201
202static struct hw_pci dove_pci __initdata = {
203 .nr_controllers = 2,
204 .swizzle = pci_std_swizzle,
205 .setup = dove_pcie_setup,
206 .scan = dove_pcie_scan_bus,
207 .map_irq = dove_pcie_map_irq,
208};
209
210static void __init add_pcie_port(int index, unsigned long base)
211{
212 printk(KERN_INFO "Dove PCIe port %d: ", index);
213
214 if (orion_pcie_link_up((void __iomem *)base)) {
215 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
216
217 printk(KERN_INFO "link up\n");
218
219 pp->index = index;
220 pp->root_bus_nr = -1;
221 pp->base = (void __iomem *)base;
222 spin_lock_init(&pp->conf_lock);
223 memset(pp->res, 0, sizeof(pp->res));
224 } else {
225 printk(KERN_INFO "link down, ignoring\n");
226 }
227}
228
229void __init dove_pcie_init(int init_port0, int init_port1)
230{
231 if (init_port0)
232 add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);
233
234 if (init_port1)
235 add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);
236
237 pci_common_init(&dove_pci);
238}
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 0aca451b216d..8bf09ae5b347 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -33,10 +33,18 @@ config MACH_SHEEVAPLUG
33 Marvell SheevaPlug Reference Board. 33 Marvell SheevaPlug Reference Board.
34 34
35config MACH_TS219 35config MACH_TS219
36 bool "QNAP TS-119 and TS-219 Turbo NAS" 36 bool "QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS"
37 help 37 help
38 Say 'Y' here if you want your kernel to support the 38 Say 'Y' here if you want your kernel to support the
39 QNAP TS-119 and TS-219 Turbo NAS devices. 39 QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS
40 devices.
41
42config MACH_TS41X
43 bool "QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS"
44 help
45 Say 'Y' here if you want your kernel to support the
46 QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS
47 devices.
40 48
41config MACH_OPENRD_BASE 49config MACH_OPENRD_BASE
42 bool "Marvell OpenRD Base Board" 50 bool "Marvell OpenRD Base Board"
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 80ab0ec90ee1..9f2f67b2b63d 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -5,7 +5,8 @@ obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o
5obj-$(CONFIG_MACH_RD88F6281) += rd88f6281-setup.o 5obj-$(CONFIG_MACH_RD88F6281) += rd88f6281-setup.o
6obj-$(CONFIG_MACH_MV88F6281GTW_GE) += mv88f6281gtw_ge-setup.o 6obj-$(CONFIG_MACH_MV88F6281GTW_GE) += mv88f6281gtw_ge-setup.o
7obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o 7obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o
8obj-$(CONFIG_MACH_TS219) += ts219-setup.o 8obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o
9obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o
9obj-$(CONFIG_MACH_OPENRD_BASE) += openrd_base-setup.o 10obj-$(CONFIG_MACH_OPENRD_BASE) += openrd_base-setup.o
10 11
11obj-$(CONFIG_CPU_IDLE) += cpuidle.o 12obj-$(CONFIG_CPU_IDLE) += cpuidle.o
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index ec1a64f263d2..2830f0fe80e0 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * 2 *
3 * QNAP TS-119/TS-219 Turbo NAS Board Setup 3 * QNAP TS-11x/TS-21x Turbo NAS Board Setup
4 * 4 *
5 * Copyright (C) 2009 Martin Michlmayr <tbm@cyrius.com> 5 * Copyright (C) 2009 Martin Michlmayr <tbm@cyrius.com>
6 * Copyright (C) 2008 Byron Bradley <byron.bbradley@gmail.com> 6 * Copyright (C) 2008 Byron Bradley <byron.bbradley@gmail.com>
@@ -14,87 +14,17 @@
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/mtd/physmap.h>
18#include <linux/spi/flash.h>
19#include <linux/spi/spi.h>
20#include <linux/spi/orion_spi.h>
21#include <linux/i2c.h> 17#include <linux/i2c.h>
22#include <linux/mv643xx_eth.h> 18#include <linux/mv643xx_eth.h>
23#include <linux/ata_platform.h> 19#include <linux/ata_platform.h>
24#include <linux/gpio_keys.h> 20#include <linux/gpio_keys.h>
25#include <linux/input.h> 21#include <linux/input.h>
26#include <linux/timex.h>
27#include <linux/serial_reg.h>
28#include <linux/pci.h>
29#include <asm/mach-types.h> 22#include <asm/mach-types.h>
30#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
31#include <mach/kirkwood.h> 24#include <mach/kirkwood.h>
32#include "common.h" 25#include "common.h"
33#include "mpp.h" 26#include "mpp.h"
34 27#include "tsx1x-common.h"
35/****************************************************************************
36 * 16 MiB NOR flash. The struct mtd_partition is not in the same order as the
37 * partitions on the device because we want to keep compatability with
38 * the QNAP firmware.
39 * Layout as used by QNAP:
40 * 0x00000000-0x00080000 : "U-Boot"
41 * 0x00200000-0x00400000 : "Kernel"
42 * 0x00400000-0x00d00000 : "RootFS"
43 * 0x00d00000-0x01000000 : "RootFS2"
44 * 0x00080000-0x000c0000 : "U-Boot Config"
45 * 0x000c0000-0x00200000 : "NAS Config"
46 *
47 * We'll use "RootFS1" instead of "RootFS" to stay compatible with the layout
48 * used by the QNAP TS-109/TS-209.
49 *
50 ***************************************************************************/
51
52static struct mtd_partition qnap_ts219_partitions[] = {
53 {
54 .name = "U-Boot",
55 .size = 0x00080000,
56 .offset = 0,
57 .mask_flags = MTD_WRITEABLE,
58 }, {
59 .name = "Kernel",
60 .size = 0x00200000,
61 .offset = 0x00200000,
62 }, {
63 .name = "RootFS1",
64 .size = 0x00900000,
65 .offset = 0x00400000,
66 }, {
67 .name = "RootFS2",
68 .size = 0x00300000,
69 .offset = 0x00d00000,
70 }, {
71 .name = "U-Boot Config",
72 .size = 0x00040000,
73 .offset = 0x00080000,
74 }, {
75 .name = "NAS Config",
76 .size = 0x00140000,
77 .offset = 0x000c0000,
78 },
79};
80
81static const struct flash_platform_data qnap_ts219_flash = {
82 .type = "m25p128",
83 .name = "spi_flash",
84 .parts = qnap_ts219_partitions,
85 .nr_parts = ARRAY_SIZE(qnap_ts219_partitions),
86};
87
88static struct spi_board_info __initdata qnap_ts219_spi_slave_info[] = {
89 {
90 .modalias = "m25p80",
91 .platform_data = &qnap_ts219_flash,
92 .irq = -1,
93 .max_speed_hz = 20000000,
94 .bus_num = 0,
95 .chip_select = 0,
96 },
97};
98 28
99static struct i2c_board_info __initdata qnap_ts219_i2c_rtc = { 29static struct i2c_board_info __initdata qnap_ts219_i2c_rtc = {
100 I2C_BOARD_INFO("s35390a", 0x30), 30 I2C_BOARD_INFO("s35390a", 0x30),
@@ -152,36 +82,10 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
152 MPP14_UART1_RXD, /* PIC controller */ 82 MPP14_UART1_RXD, /* PIC controller */
153 MPP15_GPIO, /* USB Copy button */ 83 MPP15_GPIO, /* USB Copy button */
154 MPP16_GPIO, /* Reset button */ 84 MPP16_GPIO, /* Reset button */
85 MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */
155 0 86 0
156}; 87};
157 88
158
159/*****************************************************************************
160 * QNAP TS-x19 specific power off method via UART1-attached PIC
161 ****************************************************************************/
162
163#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2))
164
165void qnap_ts219_power_off(void)
166{
167 /* 19200 baud divisor */
168 const unsigned divisor = ((kirkwood_tclk + (8 * 19200)) / (16 * 19200));
169
170 pr_info("%s: triggering power-off...\n", __func__);
171
172 /* hijack UART1 and reset into sane state (19200,8n1) */
173 writel(0x83, UART1_REG(LCR));
174 writel(divisor & 0xff, UART1_REG(DLL));
175 writel((divisor >> 8) & 0xff, UART1_REG(DLM));
176 writel(0x03, UART1_REG(LCR));
177 writel(0x00, UART1_REG(IER));
178 writel(0x00, UART1_REG(FCR));
179 writel(0x00, UART1_REG(MCR));
180
181 /* send the power-off command 'A' to PIC */
182 writel('A', UART1_REG(TX));
183}
184
185static void __init qnap_ts219_init(void) 89static void __init qnap_ts219_init(void)
186{ 90{
187 /* 91 /*
@@ -192,9 +96,7 @@ static void __init qnap_ts219_init(void)
192 96
193 kirkwood_uart0_init(); 97 kirkwood_uart0_init();
194 kirkwood_uart1_init(); /* A PIC controller is connected here. */ 98 kirkwood_uart1_init(); /* A PIC controller is connected here. */
195 spi_register_board_info(qnap_ts219_spi_slave_info, 99 qnap_tsx1x_register_flash();
196 ARRAY_SIZE(qnap_ts219_spi_slave_info));
197 kirkwood_spi_init();
198 kirkwood_i2c_init(); 100 kirkwood_i2c_init();
199 i2c_register_board_info(0, &qnap_ts219_i2c_rtc, 1); 101 i2c_register_board_info(0, &qnap_ts219_i2c_rtc, 1);
200 kirkwood_ge00_init(&qnap_ts219_ge00_data); 102 kirkwood_ge00_init(&qnap_ts219_ge00_data);
@@ -202,7 +104,7 @@ static void __init qnap_ts219_init(void)
202 kirkwood_ehci_init(); 104 kirkwood_ehci_init();
203 platform_device_register(&qnap_ts219_button_device); 105 platform_device_register(&qnap_ts219_button_device);
204 106
205 pm_power_off = qnap_ts219_power_off; 107 pm_power_off = qnap_tsx1x_power_off;
206 108
207} 109}
208 110
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
new file mode 100644
index 000000000000..de49c2d9e74b
--- /dev/null
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -0,0 +1,154 @@
1/*
2 *
3 * QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS Board Setup
4 *
5 * Copyright (C) 2009 Martin Michlmayr <tbm@cyrius.com>
6 * Copyright (C) 2008 Byron Bradley <byron.bbradley@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/i2c.h>
18#include <linux/mv643xx_eth.h>
19#include <linux/ata_platform.h>
20#include <linux/gpio_keys.h>
21#include <linux/input.h>
22#include <asm/mach-types.h>
23#include <asm/mach/arch.h>
24#include <mach/kirkwood.h>
25#include "common.h"
26#include "mpp.h"
27#include "tsx1x-common.h"
28
29static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = {
30 I2C_BOARD_INFO("s35390a", 0x30),
31};
32
33static struct mv643xx_eth_platform_data qnap_ts41x_ge00_data = {
34 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
35};
36
37static struct mv643xx_eth_platform_data qnap_ts41x_ge01_data = {
38 .phy_addr = MV643XX_ETH_PHY_ADDR(0),
39};
40
41static struct mv_sata_platform_data qnap_ts41x_sata_data = {
42 .n_ports = 2,
43};
44
45static struct gpio_keys_button qnap_ts41x_buttons[] = {
46 {
47 .code = KEY_COPY,
48 .gpio = 43,
49 .desc = "USB Copy",
50 .active_low = 1,
51 },
52 {
53 .code = KEY_RESTART,
54 .gpio = 37,
55 .desc = "Reset",
56 .active_low = 1,
57 },
58};
59
60static struct gpio_keys_platform_data qnap_ts41x_button_data = {
61 .buttons = qnap_ts41x_buttons,
62 .nbuttons = ARRAY_SIZE(qnap_ts41x_buttons),
63};
64
65static struct platform_device qnap_ts41x_button_device = {
66 .name = "gpio-keys",
67 .id = -1,
68 .num_resources = 0,
69 .dev = {
70 .platform_data = &qnap_ts41x_button_data,
71 }
72};
73
74static unsigned int qnap_ts41x_mpp_config[] __initdata = {
75 MPP0_SPI_SCn,
76 MPP1_SPI_MOSI,
77 MPP2_SPI_SCK,
78 MPP3_SPI_MISO,
79 MPP6_SYSRST_OUTn,
80 MPP7_PEX_RST_OUTn,
81 MPP8_TW_SDA,
82 MPP9_TW_SCK,
83 MPP10_UART0_TXD,
84 MPP11_UART0_RXD,
85 MPP13_UART1_TXD, /* PIC controller */
86 MPP14_UART1_RXD, /* PIC controller */
87 MPP15_SATA0_ACTn,
88 MPP16_SATA1_ACTn,
89 MPP20_GE1_0,
90 MPP21_GE1_1,
91 MPP22_GE1_2,
92 MPP23_GE1_3,
93 MPP24_GE1_4,
94 MPP25_GE1_5,
95 MPP26_GE1_6,
96 MPP27_GE1_7,
97 MPP30_GE1_10,
98 MPP31_GE1_11,
99 MPP32_GE1_12,
100 MPP33_GE1_13,
101 MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */
102 MPP37_GPIO, /* Reset button */
103 MPP43_GPIO, /* USB Copy button */
104 MPP44_GPIO, /* Board ID: 0: TS-419U, 1: TS-419 */
105 MPP45_GPIO, /* JP1: 0: console, 1: LCD */
106 MPP46_GPIO, /* External SATA HDD1 error indicator */
107 MPP47_GPIO, /* External SATA HDD2 error indicator */
108 MPP48_GPIO, /* External SATA HDD3 error indicator */
109 MPP49_GPIO, /* External SATA HDD4 error indicator */
110 0
111};
112
113static void __init qnap_ts41x_init(void)
114{
115 /*
116 * Basic setup. Needs to be called early.
117 */
118 kirkwood_init();
119 kirkwood_mpp_conf(qnap_ts41x_mpp_config);
120
121 kirkwood_uart0_init();
122 kirkwood_uart1_init(); /* A PIC controller is connected here. */
123 qnap_tsx1x_register_flash();
124 kirkwood_i2c_init();
125 i2c_register_board_info(0, &qnap_ts41x_i2c_rtc, 1);
126 kirkwood_ge00_init(&qnap_ts41x_ge00_data);
127 kirkwood_ge01_init(&qnap_ts41x_ge01_data);
128 kirkwood_sata_init(&qnap_ts41x_sata_data);
129 kirkwood_ehci_init();
130 platform_device_register(&qnap_ts41x_button_device);
131
132 pm_power_off = qnap_tsx1x_power_off;
133
134}
135
136static int __init ts41x_pci_init(void)
137{
138 if (machine_is_ts41x())
139 kirkwood_pcie_init();
140
141 return 0;
142}
143subsys_initcall(ts41x_pci_init);
144
145MACHINE_START(TS41X, "QNAP TS-41x")
146 /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
147 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
148 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
149 .boot_params = 0x00000100,
150 .init_machine = qnap_ts41x_init,
151 .map_io = kirkwood_map_io,
152 .init_irq = kirkwood_init_irq,
153 .timer = &kirkwood_timer,
154MACHINE_END
diff --git a/arch/arm/mach-kirkwood/tsx1x-common.c b/arch/arm/mach-kirkwood/tsx1x-common.c
new file mode 100644
index 000000000000..7221c20b2afa
--- /dev/null
+++ b/arch/arm/mach-kirkwood/tsx1x-common.c
@@ -0,0 +1,113 @@
1#include <linux/kernel.h>
2#include <linux/pci.h>
3#include <linux/platform_device.h>
4#include <linux/mtd/physmap.h>
5#include <linux/spi/flash.h>
6#include <linux/spi/spi.h>
7#include <linux/spi/orion_spi.h>
8#include <linux/serial_reg.h>
9#include <mach/kirkwood.h>
10#include "common.h"
11
12/*
13 * QNAP TS-x1x Boards flash
14 */
15
16/****************************************************************************
17 * 16 MiB NOR flash. The struct mtd_partition is not in the same order as the
18 * partitions on the device because we want to keep compatability with
19 * the QNAP firmware.
20 * Layout as used by QNAP:
21 * 0x00000000-0x00080000 : "U-Boot"
22 * 0x00200000-0x00400000 : "Kernel"
23 * 0x00400000-0x00d00000 : "RootFS"
24 * 0x00d00000-0x01000000 : "RootFS2"
25 * 0x00080000-0x000c0000 : "U-Boot Config"
26 * 0x000c0000-0x00200000 : "NAS Config"
27 *
28 * We'll use "RootFS1" instead of "RootFS" to stay compatible with the layout
29 * used by the QNAP TS-109/TS-209.
30 *
31 ***************************************************************************/
32
33struct mtd_partition qnap_tsx1x_partitions[] = {
34 {
35 .name = "U-Boot",
36 .size = 0x00080000,
37 .offset = 0,
38 .mask_flags = MTD_WRITEABLE,
39 }, {
40 .name = "Kernel",
41 .size = 0x00200000,
42 .offset = 0x00200000,
43 }, {
44 .name = "RootFS1",
45 .size = 0x00900000,
46 .offset = 0x00400000,
47 }, {
48 .name = "RootFS2",
49 .size = 0x00300000,
50 .offset = 0x00d00000,
51 }, {
52 .name = "U-Boot Config",
53 .size = 0x00040000,
54 .offset = 0x00080000,
55 }, {
56 .name = "NAS Config",
57 .size = 0x00140000,
58 .offset = 0x000c0000,
59 },
60};
61
62const struct flash_platform_data qnap_tsx1x_flash = {
63 .type = "m25p128",
64 .name = "spi_flash",
65 .parts = qnap_tsx1x_partitions,
66 .nr_parts = ARRAY_SIZE(qnap_tsx1x_partitions),
67};
68
69struct spi_board_info __initdata qnap_tsx1x_spi_slave_info[] = {
70 {
71 .modalias = "m25p80",
72 .platform_data = &qnap_tsx1x_flash,
73 .irq = -1,
74 .max_speed_hz = 20000000,
75 .bus_num = 0,
76 .chip_select = 0,
77 },
78};
79
80void qnap_tsx1x_register_flash(void)
81{
82 spi_register_board_info(qnap_tsx1x_spi_slave_info,
83 ARRAY_SIZE(qnap_tsx1x_spi_slave_info));
84 kirkwood_spi_init();
85}
86
87
88/*****************************************************************************
89 * QNAP TS-x1x specific power off method via UART1-attached PIC
90 ****************************************************************************/
91
92#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2))
93
94void qnap_tsx1x_power_off(void)
95{
96 /* 19200 baud divisor */
97 const unsigned divisor = ((kirkwood_tclk + (8 * 19200)) / (16 * 19200));
98
99 pr_info("%s: triggering power-off...\n", __func__);
100
101 /* hijack UART1 and reset into sane state (19200,8n1) */
102 writel(0x83, UART1_REG(LCR));
103 writel(divisor & 0xff, UART1_REG(DLL));
104 writel((divisor >> 8) & 0xff, UART1_REG(DLM));
105 writel(0x03, UART1_REG(LCR));
106 writel(0x00, UART1_REG(IER));
107 writel(0x00, UART1_REG(FCR));
108 writel(0x00, UART1_REG(MCR));
109
110 /* send the power-off command 'A' to PIC */
111 writel('A', UART1_REG(TX));
112}
113
diff --git a/arch/arm/mach-kirkwood/tsx1x-common.h b/arch/arm/mach-kirkwood/tsx1x-common.h
new file mode 100644
index 000000000000..9a592962a6ea
--- /dev/null
+++ b/arch/arm/mach-kirkwood/tsx1x-common.h
@@ -0,0 +1,7 @@
1#ifndef __ARCH_KIRKWOOD_TSX1X_COMMON_H
2#define __ARCH_KIRKWOOD_TSX1X_COMMON_H
3
4extern void qnap_tsx1x_register_flash(void);
5extern void qnap_tsx1x_power_off(void);
6
7#endif
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 9264d814cd7a..4958ef2c6254 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -388,7 +388,7 @@ config CPU_FEROCEON_OLD_ID
388 388
389# ARMv6 389# ARMv6
390config CPU_V6 390config CPU_V6
391 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX 391 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_DOVE
392 select CPU_32v6 392 select CPU_32v6
393 select CPU_ABRT_EV6 393 select CPU_ABRT_EV6
394 select CPU_PABRT_V6 394 select CPU_PABRT_V6
@@ -764,6 +764,15 @@ config CACHE_L2X0
764 help 764 help
765 This option enables the L2x0 PrimeCell. 765 This option enables the L2x0 PrimeCell.
766 766
767config CACHE_TAUROS2
768 bool "Enable the Tauros2 L2 cache controller"
769 depends on ARCH_DOVE
770 default y
771 select OUTER_CACHE
772 help
773 This option enables the Tauros2 L2 cache controller (as
774 found on PJ1/PJ4).
775
767config CACHE_XSC3L2 776config CACHE_XSC3L2
768 bool "Enable the L2 cache on XScale3" 777 bool "Enable the L2 cache on XScale3"
769 depends on CPU_XSC3 778 depends on CPU_XSC3
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 055cb2aa8134..06bcf2e73858 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -87,4 +87,4 @@ obj-$(CONFIG_CPU_V7) += proc-v7.o
87obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o 87obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o
88obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o 88obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
89obj-$(CONFIG_CACHE_XSC3L2) += cache-xsc3l2.o 89obj-$(CONFIG_CACHE_XSC3L2) += cache-xsc3l2.o
90 90obj-$(CONFIG_CACHE_TAUROS2) += cache-tauros2.o
diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c
new file mode 100644
index 000000000000..50868651890f
--- /dev/null
+++ b/arch/arm/mm/cache-tauros2.c
@@ -0,0 +1,263 @@
1/*
2 * arch/arm/mm/cache-tauros2.c - Tauros2 L2 cache controller support
3 *
4 * Copyright (C) 2008 Marvell Semiconductor
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 *
10 * References:
11 * - PJ1 CPU Core Datasheet,
12 * Document ID MV-S104837-01, Rev 0.7, January 24 2008.
13 * - PJ4 CPU Core Datasheet,
14 * Document ID MV-S105190-00, Rev 0.7, March 14 2008.
15 */
16
17#include <linux/init.h>
18#include <asm/cacheflush.h>
19#include <asm/hardware/cache-tauros2.h>
20
21
22/*
23 * When Tauros2 is used on a CPU that supports the v7 hierarchical
24 * cache operations, the cache handling code in proc-v7.S takes care
25 * of everything, including handling DMA coherency.
26 *
27 * So, we only need to register outer cache operations here if we're
28 * being used on a pre-v7 CPU, and we only need to build support for
29 * outer cache operations into the kernel image if the kernel has been
30 * configured to support a pre-v7 CPU.
31 */
32#if __LINUX_ARM_ARCH__ < 7
33/*
34 * Low-level cache maintenance operations.
35 */
36static inline void tauros2_clean_pa(unsigned long addr)
37{
38 __asm__("mcr p15, 1, %0, c7, c11, 3" : : "r" (addr));
39}
40
41static inline void tauros2_clean_inv_pa(unsigned long addr)
42{
43 __asm__("mcr p15, 1, %0, c7, c15, 3" : : "r" (addr));
44}
45
46static inline void tauros2_inv_pa(unsigned long addr)
47{
48 __asm__("mcr p15, 1, %0, c7, c7, 3" : : "r" (addr));
49}
50
51
52/*
53 * Linux primitives.
54 *
55 * Note that the end addresses passed to Linux primitives are
56 * noninclusive.
57 */
58#define CACHE_LINE_SIZE 32
59
60static void tauros2_inv_range(unsigned long start, unsigned long end)
61{
62 /*
63 * Clean and invalidate partial first cache line.
64 */
65 if (start & (CACHE_LINE_SIZE - 1)) {
66 tauros2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1));
67 start = (start | (CACHE_LINE_SIZE - 1)) + 1;
68 }
69
70 /*
71 * Clean and invalidate partial last cache line.
72 */
73 if (end & (CACHE_LINE_SIZE - 1)) {
74 tauros2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
75 end &= ~(CACHE_LINE_SIZE - 1);
76 }
77
78 /*
79 * Invalidate all full cache lines between 'start' and 'end'.
80 */
81 while (start < end) {
82 tauros2_inv_pa(start);
83 start += CACHE_LINE_SIZE;
84 }
85
86 dsb();
87}
88
89static void tauros2_clean_range(unsigned long start, unsigned long end)
90{
91 start &= ~(CACHE_LINE_SIZE - 1);
92 while (start < end) {
93 tauros2_clean_pa(start);
94 start += CACHE_LINE_SIZE;
95 }
96
97 dsb();
98}
99
100static void tauros2_flush_range(unsigned long start, unsigned long end)
101{
102 start &= ~(CACHE_LINE_SIZE - 1);
103 while (start < end) {
104 tauros2_clean_inv_pa(start);
105 start += CACHE_LINE_SIZE;
106 }
107
108 dsb();
109}
110#endif
111
112static inline u32 __init read_extra_features(void)
113{
114 u32 u;
115
116 __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u));
117
118 return u;
119}
120
121static inline void __init write_extra_features(u32 u)
122{
123 __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));
124}
125
126static void __init disable_l2_prefetch(void)
127{
128 u32 u;
129
130 /*
131 * Read the CPU Extra Features register and verify that the
132 * Disable L2 Prefetch bit is set.
133 */
134 u = read_extra_features();
135 if (!(u & 0x01000000)) {
136 printk(KERN_INFO "Tauros2: Disabling L2 prefetch.\n");
137 write_extra_features(u | 0x01000000);
138 }
139}
140
141static inline int __init cpuid_scheme(void)
142{
143 extern int processor_id;
144
145 return !!((processor_id & 0x000f0000) == 0x000f0000);
146}
147
148static inline u32 __init read_mmfr3(void)
149{
150 u32 mmfr3;
151
152 __asm__("mrc p15, 0, %0, c0, c1, 7\n" : "=r" (mmfr3));
153
154 return mmfr3;
155}
156
157static inline u32 __init read_actlr(void)
158{
159 u32 actlr;
160
161 __asm__("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr));
162
163 return actlr;
164}
165
166static inline void __init write_actlr(u32 actlr)
167{
168 __asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr));
169}
170
171void __init tauros2_init(void)
172{
173 extern int processor_id;
174 char *mode;
175
176 disable_l2_prefetch();
177
178#ifdef CONFIG_CPU_32v5
179 if ((processor_id & 0xff0f0000) == 0x56050000) {
180 u32 feat;
181
182 /*
183 * v5 CPUs with Tauros2 have the L2 cache enable bit
184 * located in the CPU Extra Features register.
185 */
186 feat = read_extra_features();
187 if (!(feat & 0x00400000)) {
188 printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
189 write_extra_features(feat | 0x00400000);
190 }
191
192 mode = "ARMv5";
193 outer_cache.inv_range = tauros2_inv_range;
194 outer_cache.clean_range = tauros2_clean_range;
195 outer_cache.flush_range = tauros2_flush_range;
196 }
197#endif
198
199#ifdef CONFIG_CPU_32v6
200 /*
201 * Check whether this CPU lacks support for the v7 hierarchical
202 * cache ops. (PJ4 is in its v6 personality mode if the MMFR3
203 * register indicates no support for the v7 hierarchical cache
204 * ops.)
205 */
206 if (cpuid_scheme() && (read_mmfr3() & 0xf) == 0) {
207 /*
208 * When Tauros2 is used in an ARMv6 system, the L2
209 * enable bit is in the ARMv6 ARM-mandated position
210 * (bit [26] of the System Control Register).
211 */
212 if (!(get_cr() & 0x04000000)) {
213 printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
214 adjust_cr(0x04000000, 0x04000000);
215 }
216
217 mode = "ARMv6";
218 outer_cache.inv_range = tauros2_inv_range;
219 outer_cache.clean_range = tauros2_clean_range;
220 outer_cache.flush_range = tauros2_flush_range;
221 }
222#endif
223
224#ifdef CONFIG_CPU_32v7
225 /*
226 * Check whether this CPU has support for the v7 hierarchical
227 * cache ops. (PJ4 is in its v7 personality mode if the MMFR3
228 * register indicates support for the v7 hierarchical cache
229 * ops.)
230 *
231 * (Although strictly speaking there may exist CPUs that
232 * implement the v7 cache ops but are only ARMv6 CPUs (due to
233 * not complying with all of the other ARMv7 requirements),
234 * there are no real-life examples of Tauros2 being used on
235 * such CPUs as of yet.)
236 */
237 if (cpuid_scheme() && (read_mmfr3() & 0xf) == 1) {
238 u32 actlr;
239
240 /*
241 * When Tauros2 is used in an ARMv7 system, the L2
242 * enable bit is located in the Auxiliary System Control
243 * Register (which is the only register allowed by the
244 * ARMv7 spec to contain fine-grained cache control bits).
245 */
246 actlr = read_actlr();
247 if (!(actlr & 0x00000002)) {
248 printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
249 write_actlr(actlr | 0x00000002);
250 }
251
252 mode = "ARMv7";
253 }
254#endif
255
256 if (mode == NULL) {
257 printk(KERN_CRIT "Tauros2: Unable to detect CPU mode.\n");
258 return;
259 }
260
261 printk(KERN_INFO "Tauros2: L2 cache support initialised "
262 "in %s mode.\n", mode);
263}
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 70f75d2e3ead..5485c821101c 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -130,9 +130,16 @@ ENTRY(cpu_v6_set_pte_ext)
130 130
131 131
132 132
133 133 .type cpu_v6_name, #object
134cpu_v6_name: 134cpu_v6_name:
135 .asciz "ARMv6-compatible processor" 135 .asciz "ARMv6-compatible processor"
136 .size cpu_v6_name, . - cpu_v6_name
137
138 .type cpu_pj4_name, #object
139cpu_pj4_name:
140 .asciz "Marvell PJ4 processor"
141 .size cpu_pj4_name, . - cpu_pj4_name
142
136 .align 143 .align
137 144
138 __INIT 145 __INIT
@@ -241,3 +248,27 @@ __v6_proc_info:
241 .long v6_user_fns 248 .long v6_user_fns
242 .long v6_cache_fns 249 .long v6_cache_fns
243 .size __v6_proc_info, . - __v6_proc_info 250 .size __v6_proc_info, . - __v6_proc_info
251
252 .type __pj4_v6_proc_info, #object
253__pj4_v6_proc_info:
254 .long 0x560f5810
255 .long 0xff0ffff0
256 .long PMD_TYPE_SECT | \
257 PMD_SECT_BUFFERABLE | \
258 PMD_SECT_CACHEABLE | \
259 PMD_SECT_AP_WRITE | \
260 PMD_SECT_AP_READ
261 .long PMD_TYPE_SECT | \
262 PMD_SECT_XN | \
263 PMD_SECT_AP_WRITE | \
264 PMD_SECT_AP_READ
265 b __v6_setup
266 .long cpu_arch_name
267 .long cpu_elf_name
268 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
269 .long cpu_pj4_name
270 .long v6_processor_functions
271 .long v6wbi_tlb_fns
272 .long v6_user_fns
273 .long v6_cache_fns
274 .size __pj4_v6_proc_info, . - __pj4_v6_proc_info
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-12 15:28:27 -0500