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-rw-r--r--arch/arm/boot/dts/spear300-evb.dts221
-rw-r--r--arch/arm/boot/dts/spear300.dtsi77
-rw-r--r--arch/arm/boot/dts/spear310-evb.dts172
-rw-r--r--arch/arm/boot/dts/spear310.dtsi80
-rw-r--r--arch/arm/boot/dts/spear320-evb.dts173
-rw-r--r--arch/arm/boot/dts/spear320.dtsi95
-rw-r--r--arch/arm/boot/dts/spear3xx.dtsi144
-rw-r--r--arch/arm/boot/dts/spear600-evb.dts4
-rw-r--r--arch/arm/boot/dts/spear600.dtsi8
-rw-r--r--arch/arm/configs/spear3xx_defconfig52
-rw-r--r--arch/arm/configs/spear6xx_defconfig41
-rw-r--r--arch/arm/mach-spear3xx/Kconfig37
-rw-r--r--arch/arm/mach-spear3xx/Makefile13
-rw-r--r--arch/arm/mach-spear3xx/Makefile.boot4
-rw-r--r--arch/arm/mach-spear3xx/include/mach/generic.h163
-rw-r--r--arch/arm/mach-spear3xx/include/mach/hardware.h3
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear.h9
-rw-r--r--arch/arm/mach-spear3xx/spear300.c613
-rw-r--r--arch/arm/mach-spear3xx/spear300_evb.c75
-rw-r--r--arch/arm/mach-spear3xx/spear310.c416
-rw-r--r--arch/arm/mach-spear3xx/spear310_evb.c81
-rw-r--r--arch/arm/mach-spear3xx/spear320.c663
-rw-r--r--arch/arm/mach-spear3xx/spear320_evb.c79
-rw-r--r--arch/arm/mach-spear3xx/spear3xx.c541
-rw-r--r--arch/arm/mach-spear6xx/Makefile.boot2
-rw-r--r--arch/arm/mach-spear6xx/spear6xx.c372
-rw-r--r--arch/arm/plat-spear/Kconfig4
-rw-r--r--arch/arm/plat-spear/Makefile4
-rw-r--r--arch/arm/plat-spear/include/plat/padmux.h92
-rw-r--r--arch/arm/plat-spear/include/plat/pl080.h21
-rw-r--r--arch/arm/plat-spear/padmux.c164
-rw-r--r--arch/arm/plat-spear/pl080.c79
32 files changed, 2387 insertions, 2115 deletions
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
new file mode 100644
index 000000000000..402ca0d55011
--- /dev/null
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -0,0 +1,221 @@
1/*
2 * DTS file for SPEAr300 Evaluation Baord
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "spear300.dtsi"
16
17/ {
18 model = "ST SPEAr300 Evaluation Board";
19 compatible = "st,spear300-evb", "st,spear300";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 reg = <0 0x40000000>;
25 };
26
27 ahb {
28 pinmux@99000000 {
29 st,pinmux-mode = <2>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&state_default>;
32
33 state_default: pinmux {
34 i2c0 {
35 st,pins = "i2c0_grp";
36 st,function = "i2c0";
37 };
38 ssp0 {
39 st,pins = "ssp0_grp";
40 st,function = "ssp0";
41 };
42 mii0 {
43 st,pins = "mii0_grp";
44 st,function = "mii0";
45 };
46 uart0 {
47 st,pins = "uart0_grp";
48 st,function = "uart0";
49 };
50 clcd {
51 st,pins = "clcd_pfmode_grp";
52 st,function = "clcd";
53 };
54 sdhci {
55 st,pins = "sdhci_4bit_grp";
56 st,function = "sdhci";
57 };
58 gpio1 {
59 st,pins = "gpio1_4_to_7_grp",
60 "gpio1_0_to_3_grp";
61 st,function = "gpio1";
62 };
63 };
64 };
65
66 clcd@60000000 {
67 status = "okay";
68 };
69
70 dma@fc400000 {
71 status = "okay";
72 };
73
74 fsmc: flash@94000000 {
75 status = "okay";
76 };
77
78 gmac: eth@e0800000 {
79 status = "okay";
80 };
81
82 sdhci@70000000 {
83 int-gpio = <&gpio1 0 0>;
84 power-gpio = <&gpio1 2 1>;
85 status = "okay";
86 };
87
88 smi: flash@fc000000 {
89 status = "okay";
90 };
91
92 spi0: spi@d0100000 {
93 status = "okay";
94 };
95
96 ehci@e1800000 {
97 status = "okay";
98 };
99
100 ohci@e1900000 {
101 status = "okay";
102 };
103
104 ohci@e2100000 {
105 status = "okay";
106 };
107
108 apb {
109 gpio0: gpio@fc980000 {
110 status = "okay";
111 };
112
113 gpio1: gpio@a9000000 {
114 status = "okay";
115 };
116
117 i2c0: i2c@d0180000 {
118 status = "okay";
119 };
120
121 kbd@a0000000 {
122 linux,keymap = < 0x00010000
123 0x00020100
124 0x00030200
125 0x00040300
126 0x00050400
127 0x00060500
128 0x00070600
129 0x00080700
130 0x00090800
131 0x000a0001
132 0x000c0101
133 0x000d0201
134 0x000e0301
135 0x000f0401
136 0x00100501
137 0x00110601
138 0x00120701
139 0x00130801
140 0x00140002
141 0x00150102
142 0x00160202
143 0x00170302
144 0x00180402
145 0x00190502
146 0x001a0602
147 0x001b0702
148 0x001c0802
149 0x001d0003
150 0x001e0103
151 0x001f0203
152 0x00200303
153 0x00210403
154 0x00220503
155 0x00230603
156 0x00240703
157 0x00250803
158 0x00260004
159 0x00270104
160 0x00280204
161 0x00290304
162 0x002a0404
163 0x002b0504
164 0x002c0604
165 0x002d0704
166 0x002e0804
167 0x002f0005
168 0x00300105
169 0x00310205
170 0x00320305
171 0x00330405
172 0x00340505
173 0x00350605
174 0x00360705
175 0x00370805
176 0x00380006
177 0x00390106
178 0x003a0206
179 0x003b0306
180 0x003c0406
181 0x003d0506
182 0x003e0606
183 0x003f0706
184 0x00400806
185 0x00410007
186 0x00420107
187 0x00430207
188 0x00440307
189 0x00450407
190 0x00460507
191 0x00470607
192 0x00480707
193 0x00490807
194 0x004a0008
195 0x004b0108
196 0x004c0208
197 0x004d0308
198 0x004e0408
199 0x004f0508
200 0x00500608
201 0x00510708
202 0x00520808 >;
203 autorepeat;
204 st,mode = <0>;
205 status = "okay";
206 };
207
208 rtc@fc900000 {
209 status = "okay";
210 };
211
212 serial@d0000000 {
213 status = "okay";
214 };
215
216 wdt@fc880000 {
217 status = "okay";
218 };
219 };
220 };
221};
diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi
new file mode 100644
index 000000000000..01c5e358fdb2
--- /dev/null
+++ b/arch/arm/boot/dts/spear300.dtsi
@@ -0,0 +1,77 @@
1/*
2 * DTS file for SPEAr300 SoC
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear3xx.dtsi"
15
16/ {
17 ahb {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "simple-bus";
21 ranges = <0x60000000 0x60000000 0x50000000
22 0xd0000000 0xd0000000 0x30000000>;
23
24 pinmux@99000000 {
25 compatible = "st,spear300-pinmux";
26 reg = <0x99000000 0x1000>;
27 };
28
29 clcd@60000000 {
30 compatible = "arm,clcd-pl110", "arm,primecell";
31 reg = <0x60000000 0x1000>;
32 interrupts = <30>;
33 status = "disabled";
34 };
35
36 fsmc: flash@94000000 {
37 compatible = "st,spear600-fsmc-nand";
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x94000000 0x1000 /* FSMC Register */
41 0x80000000 0x0010>; /* NAND Base */
42 reg-names = "fsmc_regs", "nand_data";
43 st,ale-off = <0x20000>;
44 st,cle-off = <0x10000>;
45 status = "disabled";
46 };
47
48 sdhci@70000000 {
49 compatible = "st,sdhci-spear";
50 reg = <0x70000000 0x100>;
51 interrupts = <1>;
52 status = "disabled";
53 };
54
55 apb {
56 #address-cells = <1>;
57 #size-cells = <1>;
58 compatible = "simple-bus";
59 ranges = <0xa0000000 0xa0000000 0x10000000
60 0xd0000000 0xd0000000 0x30000000>;
61
62 gpio1: gpio@a9000000 {
63 #gpio-cells = <2>;
64 compatible = "arm,pl061", "arm,primecell";
65 gpio-controller;
66 reg = <0xa9000000 0x1000>;
67 status = "disabled";
68 };
69
70 kbd@a0000000 {
71 compatible = "st,spear300-kbd";
72 reg = <0xa0000000 0x1000>;
73 status = "disabled";
74 };
75 };
76 };
77};
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
new file mode 100644
index 000000000000..6d95317100ad
--- /dev/null
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -0,0 +1,172 @@
1/*
2 * DTS file for SPEAr310 Evaluation Baord
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "spear310.dtsi"
16
17/ {
18 model = "ST SPEAr310 Evaluation Board";
19 compatible = "st,spear310-evb", "st,spear310";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 reg = <0 0x40000000>;
25 };
26
27 ahb {
28 pinmux@b4000000 {
29 pinctrl-names = "default";
30 pinctrl-0 = <&state_default>;
31
32 state_default: pinmux {
33 gpio0 {
34 st,pins = "gpio0_pin0_grp",
35 "gpio0_pin1_grp",
36 "gpio0_pin2_grp",
37 "gpio0_pin3_grp",
38 "gpio0_pin4_grp",
39 "gpio0_pin5_grp";
40 st,function = "gpio0";
41 };
42 i2c0 {
43 st,pins = "i2c0_grp";
44 st,function = "i2c0";
45 };
46 mii0 {
47 st,pins = "mii0_grp";
48 st,function = "mii0";
49 };
50 ssp0 {
51 st,pins = "ssp0_grp";
52 st,function = "ssp0";
53 };
54 uart0 {
55 st,pins = "uart0_grp";
56 st,function = "uart0";
57 };
58 emi {
59 st,pins = "emi_cs_0_to_5_grp";
60 st,function = "emi";
61 };
62 fsmc {
63 st,pins = "fsmc_grp";
64 st,function = "fsmc";
65 };
66 uart1 {
67 st,pins = "uart1_grp";
68 st,function = "uart1";
69 };
70 uart2 {
71 st,pins = "uart2_grp";
72 st,function = "uart2";
73 };
74 uart3 {
75 st,pins = "uart3_grp";
76 st,function = "uart3";
77 };
78 uart4 {
79 st,pins = "uart4_grp";
80 st,function = "uart4";
81 };
82 uart5 {
83 st,pins = "uart5_grp";
84 st,function = "uart5";
85 };
86 };
87 };
88
89 dma@fc400000 {
90 status = "okay";
91 };
92
93 fsmc: flash@44000000 {
94 status = "okay";
95 };
96
97 gmac: eth@e0800000 {
98 status = "okay";
99 };
100
101 smi: flash@fc000000 {
102 status = "okay";
103 clock-rate=<50000000>;
104
105 flash@f8000000 {
106 label = "m25p64";
107 reg = <0xf8000000 0x800000>;
108 #address-cells = <1>;
109 #size-cells = <1>;
110 st,smi-fast-mode;
111 };
112 };
113
114 spi0: spi@d0100000 {
115 status = "okay";
116 };
117
118 ehci@e1800000 {
119 status = "okay";
120 };
121
122 ohci@e1900000 {
123 status = "okay";
124 };
125
126 ohci@e2100000 {
127 status = "okay";
128 };
129
130 apb {
131 gpio0: gpio@fc980000 {
132 status = "okay";
133 };
134
135 i2c0: i2c@d0180000 {
136 status = "okay";
137 };
138
139 rtc@fc900000 {
140 status = "okay";
141 };
142
143 serial@d0000000 {
144 status = "okay";
145 };
146
147 serial@b2000000 {
148 status = "okay";
149 };
150
151 serial@b2080000 {
152 status = "okay";
153 };
154
155 serial@b2100000 {
156 status = "okay";
157 };
158
159 serial@b2180000 {
160 status = "okay";
161 };
162
163 serial@b2200000 {
164 status = "okay";
165 };
166
167 wdt@fc880000 {
168 status = "okay";
169 };
170 };
171 };
172};
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
new file mode 100644
index 000000000000..e47081c494d9
--- /dev/null
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -0,0 +1,80 @@
1/*
2 * DTS file for SPEAr310 SoC
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear3xx.dtsi"
15
16/ {
17 ahb {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "simple-bus";
21 ranges = <0x40000000 0x40000000 0x10000000
22 0xb0000000 0xb0000000 0x10000000
23 0xd0000000 0xd0000000 0x30000000>;
24
25 pinmux@b4000000 {
26 compatible = "st,spear310-pinmux";
27 reg = <0xb4000000 0x1000>;
28 };
29
30 fsmc: flash@44000000 {
31 compatible = "st,spear600-fsmc-nand";
32 #address-cells = <1>;
33 #size-cells = <1>;
34 reg = <0x44000000 0x1000 /* FSMC Register */
35 0x40000000 0x0010>; /* NAND Base */
36 reg-names = "fsmc_regs", "nand_data";
37 st,ale-off = <0x10000>;
38 st,cle-off = <0x20000>;
39 status = "disabled";
40 };
41
42 apb {
43 #address-cells = <1>;
44 #size-cells = <1>;
45 compatible = "simple-bus";
46 ranges = <0xb0000000 0xb0000000 0x10000000
47 0xd0000000 0xd0000000 0x30000000>;
48
49 serial@b2000000 {
50 compatible = "arm,pl011", "arm,primecell";
51 reg = <0xb2000000 0x1000>;
52 status = "disabled";
53 };
54
55 serial@b2080000 {
56 compatible = "arm,pl011", "arm,primecell";
57 reg = <0xb2080000 0x1000>;
58 status = "disabled";
59 };
60
61 serial@b2100000 {
62 compatible = "arm,pl011", "arm,primecell";
63 reg = <0xb2100000 0x1000>;
64 status = "disabled";
65 };
66
67 serial@b2180000 {
68 compatible = "arm,pl011", "arm,primecell";
69 reg = <0xb2180000 0x1000>;
70 status = "disabled";
71 };
72
73 serial@b2200000 {
74 compatible = "arm,pl011", "arm,primecell";
75 reg = <0xb2200000 0x1000>;
76 status = "disabled";
77 };
78 };
79 };
80};
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
new file mode 100644
index 000000000000..0c6463b71a37
--- /dev/null
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -0,0 +1,173 @@
1/*
2 * DTS file for SPEAr320 Evaluation Baord
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "spear320.dtsi"
16
17/ {
18 model = "ST SPEAr300 Evaluation Board";
19 compatible = "st,spear300-evb", "st,spear300";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 reg = <0 0x40000000>;
25 };
26
27 ahb {
28 pinmux@b3000000 {
29 st,pinmux-mode = <3>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&state_default>;
32
33 state_default: pinmux {
34 i2c0 {
35 st,pins = "i2c0_grp";
36 st,function = "i2c0";
37 };
38 mii0 {
39 st,pins = "mii0_grp";
40 st,function = "mii0";
41 };
42 ssp0 {
43 st,pins = "ssp0_grp";
44 st,function = "ssp0";
45 };
46 uart0 {
47 st,pins = "uart0_grp";
48 st,function = "uart0";
49 };
50 sdhci {
51 st,pins = "sdhci_cd_51_grp";
52 st,function = "sdhci";
53 };
54 i2s {
55 st,pins = "i2s_grp";
56 st,function = "i2s";
57 };
58 uart1 {
59 st,pins = "uart1_grp";
60 st,function = "uart1";
61 };
62 uart2 {
63 st,pins = "uart2_grp";
64 st,function = "uart2";
65 };
66 can0 {
67 st,pins = "can0_grp";
68 st,function = "can0";
69 };
70 can1 {
71 st,pins = "can1_grp";
72 st,function = "can1";
73 };
74 mii2 {
75 st,pins = "mii2_grp";
76 st,function = "mii2";
77 };
78 pwm0_1 {
79 st,pins = "pwm0_1_pin_14_15_grp";
80 st,function = "pwm0_1";
81 };
82 pwm2 {
83 st,pins = "pwm2_pin_13_grp";
84 st,function = "pwm2";
85 };
86 };
87 };
88
89 clcd@90000000 {
90 status = "okay";
91 };
92
93 dma@fc400000 {
94 status = "okay";
95 };
96
97 fsmc: flash@4c000000 {
98 status = "okay";
99 };
100
101 gmac: eth@e0800000 {
102 status = "okay";
103 };
104
105 sdhci@70000000 {
106 power-gpio = <&gpio0 2 1>;
107 power_always_enb;
108 status = "okay";
109 };
110
111 smi: flash@fc000000 {
112 status = "okay";
113 };
114
115 spi0: spi@d0100000 {
116 status = "okay";
117 };
118
119 spi1: spi@a5000000 {
120 status = "okay";
121 };
122
123 spi2: spi@a6000000 {
124 status = "okay";
125 };
126
127 ehci@e1800000 {
128 status = "okay";
129 };
130
131 ohci@e1900000 {
132 status = "okay";
133 };
134
135 ohci@e2100000 {
136 status = "okay";
137 };
138
139 apb {
140 gpio0: gpio@fc980000 {
141 status = "okay";
142 };
143
144 i2c0: i2c@d0180000 {
145 status = "okay";
146 };
147
148 i2c1: i2c@a7000000 {
149 status = "okay";
150 };
151
152 rtc@fc900000 {
153 status = "okay";
154 };
155
156 serial@d0000000 {
157 status = "okay";
158 };
159
160 serial@a3000000 {
161 status = "okay";
162 };
163
164 serial@a4000000 {
165 status = "okay";
166 };
167
168 wdt@fc880000 {
169 status = "okay";
170 };
171 };
172 };
173};
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
new file mode 100644
index 000000000000..5372ca399b1f
--- /dev/null
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -0,0 +1,95 @@
1/*
2 * DTS file for SPEAr320 SoC
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear3xx.dtsi"
15
16/ {
17 ahb {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "simple-bus";
21 ranges = <0x40000000 0x40000000 0x80000000
22 0xd0000000 0xd0000000 0x30000000>;
23
24 pinmux@b3000000 {
25 compatible = "st,spear320-pinmux";
26 reg = <0xb3000000 0x1000>;
27 };
28
29 clcd@90000000 {
30 compatible = "arm,clcd-pl110", "arm,primecell";
31 reg = <0x90000000 0x1000>;
32 interrupts = <33>;
33 status = "disabled";
34 };
35
36 fsmc: flash@4c000000 {
37 compatible = "st,spear600-fsmc-nand";
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x4c000000 0x1000 /* FSMC Register */
41 0x50000000 0x0010>; /* NAND Base */
42 reg-names = "fsmc_regs", "nand_data";
43 st,ale-off = <0x20000>;
44 st,cle-off = <0x10000>;
45 status = "disabled";
46 };
47
48 sdhci@70000000 {
49 compatible = "st,sdhci-spear";
50 reg = <0x70000000 0x100>;
51 interrupts = <29>;
52 status = "disabled";
53 };
54
55 spi1: spi@a5000000 {
56 compatible = "arm,pl022", "arm,primecell";
57 reg = <0xa5000000 0x1000>;
58 status = "disabled";
59 };
60
61 spi2: spi@a6000000 {
62 compatible = "arm,pl022", "arm,primecell";
63 reg = <0xa6000000 0x1000>;
64 status = "disabled";
65 };
66
67 apb {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "simple-bus";
71 ranges = <0xa0000000 0xa0000000 0x10000000
72 0xd0000000 0xd0000000 0x30000000>;
73
74 i2c1: i2c@a7000000 {
75 #address-cells = <1>;
76 #size-cells = <0>;
77 compatible = "snps,designware-i2c";
78 reg = <0xa7000000 0x1000>;
79 status = "disabled";
80 };
81
82 serial@a3000000 {
83 compatible = "arm,pl011", "arm,primecell";
84 reg = <0xa3000000 0x1000>;
85 status = "disabled";
86 };
87
88 serial@a4000000 {
89 compatible = "arm,pl011", "arm,primecell";
90 reg = <0xa4000000 0x1000>;
91 status = "disabled";
92 };
93 };
94 };
95};
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
new file mode 100644
index 000000000000..0ae7c8e86311
--- /dev/null
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -0,0 +1,144 @@
1/*
2 * DTS file for all SPEAr3xx SoCs
3 *
4 * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&vic>;
18
19 cpus {
20 cpu@0 {
21 compatible = "arm,arm926ejs";
22 };
23 };
24
25 memory {
26 device_type = "memory";
27 reg = <0 0x40000000>;
28 };
29
30 ahb {
31 #address-cells = <1>;
32 #size-cells = <1>;
33 compatible = "simple-bus";
34 ranges = <0xd0000000 0xd0000000 0x30000000>;
35
36 vic: interrupt-controller@f1100000 {
37 compatible = "arm,pl190-vic";
38 interrupt-controller;
39 reg = <0xf1100000 0x1000>;
40 #interrupt-cells = <1>;
41 };
42
43 dma@fc400000 {
44 compatible = "arm,pl080", "arm,primecell";
45 reg = <0xfc400000 0x1000>;
46 interrupt-parent = <&vic>;
47 interrupts = <8>;
48 status = "disabled";
49 };
50
51 gmac: eth@e0800000 {
52 compatible = "st,spear600-gmac";
53 reg = <0xe0800000 0x8000>;
54 interrupts = <23 22>;
55 interrupt-names = "macirq", "eth_wake_irq";
56 status = "disabled";
57 };
58
59 smi: flash@fc000000 {
60 compatible = "st,spear600-smi";
61 #address-cells = <1>;
62 #size-cells = <1>;
63 reg = <0xfc000000 0x1000>;
64 interrupts = <9>;
65 status = "disabled";
66 };
67
68 spi0: spi@d0100000 {
69 compatible = "arm,pl022", "arm,primecell";
70 reg = <0xd0100000 0x1000>;
71 interrupts = <20>;
72 status = "disabled";
73 };
74
75 ehci@e1800000 {
76 compatible = "st,spear600-ehci", "usb-ehci";
77 reg = <0xe1800000 0x1000>;
78 interrupts = <26>;
79 status = "disabled";
80 };
81
82 ohci@e1900000 {
83 compatible = "st,spear600-ohci", "usb-ohci";
84 reg = <0xe1900000 0x1000>;
85 interrupts = <25>;
86 status = "disabled";
87 };
88
89 ohci@e2100000 {
90 compatible = "st,spear600-ohci", "usb-ohci";
91 reg = <0xe2100000 0x1000>;
92 interrupts = <27>;
93 status = "disabled";
94 };
95
96 apb {
97 #address-cells = <1>;
98 #size-cells = <1>;
99 compatible = "simple-bus";
100 ranges = <0xd0000000 0xd0000000 0x30000000>;
101
102 gpio0: gpio@fc980000 {
103 compatible = "arm,pl061", "arm,primecell";
104 reg = <0xfc980000 0x1000>;
105 interrupts = <11>;
106 gpio-controller;
107 #gpio-cells = <2>;
108 interrupt-controller;
109 #interrupt-cells = <2>;
110 status = "disabled";
111 };
112
113 i2c0: i2c@d0180000 {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 compatible = "snps,designware-i2c";
117 reg = <0xd0180000 0x1000>;
118 interrupts = <21>;
119 status = "disabled";
120 };
121
122 rtc@fc900000 {
123 compatible = "st,spear-rtc";
124 reg = <0xfc900000 0x1000>;
125 interrupts = <10>;
126 status = "disabled";
127 };
128
129 serial@d0000000 {
130 compatible = "arm,pl011", "arm,primecell";
131 reg = <0xd0000000 0x1000>;
132 interrupts = <19>;
133 status = "disabled";
134 };
135
136 wdt@fc880000 {
137 compatible = "arm,sp805", "arm,primecell";
138 reg = <0xfc880000 0x1000>;
139 interrupts = <12>;
140 status = "disabled";
141 };
142 };
143 };
144};
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
index 636292e18c90..790a7a8a5ccd 100644
--- a/arch/arm/boot/dts/spear600-evb.dts
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -24,6 +24,10 @@
24 }; 24 };
25 25
26 ahb { 26 ahb {
27 dma@fc400000 {
28 status = "okay";
29 };
30
27 gmac: ethernet@e0800000 { 31 gmac: ethernet@e0800000 {
28 phy-mode = "gmii"; 32 phy-mode = "gmii";
29 status = "okay"; 33 status = "okay";
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index ebe0885a2b98..d777e3a6f178 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -45,6 +45,14 @@
45 #interrupt-cells = <1>; 45 #interrupt-cells = <1>;
46 }; 46 };
47 47
48 dma@fc400000 {
49 compatible = "arm,pl080", "arm,primecell";
50 reg = <0xfc400000 0x1000>;
51 interrupt-parent = <&vic1>;
52 interrupts = <10>;
53 status = "disabled";
54 };
55
48 gmac: ethernet@e0800000 { 56 gmac: ethernet@e0800000 {
49 compatible = "st,spear600-gmac"; 57 compatible = "st,spear600-gmac";
50 reg = <0xe0800000 0x8000>; 58 reg = <0xe0800000 0x8000>;
diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig
index fea7e1f026a3..7ed42912d69a 100644
--- a/arch/arm/configs/spear3xx_defconfig
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -2,33 +2,67 @@ CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y 2CONFIG_SYSVIPC=y
3CONFIG_BSD_PROCESS_ACCT=y 3CONFIG_BSD_PROCESS_ACCT=y
4CONFIG_BLK_DEV_INITRD=y 4CONFIG_BLK_DEV_INITRD=y
5CONFIG_KALLSYMS_EXTRA_PASS=y
6CONFIG_MODULES=y 5CONFIG_MODULES=y
7CONFIG_MODULE_UNLOAD=y 6CONFIG_MODULE_UNLOAD=y
8CONFIG_MODVERSIONS=y 7CONFIG_MODVERSIONS=y
8CONFIG_PARTITION_ADVANCED=y
9CONFIG_PLAT_SPEAR=y 9CONFIG_PLAT_SPEAR=y
10CONFIG_BOARD_SPEAR300_EVB=y 10CONFIG_MACH_SPEAR300=y
11CONFIG_BOARD_SPEAR310_EVB=y 11CONFIG_MACH_SPEAR310=y
12CONFIG_BOARD_SPEAR320_EVB=y 12CONFIG_MACH_SPEAR320=y
13CONFIG_BINFMT_MISC=y 13CONFIG_BINFMT_MISC=y
14CONFIG_NET=y
14CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 15CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
16CONFIG_MTD=y
17CONFIG_MTD_NAND=y
18CONFIG_MTD_NAND_FSMC=y
15CONFIG_BLK_DEV_RAM=y 19CONFIG_BLK_DEV_RAM=y
16CONFIG_BLK_DEV_RAM_SIZE=16384 20CONFIG_BLK_DEV_RAM_SIZE=16384
21CONFIG_NETDEVICES=y
22# CONFIG_NET_VENDOR_BROADCOM is not set
23# CONFIG_NET_VENDOR_CIRRUS is not set
24# CONFIG_NET_VENDOR_FARADAY is not set
25# CONFIG_NET_VENDOR_INTEL is not set
26# CONFIG_NET_VENDOR_MICREL is not set
27# CONFIG_NET_VENDOR_NATSEMI is not set
28# CONFIG_NET_VENDOR_SEEQ is not set
29# CONFIG_NET_VENDOR_SMSC is not set
30CONFIG_STMMAC_ETH=y
31# CONFIG_WLAN is not set
17CONFIG_INPUT_FF_MEMLESS=y 32CONFIG_INPUT_FF_MEMLESS=y
18# CONFIG_INPUT_MOUSEDEV_PSAUX is not set 33# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
19# CONFIG_INPUT_KEYBOARD is not set 34# CONFIG_KEYBOARD_ATKBD is not set
35CONFIG_KEYBOARD_SPEAR=y
20# CONFIG_INPUT_MOUSE is not set 36# CONFIG_INPUT_MOUSE is not set
37# CONFIG_LEGACY_PTYS is not set
21CONFIG_SERIAL_AMBA_PL011=y 38CONFIG_SERIAL_AMBA_PL011=y
22CONFIG_SERIAL_AMBA_PL011_CONSOLE=y 39CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
23# CONFIG_LEGACY_PTYS is not set
24# CONFIG_HW_RANDOM is not set 40# CONFIG_HW_RANDOM is not set
25CONFIG_RAW_DRIVER=y 41CONFIG_RAW_DRIVER=y
26CONFIG_MAX_RAW_DEVS=8192 42CONFIG_MAX_RAW_DEVS=8192
43CONFIG_I2C=y
44CONFIG_I2C_DESIGNWARE_PLATFORM=y
45CONFIG_SPI=y
46CONFIG_SPI_PL022=y
27CONFIG_GPIO_SYSFS=y 47CONFIG_GPIO_SYSFS=y
28CONFIG_GPIO_PL061=y 48CONFIG_GPIO_PL061=y
29# CONFIG_HWMON is not set 49# CONFIG_HWMON is not set
50CONFIG_WATCHDOG=y
51CONFIG_ARM_SP805_WATCHDOG=y
52CONFIG_FB=y
53CONFIG_FB_ARMCLCD=y
30# CONFIG_HID_SUPPORT is not set 54# CONFIG_HID_SUPPORT is not set
31# CONFIG_USB_SUPPORT is not set 55CONFIG_USB=y
56# CONFIG_USB_DEVICE_CLASS is not set
57CONFIG_USB_EHCI_HCD=y
58CONFIG_USB_OHCI_HCD=y
59CONFIG_MMC=y
60CONFIG_MMC_SDHCI=y
61CONFIG_MMC_SDHCI_SPEAR=y
62CONFIG_RTC_CLASS=y
63CONFIG_DMADEVICES=y
64CONFIG_AMBA_PL08X=y
65CONFIG_DMATEST=m
32CONFIG_EXT2_FS=y 66CONFIG_EXT2_FS=y
33CONFIG_EXT2_FS_XATTR=y 67CONFIG_EXT2_FS_XATTR=y
34CONFIG_EXT2_FS_SECURITY=y 68CONFIG_EXT2_FS_SECURITY=y
@@ -39,8 +73,6 @@ CONFIG_MSDOS_FS=m
39CONFIG_VFAT_FS=m 73CONFIG_VFAT_FS=m
40CONFIG_FAT_DEFAULT_IOCHARSET="ascii" 74CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
41CONFIG_TMPFS=y 75CONFIG_TMPFS=y
42CONFIG_PARTITION_ADVANCED=y
43CONFIG_NLS=y
44CONFIG_NLS_DEFAULT="utf8" 76CONFIG_NLS_DEFAULT="utf8"
45CONFIG_NLS_CODEPAGE_437=y 77CONFIG_NLS_CODEPAGE_437=y
46CONFIG_NLS_ASCII=m 78CONFIG_NLS_ASCII=m
@@ -48,6 +80,4 @@ CONFIG_MAGIC_SYSRQ=y
48CONFIG_DEBUG_FS=y 80CONFIG_DEBUG_FS=y
49CONFIG_DEBUG_KERNEL=y 81CONFIG_DEBUG_KERNEL=y
50CONFIG_DEBUG_SPINLOCK=y 82CONFIG_DEBUG_SPINLOCK=y
51CONFIG_DEBUG_SPINLOCK_SLEEP=y
52CONFIG_DEBUG_INFO=y 83CONFIG_DEBUG_INFO=y
53# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig
index cef2e836afd2..cf94bc73a0e0 100644
--- a/arch/arm/configs/spear6xx_defconfig
+++ b/arch/arm/configs/spear6xx_defconfig
@@ -2,29 +2,58 @@ CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y 2CONFIG_SYSVIPC=y
3CONFIG_BSD_PROCESS_ACCT=y 3CONFIG_BSD_PROCESS_ACCT=y
4CONFIG_BLK_DEV_INITRD=y 4CONFIG_BLK_DEV_INITRD=y
5CONFIG_KALLSYMS_EXTRA_PASS=y
6CONFIG_MODULES=y 5CONFIG_MODULES=y
7CONFIG_MODULE_UNLOAD=y 6CONFIG_MODULE_UNLOAD=y
8CONFIG_MODVERSIONS=y 7CONFIG_MODVERSIONS=y
8CONFIG_PARTITION_ADVANCED=y
9CONFIG_PLAT_SPEAR=y 9CONFIG_PLAT_SPEAR=y
10CONFIG_ARCH_SPEAR6XX=y 10CONFIG_ARCH_SPEAR6XX=y
11CONFIG_BOARD_SPEAR600_EVB=y 11CONFIG_BOARD_SPEAR600_DT=y
12CONFIG_BINFMT_MISC=y 12CONFIG_BINFMT_MISC=y
13CONFIG_NET=y
13CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 14CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
15CONFIG_MTD=y
16CONFIG_MTD_NAND=y
17CONFIG_MTD_NAND_FSMC=y
14CONFIG_BLK_DEV_RAM=y 18CONFIG_BLK_DEV_RAM=y
15CONFIG_BLK_DEV_RAM_SIZE=16384 19CONFIG_BLK_DEV_RAM_SIZE=16384
20CONFIG_NETDEVICES=y
21# CONFIG_NET_VENDOR_BROADCOM is not set
22# CONFIG_NET_VENDOR_CIRRUS is not set
23# CONFIG_NET_VENDOR_FARADAY is not set
24# CONFIG_NET_VENDOR_INTEL is not set
25# CONFIG_NET_VENDOR_MICREL is not set
26# CONFIG_NET_VENDOR_NATSEMI is not set
27# CONFIG_NET_VENDOR_SEEQ is not set
28# CONFIG_NET_VENDOR_SMSC is not set
29CONFIG_STMMAC_ETH=y
30# CONFIG_WLAN is not set
16CONFIG_INPUT_FF_MEMLESS=y 31CONFIG_INPUT_FF_MEMLESS=y
17# CONFIG_INPUT_MOUSEDEV_PSAUX is not set 32# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
33# CONFIG_INPUT_KEYBOARD is not set
34# CONFIG_INPUT_MOUSE is not set
35# CONFIG_LEGACY_PTYS is not set
18CONFIG_SERIAL_AMBA_PL011=y 36CONFIG_SERIAL_AMBA_PL011=y
19CONFIG_SERIAL_AMBA_PL011_CONSOLE=y 37CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
20# CONFIG_LEGACY_PTYS is not set
21CONFIG_RAW_DRIVER=y 38CONFIG_RAW_DRIVER=y
22CONFIG_MAX_RAW_DEVS=8192 39CONFIG_MAX_RAW_DEVS=8192
40CONFIG_I2C=y
41CONFIG_I2C_DESIGNWARE_PLATFORM=y
42CONFIG_SPI=y
43CONFIG_SPI_PL022=y
23CONFIG_GPIO_SYSFS=y 44CONFIG_GPIO_SYSFS=y
24CONFIG_GPIO_PL061=y 45CONFIG_GPIO_PL061=y
25# CONFIG_HWMON is not set 46# CONFIG_HWMON is not set
47CONFIG_WATCHDOG=y
48CONFIG_ARM_SP805_WATCHDOG=y
26# CONFIG_HID_SUPPORT is not set 49# CONFIG_HID_SUPPORT is not set
27# CONFIG_USB_SUPPORT is not set 50CONFIG_USB=y
51CONFIG_USB_EHCI_HCD=y
52CONFIG_USB_OHCI_HCD=y
53CONFIG_RTC_CLASS=y
54CONFIG_DMADEVICES=y
55CONFIG_AMBA_PL08X=y
56CONFIG_DMATEST=m
28CONFIG_EXT2_FS=y 57CONFIG_EXT2_FS=y
29CONFIG_EXT2_FS_XATTR=y 58CONFIG_EXT2_FS_XATTR=y
30CONFIG_EXT2_FS_SECURITY=y 59CONFIG_EXT2_FS_SECURITY=y
@@ -35,8 +64,6 @@ CONFIG_MSDOS_FS=m
35CONFIG_VFAT_FS=m 64CONFIG_VFAT_FS=m
36CONFIG_FAT_DEFAULT_IOCHARSET="ascii" 65CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
37CONFIG_TMPFS=y 66CONFIG_TMPFS=y
38CONFIG_PARTITION_ADVANCED=y
39CONFIG_NLS=y
40CONFIG_NLS_DEFAULT="utf8" 67CONFIG_NLS_DEFAULT="utf8"
41CONFIG_NLS_CODEPAGE_437=y 68CONFIG_NLS_CODEPAGE_437=y
42CONFIG_NLS_ASCII=m 69CONFIG_NLS_ASCII=m
@@ -44,6 +71,4 @@ CONFIG_MAGIC_SYSRQ=y
44CONFIG_DEBUG_FS=y 71CONFIG_DEBUG_FS=y
45CONFIG_DEBUG_KERNEL=y 72CONFIG_DEBUG_KERNEL=y
46CONFIG_DEBUG_SPINLOCK=y 73CONFIG_DEBUG_SPINLOCK=y
47CONFIG_DEBUG_SPINLOCK_SLEEP=y
48CONFIG_DEBUG_INFO=y 74CONFIG_DEBUG_INFO=y
49# CONFIG_CRC32 is not set
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index 2cee6b0de371..8bd37291fa4f 100644
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -5,39 +5,22 @@
5if ARCH_SPEAR3XX 5if ARCH_SPEAR3XX
6 6
7menu "SPEAr3xx Implementations" 7menu "SPEAr3xx Implementations"
8config BOARD_SPEAR300_EVB
9 bool "SPEAr300 Evaluation Board"
10 select MACH_SPEAR300
11 help
12 Supports ST SPEAr300 Evaluation Board
13
14config BOARD_SPEAR310_EVB
15 bool "SPEAr310 Evaluation Board"
16 select MACH_SPEAR310
17 help
18 Supports ST SPEAr310 Evaluation Board
19
20config BOARD_SPEAR320_EVB
21 bool "SPEAr320 Evaluation Board"
22 select MACH_SPEAR320
23 help
24 Supports ST SPEAr320 Evaluation Board
25
26endmenu
27
28config MACH_SPEAR300 8config MACH_SPEAR300
29 bool "SPEAr300" 9 bool "SPEAr300 Machine support with Device Tree"
10 select PINCTRL_SPEAR300
30 help 11 help
31 Supports ST SPEAr300 Machine 12 Supports ST SPEAr300 machine configured via the device-tree
32 13
33config MACH_SPEAR310 14config MACH_SPEAR310
34 bool "SPEAr310" 15 bool "SPEAr310 Machine support with Device Tree"
16 select PINCTRL_SPEAR310
35 help 17 help
36 Supports ST SPEAr310 Machine 18 Supports ST SPEAr310 machine configured via the device-tree
37 19
38config MACH_SPEAR320 20config MACH_SPEAR320
39 bool "SPEAr320" 21 bool "SPEAr320 Machine support with Device Tree"
22 select PINCTRL_SPEAR320
40 help 23 help
41 Supports ST SPEAr320 Machine 24 Supports ST SPEAr320 machine configured via the device-tree
42 25endmenu
43endif #ARCH_SPEAR3XX 26endif #ARCH_SPEAR3XX
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
index 5b30d0d10892..8d12faa178fd 100644
--- a/arch/arm/mach-spear3xx/Makefile
+++ b/arch/arm/mach-spear3xx/Makefile
@@ -3,24 +3,13 @@
3# 3#
4 4
5# common files 5# common files
6obj-y += spear3xx.o 6obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o
7 7
8# spear300 specific files 8# spear300 specific files
9obj-$(CONFIG_MACH_SPEAR300) += spear300.o 9obj-$(CONFIG_MACH_SPEAR300) += spear300.o
10 10
11# spear300 boards files
12obj-$(CONFIG_BOARD_SPEAR300_EVB) += spear300_evb.o
13
14
15# spear310 specific files 11# spear310 specific files
16obj-$(CONFIG_MACH_SPEAR310) += spear310.o 12obj-$(CONFIG_MACH_SPEAR310) += spear310.o
17 13
18# spear310 boards files
19obj-$(CONFIG_BOARD_SPEAR310_EVB) += spear310_evb.o
20
21
22# spear320 specific files 14# spear320 specific files
23obj-$(CONFIG_MACH_SPEAR320) += spear320.o 15obj-$(CONFIG_MACH_SPEAR320) += spear320.o
24
25# spear320 boards files
26obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o
diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot
index 4674a4c221db..d93e2177e6ec 100644
--- a/arch/arm/mach-spear3xx/Makefile.boot
+++ b/arch/arm/mach-spear3xx/Makefile.boot
@@ -1,3 +1,7 @@
1zreladdr-y += 0x00008000 1zreladdr-y += 0x00008000
2params_phys-y := 0x00000100 2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000 3initrd_phys-y := 0x00800000
4
5dtb-$(CONFIG_MACH_SPEAR300) += spear300-evb.dtb
6dtb-$(CONFIG_MACH_SPEAR310) += spear310-evb.dtb
7dtb-$(CONFIG_MACH_SPEAR320) += spear320-evb.dtb
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 15c107aad202..c10eac6c10cb 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -14,12 +14,12 @@
14#ifndef __MACH_GENERIC_H 14#ifndef __MACH_GENERIC_H
15#define __MACH_GENERIC_H 15#define __MACH_GENERIC_H
16 16
17#include <linux/amba/pl08x.h>
17#include <linux/init.h> 18#include <linux/init.h>
18#include <linux/platform_device.h> 19#include <linux/platform_device.h>
19#include <linux/amba/bus.h> 20#include <linux/amba/bus.h>
20#include <asm/mach/time.h> 21#include <asm/mach/time.h>
21#include <asm/mach/map.h> 22#include <asm/mach/map.h>
22#include <plat/padmux.h>
23 23
24/* spear3xx declarations */ 24/* spear3xx declarations */
25/* 25/*
@@ -31,171 +31,16 @@
31#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2 31#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2
32 32
33/* Add spear3xx family device structure declarations here */ 33/* Add spear3xx family device structure declarations here */
34extern struct amba_device spear3xx_gpio_device;
35extern struct amba_device spear3xx_uart_device;
36extern struct sys_timer spear3xx_timer; 34extern struct sys_timer spear3xx_timer;
35extern struct pl022_ssp_controller pl022_plat_data;
36extern struct pl08x_platform_data pl080_plat_data;
37 37
38/* Add spear3xx family function declarations here */ 38/* Add spear3xx family function declarations here */
39void __init spear_setup_timer(void); 39void __init spear_setup_timer(void);
40void __init spear3xx_clk_init(void); 40void __init spear3xx_clk_init(void);
41void __init spear3xx_map_io(void); 41void __init spear3xx_map_io(void);
42void __init spear3xx_init_irq(void); 42void __init spear3xx_dt_init_irq(void);
43void __init spear3xx_init(void);
44 43
45void spear_restart(char, const char *); 44void spear_restart(char, const char *);
46 45
47/* pad mux declarations */
48#define PMX_FIRDA_MASK (1 << 14)
49#define PMX_I2C_MASK (1 << 13)
50#define PMX_SSP_CS_MASK (1 << 12)
51#define PMX_SSP_MASK (1 << 11)
52#define PMX_MII_MASK (1 << 10)
53#define PMX_GPIO_PIN0_MASK (1 << 9)
54#define PMX_GPIO_PIN1_MASK (1 << 8)
55#define PMX_GPIO_PIN2_MASK (1 << 7)
56#define PMX_GPIO_PIN3_MASK (1 << 6)
57#define PMX_GPIO_PIN4_MASK (1 << 5)
58#define PMX_GPIO_PIN5_MASK (1 << 4)
59#define PMX_UART0_MODEM_MASK (1 << 3)
60#define PMX_UART0_MASK (1 << 2)
61#define PMX_TIMER_3_4_MASK (1 << 1)
62#define PMX_TIMER_1_2_MASK (1 << 0)
63
64/* pad mux devices */
65extern struct pmx_dev spear3xx_pmx_firda;
66extern struct pmx_dev spear3xx_pmx_i2c;
67extern struct pmx_dev spear3xx_pmx_ssp_cs;
68extern struct pmx_dev spear3xx_pmx_ssp;
69extern struct pmx_dev spear3xx_pmx_mii;
70extern struct pmx_dev spear3xx_pmx_gpio_pin0;
71extern struct pmx_dev spear3xx_pmx_gpio_pin1;
72extern struct pmx_dev spear3xx_pmx_gpio_pin2;
73extern struct pmx_dev spear3xx_pmx_gpio_pin3;
74extern struct pmx_dev spear3xx_pmx_gpio_pin4;
75extern struct pmx_dev spear3xx_pmx_gpio_pin5;
76extern struct pmx_dev spear3xx_pmx_uart0_modem;
77extern struct pmx_dev spear3xx_pmx_uart0;
78extern struct pmx_dev spear3xx_pmx_timer_3_4;
79extern struct pmx_dev spear3xx_pmx_timer_1_2;
80
81#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
82/* padmux plgpio devices */
83extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
84extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
85extern struct pmx_dev spear3xx_pmx_plgpio_4_5;
86extern struct pmx_dev spear3xx_pmx_plgpio_6_9;
87extern struct pmx_dev spear3xx_pmx_plgpio_10_27;
88extern struct pmx_dev spear3xx_pmx_plgpio_28;
89extern struct pmx_dev spear3xx_pmx_plgpio_29;
90extern struct pmx_dev spear3xx_pmx_plgpio_30;
91extern struct pmx_dev spear3xx_pmx_plgpio_31;
92extern struct pmx_dev spear3xx_pmx_plgpio_32;
93extern struct pmx_dev spear3xx_pmx_plgpio_33;
94extern struct pmx_dev spear3xx_pmx_plgpio_34_36;
95extern struct pmx_dev spear3xx_pmx_plgpio_37_42;
96extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48;
97extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
98#endif
99
100/* spear300 declarations */
101#ifdef CONFIG_MACH_SPEAR300
102/* Add spear300 machine device structure declarations here */
103extern struct amba_device spear300_gpio1_device;
104
105/* pad mux modes */
106extern struct pmx_mode spear300_nand_mode;
107extern struct pmx_mode spear300_nor_mode;
108extern struct pmx_mode spear300_photo_frame_mode;
109extern struct pmx_mode spear300_lend_ip_phone_mode;
110extern struct pmx_mode spear300_hend_ip_phone_mode;
111extern struct pmx_mode spear300_lend_wifi_phone_mode;
112extern struct pmx_mode spear300_hend_wifi_phone_mode;
113extern struct pmx_mode spear300_ata_pabx_wi2s_mode;
114extern struct pmx_mode spear300_ata_pabx_i2s_mode;
115extern struct pmx_mode spear300_caml_lcdw_mode;
116extern struct pmx_mode spear300_camu_lcd_mode;
117extern struct pmx_mode spear300_camu_wlcd_mode;
118extern struct pmx_mode spear300_caml_lcd_mode;
119
120/* pad mux devices */
121extern struct pmx_dev spear300_pmx_fsmc_2_chips;
122extern struct pmx_dev spear300_pmx_fsmc_4_chips;
123extern struct pmx_dev spear300_pmx_keyboard;
124extern struct pmx_dev spear300_pmx_clcd;
125extern struct pmx_dev spear300_pmx_telecom_gpio;
126extern struct pmx_dev spear300_pmx_telecom_tdm;
127extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk;
128extern struct pmx_dev spear300_pmx_telecom_camera;
129extern struct pmx_dev spear300_pmx_telecom_dac;
130extern struct pmx_dev spear300_pmx_telecom_i2s;
131extern struct pmx_dev spear300_pmx_telecom_boot_pins;
132extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
133extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
134extern struct pmx_dev spear300_pmx_gpio1;
135
136/* Add spear300 machine function declarations here */
137void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
138 u8 pmx_dev_count);
139
140#endif /* CONFIG_MACH_SPEAR300 */
141
142/* spear310 declarations */
143#ifdef CONFIG_MACH_SPEAR310
144/* Add spear310 machine device structure declarations here */
145
146/* pad mux devices */
147extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
148extern struct pmx_dev spear310_pmx_emi_cs_2_3;
149extern struct pmx_dev spear310_pmx_uart1;
150extern struct pmx_dev spear310_pmx_uart2;
151extern struct pmx_dev spear310_pmx_uart3_4_5;
152extern struct pmx_dev spear310_pmx_fsmc;
153extern struct pmx_dev spear310_pmx_rs485_0_1;
154extern struct pmx_dev spear310_pmx_tdm0;
155
156/* Add spear310 machine function declarations here */
157void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
158 u8 pmx_dev_count);
159#endif /* CONFIG_MACH_SPEAR310 */
160
161/* spear320 declarations */
162#ifdef CONFIG_MACH_SPEAR320
163/* Add spear320 machine device structure declarations here */
164
165/* pad mux modes */
166extern struct pmx_mode spear320_auto_net_smii_mode;
167extern struct pmx_mode spear320_auto_net_mii_mode;
168extern struct pmx_mode spear320_auto_exp_mode;
169extern struct pmx_mode spear320_small_printers_mode;
170
171/* pad mux devices */
172extern struct pmx_dev spear320_pmx_clcd;
173extern struct pmx_dev spear320_pmx_emi;
174extern struct pmx_dev spear320_pmx_fsmc;
175extern struct pmx_dev spear320_pmx_spp;
176extern struct pmx_dev spear320_pmx_sdhci;
177extern struct pmx_dev spear320_pmx_i2s;
178extern struct pmx_dev spear320_pmx_uart1;
179extern struct pmx_dev spear320_pmx_uart1_modem;
180extern struct pmx_dev spear320_pmx_uart2;
181extern struct pmx_dev spear320_pmx_touchscreen;
182extern struct pmx_dev spear320_pmx_can;
183extern struct pmx_dev spear320_pmx_sdhci_led;
184extern struct pmx_dev spear320_pmx_pwm0;
185extern struct pmx_dev spear320_pmx_pwm1;
186extern struct pmx_dev spear320_pmx_pwm2;
187extern struct pmx_dev spear320_pmx_pwm3;
188extern struct pmx_dev spear320_pmx_ssp1;
189extern struct pmx_dev spear320_pmx_ssp2;
190extern struct pmx_dev spear320_pmx_mii1;
191extern struct pmx_dev spear320_pmx_smii0;
192extern struct pmx_dev spear320_pmx_smii1;
193extern struct pmx_dev spear320_pmx_i2c1;
194
195/* Add spear320 machine function declarations here */
196void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
197 u8 pmx_dev_count);
198
199#endif /* CONFIG_MACH_SPEAR320 */
200
201#endif /* __MACH_GENERIC_H */ 46#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h
index 4660c0d8ec0d..defa374f5bee 100644
--- a/arch/arm/mach-spear3xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear3xx/include/mach/hardware.h
@@ -17,7 +17,4 @@
17#include <plat/hardware.h> 17#include <plat/hardware.h>
18#include <mach/spear.h> 18#include <mach/spear.h>
19 19
20/* Vitual to physical translation of statically mapped space */
21#define IO_ADDRESS(x) (x | 0xF0000000)
22
23#endif /* __MACH_HARDWARE_H */ 20#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index 881109522060..e7bc8bab83fe 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -25,8 +25,9 @@
25 25
26/* ICM1 - Low speed connection */ 26/* ICM1 - Low speed connection */
27#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000) 27#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000)
28#define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000)
28#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000) 29#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000)
29#define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE) 30#define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
30#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000) 31#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000)
31#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) 32#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
32#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000) 33#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000)
@@ -53,11 +54,11 @@
53#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000) 54#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000)
54#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000) 55#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000)
55#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000) 56#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000)
56#define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
57 57
58/* ICM3 - Basic Subsystem */ 58/* ICM3 - Basic Subsystem */
59#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000) 59#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000)
60#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) 60#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
61#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
61#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000) 62#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000)
62#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000) 63#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
63#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000) 64#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000)
@@ -65,9 +66,9 @@
65#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000) 66#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000)
66#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000) 67#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000)
67#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) 68#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
68#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE) 69#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
69#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000) 70#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
70#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE) 71#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
71#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000) 72#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000)
72 73
73/* Debug uart for linux, will be used for debug and uncompress messages */ 74/* Debug uart for linux, will be used for debug and uncompress messages */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index f7db66812abb..2db0bd14e481 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -3,373 +3,24 @@
3 * 3 *
4 * SPEAr300 machine source file 4 * SPEAr300 machine source file
5 * 5 *
6 * Copyright (C) 2009 ST Microelectronics 6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com> 7 * Viresh Kumar <viresh.kumar@st.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14#include <linux/types.h> 14#define pr_fmt(fmt) "SPEAr300: " fmt
15#include <linux/amba/pl061.h> 15
16#include <linux/ptrace.h> 16#include <linux/amba/pl08x.h>
17#include <asm/irq.h> 17#include <linux/of_platform.h>
18#include <asm/hardware/vic.h>
19#include <asm/mach/arch.h>
18#include <plat/shirq.h> 20#include <plat/shirq.h>
19#include <mach/generic.h> 21#include <mach/generic.h>
20#include <mach/hardware.h> 22#include <mach/hardware.h>
21 23
22/* pad multiplexing support */
23/* muxing registers */
24#define PAD_MUX_CONFIG_REG 0x00
25#define MODE_CONFIG_REG 0x04
26
27/* modes */
28#define NAND_MODE (1 << 0)
29#define NOR_MODE (1 << 1)
30#define PHOTO_FRAME_MODE (1 << 2)
31#define LEND_IP_PHONE_MODE (1 << 3)
32#define HEND_IP_PHONE_MODE (1 << 4)
33#define LEND_WIFI_PHONE_MODE (1 << 5)
34#define HEND_WIFI_PHONE_MODE (1 << 6)
35#define ATA_PABX_WI2S_MODE (1 << 7)
36#define ATA_PABX_I2S_MODE (1 << 8)
37#define CAML_LCDW_MODE (1 << 9)
38#define CAMU_LCD_MODE (1 << 10)
39#define CAMU_WLCD_MODE (1 << 11)
40#define CAML_LCD_MODE (1 << 12)
41#define ALL_MODES 0x1FFF
42
43struct pmx_mode spear300_nand_mode = {
44 .id = NAND_MODE,
45 .name = "nand mode",
46 .mask = 0x00,
47};
48
49struct pmx_mode spear300_nor_mode = {
50 .id = NOR_MODE,
51 .name = "nor mode",
52 .mask = 0x01,
53};
54
55struct pmx_mode spear300_photo_frame_mode = {
56 .id = PHOTO_FRAME_MODE,
57 .name = "photo frame mode",
58 .mask = 0x02,
59};
60
61struct pmx_mode spear300_lend_ip_phone_mode = {
62 .id = LEND_IP_PHONE_MODE,
63 .name = "lend ip phone mode",
64 .mask = 0x03,
65};
66
67struct pmx_mode spear300_hend_ip_phone_mode = {
68 .id = HEND_IP_PHONE_MODE,
69 .name = "hend ip phone mode",
70 .mask = 0x04,
71};
72
73struct pmx_mode spear300_lend_wifi_phone_mode = {
74 .id = LEND_WIFI_PHONE_MODE,
75 .name = "lend wifi phone mode",
76 .mask = 0x05,
77};
78
79struct pmx_mode spear300_hend_wifi_phone_mode = {
80 .id = HEND_WIFI_PHONE_MODE,
81 .name = "hend wifi phone mode",
82 .mask = 0x06,
83};
84
85struct pmx_mode spear300_ata_pabx_wi2s_mode = {
86 .id = ATA_PABX_WI2S_MODE,
87 .name = "ata pabx wi2s mode",
88 .mask = 0x07,
89};
90
91struct pmx_mode spear300_ata_pabx_i2s_mode = {
92 .id = ATA_PABX_I2S_MODE,
93 .name = "ata pabx i2s mode",
94 .mask = 0x08,
95};
96
97struct pmx_mode spear300_caml_lcdw_mode = {
98 .id = CAML_LCDW_MODE,
99 .name = "caml lcdw mode",
100 .mask = 0x0C,
101};
102
103struct pmx_mode spear300_camu_lcd_mode = {
104 .id = CAMU_LCD_MODE,
105 .name = "camu lcd mode",
106 .mask = 0x0D,
107};
108
109struct pmx_mode spear300_camu_wlcd_mode = {
110 .id = CAMU_WLCD_MODE,
111 .name = "camu wlcd mode",
112 .mask = 0x0E,
113};
114
115struct pmx_mode spear300_caml_lcd_mode = {
116 .id = CAML_LCD_MODE,
117 .name = "caml lcd mode",
118 .mask = 0x0F,
119};
120
121/* devices */
122static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
123 {
124 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
125 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
126 .mask = PMX_FIRDA_MASK,
127 },
128};
129
130struct pmx_dev spear300_pmx_fsmc_2_chips = {
131 .name = "fsmc_2_chips",
132 .modes = pmx_fsmc_2_chips_modes,
133 .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
134 .enb_on_reset = 1,
135};
136
137static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
138 {
139 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
140 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
141 .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
142 },
143};
144
145struct pmx_dev spear300_pmx_fsmc_4_chips = {
146 .name = "fsmc_4_chips",
147 .modes = pmx_fsmc_4_chips_modes,
148 .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
149 .enb_on_reset = 1,
150};
151
152static struct pmx_dev_mode pmx_keyboard_modes[] = {
153 {
154 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
155 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
156 CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE |
157 CAML_LCD_MODE,
158 .mask = 0x0,
159 },
160};
161
162struct pmx_dev spear300_pmx_keyboard = {
163 .name = "keyboard",
164 .modes = pmx_keyboard_modes,
165 .mode_count = ARRAY_SIZE(pmx_keyboard_modes),
166 .enb_on_reset = 1,
167};
168
169static struct pmx_dev_mode pmx_clcd_modes[] = {
170 {
171 .ids = PHOTO_FRAME_MODE,
172 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
173 }, {
174 .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
175 CAMU_LCD_MODE | CAML_LCD_MODE,
176 .mask = PMX_TIMER_3_4_MASK,
177 },
178};
179
180struct pmx_dev spear300_pmx_clcd = {
181 .name = "clcd",
182 .modes = pmx_clcd_modes,
183 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
184 .enb_on_reset = 1,
185};
186
187static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
188 {
189 .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
190 .mask = PMX_MII_MASK,
191 }, {
192 .ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE,
193 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
194 }, {
195 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE,
196 .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
197 }, {
198 .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE,
199 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
200 }, {
201 .ids = ATA_PABX_WI2S_MODE,
202 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
203 | PMX_UART0_MODEM_MASK,
204 },
205};
206
207struct pmx_dev spear300_pmx_telecom_gpio = {
208 .name = "telecom_gpio",
209 .modes = pmx_telecom_gpio_modes,
210 .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
211 .enb_on_reset = 1,
212};
213
214static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
215 {
216 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
217 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
218 | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
219 | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
220 | CAMU_WLCD_MODE | CAML_LCD_MODE,
221 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
222 },
223};
224
225struct pmx_dev spear300_pmx_telecom_tdm = {
226 .name = "telecom_tdm",
227 .modes = pmx_telecom_tdm_modes,
228 .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
229 .enb_on_reset = 1,
230};
231
232static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
233 {
234 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
235 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
236 | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE |
237 CAML_LCDW_MODE | CAML_LCD_MODE,
238 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
239 },
240};
241
242struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
243 .name = "telecom_spi_cs_i2c_clk",
244 .modes = pmx_telecom_spi_cs_i2c_clk_modes,
245 .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
246 .enb_on_reset = 1,
247};
248
249static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
250 {
251 .ids = CAML_LCDW_MODE | CAML_LCD_MODE,
252 .mask = PMX_MII_MASK,
253 }, {
254 .ids = CAMU_LCD_MODE | CAMU_WLCD_MODE,
255 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
256 },
257};
258
259struct pmx_dev spear300_pmx_telecom_camera = {
260 .name = "telecom_camera",
261 .modes = pmx_telecom_camera_modes,
262 .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
263 .enb_on_reset = 1,
264};
265
266static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
267 {
268 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
269 | CAMU_WLCD_MODE | CAML_LCD_MODE,
270 .mask = PMX_TIMER_1_2_MASK,
271 },
272};
273
274struct pmx_dev spear300_pmx_telecom_dac = {
275 .name = "telecom_dac",
276 .modes = pmx_telecom_dac_modes,
277 .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
278 .enb_on_reset = 1,
279};
280
281static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
282 {
283 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
284 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
285 ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
286 | CAMU_WLCD_MODE | CAML_LCD_MODE,
287 .mask = PMX_UART0_MODEM_MASK,
288 },
289};
290
291struct pmx_dev spear300_pmx_telecom_i2s = {
292 .name = "telecom_i2s",
293 .modes = pmx_telecom_i2s_modes,
294 .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
295 .enb_on_reset = 1,
296};
297
298static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
299 {
300 .ids = NAND_MODE | NOR_MODE,
301 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
302 PMX_TIMER_3_4_MASK,
303 },
304};
305
306struct pmx_dev spear300_pmx_telecom_boot_pins = {
307 .name = "telecom_boot_pins",
308 .modes = pmx_telecom_boot_pins_modes,
309 .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
310 .enb_on_reset = 1,
311};
312
313static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
314 {
315 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
316 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
317 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
318 CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE |
319 ATA_PABX_I2S_MODE,
320 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
321 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
322 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
323 },
324};
325
326struct pmx_dev spear300_pmx_telecom_sdhci_4bit = {
327 .name = "telecom_sdhci_4bit",
328 .modes = pmx_telecom_sdhci_4bit_modes,
329 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
330 .enb_on_reset = 1,
331};
332
333static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
334 {
335 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
336 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
337 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
338 CAMU_WLCD_MODE | CAML_LCD_MODE,
339 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
340 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
341 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
342 },
343};
344
345struct pmx_dev spear300_pmx_telecom_sdhci_8bit = {
346 .name = "telecom_sdhci_8bit",
347 .modes = pmx_telecom_sdhci_8bit_modes,
348 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
349 .enb_on_reset = 1,
350};
351
352static struct pmx_dev_mode pmx_gpio1_modes[] = {
353 {
354 .ids = PHOTO_FRAME_MODE,
355 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
356 PMX_TIMER_3_4_MASK,
357 },
358};
359
360struct pmx_dev spear300_pmx_gpio1 = {
361 .name = "arm gpio1",
362 .modes = pmx_gpio1_modes,
363 .mode_count = ARRAY_SIZE(pmx_gpio1_modes),
364 .enb_on_reset = 1,
365};
366
367/* pmx driver structure */
368static struct pmx_driver pmx_driver = {
369 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
370 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
371};
372
373/* spear3xx shared irq */ 24/* spear3xx shared irq */
374static struct shirq_dev_config shirq_ras1_config[] = { 25static struct shirq_dev_config shirq_ras1_config[] = {
375 { 26 {
@@ -423,45 +74,239 @@ static struct spear_shirq shirq_ras1 = {
423 }, 74 },
424}; 75};
425 76
426/* Add spear300 specific devices here */ 77/* DMAC platform data's slave info */
427/* arm gpio1 device registration */ 78struct pl08x_channel_data spear300_dma_info[] = {
428static struct pl061_platform_data gpio1_plat_data = { 79 {
429 .gpio_base = 8, 80 .bus_id = "uart0_rx",
430 .irq_base = SPEAR300_GPIO1_INT_BASE, 81 .min_signal = 2,
82 .max_signal = 2,
83 .muxval = 0,
84 .cctl = 0,
85 .periph_buses = PL08X_AHB1,
86 }, {
87 .bus_id = "uart0_tx",
88 .min_signal = 3,
89 .max_signal = 3,
90 .muxval = 0,
91 .cctl = 0,
92 .periph_buses = PL08X_AHB1,
93 }, {
94 .bus_id = "ssp0_rx",
95 .min_signal = 8,
96 .max_signal = 8,
97 .muxval = 0,
98 .cctl = 0,
99 .periph_buses = PL08X_AHB1,
100 }, {
101 .bus_id = "ssp0_tx",
102 .min_signal = 9,
103 .max_signal = 9,
104 .muxval = 0,
105 .cctl = 0,
106 .periph_buses = PL08X_AHB1,
107 }, {
108 .bus_id = "i2c_rx",
109 .min_signal = 10,
110 .max_signal = 10,
111 .muxval = 0,
112 .cctl = 0,
113 .periph_buses = PL08X_AHB1,
114 }, {
115 .bus_id = "i2c_tx",
116 .min_signal = 11,
117 .max_signal = 11,
118 .muxval = 0,
119 .cctl = 0,
120 .periph_buses = PL08X_AHB1,
121 }, {
122 .bus_id = "irda",
123 .min_signal = 12,
124 .max_signal = 12,
125 .muxval = 0,
126 .cctl = 0,
127 .periph_buses = PL08X_AHB1,
128 }, {
129 .bus_id = "adc",
130 .min_signal = 13,
131 .max_signal = 13,
132 .muxval = 0,
133 .cctl = 0,
134 .periph_buses = PL08X_AHB1,
135 }, {
136 .bus_id = "to_jpeg",
137 .min_signal = 14,
138 .max_signal = 14,
139 .muxval = 0,
140 .cctl = 0,
141 .periph_buses = PL08X_AHB1,
142 }, {
143 .bus_id = "from_jpeg",
144 .min_signal = 15,
145 .max_signal = 15,
146 .muxval = 0,
147 .cctl = 0,
148 .periph_buses = PL08X_AHB1,
149 }, {
150 .bus_id = "ras0_rx",
151 .min_signal = 0,
152 .max_signal = 0,
153 .muxval = 1,
154 .cctl = 0,
155 .periph_buses = PL08X_AHB1,
156 }, {
157 .bus_id = "ras0_tx",
158 .min_signal = 1,
159 .max_signal = 1,
160 .muxval = 1,
161 .cctl = 0,
162 .periph_buses = PL08X_AHB1,
163 }, {
164 .bus_id = "ras1_rx",
165 .min_signal = 2,
166 .max_signal = 2,
167 .muxval = 1,
168 .cctl = 0,
169 .periph_buses = PL08X_AHB1,
170 }, {
171 .bus_id = "ras1_tx",
172 .min_signal = 3,
173 .max_signal = 3,
174 .muxval = 1,
175 .cctl = 0,
176 .periph_buses = PL08X_AHB1,
177 }, {
178 .bus_id = "ras2_rx",
179 .min_signal = 4,
180 .max_signal = 4,
181 .muxval = 1,
182 .cctl = 0,
183 .periph_buses = PL08X_AHB1,
184 }, {
185 .bus_id = "ras2_tx",
186 .min_signal = 5,
187 .max_signal = 5,
188 .muxval = 1,
189 .cctl = 0,
190 .periph_buses = PL08X_AHB1,
191 }, {
192 .bus_id = "ras3_rx",
193 .min_signal = 6,
194 .max_signal = 6,
195 .muxval = 1,
196 .cctl = 0,
197 .periph_buses = PL08X_AHB1,
198 }, {
199 .bus_id = "ras3_tx",
200 .min_signal = 7,
201 .max_signal = 7,
202 .muxval = 1,
203 .cctl = 0,
204 .periph_buses = PL08X_AHB1,
205 }, {
206 .bus_id = "ras4_rx",
207 .min_signal = 8,
208 .max_signal = 8,
209 .muxval = 1,
210 .cctl = 0,
211 .periph_buses = PL08X_AHB1,
212 }, {
213 .bus_id = "ras4_tx",
214 .min_signal = 9,
215 .max_signal = 9,
216 .muxval = 1,
217 .cctl = 0,
218 .periph_buses = PL08X_AHB1,
219 }, {
220 .bus_id = "ras5_rx",
221 .min_signal = 10,
222 .max_signal = 10,
223 .muxval = 1,
224 .cctl = 0,
225 .periph_buses = PL08X_AHB1,
226 }, {
227 .bus_id = "ras5_tx",
228 .min_signal = 11,
229 .max_signal = 11,
230 .muxval = 1,
231 .cctl = 0,
232 .periph_buses = PL08X_AHB1,
233 }, {
234 .bus_id = "ras6_rx",
235 .min_signal = 12,
236 .max_signal = 12,
237 .muxval = 1,
238 .cctl = 0,
239 .periph_buses = PL08X_AHB1,
240 }, {
241 .bus_id = "ras6_tx",
242 .min_signal = 13,
243 .max_signal = 13,
244 .muxval = 1,
245 .cctl = 0,
246 .periph_buses = PL08X_AHB1,
247 }, {
248 .bus_id = "ras7_rx",
249 .min_signal = 14,
250 .max_signal = 14,
251 .muxval = 1,
252 .cctl = 0,
253 .periph_buses = PL08X_AHB1,
254 }, {
255 .bus_id = "ras7_tx",
256 .min_signal = 15,
257 .max_signal = 15,
258 .muxval = 1,
259 .cctl = 0,
260 .periph_buses = PL08X_AHB1,
261 },
431}; 262};
432 263
433AMBA_APB_DEVICE(spear300_gpio1, "gpio1", 0, SPEAR300_GPIO_BASE, 264/* Add SPEAr300 auxdata to pass platform data */
434 {SPEAR300_VIRQ_GPIO1}, &gpio1_plat_data); 265static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
266 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
267 &pl022_plat_data),
268 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
269 &pl080_plat_data),
270 {}
271};
435 272
436/* spear300 routines */ 273static void __init spear300_dt_init(void)
437void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
438 u8 pmx_dev_count)
439{ 274{
440 int ret = 0; 275 int ret;
276
277 pl080_plat_data.slave_channels = spear300_dma_info;
278 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
441 279
442 /* call spear3xx family common init function */ 280 of_platform_populate(NULL, of_default_bus_match_table,
443 spear3xx_init(); 281 spear300_auxdata_lookup, NULL);
444 282
445 /* shared irq registration */ 283 /* shared irq registration */
446 shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K); 284 shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
447 if (shirq_ras1.regs.base) { 285 if (shirq_ras1.regs.base) {
448 ret = spear_shirq_register(&shirq_ras1); 286 ret = spear_shirq_register(&shirq_ras1);
449 if (ret) 287 if (ret)
450 printk(KERN_ERR "Error registering Shared IRQ\n"); 288 pr_err("Error registering Shared IRQ\n");
451 } 289 }
290}
452 291
453 /* pmx initialization */ 292static const char * const spear300_dt_board_compat[] = {
454 pmx_driver.mode = pmx_mode; 293 "st,spear300",
455 pmx_driver.devs = pmx_devs; 294 "st,spear300-evb",
456 pmx_driver.devs_count = pmx_dev_count; 295 NULL,
296};
457 297
458 pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K); 298static void __init spear300_map_io(void)
459 if (pmx_driver.base) { 299{
460 ret = pmx_register(&pmx_driver); 300 spear3xx_map_io();
461 if (ret) 301 spear300_clk_init();
462 printk(KERN_ERR "padmux: registration failed. err no"
463 ": %d\n", ret);
464 /* Free Mapping, device selection already done */
465 iounmap(pmx_driver.base);
466 }
467} 302}
303
304DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
305 .map_io = spear300_map_io,
306 .init_irq = spear3xx_dt_init_irq,
307 .handle_irq = vic_handle_irq,
308 .timer = &spear3xx_timer,
309 .init_machine = spear300_dt_init,
310 .restart = spear_restart,
311 .dt_compat = spear300_dt_board_compat,
312MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
deleted file mode 100644
index 3462ab9d6122..000000000000
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/spear300_evb.c
3 *
4 * SPEAr300 evaluation board source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <asm/hardware/vic.h>
15#include <asm/mach/arch.h>
16#include <asm/mach-types.h>
17#include <mach/generic.h>
18#include <mach/hardware.h>
19
20/* padmux devices to enable */
21static struct pmx_dev *pmx_devs[] = {
22 /* spear3xx specific devices */
23 &spear3xx_pmx_i2c,
24 &spear3xx_pmx_ssp_cs,
25 &spear3xx_pmx_ssp,
26 &spear3xx_pmx_mii,
27 &spear3xx_pmx_uart0,
28
29 /* spear300 specific devices */
30 &spear300_pmx_fsmc_2_chips,
31 &spear300_pmx_clcd,
32 &spear300_pmx_telecom_sdhci_4bit,
33 &spear300_pmx_gpio1,
34};
35
36static struct amba_device *amba_devs[] __initdata = {
37 /* spear3xx specific devices */
38 &spear3xx_gpio_device,
39 &spear3xx_uart_device,
40
41 /* spear300 specific devices */
42 &spear300_gpio1_device,
43};
44
45static struct platform_device *plat_devs[] __initdata = {
46 /* spear3xx specific devices */
47
48 /* spear300 specific devices */
49};
50
51static void __init spear300_evb_init(void)
52{
53 unsigned int i;
54
55 /* call spear300 machine init function */
56 spear300_init(&spear300_photo_frame_mode, pmx_devs,
57 ARRAY_SIZE(pmx_devs));
58
59 /* Add Platform Devices */
60 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
61
62 /* Add Amba Devices */
63 for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
64 amba_device_register(amba_devs[i], &iomem_resource);
65}
66
67MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
68 .atag_offset = 0x100,
69 .map_io = spear3xx_map_io,
70 .init_irq = spear3xx_init_irq,
71 .handle_irq = vic_handle_irq,
72 .timer = &spear3xx_timer,
73 .init_machine = spear300_evb_init,
74 .restart = spear_restart,
75MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index febaa6fcfb6a..aec07c951205 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -3,142 +3,25 @@
3 * 3 *
4 * SPEAr310 machine source file 4 * SPEAr310 machine source file
5 * 5 *
6 * Copyright (C) 2009 ST Microelectronics 6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com> 7 * Viresh Kumar <viresh.kumar@st.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14#include <linux/ptrace.h> 14#define pr_fmt(fmt) "SPEAr310: " fmt
15#include <asm/irq.h> 15
16#include <linux/amba/pl08x.h>
17#include <linux/amba/serial.h>
18#include <linux/of_platform.h>
19#include <asm/hardware/vic.h>
20#include <asm/mach/arch.h>
16#include <plat/shirq.h> 21#include <plat/shirq.h>
17#include <mach/generic.h> 22#include <mach/generic.h>
18#include <mach/hardware.h> 23#include <mach/hardware.h>
19 24
20/* pad multiplexing support */
21/* muxing registers */
22#define PAD_MUX_CONFIG_REG 0x08
23
24/* devices */
25static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
26 {
27 .ids = 0x00,
28 .mask = PMX_TIMER_3_4_MASK,
29 },
30};
31
32struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = {
33 .name = "emi_cs_0_1_4_5",
34 .modes = pmx_emi_cs_0_1_4_5_modes,
35 .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
36 .enb_on_reset = 1,
37};
38
39static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
40 {
41 .ids = 0x00,
42 .mask = PMX_TIMER_1_2_MASK,
43 },
44};
45
46struct pmx_dev spear310_pmx_emi_cs_2_3 = {
47 .name = "emi_cs_2_3",
48 .modes = pmx_emi_cs_2_3_modes,
49 .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
50 .enb_on_reset = 1,
51};
52
53static struct pmx_dev_mode pmx_uart1_modes[] = {
54 {
55 .ids = 0x00,
56 .mask = PMX_FIRDA_MASK,
57 },
58};
59
60struct pmx_dev spear310_pmx_uart1 = {
61 .name = "uart1",
62 .modes = pmx_uart1_modes,
63 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
64 .enb_on_reset = 1,
65};
66
67static struct pmx_dev_mode pmx_uart2_modes[] = {
68 {
69 .ids = 0x00,
70 .mask = PMX_TIMER_1_2_MASK,
71 },
72};
73
74struct pmx_dev spear310_pmx_uart2 = {
75 .name = "uart2",
76 .modes = pmx_uart2_modes,
77 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
78 .enb_on_reset = 1,
79};
80
81static struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
82 {
83 .ids = 0x00,
84 .mask = PMX_UART0_MODEM_MASK,
85 },
86};
87
88struct pmx_dev spear310_pmx_uart3_4_5 = {
89 .name = "uart3_4_5",
90 .modes = pmx_uart3_4_5_modes,
91 .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
92 .enb_on_reset = 1,
93};
94
95static struct pmx_dev_mode pmx_fsmc_modes[] = {
96 {
97 .ids = 0x00,
98 .mask = PMX_SSP_CS_MASK,
99 },
100};
101
102struct pmx_dev spear310_pmx_fsmc = {
103 .name = "fsmc",
104 .modes = pmx_fsmc_modes,
105 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
106 .enb_on_reset = 1,
107};
108
109static struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
110 {
111 .ids = 0x00,
112 .mask = PMX_MII_MASK,
113 },
114};
115
116struct pmx_dev spear310_pmx_rs485_0_1 = {
117 .name = "rs485_0_1",
118 .modes = pmx_rs485_0_1_modes,
119 .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
120 .enb_on_reset = 1,
121};
122
123static struct pmx_dev_mode pmx_tdm0_modes[] = {
124 {
125 .ids = 0x00,
126 .mask = PMX_MII_MASK,
127 },
128};
129
130struct pmx_dev spear310_pmx_tdm0 = {
131 .name = "tdm0",
132 .modes = pmx_tdm0_modes,
133 .mode_count = ARRAY_SIZE(pmx_tdm0_modes),
134 .enb_on_reset = 1,
135};
136
137/* pmx driver structure */
138static struct pmx_driver pmx_driver = {
139 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
140};
141
142/* spear3xx shared irq */ 25/* spear3xx shared irq */
143static struct shirq_dev_config shirq_ras1_config[] = { 26static struct shirq_dev_config shirq_ras1_config[] = {
144 { 27 {
@@ -255,17 +138,247 @@ static struct spear_shirq shirq_intrcomm_ras = {
255 }, 138 },
256}; 139};
257 140
258/* Add spear310 specific devices here */ 141/* DMAC platform data's slave info */
142struct pl08x_channel_data spear310_dma_info[] = {
143 {
144 .bus_id = "uart0_rx",
145 .min_signal = 2,
146 .max_signal = 2,
147 .muxval = 0,
148 .cctl = 0,
149 .periph_buses = PL08X_AHB1,
150 }, {
151 .bus_id = "uart0_tx",
152 .min_signal = 3,
153 .max_signal = 3,
154 .muxval = 0,
155 .cctl = 0,
156 .periph_buses = PL08X_AHB1,
157 }, {
158 .bus_id = "ssp0_rx",
159 .min_signal = 8,
160 .max_signal = 8,
161 .muxval = 0,
162 .cctl = 0,
163 .periph_buses = PL08X_AHB1,
164 }, {
165 .bus_id = "ssp0_tx",
166 .min_signal = 9,
167 .max_signal = 9,
168 .muxval = 0,
169 .cctl = 0,
170 .periph_buses = PL08X_AHB1,
171 }, {
172 .bus_id = "i2c_rx",
173 .min_signal = 10,
174 .max_signal = 10,
175 .muxval = 0,
176 .cctl = 0,
177 .periph_buses = PL08X_AHB1,
178 }, {
179 .bus_id = "i2c_tx",
180 .min_signal = 11,
181 .max_signal = 11,
182 .muxval = 0,
183 .cctl = 0,
184 .periph_buses = PL08X_AHB1,
185 }, {
186 .bus_id = "irda",
187 .min_signal = 12,
188 .max_signal = 12,
189 .muxval = 0,
190 .cctl = 0,
191 .periph_buses = PL08X_AHB1,
192 }, {
193 .bus_id = "adc",
194 .min_signal = 13,
195 .max_signal = 13,
196 .muxval = 0,
197 .cctl = 0,
198 .periph_buses = PL08X_AHB1,
199 }, {
200 .bus_id = "to_jpeg",
201 .min_signal = 14,
202 .max_signal = 14,
203 .muxval = 0,
204 .cctl = 0,
205 .periph_buses = PL08X_AHB1,
206 }, {
207 .bus_id = "from_jpeg",
208 .min_signal = 15,
209 .max_signal = 15,
210 .muxval = 0,
211 .cctl = 0,
212 .periph_buses = PL08X_AHB1,
213 }, {
214 .bus_id = "uart1_rx",
215 .min_signal = 0,
216 .max_signal = 0,
217 .muxval = 1,
218 .cctl = 0,
219 .periph_buses = PL08X_AHB1,
220 }, {
221 .bus_id = "uart1_tx",
222 .min_signal = 1,
223 .max_signal = 1,
224 .muxval = 1,
225 .cctl = 0,
226 .periph_buses = PL08X_AHB1,
227 }, {
228 .bus_id = "uart2_rx",
229 .min_signal = 2,
230 .max_signal = 2,
231 .muxval = 1,
232 .cctl = 0,
233 .periph_buses = PL08X_AHB1,
234 }, {
235 .bus_id = "uart2_tx",
236 .min_signal = 3,
237 .max_signal = 3,
238 .muxval = 1,
239 .cctl = 0,
240 .periph_buses = PL08X_AHB1,
241 }, {
242 .bus_id = "uart3_rx",
243 .min_signal = 4,
244 .max_signal = 4,
245 .muxval = 1,
246 .cctl = 0,
247 .periph_buses = PL08X_AHB1,
248 }, {
249 .bus_id = "uart3_tx",
250 .min_signal = 5,
251 .max_signal = 5,
252 .muxval = 1,
253 .cctl = 0,
254 .periph_buses = PL08X_AHB1,
255 }, {
256 .bus_id = "uart4_rx",
257 .min_signal = 6,
258 .max_signal = 6,
259 .muxval = 1,
260 .cctl = 0,
261 .periph_buses = PL08X_AHB1,
262 }, {
263 .bus_id = "uart4_tx",
264 .min_signal = 7,
265 .max_signal = 7,
266 .muxval = 1,
267 .cctl = 0,
268 .periph_buses = PL08X_AHB1,
269 }, {
270 .bus_id = "uart5_rx",
271 .min_signal = 8,
272 .max_signal = 8,
273 .muxval = 1,
274 .cctl = 0,
275 .periph_buses = PL08X_AHB1,
276 }, {
277 .bus_id = "uart5_tx",
278 .min_signal = 9,
279 .max_signal = 9,
280 .muxval = 1,
281 .cctl = 0,
282 .periph_buses = PL08X_AHB1,
283 }, {
284 .bus_id = "ras5_rx",
285 .min_signal = 10,
286 .max_signal = 10,
287 .muxval = 1,
288 .cctl = 0,
289 .periph_buses = PL08X_AHB1,
290 }, {
291 .bus_id = "ras5_tx",
292 .min_signal = 11,
293 .max_signal = 11,
294 .muxval = 1,
295 .cctl = 0,
296 .periph_buses = PL08X_AHB1,
297 }, {
298 .bus_id = "ras6_rx",
299 .min_signal = 12,
300 .max_signal = 12,
301 .muxval = 1,
302 .cctl = 0,
303 .periph_buses = PL08X_AHB1,
304 }, {
305 .bus_id = "ras6_tx",
306 .min_signal = 13,
307 .max_signal = 13,
308 .muxval = 1,
309 .cctl = 0,
310 .periph_buses = PL08X_AHB1,
311 }, {
312 .bus_id = "ras7_rx",
313 .min_signal = 14,
314 .max_signal = 14,
315 .muxval = 1,
316 .cctl = 0,
317 .periph_buses = PL08X_AHB1,
318 }, {
319 .bus_id = "ras7_tx",
320 .min_signal = 15,
321 .max_signal = 15,
322 .muxval = 1,
323 .cctl = 0,
324 .periph_buses = PL08X_AHB1,
325 },
326};
259 327
260/* spear310 routines */ 328/* uart devices plat data */
261void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, 329static struct amba_pl011_data spear310_uart_data[] = {
262 u8 pmx_dev_count) 330 {
331 .dma_filter = pl08x_filter_id,
332 .dma_tx_param = "uart1_tx",
333 .dma_rx_param = "uart1_rx",
334 }, {
335 .dma_filter = pl08x_filter_id,
336 .dma_tx_param = "uart2_tx",
337 .dma_rx_param = "uart2_rx",
338 }, {
339 .dma_filter = pl08x_filter_id,
340 .dma_tx_param = "uart3_tx",
341 .dma_rx_param = "uart3_rx",
342 }, {
343 .dma_filter = pl08x_filter_id,
344 .dma_tx_param = "uart4_tx",
345 .dma_rx_param = "uart4_rx",
346 }, {
347 .dma_filter = pl08x_filter_id,
348 .dma_tx_param = "uart5_tx",
349 .dma_rx_param = "uart5_rx",
350 },
351};
352
353/* Add SPEAr310 auxdata to pass platform data */
354static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
355 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
356 &pl022_plat_data),
357 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
358 &pl080_plat_data),
359 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
360 &spear310_uart_data[0]),
361 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL,
362 &spear310_uart_data[1]),
363 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL,
364 &spear310_uart_data[2]),
365 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL,
366 &spear310_uart_data[3]),
367 OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL,
368 &spear310_uart_data[4]),
369 {}
370};
371
372static void __init spear310_dt_init(void)
263{ 373{
264 void __iomem *base; 374 void __iomem *base;
265 int ret = 0; 375 int ret;
266 376
267 /* call spear3xx family common init function */ 377 pl080_plat_data.slave_channels = spear310_dma_info;
268 spear3xx_init(); 378 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
379
380 of_platform_populate(NULL, of_default_bus_match_table,
381 spear310_auxdata_lookup, NULL);
269 382
270 /* shared irq registration */ 383 /* shared irq registration */
271 base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K); 384 base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
@@ -274,35 +387,46 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
274 shirq_ras1.regs.base = base; 387 shirq_ras1.regs.base = base;
275 ret = spear_shirq_register(&shirq_ras1); 388 ret = spear_shirq_register(&shirq_ras1);
276 if (ret) 389 if (ret)
277 printk(KERN_ERR "Error registering Shared IRQ 1\n"); 390 pr_err("Error registering Shared IRQ 1\n");
278 391
279 /* shirq 2 */ 392 /* shirq 2 */
280 shirq_ras2.regs.base = base; 393 shirq_ras2.regs.base = base;
281 ret = spear_shirq_register(&shirq_ras2); 394 ret = spear_shirq_register(&shirq_ras2);
282 if (ret) 395 if (ret)
283 printk(KERN_ERR "Error registering Shared IRQ 2\n"); 396 pr_err("Error registering Shared IRQ 2\n");
284 397
285 /* shirq 3 */ 398 /* shirq 3 */
286 shirq_ras3.regs.base = base; 399 shirq_ras3.regs.base = base;
287 ret = spear_shirq_register(&shirq_ras3); 400 ret = spear_shirq_register(&shirq_ras3);
288 if (ret) 401 if (ret)
289 printk(KERN_ERR "Error registering Shared IRQ 3\n"); 402 pr_err("Error registering Shared IRQ 3\n");
290 403
291 /* shirq 4 */ 404 /* shirq 4 */
292 shirq_intrcomm_ras.regs.base = base; 405 shirq_intrcomm_ras.regs.base = base;
293 ret = spear_shirq_register(&shirq_intrcomm_ras); 406 ret = spear_shirq_register(&shirq_intrcomm_ras);
294 if (ret) 407 if (ret)
295 printk(KERN_ERR "Error registering Shared IRQ 4\n"); 408 pr_err("Error registering Shared IRQ 4\n");
296 } 409 }
410}
297 411
298 /* pmx initialization */ 412static const char * const spear310_dt_board_compat[] = {
299 pmx_driver.base = base; 413 "st,spear310",
300 pmx_driver.mode = pmx_mode; 414 "st,spear310-evb",
301 pmx_driver.devs = pmx_devs; 415 NULL,
302 pmx_driver.devs_count = pmx_dev_count; 416};
303 417
304 ret = pmx_register(&pmx_driver); 418static void __init spear310_map_io(void)
305 if (ret) 419{
306 printk(KERN_ERR "padmux: registration failed. err no: %d\n", 420 spear3xx_map_io();
307 ret); 421 spear310_clk_init();
308} 422}
423
424DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
425 .map_io = spear310_map_io,
426 .init_irq = spear3xx_dt_init_irq,
427 .handle_irq = vic_handle_irq,
428 .timer = &spear3xx_timer,
429 .init_machine = spear310_dt_init,
430 .restart = spear_restart,
431 .dt_compat = spear310_dt_board_compat,
432MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
deleted file mode 100644
index f92c4993f65a..000000000000
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ /dev/null
@@ -1,81 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/spear310_evb.c
3 *
4 * SPEAr310 evaluation board source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <asm/hardware/vic.h>
15#include <asm/mach/arch.h>
16#include <asm/mach-types.h>
17#include <mach/generic.h>
18#include <mach/hardware.h>
19
20/* padmux devices to enable */
21static struct pmx_dev *pmx_devs[] = {
22 /* spear3xx specific devices */
23 &spear3xx_pmx_i2c,
24 &spear3xx_pmx_ssp,
25 &spear3xx_pmx_gpio_pin0,
26 &spear3xx_pmx_gpio_pin1,
27 &spear3xx_pmx_gpio_pin2,
28 &spear3xx_pmx_gpio_pin3,
29 &spear3xx_pmx_gpio_pin4,
30 &spear3xx_pmx_gpio_pin5,
31 &spear3xx_pmx_uart0,
32
33 /* spear310 specific devices */
34 &spear310_pmx_emi_cs_0_1_4_5,
35 &spear310_pmx_emi_cs_2_3,
36 &spear310_pmx_uart1,
37 &spear310_pmx_uart2,
38 &spear310_pmx_uart3_4_5,
39 &spear310_pmx_fsmc,
40 &spear310_pmx_rs485_0_1,
41 &spear310_pmx_tdm0,
42};
43
44static struct amba_device *amba_devs[] __initdata = {
45 /* spear3xx specific devices */
46 &spear3xx_gpio_device,
47 &spear3xx_uart_device,
48
49 /* spear310 specific devices */
50};
51
52static struct platform_device *plat_devs[] __initdata = {
53 /* spear3xx specific devices */
54
55 /* spear310 specific devices */
56};
57
58static void __init spear310_evb_init(void)
59{
60 unsigned int i;
61
62 /* call spear310 machine init function */
63 spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
64
65 /* Add Platform Devices */
66 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
67
68 /* Add Amba Devices */
69 for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
70 amba_device_register(amba_devs[i], &iomem_resource);
71}
72
73MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
74 .atag_offset = 0x100,
75 .map_io = spear3xx_map_io,
76 .init_irq = spear3xx_init_irq,
77 .handle_irq = vic_handle_irq,
78 .timer = &spear3xx_timer,
79 .init_machine = spear310_evb_init,
80 .restart = spear_restart,
81MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index bfdad554319c..fb28c189688e 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -3,388 +3,27 @@
3 * 3 *
4 * SPEAr320 machine source file 4 * SPEAr320 machine source file
5 * 5 *
6 * Copyright (C) 2009 ST Microelectronics 6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com> 7 * Viresh Kumar <viresh.kumar@st.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14#include <linux/ptrace.h> 14#define pr_fmt(fmt) "SPEAr320: " fmt
15#include <asm/irq.h> 15
16#include <linux/amba/pl022.h>
17#include <linux/amba/pl08x.h>
18#include <linux/amba/serial.h>
19#include <linux/of_platform.h>
20#include <asm/hardware/vic.h>
21#include <asm/mach/arch.h>
16#include <plat/shirq.h> 22#include <plat/shirq.h>
17#include <mach/generic.h> 23#include <mach/generic.h>
18#include <mach/hardware.h> 24#include <mach/hardware.h>
19#include <mach/spear.h> 25#include <mach/spear.h>
20 26
21/* pad multiplexing support */
22/* muxing registers */
23#define PAD_MUX_CONFIG_REG 0x0C
24#define MODE_CONFIG_REG 0x10
25
26/* modes */
27#define AUTO_NET_SMII_MODE (1 << 0)
28#define AUTO_NET_MII_MODE (1 << 1)
29#define AUTO_EXP_MODE (1 << 2)
30#define SMALL_PRINTERS_MODE (1 << 3)
31#define ALL_MODES 0xF
32
33struct pmx_mode spear320_auto_net_smii_mode = {
34 .id = AUTO_NET_SMII_MODE,
35 .name = "Automation Networking SMII Mode",
36 .mask = 0x00,
37};
38
39struct pmx_mode spear320_auto_net_mii_mode = {
40 .id = AUTO_NET_MII_MODE,
41 .name = "Automation Networking MII Mode",
42 .mask = 0x01,
43};
44
45struct pmx_mode spear320_auto_exp_mode = {
46 .id = AUTO_EXP_MODE,
47 .name = "Automation Expanded Mode",
48 .mask = 0x02,
49};
50
51struct pmx_mode spear320_small_printers_mode = {
52 .id = SMALL_PRINTERS_MODE,
53 .name = "Small Printers Mode",
54 .mask = 0x03,
55};
56
57/* devices */
58static struct pmx_dev_mode pmx_clcd_modes[] = {
59 {
60 .ids = AUTO_NET_SMII_MODE,
61 .mask = 0x0,
62 },
63};
64
65struct pmx_dev spear320_pmx_clcd = {
66 .name = "clcd",
67 .modes = pmx_clcd_modes,
68 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
69 .enb_on_reset = 1,
70};
71
72static struct pmx_dev_mode pmx_emi_modes[] = {
73 {
74 .ids = AUTO_EXP_MODE,
75 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
76 },
77};
78
79struct pmx_dev spear320_pmx_emi = {
80 .name = "emi",
81 .modes = pmx_emi_modes,
82 .mode_count = ARRAY_SIZE(pmx_emi_modes),
83 .enb_on_reset = 1,
84};
85
86static struct pmx_dev_mode pmx_fsmc_modes[] = {
87 {
88 .ids = ALL_MODES,
89 .mask = 0x0,
90 },
91};
92
93struct pmx_dev spear320_pmx_fsmc = {
94 .name = "fsmc",
95 .modes = pmx_fsmc_modes,
96 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
97 .enb_on_reset = 1,
98};
99
100static struct pmx_dev_mode pmx_spp_modes[] = {
101 {
102 .ids = SMALL_PRINTERS_MODE,
103 .mask = 0x0,
104 },
105};
106
107struct pmx_dev spear320_pmx_spp = {
108 .name = "spp",
109 .modes = pmx_spp_modes,
110 .mode_count = ARRAY_SIZE(pmx_spp_modes),
111 .enb_on_reset = 1,
112};
113
114static struct pmx_dev_mode pmx_sdhci_modes[] = {
115 {
116 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
117 SMALL_PRINTERS_MODE,
118 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
119 },
120};
121
122struct pmx_dev spear320_pmx_sdhci = {
123 .name = "sdhci",
124 .modes = pmx_sdhci_modes,
125 .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
126 .enb_on_reset = 1,
127};
128
129static struct pmx_dev_mode pmx_i2s_modes[] = {
130 {
131 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
132 .mask = PMX_UART0_MODEM_MASK,
133 },
134};
135
136struct pmx_dev spear320_pmx_i2s = {
137 .name = "i2s",
138 .modes = pmx_i2s_modes,
139 .mode_count = ARRAY_SIZE(pmx_i2s_modes),
140 .enb_on_reset = 1,
141};
142
143static struct pmx_dev_mode pmx_uart1_modes[] = {
144 {
145 .ids = ALL_MODES,
146 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
147 },
148};
149
150struct pmx_dev spear320_pmx_uart1 = {
151 .name = "uart1",
152 .modes = pmx_uart1_modes,
153 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
154 .enb_on_reset = 1,
155};
156
157static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
158 {
159 .ids = AUTO_EXP_MODE,
160 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
161 PMX_SSP_CS_MASK,
162 }, {
163 .ids = SMALL_PRINTERS_MODE,
164 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
165 PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
166 },
167};
168
169struct pmx_dev spear320_pmx_uart1_modem = {
170 .name = "uart1_modem",
171 .modes = pmx_uart1_modem_modes,
172 .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
173 .enb_on_reset = 1,
174};
175
176static struct pmx_dev_mode pmx_uart2_modes[] = {
177 {
178 .ids = ALL_MODES,
179 .mask = PMX_FIRDA_MASK,
180 },
181};
182
183struct pmx_dev spear320_pmx_uart2 = {
184 .name = "uart2",
185 .modes = pmx_uart2_modes,
186 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
187 .enb_on_reset = 1,
188};
189
190static struct pmx_dev_mode pmx_touchscreen_modes[] = {
191 {
192 .ids = AUTO_NET_SMII_MODE,
193 .mask = PMX_SSP_CS_MASK,
194 },
195};
196
197struct pmx_dev spear320_pmx_touchscreen = {
198 .name = "touchscreen",
199 .modes = pmx_touchscreen_modes,
200 .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
201 .enb_on_reset = 1,
202};
203
204static struct pmx_dev_mode pmx_can_modes[] = {
205 {
206 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
207 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
208 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
209 },
210};
211
212struct pmx_dev spear320_pmx_can = {
213 .name = "can",
214 .modes = pmx_can_modes,
215 .mode_count = ARRAY_SIZE(pmx_can_modes),
216 .enb_on_reset = 1,
217};
218
219static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
220 {
221 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
222 .mask = PMX_SSP_CS_MASK,
223 },
224};
225
226struct pmx_dev spear320_pmx_sdhci_led = {
227 .name = "sdhci_led",
228 .modes = pmx_sdhci_led_modes,
229 .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
230 .enb_on_reset = 1,
231};
232
233static struct pmx_dev_mode pmx_pwm0_modes[] = {
234 {
235 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
236 .mask = PMX_UART0_MODEM_MASK,
237 }, {
238 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
239 .mask = PMX_MII_MASK,
240 },
241};
242
243struct pmx_dev spear320_pmx_pwm0 = {
244 .name = "pwm0",
245 .modes = pmx_pwm0_modes,
246 .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
247 .enb_on_reset = 1,
248};
249
250static struct pmx_dev_mode pmx_pwm1_modes[] = {
251 {
252 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
253 .mask = PMX_UART0_MODEM_MASK,
254 }, {
255 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
256 .mask = PMX_MII_MASK,
257 },
258};
259
260struct pmx_dev spear320_pmx_pwm1 = {
261 .name = "pwm1",
262 .modes = pmx_pwm1_modes,
263 .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
264 .enb_on_reset = 1,
265};
266
267static struct pmx_dev_mode pmx_pwm2_modes[] = {
268 {
269 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
270 .mask = PMX_SSP_CS_MASK,
271 }, {
272 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
273 .mask = PMX_MII_MASK,
274 },
275};
276
277struct pmx_dev spear320_pmx_pwm2 = {
278 .name = "pwm2",
279 .modes = pmx_pwm2_modes,
280 .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
281 .enb_on_reset = 1,
282};
283
284static struct pmx_dev_mode pmx_pwm3_modes[] = {
285 {
286 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
287 .mask = PMX_MII_MASK,
288 },
289};
290
291struct pmx_dev spear320_pmx_pwm3 = {
292 .name = "pwm3",
293 .modes = pmx_pwm3_modes,
294 .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
295 .enb_on_reset = 1,
296};
297
298static struct pmx_dev_mode pmx_ssp1_modes[] = {
299 {
300 .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
301 .mask = PMX_MII_MASK,
302 },
303};
304
305struct pmx_dev spear320_pmx_ssp1 = {
306 .name = "ssp1",
307 .modes = pmx_ssp1_modes,
308 .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
309 .enb_on_reset = 1,
310};
311
312static struct pmx_dev_mode pmx_ssp2_modes[] = {
313 {
314 .ids = AUTO_NET_SMII_MODE,
315 .mask = PMX_MII_MASK,
316 },
317};
318
319struct pmx_dev spear320_pmx_ssp2 = {
320 .name = "ssp2",
321 .modes = pmx_ssp2_modes,
322 .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
323 .enb_on_reset = 1,
324};
325
326static struct pmx_dev_mode pmx_mii1_modes[] = {
327 {
328 .ids = AUTO_NET_MII_MODE,
329 .mask = 0x0,
330 },
331};
332
333struct pmx_dev spear320_pmx_mii1 = {
334 .name = "mii1",
335 .modes = pmx_mii1_modes,
336 .mode_count = ARRAY_SIZE(pmx_mii1_modes),
337 .enb_on_reset = 1,
338};
339
340static struct pmx_dev_mode pmx_smii0_modes[] = {
341 {
342 .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
343 .mask = PMX_MII_MASK,
344 },
345};
346
347struct pmx_dev spear320_pmx_smii0 = {
348 .name = "smii0",
349 .modes = pmx_smii0_modes,
350 .mode_count = ARRAY_SIZE(pmx_smii0_modes),
351 .enb_on_reset = 1,
352};
353
354static struct pmx_dev_mode pmx_smii1_modes[] = {
355 {
356 .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
357 .mask = PMX_MII_MASK,
358 },
359};
360
361struct pmx_dev spear320_pmx_smii1 = {
362 .name = "smii1",
363 .modes = pmx_smii1_modes,
364 .mode_count = ARRAY_SIZE(pmx_smii1_modes),
365 .enb_on_reset = 1,
366};
367
368static struct pmx_dev_mode pmx_i2c1_modes[] = {
369 {
370 .ids = AUTO_EXP_MODE,
371 .mask = 0x0,
372 },
373};
374
375struct pmx_dev spear320_pmx_i2c1 = {
376 .name = "i2c1",
377 .modes = pmx_i2c1_modes,
378 .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
379 .enb_on_reset = 1,
380};
381
382/* pmx driver structure */
383static struct pmx_driver pmx_driver = {
384 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
385 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
386};
387
388/* spear3xx shared irq */ 27/* spear3xx shared irq */
389static struct shirq_dev_config shirq_ras1_config[] = { 28static struct shirq_dev_config shirq_ras1_config[] = {
390 { 29 {
@@ -509,17 +148,250 @@ static struct spear_shirq shirq_intrcomm_ras = {
509 }, 148 },
510}; 149};
511 150
512/* Add spear320 specific devices here */ 151/* DMAC platform data's slave info */
152struct pl08x_channel_data spear320_dma_info[] = {
153 {
154 .bus_id = "uart0_rx",
155 .min_signal = 2,
156 .max_signal = 2,
157 .muxval = 0,
158 .cctl = 0,
159 .periph_buses = PL08X_AHB1,
160 }, {
161 .bus_id = "uart0_tx",
162 .min_signal = 3,
163 .max_signal = 3,
164 .muxval = 0,
165 .cctl = 0,
166 .periph_buses = PL08X_AHB1,
167 }, {
168 .bus_id = "ssp0_rx",
169 .min_signal = 8,
170 .max_signal = 8,
171 .muxval = 0,
172 .cctl = 0,
173 .periph_buses = PL08X_AHB1,
174 }, {
175 .bus_id = "ssp0_tx",
176 .min_signal = 9,
177 .max_signal = 9,
178 .muxval = 0,
179 .cctl = 0,
180 .periph_buses = PL08X_AHB1,
181 }, {
182 .bus_id = "i2c0_rx",
183 .min_signal = 10,
184 .max_signal = 10,
185 .muxval = 0,
186 .cctl = 0,
187 .periph_buses = PL08X_AHB1,
188 }, {
189 .bus_id = "i2c0_tx",
190 .min_signal = 11,
191 .max_signal = 11,
192 .muxval = 0,
193 .cctl = 0,
194 .periph_buses = PL08X_AHB1,
195 }, {
196 .bus_id = "irda",
197 .min_signal = 12,
198 .max_signal = 12,
199 .muxval = 0,
200 .cctl = 0,
201 .periph_buses = PL08X_AHB1,
202 }, {
203 .bus_id = "adc",
204 .min_signal = 13,
205 .max_signal = 13,
206 .muxval = 0,
207 .cctl = 0,
208 .periph_buses = PL08X_AHB1,
209 }, {
210 .bus_id = "to_jpeg",
211 .min_signal = 14,
212 .max_signal = 14,
213 .muxval = 0,
214 .cctl = 0,
215 .periph_buses = PL08X_AHB1,
216 }, {
217 .bus_id = "from_jpeg",
218 .min_signal = 15,
219 .max_signal = 15,
220 .muxval = 0,
221 .cctl = 0,
222 .periph_buses = PL08X_AHB1,
223 }, {
224 .bus_id = "ssp1_rx",
225 .min_signal = 0,
226 .max_signal = 0,
227 .muxval = 1,
228 .cctl = 0,
229 .periph_buses = PL08X_AHB2,
230 }, {
231 .bus_id = "ssp1_tx",
232 .min_signal = 1,
233 .max_signal = 1,
234 .muxval = 1,
235 .cctl = 0,
236 .periph_buses = PL08X_AHB2,
237 }, {
238 .bus_id = "ssp2_rx",
239 .min_signal = 2,
240 .max_signal = 2,
241 .muxval = 1,
242 .cctl = 0,
243 .periph_buses = PL08X_AHB2,
244 }, {
245 .bus_id = "ssp2_tx",
246 .min_signal = 3,
247 .max_signal = 3,
248 .muxval = 1,
249 .cctl = 0,
250 .periph_buses = PL08X_AHB2,
251 }, {
252 .bus_id = "uart1_rx",
253 .min_signal = 4,
254 .max_signal = 4,
255 .muxval = 1,
256 .cctl = 0,
257 .periph_buses = PL08X_AHB2,
258 }, {
259 .bus_id = "uart1_tx",
260 .min_signal = 5,
261 .max_signal = 5,
262 .muxval = 1,
263 .cctl = 0,
264 .periph_buses = PL08X_AHB2,
265 }, {
266 .bus_id = "uart2_rx",
267 .min_signal = 6,
268 .max_signal = 6,
269 .muxval = 1,
270 .cctl = 0,
271 .periph_buses = PL08X_AHB2,
272 }, {
273 .bus_id = "uart2_tx",
274 .min_signal = 7,
275 .max_signal = 7,
276 .muxval = 1,
277 .cctl = 0,
278 .periph_buses = PL08X_AHB2,
279 }, {
280 .bus_id = "i2c1_rx",
281 .min_signal = 8,
282 .max_signal = 8,
283 .muxval = 1,
284 .cctl = 0,
285 .periph_buses = PL08X_AHB2,
286 }, {
287 .bus_id = "i2c1_tx",
288 .min_signal = 9,
289 .max_signal = 9,
290 .muxval = 1,
291 .cctl = 0,
292 .periph_buses = PL08X_AHB2,
293 }, {
294 .bus_id = "i2c2_rx",
295 .min_signal = 10,
296 .max_signal = 10,
297 .muxval = 1,
298 .cctl = 0,
299 .periph_buses = PL08X_AHB2,
300 }, {
301 .bus_id = "i2c2_tx",
302 .min_signal = 11,
303 .max_signal = 11,
304 .muxval = 1,
305 .cctl = 0,
306 .periph_buses = PL08X_AHB2,
307 }, {
308 .bus_id = "i2s_rx",
309 .min_signal = 12,
310 .max_signal = 12,
311 .muxval = 1,
312 .cctl = 0,
313 .periph_buses = PL08X_AHB2,
314 }, {
315 .bus_id = "i2s_tx",
316 .min_signal = 13,
317 .max_signal = 13,
318 .muxval = 1,
319 .cctl = 0,
320 .periph_buses = PL08X_AHB2,
321 }, {
322 .bus_id = "rs485_rx",
323 .min_signal = 14,
324 .max_signal = 14,
325 .muxval = 1,
326 .cctl = 0,
327 .periph_buses = PL08X_AHB2,
328 }, {
329 .bus_id = "rs485_tx",
330 .min_signal = 15,
331 .max_signal = 15,
332 .muxval = 1,
333 .cctl = 0,
334 .periph_buses = PL08X_AHB2,
335 },
336};
337
338static struct pl022_ssp_controller spear320_ssp_data[] = {
339 {
340 .bus_id = 1,
341 .enable_dma = 1,
342 .dma_filter = pl08x_filter_id,
343 .dma_tx_param = "ssp1_tx",
344 .dma_rx_param = "ssp1_rx",
345 .num_chipselect = 2,
346 }, {
347 .bus_id = 2,
348 .enable_dma = 1,
349 .dma_filter = pl08x_filter_id,
350 .dma_tx_param = "ssp2_tx",
351 .dma_rx_param = "ssp2_rx",
352 .num_chipselect = 2,
353 }
354};
355
356static struct amba_pl011_data spear320_uart_data[] = {
357 {
358 .dma_filter = pl08x_filter_id,
359 .dma_tx_param = "uart1_tx",
360 .dma_rx_param = "uart1_rx",
361 }, {
362 .dma_filter = pl08x_filter_id,
363 .dma_tx_param = "uart2_tx",
364 .dma_rx_param = "uart2_rx",
365 },
366};
513 367
514/* spear320 routines */ 368/* Add SPEAr310 auxdata to pass platform data */
515void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, 369static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
516 u8 pmx_dev_count) 370 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
371 &pl022_plat_data),
372 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
373 &pl080_plat_data),
374 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
375 &spear320_ssp_data[0]),
376 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
377 &spear320_ssp_data[1]),
378 OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
379 &spear320_uart_data[0]),
380 OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
381 &spear320_uart_data[1]),
382 {}
383};
384
385static void __init spear320_dt_init(void)
517{ 386{
518 void __iomem *base; 387 void __iomem *base;
519 int ret = 0; 388 int ret;
389
390 pl080_plat_data.slave_channels = spear320_dma_info;
391 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
520 392
521 /* call spear3xx family common init function */ 393 of_platform_populate(NULL, of_default_bus_match_table,
522 spear3xx_init(); 394 spear320_auxdata_lookup, NULL);
523 395
524 /* shared irq registration */ 396 /* shared irq registration */
525 base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K); 397 base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
@@ -528,29 +400,40 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
528 shirq_ras1.regs.base = base; 400 shirq_ras1.regs.base = base;
529 ret = spear_shirq_register(&shirq_ras1); 401 ret = spear_shirq_register(&shirq_ras1);
530 if (ret) 402 if (ret)
531 printk(KERN_ERR "Error registering Shared IRQ 1\n"); 403 pr_err("Error registering Shared IRQ 1\n");
532 404
533 /* shirq 3 */ 405 /* shirq 3 */
534 shirq_ras3.regs.base = base; 406 shirq_ras3.regs.base = base;
535 ret = spear_shirq_register(&shirq_ras3); 407 ret = spear_shirq_register(&shirq_ras3);
536 if (ret) 408 if (ret)
537 printk(KERN_ERR "Error registering Shared IRQ 3\n"); 409 pr_err("Error registering Shared IRQ 3\n");
538 410
539 /* shirq 4 */ 411 /* shirq 4 */
540 shirq_intrcomm_ras.regs.base = base; 412 shirq_intrcomm_ras.regs.base = base;
541 ret = spear_shirq_register(&shirq_intrcomm_ras); 413 ret = spear_shirq_register(&shirq_intrcomm_ras);
542 if (ret) 414 if (ret)
543 printk(KERN_ERR "Error registering Shared IRQ 4\n"); 415 pr_err("Error registering Shared IRQ 4\n");
544 } 416 }
417}
545 418
546 /* pmx initialization */ 419static const char * const spear320_dt_board_compat[] = {
547 pmx_driver.base = base; 420 "st,spear320",
548 pmx_driver.mode = pmx_mode; 421 "st,spear320-evb",
549 pmx_driver.devs = pmx_devs; 422 NULL,
550 pmx_driver.devs_count = pmx_dev_count; 423};
551 424
552 ret = pmx_register(&pmx_driver); 425static void __init spear320_map_io(void)
553 if (ret) 426{
554 printk(KERN_ERR "padmux: registration failed. err no: %d\n", 427 spear3xx_map_io();
555 ret); 428 spear320_clk_init();
556} 429}
430
431DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
432 .map_io = spear320_map_io,
433 .init_irq = spear3xx_dt_init_irq,
434 .handle_irq = vic_handle_irq,
435 .timer = &spear3xx_timer,
436 .init_machine = spear320_dt_init,
437 .restart = spear_restart,
438 .dt_compat = spear320_dt_board_compat,
439MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
deleted file mode 100644
index 105334ab7021..000000000000
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ /dev/null
@@ -1,79 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/spear320_evb.c
3 *
4 * SPEAr320 evaluation board source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <asm/hardware/vic.h>
15#include <asm/mach/arch.h>
16#include <asm/mach-types.h>
17#include <mach/generic.h>
18#include <mach/hardware.h>
19
20/* padmux devices to enable */
21static struct pmx_dev *pmx_devs[] = {
22 /* spear3xx specific devices */
23 &spear3xx_pmx_i2c,
24 &spear3xx_pmx_ssp,
25 &spear3xx_pmx_mii,
26 &spear3xx_pmx_uart0,
27
28 /* spear320 specific devices */
29 &spear320_pmx_fsmc,
30 &spear320_pmx_sdhci,
31 &spear320_pmx_i2s,
32 &spear320_pmx_uart1,
33 &spear320_pmx_uart2,
34 &spear320_pmx_can,
35 &spear320_pmx_pwm0,
36 &spear320_pmx_pwm1,
37 &spear320_pmx_pwm2,
38 &spear320_pmx_mii1,
39};
40
41static struct amba_device *amba_devs[] __initdata = {
42 /* spear3xx specific devices */
43 &spear3xx_gpio_device,
44 &spear3xx_uart_device,
45
46 /* spear320 specific devices */
47};
48
49static struct platform_device *plat_devs[] __initdata = {
50 /* spear3xx specific devices */
51
52 /* spear320 specific devices */
53};
54
55static void __init spear320_evb_init(void)
56{
57 unsigned int i;
58
59 /* call spear320 machine init function */
60 spear320_init(&spear320_auto_net_mii_mode, pmx_devs,
61 ARRAY_SIZE(pmx_devs));
62
63 /* Add Platform Devices */
64 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
65
66 /* Add Amba Devices */
67 for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
68 amba_device_register(amba_devs[i], &iomem_resource);
69}
70
71MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
72 .atag_offset = 0x100,
73 .map_io = spear3xx_map_io,
74 .init_irq = spear3xx_init_irq,
75 .handle_irq = vic_handle_irq,
76 .timer = &spear3xx_timer,
77 .init_machine = spear320_evb_init,
78 .restart = spear_restart,
79MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 2625ab9a6c8b..71927c717807 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -3,71 +3,78 @@
3 * 3 *
4 * SPEAr3XX machines common source file 4 * SPEAr3XX machines common source file
5 * 5 *
6 * Copyright (C) 2009 ST Microelectronics 6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com> 7 * Viresh Kumar <viresh.kumar@st.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14#include <linux/types.h> 14#define pr_fmt(fmt) "SPEAr3xx: " fmt
15#include <linux/amba/pl061.h> 15
16#include <linux/ptrace.h> 16#include <linux/amba/pl022.h>
17#include <linux/amba/pl08x.h>
18#include <linux/of_irq.h>
17#include <linux/io.h> 19#include <linux/io.h>
20#include <asm/hardware/pl080.h>
18#include <asm/hardware/vic.h> 21#include <asm/hardware/vic.h>
19#include <asm/irq.h> 22#include <plat/pl080.h>
20#include <asm/mach/arch.h>
21#include <mach/generic.h> 23#include <mach/generic.h>
22#include <mach/hardware.h> 24#include <mach/hardware.h>
23 25
24/* Add spear3xx machines common devices here */ 26/* ssp device registration */
25/* gpio device registration */ 27struct pl022_ssp_controller pl022_plat_data = {
26static struct pl061_platform_data gpio_plat_data = { 28 .bus_id = 0,
27 .gpio_base = 0, 29 .enable_dma = 1,
28 .irq_base = SPEAR3XX_GPIO_INT_BASE, 30 .dma_filter = pl08x_filter_id,
31 .dma_tx_param = "ssp0_tx",
32 .dma_rx_param = "ssp0_rx",
33 /*
34 * This is number of spi devices that can be connected to spi. There are
35 * two type of chipselects on which slave devices can work. One is chip
36 * select provided by spi masters other is controlled through external
37 * gpio's. We can't use chipselect provided from spi master (because as
38 * soon as FIFO becomes empty, CS is disabled and transfer ends). So
39 * this number now depends on number of gpios available for spi. each
40 * slave on each master requires a separate gpio pin.
41 */
42 .num_chipselect = 2,
43};
44
45/* dmac device registration */
46struct pl08x_platform_data pl080_plat_data = {
47 .memcpy_channel = {
48 .bus_id = "memcpy",
49 .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
50 PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
51 PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
52 PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
53 PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
54 PL080_CONTROL_PROT_SYS),
55 },
56 .lli_buses = PL08X_AHB1,
57 .mem_buses = PL08X_AHB1,
58 .get_signal = pl080_get_signal,
59 .put_signal = pl080_put_signal,
29}; 60};
30 61
31AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE, 62/*
32 {SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data); 63 * Following will create 16MB static virtual/physical mappings
33 64 * PHYSICAL VIRTUAL
34/* uart device registration */ 65 * 0xD0000000 0xFD000000
35AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE, 66 * 0xFC000000 0xFC000000
36 {SPEAR3XX_IRQ_UART}, NULL); 67 */
37
38/* Do spear3xx familiy common initialization part here */
39void __init spear3xx_init(void)
40{
41 /* nothing to do for now */
42}
43
44/* This will initialize vic */
45void __init spear3xx_init_irq(void)
46{
47 vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0);
48}
49
50/* Following will create static virtual/physical mappings */
51struct map_desc spear3xx_io_desc[] __initdata = { 68struct map_desc spear3xx_io_desc[] __initdata = {
52 { 69 {
53 .virtual = VA_SPEAR3XX_ICM1_UART_BASE, 70 .virtual = VA_SPEAR3XX_ICM1_2_BASE,
54 .pfn = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE), 71 .pfn = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
55 .length = SZ_4K, 72 .length = SZ_16M,
56 .type = MT_DEVICE
57 }, {
58 .virtual = VA_SPEAR3XX_ML1_VIC_BASE,
59 .pfn = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
60 .length = SZ_4K,
61 .type = MT_DEVICE 73 .type = MT_DEVICE
62 }, { 74 }, {
63 .virtual = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE, 75 .virtual = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
64 .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE), 76 .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
65 .length = SZ_4K, 77 .length = SZ_16M,
66 .type = MT_DEVICE
67 }, {
68 .virtual = VA_SPEAR3XX_ICM3_MISC_REG_BASE,
69 .pfn = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
70 .length = SZ_4K,
71 .type = MT_DEVICE 78 .type = MT_DEVICE
72 }, 79 },
73}; 80};
@@ -76,436 +83,8 @@ struct map_desc spear3xx_io_desc[] __initdata = {
76void __init spear3xx_map_io(void) 83void __init spear3xx_map_io(void)
77{ 84{
78 iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); 85 iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
79
80 /* This will initialize clock framework */
81 spear3xx_clk_init();
82} 86}
83 87
84/* pad multiplexing support */
85/* devices */
86static struct pmx_dev_mode pmx_firda_modes[] = {
87 {
88 .ids = 0xffffffff,
89 .mask = PMX_FIRDA_MASK,
90 },
91};
92
93struct pmx_dev spear3xx_pmx_firda = {
94 .name = "firda",
95 .modes = pmx_firda_modes,
96 .mode_count = ARRAY_SIZE(pmx_firda_modes),
97 .enb_on_reset = 0,
98};
99
100static struct pmx_dev_mode pmx_i2c_modes[] = {
101 {
102 .ids = 0xffffffff,
103 .mask = PMX_I2C_MASK,
104 },
105};
106
107struct pmx_dev spear3xx_pmx_i2c = {
108 .name = "i2c",
109 .modes = pmx_i2c_modes,
110 .mode_count = ARRAY_SIZE(pmx_i2c_modes),
111 .enb_on_reset = 0,
112};
113
114static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
115 {
116 .ids = 0xffffffff,
117 .mask = PMX_SSP_CS_MASK,
118 },
119};
120
121struct pmx_dev spear3xx_pmx_ssp_cs = {
122 .name = "ssp_chip_selects",
123 .modes = pmx_ssp_cs_modes,
124 .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
125 .enb_on_reset = 0,
126};
127
128static struct pmx_dev_mode pmx_ssp_modes[] = {
129 {
130 .ids = 0xffffffff,
131 .mask = PMX_SSP_MASK,
132 },
133};
134
135struct pmx_dev spear3xx_pmx_ssp = {
136 .name = "ssp",
137 .modes = pmx_ssp_modes,
138 .mode_count = ARRAY_SIZE(pmx_ssp_modes),
139 .enb_on_reset = 0,
140};
141
142static struct pmx_dev_mode pmx_mii_modes[] = {
143 {
144 .ids = 0xffffffff,
145 .mask = PMX_MII_MASK,
146 },
147};
148
149struct pmx_dev spear3xx_pmx_mii = {
150 .name = "mii",
151 .modes = pmx_mii_modes,
152 .mode_count = ARRAY_SIZE(pmx_mii_modes),
153 .enb_on_reset = 0,
154};
155
156static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
157 {
158 .ids = 0xffffffff,
159 .mask = PMX_GPIO_PIN0_MASK,
160 },
161};
162
163struct pmx_dev spear3xx_pmx_gpio_pin0 = {
164 .name = "gpio_pin0",
165 .modes = pmx_gpio_pin0_modes,
166 .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
167 .enb_on_reset = 0,
168};
169
170static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
171 {
172 .ids = 0xffffffff,
173 .mask = PMX_GPIO_PIN1_MASK,
174 },
175};
176
177struct pmx_dev spear3xx_pmx_gpio_pin1 = {
178 .name = "gpio_pin1",
179 .modes = pmx_gpio_pin1_modes,
180 .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
181 .enb_on_reset = 0,
182};
183
184static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
185 {
186 .ids = 0xffffffff,
187 .mask = PMX_GPIO_PIN2_MASK,
188 },
189};
190
191struct pmx_dev spear3xx_pmx_gpio_pin2 = {
192 .name = "gpio_pin2",
193 .modes = pmx_gpio_pin2_modes,
194 .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
195 .enb_on_reset = 0,
196};
197
198static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
199 {
200 .ids = 0xffffffff,
201 .mask = PMX_GPIO_PIN3_MASK,
202 },
203};
204
205struct pmx_dev spear3xx_pmx_gpio_pin3 = {
206 .name = "gpio_pin3",
207 .modes = pmx_gpio_pin3_modes,
208 .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
209 .enb_on_reset = 0,
210};
211
212static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
213 {
214 .ids = 0xffffffff,
215 .mask = PMX_GPIO_PIN4_MASK,
216 },
217};
218
219struct pmx_dev spear3xx_pmx_gpio_pin4 = {
220 .name = "gpio_pin4",
221 .modes = pmx_gpio_pin4_modes,
222 .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
223 .enb_on_reset = 0,
224};
225
226static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
227 {
228 .ids = 0xffffffff,
229 .mask = PMX_GPIO_PIN5_MASK,
230 },
231};
232
233struct pmx_dev spear3xx_pmx_gpio_pin5 = {
234 .name = "gpio_pin5",
235 .modes = pmx_gpio_pin5_modes,
236 .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
237 .enb_on_reset = 0,
238};
239
240static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
241 {
242 .ids = 0xffffffff,
243 .mask = PMX_UART0_MODEM_MASK,
244 },
245};
246
247struct pmx_dev spear3xx_pmx_uart0_modem = {
248 .name = "uart0_modem",
249 .modes = pmx_uart0_modem_modes,
250 .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
251 .enb_on_reset = 0,
252};
253
254static struct pmx_dev_mode pmx_uart0_modes[] = {
255 {
256 .ids = 0xffffffff,
257 .mask = PMX_UART0_MASK,
258 },
259};
260
261struct pmx_dev spear3xx_pmx_uart0 = {
262 .name = "uart0",
263 .modes = pmx_uart0_modes,
264 .mode_count = ARRAY_SIZE(pmx_uart0_modes),
265 .enb_on_reset = 0,
266};
267
268static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
269 {
270 .ids = 0xffffffff,
271 .mask = PMX_TIMER_3_4_MASK,
272 },
273};
274
275struct pmx_dev spear3xx_pmx_timer_3_4 = {
276 .name = "timer_3_4",
277 .modes = pmx_timer_3_4_modes,
278 .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
279 .enb_on_reset = 0,
280};
281
282static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
283 {
284 .ids = 0xffffffff,
285 .mask = PMX_TIMER_1_2_MASK,
286 },
287};
288
289struct pmx_dev spear3xx_pmx_timer_1_2 = {
290 .name = "timer_1_2",
291 .modes = pmx_timer_1_2_modes,
292 .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
293 .enb_on_reset = 0,
294};
295
296#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
297/* plgpios devices */
298static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
299 {
300 .ids = 0x00,
301 .mask = PMX_FIRDA_MASK,
302 },
303};
304
305struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
306 .name = "plgpio 0 and 1",
307 .modes = pmx_plgpio_0_1_modes,
308 .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
309 .enb_on_reset = 1,
310};
311
312static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
313 {
314 .ids = 0x00,
315 .mask = PMX_UART0_MASK,
316 },
317};
318
319struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
320 .name = "plgpio 2 and 3",
321 .modes = pmx_plgpio_2_3_modes,
322 .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
323 .enb_on_reset = 1,
324};
325
326static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
327 {
328 .ids = 0x00,
329 .mask = PMX_I2C_MASK,
330 },
331};
332
333struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
334 .name = "plgpio 4 and 5",
335 .modes = pmx_plgpio_4_5_modes,
336 .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
337 .enb_on_reset = 1,
338};
339
340static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
341 {
342 .ids = 0x00,
343 .mask = PMX_SSP_MASK,
344 },
345};
346
347struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
348 .name = "plgpio 6 to 9",
349 .modes = pmx_plgpio_6_9_modes,
350 .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
351 .enb_on_reset = 1,
352};
353
354static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
355 {
356 .ids = 0x00,
357 .mask = PMX_MII_MASK,
358 },
359};
360
361struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
362 .name = "plgpio 10 to 27",
363 .modes = pmx_plgpio_10_27_modes,
364 .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
365 .enb_on_reset = 1,
366};
367
368static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
369 {
370 .ids = 0x00,
371 .mask = PMX_GPIO_PIN0_MASK,
372 },
373};
374
375struct pmx_dev spear3xx_pmx_plgpio_28 = {
376 .name = "plgpio 28",
377 .modes = pmx_plgpio_28_modes,
378 .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
379 .enb_on_reset = 1,
380};
381
382static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
383 {
384 .ids = 0x00,
385 .mask = PMX_GPIO_PIN1_MASK,
386 },
387};
388
389struct pmx_dev spear3xx_pmx_plgpio_29 = {
390 .name = "plgpio 29",
391 .modes = pmx_plgpio_29_modes,
392 .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
393 .enb_on_reset = 1,
394};
395
396static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
397 {
398 .ids = 0x00,
399 .mask = PMX_GPIO_PIN2_MASK,
400 },
401};
402
403struct pmx_dev spear3xx_pmx_plgpio_30 = {
404 .name = "plgpio 30",
405 .modes = pmx_plgpio_30_modes,
406 .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
407 .enb_on_reset = 1,
408};
409
410static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
411 {
412 .ids = 0x00,
413 .mask = PMX_GPIO_PIN3_MASK,
414 },
415};
416
417struct pmx_dev spear3xx_pmx_plgpio_31 = {
418 .name = "plgpio 31",
419 .modes = pmx_plgpio_31_modes,
420 .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
421 .enb_on_reset = 1,
422};
423
424static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
425 {
426 .ids = 0x00,
427 .mask = PMX_GPIO_PIN4_MASK,
428 },
429};
430
431struct pmx_dev spear3xx_pmx_plgpio_32 = {
432 .name = "plgpio 32",
433 .modes = pmx_plgpio_32_modes,
434 .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
435 .enb_on_reset = 1,
436};
437
438static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
439 {
440 .ids = 0x00,
441 .mask = PMX_GPIO_PIN5_MASK,
442 },
443};
444
445struct pmx_dev spear3xx_pmx_plgpio_33 = {
446 .name = "plgpio 33",
447 .modes = pmx_plgpio_33_modes,
448 .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
449 .enb_on_reset = 1,
450};
451
452static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
453 {
454 .ids = 0x00,
455 .mask = PMX_SSP_CS_MASK,
456 },
457};
458
459struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
460 .name = "plgpio 34 to 36",
461 .modes = pmx_plgpio_34_36_modes,
462 .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
463 .enb_on_reset = 1,
464};
465
466static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
467 {
468 .ids = 0x00,
469 .mask = PMX_UART0_MODEM_MASK,
470 },
471};
472
473struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
474 .name = "plgpio 37 to 42",
475 .modes = pmx_plgpio_37_42_modes,
476 .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
477 .enb_on_reset = 1,
478};
479
480static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
481 {
482 .ids = 0x00,
483 .mask = PMX_TIMER_1_2_MASK,
484 },
485};
486
487struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
488 .name = "plgpio 43, 44, 47 and 48",
489 .modes = pmx_plgpio_43_44_47_48_modes,
490 .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
491 .enb_on_reset = 1,
492};
493
494static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
495 {
496 .ids = 0x00,
497 .mask = PMX_TIMER_3_4_MASK,
498 },
499};
500
501struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
502 .name = "plgpio 45, 46, 49 and 50",
503 .modes = pmx_plgpio_45_46_49_50_modes,
504 .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
505 .enb_on_reset = 1,
506};
507#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
508
509static void __init spear3xx_timer_init(void) 88static void __init spear3xx_timer_init(void)
510{ 89{
511 char pclk_name[] = "pll3_48m_clk"; 90 char pclk_name[] = "pll3_48m_clk";
@@ -538,3 +117,13 @@ static void __init spear3xx_timer_init(void)
538struct sys_timer spear3xx_timer = { 117struct sys_timer spear3xx_timer = {
539 .init = spear3xx_timer_init, 118 .init = spear3xx_timer_init,
540}; 119};
120
121static const struct of_device_id vic_of_match[] __initconst = {
122 { .compatible = "arm,pl190-vic", .data = vic_of_init, },
123 { /* Sentinel */ }
124};
125
126void __init spear3xx_dt_init_irq(void)
127{
128 of_irq_init(vic_of_match);
129}
diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot
index 4674a4c221db..af493da37ab6 100644
--- a/arch/arm/mach-spear6xx/Makefile.boot
+++ b/arch/arm/mach-spear6xx/Makefile.boot
@@ -1,3 +1,5 @@
1zreladdr-y += 0x00008000 1zreladdr-y += 0x00008000
2params_phys-y := 0x00000100 2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000 3initrd_phys-y := 0x00800000
4
5dtb-$(CONFIG_BOARD_SPEAR600_DT) += spear600-evb.dtb
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 771e19e3c43c..e9031ec6d6e0 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -13,15 +13,377 @@
13 * warranty of any kind, whether express or implied. 13 * warranty of any kind, whether express or implied.
14 */ 14 */
15 15
16#include <linux/amba/pl08x.h>
16#include <linux/of.h> 17#include <linux/of.h>
17#include <linux/of_address.h> 18#include <linux/of_address.h>
18#include <linux/of_irq.h> 19#include <linux/of_irq.h>
19#include <linux/of_platform.h> 20#include <linux/of_platform.h>
21#include <asm/hardware/pl080.h>
20#include <asm/hardware/vic.h> 22#include <asm/hardware/vic.h>
21#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
24#include <plat/pl080.h>
22#include <mach/generic.h> 25#include <mach/generic.h>
23#include <mach/hardware.h> 26#include <mach/hardware.h>
24 27
28/* dmac device registration */
29static struct pl08x_channel_data spear600_dma_info[] = {
30 {
31 .bus_id = "ssp1_rx",
32 .min_signal = 0,
33 .max_signal = 0,
34 .muxval = 0,
35 .cctl = 0,
36 .periph_buses = PL08X_AHB1,
37 }, {
38 .bus_id = "ssp1_tx",
39 .min_signal = 1,
40 .max_signal = 1,
41 .muxval = 0,
42 .cctl = 0,
43 .periph_buses = PL08X_AHB1,
44 }, {
45 .bus_id = "uart0_rx",
46 .min_signal = 2,
47 .max_signal = 2,
48 .muxval = 0,
49 .cctl = 0,
50 .periph_buses = PL08X_AHB1,
51 }, {
52 .bus_id = "uart0_tx",
53 .min_signal = 3,
54 .max_signal = 3,
55 .muxval = 0,
56 .cctl = 0,
57 .periph_buses = PL08X_AHB1,
58 }, {
59 .bus_id = "uart1_rx",
60 .min_signal = 4,
61 .max_signal = 4,
62 .muxval = 0,
63 .cctl = 0,
64 .periph_buses = PL08X_AHB1,
65 }, {
66 .bus_id = "uart1_tx",
67 .min_signal = 5,
68 .max_signal = 5,
69 .muxval = 0,
70 .cctl = 0,
71 .periph_buses = PL08X_AHB1,
72 }, {
73 .bus_id = "ssp2_rx",
74 .min_signal = 6,
75 .max_signal = 6,
76 .muxval = 0,
77 .cctl = 0,
78 .periph_buses = PL08X_AHB2,
79 }, {
80 .bus_id = "ssp2_tx",
81 .min_signal = 7,
82 .max_signal = 7,
83 .muxval = 0,
84 .cctl = 0,
85 .periph_buses = PL08X_AHB2,
86 }, {
87 .bus_id = "ssp0_rx",
88 .min_signal = 8,
89 .max_signal = 8,
90 .muxval = 0,
91 .cctl = 0,
92 .periph_buses = PL08X_AHB1,
93 }, {
94 .bus_id = "ssp0_tx",
95 .min_signal = 9,
96 .max_signal = 9,
97 .muxval = 0,
98 .cctl = 0,
99 .periph_buses = PL08X_AHB1,
100 }, {
101 .bus_id = "i2c_rx",
102 .min_signal = 10,
103 .max_signal = 10,
104 .muxval = 0,
105 .cctl = 0,
106 .periph_buses = PL08X_AHB1,
107 }, {
108 .bus_id = "i2c_tx",
109 .min_signal = 11,
110 .max_signal = 11,
111 .muxval = 0,
112 .cctl = 0,
113 .periph_buses = PL08X_AHB1,
114 }, {
115 .bus_id = "irda",
116 .min_signal = 12,
117 .max_signal = 12,
118 .muxval = 0,
119 .cctl = 0,
120 .periph_buses = PL08X_AHB1,
121 }, {
122 .bus_id = "adc",
123 .min_signal = 13,
124 .max_signal = 13,
125 .muxval = 0,
126 .cctl = 0,
127 .periph_buses = PL08X_AHB2,
128 }, {
129 .bus_id = "to_jpeg",
130 .min_signal = 14,
131 .max_signal = 14,
132 .muxval = 0,
133 .cctl = 0,
134 .periph_buses = PL08X_AHB1,
135 }, {
136 .bus_id = "from_jpeg",
137 .min_signal = 15,
138 .max_signal = 15,
139 .muxval = 0,
140 .cctl = 0,
141 .periph_buses = PL08X_AHB1,
142 }, {
143 .bus_id = "ras0_rx",
144 .min_signal = 0,
145 .max_signal = 0,
146 .muxval = 1,
147 .cctl = 0,
148 .periph_buses = PL08X_AHB1,
149 }, {
150 .bus_id = "ras0_tx",
151 .min_signal = 1,
152 .max_signal = 1,
153 .muxval = 1,
154 .cctl = 0,
155 .periph_buses = PL08X_AHB1,
156 }, {
157 .bus_id = "ras1_rx",
158 .min_signal = 2,
159 .max_signal = 2,
160 .muxval = 1,
161 .cctl = 0,
162 .periph_buses = PL08X_AHB1,
163 }, {
164 .bus_id = "ras1_tx",
165 .min_signal = 3,
166 .max_signal = 3,
167 .muxval = 1,
168 .cctl = 0,
169 .periph_buses = PL08X_AHB1,
170 }, {
171 .bus_id = "ras2_rx",
172 .min_signal = 4,
173 .max_signal = 4,
174 .muxval = 1,
175 .cctl = 0,
176 .periph_buses = PL08X_AHB1,
177 }, {
178 .bus_id = "ras2_tx",
179 .min_signal = 5,
180 .max_signal = 5,
181 .muxval = 1,
182 .cctl = 0,
183 .periph_buses = PL08X_AHB1,
184 }, {
185 .bus_id = "ras3_rx",
186 .min_signal = 6,
187 .max_signal = 6,
188 .muxval = 1,
189 .cctl = 0,
190 .periph_buses = PL08X_AHB1,
191 }, {
192 .bus_id = "ras3_tx",
193 .min_signal = 7,
194 .max_signal = 7,
195 .muxval = 1,
196 .cctl = 0,
197 .periph_buses = PL08X_AHB1,
198 }, {
199 .bus_id = "ras4_rx",
200 .min_signal = 8,
201 .max_signal = 8,
202 .muxval = 1,
203 .cctl = 0,
204 .periph_buses = PL08X_AHB1,
205 }, {
206 .bus_id = "ras4_tx",
207 .min_signal = 9,
208 .max_signal = 9,
209 .muxval = 1,
210 .cctl = 0,
211 .periph_buses = PL08X_AHB1,
212 }, {
213 .bus_id = "ras5_rx",
214 .min_signal = 10,
215 .max_signal = 10,
216 .muxval = 1,
217 .cctl = 0,
218 .periph_buses = PL08X_AHB1,
219 }, {
220 .bus_id = "ras5_tx",
221 .min_signal = 11,
222 .max_signal = 11,
223 .muxval = 1,
224 .cctl = 0,
225 .periph_buses = PL08X_AHB1,
226 }, {
227 .bus_id = "ras6_rx",
228 .min_signal = 12,
229 .max_signal = 12,
230 .muxval = 1,
231 .cctl = 0,
232 .periph_buses = PL08X_AHB1,
233 }, {
234 .bus_id = "ras6_tx",
235 .min_signal = 13,
236 .max_signal = 13,
237 .muxval = 1,
238 .cctl = 0,
239 .periph_buses = PL08X_AHB1,
240 }, {
241 .bus_id = "ras7_rx",
242 .min_signal = 14,
243 .max_signal = 14,
244 .muxval = 1,
245 .cctl = 0,
246 .periph_buses = PL08X_AHB1,
247 }, {
248 .bus_id = "ras7_tx",
249 .min_signal = 15,
250 .max_signal = 15,
251 .muxval = 1,
252 .cctl = 0,
253 .periph_buses = PL08X_AHB1,
254 }, {
255 .bus_id = "ext0_rx",
256 .min_signal = 0,
257 .max_signal = 0,
258 .muxval = 2,
259 .cctl = 0,
260 .periph_buses = PL08X_AHB2,
261 }, {
262 .bus_id = "ext0_tx",
263 .min_signal = 1,
264 .max_signal = 1,
265 .muxval = 2,
266 .cctl = 0,
267 .periph_buses = PL08X_AHB2,
268 }, {
269 .bus_id = "ext1_rx",
270 .min_signal = 2,
271 .max_signal = 2,
272 .muxval = 2,
273 .cctl = 0,
274 .periph_buses = PL08X_AHB2,
275 }, {
276 .bus_id = "ext1_tx",
277 .min_signal = 3,
278 .max_signal = 3,
279 .muxval = 2,
280 .cctl = 0,
281 .periph_buses = PL08X_AHB2,
282 }, {
283 .bus_id = "ext2_rx",
284 .min_signal = 4,
285 .max_signal = 4,
286 .muxval = 2,
287 .cctl = 0,
288 .periph_buses = PL08X_AHB2,
289 }, {
290 .bus_id = "ext2_tx",
291 .min_signal = 5,
292 .max_signal = 5,
293 .muxval = 2,
294 .cctl = 0,
295 .periph_buses = PL08X_AHB2,
296 }, {
297 .bus_id = "ext3_rx",
298 .min_signal = 6,
299 .max_signal = 6,
300 .muxval = 2,
301 .cctl = 0,
302 .periph_buses = PL08X_AHB2,
303 }, {
304 .bus_id = "ext3_tx",
305 .min_signal = 7,
306 .max_signal = 7,
307 .muxval = 2,
308 .cctl = 0,
309 .periph_buses = PL08X_AHB2,
310 }, {
311 .bus_id = "ext4_rx",
312 .min_signal = 8,
313 .max_signal = 8,
314 .muxval = 2,
315 .cctl = 0,
316 .periph_buses = PL08X_AHB2,
317 }, {
318 .bus_id = "ext4_tx",
319 .min_signal = 9,
320 .max_signal = 9,
321 .muxval = 2,
322 .cctl = 0,
323 .periph_buses = PL08X_AHB2,
324 }, {
325 .bus_id = "ext5_rx",
326 .min_signal = 10,
327 .max_signal = 10,
328 .muxval = 2,
329 .cctl = 0,
330 .periph_buses = PL08X_AHB2,
331 }, {
332 .bus_id = "ext5_tx",
333 .min_signal = 11,
334 .max_signal = 11,
335 .muxval = 2,
336 .cctl = 0,
337 .periph_buses = PL08X_AHB2,
338 }, {
339 .bus_id = "ext6_rx",
340 .min_signal = 12,
341 .max_signal = 12,
342 .muxval = 2,
343 .cctl = 0,
344 .periph_buses = PL08X_AHB2,
345 }, {
346 .bus_id = "ext6_tx",
347 .min_signal = 13,
348 .max_signal = 13,
349 .muxval = 2,
350 .cctl = 0,
351 .periph_buses = PL08X_AHB2,
352 }, {
353 .bus_id = "ext7_rx",
354 .min_signal = 14,
355 .max_signal = 14,
356 .muxval = 2,
357 .cctl = 0,
358 .periph_buses = PL08X_AHB2,
359 }, {
360 .bus_id = "ext7_tx",
361 .min_signal = 15,
362 .max_signal = 15,
363 .muxval = 2,
364 .cctl = 0,
365 .periph_buses = PL08X_AHB2,
366 },
367};
368
369struct pl08x_platform_data pl080_plat_data = {
370 .memcpy_channel = {
371 .bus_id = "memcpy",
372 .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
373 PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
374 PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
375 PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
376 PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
377 PL080_CONTROL_PROT_SYS),
378 },
379 .lli_buses = PL08X_AHB1,
380 .mem_buses = PL08X_AHB1,
381 .get_signal = pl080_get_signal,
382 .put_signal = pl080_put_signal,
383 .slave_channels = spear600_dma_info,
384 .num_slave_channels = ARRAY_SIZE(spear600_dma_info),
385};
386
25/* Following will create static virtual/physical mappings */ 387/* Following will create static virtual/physical mappings */
26static struct map_desc spear6xx_io_desc[] __initdata = { 388static struct map_desc spear6xx_io_desc[] __initdata = {
27 { 389 {
@@ -91,9 +453,17 @@ struct sys_timer spear6xx_timer = {
91 .init = spear6xx_timer_init, 453 .init = spear6xx_timer_init,
92}; 454};
93 455
456/* Add auxdata to pass platform data */
457struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
458 OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
459 &pl080_plat_data),
460 {}
461};
462
94static void __init spear600_dt_init(void) 463static void __init spear600_dt_init(void)
95{ 464{
96 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 465 of_platform_populate(NULL, of_default_bus_match_table,
466 spear6xx_auxdata_lookup, NULL);
97} 467}
98 468
99static const char *spear600_dt_board_compat[] = { 469static const char *spear600_dt_board_compat[] = {
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 1bb3dbce8810..387655b5ce05 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -9,9 +9,11 @@ choice
9 default ARCH_SPEAR3XX 9 default ARCH_SPEAR3XX
10 10
11config ARCH_SPEAR3XX 11config ARCH_SPEAR3XX
12 bool "SPEAr3XX" 12 bool "ST SPEAr3xx with Device Tree"
13 select ARM_VIC 13 select ARM_VIC
14 select CPU_ARM926T 14 select CPU_ARM926T
15 select USE_OF
16 select PINCTRL
15 help 17 help
16 Supports for ARM's SPEAR3XX family 18 Supports for ARM's SPEAR3XX family
17 19
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index 8c0cb6a965a3..38f1235f4632 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -3,6 +3,6 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := restart.o time.o 6obj-y := restart.o time.o pl080.o
7 7
8obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o 8obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o
diff --git a/arch/arm/plat-spear/include/plat/padmux.h b/arch/arm/plat-spear/include/plat/padmux.h
deleted file mode 100644
index 877f3adcf610..000000000000
--- a/arch/arm/plat-spear/include/plat/padmux.h
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * arch/arm/plat-spear/include/plat/padmux.h
3 *
4 * SPEAr platform specific gpio pads muxing file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __PLAT_PADMUX_H
15#define __PLAT_PADMUX_H
16
17#include <linux/types.h>
18
19/*
20 * struct pmx_reg: configuration structure for mode reg and mux reg
21 *
22 * offset: offset of mode reg
23 * mask: mask of mode reg
24 */
25struct pmx_reg {
26 u32 offset;
27 u32 mask;
28};
29
30/*
31 * struct pmx_dev_mode: configuration structure every group of modes of a device
32 *
33 * ids: all modes for this configuration
34 * mask: mask for supported mode
35 */
36struct pmx_dev_mode {
37 u32 ids;
38 u32 mask;
39};
40
41/*
42 * struct pmx_mode: mode definition structure
43 *
44 * name: mode name
45 * mask: mode mask
46 */
47struct pmx_mode {
48 char *name;
49 u32 id;
50 u32 mask;
51};
52
53/*
54 * struct pmx_dev: device definition structure
55 *
56 * name: device name
57 * modes: device configuration array for different modes supported
58 * mode_count: size of modes array
59 * is_active: is peripheral active/enabled
60 * enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg
61 */
62struct pmx_dev {
63 char *name;
64 struct pmx_dev_mode *modes;
65 u8 mode_count;
66 bool is_active;
67 bool enb_on_reset;
68};
69
70/*
71 * struct pmx_driver: driver definition structure
72 *
73 * mode: mode to be set
74 * devs: array of pointer to pmx devices
75 * devs_count: ARRAY_SIZE of devs
76 * base: base address of soc config registers
77 * mode_reg: structure of mode config register
78 * mux_reg: structure of device mux config register
79 */
80struct pmx_driver {
81 struct pmx_mode *mode;
82 struct pmx_dev **devs;
83 u8 devs_count;
84 u32 *base;
85 struct pmx_reg mode_reg;
86 struct pmx_reg mux_reg;
87};
88
89/* pmx functions */
90int pmx_register(struct pmx_driver *driver);
91
92#endif /* __PLAT_PADMUX_H */
diff --git a/arch/arm/plat-spear/include/plat/pl080.h b/arch/arm/plat-spear/include/plat/pl080.h
new file mode 100644
index 000000000000..e14a3e4932f9
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/pl080.h
@@ -0,0 +1,21 @@
1/*
2 * arch/arm/plat-spear/include/plat/pl080.h
3 *
4 * DMAC pl080 definitions for SPEAr platform
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __PLAT_PL080_H
15#define __PLAT_PL080_H
16
17struct pl08x_dma_chan;
18int pl080_get_signal(struct pl08x_dma_chan *ch);
19void pl080_put_signal(struct pl08x_dma_chan *ch);
20
21#endif /* __PLAT_PL080_H */
diff --git a/arch/arm/plat-spear/padmux.c b/arch/arm/plat-spear/padmux.c
deleted file mode 100644
index 555eec6dc1cb..000000000000
--- a/arch/arm/plat-spear/padmux.c
+++ /dev/null
@@ -1,164 +0,0 @@
1/*
2 * arch/arm/plat-spear/include/plat/padmux.c
3 *
4 * SPEAr platform specific gpio pads muxing source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/slab.h>
17#include <plat/padmux.h>
18
19/*
20 * struct pmx: pmx definition structure
21 *
22 * base: base address of configuration registers
23 * mode_reg: mode configurations
24 * mux_reg: muxing configurations
25 * active_mode: pointer to current active mode
26 */
27struct pmx {
28 u32 base;
29 struct pmx_reg mode_reg;
30 struct pmx_reg mux_reg;
31 struct pmx_mode *active_mode;
32};
33
34static struct pmx *pmx;
35
36/**
37 * pmx_mode_set - Enables an multiplexing mode
38 * @mode - pointer to pmx mode
39 *
40 * It will set mode of operation in hardware.
41 * Returns -ve on Err otherwise 0
42 */
43static int pmx_mode_set(struct pmx_mode *mode)
44{
45 u32 val;
46
47 if (!mode->name)
48 return -EFAULT;
49
50 pmx->active_mode = mode;
51
52 val = readl(pmx->base + pmx->mode_reg.offset);
53 val &= ~pmx->mode_reg.mask;
54 val |= mode->mask & pmx->mode_reg.mask;
55 writel(val, pmx->base + pmx->mode_reg.offset);
56
57 return 0;
58}
59
60/**
61 * pmx_devs_enable - Enables list of devices
62 * @devs - pointer to pmx device array
63 * @count - number of devices to enable
64 *
65 * It will enable pads for all required peripherals once and only once.
66 * If peripheral is not supported by current mode then request is rejected.
67 * Conflicts between peripherals are not handled and peripherals will be
68 * enabled in the order they are present in pmx_dev array.
69 * In case of conflicts last peripheral enabled will be present.
70 * Returns -ve on Err otherwise 0
71 */
72static int pmx_devs_enable(struct pmx_dev **devs, u8 count)
73{
74 u32 val, i, mask;
75
76 if (!count)
77 return -EINVAL;
78
79 val = readl(pmx->base + pmx->mux_reg.offset);
80 for (i = 0; i < count; i++) {
81 u8 j = 0;
82
83 if (!devs[i]->name || !devs[i]->modes) {
84 printk(KERN_ERR "padmux: dev name or modes is null\n");
85 continue;
86 }
87 /* check if peripheral exists in active mode */
88 if (pmx->active_mode) {
89 bool found = false;
90 for (j = 0; j < devs[i]->mode_count; j++) {
91 if (devs[i]->modes[j].ids &
92 pmx->active_mode->id) {
93 found = true;
94 break;
95 }
96 }
97 if (found == false) {
98 printk(KERN_ERR "%s device not available in %s"\
99 "mode\n", devs[i]->name,
100 pmx->active_mode->name);
101 continue;
102 }
103 }
104
105 /* enable peripheral */
106 mask = devs[i]->modes[j].mask & pmx->mux_reg.mask;
107 if (devs[i]->enb_on_reset)
108 val &= ~mask;
109 else
110 val |= mask;
111
112 devs[i]->is_active = true;
113 }
114 writel(val, pmx->base + pmx->mux_reg.offset);
115 kfree(pmx);
116
117 /* this will ensure that multiplexing can't be changed now */
118 pmx = (struct pmx *)-1;
119
120 return 0;
121}
122
123/**
124 * pmx_register - registers a platform requesting pad mux feature
125 * @driver - pointer to driver structure containing driver specific parameters
126 *
127 * Also this must be called only once. This will allocate memory for pmx
128 * structure, will call pmx_mode_set, will call pmx_devs_enable.
129 * Returns -ve on Err otherwise 0
130 */
131int pmx_register(struct pmx_driver *driver)
132{
133 int ret = 0;
134
135 if (pmx)
136 return -EPERM;
137 if (!driver->base || !driver->devs)
138 return -EFAULT;
139
140 pmx = kzalloc(sizeof(*pmx), GFP_KERNEL);
141 if (!pmx)
142 return -ENOMEM;
143
144 pmx->base = (u32)driver->base;
145 pmx->mode_reg.offset = driver->mode_reg.offset;
146 pmx->mode_reg.mask = driver->mode_reg.mask;
147 pmx->mux_reg.offset = driver->mux_reg.offset;
148 pmx->mux_reg.mask = driver->mux_reg.mask;
149
150 /* choose mode to enable */
151 if (driver->mode) {
152 ret = pmx_mode_set(driver->mode);
153 if (ret)
154 goto pmx_fail;
155 }
156 ret = pmx_devs_enable(driver->devs, driver->devs_count);
157 if (ret)
158 goto pmx_fail;
159
160 return 0;
161
162pmx_fail:
163 return ret;
164}
diff --git a/arch/arm/plat-spear/pl080.c b/arch/arm/plat-spear/pl080.c
new file mode 100644
index 000000000000..d53d75e1af5e
--- /dev/null
+++ b/arch/arm/plat-spear/pl080.c
@@ -0,0 +1,79 @@
1/*
2 * arch/arm/plat-spear/pl080.c
3 *
4 * DMAC pl080 definitions for SPEAr platform
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/amba/pl08x.h>
15#include <linux/amba/bus.h>
16#include <linux/bug.h>
17#include <linux/err.h>
18#include <linux/io.h>
19#include <linux/spinlock_types.h>
20#include <mach/misc_regs.h>
21
22static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x);
23
24struct {
25 unsigned char busy;
26 unsigned char val;
27} signals[16] = {{0, 0}, };
28
29int pl080_get_signal(struct pl08x_dma_chan *ch)
30{
31 const struct pl08x_channel_data *cd = ch->cd;
32 unsigned int signal = cd->min_signal, val;
33 unsigned long flags;
34
35 spin_lock_irqsave(&lock, flags);
36
37 /* Return if signal is already acquired by somebody else */
38 if (signals[signal].busy &&
39 (signals[signal].val != cd->muxval)) {
40 spin_unlock_irqrestore(&lock, flags);
41 return -EBUSY;
42 }
43
44 /* If acquiring for the first time, configure it */
45 if (!signals[signal].busy) {
46 val = readl(DMA_CHN_CFG);
47
48 /*
49 * Each request line has two bits in DMA_CHN_CFG register. To
50 * goto the bits of current request line, do left shift of
51 * value by 2 * signal number.
52 */
53 val &= ~(0x3 << (signal * 2));
54 val |= cd->muxval << (signal * 2);
55 writel(val, DMA_CHN_CFG);
56 }
57
58 signals[signal].busy++;
59 signals[signal].val = cd->muxval;
60 spin_unlock_irqrestore(&lock, flags);
61
62 return signal;
63}
64
65void pl080_put_signal(struct pl08x_dma_chan *ch)
66{
67 const struct pl08x_channel_data *cd = ch->cd;
68 unsigned long flags;
69
70 spin_lock_irqsave(&lock, flags);
71
72 /* if signal is not used */
73 if (!signals[cd->min_signal].busy)
74 BUG();
75
76 signals[cd->min_signal].busy--;
77
78 spin_unlock_irqrestore(&lock, flags);
79}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-04 12:52:38 -0500