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-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c55
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c6
-rw-r--r--arch/arm/mach-omap2/board-zoom-peripherals.c10
-rw-r--r--arch/arm/mach-omap2/clock.c27
-rw-r--r--arch/arm/mach-omap2/clock.h3
-rw-r--r--arch/arm/mach-omap2/clock2420_data.c22
-rw-r--r--arch/arm/mach-omap2/clock2430_data.c32
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c44
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c215
-rw-r--r--arch/arm/mach-omap2/clockdomain.c210
-rw-r--r--arch/arm/mach-omap2/clockdomain.h11
-rw-r--r--arch/arm/mach-omap2/clockdomain2xxx_3xxx.c6
-rw-r--r--arch/arm/mach-omap2/clockdomain44xx.c13
-rw-r--r--arch/arm/mach-omap2/clockdomains44xx_data.c2
-rw-r--r--arch/arm/mach-omap2/cm44xx.h8
-rw-r--r--arch/arm/mach-omap2/cminst44xx.c150
-rw-r--r--arch/arm/mach-omap2/cminst44xx.h10
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c234
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c412
-rw-r--r--arch/arm/mach-omap2/pm.c4
-rw-r--r--arch/arm/mach-omap2/prcm.c2
-rw-r--r--arch/arm/mach-omap2/prm44xx.c145
-rw-r--r--arch/arm/mach-omap2/prm44xx.h10
-rw-r--r--arch/arm/mach-omap2/prminst44xx.c112
-rw-r--r--arch/arm/mach-omap2/prminst44xx.h12
-rw-r--r--arch/arm/mach-omap2/twl-common.c10
-rw-r--r--arch/arm/plat-omap/clock.c39
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h12
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h14
-rw-r--r--arch/arm/plat-omap/omap_device.c85
30 files changed, 1424 insertions, 491 deletions
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index a7c0b31fd084..c7cef44c75d4 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -345,11 +345,40 @@ static struct platform_device sdp4430_lcd_device = {
345 .id = -1, 345 .id = -1,
346}; 346};
347 347
348static struct regulator_consumer_supply sdp4430_vbat_supply[] = {
349 REGULATOR_SUPPLY("vddvibl", "twl6040-vibra"),
350 REGULATOR_SUPPLY("vddvibr", "twl6040-vibra"),
351};
352
353static struct regulator_init_data sdp4430_vbat_data = {
354 .constraints = {
355 .always_on = 1,
356 },
357 .num_consumer_supplies = ARRAY_SIZE(sdp4430_vbat_supply),
358 .consumer_supplies = sdp4430_vbat_supply,
359};
360
361static struct fixed_voltage_config sdp4430_vbat_pdata = {
362 .supply_name = "VBAT",
363 .microvolts = 3750000,
364 .init_data = &sdp4430_vbat_data,
365 .gpio = -EINVAL,
366};
367
368static struct platform_device sdp4430_vbat = {
369 .name = "reg-fixed-voltage",
370 .id = -1,
371 .dev = {
372 .platform_data = &sdp4430_vbat_pdata,
373 },
374};
375
348static struct platform_device *sdp4430_devices[] __initdata = { 376static struct platform_device *sdp4430_devices[] __initdata = {
349 &sdp4430_lcd_device, 377 &sdp4430_lcd_device,
350 &sdp4430_gpio_keys_device, 378 &sdp4430_gpio_keys_device,
351 &sdp4430_leds_gpio, 379 &sdp4430_leds_gpio,
352 &sdp4430_leds_pwm, 380 &sdp4430_leds_pwm,
381 &sdp4430_vbat,
353}; 382};
354 383
355static struct omap_lcd_config sdp4430_lcd_config __initdata = { 384static struct omap_lcd_config sdp4430_lcd_config __initdata = {
@@ -505,7 +534,33 @@ static struct regulator_init_data sdp4430_vusim = {
505 }, 534 },
506}; 535};
507 536
537static struct twl4030_codec_data twl6040_codec = {
538 /* single-step ramp for headset and handsfree */
539 .hs_left_step = 0x0f,
540 .hs_right_step = 0x0f,
541 .hf_left_step = 0x1d,
542 .hf_right_step = 0x1d,
543};
544
545static struct twl4030_vibra_data twl6040_vibra = {
546 .vibldrv_res = 8,
547 .vibrdrv_res = 3,
548 .viblmotor_res = 10,
549 .vibrmotor_res = 10,
550 .vddvibl_uV = 0, /* fixed volt supply - VBAT */
551 .vddvibr_uV = 0, /* fixed volt supply - VBAT */
552};
553
554static struct twl4030_audio_data twl6040_audio = {
555 .codec = &twl6040_codec,
556 .vibra = &twl6040_vibra,
557 .audpwron_gpio = 127,
558 .naudint_irq = OMAP44XX_IRQ_SYS_2N,
559 .irq_base = TWL6040_CODEC_IRQ_BASE,
560};
561
508static struct twl4030_platform_data sdp4430_twldata = { 562static struct twl4030_platform_data sdp4430_twldata = {
563 .audio = &twl6040_audio,
509 /* Regulators */ 564 /* Regulators */
510 .vusim = &sdp4430_vusim, 565 .vusim = &sdp4430_vusim,
511 .vaux1 = &sdp4430_vaux1, 566 .vaux1 = &sdp4430_vaux1,
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 0c9e0f28ed07..cc503aa89c5e 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -864,11 +864,11 @@ static struct twl4030_power_data rx51_t2scripts_data __initdata = {
864 .resource_config = twl4030_rconfig, 864 .resource_config = twl4030_rconfig,
865}; 865};
866 866
867struct twl4030_codec_vibra_data rx51_vibra_data __initdata = { 867struct twl4030_vibra_data rx51_vibra_data __initdata = {
868 .coexist = 0, 868 .coexist = 0,
869}; 869};
870 870
871struct twl4030_codec_data rx51_codec_data __initdata = { 871struct twl4030_audio_data rx51_audio_data __initdata = {
872 .audio_mclk = 26000000, 872 .audio_mclk = 26000000,
873 .vibra = &rx51_vibra_data, 873 .vibra = &rx51_vibra_data,
874}; 874};
@@ -878,7 +878,7 @@ static struct twl4030_platform_data rx51_twldata __initdata = {
878 .gpio = &rx51_gpio_data, 878 .gpio = &rx51_gpio_data,
879 .keypad = &rx51_kp_data, 879 .keypad = &rx51_kp_data,
880 .power = &rx51_t2scripts_data, 880 .power = &rx51_t2scripts_data,
881 .codec = &rx51_codec_data, 881 .audio = &rx51_audio_data,
882 882
883 .vaux1 = &rx51_vaux1, 883 .vaux1 = &rx51_vaux1,
884 .vaux2 = &rx51_vaux2, 884 .vaux2 = &rx51_vaux2,
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 13a644233667..6d0aa4fcb7c3 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -274,12 +274,12 @@ static int __init omap_i2c_init(void)
274 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2); 274 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
275 275
276 if (machine_is_omap_zoom2()) { 276 if (machine_is_omap_zoom2()) {
277 struct twl4030_codec_audio_data *audio_data; 277 struct twl4030_codec_data *codec_data;
278 audio_data = zoom_twldata.codec->audio; 278 codec_data = zoom_twldata.audio->codec;
279 279
280 audio_data->ramp_delay_value = 3; /* 161 ms */ 280 codec_data->ramp_delay_value = 3; /* 161 ms */
281 audio_data->hs_extmute = 1; 281 codec_data->hs_extmute = 1;
282 audio_data->set_hs_extmute = zoom2_set_hs_extmute; 282 codec_data->set_hs_extmute = zoom2_set_hs_extmute;
283 } 283 }
284 omap_pmic_init(1, 2400, "twl5030", INT_34XX_SYS_NIRQ, &zoom_twldata); 284 omap_pmic_init(1, 2400, "twl5030", INT_34XX_SYS_NIRQ, &zoom_twldata);
285 omap_register_i2c_bus(2, 400, NULL, 0); 285 omap_register_i2c_bus(2, 400, NULL, 0);
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index bf9c36c7dffd..1f3481f8d695 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -38,6 +38,14 @@
38u8 cpu_mask; 38u8 cpu_mask;
39 39
40/* 40/*
41 * clkdm_control: if true, then when a clock is enabled in the
42 * hardware, its clockdomain will first be enabled; and when a clock
43 * is disabled in the hardware, its clockdomain will be disabled
44 * afterwards.
45 */
46static bool clkdm_control = true;
47
48/*
41 * OMAP2+ specific clock functions 49 * OMAP2+ specific clock functions
42 */ 50 */
43 51
@@ -100,6 +108,19 @@ void omap2_init_clk_clkdm(struct clk *clk)
100} 108}
101 109
102/** 110/**
111 * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable
112 *
113 * Prevent the OMAP clock code from calling into the clockdomain code
114 * when a hardware clock in that clockdomain is enabled or disabled.
115 * Intended to be called at init time from omap*_clk_init(). No
116 * return value.
117 */
118void __init omap2_clk_disable_clkdm_control(void)
119{
120 clkdm_control = false;
121}
122
123/**
103 * omap2_clk_dflt_find_companion - find companion clock to @clk 124 * omap2_clk_dflt_find_companion - find companion clock to @clk
104 * @clk: struct clk * to find the companion clock of 125 * @clk: struct clk * to find the companion clock of
105 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in 126 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
@@ -268,7 +289,7 @@ void omap2_clk_disable(struct clk *clk)
268 clk->ops->disable(clk); 289 clk->ops->disable(clk);
269 } 290 }
270 291
271 if (clk->clkdm) 292 if (clkdm_control && clk->clkdm)
272 clkdm_clk_disable(clk->clkdm, clk); 293 clkdm_clk_disable(clk->clkdm, clk);
273 294
274 if (clk->parent) 295 if (clk->parent)
@@ -308,7 +329,7 @@ int omap2_clk_enable(struct clk *clk)
308 } 329 }
309 } 330 }
310 331
311 if (clk->clkdm) { 332 if (clkdm_control && clk->clkdm) {
312 ret = clkdm_clk_enable(clk->clkdm, clk); 333 ret = clkdm_clk_enable(clk->clkdm, clk);
313 if (ret) { 334 if (ret) {
314 WARN(1, "clock: %s: could not enable clockdomain %s: " 335 WARN(1, "clock: %s: could not enable clockdomain %s: "
@@ -330,7 +351,7 @@ int omap2_clk_enable(struct clk *clk)
330 return 0; 351 return 0;
331 352
332oce_err3: 353oce_err3:
333 if (clk->clkdm) 354 if (clkdm_control && clk->clkdm)
334 clkdm_clk_disable(clk->clkdm, clk); 355 clkdm_clk_disable(clk->clkdm, clk);
335oce_err2: 356oce_err2:
336 if (clk->parent) 357 if (clk->parent)
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index e10ff2b54844..48ac568881bd 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -16,6 +16,8 @@
16#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H 16#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
17#define __ARCH_ARM_MACH_OMAP2_CLOCK_H 17#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
18 18
19#include <linux/kernel.h>
20
19#include <plat/clock.h> 21#include <plat/clock.h>
20 22
21/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ 23/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
@@ -72,6 +74,7 @@ void omap2_clk_disable_unused(struct clk *clk);
72#endif 74#endif
73 75
74void omap2_init_clk_clkdm(struct clk *clk); 76void omap2_init_clk_clkdm(struct clk *clk);
77void __init omap2_clk_disable_clkdm_control(void);
75 78
76/* clkt_clksel.c public functions */ 79/* clkt_clksel.c public functions */
77u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, 80u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 2926d028b6e9..debc040872f1 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1805,9 +1805,9 @@ static struct omap_clk omap2420_clks[] = {
1805 CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), 1805 CLK(NULL, "gfx_ick", &gfx_ick, CK_242X),
1806 /* DSS domain clocks */ 1806 /* DSS domain clocks */
1807 CLK("omapdss_dss", "ick", &dss_ick, CK_242X), 1807 CLK("omapdss_dss", "ick", &dss_ick, CK_242X),
1808 CLK("omapdss_dss", "fck", &dss1_fck, CK_242X), 1808 CLK(NULL, "dss1_fck", &dss1_fck, CK_242X),
1809 CLK("omapdss_dss", "sys_clk", &dss2_fck, CK_242X), 1809 CLK(NULL, "dss2_fck", &dss2_fck, CK_242X),
1810 CLK("omapdss_dss", "tv_clk", &dss_54m_fck, CK_242X), 1810 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X),
1811 /* L3 domain clocks */ 1811 /* L3 domain clocks */
1812 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X), 1812 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X),
1813 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X), 1813 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X),
@@ -1844,13 +1844,13 @@ static struct omap_clk omap2420_clks[] = {
1844 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X), 1844 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X),
1845 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X), 1845 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X),
1846 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X), 1846 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X),
1847 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_242X), 1847 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X),
1848 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X), 1848 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X),
1849 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_242X), 1849 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X),
1850 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X), 1850 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X),
1851 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_242X), 1851 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X),
1852 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X), 1852 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X),
1853 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_242X), 1853 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X),
1854 CLK(NULL, "uart1_ick", &uart1_ick, CK_242X), 1854 CLK(NULL, "uart1_ick", &uart1_ick, CK_242X),
1855 CLK(NULL, "uart1_fck", &uart1_fck, CK_242X), 1855 CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
1856 CLK(NULL, "uart2_ick", &uart2_ick, CK_242X), 1856 CLK(NULL, "uart2_ick", &uart2_ick, CK_242X),
@@ -1860,7 +1860,7 @@ static struct omap_clk omap2420_clks[] = {
1860 CLK(NULL, "gpios_ick", &gpios_ick, CK_242X), 1860 CLK(NULL, "gpios_ick", &gpios_ick, CK_242X),
1861 CLK(NULL, "gpios_fck", &gpios_fck, CK_242X), 1861 CLK(NULL, "gpios_fck", &gpios_fck, CK_242X),
1862 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X), 1862 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X),
1863 CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_242X), 1863 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X),
1864 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X), 1864 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X),
1865 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X), 1865 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X),
1866 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X), 1866 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X),
@@ -1880,11 +1880,11 @@ static struct omap_clk omap2420_clks[] = {
1880 CLK(NULL, "eac_ick", &eac_ick, CK_242X), 1880 CLK(NULL, "eac_ick", &eac_ick, CK_242X),
1881 CLK(NULL, "eac_fck", &eac_fck, CK_242X), 1881 CLK(NULL, "eac_fck", &eac_fck, CK_242X),
1882 CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X), 1882 CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
1883 CLK("omap_hdq.1", "fck", &hdq_fck, CK_242X), 1883 CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X),
1884 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X), 1884 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X),
1885 CLK("omap_i2c.1", "fck", &i2c1_fck, CK_242X), 1885 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X),
1886 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X), 1886 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X),
1887 CLK("omap_i2c.2", "fck", &i2c2_fck, CK_242X), 1887 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X),
1888 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), 1888 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
1889 CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), 1889 CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
1890 CLK(NULL, "sdma_ick", &sdma_ick, CK_242X), 1890 CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 0c79d39e3021..96a942e42db1 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1895,9 +1895,9 @@ static struct omap_clk omap2430_clks[] = {
1895 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), 1895 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
1896 /* DSS domain clocks */ 1896 /* DSS domain clocks */
1897 CLK("omapdss_dss", "ick", &dss_ick, CK_243X), 1897 CLK("omapdss_dss", "ick", &dss_ick, CK_243X),
1898 CLK("omapdss_dss", "fck", &dss1_fck, CK_243X), 1898 CLK(NULL, "dss1_fck", &dss1_fck, CK_243X),
1899 CLK("omapdss_dss", "sys_clk", &dss2_fck, CK_243X), 1899 CLK(NULL, "dss2_fck", &dss2_fck, CK_243X),
1900 CLK("omapdss_dss", "tv_clk", &dss_54m_fck, CK_243X), 1900 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X),
1901 /* L3 domain clocks */ 1901 /* L3 domain clocks */
1902 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X), 1902 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X),
1903 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X), 1903 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X),
@@ -1934,21 +1934,21 @@ static struct omap_clk omap2430_clks[] = {
1934 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X), 1934 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
1935 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X), 1935 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
1936 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X), 1936 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
1937 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X), 1937 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X),
1938 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X), 1938 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
1939 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X), 1939 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X),
1940 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), 1940 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
1941 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X), 1941 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X),
1942 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), 1942 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
1943 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X), 1943 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X),
1944 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), 1944 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
1945 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X), 1945 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X),
1946 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X), 1946 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
1947 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X), 1947 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X),
1948 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X), 1948 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
1949 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X), 1949 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X),
1950 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), 1950 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
1951 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X), 1951 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X),
1952 CLK(NULL, "uart1_ick", &uart1_ick, CK_243X), 1952 CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
1953 CLK(NULL, "uart1_fck", &uart1_fck, CK_243X), 1953 CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
1954 CLK(NULL, "uart2_ick", &uart2_ick, CK_243X), 1954 CLK(NULL, "uart2_ick", &uart2_ick, CK_243X),
@@ -1958,7 +1958,7 @@ static struct omap_clk omap2430_clks[] = {
1958 CLK(NULL, "gpios_ick", &gpios_ick, CK_243X), 1958 CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
1959 CLK(NULL, "gpios_fck", &gpios_fck, CK_243X), 1959 CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
1960 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X), 1960 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
1961 CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X), 1961 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X),
1962 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X), 1962 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
1963 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X), 1963 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
1964 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X), 1964 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
@@ -1975,9 +1975,9 @@ static struct omap_clk omap2430_clks[] = {
1975 CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X), 1975 CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
1976 CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X), 1976 CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
1977 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X), 1977 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X),
1978 CLK("omap_i2c.1", "fck", &i2chs1_fck, CK_243X), 1978 CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X),
1979 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X), 1979 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X),
1980 CLK("omap_i2c.2", "fck", &i2chs2_fck, CK_243X), 1980 CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X),
1981 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X), 1981 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
1982 CLK(NULL, "sdma_fck", &sdma_fck, CK_243X), 1982 CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
1983 CLK(NULL, "sdma_ick", &sdma_ick, CK_243X), 1983 CLK(NULL, "sdma_ick", &sdma_ick, CK_243X),
@@ -1990,9 +1990,9 @@ static struct omap_clk omap2430_clks[] = {
1990 CLK(NULL, "usb_fck", &usb_fck, CK_243X), 1990 CLK(NULL, "usb_fck", &usb_fck, CK_243X),
1991 CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X), 1991 CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
1992 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X), 1992 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
1993 CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_243X), 1993 CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X),
1994 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X), 1994 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
1995 CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_243X), 1995 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X),
1996 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), 1996 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
1997 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), 1997 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
1998 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), 1998 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 75b119bd9cda..ffd55b1c4396 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3289,25 +3289,25 @@ static struct omap_clk omap3xxx_clks[] = {
3289 CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX), 3289 CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
3290 CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX), 3290 CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
3291 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), 3291 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3292 CLK("omap_hsmmc.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3292 CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3293 CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_3XXX), 3293 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX),
3294 CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX), 3294 CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX),
3295 CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_3XXX), 3295 CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_3XXX),
3296 CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX), 3296 CLK(NULL, "i2c3_fck", &i2c3_fck, CK_3XXX),
3297 CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX), 3297 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_3XXX),
3298 CLK("omap_i2c.1", "fck", &i2c1_fck, CK_3XXX), 3298 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_3XXX),
3299 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_3XXX), 3299 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_3XXX),
3300 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_3XXX), 3300 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_3XXX),
3301 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX), 3301 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX),
3302 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_3XXX), 3302 CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_3XXX),
3303 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_3XXX), 3303 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_3XXX),
3304 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_3XXX), 3304 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_3XXX),
3305 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_3XXX), 3305 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_3XXX),
3306 CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX), 3306 CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX),
3307 CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX), 3307 CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX),
3308 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), 3308 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
3309 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX), 3309 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
3310 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX), 3310 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
3311 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), 3311 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
3312 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX), 3312 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
3313 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), 3313 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
@@ -3356,11 +3356,11 @@ static struct omap_clk omap3xxx_clks[] = {
3356 CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX), 3356 CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX),
3357 CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX), 3357 CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX),
3358 CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX), 3358 CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX),
3359 CLK("omapdss_dss", "fck", &dss1_alwon_fck_3430es1, CK_3430ES1), 3359 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
3360 CLK("omapdss_dss", "fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3360 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3361 CLK("omapdss_dss", "tv_clk", &dss_tv_fck, CK_3XXX), 3361 CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_3XXX),
3362 CLK("omapdss_dss", "video_clk", &dss_96m_fck, CK_3XXX), 3362 CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX),
3363 CLK("omapdss_dss", "sys_clk", &dss2_alwon_fck, CK_3XXX), 3363 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX),
3364 CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1), 3364 CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1),
3365 CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3365 CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3366 CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX), 3366 CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX),
@@ -3385,7 +3385,7 @@ static struct omap_clk omap3xxx_clks[] = {
3385 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX), 3385 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
3386 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX), 3386 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
3387 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX), 3387 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
3388 CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX), 3388 CLK(NULL, "wdt2_fck", &wdt2_fck, CK_3XXX),
3389 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX), 3389 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX),
3390 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX), 3390 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX),
3391 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX), 3391 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
@@ -3436,9 +3436,9 @@ static struct omap_clk omap3xxx_clks[] = {
3436 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX), 3436 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
3437 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX), 3437 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
3438 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX), 3438 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
3439 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_3XXX), 3439 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX),
3440 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_3XXX), 3440 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX),
3441 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_3XXX), 3441 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX),
3442 CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX), 3442 CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
3443 CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX), 3443 CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
3444 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX), 3444 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 25473a1db3e7..2af0e3f00ce1 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -2808,19 +2808,39 @@ static struct clk trace_clk_div_ck = {
2808 2808
2809/* SCRM aux clk nodes */ 2809/* SCRM aux clk nodes */
2810 2810
2811static const struct clksel auxclk_sel[] = { 2811static const struct clksel auxclk_src_sel[] = {
2812 { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, 2812 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
2813 { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates }, 2813 { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
2814 { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates }, 2814 { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
2815 { .parent = NULL }, 2815 { .parent = NULL },
2816}; 2816};
2817 2817
2818static struct clk auxclk0_ck = { 2818static const struct clksel_rate div16_1to16_rates[] = {
2819 .name = "auxclk0_ck", 2819 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
2820 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
2821 { .div = 3, .val = 2, .flags = RATE_IN_4430 },
2822 { .div = 4, .val = 3, .flags = RATE_IN_4430 },
2823 { .div = 5, .val = 4, .flags = RATE_IN_4430 },
2824 { .div = 6, .val = 5, .flags = RATE_IN_4430 },
2825 { .div = 7, .val = 6, .flags = RATE_IN_4430 },
2826 { .div = 8, .val = 7, .flags = RATE_IN_4430 },
2827 { .div = 9, .val = 8, .flags = RATE_IN_4430 },
2828 { .div = 10, .val = 9, .flags = RATE_IN_4430 },
2829 { .div = 11, .val = 10, .flags = RATE_IN_4430 },
2830 { .div = 12, .val = 11, .flags = RATE_IN_4430 },
2831 { .div = 13, .val = 12, .flags = RATE_IN_4430 },
2832 { .div = 14, .val = 13, .flags = RATE_IN_4430 },
2833 { .div = 15, .val = 14, .flags = RATE_IN_4430 },
2834 { .div = 16, .val = 15, .flags = RATE_IN_4430 },
2835 { .div = 0 },
2836};
2837
2838static struct clk auxclk0_src_ck = {
2839 .name = "auxclk0_src_ck",
2820 .parent = &sys_clkin_ck, 2840 .parent = &sys_clkin_ck,
2821 .init = &omap2_init_clksel_parent, 2841 .init = &omap2_init_clksel_parent,
2822 .ops = &clkops_omap2_dflt, 2842 .ops = &clkops_omap2_dflt,
2823 .clksel = auxclk_sel, 2843 .clksel = auxclk_src_sel,
2824 .clksel_reg = OMAP4_SCRM_AUXCLK0, 2844 .clksel_reg = OMAP4_SCRM_AUXCLK0,
2825 .clksel_mask = OMAP4_SRCSELECT_MASK, 2845 .clksel_mask = OMAP4_SRCSELECT_MASK,
2826 .recalc = &omap2_clksel_recalc, 2846 .recalc = &omap2_clksel_recalc,
@@ -2828,12 +2848,29 @@ static struct clk auxclk0_ck = {
2828 .enable_bit = OMAP4_ENABLE_SHIFT, 2848 .enable_bit = OMAP4_ENABLE_SHIFT,
2829}; 2849};
2830 2850
2831static struct clk auxclk1_ck = { 2851static const struct clksel auxclk0_sel[] = {
2832 .name = "auxclk1_ck", 2852 { .parent = &auxclk0_src_ck, .rates = div16_1to16_rates },
2853 { .parent = NULL },
2854};
2855
2856static struct clk auxclk0_ck = {
2857 .name = "auxclk0_ck",
2858 .parent = &auxclk0_src_ck,
2859 .clksel = auxclk0_sel,
2860 .clksel_reg = OMAP4_SCRM_AUXCLK0,
2861 .clksel_mask = OMAP4_CLKDIV_MASK,
2862 .ops = &clkops_null,
2863 .recalc = &omap2_clksel_recalc,
2864 .round_rate = &omap2_clksel_round_rate,
2865 .set_rate = &omap2_clksel_set_rate,
2866};
2867
2868static struct clk auxclk1_src_ck = {
2869 .name = "auxclk1_src_ck",
2833 .parent = &sys_clkin_ck, 2870 .parent = &sys_clkin_ck,
2834 .init = &omap2_init_clksel_parent, 2871 .init = &omap2_init_clksel_parent,
2835 .ops = &clkops_omap2_dflt, 2872 .ops = &clkops_omap2_dflt,
2836 .clksel = auxclk_sel, 2873 .clksel = auxclk_src_sel,
2837 .clksel_reg = OMAP4_SCRM_AUXCLK1, 2874 .clksel_reg = OMAP4_SCRM_AUXCLK1,
2838 .clksel_mask = OMAP4_SRCSELECT_MASK, 2875 .clksel_mask = OMAP4_SRCSELECT_MASK,
2839 .recalc = &omap2_clksel_recalc, 2876 .recalc = &omap2_clksel_recalc,
@@ -2841,12 +2878,29 @@ static struct clk auxclk1_ck = {
2841 .enable_bit = OMAP4_ENABLE_SHIFT, 2878 .enable_bit = OMAP4_ENABLE_SHIFT,
2842}; 2879};
2843 2880
2844static struct clk auxclk2_ck = { 2881static const struct clksel auxclk1_sel[] = {
2845 .name = "auxclk2_ck", 2882 { .parent = &auxclk1_src_ck, .rates = div16_1to16_rates },
2883 { .parent = NULL },
2884};
2885
2886static struct clk auxclk1_ck = {
2887 .name = "auxclk1_ck",
2888 .parent = &auxclk1_src_ck,
2889 .clksel = auxclk1_sel,
2890 .clksel_reg = OMAP4_SCRM_AUXCLK1,
2891 .clksel_mask = OMAP4_CLKDIV_MASK,
2892 .ops = &clkops_null,
2893 .recalc = &omap2_clksel_recalc,
2894 .round_rate = &omap2_clksel_round_rate,
2895 .set_rate = &omap2_clksel_set_rate,
2896};
2897
2898static struct clk auxclk2_src_ck = {
2899 .name = "auxclk2_src_ck",
2846 .parent = &sys_clkin_ck, 2900 .parent = &sys_clkin_ck,
2847 .init = &omap2_init_clksel_parent, 2901 .init = &omap2_init_clksel_parent,
2848 .ops = &clkops_omap2_dflt, 2902 .ops = &clkops_omap2_dflt,
2849 .clksel = auxclk_sel, 2903 .clksel = auxclk_src_sel,
2850 .clksel_reg = OMAP4_SCRM_AUXCLK2, 2904 .clksel_reg = OMAP4_SCRM_AUXCLK2,
2851 .clksel_mask = OMAP4_SRCSELECT_MASK, 2905 .clksel_mask = OMAP4_SRCSELECT_MASK,
2852 .recalc = &omap2_clksel_recalc, 2906 .recalc = &omap2_clksel_recalc,
@@ -2854,12 +2908,29 @@ static struct clk auxclk2_ck = {
2854 .enable_bit = OMAP4_ENABLE_SHIFT, 2908 .enable_bit = OMAP4_ENABLE_SHIFT,
2855}; 2909};
2856 2910
2857static struct clk auxclk3_ck = { 2911static const struct clksel auxclk2_sel[] = {
2858 .name = "auxclk3_ck", 2912 { .parent = &auxclk2_src_ck, .rates = div16_1to16_rates },
2913 { .parent = NULL },
2914};
2915
2916static struct clk auxclk2_ck = {
2917 .name = "auxclk2_ck",
2918 .parent = &auxclk2_src_ck,
2919 .clksel = auxclk2_sel,
2920 .clksel_reg = OMAP4_SCRM_AUXCLK2,
2921 .clksel_mask = OMAP4_CLKDIV_MASK,
2922 .ops = &clkops_null,
2923 .recalc = &omap2_clksel_recalc,
2924 .round_rate = &omap2_clksel_round_rate,
2925 .set_rate = &omap2_clksel_set_rate,
2926};
2927
2928static struct clk auxclk3_src_ck = {
2929 .name = "auxclk3_src_ck",
2859 .parent = &sys_clkin_ck, 2930 .parent = &sys_clkin_ck,
2860 .init = &omap2_init_clksel_parent, 2931 .init = &omap2_init_clksel_parent,
2861 .ops = &clkops_omap2_dflt, 2932 .ops = &clkops_omap2_dflt,
2862 .clksel = auxclk_sel, 2933 .clksel = auxclk_src_sel,
2863 .clksel_reg = OMAP4_SCRM_AUXCLK3, 2934 .clksel_reg = OMAP4_SCRM_AUXCLK3,
2864 .clksel_mask = OMAP4_SRCSELECT_MASK, 2935 .clksel_mask = OMAP4_SRCSELECT_MASK,
2865 .recalc = &omap2_clksel_recalc, 2936 .recalc = &omap2_clksel_recalc,
@@ -2867,12 +2938,29 @@ static struct clk auxclk3_ck = {
2867 .enable_bit = OMAP4_ENABLE_SHIFT, 2938 .enable_bit = OMAP4_ENABLE_SHIFT,
2868}; 2939};
2869 2940
2870static struct clk auxclk4_ck = { 2941static const struct clksel auxclk3_sel[] = {
2871 .name = "auxclk4_ck", 2942 { .parent = &auxclk3_src_ck, .rates = div16_1to16_rates },
2943 { .parent = NULL },
2944};
2945
2946static struct clk auxclk3_ck = {
2947 .name = "auxclk3_ck",
2948 .parent = &auxclk3_src_ck,
2949 .clksel = auxclk3_sel,
2950 .clksel_reg = OMAP4_SCRM_AUXCLK3,
2951 .clksel_mask = OMAP4_CLKDIV_MASK,
2952 .ops = &clkops_null,
2953 .recalc = &omap2_clksel_recalc,
2954 .round_rate = &omap2_clksel_round_rate,
2955 .set_rate = &omap2_clksel_set_rate,
2956};
2957
2958static struct clk auxclk4_src_ck = {
2959 .name = "auxclk4_src_ck",
2872 .parent = &sys_clkin_ck, 2960 .parent = &sys_clkin_ck,
2873 .init = &omap2_init_clksel_parent, 2961 .init = &omap2_init_clksel_parent,
2874 .ops = &clkops_omap2_dflt, 2962 .ops = &clkops_omap2_dflt,
2875 .clksel = auxclk_sel, 2963 .clksel = auxclk_src_sel,
2876 .clksel_reg = OMAP4_SCRM_AUXCLK4, 2964 .clksel_reg = OMAP4_SCRM_AUXCLK4,
2877 .clksel_mask = OMAP4_SRCSELECT_MASK, 2965 .clksel_mask = OMAP4_SRCSELECT_MASK,
2878 .recalc = &omap2_clksel_recalc, 2966 .recalc = &omap2_clksel_recalc,
@@ -2880,12 +2968,29 @@ static struct clk auxclk4_ck = {
2880 .enable_bit = OMAP4_ENABLE_SHIFT, 2968 .enable_bit = OMAP4_ENABLE_SHIFT,
2881}; 2969};
2882 2970
2883static struct clk auxclk5_ck = { 2971static const struct clksel auxclk4_sel[] = {
2884 .name = "auxclk5_ck", 2972 { .parent = &auxclk4_src_ck, .rates = div16_1to16_rates },
2973 { .parent = NULL },
2974};
2975
2976static struct clk auxclk4_ck = {
2977 .name = "auxclk4_ck",
2978 .parent = &auxclk4_src_ck,
2979 .clksel = auxclk4_sel,
2980 .clksel_reg = OMAP4_SCRM_AUXCLK4,
2981 .clksel_mask = OMAP4_CLKDIV_MASK,
2982 .ops = &clkops_null,
2983 .recalc = &omap2_clksel_recalc,
2984 .round_rate = &omap2_clksel_round_rate,
2985 .set_rate = &omap2_clksel_set_rate,
2986};
2987
2988static struct clk auxclk5_src_ck = {
2989 .name = "auxclk5_src_ck",
2885 .parent = &sys_clkin_ck, 2990 .parent = &sys_clkin_ck,
2886 .init = &omap2_init_clksel_parent, 2991 .init = &omap2_init_clksel_parent,
2887 .ops = &clkops_omap2_dflt, 2992 .ops = &clkops_omap2_dflt,
2888 .clksel = auxclk_sel, 2993 .clksel = auxclk_src_sel,
2889 .clksel_reg = OMAP4_SCRM_AUXCLK5, 2994 .clksel_reg = OMAP4_SCRM_AUXCLK5,
2890 .clksel_mask = OMAP4_SRCSELECT_MASK, 2995 .clksel_mask = OMAP4_SRCSELECT_MASK,
2891 .recalc = &omap2_clksel_recalc, 2996 .recalc = &omap2_clksel_recalc,
@@ -2893,6 +2998,23 @@ static struct clk auxclk5_ck = {
2893 .enable_bit = OMAP4_ENABLE_SHIFT, 2998 .enable_bit = OMAP4_ENABLE_SHIFT,
2894}; 2999};
2895 3000
3001static const struct clksel auxclk5_sel[] = {
3002 { .parent = &auxclk5_src_ck, .rates = div16_1to16_rates },
3003 { .parent = NULL },
3004};
3005
3006static struct clk auxclk5_ck = {
3007 .name = "auxclk5_ck",
3008 .parent = &auxclk5_src_ck,
3009 .clksel = auxclk5_sel,
3010 .clksel_reg = OMAP4_SCRM_AUXCLK5,
3011 .clksel_mask = OMAP4_CLKDIV_MASK,
3012 .ops = &clkops_null,
3013 .recalc = &omap2_clksel_recalc,
3014 .round_rate = &omap2_clksel_round_rate,
3015 .set_rate = &omap2_clksel_set_rate,
3016};
3017
2896static const struct clksel auxclkreq_sel[] = { 3018static const struct clksel auxclkreq_sel[] = {
2897 { .parent = &auxclk0_ck, .rates = div_1_0_rates }, 3019 { .parent = &auxclk0_ck, .rates = div_1_0_rates },
2898 { .parent = &auxclk1_ck, .rates = div_1_1_rates }, 3020 { .parent = &auxclk1_ck, .rates = div_1_1_rates },
@@ -3093,12 +3215,12 @@ static struct omap_clk omap44xx_clks[] = {
3093 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), 3215 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
3094 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), 3216 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
3095 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), 3217 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
3096 CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X), 3218 CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X),
3097 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), 3219 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
3098 CLK("omap_i2c.1", "fck", &i2c1_fck, CK_443X), 3220 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X),
3099 CLK("omap_i2c.2", "fck", &i2c2_fck, CK_443X), 3221 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X),
3100 CLK("omap_i2c.3", "fck", &i2c3_fck, CK_443X), 3222 CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X),
3101 CLK("omap_i2c.4", "fck", &i2c4_fck, CK_443X), 3223 CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X),
3102 CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), 3224 CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
3103 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), 3225 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
3104 CLK(NULL, "iss_fck", &iss_fck, CK_443X), 3226 CLK(NULL, "iss_fck", &iss_fck, CK_443X),
@@ -3109,23 +3231,23 @@ static struct omap_clk omap44xx_clks[] = {
3109 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), 3231 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
3110 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), 3232 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
3111 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), 3233 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
3112 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_443X), 3234 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X),
3113 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), 3235 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
3114 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_443X), 3236 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X),
3115 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), 3237 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
3116 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X), 3238 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X),
3117 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), 3239 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
3118 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X), 3240 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X),
3119 CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), 3241 CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X),
3120 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X), 3242 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X),
3121 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X), 3243 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X),
3122 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X), 3244 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X),
3123 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X), 3245 CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X),
3124 CLK("omap_hsmmc.0", "fck", &mmc1_fck, CK_443X), 3246 CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X),
3125 CLK("omap_hsmmc.1", "fck", &mmc2_fck, CK_443X), 3247 CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X),
3126 CLK("omap_hsmmc.2", "fck", &mmc3_fck, CK_443X), 3248 CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X),
3127 CLK("omap_hsmmc.3", "fck", &mmc4_fck, CK_443X), 3249 CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X),
3128 CLK("omap_hsmmc.4", "fck", &mmc5_fck, CK_443X), 3250 CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X),
3129 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), 3251 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
3130 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), 3252 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
3131 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), 3253 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
@@ -3182,21 +3304,27 @@ static struct omap_clk omap44xx_clks[] = {
3182 CLK(NULL, "usim_ck", &usim_ck, CK_443X), 3304 CLK(NULL, "usim_ck", &usim_ck, CK_443X),
3183 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), 3305 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
3184 CLK(NULL, "usim_fck", &usim_fck, CK_443X), 3306 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
3185 CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X), 3307 CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X),
3186 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), 3308 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
3187 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), 3309 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
3188 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), 3310 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
3311 CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X),
3189 CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), 3312 CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
3190 CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
3191 CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
3192 CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
3193 CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
3194 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
3195 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), 3313 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
3314 CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X),
3315 CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
3196 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), 3316 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
3317 CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X),
3318 CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
3197 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), 3319 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
3320 CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X),
3321 CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
3198 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), 3322 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
3323 CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X),
3324 CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
3199 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), 3325 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
3326 CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X),
3327 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
3200 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), 3328 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
3201 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), 3329 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
3202 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), 3330 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
@@ -3251,6 +3379,7 @@ int __init omap4xxx_clk_init(void)
3251 } 3379 }
3252 3380
3253 clk_init(&omap2_clk_functions); 3381 clk_init(&omap2_clk_functions);
3382 omap2_clk_disable_clkdm_control();
3254 3383
3255 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); 3384 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3256 c++) 3385 c++)
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 6cb6c03293df..ab7db083f97f 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -1,8 +1,8 @@
1/* 1/*
2 * OMAP2/3/4 clockdomain framework functions 2 * OMAP2/3/4 clockdomain framework functions
3 * 3 *
4 * Copyright (C) 2008-2010 Texas Instruments, Inc. 4 * Copyright (C) 2008-2011 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation 5 * Copyright (C) 2008-2011 Nokia Corporation
6 * 6 *
7 * Written by Paul Walmsley and Jouni Högander 7 * Written by Paul Walmsley and Jouni Högander
8 * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com> 8 * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com>
@@ -92,6 +92,8 @@ static int _clkdm_register(struct clockdomain *clkdm)
92 92
93 pwrdm_add_clkdm(pwrdm, clkdm); 93 pwrdm_add_clkdm(pwrdm, clkdm);
94 94
95 spin_lock_init(&clkdm->lock);
96
95 pr_debug("clockdomain: registered %s\n", clkdm->name); 97 pr_debug("clockdomain: registered %s\n", clkdm->name);
96 98
97 return 0; 99 return 0;
@@ -690,6 +692,9 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
690 */ 692 */
691int clkdm_sleep(struct clockdomain *clkdm) 693int clkdm_sleep(struct clockdomain *clkdm)
692{ 694{
695 int ret;
696 unsigned long flags;
697
693 if (!clkdm) 698 if (!clkdm)
694 return -EINVAL; 699 return -EINVAL;
695 700
@@ -704,7 +709,11 @@ int clkdm_sleep(struct clockdomain *clkdm)
704 709
705 pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name); 710 pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name);
706 711
707 return arch_clkdm->clkdm_sleep(clkdm); 712 spin_lock_irqsave(&clkdm->lock, flags);
713 clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
714 ret = arch_clkdm->clkdm_sleep(clkdm);
715 spin_unlock_irqrestore(&clkdm->lock, flags);
716 return ret;
708} 717}
709 718
710/** 719/**
@@ -718,6 +727,9 @@ int clkdm_sleep(struct clockdomain *clkdm)
718 */ 727 */
719int clkdm_wakeup(struct clockdomain *clkdm) 728int clkdm_wakeup(struct clockdomain *clkdm)
720{ 729{
730 int ret;
731 unsigned long flags;
732
721 if (!clkdm) 733 if (!clkdm)
722 return -EINVAL; 734 return -EINVAL;
723 735
@@ -732,7 +744,11 @@ int clkdm_wakeup(struct clockdomain *clkdm)
732 744
733 pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name); 745 pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name);
734 746
735 return arch_clkdm->clkdm_wakeup(clkdm); 747 spin_lock_irqsave(&clkdm->lock, flags);
748 clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
749 ret = arch_clkdm->clkdm_wakeup(clkdm);
750 spin_unlock_irqrestore(&clkdm->lock, flags);
751 return ret;
736} 752}
737 753
738/** 754/**
@@ -747,6 +763,8 @@ int clkdm_wakeup(struct clockdomain *clkdm)
747 */ 763 */
748void clkdm_allow_idle(struct clockdomain *clkdm) 764void clkdm_allow_idle(struct clockdomain *clkdm)
749{ 765{
766 unsigned long flags;
767
750 if (!clkdm) 768 if (!clkdm)
751 return; 769 return;
752 770
@@ -762,8 +780,11 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
762 pr_debug("clockdomain: enabling automatic idle transitions for %s\n", 780 pr_debug("clockdomain: enabling automatic idle transitions for %s\n",
763 clkdm->name); 781 clkdm->name);
764 782
783 spin_lock_irqsave(&clkdm->lock, flags);
784 clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED;
765 arch_clkdm->clkdm_allow_idle(clkdm); 785 arch_clkdm->clkdm_allow_idle(clkdm);
766 pwrdm_clkdm_state_switch(clkdm); 786 pwrdm_clkdm_state_switch(clkdm);
787 spin_unlock_irqrestore(&clkdm->lock, flags);
767} 788}
768 789
769/** 790/**
@@ -777,6 +798,8 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
777 */ 798 */
778void clkdm_deny_idle(struct clockdomain *clkdm) 799void clkdm_deny_idle(struct clockdomain *clkdm)
779{ 800{
801 unsigned long flags;
802
780 if (!clkdm) 803 if (!clkdm)
781 return; 804 return;
782 805
@@ -792,11 +815,90 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
792 pr_debug("clockdomain: disabling automatic idle transitions for %s\n", 815 pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
793 clkdm->name); 816 clkdm->name);
794 817
818 spin_lock_irqsave(&clkdm->lock, flags);
819 clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
795 arch_clkdm->clkdm_deny_idle(clkdm); 820 arch_clkdm->clkdm_deny_idle(clkdm);
821 spin_unlock_irqrestore(&clkdm->lock, flags);
822}
823
824/**
825 * clkdm_in_hwsup - is clockdomain @clkdm have hardware-supervised idle enabled?
826 * @clkdm: struct clockdomain *
827 *
828 * Returns true if clockdomain @clkdm currently has
829 * hardware-supervised idle enabled, or false if it does not or if
830 * @clkdm is NULL. It is only valid to call this function after
831 * clkdm_init() has been called. This function does not actually read
832 * bits from the hardware; it instead tests an in-memory flag that is
833 * changed whenever the clockdomain code changes the auto-idle mode.
834 */
835bool clkdm_in_hwsup(struct clockdomain *clkdm)
836{
837 bool ret;
838 unsigned long flags;
839
840 if (!clkdm)
841 return false;
842
843 spin_lock_irqsave(&clkdm->lock, flags);
844 ret = (clkdm->_flags & _CLKDM_FLAG_HWSUP_ENABLED) ? true : false;
845 spin_unlock_irqrestore(&clkdm->lock, flags);
846
847 return ret;
848}
849
850/* Clockdomain-to-clock/hwmod framework interface code */
851
852static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
853{
854 unsigned long flags;
855
856 if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_enable)
857 return -EINVAL;
858
859 /*
860 * For arch's with no autodeps, clkcm_clk_enable
861 * should be called for every clock instance or hwmod that is
862 * enabled, so the clkdm can be force woken up.
863 */
864 if ((atomic_inc_return(&clkdm->usecount) > 1) && autodeps)
865 return 0;
866
867 spin_lock_irqsave(&clkdm->lock, flags);
868 arch_clkdm->clkdm_clk_enable(clkdm);
869 pwrdm_wait_transition(clkdm->pwrdm.ptr);
870 pwrdm_clkdm_state_switch(clkdm);
871 spin_unlock_irqrestore(&clkdm->lock, flags);
872
873 pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name);
874
875 return 0;
796} 876}
797 877
878static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
879{
880 unsigned long flags;
881
882 if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
883 return -EINVAL;
884
885 if (atomic_read(&clkdm->usecount) == 0) {
886 WARN_ON(1); /* underflow */
887 return -ERANGE;
888 }
889
890 if (atomic_dec_return(&clkdm->usecount) > 0)
891 return 0;
892
893 spin_lock_irqsave(&clkdm->lock, flags);
894 arch_clkdm->clkdm_clk_disable(clkdm);
895 pwrdm_clkdm_state_switch(clkdm);
896 spin_unlock_irqrestore(&clkdm->lock, flags);
798 897
799/* Clockdomain-to-clock framework interface code */ 898 pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name);
899
900 return 0;
901}
800 902
801/** 903/**
802 * clkdm_clk_enable - add an enabled downstream clock to this clkdm 904 * clkdm_clk_enable - add an enabled downstream clock to this clkdm
@@ -819,25 +921,10 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
819 * downstream clocks for debugging purposes? 921 * downstream clocks for debugging purposes?
820 */ 922 */
821 923
822 if (!clkdm || !clk) 924 if (!clk)
823 return -EINVAL; 925 return -EINVAL;
824 926
825 if (!arch_clkdm || !arch_clkdm->clkdm_clk_enable) 927 return _clkdm_clk_hwmod_enable(clkdm);
826 return -EINVAL;
827
828 if (atomic_inc_return(&clkdm->usecount) > 1)
829 return 0;
830
831 /* Clockdomain now has one enabled downstream clock */
832
833 pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name,
834 clk->name);
835
836 arch_clkdm->clkdm_clk_enable(clkdm);
837 pwrdm_wait_transition(clkdm->pwrdm.ptr);
838 pwrdm_clkdm_state_switch(clkdm);
839
840 return 0;
841} 928}
842 929
843/** 930/**
@@ -850,9 +937,8 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
850 * clockdomain usecount goes to 0, put the clockdomain to sleep 937 * clockdomain usecount goes to 0, put the clockdomain to sleep
851 * (software-supervised mode) or remove the clkdm autodependencies 938 * (software-supervised mode) or remove the clkdm autodependencies
852 * (hardware-supervised mode). Returns -EINVAL if passed null 939 * (hardware-supervised mode). Returns -EINVAL if passed null
853 * pointers; -ERANGE if the @clkdm usecount underflows and debugging 940 * pointers; -ERANGE if the @clkdm usecount underflows; or returns 0
854 * is enabled; or returns 0 upon success or if the clockdomain is in 941 * upon success or if the clockdomain is in hwsup idle mode.
855 * hwsup idle mode.
856 */ 942 */
857int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) 943int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
858{ 944{
@@ -861,30 +947,72 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
861 * downstream clocks for debugging purposes? 947 * downstream clocks for debugging purposes?
862 */ 948 */
863 949
864 if (!clkdm || !clk) 950 if (!clk)
865 return -EINVAL; 951 return -EINVAL;
866 952
867 if (!arch_clkdm || !arch_clkdm->clkdm_clk_disable) 953 return _clkdm_clk_hwmod_disable(clkdm);
954}
955
956/**
957 * clkdm_hwmod_enable - add an enabled downstream hwmod to this clkdm
958 * @clkdm: struct clockdomain *
959 * @oh: struct omap_hwmod * of the enabled downstream hwmod
960 *
961 * Increment the usecount of the clockdomain @clkdm and ensure that it
962 * is awake before @oh is enabled. Intended to be called by
963 * module_enable() code.
964 * If the clockdomain is in software-supervised idle mode, force the
965 * clockdomain to wake. If the clockdomain is in hardware-supervised idle
966 * mode, add clkdm-pwrdm autodependencies, to ensure that devices in the
967 * clockdomain can be read from/written to by on-chip processors.
968 * Returns -EINVAL if passed null pointers;
969 * returns 0 upon success or if the clockdomain is in hwsup idle mode.
970 */
971int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh)
972{
973 /* The clkdm attribute does not exist yet prior OMAP4 */
974 if (cpu_is_omap24xx() || cpu_is_omap34xx())
975 return 0;
976
977 /*
978 * XXX Rewrite this code to maintain a list of enabled
979 * downstream hwmods for debugging purposes?
980 */
981
982 if (!oh)
868 return -EINVAL; 983 return -EINVAL;
869 984
870#ifdef DEBUG 985 return _clkdm_clk_hwmod_enable(clkdm);
871 if (atomic_read(&clkdm->usecount) == 0) { 986}
872 WARN_ON(1); /* underflow */
873 return -ERANGE;
874 }
875#endif
876 987
877 if (atomic_dec_return(&clkdm->usecount) > 0) 988/**
989 * clkdm_hwmod_disable - remove an enabled downstream hwmod from this clkdm
990 * @clkdm: struct clockdomain *
991 * @oh: struct omap_hwmod * of the disabled downstream hwmod
992 *
993 * Decrement the usecount of this clockdomain @clkdm when @oh is
994 * disabled. Intended to be called by module_disable() code.
995 * If the clockdomain usecount goes to 0, put the clockdomain to sleep
996 * (software-supervised mode) or remove the clkdm autodependencies
997 * (hardware-supervised mode).
998 * Returns -EINVAL if passed null pointers; -ERANGE if the @clkdm usecount
999 * underflows; or returns 0 upon success or if the clockdomain is in hwsup
1000 * idle mode.
1001 */
1002int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
1003{
1004 /* The clkdm attribute does not exist yet prior OMAP4 */
1005 if (cpu_is_omap24xx() || cpu_is_omap34xx())
878 return 0; 1006 return 0;
879 1007
880 /* All downstream clocks of this clockdomain are now disabled */ 1008 /*
881 1009 * XXX Rewrite this code to maintain a list of enabled
882 pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name, 1010 * downstream hwmods for debugging purposes?
883 clk->name); 1011 */
884 1012
885 arch_clkdm->clkdm_clk_disable(clkdm); 1013 if (!oh)
886 pwrdm_clkdm_state_switch(clkdm); 1014 return -EINVAL;
887 1015
888 return 0; 1016 return _clkdm_clk_hwmod_disable(clkdm);
889} 1017}
890 1018
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 5823584d9cd7..1e50c88b8a07 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -17,9 +17,11 @@
17#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H 17#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H
18 18
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/spinlock.h>
20 21
21#include "powerdomain.h" 22#include "powerdomain.h"
22#include <plat/clock.h> 23#include <plat/clock.h>
24#include <plat/omap_hwmod.h>
23#include <plat/cpu.h> 25#include <plat/cpu.h>
24 26
25/* 27/*
@@ -82,6 +84,9 @@ struct clkdm_dep {
82 const struct omap_chip_id omap_chip; 84 const struct omap_chip_id omap_chip;
83}; 85};
84 86
87/* Possible flags for struct clockdomain._flags */
88#define _CLKDM_FLAG_HWSUP_ENABLED BIT(0)
89
85/** 90/**
86 * struct clockdomain - OMAP clockdomain 91 * struct clockdomain - OMAP clockdomain
87 * @name: clockdomain name 92 * @name: clockdomain name
@@ -89,6 +94,7 @@ struct clkdm_dep {
89 * @clktrctrl_reg: CLKSTCTRL reg for the given clock domain 94 * @clktrctrl_reg: CLKSTCTRL reg for the given clock domain
90 * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg 95 * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg
91 * @flags: Clockdomain capability flags 96 * @flags: Clockdomain capability flags
97 * @_flags: Flags for use only by internal clockdomain code
92 * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit 98 * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit
93 * @prcm_partition: (OMAP4 only) PRCM partition ID for this clkdm's registers 99 * @prcm_partition: (OMAP4 only) PRCM partition ID for this clkdm's registers
94 * @cm_inst: (OMAP4 only) CM instance register offset 100 * @cm_inst: (OMAP4 only) CM instance register offset
@@ -113,6 +119,7 @@ struct clockdomain {
113 } pwrdm; 119 } pwrdm;
114 const u16 clktrctrl_mask; 120 const u16 clktrctrl_mask;
115 const u8 flags; 121 const u8 flags;
122 u8 _flags;
116 const u8 dep_bit; 123 const u8 dep_bit;
117 const u8 prcm_partition; 124 const u8 prcm_partition;
118 const s16 cm_inst; 125 const s16 cm_inst;
@@ -122,6 +129,7 @@ struct clockdomain {
122 const struct omap_chip_id omap_chip; 129 const struct omap_chip_id omap_chip;
123 atomic_t usecount; 130 atomic_t usecount;
124 struct list_head node; 131 struct list_head node;
132 spinlock_t lock;
125}; 133};
126 134
127/** 135/**
@@ -177,12 +185,15 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
177 185
178void clkdm_allow_idle(struct clockdomain *clkdm); 186void clkdm_allow_idle(struct clockdomain *clkdm);
179void clkdm_deny_idle(struct clockdomain *clkdm); 187void clkdm_deny_idle(struct clockdomain *clkdm);
188bool clkdm_in_hwsup(struct clockdomain *clkdm);
180 189
181int clkdm_wakeup(struct clockdomain *clkdm); 190int clkdm_wakeup(struct clockdomain *clkdm);
182int clkdm_sleep(struct clockdomain *clkdm); 191int clkdm_sleep(struct clockdomain *clkdm);
183 192
184int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); 193int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
185int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); 194int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
195int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh);
196int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
186 197
187extern void __init omap2xxx_clockdomains_init(void); 198extern void __init omap2xxx_clockdomains_init(void);
188extern void __init omap3xxx_clockdomains_init(void); 199extern void __init omap3xxx_clockdomains_init(void);
diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
index 48d0db7e6069..f740edb111f4 100644
--- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
@@ -183,7 +183,8 @@ static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
183 _clkdm_add_autodeps(clkdm); 183 _clkdm_add_autodeps(clkdm);
184 _enable_hwsup(clkdm); 184 _enable_hwsup(clkdm);
185 } else { 185 } else {
186 clkdm_wakeup(clkdm); 186 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
187 omap2_clkdm_wakeup(clkdm);
187 } 188 }
188 189
189 return 0; 190 return 0;
@@ -205,7 +206,8 @@ static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
205 _clkdm_del_autodeps(clkdm); 206 _clkdm_del_autodeps(clkdm);
206 _enable_hwsup(clkdm); 207 _enable_hwsup(clkdm);
207 } else { 208 } else {
208 clkdm_sleep(clkdm); 209 if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
210 omap2_clkdm_sleep(clkdm);
209 } 211 }
210 212
211 return 0; 213 return 0;
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
index a1a4ecd26544..b43706aa08bd 100644
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -95,13 +95,8 @@ static void omap4_clkdm_deny_idle(struct clockdomain *clkdm)
95 95
96static int omap4_clkdm_clk_enable(struct clockdomain *clkdm) 96static int omap4_clkdm_clk_enable(struct clockdomain *clkdm)
97{ 97{
98 bool hwsup = false; 98 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
99 99 return omap4_clkdm_wakeup(clkdm);
100 hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
101 clkdm->cm_inst, clkdm->clkdm_offs);
102
103 if (!hwsup)
104 clkdm_wakeup(clkdm);
105 100
106 return 0; 101 return 0;
107} 102}
@@ -113,8 +108,8 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
113 hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, 108 hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
114 clkdm->cm_inst, clkdm->clkdm_offs); 109 clkdm->cm_inst, clkdm->clkdm_offs);
115 110
116 if (!hwsup) 111 if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
117 clkdm_sleep(clkdm); 112 omap4_clkdm_sleep(clkdm);
118 113
119 return 0; 114 return 0;
120} 115}
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index 66090f2676ce..dccc651fa0d0 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -565,7 +565,7 @@ static struct clockdomain ducati_44xx_clkdm = {
565}; 565};
566 566
567static struct clockdomain mpu_44xx_clkdm = { 567static struct clockdomain mpu_44xx_clkdm = {
568 .name = "mpu_clkdm", 568 .name = "mpuss_clkdm",
569 .pwrdm = { .name = "mpu_pwrdm" }, 569 .pwrdm = { .name = "mpu_pwrdm" },
570 .prcm_partition = OMAP4430_CM1_PARTITION, 570 .prcm_partition = OMAP4430_CM1_PARTITION,
571 .cm_inst = OMAP4430_CM1_MPU_INST, 571 .cm_inst = OMAP4430_CM1_MPU_INST,
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
index 0b87ec82b41c..3380beeace6e 100644
--- a/arch/arm/mach-omap2/cm44xx.h
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * OMAP4 Clock Management (CM) definitions 2 * OMAP4 Clock Management (CM) definitions
3 * 3 *
4 * Copyright (C) 2007-2009 Texas Instruments, Inc. 4 * Copyright (C) 2007-2011 Texas Instruments, Inc.
5 * Copyright (C) 2007-2009 Nokia Corporation 5 * Copyright (C) 2007-2009 Nokia Corporation
6 * 6 *
7 * Written by Paul Walmsley 7 * Written by Paul Walmsley
@@ -23,10 +23,4 @@
23#define OMAP4_CM_CLKSTCTRL 0x0000 23#define OMAP4_CM_CLKSTCTRL 0x0000
24#define OMAP4_CM_STATICDEP 0x0004 24#define OMAP4_CM_STATICDEP 0x0004
25 25
26/* Function prototypes */
27# ifndef __ASSEMBLER__
28
29extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
30
31# endif
32#endif 26#endif
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index a482bfa0a954..eb2a472bbf46 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -2,6 +2,7 @@
2 * OMAP4 CM instance functions 2 * OMAP4 CM instance functions
3 * 3 *
4 * Copyright (C) 2009 Nokia Corporation 4 * Copyright (C) 2009 Nokia Corporation
5 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Paul Walmsley 6 * Paul Walmsley
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
@@ -32,6 +33,22 @@
32#include "prm44xx.h" 33#include "prm44xx.h"
33#include "prcm_mpu44xx.h" 34#include "prcm_mpu44xx.h"
34 35
36/*
37 * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
38 *
39 * 0x0 func: Module is fully functional, including OCP
40 * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep
41 * abortion
42 * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if
43 * using separate functional clock
44 * 0x3 disabled: Module is disabled and cannot be accessed
45 *
46 */
47#define CLKCTRL_IDLEST_FUNCTIONAL 0x0
48#define CLKCTRL_IDLEST_INTRANSITION 0x1
49#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
50#define CLKCTRL_IDLEST_DISABLED 0x3
51
35static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = { 52static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
36 [OMAP4430_INVALID_PRCM_PARTITION] = 0, 53 [OMAP4430_INVALID_PRCM_PARTITION] = 0,
37 [OMAP4430_PRM_PARTITION] = OMAP4430_PRM_BASE, 54 [OMAP4430_PRM_PARTITION] = OMAP4430_PRM_BASE,
@@ -41,6 +58,48 @@ static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
41 [OMAP4430_PRCM_MPU_PARTITION] = OMAP4430_PRCM_MPU_BASE, 58 [OMAP4430_PRCM_MPU_PARTITION] = OMAP4430_PRCM_MPU_BASE,
42}; 59};
43 60
61/* Private functions */
62
63/**
64 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
65 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
66 * @inst: CM instance register offset (*_INST macro)
67 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
68 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
69 *
70 * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
71 * bit 0.
72 */
73static u32 _clkctrl_idlest(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
74{
75 u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
76 v &= OMAP4430_IDLEST_MASK;
77 v >>= OMAP4430_IDLEST_SHIFT;
78 return v;
79}
80
81/**
82 * _is_module_ready - can module registers be accessed without causing an abort?
83 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
84 * @inst: CM instance register offset (*_INST macro)
85 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
86 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
87 *
88 * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
89 * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
90 */
91static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
92{
93 u32 v;
94
95 v = _clkctrl_idlest(part, inst, cdoffs, clkctrl_offs);
96
97 return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
98 v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
99}
100
101/* Public functions */
102
44/* Read a register in a CM instance */ 103/* Read a register in a CM instance */
45u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx) 104u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
46{ 105{
@@ -200,36 +259,93 @@ void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs)
200 */ 259 */
201 260
202/** 261/**
203 * omap4_cm_wait_module_ready - wait for a module to be in 'func' state 262 * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state
204 * @clkctrl_reg: CLKCTRL module address 263 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
264 * @inst: CM instance register offset (*_INST macro)
265 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
266 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
205 * 267 *
206 * Wait for the module IDLEST to be functional. If the idle state is in any 268 * Wait for the module IDLEST to be functional. If the idle state is in any
207 * the non functional state (trans, idle or disabled), module and thus the 269 * the non functional state (trans, idle or disabled), module and thus the
208 * sysconfig cannot be accessed and will probably lead to an "imprecise 270 * sysconfig cannot be accessed and will probably lead to an "imprecise
209 * external abort" 271 * external abort"
272 */
273int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs,
274 u16 clkctrl_offs)
275{
276 int i = 0;
277
278 if (!clkctrl_offs)
279 return 0;
280
281 omap_test_timeout(_is_module_ready(part, inst, cdoffs, clkctrl_offs),
282 MAX_MODULE_READY_TIME, i);
283
284 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
285}
286
287/**
288 * omap4_cminst_wait_module_idle - wait for a module to be in 'disabled'
289 * state
290 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
291 * @inst: CM instance register offset (*_INST macro)
292 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
293 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
210 * 294 *
211 * Module idle state: 295 * Wait for the module IDLEST to be disabled. Some PRCM transition,
212 * 0x0 func: Module is fully functional, including OCP 296 * like reset assertion or parent clock de-activation must wait the
213 * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep 297 * module to be fully disabled.
214 * abortion
215 * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if
216 * using separate functional clock
217 * 0x3 disabled: Module is disabled and cannot be accessed
218 *
219 */ 298 */
220int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg) 299int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
221{ 300{
222 int i = 0; 301 int i = 0;
223 302
224 if (!clkctrl_reg) 303 if (!clkctrl_offs)
225 return 0; 304 return 0;
226 305
227 omap_test_timeout(( 306 omap_test_timeout((_clkctrl_idlest(part, inst, cdoffs, clkctrl_offs) ==
228 ((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) == 0) || 307 CLKCTRL_IDLEST_DISABLED),
229 (((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) >> 308 MAX_MODULE_READY_TIME, i);
230 OMAP4430_IDLEST_SHIFT) == 0x2)),
231 MAX_MODULE_READY_TIME, i);
232 309
233 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; 310 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
234} 311}
235 312
313/**
314 * omap4_cminst_module_enable - Enable the modulemode inside CLKCTRL
315 * @mode: Module mode (SW or HW)
316 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
317 * @inst: CM instance register offset (*_INST macro)
318 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
319 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
320 *
321 * No return value.
322 */
323void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
324 u16 clkctrl_offs)
325{
326 u32 v;
327
328 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
329 v &= ~OMAP4430_MODULEMODE_MASK;
330 v |= mode << OMAP4430_MODULEMODE_SHIFT;
331 omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
332}
333
334/**
335 * omap4_cminst_module_disable - Disable the module inside CLKCTRL
336 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
337 * @inst: CM instance register offset (*_INST macro)
338 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
339 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
340 *
341 * No return value.
342 */
343void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
344 u16 clkctrl_offs)
345{
346 u32 v;
347
348 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
349 v &= ~OMAP4430_MODULEMODE_MASK;
350 omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
351}
diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
index 2b32c181a2ee..f2ea6453ade0 100644
--- a/arch/arm/mach-omap2/cminst44xx.h
+++ b/arch/arm/mach-omap2/cminst44xx.h
@@ -17,6 +17,14 @@ extern void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs);
17extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs); 17extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs);
18extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs); 18extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
19 19
20extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
21extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
22
23extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
24 u16 clkctrl_offs);
25extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
26 u16 clkctrl_offs);
27
20/* 28/*
21 * In an ideal world, we would not export these low-level functions, 29 * In an ideal world, we would not export these low-level functions,
22 * but this will probably take some time to fix properly 30 * but this will probably take some time to fix properly
@@ -32,6 +40,4 @@ extern u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst,
32extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, 40extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx,
33 u32 mask); 41 u32 mask);
34 42
35extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
36
37#endif 43#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 02b6016393a8..84cc0bdda3ae 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -146,9 +146,10 @@
146#include <plat/prcm.h> 146#include <plat/prcm.h>
147 147
148#include "cm2xxx_3xxx.h" 148#include "cm2xxx_3xxx.h"
149#include "cm44xx.h" 149#include "cminst44xx.h"
150#include "prm2xxx_3xxx.h" 150#include "prm2xxx_3xxx.h"
151#include "prm44xx.h" 151#include "prm44xx.h"
152#include "prminst44xx.h"
152#include "mux.h" 153#include "mux.h"
153 154
154/* Maximum microseconds to wait for OMAP module to softreset */ 155/* Maximum microseconds to wait for OMAP module to softreset */
@@ -679,6 +680,56 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
679} 680}
680 681
681/** 682/**
683 * _enable_module - enable CLKCTRL modulemode on OMAP4
684 * @oh: struct omap_hwmod *
685 *
686 * Enables the PRCM module mode related to the hwmod @oh.
687 * No return value.
688 */
689static void _enable_module(struct omap_hwmod *oh)
690{
691 /* The module mode does not exist prior OMAP4 */
692 if (cpu_is_omap24xx() || cpu_is_omap34xx())
693 return;
694
695 if (!oh->clkdm || !oh->prcm.omap4.modulemode)
696 return;
697
698 pr_debug("omap_hwmod: %s: _enable_module: %d\n",
699 oh->name, oh->prcm.omap4.modulemode);
700
701 omap4_cminst_module_enable(oh->prcm.omap4.modulemode,
702 oh->clkdm->prcm_partition,
703 oh->clkdm->cm_inst,
704 oh->clkdm->clkdm_offs,
705 oh->prcm.omap4.clkctrl_offs);
706}
707
708/**
709 * _disable_module - enable CLKCTRL modulemode on OMAP4
710 * @oh: struct omap_hwmod *
711 *
712 * Disable the PRCM module mode related to the hwmod @oh.
713 * No return value.
714 */
715static void _disable_module(struct omap_hwmod *oh)
716{
717 /* The module mode does not exist prior OMAP4 */
718 if (cpu_is_omap24xx() || cpu_is_omap34xx())
719 return;
720
721 if (!oh->clkdm || !oh->prcm.omap4.modulemode)
722 return;
723
724 pr_debug("omap_hwmod: %s: _disable_module\n", oh->name);
725
726 omap4_cminst_module_disable(oh->clkdm->prcm_partition,
727 oh->clkdm->cm_inst,
728 oh->clkdm->clkdm_offs,
729 oh->prcm.omap4.clkctrl_offs);
730}
731
732/**
682 * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh 733 * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh
683 * @oh: struct omap_hwmod *oh 734 * @oh: struct omap_hwmod *oh
684 * 735 *
@@ -990,9 +1041,40 @@ static struct omap_hwmod *_lookup(const char *name)
990 1041
991 return oh; 1042 return oh;
992} 1043}
1044/**
1045 * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod
1046 * @oh: struct omap_hwmod *
1047 *
1048 * Convert a clockdomain name stored in a struct omap_hwmod into a
1049 * clockdomain pointer, and save it into the struct omap_hwmod.
1050 * return -EINVAL if clkdm_name does not exist or if the lookup failed.
1051 */
1052static int _init_clkdm(struct omap_hwmod *oh)
1053{
1054 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1055 return 0;
1056
1057 if (!oh->clkdm_name) {
1058 pr_warning("omap_hwmod: %s: no clkdm_name\n", oh->name);
1059 return -EINVAL;
1060 }
1061
1062 oh->clkdm = clkdm_lookup(oh->clkdm_name);
1063 if (!oh->clkdm) {
1064 pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
1065 oh->name, oh->clkdm_name);
1066 return -EINVAL;
1067 }
1068
1069 pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
1070 oh->name, oh->clkdm_name);
1071
1072 return 0;
1073}
993 1074
994/** 1075/**
995 * _init_clocks - clk_get() all clocks associated with this hwmod 1076 * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as
1077 * well the clockdomain.
996 * @oh: struct omap_hwmod * 1078 * @oh: struct omap_hwmod *
997 * @data: not used; pass NULL 1079 * @data: not used; pass NULL
998 * 1080 *
@@ -1012,6 +1094,7 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
1012 ret |= _init_main_clk(oh); 1094 ret |= _init_main_clk(oh);
1013 ret |= _init_interface_clks(oh); 1095 ret |= _init_interface_clks(oh);
1014 ret |= _init_opt_clks(oh); 1096 ret |= _init_opt_clks(oh);
1097 ret |= _init_clkdm(oh);
1015 1098
1016 if (!ret) 1099 if (!ret)
1017 oh->_state = _HWMOD_STATE_CLKS_INITED; 1100 oh->_state = _HWMOD_STATE_CLKS_INITED;
@@ -1028,7 +1111,7 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
1028 * Wait for a module @oh to leave slave idle. Returns 0 if the module 1111 * Wait for a module @oh to leave slave idle. Returns 0 if the module
1029 * does not have an IDLEST bit or if the module successfully leaves 1112 * does not have an IDLEST bit or if the module successfully leaves
1030 * slave idle; otherwise, pass along the return value of the 1113 * slave idle; otherwise, pass along the return value of the
1031 * appropriate *_cm_wait_module_ready() function. 1114 * appropriate *_cm*_wait_module_ready() function.
1032 */ 1115 */
1033static int _wait_target_ready(struct omap_hwmod *oh) 1116static int _wait_target_ready(struct omap_hwmod *oh)
1034{ 1117{
@@ -1055,7 +1138,13 @@ static int _wait_target_ready(struct omap_hwmod *oh)
1055 oh->prcm.omap2.idlest_reg_id, 1138 oh->prcm.omap2.idlest_reg_id,
1056 oh->prcm.omap2.idlest_idle_bit); 1139 oh->prcm.omap2.idlest_idle_bit);
1057 } else if (cpu_is_omap44xx()) { 1140 } else if (cpu_is_omap44xx()) {
1058 ret = omap4_cm_wait_module_ready(oh->prcm.omap4.clkctrl_reg); 1141 if (!oh->clkdm)
1142 return -EINVAL;
1143
1144 ret = omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition,
1145 oh->clkdm->cm_inst,
1146 oh->clkdm->clkdm_offs,
1147 oh->prcm.omap4.clkctrl_offs);
1059 } else { 1148 } else {
1060 BUG(); 1149 BUG();
1061 }; 1150 };
@@ -1064,6 +1153,36 @@ static int _wait_target_ready(struct omap_hwmod *oh)
1064} 1153}
1065 1154
1066/** 1155/**
1156 * _wait_target_disable - wait for a module to be disabled
1157 * @oh: struct omap_hwmod *
1158 *
1159 * Wait for a module @oh to enter slave idle. Returns 0 if the module
1160 * does not have an IDLEST bit or if the module successfully enters
1161 * slave idle; otherwise, pass along the return value of the
1162 * appropriate *_cm*_wait_module_idle() function.
1163 */
1164static int _wait_target_disable(struct omap_hwmod *oh)
1165{
1166 /* TODO: For now just handle OMAP4+ */
1167 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1168 return 0;
1169
1170 if (!oh)
1171 return -EINVAL;
1172
1173 if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
1174 return 0;
1175
1176 if (oh->flags & HWMOD_NO_IDLEST)
1177 return 0;
1178
1179 return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition,
1180 oh->clkdm->cm_inst,
1181 oh->clkdm->clkdm_offs,
1182 oh->prcm.omap4.clkctrl_offs);
1183}
1184
1185/**
1067 * _lookup_hardreset - fill register bit info for this hwmod/reset line 1186 * _lookup_hardreset - fill register bit info for this hwmod/reset line
1068 * @oh: struct omap_hwmod * 1187 * @oh: struct omap_hwmod *
1069 * @name: name of the reset line in the context of this hwmod 1188 * @name: name of the reset line in the context of this hwmod
@@ -1119,8 +1238,10 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
1119 return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, 1238 return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
1120 ohri.rst_shift); 1239 ohri.rst_shift);
1121 else if (cpu_is_omap44xx()) 1240 else if (cpu_is_omap44xx())
1122 return omap4_prm_assert_hardreset(oh->prcm.omap4.rstctrl_reg, 1241 return omap4_prminst_assert_hardreset(ohri.rst_shift,
1123 ohri.rst_shift); 1242 oh->clkdm->pwrdm.ptr->prcm_partition,
1243 oh->clkdm->pwrdm.ptr->prcm_offs,
1244 oh->prcm.omap4.rstctrl_offs);
1124 else 1245 else
1125 return -EINVAL; 1246 return -EINVAL;
1126} 1247}
@@ -1155,8 +1276,10 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
1155 if (ohri.st_shift) 1276 if (ohri.st_shift)
1156 pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", 1277 pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
1157 oh->name, name); 1278 oh->name, name);
1158 ret = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg, 1279 ret = omap4_prminst_deassert_hardreset(ohri.rst_shift,
1159 ohri.rst_shift); 1280 oh->clkdm->pwrdm.ptr->prcm_partition,
1281 oh->clkdm->pwrdm.ptr->prcm_offs,
1282 oh->prcm.omap4.rstctrl_offs);
1160 } else { 1283 } else {
1161 return -EINVAL; 1284 return -EINVAL;
1162 } 1285 }
@@ -1191,8 +1314,10 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
1191 return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs, 1314 return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
1192 ohri.st_shift); 1315 ohri.st_shift);
1193 } else if (cpu_is_omap44xx()) { 1316 } else if (cpu_is_omap44xx()) {
1194 return omap4_prm_is_hardreset_asserted(oh->prcm.omap4.rstctrl_reg, 1317 return omap4_prminst_is_hardreset_asserted(ohri.rst_shift,
1195 ohri.rst_shift); 1318 oh->clkdm->pwrdm.ptr->prcm_partition,
1319 oh->clkdm->pwrdm.ptr->prcm_offs,
1320 oh->prcm.omap4.rstctrl_offs);
1196 } else { 1321 } else {
1197 return -EINVAL; 1322 return -EINVAL;
1198 } 1323 }
@@ -1312,6 +1437,7 @@ static int _reset(struct omap_hwmod *oh)
1312static int _enable(struct omap_hwmod *oh) 1437static int _enable(struct omap_hwmod *oh)
1313{ 1438{
1314 int r; 1439 int r;
1440 int hwsup = 0;
1315 1441
1316 pr_debug("omap_hwmod: %s: enabling\n", oh->name); 1442 pr_debug("omap_hwmod: %s: enabling\n", oh->name);
1317 1443
@@ -1323,14 +1449,6 @@ static int _enable(struct omap_hwmod *oh)
1323 return -EINVAL; 1449 return -EINVAL;
1324 } 1450 }
1325 1451
1326 /* Mux pins for device runtime if populated */
1327 if (oh->mux && (!oh->mux->enabled ||
1328 ((oh->_state == _HWMOD_STATE_IDLE) &&
1329 oh->mux->pads_dynamic)))
1330 omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
1331
1332 _add_initiator_dep(oh, mpu_oh);
1333 _enable_clocks(oh);
1334 1452
1335 /* 1453 /*
1336 * If an IP contains only one HW reset line, then de-assert it in order 1454 * If an IP contains only one HW reset line, then de-assert it in order
@@ -1341,22 +1459,56 @@ static int _enable(struct omap_hwmod *oh)
1341 oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1) 1459 oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
1342 _deassert_hardreset(oh, oh->rst_lines[0].name); 1460 _deassert_hardreset(oh, oh->rst_lines[0].name);
1343 1461
1344 r = _wait_target_ready(oh); 1462 /* Mux pins for device runtime if populated */
1345 if (r) { 1463 if (oh->mux && (!oh->mux->enabled ||
1346 pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", 1464 ((oh->_state == _HWMOD_STATE_IDLE) &&
1347 oh->name, r); 1465 oh->mux->pads_dynamic)))
1348 _disable_clocks(oh); 1466 omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
1349 1467
1350 return r; 1468 _add_initiator_dep(oh, mpu_oh);
1469
1470 if (oh->clkdm) {
1471 /*
1472 * A clockdomain must be in SW_SUP before enabling
1473 * completely the module. The clockdomain can be set
1474 * in HW_AUTO only when the module become ready.
1475 */
1476 hwsup = clkdm_in_hwsup(oh->clkdm);
1477 r = clkdm_hwmod_enable(oh->clkdm, oh);
1478 if (r) {
1479 WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
1480 oh->name, oh->clkdm->name, r);
1481 return r;
1482 }
1351 } 1483 }
1352 1484
1353 oh->_state = _HWMOD_STATE_ENABLED; 1485 _enable_clocks(oh);
1486 _enable_module(oh);
1354 1487
1355 /* Access the sysconfig only if the target is ready */ 1488 r = _wait_target_ready(oh);
1356 if (oh->class->sysc) { 1489 if (!r) {
1357 if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) 1490 /*
1358 _update_sysc_cache(oh); 1491 * Set the clockdomain to HW_AUTO only if the target is ready,
1359 _enable_sysc(oh); 1492 * assuming that the previous state was HW_AUTO
1493 */
1494 if (oh->clkdm && hwsup)
1495 clkdm_allow_idle(oh->clkdm);
1496
1497 oh->_state = _HWMOD_STATE_ENABLED;
1498
1499 /* Access the sysconfig only if the target is ready */
1500 if (oh->class->sysc) {
1501 if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
1502 _update_sysc_cache(oh);
1503 _enable_sysc(oh);
1504 }
1505 } else {
1506 _disable_clocks(oh);
1507 pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
1508 oh->name, r);
1509
1510 if (oh->clkdm)
1511 clkdm_hwmod_disable(oh->clkdm, oh);
1360 } 1512 }
1361 1513
1362 return r; 1514 return r;
@@ -1372,6 +1524,8 @@ static int _enable(struct omap_hwmod *oh)
1372 */ 1524 */
1373static int _idle(struct omap_hwmod *oh) 1525static int _idle(struct omap_hwmod *oh)
1374{ 1526{
1527 int ret;
1528
1375 pr_debug("omap_hwmod: %s: idling\n", oh->name); 1529 pr_debug("omap_hwmod: %s: idling\n", oh->name);
1376 1530
1377 if (oh->_state != _HWMOD_STATE_ENABLED) { 1531 if (oh->_state != _HWMOD_STATE_ENABLED) {
@@ -1383,7 +1537,20 @@ static int _idle(struct omap_hwmod *oh)
1383 if (oh->class->sysc) 1537 if (oh->class->sysc)
1384 _idle_sysc(oh); 1538 _idle_sysc(oh);
1385 _del_initiator_dep(oh, mpu_oh); 1539 _del_initiator_dep(oh, mpu_oh);
1540 _disable_module(oh);
1541 ret = _wait_target_disable(oh);
1542 if (ret)
1543 pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
1544 oh->name);
1545 /*
1546 * The module must be in idle mode before disabling any parents
1547 * clocks. Otherwise, the parent clock might be disabled before
1548 * the module transition is done, and thus will prevent the
1549 * transition to complete properly.
1550 */
1386 _disable_clocks(oh); 1551 _disable_clocks(oh);
1552 if (oh->clkdm)
1553 clkdm_hwmod_disable(oh->clkdm, oh);
1387 1554
1388 /* Mux pins for device idle if populated */ 1555 /* Mux pins for device idle if populated */
1389 if (oh->mux && oh->mux->pads_dynamic) 1556 if (oh->mux && oh->mux->pads_dynamic)
@@ -1475,7 +1642,14 @@ static int _shutdown(struct omap_hwmod *oh)
1475 if (oh->_state == _HWMOD_STATE_ENABLED) { 1642 if (oh->_state == _HWMOD_STATE_ENABLED) {
1476 _del_initiator_dep(oh, mpu_oh); 1643 _del_initiator_dep(oh, mpu_oh);
1477 /* XXX what about the other system initiators here? dma, dsp */ 1644 /* XXX what about the other system initiators here? dma, dsp */
1645 _disable_module(oh);
1646 ret = _wait_target_disable(oh);
1647 if (ret)
1648 pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
1649 oh->name);
1478 _disable_clocks(oh); 1650 _disable_clocks(oh);
1651 if (oh->clkdm)
1652 clkdm_hwmod_disable(oh->clkdm, oh);
1479 } 1653 }
1480 /* XXX Should this code also force-disable the optional clocks? */ 1654 /* XXX Should this code also force-disable the optional clocks? */
1481 1655
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 5d5df49749df..6201422c0606 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -123,9 +123,16 @@ static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
123static struct omap_hwmod omap44xx_dmm_hwmod = { 123static struct omap_hwmod omap44xx_dmm_hwmod = {
124 .name = "dmm", 124 .name = "dmm",
125 .class = &omap44xx_dmm_hwmod_class, 125 .class = &omap44xx_dmm_hwmod_class,
126 .mpu_irqs = omap44xx_dmm_irqs, 126 .clkdm_name = "l3_emif_clkdm",
127 .prcm = {
128 .omap4 = {
129 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
130 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
131 },
132 },
127 .slaves = omap44xx_dmm_slaves, 133 .slaves = omap44xx_dmm_slaves,
128 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), 134 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
135 .mpu_irqs = omap44xx_dmm_irqs,
129 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 136 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
130}; 137};
131 138
@@ -173,6 +180,13 @@ static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
173static struct omap_hwmod omap44xx_emif_fw_hwmod = { 180static struct omap_hwmod omap44xx_emif_fw_hwmod = {
174 .name = "emif_fw", 181 .name = "emif_fw",
175 .class = &omap44xx_emif_fw_hwmod_class, 182 .class = &omap44xx_emif_fw_hwmod_class,
183 .clkdm_name = "l3_emif_clkdm",
184 .prcm = {
185 .omap4 = {
186 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
187 .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
188 },
189 },
176 .slaves = omap44xx_emif_fw_slaves, 190 .slaves = omap44xx_emif_fw_slaves,
177 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves), 191 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
178 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 192 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -212,6 +226,14 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
212static struct omap_hwmod omap44xx_l3_instr_hwmod = { 226static struct omap_hwmod omap44xx_l3_instr_hwmod = {
213 .name = "l3_instr", 227 .name = "l3_instr",
214 .class = &omap44xx_l3_hwmod_class, 228 .class = &omap44xx_l3_hwmod_class,
229 .clkdm_name = "l3_instr_clkdm",
230 .prcm = {
231 .omap4 = {
232 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
233 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
234 .modulemode = MODULEMODE_HWCTRL,
235 },
236 },
215 .slaves = omap44xx_l3_instr_slaves, 237 .slaves = omap44xx_l3_instr_slaves,
216 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves), 238 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
217 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 239 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -304,7 +326,14 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
304static struct omap_hwmod omap44xx_l3_main_1_hwmod = { 326static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
305 .name = "l3_main_1", 327 .name = "l3_main_1",
306 .class = &omap44xx_l3_hwmod_class, 328 .class = &omap44xx_l3_hwmod_class,
329 .clkdm_name = "l3_1_clkdm",
307 .mpu_irqs = omap44xx_l3_main_1_irqs, 330 .mpu_irqs = omap44xx_l3_main_1_irqs,
331 .prcm = {
332 .omap4 = {
333 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
334 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
335 },
336 },
308 .slaves = omap44xx_l3_main_1_slaves, 337 .slaves = omap44xx_l3_main_1_slaves,
309 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), 338 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
310 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 339 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -400,6 +429,13 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
400static struct omap_hwmod omap44xx_l3_main_2_hwmod = { 429static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
401 .name = "l3_main_2", 430 .name = "l3_main_2",
402 .class = &omap44xx_l3_hwmod_class, 431 .class = &omap44xx_l3_hwmod_class,
432 .clkdm_name = "l3_2_clkdm",
433 .prcm = {
434 .omap4 = {
435 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
436 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
437 },
438 },
403 .slaves = omap44xx_l3_main_2_slaves, 439 .slaves = omap44xx_l3_main_2_slaves,
404 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves), 440 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
405 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 441 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -450,6 +486,14 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
450static struct omap_hwmod omap44xx_l3_main_3_hwmod = { 486static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
451 .name = "l3_main_3", 487 .name = "l3_main_3",
452 .class = &omap44xx_l3_hwmod_class, 488 .class = &omap44xx_l3_hwmod_class,
489 .clkdm_name = "l3_instr_clkdm",
490 .prcm = {
491 .omap4 = {
492 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
493 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
494 .modulemode = MODULEMODE_HWCTRL,
495 },
496 },
453 .slaves = omap44xx_l3_main_3_slaves, 497 .slaves = omap44xx_l3_main_3_slaves,
454 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves), 498 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
455 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 499 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -507,6 +551,12 @@ static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
507static struct omap_hwmod omap44xx_l4_abe_hwmod = { 551static struct omap_hwmod omap44xx_l4_abe_hwmod = {
508 .name = "l4_abe", 552 .name = "l4_abe",
509 .class = &omap44xx_l4_hwmod_class, 553 .class = &omap44xx_l4_hwmod_class,
554 .clkdm_name = "abe_clkdm",
555 .prcm = {
556 .omap4 = {
557 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
558 },
559 },
510 .slaves = omap44xx_l4_abe_slaves, 560 .slaves = omap44xx_l4_abe_slaves,
511 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves), 561 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
512 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 562 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -529,6 +579,13 @@ static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
529static struct omap_hwmod omap44xx_l4_cfg_hwmod = { 579static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
530 .name = "l4_cfg", 580 .name = "l4_cfg",
531 .class = &omap44xx_l4_hwmod_class, 581 .class = &omap44xx_l4_hwmod_class,
582 .clkdm_name = "l4_cfg_clkdm",
583 .prcm = {
584 .omap4 = {
585 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
586 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
587 },
588 },
532 .slaves = omap44xx_l4_cfg_slaves, 589 .slaves = omap44xx_l4_cfg_slaves,
533 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves), 590 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
534 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 591 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -551,6 +608,13 @@ static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
551static struct omap_hwmod omap44xx_l4_per_hwmod = { 608static struct omap_hwmod omap44xx_l4_per_hwmod = {
552 .name = "l4_per", 609 .name = "l4_per",
553 .class = &omap44xx_l4_hwmod_class, 610 .class = &omap44xx_l4_hwmod_class,
611 .clkdm_name = "l4_per_clkdm",
612 .prcm = {
613 .omap4 = {
614 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
615 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
616 },
617 },
554 .slaves = omap44xx_l4_per_slaves, 618 .slaves = omap44xx_l4_per_slaves,
555 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves), 619 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
556 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 620 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -573,6 +637,13 @@ static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
573static struct omap_hwmod omap44xx_l4_wkup_hwmod = { 637static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
574 .name = "l4_wkup", 638 .name = "l4_wkup",
575 .class = &omap44xx_l4_hwmod_class, 639 .class = &omap44xx_l4_hwmod_class,
640 .clkdm_name = "l4_wkup_clkdm",
641 .prcm = {
642 .omap4 = {
643 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
644 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
645 },
646 },
576 .slaves = omap44xx_l4_wkup_slaves, 647 .slaves = omap44xx_l4_wkup_slaves,
577 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves), 648 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
578 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 649 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -603,6 +674,7 @@ static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
603static struct omap_hwmod omap44xx_mpu_private_hwmod = { 674static struct omap_hwmod omap44xx_mpu_private_hwmod = {
604 .name = "mpu_private", 675 .name = "mpu_private",
605 .class = &omap44xx_mpu_bus_hwmod_class, 676 .class = &omap44xx_mpu_bus_hwmod_class,
677 .clkdm_name = "mpuss_clkdm",
606 .slaves = omap44xx_mpu_private_slaves, 678 .slaves = omap44xx_mpu_private_slaves,
607 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves), 679 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
608 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 680 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -741,12 +813,15 @@ static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
741static struct omap_hwmod omap44xx_aess_hwmod = { 813static struct omap_hwmod omap44xx_aess_hwmod = {
742 .name = "aess", 814 .name = "aess",
743 .class = &omap44xx_aess_hwmod_class, 815 .class = &omap44xx_aess_hwmod_class,
816 .clkdm_name = "abe_clkdm",
744 .mpu_irqs = omap44xx_aess_irqs, 817 .mpu_irqs = omap44xx_aess_irqs,
745 .sdma_reqs = omap44xx_aess_sdma_reqs, 818 .sdma_reqs = omap44xx_aess_sdma_reqs,
746 .main_clk = "aess_fck", 819 .main_clk = "aess_fck",
747 .prcm = { 820 .prcm = {
748 .omap4 = { 821 .omap4 = {
749 .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, 822 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
823 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
824 .modulemode = MODULEMODE_SWCTRL,
750 }, 825 },
751 }, 826 },
752 .slaves = omap44xx_aess_slaves, 827 .slaves = omap44xx_aess_slaves,
@@ -773,9 +848,10 @@ static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
773static struct omap_hwmod omap44xx_bandgap_hwmod = { 848static struct omap_hwmod omap44xx_bandgap_hwmod = {
774 .name = "bandgap", 849 .name = "bandgap",
775 .class = &omap44xx_bandgap_hwmod_class, 850 .class = &omap44xx_bandgap_hwmod_class,
851 .clkdm_name = "l4_wkup_clkdm",
776 .prcm = { 852 .prcm = {
777 .omap4 = { 853 .omap4 = {
778 .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, 854 .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
779 }, 855 },
780 }, 856 },
781 .opt_clks = bandgap_opt_clks, 857 .opt_clks = bandgap_opt_clks,
@@ -830,11 +906,13 @@ static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
830static struct omap_hwmod omap44xx_counter_32k_hwmod = { 906static struct omap_hwmod omap44xx_counter_32k_hwmod = {
831 .name = "counter_32k", 907 .name = "counter_32k",
832 .class = &omap44xx_counter_hwmod_class, 908 .class = &omap44xx_counter_hwmod_class,
909 .clkdm_name = "l4_wkup_clkdm",
833 .flags = HWMOD_SWSUP_SIDLE, 910 .flags = HWMOD_SWSUP_SIDLE,
834 .main_clk = "sys_32k_ck", 911 .main_clk = "sys_32k_ck",
835 .prcm = { 912 .prcm = {
836 .omap4 = { 913 .omap4 = {
837 .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL, 914 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
915 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
838 }, 916 },
839 }, 917 },
840 .slaves = omap44xx_counter_32k_slaves, 918 .slaves = omap44xx_counter_32k_slaves,
@@ -913,11 +991,13 @@ static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
913static struct omap_hwmod omap44xx_dma_system_hwmod = { 991static struct omap_hwmod omap44xx_dma_system_hwmod = {
914 .name = "dma_system", 992 .name = "dma_system",
915 .class = &omap44xx_dma_hwmod_class, 993 .class = &omap44xx_dma_hwmod_class,
994 .clkdm_name = "l3_dma_clkdm",
916 .mpu_irqs = omap44xx_dma_system_irqs, 995 .mpu_irqs = omap44xx_dma_system_irqs,
917 .main_clk = "l3_div_ck", 996 .main_clk = "l3_div_ck",
918 .prcm = { 997 .prcm = {
919 .omap4 = { 998 .omap4 = {
920 .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL, 999 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
1000 .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
921 }, 1001 },
922 }, 1002 },
923 .dev_attr = &dma_dev_attr, 1003 .dev_attr = &dma_dev_attr,
@@ -1005,12 +1085,15 @@ static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
1005static struct omap_hwmod omap44xx_dmic_hwmod = { 1085static struct omap_hwmod omap44xx_dmic_hwmod = {
1006 .name = "dmic", 1086 .name = "dmic",
1007 .class = &omap44xx_dmic_hwmod_class, 1087 .class = &omap44xx_dmic_hwmod_class,
1088 .clkdm_name = "abe_clkdm",
1008 .mpu_irqs = omap44xx_dmic_irqs, 1089 .mpu_irqs = omap44xx_dmic_irqs,
1009 .sdma_reqs = omap44xx_dmic_sdma_reqs, 1090 .sdma_reqs = omap44xx_dmic_sdma_reqs,
1010 .main_clk = "dmic_fck", 1091 .main_clk = "dmic_fck",
1011 .prcm = { 1092 .prcm = {
1012 .omap4 = { 1093 .omap4 = {
1013 .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, 1094 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
1095 .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
1096 .modulemode = MODULEMODE_SWCTRL,
1014 }, 1097 },
1015 }, 1098 },
1016 .slaves = omap44xx_dmic_slaves, 1099 .slaves = omap44xx_dmic_slaves,
@@ -1072,12 +1155,13 @@ static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1072static struct omap_hwmod omap44xx_dsp_c0_hwmod = { 1155static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1073 .name = "dsp_c0", 1156 .name = "dsp_c0",
1074 .class = &omap44xx_dsp_hwmod_class, 1157 .class = &omap44xx_dsp_hwmod_class,
1158 .clkdm_name = "tesla_clkdm",
1075 .flags = HWMOD_INIT_NO_RESET, 1159 .flags = HWMOD_INIT_NO_RESET,
1076 .rst_lines = omap44xx_dsp_c0_resets, 1160 .rst_lines = omap44xx_dsp_c0_resets,
1077 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets), 1161 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1078 .prcm = { 1162 .prcm = {
1079 .omap4 = { 1163 .omap4 = {
1080 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL, 1164 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1081 }, 1165 },
1082 }, 1166 },
1083 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1167 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1086,14 +1170,17 @@ static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1086static struct omap_hwmod omap44xx_dsp_hwmod = { 1170static struct omap_hwmod omap44xx_dsp_hwmod = {
1087 .name = "dsp", 1171 .name = "dsp",
1088 .class = &omap44xx_dsp_hwmod_class, 1172 .class = &omap44xx_dsp_hwmod_class,
1173 .clkdm_name = "tesla_clkdm",
1089 .mpu_irqs = omap44xx_dsp_irqs, 1174 .mpu_irqs = omap44xx_dsp_irqs,
1090 .rst_lines = omap44xx_dsp_resets, 1175 .rst_lines = omap44xx_dsp_resets,
1091 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), 1176 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
1092 .main_clk = "dsp_fck", 1177 .main_clk = "dsp_fck",
1093 .prcm = { 1178 .prcm = {
1094 .omap4 = { 1179 .omap4 = {
1095 .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, 1180 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
1096 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL, 1181 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1182 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
1183 .modulemode = MODULEMODE_HWCTRL,
1097 }, 1184 },
1098 }, 1185 },
1099 .slaves = omap44xx_dsp_slaves, 1186 .slaves = omap44xx_dsp_slaves,
@@ -1177,10 +1264,12 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1177static struct omap_hwmod omap44xx_dss_hwmod = { 1264static struct omap_hwmod omap44xx_dss_hwmod = {
1178 .name = "dss_core", 1265 .name = "dss_core",
1179 .class = &omap44xx_dss_hwmod_class, 1266 .class = &omap44xx_dss_hwmod_class,
1267 .clkdm_name = "l3_dss_clkdm",
1180 .main_clk = "dss_dss_clk", 1268 .main_clk = "dss_dss_clk",
1181 .prcm = { 1269 .prcm = {
1182 .omap4 = { 1270 .omap4 = {
1183 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, 1271 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1272 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1184 }, 1273 },
1185 }, 1274 },
1186 .opt_clks = dss_opt_clks, 1275 .opt_clks = dss_opt_clks,
@@ -1278,13 +1367,14 @@ static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
1278static struct omap_hwmod omap44xx_dss_dispc_hwmod = { 1367static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1279 .name = "dss_dispc", 1368 .name = "dss_dispc",
1280 .class = &omap44xx_dispc_hwmod_class, 1369 .class = &omap44xx_dispc_hwmod_class,
1281 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1370 .clkdm_name = "l3_dss_clkdm",
1282 .mpu_irqs = omap44xx_dss_dispc_irqs, 1371 .mpu_irqs = omap44xx_dss_dispc_irqs,
1283 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, 1372 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
1284 .main_clk = "dss_dss_clk", 1373 .main_clk = "dss_dss_clk",
1285 .prcm = { 1374 .prcm = {
1286 .omap4 = { 1375 .omap4 = {
1287 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, 1376 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1377 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1288 }, 1378 },
1289 }, 1379 },
1290 .opt_clks = dss_dispc_opt_clks, 1380 .opt_clks = dss_dispc_opt_clks,
@@ -1376,12 +1466,14 @@ static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1376static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { 1466static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1377 .name = "dss_dsi1", 1467 .name = "dss_dsi1",
1378 .class = &omap44xx_dsi_hwmod_class, 1468 .class = &omap44xx_dsi_hwmod_class,
1469 .clkdm_name = "l3_dss_clkdm",
1379 .mpu_irqs = omap44xx_dss_dsi1_irqs, 1470 .mpu_irqs = omap44xx_dss_dsi1_irqs,
1380 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, 1471 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
1381 .main_clk = "dss_dss_clk", 1472 .main_clk = "dss_dss_clk",
1382 .prcm = { 1473 .prcm = {
1383 .omap4 = { 1474 .omap4 = {
1384 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, 1475 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1476 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1385 }, 1477 },
1386 }, 1478 },
1387 .opt_clks = dss_dsi1_opt_clks, 1479 .opt_clks = dss_dsi1_opt_clks,
@@ -1452,12 +1544,14 @@ static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1452static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { 1544static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1453 .name = "dss_dsi2", 1545 .name = "dss_dsi2",
1454 .class = &omap44xx_dsi_hwmod_class, 1546 .class = &omap44xx_dsi_hwmod_class,
1547 .clkdm_name = "l3_dss_clkdm",
1455 .mpu_irqs = omap44xx_dss_dsi2_irqs, 1548 .mpu_irqs = omap44xx_dss_dsi2_irqs,
1456 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, 1549 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
1457 .main_clk = "dss_dss_clk", 1550 .main_clk = "dss_dss_clk",
1458 .prcm = { 1551 .prcm = {
1459 .omap4 = { 1552 .omap4 = {
1460 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, 1553 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1554 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1461 }, 1555 },
1462 }, 1556 },
1463 .opt_clks = dss_dsi2_opt_clks, 1557 .opt_clks = dss_dsi2_opt_clks,
@@ -1548,12 +1642,14 @@ static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1548static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { 1642static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1549 .name = "dss_hdmi", 1643 .name = "dss_hdmi",
1550 .class = &omap44xx_hdmi_hwmod_class, 1644 .class = &omap44xx_hdmi_hwmod_class,
1645 .clkdm_name = "l3_dss_clkdm",
1551 .mpu_irqs = omap44xx_dss_hdmi_irqs, 1646 .mpu_irqs = omap44xx_dss_hdmi_irqs,
1552 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, 1647 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
1553 .main_clk = "dss_dss_clk", 1648 .main_clk = "dss_dss_clk",
1554 .prcm = { 1649 .prcm = {
1555 .omap4 = { 1650 .omap4 = {
1556 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, 1651 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1652 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1557 }, 1653 },
1558 }, 1654 },
1559 .opt_clks = dss_hdmi_opt_clks, 1655 .opt_clks = dss_hdmi_opt_clks,
@@ -1639,11 +1735,13 @@ static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1639static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { 1735static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1640 .name = "dss_rfbi", 1736 .name = "dss_rfbi",
1641 .class = &omap44xx_rfbi_hwmod_class, 1737 .class = &omap44xx_rfbi_hwmod_class,
1738 .clkdm_name = "l3_dss_clkdm",
1642 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, 1739 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
1643 .main_clk = "dss_dss_clk", 1740 .main_clk = "dss_dss_clk",
1644 .prcm = { 1741 .prcm = {
1645 .omap4 = { 1742 .omap4 = {
1646 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, 1743 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1744 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1647 }, 1745 },
1648 }, 1746 },
1649 .opt_clks = dss_rfbi_opt_clks, 1747 .opt_clks = dss_rfbi_opt_clks,
@@ -1709,10 +1807,12 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1709static struct omap_hwmod omap44xx_dss_venc_hwmod = { 1807static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1710 .name = "dss_venc", 1808 .name = "dss_venc",
1711 .class = &omap44xx_venc_hwmod_class, 1809 .class = &omap44xx_venc_hwmod_class,
1810 .clkdm_name = "l3_dss_clkdm",
1712 .main_clk = "dss_dss_clk", 1811 .main_clk = "dss_dss_clk",
1713 .prcm = { 1812 .prcm = {
1714 .omap4 = { 1813 .omap4 = {
1715 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, 1814 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1815 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1716 }, 1816 },
1717 }, 1817 },
1718 .slaves = omap44xx_dss_venc_slaves, 1818 .slaves = omap44xx_dss_venc_slaves,
@@ -1786,11 +1886,14 @@ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1786static struct omap_hwmod omap44xx_gpio1_hwmod = { 1886static struct omap_hwmod omap44xx_gpio1_hwmod = {
1787 .name = "gpio1", 1887 .name = "gpio1",
1788 .class = &omap44xx_gpio_hwmod_class, 1888 .class = &omap44xx_gpio_hwmod_class,
1889 .clkdm_name = "l4_wkup_clkdm",
1789 .mpu_irqs = omap44xx_gpio1_irqs, 1890 .mpu_irqs = omap44xx_gpio1_irqs,
1790 .main_clk = "gpio1_ick", 1891 .main_clk = "gpio1_ick",
1791 .prcm = { 1892 .prcm = {
1792 .omap4 = { 1893 .omap4 = {
1793 .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, 1894 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1895 .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1896 .modulemode = MODULEMODE_HWCTRL,
1794 }, 1897 },
1795 }, 1898 },
1796 .opt_clks = gpio1_opt_clks, 1899 .opt_clks = gpio1_opt_clks,
@@ -1838,12 +1941,15 @@ static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1838static struct omap_hwmod omap44xx_gpio2_hwmod = { 1941static struct omap_hwmod omap44xx_gpio2_hwmod = {
1839 .name = "gpio2", 1942 .name = "gpio2",
1840 .class = &omap44xx_gpio_hwmod_class, 1943 .class = &omap44xx_gpio_hwmod_class,
1944 .clkdm_name = "l4_per_clkdm",
1841 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1945 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1842 .mpu_irqs = omap44xx_gpio2_irqs, 1946 .mpu_irqs = omap44xx_gpio2_irqs,
1843 .main_clk = "gpio2_ick", 1947 .main_clk = "gpio2_ick",
1844 .prcm = { 1948 .prcm = {
1845 .omap4 = { 1949 .omap4 = {
1846 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, 1950 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1951 .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1952 .modulemode = MODULEMODE_HWCTRL,
1847 }, 1953 },
1848 }, 1954 },
1849 .opt_clks = gpio2_opt_clks, 1955 .opt_clks = gpio2_opt_clks,
@@ -1891,12 +1997,15 @@ static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1891static struct omap_hwmod omap44xx_gpio3_hwmod = { 1997static struct omap_hwmod omap44xx_gpio3_hwmod = {
1892 .name = "gpio3", 1998 .name = "gpio3",
1893 .class = &omap44xx_gpio_hwmod_class, 1999 .class = &omap44xx_gpio_hwmod_class,
2000 .clkdm_name = "l4_per_clkdm",
1894 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 2001 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1895 .mpu_irqs = omap44xx_gpio3_irqs, 2002 .mpu_irqs = omap44xx_gpio3_irqs,
1896 .main_clk = "gpio3_ick", 2003 .main_clk = "gpio3_ick",
1897 .prcm = { 2004 .prcm = {
1898 .omap4 = { 2005 .omap4 = {
1899 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, 2006 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
2007 .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
2008 .modulemode = MODULEMODE_HWCTRL,
1900 }, 2009 },
1901 }, 2010 },
1902 .opt_clks = gpio3_opt_clks, 2011 .opt_clks = gpio3_opt_clks,
@@ -1944,12 +2053,15 @@ static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1944static struct omap_hwmod omap44xx_gpio4_hwmod = { 2053static struct omap_hwmod omap44xx_gpio4_hwmod = {
1945 .name = "gpio4", 2054 .name = "gpio4",
1946 .class = &omap44xx_gpio_hwmod_class, 2055 .class = &omap44xx_gpio_hwmod_class,
2056 .clkdm_name = "l4_per_clkdm",
1947 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 2057 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1948 .mpu_irqs = omap44xx_gpio4_irqs, 2058 .mpu_irqs = omap44xx_gpio4_irqs,
1949 .main_clk = "gpio4_ick", 2059 .main_clk = "gpio4_ick",
1950 .prcm = { 2060 .prcm = {
1951 .omap4 = { 2061 .omap4 = {
1952 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, 2062 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
2063 .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
2064 .modulemode = MODULEMODE_HWCTRL,
1953 }, 2065 },
1954 }, 2066 },
1955 .opt_clks = gpio4_opt_clks, 2067 .opt_clks = gpio4_opt_clks,
@@ -1997,12 +2109,15 @@ static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1997static struct omap_hwmod omap44xx_gpio5_hwmod = { 2109static struct omap_hwmod omap44xx_gpio5_hwmod = {
1998 .name = "gpio5", 2110 .name = "gpio5",
1999 .class = &omap44xx_gpio_hwmod_class, 2111 .class = &omap44xx_gpio_hwmod_class,
2112 .clkdm_name = "l4_per_clkdm",
2000 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 2113 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2001 .mpu_irqs = omap44xx_gpio5_irqs, 2114 .mpu_irqs = omap44xx_gpio5_irqs,
2002 .main_clk = "gpio5_ick", 2115 .main_clk = "gpio5_ick",
2003 .prcm = { 2116 .prcm = {
2004 .omap4 = { 2117 .omap4 = {
2005 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, 2118 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
2119 .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
2120 .modulemode = MODULEMODE_HWCTRL,
2006 }, 2121 },
2007 }, 2122 },
2008 .opt_clks = gpio5_opt_clks, 2123 .opt_clks = gpio5_opt_clks,
@@ -2050,12 +2165,15 @@ static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2050static struct omap_hwmod omap44xx_gpio6_hwmod = { 2165static struct omap_hwmod omap44xx_gpio6_hwmod = {
2051 .name = "gpio6", 2166 .name = "gpio6",
2052 .class = &omap44xx_gpio_hwmod_class, 2167 .class = &omap44xx_gpio_hwmod_class,
2168 .clkdm_name = "l4_per_clkdm",
2053 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 2169 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2054 .mpu_irqs = omap44xx_gpio6_irqs, 2170 .mpu_irqs = omap44xx_gpio6_irqs,
2055 .main_clk = "gpio6_ick", 2171 .main_clk = "gpio6_ick",
2056 .prcm = { 2172 .prcm = {
2057 .omap4 = { 2173 .omap4 = {
2058 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, 2174 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
2175 .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
2176 .modulemode = MODULEMODE_HWCTRL,
2059 }, 2177 },
2060 }, 2178 },
2061 .opt_clks = gpio6_opt_clks, 2179 .opt_clks = gpio6_opt_clks,
@@ -2129,11 +2247,14 @@ static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2129static struct omap_hwmod omap44xx_hsi_hwmod = { 2247static struct omap_hwmod omap44xx_hsi_hwmod = {
2130 .name = "hsi", 2248 .name = "hsi",
2131 .class = &omap44xx_hsi_hwmod_class, 2249 .class = &omap44xx_hsi_hwmod_class,
2250 .clkdm_name = "l3_init_clkdm",
2132 .mpu_irqs = omap44xx_hsi_irqs, 2251 .mpu_irqs = omap44xx_hsi_irqs,
2133 .main_clk = "hsi_fck", 2252 .main_clk = "hsi_fck",
2134 .prcm = { 2253 .prcm = {
2135 .omap4 = { 2254 .omap4 = {
2136 .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, 2255 .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
2256 .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
2257 .modulemode = MODULEMODE_HWCTRL,
2137 }, 2258 },
2138 }, 2259 },
2139 .slaves = omap44xx_hsi_slaves, 2260 .slaves = omap44xx_hsi_slaves,
@@ -2209,13 +2330,16 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2209static struct omap_hwmod omap44xx_i2c1_hwmod = { 2330static struct omap_hwmod omap44xx_i2c1_hwmod = {
2210 .name = "i2c1", 2331 .name = "i2c1",
2211 .class = &omap44xx_i2c_hwmod_class, 2332 .class = &omap44xx_i2c_hwmod_class,
2333 .clkdm_name = "l4_per_clkdm",
2212 .flags = HWMOD_16BIT_REG, 2334 .flags = HWMOD_16BIT_REG,
2213 .mpu_irqs = omap44xx_i2c1_irqs, 2335 .mpu_irqs = omap44xx_i2c1_irqs,
2214 .sdma_reqs = omap44xx_i2c1_sdma_reqs, 2336 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
2215 .main_clk = "i2c1_fck", 2337 .main_clk = "i2c1_fck",
2216 .prcm = { 2338 .prcm = {
2217 .omap4 = { 2339 .omap4 = {
2218 .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, 2340 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
2341 .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
2342 .modulemode = MODULEMODE_SWCTRL,
2219 }, 2343 },
2220 }, 2344 },
2221 .slaves = omap44xx_i2c1_slaves, 2345 .slaves = omap44xx_i2c1_slaves,
@@ -2263,13 +2387,16 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2263static struct omap_hwmod omap44xx_i2c2_hwmod = { 2387static struct omap_hwmod omap44xx_i2c2_hwmod = {
2264 .name = "i2c2", 2388 .name = "i2c2",
2265 .class = &omap44xx_i2c_hwmod_class, 2389 .class = &omap44xx_i2c_hwmod_class,
2390 .clkdm_name = "l4_per_clkdm",
2266 .flags = HWMOD_16BIT_REG, 2391 .flags = HWMOD_16BIT_REG,
2267 .mpu_irqs = omap44xx_i2c2_irqs, 2392 .mpu_irqs = omap44xx_i2c2_irqs,
2268 .sdma_reqs = omap44xx_i2c2_sdma_reqs, 2393 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
2269 .main_clk = "i2c2_fck", 2394 .main_clk = "i2c2_fck",
2270 .prcm = { 2395 .prcm = {
2271 .omap4 = { 2396 .omap4 = {
2272 .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, 2397 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
2398 .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
2399 .modulemode = MODULEMODE_SWCTRL,
2273 }, 2400 },
2274 }, 2401 },
2275 .slaves = omap44xx_i2c2_slaves, 2402 .slaves = omap44xx_i2c2_slaves,
@@ -2317,13 +2444,16 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2317static struct omap_hwmod omap44xx_i2c3_hwmod = { 2444static struct omap_hwmod omap44xx_i2c3_hwmod = {
2318 .name = "i2c3", 2445 .name = "i2c3",
2319 .class = &omap44xx_i2c_hwmod_class, 2446 .class = &omap44xx_i2c_hwmod_class,
2447 .clkdm_name = "l4_per_clkdm",
2320 .flags = HWMOD_16BIT_REG, 2448 .flags = HWMOD_16BIT_REG,
2321 .mpu_irqs = omap44xx_i2c3_irqs, 2449 .mpu_irqs = omap44xx_i2c3_irqs,
2322 .sdma_reqs = omap44xx_i2c3_sdma_reqs, 2450 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
2323 .main_clk = "i2c3_fck", 2451 .main_clk = "i2c3_fck",
2324 .prcm = { 2452 .prcm = {
2325 .omap4 = { 2453 .omap4 = {
2326 .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, 2454 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
2455 .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
2456 .modulemode = MODULEMODE_SWCTRL,
2327 }, 2457 },
2328 }, 2458 },
2329 .slaves = omap44xx_i2c3_slaves, 2459 .slaves = omap44xx_i2c3_slaves,
@@ -2371,13 +2501,16 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2371static struct omap_hwmod omap44xx_i2c4_hwmod = { 2501static struct omap_hwmod omap44xx_i2c4_hwmod = {
2372 .name = "i2c4", 2502 .name = "i2c4",
2373 .class = &omap44xx_i2c_hwmod_class, 2503 .class = &omap44xx_i2c_hwmod_class,
2504 .clkdm_name = "l4_per_clkdm",
2374 .flags = HWMOD_16BIT_REG, 2505 .flags = HWMOD_16BIT_REG,
2375 .mpu_irqs = omap44xx_i2c4_irqs, 2506 .mpu_irqs = omap44xx_i2c4_irqs,
2376 .sdma_reqs = omap44xx_i2c4_sdma_reqs, 2507 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
2377 .main_clk = "i2c4_fck", 2508 .main_clk = "i2c4_fck",
2378 .prcm = { 2509 .prcm = {
2379 .omap4 = { 2510 .omap4 = {
2380 .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, 2511 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
2512 .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
2513 .modulemode = MODULEMODE_SWCTRL,
2381 }, 2514 },
2382 }, 2515 },
2383 .slaves = omap44xx_i2c4_slaves, 2516 .slaves = omap44xx_i2c4_slaves,
@@ -2435,12 +2568,13 @@ static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2435static struct omap_hwmod omap44xx_ipu_c0_hwmod = { 2568static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2436 .name = "ipu_c0", 2569 .name = "ipu_c0",
2437 .class = &omap44xx_ipu_hwmod_class, 2570 .class = &omap44xx_ipu_hwmod_class,
2571 .clkdm_name = "ducati_clkdm",
2438 .flags = HWMOD_INIT_NO_RESET, 2572 .flags = HWMOD_INIT_NO_RESET,
2439 .rst_lines = omap44xx_ipu_c0_resets, 2573 .rst_lines = omap44xx_ipu_c0_resets,
2440 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets), 2574 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2441 .prcm = { 2575 .prcm = {
2442 .omap4 = { 2576 .omap4 = {
2443 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, 2577 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2444 }, 2578 },
2445 }, 2579 },
2446 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 2580 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -2450,12 +2584,13 @@ static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2450static struct omap_hwmod omap44xx_ipu_c1_hwmod = { 2584static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2451 .name = "ipu_c1", 2585 .name = "ipu_c1",
2452 .class = &omap44xx_ipu_hwmod_class, 2586 .class = &omap44xx_ipu_hwmod_class,
2587 .clkdm_name = "ducati_clkdm",
2453 .flags = HWMOD_INIT_NO_RESET, 2588 .flags = HWMOD_INIT_NO_RESET,
2454 .rst_lines = omap44xx_ipu_c1_resets, 2589 .rst_lines = omap44xx_ipu_c1_resets,
2455 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets), 2590 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2456 .prcm = { 2591 .prcm = {
2457 .omap4 = { 2592 .omap4 = {
2458 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, 2593 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2459 }, 2594 },
2460 }, 2595 },
2461 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 2596 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -2464,14 +2599,17 @@ static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2464static struct omap_hwmod omap44xx_ipu_hwmod = { 2599static struct omap_hwmod omap44xx_ipu_hwmod = {
2465 .name = "ipu", 2600 .name = "ipu",
2466 .class = &omap44xx_ipu_hwmod_class, 2601 .class = &omap44xx_ipu_hwmod_class,
2602 .clkdm_name = "ducati_clkdm",
2467 .mpu_irqs = omap44xx_ipu_irqs, 2603 .mpu_irqs = omap44xx_ipu_irqs,
2468 .rst_lines = omap44xx_ipu_resets, 2604 .rst_lines = omap44xx_ipu_resets,
2469 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), 2605 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
2470 .main_clk = "ipu_fck", 2606 .main_clk = "ipu_fck",
2471 .prcm = { 2607 .prcm = {
2472 .omap4 = { 2608 .omap4 = {
2473 .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, 2609 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2474 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, 2610 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2611 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2612 .modulemode = MODULEMODE_HWCTRL,
2475 }, 2613 },
2476 }, 2614 },
2477 .slaves = omap44xx_ipu_slaves, 2615 .slaves = omap44xx_ipu_slaves,
@@ -2551,12 +2689,15 @@ static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2551static struct omap_hwmod omap44xx_iss_hwmod = { 2689static struct omap_hwmod omap44xx_iss_hwmod = {
2552 .name = "iss", 2690 .name = "iss",
2553 .class = &omap44xx_iss_hwmod_class, 2691 .class = &omap44xx_iss_hwmod_class,
2692 .clkdm_name = "iss_clkdm",
2554 .mpu_irqs = omap44xx_iss_irqs, 2693 .mpu_irqs = omap44xx_iss_irqs,
2555 .sdma_reqs = omap44xx_iss_sdma_reqs, 2694 .sdma_reqs = omap44xx_iss_sdma_reqs,
2556 .main_clk = "iss_fck", 2695 .main_clk = "iss_fck",
2557 .prcm = { 2696 .prcm = {
2558 .omap4 = { 2697 .omap4 = {
2559 .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, 2698 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
2699 .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
2700 .modulemode = MODULEMODE_SWCTRL,
2560 }, 2701 },
2561 }, 2702 },
2562 .opt_clks = iss_opt_clks, 2703 .opt_clks = iss_opt_clks,
@@ -2631,12 +2772,13 @@ static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2631static struct omap_hwmod omap44xx_iva_seq0_hwmod = { 2772static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2632 .name = "iva_seq0", 2773 .name = "iva_seq0",
2633 .class = &omap44xx_iva_hwmod_class, 2774 .class = &omap44xx_iva_hwmod_class,
2775 .clkdm_name = "ivahd_clkdm",
2634 .flags = HWMOD_INIT_NO_RESET, 2776 .flags = HWMOD_INIT_NO_RESET,
2635 .rst_lines = omap44xx_iva_seq0_resets, 2777 .rst_lines = omap44xx_iva_seq0_resets,
2636 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets), 2778 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2637 .prcm = { 2779 .prcm = {
2638 .omap4 = { 2780 .omap4 = {
2639 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, 2781 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2640 }, 2782 },
2641 }, 2783 },
2642 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 2784 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -2646,12 +2788,13 @@ static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2646static struct omap_hwmod omap44xx_iva_seq1_hwmod = { 2788static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2647 .name = "iva_seq1", 2789 .name = "iva_seq1",
2648 .class = &omap44xx_iva_hwmod_class, 2790 .class = &omap44xx_iva_hwmod_class,
2791 .clkdm_name = "ivahd_clkdm",
2649 .flags = HWMOD_INIT_NO_RESET, 2792 .flags = HWMOD_INIT_NO_RESET,
2650 .rst_lines = omap44xx_iva_seq1_resets, 2793 .rst_lines = omap44xx_iva_seq1_resets,
2651 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets), 2794 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2652 .prcm = { 2795 .prcm = {
2653 .omap4 = { 2796 .omap4 = {
2654 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, 2797 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2655 }, 2798 },
2656 }, 2799 },
2657 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 2800 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -2660,14 +2803,17 @@ static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2660static struct omap_hwmod omap44xx_iva_hwmod = { 2803static struct omap_hwmod omap44xx_iva_hwmod = {
2661 .name = "iva", 2804 .name = "iva",
2662 .class = &omap44xx_iva_hwmod_class, 2805 .class = &omap44xx_iva_hwmod_class,
2806 .clkdm_name = "ivahd_clkdm",
2663 .mpu_irqs = omap44xx_iva_irqs, 2807 .mpu_irqs = omap44xx_iva_irqs,
2664 .rst_lines = omap44xx_iva_resets, 2808 .rst_lines = omap44xx_iva_resets,
2665 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), 2809 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
2666 .main_clk = "iva_fck", 2810 .main_clk = "iva_fck",
2667 .prcm = { 2811 .prcm = {
2668 .omap4 = { 2812 .omap4 = {
2669 .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, 2813 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
2670 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, 2814 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2815 .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
2816 .modulemode = MODULEMODE_HWCTRL,
2671 }, 2817 },
2672 }, 2818 },
2673 .slaves = omap44xx_iva_slaves, 2819 .slaves = omap44xx_iva_slaves,
@@ -2732,11 +2878,14 @@ static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2732static struct omap_hwmod omap44xx_kbd_hwmod = { 2878static struct omap_hwmod omap44xx_kbd_hwmod = {
2733 .name = "kbd", 2879 .name = "kbd",
2734 .class = &omap44xx_kbd_hwmod_class, 2880 .class = &omap44xx_kbd_hwmod_class,
2881 .clkdm_name = "l4_wkup_clkdm",
2735 .mpu_irqs = omap44xx_kbd_irqs, 2882 .mpu_irqs = omap44xx_kbd_irqs,
2736 .main_clk = "kbd_fck", 2883 .main_clk = "kbd_fck",
2737 .prcm = { 2884 .prcm = {
2738 .omap4 = { 2885 .omap4 = {
2739 .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, 2886 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
2887 .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
2888 .modulemode = MODULEMODE_SWCTRL,
2740 }, 2889 },
2741 }, 2890 },
2742 .slaves = omap44xx_kbd_slaves, 2891 .slaves = omap44xx_kbd_slaves,
@@ -2797,10 +2946,12 @@ static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2797static struct omap_hwmod omap44xx_mailbox_hwmod = { 2946static struct omap_hwmod omap44xx_mailbox_hwmod = {
2798 .name = "mailbox", 2947 .name = "mailbox",
2799 .class = &omap44xx_mailbox_hwmod_class, 2948 .class = &omap44xx_mailbox_hwmod_class,
2949 .clkdm_name = "l4_cfg_clkdm",
2800 .mpu_irqs = omap44xx_mailbox_irqs, 2950 .mpu_irqs = omap44xx_mailbox_irqs,
2801 .prcm = { 2951 .prcm = {
2802 .omap4 = { 2952 .omap4 = {
2803 .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL, 2953 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
2954 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
2804 }, 2955 },
2805 }, 2956 },
2806 .slaves = omap44xx_mailbox_slaves, 2957 .slaves = omap44xx_mailbox_slaves,
@@ -2887,12 +3038,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2887static struct omap_hwmod omap44xx_mcbsp1_hwmod = { 3038static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2888 .name = "mcbsp1", 3039 .name = "mcbsp1",
2889 .class = &omap44xx_mcbsp_hwmod_class, 3040 .class = &omap44xx_mcbsp_hwmod_class,
3041 .clkdm_name = "abe_clkdm",
2890 .mpu_irqs = omap44xx_mcbsp1_irqs, 3042 .mpu_irqs = omap44xx_mcbsp1_irqs,
2891 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, 3043 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
2892 .main_clk = "mcbsp1_fck", 3044 .main_clk = "mcbsp1_fck",
2893 .prcm = { 3045 .prcm = {
2894 .omap4 = { 3046 .omap4 = {
2895 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, 3047 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
3048 .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
3049 .modulemode = MODULEMODE_SWCTRL,
2896 }, 3050 },
2897 }, 3051 },
2898 .slaves = omap44xx_mcbsp1_slaves, 3052 .slaves = omap44xx_mcbsp1_slaves,
@@ -2960,12 +3114,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
2960static struct omap_hwmod omap44xx_mcbsp2_hwmod = { 3114static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2961 .name = "mcbsp2", 3115 .name = "mcbsp2",
2962 .class = &omap44xx_mcbsp_hwmod_class, 3116 .class = &omap44xx_mcbsp_hwmod_class,
3117 .clkdm_name = "abe_clkdm",
2963 .mpu_irqs = omap44xx_mcbsp2_irqs, 3118 .mpu_irqs = omap44xx_mcbsp2_irqs,
2964 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, 3119 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
2965 .main_clk = "mcbsp2_fck", 3120 .main_clk = "mcbsp2_fck",
2966 .prcm = { 3121 .prcm = {
2967 .omap4 = { 3122 .omap4 = {
2968 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, 3123 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
3124 .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
3125 .modulemode = MODULEMODE_SWCTRL,
2969 }, 3126 },
2970 }, 3127 },
2971 .slaves = omap44xx_mcbsp2_slaves, 3128 .slaves = omap44xx_mcbsp2_slaves,
@@ -3033,12 +3190,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
3033static struct omap_hwmod omap44xx_mcbsp3_hwmod = { 3190static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3034 .name = "mcbsp3", 3191 .name = "mcbsp3",
3035 .class = &omap44xx_mcbsp_hwmod_class, 3192 .class = &omap44xx_mcbsp_hwmod_class,
3193 .clkdm_name = "abe_clkdm",
3036 .mpu_irqs = omap44xx_mcbsp3_irqs, 3194 .mpu_irqs = omap44xx_mcbsp3_irqs,
3037 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, 3195 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
3038 .main_clk = "mcbsp3_fck", 3196 .main_clk = "mcbsp3_fck",
3039 .prcm = { 3197 .prcm = {
3040 .omap4 = { 3198 .omap4 = {
3041 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, 3199 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
3200 .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
3201 .modulemode = MODULEMODE_SWCTRL,
3042 }, 3202 },
3043 }, 3203 },
3044 .slaves = omap44xx_mcbsp3_slaves, 3204 .slaves = omap44xx_mcbsp3_slaves,
@@ -3085,12 +3245,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3085static struct omap_hwmod omap44xx_mcbsp4_hwmod = { 3245static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3086 .name = "mcbsp4", 3246 .name = "mcbsp4",
3087 .class = &omap44xx_mcbsp_hwmod_class, 3247 .class = &omap44xx_mcbsp_hwmod_class,
3248 .clkdm_name = "l4_per_clkdm",
3088 .mpu_irqs = omap44xx_mcbsp4_irqs, 3249 .mpu_irqs = omap44xx_mcbsp4_irqs,
3089 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, 3250 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
3090 .main_clk = "mcbsp4_fck", 3251 .main_clk = "mcbsp4_fck",
3091 .prcm = { 3252 .prcm = {
3092 .omap4 = { 3253 .omap4 = {
3093 .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, 3254 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
3255 .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
3256 .modulemode = MODULEMODE_SWCTRL,
3094 }, 3257 },
3095 }, 3258 },
3096 .slaves = omap44xx_mcbsp4_slaves, 3259 .slaves = omap44xx_mcbsp4_slaves,
@@ -3177,12 +3340,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3177static struct omap_hwmod omap44xx_mcpdm_hwmod = { 3340static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3178 .name = "mcpdm", 3341 .name = "mcpdm",
3179 .class = &omap44xx_mcpdm_hwmod_class, 3342 .class = &omap44xx_mcpdm_hwmod_class,
3343 .clkdm_name = "abe_clkdm",
3180 .mpu_irqs = omap44xx_mcpdm_irqs, 3344 .mpu_irqs = omap44xx_mcpdm_irqs,
3181 .sdma_reqs = omap44xx_mcpdm_sdma_reqs, 3345 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
3182 .main_clk = "mcpdm_fck", 3346 .main_clk = "mcpdm_fck",
3183 .prcm = { 3347 .prcm = {
3184 .omap4 = { 3348 .omap4 = {
3185 .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, 3349 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
3350 .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
3351 .modulemode = MODULEMODE_SWCTRL,
3186 }, 3352 },
3187 }, 3353 },
3188 .slaves = omap44xx_mcpdm_slaves, 3354 .slaves = omap44xx_mcpdm_slaves,
@@ -3262,12 +3428,15 @@ static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3262static struct omap_hwmod omap44xx_mcspi1_hwmod = { 3428static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3263 .name = "mcspi1", 3429 .name = "mcspi1",
3264 .class = &omap44xx_mcspi_hwmod_class, 3430 .class = &omap44xx_mcspi_hwmod_class,
3431 .clkdm_name = "l4_per_clkdm",
3265 .mpu_irqs = omap44xx_mcspi1_irqs, 3432 .mpu_irqs = omap44xx_mcspi1_irqs,
3266 .sdma_reqs = omap44xx_mcspi1_sdma_reqs, 3433 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
3267 .main_clk = "mcspi1_fck", 3434 .main_clk = "mcspi1_fck",
3268 .prcm = { 3435 .prcm = {
3269 .omap4 = { 3436 .omap4 = {
3270 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, 3437 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
3438 .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
3439 .modulemode = MODULEMODE_SWCTRL,
3271 }, 3440 },
3272 }, 3441 },
3273 .dev_attr = &mcspi1_dev_attr, 3442 .dev_attr = &mcspi1_dev_attr,
@@ -3322,12 +3491,15 @@ static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3322static struct omap_hwmod omap44xx_mcspi2_hwmod = { 3491static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3323 .name = "mcspi2", 3492 .name = "mcspi2",
3324 .class = &omap44xx_mcspi_hwmod_class, 3493 .class = &omap44xx_mcspi_hwmod_class,
3494 .clkdm_name = "l4_per_clkdm",
3325 .mpu_irqs = omap44xx_mcspi2_irqs, 3495 .mpu_irqs = omap44xx_mcspi2_irqs,
3326 .sdma_reqs = omap44xx_mcspi2_sdma_reqs, 3496 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
3327 .main_clk = "mcspi2_fck", 3497 .main_clk = "mcspi2_fck",
3328 .prcm = { 3498 .prcm = {
3329 .omap4 = { 3499 .omap4 = {
3330 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, 3500 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
3501 .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
3502 .modulemode = MODULEMODE_SWCTRL,
3331 }, 3503 },
3332 }, 3504 },
3333 .dev_attr = &mcspi2_dev_attr, 3505 .dev_attr = &mcspi2_dev_attr,
@@ -3382,12 +3554,15 @@ static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3382static struct omap_hwmod omap44xx_mcspi3_hwmod = { 3554static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3383 .name = "mcspi3", 3555 .name = "mcspi3",
3384 .class = &omap44xx_mcspi_hwmod_class, 3556 .class = &omap44xx_mcspi_hwmod_class,
3557 .clkdm_name = "l4_per_clkdm",
3385 .mpu_irqs = omap44xx_mcspi3_irqs, 3558 .mpu_irqs = omap44xx_mcspi3_irqs,
3386 .sdma_reqs = omap44xx_mcspi3_sdma_reqs, 3559 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
3387 .main_clk = "mcspi3_fck", 3560 .main_clk = "mcspi3_fck",
3388 .prcm = { 3561 .prcm = {
3389 .omap4 = { 3562 .omap4 = {
3390 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, 3563 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
3564 .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
3565 .modulemode = MODULEMODE_SWCTRL,
3391 }, 3566 },
3392 }, 3567 },
3393 .dev_attr = &mcspi3_dev_attr, 3568 .dev_attr = &mcspi3_dev_attr,
@@ -3440,12 +3615,15 @@ static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3440static struct omap_hwmod omap44xx_mcspi4_hwmod = { 3615static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3441 .name = "mcspi4", 3616 .name = "mcspi4",
3442 .class = &omap44xx_mcspi_hwmod_class, 3617 .class = &omap44xx_mcspi_hwmod_class,
3618 .clkdm_name = "l4_per_clkdm",
3443 .mpu_irqs = omap44xx_mcspi4_irqs, 3619 .mpu_irqs = omap44xx_mcspi4_irqs,
3444 .sdma_reqs = omap44xx_mcspi4_sdma_reqs, 3620 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
3445 .main_clk = "mcspi4_fck", 3621 .main_clk = "mcspi4_fck",
3446 .prcm = { 3622 .prcm = {
3447 .omap4 = { 3623 .omap4 = {
3448 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, 3624 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
3625 .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
3626 .modulemode = MODULEMODE_SWCTRL,
3449 }, 3627 },
3450 }, 3628 },
3451 .dev_attr = &mcspi4_dev_attr, 3629 .dev_attr = &mcspi4_dev_attr,
@@ -3524,12 +3702,15 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = {
3524static struct omap_hwmod omap44xx_mmc1_hwmod = { 3702static struct omap_hwmod omap44xx_mmc1_hwmod = {
3525 .name = "mmc1", 3703 .name = "mmc1",
3526 .class = &omap44xx_mmc_hwmod_class, 3704 .class = &omap44xx_mmc_hwmod_class,
3705 .clkdm_name = "l3_init_clkdm",
3527 .mpu_irqs = omap44xx_mmc1_irqs, 3706 .mpu_irqs = omap44xx_mmc1_irqs,
3528 .sdma_reqs = omap44xx_mmc1_sdma_reqs, 3707 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
3529 .main_clk = "mmc1_fck", 3708 .main_clk = "mmc1_fck",
3530 .prcm = { 3709 .prcm = {
3531 .omap4 = { 3710 .omap4 = {
3532 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, 3711 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
3712 .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
3713 .modulemode = MODULEMODE_SWCTRL,
3533 }, 3714 },
3534 }, 3715 },
3535 .dev_attr = &mmc1_dev_attr, 3716 .dev_attr = &mmc1_dev_attr,
@@ -3583,12 +3764,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3583static struct omap_hwmod omap44xx_mmc2_hwmod = { 3764static struct omap_hwmod omap44xx_mmc2_hwmod = {
3584 .name = "mmc2", 3765 .name = "mmc2",
3585 .class = &omap44xx_mmc_hwmod_class, 3766 .class = &omap44xx_mmc_hwmod_class,
3767 .clkdm_name = "l3_init_clkdm",
3586 .mpu_irqs = omap44xx_mmc2_irqs, 3768 .mpu_irqs = omap44xx_mmc2_irqs,
3587 .sdma_reqs = omap44xx_mmc2_sdma_reqs, 3769 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
3588 .main_clk = "mmc2_fck", 3770 .main_clk = "mmc2_fck",
3589 .prcm = { 3771 .prcm = {
3590 .omap4 = { 3772 .omap4 = {
3591 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, 3773 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
3774 .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
3775 .modulemode = MODULEMODE_SWCTRL,
3592 }, 3776 },
3593 }, 3777 },
3594 .slaves = omap44xx_mmc2_slaves, 3778 .slaves = omap44xx_mmc2_slaves,
@@ -3637,12 +3821,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3637static struct omap_hwmod omap44xx_mmc3_hwmod = { 3821static struct omap_hwmod omap44xx_mmc3_hwmod = {
3638 .name = "mmc3", 3822 .name = "mmc3",
3639 .class = &omap44xx_mmc_hwmod_class, 3823 .class = &omap44xx_mmc_hwmod_class,
3824 .clkdm_name = "l4_per_clkdm",
3640 .mpu_irqs = omap44xx_mmc3_irqs, 3825 .mpu_irqs = omap44xx_mmc3_irqs,
3641 .sdma_reqs = omap44xx_mmc3_sdma_reqs, 3826 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
3642 .main_clk = "mmc3_fck", 3827 .main_clk = "mmc3_fck",
3643 .prcm = { 3828 .prcm = {
3644 .omap4 = { 3829 .omap4 = {
3645 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, 3830 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
3831 .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
3832 .modulemode = MODULEMODE_SWCTRL,
3646 }, 3833 },
3647 }, 3834 },
3648 .slaves = omap44xx_mmc3_slaves, 3835 .slaves = omap44xx_mmc3_slaves,
@@ -3689,13 +3876,16 @@ static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3689static struct omap_hwmod omap44xx_mmc4_hwmod = { 3876static struct omap_hwmod omap44xx_mmc4_hwmod = {
3690 .name = "mmc4", 3877 .name = "mmc4",
3691 .class = &omap44xx_mmc_hwmod_class, 3878 .class = &omap44xx_mmc_hwmod_class,
3879 .clkdm_name = "l4_per_clkdm",
3692 .mpu_irqs = omap44xx_mmc4_irqs, 3880 .mpu_irqs = omap44xx_mmc4_irqs,
3693 3881
3694 .sdma_reqs = omap44xx_mmc4_sdma_reqs, 3882 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
3695 .main_clk = "mmc4_fck", 3883 .main_clk = "mmc4_fck",
3696 .prcm = { 3884 .prcm = {
3697 .omap4 = { 3885 .omap4 = {
3698 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, 3886 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
3887 .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
3888 .modulemode = MODULEMODE_SWCTRL,
3699 }, 3889 },
3700 }, 3890 },
3701 .slaves = omap44xx_mmc4_slaves, 3891 .slaves = omap44xx_mmc4_slaves,
@@ -3742,12 +3932,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3742static struct omap_hwmod omap44xx_mmc5_hwmod = { 3932static struct omap_hwmod omap44xx_mmc5_hwmod = {
3743 .name = "mmc5", 3933 .name = "mmc5",
3744 .class = &omap44xx_mmc_hwmod_class, 3934 .class = &omap44xx_mmc_hwmod_class,
3935 .clkdm_name = "l4_per_clkdm",
3745 .mpu_irqs = omap44xx_mmc5_irqs, 3936 .mpu_irqs = omap44xx_mmc5_irqs,
3746 .sdma_reqs = omap44xx_mmc5_sdma_reqs, 3937 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
3747 .main_clk = "mmc5_fck", 3938 .main_clk = "mmc5_fck",
3748 .prcm = { 3939 .prcm = {
3749 .omap4 = { 3940 .omap4 = {
3750 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, 3941 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
3942 .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
3943 .modulemode = MODULEMODE_SWCTRL,
3751 }, 3944 },
3752 }, 3945 },
3753 .slaves = omap44xx_mmc5_slaves, 3946 .slaves = omap44xx_mmc5_slaves,
@@ -3782,12 +3975,14 @@ static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3782static struct omap_hwmod omap44xx_mpu_hwmod = { 3975static struct omap_hwmod omap44xx_mpu_hwmod = {
3783 .name = "mpu", 3976 .name = "mpu",
3784 .class = &omap44xx_mpu_hwmod_class, 3977 .class = &omap44xx_mpu_hwmod_class,
3978 .clkdm_name = "mpuss_clkdm",
3785 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, 3979 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3786 .mpu_irqs = omap44xx_mpu_irqs, 3980 .mpu_irqs = omap44xx_mpu_irqs,
3787 .main_clk = "dpll_mpu_m2_ck", 3981 .main_clk = "dpll_mpu_m2_ck",
3788 .prcm = { 3982 .prcm = {
3789 .omap4 = { 3983 .omap4 = {
3790 .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL, 3984 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
3985 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
3791 }, 3986 },
3792 }, 3987 },
3793 .masters = omap44xx_mpu_masters, 3988 .masters = omap44xx_mpu_masters,
@@ -3854,13 +4049,16 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3854static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { 4049static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3855 .name = "smartreflex_core", 4050 .name = "smartreflex_core",
3856 .class = &omap44xx_smartreflex_hwmod_class, 4051 .class = &omap44xx_smartreflex_hwmod_class,
4052 .clkdm_name = "l4_ao_clkdm",
3857 .mpu_irqs = omap44xx_smartreflex_core_irqs, 4053 .mpu_irqs = omap44xx_smartreflex_core_irqs,
3858 4054
3859 .main_clk = "smartreflex_core_fck", 4055 .main_clk = "smartreflex_core_fck",
3860 .vdd_name = "core", 4056 .vdd_name = "core",
3861 .prcm = { 4057 .prcm = {
3862 .omap4 = { 4058 .omap4 = {
3863 .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, 4059 .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
4060 .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
4061 .modulemode = MODULEMODE_SWCTRL,
3864 }, 4062 },
3865 }, 4063 },
3866 .slaves = omap44xx_smartreflex_core_slaves, 4064 .slaves = omap44xx_smartreflex_core_slaves,
@@ -3901,12 +4099,15 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
3901static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { 4099static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3902 .name = "smartreflex_iva", 4100 .name = "smartreflex_iva",
3903 .class = &omap44xx_smartreflex_hwmod_class, 4101 .class = &omap44xx_smartreflex_hwmod_class,
4102 .clkdm_name = "l4_ao_clkdm",
3904 .mpu_irqs = omap44xx_smartreflex_iva_irqs, 4103 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
3905 .main_clk = "smartreflex_iva_fck", 4104 .main_clk = "smartreflex_iva_fck",
3906 .vdd_name = "iva", 4105 .vdd_name = "iva",
3907 .prcm = { 4106 .prcm = {
3908 .omap4 = { 4107 .omap4 = {
3909 .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, 4108 .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
4109 .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
4110 .modulemode = MODULEMODE_SWCTRL,
3910 }, 4111 },
3911 }, 4112 },
3912 .slaves = omap44xx_smartreflex_iva_slaves, 4113 .slaves = omap44xx_smartreflex_iva_slaves,
@@ -3947,12 +4148,15 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
3947static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { 4148static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3948 .name = "smartreflex_mpu", 4149 .name = "smartreflex_mpu",
3949 .class = &omap44xx_smartreflex_hwmod_class, 4150 .class = &omap44xx_smartreflex_hwmod_class,
4151 .clkdm_name = "l4_ao_clkdm",
3950 .mpu_irqs = omap44xx_smartreflex_mpu_irqs, 4152 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
3951 .main_clk = "smartreflex_mpu_fck", 4153 .main_clk = "smartreflex_mpu_fck",
3952 .vdd_name = "mpu", 4154 .vdd_name = "mpu",
3953 .prcm = { 4155 .prcm = {
3954 .omap4 = { 4156 .omap4 = {
3955 .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, 4157 .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
4158 .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
4159 .modulemode = MODULEMODE_SWCTRL,
3956 }, 4160 },
3957 }, 4161 },
3958 .slaves = omap44xx_smartreflex_mpu_slaves, 4162 .slaves = omap44xx_smartreflex_mpu_slaves,
@@ -4011,9 +4215,11 @@ static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
4011static struct omap_hwmod omap44xx_spinlock_hwmod = { 4215static struct omap_hwmod omap44xx_spinlock_hwmod = {
4012 .name = "spinlock", 4216 .name = "spinlock",
4013 .class = &omap44xx_spinlock_hwmod_class, 4217 .class = &omap44xx_spinlock_hwmod_class,
4218 .clkdm_name = "l4_cfg_clkdm",
4014 .prcm = { 4219 .prcm = {
4015 .omap4 = { 4220 .omap4 = {
4016 .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL, 4221 .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
4222 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
4017 }, 4223 },
4018 }, 4224 },
4019 .slaves = omap44xx_spinlock_slaves, 4225 .slaves = omap44xx_spinlock_slaves,
@@ -4092,11 +4298,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4092static struct omap_hwmod omap44xx_timer1_hwmod = { 4298static struct omap_hwmod omap44xx_timer1_hwmod = {
4093 .name = "timer1", 4299 .name = "timer1",
4094 .class = &omap44xx_timer_1ms_hwmod_class, 4300 .class = &omap44xx_timer_1ms_hwmod_class,
4301 .clkdm_name = "l4_wkup_clkdm",
4095 .mpu_irqs = omap44xx_timer1_irqs, 4302 .mpu_irqs = omap44xx_timer1_irqs,
4096 .main_clk = "timer1_fck", 4303 .main_clk = "timer1_fck",
4097 .prcm = { 4304 .prcm = {
4098 .omap4 = { 4305 .omap4 = {
4099 .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, 4306 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
4307 .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
4308 .modulemode = MODULEMODE_SWCTRL,
4100 }, 4309 },
4101 }, 4310 },
4102 .slaves = omap44xx_timer1_slaves, 4311 .slaves = omap44xx_timer1_slaves,
@@ -4137,11 +4346,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4137static struct omap_hwmod omap44xx_timer2_hwmod = { 4346static struct omap_hwmod omap44xx_timer2_hwmod = {
4138 .name = "timer2", 4347 .name = "timer2",
4139 .class = &omap44xx_timer_1ms_hwmod_class, 4348 .class = &omap44xx_timer_1ms_hwmod_class,
4349 .clkdm_name = "l4_per_clkdm",
4140 .mpu_irqs = omap44xx_timer2_irqs, 4350 .mpu_irqs = omap44xx_timer2_irqs,
4141 .main_clk = "timer2_fck", 4351 .main_clk = "timer2_fck",
4142 .prcm = { 4352 .prcm = {
4143 .omap4 = { 4353 .omap4 = {
4144 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, 4354 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
4355 .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
4356 .modulemode = MODULEMODE_SWCTRL,
4145 }, 4357 },
4146 }, 4358 },
4147 .slaves = omap44xx_timer2_slaves, 4359 .slaves = omap44xx_timer2_slaves,
@@ -4182,11 +4394,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4182static struct omap_hwmod omap44xx_timer3_hwmod = { 4394static struct omap_hwmod omap44xx_timer3_hwmod = {
4183 .name = "timer3", 4395 .name = "timer3",
4184 .class = &omap44xx_timer_hwmod_class, 4396 .class = &omap44xx_timer_hwmod_class,
4397 .clkdm_name = "l4_per_clkdm",
4185 .mpu_irqs = omap44xx_timer3_irqs, 4398 .mpu_irqs = omap44xx_timer3_irqs,
4186 .main_clk = "timer3_fck", 4399 .main_clk = "timer3_fck",
4187 .prcm = { 4400 .prcm = {
4188 .omap4 = { 4401 .omap4 = {
4189 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, 4402 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
4403 .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
4404 .modulemode = MODULEMODE_SWCTRL,
4190 }, 4405 },
4191 }, 4406 },
4192 .slaves = omap44xx_timer3_slaves, 4407 .slaves = omap44xx_timer3_slaves,
@@ -4227,11 +4442,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4227static struct omap_hwmod omap44xx_timer4_hwmod = { 4442static struct omap_hwmod omap44xx_timer4_hwmod = {
4228 .name = "timer4", 4443 .name = "timer4",
4229 .class = &omap44xx_timer_hwmod_class, 4444 .class = &omap44xx_timer_hwmod_class,
4445 .clkdm_name = "l4_per_clkdm",
4230 .mpu_irqs = omap44xx_timer4_irqs, 4446 .mpu_irqs = omap44xx_timer4_irqs,
4231 .main_clk = "timer4_fck", 4447 .main_clk = "timer4_fck",
4232 .prcm = { 4448 .prcm = {
4233 .omap4 = { 4449 .omap4 = {
4234 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, 4450 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
4451 .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
4452 .modulemode = MODULEMODE_SWCTRL,
4235 }, 4453 },
4236 }, 4454 },
4237 .slaves = omap44xx_timer4_slaves, 4455 .slaves = omap44xx_timer4_slaves,
@@ -4291,11 +4509,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4291static struct omap_hwmod omap44xx_timer5_hwmod = { 4509static struct omap_hwmod omap44xx_timer5_hwmod = {
4292 .name = "timer5", 4510 .name = "timer5",
4293 .class = &omap44xx_timer_hwmod_class, 4511 .class = &omap44xx_timer_hwmod_class,
4512 .clkdm_name = "abe_clkdm",
4294 .mpu_irqs = omap44xx_timer5_irqs, 4513 .mpu_irqs = omap44xx_timer5_irqs,
4295 .main_clk = "timer5_fck", 4514 .main_clk = "timer5_fck",
4296 .prcm = { 4515 .prcm = {
4297 .omap4 = { 4516 .omap4 = {
4298 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, 4517 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
4518 .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
4519 .modulemode = MODULEMODE_SWCTRL,
4299 }, 4520 },
4300 }, 4521 },
4301 .slaves = omap44xx_timer5_slaves, 4522 .slaves = omap44xx_timer5_slaves,
@@ -4355,12 +4576,15 @@ static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4355static struct omap_hwmod omap44xx_timer6_hwmod = { 4576static struct omap_hwmod omap44xx_timer6_hwmod = {
4356 .name = "timer6", 4577 .name = "timer6",
4357 .class = &omap44xx_timer_hwmod_class, 4578 .class = &omap44xx_timer_hwmod_class,
4579 .clkdm_name = "abe_clkdm",
4358 .mpu_irqs = omap44xx_timer6_irqs, 4580 .mpu_irqs = omap44xx_timer6_irqs,
4359 4581
4360 .main_clk = "timer6_fck", 4582 .main_clk = "timer6_fck",
4361 .prcm = { 4583 .prcm = {
4362 .omap4 = { 4584 .omap4 = {
4363 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, 4585 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
4586 .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
4587 .modulemode = MODULEMODE_SWCTRL,
4364 }, 4588 },
4365 }, 4589 },
4366 .slaves = omap44xx_timer6_slaves, 4590 .slaves = omap44xx_timer6_slaves,
@@ -4420,11 +4644,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4420static struct omap_hwmod omap44xx_timer7_hwmod = { 4644static struct omap_hwmod omap44xx_timer7_hwmod = {
4421 .name = "timer7", 4645 .name = "timer7",
4422 .class = &omap44xx_timer_hwmod_class, 4646 .class = &omap44xx_timer_hwmod_class,
4647 .clkdm_name = "abe_clkdm",
4423 .mpu_irqs = omap44xx_timer7_irqs, 4648 .mpu_irqs = omap44xx_timer7_irqs,
4424 .main_clk = "timer7_fck", 4649 .main_clk = "timer7_fck",
4425 .prcm = { 4650 .prcm = {
4426 .omap4 = { 4651 .omap4 = {
4427 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, 4652 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
4653 .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
4654 .modulemode = MODULEMODE_SWCTRL,
4428 }, 4655 },
4429 }, 4656 },
4430 .slaves = omap44xx_timer7_slaves, 4657 .slaves = omap44xx_timer7_slaves,
@@ -4484,11 +4711,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4484static struct omap_hwmod omap44xx_timer8_hwmod = { 4711static struct omap_hwmod omap44xx_timer8_hwmod = {
4485 .name = "timer8", 4712 .name = "timer8",
4486 .class = &omap44xx_timer_hwmod_class, 4713 .class = &omap44xx_timer_hwmod_class,
4714 .clkdm_name = "abe_clkdm",
4487 .mpu_irqs = omap44xx_timer8_irqs, 4715 .mpu_irqs = omap44xx_timer8_irqs,
4488 .main_clk = "timer8_fck", 4716 .main_clk = "timer8_fck",
4489 .prcm = { 4717 .prcm = {
4490 .omap4 = { 4718 .omap4 = {
4491 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, 4719 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
4720 .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
4721 .modulemode = MODULEMODE_SWCTRL,
4492 }, 4722 },
4493 }, 4723 },
4494 .slaves = omap44xx_timer8_slaves, 4724 .slaves = omap44xx_timer8_slaves,
@@ -4529,11 +4759,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4529static struct omap_hwmod omap44xx_timer9_hwmod = { 4759static struct omap_hwmod omap44xx_timer9_hwmod = {
4530 .name = "timer9", 4760 .name = "timer9",
4531 .class = &omap44xx_timer_hwmod_class, 4761 .class = &omap44xx_timer_hwmod_class,
4762 .clkdm_name = "l4_per_clkdm",
4532 .mpu_irqs = omap44xx_timer9_irqs, 4763 .mpu_irqs = omap44xx_timer9_irqs,
4533 .main_clk = "timer9_fck", 4764 .main_clk = "timer9_fck",
4534 .prcm = { 4765 .prcm = {
4535 .omap4 = { 4766 .omap4 = {
4536 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, 4767 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
4768 .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
4769 .modulemode = MODULEMODE_SWCTRL,
4537 }, 4770 },
4538 }, 4771 },
4539 .slaves = omap44xx_timer9_slaves, 4772 .slaves = omap44xx_timer9_slaves,
@@ -4574,11 +4807,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4574static struct omap_hwmod omap44xx_timer10_hwmod = { 4807static struct omap_hwmod omap44xx_timer10_hwmod = {
4575 .name = "timer10", 4808 .name = "timer10",
4576 .class = &omap44xx_timer_1ms_hwmod_class, 4809 .class = &omap44xx_timer_1ms_hwmod_class,
4810 .clkdm_name = "l4_per_clkdm",
4577 .mpu_irqs = omap44xx_timer10_irqs, 4811 .mpu_irqs = omap44xx_timer10_irqs,
4578 .main_clk = "timer10_fck", 4812 .main_clk = "timer10_fck",
4579 .prcm = { 4813 .prcm = {
4580 .omap4 = { 4814 .omap4 = {
4581 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, 4815 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
4816 .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
4817 .modulemode = MODULEMODE_SWCTRL,
4582 }, 4818 },
4583 }, 4819 },
4584 .slaves = omap44xx_timer10_slaves, 4820 .slaves = omap44xx_timer10_slaves,
@@ -4619,11 +4855,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4619static struct omap_hwmod omap44xx_timer11_hwmod = { 4855static struct omap_hwmod omap44xx_timer11_hwmod = {
4620 .name = "timer11", 4856 .name = "timer11",
4621 .class = &omap44xx_timer_hwmod_class, 4857 .class = &omap44xx_timer_hwmod_class,
4858 .clkdm_name = "l4_per_clkdm",
4622 .mpu_irqs = omap44xx_timer11_irqs, 4859 .mpu_irqs = omap44xx_timer11_irqs,
4623 .main_clk = "timer11_fck", 4860 .main_clk = "timer11_fck",
4624 .prcm = { 4861 .prcm = {
4625 .omap4 = { 4862 .omap4 = {
4626 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, 4863 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
4864 .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
4865 .modulemode = MODULEMODE_SWCTRL,
4627 }, 4866 },
4628 }, 4867 },
4629 .slaves = omap44xx_timer11_slaves, 4868 .slaves = omap44xx_timer11_slaves,
@@ -4692,12 +4931,15 @@ static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4692static struct omap_hwmod omap44xx_uart1_hwmod = { 4931static struct omap_hwmod omap44xx_uart1_hwmod = {
4693 .name = "uart1", 4932 .name = "uart1",
4694 .class = &omap44xx_uart_hwmod_class, 4933 .class = &omap44xx_uart_hwmod_class,
4934 .clkdm_name = "l4_per_clkdm",
4695 .mpu_irqs = omap44xx_uart1_irqs, 4935 .mpu_irqs = omap44xx_uart1_irqs,
4696 .sdma_reqs = omap44xx_uart1_sdma_reqs, 4936 .sdma_reqs = omap44xx_uart1_sdma_reqs,
4697 .main_clk = "uart1_fck", 4937 .main_clk = "uart1_fck",
4698 .prcm = { 4938 .prcm = {
4699 .omap4 = { 4939 .omap4 = {
4700 .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, 4940 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
4941 .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
4942 .modulemode = MODULEMODE_SWCTRL,
4701 }, 4943 },
4702 }, 4944 },
4703 .slaves = omap44xx_uart1_slaves, 4945 .slaves = omap44xx_uart1_slaves,
@@ -4744,12 +4986,15 @@ static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4744static struct omap_hwmod omap44xx_uart2_hwmod = { 4986static struct omap_hwmod omap44xx_uart2_hwmod = {
4745 .name = "uart2", 4987 .name = "uart2",
4746 .class = &omap44xx_uart_hwmod_class, 4988 .class = &omap44xx_uart_hwmod_class,
4989 .clkdm_name = "l4_per_clkdm",
4747 .mpu_irqs = omap44xx_uart2_irqs, 4990 .mpu_irqs = omap44xx_uart2_irqs,
4748 .sdma_reqs = omap44xx_uart2_sdma_reqs, 4991 .sdma_reqs = omap44xx_uart2_sdma_reqs,
4749 .main_clk = "uart2_fck", 4992 .main_clk = "uart2_fck",
4750 .prcm = { 4993 .prcm = {
4751 .omap4 = { 4994 .omap4 = {
4752 .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, 4995 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
4996 .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
4997 .modulemode = MODULEMODE_SWCTRL,
4753 }, 4998 },
4754 }, 4999 },
4755 .slaves = omap44xx_uart2_slaves, 5000 .slaves = omap44xx_uart2_slaves,
@@ -4796,13 +5041,16 @@ static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4796static struct omap_hwmod omap44xx_uart3_hwmod = { 5041static struct omap_hwmod omap44xx_uart3_hwmod = {
4797 .name = "uart3", 5042 .name = "uart3",
4798 .class = &omap44xx_uart_hwmod_class, 5043 .class = &omap44xx_uart_hwmod_class,
5044 .clkdm_name = "l4_per_clkdm",
4799 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, 5045 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
4800 .mpu_irqs = omap44xx_uart3_irqs, 5046 .mpu_irqs = omap44xx_uart3_irqs,
4801 .sdma_reqs = omap44xx_uart3_sdma_reqs, 5047 .sdma_reqs = omap44xx_uart3_sdma_reqs,
4802 .main_clk = "uart3_fck", 5048 .main_clk = "uart3_fck",
4803 .prcm = { 5049 .prcm = {
4804 .omap4 = { 5050 .omap4 = {
4805 .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, 5051 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
5052 .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
5053 .modulemode = MODULEMODE_SWCTRL,
4806 }, 5054 },
4807 }, 5055 },
4808 .slaves = omap44xx_uart3_slaves, 5056 .slaves = omap44xx_uart3_slaves,
@@ -4849,12 +5097,15 @@ static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
4849static struct omap_hwmod omap44xx_uart4_hwmod = { 5097static struct omap_hwmod omap44xx_uart4_hwmod = {
4850 .name = "uart4", 5098 .name = "uart4",
4851 .class = &omap44xx_uart_hwmod_class, 5099 .class = &omap44xx_uart_hwmod_class,
5100 .clkdm_name = "l4_per_clkdm",
4852 .mpu_irqs = omap44xx_uart4_irqs, 5101 .mpu_irqs = omap44xx_uart4_irqs,
4853 .sdma_reqs = omap44xx_uart4_sdma_reqs, 5102 .sdma_reqs = omap44xx_uart4_sdma_reqs,
4854 .main_clk = "uart4_fck", 5103 .main_clk = "uart4_fck",
4855 .prcm = { 5104 .prcm = {
4856 .omap4 = { 5105 .omap4 = {
4857 .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, 5106 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
5107 .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
5108 .modulemode = MODULEMODE_SWCTRL,
4858 }, 5109 },
4859 }, 5110 },
4860 .slaves = omap44xx_uart4_slaves, 5111 .slaves = omap44xx_uart4_slaves,
@@ -4927,12 +5178,15 @@ static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
4927static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { 5178static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
4928 .name = "usb_otg_hs", 5179 .name = "usb_otg_hs",
4929 .class = &omap44xx_usb_otg_hs_hwmod_class, 5180 .class = &omap44xx_usb_otg_hs_hwmod_class,
5181 .clkdm_name = "l3_init_clkdm",
4930 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 5182 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
4931 .mpu_irqs = omap44xx_usb_otg_hs_irqs, 5183 .mpu_irqs = omap44xx_usb_otg_hs_irqs,
4932 .main_clk = "usb_otg_hs_ick", 5184 .main_clk = "usb_otg_hs_ick",
4933 .prcm = { 5185 .prcm = {
4934 .omap4 = { 5186 .omap4 = {
4935 .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, 5187 .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
5188 .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
5189 .modulemode = MODULEMODE_HWCTRL,
4936 }, 5190 },
4937 }, 5191 },
4938 .opt_clks = usb_otg_hs_opt_clks, 5192 .opt_clks = usb_otg_hs_opt_clks,
@@ -5000,11 +5254,14 @@ static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
5000static struct omap_hwmod omap44xx_wd_timer2_hwmod = { 5254static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
5001 .name = "wd_timer2", 5255 .name = "wd_timer2",
5002 .class = &omap44xx_wd_timer_hwmod_class, 5256 .class = &omap44xx_wd_timer_hwmod_class,
5257 .clkdm_name = "l4_wkup_clkdm",
5003 .mpu_irqs = omap44xx_wd_timer2_irqs, 5258 .mpu_irqs = omap44xx_wd_timer2_irqs,
5004 .main_clk = "wd_timer2_fck", 5259 .main_clk = "wd_timer2_fck",
5005 .prcm = { 5260 .prcm = {
5006 .omap4 = { 5261 .omap4 = {
5007 .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, 5262 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
5263 .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
5264 .modulemode = MODULEMODE_SWCTRL,
5008 }, 5265 },
5009 }, 5266 },
5010 .slaves = omap44xx_wd_timer2_slaves, 5267 .slaves = omap44xx_wd_timer2_slaves,
@@ -5064,11 +5321,14 @@ static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5064static struct omap_hwmod omap44xx_wd_timer3_hwmod = { 5321static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5065 .name = "wd_timer3", 5322 .name = "wd_timer3",
5066 .class = &omap44xx_wd_timer_hwmod_class, 5323 .class = &omap44xx_wd_timer_hwmod_class,
5324 .clkdm_name = "abe_clkdm",
5067 .mpu_irqs = omap44xx_wd_timer3_irqs, 5325 .mpu_irqs = omap44xx_wd_timer3_irqs,
5068 .main_clk = "wd_timer3_fck", 5326 .main_clk = "wd_timer3_fck",
5069 .prcm = { 5327 .prcm = {
5070 .omap4 = { 5328 .omap4 = {
5071 .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, 5329 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
5330 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
5331 .modulemode = MODULEMODE_SWCTRL,
5072 }, 5332 },
5073 }, 5333 },
5074 .slaves = omap44xx_wd_timer3_slaves, 5334 .slaves = omap44xx_wd_timer3_slaves,
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index d48813fd62de..3feb35911a32 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -108,6 +108,7 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
108 u32 cur_state; 108 u32 cur_state;
109 int sleep_switch = -1; 109 int sleep_switch = -1;
110 int ret = 0; 110 int ret = 0;
111 int hwsup = 0;
111 112
112 if (pwrdm == NULL || IS_ERR(pwrdm)) 113 if (pwrdm == NULL || IS_ERR(pwrdm))
113 return -EINVAL; 114 return -EINVAL;
@@ -127,6 +128,7 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
127 (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) { 128 (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) {
128 sleep_switch = LOWPOWERSTATE_SWITCH; 129 sleep_switch = LOWPOWERSTATE_SWITCH;
129 } else { 130 } else {
131 hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]);
130 clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); 132 clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
131 pwrdm_wait_transition(pwrdm); 133 pwrdm_wait_transition(pwrdm);
132 sleep_switch = FORCEWAKEUP_SWITCH; 134 sleep_switch = FORCEWAKEUP_SWITCH;
@@ -142,7 +144,7 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
142 144
143 switch (sleep_switch) { 145 switch (sleep_switch) {
144 case FORCEWAKEUP_SWITCH: 146 case FORCEWAKEUP_SWITCH:
145 if (pwrdm->pwrdm_clkdms[0]->flags & CLKDM_CAN_ENABLE_AUTO) 147 if (hwsup)
146 clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); 148 clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
147 else 149 else
148 clkdm_sleep(pwrdm->pwrdm_clkdms[0]); 150 clkdm_sleep(pwrdm->pwrdm_clkdms[0]);
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 6be14389e4f3..2e40a5cf0163 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -70,7 +70,7 @@ static void omap_prcm_arch_reset(char mode, const char *cmd)
70 prcm_offs = OMAP3430_GR_MOD; 70 prcm_offs = OMAP3430_GR_MOD;
71 omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0)); 71 omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
72 } else if (cpu_is_omap44xx()) { 72 } else if (cpu_is_omap44xx()) {
73 omap4_prm_global_warm_sw_reset(); /* never returns */ 73 omap4_prminst_global_warm_sw_reset(); /* never returns */
74 } else { 74 } else {
75 WARN_ON(1); 75 WARN_ON(1);
76 } 76 }
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index a2a04bfa9628..00165558fc4d 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * OMAP4 PRM module functions 2 * OMAP4 PRM module functions
3 * 3 *
4 * Copyright (C) 2010 Texas Instruments, Inc. 4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Copyright (C) 2010 Nokia Corporation 5 * Copyright (C) 2010 Nokia Corporation
6 * Benoît Cousson 6 * Benoît Cousson
7 * Paul Walmsley 7 * Paul Walmsley
@@ -24,12 +24,6 @@
24#include "prm44xx.h" 24#include "prm44xx.h"
25#include "prm-regbits-44xx.h" 25#include "prm-regbits-44xx.h"
26 26
27/*
28 * Address offset (in bytes) between the reset control and the reset
29 * status registers: 4 bytes on OMAP4
30 */
31#define OMAP4_RST_CTRL_ST_OFFSET 4
32
33/* PRM low-level functions */ 27/* PRM low-level functions */
34 28
35/* Read a register in a CM/PRM instance in the PRM module */ 29/* Read a register in a CM/PRM instance in the PRM module */
@@ -56,140 +50,3 @@ u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
56 50
57 return v; 51 return v;
58} 52}
59
60/* Read a PRM register, AND it, and shift the result down to bit 0 */
61/* XXX deprecated */
62u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask)
63{
64 u32 v;
65
66 v = __raw_readl(reg);
67 v &= mask;
68 v >>= __ffs(mask);
69
70 return v;
71}
72
73/* Read-modify-write a register in a PRM module. Caller must lock */
74/* XXX deprecated */
75u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg)
76{
77 u32 v;
78
79 v = __raw_readl(reg);
80 v &= ~mask;
81 v |= bits;
82 __raw_writel(v, reg);
83
84 return v;
85}
86
87u32 omap4_prm_set_inst_reg_bits(u32 bits, s16 inst, s16 reg)
88{
89 return omap4_prm_rmw_inst_reg_bits(bits, bits, inst, reg);
90}
91
92u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 reg)
93{
94 return omap4_prm_rmw_inst_reg_bits(bits, 0x0, inst, reg);
95}
96
97/**
98 * omap4_prm_is_hardreset_asserted - read the HW reset line state of
99 * submodules contained in the hwmod module
100 * @rstctrl_reg: RM_RSTCTRL register address for this module
101 * @shift: register bit shift corresponding to the reset line to check
102 *
103 * Returns 1 if the (sub)module hardreset line is currently asserted,
104 * 0 if the (sub)module hardreset line is not currently asserted, or
105 * -EINVAL upon parameter error.
106 */
107int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift)
108{
109 if (!cpu_is_omap44xx() || !rstctrl_reg)
110 return -EINVAL;
111
112 return omap4_prm_read_bits_shift(rstctrl_reg, (1 << shift));
113}
114
115/**
116 * omap4_prm_assert_hardreset - assert the HW reset line of a submodule
117 * @rstctrl_reg: RM_RSTCTRL register address for this module
118 * @shift: register bit shift corresponding to the reset line to assert
119 *
120 * Some IPs like dsp, ipu or iva contain processors that require an HW
121 * reset line to be asserted / deasserted in order to fully enable the
122 * IP. These modules may have multiple hard-reset lines that reset
123 * different 'submodules' inside the IP block. This function will
124 * place the submodule into reset. Returns 0 upon success or -EINVAL
125 * upon an argument error.
126 */
127int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift)
128{
129 u32 mask;
130
131 if (!cpu_is_omap44xx() || !rstctrl_reg)
132 return -EINVAL;
133
134 mask = 1 << shift;
135 omap4_prm_rmw_reg_bits(mask, mask, rstctrl_reg);
136
137 return 0;
138}
139
140/**
141 * omap4_prm_deassert_hardreset - deassert a submodule hardreset line and wait
142 * @rstctrl_reg: RM_RSTCTRL register address for this module
143 * @shift: register bit shift corresponding to the reset line to deassert
144 *
145 * Some IPs like dsp, ipu or iva contain processors that require an HW
146 * reset line to be asserted / deasserted in order to fully enable the
147 * IP. These modules may have multiple hard-reset lines that reset
148 * different 'submodules' inside the IP block. This function will
149 * take the submodule out of reset and wait until the PRCM indicates
150 * that the reset has completed before returning. Returns 0 upon success or
151 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
152 * of reset, or -EBUSY if the submodule did not exit reset promptly.
153 */
154int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift)
155{
156 u32 mask;
157 void __iomem *rstst_reg;
158 int c;
159
160 if (!cpu_is_omap44xx() || !rstctrl_reg)
161 return -EINVAL;
162
163 rstst_reg = rstctrl_reg + OMAP4_RST_CTRL_ST_OFFSET;
164
165 mask = 1 << shift;
166
167 /* Check the current status to avoid de-asserting the line twice */
168 if (omap4_prm_read_bits_shift(rstctrl_reg, mask) == 0)
169 return -EEXIST;
170
171 /* Clear the reset status by writing 1 to the status bit */
172 omap4_prm_rmw_reg_bits(0xffffffff, mask, rstst_reg);
173 /* de-assert the reset control line */
174 omap4_prm_rmw_reg_bits(mask, 0, rstctrl_reg);
175 /* wait the status to be set */
176 omap_test_timeout(omap4_prm_read_bits_shift(rstst_reg, mask),
177 MAX_MODULE_HARDRESET_WAIT, c);
178
179 return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
180}
181
182void omap4_prm_global_warm_sw_reset(void)
183{
184 u32 v;
185
186 v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
187 OMAP4_RM_RSTCTRL);
188 v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
189 omap4_prm_write_inst_reg(v, OMAP4430_PRM_DEVICE_INST,
190 OMAP4_RM_RSTCTRL);
191
192 /* OCP barrier */
193 v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
194 OMAP4_RM_RSTCTRL);
195}
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 6e53120fd6cb..7dfa379b625d 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -750,16 +750,6 @@
750extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx); 750extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
751extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx); 751extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
752extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); 752extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
753extern u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg);
754extern u32 omap4_prm_set_inst_reg_bits(u32 bits, s16 inst, s16 idx);
755extern u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 idx);
756extern u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask);
757
758extern int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift);
759extern int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift);
760extern int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift);
761
762extern void omap4_prm_global_warm_sw_reset(void);
763 753
764# endif 754# endif
765 755
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index a30324297278..3a7bab16edd5 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -2,6 +2,7 @@
2 * OMAP4 PRM instance functions 2 * OMAP4 PRM instance functions
3 * 3 *
4 * Copyright (C) 2009 Nokia Corporation 4 * Copyright (C) 2009 Nokia Corporation
5 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Paul Walmsley 6 * Paul Walmsley
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
@@ -53,7 +54,7 @@ void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
53 54
54/* Read-modify-write a register in PRM. Caller must lock */ 55/* Read-modify-write a register in PRM. Caller must lock */
55u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, 56u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
56 s16 idx) 57 u16 idx)
57{ 58{
58 u32 v; 59 u32 v;
59 60
@@ -64,3 +65,112 @@ u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
64 65
65 return v; 66 return v;
66} 67}
68
69/*
70 * Address offset (in bytes) between the reset control and the reset
71 * status registers: 4 bytes on OMAP4
72 */
73#define OMAP4_RST_CTRL_ST_OFFSET 4
74
75/**
76 * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
77 * submodules contained in the hwmod module
78 * @rstctrl_reg: RM_RSTCTRL register address for this module
79 * @shift: register bit shift corresponding to the reset line to check
80 *
81 * Returns 1 if the (sub)module hardreset line is currently asserted,
82 * 0 if the (sub)module hardreset line is not currently asserted, or
83 * -EINVAL upon parameter error.
84 */
85int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
86 u16 rstctrl_offs)
87{
88 u32 v;
89
90 v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs);
91 v &= 1 << shift;
92 v >>= shift;
93
94 return v;
95}
96
97/**
98 * omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
99 * @rstctrl_reg: RM_RSTCTRL register address for this module
100 * @shift: register bit shift corresponding to the reset line to assert
101 *
102 * Some IPs like dsp, ipu or iva contain processors that require an HW
103 * reset line to be asserted / deasserted in order to fully enable the
104 * IP. These modules may have multiple hard-reset lines that reset
105 * different 'submodules' inside the IP block. This function will
106 * place the submodule into reset. Returns 0 upon success or -EINVAL
107 * upon an argument error.
108 */
109int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
110 u16 rstctrl_offs)
111{
112 u32 mask = 1 << shift;
113
114 omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs);
115
116 return 0;
117}
118
119/**
120 * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
121 * wait
122 * @rstctrl_reg: RM_RSTCTRL register address for this module
123 * @shift: register bit shift corresponding to the reset line to deassert
124 *
125 * Some IPs like dsp, ipu or iva contain processors that require an HW
126 * reset line to be asserted / deasserted in order to fully enable the
127 * IP. These modules may have multiple hard-reset lines that reset
128 * different 'submodules' inside the IP block. This function will
129 * take the submodule out of reset and wait until the PRCM indicates
130 * that the reset has completed before returning. Returns 0 upon success or
131 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
132 * of reset, or -EBUSY if the submodule did not exit reset promptly.
133 */
134int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
135 u16 rstctrl_offs)
136{
137 int c;
138 u32 mask = 1 << shift;
139 u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET;
140
141 /* Check the current status to avoid de-asserting the line twice */
142 if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
143 rstctrl_offs) == 0)
144 return -EEXIST;
145
146 /* Clear the reset status by writing 1 to the status bit */
147 omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst,
148 rstst_offs);
149 /* de-assert the reset control line */
150 omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
151 /* wait the status to be set */
152 omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst,
153 rstst_offs),
154 MAX_MODULE_HARDRESET_WAIT, c);
155
156 return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
157}
158
159
160void omap4_prminst_global_warm_sw_reset(void)
161{
162 u32 v;
163
164 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
165 OMAP4430_PRM_DEVICE_INST,
166 OMAP4_PRM_RSTCTRL_OFFSET);
167 v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
168 omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
169 OMAP4430_PRM_DEVICE_INST,
170 OMAP4_PRM_RSTCTRL_OFFSET);
171
172 /* OCP barrier */
173 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
174 OMAP4430_PRM_DEVICE_INST,
175 OMAP4_PRM_RSTCTRL_OFFSET);
176}
diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h
index 02dd66ddda8b..46f2efb36596 100644
--- a/arch/arm/mach-omap2/prminst44xx.h
+++ b/arch/arm/mach-omap2/prminst44xx.h
@@ -2,6 +2,7 @@
2 * OMAP4 Power/Reset Management (PRM) function prototypes 2 * OMAP4 Power/Reset Management (PRM) function prototypes
3 * 3 *
4 * Copyright (C) 2010 Nokia Corporation 4 * Copyright (C) 2010 Nokia Corporation
5 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Paul Walmsley 6 * Paul Walmsley
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
@@ -18,8 +19,15 @@
18extern u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx); 19extern u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx);
19extern void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx); 20extern void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
20extern u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, 21extern u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
21 s16 inst, s16 idx); 22 s16 inst, u16 idx);
22 23
23extern void omap4_prm_global_warm_sw_reset(void); 24extern void omap4_prminst_global_warm_sw_reset(void);
25
26extern int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
27 u16 rstctrl_offs);
28extern int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
29 u16 rstctrl_offs);
30extern int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
31 u16 rstctrl_offs);
24 32
25#endif 33#endif
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 3aaa46f6cd12..2543342dbccb 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -80,11 +80,11 @@ static struct twl4030_madc_platform_data omap3_madc_pdata = {
80 .irq_line = 1, 80 .irq_line = 1,
81}; 81};
82 82
83static struct twl4030_codec_audio_data omap3_audio; 83static struct twl4030_codec_data omap3_codec;
84 84
85static struct twl4030_codec_data omap3_codec_pdata = { 85static struct twl4030_audio_data omap3_audio_pdata = {
86 .audio_mclk = 26000000, 86 .audio_mclk = 26000000,
87 .audio = &omap3_audio, 87 .codec = &omap3_codec,
88}; 88};
89 89
90static struct regulator_consumer_supply omap3_vdda_dac_supplies[] = { 90static struct regulator_consumer_supply omap3_vdda_dac_supplies[] = {
@@ -292,8 +292,8 @@ void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
292 if (pdata_flags & TWL_COMMON_PDATA_MADC && !pmic_data->madc) 292 if (pdata_flags & TWL_COMMON_PDATA_MADC && !pmic_data->madc)
293 pmic_data->madc = &omap3_madc_pdata; 293 pmic_data->madc = &omap3_madc_pdata;
294 294
295 if (pdata_flags & TWL_COMMON_PDATA_AUDIO && !pmic_data->codec) 295 if (pdata_flags & TWL_COMMON_PDATA_AUDIO && !pmic_data->audio)
296 pmic_data->codec = &omap3_codec_pdata; 296 pmic_data->audio = &omap3_audio_pdata;
297 297
298 /* Common regulator configurations */ 298 /* Common regulator configurations */
299 if (regulators_flags & TWL_COMMON_REGULATOR_VDAC && !pmic_data->vdac) 299 if (regulators_flags & TWL_COMMON_REGULATOR_VDAC && !pmic_data->vdac)
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 964704f40bbe..3ba4d11ca73e 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -475,8 +475,41 @@ int __init clk_init(struct clk_functions * custom_clocks)
475/* 475/*
476 * debugfs support to trace clock tree hierarchy and attributes 476 * debugfs support to trace clock tree hierarchy and attributes
477 */ 477 */
478
479#include <linux/debugfs.h>
480#include <linux/seq_file.h>
481
478static struct dentry *clk_debugfs_root; 482static struct dentry *clk_debugfs_root;
479 483
484static int clk_dbg_show_summary(struct seq_file *s, void *unused)
485{
486 struct clk *c;
487 struct clk *pa;
488
489 seq_printf(s, "%-30s %-30s %-10s %s\n",
490 "clock-name", "parent-name", "rate", "use-count");
491
492 list_for_each_entry(c, &clocks, node) {
493 pa = c->parent;
494 seq_printf(s, "%-30s %-30s %-10lu %d\n",
495 c->name, pa ? pa->name : "none", c->rate, c->usecount);
496 }
497
498 return 0;
499}
500
501static int clk_dbg_open(struct inode *inode, struct file *file)
502{
503 return single_open(file, clk_dbg_show_summary, inode->i_private);
504}
505
506static const struct file_operations debug_clock_fops = {
507 .open = clk_dbg_open,
508 .read = seq_read,
509 .llseek = seq_lseek,
510 .release = single_release,
511};
512
480static int clk_debugfs_register_one(struct clk *c) 513static int clk_debugfs_register_one(struct clk *c)
481{ 514{
482 int err; 515 int err;
@@ -545,6 +578,12 @@ static int __init clk_debugfs_init(void)
545 if (err) 578 if (err)
546 goto err_out; 579 goto err_out;
547 } 580 }
581
582 d = debugfs_create_file("summary", S_IRUGO,
583 d, NULL, &debug_clock_fops);
584 if (!d)
585 return -ENOMEM;
586
548 return 0; 587 return 0;
549err_out: 588err_out:
550 debugfs_remove_recursive(clk_debugfs_root); 589 debugfs_remove_recursive(clk_debugfs_root);
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index c88432005665..926d25c780f3 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -407,11 +407,19 @@
407#endif 407#endif
408#define TWL6030_IRQ_END (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS) 408#define TWL6030_IRQ_END (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS)
409 409
410#define TWL6040_CODEC_IRQ_BASE TWL6030_IRQ_END
411#ifdef CONFIG_TWL6040_CODEC
412#define TWL6040_CODEC_NR_IRQS 6
413#else
414#define TWL6040_CODEC_NR_IRQS 0
415#endif
416#define TWL6040_CODEC_IRQ_END (TWL6040_CODEC_IRQ_BASE + TWL6040_CODEC_NR_IRQS)
417
410/* Total number of interrupts depends on the enabled blocks above */ 418/* Total number of interrupts depends on the enabled blocks above */
411#if (TWL4030_GPIO_IRQ_END > TWL6030_IRQ_END) 419#if (TWL4030_GPIO_IRQ_END > TWL6040_CODEC_IRQ_END)
412#define TWL_IRQ_END TWL4030_GPIO_IRQ_END 420#define TWL_IRQ_END TWL4030_GPIO_IRQ_END
413#else 421#else
414#define TWL_IRQ_END TWL6030_IRQ_END 422#define TWL_IRQ_END TWL6040_CODEC_IRQ_END
415#endif 423#endif
416 424
417/* GPMC related */ 425/* GPMC related */
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index fafdfe3c8d4e..0e329ca88a70 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -2,6 +2,7 @@
2 * omap_hwmod macros, structures 2 * omap_hwmod macros, structures
3 * 3 *
4 * Copyright (C) 2009-2011 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Paul Walmsley 6 * Paul Walmsley
6 * 7 *
7 * Created in collaboration with (alphabetical order): Benoît Cousson, 8 * Created in collaboration with (alphabetical order): Benoît Cousson,
@@ -79,6 +80,11 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
79#define HWMOD_IDLEMODE_SMART (1 << 2) 80#define HWMOD_IDLEMODE_SMART (1 << 2)
80#define HWMOD_IDLEMODE_SMART_WKUP (1 << 3) 81#define HWMOD_IDLEMODE_SMART_WKUP (1 << 3)
81 82
83/* modulemode control type (SW or HW) */
84#define MODULEMODE_HWCTRL 1
85#define MODULEMODE_SWCTRL 2
86
87
82/** 88/**
83 * struct omap_hwmod_mux_info - hwmod specific mux configuration 89 * struct omap_hwmod_mux_info - hwmod specific mux configuration
84 * @pads: array of omap_device_pad entries 90 * @pads: array of omap_device_pad entries
@@ -360,9 +366,11 @@ struct omap_hwmod_omap2_prcm {
360 * @submodule_wkdep_bit: bit shift of the WKDEP range 366 * @submodule_wkdep_bit: bit shift of the WKDEP range
361 */ 367 */
362struct omap_hwmod_omap4_prcm { 368struct omap_hwmod_omap4_prcm {
363 void __iomem *clkctrl_reg; 369 u16 clkctrl_offs;
364 void __iomem *rstctrl_reg; 370 u16 rstctrl_offs;
371 u16 context_offs;
365 u8 submodule_wkdep_bit; 372 u8 submodule_wkdep_bit;
373 u8 modulemode;
366}; 374};
367 375
368 376
@@ -515,6 +523,8 @@ struct omap_hwmod {
515 const char *main_clk; 523 const char *main_clk;
516 struct clk *_clk; 524 struct clk *_clk;
517 struct omap_hwmod_opt_clk *opt_clks; 525 struct omap_hwmod_opt_clk *opt_clks;
526 char *clkdm_name;
527 struct clockdomain *clkdm;
518 char *vdd_name; 528 char *vdd_name;
519 struct voltagedomain *voltdm; 529 struct voltagedomain *voltdm;
520 struct omap_hwmod_ocp_if **masters; /* connect to *_IA */ 530 struct omap_hwmod_ocp_if **masters; /* connect to *_IA */
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 3471c650743b..b6b409744954 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -236,56 +236,71 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
236 return 0; 236 return 0;
237} 237}
238 238
239static void _add_clkdev(struct omap_device *od, const char *clk_alias,
240 const char *clk_name)
241{
242 struct clk *r;
243 struct clk_lookup *l;
244
245 if (!clk_alias || !clk_name)
246 return;
247
248 pr_debug("omap_device: %s: Creating %s -> %s\n",
249 dev_name(&od->pdev.dev), clk_alias, clk_name);
250
251 r = clk_get_sys(dev_name(&od->pdev.dev), clk_alias);
252 if (!IS_ERR(r)) {
253 pr_warning("omap_device: %s: alias %s already exists\n",
254 dev_name(&od->pdev.dev), clk_alias);
255 clk_put(r);
256 return;
257 }
258
259 r = omap_clk_get_by_name(clk_name);
260 if (IS_ERR(r)) {
261 pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n",
262 dev_name(&od->pdev.dev), clk_name);
263 return;
264 }
265
266 l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev.dev));
267 if (!l) {
268 pr_err("omap_device: %s: clkdev_alloc for %s failed\n",
269 dev_name(&od->pdev.dev), clk_alias);
270 return;
271 }
272
273 clkdev_add(l);
274}
275
239/** 276/**
240 * _add_optional_clock_clkdev - Add clkdev entry for hwmod optional clocks 277 * _add_hwmod_clocks_clkdev - Add clkdev entry for hwmod optional clocks
278 * and main clock
241 * @od: struct omap_device *od 279 * @od: struct omap_device *od
280 * @oh: struct omap_hwmod *oh
242 * 281 *
243 * For every optional clock present per hwmod per omap_device, this function 282 * For the main clock and every optional clock present per hwmod per
244 * adds an entry in the clkdev table of the form <dev-id=dev_name, con-id=role> 283 * omap_device, this function adds an entry in the clkdev table of the
245 * if it does not exist already. 284 * form <dev-id=dev_name, con-id=role> if it does not exist already.
246 * 285 *
247 * The function is called from inside omap_device_build_ss(), after 286 * The function is called from inside omap_device_build_ss(), after
248 * omap_device_register. 287 * omap_device_register.
249 * 288 *
250 * This allows drivers to get a pointer to its optional clocks based on its role 289 * This allows drivers to get a pointer to its optional clocks based on its role
251 * by calling clk_get(<dev*>, <role>). 290 * by calling clk_get(<dev*>, <role>).
291 * In the case of the main clock, a "fck" alias is used.
252 * 292 *
253 * No return value. 293 * No return value.
254 */ 294 */
255static void _add_optional_clock_clkdev(struct omap_device *od, 295static void _add_hwmod_clocks_clkdev(struct omap_device *od,
256 struct omap_hwmod *oh) 296 struct omap_hwmod *oh)
257{ 297{
258 int i; 298 int i;
259 299
260 for (i = 0; i < oh->opt_clks_cnt; i++) { 300 _add_clkdev(od, "fck", oh->main_clk);
261 struct omap_hwmod_opt_clk *oc;
262 struct clk *r;
263 struct clk_lookup *l;
264
265 oc = &oh->opt_clks[i];
266
267 if (!oc->_clk)
268 continue;
269
270 r = clk_get_sys(dev_name(&od->pdev.dev), oc->role);
271 if (!IS_ERR(r))
272 continue; /* clkdev entry exists */
273 301
274 r = omap_clk_get_by_name((char *)oc->clk); 302 for (i = 0; i < oh->opt_clks_cnt; i++)
275 if (IS_ERR(r)) { 303 _add_clkdev(od, oh->opt_clks[i].role, oh->opt_clks[i].clk);
276 pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n",
277 dev_name(&od->pdev.dev), oc->clk);
278 continue;
279 }
280
281 l = clkdev_alloc(r, oc->role, dev_name(&od->pdev.dev));
282 if (!l) {
283 pr_err("omap_device: %s: clkdev_alloc for %s failed\n",
284 dev_name(&od->pdev.dev), oc->role);
285 return;
286 }
287 clkdev_add(l);
288 }
289} 304}
290 305
291 306
@@ -492,7 +507,7 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
492 507
493 for (i = 0; i < oh_cnt; i++) { 508 for (i = 0; i < oh_cnt; i++) {
494 hwmods[i]->od = od; 509 hwmods[i]->od = od;
495 _add_optional_clock_clkdev(od, hwmods[i]); 510 _add_hwmod_clocks_clkdev(od, hwmods[i]);
496 } 511 }
497 512
498 if (ret) 513 if (ret)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 21:04:42 -0500